Patched in Tegra support.

305 files changed, 4288 insertions, 74943 deletions

diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 9b54b7a403d..7897f05e316 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -1,2 +1,3 @@
-# MIPS headers
-generic-y += trace_clock.h
+include include/asm-generic/Kbuild.asm
+
+header-y += cachectl.h sgidefs.h sysmips.h
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 01cc6ba6483..1d93f81d57e 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -18,8 +18,8 @@
 #include <linux/types.h>
 #include <asm/barrier.h>
 #include <asm/cpu-features.h>
-#include <asm/cmpxchg.h>
 #include <asm/war.h>
+#include <asm/system.h>
 
 #define ATOMIC_INIT(i)    { (i) }
 
@@ -59,8 +59,8 @@ static __inline__ void atomic_add(int i, atomic_t * v)
                 "       sc      %0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "+m" (v->counter)
-                : "Ir" (i));
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
         } else if (kernel_uses_llsc) {
                 int temp;
 
@@ -71,8 +71,8 @@ static __inline__ void atomic_add(int i, atomic_t * v)
                         "       addu    %0, %2                          \n"
                         "       sc      %0, %1                          \n"
                         "       .set    mips0                           \n"
-                        : "=&r" (temp), "+m" (v->counter)
-                        : "Ir" (i));
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
                 } while (unlikely(!temp));
         } else {
                 unsigned long flags;
@@ -102,8 +102,8 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
                 "       sc      %0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "+m" (v->counter)
-                : "Ir" (i));
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
         } else if (kernel_uses_llsc) {
                 int temp;
 
@@ -114,8 +114,8 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
                         "       subu    %0, %2                          \n"
                         "       sc      %0, %1                          \n"
                         "       .set    mips0                           \n"
-                        : "=&r" (temp), "+m" (v->counter)
-                        : "Ir" (i));
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
                 } while (unlikely(!temp));
         } else {
                 unsigned long flags;
@@ -146,8 +146,9 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                 "       beqzl   %0, 1b                                  \n"
                 "       addu    %0, %1, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "+m" (v->counter)
-                : "Ir" (i));
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
         } else if (kernel_uses_llsc) {
                 int temp;
 
@@ -158,8 +159,9 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                         "       addu    %0, %1, %3                      \n"
                         "       sc      %0, %2                          \n"
                         "       .set    mips0                           \n"
-                        : "=&r" (result), "=&r" (temp), "+m" (v->counter)
-                        : "Ir" (i));
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
                 } while (unlikely(!result));
 
                 result = temp + i;
@@ -210,8 +212,9 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                         "       subu    %0, %1, %3                      \n"
                         "       sc      %0, %2                          \n"
                         "       .set    mips0                           \n"
-                        : "=&r" (result), "=&r" (temp), "+m" (v->counter)
-                        : "Ir" (i));
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
                 } while (unlikely(!result));
 
                 result = temp - i;
@@ -259,7 +262,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                 "       .set    reorder                                 \n"
                 "1:                                                     \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "+m" (v->counter)
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
         } else if (kernel_uses_llsc) {
@@ -277,8 +280,9 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                 "       .set    reorder                                 \n"
                 "1:                                                     \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "+m" (v->counter)
-                : "Ir" (i));
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
         } else {
                 unsigned long flags;
 
@@ -426,8 +430,8 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
                 "       scd     %0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "+m" (v->counter)
-                : "Ir" (i));
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
         } else if (kernel_uses_llsc) {
                 long temp;
 
@@ -438,8 +442,8 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
                         "       daddu   %0, %2                          \n"
                         "       scd     %0, %1                          \n"
                         "       .set    mips0                           \n"
-                        : "=&r" (temp), "+m" (v->counter)
-                        : "Ir" (i));
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
                 } while (unlikely(!temp));
         } else {
                 unsigned long flags;
@@ -469,8 +473,8 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
                 "       scd     %0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "+m" (v->counter)
-                : "Ir" (i));
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
         } else if (kernel_uses_llsc) {
                 long temp;
 
@@ -481,8 +485,8 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
                         "       dsubu   %0, %2                          \n"
                         "       scd     %0, %1                          \n"
                         "       .set    mips0                           \n"
-                        : "=&r" (temp), "+m" (v->counter)
-                        : "Ir" (i));
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
                 } while (unlikely(!temp));
         } else {
                 unsigned long flags;
@@ -513,8 +517,9 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                 "       beqzl   %0, 1b                                  \n"
                 "       daddu   %0, %1, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "+m" (v->counter)
-                : "Ir" (i));
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
         } else if (kernel_uses_llsc) {
                 long temp;
 
@@ -644,8 +649,9 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                 "       .set    reorder                                 \n"
                 "1:                                                     \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "+m" (v->counter)
-                : "Ir" (i));
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
         } else {
                 unsigned long flags;
 
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index f7fdc24e972..c0884f02d3a 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -8,8 +8,6 @@
 #ifndef __ASM_BARRIER_H
 #define __ASM_BARRIER_H
 
-#include <asm/addrspace.h>
-
 /*
  * read_barrier_depends - Flush all pending reads that subsequents reads
  * depend on.
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 46ac73abd5e..2e1ad4c652b 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -14,8 +14,10 @@
 #endif
 
 #include <linux/compiler.h>
+#include <linux/irqflags.h>
 #include <linux/types.h>
 #include <asm/barrier.h>
+#include <asm/bug.h>
 #include <asm/byteorder.h>              /* sigh ... */
 #include <asm/cpu-features.h>
 #include <asm/sgidefs.h>
@@ -43,24 +45,6 @@
 #define smp_mb__before_clear_bit()      smp_mb__before_llsc()
 #define smp_mb__after_clear_bit()       smp_llsc_mb()
 
-
-/*
- * These are the "slower" versions of the functions and are in bitops.c.
- * These functions call raw_local_irq_{save,restore}().
- */
-void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
-void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
-void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
-int __mips_test_and_set_bit(unsigned long nr,
-                            volatile unsigned long *addr);
-int __mips_test_and_set_bit_lock(unsigned long nr,
-                                 volatile unsigned long *addr);
-int __mips_test_and_clear_bit(unsigned long nr,
-                              volatile unsigned long *addr);
-int __mips_test_and_change_bit(unsigned long nr,
-                               volatile unsigned long *addr);
-
-
 /*
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
@@ -74,7 +58,7 @@ int __mips_test_and_change_bit(unsigned long nr,
 static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 {
         unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-        int bit = nr & SZLONG_MASK;
+        unsigned short bit = nr & SZLONG_MASK;
         unsigned long temp;
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -109,8 +93,17 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                         : "=&r" (temp), "+m" (*m)
                         : "ir" (1UL << bit));
                 } while (unlikely(!temp));
-        } else
-                __mips_set_bit(nr, addr);
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                *a |= mask;
+                raw_local_irq_restore(flags);
+        }
 }
 
 /*
@@ -126,7 +119,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 {
         unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-        int bit = nr & SZLONG_MASK;
+        unsigned short bit = nr & SZLONG_MASK;
         unsigned long temp;
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -161,8 +154,17 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                         : "=&r" (temp), "+m" (*m)
                         : "ir" (~(1UL << bit)));
                 } while (unlikely(!temp));
-        } else
-                __mips_clear_bit(nr, addr);
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                *a &= ~mask;
+                raw_local_irq_restore(flags);
+        }
 }
 
 /*
@@ -190,7 +192,7 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad
  */
 static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 {
-        int bit = nr & SZLONG_MASK;
+        unsigned short bit = nr & SZLONG_MASK;
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -219,8 +221,17 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                         : "=&r" (temp), "+m" (*m)
                         : "ir" (1UL << bit));
                 } while (unlikely(!temp));
-        } else
-                __mips_change_bit(nr, addr);
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                *a ^= mask;
+                raw_local_irq_restore(flags);
+        }
 }
 
 /*
@@ -234,7 +245,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 static inline int test_and_set_bit(unsigned long nr,
         volatile unsigned long *addr)
 {
-        int bit = nr & SZLONG_MASK;
+        unsigned short bit = nr & SZLONG_MASK;
         unsigned long res;
 
         smp_mb__before_llsc();
@@ -271,8 +282,18 @@ static inline int test_and_set_bit(unsigned long nr,
                 } while (unlikely(!res));
 
                 res = temp & (1UL << bit);
-        } else
-                res = __mips_test_and_set_bit(nr, addr);
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                res = (mask & *a);
+                *a |= mask;
+                raw_local_irq_restore(flags);
+        }
 
         smp_llsc_mb();
 
@@ -290,7 +311,7 @@ static inline int test_and_set_bit(unsigned long nr,
 static inline int test_and_set_bit_lock(unsigned long nr,
         volatile unsigned long *addr)
 {
-        int bit = nr & SZLONG_MASK;
+        unsigned short bit = nr & SZLONG_MASK;
         unsigned long res;
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -325,8 +346,18 @@ static inline int test_and_set_bit_lock(unsigned long nr,
                 } while (unlikely(!res));
 
                 res = temp & (1UL << bit);
-        } else
-                res = __mips_test_and_set_bit_lock(nr, addr);
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                res = (mask & *a);
+                *a |= mask;
+                raw_local_irq_restore(flags);
+        }
 
         smp_llsc_mb();
 
@@ -343,7 +374,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
 static inline int test_and_clear_bit(unsigned long nr,
         volatile unsigned long *addr)
 {
-        int bit = nr & SZLONG_MASK;
+        unsigned short bit = nr & SZLONG_MASK;
         unsigned long res;
 
         smp_mb__before_llsc();
@@ -398,8 +429,18 @@ static inline int test_and_clear_bit(unsigned long nr,
                 } while (unlikely(!res));
 
                 res = temp & (1UL << bit);
-        } else
-                res = __mips_test_and_clear_bit(nr, addr);
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                res = (mask & *a);
+                *a &= ~mask;
+                raw_local_irq_restore(flags);
+        }
 
         smp_llsc_mb();
 
@@ -417,7 +458,7 @@ static inline int test_and_clear_bit(unsigned long nr,
 static inline int test_and_change_bit(unsigned long nr,
         volatile unsigned long *addr)
 {
-        int bit = nr & SZLONG_MASK;
+        unsigned short bit = nr & SZLONG_MASK;
         unsigned long res;
 
         smp_mb__before_llsc();
@@ -454,8 +495,18 @@ static inline int test_and_change_bit(unsigned long nr,
                 } while (unlikely(!res));
 
                 res = temp & (1UL << bit);
-        } else
-                res = __mips_test_and_change_bit(nr, addr);
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                res = (mask & *a);
+                *a ^= mask;
+                raw_local_irq_restore(flags);
+        }
 
         smp_llsc_mb();
 
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
deleted file mode 100644
index 552a65a0cf2..00000000000
--- a/arch/mips/include/asm/bmips.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
- *
- * Definitions for BMIPS processors
- */
-#ifndef _ASM_BMIPS_H
-#define _ASM_BMIPS_H
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <asm/addrspace.h>
-#include <asm/mipsregs.h>
-#include <asm/hazards.h>
-
-/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
-#define BMIPS_GET_CBR()                 ((void __iomem *)(CKSEG1 | \
-                                         (unsigned long) \
-                                         ((read_c0_brcm_cbr() >> 18) << 18)))
-
-#define BMIPS_RAC_CONFIG                0x00000000
-#define BMIPS_RAC_ADDRESS_RANGE         0x00000004
-#define BMIPS_RAC_CONFIG_1              0x00000008
-#define BMIPS_L2_CONFIG                 0x0000000c
-#define BMIPS_LMB_CONTROL               0x0000001c
-#define BMIPS_SYSTEM_BASE               0x00000020
-#define BMIPS_PERF_GLOBAL_CONTROL       0x00020000
-#define BMIPS_PERF_CONTROL_0            0x00020004
-#define BMIPS_PERF_CONTROL_1            0x00020008
-#define BMIPS_PERF_COUNTER_0            0x00020010
-#define BMIPS_PERF_COUNTER_1            0x00020014
-#define BMIPS_PERF_COUNTER_2            0x00020018
-#define BMIPS_PERF_COUNTER_3            0x0002001c
-#define BMIPS_RELO_VECTOR_CONTROL_0     0x00030000
-#define BMIPS_RELO_VECTOR_CONTROL_1     0x00038000
-
-#define BMIPS_NMI_RESET_VEC             0x80000000
-#define BMIPS_WARM_RESTART_VEC          0x80000380
-
-#define ZSCM_REG_BASE                   0x97000000
-
-#if !defined(__ASSEMBLY__)
-
-#include <linux/cpumask.h>
-#include <asm/r4kcache.h>
-
-extern struct plat_smp_ops bmips_smp_ops;
-extern char bmips_reset_nmi_vec;
-extern char bmips_reset_nmi_vec_end;
-extern char bmips_smp_movevec;
-extern char bmips_smp_int_vec;
-extern char bmips_smp_int_vec_end;
-
-extern int bmips_smp_enabled;
-extern int bmips_cpu_offset;
-extern cpumask_t bmips_booted_mask;
-
-extern void bmips_ebase_setup(void);
-extern asmlinkage void plat_wired_tlb_setup(void);
-
-static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
-{
-        unsigned long ret;
-
-        __asm__ __volatile__(
-                ".set push\n"
-                ".set noreorder\n"
-                "cache %1, 0(%2)\n"
-                "sync\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                "mfc0 %0, $28, 3\n"
-                "_ssnop\n"
-                ".set pop\n"
-                : "=&r" (ret)
-                : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
-                : "memory");
-        return ret;
-}
-
-static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
-{
-        __asm__ __volatile__(
-                ".set push\n"
-                ".set noreorder\n"
-                "mtc0 %0, $28, 3\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                "cache %1, 0(%2)\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                "_ssnop\n"
-                : /* no outputs */
-                : "r" (data),
-                  "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
-                : "memory");
-}
-
-#endif /* !defined(__ASSEMBLY__) */
-
-#endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 7a51d879e6c..35cd1bab69c 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -86,7 +86,6 @@ extern unsigned long mips_machtype;
 #define BOOT_MEM_RAM            1
 #define BOOT_MEM_ROM_DATA       2
 #define BOOT_MEM_RESERVED       3
-#define BOOT_MEM_INIT_RAM       4
 
 /*
  * A memory map that's built upon what was determined
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index 888766ae1f8..37c6857c8d4 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -9,7 +9,6 @@
 #define _ASM_BRANCH_H
 
 #include <asm/ptrace.h>
-#include <asm/inst.h>
 
 static inline int delay_slot(struct pt_regs *regs)
 {
@@ -24,11 +23,7 @@ static inline unsigned long exception_epc(struct pt_regs *regs)
         return regs->cp0_epc + 4;
 }
 
-#define BRANCH_LIKELY_TAKEN 0x0001
-
 extern int __compute_return_epc(struct pt_regs *regs);
-extern int __compute_return_epc_for_insn(struct pt_regs *regs,
-                                         union mips_instruction insn);
 
 static inline int compute_return_epc(struct pt_regs *regs)
 {
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 69468ded282..40bb9fde205 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -114,28 +114,4 @@ unsigned long run_uncached(void *func);
 extern void *kmap_coherent(struct page *page, unsigned long addr);
 extern void kunmap_coherent(void);
 
-#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
-static inline void flush_kernel_dcache_page(struct page *page)
-{
-        BUG_ON(cpu_has_dc_aliases && PageHighMem(page));
-}
-
-/*
- * For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
- * cache writeback and invalidate operation.
- */
-extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
-
-static inline void flush_kernel_vmap_range(void *vaddr, int size)
-{
-        if (cpu_has_dc_aliases)
-                __flush_kernel_vmap_range((unsigned long) vaddr, size);
-}
-
-static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
-{
-        if (cpu_has_dc_aliases)
-                __flush_kernel_vmap_range((unsigned long) vaddr, size);
-}
-
 #endif /* _ASM_CACHEFLUSH_H */
diff --git a/arch/mips/include/asm/clkdev.h b/arch/mips/include/asm/clkdev.h
deleted file mode 100644
index 262475414e5..00000000000
--- a/arch/mips/include/asm/clkdev.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *  based on arch/arm/include/asm/clkdev.h
- *
- *  Copyright (C) 2008 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Helper for the clk API to assist looking up a struct clk.
- */
-#ifndef __ASM_CLKDEV_H
-#define __ASM_CLKDEV_H
-
-#include <linux/slab.h>
-
-#define __clk_get(clk)  ({ 1; })
-#define __clk_put(clk)  do { } while (0)
-
-static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
-{
-        return kzalloc(size, GFP_KERNEL);
-}
-
-#endif
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
index c9456e7a728..83894aa7932 100644
--- a/arch/mips/include/asm/clock.h
+++ b/arch/mips/include/asm/clock.h
@@ -50,4 +50,15 @@ void clk_recalc_rate(struct clk *);
 int clk_register(struct clk *);
 void clk_unregister(struct clk *);
 
+/* the exported API, in addition to clk_set_rate */
+/**
+ * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ * @algo_id: algorithm id to be passed down to ops->set_rate
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
+
 #endif                          /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index eee10dc07ac..d8d1c2805ac 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -8,132 +8,7 @@
 #ifndef __ASM_CMPXCHG_H
 #define __ASM_CMPXCHG_H
 
-#include <linux/bug.h>
 #include <linux/irqflags.h>
-#include <asm/war.h>
-
-static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
-{
-        __u32 retval;
-
-        smp_mb__before_llsc();
-
-        if (kernel_uses_llsc && R10000_LLSC_WAR) {
-                unsigned long dummy;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %3                  # xchg_u32      \n"
-                "       .set    mips0                                   \n"
-                "       move    %2, %z4                                 \n"
-                "       .set    mips3                                   \n"
-                "       sc      %2, %1                                  \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
-        } else if (kernel_uses_llsc) {
-                unsigned long dummy;
-
-                do {
-                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
-                        "       ll      %0, %3          # xchg_u32      \n"
-                        "       .set    mips0                           \n"
-                        "       move    %2, %z4                         \n"
-                        "       .set    mips3                           \n"
-                        "       sc      %2, %1                          \n"
-                        "       .set    mips0                           \n"
-                        : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                        : "R" (*m), "Jr" (val)
-                        : "memory");
-                } while (unlikely(!dummy));
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                retval = *m;
-                *m = val;
-                raw_local_irq_restore(flags);   /* implies memory barrier  */
-        }
-
-        smp_llsc_mb();
-
-        return retval;
-}
-
-#ifdef CONFIG_64BIT
-static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
-{
-        __u64 retval;
-
-        smp_mb__before_llsc();
-
-        if (kernel_uses_llsc && R10000_LLSC_WAR) {
-                unsigned long dummy;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %3                  # xchg_u64      \n"
-                "       move    %2, %z4                                 \n"
-                "       scd     %2, %1                                  \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
-        } else if (kernel_uses_llsc) {
-                unsigned long dummy;
-
-                do {
-                        __asm__ __volatile__(
-                        "       .set    mips3                           \n"
-                        "       lld     %0, %3          # xchg_u64      \n"
-                        "       move    %2, %z4                         \n"
-                        "       scd     %2, %1                          \n"
-                        "       .set    mips0                           \n"
-                        : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                        : "R" (*m), "Jr" (val)
-                        : "memory");
-                } while (unlikely(!dummy));
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                retval = *m;
-                *m = val;
-                raw_local_irq_restore(flags);   /* implies memory barrier  */
-        }
-
-        smp_llsc_mb();
-
-        return retval;
-}
-#else
-extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
-#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
-#endif
-
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
-{
-        switch (size) {
-        case 4:
-                return __xchg_u32(ptr, x);
-        case 8:
-                return __xchg_u64(ptr, x);
-        }
-
-        return x;
-}
-
-#define xchg(ptr, x)                                                    \
-({                                                                      \
-        BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc);                            \
-                                                                        \
-        ((__typeof__(*(ptr)))                                           \
-                __xchg((unsigned long)(x), (ptr), sizeof(*(ptr))));     \
-})
 
 #define __HAVE_ARCH_CMPXCHG 1
 
diff --git a/arch/mips/include/asm/compat-signal.h b/arch/mips/include/asm/compat-signal.h
index 6599a901b63..368a99e5c3e 100644
--- a/arch/mips/include/asm/compat-signal.h
+++ b/arch/mips/include/asm/compat-signal.h
@@ -10,6 +10,68 @@
 
 #include <asm/uaccess.h>
 
+#define SI_PAD_SIZE32   ((SI_MAX_SIZE/sizeof(int)) - 3)
+
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_code;
+        int si_errno;
+
+        union {
+                int _pad[SI_PAD_SIZE32];
+
+                /* kill() */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        compat_uid_t _uid;      /* sender's uid */
+                } _kill;
+
+                /* SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        compat_uid_t _uid;      /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* IRIX SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        compat_clock_t _utime;
+                        int _status;            /* exit code */
+                        compat_clock_t _stime;
+                } _irix_sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        s32 _addr; /* faulting insn/memory ref. */
+                } _sigfault;
+
+                /* SIGPOLL, SIGXFSZ (To do ...)  */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+
+                /* POSIX.1b timers */
+                struct {
+                        timer_t _tid;           /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;/* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        compat_uid_t _uid;      /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+        } _sifields;
+} compat_siginfo_t;
+
 static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
         const sigset_t *s)
 {
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index 3c5d1464b7b..dbc51065df5 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -43,7 +43,6 @@ typedef s64		compat_s64;
 typedef u32             compat_uint_t;
 typedef u32             compat_ulong_t;
 typedef u64             compat_u64;
-typedef u32             compat_uptr_t;
 
 struct compat_timespec {
         compat_time_t   tv_sec;
@@ -112,8 +111,7 @@ struct compat_statfs {
         int             f_bavail;
         compat_fsid_t   f_fsid;
         int             f_namelen;
-        int             f_flags;
-        int             f_spare[5];
+        int             f_spare[6];
 };
 
 #define COMPAT_RLIM_INFINITY    0x7fffffffUL
@@ -125,73 +123,6 @@ typedef u32		compat_old_sigset_t;	/* at least 32 bits */
 
 typedef u32             compat_sigset_word;
 
-typedef union compat_sigval {
-        compat_int_t    sival_int;
-        compat_uptr_t   sival_ptr;
-} compat_sigval_t;
-
-#define SI_PAD_SIZE32   (128/sizeof(int) - 3)
-
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_code;
-        int si_errno;
-
-        union {
-                int _pad[SI_PAD_SIZE32];
-
-                /* kill() */
-                struct {
-                        compat_pid_t _pid;      /* sender's pid */
-                        __compat_uid_t _uid;    /* sender's uid */
-                } _kill;
-
-                /* SIGCHLD */
-                struct {
-                        compat_pid_t _pid;      /* which child */
-                        __compat_uid_t _uid;    /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* IRIX SIGCHLD */
-                struct {
-                        compat_pid_t _pid;      /* which child */
-                        compat_clock_t _utime;
-                        int _status;            /* exit code */
-                        compat_clock_t _stime;
-                } _irix_sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        s32 _addr; /* faulting insn/memory ref. */
-                } _sigfault;
-
-                /* SIGPOLL, SIGXFSZ (To do ...)  */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-
-                /* POSIX.1b timers */
-                struct {
-                        timer_t _tid;           /* timer id */
-                        int _overrun;           /* overrun count */
-                        compat_sigval_t _sigval;/* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        compat_pid_t _pid;      /* sender's pid */
-                        __compat_uid_t _uid;    /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-        } _sifields;
-} compat_siginfo_t;
-
 #define COMPAT_OFF_T_MAX        0x7fffffff
 #define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
 
@@ -201,6 +132,7 @@ typedef struct compat_siginfo {
  * as pointers because the syscall entry code will have
  * appropriately converted them already.
  */
+typedef u32             compat_uptr_t;
 
 static inline void __user *compat_ptr(compat_uptr_t uptr)
 {
@@ -290,7 +222,7 @@ struct compat_shmid64_ds {
 
 static inline int is_compat_task(void)
 {
-        return test_thread_flag(TIF_32BIT_ADDR);
+        return test_thread_flag(TIF_32BIT);
 }
 
 #endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c507b931b48..ca400f7c3f5 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -95,8 +95,8 @@
 #ifndef cpu_has_smartmips
 #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 #endif
-#ifndef cpu_has_rixi
-#define cpu_has_rixi            (cpu_data[0].options & MIPS_CPU_RIXI)
+#ifndef kernel_uses_smartmips_rixi
+#define kernel_uses_smartmips_rixi 0
 #endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
@@ -171,10 +171,6 @@
 #define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
 #endif
 
-#ifndef cpu_has_dsp2
-#define cpu_has_dsp2            (cpu_data[0].ases & MIPS_ASE_DSP2P)
-#endif
-
 #ifndef cpu_has_mipsmt
 #define cpu_has_mipsmt          (cpu_data[0].ases & MIPS_ASE_MIPSMT)
 #endif
@@ -256,8 +252,4 @@
 #define cpu_hwrena_impl_bits            0
 #endif
 
-#ifndef cpu_has_perf_cntr_intr_bit
-#define cpu_has_perf_cntr_intr_bit      (cpu_data[0].options & MIPS_CPU_PCI)
-#endif
-
 #endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 90112adb194..5f95a4bfc73 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -94,8 +94,6 @@
 #define PRID_IMP_24KE           0x9600
 #define PRID_IMP_74K            0x9700
 #define PRID_IMP_1004K          0x9900
-#define PRID_IMP_1074K          0x9a00
-#define PRID_IMP_M14KC          0x9c00
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -137,9 +135,6 @@
 #define PRID_IMP_CAVIUM_CN50XX 0x0600
 #define PRID_IMP_CAVIUM_CN52XX 0x0700
 #define PRID_IMP_CAVIUM_CN63XX 0x9000
-#define PRID_IMP_CAVIUM_CN68XX 0x9100
-#define PRID_IMP_CAVIUM_CN66XX 0x9200
-#define PRID_IMP_CAVIUM_CN61XX 0x9300
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -171,10 +166,6 @@
 #define PRID_IMP_NETLOGIC_XLS412B       0x4c00
 #define PRID_IMP_NETLOGIC_XLS408B       0x4e00
 #define PRID_IMP_NETLOGIC_XLS404B       0x4f00
-#define PRID_IMP_NETLOGIC_AU13XX        0x8000
-
-#define PRID_IMP_NETLOGIC_XLP8XX        0x1000
-#define PRID_IMP_NETLOGIC_XLP3XX        0x1100
 
 /*
  * Definitions for 7:0 on legacy processors
@@ -198,7 +189,6 @@
 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 #define PRID_REV_VR4130         0x0080
 #define PRID_REV_34K_V1_0_2     0x0022
-#define PRID_REV_LOONGSON1B     0x0020
 #define PRID_REV_LOONGSON2E     0x0002
 #define PRID_REV_LOONGSON2F     0x0003
 
@@ -243,9 +233,9 @@ enum cpu_type_enum {
          */
         CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
         CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
-        CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
-        CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
-        CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
+        CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
+        CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
+        CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
         CPU_SR71000, CPU_RM9000, CPU_TX49XX,
 
         /*
@@ -263,14 +253,14 @@ enum cpu_type_enum {
          */
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
         CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
-        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
+        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
 
         /*
          * MIPS64 class processors
          */
-        CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
+        CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
         CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
-        CPU_XLR, CPU_XLP,
+        CPU_XLR,
 
         CPU_LAST
 };
@@ -291,7 +281,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_ISA_M64R2      0x00000100
 
 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
-        MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2)
+        MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
         MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
 
@@ -320,8 +310,6 @@ enum cpu_type_enum {
 #define MIPS_CPU_VINT           0x00080000 /* CPU supports MIPSR2 vectored interrupts */
 #define MIPS_CPU_VEIC           0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
 #define MIPS_CPU_ULRI           0x00200000 /* CPU has ULRI feature */
-#define MIPS_CPU_PCI            0x00400000 /* CPU has Perf Ctr Int indicator */
-#define MIPS_CPU_RIXI           0x00800000 /* CPU has TLB Read/eXec Inhibit */
 
 /*
  * CPU ASE encodings
@@ -332,7 +320,6 @@ enum cpu_type_enum {
 #define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
 #define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
 #define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
-#define MIPS_ASE_DSP2P          0x00000040 /* Signal Processing ASE Rev 2 */
 
 
 #endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h
index dc0a5f77a35..e7cd78277c2 100644
--- a/arch/mips/include/asm/delay.h
+++ b/arch/mips/include/asm/delay.h
@@ -13,9 +13,9 @@
 
 #include <linux/param.h>
 
-extern void __delay(unsigned long loops);
-extern void __ndelay(unsigned long ns);
-extern void __udelay(unsigned long us);
+extern void __delay(unsigned int loops);
+extern void __ndelay(unsigned int ns);
+extern void __udelay(unsigned int us);
 
 #define ndelay(ns) __ndelay(ns)
 #define udelay(us) __udelay(us)
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 006b43e38a9..7aa37ddfca4 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -40,8 +40,6 @@ static inline int dma_supported(struct device *dev, u64 mask)
 static inline int dma_mapping_error(struct device *dev, u64 mask)
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
-
-        debug_dma_mapping_error(dev, mask);
         return ops->mapping_error(dev, mask);
 }
 
@@ -59,31 +57,25 @@ dma_set_mask(struct device *dev, u64 mask)
 extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                enum dma_data_direction direction);
 
-#define dma_alloc_coherent(d,s,h,f)     dma_alloc_attrs(d,s,h,f,NULL)
-
-static inline void *dma_alloc_attrs(struct device *dev, size_t size,
-                                    dma_addr_t *dma_handle, gfp_t gfp,
-                                    struct dma_attrs *attrs)
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t *dma_handle, gfp_t gfp)
 {
         void *ret;
         struct dma_map_ops *ops = get_dma_ops(dev);
 
-        ret = ops->alloc(dev, size, dma_handle, gfp, attrs);
+        ret = ops->alloc_coherent(dev, size, dma_handle, gfp);
 
         debug_dma_alloc_coherent(dev, size, *dma_handle, ret);
 
         return ret;
 }
 
-#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
-
-static inline void dma_free_attrs(struct device *dev, size_t size,
-                                  void *vaddr, dma_addr_t dma_handle,
-                                  struct dma_attrs *attrs)
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *vaddr, dma_addr_t dma_handle)
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
 
-        ops->free(dev, size, vaddr, dma_handle, attrs);
+        ops->free_coherent(dev, size, vaddr, dma_handle);
 
         debug_dma_free_coherent(dev, size, vaddr, dma_handle);
 }
diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
index f5097f65a8a..2d47da62d5a 100644
--- a/arch/mips/include/asm/dma.h
+++ b/arch/mips/include/asm/dma.h
@@ -15,6 +15,7 @@
 #include <asm/io.h>                     /* need byte IO */
 #include <linux/spinlock.h>             /* And spinlocks */
 #include <linux/delay.h>
+#include <asm/system.h>
 
 
 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
diff --git a/arch/mips/include/asm/errno.h b/arch/mips/include/asm/errno.h
index 21d91cdfe3c..6dcd3583ed0 100644
--- a/arch/mips/include/asm/errno.h
+++ b/arch/mips/include/asm/errno.h
@@ -8,10 +8,128 @@
 #ifndef _ASM_ERRNO_H
 #define _ASM_ERRNO_H
 
-#include <uapi/asm/errno.h>
+/*
+ * These error numbers are intended to be MIPS ABI compatible
+ */
+
+#include <asm-generic/errno-base.h>
+
+#define ENOMSG          35      /* No message of desired type */
+#define EIDRM           36      /* Identifier removed */
+#define ECHRNG          37      /* Channel number out of range */
+#define EL2NSYNC        38      /* Level 2 not synchronized */
+#define EL3HLT          39      /* Level 3 halted */
+#define EL3RST          40      /* Level 3 reset */
+#define ELNRNG          41      /* Link number out of range */
+#define EUNATCH         42      /* Protocol driver not attached */
+#define ENOCSI          43      /* No CSI structure available */
+#define EL2HLT          44      /* Level 2 halted */
+#define EDEADLK         45      /* Resource deadlock would occur */
+#define ENOLCK          46      /* No record locks available */
+#define EBADE           50      /* Invalid exchange */
+#define EBADR           51      /* Invalid request descriptor */
+#define EXFULL          52      /* Exchange full */
+#define ENOANO          53      /* No anode */
+#define EBADRQC         54      /* Invalid request code */
+#define EBADSLT         55      /* Invalid slot */
+#define EDEADLOCK       56      /* File locking deadlock error */
+#define EBFONT          59      /* Bad font file format */
+#define ENOSTR          60      /* Device not a stream */
+#define ENODATA         61      /* No data available */
+#define ETIME           62      /* Timer expired */
+#define ENOSR           63      /* Out of streams resources */
+#define ENONET          64      /* Machine is not on the network */
+#define ENOPKG          65      /* Package not installed */
+#define EREMOTE         66      /* Object is remote */
+#define ENOLINK         67      /* Link has been severed */
+#define EADV            68      /* Advertise error */
+#define ESRMNT          69      /* Srmount error */
+#define ECOMM           70      /* Communication error on send */
+#define EPROTO          71      /* Protocol error */
+#define EDOTDOT         73      /* RFS specific error */
+#define EMULTIHOP       74      /* Multihop attempted */
+#define EBADMSG         77      /* Not a data message */
+#define ENAMETOOLONG    78      /* File name too long */
+#define EOVERFLOW       79      /* Value too large for defined data type */
+#define ENOTUNIQ        80      /* Name not unique on network */
+#define EBADFD          81      /* File descriptor in bad state */
+#define EREMCHG         82      /* Remote address changed */
+#define ELIBACC         83      /* Can not access a needed shared library */
+#define ELIBBAD         84      /* Accessing a corrupted shared library */
+#define ELIBSCN         85      /* .lib section in a.out corrupted */
+#define ELIBMAX         86      /* Attempting to link in too many shared libraries */
+#define ELIBEXEC        87      /* Cannot exec a shared library directly */
+#define EILSEQ          88      /* Illegal byte sequence */
+#define ENOSYS          89      /* Function not implemented */
+#define ELOOP           90      /* Too many symbolic links encountered */
+#define ERESTART        91      /* Interrupted system call should be restarted */
+#define ESTRPIPE        92      /* Streams pipe error */
+#define ENOTEMPTY       93      /* Directory not empty */
+#define EUSERS          94      /* Too many users */
+#define ENOTSOCK        95      /* Socket operation on non-socket */
+#define EDESTADDRREQ    96      /* Destination address required */
+#define EMSGSIZE        97      /* Message too long */
+#define EPROTOTYPE      98      /* Protocol wrong type for socket */
+#define ENOPROTOOPT     99      /* Protocol not available */
+#define EPROTONOSUPPORT 120     /* Protocol not supported */
+#define ESOCKTNOSUPPORT 121     /* Socket type not supported */
+#define EOPNOTSUPP      122     /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT    123     /* Protocol family not supported */
+#define EAFNOSUPPORT    124     /* Address family not supported by protocol */
+#define EADDRINUSE      125     /* Address already in use */
+#define EADDRNOTAVAIL   126     /* Cannot assign requested address */
+#define ENETDOWN        127     /* Network is down */
+#define ENETUNREACH     128     /* Network is unreachable */
+#define ENETRESET       129     /* Network dropped connection because of reset */
+#define ECONNABORTED    130     /* Software caused connection abort */
+#define ECONNRESET      131     /* Connection reset by peer */
+#define ENOBUFS         132     /* No buffer space available */
+#define EISCONN         133     /* Transport endpoint is already connected */
+#define ENOTCONN        134     /* Transport endpoint is not connected */
+#define EUCLEAN         135     /* Structure needs cleaning */
+#define ENOTNAM         137     /* Not a XENIX named type file */
+#define ENAVAIL         138     /* No XENIX semaphores available */
+#define EISNAM          139     /* Is a named type file */
+#define EREMOTEIO       140     /* Remote I/O error */
+#define EINIT           141     /* Reserved */
+#define EREMDEV         142     /* Error 142 */
+#define ESHUTDOWN       143     /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS    144     /* Too many references: cannot splice */
+#define ETIMEDOUT       145     /* Connection timed out */
+#define ECONNREFUSED    146     /* Connection refused */
+#define EHOSTDOWN       147     /* Host is down */
+#define EHOSTUNREACH    148     /* No route to host */
+#define EWOULDBLOCK     EAGAIN  /* Operation would block */
+#define EALREADY        149     /* Operation already in progress */
+#define EINPROGRESS     150     /* Operation now in progress */
+#define ESTALE          151     /* Stale NFS file handle */
+#define ECANCELED       158     /* AIO operation canceled */
+
+/*
+ * These error are Linux extensions.
+ */
+#define ENOMEDIUM       159     /* No medium found */
+#define EMEDIUMTYPE     160     /* Wrong medium type */
+#define ENOKEY          161     /* Required key not available */
+#define EKEYEXPIRED     162     /* Key has expired */
+#define EKEYREVOKED     163     /* Key has been revoked */
+#define EKEYREJECTED    164     /* Key was rejected by service */
+
+/* for robust mutexes */
+#define EOWNERDEAD      165     /* Owner died */
+#define ENOTRECOVERABLE 166     /* State not recoverable */
+
+#define ERFKILL         167     /* Operation not possible due to RF-kill */
 
+#define EHWPOISON       168     /* Memory page has hardware error */
+
+#define EDQUOT          1133    /* Quota exceeded */
+
+#ifdef __KERNEL__
 
 /* The biggest error number defined here or in <linux/errno.h>. */
 #define EMAXERRNO       1133
 
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_ERRNO_H */
diff --git a/arch/mips/include/asm/exec.h b/arch/mips/include/asm/exec.h
deleted file mode 100644
index c1f6afa4bc4..00000000000
--- a/arch/mips/include/asm/exec.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
- * Copyright (C) 1996 by Paul M. Antoine
- * Copyright (C) 1999 Silicon Graphics
- * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.
- */
-#ifndef _ASM_EXEC_H
-#define _ASM_EXEC_H
-
-extern unsigned long arch_align_stack(unsigned long sp);
-
-#endif /* _ASM_EXEC_H */
diff --git a/arch/mips/include/asm/fw/arc/types.h b/arch/mips/include/asm/fw/arc/types.h
index 2b11f87d6fb..b9adcd6f086 100644
--- a/arch/mips/include/asm/fw/arc/types.h
+++ b/arch/mips/include/asm/fw/arc/types.h
@@ -10,7 +10,7 @@
 #define _ASM_ARC_TYPES_H
 
 
-#ifdef CONFIG_FW_ARC32
+#ifdef CONFIG_ARC32
 
 typedef char            CHAR;
 typedef short           SHORT;
@@ -33,9 +33,9 @@ typedef LONG		_PUSHORT;
 typedef LONG            _PULONG;
 typedef LONG            _PVOID;
 
-#endif /* CONFIG_FW_ARC32 */
+#endif /* CONFIG_ARC32 */
 
-#ifdef CONFIG_FW_ARC64
+#ifdef CONFIG_ARC64
 
 typedef char            CHAR;
 typedef short           SHORT;
@@ -57,7 +57,7 @@ typedef USHORT		*_PUSHORT;
 typedef ULONG           *_PULONG;
 typedef VOID            *_PVOID;
 
-#endif /* CONFIG_FW_ARC64  */
+#endif /* CONFIG_ARC64  */
 
 typedef CHAR            *PCHAR;
 typedef SHORT           *PSHORT;
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 37620db588b..86548da650e 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -33,13 +33,13 @@
         REG32(_gic_base + segment##_##SECTION_OFS + offset)
 
 #define GIC_ABS_REG(segment, offset) \
-        (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
+       (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
 #define GIC_REG_ABS_ADDR(segment, offset) \
-        (_gic_base + segment##_##SECTION_OFS + offset)
+       (_gic_base + segment##_##SECTION_OFS + offset)
 
 #ifdef GICISBYTELITTLEENDIAN
-#define GICREAD(reg, data)      ((data) = (reg), (data) = le32_to_cpu(data))
-#define GICWRITE(reg, data)     ((reg) = cpu_to_le32(data))
+#define GICREAD(reg, data)      (data) = (reg), (data) = le32_to_cpu(data)
+#define GICWRITE(reg, data)     (reg) = cpu_to_le32(data)
 #define GICBIS(reg, bits)                       \
         ({unsigned int data;                    \
                 GICREAD(reg, data);             \
@@ -48,9 +48,9 @@
         })
 
 #else
-#define GICREAD(reg, data)      ((data) = (reg))
-#define GICWRITE(reg, data)     ((reg) = (data))
-#define GICBIS(reg, bits)       ((reg) |= (bits))
+#define GICREAD(reg, data)      (data) = (reg)
+#define GICWRITE(reg, data)     (reg) = (data)
+#define GICBIS(reg, bits)       (reg) |= (bits)
 #endif
 
 
@@ -206,7 +206,7 @@
 
 #define GIC_VPE_EIC_SHADOW_SET_BASE     0x0100
 #define GIC_VPE_EIC_SS(intr) \
-        (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
+        (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
 
 #define GIC_VPE_EIC_VEC_BASE            0x0800
 #define GIC_VPE_EIC_VEC(intr) \
@@ -304,15 +304,15 @@
                  GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
 
 struct gic_pcpu_mask {
-        DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
+       DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
 };
 
 struct gic_pending_regs {
-        DECLARE_BITMAP(pending, GIC_NUM_INTRS);
+       DECLARE_BITMAP(pending, GIC_NUM_INTRS);
 };
 
 struct gic_intrmask_regs {
-        DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
+       DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
 };
 
 /*
@@ -330,55 +330,13 @@ struct gic_intr_map {
 #define GIC_FLAG_TRANSPARENT   0x02
 };
 
-/*
- * This is only used in EIC mode. This helps to figure out which
- * shared interrupts we need to process when we get a vector interrupt.
- */
-#define GIC_MAX_SHARED_INTR  0x5
-struct gic_shared_intr_map {
-        unsigned int num_shared_intr;
-        unsigned int intr_list[GIC_MAX_SHARED_INTR];
-        unsigned int local_intr_mask;
-};
-
-/* GIC nomenclature for Core Interrupt Pins. */
-#define GIC_CPU_INT0            0 /* Core Interrupt 2 */
-#define GIC_CPU_INT1            1 /* .                */
-#define GIC_CPU_INT2            2 /* .                */
-#define GIC_CPU_INT3            3 /* .                */
-#define GIC_CPU_INT4            4 /* .                */
-#define GIC_CPU_INT5            5 /* Core Interrupt 5 */
-
-/* Local GIC interrupts. */
-#define GIC_INT_TMR             (GIC_CPU_INT5)
-#define GIC_INT_PERFCTR         (GIC_CPU_INT5)
-
-/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
-#define GIC_CPU_TO_VEC_OFFSET   (2)
-
-/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
-#define GIC_PIN_TO_VEC_OFFSET   (1)
-
-extern unsigned long _gic_base;
-extern unsigned int gic_irq_base;
-extern unsigned int gic_irq_flags[];
-extern struct gic_shared_intr_map gic_shared_intr_map[];
-
 extern void gic_init(unsigned long gic_base_addr,
         unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
         unsigned int intrmap_size, unsigned int irqbase);
 
-extern void gic_clocksource_init(unsigned int);
 extern unsigned int gic_get_int(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
-extern void gic_bind_eic_interrupt(int irq, int set);
-extern unsigned int gic_get_timer_pending(void);
-extern void gic_enable_interrupt(int irq_vec);
-extern void gic_disable_interrupt(int irq_vec);
-extern void gic_irq_ack(struct irq_data *d);
-extern void gic_finish_irq(struct irq_data *d);
-extern void gic_platform_init(int irqs, struct irq_chip *irq_controller);
 
 #endif /* _ASM_GICREGS_H */
diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h
deleted file mode 100644
index 5437c84664b..00000000000
--- a/arch/mips/include/asm/gio_device.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#include <linux/device.h>
-#include <linux/mod_devicetable.h>
-
-struct gio_device_id {
-        __u8 id;
-};
-
-struct gio_device {
-        struct device   dev;
-        struct resource resource;
-        unsigned int    irq;
-        unsigned int    slotno;
-
-        const char      *name;
-        struct gio_device_id id;
-        unsigned        id32:1;
-        unsigned        gio64:1;
-};
-#define to_gio_device(d) container_of(d, struct gio_device, dev)
-
-struct gio_driver {
-        const char    *name;
-        struct module *owner;
-        const struct gio_device_id *id_table;
-
-        int  (*probe)(struct gio_device *, const struct gio_device_id *);
-        void (*remove)(struct gio_device *);
-        int  (*suspend)(struct gio_device *, pm_message_t);
-        int  (*resume)(struct gio_device *);
-        void (*shutdown)(struct gio_device *);
-
-        struct device_driver driver;
-};
-#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver)
-
-extern const struct gio_device_id *gio_match_device(const struct gio_device_id *,
-                                                    const struct gio_device *);
-extern struct gio_device *gio_dev_get(struct gio_device *);
-extern void gio_dev_put(struct gio_device *);
-
-extern int gio_device_register(struct gio_device *);
-extern void gio_device_unregister(struct gio_device *);
-extern void gio_release_dev(struct device *);
-
-static inline void gio_device_free(struct gio_device *dev)
-{
-        gio_release_dev(&dev->dev);
-}
-
-extern int gio_register_driver(struct gio_driver *);
-extern void gio_unregister_driver(struct gio_driver *);
-
-#define gio_get_drvdata(_dev)        drv_get_drvdata(&(_dev)->dev)
-#define gio_set_drvdata(_dev, data)  drv_set_drvdata(&(_dev)->dev, (data))
-
-extern void gio_set_master(struct gio_device *);
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index f0324e92d08..4e332165d7b 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,8 +87,7 @@ do {									\
         : "=r" (tmp));                                                  \
 } while (0)
 
-#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
-        defined(CONFIG_CPU_BMIPS)
+#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -140,8 +139,8 @@ do {									\
 } while (0)
 
 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
-        defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
-        defined(CONFIG_CPU_R5500)
+      defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
+      defined(CONFIG_CPU_R5500)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -161,6 +160,31 @@ ASMMACRO(back_to_back_c0_hazard,
         )
 #define instruction_hazard() do { } while (0)
 
+#elif defined(CONFIG_CPU_RM9000)
+
+/*
+ * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
+ * use of the JTLB for instructions should not occur for 4 cpu cycles and use
+ * for data translations should not occur for 3 cpu cycles.
+ */
+
+ASMMACRO(mtc0_tlbw_hazard,
+         _ssnop; _ssnop; _ssnop; _ssnop
+        )
+ASMMACRO(tlbw_use_hazard,
+         _ssnop; _ssnop; _ssnop; _ssnop
+        )
+ASMMACRO(tlb_probe_hazard,
+         _ssnop; _ssnop; _ssnop; _ssnop
+        )
+ASMMACRO(irq_enable_hazard,
+        )
+ASMMACRO(irq_disable_hazard,
+        )
+ASMMACRO(back_to_back_c0_hazard,
+        )
+#define instruction_hazard() do { } while (0)
+
 #elif defined(CONFIG_CPU_SB1)
 
 /*
diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h
index 2d91888c9b7..77e644082a3 100644
--- a/arch/mips/include/asm/highmem.h
+++ b/arch/mips/include/asm/highmem.h
@@ -47,7 +47,7 @@ extern void kunmap_high(struct page *page);
 
 extern void *kmap(struct page *page);
 extern void kunmap(struct page *page);
-extern void *kmap_atomic(struct page *page);
+extern void *__kmap_atomic(struct page *page);
 extern void __kunmap_atomic(void *kvaddr);
 extern void *kmap_atomic_pfn(unsigned long pfn);
 extern struct page *kmap_atomic_to_page(void *ptr);
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index ef99db994c2..c565b7c3f0b 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -70,7 +70,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
 static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
                                          unsigned long addr, pte_t *ptep)
 {
-        flush_tlb_page(vma, addr & huge_page_mask(hstate_vma(vma)));
+        flush_tlb_mm(vma->vm_mm);
 }
 
 static inline int huge_pte_none(pte_t pte)
@@ -95,17 +95,7 @@ static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
                                              pte_t *ptep, pte_t pte,
                                              int dirty)
 {
-        int changed = !pte_same(*ptep, pte);
-
-        if (changed) {
-                set_pte_at(vma->vm_mm, addr, ptep, pte);
-                /*
-                 * There could be some standard sized pages in there,
-                 * get them all.
-                 */
-                flush_tlb_range(vma, addr, addr + HPAGE_SIZE);
-        }
-        return changed;
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
 }
 
 static inline pte_t huge_ptep_get(pte_t *ptep)
@@ -122,8 +112,4 @@ static inline void arch_release_hugepage(struct page *page)
 {
 }
 
-static inline void arch_clear_hugepage_flags(struct page *page)
-{
-}
-
 #endif /* __ASM_HUGETLB_H */
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index ab84064283d..7ebfc392e58 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -251,7 +251,7 @@ struct f_format {	/* FPU register format */
         unsigned int func : 6;
 };
 
-struct ma_format {      /* FPU multiply and add format (MIPS IV) */
+struct ma_format {      /* FPU multipy and add format (MIPS IV) */
         unsigned int opcode : 6;
         unsigned int fr : 5;
         unsigned int ft : 5;
@@ -324,7 +324,7 @@ struct f_format {	/* FPU register format */
         unsigned int opcode : 6;
 };
 
-struct ma_format {      /* FPU multiply and add format (MIPS IV) */
+struct ma_format {      /* FPU multipy and add format (MIPS IV) */
         unsigned int fmt : 2;
         unsigned int func : 4;
         unsigned int fd : 5;
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index ff2e0345e01..b04e4de5dd2 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -15,10 +15,8 @@
 #include <linux/compiler.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/irqflags.h>
 
 #include <asm/addrspace.h>
-#include <asm/bug.h>
 #include <asm/byteorder.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
@@ -331,10 +329,14 @@ static inline void pfx##write##bwlq(type val,				\
                         "dsrl32 %L0, %L0, 0"                    "\n\t"  \
                         "dsll32 %M0, %M0, 0"                    "\n\t"  \
                         "or     %L0, %L0, %M0"                  "\n\t"  \
+                        ".set   push"                           "\n\t"  \
+                        ".set   noreorder"                      "\n\t"  \
+                        ".set   nomacro"                        "\n\t"  \
                         "sd     %L0, %2"                        "\n\t"  \
+                        ".set   pop"                            "\n\t"  \
                         ".set   mips0"                          "\n"    \
                         : "=r" (__tmp)                                  \
-                        : "0" (__val), "m" (*__mem));                   \
+                        : "0" (__val), "R" (*__mem));                   \
                 if (irq)                                                \
                         local_irq_restore(__flags);                     \
         } else                                                          \
@@ -357,12 +359,16 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem)	\
                         local_irq_save(__flags);                        \
                 __asm__ __volatile__(                                   \
                         ".set   mips3"          "\t\t# __readq" "\n\t"  \
+                        ".set   push"                           "\n\t"  \
+                        ".set   noreorder"                      "\n\t"  \
+                        ".set   nomacro"                        "\n\t"  \
                         "ld     %L0, %1"                        "\n\t"  \
+                        ".set   pop"                            "\n\t"  \
                         "dsra32 %M0, %L0, 0"                    "\n\t"  \
                         "sll    %L0, %L0, 0"                    "\n\t"  \
                         ".set   mips0"                          "\n"    \
                         : "=r" (__val)                                  \
-                        : "m" (*__mem));                                \
+                        : "R" (*__mem));                                \
                 if (irq)                                                \
                         local_irq_restore(__flags);                     \
         } else {                                                        \
diff --git a/arch/mips/include/asm/ip32/mace.h b/arch/mips/include/asm/ip32/mace.h
index c523123df38..d08d7c67213 100644
--- a/arch/mips/include/asm/ip32/mace.h
+++ b/arch/mips/include/asm/ip32/mace.h
@@ -95,7 +95,7 @@ struct mace_video {
  * Ethernet interface
  */
 struct mace_ethernet {
-        volatile u64 mac_ctrl;
+        volatile unsigned long mac_ctrl;
         volatile unsigned long int_stat;
         volatile unsigned long dma_ctrl;
         volatile unsigned long timer;
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 78dbb8a86da..2354c870a63 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -11,12 +11,15 @@
 
 #include <linux/linkage.h>
 #include <linux/smp.h>
-#include <linux/irqdomain.h>
 
 #include <asm/mipsmtregs.h>
 
 #include <irq.h>
 
+static inline void irq_dispose_mapping(unsigned int virq)
+{
+}
+
 #ifdef CONFIG_I8259
 static inline int irq_canonicalize(int irq)
 {
@@ -136,7 +139,6 @@ extern void free_irqno(unsigned int irq);
  * IE7.  Since R2 their number has to be read from the c0_intctl register.
  */
 #define CP0_LEGACY_COMPARE_IRQ 7
-#define CP0_LEGACY_PERFCNT_IRQ 7
 
 extern int cp0_compare_irq;
 extern int cp0_compare_irq_shift;
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 9f3384c789d..309cbcd6909 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -16,13 +16,83 @@
 #include <linux/compiler.h>
 #include <asm/hazards.h>
 
-#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC)
+__asm__(
+        "       .macro  arch_local_irq_enable                           \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    $1, $2, 1       # SMTC - clear TCStatus.IXMT    \n"
+        "       ori     $1, 0x400                                       \n"
+        "       xori    $1, 0x400                                       \n"
+        "       mtc0    $1, $2, 1                                       \n"
+#elif defined(CONFIG_CPU_MIPSR2)
+        "       ei                                                      \n"
+#else
+        "       mfc0    $1,$12                                          \n"
+        "       ori     $1,0x1f                                         \n"
+        "       xori    $1,0x1e                                         \n"
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       irq_enable_hazard                                       \n"
+        "       .set    pop                                             \n"
+        "       .endm");
 
+extern void smtc_ipi_replay(void);
+
+static inline void arch_local_irq_enable(void)
+{
+#ifdef CONFIG_MIPS_MT_SMTC
+        /*
+         * SMTC kernel needs to do a software replay of queued
+         * IPIs, at the cost of call overhead on each local_irq_enable()
+         */
+        smtc_ipi_replay();
+#endif
+        __asm__ __volatile__(
+                "arch_local_irq_enable"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory");
+}
+
+
+/*
+ * For cli() we have to insert nops to make sure that the new value
+ * has actually arrived in the status register before the end of this
+ * macro.
+ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
+ * no nops at all.
+ */
+/*
+ * For TX49, operating only IE bit is not enough.
+ *
+ * If mfc0 $12 follows store and the mfc0 is last instruction of a
+ * page and fetching the next instruction causes TLB miss, the result
+ * of the mfc0 might wrongly contain EXL bit.
+ *
+ * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
+ *
+ * Workaround: mask EXL bit of the result or place a nop before mfc0.
+ */
 __asm__(
         "       .macro  arch_local_irq_disable\n"
         "       .set    push                                            \n"
         "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    $1, $2, 1                                       \n"
+        "       ori     $1, 0x400                                       \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $2, 1                                       \n"
+#elif defined(CONFIG_CPU_MIPSR2)
         "       di                                                      \n"
+#else
+        "       mfc0    $1,$12                                          \n"
+        "       ori     $1,0x1f                                         \n"
+        "       xori    $1,0x1f                                         \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1,$12                                          \n"
+#endif
         "       irq_disable_hazard                                      \n"
         "       .set    pop                                             \n"
         "       .endm                                                   \n");
@@ -36,14 +106,46 @@ static inline void arch_local_irq_disable(void)
                 : "memory");
 }
 
+__asm__(
+        "       .macro  arch_local_save_flags flags                     \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    \\flags, $2, 1                                  \n"
+#else
+        "       mfc0    \\flags, $12                                    \n"
+#endif
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
+
+static inline unsigned long arch_local_save_flags(void)
+{
+        unsigned long flags;
+        asm volatile("arch_local_save_flags %0" : "=r" (flags));
+        return flags;
+}
 
 __asm__(
         "       .macro  arch_local_irq_save result                      \n"
         "       .set    push                                            \n"
         "       .set    reorder                                         \n"
         "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    \\result, $2, 1                                 \n"
+        "       ori     $1, \\result, 0x400                             \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $2, 1                                       \n"
+        "       andi    \\result, \\result, 0x400                       \n"
+#elif defined(CONFIG_CPU_MIPSR2)
         "       di      \\result                                        \n"
         "       andi    \\result, 1                                     \n"
+#else
+        "       mfc0    \\result, $12                                   \n"
+        "       ori     $1, \\result, 0x1f                              \n"
+        "       xori    $1, 0x1f                                        \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $12                                         \n"
+#endif
         "       irq_disable_hazard                                      \n"
         "       .set    pop                                             \n"
         "       .endm                                                   \n");
@@ -58,37 +160,61 @@ static inline unsigned long arch_local_irq_save(void)
         return flags;
 }
 
-
 __asm__(
         "       .macro  arch_local_irq_restore flags                    \n"
         "       .set    push                                            \n"
         "       .set    noreorder                                       \n"
         "       .set    noat                                            \n"
-#if defined(CONFIG_IRQ_CPU)
+#ifdef CONFIG_MIPS_MT_SMTC
+        "mfc0   $1, $2, 1                                               \n"
+        "andi   \\flags, 0x400                                          \n"
+        "ori    $1, 0x400                                               \n"
+        "xori   $1, 0x400                                               \n"
+        "or     \\flags, $1                                             \n"
+        "mtc0   \\flags, $2, 1                                          \n"
+#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
         /*
          * Slow, but doesn't suffer from a relatively unlikely race
          * condition we're having since days 1.
          */
         "       beqz    \\flags, 1f                                     \n"
-        "       di                                                      \n"
+        "        di                                                     \n"
         "       ei                                                      \n"
         "1:                                                             \n"
-#else
+#elif defined(CONFIG_CPU_MIPSR2)
         /*
          * Fast, dangerous.  Life is fun, life is good.
          */
         "       mfc0    $1, $12                                         \n"
         "       ins     $1, \\flags, 0, 1                               \n"
         "       mtc0    $1, $12                                         \n"
+#else
+        "       mfc0    $1, $12                                         \n"
+        "       andi    \\flags, 1                                      \n"
+        "       ori     $1, 0x1f                                        \n"
+        "       xori    $1, 0x1f                                        \n"
+        "       or      \\flags, $1                                     \n"
+        "       mtc0    \\flags, $12                                    \n"
 #endif
         "       irq_disable_hazard                                      \n"
         "       .set    pop                                             \n"
         "       .endm                                                   \n");
 
+
 static inline void arch_local_irq_restore(unsigned long flags)
 {
         unsigned long __tmp1;
 
+#ifdef CONFIG_MIPS_MT_SMTC
+        /*
+         * SMTC kernel needs to do a software replay of queued
+         * IPIs, at the cost of branch and call overhead on each
+         * local_irq_restore()
+         */
+        if (unlikely(!(flags & 0x0400)))
+                smtc_ipi_replay();
+#endif
+
         __asm__ __volatile__(
                 "arch_local_irq_restore\t%0"
                 : "=r" (__tmp1)
@@ -106,75 +232,6 @@ static inline void __arch_local_irq_restore(unsigned long flags)
                 : "0" (flags)
                 : "memory");
 }
-#else
-/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */
-void arch_local_irq_disable(void);
-unsigned long arch_local_irq_save(void);
-void arch_local_irq_restore(unsigned long flags);
-void __arch_local_irq_restore(unsigned long flags);
-#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */
-
-
-__asm__(
-        "       .macro  arch_local_irq_enable                           \n"
-        "       .set    push                                            \n"
-        "       .set    reorder                                         \n"
-        "       .set    noat                                            \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    $1, $2, 1       # SMTC - clear TCStatus.IXMT    \n"
-        "       ori     $1, 0x400                                       \n"
-        "       xori    $1, 0x400                                       \n"
-        "       mtc0    $1, $2, 1                                       \n"
-#elif defined(CONFIG_CPU_MIPSR2)
-        "       ei                                                      \n"
-#else
-        "       mfc0    $1,$12                                          \n"
-        "       ori     $1,0x1f                                         \n"
-        "       xori    $1,0x1e                                         \n"
-        "       mtc0    $1,$12                                          \n"
-#endif
-        "       irq_enable_hazard                                       \n"
-        "       .set    pop                                             \n"
-        "       .endm");
-
-extern void smtc_ipi_replay(void);
-
-static inline void arch_local_irq_enable(void)
-{
-#ifdef CONFIG_MIPS_MT_SMTC
-        /*
-         * SMTC kernel needs to do a software replay of queued
-         * IPIs, at the cost of call overhead on each local_irq_enable()
-         */
-        smtc_ipi_replay();
-#endif
-        __asm__ __volatile__(
-                "arch_local_irq_enable"
-                : /* no outputs */
-                : /* no inputs */
-                : "memory");
-}
-
-
-__asm__(
-        "       .macro  arch_local_save_flags flags                     \n"
-        "       .set    push                                            \n"
-        "       .set    reorder                                         \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    \\flags, $2, 1                                  \n"
-#else
-        "       mfc0    \\flags, $12                                    \n"
-#endif
-        "       .set    pop                                             \n"
-        "       .endm                                                   \n");
-
-static inline unsigned long arch_local_save_flags(void)
-{
-        unsigned long flags;
-        asm volatile("arch_local_save_flags %0" : "=r" (flags));
-        return flags;
-}
-
 
 static inline int arch_irqs_disabled_flags(unsigned long flags)
 {
@@ -188,7 +245,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
 #endif
 }
 
-#endif /* #ifndef __ASSEMBLY__ */
+#endif
 
 /*
  * Do the CPU's IRQ-state tracing from assembly code.
diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h
index 4d6d77ed9b9..1881b316ca4 100644
--- a/arch/mips/include/asm/jump_label.h
+++ b/arch/mips/include/asm/jump_label.h
@@ -20,7 +20,7 @@
 #define WORD_INSN ".word"
 #endif
 
-static __always_inline bool arch_static_branch(struct static_key *key)
+static __always_inline bool arch_static_branch(struct jump_label_key *key)
 {
         asm goto("1:\tnop\n\t"
                 "nop\n\t"
diff --git a/arch/mips/include/asm/kexec.h b/arch/mips/include/asm/kexec.h
index ee25ebbf2a2..4314892aaeb 100644
--- a/arch/mips/include/asm/kexec.h
+++ b/arch/mips/include/asm/kexec.h
@@ -9,43 +9,22 @@
 #ifndef _MIPS_KEXEC
 # define _MIPS_KEXEC
 
-#include <asm/stacktrace.h>
-
 /* Maximum physical address we can use pages from */
 #define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000)
 /* Maximum address we can reach in physical address mode */
 #define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000)
  /* Maximum address we can use for the control code buffer */
 #define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000)
-/* Reserve 3*4096 bytes for board-specific info */
-#define KEXEC_CONTROL_PAGE_SIZE (4096 + 3*4096)
+
+#define KEXEC_CONTROL_PAGE_SIZE 4096
 
 /* The native architecture */
 #define KEXEC_ARCH KEXEC_ARCH_MIPS
-#define MAX_NOTE_BYTES 1024
 
 static inline void crash_setup_regs(struct pt_regs *newregs,
                                     struct pt_regs *oldregs)
 {
-        if (oldregs)
-                memcpy(newregs, oldregs, sizeof(*newregs));
-        else
-                prepare_frametrace(newregs);
+        /* Dummy implementation for now */
 }
 
-#ifdef CONFIG_KEXEC
-struct kimage;
-extern unsigned long kexec_args[4];
-extern int (*_machine_kexec_prepare)(struct kimage *);
-extern void (*_machine_kexec_shutdown)(void);
-extern void (*_machine_crash_shutdown)(struct pt_regs *regs);
-extern void default_machine_crash_shutdown(struct pt_regs *regs);
-#ifdef CONFIG_SMP
-extern const unsigned char kexec_smp_wait[];
-extern unsigned long secondary_kexec_args[4];
-extern void (*relocated_kexec_smp_wait) (void *);
-extern atomic_t kexec_ready_to_reboot;
-#endif
-#endif
-
 #endif /* !_MIPS_KEXEC */
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
index 1fbbca01e68..e6ea4d4d720 100644
--- a/arch/mips/include/asm/kprobes.h
+++ b/arch/mips/include/asm/kprobes.h
@@ -74,8 +74,6 @@ struct prev_kprobe {
                 : MAX_JPROBES_STACK_SIZE)
 
 
-#define SKIP_DELAYSLOT 0x0001
-
 /* per-cpu kprobe control block */
 struct kprobe_ctlblk {
         unsigned long kprobe_status;
@@ -84,9 +82,6 @@ struct kprobe_ctlblk {
         unsigned long kprobe_saved_epc;
         unsigned long jprobe_saved_sp;
         struct pt_regs jprobe_saved_regs;
-        /* Per-thread fields, used while emulating branches */
-        unsigned long flags;
-        unsigned long target_epc;
         u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
         struct prev_kprobe prev_kprobe;
 };
diff --git a/arch/mips/include/asm/kspd.h b/arch/mips/include/asm/kspd.h
index ec6832950ac..4e9e724c893 100644
--- a/arch/mips/include/asm/kspd.h
+++ b/arch/mips/include/asm/kspd.h
@@ -25,8 +25,12 @@ struct kspd_notifications {
         struct list_head list;
 };
 
+#ifdef CONFIG_MIPS_APSP_KSPD
+extern void kspd_notify(struct kspd_notifications *notify);
+#else
 static inline void kspd_notify(struct kspd_notifications *notify)
 {
 }
+#endif
 
 #endif
diff --git a/arch/mips/include/asm/lasat/lasat.h b/arch/mips/include/asm/lasat/lasat.h
index e8ff70f80e1..a1ada1c27c1 100644
--- a/arch/mips/include/asm/lasat/lasat.h
+++ b/arch/mips/include/asm/lasat/lasat.h
@@ -41,8 +41,10 @@ enum lasat_mtdparts {
 
 /*
  * The format of the data record in the EEPROM.
- * See the LASAT Hardware Configuration field specification for a detailed
- * description of the config field.
+ * See Documentation/LASAT/eeprom.txt for a detailed description
+ * of the fields in this struct, and the LASAT Hardware Configuration
+ * field specification for a detailed description of the config
+ * field.
  */
 #include <linux/types.h>
 
diff --git a/arch/mips/include/asm/mach-ar7/war.h b/arch/mips/include/asm/mach-ar7/war.h
index 99071e50faa..f4862b56308 100644
--- a/arch/mips/include/asm/mach-ar7/war.h
+++ b/arch/mips/include/asm/mach-ar7/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index a5e0f17ea77..cda1c8070b2 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -1,11 +1,10 @@
 /*
  *  Atheros AR71XX/AR724X/AR913X SoC register definitions
  *
- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
- *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
@@ -21,10 +20,6 @@
 #include <linux/bitops.h>
 
 #define AR71XX_APB_BASE         0x18000000
-#define AR71XX_EHCI_BASE        0x1b000000
-#define AR71XX_EHCI_SIZE        0x1000
-#define AR71XX_OHCI_BASE        0x1c000000
-#define AR71XX_OHCI_SIZE        0x1000
 #define AR71XX_SPI_BASE         0x1f000000
 #define AR71XX_SPI_SIZE         0x01000000
 
@@ -32,8 +27,6 @@
 #define AR71XX_DDR_CTRL_SIZE    0x100
 #define AR71XX_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
 #define AR71XX_UART_SIZE        0x100
-#define AR71XX_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
-#define AR71XX_USB_CTRL_SIZE    0x100
 #define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
 #define AR71XX_GPIO_SIZE        0x100
 #define AR71XX_PLL_BASE         (AR71XX_APB_BASE + 0x00050000)
@@ -41,33 +34,9 @@
 #define AR71XX_RESET_BASE       (AR71XX_APB_BASE + 0x00060000)
 #define AR71XX_RESET_SIZE       0x100
 
-#define AR7240_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
-#define AR7240_USB_CTRL_SIZE    0x100
-#define AR7240_OHCI_BASE        0x1b000000
-#define AR7240_OHCI_SIZE        0x1000
-
-#define AR724X_EHCI_BASE        0x1b000000
-#define AR724X_EHCI_SIZE        0x1000
-
-#define AR913X_EHCI_BASE        0x1b000000
-#define AR913X_EHCI_SIZE        0x1000
 #define AR913X_WMAC_BASE        (AR71XX_APB_BASE + 0x000C0000)
 #define AR913X_WMAC_SIZE        0x30000
 
-#define AR933X_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
-#define AR933X_UART_SIZE        0x14
-#define AR933X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
-#define AR933X_WMAC_SIZE        0x20000
-#define AR933X_EHCI_BASE        0x1b000000
-#define AR933X_EHCI_SIZE        0x1000
-
-#define AR934X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
-#define AR934X_WMAC_SIZE        0x20000
-#define AR934X_EHCI_BASE        0x1b000000
-#define AR934X_EHCI_SIZE        0x200
-#define AR934X_SRIF_BASE        (AR71XX_APB_BASE + 0x00116000)
-#define AR934X_SRIF_SIZE        0x1000
-
 /*
  * DDR_CTRL block
  */
@@ -94,17 +63,6 @@
 #define AR913X_DDR_REG_FLUSH_USB        0x84
 #define AR913X_DDR_REG_FLUSH_WMAC       0x88
 
-#define AR933X_DDR_REG_FLUSH_GE0        0x7c
-#define AR933X_DDR_REG_FLUSH_GE1        0x80
-#define AR933X_DDR_REG_FLUSH_USB        0x84
-#define AR933X_DDR_REG_FLUSH_WMAC       0x88
-
-#define AR934X_DDR_REG_FLUSH_GE0        0x9c
-#define AR934X_DDR_REG_FLUSH_GE1        0xa0
-#define AR934X_DDR_REG_FLUSH_USB        0xa4
-#define AR934X_DDR_REG_FLUSH_PCIE       0xa8
-#define AR934X_DDR_REG_FLUSH_WMAC       0xac
-
 /*
  * PLL block
  */
@@ -146,65 +104,6 @@
 #define AR913X_AHB_DIV_SHIFT            19
 #define AR913X_AHB_DIV_MASK             0x1
 
-#define AR933X_PLL_CPU_CONFIG_REG       0x00
-#define AR933X_PLL_CLOCK_CTRL_REG       0x08
-
-#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT        10
-#define AR933X_PLL_CPU_CONFIG_NINT_MASK         0x3f
-#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT      16
-#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
-#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT      23
-#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK       0x7
-
-#define AR933X_PLL_CLOCK_CTRL_BYPASS            BIT(2)
-#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT     5
-#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK      0x3
-#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT     10
-#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK      0x3
-#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT     15
-#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK      0x7
-
-#define AR934X_PLL_CPU_CONFIG_REG               0x00
-#define AR934X_PLL_DDR_CONFIG_REG               0x04
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG         0x08
-
-#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT       0
-#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK        0x3f
-#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT        6
-#define AR934X_PLL_CPU_CONFIG_NINT_MASK         0x3f
-#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT      12
-#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
-#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT      19
-#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK       0x3
-
-#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT       0
-#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK        0x3ff
-#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT        10
-#define AR934X_PLL_DDR_CONFIG_NINT_MASK         0x3f
-#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT      16
-#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK       0x1f
-#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT      23
-#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK       0x7
-
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS      BIT(2)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS      BIT(3)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS      BIT(4)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT  5
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK   0x1f
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT  10
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK   0x1f
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT  15
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK   0x1f
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL  BIT(20)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL  BIT(21)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL  BIT(24)
-
-/*
- * USB_CONFIG block
- */
-#define AR71XX_USB_CTRL_REG_FLADJ       0x00
-#define AR71XX_USB_CTRL_REG_CONFIG      0x04
-
 /*
  * RESET block
  */
@@ -231,17 +130,6 @@
 
 #define AR724X_RESET_REG_RESET_MODULE           0x1c
 
-#define AR933X_RESET_REG_RESET_MODULE           0x1c
-#define AR933X_RESET_REG_BOOTSTRAP              0xac
-
-#define AR934X_RESET_REG_RESET_MODULE           0x1c
-#define AR934X_RESET_REG_BOOTSTRAP              0xb0
-#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS   0xac
-
-#define MISC_INT_ETHSW                  BIT(12)
-#define MISC_INT_TIMER4                 BIT(10)
-#define MISC_INT_TIMER3                 BIT(9)
-#define MISC_INT_TIMER2                 BIT(8)
 #define MISC_INT_DMA                    BIT(7)
 #define MISC_INT_OHCI                   BIT(6)
 #define MISC_INT_PERFC                  BIT(5)
@@ -270,68 +158,14 @@
 #define AR71XX_RESET_PCI_BUS            BIT(1)
 #define AR71XX_RESET_PCI_CORE           BIT(0)
 
-#define AR7240_RESET_USB_HOST           BIT(5)
-#define AR7240_RESET_OHCI_DLL           BIT(3)
-
 #define AR724X_RESET_GE1_MDIO           BIT(23)
 #define AR724X_RESET_GE0_MDIO           BIT(22)
 #define AR724X_RESET_PCIE_PHY_SERIAL    BIT(10)
 #define AR724X_RESET_PCIE_PHY           BIT(7)
 #define AR724X_RESET_PCIE               BIT(6)
-#define AR724X_RESET_USB_HOST           BIT(5)
-#define AR724X_RESET_USB_PHY            BIT(4)
-#define AR724X_RESET_USBSUS_OVERRIDE    BIT(3)
+#define AR724X_RESET_OHCI_DLL           BIT(3)
 
 #define AR913X_RESET_AMBA2WMAC          BIT(22)
-#define AR913X_RESET_USBSUS_OVERRIDE    BIT(10)
-#define AR913X_RESET_USB_HOST           BIT(5)
-#define AR913X_RESET_USB_PHY            BIT(4)
-
-#define AR933X_RESET_WMAC               BIT(11)
-#define AR933X_RESET_USB_HOST           BIT(5)
-#define AR933X_RESET_USB_PHY            BIT(4)
-#define AR933X_RESET_USBSUS_OVERRIDE    BIT(3)
-
-#define AR934X_RESET_USB_PHY_ANALOG     BIT(11)
-#define AR934X_RESET_USB_HOST           BIT(5)
-#define AR934X_RESET_USB_PHY            BIT(4)
-#define AR934X_RESET_USBSUS_OVERRIDE    BIT(3)
-
-#define AR933X_BOOTSTRAP_REF_CLK_40     BIT(0)
-
-#define AR934X_BOOTSTRAP_SW_OPTION8     BIT(23)
-#define AR934X_BOOTSTRAP_SW_OPTION7     BIT(22)
-#define AR934X_BOOTSTRAP_SW_OPTION6     BIT(21)
-#define AR934X_BOOTSTRAP_SW_OPTION5     BIT(20)
-#define AR934X_BOOTSTRAP_SW_OPTION4     BIT(19)
-#define AR934X_BOOTSTRAP_SW_OPTION3     BIT(18)
-#define AR934X_BOOTSTRAP_SW_OPTION2     BIT(17)
-#define AR934X_BOOTSTRAP_SW_OPTION1     BIT(16)
-#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
-#define AR934X_BOOTSTRAP_PCIE_RC        BIT(6)
-#define AR934X_BOOTSTRAP_EJTAG_MODE     BIT(5)
-#define AR934X_BOOTSTRAP_REF_CLK_40     BIT(4)
-#define AR934X_BOOTSTRAP_BOOT_FROM_SPI  BIT(2)
-#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
-#define AR934X_BOOTSTRAP_DDR1           BIT(0)
-
-#define AR934X_PCIE_WMAC_INT_WMAC_MISC          BIT(0)
-#define AR934X_PCIE_WMAC_INT_WMAC_TX            BIT(1)
-#define AR934X_PCIE_WMAC_INT_WMAC_RXLP          BIT(2)
-#define AR934X_PCIE_WMAC_INT_WMAC_RXHP          BIT(3)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC            BIT(4)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC0           BIT(5)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC1           BIT(6)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC2           BIT(7)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC3           BIT(8)
-#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
-        (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
-         AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
-
-#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
-        (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
-         AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
-         AR934X_PCIE_WMAC_INT_PCIE_RC3)
 
 #define REV_ID_MAJOR_MASK               0xfff0
 #define REV_ID_MAJOR_AR71XX             0x00a0
@@ -339,11 +173,6 @@
 #define REV_ID_MAJOR_AR7240             0x00c0
 #define REV_ID_MAJOR_AR7241             0x0100
 #define REV_ID_MAJOR_AR7242             0x1100
-#define REV_ID_MAJOR_AR9330             0x0110
-#define REV_ID_MAJOR_AR9331             0x1110
-#define REV_ID_MAJOR_AR9341             0x0120
-#define REV_ID_MAJOR_AR9342             0x1120
-#define REV_ID_MAJOR_AR9344             0x2120
 
 #define AR71XX_REV_ID_MINOR_MASK        0x3
 #define AR71XX_REV_ID_MINOR_AR7130      0x0
@@ -358,12 +187,8 @@
 #define AR913X_REV_ID_REVISION_MASK     0x3
 #define AR913X_REV_ID_REVISION_SHIFT    2
 
-#define AR933X_REV_ID_REVISION_MASK     0x3
-
 #define AR724X_REV_ID_REVISION_MASK     0x3
 
-#define AR934X_REV_ID_REVISION_MASK     0xf
-
 /*
  * SPI block
  */
@@ -402,31 +227,7 @@
 #define AR71XX_GPIO_REG_FUNC            0x28
 
 #define AR71XX_GPIO_COUNT               16
-#define AR7240_GPIO_COUNT               18
-#define AR7241_GPIO_COUNT               20
+#define AR724X_GPIO_COUNT               18
 #define AR913X_GPIO_COUNT               22
-#define AR933X_GPIO_COUNT               30
-#define AR934X_GPIO_COUNT               23
-
-/*
- * SRIF block
- */
-#define AR934X_SRIF_CPU_DPLL1_REG       0x1c0
-#define AR934X_SRIF_CPU_DPLL2_REG       0x1c4
-#define AR934X_SRIF_CPU_DPLL3_REG       0x1c8
-
-#define AR934X_SRIF_DDR_DPLL1_REG       0x240
-#define AR934X_SRIF_DDR_DPLL2_REG       0x244
-#define AR934X_SRIF_DDR_DPLL3_REG       0x248
-
-#define AR934X_SRIF_DPLL1_REFDIV_SHIFT  27
-#define AR934X_SRIF_DPLL1_REFDIV_MASK   0x1f
-#define AR934X_SRIF_DPLL1_NINT_SHIFT    18
-#define AR934X_SRIF_DPLL1_NINT_MASK     0x1ff
-#define AR934X_SRIF_DPLL1_NFRAC_MASK    0x0003ffff
-
-#define AR934X_SRIF_DPLL2_LOCAL_PLL     BIT(30)
-#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT  13
-#define AR934X_SRIF_DPLL2_OUTDIV_MASK   0x7
 
 #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
deleted file mode 100644
index 52730555937..00000000000
--- a/arch/mips/include/asm/mach-ath79/ar933x_uart.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *  Atheros AR933X UART defines
- *
- *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#ifndef __AR933X_UART_H
-#define __AR933X_UART_H
-
-#define AR933X_UART_REGS_SIZE           20
-#define AR933X_UART_FIFO_SIZE           16
-
-#define AR933X_UART_DATA_REG            0x00
-#define AR933X_UART_CS_REG              0x04
-#define AR933X_UART_CLOCK_REG           0x08
-#define AR933X_UART_INT_REG             0x0c
-#define AR933X_UART_INT_EN_REG          0x10
-
-#define AR933X_UART_DATA_TX_RX_MASK     0xff
-#define AR933X_UART_DATA_RX_CSR         BIT(8)
-#define AR933X_UART_DATA_TX_CSR         BIT(9)
-
-#define AR933X_UART_CS_PARITY_S         0
-#define AR933X_UART_CS_PARITY_M         0x3
-#define   AR933X_UART_CS_PARITY_NONE    0
-#define   AR933X_UART_CS_PARITY_ODD     1
-#define   AR933X_UART_CS_PARITY_EVEN    2
-#define AR933X_UART_CS_IF_MODE_S        2
-#define AR933X_UART_CS_IF_MODE_M        0x3
-#define   AR933X_UART_CS_IF_MODE_NONE   0
-#define   AR933X_UART_CS_IF_MODE_DTE    1
-#define   AR933X_UART_CS_IF_MODE_DCE    2
-#define AR933X_UART_CS_FLOW_CTRL_S      4
-#define AR933X_UART_CS_FLOW_CTRL_M      0x3
-#define AR933X_UART_CS_DMA_EN           BIT(6)
-#define AR933X_UART_CS_TX_READY_ORIDE   BIT(7)
-#define AR933X_UART_CS_RX_READY_ORIDE   BIT(8)
-#define AR933X_UART_CS_TX_READY         BIT(9)
-#define AR933X_UART_CS_RX_BREAK         BIT(10)
-#define AR933X_UART_CS_TX_BREAK         BIT(11)
-#define AR933X_UART_CS_HOST_INT         BIT(12)
-#define AR933X_UART_CS_HOST_INT_EN      BIT(13)
-#define AR933X_UART_CS_TX_BUSY          BIT(14)
-#define AR933X_UART_CS_RX_BUSY          BIT(15)
-
-#define AR933X_UART_CLOCK_STEP_M        0xffff
-#define AR933X_UART_CLOCK_SCALE_M       0xfff
-#define AR933X_UART_CLOCK_SCALE_S       16
-#define AR933X_UART_CLOCK_STEP_M        0xffff
-
-#define AR933X_UART_INT_RX_VALID        BIT(0)
-#define AR933X_UART_INT_TX_READY        BIT(1)
-#define AR933X_UART_INT_RX_FRAMING_ERR  BIT(2)
-#define AR933X_UART_INT_RX_OFLOW_ERR    BIT(3)
-#define AR933X_UART_INT_TX_OFLOW_ERR    BIT(4)
-#define AR933X_UART_INT_RX_PARITY_ERR   BIT(5)
-#define AR933X_UART_INT_RX_BREAK_ON     BIT(6)
-#define AR933X_UART_INT_RX_BREAK_OFF    BIT(7)
-#define AR933X_UART_INT_RX_FULL         BIT(8)
-#define AR933X_UART_INT_TX_EMPTY        BIT(9)
-#define AR933X_UART_INT_ALLINTS         0x3ff
-
-#endif /* __AR933X_UART_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
deleted file mode 100644
index 6cb30f2b719..00000000000
--- a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  Platform data definition for Atheros AR933X UART
- *
- *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#ifndef _AR933X_UART_PLATFORM_H
-#define _AR933X_UART_PLATFORM_H
-
-struct ar933x_uart_platform_data {
-        unsigned        uartclk;
-};
-
-#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 4f248c3d7b2..6a9f168506f 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -26,16 +26,10 @@ enum ath79_soc_type {
         ATH79_SOC_AR7241,
         ATH79_SOC_AR7242,
         ATH79_SOC_AR9130,
-        ATH79_SOC_AR9132,
-        ATH79_SOC_AR9330,
-        ATH79_SOC_AR9331,
-        ATH79_SOC_AR9341,
-        ATH79_SOC_AR9342,
-        ATH79_SOC_AR9344,
+        ATH79_SOC_AR9132
 };
 
 extern enum ath79_soc_type ath79_soc;
-extern unsigned int ath79_soc_rev;
 
 static inline int soc_is_ar71xx(void)
 {
@@ -72,32 +66,6 @@ static inline int soc_is_ar913x(void)
                 ath79_soc == ATH79_SOC_AR9132);
 }
 
-static inline int soc_is_ar933x(void)
-{
-        return (ath79_soc == ATH79_SOC_AR9330 ||
-                ath79_soc == ATH79_SOC_AR9331);
-}
-
-static inline int soc_is_ar9341(void)
-{
-        return (ath79_soc == ATH79_SOC_AR9341);
-}
-
-static inline int soc_is_ar9342(void)
-{
-        return (ath79_soc == ATH79_SOC_AR9342);
-}
-
-static inline int soc_is_ar9344(void)
-{
-        return (ath79_soc == ATH79_SOC_AR9344);
-}
-
-static inline int soc_is_ar934x(void)
-{
-        return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
-}
-
 extern void __iomem *ath79_ddr_base;
 extern void __iomem *ath79_pll_base;
 extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
index ea4b66dccf6..4476fa03bf3 100644
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -43,7 +43,6 @@
 #define cpu_has_mips64r2        0
 
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_mipsmt          0
 
 #define cpu_has_64bits          0
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 0968f69e201..189bc6eb9c1 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,18 +10,10 @@
 #define __ASM_MACH_ATH79_IRQ_H
 
 #define MIPS_CPU_IRQ_BASE       0
-#define NR_IRQS                 48
+#define NR_IRQS                 16
 
 #define ATH79_MISC_IRQ_BASE     8
-#define ATH79_MISC_IRQ_COUNT    32
-
-#define ATH79_PCI_IRQ_BASE      (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
-#define ATH79_PCI_IRQ_COUNT     6
-#define ATH79_PCI_IRQ(_x)       (ATH79_PCI_IRQ_BASE + (_x))
-
-#define ATH79_IP2_IRQ_BASE      (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
-#define ATH79_IP2_IRQ_COUNT     2
-#define ATH79_IP2_IRQ(_x)       (ATH79_IP2_IRQ_BASE + (_x))
+#define ATH79_MISC_IRQ_COUNT    8
 
 #define ATH79_CPU_IRQ_IP2       (MIPS_CPU_IRQ_BASE + 2)
 #define ATH79_CPU_IRQ_USB       (MIPS_CPU_IRQ_BASE + 3)
@@ -38,10 +30,6 @@
 #define ATH79_MISC_IRQ_PERFC    (ATH79_MISC_IRQ_BASE + 5)
 #define ATH79_MISC_IRQ_OHCI     (ATH79_MISC_IRQ_BASE + 6)
 #define ATH79_MISC_IRQ_DMA      (ATH79_MISC_IRQ_BASE + 7)
-#define ATH79_MISC_IRQ_TIMER2   (ATH79_MISC_IRQ_BASE + 8)
-#define ATH79_MISC_IRQ_TIMER3   (ATH79_MISC_IRQ_BASE + 9)
-#define ATH79_MISC_IRQ_TIMER4   (ATH79_MISC_IRQ_BASE + 10)
-#define ATH79_MISC_IRQ_ETHSW    (ATH79_MISC_IRQ_BASE + 12)
 
 #include_next <irq.h>
 
diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h
deleted file mode 100644
index 7868f7fa028..00000000000
--- a/arch/mips/include/asm/mach-ath79/pci.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *  Atheros AR71XX/AR724X PCI support
- *
- *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_ATH79_PCI_H
-#define __ASM_MACH_ATH79_PCI_H
-
-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
-int ar71xx_pcibios_init(void);
-#else
-static inline int ar71xx_pcibios_init(void) { return 0; }
-#endif
-
-#if defined(CONFIG_PCI_AR724X)
-int ar724x_pcibios_init(int irq);
-#else
-static inline int ar724x_pcibios_init(int irq) { return 0; }
-#endif
-
-#endif /* __ASM_MACH_ATH79_PCI_H */
diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h
index 0bb30905fd5..323d9f1d8c4 100644
--- a/arch/mips/include/asm/mach-ath79/war.h
+++ b/arch/mips/include/asm/mach-ath79/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 569828d3cca..f260ebed713 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -136,7 +136,6 @@ static inline int au1xxx_cpu_needs_config_od(void)
 #define ALCHEMY_CPU_AU1100      2
 #define ALCHEMY_CPU_AU1550      3
 #define ALCHEMY_CPU_AU1200      4
-#define ALCHEMY_CPU_AU1300      5
 
 static inline int alchemy_get_cputype(void)
 {
@@ -157,9 +156,6 @@ static inline int alchemy_get_cputype(void)
         case 0x05030000:
                 return ALCHEMY_CPU_AU1200;
                 break;
-        case 0x800c0000:
-                return ALCHEMY_CPU_AU1300;
-                break;
         }
 
         return ALCHEMY_CPU_UNKNOWN;
@@ -170,7 +166,6 @@ static inline int alchemy_get_uarts(int type)
 {
         switch (type) {
         case ALCHEMY_CPU_AU1000:
-        case ALCHEMY_CPU_AU1300:
                 return 4;
         case ALCHEMY_CPU_AU1500:
         case ALCHEMY_CPU_AU1200:
@@ -248,114 +243,17 @@ extern unsigned long au1xxx_calc_clock(void);
 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
 void alchemy_sleep_au1000(void);
 void alchemy_sleep_au1550(void);
-void alchemy_sleep_au1300(void);
 void au_sleep(void);
 
-/* USB: drivers/usb/host/alchemy-common.c */
-enum alchemy_usb_block {
-        ALCHEMY_USB_OHCI0,
-        ALCHEMY_USB_UDC0,
-        ALCHEMY_USB_EHCI0,
-        ALCHEMY_USB_OTG0,
-        ALCHEMY_USB_OHCI1,
-};
-int alchemy_usb_control(int block, int enable);
-
-/* PCI controller platform data */
-struct alchemy_pci_platdata {
-        int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
-        int (*board_pci_idsel)(unsigned int devsel, int assert);
-        /* bits to set/clear in PCI_CONFIG register */
-        unsigned long pci_cfg_set;
-        unsigned long pci_cfg_clr;
-};
-
-/* Multifunction pins: Each of these pins can either be assigned to the
- * GPIO controller or a on-chip peripheral.
- * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
- * assign one of these to either the GPIO controller or the device.
- */
-enum au1300_multifunc_pins {
-        /* wake-from-str pins 0-3 */
-        AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
-        AU1300_PIN_WAKE3,
-        /* external clock sources for PSCs: 4-5 */
-        AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
-        /* 8bit MMC interface on SD0: 6-9 */
-        AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
-        AU1300_PIN_SD0DAT7,
-        /* aux clk input for freqgen 3: 10 */
-        AU1300_PIN_FG3AUX,
-        /* UART1 pins: 11-18 */
-        AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
-        AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
-        AU1300_PIN_U1RX, AU1300_PIN_U1TX,
-        /* UART0 pins: 19-24 */
-        AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
-        AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
-        /* UART2: 25-26 */
-        AU1300_PIN_U2RX, AU1300_PIN_U2TX,
-        /* UART3: 27-28 */
-        AU1300_PIN_U3RX, AU1300_PIN_U3TX,
-        /* LCD controller PWMs, ext pixclock: 29-31 */
-        AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
-        /* SD1 interface: 32-37 */
-        AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
-        AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
-        /* SD2 interface: 38-43 */
-        AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
-        AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
-        /* PSC0/1 clocks: 44-45 */
-        AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
-        /* PSCs: 46-49/50-53/54-57/58-61 */
-        AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
-        AU1300_PIN_PSC0D1,
-        AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
-        AU1300_PIN_PSC1D1,
-        AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
-        AU1300_PIN_PSC2D1,
-        AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
-        AU1300_PIN_PSC3D1,
-        /* PCMCIA interface: 62-70 */
-        AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
-        AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
-        AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
-        /* camera interface H/V sync inputs: 71-72 */
-        AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
-        /* PSC2/3 clocks: 73-74 */
-        AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
-};
-
-/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
-extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
-extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
-extern void au1300_set_irq_priority(unsigned int irq, int p);
-extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
-
-/* Au1300 allows to disconnect certain blocks from internal power supply */
-enum au1300_vss_block {
-        AU1300_VSS_MPE = 0,
-        AU1300_VSS_BSA,
-        AU1300_VSS_GPE,
-        AU1300_VSS_MGP,
-};
-
-extern void au1300_vss_block_control(int block, int enable);
-
 
 /* SOC Interrupt numbers */
-/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
+
 #define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
 #define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
 #define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_LAST + 1)
 #define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
 #define AU1000_MAX_INTR         AU1000_INTC1_INT_LAST
 
-/* Au1300-style (GPIC): 1 controller with up to 128 sources */
-#define ALCHEMY_GPIC_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
-#define ALCHEMY_GPIC_INT_NUM    128
-#define ALCHEMY_GPIC_INT_LAST   (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
-
 enum soc_au1000_ints {
         AU1000_FIRST_INT        = AU1000_INTC0_INT_BASE,
         AU1000_UART0_INT        = AU1000_FIRST_INT,
@@ -676,208 +574,39 @@ enum soc_au1200_ints {
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
-/* Au1300 peripheral interrupt numbers */
-#define AU1300_FIRST_INT        (ALCHEMY_GPIC_INT_BASE)
-#define AU1300_UART1_INT        (AU1300_FIRST_INT + 17)
-#define AU1300_UART2_INT        (AU1300_FIRST_INT + 25)
-#define AU1300_UART3_INT        (AU1300_FIRST_INT + 27)
-#define AU1300_SD1_INT          (AU1300_FIRST_INT + 32)
-#define AU1300_SD2_INT          (AU1300_FIRST_INT + 38)
-#define AU1300_PSC0_INT         (AU1300_FIRST_INT + 48)
-#define AU1300_PSC1_INT         (AU1300_FIRST_INT + 52)
-#define AU1300_PSC2_INT         (AU1300_FIRST_INT + 56)
-#define AU1300_PSC3_INT         (AU1300_FIRST_INT + 60)
-#define AU1300_NAND_INT         (AU1300_FIRST_INT + 62)
-#define AU1300_DDMA_INT         (AU1300_FIRST_INT + 75)
-#define AU1300_MMU_INT          (AU1300_FIRST_INT + 76)
-#define AU1300_MPU_INT          (AU1300_FIRST_INT + 77)
-#define AU1300_GPU_INT          (AU1300_FIRST_INT + 78)
-#define AU1300_UDMA_INT         (AU1300_FIRST_INT + 79)
-#define AU1300_TOY_INT          (AU1300_FIRST_INT + 80)
-#define AU1300_TOY_MATCH0_INT   (AU1300_FIRST_INT + 81)
-#define AU1300_TOY_MATCH1_INT   (AU1300_FIRST_INT + 82)
-#define AU1300_TOY_MATCH2_INT   (AU1300_FIRST_INT + 83)
-#define AU1300_RTC_INT          (AU1300_FIRST_INT + 84)
-#define AU1300_RTC_MATCH0_INT   (AU1300_FIRST_INT + 85)
-#define AU1300_RTC_MATCH1_INT   (AU1300_FIRST_INT + 86)
-#define AU1300_RTC_MATCH2_INT   (AU1300_FIRST_INT + 87)
-#define AU1300_UART0_INT        (AU1300_FIRST_INT + 88)
-#define AU1300_SD0_INT          (AU1300_FIRST_INT + 89)
-#define AU1300_USB_INT          (AU1300_FIRST_INT + 90)
-#define AU1300_LCD_INT          (AU1300_FIRST_INT + 91)
-#define AU1300_BSA_INT          (AU1300_FIRST_INT + 92)
-#define AU1300_MPE_INT          (AU1300_FIRST_INT + 93)
-#define AU1300_ITE_INT          (AU1300_FIRST_INT + 94)
-#define AU1300_AES_INT          (AU1300_FIRST_INT + 95)
-#define AU1300_CIM_INT          (AU1300_FIRST_INT + 96)
-
-/**********************************************************************/
-
 /*
- * Physical base addresses for integrated peripherals
- * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
+ * SDRAM register offsets
  */
-
-#define AU1000_AC97_PHYS_ADDR           0x10000000 /* 012 */
-#define AU1300_ROM_PHYS_ADDR            0x10000000 /* 5 */
-#define AU1300_OTP_PHYS_ADDR            0x10002000 /* 5 */
-#define AU1300_VSS_PHYS_ADDR            0x10003000 /* 5 */
-#define AU1300_UART0_PHYS_ADDR          0x10100000 /* 5 */
-#define AU1300_UART1_PHYS_ADDR          0x10101000 /* 5 */
-#define AU1300_UART2_PHYS_ADDR          0x10102000 /* 5 */
-#define AU1300_UART3_PHYS_ADDR          0x10103000 /* 5 */
-#define AU1000_USB_OHCI_PHYS_ADDR       0x10100000 /* 012 */
-#define AU1000_USB_UDC_PHYS_ADDR        0x10200000 /* 0123 */
-#define AU1300_GPIC_PHYS_ADDR           0x10200000 /* 5 */
-#define AU1000_IRDA_PHYS_ADDR           0x10300000 /* 02 */
-#define AU1200_AES_PHYS_ADDR            0x10300000 /* 45 */
-#define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
-#define AU1300_GPU_PHYS_ADDR            0x10500000 /* 5 */
-#define AU1000_MAC0_PHYS_ADDR           0x10500000 /* 023 */
-#define AU1000_MAC1_PHYS_ADDR           0x10510000 /* 023 */
-#define AU1000_MACEN_PHYS_ADDR          0x10520000 /* 023 */
-#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 245 */
-#define AU1300_SD1_PHYS_ADDR            0x10601000 /* 5 */
-#define AU1300_SD2_PHYS_ADDR            0x10602000 /* 5 */
-#define AU1100_SD1_PHYS_ADDR            0x10680000 /* 24 */
-#define AU1300_SYS_PHYS_ADDR            0x10900000 /* 5 */
-#define AU1550_PSC2_PHYS_ADDR           0x10A00000 /* 3 */
-#define AU1550_PSC3_PHYS_ADDR           0x10B00000 /* 3 */
-#define AU1300_PSC0_PHYS_ADDR           0x10A00000 /* 5 */
-#define AU1300_PSC1_PHYS_ADDR           0x10A01000 /* 5 */
-#define AU1300_PSC2_PHYS_ADDR           0x10A02000 /* 5 */
-#define AU1300_PSC3_PHYS_ADDR           0x10A03000 /* 5 */
-#define AU1000_I2S_PHYS_ADDR            0x11000000 /* 02 */
-#define AU1500_MAC0_PHYS_ADDR           0x11500000 /* 1 */
-#define AU1500_MAC1_PHYS_ADDR           0x11510000 /* 1 */
-#define AU1500_MACEN_PHYS_ADDR          0x11520000 /* 1 */
-#define AU1000_UART0_PHYS_ADDR          0x11100000 /* 01234 */
-#define AU1200_SWCNT_PHYS_ADDR          0x1110010C /* 4 */
-#define AU1000_UART1_PHYS_ADDR          0x11200000 /* 0234 */
-#define AU1000_UART2_PHYS_ADDR          0x11300000 /* 0 */
-#define AU1000_UART3_PHYS_ADDR          0x11400000 /* 0123 */
-#define AU1000_SSI0_PHYS_ADDR           0x11600000 /* 02 */
-#define AU1000_SSI1_PHYS_ADDR           0x11680000 /* 02 */
-#define AU1500_GPIO2_PHYS_ADDR          0x11700000 /* 1234 */
-#define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
-#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 012345 */
-#define AU1550_PSC0_PHYS_ADDR           0x11A00000 /* 34 */
-#define AU1550_PSC1_PHYS_ADDR           0x11B00000 /* 34 */
-#define AU1000_MEM_PHYS_ADDR            0x14000000 /* 01234 */
-#define AU1000_STATIC_MEM_PHYS_ADDR     0x14001000 /* 01234 */
-#define AU1300_UDMA_PHYS_ADDR           0x14001800 /* 5 */
-#define AU1000_DMA_PHYS_ADDR            0x14002000 /* 012 */
-#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 345 */
-#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 345 */
-#define AU1000_MACDMA0_PHYS_ADDR        0x14004000 /* 0123 */
-#define AU1000_MACDMA1_PHYS_ADDR        0x14004200 /* 0123 */
-#define AU1200_CIM_PHYS_ADDR            0x14004000 /* 45 */
-#define AU1500_PCI_PHYS_ADDR            0x14005000 /* 13 */
-#define AU1550_PE_PHYS_ADDR             0x14008000 /* 3 */
-#define AU1200_MAEBE_PHYS_ADDR          0x14010000 /* 4 */
-#define AU1200_MAEFE_PHYS_ADDR          0x14012000 /* 4 */
-#define AU1300_MAEITE_PHYS_ADDR         0x14010000 /* 5 */
-#define AU1300_MAEMPE_PHYS_ADDR         0x14014000 /* 5 */
-#define AU1550_USB_OHCI_PHYS_ADDR       0x14020000 /* 3 */
-#define AU1200_USB_CTL_PHYS_ADDR        0x14020000 /* 4 */
-#define AU1200_USB_OTG_PHYS_ADDR        0x14020020 /* 4 */
-#define AU1200_USB_OHCI_PHYS_ADDR       0x14020100 /* 4 */
-#define AU1200_USB_EHCI_PHYS_ADDR       0x14020200 /* 4 */
-#define AU1200_USB_UDC_PHYS_ADDR        0x14022000 /* 4 */
-#define AU1300_USB_EHCI_PHYS_ADDR       0x14020000 /* 5 */
-#define AU1300_USB_OHCI0_PHYS_ADDR      0x14020400 /* 5 */
-#define AU1300_USB_OHCI1_PHYS_ADDR      0x14020800 /* 5 */
-#define AU1300_USB_CTL_PHYS_ADDR        0x14021000 /* 5 */
-#define AU1300_USB_OTG_PHYS_ADDR        0x14022000 /* 5 */
-#define AU1300_MAEBSA_PHYS_ADDR         0x14030000 /* 5 */
-#define AU1100_LCD_PHYS_ADDR            0x15000000 /* 2 */
-#define AU1200_LCD_PHYS_ADDR            0x15000000 /* 45 */
-#define AU1500_PCI_MEM_PHYS_ADDR        0x400000000ULL /* 13 */
-#define AU1500_PCI_IO_PHYS_ADDR         0x500000000ULL /* 13 */
-#define AU1500_PCI_CONFIG0_PHYS_ADDR    0x600000000ULL /* 13 */
-#define AU1500_PCI_CONFIG1_PHYS_ADDR    0x680000000ULL /* 13 */
-#define AU1000_PCMCIA_IO_PHYS_ADDR      0xF00000000ULL /* 012345 */
-#define AU1000_PCMCIA_ATTR_PHYS_ADDR    0xF40000000ULL /* 012345 */
-#define AU1000_PCMCIA_MEM_PHYS_ADDR     0xF80000000ULL /* 012345 */
-
-/**********************************************************************/
-
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
+    defined(CONFIG_SOC_AU1100)
+#define MEM_SDMODE0             0x0000
+#define MEM_SDMODE1             0x0004
+#define MEM_SDMODE2             0x0008
+#define MEM_SDADDR0             0x000C
+#define MEM_SDADDR1             0x0010
+#define MEM_SDADDR2             0x0014
+#define MEM_SDREFCFG            0x0018
+#define MEM_SDPRECMD            0x001C
+#define MEM_SDAUTOREF           0x0020
+#define MEM_SDWRMD0             0x0024
+#define MEM_SDWRMD1             0x0028
+#define MEM_SDWRMD2             0x002C
+#define MEM_SDSLEEP             0x0030
+#define MEM_SDSMCKE             0x0034
 
 /*
- * Au1300 GPIO+INT controller (GPIC) register offsets and bits
- * Registers are 128bits (0x10 bytes), divided into 4 "banks".
+ * MEM_SDMODE register content definitions
  */
-#define AU1300_GPIC_PINVAL      0x0000
-#define AU1300_GPIC_PINVALCLR   0x0010
-#define AU1300_GPIC_IPEND       0x0020
-#define AU1300_GPIC_PRIENC      0x0030
-#define AU1300_GPIC_IEN         0x0040  /* int_mask in manual */
-#define AU1300_GPIC_IDIS        0x0050  /* int_maskclr in manual */
-#define AU1300_GPIC_DMASEL      0x0060
-#define AU1300_GPIC_DEVSEL      0x0080
-#define AU1300_GPIC_DEVCLR      0x0090
-#define AU1300_GPIC_RSTVAL      0x00a0
-/* pin configuration space. one 32bit register for up to 128 IRQs */
-#define AU1300_GPIC_PINCFG      0x1000
-
-#define GPIC_GPIO_TO_BIT(gpio)  \
-        (1 << ((gpio) & 0x1f))
-
-#define GPIC_GPIO_BANKOFF(gpio) \
-        (((gpio) >> 5) * 4)
-
-/* Pin Control bits: who owns the pin, what does it do */
-#define GPIC_CFG_PC_GPIN                0
-#define GPIC_CFG_PC_DEV                 1
-#define GPIC_CFG_PC_GPOLOW              2
-#define GPIC_CFG_PC_GPOHIGH             3
-#define GPIC_CFG_PC_MASK                3
-
-/* assign pin to MIPS IRQ line */
-#define GPIC_CFG_IL_SET(x)      (((x) & 3) << 2)
-#define GPIC_CFG_IL_MASK        (3 << 2)
-
-/* pin interrupt type setup */
-#define GPIC_CFG_IC_OFF         (0 << 4)
-#define GPIC_CFG_IC_LEVEL_LOW   (1 << 4)
-#define GPIC_CFG_IC_LEVEL_HIGH  (2 << 4)
-#define GPIC_CFG_IC_EDGE_FALL   (5 << 4)
-#define GPIC_CFG_IC_EDGE_RISE   (6 << 4)
-#define GPIC_CFG_IC_EDGE_BOTH   (7 << 4)
-#define GPIC_CFG_IC_MASK        (7 << 4)
-
-/* allow interrupt to wake cpu from 'wait' */
-#define GPIC_CFG_IDLEWAKE       (1 << 7)
-
-/***********************************************************************/
-
-/* Au1000 SDRAM memory controller register offsets */
-#define AU1000_MEM_SDMODE0              0x0000
-#define AU1000_MEM_SDMODE1              0x0004
-#define AU1000_MEM_SDMODE2              0x0008
-#define AU1000_MEM_SDADDR0              0x000C
-#define AU1000_MEM_SDADDR1              0x0010
-#define AU1000_MEM_SDADDR2              0x0014
-#define AU1000_MEM_SDREFCFG             0x0018
-#define AU1000_MEM_SDPRECMD             0x001C
-#define AU1000_MEM_SDAUTOREF            0x0020
-#define AU1000_MEM_SDWRMD0              0x0024
-#define AU1000_MEM_SDWRMD1              0x0028
-#define AU1000_MEM_SDWRMD2              0x002C
-#define AU1000_MEM_SDSLEEP              0x0030
-#define AU1000_MEM_SDSMCKE              0x0034
-
-/* MEM_SDMODE register content definitions */
 #define MEM_SDMODE_F            (1 << 22)
 #define MEM_SDMODE_SR           (1 << 21)
 #define MEM_SDMODE_BS           (1 << 20)
 #define MEM_SDMODE_RS           (3 << 18)
 #define MEM_SDMODE_CS           (7 << 15)
-#define MEM_SDMODE_TRAS         (15 << 11)
-#define MEM_SDMODE_TMRD         (3 << 9)
+#define MEM_SDMODE_TRAS         (15 << 11)
+#define MEM_SDMODE_TMRD         (3 << 9)
 #define MEM_SDMODE_TWR          (3 << 7)
 #define MEM_SDMODE_TRP          (3 << 5)
-#define MEM_SDMODE_TRCD         (3 << 3)
+#define MEM_SDMODE_TRCD         (3 << 3)
 #define MEM_SDMODE_TCL          (7 << 0)
 
 #define MEM_SDMODE_BS_2Bank     (0 << 20)
@@ -899,43 +628,173 @@ enum soc_au1200_ints {
 #define MEM_SDMODE_TRCD_N(N)    ((N) << 3)
 #define MEM_SDMODE_TCL_N(N)     ((N) << 0)
 
-/* MEM_SDADDR register contents definitions */
+/*
+ * MEM_SDADDR register contents definitions
+ */
 #define MEM_SDADDR_E            (1 << 20)
-#define MEM_SDADDR_CSBA         (0x03FF << 10)
+#define MEM_SDADDR_CSBA         (0x03FF << 10)
 #define MEM_SDADDR_CSMASK       (0x03FF << 0)
 #define MEM_SDADDR_CSBA_N(N)    ((N) & (0x03FF << 22) >> 12)
 #define MEM_SDADDR_CSMASK_N(N)  ((N)&(0x03FF << 22) >> 22)
 
-/* MEM_SDREFCFG register content definitions */
+/*
+ * MEM_SDREFCFG register content definitions
+ */
 #define MEM_SDREFCFG_TRC        (15 << 28)
 #define MEM_SDREFCFG_TRPM       (3 << 26)
 #define MEM_SDREFCFG_E          (1 << 25)
-#define MEM_SDREFCFG_RE         (0x1ffffff << 0)
+#define MEM_SDREFCFG_RE         (0x1ffffff << 0)
 #define MEM_SDREFCFG_TRC_N(N)   ((N) << MEM_SDREFCFG_TRC)
 #define MEM_SDREFCFG_TRPM_N(N)  ((N) << MEM_SDREFCFG_TRPM)
 #define MEM_SDREFCFG_REF_N(N)   (N)
+#endif
+
+/***********************************************************************/
+
+/*
+ * Au1550 SDRAM Register Offsets
+ */
+
+/***********************************************************************/
+
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+#define MEM_SDMODE0             0x0800
+#define MEM_SDMODE1             0x0808
+#define MEM_SDMODE2             0x0810
+#define MEM_SDADDR0             0x0820
+#define MEM_SDADDR1             0x0828
+#define MEM_SDADDR2             0x0830
+#define MEM_SDCONFIGA           0x0840
+#define MEM_SDCONFIGB           0x0848
+#define MEM_SDSTAT              0x0850
+#define MEM_SDERRADDR           0x0858
+#define MEM_SDSTRIDE0           0x0860
+#define MEM_SDSTRIDE1           0x0868
+#define MEM_SDSTRIDE2           0x0870
+#define MEM_SDWRMD0             0x0880
+#define MEM_SDWRMD1             0x0888
+#define MEM_SDWRMD2             0x0890
+#define MEM_SDPRECMD            0x08C0
+#define MEM_SDAUTOREF           0x08C8
+#define MEM_SDSREF              0x08D0
+#define MEM_SDSLEEP             MEM_SDSREF
+
+#endif
+
+/*
+ * Physical base addresses for integrated peripherals
+ * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
+ */
+
+#define AU1000_AC97_PHYS_ADDR           0x10000000 /* 012 */
+#define AU1000_USBD_PHYS_ADDR           0x10200000 /* 0123 */
+#define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
+#define AU1000_MAC0_PHYS_ADDR           0x10500000 /* 023 */
+#define AU1000_MAC1_PHYS_ADDR           0x10510000 /* 023 */
+#define AU1000_MACEN_PHYS_ADDR          0x10520000 /* 023 */
+#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 24 */
+#define AU1100_SD1_PHYS_ADDR            0x10680000 /* 24 */
+#define AU1000_I2S_PHYS_ADDR            0x11000000 /* 02 */
+#define AU1500_MAC0_PHYS_ADDR           0x11500000 /* 1 */
+#define AU1500_MAC1_PHYS_ADDR           0x11510000 /* 1 */
+#define AU1500_MACEN_PHYS_ADDR          0x11520000 /* 1 */
+#define AU1000_UART0_PHYS_ADDR          0x11100000 /* 01234 */
+#define AU1000_UART1_PHYS_ADDR          0x11200000 /* 0234 */
+#define AU1000_UART2_PHYS_ADDR          0x11300000 /* 0 */
+#define AU1000_UART3_PHYS_ADDR          0x11400000 /* 0123 */
+#define AU1500_GPIO2_PHYS_ADDR          0x11700000 /* 1234 */
+#define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
+#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 01234 */
+#define AU1000_DMA_PHYS_ADDR            0x14002000 /* 012 */
+#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 34 */
+#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 34 */
+#define AU1000_MACDMA0_PHYS_ADDR        0x14004000 /* 0123 */
+#define AU1000_MACDMA1_PHYS_ADDR        0x14004200 /* 0123 */
+
+
+#ifdef CONFIG_SOC_AU1000
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define USBH_PHYS_ADDR          0x10100000
+#define IRDA_PHYS_ADDR          0x10300000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
+
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1500
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define USBH_PHYS_ADDR          0x10100000
+#define PCI_PHYS_ADDR           0x14005000
+#define PCI_MEM_PHYS_ADDR       0x400000000ULL
+#define PCI_IO_PHYS_ADDR        0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR   0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
+
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1100
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define USBH_PHYS_ADDR          0x10100000
+#define IRDA_PHYS_ADDR          0x10300000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define LCD_PHYS_ADDR           0x15000000
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1550
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define USBH_PHYS_ADDR          0x14020000
+#define PCI_PHYS_ADDR           0x14005000
+#define PE_PHYS_ADDR            0x14008000
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define PSC2_PHYS_ADDR          0x10A00000
+#define PSC3_PHYS_ADDR          0x10B00000
+#define PCI_MEM_PHYS_ADDR       0x400000000ULL
+#define PCI_IO_PHYS_ADDR        0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR   0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
+
+/***********************************************************************/
 
-/* Au1550 SDRAM Register Offsets */
-#define AU1550_MEM_SDMODE0              0x0800
-#define AU1550_MEM_SDMODE1              0x0808
-#define AU1550_MEM_SDMODE2              0x0810
-#define AU1550_MEM_SDADDR0              0x0820
-#define AU1550_MEM_SDADDR1              0x0828
-#define AU1550_MEM_SDADDR2              0x0830
-#define AU1550_MEM_SDCONFIGA            0x0840
-#define AU1550_MEM_SDCONFIGB            0x0848
-#define AU1550_MEM_SDSTAT               0x0850
-#define AU1550_MEM_SDERRADDR            0x0858
-#define AU1550_MEM_SDSTRIDE0            0x0860
-#define AU1550_MEM_SDSTRIDE1            0x0868
-#define AU1550_MEM_SDSTRIDE2            0x0870
-#define AU1550_MEM_SDWRMD0              0x0880
-#define AU1550_MEM_SDWRMD1              0x0888
-#define AU1550_MEM_SDWRMD2              0x0890
-#define AU1550_MEM_SDPRECMD             0x08C0
-#define AU1550_MEM_SDAUTOREF            0x08C8
-#define AU1550_MEM_SDSREF               0x08D0
-#define AU1550_MEM_SDSLEEP              MEM_SDSREF
+#ifdef CONFIG_SOC_AU1200
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define AES_PHYS_ADDR           0x10300000
+#define CIM_PHYS_ADDR           0x14004000
+#define USBM_PHYS_ADDR          0x14020000
+#define USBH_PHYS_ADDR          0x14020100
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define LCD_PHYS_ADDR           0x15000000
+#define SWCNT_PHYS_ADDR         0x1110010C
+#define MAEFE_PHYS_ADDR         0x14012000
+#define MAEBE_PHYS_ADDR         0x14010000
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
 
 /* Static Bus Controller */
 #define MEM_STCFG0              0xB4001000
@@ -954,13 +813,80 @@ enum soc_au1200_ints {
 #define MEM_STTIME3             0xB4001034
 #define MEM_STADDR3             0xB4001038
 
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
 #define MEM_STNDCTL             0xB4001100
 #define MEM_STSTAT              0xB4001104
 
 #define MEM_STNAND_CMD          0x0
 #define MEM_STNAND_ADDR         0x4
 #define MEM_STNAND_DATA         0x20
+#endif
+
+
+
 
+/* Au1000 */
+#ifdef CONFIG_SOC_AU1000
+
+#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
+#define USB_HOST_CONFIG         0xB017FFFC
+#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
+#endif /* CONFIG_SOC_AU1000 */
+
+/* Au1500 */
+#ifdef CONFIG_SOC_AU1500
+
+#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
+#define USB_HOST_CONFIG         0xB017fffc
+#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
+#endif /* CONFIG_SOC_AU1500 */
+
+/* Au1100 */
+#ifdef CONFIG_SOC_AU1100
+
+#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
+#define USB_HOST_CONFIG         0xB017FFFC
+#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
+#endif /* CONFIG_SOC_AU1100 */
+
+#ifdef CONFIG_SOC_AU1550
+
+#define USB_OHCI_BASE           0x14020000      /* phys addr for ioremap */
+#define USB_OHCI_LEN            0x00060000
+#define USB_HOST_CONFIG         0xB4027ffc
+#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
+#endif /* CONFIG_SOC_AU1550 */
+
+
+#ifdef CONFIG_SOC_AU1200
+
+#define USB_UOC_BASE            0x14020020
+#define USB_UOC_LEN             0x20
+#define USB_OHCI_BASE           0x14020100
+#define USB_OHCI_LEN            0x100
+#define USB_EHCI_BASE           0x14020200
+#define USB_EHCI_LEN            0x100
+#define USB_UDC_BASE            0x14022000
+#define USB_UDC_LEN             0x2000
+#define USB_MSR_BASE            0xB4020000
+#define USB_MSR_MCFG            4
+#define USBMSRMCFG_OMEMEN       0
+#define USBMSRMCFG_OBMEN        1
+#define USBMSRMCFG_EMEMEN       2
+#define USBMSRMCFG_EBMEN        3
+#define USBMSRMCFG_DMEMEN       4
+#define USBMSRMCFG_DBMEN        5
+#define USBMSRMCFG_GMEMEN       6
+#define USBMSRMCFG_OHCCLKEN     16
+#define USBMSRMCFG_EHCCLKEN     17
+#define USBMSRMCFG_UDCCLKEN     18
+#define USBMSRMCFG_PHYPLLEN     19
+#define USBMSRMCFG_RDCOMB       30
+#define USBMSRMCFG_PFEN         31
+
+#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
+
+#endif /* CONFIG_SOC_AU1200 */
 
 /* Programmable Counters 0 and 1 */
 #define SYS_BASE                0xB1900000
@@ -1032,6 +958,56 @@ enum soc_au1200_ints {
 #  define I2S_CONTROL_D         (1 << 1)
 #  define I2S_CONTROL_CE        (1 << 0)
 
+/* USB Host Controller */
+#ifndef USB_OHCI_LEN
+#define USB_OHCI_LEN            0x00100000
+#endif
+
+#ifndef CONFIG_SOC_AU1200
+
+/* USB Device Controller */
+#define USBD_EP0RD              0xB0200000
+#define USBD_EP0WR              0xB0200004
+#define USBD_EP2WR              0xB0200008
+#define USBD_EP3WR              0xB020000C
+#define USBD_EP4RD              0xB0200010
+#define USBD_EP5RD              0xB0200014
+#define USBD_INTEN              0xB0200018
+#define USBD_INTSTAT            0xB020001C
+#  define USBDEV_INT_SOF        (1 << 12)
+#  define USBDEV_INT_HF_BIT     6
+#  define USBDEV_INT_HF_MASK    (0x3f << USBDEV_INT_HF_BIT)
+#  define USBDEV_INT_CMPLT_BIT  0
+#  define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
+#define USBD_CONFIG             0xB0200020
+#define USBD_EP0CS              0xB0200024
+#define USBD_EP2CS              0xB0200028
+#define USBD_EP3CS              0xB020002C
+#define USBD_EP4CS              0xB0200030
+#define USBD_EP5CS              0xB0200034
+#  define USBDEV_CS_SU          (1 << 14)
+#  define USBDEV_CS_NAK         (1 << 13)
+#  define USBDEV_CS_ACK         (1 << 12)
+#  define USBDEV_CS_BUSY        (1 << 11)
+#  define USBDEV_CS_TSIZE_BIT   1
+#  define USBDEV_CS_TSIZE_MASK  (0x3ff << USBDEV_CS_TSIZE_BIT)
+#  define USBDEV_CS_STALL       (1 << 0)
+#define USBD_EP0RDSTAT          0xB0200040
+#define USBD_EP0WRSTAT          0xB0200044
+#define USBD_EP2WRSTAT          0xB0200048
+#define USBD_EP3WRSTAT          0xB020004C
+#define USBD_EP4RDSTAT          0xB0200050
+#define USBD_EP5RDSTAT          0xB0200054
+#  define USBDEV_FSTAT_FLUSH    (1 << 6)
+#  define USBDEV_FSTAT_UF       (1 << 5)
+#  define USBDEV_FSTAT_OF       (1 << 4)
+#  define USBDEV_FSTAT_FCNT_BIT 0
+#  define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
+#define USBD_ENABLE             0xB0200058
+#  define USBDEV_ENABLE         (1 << 1)
+#  define USBDEV_CE             (1 << 0)
+
+#endif /* !CONFIG_SOC_AU1200 */
 
 /* Ethernet Controllers  */
 
@@ -1265,20 +1241,44 @@ enum soc_au1200_ints {
 #define SSI_ENABLE_CD           (1 << 1)
 #define SSI_ENABLE_E            (1 << 0)
 
-
-/*
- * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
- * used to select FIR/SIR mode on the transceiver but as a GPIO.  Instead a
- * CPLD has to be told about the mode.
- */
-#define AU1000_IRDA_PHY_MODE_OFF        0
-#define AU1000_IRDA_PHY_MODE_SIR        1
-#define AU1000_IRDA_PHY_MODE_FIR        2
-
-struct au1k_irda_platform_data {
-        void(*set_phy_mode)(int mode);
-};
-
+/* IrDA Controller */
+#define IRDA_BASE               0xB0300000
+#define IR_RING_PTR_STATUS      (IRDA_BASE + 0x00)
+#define IR_RING_BASE_ADDR_H     (IRDA_BASE + 0x04)
+#define IR_RING_BASE_ADDR_L     (IRDA_BASE + 0x08)
+#define IR_RING_SIZE            (IRDA_BASE + 0x0C)
+#define IR_RING_PROMPT          (IRDA_BASE + 0x10)
+#define IR_RING_ADDR_CMPR       (IRDA_BASE + 0x14)
+#define IR_INT_CLEAR            (IRDA_BASE + 0x18)
+#define IR_CONFIG_1             (IRDA_BASE + 0x20)
+#  define IR_RX_INVERT_LED      (1 << 0)
+#  define IR_TX_INVERT_LED      (1 << 1)
+#  define IR_ST                 (1 << 2)
+#  define IR_SF                 (1 << 3)
+#  define IR_SIR                (1 << 4)
+#  define IR_MIR                (1 << 5)
+#  define IR_FIR                (1 << 6)
+#  define IR_16CRC              (1 << 7)
+#  define IR_TD                 (1 << 8)
+#  define IR_RX_ALL             (1 << 9)
+#  define IR_DMA_ENABLE         (1 << 10)
+#  define IR_RX_ENABLE          (1 << 11)
+#  define IR_TX_ENABLE          (1 << 12)
+#  define IR_LOOPBACK           (1 << 14)
+#  define IR_SIR_MODE           (IR_SIR | IR_DMA_ENABLE | \
+                                 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+#define IR_SIR_FLAGS            (IRDA_BASE + 0x24)
+#define IR_ENABLE               (IRDA_BASE + 0x28)
+#  define IR_RX_STATUS          (1 << 9)
+#  define IR_TX_STATUS          (1 << 10)
+#define IR_READ_PHY_CONFIG      (IRDA_BASE + 0x2C)
+#define IR_WRITE_PHY_CONFIG     (IRDA_BASE + 0x30)
+#define IR_MAX_PKT_LEN          (IRDA_BASE + 0x34)
+#define IR_RX_BYTE_CNT          (IRDA_BASE + 0x38)
+#define IR_CONFIG_2             (IRDA_BASE + 0x3C)
+#  define IR_MODE_INV           (1 << 0)
+#  define IR_ONE_PIN            (1 << 1)
+#define IR_INTERFACE_CONFIG     (IRDA_BASE + 0x40)
 
 /* GPIO */
 #define SYS_PINFUNC             0xB190002C
@@ -1322,6 +1322,7 @@ struct au1k_irda_platform_data {
 #  define SYS_PF_MUST_BE_SET    ((1 << 5) | (1 << 2))
 
 /* Au1200 only */
+#ifdef CONFIG_SOC_AU1200
 #define SYS_PINFUNC_DMA         (1 << 31)
 #define SYS_PINFUNC_S0A         (1 << 30)
 #define SYS_PINFUNC_S1A         (1 << 29)
@@ -1349,6 +1350,7 @@ struct au1k_irda_platform_data {
 #define SYS_PINFUNC_P0B         (1 << 4)
 #define SYS_PINFUNC_U0T         (1 << 3)
 #define SYS_PINFUNC_S1B         (1 << 2)
+#endif
 
 /* Power Management */
 #define SYS_SCRATCH0            0xB1900018
@@ -1404,12 +1406,12 @@ struct au1k_irda_platform_data {
 #  define SYS_CS_MI2_MASK       (0x7 << SYS_CS_MI2_BIT)
 #  define SYS_CS_DI2            (1 << 16)
 #  define SYS_CS_CI2            (1 << 15)
-
+#ifdef CONFIG_SOC_AU1100
 #  define SYS_CS_ML_BIT         7
 #  define SYS_CS_ML_MASK        (0x7 << SYS_CS_ML_BIT)
 #  define SYS_CS_DL             (1 << 6)
 #  define SYS_CS_CL             (1 << 5)
-
+#else
 #  define SYS_CS_MUH_BIT        12
 #  define SYS_CS_MUH_MASK       (0x7 << SYS_CS_MUH_BIT)
 #  define SYS_CS_DUH            (1 << 11)
@@ -1418,7 +1420,7 @@ struct au1k_irda_platform_data {
 #  define SYS_CS_MUD_MASK       (0x7 << SYS_CS_MUD_BIT)
 #  define SYS_CS_DUD            (1 << 6)
 #  define SYS_CS_CUD            (1 << 5)
-
+#endif
 #  define SYS_CS_MIR_BIT        2
 #  define SYS_CS_MIR_MASK       (0x7 << SYS_CS_MIR_BIT)
 #  define SYS_CS_DIR            (1 << 1)
@@ -1465,30 +1467,58 @@ struct au1k_irda_platform_data {
 #  define AC97C_RS              (1 << 1)
 #  define AC97C_CE              (1 << 0)
 
+#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
+/* Au1500 PCI Controller */
+#define Au1500_CFG_BASE         0xB4005000      /* virtual, KSEG1 addr */
+#define Au1500_PCI_CMEM         (Au1500_CFG_BASE + 0)
+#define Au1500_PCI_CFG          (Au1500_CFG_BASE + 4)
+#  define PCI_ERROR             ((1 << 22) | (1 << 23) | (1 << 24) | \
+                                 (1 << 25) | (1 << 26) | (1 << 27))
+#define Au1500_PCI_B2BMASK_CCH  (Au1500_CFG_BASE + 8)
+#define Au1500_PCI_B2B0_VID     (Au1500_CFG_BASE + 0xC)
+#define Au1500_PCI_B2B1_ID      (Au1500_CFG_BASE + 0x10)
+#define Au1500_PCI_MWMASK_DEV   (Au1500_CFG_BASE + 0x14)
+#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
+#define Au1500_PCI_ERR_ADDR     (Au1500_CFG_BASE + 0x1C)
+#define Au1500_PCI_SPEC_INTACK  (Au1500_CFG_BASE + 0x20)
+#define Au1500_PCI_ID           (Au1500_CFG_BASE + 0x100)
+#define Au1500_PCI_STATCMD      (Au1500_CFG_BASE + 0x104)
+#define Au1500_PCI_CLASSREV     (Au1500_CFG_BASE + 0x108)
+#define Au1500_PCI_HDRTYPE      (Au1500_CFG_BASE + 0x10C)
+#define Au1500_PCI_MBAR         (Au1500_CFG_BASE + 0x110)
+
+#define Au1500_PCI_HDR          0xB4005100      /* virtual, KSEG1 addr */
 
-/* The PCI chip selects are outside the 32bit space, and since we can't
- * just program the 36bit addresses into BARs, we have to take a chunk
- * out of the 32bit space and reserve it for PCI.  When these addresses
- * are ioremap()ed, they'll be fixed up to the real 36bit address before
- * being passed to the real ioremap function.
+/*
+ * All of our structures, like PCI resource, have 32-bit members.
+ * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
+ * hard to store 0x4 0000 0000 in a 32-bit type.  We require a small patch
+ * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
+ * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
+ * addresses.  For PCI I/O, it's simpler because we get to do the ioremap
+ * ourselves and then adjust the device's resources.
  */
-#define ALCHEMY_PCI_MEMWIN_START        (AU1500_PCI_MEM_PHYS_ADDR >> 4)
-#define ALCHEMY_PCI_MEMWIN_END          (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
+#define Au1500_EXT_CFG          0x600000000ULL
+#define Au1500_EXT_CFG_TYPE1    0x680000000ULL
+#define Au1500_PCI_IO_START     0x500000000ULL
+#define Au1500_PCI_IO_END       0x5000FFFFFULL
+#define Au1500_PCI_MEM_START    0x440000000ULL
+#define Au1500_PCI_MEM_END      0x44FFFFFFFULL
 
-/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
- * adjust the device's resources.
- */
-#define ALCHEMY_PCI_IOWIN_START         0x00001000
-#define ALCHEMY_PCI_IOWIN_END           0x0000FFFF
+#define PCI_IO_START    0x00001000
+#define PCI_IO_END      0x000FFFFF
+#define PCI_MEM_START   0x40000000
+#define PCI_MEM_END     0x4FFFFFFF
 
-#ifdef CONFIG_PCI
+#define PCI_FIRST_DEVFN (0 << 3)
+#define PCI_LAST_DEVFN  (19 << 3)
 
 #define IOPORT_RESOURCE_START   0x00001000      /* skip legacy probing */
 #define IOPORT_RESOURCE_END     0xffffffff
 #define IOMEM_RESOURCE_START    0x10000000
 #define IOMEM_RESOURCE_END      0xfffffffffULL
 
-#else
+#else /* Au1000 and Au1100 and Au1200 */
 
 /* Don't allow any legacy ports probing */
 #define IOPORT_RESOURCE_START   0x10000000
@@ -1496,77 +1526,13 @@ struct au1k_irda_platform_data {
 #define IOMEM_RESOURCE_START    0x10000000
 #define IOMEM_RESOURCE_END      0xfffffffffULL
 
-#endif
+#define PCI_IO_START    0
+#define PCI_IO_END      0
+#define PCI_MEM_START   0
+#define PCI_MEM_END     0
+#define PCI_FIRST_DEVFN 0
+#define PCI_LAST_DEVFN  0
 
-/* PCI controller block register offsets */
-#define PCI_REG_CMEM            0x0000
-#define PCI_REG_CONFIG          0x0004
-#define PCI_REG_B2BMASK_CCH     0x0008
-#define PCI_REG_B2BBASE0_VID    0x000C
-#define PCI_REG_B2BBASE1_SID    0x0010
-#define PCI_REG_MWMASK_DEV      0x0014
-#define PCI_REG_MWBASE_REV_CCL  0x0018
-#define PCI_REG_ERR_ADDR        0x001C
-#define PCI_REG_SPEC_INTACK     0x0020
-#define PCI_REG_ID              0x0100
-#define PCI_REG_STATCMD         0x0104
-#define PCI_REG_CLASSREV        0x0108
-#define PCI_REG_PARAM           0x010C
-#define PCI_REG_MBAR            0x0110
-#define PCI_REG_TIMEOUT         0x0140
-
-/* PCI controller block register bits */
-#define PCI_CMEM_E              (1 << 28)       /* enable cacheable memory */
-#define PCI_CMEM_CMBASE(x)      (((x) & 0x3fff) << 14)
-#define PCI_CMEM_CMMASK(x)      ((x) & 0x3fff)
-#define PCI_CONFIG_ERD          (1 << 27) /* pci error during R/W */
-#define PCI_CONFIG_ET           (1 << 26) /* error in target mode */
-#define PCI_CONFIG_EF           (1 << 25) /* fatal error */
-#define PCI_CONFIG_EP           (1 << 24) /* parity error */
-#define PCI_CONFIG_EM           (1 << 23) /* multiple errors */
-#define PCI_CONFIG_BM           (1 << 22) /* bad master error */
-#define PCI_CONFIG_PD           (1 << 20) /* PCI Disable */
-#define PCI_CONFIG_BME          (1 << 19) /* Byte Mask Enable for reads */
-#define PCI_CONFIG_NC           (1 << 16) /* mark mem access non-coherent */
-#define PCI_CONFIG_IA           (1 << 15) /* INTA# enabled (target mode) */
-#define PCI_CONFIG_IP           (1 << 13) /* int on PCI_PERR# */
-#define PCI_CONFIG_IS           (1 << 12) /* int on PCI_SERR# */
-#define PCI_CONFIG_IMM          (1 << 11) /* int on master abort */
-#define PCI_CONFIG_ITM          (1 << 10) /* int on target abort (as master) */
-#define PCI_CONFIG_ITT          (1 << 9)  /* int on target abort (as target) */
-#define PCI_CONFIG_IPB          (1 << 8)  /* int on PERR# in bus master acc */
-#define PCI_CONFIG_SIC_NO       (0 << 6)  /* no byte mask changes */
-#define PCI_CONFIG_SIC_BA_ADR   (1 << 6)  /* on byte/hw acc, invert adr bits */
-#define PCI_CONFIG_SIC_HWA_DAT  (2 << 6)  /* on halfword acc, swap data */
-#define PCI_CONFIG_SIC_ALL      (3 << 6)  /* swap data bytes on all accesses */
-#define PCI_CONFIG_ST           (1 << 5)  /* swap data by target transactions */
-#define PCI_CONFIG_SM           (1 << 4)  /* swap data from PCI ctl */
-#define PCI_CONFIG_AEN          (1 << 3)  /* enable internal arbiter */
-#define PCI_CONFIG_R2H          (1 << 2)  /* REQ2# to hi-prio arbiter */
-#define PCI_CONFIG_R1H          (1 << 1)  /* REQ1# to hi-prio arbiter */
-#define PCI_CONFIG_CH           (1 << 0)  /* PCI ctl to hi-prio arbiter */
-#define PCI_B2BMASK_B2BMASK(x)  (((x) & 0xffff) << 16)
-#define PCI_B2BMASK_CCH(x)      ((x) & 0xffff) /* 16 upper bits of class code */
-#define PCI_B2BBASE0_VID_B0(x)  (((x) & 0xffff) << 16)
-#define PCI_B2BBASE0_VID_SV(x)  ((x) & 0xffff)
-#define PCI_B2BBASE1_SID_B1(x)  (((x) & 0xffff) << 16)
-#define PCI_B2BBASE1_SID_SI(x)  ((x) & 0xffff)
-#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
-#define PCI_MWMASKDEV_DEVID(x)  ((x) & 0xffff)
-#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
-#define PCI_MWBASEREVCCL_REV(x)  (((x) & 0xff) << 8)
-#define PCI_MWBASEREVCCL_CCL(x)  ((x) & 0xff)
-#define PCI_ID_DID(x)           (((x) & 0xffff) << 16)
-#define PCI_ID_VID(x)           ((x) & 0xffff)
-#define PCI_STATCMD_STATUS(x)   (((x) & 0xffff) << 16)
-#define PCI_STATCMD_CMD(x)      ((x) & 0xffff)
-#define PCI_CLASSREV_CLASS(x)   (((x) & 0x00ffffff) << 8)
-#define PCI_CLASSREV_REV(x)     ((x) & 0xff)
-#define PCI_PARAM_BIST(x)       (((x) & 0xff) << 24)
-#define PCI_PARAM_HT(x)         (((x) & 0xff) << 16)
-#define PCI_PARAM_LT(x)         (((x) & 0xff) << 8)
-#define PCI_PARAM_CLS(x)        ((x) & 0xff)
-#define PCI_TIMEOUT_RETRIES(x)  (((x) & 0xff) << 8)     /* max retries */
-#define PCI_TIMEOUT_TO(x)       ((x) & 0xff)    /* target ready timeout */
+#endif
 
 #endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
index ba4cf0e91c8..59f5b55b220 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -33,6 +33,7 @@
 #include <linux/io.h>           /* need byte IO */
 #include <linux/spinlock.h>     /* And spinlocks */
 #include <linux/delay.h>
+#include <asm/system.h>
 
 #define NUM_AU1000_DMA_CHANNELS 8
 
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index e221659f1bc..94000a3b6f0 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -130,10 +130,8 @@ struct au1xmmc_platform_data {
 #define SD_CONFIG2_DF   (0x00000008)
 #define SD_CONFIG2_DC   (0x00000010)
 #define SD_CONFIG2_xx2  (0x000000e0)
-#define SD_CONFIG2_BB   (0x00000080)
 #define SD_CONFIG2_WB   (0x00000100)
 #define SD_CONFIG2_RW   (0x00000200)
-#define SD_CONFIG2_DP   (0x00000400)
 
 
 /*
diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h
deleted file mode 100644
index b3c87cc64bb..00000000000
--- a/arch/mips/include/asm/mach-au1x00/au1200fb.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * platform data for au1200fb driver.
- */
-
-#ifndef _AU1200FB_PLAT_H_
-#define _AU1200FB_PLAT_H_
-
-struct au1200fb_platdata {
-        int (*panel_index)(void);
-        int (*panel_init)(void);
-        int (*panel_shutdown)(void);
-};
-
-#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h
deleted file mode 100644
index ad4c0a03afe..00000000000
--- a/arch/mips/include/asm/mach-au1x00/au1550nd.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * platform data for the Au1550 NAND driver
- */
-
-#ifndef _AU1550ND_H_
-#define _AU1550ND_H_
-
-#include <linux/mtd/partitions.h>
-
-struct au1550nd_platdata {
-        struct mtd_partition *parts;
-        int num_parts;
-        int devwidth;   /* 0 = 8bit device, 1 = 16bit device */
-};
-
-#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 217810e1836..2fdacfe85e2 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -126,93 +126,66 @@ typedef volatile struct au1xxx_ddma_desc {
 #define SW_STATUS_INUSE         (1 << 0)
 
 /* Command 0 device IDs. */
-#define AU1550_DSCR_CMD0_UART0_TX       0
-#define AU1550_DSCR_CMD0_UART0_RX       1
-#define AU1550_DSCR_CMD0_UART3_TX       2
-#define AU1550_DSCR_CMD0_UART3_RX       3
-#define AU1550_DSCR_CMD0_DMA_REQ0       4
-#define AU1550_DSCR_CMD0_DMA_REQ1       5
-#define AU1550_DSCR_CMD0_DMA_REQ2       6
-#define AU1550_DSCR_CMD0_DMA_REQ3       7
-#define AU1550_DSCR_CMD0_USBDEV_RX0     8
-#define AU1550_DSCR_CMD0_USBDEV_TX0     9
-#define AU1550_DSCR_CMD0_USBDEV_TX1     10
-#define AU1550_DSCR_CMD0_USBDEV_TX2     11
-#define AU1550_DSCR_CMD0_USBDEV_RX3     12
-#define AU1550_DSCR_CMD0_USBDEV_RX4     13
-#define AU1550_DSCR_CMD0_PSC0_TX        14
-#define AU1550_DSCR_CMD0_PSC0_RX        15
-#define AU1550_DSCR_CMD0_PSC1_TX        16
-#define AU1550_DSCR_CMD0_PSC1_RX        17
-#define AU1550_DSCR_CMD0_PSC2_TX        18
-#define AU1550_DSCR_CMD0_PSC2_RX        19
-#define AU1550_DSCR_CMD0_PSC3_TX        20
-#define AU1550_DSCR_CMD0_PSC3_RX        21
-#define AU1550_DSCR_CMD0_PCI_WRITE      22
-#define AU1550_DSCR_CMD0_NAND_FLASH     23
-#define AU1550_DSCR_CMD0_MAC0_RX        24
-#define AU1550_DSCR_CMD0_MAC0_TX        25
-#define AU1550_DSCR_CMD0_MAC1_RX        26
-#define AU1550_DSCR_CMD0_MAC1_TX        27
-
-#define AU1200_DSCR_CMD0_UART0_TX       0
-#define AU1200_DSCR_CMD0_UART0_RX       1
-#define AU1200_DSCR_CMD0_UART1_TX       2
-#define AU1200_DSCR_CMD0_UART1_RX       3
-#define AU1200_DSCR_CMD0_DMA_REQ0       4
-#define AU1200_DSCR_CMD0_DMA_REQ1       5
-#define AU1200_DSCR_CMD0_MAE_BE         6
-#define AU1200_DSCR_CMD0_MAE_FE         7
-#define AU1200_DSCR_CMD0_SDMS_TX0       8
-#define AU1200_DSCR_CMD0_SDMS_RX0       9
-#define AU1200_DSCR_CMD0_SDMS_TX1       10
-#define AU1200_DSCR_CMD0_SDMS_RX1       11
-#define AU1200_DSCR_CMD0_AES_TX         13
-#define AU1200_DSCR_CMD0_AES_RX         12
-#define AU1200_DSCR_CMD0_PSC0_TX        14
-#define AU1200_DSCR_CMD0_PSC0_RX        15
-#define AU1200_DSCR_CMD0_PSC1_TX        16
-#define AU1200_DSCR_CMD0_PSC1_RX        17
-#define AU1200_DSCR_CMD0_CIM_RXA        18
-#define AU1200_DSCR_CMD0_CIM_RXB        19
-#define AU1200_DSCR_CMD0_CIM_RXC        20
-#define AU1200_DSCR_CMD0_MAE_BOTH       21
-#define AU1200_DSCR_CMD0_LCD            22
-#define AU1200_DSCR_CMD0_NAND_FLASH     23
-#define AU1200_DSCR_CMD0_PSC0_SYNC      24
-#define AU1200_DSCR_CMD0_PSC1_SYNC      25
-#define AU1200_DSCR_CMD0_CIM_SYNC       26
-
-#define AU1300_DSCR_CMD0_UART0_TX      0
-#define AU1300_DSCR_CMD0_UART0_RX      1
-#define AU1300_DSCR_CMD0_UART1_TX      2
-#define AU1300_DSCR_CMD0_UART1_RX      3
-#define AU1300_DSCR_CMD0_UART2_TX      4
-#define AU1300_DSCR_CMD0_UART2_RX      5
-#define AU1300_DSCR_CMD0_UART3_TX      6
-#define AU1300_DSCR_CMD0_UART3_RX      7
-#define AU1300_DSCR_CMD0_SDMS_TX0      8
-#define AU1300_DSCR_CMD0_SDMS_RX0      9
-#define AU1300_DSCR_CMD0_SDMS_TX1      10
-#define AU1300_DSCR_CMD0_SDMS_RX1      11
-#define AU1300_DSCR_CMD0_AES_TX        12
-#define AU1300_DSCR_CMD0_AES_RX        13
-#define AU1300_DSCR_CMD0_PSC0_TX       14
-#define AU1300_DSCR_CMD0_PSC0_RX       15
-#define AU1300_DSCR_CMD0_PSC1_TX       16
-#define AU1300_DSCR_CMD0_PSC1_RX       17
-#define AU1300_DSCR_CMD0_PSC2_TX       18
-#define AU1300_DSCR_CMD0_PSC2_RX       19
-#define AU1300_DSCR_CMD0_PSC3_TX       20
-#define AU1300_DSCR_CMD0_PSC3_RX       21
-#define AU1300_DSCR_CMD0_LCD           22
-#define AU1300_DSCR_CMD0_NAND_FLASH    23
-#define AU1300_DSCR_CMD0_SDMS_TX2      24
-#define AU1300_DSCR_CMD0_SDMS_RX2      25
-#define AU1300_DSCR_CMD0_CIM_SYNC      26
-#define AU1300_DSCR_CMD0_UDMA          27
-#define AU1300_DSCR_CMD0_DMA_REQ0      28
-#define AU1300_DSCR_CMD0_DMA_REQ1      29
+#ifdef CONFIG_SOC_AU1550
+#define DSCR_CMD0_UART0_TX      0
+#define DSCR_CMD0_UART0_RX      1
+#define DSCR_CMD0_UART3_TX      2
+#define DSCR_CMD0_UART3_RX      3
+#define DSCR_CMD0_DMA_REQ0      4
+#define DSCR_CMD0_DMA_REQ1      5
+#define DSCR_CMD0_DMA_REQ2      6
+#define DSCR_CMD0_DMA_REQ3      7
+#define DSCR_CMD0_USBDEV_RX0    8
+#define DSCR_CMD0_USBDEV_TX0    9
+#define DSCR_CMD0_USBDEV_TX1    10
+#define DSCR_CMD0_USBDEV_TX2    11
+#define DSCR_CMD0_USBDEV_RX3    12
+#define DSCR_CMD0_USBDEV_RX4    13
+#define DSCR_CMD0_PSC0_TX       14
+#define DSCR_CMD0_PSC0_RX       15
+#define DSCR_CMD0_PSC1_TX       16
+#define DSCR_CMD0_PSC1_RX       17
+#define DSCR_CMD0_PSC2_TX       18
+#define DSCR_CMD0_PSC2_RX       19
+#define DSCR_CMD0_PSC3_TX       20
+#define DSCR_CMD0_PSC3_RX       21
+#define DSCR_CMD0_PCI_WRITE     22
+#define DSCR_CMD0_NAND_FLASH    23
+#define DSCR_CMD0_MAC0_RX       24
+#define DSCR_CMD0_MAC0_TX       25
+#define DSCR_CMD0_MAC1_RX       26
+#define DSCR_CMD0_MAC1_TX       27
+#endif /* CONFIG_SOC_AU1550 */
+
+#ifdef CONFIG_SOC_AU1200
+#define DSCR_CMD0_UART0_TX      0
+#define DSCR_CMD0_UART0_RX      1
+#define DSCR_CMD0_UART1_TX      2
+#define DSCR_CMD0_UART1_RX      3
+#define DSCR_CMD0_DMA_REQ0      4
+#define DSCR_CMD0_DMA_REQ1      5
+#define DSCR_CMD0_MAE_BE        6
+#define DSCR_CMD0_MAE_FE        7
+#define DSCR_CMD0_SDMS_TX0      8
+#define DSCR_CMD0_SDMS_RX0      9
+#define DSCR_CMD0_SDMS_TX1      10
+#define DSCR_CMD0_SDMS_RX1      11
+#define DSCR_CMD0_AES_TX        13
+#define DSCR_CMD0_AES_RX        12
+#define DSCR_CMD0_PSC0_TX       14
+#define DSCR_CMD0_PSC0_RX       15
+#define DSCR_CMD0_PSC1_TX       16
+#define DSCR_CMD0_PSC1_RX       17
+#define DSCR_CMD0_CIM_RXA       18
+#define DSCR_CMD0_CIM_RXB       19
+#define DSCR_CMD0_CIM_RXC       20
+#define DSCR_CMD0_MAE_BOTH      21
+#define DSCR_CMD0_LCD           22
+#define DSCR_CMD0_NAND_FLASH    23
+#define DSCR_CMD0_PSC0_SYNC     24
+#define DSCR_CMD0_PSC1_SYNC     25
+#define DSCR_CMD0_CIM_SYNC      26
+#endif /* CONFIG_SOC_AU1200 */
 
 #define DSCR_CMD0_THROTTLE      30
 #define DSCR_CMD0_ALWAYS        31
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
index e306384b141..5656c72de6d 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
@@ -58,7 +58,6 @@ typedef struct {
 #endif
         int                     irq;
         u32                     regbase;
-        int                     ddma_id;
 } _auide_hwif;
 
 /******************************************************************************/
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
index 4e3f3bc26c6..892b7f168eb 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -33,6 +33,19 @@
 #ifndef _AU1000_PSC_H_
 #define _AU1000_PSC_H_
 
+/* The PSC base addresses.  */
+#ifdef CONFIG_SOC_AU1550
+#define PSC0_BASE_ADDR          0xb1a00000
+#define PSC1_BASE_ADDR          0xb1b00000
+#define PSC2_BASE_ADDR          0xb0a00000
+#define PSC3_BASE_ADDR          0xb0b00000
+#endif
+
+#ifdef CONFIG_SOC_AU1200
+#define PSC0_BASE_ADDR          0xb1a00000
+#define PSC1_BASE_ADDR          0xb1b00000
+#endif
+
 /*
  * The PSC select and control registers are common to all protocols.
  */
@@ -67,6 +80,19 @@
 #define PSC_AC97GPO_OFFSET      0x00000028
 #define PSC_AC97GPI_OFFSET      0x0000002c
 
+#define AC97_PSC_SEL            (AC97_PSC_BASE + PSC_SEL_OFFSET)
+#define AC97_PSC_CTRL           (AC97_PSC_BASE + PSC_CTRL_OFFSET)
+#define PSC_AC97CFG             (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
+#define PSC_AC97MSK             (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
+#define PSC_AC97PCR             (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
+#define PSC_AC97STAT            (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
+#define PSC_AC97EVNT            (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
+#define PSC_AC97TXRX            (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
+#define PSC_AC97CDC             (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
+#define PSC_AC97RST             (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
+#define PSC_AC97GPO             (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
+#define PSC_AC97GPI             (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
+
 /* AC97 Config Register. */
 #define PSC_AC97CFG_RT_MASK     (3 << 30)
 #define PSC_AC97CFG_RT_FIFO1    (0 << 30)
@@ -368,6 +394,19 @@ typedef struct	psc_spi {
 #define PSC_SPITXRX_LC          (1 << 29)
 #define PSC_SPITXRX_SR          (1 << 28)
 
+/* PSC in SMBus (I2C) Mode. */
+typedef struct  psc_smb {
+        u32     psc_sel;
+        u32     psc_ctrl;
+        u32     psc_smbcfg;
+        u32     psc_smbmsk;
+        u32     psc_smbpcr;
+        u32     psc_smbstat;
+        u32     psc_smbevnt;
+        u32     psc_smbtxrx;
+        u32     psc_smbtmr;
+} psc_smb_t;
+
 /* SMBus Config Register. */
 #define PSC_SMBCFG_RT_MASK      (3 << 30)
 #define PSC_SMBCFG_RT_FIFO1     (0 << 30)
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index 09f45e6afad..d5df0cab9b8 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -13,14 +13,12 @@
 #define cpu_has_4k_cache                1
 #define cpu_has_tx39_cache              0
 #define cpu_has_fpu                     0
-#define cpu_has_32fpr                   0
 #define cpu_has_counter                 1
 #define cpu_has_watch                   1
 #define cpu_has_divec                   1
 #define cpu_has_vce                     0
 #define cpu_has_cache_cdex_p            0
 #define cpu_has_cache_cdex_s            0
-#define cpu_has_prefetch                1
 #define cpu_has_mcheck                  1
 #define cpu_has_ejtag                   1
 #define cpu_has_llsc                    1
@@ -31,13 +29,11 @@
 #define cpu_has_vtag_icache             0
 #define cpu_has_dc_aliases              0
 #define cpu_has_ic_fills_f_dc           1
-#define cpu_has_pindexed_dcache         0
 #define cpu_has_mips32r1                1
 #define cpu_has_mips32r2                0
 #define cpu_has_mips64r1                0
 #define cpu_has_mips64r2                0
 #define cpu_has_dsp                     0
-#define cpu_has_dsp2                    0
 #define cpu_has_mipsmt                  0
 #define cpu_has_userlocal               0
 #define cpu_has_nofpuex                 0
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 73853b5a2a3..1f41a522906 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -347,6 +347,17 @@ static inline int alchemy_gpio2_to_irq(int gpio)
 
 /**********************************************************************/
 
+/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
+ * SYS_PININPUTEN is written to at least once.  On Au1550/Au1200 this
+ * register enables use of GPIOs as wake source.
+ */
+static inline void alchemy_gpio1_input_enable(void)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
+        __raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */
+        wmb();
+}
+
 /* GPIO2 shared interrupts and control */
 
 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
@@ -550,7 +561,6 @@ static inline int alchemy_irq_to_gpio(int irq)
 
 #ifndef CONFIG_GPIOLIB
 
-#ifdef CONFIG_ALCHEMY_GPIOINT_AU1000
 
 #ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (4) */
 
@@ -655,7 +665,24 @@ static inline void gpio_unexport(unsigned gpio)
 
 #endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
 
-#endif  /* CONFIG_ALCHEMY_GPIOINT_AU1000 */
+
+#else   /* CONFIG GPIOLIB */
+
+
+ /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
+#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (2) */
+
+/* get everything through gpiolib */
+#define gpio_to_irq     __gpio_to_irq
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define irq_to_gpio     alchemy_irq_to_gpio
+
+#include <asm-generic/gpio.h>
+
+#endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
+
 
 #endif  /* !CONFIG_GPIOLIB */
 
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
deleted file mode 100644
index fb9975c74c5..00000000000
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
- *
- * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
- */
-
-#ifndef _GPIO_AU1300_H_
-#define _GPIO_AU1300_H_
-
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/mach-au1x00/au1000.h>
-
-struct gpio;
-struct gpio_chip;
-
-/* with the current GPIC design, up to 128 GPIOs are possible.
- * The only implementation so far is in the Au1300, which has 75 externally
- * available GPIOs.
- */
-#define AU1300_GPIO_BASE        0
-#define AU1300_GPIO_NUM         75
-#define AU1300_GPIO_MAX         (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
-
-#define AU1300_GPIC_ADDR        \
-        (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
-
-static inline int au1300_gpio_get_value(unsigned int gpio)
-{
-        void __iomem *roff = AU1300_GPIC_ADDR;
-        int bit;
-
-        gpio -= AU1300_GPIO_BASE;
-        roff += GPIC_GPIO_BANKOFF(gpio);
-        bit = GPIC_GPIO_TO_BIT(gpio);
-        return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
-}
-
-static inline int au1300_gpio_direction_input(unsigned int gpio)
-{
-        void __iomem *roff = AU1300_GPIC_ADDR;
-        unsigned long bit;
-
-        gpio -= AU1300_GPIO_BASE;
-
-        roff += GPIC_GPIO_BANKOFF(gpio);
-        bit = GPIC_GPIO_TO_BIT(gpio);
-        __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
-        wmb();
-
-        return 0;
-}
-
-static inline int au1300_gpio_set_value(unsigned int gpio, int v)
-{
-        void __iomem *roff = AU1300_GPIC_ADDR;
-        unsigned long bit;
-
-        gpio -= AU1300_GPIO_BASE;
-
-        roff += GPIC_GPIO_BANKOFF(gpio);
-        bit = GPIC_GPIO_TO_BIT(gpio);
-        __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
-                                    : AU1300_GPIC_PINVALCLR));
-        wmb();
-
-        return 0;
-}
-
-static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
-{
-        /* hw switches to output automatically */
-        return au1300_gpio_set_value(gpio, v);
-}
-
-static inline int au1300_gpio_to_irq(unsigned int gpio)
-{
-        return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
-}
-
-static inline int au1300_irq_to_gpio(unsigned int irq)
-{
-        return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
-}
-
-static inline int au1300_gpio_is_valid(unsigned int gpio)
-{
-        int ret;
-
-        switch (alchemy_get_cputype()) {
-        case ALCHEMY_CPU_AU1300:
-                ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
-                break;
-        default:
-                ret = 0;
-        }
-        return ret;
-}
-
-static inline int au1300_gpio_cansleep(unsigned int gpio)
-{
-        return 0;
-}
-
-/* hardware remembers gpio 0-63 levels on powerup */
-static inline int au1300_gpio_getinitlvl(unsigned int gpio)
-{
-        void __iomem *roff = AU1300_GPIC_ADDR;
-        unsigned long v;
-
-        if (unlikely(gpio > 63))
-                return 0;
-        else if (gpio > 31) {
-                gpio -= 32;
-                roff += 4;
-        }
-
-        v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
-        return (v >> gpio) & 1;
-}
-
-/**********************************************************************/
-
-/* Linux gpio framework integration.
-*
-* 4 use cases of Alchemy GPIOS:
-*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
-*       Board must register gpiochips.
-*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
-*       A gpiochip for the 75 GPIOs is registered.
-*
-*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
-*       the boards' gpio.h must provide the linux gpio wrapper functions,
-*
-*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
-*       inlinable gpio functions are provided which enable access to the
-*       Au1300 gpios only by using the numbers straight out of the data-
-*       sheets.
-
-* Cases 1 and 3 are intended for boards which want to provide their own
-* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
-* which are in part provided by spare Au1300 GPIO pins and in part by
-* an external FPGA but you still want them to be accssible in linux
-* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
-* as required).
-*/
-
-#ifndef CONFIG_GPIOLIB
-
-#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
-
-#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (4) */
-
-static inline int gpio_direction_input(unsigned int gpio)
-{
-        return au1300_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned int gpio, int v)
-{
-        return au1300_gpio_direction_output(gpio, v);
-}
-
-static inline int gpio_get_value(unsigned int gpio)
-{
-        return au1300_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned int gpio, int v)
-{
-        au1300_gpio_set_value(gpio, v);
-}
-
-static inline int gpio_get_value_cansleep(unsigned gpio)
-{
-        return gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value_cansleep(unsigned gpio, int value)
-{
-        gpio_set_value(gpio, value);
-}
-
-static inline int gpio_is_valid(unsigned int gpio)
-{
-        return au1300_gpio_is_valid(gpio);
-}
-
-static inline int gpio_cansleep(unsigned int gpio)
-{
-        return au1300_gpio_cansleep(gpio);
-}
-
-static inline int gpio_to_irq(unsigned int gpio)
-{
-        return au1300_gpio_to_irq(gpio);
-}
-
-static inline int irq_to_gpio(unsigned int irq)
-{
-        return au1300_irq_to_gpio(irq);
-}
-
-static inline int gpio_request(unsigned int gpio, const char *label)
-{
-        return 0;
-}
-
-static inline int gpio_request_one(unsigned gpio,
-                                        unsigned long flags, const char *label)
-{
-        return 0;
-}
-
-static inline int gpio_request_array(struct gpio *array, size_t num)
-{
-        return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-}
-
-static inline void gpio_free_array(struct gpio *array, size_t num)
-{
-}
-
-static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
-{
-        return -ENOSYS;
-}
-
-static inline void gpio_unexport(unsigned gpio)
-{
-}
-
-static inline int gpio_export(unsigned gpio, bool direction_may_change)
-{
-        return -ENOSYS;
-}
-
-static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
-{
-        return -ENOSYS;
-}
-
-static inline int gpio_export_link(struct device *dev, const char *name,
-                                   unsigned gpio)
-{
-        return -ENOSYS;
-}
-
-#endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
-
-#endif  /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
-
-#endif  /* CONFIG GPIOLIB */
-
-#endif /* _GPIO_AU1300_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index 22e7ff17fc4..c3f60cdc320 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -1,86 +1,10 @@
-/*
- * Alchemy GPIO support.
- *
- * With CONFIG_GPIOLIB=y different types of on-chip GPIO can be supported within
- *  the same kernel image.
- * With CONFIG_GPIOLIB=n, your board must select ALCHEMY_GPIOINT_AU1XXX for the
- *  appropriate CPU type (AU1000 currently).
- */
-
 #ifndef _ALCHEMY_GPIO_H_
 #define _ALCHEMY_GPIO_H_
 
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-au1x00/gpio-au1000.h>
-#include <asm/mach-au1x00/gpio-au1300.h>
-
-/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
- * SYS_PININPUTEN is written to at least once.  On Au1550/Au1200/Au1300 this
- * register enables use of GPIOs as wake source.
- */
-static inline void alchemy_gpio1_input_enable(void)
-{
-        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
-        __raw_writel(0, base + 0x110);          /* the write op is key */
-        wmb();
-}
-
-
-/* Linux gpio framework integration.
-*
-* 4 use cases of Alchemy GPIOS:
-*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
-*       Board must register gpiochips.
-*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
-*       A gpiochip for the 75 GPIOs is registered.
-*
-*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
-*       the boards' gpio.h must provide the linux gpio wrapper functions,
-*
-*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
-*       inlinable gpio functions are provided which enable access to the
-*       Au1300 gpios only by using the numbers straight out of the data-
-*       sheets.
-
-* Cases 1 and 3 are intended for boards which want to provide their own
-* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
-* which are in part provided by spare Au1300 GPIO pins and in part by
-* an external FPGA but you still want them to be accssible in linux
-* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
-* as required).
-*/
-
-#ifdef CONFIG_GPIOLIB
-
-/* wraps the cpu-dependent irq_to_gpio functions */
-/* FIXME: gpiolib needs an irq_to_gpio hook */
-static inline int __au_irq_to_gpio(unsigned int irq)
-{
-        switch (alchemy_get_cputype()) {
-        case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
-                return alchemy_irq_to_gpio(irq);
-        case ALCHEMY_CPU_AU1300:
-                return au1300_irq_to_gpio(irq);
-        }
-        return -EINVAL;
-}
-
-
-/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
-#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (2) */
-
-/* get everything through gpiolib */
-#define gpio_to_irq     __gpio_to_irq
-#define gpio_get_value  __gpio_get_value
-#define gpio_set_value  __gpio_set_value
-#define gpio_cansleep   __gpio_cansleep
-#define irq_to_gpio     __au_irq_to_gpio
-
-#include <asm-generic/gpio.h>
-
-#endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
+#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000)
 
+#include <asm/mach-au1x00/gpio-au1000.h>
 
-#endif  /* CONFIG_GPIOLIB */
+#endif
 
 #endif  /* _ALCHEMY_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/war.h b/arch/mips/include/asm/mach-au1x00/war.h
index 72e260d24e5..dd57d03d68b 100644
--- a/arch/mips/include/asm/mach-au1x00/war.h
+++ b/arch/mips/include/asm/mach-au1x00/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index cc7563ba1cb..d008f47a28b 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -19,41 +19,7 @@
 #ifndef __ASM_BCM47XX_H
 #define __ASM_BCM47XX_H
 
-#include <linux/ssb/ssb.h>
-#include <linux/bcma/bcma.h>
-#include <linux/bcma/bcma_soc.h>
-
-enum bcm47xx_bus_type {
-#ifdef CONFIG_BCM47XX_SSB
-        BCM47XX_BUS_TYPE_SSB,
-#endif
-#ifdef CONFIG_BCM47XX_BCMA
-        BCM47XX_BUS_TYPE_BCMA,
-#endif
-};
-
-union bcm47xx_bus {
-#ifdef CONFIG_BCM47XX_SSB
-        struct ssb_bus ssb;
-#endif
-#ifdef CONFIG_BCM47XX_BCMA
-        struct bcma_soc bcma;
-#endif
-};
-
-extern union bcm47xx_bus bcm47xx_bus;
-extern enum bcm47xx_bus_type bcm47xx_bus_type;
-
-void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
-                        bool fallback);
-
-#ifdef CONFIG_BCM47XX_SSB
-void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo,
-                                const char *prefix);
-#endif
-#ifdef CONFIG_BCM47XX_BCMA
-void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo,
-                                 const char *prefix);
-#endif
+/* SSB bus */
+extern struct ssb_bus ssb_bcm47xx;
 
 #endif /* __ASM_BCM47XX_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
index 90daefa24a4..98504142124 100644
--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
@@ -1,17 +1,65 @@
-#ifndef __ASM_MIPS_MACH_BCM47XX_GPIO_H
-#define __ASM_MIPS_MACH_BCM47XX_GPIO_H
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
+ */
 
-#include <asm-generic/gpio.h>
+#ifndef __BCM47XX_GPIO_H
+#define __BCM47XX_GPIO_H
+
+#include <linux/ssb/ssb_embedded.h>
+#include <asm/mach-bcm47xx/bcm47xx.h>
+
+#define BCM47XX_EXTIF_GPIO_LINES        5
+#define BCM47XX_CHIPCO_GPIO_LINES       16
+
+extern int gpio_request(unsigned gpio, const char *label);
+extern void gpio_free(unsigned gpio);
+extern int gpio_to_irq(unsigned gpio);
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return ssb_gpio_in(&ssb_bcm47xx, 1 << gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        ssb_gpio_out(&ssb_bcm47xx, 1 << gpio, value ? 1 << gpio : 0);
+}
 
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
+static inline int gpio_direction_input(unsigned gpio)
+{
+        ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 0);
+        return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        /* first set the gpio out value */
+        ssb_gpio_out(&ssb_bcm47xx, 1 << gpio, value ? 1 << gpio : 0);
+        /* then set the gpio mode */
+        ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio);
+        return 0;
+}
 
-#define gpio_cansleep __gpio_cansleep
-#define gpio_to_irq __gpio_to_irq
+static inline int gpio_intmask(unsigned gpio, int value)
+{
+        ssb_gpio_intmask(&ssb_bcm47xx, 1 << gpio,
+                         value ? 1 << gpio : 0);
+        return 0;
+}
 
-static inline int irq_to_gpio(unsigned int irq)
+static inline int gpio_polarity(unsigned gpio, int value)
 {
-        return -EINVAL;
+        ssb_gpio_polarity(&ssb_bcm47xx, 1 << gpio,
+                          value ? 1 << gpio : 0);
+        return 0;
 }
 
-#endif
+
+/* cansleep wrappers */
+#include <asm-generic/gpio.h>
+
+#endif /* __BCM47XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h
index 69ef3efe06e..184d5ecb5f5 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h
@@ -37,7 +37,7 @@ struct nvram_header {
 
 extern int nvram_getenv(char *name, char *val, size_t val_len);
 
-static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
+static inline void nvram_parse_macaddr(char *buf, u8 *macaddr)
 {
         if (strchr(buf, ':'))
                 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
diff --git a/arch/mips/include/asm/mach-bcm47xx/war.h b/arch/mips/include/asm/mach-bcm47xx/war.h
index a3d2f448b10..87cd4651dda 100644
--- a/arch/mips/include/asm/mach-bcm47xx/war.h
+++ b/arch/mips/include/asm/mach-bcm47xx/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index dbd5b5ad07a..96a2391ad85 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,31 +9,16 @@
  * compile time if only one CPU support is enabled (idea stolen from
  * arm mach-types)
  */
-#define BCM6328_CPU_ID          0x6328
 #define BCM6338_CPU_ID          0x6338
 #define BCM6345_CPU_ID          0x6345
 #define BCM6348_CPU_ID          0x6348
 #define BCM6358_CPU_ID          0x6358
-#define BCM6368_CPU_ID          0x6368
 
 void __init bcm63xx_cpu_init(void);
 u16 __bcm63xx_get_cpu_id(void);
 u16 bcm63xx_get_cpu_rev(void);
 unsigned int bcm63xx_get_cpu_freq(void);
 
-#ifdef CONFIG_BCM63XX_CPU_6328
-# ifdef bcm63xx_get_cpu_id
-#  undef bcm63xx_get_cpu_id
-#  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
-#  define BCMCPU_RUNTIME_DETECT
-# else
-#  define bcm63xx_get_cpu_id()  BCM6328_CPU_ID
-# endif
-# define BCMCPU_IS_6328()       (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
-#else
-# define BCMCPU_IS_6328()       (0)
-#endif
-
 #ifdef CONFIG_BCM63XX_CPU_6338
 # ifdef bcm63xx_get_cpu_id
 #  undef bcm63xx_get_cpu_id
@@ -86,19 +71,6 @@ unsigned int bcm63xx_get_cpu_freq(void);
 # define BCMCPU_IS_6358()       (0)
 #endif
 
-#ifdef CONFIG_BCM63XX_CPU_6368
-# ifdef bcm63xx_get_cpu_id
-#  undef bcm63xx_get_cpu_id
-#  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
-#  define BCMCPU_RUNTIME_DETECT
-# else
-#  define bcm63xx_get_cpu_id()  BCM6368_CPU_ID
-# endif
-# define BCMCPU_IS_6368()       (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
-#else
-# define BCMCPU_IS_6368()       (0)
-#endif
-
 #ifndef bcm63xx_get_cpu_id
 #error "No CPU support configured"
 #endif
@@ -120,107 +92,30 @@ enum bcm63xx_regs_set {
         RSET_OHCI0,
         RSET_OHCI_PRIV,
         RSET_USBH_PRIV,
-        RSET_USBD,
-        RSET_USBDMA,
         RSET_MPI,
         RSET_PCMCIA,
-        RSET_PCIE,
         RSET_DSL,
         RSET_ENET0,
         RSET_ENET1,
         RSET_ENETDMA,
-        RSET_ENETDMAC,
-        RSET_ENETDMAS,
-        RSET_ENETSW,
         RSET_EHCI0,
         RSET_SDRAM,
         RSET_MEMC,
         RSET_DDR,
-        RSET_M2M,
-        RSET_ATM,
-        RSET_XTM,
-        RSET_XTMDMA,
-        RSET_XTMDMAC,
-        RSET_XTMDMAS,
-        RSET_PCM,
-        RSET_PCMDMA,
-        RSET_PCMDMAC,
-        RSET_PCMDMAS,
-        RSET_RNG,
-        RSET_MISC
 };
 
 #define RSET_DSL_LMEM_SIZE              (64 * 1024 * 4)
 #define RSET_DSL_SIZE                   4096
 #define RSET_WDT_SIZE                   12
-#define BCM_6338_RSET_SPI_SIZE          64
-#define BCM_6348_RSET_SPI_SIZE          64
-#define BCM_6358_RSET_SPI_SIZE          1804
-#define BCM_6368_RSET_SPI_SIZE          1804
 #define RSET_ENET_SIZE                  2048
 #define RSET_ENETDMA_SIZE               2048
-#define RSET_ENETSW_SIZE                65536
 #define RSET_UART_SIZE                  24
 #define RSET_UDC_SIZE                   256
 #define RSET_OHCI_SIZE                  256
 #define RSET_EHCI_SIZE                  256
-#define RSET_USBD_SIZE                  256
-#define RSET_USBDMA_SIZE                1280
 #define RSET_PCMCIA_SIZE                12
-#define RSET_M2M_SIZE                   256
-#define RSET_ATM_SIZE                   4096
-#define RSET_XTM_SIZE                   10240
-#define RSET_XTMDMA_SIZE                256
-#define RSET_XTMDMAC_SIZE(chans)        (16 * (chans))
-#define RSET_XTMDMAS_SIZE(chans)        (16 * (chans))
-#define RSET_RNG_SIZE                   20
 
 /*
- * 6328 register sets base address
- */
-#define BCM_6328_DSL_LMEM_BASE          (0xdeadbeef)
-#define BCM_6328_PERF_BASE              (0xb0000000)
-#define BCM_6328_TIMER_BASE             (0xb0000040)
-#define BCM_6328_WDT_BASE               (0xb000005c)
-#define BCM_6328_UART0_BASE             (0xb0000100)
-#define BCM_6328_UART1_BASE             (0xb0000120)
-#define BCM_6328_GPIO_BASE              (0xb0000080)
-#define BCM_6328_SPI_BASE               (0xdeadbeef)
-#define BCM_6328_UDC0_BASE              (0xdeadbeef)
-#define BCM_6328_USBDMA_BASE            (0xb000c000)
-#define BCM_6328_OHCI0_BASE             (0xb0002600)
-#define BCM_6328_OHCI_PRIV_BASE         (0xdeadbeef)
-#define BCM_6328_USBH_PRIV_BASE         (0xb0002700)
-#define BCM_6328_USBD_BASE              (0xb0002400)
-#define BCM_6328_MPI_BASE               (0xdeadbeef)
-#define BCM_6328_PCMCIA_BASE            (0xdeadbeef)
-#define BCM_6328_PCIE_BASE              (0xb0e40000)
-#define BCM_6328_SDRAM_REGS_BASE        (0xdeadbeef)
-#define BCM_6328_DSL_BASE               (0xb0001900)
-#define BCM_6328_UBUS_BASE              (0xdeadbeef)
-#define BCM_6328_ENET0_BASE             (0xdeadbeef)
-#define BCM_6328_ENET1_BASE             (0xdeadbeef)
-#define BCM_6328_ENETDMA_BASE           (0xb000d800)
-#define BCM_6328_ENETDMAC_BASE          (0xb000da00)
-#define BCM_6328_ENETDMAS_BASE          (0xb000dc00)
-#define BCM_6328_ENETSW_BASE            (0xb0e00000)
-#define BCM_6328_EHCI0_BASE             (0xb0002500)
-#define BCM_6328_SDRAM_BASE             (0xdeadbeef)
-#define BCM_6328_MEMC_BASE              (0xdeadbeef)
-#define BCM_6328_DDR_BASE               (0xb0003000)
-#define BCM_6328_M2M_BASE               (0xdeadbeef)
-#define BCM_6328_ATM_BASE               (0xdeadbeef)
-#define BCM_6328_XTM_BASE               (0xdeadbeef)
-#define BCM_6328_XTMDMA_BASE            (0xb000b800)
-#define BCM_6328_XTMDMAC_BASE           (0xdeadbeef)
-#define BCM_6328_XTMDMAS_BASE           (0xdeadbeef)
-#define BCM_6328_PCM_BASE               (0xb000a800)
-#define BCM_6328_PCMDMA_BASE            (0xdeadbeef)
-#define BCM_6328_PCMDMAC_BASE           (0xdeadbeef)
-#define BCM_6328_PCMDMAS_BASE           (0xdeadbeef)
-#define BCM_6328_RNG_BASE               (0xdeadbeef)
-#define BCM_6328_MISC_BASE              (0xb0001800)
-/*
  * 6338 register sets base address
  */
 #define BCM_6338_DSL_LMEM_BASE          (0xfff00000)
@@ -237,35 +132,19 @@ enum bcm63xx_regs_set {
 #define BCM_6338_OHCI0_BASE             (0xdeadbeef)
 #define BCM_6338_OHCI_PRIV_BASE         (0xfffe3000)
 #define BCM_6338_USBH_PRIV_BASE         (0xdeadbeef)
-#define BCM_6338_USBD_BASE              (0xdeadbeef)
 #define BCM_6338_MPI_BASE               (0xfffe3160)
 #define BCM_6338_PCMCIA_BASE            (0xdeadbeef)
-#define BCM_6338_PCIE_BASE              (0xdeadbeef)
 #define BCM_6338_SDRAM_REGS_BASE        (0xfffe3100)
 #define BCM_6338_DSL_BASE               (0xfffe1000)
+#define BCM_6338_SAR_BASE               (0xfffe2000)
 #define BCM_6338_UBUS_BASE              (0xdeadbeef)
 #define BCM_6338_ENET0_BASE             (0xfffe2800)
 #define BCM_6338_ENET1_BASE             (0xdeadbeef)
 #define BCM_6338_ENETDMA_BASE           (0xfffe2400)
-#define BCM_6338_ENETDMAC_BASE          (0xfffe2500)
-#define BCM_6338_ENETDMAS_BASE          (0xfffe2600)
-#define BCM_6338_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6338_EHCI0_BASE             (0xdeadbeef)
 #define BCM_6338_SDRAM_BASE             (0xfffe3100)
 #define BCM_6338_MEMC_BASE              (0xdeadbeef)
 #define BCM_6338_DDR_BASE               (0xdeadbeef)
-#define BCM_6338_M2M_BASE               (0xdeadbeef)
-#define BCM_6338_ATM_BASE               (0xfffe2000)
-#define BCM_6338_XTM_BASE               (0xdeadbeef)
-#define BCM_6338_XTMDMA_BASE            (0xdeadbeef)
-#define BCM_6338_XTMDMAC_BASE           (0xdeadbeef)
-#define BCM_6338_XTMDMAS_BASE           (0xdeadbeef)
-#define BCM_6338_PCM_BASE               (0xdeadbeef)
-#define BCM_6338_PCMDMA_BASE            (0xdeadbeef)
-#define BCM_6338_PCMDMAC_BASE           (0xdeadbeef)
-#define BCM_6338_PCMDMAS_BASE           (0xdeadbeef)
-#define BCM_6338_RNG_BASE               (0xdeadbeef)
-#define BCM_6338_MISC_BASE              (0xdeadbeef)
 
 /*
  * 6345 register sets base address
@@ -283,36 +162,20 @@ enum bcm63xx_regs_set {
 #define BCM_6345_USBDMA_BASE            (0xfffe2800)
 #define BCM_6345_ENET0_BASE             (0xfffe1800)
 #define BCM_6345_ENETDMA_BASE           (0xfffe2800)
-#define BCM_6345_ENETDMAC_BASE          (0xfffe2900)
-#define BCM_6345_ENETDMAS_BASE          (0xfffe2a00)
-#define BCM_6345_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE            (0xfffe2028)
-#define BCM_6345_MPI_BASE               (0xfffe2000)
-#define BCM_6345_PCIE_BASE              (0xdeadbeef)
+#define BCM_6345_MPI_BASE               (0xdeadbeef)
 #define BCM_6345_OHCI0_BASE             (0xfffe2100)
 #define BCM_6345_OHCI_PRIV_BASE         (0xfffe2200)
 #define BCM_6345_USBH_PRIV_BASE         (0xdeadbeef)
-#define BCM_6345_USBD_BASE              (0xdeadbeef)
 #define BCM_6345_SDRAM_REGS_BASE        (0xfffe2300)
 #define BCM_6345_DSL_BASE               (0xdeadbeef)
+#define BCM_6345_SAR_BASE               (0xdeadbeef)
 #define BCM_6345_UBUS_BASE              (0xdeadbeef)
 #define BCM_6345_ENET1_BASE             (0xdeadbeef)
 #define BCM_6345_EHCI0_BASE             (0xdeadbeef)
 #define BCM_6345_SDRAM_BASE             (0xfffe2300)
 #define BCM_6345_MEMC_BASE              (0xdeadbeef)
 #define BCM_6345_DDR_BASE               (0xdeadbeef)
-#define BCM_6345_M2M_BASE               (0xdeadbeef)
-#define BCM_6345_ATM_BASE               (0xfffe4000)
-#define BCM_6345_XTM_BASE               (0xdeadbeef)
-#define BCM_6345_XTMDMA_BASE            (0xdeadbeef)
-#define BCM_6345_XTMDMAC_BASE           (0xdeadbeef)
-#define BCM_6345_XTMDMAS_BASE           (0xdeadbeef)
-#define BCM_6345_PCM_BASE               (0xdeadbeef)
-#define BCM_6345_PCMDMA_BASE            (0xdeadbeef)
-#define BCM_6345_PCMDMAC_BASE           (0xdeadbeef)
-#define BCM_6345_PCMDMAS_BASE           (0xdeadbeef)
-#define BCM_6345_RNG_BASE               (0xdeadbeef)
-#define BCM_6345_MISC_BASE              (0xdeadbeef)
 
 /*
  * 6348 register sets base address
@@ -326,38 +189,20 @@ enum bcm63xx_regs_set {
 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 #define BCM_6348_SPI_BASE               (0xfffe0c00)
 #define BCM_6348_UDC0_BASE              (0xfffe1000)
-#define BCM_6348_USBDMA_BASE            (0xdeadbeef)
 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
 #define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
 #define BCM_6348_USBH_PRIV_BASE         (0xdeadbeef)
-#define BCM_6348_USBD_BASE              (0xdeadbeef)
 #define BCM_6348_MPI_BASE               (0xfffe2000)
 #define BCM_6348_PCMCIA_BASE            (0xfffe2054)
-#define BCM_6348_PCIE_BASE              (0xdeadbeef)
 #define BCM_6348_SDRAM_REGS_BASE        (0xfffe2300)
-#define BCM_6348_M2M_BASE               (0xfffe2800)
 #define BCM_6348_DSL_BASE               (0xfffe3000)
 #define BCM_6348_ENET0_BASE             (0xfffe6000)
 #define BCM_6348_ENET1_BASE             (0xfffe6800)
 #define BCM_6348_ENETDMA_BASE           (0xfffe7000)
-#define BCM_6348_ENETDMAC_BASE          (0xfffe7100)
-#define BCM_6348_ENETDMAS_BASE          (0xfffe7200)
-#define BCM_6348_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6348_EHCI0_BASE             (0xdeadbeef)
 #define BCM_6348_SDRAM_BASE             (0xfffe2300)
 #define BCM_6348_MEMC_BASE              (0xdeadbeef)
 #define BCM_6348_DDR_BASE               (0xdeadbeef)
-#define BCM_6348_ATM_BASE               (0xfffe4000)
-#define BCM_6348_XTM_BASE               (0xdeadbeef)
-#define BCM_6348_XTMDMA_BASE            (0xdeadbeef)
-#define BCM_6348_XTMDMAC_BASE           (0xdeadbeef)
-#define BCM_6348_XTMDMAS_BASE           (0xdeadbeef)
-#define BCM_6348_PCM_BASE               (0xdeadbeef)
-#define BCM_6348_PCMDMA_BASE            (0xdeadbeef)
-#define BCM_6348_PCMDMAC_BASE           (0xdeadbeef)
-#define BCM_6348_PCMDMAS_BASE           (0xdeadbeef)
-#define BCM_6348_RNG_BASE               (0xdeadbeef)
-#define BCM_6348_MISC_BASE              (0xdeadbeef)
 
 /*
  * 6358 register sets base address
@@ -369,203 +214,222 @@ enum bcm63xx_regs_set {
 #define BCM_6358_UART0_BASE             (0xfffe0100)
 #define BCM_6358_UART1_BASE             (0xfffe0120)
 #define BCM_6358_GPIO_BASE              (0xfffe0080)
-#define BCM_6358_SPI_BASE               (0xfffe0800)
+#define BCM_6358_SPI_BASE               (0xdeadbeef)
 #define BCM_6358_UDC0_BASE              (0xfffe0800)
-#define BCM_6358_USBDMA_BASE            (0xdeadbeef)
 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
 #define BCM_6358_USBH_PRIV_BASE         (0xfffe1500)
-#define BCM_6358_USBD_BASE              (0xdeadbeef)
 #define BCM_6358_MPI_BASE               (0xfffe1000)
 #define BCM_6358_PCMCIA_BASE            (0xfffe1054)
-#define BCM_6358_PCIE_BASE              (0xdeadbeef)
 #define BCM_6358_SDRAM_REGS_BASE        (0xfffe2300)
-#define BCM_6358_M2M_BASE               (0xdeadbeef)
 #define BCM_6358_DSL_BASE               (0xfffe3000)
 #define BCM_6358_ENET0_BASE             (0xfffe4000)
 #define BCM_6358_ENET1_BASE             (0xfffe4800)
 #define BCM_6358_ENETDMA_BASE           (0xfffe5000)
-#define BCM_6358_ENETDMAC_BASE          (0xfffe5100)
-#define BCM_6358_ENETDMAS_BASE          (0xfffe5200)
-#define BCM_6358_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6358_EHCI0_BASE             (0xfffe1300)
 #define BCM_6358_SDRAM_BASE             (0xdeadbeef)
 #define BCM_6358_MEMC_BASE              (0xfffe1200)
 #define BCM_6358_DDR_BASE               (0xfffe12a0)
-#define BCM_6358_ATM_BASE               (0xfffe2000)
-#define BCM_6358_XTM_BASE               (0xdeadbeef)
-#define BCM_6358_XTMDMA_BASE            (0xdeadbeef)
-#define BCM_6358_XTMDMAC_BASE           (0xdeadbeef)
-#define BCM_6358_XTMDMAS_BASE           (0xdeadbeef)
-#define BCM_6358_PCM_BASE               (0xfffe1600)
-#define BCM_6358_PCMDMA_BASE            (0xfffe1800)
-#define BCM_6358_PCMDMAC_BASE           (0xfffe1900)
-#define BCM_6358_PCMDMAS_BASE           (0xfffe1a00)
-#define BCM_6358_RNG_BASE               (0xdeadbeef)
-#define BCM_6358_MISC_BASE              (0xdeadbeef)
-
-
-/*
- * 6368 register sets base address
- */
-#define BCM_6368_DSL_LMEM_BASE          (0xdeadbeef)
-#define BCM_6368_PERF_BASE              (0xb0000000)
-#define BCM_6368_TIMER_BASE             (0xb0000040)
-#define BCM_6368_WDT_BASE               (0xb000005c)
-#define BCM_6368_UART0_BASE             (0xb0000100)
-#define BCM_6368_UART1_BASE             (0xb0000120)
-#define BCM_6368_GPIO_BASE              (0xb0000080)
-#define BCM_6368_SPI_BASE               (0xb0000800)
-#define BCM_6368_UDC0_BASE              (0xdeadbeef)
-#define BCM_6368_USBDMA_BASE            (0xb0004800)
-#define BCM_6368_OHCI0_BASE             (0xb0001600)
-#define BCM_6368_OHCI_PRIV_BASE         (0xdeadbeef)
-#define BCM_6368_USBH_PRIV_BASE         (0xb0001700)
-#define BCM_6368_USBD_BASE              (0xb0001400)
-#define BCM_6368_MPI_BASE               (0xb0001000)
-#define BCM_6368_PCMCIA_BASE            (0xb0001054)
-#define BCM_6368_PCIE_BASE              (0xdeadbeef)
-#define BCM_6368_SDRAM_REGS_BASE        (0xdeadbeef)
-#define BCM_6368_M2M_BASE               (0xdeadbeef)
-#define BCM_6368_DSL_BASE               (0xdeadbeef)
-#define BCM_6368_ENET0_BASE             (0xdeadbeef)
-#define BCM_6368_ENET1_BASE             (0xdeadbeef)
-#define BCM_6368_ENETDMA_BASE           (0xb0006800)
-#define BCM_6368_ENETDMAC_BASE          (0xb0006a00)
-#define BCM_6368_ENETDMAS_BASE          (0xb0006c00)
-#define BCM_6368_ENETSW_BASE            (0xb0f00000)
-#define BCM_6368_EHCI0_BASE             (0xb0001500)
-#define BCM_6368_SDRAM_BASE             (0xdeadbeef)
-#define BCM_6368_MEMC_BASE              (0xb0001200)
-#define BCM_6368_DDR_BASE               (0xb0001280)
-#define BCM_6368_ATM_BASE               (0xdeadbeef)
-#define BCM_6368_XTM_BASE               (0xb0001800)
-#define BCM_6368_XTMDMA_BASE            (0xb0005000)
-#define BCM_6368_XTMDMAC_BASE           (0xb0005200)
-#define BCM_6368_XTMDMAS_BASE           (0xb0005400)
-#define BCM_6368_PCM_BASE               (0xb0004000)
-#define BCM_6368_PCMDMA_BASE            (0xb0005800)
-#define BCM_6368_PCMDMAC_BASE           (0xb0005a00)
-#define BCM_6368_PCMDMAS_BASE           (0xb0005c00)
-#define BCM_6368_RNG_BASE               (0xb0004180)
-#define BCM_6368_MISC_BASE              (0xdeadbeef)
 
 
 extern const unsigned long *bcm63xx_regs_base;
 
-#define __GEN_RSET_BASE(__cpu, __rset)                                  \
-        case RSET_## __rset :                                           \
-                return BCM_## __cpu ##_## __rset ##_BASE;
-
-#define __GEN_RSET(__cpu)                                               \
-        switch (set) {                                                  \
-        __GEN_RSET_BASE(__cpu, DSL_LMEM)                                \
-        __GEN_RSET_BASE(__cpu, PERF)                                    \
-        __GEN_RSET_BASE(__cpu, TIMER)                                   \
-        __GEN_RSET_BASE(__cpu, WDT)                                     \
-        __GEN_RSET_BASE(__cpu, UART0)                                   \
-        __GEN_RSET_BASE(__cpu, UART1)                                   \
-        __GEN_RSET_BASE(__cpu, GPIO)                                    \
-        __GEN_RSET_BASE(__cpu, SPI)                                     \
-        __GEN_RSET_BASE(__cpu, UDC0)                                    \
-        __GEN_RSET_BASE(__cpu, OHCI0)                                   \
-        __GEN_RSET_BASE(__cpu, OHCI_PRIV)                               \
-        __GEN_RSET_BASE(__cpu, USBH_PRIV)                               \
-        __GEN_RSET_BASE(__cpu, USBD)                                    \
-        __GEN_RSET_BASE(__cpu, USBDMA)                                  \
-        __GEN_RSET_BASE(__cpu, MPI)                                     \
-        __GEN_RSET_BASE(__cpu, PCMCIA)                                  \
-        __GEN_RSET_BASE(__cpu, PCIE)                                    \
-        __GEN_RSET_BASE(__cpu, DSL)                                     \
-        __GEN_RSET_BASE(__cpu, ENET0)                                   \
-        __GEN_RSET_BASE(__cpu, ENET1)                                   \
-        __GEN_RSET_BASE(__cpu, ENETDMA)                                 \
-        __GEN_RSET_BASE(__cpu, ENETDMAC)                                \
-        __GEN_RSET_BASE(__cpu, ENETDMAS)                                \
-        __GEN_RSET_BASE(__cpu, ENETSW)                                  \
-        __GEN_RSET_BASE(__cpu, EHCI0)                                   \
-        __GEN_RSET_BASE(__cpu, SDRAM)                                   \
-        __GEN_RSET_BASE(__cpu, MEMC)                                    \
-        __GEN_RSET_BASE(__cpu, DDR)                                     \
-        __GEN_RSET_BASE(__cpu, M2M)                                     \
-        __GEN_RSET_BASE(__cpu, ATM)                                     \
-        __GEN_RSET_BASE(__cpu, XTM)                                     \
-        __GEN_RSET_BASE(__cpu, XTMDMA)                                  \
-        __GEN_RSET_BASE(__cpu, XTMDMAC)                                 \
-        __GEN_RSET_BASE(__cpu, XTMDMAS)                                 \
-        __GEN_RSET_BASE(__cpu, PCM)                                     \
-        __GEN_RSET_BASE(__cpu, PCMDMA)                                  \
-        __GEN_RSET_BASE(__cpu, PCMDMAC)                                 \
-        __GEN_RSET_BASE(__cpu, PCMDMAS)                                 \
-        __GEN_RSET_BASE(__cpu, RNG)                                     \
-        __GEN_RSET_BASE(__cpu, MISC)                                    \
-        }
-
-#define __GEN_CPU_REGS_TABLE(__cpu)                                     \
-        [RSET_DSL_LMEM]         = BCM_## __cpu ##_DSL_LMEM_BASE,        \
-        [RSET_PERF]             = BCM_## __cpu ##_PERF_BASE,            \
-        [RSET_TIMER]            = BCM_## __cpu ##_TIMER_BASE,           \
-        [RSET_WDT]              = BCM_## __cpu ##_WDT_BASE,             \
-        [RSET_UART0]            = BCM_## __cpu ##_UART0_BASE,           \
-        [RSET_UART1]            = BCM_## __cpu ##_UART1_BASE,           \
-        [RSET_GPIO]             = BCM_## __cpu ##_GPIO_BASE,            \
-        [RSET_SPI]              = BCM_## __cpu ##_SPI_BASE,             \
-        [RSET_UDC0]             = BCM_## __cpu ##_UDC0_BASE,            \
-        [RSET_OHCI0]            = BCM_## __cpu ##_OHCI0_BASE,           \
-        [RSET_OHCI_PRIV]        = BCM_## __cpu ##_OHCI_PRIV_BASE,       \
-        [RSET_USBH_PRIV]        = BCM_## __cpu ##_USBH_PRIV_BASE,       \
-        [RSET_USBD]             = BCM_## __cpu ##_USBD_BASE,            \
-        [RSET_USBDMA]           = BCM_## __cpu ##_USBDMA_BASE,          \
-        [RSET_MPI]              = BCM_## __cpu ##_MPI_BASE,             \
-        [RSET_PCMCIA]           = BCM_## __cpu ##_PCMCIA_BASE,          \
-        [RSET_PCIE]             = BCM_## __cpu ##_PCIE_BASE,            \
-        [RSET_DSL]              = BCM_## __cpu ##_DSL_BASE,             \
-        [RSET_ENET0]            = BCM_## __cpu ##_ENET0_BASE,           \
-        [RSET_ENET1]            = BCM_## __cpu ##_ENET1_BASE,           \
-        [RSET_ENETDMA]          = BCM_## __cpu ##_ENETDMA_BASE,         \
-        [RSET_ENETDMAC]         = BCM_## __cpu ##_ENETDMAC_BASE,        \
-        [RSET_ENETDMAS]         = BCM_## __cpu ##_ENETDMAS_BASE,        \
-        [RSET_ENETSW]           = BCM_## __cpu ##_ENETSW_BASE,          \
-        [RSET_EHCI0]            = BCM_## __cpu ##_EHCI0_BASE,           \
-        [RSET_SDRAM]            = BCM_## __cpu ##_SDRAM_BASE,           \
-        [RSET_MEMC]             = BCM_## __cpu ##_MEMC_BASE,            \
-        [RSET_DDR]              = BCM_## __cpu ##_DDR_BASE,             \
-        [RSET_M2M]              = BCM_## __cpu ##_M2M_BASE,             \
-        [RSET_ATM]              = BCM_## __cpu ##_ATM_BASE,             \
-        [RSET_XTM]              = BCM_## __cpu ##_XTM_BASE,             \
-        [RSET_XTMDMA]           = BCM_## __cpu ##_XTMDMA_BASE,          \
-        [RSET_XTMDMAC]          = BCM_## __cpu ##_XTMDMAC_BASE,         \
-        [RSET_XTMDMAS]          = BCM_## __cpu ##_XTMDMAS_BASE,         \
-        [RSET_PCM]              = BCM_## __cpu ##_PCM_BASE,             \
-        [RSET_PCMDMA]           = BCM_## __cpu ##_PCMDMA_BASE,          \
-        [RSET_PCMDMAC]          = BCM_## __cpu ##_PCMDMAC_BASE,         \
-        [RSET_PCMDMAS]          = BCM_## __cpu ##_PCMDMAS_BASE,         \
-        [RSET_RNG]              = BCM_## __cpu ##_RNG_BASE,             \
-        [RSET_MISC]             = BCM_## __cpu ##_MISC_BASE,            \
-
-
 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 {
 #ifdef BCMCPU_RUNTIME_DETECT
         return bcm63xx_regs_base[set];
 #else
-#ifdef CONFIG_BCM63XX_CPU_6328
-        __GEN_RSET(6328)
-#endif
 #ifdef CONFIG_BCM63XX_CPU_6338
-        __GEN_RSET(6338)
+        switch (set) {
+        case RSET_DSL_LMEM:
+                return BCM_6338_DSL_LMEM_BASE;
+        case RSET_PERF:
+                return BCM_6338_PERF_BASE;
+        case RSET_TIMER:
+                return BCM_6338_TIMER_BASE;
+        case RSET_WDT:
+                return BCM_6338_WDT_BASE;
+        case RSET_UART0:
+                return BCM_6338_UART0_BASE;
+        case RSET_UART1:
+                return BCM_6338_UART1_BASE;
+        case RSET_GPIO:
+                return BCM_6338_GPIO_BASE;
+        case RSET_SPI:
+                return BCM_6338_SPI_BASE;
+        case RSET_UDC0:
+                return BCM_6338_UDC0_BASE;
+        case RSET_OHCI0:
+                return BCM_6338_OHCI0_BASE;
+        case RSET_OHCI_PRIV:
+                return BCM_6338_OHCI_PRIV_BASE;
+        case RSET_USBH_PRIV:
+                return BCM_6338_USBH_PRIV_BASE;
+        case RSET_MPI:
+                return BCM_6338_MPI_BASE;
+        case RSET_PCMCIA:
+                return BCM_6338_PCMCIA_BASE;
+        case RSET_DSL:
+                return BCM_6338_DSL_BASE;
+        case RSET_ENET0:
+                return BCM_6338_ENET0_BASE;
+        case RSET_ENET1:
+                return BCM_6338_ENET1_BASE;
+        case RSET_ENETDMA:
+                return BCM_6338_ENETDMA_BASE;
+        case RSET_EHCI0:
+                return BCM_6338_EHCI0_BASE;
+        case RSET_SDRAM:
+                return BCM_6338_SDRAM_BASE;
+        case RSET_MEMC:
+                return BCM_6338_MEMC_BASE;
+        case RSET_DDR:
+                return BCM_6338_DDR_BASE;
+        }
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6345
-        __GEN_RSET(6345)
+        switch (set) {
+        case RSET_DSL_LMEM:
+                return BCM_6345_DSL_LMEM_BASE;
+        case RSET_PERF:
+                return BCM_6345_PERF_BASE;
+        case RSET_TIMER:
+                return BCM_6345_TIMER_BASE;
+        case RSET_WDT:
+                return BCM_6345_WDT_BASE;
+        case RSET_UART0:
+                return BCM_6345_UART0_BASE;
+        case RSET_UART1:
+                return BCM_6345_UART1_BASE;
+        case RSET_GPIO:
+                return BCM_6345_GPIO_BASE;
+        case RSET_SPI:
+                return BCM_6345_SPI_BASE;
+        case RSET_UDC0:
+                return BCM_6345_UDC0_BASE;
+        case RSET_OHCI0:
+                return BCM_6345_OHCI0_BASE;
+        case RSET_OHCI_PRIV:
+                return BCM_6345_OHCI_PRIV_BASE;
+        case RSET_USBH_PRIV:
+                return BCM_6345_USBH_PRIV_BASE;
+        case RSET_MPI:
+                return BCM_6345_MPI_BASE;
+        case RSET_PCMCIA:
+                return BCM_6345_PCMCIA_BASE;
+        case RSET_DSL:
+                return BCM_6345_DSL_BASE;
+        case RSET_ENET0:
+                return BCM_6345_ENET0_BASE;
+        case RSET_ENET1:
+                return BCM_6345_ENET1_BASE;
+        case RSET_ENETDMA:
+                return BCM_6345_ENETDMA_BASE;
+        case RSET_EHCI0:
+                return BCM_6345_EHCI0_BASE;
+        case RSET_SDRAM:
+                return BCM_6345_SDRAM_BASE;
+        case RSET_MEMC:
+                return BCM_6345_MEMC_BASE;
+        case RSET_DDR:
+                return BCM_6345_DDR_BASE;
+        }
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6348
-        __GEN_RSET(6348)
+        switch (set) {
+        case RSET_DSL_LMEM:
+                return BCM_6348_DSL_LMEM_BASE;
+        case RSET_PERF:
+                return BCM_6348_PERF_BASE;
+        case RSET_TIMER:
+                return BCM_6348_TIMER_BASE;
+        case RSET_WDT:
+                return BCM_6348_WDT_BASE;
+        case RSET_UART0:
+                return BCM_6348_UART0_BASE;
+        case RSET_UART1:
+                return BCM_6348_UART1_BASE;
+        case RSET_GPIO:
+                return BCM_6348_GPIO_BASE;
+        case RSET_SPI:
+                return BCM_6348_SPI_BASE;
+        case RSET_UDC0:
+                return BCM_6348_UDC0_BASE;
+        case RSET_OHCI0:
+                return BCM_6348_OHCI0_BASE;
+        case RSET_OHCI_PRIV:
+                return BCM_6348_OHCI_PRIV_BASE;
+        case RSET_USBH_PRIV:
+                return BCM_6348_USBH_PRIV_BASE;
+        case RSET_MPI:
+                return BCM_6348_MPI_BASE;
+        case RSET_PCMCIA:
+                return BCM_6348_PCMCIA_BASE;
+        case RSET_DSL:
+                return BCM_6348_DSL_BASE;
+        case RSET_ENET0:
+                return BCM_6348_ENET0_BASE;
+        case RSET_ENET1:
+                return BCM_6348_ENET1_BASE;
+        case RSET_ENETDMA:
+                return BCM_6348_ENETDMA_BASE;
+        case RSET_EHCI0:
+                return BCM_6348_EHCI0_BASE;
+        case RSET_SDRAM:
+                return BCM_6348_SDRAM_BASE;
+        case RSET_MEMC:
+                return BCM_6348_MEMC_BASE;
+        case RSET_DDR:
+                return BCM_6348_DDR_BASE;
+        }
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6358
-        __GEN_RSET(6358)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6368
-        __GEN_RSET(6368)
+        switch (set) {
+        case RSET_DSL_LMEM:
+                return BCM_6358_DSL_LMEM_BASE;
+        case RSET_PERF:
+                return BCM_6358_PERF_BASE;
+        case RSET_TIMER:
+                return BCM_6358_TIMER_BASE;
+        case RSET_WDT:
+                return BCM_6358_WDT_BASE;
+        case RSET_UART0:
+                return BCM_6358_UART0_BASE;
+        case RSET_UART1:
+                return BCM_6358_UART1_BASE;
+        case RSET_GPIO:
+                return BCM_6358_GPIO_BASE;
+        case RSET_SPI:
+                return BCM_6358_SPI_BASE;
+        case RSET_UDC0:
+                return BCM_6358_UDC0_BASE;
+        case RSET_OHCI0:
+                return BCM_6358_OHCI0_BASE;
+        case RSET_OHCI_PRIV:
+                return BCM_6358_OHCI_PRIV_BASE;
+        case RSET_USBH_PRIV:
+                return BCM_6358_USBH_PRIV_BASE;
+        case RSET_MPI:
+                return BCM_6358_MPI_BASE;
+        case RSET_PCMCIA:
+                return BCM_6358_PCMCIA_BASE;
+        case RSET_ENET0:
+                return BCM_6358_ENET0_BASE;
+        case RSET_ENET1:
+                return BCM_6358_ENET1_BASE;
+        case RSET_ENETDMA:
+                return BCM_6358_ENETDMA_BASE;
+        case RSET_DSL:
+                return BCM_6358_DSL_BASE;
+        case RSET_EHCI0:
+                return BCM_6358_EHCI0_BASE;
+        case RSET_SDRAM:
+                return BCM_6358_SDRAM_BASE;
+        case RSET_MEMC:
+                return BCM_6358_MEMC_BASE;
+        case RSET_DDR:
+                return BCM_6358_DDR_BASE;
+        }
 #endif
 #endif
         /* unreached */
@@ -577,7 +441,6 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
  */
 enum bcm63xx_irq {
         IRQ_TIMER = 0,
-        IRQ_SPI,
         IRQ_UART0,
         IRQ_UART1,
         IRQ_DSL,
@@ -586,326 +449,97 @@ enum bcm63xx_irq {
         IRQ_ENET_PHY,
         IRQ_OHCI0,
         IRQ_EHCI0,
-        IRQ_USBD,
-        IRQ_USBD_RXDMA0,
-        IRQ_USBD_TXDMA0,
-        IRQ_USBD_RXDMA1,
-        IRQ_USBD_TXDMA1,
-        IRQ_USBD_RXDMA2,
-        IRQ_USBD_TXDMA2,
+        IRQ_PCMCIA0,
         IRQ_ENET0_RXDMA,
         IRQ_ENET0_TXDMA,
         IRQ_ENET1_RXDMA,
         IRQ_ENET1_TXDMA,
         IRQ_PCI,
         IRQ_PCMCIA,
-        IRQ_ATM,
-        IRQ_ENETSW_RXDMA0,
-        IRQ_ENETSW_RXDMA1,
-        IRQ_ENETSW_RXDMA2,
-        IRQ_ENETSW_RXDMA3,
-        IRQ_ENETSW_TXDMA0,
-        IRQ_ENETSW_TXDMA1,
-        IRQ_ENETSW_TXDMA2,
-        IRQ_ENETSW_TXDMA3,
-        IRQ_XTM,
-        IRQ_XTM_DMA0,
 };
 
 /*
- * 6328 irqs
- */
-#define BCM_6328_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
-
-#define BCM_6328_TIMER_IRQ              (IRQ_INTERNAL_BASE + 31)
-#define BCM_6328_SPI_IRQ                0
-#define BCM_6328_UART0_IRQ              (IRQ_INTERNAL_BASE + 28)
-#define BCM_6328_UART1_IRQ              (BCM_6328_HIGH_IRQ_BASE + 7)
-#define BCM_6328_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
-#define BCM_6328_UDC0_IRQ               0
-#define BCM_6328_ENET0_IRQ              0
-#define BCM_6328_ENET1_IRQ              0
-#define BCM_6328_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
-#define BCM_6328_OHCI0_IRQ              (BCM_6328_HIGH_IRQ_BASE + 9)
-#define BCM_6328_EHCI0_IRQ              (BCM_6328_HIGH_IRQ_BASE + 10)
-#define BCM_6328_USBD_IRQ               (IRQ_INTERNAL_BASE + 4)
-#define BCM_6328_USBD_RXDMA0_IRQ        (IRQ_INTERNAL_BASE + 5)
-#define BCM_6328_USBD_TXDMA0_IRQ        (IRQ_INTERNAL_BASE + 6)
-#define BCM_6328_USBD_RXDMA1_IRQ        (IRQ_INTERNAL_BASE + 7)
-#define BCM_6328_USBD_TXDMA1_IRQ        (IRQ_INTERNAL_BASE + 8)
-#define BCM_6328_USBD_RXDMA2_IRQ        (IRQ_INTERNAL_BASE + 9)
-#define BCM_6328_USBD_TXDMA2_IRQ        (IRQ_INTERNAL_BASE + 10)
-#define BCM_6328_PCMCIA_IRQ             0
-#define BCM_6328_ENET0_RXDMA_IRQ        0
-#define BCM_6328_ENET0_TXDMA_IRQ        0
-#define BCM_6328_ENET1_RXDMA_IRQ        0
-#define BCM_6328_ENET1_TXDMA_IRQ        0
-#define BCM_6328_PCI_IRQ                (IRQ_INTERNAL_BASE + 23)
-#define BCM_6328_ATM_IRQ                0
-#define BCM_6328_ENETSW_RXDMA0_IRQ      (BCM_6328_HIGH_IRQ_BASE + 0)
-#define BCM_6328_ENETSW_RXDMA1_IRQ      (BCM_6328_HIGH_IRQ_BASE + 1)
-#define BCM_6328_ENETSW_RXDMA2_IRQ      (BCM_6328_HIGH_IRQ_BASE + 2)
-#define BCM_6328_ENETSW_RXDMA3_IRQ      (BCM_6328_HIGH_IRQ_BASE + 3)
-#define BCM_6328_ENETSW_TXDMA0_IRQ      0
-#define BCM_6328_ENETSW_TXDMA1_IRQ      0
-#define BCM_6328_ENETSW_TXDMA2_IRQ      0
-#define BCM_6328_ENETSW_TXDMA3_IRQ      0
-#define BCM_6328_XTM_IRQ                (BCM_6328_HIGH_IRQ_BASE + 31)
-#define BCM_6328_XTM_DMA0_IRQ           (BCM_6328_HIGH_IRQ_BASE + 11)
-
-#define BCM_6328_PCM_DMA0_IRQ           (IRQ_INTERNAL_BASE + 2)
-#define BCM_6328_PCM_DMA1_IRQ           (IRQ_INTERNAL_BASE + 3)
-#define BCM_6328_EXT_IRQ0               (IRQ_INTERNAL_BASE + 24)
-#define BCM_6328_EXT_IRQ1               (IRQ_INTERNAL_BASE + 25)
-#define BCM_6328_EXT_IRQ2               (IRQ_INTERNAL_BASE + 26)
-#define BCM_6328_EXT_IRQ3               (IRQ_INTERNAL_BASE + 27)
-
-/*
  * 6338 irqs
  */
 #define BCM_6338_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 #define BCM_6338_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 #define BCM_6338_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
-#define BCM_6338_UART1_IRQ              0
+#define BCM_6338_DG_IRQ                 (IRQ_INTERNAL_BASE + 4)
 #define BCM_6338_DSL_IRQ                (IRQ_INTERNAL_BASE + 5)
+#define BCM_6338_ATM_IRQ                (IRQ_INTERNAL_BASE + 6)
+#define BCM_6338_UDC0_IRQ               (IRQ_INTERNAL_BASE + 7)
 #define BCM_6338_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
-#define BCM_6338_ENET1_IRQ              0
 #define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
-#define BCM_6338_OHCI0_IRQ              0
-#define BCM_6338_EHCI0_IRQ              0
-#define BCM_6338_USBD_IRQ               0
-#define BCM_6338_USBD_RXDMA0_IRQ        0
-#define BCM_6338_USBD_TXDMA0_IRQ        0
-#define BCM_6338_USBD_RXDMA1_IRQ        0
-#define BCM_6338_USBD_TXDMA1_IRQ        0
-#define BCM_6338_USBD_RXDMA2_IRQ        0
-#define BCM_6338_USBD_TXDMA2_IRQ        0
+#define BCM_6338_SDRAM_IRQ              (IRQ_INTERNAL_BASE + 10)
+#define BCM_6338_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 11)
+#define BCM_6338_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 12)
+#define BCM_6338_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13)
+#define BCM_6338_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 14)
 #define BCM_6338_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 #define BCM_6338_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
-#define BCM_6338_ENET1_RXDMA_IRQ        0
-#define BCM_6338_ENET1_TXDMA_IRQ        0
-#define BCM_6338_PCI_IRQ                0
-#define BCM_6338_PCMCIA_IRQ             0
-#define BCM_6338_ATM_IRQ                0
-#define BCM_6338_ENETSW_RXDMA0_IRQ      0
-#define BCM_6338_ENETSW_RXDMA1_IRQ      0
-#define BCM_6338_ENETSW_RXDMA2_IRQ      0
-#define BCM_6338_ENETSW_RXDMA3_IRQ      0
-#define BCM_6338_ENETSW_TXDMA0_IRQ      0
-#define BCM_6338_ENETSW_TXDMA1_IRQ      0
-#define BCM_6338_ENETSW_TXDMA2_IRQ      0
-#define BCM_6338_ENETSW_TXDMA3_IRQ      0
-#define BCM_6338_XTM_IRQ                0
-#define BCM_6338_XTM_DMA0_IRQ           0
+#define BCM_6338_SDIO_IRQ               (IRQ_INTERNAL_BASE + 17)
 
 /*
  * 6345 irqs
  */
 #define BCM_6345_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
-#define BCM_6345_SPI_IRQ                0
 #define BCM_6345_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
-#define BCM_6345_UART1_IRQ              0
 #define BCM_6345_DSL_IRQ                (IRQ_INTERNAL_BASE + 3)
+#define BCM_6345_ATM_IRQ                (IRQ_INTERNAL_BASE + 4)
+#define BCM_6345_USB_IRQ                (IRQ_INTERNAL_BASE + 5)
 #define BCM_6345_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
-#define BCM_6345_ENET1_IRQ              0
 #define BCM_6345_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
-#define BCM_6345_OHCI0_IRQ              0
-#define BCM_6345_EHCI0_IRQ              0
-#define BCM_6345_USBD_IRQ               0
-#define BCM_6345_USBD_RXDMA0_IRQ        0
-#define BCM_6345_USBD_TXDMA0_IRQ        0
-#define BCM_6345_USBD_RXDMA1_IRQ        0
-#define BCM_6345_USBD_TXDMA1_IRQ        0
-#define BCM_6345_USBD_RXDMA2_IRQ        0
-#define BCM_6345_USBD_TXDMA2_IRQ        0
 #define BCM_6345_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 1)
 #define BCM_6345_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 2)
-#define BCM_6345_ENET1_RXDMA_IRQ        0
-#define BCM_6345_ENET1_TXDMA_IRQ        0
-#define BCM_6345_PCI_IRQ                0
-#define BCM_6345_PCMCIA_IRQ             0
-#define BCM_6345_ATM_IRQ                0
-#define BCM_6345_ENETSW_RXDMA0_IRQ      0
-#define BCM_6345_ENETSW_RXDMA1_IRQ      0
-#define BCM_6345_ENETSW_RXDMA2_IRQ      0
-#define BCM_6345_ENETSW_RXDMA3_IRQ      0
-#define BCM_6345_ENETSW_TXDMA0_IRQ      0
-#define BCM_6345_ENETSW_TXDMA1_IRQ      0
-#define BCM_6345_ENETSW_TXDMA2_IRQ      0
-#define BCM_6345_ENETSW_TXDMA3_IRQ      0
-#define BCM_6345_XTM_IRQ                0
-#define BCM_6345_XTM_DMA0_IRQ           0
+#define BCM_6345_EBI_RX_IRQ             (IRQ_INTERNAL_BASE + 13 + 5)
+#define BCM_6345_EBI_TX_IRQ             (IRQ_INTERNAL_BASE + 13 + 6)
+#define BCM_6345_RESERVED_RX_IRQ        (IRQ_INTERNAL_BASE + 13 + 9)
+#define BCM_6345_RESERVED_TX_IRQ        (IRQ_INTERNAL_BASE + 13 + 10)
+#define BCM_6345_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 13)
+#define BCM_6345_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 14)
+#define BCM_6345_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 15)
+#define BCM_6345_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 16)
+#define BCM_6345_USB_ISO_RX_DMA_IRQ     (IRQ_INTERNAL_BASE + 13 + 17)
+#define BCM_6345_USB_ISO_TX_DMA_IRQ     (IRQ_INTERNAL_BASE + 13 + 18)
 
 /*
  * 6348 irqs
  */
 #define BCM_6348_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
-#define BCM_6348_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 #define BCM_6348_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
-#define BCM_6348_UART1_IRQ              0
 #define BCM_6348_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
-#define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 #define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
+#define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 #define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 #define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
-#define BCM_6348_EHCI0_IRQ              0
-#define BCM_6348_USBD_IRQ               0
-#define BCM_6348_USBD_RXDMA0_IRQ        0
-#define BCM_6348_USBD_TXDMA0_IRQ        0
-#define BCM_6348_USBD_RXDMA1_IRQ        0
-#define BCM_6348_USBD_TXDMA1_IRQ        0
-#define BCM_6348_USBD_RXDMA2_IRQ        0
-#define BCM_6348_USBD_TXDMA2_IRQ        0
 #define BCM_6348_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 20)
 #define BCM_6348_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 21)
 #define BCM_6348_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 22)
 #define BCM_6348_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 23)
-#define BCM_6348_PCI_IRQ                (IRQ_INTERNAL_BASE + 24)
 #define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
-#define BCM_6348_ATM_IRQ                (IRQ_INTERNAL_BASE + 5)
-#define BCM_6348_ENETSW_RXDMA0_IRQ      0
-#define BCM_6348_ENETSW_RXDMA1_IRQ      0
-#define BCM_6348_ENETSW_RXDMA2_IRQ      0
-#define BCM_6348_ENETSW_RXDMA3_IRQ      0
-#define BCM_6348_ENETSW_TXDMA0_IRQ      0
-#define BCM_6348_ENETSW_TXDMA1_IRQ      0
-#define BCM_6348_ENETSW_TXDMA2_IRQ      0
-#define BCM_6348_ENETSW_TXDMA3_IRQ      0
-#define BCM_6348_XTM_IRQ                0
-#define BCM_6348_XTM_DMA0_IRQ           0
+#define BCM_6348_PCI_IRQ                (IRQ_INTERNAL_BASE + 24)
 
 /*
  * 6358 irqs
  */
 #define BCM_6358_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
-#define BCM_6358_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 #define BCM_6358_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 #define BCM_6358_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
-#define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
-#define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
+#define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 #define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
-#define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
-#define BCM_6358_USBD_IRQ               0
-#define BCM_6358_USBD_RXDMA0_IRQ        0
-#define BCM_6358_USBD_TXDMA0_IRQ        0
-#define BCM_6358_USBD_RXDMA1_IRQ        0
-#define BCM_6358_USBD_TXDMA1_IRQ        0
-#define BCM_6358_USBD_RXDMA2_IRQ        0
-#define BCM_6358_USBD_TXDMA2_IRQ        0
 #define BCM_6358_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 #define BCM_6358_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 #define BCM_6358_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
 #define BCM_6358_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
+#define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
 #define BCM_6358_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
 #define BCM_6358_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
-#define BCM_6358_ATM_IRQ                (IRQ_INTERNAL_BASE + 19)
-#define BCM_6358_ENETSW_RXDMA0_IRQ      0
-#define BCM_6358_ENETSW_RXDMA1_IRQ      0
-#define BCM_6358_ENETSW_RXDMA2_IRQ      0
-#define BCM_6358_ENETSW_RXDMA3_IRQ      0
-#define BCM_6358_ENETSW_TXDMA0_IRQ      0
-#define BCM_6358_ENETSW_TXDMA1_IRQ      0
-#define BCM_6358_ENETSW_TXDMA2_IRQ      0
-#define BCM_6358_ENETSW_TXDMA3_IRQ      0
-#define BCM_6358_XTM_IRQ                0
-#define BCM_6358_XTM_DMA0_IRQ           0
-
-#define BCM_6358_PCM_DMA0_IRQ           (IRQ_INTERNAL_BASE + 23)
-#define BCM_6358_PCM_DMA1_IRQ           (IRQ_INTERNAL_BASE + 24)
-#define BCM_6358_EXT_IRQ0               (IRQ_INTERNAL_BASE + 25)
-#define BCM_6358_EXT_IRQ1               (IRQ_INTERNAL_BASE + 26)
-#define BCM_6358_EXT_IRQ2               (IRQ_INTERNAL_BASE + 27)
-#define BCM_6358_EXT_IRQ3               (IRQ_INTERNAL_BASE + 28)
-
-/*
- * 6368 irqs
- */
-#define BCM_6368_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
-
-#define BCM_6368_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
-#define BCM_6368_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
-#define BCM_6368_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
-#define BCM_6368_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
-#define BCM_6368_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
-#define BCM_6368_ENET0_IRQ              0
-#define BCM_6368_ENET1_IRQ              0
-#define BCM_6368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 15)
-#define BCM_6368_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
-#define BCM_6368_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 7)
-#define BCM_6368_USBD_IRQ               (IRQ_INTERNAL_BASE + 8)
-#define BCM_6368_USBD_RXDMA0_IRQ        (IRQ_INTERNAL_BASE + 26)
-#define BCM_6368_USBD_TXDMA0_IRQ        (IRQ_INTERNAL_BASE + 27)
-#define BCM_6368_USBD_RXDMA1_IRQ        (IRQ_INTERNAL_BASE + 28)
-#define BCM_6368_USBD_TXDMA1_IRQ        (IRQ_INTERNAL_BASE + 29)
-#define BCM_6368_USBD_RXDMA2_IRQ        (IRQ_INTERNAL_BASE + 30)
-#define BCM_6368_USBD_TXDMA2_IRQ        (IRQ_INTERNAL_BASE + 31)
-#define BCM_6368_PCMCIA_IRQ             0
-#define BCM_6368_ENET0_RXDMA_IRQ        0
-#define BCM_6368_ENET0_TXDMA_IRQ        0
-#define BCM_6368_ENET1_RXDMA_IRQ        0
-#define BCM_6368_ENET1_TXDMA_IRQ        0
-#define BCM_6368_PCI_IRQ                (IRQ_INTERNAL_BASE + 13)
-#define BCM_6368_ATM_IRQ                0
-#define BCM_6368_ENETSW_RXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 0)
-#define BCM_6368_ENETSW_RXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 1)
-#define BCM_6368_ENETSW_RXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 2)
-#define BCM_6368_ENETSW_RXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 3)
-#define BCM_6368_ENETSW_TXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 4)
-#define BCM_6368_ENETSW_TXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 5)
-#define BCM_6368_ENETSW_TXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 6)
-#define BCM_6368_ENETSW_TXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 7)
-#define BCM_6368_XTM_IRQ                (IRQ_INTERNAL_BASE + 11)
-#define BCM_6368_XTM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 8)
-
-#define BCM_6368_PCM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 30)
-#define BCM_6368_PCM_DMA1_IRQ           (BCM_6368_HIGH_IRQ_BASE + 31)
-#define BCM_6368_EXT_IRQ0               (IRQ_INTERNAL_BASE + 20)
-#define BCM_6368_EXT_IRQ1               (IRQ_INTERNAL_BASE + 21)
-#define BCM_6368_EXT_IRQ2               (IRQ_INTERNAL_BASE + 22)
-#define BCM_6368_EXT_IRQ3               (IRQ_INTERNAL_BASE + 23)
-#define BCM_6368_EXT_IRQ4               (IRQ_INTERNAL_BASE + 24)
-#define BCM_6368_EXT_IRQ5               (IRQ_INTERNAL_BASE + 25)
 
 extern const int *bcm63xx_irqs;
 
-#define __GEN_CPU_IRQ_TABLE(__cpu)                                      \
-        [IRQ_TIMER]             = BCM_## __cpu ##_TIMER_IRQ,            \
-        [IRQ_SPI]               = BCM_## __cpu ##_SPI_IRQ,              \
-        [IRQ_UART0]             = BCM_## __cpu ##_UART0_IRQ,            \
-        [IRQ_UART1]             = BCM_## __cpu ##_UART1_IRQ,            \
-        [IRQ_DSL]               = BCM_## __cpu ##_DSL_IRQ,              \
-        [IRQ_ENET0]             = BCM_## __cpu ##_ENET0_IRQ,            \
-        [IRQ_ENET1]             = BCM_## __cpu ##_ENET1_IRQ,            \
-        [IRQ_ENET_PHY]          = BCM_## __cpu ##_ENET_PHY_IRQ,         \
-        [IRQ_OHCI0]             = BCM_## __cpu ##_OHCI0_IRQ,            \
-        [IRQ_EHCI0]             = BCM_## __cpu ##_EHCI0_IRQ,            \
-        [IRQ_USBD]              = BCM_## __cpu ##_USBD_IRQ,             \
-        [IRQ_USBD_RXDMA0]       = BCM_## __cpu ##_USBD_RXDMA0_IRQ,      \
-        [IRQ_USBD_TXDMA0]       = BCM_## __cpu ##_USBD_TXDMA0_IRQ,      \
-        [IRQ_USBD_RXDMA1]       = BCM_## __cpu ##_USBD_RXDMA1_IRQ,      \
-        [IRQ_USBD_TXDMA1]       = BCM_## __cpu ##_USBD_TXDMA1_IRQ,      \
-        [IRQ_USBD_RXDMA2]       = BCM_## __cpu ##_USBD_RXDMA2_IRQ,      \
-        [IRQ_USBD_TXDMA2]       = BCM_## __cpu ##_USBD_TXDMA2_IRQ,      \
-        [IRQ_ENET0_RXDMA]       = BCM_## __cpu ##_ENET0_RXDMA_IRQ,      \
-        [IRQ_ENET0_TXDMA]       = BCM_## __cpu ##_ENET0_TXDMA_IRQ,      \
-        [IRQ_ENET1_RXDMA]       = BCM_## __cpu ##_ENET1_RXDMA_IRQ,      \
-        [IRQ_ENET1_TXDMA]       = BCM_## __cpu ##_ENET1_TXDMA_IRQ,      \
-        [IRQ_PCI]               = BCM_## __cpu ##_PCI_IRQ,              \
-        [IRQ_PCMCIA]            = BCM_## __cpu ##_PCMCIA_IRQ,           \
-        [IRQ_ATM]               = BCM_## __cpu ##_ATM_IRQ,              \
-        [IRQ_ENETSW_RXDMA0]     = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ,    \
-        [IRQ_ENETSW_RXDMA1]     = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ,    \
-        [IRQ_ENETSW_RXDMA2]     = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ,    \
-        [IRQ_ENETSW_RXDMA3]     = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ,    \
-        [IRQ_ENETSW_TXDMA0]     = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ,    \
-        [IRQ_ENETSW_TXDMA1]     = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ,    \
-        [IRQ_ENETSW_TXDMA2]     = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ,    \
-        [IRQ_ENETSW_TXDMA3]     = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ,    \
-        [IRQ_XTM]               = BCM_## __cpu ##_XTM_IRQ,              \
-        [IRQ_XTM_DMA0]          = BCM_## __cpu ##_XTM_DMA0_IRQ,         \
-
 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 {
         return bcm63xx_irqs[irq];
@@ -916,8 +550,4 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
  */
 unsigned int bcm63xx_get_memory_size(void);
 
-void bcm63xx_machine_halt(void);
-
-void bcm63xx_machine_reboot(void);
-
 #endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
deleted file mode 100644
index 354b8481ec4..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __BCM63XX_FLASH_H
-#define __BCM63XX_FLASH_H
-
-enum {
-        BCM63XX_FLASH_TYPE_PARALLEL,
-        BCM63XX_FLASH_TYPE_SERIAL,
-        BCM63XX_FLASH_TYPE_NAND,
-};
-
-int __init bcm63xx_flash_register(void);
-
-#endif /* __BCM63XX_FLASH_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
deleted file mode 100644
index c9bae136260..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef BCM63XX_DEV_SPI_H
-#define BCM63XX_DEV_SPI_H
-
-#include <linux/types.h>
-#include <bcm63xx_io.h>
-#include <bcm63xx_regs.h>
-
-int __init bcm63xx_spi_register(void);
-
-struct bcm63xx_spi_pdata {
-        unsigned int    fifo_size;
-        unsigned int    msg_type_shift;
-        unsigned int    msg_ctl_width;
-        int             bus_num;
-        int             num_chipselect;
-        u32             speed_hz;
-};
-
-enum bcm63xx_regs_spi {
-        SPI_CMD,
-        SPI_INT_STATUS,
-        SPI_INT_MASK_ST,
-        SPI_INT_MASK,
-        SPI_ST,
-        SPI_CLK_CFG,
-        SPI_FILL_BYTE,
-        SPI_MSG_TAIL,
-        SPI_RX_TAIL,
-        SPI_MSG_CTL,
-        SPI_MSG_DATA,
-        SPI_RX_DATA,
-};
-
-#define __GEN_SPI_RSET_BASE(__cpu, __rset)                              \
-        case SPI_## __rset:                                             \
-                return SPI_## __cpu ##_## __rset;
-
-#define __GEN_SPI_RSET(__cpu)                                           \
-        switch (reg) {                                                  \
-        __GEN_SPI_RSET_BASE(__cpu, CMD)                                 \
-        __GEN_SPI_RSET_BASE(__cpu, INT_STATUS)                          \
-        __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST)                         \
-        __GEN_SPI_RSET_BASE(__cpu, INT_MASK)                            \
-        __GEN_SPI_RSET_BASE(__cpu, ST)                                  \
-        __GEN_SPI_RSET_BASE(__cpu, CLK_CFG)                             \
-        __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE)                           \
-        __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL)                            \
-        __GEN_SPI_RSET_BASE(__cpu, RX_TAIL)                             \
-        __GEN_SPI_RSET_BASE(__cpu, MSG_CTL)                             \
-        __GEN_SPI_RSET_BASE(__cpu, MSG_DATA)                            \
-        __GEN_SPI_RSET_BASE(__cpu, RX_DATA)                             \
-        }
-
-#define __GEN_SPI_REGS_TABLE(__cpu)                                     \
-        [SPI_CMD]               = SPI_## __cpu ##_CMD,                  \
-        [SPI_INT_STATUS]        = SPI_## __cpu ##_INT_STATUS,           \
-        [SPI_INT_MASK_ST]       = SPI_## __cpu ##_INT_MASK_ST,          \
-        [SPI_INT_MASK]          = SPI_## __cpu ##_INT_MASK,             \
-        [SPI_ST]                = SPI_## __cpu ##_ST,                   \
-        [SPI_CLK_CFG]           = SPI_## __cpu ##_CLK_CFG,              \
-        [SPI_FILL_BYTE]         = SPI_## __cpu ##_FILL_BYTE,            \
-        [SPI_MSG_TAIL]          = SPI_## __cpu ##_MSG_TAIL,             \
-        [SPI_RX_TAIL]           = SPI_## __cpu ##_RX_TAIL,              \
-        [SPI_MSG_CTL]           = SPI_## __cpu ##_MSG_CTL,              \
-        [SPI_MSG_DATA]          = SPI_## __cpu ##_MSG_DATA,             \
-        [SPI_RX_DATA]           = SPI_## __cpu ##_RX_DATA,
-
-static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
-{
-#ifdef BCMCPU_RUNTIME_DETECT
-        extern const unsigned long *bcm63xx_regs_spi;
-
-        return bcm63xx_regs_spi[reg];
-#else
-#ifdef CONFIG_BCM63XX_CPU_6338
-        __GEN_SPI_RSET(6338)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6348
-        __GEN_SPI_RSET(6348)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6358
-        __GEN_SPI_RSET(6358)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6368
-        __GEN_SPI_RSET(6368)
-#endif
-#endif
-        return 0;
-}
-
-#endif /* BCM63XX_DEV_SPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h
deleted file mode 100644
index 5d6d6986f40..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef BCM63XX_DEV_USB_USBD_H_
-#define BCM63XX_DEV_USB_USBD_H_
-
-/*
- * usb device platform data
- */
-struct bcm63xx_usbd_platform_data {
-        /* board can only support full speed (USB 1.1) */
-        int use_fullspeed;
-
-        /* 0-based port index, for chips with >1 USB PHY */
-        int port_no;
-};
-
-int bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd);
-
-#endif /* BCM63XX_DEV_USB_USBD_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 0a9891f7580..3999ec0aa7f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -2,23 +2,18 @@
 #define BCM63XX_GPIO_H
 
 #include <linux/init.h>
-#include <bcm63xx_cpu.h>
 
 int __init bcm63xx_gpio_init(void);
 
 static inline unsigned long bcm63xx_gpio_count(void)
 {
         switch (bcm63xx_get_cpu_id()) {
-        case BCM6328_CPU_ID:
-                return 32;
         case BCM6358_CPU_ID:
                 return 40;
         case BCM6338_CPU_ID:
                 return 8;
         case BCM6345_CPU_ID:
                 return 16;
-        case BCM6368_CPU_ID:
-                return 38;
         case BCM6348_CPU_ID:
         default:
                 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 03a54df5fb8..91180fac6ed 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -1,7 +1,7 @@
 #ifndef BCM63XX_IO_H_
 #define BCM63XX_IO_H_
 
-#include <asm/mach-bcm63xx/bcm63xx_cpu.h>
+#include "bcm63xx_cpu.h"
 
 /*
  * Physical memory map, RAM is mapped at 0x0.
@@ -40,10 +40,6 @@
 #define BCM_CB_MEM_END_PA               (BCM_CB_MEM_BASE_PA +           \
                                         BCM_CB_MEM_SIZE - 1)
 
-#define BCM_PCIE_MEM_BASE_PA            0x10f00000
-#define BCM_PCIE_MEM_SIZE               (16 * 1024 * 1024)
-#define BCM_PCIE_MEM_END_PA             (BCM_PCIE_MEM_BASE_PA +         \
-                                        BCM_PCIE_MEM_SIZE - 1)
 
 /*
  * Internal registers are accessed through KSEG3
@@ -53,11 +49,9 @@
 #define bcm_readb(a)    (*(volatile unsigned char *)    BCM_REGS_VA(a))
 #define bcm_readw(a)    (*(volatile unsigned short *)   BCM_REGS_VA(a))
 #define bcm_readl(a)    (*(volatile unsigned int *)     BCM_REGS_VA(a))
-#define bcm_readq(a)    (*(volatile u64 *)              BCM_REGS_VA(a))
 #define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
 #define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
 #define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
-#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
 
 /*
  * IO helpers to access register set for current CPU
@@ -89,15 +83,11 @@
 #define bcm_mpi_writel(v, o)    bcm_rset_writel(RSET_MPI, (v), (o))
 #define bcm_pcmcia_readl(o)     bcm_rset_readl(RSET_PCMCIA, (o))
 #define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
-#define bcm_pcie_readl(o)       bcm_rset_readl(RSET_PCIE, (o))
-#define bcm_pcie_writel(v, o)   bcm_rset_writel(RSET_PCIE, (v), (o))
 #define bcm_sdram_readl(o)      bcm_rset_readl(RSET_SDRAM, (o))
 #define bcm_sdram_writel(v, o)  bcm_rset_writel(RSET_SDRAM, (v), (o))
 #define bcm_memc_readl(o)       bcm_rset_readl(RSET_MEMC, (o))
 #define bcm_memc_writel(v, o)   bcm_rset_writel(RSET_MEMC, (v), (o))
 #define bcm_ddr_readl(o)        bcm_rset_readl(RSET_DDR, (o))
 #define bcm_ddr_writel(v, o)    bcm_rset_writel(RSET_DDR, (v), (o))
-#define bcm_misc_readl(o)       bcm_rset_readl(RSET_MISC, (o))
-#define bcm_misc_writel(v, o)   bcm_rset_writel(RSET_MISC, (v), (o))
 
 #endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
index 0c3074b871b..5f95577c821 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -3,11 +3,13 @@
 
 #include <bcm63xx_cpu.h>
 
+#define IRQ_MIPS_BASE                   0
 #define IRQ_INTERNAL_BASE               8
-#define IRQ_EXTERNAL_BASE               100
-#define IRQ_EXT_0                       (IRQ_EXTERNAL_BASE + 0)
-#define IRQ_EXT_1                       (IRQ_EXTERNAL_BASE + 1)
-#define IRQ_EXT_2                       (IRQ_EXTERNAL_BASE + 2)
-#define IRQ_EXT_3                       (IRQ_EXTERNAL_BASE + 3)
+
+#define IRQ_EXT_BASE                    (IRQ_MIPS_BASE + 3)
+#define IRQ_EXT_0                       (IRQ_EXT_BASE + 0)
+#define IRQ_EXT_1                       (IRQ_EXT_BASE + 1)
+#define IRQ_EXT_2                       (IRQ_EXT_BASE + 2)
+#define IRQ_EXT_3                       (IRQ_EXT_BASE + 3)
 
 #endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
deleted file mode 100644
index a5bbff31c89..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef BCM63XX_IUDMA_H_
-#define BCM63XX_IUDMA_H_
-
-#include <linux/types.h>
-
-/*
- * rx/tx dma descriptor
- */
-struct bcm_enet_desc {
-        u32 len_stat;
-        u32 address;
-};
-
-/* control */
-#define DMADESC_LENGTH_SHIFT    16
-#define DMADESC_LENGTH_MASK     (0xfff << DMADESC_LENGTH_SHIFT)
-#define DMADESC_OWNER_MASK      (1 << 15)
-#define DMADESC_EOP_MASK        (1 << 14)
-#define DMADESC_SOP_MASK        (1 << 13)
-#define DMADESC_ESOP_MASK       (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
-#define DMADESC_WRAP_MASK       (1 << 12)
-#define DMADESC_USB_NOZERO_MASK (1 << 1)
-#define DMADESC_USB_ZERO_MASK   (1 << 0)
-
-/* status */
-#define DMADESC_UNDER_MASK      (1 << 9)
-#define DMADESC_APPEND_CRC      (1 << 8)
-#define DMADESC_OVSIZE_MASK     (1 << 4)
-#define DMADESC_RXER_MASK       (1 << 2)
-#define DMADESC_CRC_MASK        (1 << 1)
-#define DMADESC_OV_MASK         (1 << 0)
-#define DMADESC_ERR_MASK        (DMADESC_UNDER_MASK | \
-                                DMADESC_OVSIZE_MASK | \
-                                DMADESC_RXER_MASK | \
-                                DMADESC_CRC_MASK | \
-                                DMADESC_OV_MASK)
-
-#endif /* ! BCM63XX_IUDMA_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
deleted file mode 100644
index 62d6a3b4d3b..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef BCM63XX_NVRAM_H
-#define BCM63XX_NVRAM_H
-
-#include <linux/types.h>
-
-/**
- * bcm63xx_nvram_init() - initializes nvram
- * @nvram:      address of the nvram data
- *
- * Initialized the local nvram copy from the target address and checks
- * its checksum.
- *
- * Returns 0 on success.
- */
-int __init bcm63xx_nvram_init(void *nvram);
-
-/**
- * bcm63xx_nvram_get_name() - returns the board name according to nvram
- *
- * Returns the board name field from nvram. Note that it might not be
- * null terminated if it is exactly 16 bytes long.
- */
-u8 *bcm63xx_nvram_get_name(void);
-
-/**
- * bcm63xx_nvram_get_mac_address() - register & return a new mac address
- * @mac:        pointer to array for allocated mac
- *
- * Registers and returns a mac address from the allocated macs from nvram.
- *
- * Returns 0 on success.
- */
-int bcm63xx_nvram_get_mac_address(u8 *mac);
-
-#endif /* BCM63XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index c3eeb90b480..0ed5230243c 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,30 +15,6 @@
 /* Clock Control register */
 #define PERF_CKCTL_REG                  0x4
 
-#define CKCTL_6328_PHYMIPS_EN           (1 << 0)
-#define CKCTL_6328_ADSL_QPROC_EN        (1 << 1)
-#define CKCTL_6328_ADSL_AFE_EN          (1 << 2)
-#define CKCTL_6328_ADSL_EN              (1 << 3)
-#define CKCTL_6328_MIPS_EN              (1 << 4)
-#define CKCTL_6328_SAR_EN               (1 << 5)
-#define CKCTL_6328_PCM_EN               (1 << 6)
-#define CKCTL_6328_USBD_EN              (1 << 7)
-#define CKCTL_6328_USBH_EN              (1 << 8)
-#define CKCTL_6328_HSSPI_EN             (1 << 9)
-#define CKCTL_6328_PCIE_EN              (1 << 10)
-#define CKCTL_6328_ROBOSW_EN            (1 << 11)
-
-#define CKCTL_6328_ALL_SAFE_EN          (CKCTL_6328_PHYMIPS_EN |        \
-                                        CKCTL_6328_ADSL_QPROC_EN |      \
-                                        CKCTL_6328_ADSL_AFE_EN |        \
-                                        CKCTL_6328_ADSL_EN |            \
-                                        CKCTL_6328_SAR_EN  |            \
-                                        CKCTL_6328_PCM_EN  |            \
-                                        CKCTL_6328_USBD_EN |            \
-                                        CKCTL_6328_USBH_EN |            \
-                                        CKCTL_6328_ROBOSW_EN |          \
-                                        CKCTL_6328_PCIE_EN)
-
 #define CKCTL_6338_ADSLPHY_EN           (1 << 0)
 #define CKCTL_6338_MPI_EN               (1 << 1)
 #define CKCTL_6338_DRAM_EN              (1 << 2)
@@ -53,18 +29,13 @@
                                         CKCTL_6338_SAR_EN |             \
                                         CKCTL_6338_SPI_EN)
 
-/* BCM6345 clock bits are shifted by 16 on the left, because of the test
- * control register which is 16-bits wide. That way we do not have any
- * specific BCM6345 code for handling clocks, and writing 0 to the test
- * control register is fine.
- */
-#define CKCTL_6345_CPU_EN               (1 << 16)
-#define CKCTL_6345_BUS_EN               (1 << 17)
-#define CKCTL_6345_EBI_EN               (1 << 18)
-#define CKCTL_6345_UART_EN              (1 << 19)
-#define CKCTL_6345_ADSLPHY_EN           (1 << 20)
-#define CKCTL_6345_ENET_EN              (1 << 23)
-#define CKCTL_6345_USBH_EN              (1 << 24)
+#define CKCTL_6345_CPU_EN               (1 << 0)
+#define CKCTL_6345_BUS_EN               (1 << 1)
+#define CKCTL_6345_EBI_EN               (1 << 2)
+#define CKCTL_6345_UART_EN              (1 << 3)
+#define CKCTL_6345_ADSLPHY_EN           (1 << 4)
+#define CKCTL_6345_ENET_EN              (1 << 7)
+#define CKCTL_6345_USBH_EN              (1 << 8)
 
 #define CKCTL_6345_ALL_SAFE_EN          (CKCTL_6345_ENET_EN |   \
                                         CKCTL_6345_USBH_EN |    \
@@ -112,104 +83,30 @@
                                         CKCTL_6358_USBSU_EN |           \
                                         CKCTL_6358_EPHY_EN)
 
-#define CKCTL_6368_VDSL_QPROC_EN        (1 << 2)
-#define CKCTL_6368_VDSL_AFE_EN          (1 << 3)
-#define CKCTL_6368_VDSL_BONDING_EN      (1 << 4)
-#define CKCTL_6368_VDSL_EN              (1 << 5)
-#define CKCTL_6368_PHYMIPS_EN           (1 << 6)
-#define CKCTL_6368_SWPKT_USB_EN         (1 << 7)
-#define CKCTL_6368_SWPKT_SAR_EN         (1 << 8)
-#define CKCTL_6368_SPI_EN               (1 << 9)
-#define CKCTL_6368_USBD_EN              (1 << 10)
-#define CKCTL_6368_SAR_EN               (1 << 11)
-#define CKCTL_6368_ROBOSW_EN            (1 << 12)
-#define CKCTL_6368_UTOPIA_EN            (1 << 13)
-#define CKCTL_6368_PCM_EN               (1 << 14)
-#define CKCTL_6368_USBH_EN              (1 << 15)
-#define CKCTL_6368_DISABLE_GLESS_EN     (1 << 16)
-#define CKCTL_6368_NAND_EN              (1 << 17)
-#define CKCTL_6368_IPSEC_EN             (1 << 18)
-
-#define CKCTL_6368_ALL_SAFE_EN          (CKCTL_6368_SWPKT_USB_EN |      \
-                                        CKCTL_6368_SWPKT_SAR_EN |       \
-                                        CKCTL_6368_SPI_EN |             \
-                                        CKCTL_6368_USBD_EN |            \
-                                        CKCTL_6368_SAR_EN |             \
-                                        CKCTL_6368_ROBOSW_EN |          \
-                                        CKCTL_6368_UTOPIA_EN |          \
-                                        CKCTL_6368_PCM_EN |             \
-                                        CKCTL_6368_USBH_EN |            \
-                                        CKCTL_6368_DISABLE_GLESS_EN |   \
-                                        CKCTL_6368_NAND_EN |            \
-                                        CKCTL_6368_IPSEC_EN)
-
 /* System PLL Control register  */
 #define PERF_SYS_PLL_CTL_REG            0x8
 #define SYS_PLL_SOFT_RESET              0x1
 
 /* Interrupt Mask register */
-#define PERF_IRQMASK_6328_REG           0x20
-#define PERF_IRQMASK_6338_REG           0xc
-#define PERF_IRQMASK_6345_REG           0xc
-#define PERF_IRQMASK_6348_REG           0xc
-#define PERF_IRQMASK_6358_REG           0xc
-#define PERF_IRQMASK_6368_REG           0x20
+#define PERF_IRQMASK_REG                0xc
 
 /* Interrupt Status register */
-#define PERF_IRQSTAT_6328_REG           0x28
-#define PERF_IRQSTAT_6338_REG           0x10
-#define PERF_IRQSTAT_6345_REG           0x10
-#define PERF_IRQSTAT_6348_REG           0x10
-#define PERF_IRQSTAT_6358_REG           0x10
-#define PERF_IRQSTAT_6368_REG           0x28
+#define PERF_IRQSTAT_REG                0x10
 
 /* External Interrupt Configuration register */
-#define PERF_EXTIRQ_CFG_REG_6328        0x18
-#define PERF_EXTIRQ_CFG_REG_6338        0x14
-#define PERF_EXTIRQ_CFG_REG_6345        0x14
-#define PERF_EXTIRQ_CFG_REG_6348        0x14
-#define PERF_EXTIRQ_CFG_REG_6358        0x14
-#define PERF_EXTIRQ_CFG_REG_6368        0x18
-
-#define PERF_EXTIRQ_CFG_REG2_6368       0x1c
-
-/* for 6348 only */
-#define EXTIRQ_CFG_SENSE_6348(x)        (1 << (x))
-#define EXTIRQ_CFG_STAT_6348(x)         (1 << (x + 5))
-#define EXTIRQ_CFG_CLEAR_6348(x)        (1 << (x + 10))
-#define EXTIRQ_CFG_MASK_6348(x)         (1 << (x + 15))
-#define EXTIRQ_CFG_BOTHEDGE_6348(x)     (1 << (x + 20))
-#define EXTIRQ_CFG_LEVELSENSE_6348(x)   (1 << (x + 25))
-#define EXTIRQ_CFG_CLEAR_ALL_6348       (0xf << 10)
-#define EXTIRQ_CFG_MASK_ALL_6348        (0xf << 15)
-
-/* for all others */
+#define PERF_EXTIRQ_CFG_REG             0x14
 #define EXTIRQ_CFG_SENSE(x)             (1 << (x))
-#define EXTIRQ_CFG_STAT(x)              (1 << (x + 4))
-#define EXTIRQ_CFG_CLEAR(x)             (1 << (x + 8))
-#define EXTIRQ_CFG_MASK(x)              (1 << (x + 12))
-#define EXTIRQ_CFG_BOTHEDGE(x)          (1 << (x + 16))
-#define EXTIRQ_CFG_LEVELSENSE(x)        (1 << (x + 20))
-#define EXTIRQ_CFG_CLEAR_ALL            (0xf << 8)
-#define EXTIRQ_CFG_MASK_ALL             (0xf << 12)
+#define EXTIRQ_CFG_STAT(x)              (1 << (x + 5))
+#define EXTIRQ_CFG_CLEAR(x)             (1 << (x + 10))
+#define EXTIRQ_CFG_MASK(x)              (1 << (x + 15))
+#define EXTIRQ_CFG_BOTHEDGE(x)          (1 << (x + 20))
+#define EXTIRQ_CFG_LEVELSENSE(x)        (1 << (x + 25))
+
+#define EXTIRQ_CFG_CLEAR_ALL            (0xf << 10)
+#define EXTIRQ_CFG_MASK_ALL             (0xf << 15)
 
 /* Soft Reset register */
 #define PERF_SOFTRESET_REG              0x28
-#define PERF_SOFTRESET_6328_REG         0x10
-#define PERF_SOFTRESET_6358_REG         0x34
-#define PERF_SOFTRESET_6368_REG         0x10
-
-#define SOFTRESET_6328_SPI_MASK         (1 << 0)
-#define SOFTRESET_6328_EPHY_MASK        (1 << 1)
-#define SOFTRESET_6328_SAR_MASK         (1 << 2)
-#define SOFTRESET_6328_ENETSW_MASK      (1 << 3)
-#define SOFTRESET_6328_USBS_MASK        (1 << 4)
-#define SOFTRESET_6328_USBH_MASK        (1 << 5)
-#define SOFTRESET_6328_PCM_MASK         (1 << 6)
-#define SOFTRESET_6328_PCIE_CORE_MASK   (1 << 7)
-#define SOFTRESET_6328_PCIE_MASK        (1 << 8)
-#define SOFTRESET_6328_PCIE_EXT_MASK    (1 << 9)
-#define SOFTRESET_6328_PCIE_HARD_MASK   (1 << 10)
 
 #define SOFTRESET_6338_SPI_MASK         (1 << 0)
 #define SOFTRESET_6338_ENET_MASK        (1 << 2)
@@ -250,24 +147,6 @@
                                   SOFTRESET_6348_ACLC_MASK |            \
                                   SOFTRESET_6348_ADSLMIPSPLL_MASK)
 
-#define SOFTRESET_6358_SPI_MASK         (1 << 0)
-#define SOFTRESET_6358_ENET_MASK        (1 << 2)
-#define SOFTRESET_6358_MPI_MASK         (1 << 3)
-#define SOFTRESET_6358_EPHY_MASK        (1 << 6)
-#define SOFTRESET_6358_SAR_MASK         (1 << 7)
-#define SOFTRESET_6358_USBH_MASK        (1 << 12)
-#define SOFTRESET_6358_PCM_MASK         (1 << 13)
-#define SOFTRESET_6358_ADSL_MASK        (1 << 14)
-
-#define SOFTRESET_6368_SPI_MASK         (1 << 0)
-#define SOFTRESET_6368_MPI_MASK         (1 << 3)
-#define SOFTRESET_6368_EPHY_MASK        (1 << 6)
-#define SOFTRESET_6368_SAR_MASK         (1 << 7)
-#define SOFTRESET_6368_ENETSW_MASK      (1 << 10)
-#define SOFTRESET_6368_USBS_MASK        (1 << 11)
-#define SOFTRESET_6368_USBH_MASK        (1 << 12)
-#define SOFTRESET_6368_PCM_MASK         (1 << 13)
-
 /* MIPS PLL control register */
 #define PERF_MIPSPLLCTL_REG             0x34
 #define MIPSPLLCTL_N1_SHIFT             20
@@ -363,8 +242,6 @@
 /* Watchdog reset length register */
 #define WDT_RSTLEN_REG                  0x8
 
-/* Watchdog soft reset register (BCM6328 only) */
-#define WDT_SOFTRESET_REG               0xc
 
 /*************************************************************************
  * _REG relative to RSET_UARTx
@@ -495,7 +372,6 @@
 #define GPIO_CTL_LO_REG                 0x4
 #define GPIO_DATA_HI_REG                0x8
 #define GPIO_DATA_LO_REG                0xC
-#define GPIO_DATA_LO_REG_6345           0x8
 
 /* GPIO mux registers and constants */
 #define GPIO_MODE_REG                   0x18
@@ -526,59 +402,6 @@
 #define GPIO_MODE_6358_SERIAL_LED       (1 << 10)
 #define GPIO_MODE_6358_UTOPIA           (1 << 12)
 
-#define GPIO_MODE_6368_ANALOG_AFE_0     (1 << 0)
-#define GPIO_MODE_6368_ANALOG_AFE_1     (1 << 1)
-#define GPIO_MODE_6368_SYS_IRQ          (1 << 2)
-#define GPIO_MODE_6368_SERIAL_LED_DATA  (1 << 3)
-#define GPIO_MODE_6368_SERIAL_LED_CLK   (1 << 4)
-#define GPIO_MODE_6368_INET_LED         (1 << 5)
-#define GPIO_MODE_6368_EPHY0_LED        (1 << 6)
-#define GPIO_MODE_6368_EPHY1_LED        (1 << 7)
-#define GPIO_MODE_6368_EPHY2_LED        (1 << 8)
-#define GPIO_MODE_6368_EPHY3_LED        (1 << 9)
-#define GPIO_MODE_6368_ROBOSW_LED_DAT   (1 << 10)
-#define GPIO_MODE_6368_ROBOSW_LED_CLK   (1 << 11)
-#define GPIO_MODE_6368_ROBOSW_LED0      (1 << 12)
-#define GPIO_MODE_6368_ROBOSW_LED1      (1 << 13)
-#define GPIO_MODE_6368_USBD_LED         (1 << 14)
-#define GPIO_MODE_6368_NTR_PULSE        (1 << 15)
-#define GPIO_MODE_6368_PCI_REQ1         (1 << 16)
-#define GPIO_MODE_6368_PCI_GNT1         (1 << 17)
-#define GPIO_MODE_6368_PCI_INTB         (1 << 18)
-#define GPIO_MODE_6368_PCI_REQ0         (1 << 19)
-#define GPIO_MODE_6368_PCI_GNT0         (1 << 20)
-#define GPIO_MODE_6368_PCMCIA_CD1       (1 << 22)
-#define GPIO_MODE_6368_PCMCIA_CD2       (1 << 23)
-#define GPIO_MODE_6368_PCMCIA_VS1       (1 << 24)
-#define GPIO_MODE_6368_PCMCIA_VS2       (1 << 25)
-#define GPIO_MODE_6368_EBI_CS2          (1 << 26)
-#define GPIO_MODE_6368_EBI_CS3          (1 << 27)
-#define GPIO_MODE_6368_SPI_SSN2         (1 << 28)
-#define GPIO_MODE_6368_SPI_SSN3         (1 << 29)
-#define GPIO_MODE_6368_SPI_SSN4         (1 << 30)
-#define GPIO_MODE_6368_SPI_SSN5         (1 << 31)
-
-
-#define GPIO_PINMUX_OTHR_REG            0x24
-#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
-#define GPIO_PINMUX_OTHR_6328_USB_MASK  (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
-#define GPIO_PINMUX_OTHR_6328_USB_HOST  (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
-#define GPIO_PINMUX_OTHR_6328_USB_DEV   (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
-
-#define GPIO_BASEMODE_6368_REG          0x38
-#define GPIO_BASEMODE_6368_UART2        0x1
-#define GPIO_BASEMODE_6368_GPIO         0x0
-#define GPIO_BASEMODE_6368_MASK         0x7
-/* those bits must be kept as read in gpio basemode register*/
-
-#define GPIO_STRAPBUS_REG               0x40
-#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
-#define STRAPBUS_6358_BOOT_SEL_SERIAL   (0 << 1)
-#define STRAPBUS_6368_BOOT_SEL_MASK     0x3
-#define STRAPBUS_6368_BOOT_SEL_NAND     0
-#define STRAPBUS_6368_BOOT_SEL_SERIAL   1
-#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
-
 
 /*************************************************************************
  * _REG relative to RSET_ENET
@@ -692,12 +515,6 @@
 #define ENETDMA_BUFALLOC_FORCE_SHIFT    31
 #define ENETDMA_BUFALLOC_FORCE_MASK     (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
 
-/* Global interrupt status */
-#define ENETDMA_GLB_IRQSTAT_REG         (0x40)
-
-/* Global interrupt mask */
-#define ENETDMA_GLB_IRQMASK_REG         (0x44)
-
 /* Channel Configuration register */
 #define ENETDMA_CHANCFG_REG(x)          (0x100 + (x) * 0x10)
 #define ENETDMA_CHANCFG_EN_SHIFT        0
@@ -731,58 +548,6 @@
 
 
 /*************************************************************************
- * _REG relative to RSET_ENETDMAC
- *************************************************************************/
-
-/* Channel Configuration register */
-#define ENETDMAC_CHANCFG_REG(x)         ((x) * 0x10)
-#define ENETDMAC_CHANCFG_EN_SHIFT       0
-#define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMAC_CHANCFG_EN_SHIFT)
-#define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
-#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
-#define ENETDMAC_CHANCFG_BUFHALT_SHIFT  2
-#define ENETDMAC_CHANCFG_BUFHALT_MASK   (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
-
-/* Interrupt Control/Status register */
-#define ENETDMAC_IR_REG(x)              (0x4 + (x) * 0x10)
-#define ENETDMAC_IR_BUFDONE_MASK        (1 << 0)
-#define ENETDMAC_IR_PKTDONE_MASK        (1 << 1)
-#define ENETDMAC_IR_NOTOWNER_MASK       (1 << 2)
-
-/* Interrupt Mask register */
-#define ENETDMAC_IRMASK_REG(x)          (0x8 + (x) * 0x10)
-
-/* Maximum Burst Length */
-#define ENETDMAC_MAXBURST_REG(x)        (0xc + (x) * 0x10)
-
-
-/*************************************************************************
- * _REG relative to RSET_ENETDMAS
- *************************************************************************/
-
-/* Ring Start Address register */
-#define ENETDMAS_RSTART_REG(x)          ((x) * 0x10)
-
-/* State Ram Word 2 */
-#define ENETDMAS_SRAM2_REG(x)           (0x4 + (x) * 0x10)
-
-/* State Ram Word 3 */
-#define ENETDMAS_SRAM3_REG(x)           (0x8 + (x) * 0x10)
-
-/* State Ram Word 4 */
-#define ENETDMAS_SRAM4_REG(x)           (0xc + (x) * 0x10)
-
-
-/*************************************************************************
- * _REG relative to RSET_ENETSW
- *************************************************************************/
-
-/* MIB register */
-#define ENETSW_MIB_REG(x)               (0x2800 + (x) * 4)
-#define ENETSW_MIB_REG_COUNT            47
-
-
-/*************************************************************************
  * _REG relative to RSET_OHCI_PRIV
  *************************************************************************/
 
@@ -797,11 +562,7 @@
  * _REG relative to RSET_USBH_PRIV
  *************************************************************************/
 
-#define USBH_PRIV_SWAP_6358_REG         0x0
-#define USBH_PRIV_SWAP_6368_REG         0x1c
-
-#define USBH_PRIV_SWAP_USBD_SHIFT       6
-#define USBH_PRIV_SWAP_USBD_MASK        (1 << USBH_PRIV_SWAP_USBD_SHIFT)
+#define USBH_PRIV_SWAP_REG              0x0
 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT  4
 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT  3
@@ -811,160 +572,7 @@
 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT  0
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
-#define USBH_PRIV_UTMI_CTL_6368_REG     0x10
-#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
-#define USBH_PRIV_UTMI_CTL_NODRIV_MASK  (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
-#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT  0
-#define USBH_PRIV_UTMI_CTL_HOSTB_MASK   (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
-
-#define USBH_PRIV_TEST_6358_REG         0x24
-#define USBH_PRIV_TEST_6368_REG         0x14
-
-#define USBH_PRIV_SETUP_6368_REG        0x28
-#define USBH_PRIV_SETUP_IOC_SHIFT       4
-#define USBH_PRIV_SETUP_IOC_MASK        (1 << USBH_PRIV_SETUP_IOC_SHIFT)
-
-
-/*************************************************************************
- * _REG relative to RSET_USBD
- *************************************************************************/
-
-/* General control */
-#define USBD_CONTROL_REG                0x00
-#define USBD_CONTROL_TXZLENINS_SHIFT    14
-#define USBD_CONTROL_TXZLENINS_MASK     (1 << USBD_CONTROL_TXZLENINS_SHIFT)
-#define USBD_CONTROL_AUTO_CSRS_SHIFT    13
-#define USBD_CONTROL_AUTO_CSRS_MASK     (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
-#define USBD_CONTROL_RXZSCFG_SHIFT      12
-#define USBD_CONTROL_RXZSCFG_MASK       (1 << USBD_CONTROL_RXZSCFG_SHIFT)
-#define USBD_CONTROL_INIT_SEL_SHIFT     8
-#define USBD_CONTROL_INIT_SEL_MASK      (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
-#define USBD_CONTROL_FIFO_RESET_SHIFT   6
-#define USBD_CONTROL_FIFO_RESET_MASK    (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
-#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
-#define USBD_CONTROL_SETUPERRLOCK_MASK  (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
-#define USBD_CONTROL_DONE_CSRS_SHIFT    0
-#define USBD_CONTROL_DONE_CSRS_MASK     (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
-
-/* Strap options */
-#define USBD_STRAPS_REG                 0x04
-#define USBD_STRAPS_APP_SELF_PWR_SHIFT  10
-#define USBD_STRAPS_APP_SELF_PWR_MASK   (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
-#define USBD_STRAPS_APP_DISCON_SHIFT    9
-#define USBD_STRAPS_APP_DISCON_MASK     (1 << USBD_STRAPS_APP_DISCON_SHIFT)
-#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
-#define USBD_STRAPS_APP_CSRPRGSUP_MASK  (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
-#define USBD_STRAPS_APP_RMTWKUP_SHIFT   6
-#define USBD_STRAPS_APP_RMTWKUP_MASK    (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
-#define USBD_STRAPS_APP_RAM_IF_SHIFT    7
-#define USBD_STRAPS_APP_RAM_IF_MASK     (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
-#define USBD_STRAPS_APP_8BITPHY_SHIFT   2
-#define USBD_STRAPS_APP_8BITPHY_MASK    (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
-#define USBD_STRAPS_SPEED_SHIFT         0
-#define USBD_STRAPS_SPEED_MASK          (3 << USBD_STRAPS_SPEED_SHIFT)
-
-/* Stall control */
-#define USBD_STALL_REG                  0x08
-#define USBD_STALL_UPDATE_SHIFT         7
-#define USBD_STALL_UPDATE_MASK          (1 << USBD_STALL_UPDATE_SHIFT)
-#define USBD_STALL_ENABLE_SHIFT         6
-#define USBD_STALL_ENABLE_MASK          (1 << USBD_STALL_ENABLE_SHIFT)
-#define USBD_STALL_EPNUM_SHIFT          0
-#define USBD_STALL_EPNUM_MASK           (0xf << USBD_STALL_EPNUM_SHIFT)
-
-/* General status */
-#define USBD_STATUS_REG                 0x0c
-#define USBD_STATUS_SOF_SHIFT           16
-#define USBD_STATUS_SOF_MASK            (0x7ff << USBD_STATUS_SOF_SHIFT)
-#define USBD_STATUS_SPD_SHIFT           12
-#define USBD_STATUS_SPD_MASK            (3 << USBD_STATUS_SPD_SHIFT)
-#define USBD_STATUS_ALTINTF_SHIFT       8
-#define USBD_STATUS_ALTINTF_MASK        (0xf << USBD_STATUS_ALTINTF_SHIFT)
-#define USBD_STATUS_INTF_SHIFT          4
-#define USBD_STATUS_INTF_MASK           (0xf << USBD_STATUS_INTF_SHIFT)
-#define USBD_STATUS_CFG_SHIFT           0
-#define USBD_STATUS_CFG_MASK            (0xf << USBD_STATUS_CFG_SHIFT)
-
-/* Other events */
-#define USBD_EVENTS_REG                 0x10
-#define USBD_EVENTS_USB_LINK_SHIFT      10
-#define USBD_EVENTS_USB_LINK_MASK       (1 << USBD_EVENTS_USB_LINK_SHIFT)
-
-/* IRQ status */
-#define USBD_EVENT_IRQ_STATUS_REG       0x14
-
-/* IRQ level (2 bits per IRQ event) */
-#define USBD_EVENT_IRQ_CFG_HI_REG       0x18
-
-#define USBD_EVENT_IRQ_CFG_LO_REG       0x1c
-
-#define USBD_EVENT_IRQ_CFG_SHIFT(x)     ((x & 0xf) << 1)
-#define USBD_EVENT_IRQ_CFG_MASK(x)      (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
-#define USBD_EVENT_IRQ_CFG_RISING(x)    (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
-#define USBD_EVENT_IRQ_CFG_FALLING(x)   (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
-
-/* IRQ mask (1=unmasked) */
-#define USBD_EVENT_IRQ_MASK_REG         0x20
-
-/* IRQ bits */
-#define USBD_EVENT_IRQ_USB_LINK         10
-#define USBD_EVENT_IRQ_SETCFG           9
-#define USBD_EVENT_IRQ_SETINTF          8
-#define USBD_EVENT_IRQ_ERRATIC_ERR      7
-#define USBD_EVENT_IRQ_SET_CSRS         6
-#define USBD_EVENT_IRQ_SUSPEND          5
-#define USBD_EVENT_IRQ_EARLY_SUSPEND    4
-#define USBD_EVENT_IRQ_SOF              3
-#define USBD_EVENT_IRQ_ENUM_ON          2
-#define USBD_EVENT_IRQ_SETUP            1
-#define USBD_EVENT_IRQ_USB_RESET        0
-
-/* TX FIFO partitioning */
-#define USBD_TXFIFO_CONFIG_REG          0x40
-#define USBD_TXFIFO_CONFIG_END_SHIFT    16
-#define USBD_TXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
-#define USBD_TXFIFO_CONFIG_START_SHIFT  0
-#define USBD_TXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
-
-/* RX FIFO partitioning */
-#define USBD_RXFIFO_CONFIG_REG          0x44
-#define USBD_RXFIFO_CONFIG_END_SHIFT    16
-#define USBD_RXFIFO_CONFIG_END_MASK     (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
-#define USBD_RXFIFO_CONFIG_START_SHIFT  0
-#define USBD_RXFIFO_CONFIG_START_MASK   (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
-
-/* TX FIFO/endpoint configuration */
-#define USBD_TXFIFO_EPSIZE_REG          0x48
-
-/* RX FIFO/endpoint configuration */
-#define USBD_RXFIFO_EPSIZE_REG          0x4c
-
-/* Endpoint<->DMA mappings */
-#define USBD_EPNUM_TYPEMAP_REG          0x50
-#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT   8
-#define USBD_EPNUM_TYPEMAP_TYPE_MASK    (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
-#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
-#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK  (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
-
-/* Misc per-endpoint settings */
-#define USBD_CSR_SETUPADDR_REG          0x80
-#define USBD_CSR_SETUPADDR_DEF          0xb550
-
-#define USBD_CSR_EP_REG(x)              (0x84 + (x) * 4)
-#define USBD_CSR_EP_MAXPKT_SHIFT        19
-#define USBD_CSR_EP_MAXPKT_MASK         (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
-#define USBD_CSR_EP_ALTIFACE_SHIFT      15
-#define USBD_CSR_EP_ALTIFACE_MASK       (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
-#define USBD_CSR_EP_IFACE_SHIFT         11
-#define USBD_CSR_EP_IFACE_MASK          (0xf << USBD_CSR_EP_IFACE_SHIFT)
-#define USBD_CSR_EP_CFG_SHIFT           7
-#define USBD_CSR_EP_CFG_MASK            (0xf << USBD_CSR_EP_CFG_SHIFT)
-#define USBD_CSR_EP_TYPE_SHIFT          5
-#define USBD_CSR_EP_TYPE_MASK           (3 << USBD_CSR_EP_TYPE_SHIFT)
-#define USBD_CSR_EP_DIR_SHIFT           4
-#define USBD_CSR_EP_DIR_MASK            (1 << USBD_CSR_EP_DIR_SHIFT)
-#define USBD_CSR_EP_LOG_SHIFT           0
-#define USBD_CSR_EP_LOG_MASK            (0xf << USBD_CSR_EP_LOG_SHIFT)
+#define USBH_PRIV_TEST_REG              0x24
 
 
 /*************************************************************************
@@ -1126,8 +734,6 @@
 #define SDRAM_CFG_BANK_SHIFT            13
 #define SDRAM_CFG_BANK_MASK             (1 << SDRAM_CFG_BANK_SHIFT)
 
-#define SDRAM_MBASE_REG                 0xc
-
 #define SDRAM_PRIO_REG                  0x2C
 #define SDRAM_PRIO_MIPS_SHIFT           29
 #define SDRAM_PRIO_MIPS_MASK            (1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -1154,8 +760,6 @@
  * _REG relative to RSET_DDR
  *************************************************************************/
 
-#define DDR_CSEND_REG                   0x8
-
 #define DDR_DMIPSPLLCFG_REG             0x18
 #define DMIPSPLLCFG_M1_SHIFT            0
 #define DMIPSPLLCFG_M1_MASK             (0xff << DMIPSPLLCFG_M1_SHIFT)
@@ -1164,249 +768,4 @@
 #define DMIPSPLLCFG_N2_SHIFT            29
 #define DMIPSPLLCFG_N2_MASK             (0x7 << DMIPSPLLCFG_N2_SHIFT)
 
-#define DDR_DMIPSPLLCFG_6368_REG        0x20
-#define DMIPSPLLCFG_6368_P1_SHIFT       0
-#define DMIPSPLLCFG_6368_P1_MASK        (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
-#define DMIPSPLLCFG_6368_P2_SHIFT       4
-#define DMIPSPLLCFG_6368_P2_MASK        (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
-#define DMIPSPLLCFG_6368_NDIV_SHIFT     16
-#define DMIPSPLLCFG_6368_NDIV_MASK      (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
-
-#define DDR_DMIPSPLLDIV_6368_REG        0x24
-#define DMIPSPLLDIV_6368_MDIV_SHIFT     0
-#define DMIPSPLLDIV_6368_MDIV_MASK      (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
-
-
-/*************************************************************************
- * _REG relative to RSET_M2M
- *************************************************************************/
-
-#define M2M_RX                          0
-#define M2M_TX                          1
-
-#define M2M_SRC_REG(x)                  ((x) * 0x40 + 0x00)
-#define M2M_DST_REG(x)                  ((x) * 0x40 + 0x04)
-#define M2M_SIZE_REG(x)                 ((x) * 0x40 + 0x08)
-
-#define M2M_CTRL_REG(x)                 ((x) * 0x40 + 0x0c)
-#define M2M_CTRL_ENABLE_MASK            (1 << 0)
-#define M2M_CTRL_IRQEN_MASK             (1 << 1)
-#define M2M_CTRL_ERROR_CLR_MASK         (1 << 6)
-#define M2M_CTRL_DONE_CLR_MASK          (1 << 7)
-#define M2M_CTRL_NOINC_MASK             (1 << 8)
-#define M2M_CTRL_PCMCIASWAP_MASK        (1 << 9)
-#define M2M_CTRL_SWAPBYTE_MASK          (1 << 10)
-#define M2M_CTRL_ENDIAN_MASK            (1 << 11)
-
-#define M2M_STAT_REG(x)                 ((x) * 0x40 + 0x10)
-#define M2M_STAT_DONE                   (1 << 0)
-#define M2M_STAT_ERROR                  (1 << 1)
-
-#define M2M_SRCID_REG(x)                ((x) * 0x40 + 0x14)
-#define M2M_DSTID_REG(x)                ((x) * 0x40 + 0x18)
-
-/*************************************************************************
- * _REG relative to RSET_RNG
- *************************************************************************/
-
-#define RNG_CTRL                        0x00
-#define RNG_EN                          (1 << 0)
-
-#define RNG_STAT                        0x04
-#define RNG_AVAIL_MASK                  (0xff000000)
-
-#define RNG_DATA                        0x08
-#define RNG_THRES                       0x0c
-#define RNG_MASK                        0x10
-
-/*************************************************************************
- * _REG relative to RSET_SPI
- *************************************************************************/
-
-/* BCM 6338 SPI core */
-#define SPI_6338_CMD                    0x00    /* 16-bits register */
-#define SPI_6338_INT_STATUS             0x02
-#define SPI_6338_INT_MASK_ST            0x03
-#define SPI_6338_INT_MASK               0x04
-#define SPI_6338_ST                     0x05
-#define SPI_6338_CLK_CFG                0x06
-#define SPI_6338_FILL_BYTE              0x07
-#define SPI_6338_MSG_TAIL               0x09
-#define SPI_6338_RX_TAIL                0x0b
-#define SPI_6338_MSG_CTL                0x40    /* 8-bits register */
-#define SPI_6338_MSG_CTL_WIDTH          8
-#define SPI_6338_MSG_DATA               0x41
-#define SPI_6338_MSG_DATA_SIZE          0x3f
-#define SPI_6338_RX_DATA                0x80
-#define SPI_6338_RX_DATA_SIZE           0x3f
-
-/* BCM 6348 SPI core */
-#define SPI_6348_CMD                    0x00    /* 16-bits register */
-#define SPI_6348_INT_STATUS             0x02
-#define SPI_6348_INT_MASK_ST            0x03
-#define SPI_6348_INT_MASK               0x04
-#define SPI_6348_ST                     0x05
-#define SPI_6348_CLK_CFG                0x06
-#define SPI_6348_FILL_BYTE              0x07
-#define SPI_6348_MSG_TAIL               0x09
-#define SPI_6348_RX_TAIL                0x0b
-#define SPI_6348_MSG_CTL                0x40    /* 8-bits register */
-#define SPI_6348_MSG_CTL_WIDTH          8
-#define SPI_6348_MSG_DATA               0x41
-#define SPI_6348_MSG_DATA_SIZE          0x3f
-#define SPI_6348_RX_DATA                0x80
-#define SPI_6348_RX_DATA_SIZE           0x3f
-
-/* BCM 6358 SPI core */
-#define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
-#define SPI_6358_MSG_CTL_WIDTH          16
-#define SPI_6358_MSG_DATA               0x02
-#define SPI_6358_MSG_DATA_SIZE          0x21e
-#define SPI_6358_RX_DATA                0x400
-#define SPI_6358_RX_DATA_SIZE           0x220
-#define SPI_6358_CMD                    0x700   /* 16-bits register */
-#define SPI_6358_INT_STATUS             0x702
-#define SPI_6358_INT_MASK_ST            0x703
-#define SPI_6358_INT_MASK               0x704
-#define SPI_6358_ST                     0x705
-#define SPI_6358_CLK_CFG                0x706
-#define SPI_6358_FILL_BYTE              0x707
-#define SPI_6358_MSG_TAIL               0x709
-#define SPI_6358_RX_TAIL                0x70B
-
-/* BCM 6358 SPI core */
-#define SPI_6368_MSG_CTL                0x00    /* 16-bits register */
-#define SPI_6368_MSG_CTL_WIDTH          16
-#define SPI_6368_MSG_DATA               0x02
-#define SPI_6368_MSG_DATA_SIZE          0x21e
-#define SPI_6368_RX_DATA                0x400
-#define SPI_6368_RX_DATA_SIZE           0x220
-#define SPI_6368_CMD                    0x700   /* 16-bits register */
-#define SPI_6368_INT_STATUS             0x702
-#define SPI_6368_INT_MASK_ST            0x703
-#define SPI_6368_INT_MASK               0x704
-#define SPI_6368_ST                     0x705
-#define SPI_6368_CLK_CFG                0x706
-#define SPI_6368_FILL_BYTE              0x707
-#define SPI_6368_MSG_TAIL               0x709
-#define SPI_6368_RX_TAIL                0x70B
-
-/* Shared SPI definitions */
-
-/* Message configuration */
-#define SPI_FD_RW                       0x00
-#define SPI_HD_W                        0x01
-#define SPI_HD_R                        0x02
-#define SPI_BYTE_CNT_SHIFT              0
-#define SPI_6338_MSG_TYPE_SHIFT         6
-#define SPI_6348_MSG_TYPE_SHIFT         6
-#define SPI_6358_MSG_TYPE_SHIFT         14
-#define SPI_6368_MSG_TYPE_SHIFT         14
-
-/* Command */
-#define SPI_CMD_NOOP                    0x00
-#define SPI_CMD_SOFT_RESET              0x01
-#define SPI_CMD_HARD_RESET              0x02
-#define SPI_CMD_START_IMMEDIATE         0x03
-#define SPI_CMD_COMMAND_SHIFT           0
-#define SPI_CMD_COMMAND_MASK            0x000f
-#define SPI_CMD_DEVICE_ID_SHIFT         4
-#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
-#define SPI_CMD_ONE_BYTE_SHIFT          11
-#define SPI_CMD_ONE_WIRE_SHIFT          12
-#define SPI_DEV_ID_0                    0
-#define SPI_DEV_ID_1                    1
-#define SPI_DEV_ID_2                    2
-#define SPI_DEV_ID_3                    3
-
-/* Interrupt mask */
-#define SPI_INTR_CMD_DONE               0x01
-#define SPI_INTR_RX_OVERFLOW            0x02
-#define SPI_INTR_TX_UNDERFLOW           0x04
-#define SPI_INTR_TX_OVERFLOW            0x08
-#define SPI_INTR_RX_UNDERFLOW           0x10
-#define SPI_INTR_CLEAR_ALL              0x1f
-
-/* Status */
-#define SPI_RX_EMPTY                    0x02
-#define SPI_CMD_BUSY                    0x04
-#define SPI_SERIAL_BUSY                 0x08
-
-/* Clock configuration */
-#define SPI_CLK_20MHZ                   0x00
-#define SPI_CLK_0_391MHZ                0x01
-#define SPI_CLK_0_781MHZ                0x02 /* default */
-#define SPI_CLK_1_563MHZ                0x03
-#define SPI_CLK_3_125MHZ                0x04
-#define SPI_CLK_6_250MHZ                0x05
-#define SPI_CLK_12_50MHZ                0x06
-#define SPI_CLK_MASK                    0x07
-#define SPI_SSOFFTIME_MASK              0x38
-#define SPI_SSOFFTIME_SHIFT             3
-#define SPI_BYTE_SWAP                   0x80
-
-/*************************************************************************
- * _REG relative to RSET_MISC
- *************************************************************************/
-#define MISC_SERDES_CTRL_REG            0x0
-#define SERDES_PCIE_EN                  (1 << 0)
-#define SERDES_PCIE_EXD_EN              (1 << 15)
-
-#define MISC_STRAPBUS_6328_REG          0x240
-#define STRAPBUS_6328_FCVO_SHIFT        7
-#define STRAPBUS_6328_FCVO_MASK         (0x1f << STRAPBUS_6328_FCVO_SHIFT)
-#define STRAPBUS_6328_BOOT_SEL_SERIAL   (1 << 28)
-#define STRAPBUS_6328_BOOT_SEL_NAND     (0 << 28)
-
-/*************************************************************************
- * _REG relative to RSET_PCIE
- *************************************************************************/
-
-#define PCIE_CONFIG2_REG                0x408
-#define CONFIG2_BAR1_SIZE_EN            1
-#define CONFIG2_BAR1_SIZE_MASK          0xf
-
-#define PCIE_IDVAL3_REG                 0x43c
-#define IDVAL3_CLASS_CODE_MASK          0xffffff
-#define IDVAL3_SUBCLASS_SHIFT           8
-#define IDVAL3_CLASS_SHIFT              16
-
-#define PCIE_DLSTATUS_REG               0x1048
-#define DLSTATUS_PHYLINKUP              (1 << 13)
-
-#define PCIE_BRIDGE_OPT1_REG            0x2820
-#define OPT1_RD_BE_OPT_EN               (1 << 7)
-#define OPT1_RD_REPLY_BE_FIX_EN         (1 << 9)
-#define OPT1_PCIE_BRIDGE_HOLE_DET_EN    (1 << 11)
-#define OPT1_L1_INT_STATUS_MASK_POL     (1 << 12)
-
-#define PCIE_BRIDGE_OPT2_REG            0x2824
-#define OPT2_UBUS_UR_DECODE_DIS         (1 << 2)
-#define OPT2_TX_CREDIT_CHK_EN           (1 << 4)
-#define OPT2_CFG_TYPE1_BD_SEL           (1 << 7)
-#define OPT2_CFG_TYPE1_BUS_NO_SHIFT     16
-#define OPT2_CFG_TYPE1_BUS_NO_MASK      (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
-
-#define PCIE_BRIDGE_BAR0_BASEMASK_REG   0x2828
-#define PCIE_BRIDGE_BAR1_BASEMASK_REG   0x2830
-#define BASEMASK_REMAP_EN               (1 << 0)
-#define BASEMASK_SWAP_EN                (1 << 1)
-#define BASEMASK_MASK_SHIFT             4
-#define BASEMASK_MASK_MASK              (0xfff << BASEMASK_MASK_SHIFT)
-#define BASEMASK_BASE_SHIFT             20
-#define BASEMASK_BASE_MASK              (0xfff << BASEMASK_BASE_SHIFT)
-
-#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
-#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
-#define REBASE_ADDR_BASE_SHIFT          20
-#define REBASE_ADDR_BASE_MASK           (0xfff << REBASE_ADDR_BASE_SHIFT)
-
-#define PCIE_BRIDGE_RC_INT_MASK_REG     0x2854
-#define PCIE_RC_INT_A                   (1 << 0)
-#define PCIE_RC_INT_B                   (1 << 1)
-#define PCIE_RC_INT_C                   (1 << 2)
-#define PCIE_RC_INT_D                   (1 << 3)
-
-#define PCIE_DEVICE_OFFSET              0x8000
-
 #endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
deleted file mode 100644
index 3a6eb9c1adc..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __BCM63XX_RESET_H
-#define __BCM63XX_RESET_H
-
-enum bcm63xx_core_reset {
-        BCM63XX_RESET_SPI,
-        BCM63XX_RESET_ENET,
-        BCM63XX_RESET_USBH,
-        BCM63XX_RESET_USBD,
-        BCM63XX_RESET_SAR,
-        BCM63XX_RESET_DSL,
-        BCM63XX_RESET_EPHY,
-        BCM63XX_RESET_ENETSW,
-        BCM63XX_RESET_PCM,
-        BCM63XX_RESET_MPI,
-        BCM63XX_RESET_PCIE,
-        BCM63XX_RESET_PCIE_EXT,
-};
-
-void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
-
-#endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
index 1e6b587f62c..ed72e6a26b7 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
@@ -16,6 +16,7 @@
 #define TAGINFO1_LEN            30      /* Length of vendor information field1 in tag */
 #define FLASHLAYOUTVER_LEN      4       /* Length of Flash Layout Version String tag */
 #define TAGINFO2_LEN            16      /* Length of vendor information field2 in tag */
+#define CRC_LEN                 4       /* Length of CRC in bytes */
 #define ALTTAGINFO_LEN          54      /* Alternate length for vendor information; Pirelli */
 
 #define NUM_PIRELLI             2
@@ -76,19 +77,19 @@ struct bcm_tag {
         /* 192-195: Version flash layout */
         char flash_layout_ver[FLASHLAYOUTVER_LEN];
         /* 196-199: kernel+rootfs CRC32 */
-        __u32 fskernel_crc;
+        char fskernel_crc[CRC_LEN];
         /* 200-215: Unused except on Alice Gate where is is information */
         char information2[TAGINFO2_LEN];
         /* 216-219: CRC32 of image less imagetag (kernel for Alice Gate) */
-        __u32 image_crc;
+        char image_crc[CRC_LEN];
         /* 220-223: CRC32 of rootfs partition */
-        __u32 rootfs_crc;
+        char rootfs_crc[CRC_LEN];
         /* 224-227: CRC32 of kernel partition */
-        __u32 kernel_crc;
+        char kernel_crc[CRC_LEN];
         /* 228-235: Unused at present */
         char reserved1[8];
         /* 236-239: CRC32 of header excluding last 20 bytes */
-        __u32 header_crc;
+        char header_crc[CRC_LEN];
         /* 240-255: Unused at present */
         char reserved2[16];
 };
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index 682bcf3b492..474daaa5349 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -5,7 +5,6 @@
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <bcm63xx_dev_enet.h>
-#include <bcm63xx_dev_usb_usbd.h>
 #include <bcm63xx_dev_dsp.h>
 
 /*
@@ -15,6 +14,23 @@
 #define BCM963XX_NVRAM_OFFSET           0x580
 
 /*
+ * nvram structure
+ */
+struct bcm963xx_nvram {
+        u32     version;
+        u8      reserved1[256];
+        u8      name[16];
+        u32     main_tp_number;
+        u32     psi_size;
+        u32     mac_addr_count;
+        u8      mac_addr_base[6];
+        u8      reserved2[2];
+        u32     checksum_old;
+        u8      reserved3[720];
+        u32     checksum_high;
+};
+
+/*
  * board definition
  */
 struct board_info {
@@ -28,7 +44,6 @@ struct board_info {
         unsigned int    has_pccard:1;
         unsigned int    has_ohci0:1;
         unsigned int    has_ehci0:1;
-        unsigned int    has_usbd:1;
         unsigned int    has_dsp:1;
         unsigned int    has_uart0:1;
         unsigned int    has_uart1:1;
@@ -37,9 +52,6 @@ struct board_info {
         struct bcm63xx_enet_platform_data enet0;
         struct bcm63xx_enet_platform_data enet1;
 
-        /* USB config */
-        struct bcm63xx_usbd_platform_data usbd;
-
         /* DSP config */
         struct bcm63xx_dsp_platform_data dsp;
 
diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
index e9c408e8ff4..f453c01d067 100644
--- a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -37,7 +37,6 @@
 #define cpu_has_mips64r2                0
 
 #define cpu_has_dsp                     0
-#define cpu_has_dsp2                    0
 #define cpu_has_mipsmt                  0
 #define cpu_has_userlocal               0
 
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
deleted file mode 100644
index 30931c42379..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef BCM63XX_IOREMAP_H_
-#define BCM63XX_IOREMAP_H_
-
-#include <bcm63xx_cpu.h>
-
-static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-        return phys_addr;
-}
-
-static inline int is_bcm63xx_internal_registers(phys_t offset)
-{
-        switch (bcm63xx_get_cpu_id()) {
-        case BCM6338_CPU_ID:
-        case BCM6345_CPU_ID:
-        case BCM6348_CPU_ID:
-        case BCM6358_CPU_ID:
-                if (offset >= 0xfff00000)
-                        return 1;
-                break;
-        case BCM6328_CPU_ID:
-        case BCM6368_CPU_ID:
-                if (offset >= 0xb0000000 && offset < 0xb1000000)
-                        return 1;
-                break;
-        }
-        return 0;
-}
-
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
-                                         unsigned long flags)
-{
-        if (is_bcm63xx_internal_registers(offset))
-                return (void __iomem *)offset;
-        return NULL;
-}
-
-static inline int plat_iounmap(const volatile void __iomem *addr)
-{
-        return is_bcm63xx_internal_registers((unsigned long)addr);
-}
-
-#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
deleted file mode 100644
index 9332e788a5c..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/irq.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_BCM63XX_IRQ_H
-#define __ASM_MACH_BCM63XX_IRQ_H
-
-#define NR_IRQS 128
-#define MIPS_CPU_IRQ_BASE 0
-
-#endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
index 05ee8671bef..8e3f3fdf320 100644
--- a/arch/mips/include/asm/mach-bcm63xx/war.h
+++ b/arch/mips/include/asm/mach-bcm63xx/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 94ed063eec9..a58addb98cf 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -53,13 +53,12 @@
 #define cpu_has_mips64r2        1
 #define cpu_has_mips_r2_exec_hazard 0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_mipsmt          0
 #define cpu_has_vint            0
 #define cpu_has_veic            0
 #define cpu_hwrena_impl_bits    0xc0000000
 
-#define cpu_has_rixi            (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
+#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
 
 #define ARCH_HAS_IRQ_PER_CPU    1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 502bb1815ae..5b05f186e39 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -21,11 +21,14 @@ enum octeon_irq {
         OCTEON_IRQ_TIMER,
 /* sources in CIU_INTX_EN0 */
         OCTEON_IRQ_WORKQ0,
-        OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
-        OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
+        OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
+        OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
+        OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
+        OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
         OCTEON_IRQ_MBOX1,
-        OCTEON_IRQ_MBOX2,
-        OCTEON_IRQ_MBOX3,
+        OCTEON_IRQ_UART0,
+        OCTEON_IRQ_UART1,
+        OCTEON_IRQ_UART2,
         OCTEON_IRQ_PCI_INT0,
         OCTEON_IRQ_PCI_INT1,
         OCTEON_IRQ_PCI_INT2,
@@ -35,24 +38,64 @@ enum octeon_irq {
         OCTEON_IRQ_PCI_MSI2,
         OCTEON_IRQ_PCI_MSI3,
 
+        OCTEON_IRQ_TWSI,
+        OCTEON_IRQ_TWSI2,
         OCTEON_IRQ_RML,
+        OCTEON_IRQ_TRACE0,
+        OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
+        OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
+        OCTEON_IRQ_KEY_ZERO,
         OCTEON_IRQ_TIMER0,
         OCTEON_IRQ_TIMER1,
         OCTEON_IRQ_TIMER2,
         OCTEON_IRQ_TIMER3,
         OCTEON_IRQ_USB0,
         OCTEON_IRQ_USB1,
-#ifndef CONFIG_PCI_MSI
-        OCTEON_IRQ_LAST = 127
-#endif
+        OCTEON_IRQ_PCM,
+        OCTEON_IRQ_MPI,
+        OCTEON_IRQ_POWIQ,
+        OCTEON_IRQ_IPDPPTHR,
+        OCTEON_IRQ_MII0,
+        OCTEON_IRQ_MII1,
+        OCTEON_IRQ_BOOTDMA,
+
+        OCTEON_IRQ_NAND,
+        OCTEON_IRQ_MIO,         /* Summary of MIO_BOOT_ERR */
+        OCTEON_IRQ_IOB,         /* Summary of IOB_INT_SUM */
+        OCTEON_IRQ_FPA,         /* Summary of FPA_INT_SUM */
+        OCTEON_IRQ_POW,         /* Summary of POW_ECC_ERR */
+        OCTEON_IRQ_L2C,         /* Summary of L2C_INT_STAT */
+        OCTEON_IRQ_IPD,         /* Summary of IPD_INT_SUM */
+        OCTEON_IRQ_PIP,         /* Summary of PIP_INT_REG */
+        OCTEON_IRQ_PKO,         /* Summary of PKO_REG_ERROR */
+        OCTEON_IRQ_ZIP,         /* Summary of ZIP_ERROR */
+        OCTEON_IRQ_TIM,         /* Summary of TIM_REG_ERROR */
+        OCTEON_IRQ_RAD,         /* Summary of RAD_REG_ERROR */
+        OCTEON_IRQ_KEY,         /* Summary of KEY_INT_SUM */
+        OCTEON_IRQ_DFA,         /* Summary of DFA */
+        OCTEON_IRQ_USBCTL,      /* Summary of USBN0_INT_SUM */
+        OCTEON_IRQ_SLI,         /* Summary of SLI_INT_SUM */
+        OCTEON_IRQ_DPI,         /* Summary of DPI_INT_SUM */
+        OCTEON_IRQ_AGX0,        /* Summary of GMX0*+PCS0_INT*_REG */
+        OCTEON_IRQ_AGL  = OCTEON_IRQ_AGX0 + 5,
+        OCTEON_IRQ_PTP,
+        OCTEON_IRQ_PEM0,
+        OCTEON_IRQ_PEM1,
+        OCTEON_IRQ_SRIO0,
+        OCTEON_IRQ_SRIO1,
+        OCTEON_IRQ_LMC0,
+        OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4,           /* Summary of DFM */
+        OCTEON_IRQ_RST,
 };
 
 #ifdef CONFIG_PCI_MSI
-/* 256 - 511 represent the MSI interrupts 0-255 */
-#define OCTEON_IRQ_MSI_BIT0     (256)
+/* 152 - 407 represent the MSI interrupts 0-255 */
+#define OCTEON_IRQ_MSI_BIT0     (OCTEON_IRQ_RST + 1)
 
 #define OCTEON_IRQ_MSI_LAST      (OCTEON_IRQ_MSI_BIT0 + 255)
 #define OCTEON_IRQ_LAST          (OCTEON_IRQ_MSI_LAST + 1)
+#else
+#define OCTEON_IRQ_LAST         (OCTEON_IRQ_RST + 1)
 #endif
 
 #endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index eb72b35cf04..c4712d7cc81 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -18,6 +18,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
index babc8374e37..b3314cf5319 100644
--- a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
@@ -45,7 +45,6 @@
 #define cpu_has_ic_fills_f_dc   0
 #define cpu_icache_snoops_remote_store  0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_mipsmt          0
 #define cpu_has_userlocal       0
 
diff --git a/arch/mips/include/asm/mach-cobalt/war.h b/arch/mips/include/asm/mach-cobalt/war.h
index 34ae4046541..97884fd18ac 100644
--- a/arch/mips/include/asm/mach-cobalt/war.h
+++ b/arch/mips/include/asm/mach-cobalt/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 16f1cf5982b..618d2de02ed 100644
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -34,8 +34,6 @@
 #define PB1200_BCSR_PHYS_ADDR   0x0D800000
 #define PB1200_BCSR_HEXLED_OFS  0x00400000
 
-#define DB1300_BCSR_PHYS_ADDR   0x19800000
-#define DB1300_BCSR_HEXLED_OFS  0x00400000
 
 enum bcsr_id {
         /* BCSR base 1 */
@@ -107,7 +105,6 @@ enum bcsr_whoami_boards {
         BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
         BCSR_WHOAMI_PB1200_DDR2,
         BCSR_WHOAMI_DB1200,
-        BCSR_WHOAMI_DB1300,
 };
 
 /* STATUS reg.  Unless otherwise noted, they're valid on all boards.
@@ -121,12 +118,12 @@ enum bcsr_whoami_boards {
 #define BCSR_STATUS_SRAMWIDTH           0x0080
 #define BCSR_STATUS_FLASHBUSY           0x0100
 #define BCSR_STATUS_ROMBUSY             0x0400
-#define BCSR_STATUS_SD0WP               0x0400  /* DB1200/DB1300:SD1 */
+#define BCSR_STATUS_SD0WP               0x0400  /* DB1200 */
 #define BCSR_STATUS_SD1WP               0x0800
 #define BCSR_STATUS_USBOTGID            0x0800  /* PB/DB1550 */
 #define BCSR_STATUS_DB1000_SWAPBOOT     0x2000
-#define BCSR_STATUS_DB1200_SWAPBOOT     0x0040  /* DB1200/1300 */
-#define BCSR_STATUS_IDECBLID            0x0200  /* DB1200/1300 */
+#define BCSR_STATUS_DB1200_SWAPBOOT     0x0040  /* DB1200 */
+#define BCSR_STATUS_IDECBLID            0x0200  /* DB1200 */
 #define BCSR_STATUS_DB1200_U0RXD        0x1000  /* DB1200 */
 #define BCSR_STATUS_DB1200_U1RXD        0x2000  /* DB1200 */
 #define BCSR_STATUS_FLASHDEN            0xC000
@@ -136,11 +133,6 @@ enum bcsr_whoami_boards {
 #define BCSR_STATUS_PB1550_U1RXD        0x2000  /* PB1550 */
 #define BCSR_STATUS_PB1550_U3RXD        0x8000  /* PB1550 */
 
-#define BCSR_STATUS_CFWP                0x4000  /* DB1300 */
-#define BCSR_STATUS_USBOCn              0x2000  /* DB1300 */
-#define BCSR_STATUS_OTGOCn              0x1000  /* DB1300 */
-#define BCSR_STATUS_DCDMARQ             0x0010  /* DB1300 */
-#define BCSR_STATUS_IDEDMARQ            0x0020  /* DB1300 */
 
 /* DB/PB1000,1100,1500,1550 */
 #define BCSR_RESETS_PHY0                0x0001
@@ -162,20 +154,18 @@ enum bcsr_whoami_boards {
 #define BCSR_BOARD_PCIEXTARB            0x0200
 #define BCSR_BOARD_GPIO200RST           0x0400
 #define BCSR_BOARD_PCICLKOUT            0x0800
-#define BCSR_BOARD_PB1100_SD0PWR        0x0400
-#define BCSR_BOARD_PB1100_SD1PWR        0x0800
 #define BCSR_BOARD_PCICFG               0x1000
-#define BCSR_BOARD_SPISEL               0x2000  /* PB/DB1550 */
+#define BCSR_BOARD_SPISEL               0x4000  /* PB/DB1550 */
 #define BCSR_BOARD_SD0WP                0x4000  /* DB1100 */
 #define BCSR_BOARD_SD1WP                0x8000  /* DB1100 */
 
 
-/* DB/PB1200/1300 */
+/* DB/PB1200 */
 #define BCSR_RESETS_ETH                 0x0001
 #define BCSR_RESETS_CAMERA              0x0002
 #define BCSR_RESETS_DC                  0x0004
 #define BCSR_RESETS_IDE                 0x0008
-#define BCSR_RESETS_TV                  0x0010  /* DB1200/1300 */
+#define BCSR_RESETS_TV                  0x0010  /* DB1200 */
 /* Not resets but in the same register */
 #define BCSR_RESETS_PWMR1MUX            0x0800  /* DB1200 */
 #define BCSR_RESETS_PB1200_WSCFSM       0x0800  /* PB1200 */
@@ -184,22 +174,13 @@ enum bcsr_whoami_boards {
 #define BCSR_RESETS_SPISEL              0x4000
 #define BCSR_RESETS_SD1MUX              0x8000  /* PB1200 */
 
-#define BCSR_RESETS_VDDQSHDN            0x0200  /* DB1300 */
-#define BCSR_RESETS_OTPPGM              0x0400  /* DB1300 */
-#define BCSR_RESETS_OTPSCLK             0x0800  /* DB1300 */
-#define BCSR_RESETS_OTPWRPROT           0x1000  /* DB1300 */
-#define BCSR_RESETS_OTPCSB              0x2000  /* DB1300 */
-#define BCSR_RESETS_OTGPWR              0x4000  /* DB1300 */
-#define BCSR_RESETS_USBHPWR             0x8000  /* DB1300 */
-
 #define BCSR_BOARD_LCDVEE               0x0001
 #define BCSR_BOARD_LCDVDD               0x0002
 #define BCSR_BOARD_LCDBL                0x0004
 #define BCSR_BOARD_CAMSNAP              0x0010
 #define BCSR_BOARD_CAMPWR               0x0020
 #define BCSR_BOARD_SD0PWR               0x0040
-#define BCSR_BOARD_CAMCS                0x0010  /* DB1300 */
-#define BCSR_BOARD_HDMI_DE              0x0040  /* DB1300 */
+
 
 #define BCSR_SWITCHES_DIP               0x00FF
 #define BCSR_SWITCHES_DIP_1             0x0080
@@ -233,10 +214,7 @@ enum bcsr_whoami_boards {
 #define BCSR_SYSTEM_RESET               0x8000  /* clear to reset */
 #define BCSR_SYSTEM_PWROFF              0x4000  /* set to power off */
 #define BCSR_SYSTEM_VDDI                0x001F  /* PB1xxx boards */
-#define BCSR_SYSTEM_DEBUGCSMASK         0x003F  /* DB1300 */
-#define BCSR_SYSTEM_UDMAMODE            0x0100  /* DB1300 */
-#define BCSR_SYSTEM_WAKEONIRQ           0x0200  /* DB1300 */
-#define BCSR_SYSTEM_VDDI1300            0x3C00  /* DB1300 */
+
 
 
 
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index b2a8319521e..3404248f509 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -43,20 +43,17 @@
 #define BCSR_INT_PC1EJECT       0x0800
 #define BCSR_INT_SD0INSERT      0x1000
 #define BCSR_INT_SD0EJECT       0x2000
-#define BCSR_INT_SD1INSERT      0x4000
-#define BCSR_INT_SD1EJECT       0x8000
 
+#define IDE_PHYS_ADDR           0x18800000
 #define IDE_REG_SHIFT           5
+#define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
+#define IDE_RQSIZE              128
 
-#define DB1200_IDE_PHYS_ADDR    0x18800000
+#define DB1200_IDE_PHYS_ADDR    IDE_PHYS_ADDR
 #define DB1200_IDE_PHYS_LEN     (16 << IDE_REG_SHIFT)
 #define DB1200_ETH_PHYS_ADDR    0x19000300
 #define DB1200_NAND_PHYS_ADDR   0x20000000
 
-#define PB1200_IDE_PHYS_ADDR    0x0C800000
-#define PB1200_ETH_PHYS_ADDR    0x0D000300
-#define PB1200_NAND_PHYS_ADDR   0x1C000000
-
 /*
  * External Interrupts for DBAu1200 as of 8/6/2004.
  * Bit positions in the CPLD registers can be calculated by taking
@@ -82,8 +79,6 @@ enum external_db1200_ints {
         DB1200_PC1_EJECT_INT,
         DB1200_SD0_INSERT_INT,
         DB1200_SD0_EJECT_INT,
-        PB1200_SD1_INSERT_INT,
-        PB1200_SD1_EJECT_INT,
 
         DB1200_INT_END          = DB1200_INT_BEGIN + 15,
 };
diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
deleted file mode 100644
index 7fe5fb3ba87..00000000000
--- a/arch/mips/include/asm/mach-db1x00/db1300.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * NetLogic DB1300 board constants
- */
-
-#ifndef _DB1300_H_
-#define _DB1300_H_
-
-/* FPGA (external mux) interrupt sources */
-#define DB1300_FIRST_INT        (ALCHEMY_GPIC_INT_LAST + 1)
-#define DB1300_IDE_INT          (DB1300_FIRST_INT + 0)
-#define DB1300_ETH_INT          (DB1300_FIRST_INT + 1)
-#define DB1300_CF_INT           (DB1300_FIRST_INT + 2)
-#define DB1300_VIDEO_INT        (DB1300_FIRST_INT + 4)
-#define DB1300_HDMI_INT         (DB1300_FIRST_INT + 5)
-#define DB1300_DC_INT           (DB1300_FIRST_INT + 6)
-#define DB1300_FLASH_INT        (DB1300_FIRST_INT + 7)
-#define DB1300_CF_INSERT_INT    (DB1300_FIRST_INT + 8)
-#define DB1300_CF_EJECT_INT     (DB1300_FIRST_INT + 9)
-#define DB1300_AC97_INT         (DB1300_FIRST_INT + 10)
-#define DB1300_AC97_PEN_INT     (DB1300_FIRST_INT + 11)
-#define DB1300_SD1_INSERT_INT   (DB1300_FIRST_INT + 12)
-#define DB1300_SD1_EJECT_INT    (DB1300_FIRST_INT + 13)
-#define DB1300_OTG_VBUS_OC_INT  (DB1300_FIRST_INT + 14)
-#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
-#define DB1300_LAST_INT         (DB1300_FIRST_INT + 15)
-
-/* SMSC9210 CS */
-#define DB1300_ETH_PHYS_ADDR    0x19000000
-#define DB1300_ETH_PHYS_END     0x197fffff
-
-/* ATA CS */
-#define DB1300_IDE_PHYS_ADDR    0x18800000
-#define DB1300_IDE_REG_SHIFT    5
-#define DB1300_IDE_PHYS_LEN     (16 << DB1300_IDE_REG_SHIFT)
-
-/* NAND CS */
-#define DB1300_NAND_PHYS_ADDR   0x20000000
-#define DB1300_NAND_PHYS_END    0x20000fff
-
-#endif  /* _DB1300_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h
deleted file mode 100644
index 15b26693238..00000000000
--- a/arch/mips/include/asm/mach-db1x00/irq.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 by Ralf Baechle
- */
-#ifndef __ASM_MACH_GENERIC_IRQ_H
-#define __ASM_MACH_GENERIC_IRQ_H
-
-
-#ifdef NR_IRQS
-#undef NR_IRQS
-#endif
-
-#ifndef MIPS_CPU_IRQ_BASE
-#define MIPS_CPU_IRQ_BASE 0
-#endif
-
-/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */
-#define NR_IRQS 152
-
-#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-dec/war.h b/arch/mips/include/asm/mach-dec/war.h
index d29996feb3e..ca5e2ef909a 100644
--- a/arch/mips/include/asm/mach-dec/war.h
+++ b/arch/mips/include/asm/mach-dec/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-emma2rh/war.h b/arch/mips/include/asm/mach-emma2rh/war.h
index 79ae82da3ec..b660a4c30e6 100644
--- a/arch/mips/include/asm/mach-emma2rh/war.h
+++ b/arch/mips/include/asm/mach-emma2rh/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index a38f4d43e5e..001a8ce17c1 100644
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -98,7 +98,7 @@ static inline void fd_disable_irq(void)
 static inline int fd_request_irq(void)
 {
         return request_irq(FLOPPY_IRQ, floppy_interrupt,
-                           0, "floppy", NULL);
+                           IRQF_DISABLED, "floppy", NULL);
 }
 
 static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index e014264b2be..70d9a25132c 100644
--- a/arch/mips/include/asm/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -34,6 +34,12 @@
 #endif
 #endif
 
+#ifdef CONFIG_IRQ_CPU_RM9K
+#ifndef RM9K_CPU_IRQ_BASE
+#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
+#endif
+#endif
+
 #endif /* CONFIG_IRQ_CPU */
 
 #endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
index f4caacd2555..9c8735158da 100644
--- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -30,7 +30,6 @@
 #define cpu_has_ic_fills_f_dc   0
 
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_mipsmt          0
 #define cpu_has_userlocal       0
 
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index fba640517f4..a44fa9656a8 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -21,6 +21,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
index 1d2b6ff60d3..7d3112b148d 100644
--- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -26,7 +26,6 @@
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_icache_snoops_remote_store  1
 #define cpu_has_mipsmt          0
 #define cpu_has_userlocal       0
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index b2cf641f206..1b1a7d1632b 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -36,6 +36,23 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
 
 #define node_distance(from, to) (__node_distances[(from)][(to)])
 
+/* sched_domains SD_NODE_INIT for SGI IP27 machines */
+#define SD_NODE_INIT (struct sched_domain) {            \
+        .parent                 = NULL,                 \
+        .child                  = NULL,                 \
+        .groups                 = NULL,                 \
+        .min_interval           = 8,                    \
+        .max_interval           = 32,                   \
+        .busy_factor            = 32,                   \
+        .imbalance_pct          = 125,                  \
+        .cache_nice_tries       = 1,                    \
+        .flags                  = SD_LOAD_BALANCE |     \
+                                  SD_BALANCE_EXEC,      \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 1,                    \
+        .nr_balance_failed      = 0,                    \
+}
+
 #include <asm-generic/topology.h>
 
 #endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 4ee0e4bdf4f..e2ddcc9b1ff 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 1
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
index 50d344ca60a..9a53b326f84 100644
--- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
@@ -27,7 +27,6 @@
 #define cpu_has_dc_aliases      0 /* see probe_pcache() */
 #define cpu_has_ic_fills_f_dc   0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_icache_snoops_remote_store  1
 #define cpu_has_mipsmt          0
 #define cpu_has_userlocal       0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 4821c7b7a38..a1baafab486 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 1
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
index 2e1ec6cfedd..6782fccebe8 100644
--- a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
@@ -37,7 +37,6 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_ic_fills_f_dc   0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_4k_cache        1
 #define cpu_has_mipsmt          0
 #define cpu_has_userlocal       0
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 7237a935a13..d194056dcd7 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 88b5acb7514..56e9ca6ae42 100644
--- a/arch/mips/include/asm/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -90,7 +90,7 @@ static inline void fd_disable_irq(void)
 static inline int fd_request_irq(void)
 {
         return request_irq(FLOPPY_IRQ, floppy_interrupt,
-                           0, "floppy", NULL);
+                           IRQF_DISABLED, "floppy", NULL);
 }
 
 static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-jazz/war.h b/arch/mips/include/asm/mach-jazz/war.h
index 5b18b9a3d0e..6158ee861bf 100644
--- a/arch/mips/include/asm/mach-jazz/war.h
+++ b/arch/mips/include/asm/mach-jazz/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
index a225baaa215..d12e5c6477b 100644
--- a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
@@ -38,7 +38,6 @@
 #define cpu_has_mips64r1        0
 #define cpu_has_mips64r2        0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_mipsmt          0
 #define cpu_has_userlocal       0
 #define cpu_has_nofpuex 0
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
index 5ad1a9c113c..a865c983c70 100644
--- a/arch/mips/include/asm/mach-jz4740/irq.h
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -45,7 +45,7 @@
 #define JZ4740_IRQ_LCD          JZ4740_IRQ(30)
 
 /* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (x))
+#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (X))
 
 #define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
 #define JZ4740_IRQ_GPIO(x)      (JZ4740_IRQ(48) + (x))
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
index 986982db7c3..bb5b9a4e29c 100644
--- a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
@@ -19,8 +19,6 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
-#define JZ_NAND_NUM_BANKS 4
-
 struct jz_nand_platform_data {
         int                     num_partitions;
         struct mtd_partition    *partitions;
@@ -29,8 +27,6 @@ struct jz_nand_platform_data {
 
         unsigned int busy_gpio;
 
-        unsigned char banks[JZ_NAND_NUM_BANKS];
-
         void (*ident_callback)(struct platform_device *, struct nand_chip *,
                                 struct mtd_partition **, int *num_partitions);
 };
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
index 163e81db880..564ab81d6cd 100644
--- a/arch/mips/include/asm/mach-jz4740/platform.h
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -31,7 +31,6 @@ extern struct platform_device jz4740_pcm_device;
 extern struct platform_device jz4740_codec_device;
 extern struct platform_device jz4740_adc_device;
 extern struct platform_device jz4740_wdt_device;
-extern struct platform_device jz4740_pwm_device;
 
 void jz4740_serial_device_register(void);
 
diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h
index a7759fb1f73..9baa03ce748 100644
--- a/arch/mips/include/asm/mach-jz4740/timer.h
+++ b/arch/mips/include/asm/mach-jz4740/timer.h
@@ -16,120 +16,7 @@
 #ifndef __ASM_MACH_JZ4740_TIMER
 #define __ASM_MACH_JZ4740_TIMER
 
-#define JZ_REG_TIMER_STOP               0x0C
-#define JZ_REG_TIMER_STOP_SET           0x1C
-#define JZ_REG_TIMER_STOP_CLEAR         0x2C
-#define JZ_REG_TIMER_ENABLE             0x00
-#define JZ_REG_TIMER_ENABLE_SET         0x04
-#define JZ_REG_TIMER_ENABLE_CLEAR       0x08
-#define JZ_REG_TIMER_FLAG               0x10
-#define JZ_REG_TIMER_FLAG_SET           0x14
-#define JZ_REG_TIMER_FLAG_CLEAR         0x18
-#define JZ_REG_TIMER_MASK               0x20
-#define JZ_REG_TIMER_MASK_SET           0x24
-#define JZ_REG_TIMER_MASK_CLEAR         0x28
-
-#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
-#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
-#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
-#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
-
-#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
-#define JZ_TIMER_IRQ_FULL(x) BIT(x)
-
-#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN      BIT(9)
-#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW            BIT(8)
-#define JZ_TIMER_CTRL_PWM_ENABLE                BIT(7)
-#define JZ_TIMER_CTRL_PRESCALE_MASK             0x1c
-#define JZ_TIMER_CTRL_PRESCALE_OFFSET           0x3
-#define JZ_TIMER_CTRL_PRESCALE_1                (0 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_4                (1 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_16               (2 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_64               (3 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_256              (4 << 3)
-#define JZ_TIMER_CTRL_PRESCALE_1024             (5 << 3)
-
-#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
-
-#define JZ_TIMER_CTRL_SRC_EXT           BIT(2)
-#define JZ_TIMER_CTRL_SRC_RTC           BIT(1)
-#define JZ_TIMER_CTRL_SRC_PCLK          BIT(0)
-
-extern void __iomem *jz4740_timer_base;
-void __init jz4740_timer_init(void);
-
 void jz4740_timer_enable_watchdog(void);
 void jz4740_timer_disable_watchdog(void);
 
-static inline void jz4740_timer_stop(unsigned int timer)
-{
-        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
-}
-
-static inline void jz4740_timer_start(unsigned int timer)
-{
-        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
-}
-
-static inline bool jz4740_timer_is_enabled(unsigned int timer)
-{
-        return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
-}
-
-static inline void jz4740_timer_enable(unsigned int timer)
-{
-        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
-}
-
-static inline void jz4740_timer_disable(unsigned int timer)
-{
-        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
-}
-
-static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
-{
-        writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
-}
-
-static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
-{
-        writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
-}
-
-static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
-{
-        writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
-}
-
-static inline uint16_t jz4740_timer_get_count(unsigned int timer)
-{
-        return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
-}
-
-static inline void jz4740_timer_ack_full(unsigned int timer)
-{
-        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
-}
-
-static inline void jz4740_timer_irq_full_enable(unsigned int timer)
-{
-        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
-        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
-}
-
-static inline void jz4740_timer_irq_full_disable(unsigned int timer)
-{
-        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
-}
-
-static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
-{
-        writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
-}
-
-static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
-{
-        return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
-}
-
 #endif
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
index 9b511d32383..3a5bc17e28f 100644
--- a/arch/mips/include/asm/mach-jz4740/war.h
+++ b/arch/mips/include/asm/mach-jz4740/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
deleted file mode 100644
index c6b63a40964..00000000000
--- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
- */
-
-#ifndef _FALCON_IRQ__
-#define _FALCON_IRQ__
-
-#define INT_NUM_IRQ0                    8
-#define INT_NUM_IM0_IRL0                (INT_NUM_IRQ0 + 0)
-#define INT_NUM_IM1_IRL0                (INT_NUM_IM0_IRL0 + 32)
-#define INT_NUM_IM2_IRL0                (INT_NUM_IM1_IRL0 + 32)
-#define INT_NUM_IM3_IRL0                (INT_NUM_IM2_IRL0 + 32)
-#define INT_NUM_IM4_IRL0                (INT_NUM_IM3_IRL0 + 32)
-#define INT_NUM_EXTRA_START             (INT_NUM_IM4_IRL0 + 32)
-#define INT_NUM_IM_OFFSET               (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
-
-#define MIPS_CPU_TIMER_IRQ                      7
-
-#define MAX_IM                  5
-
-#endif /* _FALCON_IRQ__ */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
deleted file mode 100644
index 2caccd9f9db..00000000000
--- a/arch/mips/include/asm/mach-lantiq/falcon/irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
- */
-
-#ifndef __FALCON_IRQ_H
-#define __FALCON_IRQ_H
-
-#include <falcon_irq.h>
-
-#define NR_IRQS 328
-
-#include_next <irq.h>
-
-#endif
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
deleted file mode 100644
index fccac359265..00000000000
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#ifndef _LTQ_FALCON_H__
-#define _LTQ_FALCON_H__
-
-#ifdef CONFIG_SOC_FALCON
-
-#include <linux/pinctrl/pinctrl.h>
-#include <lantiq.h>
-
-/* Chip IDs */
-#define SOC_ID_FALCON           0x01B8
-
-/* SoC Types */
-#define SOC_TYPE_FALCON         0x01
-
-/*
- * during early_printk no ioremap possible at this early stage
- * lets use KSEG1 instead
- */
-#define LTQ_ASC0_BASE_ADDR      0x1E100C00
-#define LTQ_EARLY_ASC           KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
-
-/* WDT */
-#define LTQ_RST_CAUSE_WDTRST    0x0002
-
-/* CHIP ID */
-#define LTQ_STATUS_BASE_ADDR    0x1E802000
-
-#define FALCON_CHIPID           ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
-#define FALCON_CHIPTYPE         ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
-#define FALCON_CHIPCONF         ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
-
-/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
-#define SYSCTL_SYS1             0
-#define SYSCTL_SYSETH           1
-#define SYSCTL_SYSGPE           2
-
-/* BOOT_SEL - find what boot media we have */
-#define BS_FLASH                0x1
-#define BS_SPI                  0x4
-
-/* global register ranges */
-extern __iomem void *ltq_ebu_membase;
-extern __iomem void *ltq_sys1_membase;
-#define ltq_ebu_w32(x, y)       ltq_w32((x), ltq_ebu_membase + (y))
-#define ltq_ebu_r32(x)          ltq_r32(ltq_ebu_membase + (x))
-
-#define ltq_sys1_w32(x, y)      ltq_w32((x), ltq_sys1_membase + (y))
-#define ltq_sys1_r32(x)         ltq_r32(ltq_sys1_membase + (x))
-#define ltq_sys1_w32_mask(clear, set, reg)   \
-        ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
-
-/* allow the gpio and pinctrl drivers to talk to eachother */
-extern int pinctrl_falcon_get_range_size(int id);
-extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
-
-/*
- * to keep the irq code generic we need to define this to 0 as falcon
- * has no EIU/EBU
- */
-#define LTQ_EBU_PCC_ISTAT       0
-
-#endif /* CONFIG_SOC_FALCON */
-#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lantiq/gpio.h b/arch/mips/include/asm/mach-lantiq/gpio.h
deleted file mode 100644
index 9ba1caebca5..00000000000
--- a/arch/mips/include/asm/mach-lantiq/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_MIPS_MACH_LANTIQ_GPIO_H
-#define __ASM_MIPS_MACH_LANTIQ_GPIO_H
-
-#define gpio_to_irq __gpio_to_irq
-
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-
-#define gpio_cansleep __gpio_cansleep
-
-#include <asm-generic/gpio.h>
-
-#endif
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 5e8a6e96575..ce2f02929d2 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -9,8 +9,6 @@
 #define _LANTIQ_H__
 
 #include <linux/irq.h>
-#include <linux/device.h>
-#include <linux/clk.h>
 
 /* generic reg access functions */
 #define ltq_r32(reg)            __raw_readl(reg)
@@ -23,9 +21,25 @@
 /* register access macros for EBU and CGU */
 #define ltq_ebu_w32(x, y)       ltq_w32((x), ltq_ebu_membase + (y))
 #define ltq_ebu_r32(x)          ltq_r32(ltq_ebu_membase + (x))
-#define ltq_ebu_w32_mask(x, y, z) \
-        ltq_w32_mask(x, y, ltq_ebu_membase + (z))
+#define ltq_cgu_w32(x, y)       ltq_w32((x), ltq_cgu_membase + (y))
+#define ltq_cgu_r32(x)          ltq_r32(ltq_cgu_membase + (x))
+
 extern __iomem void *ltq_ebu_membase;
+extern __iomem void *ltq_cgu_membase;
+
+extern unsigned int ltq_get_cpu_ver(void);
+extern unsigned int ltq_get_soc_type(void);
+
+/* clock speeds */
+#define CLOCK_60M       60000000
+#define CLOCK_83M       83333333
+#define CLOCK_111M      111111111
+#define CLOCK_133M      133333333
+#define CLOCK_167M      166666667
+#define CLOCK_200M      200000000
+#define CLOCK_266M      266666666
+#define CLOCK_333M      333333333
+#define CLOCK_400M      400000000
 
 /* spinlock all ebu i/o */
 extern spinlock_t ebu_lock;
@@ -35,21 +49,15 @@ extern void ltq_disable_irq(struct irq_data *data);
 extern void ltq_mask_and_ack_irq(struct irq_data *data);
 extern void ltq_enable_irq(struct irq_data *data);
 
-/* clock handling */
-extern int clk_activate(struct clk *clk);
-extern void clk_deactivate(struct clk *clk);
-extern struct clk *clk_get_cpu(void);
-extern struct clk *clk_get_fpi(void);
-extern struct clk *clk_get_io(void);
-
-/* find out what bootsource we have */
-extern unsigned char ltq_boot_select(void);
 /* find out what caused the last cpu reset */
 extern int ltq_reset_cause(void);
+#define LTQ_RST_CAUSE_WDTRST    0x20
 
 #define IOPORT_RESOURCE_START   0x10000000
 #define IOPORT_RESOURCE_END     0xffffffff
 #define IOMEM_RESOURCE_START    0x10000000
 #define IOMEM_RESOURCE_END      0xffffffff
+#define LTQ_FLASH_START         0x10000000
+#define LTQ_FLASH_MAX           0x04000000
 
 #endif
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
index e23bf7c9a2d..a305f1d0259 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
@@ -9,8 +9,41 @@
 #ifndef _LANTIQ_PLATFORM_H__
 #define _LANTIQ_PLATFORM_H__
 
+#include <linux/mtd/partitions.h>
 #include <linux/socket.h>
 
+/* struct used to pass info to the pci core */
+enum {
+        PCI_CLOCK_INT = 0,
+        PCI_CLOCK_EXT
+};
+
+#define PCI_EXIN0       0x0001
+#define PCI_EXIN1       0x0002
+#define PCI_EXIN2       0x0004
+#define PCI_EXIN3       0x0008
+#define PCI_EXIN4       0x0010
+#define PCI_EXIN5       0x0020
+#define PCI_EXIN_MAX    6
+
+#define PCI_GNT1        0x0040
+#define PCI_GNT2        0x0080
+#define PCI_GNT3        0x0100
+#define PCI_GNT4        0x0200
+
+#define PCI_REQ1        0x0400
+#define PCI_REQ2        0x0800
+#define PCI_REQ3        0x1000
+#define PCI_REQ4        0x2000
+#define PCI_REQ_SHIFT   10
+#define PCI_REQ_MASK    0xf
+
+struct ltq_pci_data {
+        int clock;
+        int gpio;
+        int irq[16];
+};
+
 /* struct used to pass info to network drivers */
 struct ltq_eth_data {
         struct sockaddr mac;
diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
index b6c568c280e..01b08ef368d 100644
--- a/arch/mips/include/asm/mach-lantiq/war.h
+++ b/arch/mips/include/asm/mach-lantiq/war.h
@@ -16,6 +16,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
index 5eadfe58252..b4465a888e2 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -17,10 +17,50 @@
 #define INT_NUM_IM4_IRL0        (INT_NUM_IRQ0 + 128)
 #define INT_NUM_IM_OFFSET       (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
 
+#define LTQ_ASC_TIR(x)          (INT_NUM_IM3_IRL0 + (x * 8))
+#define LTQ_ASC_RIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 1)
+#define LTQ_ASC_EIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 2)
+
+#define LTQ_ASC_ASE_TIR         INT_NUM_IM2_IRL0
+#define LTQ_ASC_ASE_RIR         (INT_NUM_IM2_IRL0 + 2)
+#define LTQ_ASC_ASE_EIR         (INT_NUM_IM2_IRL0 + 3)
+
+#define LTQ_SSC_TIR             (INT_NUM_IM0_IRL0 + 15)
+#define LTQ_SSC_RIR             (INT_NUM_IM0_IRL0 + 14)
+#define LTQ_SSC_EIR             (INT_NUM_IM0_IRL0 + 16)
+
+#define LTQ_MEI_DYING_GASP_INT  (INT_NUM_IM1_IRL0 + 21)
+#define LTQ_MEI_INT             (INT_NUM_IM1_IRL0 + 23)
+
+#define LTQ_TIMER6_INT          (INT_NUM_IM1_IRL0 + 23)
+#define LTQ_USB_INT             (INT_NUM_IM1_IRL0 + 22)
+#define LTQ_USB_OC_INT          (INT_NUM_IM4_IRL0 + 23)
+
+#define MIPS_CPU_TIMER_IRQ              7
+
 #define LTQ_DMA_CH0_INT         (INT_NUM_IM2_IRL0)
+#define LTQ_DMA_CH1_INT         (INT_NUM_IM2_IRL0 + 1)
+#define LTQ_DMA_CH2_INT         (INT_NUM_IM2_IRL0 + 2)
+#define LTQ_DMA_CH3_INT         (INT_NUM_IM2_IRL0 + 3)
+#define LTQ_DMA_CH4_INT         (INT_NUM_IM2_IRL0 + 4)
+#define LTQ_DMA_CH5_INT         (INT_NUM_IM2_IRL0 + 5)
+#define LTQ_DMA_CH6_INT         (INT_NUM_IM2_IRL0 + 6)
+#define LTQ_DMA_CH7_INT         (INT_NUM_IM2_IRL0 + 7)
+#define LTQ_DMA_CH8_INT         (INT_NUM_IM2_IRL0 + 8)
+#define LTQ_DMA_CH9_INT         (INT_NUM_IM2_IRL0 + 9)
+#define LTQ_DMA_CH10_INT        (INT_NUM_IM2_IRL0 + 10)
+#define LTQ_DMA_CH11_INT        (INT_NUM_IM2_IRL0 + 11)
+#define LTQ_DMA_CH12_INT        (INT_NUM_IM2_IRL0 + 25)
+#define LTQ_DMA_CH13_INT        (INT_NUM_IM2_IRL0 + 26)
+#define LTQ_DMA_CH14_INT        (INT_NUM_IM2_IRL0 + 27)
+#define LTQ_DMA_CH15_INT        (INT_NUM_IM2_IRL0 + 28)
+#define LTQ_DMA_CH16_INT        (INT_NUM_IM2_IRL0 + 29)
+#define LTQ_DMA_CH17_INT        (INT_NUM_IM2_IRL0 + 30)
+#define LTQ_DMA_CH18_INT        (INT_NUM_IM2_IRL0 + 16)
+#define LTQ_DMA_CH19_INT        (INT_NUM_IM2_IRL0 + 21)
 
-#define MIPS_CPU_TIMER_IRQ      7
+#define LTQ_PPE_MBOX_INT        (INT_NUM_IM2_IRL0 + 24)
 
-#define MAX_IM                  5
+#define INT_NUM_IM4_IRL14       (INT_NUM_IM4_IRL0 + 14)
 
 #endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 133336b493b..8a3c6be669d 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -17,56 +17,38 @@
 #define SOC_ID_DANUBE1          0x129
 #define SOC_ID_DANUBE2          0x12B
 #define SOC_ID_TWINPASS         0x12D
-#define SOC_ID_AMAZON_SE_1      0x152 /* 50601 */
-#define SOC_ID_AMAZON_SE_2      0x153 /* 50600 */
+#define SOC_ID_AMAZON_SE        0x152
 #define SOC_ID_ARX188           0x16C
-#define SOC_ID_ARX168_1         0x16D
-#define SOC_ID_ARX168_2         0x16E
+#define SOC_ID_ARX168           0x16D
 #define SOC_ID_ARX182           0x16F
-#define SOC_ID_GRX188           0x170
-#define SOC_ID_GRX168           0x171
-
-#define SOC_ID_VRX288           0x1C0 /* v1.1 */
-#define SOC_ID_VRX282           0x1C1 /* v1.1 */
-#define SOC_ID_VRX268           0x1C2 /* v1.1 */
-#define SOC_ID_GRX268           0x1C8 /* v1.1 */
-#define SOC_ID_GRX288           0x1C9 /* v1.1 */
-#define SOC_ID_VRX288_2         0x00B /* v1.2 */
-#define SOC_ID_VRX268_2         0x00C /* v1.2 */
-#define SOC_ID_GRX288_2         0x00D /* v1.2 */
-#define SOC_ID_GRX282_2         0x00E /* v1.2 */
-
- /* SoC Types */
+
+/* SoC Types */
 #define SOC_TYPE_DANUBE         0x01
 #define SOC_TYPE_TWINPASS       0x02
 #define SOC_TYPE_AR9            0x03
-#define SOC_TYPE_VR9            0x04 /* v1.1 */
-#define SOC_TYPE_VR9_2          0x05 /* v1.2 */
-#define SOC_TYPE_AMAZON_SE      0x06
-
-/* BOOT_SEL - find what boot media we have */
-#define BS_EXT_ROM              0x0
-#define BS_FLASH                0x1
-#define BS_MII0                 0x2
-#define BS_PCI                  0x3
-#define BS_UART1                0x4
-#define BS_SPI                  0x5
-#define BS_NAND                 0x6
-#define BS_RMII0                0x7
-
-/* helpers used to access the cgu */
-#define ltq_cgu_w32(x, y)       ltq_w32((x), ltq_cgu_membase + (y))
-#define ltq_cgu_r32(x)          ltq_r32(ltq_cgu_membase + (x))
-extern __iomem void *ltq_cgu_membase;
+#define SOC_TYPE_VR9            0x04
+#define SOC_TYPE_AMAZON_SE      0x05
 
-/*
- * during early_printk no ioremap is possible
- * lets use KSEG1 instead
- */
+/* ASC0/1 - serial port */
+#define LTQ_ASC0_BASE_ADDR      0x1E100400
 #define LTQ_ASC1_BASE_ADDR      0x1E100C00
-#define LTQ_EARLY_ASC           KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
+#define LTQ_ASC_SIZE            0x400
+
+/* RCU - reset control unit */
+#define LTQ_RCU_BASE_ADDR       0x1F203000
+#define LTQ_RCU_SIZE            0x1000
+
+/* GPTU - general purpose timer unit */
+#define LTQ_GPTU_BASE_ADDR      0x18000300
+#define LTQ_GPTU_SIZE           0x100
 
 /* EBU - external bus unit */
+#define LTQ_EBU_GPIO_START      0x14000000
+#define LTQ_EBU_GPIO_SIZE       0x1000
+
+#define LTQ_EBU_BASE_ADDR       0x1E105300
+#define LTQ_EBU_SIZE            0x100
+
 #define LTQ_EBU_BUSCON0         0x0060
 #define LTQ_EBU_PCC_CON         0x0090
 #define LTQ_EBU_PCC_IEN         0x00A4
@@ -75,20 +57,85 @@ extern __iomem void *ltq_cgu_membase;
 #define LTQ_EBU_ADDRSEL1        0x0024
 #define EBU_WRDIS               0x80000000
 
+/* CGU - clock generation unit */
+#define LTQ_CGU_BASE_ADDR       0x1F103000
+#define LTQ_CGU_SIZE            0x1000
+
+/* ICU - interrupt control unit */
+#define LTQ_ICU_BASE_ADDR       0x1F880200
+#define LTQ_ICU_SIZE            0x100
+
+/* EIU - external interrupt unit */
+#define LTQ_EIU_BASE_ADDR       0x1F101000
+#define LTQ_EIU_SIZE            0x1000
+
+/* PMU - power management unit */
+#define LTQ_PMU_BASE_ADDR       0x1F102000
+#define LTQ_PMU_SIZE            0x1000
+
+#define PMU_DMA                 0x0020
+#define PMU_USB                 0x8041
+#define PMU_LED                 0x0800
+#define PMU_GPT                 0x1000
+#define PMU_PPE                 0x2000
+#define PMU_FPI                 0x4000
+#define PMU_SWITCH              0x10000000
+
+/* ETOP - ethernet */
+#define LTQ_ETOP_BASE_ADDR      0x1E180000
+#define LTQ_ETOP_SIZE           0x40000
+
+/* DMA */
+#define LTQ_DMA_BASE_ADDR       0x1E104100
+#define LTQ_DMA_SIZE            0x800
+
+/* PCI */
+#define PCI_CR_BASE_ADDR        0x1E105400
+#define PCI_CR_SIZE             0x400
+
 /* WDT */
-#define LTQ_RST_CAUSE_WDTRST    0x20
+#define LTQ_WDT_BASE_ADDR       0x1F8803F0
+#define LTQ_WDT_SIZE            0x10
+
+/* STP - serial to parallel conversion unit */
+#define LTQ_STP_BASE_ADDR       0x1E100BB0
+#define LTQ_STP_SIZE            0x40
+
+/* GPIO */
+#define LTQ_GPIO0_BASE_ADDR     0x1E100B10
+#define LTQ_GPIO1_BASE_ADDR     0x1E100B40
+#define LTQ_GPIO2_BASE_ADDR     0x1E100B70
+#define LTQ_GPIO_SIZE           0x30
+
+/* SSC */
+#define LTQ_SSC_BASE_ADDR       0x1e100800
+#define LTQ_SSC_SIZE            0x100
+
+/* MEI - dsl core */
+#define LTQ_MEI_BASE_ADDR       0x1E116000
+
+/* DEU - data encryption unit */
+#define LTQ_DEU_BASE_ADDR       0x1E103100
 
 /* MPS - multi processor unit (voice) */
 #define LTQ_MPS_BASE_ADDR       (KSEG1 + 0x1F107000)
 #define LTQ_MPS_CHIPID          ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
 
-/* allow booting xrx200 phys */
-int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
-
 /* request a non-gpio and set the PIO config */
-#define PMU_PPE                  BIT(13)
+extern int  ltq_gpio_request(unsigned int pin, unsigned int alt0,
+        unsigned int alt1, unsigned int dir, const char *name);
 extern void ltq_pmu_enable(unsigned int module);
 extern void ltq_pmu_disable(unsigned int module);
 
+static inline int ltq_is_ar9(void)
+{
+        return (ltq_get_soc_type() == SOC_TYPE_AR9);
+}
+
+static inline int ltq_is_vr9(void)
+{
+        return (ltq_get_soc_type() == SOC_TYPE_VR9);
+}
+
 #endif /* CONFIG_SOC_TYPE_XWAY */
 #endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lasat/war.h b/arch/mips/include/asm/mach-lasat/war.h
index 741ae724adc..bb1e0325c9b 100644
--- a/arch/mips/include/asm/mach-lasat/war.h
+++ b/arch/mips/include/asm/mach-lasat/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 1a05d854e34..675bd8641d5 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -32,7 +32,6 @@
 #define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
 #define cpu_has_divec           0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_ejtag           0
 #define cpu_has_fpu             1
 #define cpu_has_ic_fills_f_dc   0
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 5222a007bc2..1e29b9dd1d7 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -14,7 +14,6 @@
 #include <linux/io.h>
 #include <linux/init.h>
 #include <linux/irq.h>
-#include <linux/kconfig.h>
 
 /* loongson internal northbridge initialization */
 extern void bonito_irq_init(void);
@@ -67,7 +66,7 @@ extern int mach_i8259_irq(void);
 #include <linux/interrupt.h>
 static inline void do_perfcnt_IRQ(void)
 {
-#if IS_ENABLED(CONFIG_OPROFILE)
+#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
         do_IRQ(LOONGSON2_PERFCNT_IRQ);
 #endif
 }
@@ -245,6 +244,7 @@ static inline void do_perfcnt_IRQ(void)
 
 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
 #include <linux/cpufreq.h>
+extern void loongson2_cpu_wait(void);
 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
 
 /* Chip Config */
diff --git a/arch/mips/include/asm/mach-loongson/war.h b/arch/mips/include/asm/mach-loongson/war.h
index f2570df66bb..4b971c3ffd8 100644
--- a/arch/mips/include/asm/mach-loongson/war.h
+++ b/arch/mips/include/asm/mach-loongson/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h
deleted file mode 100644
index da96ed42f73..00000000000
--- a/arch/mips/include/asm/mach-loongson1/irq.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
- *
- * IRQ mappings for Loongson 1
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-
-#ifndef __ASM_MACH_LOONGSON1_IRQ_H
-#define __ASM_MACH_LOONGSON1_IRQ_H
-
-/*
- * CPU core Interrupt Numbers
- */
-#define MIPS_CPU_IRQ_BASE               0
-#define MIPS_CPU_IRQ(x)                 (MIPS_CPU_IRQ_BASE + (x))
-
-#define SOFTINT0_IRQ                    MIPS_CPU_IRQ(0)
-#define SOFTINT1_IRQ                    MIPS_CPU_IRQ(1)
-#define INT0_IRQ                        MIPS_CPU_IRQ(2)
-#define INT1_IRQ                        MIPS_CPU_IRQ(3)
-#define INT2_IRQ                        MIPS_CPU_IRQ(4)
-#define INT3_IRQ                        MIPS_CPU_IRQ(5)
-#define INT4_IRQ                        MIPS_CPU_IRQ(6)
-#define TIMER_IRQ                       MIPS_CPU_IRQ(7)         /* cpu timer */
-
-#define MIPS_CPU_IRQS           (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
-
-/*
- * INT0~3 Interrupt Numbers
- */
-#define LS1X_IRQ_BASE                   MIPS_CPU_IRQS
-#define LS1X_IRQ(n, x)                  (LS1X_IRQ_BASE + (n << 5) + (x))
-
-#define LS1X_UART0_IRQ                  LS1X_IRQ(0, 2)
-#define LS1X_UART1_IRQ                  LS1X_IRQ(0, 3)
-#define LS1X_UART2_IRQ                  LS1X_IRQ(0, 4)
-#define LS1X_UART3_IRQ                  LS1X_IRQ(0, 5)
-#define LS1X_CAN0_IRQ                   LS1X_IRQ(0, 6)
-#define LS1X_CAN1_IRQ                   LS1X_IRQ(0, 7)
-#define LS1X_SPI0_IRQ                   LS1X_IRQ(0, 8)
-#define LS1X_SPI1_IRQ                   LS1X_IRQ(0, 9)
-#define LS1X_AC97_IRQ                   LS1X_IRQ(0, 10)
-#define LS1X_DMA0_IRQ                   LS1X_IRQ(0, 13)
-#define LS1X_DMA1_IRQ                   LS1X_IRQ(0, 14)
-#define LS1X_DMA2_IRQ                   LS1X_IRQ(0, 15)
-#define LS1X_PWM0_IRQ                   LS1X_IRQ(0, 17)
-#define LS1X_PWM1_IRQ                   LS1X_IRQ(0, 18)
-#define LS1X_PWM2_IRQ                   LS1X_IRQ(0, 19)
-#define LS1X_PWM3_IRQ                   LS1X_IRQ(0, 20)
-#define LS1X_RTC_INT0_IRQ               LS1X_IRQ(0, 21)
-#define LS1X_RTC_INT1_IRQ               LS1X_IRQ(0, 22)
-#define LS1X_RTC_INT2_IRQ               LS1X_IRQ(0, 23)
-#define LS1X_TOY_INT0_IRQ               LS1X_IRQ(0, 24)
-#define LS1X_TOY_INT1_IRQ               LS1X_IRQ(0, 25)
-#define LS1X_TOY_INT2_IRQ               LS1X_IRQ(0, 26)
-#define LS1X_RTC_TICK_IRQ               LS1X_IRQ(0, 27)
-#define LS1X_TOY_TICK_IRQ               LS1X_IRQ(0, 28)
-
-#define LS1X_EHCI_IRQ                   LS1X_IRQ(1, 0)
-#define LS1X_OHCI_IRQ                   LS1X_IRQ(1, 1)
-#define LS1X_GMAC0_IRQ                  LS1X_IRQ(1, 2)
-#define LS1X_GMAC1_IRQ                  LS1X_IRQ(1, 3)
-
-#define LS1X_IRQS               (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
-
-#define NR_IRQS                 (MIPS_CPU_IRQS + LS1X_IRQS)
-
-#endif /* __ASM_MACH_LOONGSON1_IRQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
deleted file mode 100644
index 4e18e88cebb..00000000000
--- a/arch/mips/include/asm/mach-loongson1/loongson1.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
- *
- * Register mappings for Loongson 1
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-
-#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
-#define __ASM_MACH_LOONGSON1_LOONGSON1_H
-
-#define DEFAULT_MEMSIZE                 256     /* If no memsize provided */
-
-/* Loongson 1 Register Bases */
-#define LS1X_INTC_BASE                  0x1fd01040
-#define LS1X_EHCI_BASE                  0x1fe00000
-#define LS1X_OHCI_BASE                  0x1fe08000
-#define LS1X_GMAC0_BASE                 0x1fe10000
-#define LS1X_GMAC1_BASE                 0x1fe20000
-
-#define LS1X_UART0_BASE                 0x1fe40000
-#define LS1X_UART1_BASE                 0x1fe44000
-#define LS1X_UART2_BASE                 0x1fe48000
-#define LS1X_UART3_BASE                 0x1fe4c000
-#define LS1X_CAN0_BASE                  0x1fe50000
-#define LS1X_CAN1_BASE                  0x1fe54000
-#define LS1X_I2C0_BASE                  0x1fe58000
-#define LS1X_I2C1_BASE                  0x1fe68000
-#define LS1X_I2C2_BASE                  0x1fe70000
-#define LS1X_PWM_BASE                   0x1fe5c000
-#define LS1X_WDT_BASE                   0x1fe5c060
-#define LS1X_RTC_BASE                   0x1fe64000
-#define LS1X_AC97_BASE                  0x1fe74000
-#define LS1X_NAND_BASE                  0x1fe78000
-#define LS1X_CLK_BASE                   0x1fe78030
-
-#include <regs-clk.h>
-#include <regs-wdt.h>
-
-#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
deleted file mode 100644
index 718a1228a4f..00000000000
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-
-#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H
-#define __ASM_MACH_LOONGSON1_PLATFORM_H
-
-#include <linux/platform_device.h>
-
-extern struct platform_device ls1x_uart_device;
-extern struct platform_device ls1x_eth0_device;
-extern struct platform_device ls1x_ehci_device;
-extern struct platform_device ls1x_rtc_device;
-
-extern void __init ls1x_clk_init(void);
-extern void __init ls1x_serial_setup(struct platform_device *pdev);
-
-#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h
deleted file mode 100644
index b871dc41b8d..00000000000
--- a/arch/mips/include/asm/mach-loongson1/prom.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __ASM_MACH_LOONGSON1_PROM_H
-#define __ASM_MACH_LOONGSON1_PROM_H
-
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-
-/* environment arguments from bootloader */
-extern unsigned long memsize, highmemsize;
-
-/* loongson-specific command line, env and memory initialization */
-extern char *prom_getenv(char *name);
-extern void __init prom_init_cmdline(void);
-
-#endif /* __ASM_MACH_LOONGSON1_PROM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
deleted file mode 100644
index a81fa3d0dc9..00000000000
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
- *
- * Loongson 1 Clock Register Definitions.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
-#define __ASM_MACH_LOONGSON1_REGS_CLK_H
-
-#define LS1X_CLK_REG(x) \
-                ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
-
-#define LS1X_CLK_PLL_FREQ               LS1X_CLK_REG(0x0)
-#define LS1X_CLK_PLL_DIV                LS1X_CLK_REG(0x4)
-
-/* Clock PLL Divisor Register Bits */
-#define DIV_DC_EN                       (0x1 << 31)
-#define DIV_CPU_EN                      (0x1 << 25)
-#define DIV_DDR_EN                      (0x1 << 19)
-
-#define DIV_DC_SHIFT                    26
-#define DIV_CPU_SHIFT                   20
-#define DIV_DDR_SHIFT                   14
-
-#define DIV_DC_WIDTH                    5
-#define DIV_CPU_WIDTH                   5
-#define DIV_DDR_WIDTH                   5
-
-#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
deleted file mode 100644
index f897de68c52..00000000000
--- a/arch/mips/include/asm/mach-loongson1/regs-wdt.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
- *
- * Loongson 1 watchdog register definitions.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H
-#define __ASM_MACH_LOONGSON1_REGS_WDT_H
-
-#define LS1X_WDT_REG(x) \
-                ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x)))
-
-#define LS1X_WDT_EN                     LS1X_WDT_REG(0x0)
-#define LS1X_WDT_SET                    LS1X_WDT_REG(0x4)
-#define LS1X_WDT_TIMER                  LS1X_WDT_REG(0x8)
-
-#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
deleted file mode 100644
index 8fb50d00813..00000000000
--- a/arch/mips/include/asm/mach-loongson1/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MACH_LOONGSON1_WAR_H
-#define __ASM_MACH_LOONGSON1_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MACH_LOONGSON1_WAR_H */
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index d068fc411f4..7c6931d5f45 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        1
 #define MIPS_CACHE_SYNC_WAR             1
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 091deb1700e..3b728275b9b 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,33 +24,24 @@
 
 #define cpu_has_llsc            1
 #define cpu_has_vtag_icache     0
-#define cpu_has_ic_fills_f_dc   1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_mipsmt          0
-#define cpu_icache_snoops_remote_store  1
+#define cpu_has_userlocal       0
+#define cpu_icache_snoops_remote_store  0
 
+#define cpu_has_nofpuex         0
 #define cpu_has_64bits          1
 
 #define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        0
 #define cpu_has_mips64r1        1
+#define cpu_has_mips64r2        0
 
 #define cpu_has_inclusive_pcaches       0
 
 #define cpu_dcache_line_size()  32
 #define cpu_icache_line_size()  32
 
-#if defined(CONFIG_CPU_XLR)
-#define cpu_has_userlocal       0
-#define cpu_has_dc_aliases      0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r2        0
-#elif defined(CONFIG_CPU_XLP)
-#define cpu_has_userlocal       1
-#define cpu_has_mips32r2        1
-#define cpu_has_mips64r2        1
-#else
-#error "Unknown Netlogic CPU"
-#endif
-
 #endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
index 868ed8a2ed5..b5902458e7c 100644
--- a/arch/mips/include/asm/mach-netlogic/irq.h
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -8,9 +8,7 @@
 #ifndef __ASM_NETLOGIC_IRQ_H
 #define __ASM_NETLOGIC_IRQ_H
 
-#include <asm/mach-netlogic/multi-node.h>
-#define NR_IRQS                 (64 * NLM_NR_NODES)
-
+#define NR_IRQS                 64
 #define MIPS_CPU_IRQ_BASE       0
 
 #endif /* __ASM_NETLOGIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
deleted file mode 100644
index d62fc773f4d..00000000000
--- a/arch/mips/include/asm/mach-netlogic/multi-node.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NETLOGIC_MULTI_NODE_H_
-#define _NETLOGIC_MULTI_NODE_H_
-
-#ifndef CONFIG_NLM_MULTINODE
-#define NLM_NR_NODES            1
-#else
-#if defined(CONFIG_NLM_MULTINODE_2)
-#define NLM_NR_NODES            2
-#elif defined(CONFIG_NLM_MULTINODE_4)
-#define NLM_NR_NODES            4
-#else
-#define NLM_NR_NODES            1
-#endif
-#endif
-
-#define NLM_CORES_PER_NODE      8
-#define NLM_THREADS_PER_CORE    4
-#define NLM_CPUS_PER_NODE       (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE)
-
-#endif
diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h
index 2c7216840e1..22da8932735 100644
--- a/arch/mips/include/asm/mach-netlogic/war.h
+++ b/arch/mips/include/asm/mach-netlogic/war.h
@@ -18,6 +18,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h
index f192acf4a8a..ed3a88da70f 100644
--- a/arch/mips/include/asm/mach-pnx833x/gpio.h
+++ b/arch/mips/include/asm/mach-pnx833x/gpio.h
@@ -30,7 +30,7 @@
    - including locking between different uses
 */
 
-#include <asm/mach-pnx833x/pnx833x.h>
+#include "pnx833x.h"
 
 #define SET_REG_BIT(reg, bit)           do { (reg |= (1 << (bit))); } while (0)
 #define CLEAR_REG_BIT(reg, bit)         do { (reg &= ~(1 << (bit))); } while (0)
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
index edaa06d9d49..82cd1e97bc2 100644
--- a/arch/mips/include/asm/mach-pnx833x/war.h
+++ b/arch/mips/include/asm/mach-pnx833x/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-pnx8550/war.h b/arch/mips/include/asm/mach-pnx8550/war.h
index de8894c4668..d0458dd082f 100644
--- a/arch/mips/include/asm/mach-pnx8550/war.h
+++ b/arch/mips/include/asm/mach-pnx8550/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
index 58c76ec32a1..f751e3ec56f 100644
--- a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
@@ -45,7 +45,6 @@
 #define cpu_has_mips64r1                0
 #define cpu_has_mips64r2                0
 #define cpu_has_dsp                     0
-#define cpu_has_dsp2                    0
 #define cpu_has_mipsmt                  0
 #define cpu_has_userlocal               0
 #define cpu_has_nofpuex                 0
diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h
index c5651c8e58d..7ac05ecc512 100644
--- a/arch/mips/include/asm/mach-powertv/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -20,6 +20,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        1
 #define MIPS_CACHE_SYNC_WAR             1
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
index b15307597ee..c3e4d3a4c95 100644
--- a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
@@ -60,7 +60,6 @@
 #define cpu_has_mips64r2                0
 
 #define cpu_has_dsp                     0
-#define cpu_has_dsp2                    0
 #define cpu_has_mipsmt                  0
 
 /* #define cpu_has_nofpuex              ? */
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 1bfd489a370..3ddf187e98a 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        1
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
index f095c529c48..ccf54336353 100644
--- a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
@@ -30,7 +30,6 @@
 #define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
 #define cpu_has_ic_fills_f_dc   0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_nofpuex         0
 #define cpu_has_64bits          1
 #define cpu_has_mipsmt          0
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index a3dde98549b..948d3129a11 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -21,6 +21,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
deleted file mode 100644
index 7f3e3f9bd23..00000000000
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Chris Dearman
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
-
-
-/*
- * CPU feature overrides for MIPS boards
- */
-#ifdef CONFIG_CPU_MIPS32
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_4k_cache        1
-/* #define cpu_has_fpu          ? */
-/* #define cpu_has_32fpr        ? */
-#define cpu_has_counter         1
-/* #define cpu_has_watch        ? */
-#define cpu_has_divec           1
-#define cpu_has_vce             0
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-/* #define cpu_has_prefetch     ? */
-#define cpu_has_mcheck          1
-/* #define cpu_has_ejtag        ? */
-#ifdef CONFIG_CPU_HAS_LLSC
-#define cpu_has_llsc            1
-#else
-#define cpu_has_llsc            0
-#endif
-/* #define cpu_has_vtag_icache  ? */
-/* #define cpu_has_dc_aliases   ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_nofpuex         0
-/* #define cpu_has_64bits       ? */
-/* #define cpu_has_64bit_zero_reg ? */
-/* #define cpu_has_inclusive_pcaches ? */
-#define cpu_icache_snoops_remote_store 1
-#endif
-
-#ifdef CONFIG_CPU_MIPS64
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_4k_cache        1
-/* #define cpu_has_fpu          ? */
-/* #define cpu_has_32fpr        ? */
-#define cpu_has_counter         1
-/* #define cpu_has_watch        ? */
-#define cpu_has_divec           1
-#define cpu_has_vce             0
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-/* #define cpu_has_prefetch     ? */
-#define cpu_has_mcheck          1
-/* #define cpu_has_ejtag        ? */
-#define cpu_has_llsc            1
-/* #define cpu_has_vtag_icache  ? */
-/* #define cpu_has_dc_aliases   ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_nofpuex         0
-/* #define cpu_has_64bits       ? */
-/* #define cpu_has_64bit_zero_reg ? */
-/* #define cpu_has_inclusive_pcaches ? */
-#define cpu_icache_snoops_remote_store 1
-#endif
-
-#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h
deleted file mode 100644
index 652ea4c38cd..00000000000
--- a/arch/mips/include/asm/mach-sead3/irq.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __ASM_MACH_MIPS_IRQ_H
-#define __ASM_MACH_MIPS_IRQ_H
-
-#define NR_IRQS 256
-
-
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h
deleted file mode 100644
index 3dfbd8e7947..00000000000
--- a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Chris Dearman (chris@mips.com)
- * Copyright (C) 2007 Mips Technologies, Inc.
- */
-#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
-#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
-
-        .macro  kernel_entry_setup
-#ifdef CONFIG_MIPS_MT_SMTC
-        mfc0    t0, CP0_CONFIG
-        bgez    t0, 9f
-        mfc0    t0, CP0_CONFIG, 1
-        bgez    t0, 9f
-        mfc0    t0, CP0_CONFIG, 2
-        bgez    t0, 9f
-        mfc0    t0, CP0_CONFIG, 3
-        and     t0, 1<<2
-        bnez    t0, 0f
-9 :
-        /* Assume we came from YAMON... */
-        PTR_LA  v0, 0x9fc00534  /* YAMON print */
-        lw      v0, (v0)
-        move    a0, zero
-        PTR_LA  a1, nonmt_processor
-        jal     v0
-
-        PTR_LA  v0, 0x9fc00520  /* YAMON exit */
-        lw      v0, (v0)
-        li      a0, 1
-        jal     v0
-
-1 :     b       1b
-
-        __INITDATA
-nonmt_processor :
-        .asciz  "SMTC kernel requires the MT ASE to run\n"
-        __FINIT
-0 :
-#endif
-        .endm
-
-/*
- * Do SMP slave processor setup necessary before we can safely execute C code.
- */
-        .macro  smp_slave_setup
-        .endm
-
-#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h
deleted file mode 100644
index d068fc411f4..00000000000
--- a/arch/mips/include/asm/mach-sead3/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
-#define __ASM_MIPS_MACH_MIPS_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        1
-#define MIPS_CACHE_SYNC_WAR             1
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
index 92927b62b5a..1c1f92415b9 100644
--- a/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
@@ -26,7 +26,6 @@
 #define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
 #define cpu_has_dsp             0
-#define cpu_has_dsp2            0
 #define cpu_has_mipsmt          0
 #define cpu_has_userlocal       0
 #define cpu_icache_snoops_remote_store  0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 176f5b32dc6..743385d7b5f 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -33,6 +33,7 @@ extern int sb1250_m3_workaround_needed(void);
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-tx39xx/war.h b/arch/mips/include/asm/mach-tx39xx/war.h
index 6a52e653477..43381461635 100644
--- a/arch/mips/include/asm/mach-tx39xx/war.h
+++ b/arch/mips/include/asm/mach-tx39xx/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
index 7f5144c6ce2..275eaf92c74 100644
--- a/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
@@ -12,7 +12,6 @@
 #define cpu_has_vtag_icache     0
 #define cpu_has_ic_fills_f_dc   0
 #define cpu_has_dsp     0
-#define cpu_has_dsp2            0
 #define cpu_has_mipsmt  0
 #define cpu_has_userlocal       0
 
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
index 490867b03c8..5e6912fdd0e 100644
--- a/arch/mips/include/asm/mach-tx49xx/mangle-port.h
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -9,7 +9,7 @@
 #define ioswabb(a, x)           (x)
 #define __mem_ioswabb(a, x)     (x)
 #if defined(CONFIG_TOSHIBA_RBTX4939) && \
-        IS_ENABLED(CONFIG_SMC91X) && \
+        (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \
         defined(__BIG_ENDIAN)
 #define NEEDS_TXX9_IOSWABW
 extern u16 (*ioswabw)(volatile u16 *a, u16 x);
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index a8e2c586a18..39b5d1177c5 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     1
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-vr41xx/war.h b/arch/mips/include/asm/mach-vr41xx/war.h
index ffe31e73600..56a38926412 100644
--- a/arch/mips/include/asm/mach-vr41xx/war.h
+++ b/arch/mips/include/asm/mach-vr41xx/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
index e86084c0bd6..ac48629bb1c 100644
--- a/arch/mips/include/asm/mach-wrppmc/war.h
+++ b/arch/mips/include/asm/mach-wrppmc/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 6e23ceb0ba8..46c08563e53 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -93,4 +93,8 @@ extern void mips_pcibios_init(void);
 #define mips_pcibios_init() do { } while (0)
 #endif
 
+#ifdef CONFIG_KGDB
+extern void kgdb_config(void);
+#endif
+
 #endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index 66924481575..d11aa02a956 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -1,16 +1,31 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines for the Malta interrupt controller.
  *
- * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
- *      Carsten Langgaard <carstenl@mips.com>
- *      Steven J. Hill <sjhill@mips.com>
  */
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H
 
-#define MIPS_GIC_IRQ_BASE       (MIPS_CPU_IRQ_BASE + 8)
+#include <irq.h>
 
 /*
  * Interrupts 0..15 are used for Malta ISA compatible interrupts
@@ -63,6 +78,16 @@
 #define MSC01E_INT_PERFCTR      10
 #define MSC01E_INT_CPUCTR       11
 
+/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
+#define GIC_CPU_INT0            0 /* Core Interrupt 2   */
+#define GIC_CPU_INT1            1 /* .                  */
+#define GIC_CPU_INT2            2 /* .                  */
+#define GIC_CPU_INT3            3 /* .                  */
+#define GIC_CPU_INT4            4 /* .                  */
+#define GIC_CPU_INT5            5 /* Core Interrupt 5   */
+
+#define GIC_EXT_INTR(x)         x
+
 /* External Interrupts used for IPI */
 #define GIC_IPI_EXT_INTR_RESCHED_VPE0   16
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0   17
@@ -73,4 +98,10 @@
 #define GIC_IPI_EXT_INTR_RESCHED_VPE3   22
 #define GIC_IPI_EXT_INTR_CALLFNC_VPE3   23
 
+#define MIPS_GIC_IRQ_BASE       (MIPS_CPU_IRQ_BASE + 8)
+
+#ifndef __ASSEMBLY__
+extern void maltaint_init(void);
+#endif
+
 #endif /* !(_MIPS_MALTAINT_H) */
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
deleted file mode 100644
index d634d9a807f..00000000000
--- a/arch/mips/include/asm/mips-boards/sead3int.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
- *      Douglas Leung <douglas@mips.com>
- *      Steven J. Hill <sjhill@mips.com>
- */
-#ifndef _MIPS_SEAD3INT_H
-#define _MIPS_SEAD3INT_H
-
-/* SEAD-3 GIC address space definitions. */
-#define GIC_BASE_ADDR           0x1b1c0000
-#define GIC_ADDRSPACE_SZ        (128 * 1024)
-
-#define MIPS_GIC_IRQ_BASE       (MIPS_CPU_IRQ_BASE + 0)
-
-#endif /* !(_MIPS_SEAD3INT_H) */
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index 5b3cb8553e9..c9420aa97e3 100644
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -28,9 +28,6 @@
 #define read_c0_vpeconf0()              __read_32bit_c0_register($1, 2)
 #define write_c0_vpeconf0(val)          __write_32bit_c0_register($1, 2, val)
 
-#define read_c0_vpeconf1()              __read_32bit_c0_register($1, 3)
-#define write_c0_vpeconf1(val)          __write_32bit_c0_register($1, 3, val)
-
 #define read_c0_tcstatus()              __read_32bit_c0_register($2, 1)
 #define write_c0_tcstatus(val)          __write_32bit_c0_register($2, 1, val)
 
@@ -51,7 +48,7 @@
 #define CP0_VPECONF0            $1, 2
 #define CP0_VPECONF1            $1, 3
 #define CP0_YQMASK              $1, 4
-#define CP0_VPESCHEDULE         $1, 5
+#define CP0_VPESCHEDULE $1, 5
 #define CP0_VPESCHEFBK          $1, 6
 #define CP0_TCSTATUS            $2, 1
 #define CP0_TCBIND              $2, 2
@@ -127,14 +124,6 @@
 #define VPECONF0_XTC_SHIFT      21
 #define VPECONF0_XTC            (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
 
-/* VPEConf1 fields (per VPE) */
-#define VPECONF1_NCP1_SHIFT     0
-#define VPECONF1_NCP1           (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
-#define VPECONF1_NCP2_SHIFT     10
-#define VPECONF1_NCP2           (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
-#define VPECONF1_NCX_SHIFT      20
-#define VPECONF1_NCX            (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
-
 /* TCStatus fields (per TC) */
 #define TCSTATUS_TASID          (_ULCAST_(0xff))
 #define TCSTATUS_IXMT_SHIFT     10
@@ -361,8 +350,6 @@ do {									\
 #define write_vpe_c0_vpecontrol(val)    mttc0(1, 1, val)
 #define read_vpe_c0_vpeconf0()          mftc0(1, 2)
 #define write_vpe_c0_vpeconf0(val)      mttc0(1, 2, val)
-#define read_vpe_c0_vpeconf1()          mftc0(1, 3)
-#define write_vpe_c0_vpeconf1(val)      mttc0(1, 3, val)
 #define read_vpe_c0_count()             mftc0(9, 0)
 #define write_vpe_c0_count(val)         mttc0(9, 0, val)
 #define read_vpe_c0_status()            mftc0(12, 0)
diff --git a/arch/mips/include/asm/mipsprom.h b/arch/mips/include/asm/mipsprom.h
index e93943fabea..146d41b67ad 100644
--- a/arch/mips/include/asm/mipsprom.h
+++ b/arch/mips/include/asm/mipsprom.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MIPSPROM_H
-#define __ASM_MIPSPROM_H
+#ifndef __ASM_MIPS_PROM_H
+#define __ASM_MIPS_PROM_H
 
 #define PROM_RESET              0
 #define PROM_EXEC               1
@@ -73,4 +73,4 @@
 
 extern char *prom_getenv(char *);
 
-#endif /* __ASM_MIPSPROM_H */
+#endif /* __ASM_MIPS_PROM_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 7e4e6f8fab3..6a6f8a8f542 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -240,7 +240,7 @@
 #define PM_HUGE_MASK    PM_64M
 #elif defined(CONFIG_PAGE_SIZE_64KB)
 #define PM_HUGE_MASK    PM_256M
-#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+#elif defined(CONFIG_HUGETLB_PAGE)
 #error Bad page size configuration for hugetlbfs!
 #endif
 
@@ -458,8 +458,6 @@
 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 #define  CAUSEB_IV              23
 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
-#define  CAUSEB_PCI             26
-#define  CAUSEF_PCI             (_ULCAST_(1)   << 26)
 #define  CAUSEB_CE              28
 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 #define  CAUSEB_TI              30
@@ -592,16 +590,12 @@
 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
-#define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
-#define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 
 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 
-#define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
-
 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 
 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
@@ -977,6 +971,10 @@ do {									\
 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
 
+/* RM9000 PerfControl performance counter control register */
+#define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
+#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
+
 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
 
@@ -1008,26 +1006,22 @@ do {									\
 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
-#define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
-#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
-#define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
-#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
-#define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
-#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
-#define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
-#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
+
+/* RM9000 PerfCount performance counter register */
+#define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
+#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
 
 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
@@ -1104,7 +1098,7 @@ do {									\
 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
 
-/* BMIPS43xx */
+/* BMIPS4380 */
 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
 
@@ -1665,13 +1659,6 @@ __BUILD_SET_C0(config)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
-__BUILD_SET_C0(brcm_config_0)
-__BUILD_SET_C0(brcm_bus_pll)
-__BUILD_SET_C0(brcm_reset)
-__BUILD_SET_C0(brcm_cmt_intr)
-__BUILD_SET_C0(brcm_cmt_ctrl)
-__BUILD_SET_C0(brcm_config)
-__BUILD_SET_C0(brcm_mode)
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 45cfa1ad86a..73c0d45798d 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -37,6 +37,12 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
                 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
         } while (0)
 
+
+static inline unsigned long get_current_pgd(void)
+{
+        return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
+}
+
 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
 
 /*
@@ -72,6 +78,12 @@ extern unsigned long pgd_current[];
 #define ASID_INC        0x10
 #define ASID_MASK       0xff0
 
+#elif defined(CONFIG_CPU_RM9000)
+
+#define ASID_INC        0x1
+#define ASID_MASK       0xfff
+
+/* SMTC/34K debug hack - but maybe we'll keep it */
 #elif defined(CONFIG_MIPS_MT_SMTC)
 
 #define ASID_INC        0x1
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 44b705d0826..bc01a02cacd 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -2,7 +2,6 @@
 #define _ASM_MODULE_H
 
 #include <linux/list.h>
-#include <linux/elf.h>
 #include <asm/uaccess.h>
 
 struct mod_arch_specific {
@@ -10,7 +9,6 @@ struct mod_arch_specific {
         struct list_head dbe_list;
         const struct exception_table_entry *dbe_start;
         const struct exception_table_entry *dbe_end;
-        struct mips_hi16 *r_mips_hi16_list;
 };
 
 typedef uint8_t Elf64_Byte;             /* Type for a 8-bit quantity.  */
@@ -35,14 +33,11 @@ typedef struct {
 } Elf64_Mips_Rela;
 
 #ifdef CONFIG_32BIT
+
 #define Elf_Shdr        Elf32_Shdr
 #define Elf_Sym         Elf32_Sym
 #define Elf_Ehdr        Elf32_Ehdr
 #define Elf_Addr        Elf32_Addr
-#define Elf_Rel         Elf32_Rel
-#define Elf_Rela        Elf32_Rela
-#define ELF_R_TYPE(X)   ELF32_R_TYPE(X)
-#define ELF_R_SYM(X)    ELF32_R_SYM(X)
 
 #define Elf_Mips_Rel    Elf32_Rel
 #define Elf_Mips_Rela   Elf32_Rela
@@ -53,14 +48,11 @@ typedef struct {
 #endif
 
 #ifdef CONFIG_64BIT
+
 #define Elf_Shdr        Elf64_Shdr
 #define Elf_Sym         Elf64_Sym
 #define Elf_Ehdr        Elf64_Ehdr
 #define Elf_Addr        Elf64_Addr
-#define Elf_Rel         Elf64_Rel
-#define Elf_Rela        Elf64_Rela
-#define ELF_R_TYPE(X)   ELF64_R_TYPE(X)
-#define ELF_R_SYM(X)    ELF64_R_SYM(X)
 
 #define Elf_Mips_Rel    Elf64_Mips_Rel
 #define Elf_Mips_Rela   Elf64_Mips_Rela
@@ -82,9 +74,7 @@ search_module_dbetables(unsigned long addr)
 }
 #endif
 
-#ifdef CONFIG_CPU_BMIPS
-#define MODULE_PROC_FAMILY "BMIPS "
-#elif defined CONFIG_CPU_MIPS32_R1
+#ifdef CONFIG_CPU_MIPS32_R1
 #define MODULE_PROC_FAMILY "MIPS32_R1 "
 #elif defined CONFIG_CPU_MIPS32_R2
 #define MODULE_PROC_FAMILY "MIPS32_R2 "
@@ -120,18 +110,16 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "R10000 "
 #elif defined CONFIG_CPU_RM7000
 #define MODULE_PROC_FAMILY "RM7000 "
+#elif defined CONFIG_CPU_RM9000
+#define MODULE_PROC_FAMILY "RM9000 "
 #elif defined CONFIG_CPU_SB1
 #define MODULE_PROC_FAMILY "SB1 "
-#elif defined CONFIG_CPU_LOONGSON1
-#define MODULE_PROC_FAMILY "LOONGSON1 "
 #elif defined CONFIG_CPU_LOONGSON2
 #define MODULE_PROC_FAMILY "LOONGSON2 "
 #elif defined CONFIG_CPU_CAVIUM_OCTEON
 #define MODULE_PROC_FAMILY "OCTEON "
 #elif defined CONFIG_CPU_XLR
 #define MODULE_PROC_FAMILY "XLR "
-#elif defined CONFIG_CPU_XLP
-#define MODULE_PROC_FAMILY "XLP "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
deleted file mode 100644
index 42bfd5f1eee..00000000000
--- a/arch/mips/include/asm/netlogic/common.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NETLOGIC_COMMON_H_
-#define _NETLOGIC_COMMON_H_
-
-/*
- * Common SMP definitions
- */
-#define RESET_VEC_PHYS          0x1fc00000
-#define RESET_DATA_PHYS         (RESET_VEC_PHYS + (1<<10))
-#define BOOT_THREAD_MODE        0
-#define BOOT_NMI_LOCK           4
-#define BOOT_NMI_HANDLER        8
-
-#ifndef __ASSEMBLY__
-#include <linux/cpumask.h>
-#include <linux/spinlock.h>
-#include <asm/irq.h>
-#include <asm/mach-netlogic/multi-node.h>
-
-struct irq_desc;
-void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
-void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
-void nlm_smp_irq_init(int hwcpuid);
-void nlm_boot_secondary_cpus(void);
-int nlm_wakeup_secondary_cpus(void);
-void nlm_rmiboot_preboot(void);
-void nlm_percpu_init(int hwcpuid);
-
-static inline void
-nlm_set_nmi_handler(void *handler)
-{
-        char *reset_data;
-
-        reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
-        *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
-}
-
-/*
- * Misc.
- */
-unsigned int nlm_get_cpu_frequency(void);
-void nlm_node_init(int node);
-extern struct plat_smp_ops nlm_smp_ops;
-extern char nlm_reset_entry[], nlm_reset_entry_end[];
-
-extern unsigned int nlm_threads_per_core;
-extern cpumask_t nlm_cpumask;
-
-struct nlm_soc_info {
-        unsigned long coremask; /* cores enabled on the soc */
-        unsigned long ebase;
-        uint64_t irqmask;
-        uint64_t sysbase;       /* only for XLP */
-        uint64_t picbase;
-        spinlock_t piclock;
-};
-
-#define nlm_get_node(i)         (&nlm_nodes[i])
-#ifdef CONFIG_CPU_XLR
-#define nlm_current_node()      (&nlm_nodes[0])
-#else
-#define nlm_current_node()      (&nlm_nodes[nlm_nodeid()])
-#endif
-
-struct irq_data;
-uint64_t nlm_pci_irqmask(int node);
-void nlm_set_pic_extra_ack(int node, int irq,  void (*xack)(struct irq_data *));
-
-/*
- * The NR_IRQs is divided between nodes, each of them has a separate irq space
- */
-static inline int nlm_irq_to_xirq(int node, int irq)
-{
-        return node * NR_IRQS / NLM_NR_NODES + irq;
-}
-
-extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
-extern int nlm_cpu_ready[];
-#endif
-#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
deleted file mode 100644
index 72a0c788b47..00000000000
--- a/arch/mips/include/asm/netlogic/haldefs.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_HALDEFS_H__
-#define __NLM_HAL_HALDEFS_H__
-
-/*
- * This file contains platform specific memory mapped IO implementation
- * and will provide a way to read 32/64 bit memory mapped registers in
- * all ABIs
- */
-#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
-#error "o32 compile not supported on XLP yet"
-#endif
-/*
- * For o32 compilation, we have to disable interrupts and enable KX bit to
- * access 64 bit addresses or data.
- *
- * We need to disable interrupts because we save just the lower 32 bits of
- * registers in  interrupt handling. So if we get hit by an interrupt while
- * using the upper 32 bits of a register, we lose.
- */
-static inline uint32_t nlm_save_flags_kx(void)
-{
-        return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
-}
-
-static inline uint32_t nlm_save_flags_cop2(void)
-{
-        return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
-}
-
-static inline void nlm_restore_flags(uint32_t sr)
-{
-        write_c0_status(sr);
-}
-
-/*
- * The n64 implementations are simple, the o32 implementations when they
- * are added, will have to disable interrupts and enable KX before doing
- * 64 bit ops.
- */
-static inline uint32_t
-nlm_read_reg(uint64_t base, uint32_t reg)
-{
-        volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
-
-        return *addr;
-}
-
-static inline void
-nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
-{
-        volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
-
-        *addr = val;
-}
-
-static inline uint64_t
-nlm_read_reg64(uint64_t base, uint32_t reg)
-{
-        uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
-        volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
-
-        return *ptr;
-}
-
-static inline void
-nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
-{
-        uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
-        volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
-
-        *ptr = val;
-}
-
-/*
- * Routines to store 32/64 bit values to 64 bit addresses,
- * used when going thru XKPHYS to access registers
- */
-static inline uint32_t
-nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
-{
-        return nlm_read_reg(base, reg);
-}
-
-static inline void
-nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
-{
-        nlm_write_reg(base, reg, val);
-}
-
-static inline uint64_t
-nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
-{
-        return nlm_read_reg64(base, reg);
-}
-
-static inline void
-nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
-{
-        nlm_write_reg64(base, reg, val);
-}
-
-/* Location where IO base is mapped */
-extern uint64_t nlm_io_base;
-
-#if defined(CONFIG_CPU_XLP)
-static inline uint64_t
-nlm_pcicfg_base(uint32_t devoffset)
-{
-        return nlm_io_base + devoffset;
-}
-
-static inline uint64_t
-nlm_xkphys_map_pcibar0(uint64_t pcibase)
-{
-        uint64_t paddr;
-
-        paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
-        return (uint64_t)0x9000000000000000 | paddr;
-}
-#elif defined(CONFIG_CPU_XLR)
-
-static inline uint64_t
-nlm_mmio_base(uint32_t devoffset)
-{
-        return nlm_io_base + devoffset;
-}
-#endif
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h
index ed5993d9b7b..a85aadb6cfd 100644
--- a/arch/mips/include/asm/netlogic/interrupt.h
+++ b/arch/mips/include/asm/netlogic/interrupt.h
@@ -39,7 +39,7 @@
 
 #define IRQ_IPI_SMP_FUNCTION    3
 #define IRQ_IPI_SMP_RESCHEDULE  4
-#define IRQ_FMN                 5
+#define IRQ_MSGRING             6
 #define IRQ_TIMER               7
 
 #endif
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 32ba6d95d47..8c53d0ba4bf 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -73,146 +73,4 @@ static inline int hard_smp_processor_id(void)
         return __read_32bit_c0_register($15, 1) & 0x3ff;
 }
 
-static inline int nlm_nodeid(void)
-{
-        return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
-}
-
-static inline unsigned int nlm_core_id(void)
-{
-        return (read_c0_ebase() & 0x1c) >> 2;
-}
-
-static inline unsigned int nlm_thread_id(void)
-{
-        return read_c0_ebase() & 0x3;
-}
-
-#define __read_64bit_c2_split(source, sel)                              \
-({                                                                      \
-        unsigned long long __val;                                       \
-        unsigned long __flags;                                          \
-                                                                        \
-        local_irq_save(__flags);                                        \
-        if (sel == 0)                                                   \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmfc2\t%M0, " #source "\n\t"                   \
-                        "dsll\t%L0, %M0, 32\n\t"                        \
-                        "dsra\t%M0, %M0, 32\n\t"                        \
-                        "dsra\t%L0, %L0, 32\n\t"                        \
-                        ".set\tmips0\n\t"                               \
-                        : "=r" (__val));                                \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmfc2\t%M0, " #source ", " #sel "\n\t"         \
-                        "dsll\t%L0, %M0, 32\n\t"                        \
-                        "dsra\t%M0, %M0, 32\n\t"                        \
-                        "dsra\t%L0, %L0, 32\n\t"                        \
-                        ".set\tmips0\n\t"                               \
-                        : "=r" (__val));                                \
-        local_irq_restore(__flags);                                     \
-                                                                        \
-        __val;                                                          \
-})
-
-#define __write_64bit_c2_split(source, sel, val)                        \
-do {                                                                    \
-        unsigned long __flags;                                          \
-                                                                        \
-        local_irq_save(__flags);                                        \
-        if (sel == 0)                                                   \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dsll\t%L0, %L0, 32\n\t"                        \
-                        "dsrl\t%L0, %L0, 32\n\t"                        \
-                        "dsll\t%M0, %M0, 32\n\t"                        \
-                        "or\t%L0, %L0, %M0\n\t"                         \
-                        "dmtc2\t%L0, " #source "\n\t"                   \
-                        ".set\tmips0\n\t"                               \
-                        : : "r" (val));                                 \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dsll\t%L0, %L0, 32\n\t"                        \
-                        "dsrl\t%L0, %L0, 32\n\t"                        \
-                        "dsll\t%M0, %M0, 32\n\t"                        \
-                        "or\t%L0, %L0, %M0\n\t"                         \
-                        "dmtc2\t%L0, " #source ", " #sel "\n\t"         \
-                        ".set\tmips0\n\t"                               \
-                        : : "r" (val));                                 \
-        local_irq_restore(__flags);                                     \
-} while (0)
-
-#define __read_32bit_c2_register(source, sel)                           \
-({ uint32_t __res;                                                      \
-        if (sel == 0)                                                   \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips32\n\t"                              \
-                        "mfc2\t%0, " #source "\n\t"                     \
-                        ".set\tmips0\n\t"                               \
-                        : "=r" (__res));                                \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips32\n\t"                              \
-                        "mfc2\t%0, " #source ", " #sel "\n\t"           \
-                        ".set\tmips0\n\t"                               \
-                        : "=r" (__res));                                \
-        __res;                                                          \
-})
-
-#define __read_64bit_c2_register(source, sel)                           \
-({ unsigned long long __res;                                            \
-        if (sizeof(unsigned long) == 4)                                 \
-                __res = __read_64bit_c2_split(source, sel);             \
-        else if (sel == 0)                                              \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmfc2\t%0, " #source "\n\t"                    \
-                        ".set\tmips0\n\t"                               \
-                        : "=r" (__res));                                \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmfc2\t%0, " #source ", " #sel "\n\t"          \
-                        ".set\tmips0\n\t"                               \
-                        : "=r" (__res));                                \
-        __res;                                                          \
-})
-
-#define __write_64bit_c2_register(register, sel, value)                 \
-do {                                                                    \
-        if (sizeof(unsigned long) == 4)                                 \
-                __write_64bit_c2_split(register, sel, value);           \
-        else if (sel == 0)                                              \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmtc2\t%z0, " #register "\n\t"                 \
-                        ".set\tmips0\n\t"                               \
-                        : : "Jr" (value));                              \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmtc2\t%z0, " #register ", " #sel "\n\t"       \
-                        ".set\tmips0\n\t"                               \
-                        : : "Jr" (value));                              \
-} while (0)
-
-#define __write_32bit_c2_register(reg, sel, value)                      \
-({                                                                      \
-        if (sel == 0)                                                   \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips32\n\t"                              \
-                        "mtc2\t%z0, " #reg "\n\t"                       \
-                        ".set\tmips0\n\t"                               \
-                        : : "Jr" (value));                              \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips32\n\t"                              \
-                        "mtc2\t%z0, " #reg ", " #sel "\n\t"             \
-                        ".set\tmips0\n\t"                               \
-                        : : "Jr" (value));                              \
-})
-
 #endif /*_ASM_NLM_MIPS_EXTS_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
deleted file mode 100644
index ca95133f1ad..00000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_BRIDGE_H__
-#define __NLM_HAL_BRIDGE_H__
-
-/**
-* @file_name mio.h
-* @author Netlogic Microsystems
-* @brief Basic definitions of XLP memory and io subsystem
-*/
-
-/*
- * BRIDGE specific registers
- *
- * These registers start after the PCIe header, which has 0x40
- * standard entries
- */
-#define BRIDGE_MODE                     0x00
-#define BRIDGE_PCI_CFG_BASE             0x01
-#define BRIDGE_PCI_CFG_LIMIT            0x02
-#define BRIDGE_PCIE_CFG_BASE            0x03
-#define BRIDGE_PCIE_CFG_LIMIT           0x04
-#define BRIDGE_BUSNUM_BAR0              0x05
-#define BRIDGE_BUSNUM_BAR1              0x06
-#define BRIDGE_BUSNUM_BAR2              0x07
-#define BRIDGE_BUSNUM_BAR3              0x08
-#define BRIDGE_BUSNUM_BAR4              0x09
-#define BRIDGE_BUSNUM_BAR5              0x0a
-#define BRIDGE_BUSNUM_BAR6              0x0b
-#define BRIDGE_FLASH_BAR0               0x0c
-#define BRIDGE_FLASH_BAR1               0x0d
-#define BRIDGE_FLASH_BAR2               0x0e
-#define BRIDGE_FLASH_BAR3               0x0f
-#define BRIDGE_FLASH_LIMIT0             0x10
-#define BRIDGE_FLASH_LIMIT1             0x11
-#define BRIDGE_FLASH_LIMIT2             0x12
-#define BRIDGE_FLASH_LIMIT3             0x13
-
-#define BRIDGE_DRAM_BAR(i)              (0x14 + (i))
-#define BRIDGE_DRAM_BAR0                0x14
-#define BRIDGE_DRAM_BAR1                0x15
-#define BRIDGE_DRAM_BAR2                0x16
-#define BRIDGE_DRAM_BAR3                0x17
-#define BRIDGE_DRAM_BAR4                0x18
-#define BRIDGE_DRAM_BAR5                0x19
-#define BRIDGE_DRAM_BAR6                0x1a
-#define BRIDGE_DRAM_BAR7                0x1b
-
-#define BRIDGE_DRAM_LIMIT(i)            (0x1c + (i))
-#define BRIDGE_DRAM_LIMIT0              0x1c
-#define BRIDGE_DRAM_LIMIT1              0x1d
-#define BRIDGE_DRAM_LIMIT2              0x1e
-#define BRIDGE_DRAM_LIMIT3              0x1f
-#define BRIDGE_DRAM_LIMIT4              0x20
-#define BRIDGE_DRAM_LIMIT5              0x21
-#define BRIDGE_DRAM_LIMIT6              0x22
-#define BRIDGE_DRAM_LIMIT7              0x23
-
-#define BRIDGE_DRAM_NODE_TRANSLN0       0x24
-#define BRIDGE_DRAM_NODE_TRANSLN1       0x25
-#define BRIDGE_DRAM_NODE_TRANSLN2       0x26
-#define BRIDGE_DRAM_NODE_TRANSLN3       0x27
-#define BRIDGE_DRAM_NODE_TRANSLN4       0x28
-#define BRIDGE_DRAM_NODE_TRANSLN5       0x29
-#define BRIDGE_DRAM_NODE_TRANSLN6       0x2a
-#define BRIDGE_DRAM_NODE_TRANSLN7       0x2b
-#define BRIDGE_DRAM_CHNL_TRANSLN0       0x2c
-#define BRIDGE_DRAM_CHNL_TRANSLN1       0x2d
-#define BRIDGE_DRAM_CHNL_TRANSLN2       0x2e
-#define BRIDGE_DRAM_CHNL_TRANSLN3       0x2f
-#define BRIDGE_DRAM_CHNL_TRANSLN4       0x30
-#define BRIDGE_DRAM_CHNL_TRANSLN5       0x31
-#define BRIDGE_DRAM_CHNL_TRANSLN6       0x32
-#define BRIDGE_DRAM_CHNL_TRANSLN7       0x33
-#define BRIDGE_PCIEMEM_BASE0            0x34
-#define BRIDGE_PCIEMEM_BASE1            0x35
-#define BRIDGE_PCIEMEM_BASE2            0x36
-#define BRIDGE_PCIEMEM_BASE3            0x37
-#define BRIDGE_PCIEMEM_LIMIT0           0x38
-#define BRIDGE_PCIEMEM_LIMIT1           0x39
-#define BRIDGE_PCIEMEM_LIMIT2           0x3a
-#define BRIDGE_PCIEMEM_LIMIT3           0x3b
-#define BRIDGE_PCIEIO_BASE0             0x3c
-#define BRIDGE_PCIEIO_BASE1             0x3d
-#define BRIDGE_PCIEIO_BASE2             0x3e
-#define BRIDGE_PCIEIO_BASE3             0x3f
-#define BRIDGE_PCIEIO_LIMIT0            0x40
-#define BRIDGE_PCIEIO_LIMIT1            0x41
-#define BRIDGE_PCIEIO_LIMIT2            0x42
-#define BRIDGE_PCIEIO_LIMIT3            0x43
-#define BRIDGE_PCIEMEM_BASE4            0x44
-#define BRIDGE_PCIEMEM_BASE5            0x45
-#define BRIDGE_PCIEMEM_BASE6            0x46
-#define BRIDGE_PCIEMEM_LIMIT4           0x47
-#define BRIDGE_PCIEMEM_LIMIT5           0x48
-#define BRIDGE_PCIEMEM_LIMIT6           0x49
-#define BRIDGE_PCIEIO_BASE4             0x4a
-#define BRIDGE_PCIEIO_BASE5             0x4b
-#define BRIDGE_PCIEIO_BASE6             0x4c
-#define BRIDGE_PCIEIO_LIMIT4            0x4d
-#define BRIDGE_PCIEIO_LIMIT5            0x4e
-#define BRIDGE_PCIEIO_LIMIT6            0x4f
-#define BRIDGE_NBU_EVENT_CNT_CTL        0x50
-#define BRIDGE_EVNTCTR1_LOW             0x51
-#define BRIDGE_EVNTCTR1_HI              0x52
-#define BRIDGE_EVNT_CNT_CTL2            0x53
-#define BRIDGE_EVNTCTR2_LOW             0x54
-#define BRIDGE_EVNTCTR2_HI              0x55
-#define BRIDGE_TRACEBUF_MATCH0          0x56
-#define BRIDGE_TRACEBUF_MATCH1          0x57
-#define BRIDGE_TRACEBUF_MATCH_LOW       0x58
-#define BRIDGE_TRACEBUF_MATCH_HI        0x59
-#define BRIDGE_TRACEBUF_CTRL            0x5a
-#define BRIDGE_TRACEBUF_INIT            0x5b
-#define BRIDGE_TRACEBUF_ACCESS          0x5c
-#define BRIDGE_TRACEBUF_READ_DATA0      0x5d
-#define BRIDGE_TRACEBUF_READ_DATA1      0x5d
-#define BRIDGE_TRACEBUF_READ_DATA2      0x5f
-#define BRIDGE_TRACEBUF_READ_DATA3      0x60
-#define BRIDGE_TRACEBUF_STATUS          0x61
-#define BRIDGE_ADDRESS_ERROR0           0x62
-#define BRIDGE_ADDRESS_ERROR1           0x63
-#define BRIDGE_ADDRESS_ERROR2           0x64
-#define BRIDGE_TAG_ECC_ADDR_ERROR0      0x65
-#define BRIDGE_TAG_ECC_ADDR_ERROR1      0x66
-#define BRIDGE_TAG_ECC_ADDR_ERROR2      0x67
-#define BRIDGE_LINE_FLUSH0              0x68
-#define BRIDGE_LINE_FLUSH1              0x69
-#define BRIDGE_NODE_ID                  0x6a
-#define BRIDGE_ERROR_INTERRUPT_EN       0x6b
-#define BRIDGE_PCIE0_WEIGHT             0x2c0
-#define BRIDGE_PCIE1_WEIGHT             0x2c1
-#define BRIDGE_PCIE2_WEIGHT             0x2c2
-#define BRIDGE_PCIE3_WEIGHT             0x2c3
-#define BRIDGE_USB_WEIGHT               0x2c4
-#define BRIDGE_NET_WEIGHT               0x2c5
-#define BRIDGE_POE_WEIGHT               0x2c6
-#define BRIDGE_CMS_WEIGHT               0x2c7
-#define BRIDGE_DMAENG_WEIGHT            0x2c8
-#define BRIDGE_SEC_WEIGHT               0x2c9
-#define BRIDGE_COMP_WEIGHT              0x2ca
-#define BRIDGE_GIO_WEIGHT               0x2cb
-#define BRIDGE_FLASH_WEIGHT             0x2cc
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_bridge_reg(b, r)       nlm_read_reg(b, r)
-#define nlm_write_bridge_reg(b, r, v)   nlm_write_reg(b, r, v)
-#define nlm_get_bridge_pcibase(node)    \
-                        nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
-#define nlm_get_bridge_regbase(node)    \
-                        (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-#endif /* __ASSEMBLY__ */
-#endif /* __NLM_HAL_BRIDGE_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
deleted file mode 100644
index 7b63a6b722a..00000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_CPUCONTROL_H__
-#define __NLM_HAL_CPUCONTROL_H__
-
-#define CPU_BLOCKID_IFU         0
-#define CPU_BLOCKID_ICU         1
-#define CPU_BLOCKID_IEU         2
-#define CPU_BLOCKID_LSU         3
-#define CPU_BLOCKID_MMU         4
-#define CPU_BLOCKID_PRF         5
-#define CPU_BLOCKID_SCH         7
-#define CPU_BLOCKID_SCU         8
-#define CPU_BLOCKID_FPU         9
-#define CPU_BLOCKID_MAP         10
-
-#define LSU_DEFEATURE           0x304
-#define LSU_DEBUG_ADDR          0x305
-#define LSU_DEBUG_DATA0         0x306
-#define LSU_CERRLOG_REGID       0x309
-#define SCHED_DEFEATURE         0x700
-
-/* Offsets of interest from the 'MAP' Block */
-#define MAP_THREADMODE                  0x00
-#define MAP_EXT_EBASE_ENABLE            0x04
-#define MAP_CCDI_CONFIG                 0x08
-#define MAP_THRD0_CCDI_STATUS           0x0c
-#define MAP_THRD1_CCDI_STATUS           0x10
-#define MAP_THRD2_CCDI_STATUS           0x14
-#define MAP_THRD3_CCDI_STATUS           0x18
-#define MAP_THRD0_DEBUG_MODE            0x1c
-#define MAP_THRD1_DEBUG_MODE            0x20
-#define MAP_THRD2_DEBUG_MODE            0x24
-#define MAP_THRD3_DEBUG_MODE            0x28
-#define MAP_MISC_STATE                  0x60
-#define MAP_DEBUG_READ_CTL              0x64
-#define MAP_DEBUG_READ_REG0             0x68
-#define MAP_DEBUG_READ_REG1             0x6c
-
-#define MMU_SETUP               0x400
-#define MMU_LFSRSEED            0x401
-#define MMU_HPW_NUM_PAGE_LVL    0x410
-#define MMU_PGWKR_PGDBASE       0x411
-#define MMU_PGWKR_PGDSHFT       0x412
-#define MMU_PGWKR_PGDMASK       0x413
-#define MMU_PGWKR_PUDSHFT       0x414
-#define MMU_PGWKR_PUDMASK       0x415
-#define MMU_PGWKR_PMDSHFT       0x416
-#define MMU_PGWKR_PMDMASK       0x417
-#define MMU_PGWKR_PTESHFT       0x418
-#define MMU_PGWKR_PTEMASK       0x419
-
-#endif /* __NLM_CPUCONTROL_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
deleted file mode 100644
index 2c63f975464..00000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_IOMAP_H__
-#define __NLM_HAL_IOMAP_H__
-
-#define XLP_DEFAULT_IO_BASE             0x18000000
-#define XLP_DEFAULT_PCI_ECFG_BASE       XLP_DEFAULT_IO_BASE
-#define XLP_DEFAULT_PCI_CFG_BASE        0x1c000000
-
-#define NMI_BASE                        0xbfc00000
-#define XLP_IO_CLK                      133333333
-
-#define XLP_PCIE_CFG_SIZE               0x1000          /* 4K */
-#define XLP_PCIE_DEV_BLK_SIZE           (8 * XLP_PCIE_CFG_SIZE)
-#define XLP_PCIE_BUS_BLK_SIZE           (256 * XLP_PCIE_DEV_BLK_SIZE)
-#define XLP_IO_SIZE                     (64 << 20)      /* ECFG space size */
-#define XLP_IO_PCI_HDRSZ                0x100
-#define XLP_IO_DEV(node, dev)           ((dev) + (node) * 8)
-#define XLP_HDR_OFFSET(node, bus, dev, fn)      (((bus) << 20) | \
-                                ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
-
-#define XLP_IO_BRIDGE_OFFSET(node)      XLP_HDR_OFFSET(node, 0, 0, 0)
-/* coherent inter chip */
-#define XLP_IO_CIC0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 1)
-#define XLP_IO_CIC1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 2)
-#define XLP_IO_CIC2_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 3)
-#define XLP_IO_PIC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 0, 4)
-
-#define XLP_IO_PCIE_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 1, i)
-#define XLP_IO_PCIE0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 0)
-#define XLP_IO_PCIE1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 1)
-#define XLP_IO_PCIE2_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 2)
-#define XLP_IO_PCIE3_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 3)
-
-#define XLP_IO_USB_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 2, i)
-#define XLP_IO_USB_EHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 0)
-#define XLP_IO_USB_OHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 1)
-#define XLP_IO_USB_OHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 2)
-#define XLP_IO_USB_EHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 3)
-#define XLP_IO_USB_OHCI2_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 4)
-#define XLP_IO_USB_OHCI3_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 5)
-
-#define XLP_IO_NAE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 0)
-#define XLP_IO_POE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 1)
-
-#define XLP_IO_CMS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 4, 0)
-
-#define XLP_IO_DMA_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 1)
-#define XLP_IO_SEC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 2)
-#define XLP_IO_CMP_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 3)
-
-#define XLP_IO_UART_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 6, i)
-#define XLP_IO_UART0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 0)
-#define XLP_IO_UART1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 1)
-#define XLP_IO_I2C_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 6, 2 + i)
-#define XLP_IO_I2C0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 2)
-#define XLP_IO_I2C1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 3)
-#define XLP_IO_GPIO_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 4)
-/* system management */
-#define XLP_IO_SYS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 6, 5)
-#define XLP_IO_JTAG_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 6)
-
-#define XLP_IO_NOR_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 0)
-#define XLP_IO_NAND_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 7, 1)
-#define XLP_IO_SPI_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 2)
-/* SD flash */
-#define XLP_IO_SD_OFFSET(node)          XLP_HDR_OFFSET(node, 0, 7, 3)
-#define XLP_IO_MMC_OFFSET(node, slot)   \
-                ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
-
-/* PCI config header register id's */
-#define XLP_PCI_CFGREG0                 0x00
-#define XLP_PCI_CFGREG1                 0x01
-#define XLP_PCI_CFGREG2                 0x02
-#define XLP_PCI_CFGREG3                 0x03
-#define XLP_PCI_CFGREG4                 0x04
-#define XLP_PCI_CFGREG5                 0x05
-#define XLP_PCI_DEVINFO_REG0            0x30
-#define XLP_PCI_DEVINFO_REG1            0x31
-#define XLP_PCI_DEVINFO_REG2            0x32
-#define XLP_PCI_DEVINFO_REG3            0x33
-#define XLP_PCI_DEVINFO_REG4            0x34
-#define XLP_PCI_DEVINFO_REG5            0x35
-#define XLP_PCI_DEVINFO_REG6            0x36
-#define XLP_PCI_DEVINFO_REG7            0x37
-#define XLP_PCI_DEVSCRATCH_REG0         0x38
-#define XLP_PCI_DEVSCRATCH_REG1         0x39
-#define XLP_PCI_DEVSCRATCH_REG2         0x3a
-#define XLP_PCI_DEVSCRATCH_REG3         0x3b
-#define XLP_PCI_MSGSTN_REG              0x3c
-#define XLP_PCI_IRTINFO_REG             0x3d
-#define XLP_PCI_UCODEINFO_REG           0x3e
-#define XLP_PCI_SBB_WT_REG              0x3f
-
-/* PCI IDs for SoC device */
-#define PCI_VENDOR_NETLOGIC             0x184e
-
-#define PCI_DEVICE_ID_NLM_ROOT          0x1001
-#define PCI_DEVICE_ID_NLM_ICI           0x1002
-#define PCI_DEVICE_ID_NLM_PIC           0x1003
-#define PCI_DEVICE_ID_NLM_PCIE          0x1004
-#define PCI_DEVICE_ID_NLM_EHCI          0x1007
-#define PCI_DEVICE_ID_NLM_OHCI          0x1008
-#define PCI_DEVICE_ID_NLM_NAE           0x1009
-#define PCI_DEVICE_ID_NLM_POE           0x100A
-#define PCI_DEVICE_ID_NLM_FMN           0x100B
-#define PCI_DEVICE_ID_NLM_RAID          0x100D
-#define PCI_DEVICE_ID_NLM_SAE           0x100D
-#define PCI_DEVICE_ID_NLM_RSA           0x100E
-#define PCI_DEVICE_ID_NLM_CMP           0x100F
-#define PCI_DEVICE_ID_NLM_UART          0x1010
-#define PCI_DEVICE_ID_NLM_I2C           0x1011
-#define PCI_DEVICE_ID_NLM_NOR           0x1015
-#define PCI_DEVICE_ID_NLM_NAND          0x1016
-#define PCI_DEVICE_ID_NLM_MMC           0x1018
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_pci_reg(b, r)          nlm_read_reg(b, r)
-#define nlm_write_pci_reg(b, r, v)      nlm_write_reg(b, r, v)
-
-#endif /* !__ASSEMBLY */
-
-#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
deleted file mode 100644
index 66c323d1bd7..00000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_PCIBUS_H__
-#define __NLM_HAL_PCIBUS_H__
-
-/* PCIE Memory and IO regions */
-#define PCIE_MEM_BASE                   0xd0000000ULL
-#define PCIE_MEM_LIMIT                  0xdfffffffULL
-#define PCIE_IO_BASE                    0x14000000ULL
-#define PCIE_IO_LIMIT                   0x15ffffffULL
-
-#define PCIE_BRIDGE_CMD                 0x1
-#define PCIE_BRIDGE_MSI_CAP             0x14
-#define PCIE_BRIDGE_MSI_ADDRL           0x15
-#define PCIE_BRIDGE_MSI_ADDRH           0x16
-#define PCIE_BRIDGE_MSI_DATA            0x17
-
-/* XLP Global PCIE configuration space registers */
-#define PCIE_BYTE_SWAP_MEM_BASE         0x247
-#define PCIE_BYTE_SWAP_MEM_LIM          0x248
-#define PCIE_BYTE_SWAP_IO_BASE          0x249
-#define PCIE_BYTE_SWAP_IO_LIM           0x24A
-#define PCIE_MSI_STATUS                 0x25A
-#define PCIE_MSI_EN                     0x25B
-#define PCIE_INT_EN0                    0x261
-
-/* PCIE_MSI_EN */
-#define PCIE_MSI_VECTOR_INT_EN          0xFFFFFFFF
-
-/* PCIE_INT_EN0 */
-#define PCIE_MSI_INT_EN                 (1 << 9)
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_pcie_reg(b, r)         nlm_read_reg(b, r)
-#define nlm_write_pcie_reg(b, r, v)     nlm_write_reg(b, r, v)
-#define nlm_get_pcie_base(node, inst)   \
-                        nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
-#define nlm_get_pcie_regbase(node, inst)        \
-                        (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
-
-int xlp_pcie_link_irt(int link);
-#endif
-#endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
deleted file mode 100644
index b2e53a5383a..00000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NLM_HAL_PIC_H
-#define _NLM_HAL_PIC_H
-
-/* PIC Specific registers */
-#define PIC_CTRL                0x00
-
-/* PIC control register defines */
-#define PIC_CTRL_ITV            32 /* interrupt timeout value */
-#define PIC_CTRL_ICI            19 /* ICI interrupt timeout enable */
-#define PIC_CTRL_ITE            18 /* interrupt timeout enable */
-#define PIC_CTRL_STE            10 /* system timer interrupt enable */
-#define PIC_CTRL_WWR1           8  /* watchdog 1 wraparound count for reset */
-#define PIC_CTRL_WWR0           6  /* watchdog 0 wraparound count for reset */
-#define PIC_CTRL_WWN1           4  /* watchdog 1 wraparound count for NMI */
-#define PIC_CTRL_WWN0           2  /* watchdog 0 wraparound count for NMI */
-#define PIC_CTRL_WTE            0  /* watchdog timer enable */
-
-/* PIC Status register defines */
-#define PIC_ICI_STATUS          33 /* ICI interrupt timeout status */
-#define PIC_ITE_STATUS          32 /* interrupt timeout status */
-#define PIC_STS_STATUS          4  /* System timer interrupt status */
-#define PIC_WNS_STATUS          2  /* NMI status for watchdog timers */
-#define PIC_WIS_STATUS          0  /* Interrupt status for watchdog timers */
-
-/* PIC IPI control register offsets */
-#define PIC_IPICTRL_NMI         32
-#define PIC_IPICTRL_RIV         20 /* received interrupt vector */
-#define PIC_IPICTRL_IDB         16 /* interrupt destination base */
-#define PIC_IPICTRL_DTE          0 /* interrupt destination thread enables */
-
-/* PIC IRT register offsets */
-#define PIC_IRT_ENABLE          31
-#define PIC_IRT_NMI             29
-#define PIC_IRT_SCH             28 /* Scheduling scheme */
-#define PIC_IRT_RVEC            20 /* Interrupt receive vectors */
-#define PIC_IRT_DT              19 /* Destination type */
-#define PIC_IRT_DB              16 /* Destination base */
-#define PIC_IRT_DTE             0  /* Destination thread enables */
-
-#define PIC_BYTESWAP            0x02
-#define PIC_STATUS              0x04
-#define PIC_INTR_TIMEOUT        0x06
-#define PIC_ICI0_INTR_TIMEOUT   0x08
-#define PIC_ICI1_INTR_TIMEOUT   0x0a
-#define PIC_ICI2_INTR_TIMEOUT   0x0c
-#define PIC_IPI_CTL             0x0e
-#define PIC_INT_ACK             0x10
-#define PIC_INT_PENDING0        0x12
-#define PIC_INT_PENDING1        0x14
-#define PIC_INT_PENDING2        0x16
-
-#define PIC_WDOG0_MAXVAL        0x18
-#define PIC_WDOG0_COUNT         0x1a
-#define PIC_WDOG0_ENABLE0       0x1c
-#define PIC_WDOG0_ENABLE1       0x1e
-#define PIC_WDOG0_BEATCMD       0x20
-#define PIC_WDOG0_BEAT0         0x22
-#define PIC_WDOG0_BEAT1         0x24
-
-#define PIC_WDOG1_MAXVAL        0x26
-#define PIC_WDOG1_COUNT         0x28
-#define PIC_WDOG1_ENABLE0       0x2a
-#define PIC_WDOG1_ENABLE1       0x2c
-#define PIC_WDOG1_BEATCMD       0x2e
-#define PIC_WDOG1_BEAT0         0x30
-#define PIC_WDOG1_BEAT1         0x32
-
-#define PIC_WDOG_MAXVAL(i)      (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
-#define PIC_WDOG_COUNT(i)       (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
-#define PIC_WDOG_ENABLE0(i)     (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
-#define PIC_WDOG_ENABLE1(i)     (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
-#define PIC_WDOG_BEATCMD(i)     (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
-#define PIC_WDOG_BEAT0(i)       (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
-#define PIC_WDOG_BEAT1(i)       (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
-
-#define PIC_TIMER0_MAXVAL    0x34
-#define PIC_TIMER1_MAXVAL    0x36
-#define PIC_TIMER2_MAXVAL    0x38
-#define PIC_TIMER3_MAXVAL    0x3a
-#define PIC_TIMER4_MAXVAL    0x3c
-#define PIC_TIMER5_MAXVAL    0x3e
-#define PIC_TIMER6_MAXVAL    0x40
-#define PIC_TIMER7_MAXVAL    0x42
-#define PIC_TIMER_MAXVAL(i)  (PIC_TIMER0_MAXVAL + ((i) * 2))
-
-#define PIC_TIMER0_COUNT     0x44
-#define PIC_TIMER1_COUNT     0x46
-#define PIC_TIMER2_COUNT     0x48
-#define PIC_TIMER3_COUNT     0x4a
-#define PIC_TIMER4_COUNT     0x4c
-#define PIC_TIMER5_COUNT     0x4e
-#define PIC_TIMER6_COUNT     0x50
-#define PIC_TIMER7_COUNT     0x52
-#define PIC_TIMER_COUNT(i)   (PIC_TIMER0_COUNT + ((i) * 2))
-
-#define PIC_ITE0_N0_N1          0x54
-#define PIC_ITE1_N0_N1          0x58
-#define PIC_ITE2_N0_N1          0x5c
-#define PIC_ITE3_N0_N1          0x60
-#define PIC_ITE4_N0_N1          0x64
-#define PIC_ITE5_N0_N1          0x68
-#define PIC_ITE6_N0_N1          0x6c
-#define PIC_ITE7_N0_N1          0x70
-#define PIC_ITE_N0_N1(i)        (PIC_ITE0_N0_N1 + ((i) * 4))
-
-#define PIC_ITE0_N2_N3          0x56
-#define PIC_ITE1_N2_N3          0x5a
-#define PIC_ITE2_N2_N3          0x5e
-#define PIC_ITE3_N2_N3          0x62
-#define PIC_ITE4_N2_N3          0x66
-#define PIC_ITE5_N2_N3          0x6a
-#define PIC_ITE6_N2_N3          0x6e
-#define PIC_ITE7_N2_N3          0x72
-#define PIC_ITE_N2_N3(i)        (PIC_ITE0_N2_N3 + ((i) * 4))
-
-#define PIC_IRT0                0x74
-#define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
-
-#define TIMER_CYCLES_MAXVAL     0xffffffffffffffffULL
-
-/*
- *    IRT Map
- */
-#define PIC_NUM_IRTS            160
-
-#define PIC_IRT_WD_0_INDEX      0
-#define PIC_IRT_WD_1_INDEX      1
-#define PIC_IRT_WD_NMI_0_INDEX  2
-#define PIC_IRT_WD_NMI_1_INDEX  3
-#define PIC_IRT_TIMER_0_INDEX   4
-#define PIC_IRT_TIMER_1_INDEX   5
-#define PIC_IRT_TIMER_2_INDEX   6
-#define PIC_IRT_TIMER_3_INDEX   7
-#define PIC_IRT_TIMER_4_INDEX   8
-#define PIC_IRT_TIMER_5_INDEX   9
-#define PIC_IRT_TIMER_6_INDEX   10
-#define PIC_IRT_TIMER_7_INDEX   11
-#define PIC_IRT_CLOCK_INDEX     PIC_IRT_TIMER_7_INDEX
-#define PIC_IRT_TIMER_INDEX(num)        ((num) + PIC_IRT_TIMER_0_INDEX)
-
-
-/* 11 and 12 */
-#define PIC_NUM_MSG_Q_IRTS      32
-#define PIC_IRT_MSG_Q0_INDEX    12
-#define PIC_IRT_MSG_Q_INDEX(qid)        ((qid) + PIC_IRT_MSG_Q0_INDEX)
-/* 12 to 43 */
-#define PIC_IRT_MSG_0_INDEX     44
-#define PIC_IRT_MSG_1_INDEX     45
-/* 44 and 45 */
-#define PIC_NUM_PCIE_MSIX_IRTS  32
-#define PIC_IRT_PCIE_MSIX_0_INDEX       46
-#define PIC_IRT_PCIE_MSIX_INDEX(num)    ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
-/* 46 to 77 */
-#define PIC_NUM_PCIE_LINK_IRTS          4
-#define PIC_IRT_PCIE_LINK_0_INDEX       78
-#define PIC_IRT_PCIE_LINK_1_INDEX       79
-#define PIC_IRT_PCIE_LINK_2_INDEX       80
-#define PIC_IRT_PCIE_LINK_3_INDEX       81
-#define PIC_IRT_PCIE_LINK_INDEX(num)    ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
-/* 78 to 81 */
-#define PIC_NUM_NA_IRTS                 32
-/* 82 to 113 */
-#define PIC_IRT_NA_0_INDEX              82
-#define PIC_IRT_NA_INDEX(num)           ((num) + PIC_IRT_NA_0_INDEX)
-#define PIC_IRT_POE_INDEX               114
-
-#define PIC_NUM_USB_IRTS                6
-#define PIC_IRT_USB_0_INDEX             115
-#define PIC_IRT_EHCI_0_INDEX            115
-#define PIC_IRT_OHCI_0_INDEX            116
-#define PIC_IRT_OHCI_1_INDEX            117
-#define PIC_IRT_EHCI_1_INDEX            118
-#define PIC_IRT_OHCI_2_INDEX            119
-#define PIC_IRT_OHCI_3_INDEX            120
-#define PIC_IRT_USB_INDEX(num)          ((num) + PIC_IRT_USB_0_INDEX)
-/* 115 to 120 */
-#define PIC_IRT_GDX_INDEX               121
-#define PIC_IRT_SEC_INDEX               122
-#define PIC_IRT_RSA_INDEX               123
-
-#define PIC_NUM_COMP_IRTS               4
-#define PIC_IRT_COMP_0_INDEX            124
-#define PIC_IRT_COMP_INDEX(num)         ((num) + PIC_IRT_COMP_0_INDEX)
-/* 124 to 127 */
-#define PIC_IRT_GBU_INDEX               128
-#define PIC_IRT_ICC_0_INDEX             129 /* ICC - Inter Chip Coherency */
-#define PIC_IRT_ICC_1_INDEX             130
-#define PIC_IRT_ICC_2_INDEX             131
-#define PIC_IRT_CAM_INDEX               132
-#define PIC_IRT_UART_0_INDEX            133
-#define PIC_IRT_UART_1_INDEX            134
-#define PIC_IRT_I2C_0_INDEX             135
-#define PIC_IRT_I2C_1_INDEX             136
-#define PIC_IRT_SYS_0_INDEX             137
-#define PIC_IRT_SYS_1_INDEX             138
-#define PIC_IRT_JTAG_INDEX              139
-#define PIC_IRT_PIC_INDEX               140
-#define PIC_IRT_NBU_INDEX               141
-#define PIC_IRT_TCU_INDEX               142
-#define PIC_IRT_GCU_INDEX               143 /* GBC - Global Coherency */
-#define PIC_IRT_DMC_0_INDEX             144
-#define PIC_IRT_DMC_1_INDEX             145
-
-#define PIC_NUM_GPIO_IRTS               4
-#define PIC_IRT_GPIO_0_INDEX            146
-#define PIC_IRT_GPIO_INDEX(num)         ((num) + PIC_IRT_GPIO_0_INDEX)
-
-/* 146 to 149 */
-#define PIC_IRT_NOR_INDEX               150
-#define PIC_IRT_NAND_INDEX              151
-#define PIC_IRT_SPI_INDEX               152
-#define PIC_IRT_MMC_INDEX               153
-
-#define PIC_CLOCK_TIMER                 7
-#define PIC_IRQ_BASE                    8
-
-#if !defined(LOCORE) && !defined(__ASSEMBLY__)
-
-#define PIC_IRT_FIRST_IRQ               (PIC_IRQ_BASE)
-#define PIC_IRT_LAST_IRQ                63
-#define PIC_IRQ_IS_IRT(irq)             ((irq) >= PIC_IRT_FIRST_IRQ)
-
-/*
- *   Misc
- */
-#define PIC_IRT_VALID                   1
-#define PIC_LOCAL_SCHEDULING            1
-#define PIC_GLOBAL_SCHEDULING           0
-
-#define nlm_read_pic_reg(b, r)  nlm_read_reg64(b, r)
-#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
-#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
-#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-/* IRT and h/w interrupt routines */
-static inline int
-nlm_pic_read_irt(uint64_t base, int irt_index)
-{
-        return nlm_read_pic_reg(base, PIC_IRT(irt_index));
-}
-
-static inline void
-nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
-{
-        uint64_t val;
-
-        val = nlm_read_pic_reg(base, PIC_IRT(irt));
-        /* clear cpuset and mask */
-        val &= ~((0x7ull << 16) | 0xffff);
-        /* set DB, cpuset and cpumask */
-        val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf));
-        nlm_write_pic_reg(base, PIC_IRT(irt), val);
-}
-
-static inline void
-nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
-        int sch, int vec, int dt, int db, int dte)
-{
-        uint64_t val;
-
-        val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
-                        ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
-                        ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
-                        (dte & 0xffff);
-
-        nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
-}
-
-static inline void
-nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
-        int sch, int vec, int cpu)
-{
-        nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
-                (cpu >> 4),             /* thread group */
-                1 << (cpu & 0xf));      /* thread mask */
-}
-
-static inline uint64_t
-nlm_pic_read_timer(uint64_t base, int timer)
-{
-        return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
-}
-
-static inline void
-nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
-{
-        nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
-}
-
-static inline void
-nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
-{
-        uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
-        int en;
-
-        en = (irq > 0);
-        nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
-        nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
-                en, 0, 0, irq, cpu);
-
-        /* enable the timer */
-        pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
-        nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
-}
-
-static inline void
-nlm_pic_enable_irt(uint64_t base, int irt)
-{
-        uint64_t reg;
-
-        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
-        nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
-}
-
-static inline void
-nlm_pic_disable_irt(uint64_t base, int irt)
-{
-        uint64_t reg;
-
-        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
-        nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
-}
-
-static inline void
-nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
-{
-        uint64_t ipi;
-
-        ipi = (nmi << 31) | (irq << 20);
-        ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
-        nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
-}
-
-static inline void
-nlm_pic_ack(uint64_t base, int irt_num)
-{
-        nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
-
-        /* Ack the Status register for Watchdog & System timers */
-        if (irt_num < 12)
-                nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
-}
-
-static inline void
-nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
-{
-        nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt);
-}
-
-int nlm_irq_to_irt(int irq);
-
-#endif /* __ASSEMBLY__ */
-#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
deleted file mode 100644
index 258e8cc00e9..00000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_SYS_H__
-#define __NLM_HAL_SYS_H__
-
-/**
-* @file_name sys.h
-* @author Netlogic Microsystems
-* @brief HAL for System configuration registers
-*/
-#define SYS_CHIP_RESET                          0x00
-#define SYS_POWER_ON_RESET_CFG                  0x01
-#define SYS_EFUSE_DEVICE_CFG_STATUS0            0x02
-#define SYS_EFUSE_DEVICE_CFG_STATUS1            0x03
-#define SYS_EFUSE_DEVICE_CFG_STATUS2            0x04
-#define SYS_EFUSE_DEVICE_CFG3                   0x05
-#define SYS_EFUSE_DEVICE_CFG4                   0x06
-#define SYS_EFUSE_DEVICE_CFG5                   0x07
-#define SYS_EFUSE_DEVICE_CFG6                   0x08
-#define SYS_EFUSE_DEVICE_CFG7                   0x09
-#define SYS_PLL_CTRL                            0x0a
-#define SYS_CPU_RESET                           0x0b
-#define SYS_CPU_NONCOHERENT_MODE                0x0d
-#define SYS_CORE_DFS_DIS_CTRL                   0x0e
-#define SYS_CORE_DFS_RST_CTRL                   0x0f
-#define SYS_CORE_DFS_BYP_CTRL                   0x10
-#define SYS_CORE_DFS_PHA_CTRL                   0x11
-#define SYS_CORE_DFS_DIV_INC_CTRL               0x12
-#define SYS_CORE_DFS_DIV_DEC_CTRL               0x13
-#define SYS_CORE_DFS_DIV_VALUE                  0x14
-#define SYS_RESET                               0x15
-#define SYS_DFS_DIS_CTRL                        0x16
-#define SYS_DFS_RST_CTRL                        0x17
-#define SYS_DFS_BYP_CTRL                        0x18
-#define SYS_DFS_DIV_INC_CTRL                    0x19
-#define SYS_DFS_DIV_DEC_CTRL                    0x1a
-#define SYS_DFS_DIV_VALUE0                      0x1b
-#define SYS_DFS_DIV_VALUE1                      0x1c
-#define SYS_SENSE_AMP_DLY                       0x1d
-#define SYS_SOC_SENSE_AMP_DLY                   0x1e
-#define SYS_CTRL0                               0x1f
-#define SYS_CTRL1                               0x20
-#define SYS_TIMEOUT_BS1                         0x21
-#define SYS_BYTE_SWAP                           0x22
-#define SYS_VRM_VID                             0x23
-#define SYS_PWR_RAM_CMD                         0x24
-#define SYS_PWR_RAM_ADDR                        0x25
-#define SYS_PWR_RAM_DATA0                       0x26
-#define SYS_PWR_RAM_DATA1                       0x27
-#define SYS_PWR_RAM_DATA2                       0x28
-#define SYS_PWR_UCODE                           0x29
-#define SYS_CPU0_PWR_STATUS                     0x2a
-#define SYS_CPU1_PWR_STATUS                     0x2b
-#define SYS_CPU2_PWR_STATUS                     0x2c
-#define SYS_CPU3_PWR_STATUS                     0x2d
-#define SYS_CPU4_PWR_STATUS                     0x2e
-#define SYS_CPU5_PWR_STATUS                     0x2f
-#define SYS_CPU6_PWR_STATUS                     0x30
-#define SYS_CPU7_PWR_STATUS                     0x31
-#define SYS_STATUS                              0x32
-#define SYS_INT_POL                             0x33
-#define SYS_INT_TYPE                            0x34
-#define SYS_INT_STATUS                          0x35
-#define SYS_INT_MASK0                           0x36
-#define SYS_INT_MASK1                           0x37
-#define SYS_UCO_S_ECC                           0x38
-#define SYS_UCO_M_ECC                           0x39
-#define SYS_UCO_ADDR                            0x3a
-#define SYS_UCO_INSTR                           0x3b
-#define SYS_MEM_BIST0                           0x3c
-#define SYS_MEM_BIST1                           0x3d
-#define SYS_MEM_BIST2                           0x3e
-#define SYS_MEM_BIST3                           0x3f
-#define SYS_MEM_BIST4                           0x40
-#define SYS_MEM_BIST5                           0x41
-#define SYS_MEM_BIST6                           0x42
-#define SYS_MEM_BIST7                           0x43
-#define SYS_MEM_BIST8                           0x44
-#define SYS_MEM_BIST9                           0x45
-#define SYS_MEM_BIST10                          0x46
-#define SYS_MEM_BIST11                          0x47
-#define SYS_MEM_BIST12                          0x48
-#define SYS_SCRTCH0                             0x49
-#define SYS_SCRTCH1                             0x4a
-#define SYS_SCRTCH2                             0x4b
-#define SYS_SCRTCH3                             0x4c
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_sys_reg(b, r)          nlm_read_reg(b, r)
-#define nlm_write_sys_reg(b, r, v)      nlm_write_reg(b, r, v)
-#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
-#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-#endif
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
deleted file mode 100644
index 6a7046ca094..00000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __XLP_HAL_UART_H__
-#define __XLP_HAL_UART_H__
-
-/* UART Specific registers */
-#define UART_RX_DATA            0x00
-#define UART_TX_DATA            0x00
-
-#define UART_INT_EN             0x01
-#define UART_INT_ID             0x02
-#define UART_FIFO_CTL           0x02
-#define UART_LINE_CTL           0x03
-#define UART_MODEM_CTL          0x04
-#define UART_LINE_STS           0x05
-#define UART_MODEM_STS          0x06
-
-#define UART_DIVISOR0           0x00
-#define UART_DIVISOR1           0x01
-
-#define BASE_BAUD               (XLP_IO_CLK/16)
-#define BAUD_DIVISOR(baud)      (BASE_BAUD / baud)
-
-/* LCR mask values */
-#define LCR_5BITS               0x00
-#define LCR_6BITS               0x01
-#define LCR_7BITS               0x02
-#define LCR_8BITS               0x03
-#define LCR_STOPB               0x04
-#define LCR_PENAB               0x08
-#define LCR_PODD                0x00
-#define LCR_PEVEN               0x10
-#define LCR_PONE                0x20
-#define LCR_PZERO               0x30
-#define LCR_SBREAK              0x40
-#define LCR_EFR_ENABLE          0xbf
-#define LCR_DLAB                0x80
-
-/* MCR mask values */
-#define MCR_DTR                 0x01
-#define MCR_RTS                 0x02
-#define MCR_DRS                 0x04
-#define MCR_IE                  0x08
-#define MCR_LOOPBACK            0x10
-
-/* FCR mask values */
-#define FCR_RCV_RST             0x02
-#define FCR_XMT_RST             0x04
-#define FCR_RX_LOW              0x00
-#define FCR_RX_MEDL             0x40
-#define FCR_RX_MEDH             0x80
-#define FCR_RX_HIGH             0xc0
-
-/* IER mask values */
-#define IER_ERXRDY              0x1
-#define IER_ETXRDY              0x2
-#define IER_ERLS                0x4
-#define IER_EMSC                0x8
-
-#if !defined(LOCORE) && !defined(__ASSEMBLY__)
-
-#define nlm_read_uart_reg(b, r)         nlm_read_reg(b, r)
-#define nlm_write_uart_reg(b, r, v)     nlm_write_reg(b, r, v)
-#define nlm_get_uart_pcibase(node, inst)        \
-                nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
-#define nlm_get_uart_regbase(node, inst)        \
-                        (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
-
-static inline void
-nlm_uart_set_baudrate(uint64_t base, int baud)
-{
-        uint32_t lcr;
-
-        lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
-
-        /* enable divisor register, and write baud values */
-        nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
-        nlm_write_uart_reg(base, UART_DIVISOR0,
-                        (BAUD_DIVISOR(baud) & 0xff));
-        nlm_write_uart_reg(base, UART_DIVISOR1,
-                        ((BAUD_DIVISOR(baud) >> 8) & 0xff));
-
-        /* restore default lcr */
-        nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
-}
-
-static inline void
-nlm_uart_outbyte(uint64_t base, char c)
-{
-        uint32_t lsr;
-
-        for (;;) {
-                lsr = nlm_read_uart_reg(base, UART_LINE_STS);
-                if (lsr & 0x20)
-                        break;
-        }
-
-        nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
-}
-
-static inline char
-nlm_uart_inbyte(uint64_t base)
-{
-        int data, lsr;
-
-        for (;;) {
-                lsr = nlm_read_uart_reg(base, UART_LINE_STS);
-                if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
-                        data = 0;
-                        break;
-                }
-                if (lsr & 0x01) {       /* Rx data */
-                        data = nlm_read_uart_reg(base, UART_RX_DATA);
-                        break;
-                }
-        }
-
-        return (char)data;
-}
-
-static inline int
-nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
-        int parity, int int_en, int loopback)
-{
-        uint32_t lcr;
-
-        lcr = 0;
-        if (databits >= 8)
-                lcr |= LCR_8BITS;
-        else if (databits == 7)
-                lcr |= LCR_7BITS;
-        else if (databits == 6)
-                lcr |= LCR_6BITS;
-        else
-                lcr |= LCR_5BITS;
-
-        if (stopbits > 1)
-                lcr |= LCR_STOPB;
-
-        lcr |= parity << 3;
-
-        /* setup default lcr */
-        nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
-
-        /* Reset the FIFOs */
-        nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
-
-        nlm_uart_set_baudrate(base, baud);
-
-        if (loopback)
-                nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
-
-        if (int_en)
-                nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
-
-        return 0;
-}
-#endif /* !LOCORE && !__ASSEMBLY__ */
-#endif /* __XLP_HAL_UART_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/usb.h b/arch/mips/include/asm/netlogic/xlp-hal/usb.h
deleted file mode 100644
index a9cd350dfb6..00000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/usb.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_USB_H__
-#define __NLM_HAL_USB_H__
-
-#define USB_CTL_0                       0x01
-#define USB_PHY_0                       0x0A
-#define USB_PHY_RESET                   0x01
-#define USB_PHY_PORT_RESET_0            0x10
-#define USB_PHY_PORT_RESET_1            0x20
-#define USB_CONTROLLER_RESET            0x01
-#define USB_INT_STATUS                  0x0E
-#define USB_INT_EN                      0x0F
-#define USB_PHY_INTERRUPT_EN            0x01
-#define USB_OHCI_INTERRUPT_EN           0x02
-#define USB_OHCI_INTERRUPT1_EN          0x04
-#define USB_OHCI_INTERRUPT2_EN          0x08
-#define USB_CTRL_INTERRUPT_EN           0x10
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_usb_reg(b, r)                  nlm_read_reg(b, r)
-#define nlm_write_usb_reg(b, r, v)              nlm_write_reg(b, r, v)
-#define nlm_get_usb_pcibase(node, inst)         \
-        nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
-#define nlm_get_usb_hcd_base(node, inst)        \
-        nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst))
-#define nlm_get_usb_regbase(node, inst)         \
-        (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
-
-#endif
-#endif /* __NLM_HAL_USB_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
deleted file mode 100644
index 7e47209327a..00000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NLM_HAL_XLP_H
-#define _NLM_HAL_XLP_H
-
-#define PIC_UART_0_IRQ                  17
-#define PIC_UART_1_IRQ                  18
-#define PIC_PCIE_LINK_0_IRQ             19
-#define PIC_PCIE_LINK_1_IRQ             20
-#define PIC_PCIE_LINK_2_IRQ             21
-#define PIC_PCIE_LINK_3_IRQ             22
-#define PIC_EHCI_0_IRQ                  23
-#define PIC_EHCI_1_IRQ                  24
-#define PIC_OHCI_0_IRQ                  25
-#define PIC_OHCI_1_IRQ                  26
-#define PIC_OHCI_2_IRQ                  27
-#define PIC_OHCI_3_IRQ                  28
-#define PIC_MMC_IRQ                     29
-#define PIC_I2C_0_IRQ                   30
-#define PIC_I2C_1_IRQ                   31
-
-#ifndef __ASSEMBLY__
-
-/* SMP support functions */
-void xlp_boot_core0_siblings(void);
-void xlp_wakeup_secondary_cpus(void);
-
-void xlp_mmu_init(void);
-void nlm_hal_init(void);
-
-#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h
deleted file mode 100644
index 2d02428c4f1..00000000000
--- a/arch/mips/include/asm/netlogic/xlr/bridge.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _ASM_NLM_BRIDGE_H_
-#define _ASM_NLM_BRIDGE_H_
-
-#define BRIDGE_DRAM_0_BAR               0
-#define BRIDGE_DRAM_1_BAR               1
-#define BRIDGE_DRAM_2_BAR               2
-#define BRIDGE_DRAM_3_BAR               3
-#define BRIDGE_DRAM_4_BAR               4
-#define BRIDGE_DRAM_5_BAR               5
-#define BRIDGE_DRAM_6_BAR               6
-#define BRIDGE_DRAM_7_BAR               7
-#define BRIDGE_DRAM_CHN_0_MTR_0_BAR     8
-#define BRIDGE_DRAM_CHN_0_MTR_1_BAR     9
-#define BRIDGE_DRAM_CHN_0_MTR_2_BAR     10
-#define BRIDGE_DRAM_CHN_0_MTR_3_BAR     11
-#define BRIDGE_DRAM_CHN_0_MTR_4_BAR     12
-#define BRIDGE_DRAM_CHN_0_MTR_5_BAR     13
-#define BRIDGE_DRAM_CHN_0_MTR_6_BAR     14
-#define BRIDGE_DRAM_CHN_0_MTR_7_BAR     15
-#define BRIDGE_DRAM_CHN_1_MTR_0_BAR     16
-#define BRIDGE_DRAM_CHN_1_MTR_1_BAR     17
-#define BRIDGE_DRAM_CHN_1_MTR_2_BAR     18
-#define BRIDGE_DRAM_CHN_1_MTR_3_BAR     19
-#define BRIDGE_DRAM_CHN_1_MTR_4_BAR     20
-#define BRIDGE_DRAM_CHN_1_MTR_5_BAR     21
-#define BRIDGE_DRAM_CHN_1_MTR_6_BAR     22
-#define BRIDGE_DRAM_CHN_1_MTR_7_BAR     23
-#define BRIDGE_CFG_BAR                  24
-#define BRIDGE_PHNX_IO_BAR              25
-#define BRIDGE_FLASH_BAR                26
-#define BRIDGE_SRAM_BAR                 27
-#define BRIDGE_HTMEM_BAR                28
-#define BRIDGE_HTINT_BAR                29
-#define BRIDGE_HTPIC_BAR                30
-#define BRIDGE_HTSM_BAR                 31
-#define BRIDGE_HTIO_BAR                 32
-#define BRIDGE_HTCFG_BAR                33
-#define BRIDGE_PCIXCFG_BAR              34
-#define BRIDGE_PCIXMEM_BAR              35
-#define BRIDGE_PCIXIO_BAR               36
-#define BRIDGE_DEVICE_MASK              37
-#define BRIDGE_AERR_INTR_LOG1           38
-#define BRIDGE_AERR_INTR_LOG2           39
-#define BRIDGE_AERR_INTR_LOG3           40
-#define BRIDGE_AERR_DEV_STAT            41
-#define BRIDGE_AERR1_LOG1               42
-#define BRIDGE_AERR1_LOG2               43
-#define BRIDGE_AERR1_LOG3               44
-#define BRIDGE_AERR1_DEV_STAT           45
-#define BRIDGE_AERR_INTR_EN             46
-#define BRIDGE_AERR_UPG                 47
-#define BRIDGE_AERR_CLEAR               48
-#define BRIDGE_AERR1_CLEAR              49
-#define BRIDGE_SBE_COUNTS               50
-#define BRIDGE_DBE_COUNTS               51
-#define BRIDGE_BITERR_INT_EN            52
-
-#define BRIDGE_SYS2IO_CREDITS           53
-#define BRIDGE_EVNT_CNT_CTRL1           54
-#define BRIDGE_EVNT_COUNTER1            55
-#define BRIDGE_EVNT_CNT_CTRL2           56
-#define BRIDGE_EVNT_COUNTER2            57
-#define BRIDGE_RESERVED1                58
-
-#define BRIDGE_DEFEATURE                59
-#define BRIDGE_SCRATCH0                 60
-#define BRIDGE_SCRATCH1                 61
-#define BRIDGE_SCRATCH2                 62
-#define BRIDGE_SCRATCH3                 63
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h
deleted file mode 100644
index f8aca5472b6..00000000000
--- a/arch/mips/include/asm/netlogic/xlr/flash.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _ASM_NLM_FLASH_H_
-#define _ASM_NLM_FLASH_H_
-
-#define FLASH_CSBASE_ADDR(cs)           (cs)
-#define FLASH_CSADDR_MASK(cs)           (0x10 + (cs))
-#define FLASH_CSDEV_PARM(cs)            (0x20 + (cs))
-#define FLASH_CSTIME_PARMA(cs)          (0x30 + (cs))
-#define FLASH_CSTIME_PARMB(cs)          (0x40 + (cs))
-
-#define FLASH_INT_MASK                  0x50
-#define FLASH_INT_STATUS                0x60
-#define FLASH_ERROR_STATUS              0x70
-#define FLASH_ERROR_ADDR                0x80
-
-#define FLASH_NAND_CLE(cs)              (0x90 + (cs))
-#define FLASH_NAND_ALE(cs)              (0xa0 + (cs))
-
-#define FLASH_NAND_CSDEV_PARAM          0x000041e6
-#define FLASH_NAND_CSTIME_PARAMA        0x4f400e22
-#define FLASH_NAND_CSTIME_PARAMB        0x000083cf
-
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
deleted file mode 100644
index 68d5167c86b..00000000000
--- a/arch/mips/include/asm/netlogic/xlr/fmn.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NLM_FMN_H_
-#define _NLM_FMN_H_
-
-#include <asm/netlogic/mips-extns.h> /* for COP2 access */
-
-/* Station IDs */
-#define FMN_STNID_CPU0                  0x00
-#define FMN_STNID_CPU1                  0x08
-#define FMN_STNID_CPU2                  0x10
-#define FMN_STNID_CPU3                  0x18
-#define FMN_STNID_CPU4                  0x20
-#define FMN_STNID_CPU5                  0x28
-#define FMN_STNID_CPU6                  0x30
-#define FMN_STNID_CPU7                  0x38
-
-#define FMN_STNID_XGS0_TX               64
-#define FMN_STNID_XMAC0_00_TX           64
-#define FMN_STNID_XMAC0_01_TX           65
-#define FMN_STNID_XMAC0_02_TX           66
-#define FMN_STNID_XMAC0_03_TX           67
-#define FMN_STNID_XMAC0_04_TX           68
-#define FMN_STNID_XMAC0_05_TX           69
-#define FMN_STNID_XMAC0_06_TX           70
-#define FMN_STNID_XMAC0_07_TX           71
-#define FMN_STNID_XMAC0_08_TX           72
-#define FMN_STNID_XMAC0_09_TX           73
-#define FMN_STNID_XMAC0_10_TX           74
-#define FMN_STNID_XMAC0_11_TX           75
-#define FMN_STNID_XMAC0_12_TX           76
-#define FMN_STNID_XMAC0_13_TX           77
-#define FMN_STNID_XMAC0_14_TX           78
-#define FMN_STNID_XMAC0_15_TX           79
-
-#define FMN_STNID_XGS1_TX               80
-#define FMN_STNID_XMAC1_00_TX           80
-#define FMN_STNID_XMAC1_01_TX           81
-#define FMN_STNID_XMAC1_02_TX           82
-#define FMN_STNID_XMAC1_03_TX           83
-#define FMN_STNID_XMAC1_04_TX           84
-#define FMN_STNID_XMAC1_05_TX           85
-#define FMN_STNID_XMAC1_06_TX           86
-#define FMN_STNID_XMAC1_07_TX           87
-#define FMN_STNID_XMAC1_08_TX           88
-#define FMN_STNID_XMAC1_09_TX           89
-#define FMN_STNID_XMAC1_10_TX           90
-#define FMN_STNID_XMAC1_11_TX           91
-#define FMN_STNID_XMAC1_12_TX           92
-#define FMN_STNID_XMAC1_13_TX           93
-#define FMN_STNID_XMAC1_14_TX           94
-#define FMN_STNID_XMAC1_15_TX           95
-
-#define FMN_STNID_GMAC                  96
-#define FMN_STNID_GMACJFR_0             96
-#define FMN_STNID_GMACRFR_0             97
-#define FMN_STNID_GMACTX0               98
-#define FMN_STNID_GMACTX1               99
-#define FMN_STNID_GMACTX2               100
-#define FMN_STNID_GMACTX3               101
-#define FMN_STNID_GMACJFR_1             102
-#define FMN_STNID_GMACRFR_1             103
-
-#define FMN_STNID_DMA                   104
-#define FMN_STNID_DMA_0                 104
-#define FMN_STNID_DMA_1                 105
-#define FMN_STNID_DMA_2                 106
-#define FMN_STNID_DMA_3                 107
-
-#define FMN_STNID_XGS0FR                112
-#define FMN_STNID_XMAC0JFR              112
-#define FMN_STNID_XMAC0RFR              113
-
-#define FMN_STNID_XGS1FR                114
-#define FMN_STNID_XMAC1JFR              114
-#define FMN_STNID_XMAC1RFR              115
-#define FMN_STNID_SEC                   120
-#define FMN_STNID_SEC0                  120
-#define FMN_STNID_SEC1                  121
-#define FMN_STNID_SEC2                  122
-#define FMN_STNID_SEC3                  123
-#define FMN_STNID_PK0                   124
-#define FMN_STNID_SEC_RSA               124
-#define FMN_STNID_SEC_RSVD0             125
-#define FMN_STNID_SEC_RSVD1             126
-#define FMN_STNID_SEC_RSVD2             127
-
-#define FMN_STNID_GMAC1                 80
-#define FMN_STNID_GMAC1_FR_0            81
-#define FMN_STNID_GMAC1_TX0             82
-#define FMN_STNID_GMAC1_TX1             83
-#define FMN_STNID_GMAC1_TX2             84
-#define FMN_STNID_GMAC1_TX3             85
-#define FMN_STNID_GMAC1_FR_1            87
-#define FMN_STNID_GMAC0                 96
-#define FMN_STNID_GMAC0_FR_0            97
-#define FMN_STNID_GMAC0_TX0             98
-#define FMN_STNID_GMAC0_TX1             99
-#define FMN_STNID_GMAC0_TX2             100
-#define FMN_STNID_GMAC0_TX3             101
-#define FMN_STNID_GMAC0_FR_1            103
-#define FMN_STNID_CMP_0                 108
-#define FMN_STNID_CMP_1                 109
-#define FMN_STNID_CMP_2                 110
-#define FMN_STNID_CMP_3                 111
-#define FMN_STNID_PCIE_0                116
-#define FMN_STNID_PCIE_1                117
-#define FMN_STNID_PCIE_2                118
-#define FMN_STNID_PCIE_3                119
-#define FMN_STNID_XLS_PK0               121
-
-#define nlm_read_c2_cc0(s)              __read_32bit_c2_register($16, s)
-#define nlm_read_c2_cc1(s)              __read_32bit_c2_register($17, s)
-#define nlm_read_c2_cc2(s)              __read_32bit_c2_register($18, s)
-#define nlm_read_c2_cc3(s)              __read_32bit_c2_register($19, s)
-#define nlm_read_c2_cc4(s)              __read_32bit_c2_register($20, s)
-#define nlm_read_c2_cc5(s)              __read_32bit_c2_register($21, s)
-#define nlm_read_c2_cc6(s)              __read_32bit_c2_register($22, s)
-#define nlm_read_c2_cc7(s)              __read_32bit_c2_register($23, s)
-#define nlm_read_c2_cc8(s)              __read_32bit_c2_register($24, s)
-#define nlm_read_c2_cc9(s)              __read_32bit_c2_register($25, s)
-#define nlm_read_c2_cc10(s)             __read_32bit_c2_register($26, s)
-#define nlm_read_c2_cc11(s)             __read_32bit_c2_register($27, s)
-#define nlm_read_c2_cc12(s)             __read_32bit_c2_register($28, s)
-#define nlm_read_c2_cc13(s)             __read_32bit_c2_register($29, s)
-#define nlm_read_c2_cc14(s)             __read_32bit_c2_register($30, s)
-#define nlm_read_c2_cc15(s)             __read_32bit_c2_register($31, s)
-
-#define nlm_write_c2_cc0(s, v)          __write_32bit_c2_register($16, s, v)
-#define nlm_write_c2_cc1(s, v)          __write_32bit_c2_register($17, s, v)
-#define nlm_write_c2_cc2(s, v)          __write_32bit_c2_register($18, s, v)
-#define nlm_write_c2_cc3(s, v)          __write_32bit_c2_register($19, s, v)
-#define nlm_write_c2_cc4(s, v)          __write_32bit_c2_register($20, s, v)
-#define nlm_write_c2_cc5(s, v)          __write_32bit_c2_register($21, s, v)
-#define nlm_write_c2_cc6(s, v)          __write_32bit_c2_register($22, s, v)
-#define nlm_write_c2_cc7(s, v)          __write_32bit_c2_register($23, s, v)
-#define nlm_write_c2_cc8(s, v)          __write_32bit_c2_register($24, s, v)
-#define nlm_write_c2_cc9(s, v)          __write_32bit_c2_register($25, s, v)
-#define nlm_write_c2_cc10(s, v)         __write_32bit_c2_register($26, s, v)
-#define nlm_write_c2_cc11(s, v)         __write_32bit_c2_register($27, s, v)
-#define nlm_write_c2_cc12(s, v)         __write_32bit_c2_register($28, s, v)
-#define nlm_write_c2_cc13(s, v)         __write_32bit_c2_register($29, s, v)
-#define nlm_write_c2_cc14(s, v)         __write_32bit_c2_register($30, s, v)
-#define nlm_write_c2_cc15(s, v)         __write_32bit_c2_register($31, s, v)
-
-#define nlm_read_c2_status(sel)         __read_32bit_c2_register($2, 0)
-#define nlm_read_c2_config()            __read_32bit_c2_register($3, 0)
-#define nlm_write_c2_config(v)          __write_32bit_c2_register($3, 0, v)
-#define nlm_read_c2_bucksize(b)         __read_32bit_c2_register($4, b)
-#define nlm_write_c2_bucksize(b, v)     __write_32bit_c2_register($4, b, v)
-
-#define nlm_read_c2_rx_msg0()           __read_64bit_c2_register($1, 0)
-#define nlm_read_c2_rx_msg1()           __read_64bit_c2_register($1, 1)
-#define nlm_read_c2_rx_msg2()           __read_64bit_c2_register($1, 2)
-#define nlm_read_c2_rx_msg3()           __read_64bit_c2_register($1, 3)
-
-#define nlm_write_c2_tx_msg0(v)         __write_64bit_c2_register($0, 0, v)
-#define nlm_write_c2_tx_msg1(v)         __write_64bit_c2_register($0, 1, v)
-#define nlm_write_c2_tx_msg2(v)         __write_64bit_c2_register($0, 2, v)
-#define nlm_write_c2_tx_msg3(v)         __write_64bit_c2_register($0, 3, v)
-
-#define FMN_STN_RX_QSIZE                256
-#define FMN_NSTATIONS                   128
-#define FMN_CORE_NBUCKETS               8
-
-static inline void nlm_msgsnd(unsigned int stid)
-{
-        __asm__ volatile (
-            ".set       push\n"
-            ".set       noreorder\n"
-            ".set       noat\n"
-            "move       $1, %0\n"
-            "c2         0x10001\n"      /* msgsnd $1 */
-            ".set       pop\n"
-            : : "r" (stid) : "$1"
-        );
-}
-
-static inline void nlm_msgld(unsigned int pri)
-{
-        __asm__ volatile (
-            ".set       push\n"
-            ".set       noreorder\n"
-            ".set       noat\n"
-            "move       $1, %0\n"
-            "c2         0x10002\n"    /* msgld $1 */
-            ".set       pop\n"
-            : : "r" (pri) : "$1"
-        );
-}
-
-static inline void nlm_msgwait(unsigned int mask)
-{
-        __asm__ volatile (
-            ".set       push\n"
-            ".set       noreorder\n"
-            ".set       noat\n"
-            "move       $8, %0\n"
-            "c2         0x10003\n"    /* msgwait $1 */
-            ".set       pop\n"
-            : : "r" (mask) : "$1"
-        );
-}
-
-/*
- * Disable interrupts and enable COP2 access
- */
-static inline uint32_t nlm_cop2_enable(void)
-{
-        uint32_t sr = read_c0_status();
-
-        write_c0_status((sr & ~ST0_IE) | ST0_CU2);
-        return sr;
-}
-
-static inline void nlm_cop2_restore(uint32_t sr)
-{
-        write_c0_status(sr);
-}
-
-static inline void nlm_fmn_setup_intr(int irq, unsigned int tmask)
-{
-        uint32_t config;
-
-        config = (1 << 24)      /* interrupt water mark - 1 msg */
-                | (irq << 16)   /* irq */
-                | (tmask << 8)  /* thread mask */
-                | 0x2;          /* enable watermark intr, disable empty intr */
-        nlm_write_c2_config(config);
-}
-
-struct nlm_fmn_msg {
-        uint64_t msg0;
-        uint64_t msg1;
-        uint64_t msg2;
-        uint64_t msg3;
-};
-
-static inline int nlm_fmn_send(unsigned int size, unsigned int code,
-                unsigned int stid, struct nlm_fmn_msg *msg)
-{
-        unsigned int dest;
-        uint32_t status;
-        int i;
-
-        /*
-         * Make sure that all the writes pending at the cpu are flushed.
-         * Any writes pending on CPU will not be see by devices. L1/L2
-         * caches are coherent with IO, so no cache flush needed.
-         */
-        __asm __volatile("sync");
-
-        /* Load TX message buffers */
-        nlm_write_c2_tx_msg0(msg->msg0);
-        nlm_write_c2_tx_msg1(msg->msg1);
-        nlm_write_c2_tx_msg2(msg->msg2);
-        nlm_write_c2_tx_msg3(msg->msg3);
-        dest = ((size - 1) << 16) | (code << 8) | stid;
-
-        /*
-         * Retry a few times on credit fail, this should be a
-         * transient condition, unless there is a configuration
-         * failure, or the receiver is stuck.
-         */
-        for (i = 0; i < 8; i++) {
-                nlm_msgsnd(dest);
-                status = nlm_read_c2_status(0);
-                if ((status & 0x2) == 1)
-                        pr_info("Send pending fail!\n");
-                if ((status & 0x4) == 0)
-                        return 0;
-        }
-
-        /* If there is a credit failure, return error */
-        return status & 0x06;
-}
-
-static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
-                struct nlm_fmn_msg *msg)
-{
-        uint32_t status, tmp;
-
-        nlm_msgld(bucket);
-
-        /* wait for load pending to clear */
-        do {
-                status = nlm_read_c2_status(1);
-        } while ((status & 0x08) != 0);
-
-        /* receive error bits */
-        tmp = status & 0x30;
-        if (tmp != 0)
-                return tmp;
-
-        *size = ((status & 0xc0) >> 6) + 1;
-        *code = (status & 0xff00) >> 8;
-        *stid = (status & 0x7f0000) >> 16;
-        msg->msg0 = nlm_read_c2_rx_msg0();
-        msg->msg1 = nlm_read_c2_rx_msg1();
-        msg->msg2 = nlm_read_c2_rx_msg2();
-        msg->msg3 = nlm_read_c2_rx_msg3();
-
-        return 0;
-}
-
-struct xlr_fmn_info {
-        int num_buckets;
-        int start_stn_id;
-        int end_stn_id;
-        int credit_config[128];
-};
-
-struct xlr_board_fmn_config {
-        int bucket_size[128];           /* size of buckets for all stations */
-        struct xlr_fmn_info cpu[8];
-        struct xlr_fmn_info gmac[2];
-        struct xlr_fmn_info dma;
-        struct xlr_fmn_info cmp;
-        struct xlr_fmn_info sae;
-        struct xlr_fmn_info xgmac[2];
-};
-
-extern int nlm_register_fmn_handler(int start, int end,
-        void (*fn)(int, int, int, int, struct nlm_fmn_msg *, void *),
-        void *arg);
-extern void xlr_percpu_fmn_init(void);
-extern void nlm_setup_fmn_irq(void);
-extern void xlr_board_info_setup(void);
-
-extern struct xlr_board_fmn_config xlr_board_fmn_config;
-#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
index 8492e835b11..51f6ad4aeb1 100644
--- a/arch/mips/include/asm/netlogic/xlr/gpio.h
+++ b/arch/mips/include/asm/netlogic/xlr/gpio.h
@@ -35,40 +35,39 @@
 #ifndef _ASM_NLM_GPIO_H
 #define _ASM_NLM_GPIO_H
 
-#define GPIO_INT_EN_REG                 0
-#define GPIO_INPUT_INVERSION_REG        1
-#define GPIO_IO_DIR_REG                 2
-#define GPIO_IO_DATA_WR_REG             3
-#define GPIO_IO_DATA_RD_REG             4
+#define NETLOGIC_GPIO_INT_EN_REG                0
+#define NETLOGIC_GPIO_INPUT_INVERSION_REG       1
+#define NETLOGIC_GPIO_IO_DIR_REG                2
+#define NETLOGIC_GPIO_IO_DATA_WR_REG            3
+#define NETLOGIC_GPIO_IO_DATA_RD_REG            4
 
-#define GPIO_SWRESET_REG                8
-#define GPIO_DRAM1_CNTRL_REG            9
-#define GPIO_DRAM1_RATIO_REG            10
-#define GPIO_DRAM1_RESET_REG            11
-#define GPIO_DRAM1_STATUS_REG           12
-#define GPIO_DRAM2_CNTRL_REG            13
-#define GPIO_DRAM2_RATIO_REG            14
-#define GPIO_DRAM2_RESET_REG            15
-#define GPIO_DRAM2_STATUS_REG           16
+#define NETLOGIC_GPIO_SWRESET_REG               8
+#define NETLOGIC_GPIO_DRAM1_CNTRL_REG           9
+#define NETLOGIC_GPIO_DRAM1_RATIO_REG           10
+#define NETLOGIC_GPIO_DRAM1_RESET_REG           11
+#define NETLOGIC_GPIO_DRAM1_STATUS_REG          12
+#define NETLOGIC_GPIO_DRAM2_CNTRL_REG           13
+#define NETLOGIC_GPIO_DRAM2_RATIO_REG           14
+#define NETLOGIC_GPIO_DRAM2_RESET_REG           15
+#define NETLOGIC_GPIO_DRAM2_STATUS_REG          16
 
-#define GPIO_PWRON_RESET_CFG_REG        21
-#define GPIO_BIST_ALL_GO_STATUS_REG     24
-#define GPIO_BIST_CPU_GO_STATUS_REG     25
-#define GPIO_BIST_DEV_GO_STATUS_REG     26
+#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG       21
+#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG    24
+#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG    25
+#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG    26
 
-#define GPIO_FUSE_BANK_REG              35
-#define GPIO_CPU_RESET_REG              40
-#define GPIO_RNG_REG                    43
+#define NETLOGIC_GPIO_FUSE_BANK_REG             35
+#define NETLOGIC_GPIO_CPU_RESET_REG             40
+#define NETLOGIC_GPIO_RNG_REG                   43
 
-#define PWRON_RESET_PCMCIA_BOOT         17
+#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT        17
+#define NETLOGIC_GPIO_LED_BITMAP        0x1700000
+#define NETLOGIC_GPIO_LED_0_SHIFT               20
+#define NETLOGIC_GPIO_LED_1_SHIFT               24
 
-#define GPIO_LED_BITMAP                 0x1700000
-#define GPIO_LED_0_SHIFT                20
-#define GPIO_LED_1_SHIFT                24
-
-#define GPIO_LED_OUTPUT_CODE_RESET      0x01
-#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
-#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
-#define GPIO_LED_OUTPUT_CODE_MAIN       0x04
+#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET     0x01
+#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
+#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
+#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN      0x04
 
 #endif
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
index 2e768f032e8..2e3a4dd5304 100644
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -106,4 +106,26 @@
 #define DEFAULT_HT_TYPE0_CFG_BASE       0x16000000
 #define DEFAULT_HT_TYPE1_CFG_BASE       0x17000000
 
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+typedef volatile __u32 nlm_reg_t;
+extern unsigned long netlogic_io_base;
+
+/* FIXME read once in write_reg */
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define netlogic_read_reg(base, offset)         ((base)[(offset)])
+#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
+#else
+#define netlogic_read_reg(base, offset)         (be32_to_cpu((base)[(offset)]))
+#define netlogic_write_reg(base, offset, value) \
+                                ((base)[(offset)] = cpu_to_be32((value)))
+#endif
+
+#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
+#define netlogic_write_reg_le32(base, offset, value) \
+                                ((base)[(offset)] = cpu_to_le32((value)))
+#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
+#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
deleted file mode 100644
index 7e39d40be4f..00000000000
--- a/arch/mips/include/asm/netlogic/xlr/msidef.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef ASM_RMI_MSIDEF_H
-#define ASM_RMI_MSIDEF_H
-
-/*
- * Constants for Intel APIC based MSI messages.
- * Adapted for the RMI XLR using identical defines
- */
-
-/*
- * Shifts for MSI data
- */
-
-#define MSI_DATA_VECTOR_SHIFT           0
-#define  MSI_DATA_VECTOR_MASK           0x000000ff
-#define  MSI_DATA_VECTOR(v)             (((v) << MSI_DATA_VECTOR_SHIFT) & \
-                                                MSI_DATA_VECTOR_MASK)
-
-#define MSI_DATA_DELIVERY_MODE_SHIFT    8
-#define  MSI_DATA_DELIVERY_FIXED        (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
-#define  MSI_DATA_DELIVERY_LOWPRI       (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
-
-#define MSI_DATA_LEVEL_SHIFT            14
-#define  MSI_DATA_LEVEL_DEASSERT        (0 << MSI_DATA_LEVEL_SHIFT)
-#define  MSI_DATA_LEVEL_ASSERT          (1 << MSI_DATA_LEVEL_SHIFT)
-
-#define MSI_DATA_TRIGGER_SHIFT          15
-#define  MSI_DATA_TRIGGER_EDGE          (0 << MSI_DATA_TRIGGER_SHIFT)
-#define  MSI_DATA_TRIGGER_LEVEL         (1 << MSI_DATA_TRIGGER_SHIFT)
-
-/*
- * Shift/mask fields for msi address
- */
-
-#define MSI_ADDR_BASE_HI                0
-#define MSI_ADDR_BASE_LO                0xfee00000
-
-#define MSI_ADDR_DEST_MODE_SHIFT        2
-#define  MSI_ADDR_DEST_MODE_PHYSICAL    (0 << MSI_ADDR_DEST_MODE_SHIFT)
-#define  MSI_ADDR_DEST_MODE_LOGICAL     (1 << MSI_ADDR_DEST_MODE_SHIFT)
-
-#define MSI_ADDR_REDIRECTION_SHIFT      3
-#define  MSI_ADDR_REDIRECTION_CPU       (0 << MSI_ADDR_REDIRECTION_SHIFT)
-#define  MSI_ADDR_REDIRECTION_LOWPRI    (1 << MSI_ADDR_REDIRECTION_SHIFT)
-
-#define MSI_ADDR_DEST_ID_SHIFT          12
-#define  MSI_ADDR_DEST_ID_MASK          0x00ffff0
-#define  MSI_ADDR_DEST_ID(dest)         (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
-                                                 MSI_ADDR_DEST_ID_MASK)
-
-#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 9a691b1f91b..5cceb746f08 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -193,70 +193,39 @@
 /* end XLS */
 
 #ifndef __ASSEMBLY__
-
-#define PIC_IRQ_IS_EDGE_TRIGGERED(irq)  (((irq) >= PIC_TIMER_0_IRQ) && \
-                                        ((irq) <= PIC_TIMER_7_IRQ))
-#define PIC_IRQ_IS_IRT(irq)             (((irq) >= PIC_IRT_FIRST_IRQ) && \
-                                        ((irq) <= PIC_IRT_LAST_IRQ))
-
-static inline int
-nlm_irq_to_irt(int irq)
-{
-        if (PIC_IRQ_IS_IRT(irq) == 0)
-                return -1;
-
-        return PIC_IRQ_TO_INTR(irq);
-}
-
-static inline int
-nlm_irt_to_irq(int irt)
+static inline void pic_send_ipi(u32 ipi)
 {
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
-        return PIC_INTR_TO_IRQ(irt);
+        netlogic_write_reg(mmio, PIC_IPI, ipi);
 }
 
-static inline void
-nlm_pic_enable_irt(uint64_t base, int irt)
+static inline u32 pic_read_control(void)
 {
-        uint32_t reg;
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
-        reg = nlm_read_reg(base, PIC_IRT_1(irt));
-        nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
+        return netlogic_read_reg(mmio, PIC_CTRL);
 }
 
-static inline void
-nlm_pic_disable_irt(uint64_t base, int irt)
+static inline void pic_write_control(u32 control)
 {
-        uint32_t reg;
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
-        reg = nlm_read_reg(base, PIC_IRT_1(irt));
-        nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
+        netlogic_write_reg(mmio, PIC_CTRL, control);
 }
 
-static inline void
-nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
+static inline void pic_update_control(u32 control)
 {
-        unsigned int tid, pid;
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
-        tid = hwt & 0x3;
-        pid = (hwt >> 2) & 0x07;
-        nlm_write_reg(base, PIC_IPI,
-                (pid << 20) | (tid << 16) | (nmi << 8) | irq);
+        netlogic_write_reg(mmio, PIC_CTRL,
+                (control | netlogic_read_reg(mmio, PIC_CTRL)));
 }
 
-static inline void
-nlm_pic_ack(uint64_t base, int irt)
-{
-        nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
-}
-
-static inline void
-nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
-{
-        nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
-        /* local scheduling, invalid, level by default */
-        nlm_write_reg(base, PIC_IRT_1(irt),
-                (1 << 30) | (1 << 6) | irq);
-}
+#define PIC_IRQ_IS_EDGE_TRIGGERED(irq)  (((irq) >= PIC_TIMER_0_IRQ) && \
+                                        ((irq) <= PIC_TIMER_7_IRQ))
+#define PIC_IRQ_IS_IRT(irq)             (((irq) >= PIC_IRT_FIRST_IRQ) && \
+                                        ((irq) <= PIC_IRT_LAST_IRQ))
 #endif
+
 #endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index c1667e0c272..3e6372692a0 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -40,8 +40,17 @@ struct uart_port;
 unsigned int nlm_xlr_uart_in(struct uart_port *, int);
 void nlm_xlr_uart_out(struct uart_port *, int, int);
 
-/* SMP helpers */
-void xlr_wakeup_secondary_cpus(void);
+/* SMP support functions */
+struct irq_desc;
+void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
+void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
+int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
+void nlm_smp_irq_init(void);
+void nlm_boot_smp_nmi(void);
+void prom_pre_boot_secondary_cpus(void);
+
+extern struct plat_smp_ops nlm_smp_ops;
+extern unsigned long nlm_common_ebase;
 
 /* XLS B silicon "Rook" */
 static inline unsigned int nlm_chip_is_xls_b(void)
@@ -51,8 +60,10 @@ static inline unsigned int nlm_chip_is_xls_b(void)
         return ((prid & 0xf000) == 0x4000);
 }
 
-/*  XLR chip types */
-/* The XLS product line has chip versions 0x[48c]? */
+/*
+ *  XLR chip types
+ */
+ /* The XLS product line has chip versions 0x[48c]? */
 static inline unsigned int nlm_chip_is_xls(void)
 {
         uint32_t prid = read_c0_prid();
diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h
deleted file mode 100644
index 3c74d826e2e..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-address.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2009 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * Typedefs and defines for working with Octeon physical addresses.
- *
- */
-#ifndef __CVMX_ADDRESS_H__
-#define __CVMX_ADDRESS_H__
-
-#if 0
-typedef enum {
-        CVMX_MIPS_SPACE_XKSEG = 3LL,
-        CVMX_MIPS_SPACE_XKPHYS = 2LL,
-        CVMX_MIPS_SPACE_XSSEG = 1LL,
-        CVMX_MIPS_SPACE_XUSEG = 0LL
-} cvmx_mips_space_t;
-#endif
-
-typedef enum {
-        CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
-        CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
-        CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
-        CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
-} cvmx_mips_xkseg_space_t;
-
-/* decodes <14:13> of a kseg3 window address */
-typedef enum {
-        CVMX_ADD_WIN_SCR = 0L,
-        /* see cvmx_add_win_dma_dec_t for further decode */
-        CVMX_ADD_WIN_DMA = 1L,
-        CVMX_ADD_WIN_UNUSED = 2L,
-        CVMX_ADD_WIN_UNUSED2 = 3L
-} cvmx_add_win_dec_t;
-
-/* decode within DMA space */
-typedef enum {
-        /*
-         * Add store data to the write buffer entry, allocating it if
-         * necessary.
-         */
-        CVMX_ADD_WIN_DMA_ADD = 0L,
-        /* send out the write buffer entry to DRAM */
-        CVMX_ADD_WIN_DMA_SENDMEM = 1L,
-        /* store data must be normal DRAM memory space address in this case */
-        /* send out the write buffer entry as an IOBDMA command */
-        CVMX_ADD_WIN_DMA_SENDDMA = 2L,
-        /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
-        /* send out the write buffer entry as an IO write */
-        CVMX_ADD_WIN_DMA_SENDIO = 3L,
-        /* store data must be normal IO space address in this case */
-        /* send out a single-tick command on the NCB bus */
-        CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
-        /* no write buffer data needed/used */
-} cvmx_add_win_dma_dec_t;
-
-/*
- *   Physical Address Decode
- *
- * Octeon-I HW never interprets this X (<39:36> reserved
- * for future expansion), software should set to 0.
- *
- *  - 0x0 XXX0 0000 0000 to      DRAM         Cached
- *  - 0x0 XXX0 0FFF FFFF
- *
- *  - 0x0 XXX0 1000 0000 to      Boot Bus     Uncached  (Converted to 0x1 00X0 1000 0000
- *  - 0x0 XXX0 1FFF FFFF         + EJTAG                           to 0x1 00X0 1FFF FFFF)
- *
- *  - 0x0 XXX0 2000 0000 to      DRAM         Cached
- *  - 0x0 XXXF FFFF FFFF
- *
- *  - 0x1 00X0 0000 0000 to      Boot Bus     Uncached
- *  - 0x1 00XF FFFF FFFF
- *
- *  - 0x1 01X0 0000 0000 to      Other NCB    Uncached
- *  - 0x1 FFXF FFFF FFFF         devices
- *
- * Decode of all Octeon addresses
- */
-typedef union {
-
-        uint64_t u64;
-        /* mapped or unmapped virtual address */
-        struct {
-                uint64_t R:2;
-                uint64_t offset:62;
-        } sva;
-
-        /* mapped USEG virtual addresses (typically) */
-        struct {
-                uint64_t zeroes:33;
-                uint64_t offset:31;
-        } suseg;
-
-        /* mapped or unmapped virtual address */
-        struct {
-                uint64_t ones:33;
-                uint64_t sp:2;
-                uint64_t offset:29;
-        } sxkseg;
-
-        /*
-         * physical address accessed through xkphys unmapped virtual
-         * address.
-         */
-        struct {
-                uint64_t R:2;   /* CVMX_MIPS_SPACE_XKPHYS in this case */
-                uint64_t cca:3; /* ignored by octeon */
-                uint64_t mbz:10;
-                uint64_t pa:49; /* physical address */
-        } sxkphys;
-
-        /* physical address */
-        struct {
-                uint64_t mbz:15;
-                /* if set, the address is uncached and resides on MCB bus */
-                uint64_t is_io:1;
-                /*
-                 * the hardware ignores this field when is_io==0, else
-                 * device ID.
-                 */
-                uint64_t did:8;
-                /* the hardware ignores <39:36> in Octeon I */
-                uint64_t unaddr:4;
-                uint64_t offset:36;
-        } sphys;
-
-        /* physical mem address */
-        struct {
-                /* techically, <47:40> are dont-cares */
-                uint64_t zeroes:24;
-                /* the hardware ignores <39:36> in Octeon I */
-                uint64_t unaddr:4;
-                uint64_t offset:36;
-        } smem;
-
-        /* physical IO address */
-        struct {
-                uint64_t mem_region:2;
-                uint64_t mbz:13;
-                /* 1 in this case */
-                uint64_t is_io:1;
-                /*
-                 * The hardware ignores this field when is_io==0, else
-                 * device ID.
-                 */
-                uint64_t did:8;
-                /* the hardware ignores <39:36> in Octeon I */
-                uint64_t unaddr:4;
-                uint64_t offset:36;
-        } sio;
-
-        /*
-         * Scratchpad virtual address - accessed through a window at
-         * the end of kseg3
-         */
-        struct {
-                uint64_t ones:49;
-                /* CVMX_ADD_WIN_SCR (0) in this case */
-                cvmx_add_win_dec_t csrdec:2;
-                uint64_t addr:13;
-        } sscr;
-
-        /* there should only be stores to IOBDMA space, no loads */
-        /*
-         * IOBDMA virtual address - accessed through a window at the
-         * end of kseg3
-         */
-        struct {
-                uint64_t ones:49;
-                uint64_t csrdec:2;      /* CVMX_ADD_WIN_DMA (1) in this case */
-                uint64_t unused2:3;
-                uint64_t type:3;
-                uint64_t addr:7;
-        } sdma;
-
-        struct {
-                uint64_t didspace:24;
-                uint64_t unused:40;
-        } sfilldidspace;
-
-} cvmx_addr_t;
-
-/* These macros for used by 32 bit applications */
-
-#define CVMX_MIPS32_SPACE_KSEG0 1l
-#define CVMX_ADD_SEG32(segment, add) \
-        (((int32_t)segment << 31) | (int32_t)(add))
-
-/*
- * Currently all IOs are performed using XKPHYS addressing. Linux uses
- * the CvmMemCtl register to enable XKPHYS addressing to IO space from
- * user mode.  Future OSes may need to change the upper bits of IO
- * addresses. The following define controls the upper two bits for all
- * IO addresses generated by the simple executive library.
- */
-#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
-
-/* These macros simplify the process of creating common IO addresses */
-#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
-#ifndef CVMX_ADD_IO_SEG
-#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
-#endif
-#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
-#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
-#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
-
-  /* from include/ncb_rsl_id.v */
-#define CVMX_OCT_DID_MIS 0ULL   /* misc stuff */
-#define CVMX_OCT_DID_GMX0 1ULL
-#define CVMX_OCT_DID_GMX1 2ULL
-#define CVMX_OCT_DID_PCI 3ULL
-#define CVMX_OCT_DID_KEY 4ULL
-#define CVMX_OCT_DID_FPA 5ULL
-#define CVMX_OCT_DID_DFA 6ULL
-#define CVMX_OCT_DID_ZIP 7ULL
-#define CVMX_OCT_DID_RNG 8ULL
-#define CVMX_OCT_DID_IPD 9ULL
-#define CVMX_OCT_DID_PKT 10ULL
-#define CVMX_OCT_DID_TIM 11ULL
-#define CVMX_OCT_DID_TAG 12ULL
-  /* the rest are not on the IO bus */
-#define CVMX_OCT_DID_L2C 16ULL
-#define CVMX_OCT_DID_LMC 17ULL
-#define CVMX_OCT_DID_SPX0 18ULL
-#define CVMX_OCT_DID_SPX1 19ULL
-#define CVMX_OCT_DID_PIP 20ULL
-#define CVMX_OCT_DID_ASX0 22ULL
-#define CVMX_OCT_DID_ASX1 23ULL
-#define CVMX_OCT_DID_IOB 30ULL
-
-#define CVMX_OCT_DID_PKT_SEND       CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
-#define CVMX_OCT_DID_TAG_SWTAG      CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
-#define CVMX_OCT_DID_TAG_TAG1       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
-#define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
-#define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
-#define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
-#define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
-#define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
-#define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
-#define CVMX_OCT_DID_KEY_RW         CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
-#define CVMX_OCT_DID_PCI_6          CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
-#define CVMX_OCT_DID_MIS_BOO        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
-#define CVMX_OCT_DID_PCI_RML        CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
-#define CVMX_OCT_DID_IPD_CSR        CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
-#define CVMX_OCT_DID_DFA_CSR        CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
-#define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
-#define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
-
-#endif /* __CVMX_ADDRESS_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
index 542ee09510b..30d68f2365e 100644
--- a/arch/mips/include/asm/octeon/cvmx-agl-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -106,7 +106,6 @@
 union cvmx_agl_gmx_bad_reg {
         uint64_t u64;
         struct cvmx_agl_gmx_bad_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_38_63:26;
                 uint64_t txpsh1:1;
                 uint64_t txpop1:1;
@@ -121,25 +120,8 @@ union cvmx_agl_gmx_bad_reg {
                 uint64_t reserved_4_21:18;
                 uint64_t out_ovr:2;
                 uint64_t reserved_0_1:2;
-#else
-                uint64_t reserved_0_1:2;
-                uint64_t out_ovr:2;
-                uint64_t reserved_4_21:18;
-                uint64_t loststat:2;
-                uint64_t reserved_24_25:2;
-                uint64_t statovr:1;
-                uint64_t reserved_27_31:5;
-                uint64_t ovrflw:1;
-                uint64_t txpop:1;
-                uint64_t txpsh:1;
-                uint64_t ovrflw1:1;
-                uint64_t txpop1:1;
-                uint64_t txpsh1:1;
-                uint64_t reserved_38_63:26;
-#endif
         } s;
         struct cvmx_agl_gmx_bad_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_38_63:26;
                 uint64_t txpsh1:1;
                 uint64_t txpop1:1;
@@ -154,26 +136,9 @@ union cvmx_agl_gmx_bad_reg {
                 uint64_t reserved_4_21:18;
                 uint64_t out_ovr:2;
                 uint64_t reserved_0_1:2;
-#else
-                uint64_t reserved_0_1:2;
-                uint64_t out_ovr:2;
-                uint64_t reserved_4_21:18;
-                uint64_t loststat:1;
-                uint64_t reserved_23_25:3;
-                uint64_t statovr:1;
-                uint64_t reserved_27_31:5;
-                uint64_t ovrflw:1;
-                uint64_t txpop:1;
-                uint64_t txpsh:1;
-                uint64_t ovrflw1:1;
-                uint64_t txpop1:1;
-                uint64_t txpsh1:1;
-                uint64_t reserved_38_63:26;
-#endif
         } cn52xx;
         struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_bad_reg_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_35_63:29;
                 uint64_t txpsh:1;
                 uint64_t txpop:1;
@@ -185,64 +150,32 @@ union cvmx_agl_gmx_bad_reg {
                 uint64_t reserved_3_21:19;
                 uint64_t out_ovr:1;
                 uint64_t reserved_0_1:2;
-#else
-                uint64_t reserved_0_1:2;
-                uint64_t out_ovr:1;
-                uint64_t reserved_3_21:19;
-                uint64_t loststat:1;
-                uint64_t reserved_23_25:3;
-                uint64_t statovr:1;
-                uint64_t reserved_27_31:5;
-                uint64_t ovrflw:1;
-                uint64_t txpop:1;
-                uint64_t txpsh:1;
-                uint64_t reserved_35_63:29;
-#endif
         } cn56xx;
         struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
-        struct cvmx_agl_gmx_bad_reg_s cn61xx;
         struct cvmx_agl_gmx_bad_reg_s cn63xx;
         struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
-        struct cvmx_agl_gmx_bad_reg_s cn66xx;
-        struct cvmx_agl_gmx_bad_reg_s cn68xx;
-        struct cvmx_agl_gmx_bad_reg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_bist {
         uint64_t u64;
         struct cvmx_agl_gmx_bist_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_25_63:39;
                 uint64_t status:25;
-#else
-                uint64_t status:25;
-                uint64_t reserved_25_63:39;
-#endif
         } s;
         struct cvmx_agl_gmx_bist_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t status:10;
-#else
-                uint64_t status:10;
-                uint64_t reserved_10_63:54;
-#endif
         } cn52xx;
         struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_bist_cn52xx cn56xx;
         struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
-        struct cvmx_agl_gmx_bist_s cn61xx;
         struct cvmx_agl_gmx_bist_s cn63xx;
         struct cvmx_agl_gmx_bist_s cn63xxp1;
-        struct cvmx_agl_gmx_bist_s cn66xx;
-        struct cvmx_agl_gmx_bist_s cn68xx;
-        struct cvmx_agl_gmx_bist_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_drv_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_drv_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_49_63:15;
                 uint64_t byp_en1:1;
                 uint64_t reserved_45_47:3;
@@ -255,39 +188,16 @@ union cvmx_agl_gmx_drv_ctl {
                 uint64_t pctl:5;
                 uint64_t reserved_5_7:3;
                 uint64_t nctl:5;
-#else
-                uint64_t nctl:5;
-                uint64_t reserved_5_7:3;
-                uint64_t pctl:5;
-                uint64_t reserved_13_15:3;
-                uint64_t byp_en:1;
-                uint64_t reserved_17_31:15;
-                uint64_t nctl1:5;
-                uint64_t reserved_37_39:3;
-                uint64_t pctl1:5;
-                uint64_t reserved_45_47:3;
-                uint64_t byp_en1:1;
-                uint64_t reserved_49_63:15;
-#endif
         } s;
         struct cvmx_agl_gmx_drv_ctl_s cn52xx;
         struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_drv_ctl_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t byp_en:1;
                 uint64_t reserved_13_15:3;
                 uint64_t pctl:5;
                 uint64_t reserved_5_7:3;
                 uint64_t nctl:5;
-#else
-                uint64_t nctl:5;
-                uint64_t reserved_5_7:3;
-                uint64_t pctl:5;
-                uint64_t reserved_13_15:3;
-                uint64_t byp_en:1;
-                uint64_t reserved_17_63:47;
-#endif
         } cn56xx;
         struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
 };
@@ -295,15 +205,9 @@ union cvmx_agl_gmx_drv_ctl {
 union cvmx_agl_gmx_inf_mode {
         uint64_t u64;
         struct cvmx_agl_gmx_inf_mode_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t en:1;
                 uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t en:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_agl_gmx_inf_mode_s cn52xx;
         struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
@@ -314,7 +218,6 @@ union cvmx_agl_gmx_inf_mode {
 union cvmx_agl_gmx_prtx_cfg {
         uint64_t u64;
         struct cvmx_agl_gmx_prtx_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t tx_idle:1;
                 uint64_t rx_idle:1;
@@ -328,24 +231,8 @@ union cvmx_agl_gmx_prtx_cfg {
                 uint64_t duplex:1;
                 uint64_t speed:1;
                 uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t speed:1;
-                uint64_t duplex:1;
-                uint64_t slottime:1;
-                uint64_t rx_en:1;
-                uint64_t tx_en:1;
-                uint64_t burst:1;
-                uint64_t reserved_7_7:1;
-                uint64_t speed_msb:1;
-                uint64_t reserved_9_11:3;
-                uint64_t rx_idle:1;
-                uint64_t tx_idle:1;
-                uint64_t reserved_14_63:50;
-#endif
         } s;
         struct cvmx_agl_gmx_prtx_cfg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t tx_en:1;
                 uint64_t rx_en:1;
@@ -353,230 +240,139 @@ union cvmx_agl_gmx_prtx_cfg {
                 uint64_t duplex:1;
                 uint64_t speed:1;
                 uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t speed:1;
-                uint64_t duplex:1;
-                uint64_t slottime:1;
-                uint64_t rx_en:1;
-                uint64_t tx_en:1;
-                uint64_t reserved_6_63:58;
-#endif
         } cn52xx;
         struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
         struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
-        struct cvmx_agl_gmx_prtx_cfg_s cn61xx;
         struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
         struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
-        struct cvmx_agl_gmx_prtx_cfg_s cn66xx;
-        struct cvmx_agl_gmx_prtx_cfg_s cn68xx;
-        struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam0 {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_adr_cam0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx;
-        struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx;
-        struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam1 {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_adr_cam1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx;
-        struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx;
-        struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam2 {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_adr_cam2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx;
-        struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx;
-        struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam3 {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_adr_cam3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx;
-        struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx;
-        struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam4 {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_adr_cam4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx;
-        struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx;
-        struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam5 {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_adr_cam5_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t adr:64;
-#else
                 uint64_t adr:64;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx;
-        struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx;
-        struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam_en {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t en:8;
-#else
-                uint64_t en:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx;
-        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx;
-        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_adr_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t cam_mode:1;
                 uint64_t mcst:2;
                 uint64_t bcst:1;
-#else
-                uint64_t bcst:1;
-                uint64_t mcst:2;
-                uint64_t cam_mode:1;
-                uint64_t reserved_4_63:60;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx;
-        struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx;
-        struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_decision {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_decision_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t cnt:5;
-#else
-                uint64_t cnt:5;
-                uint64_t reserved_5_63:59;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_decision_s cn52xx;
         struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_decision_s cn56xx;
         struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_decision_s cn61xx;
         struct cvmx_agl_gmx_rxx_decision_s cn63xx;
         struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_decision_s cn66xx;
-        struct cvmx_agl_gmx_rxx_decision_s cn68xx;
-        struct cvmx_agl_gmx_rxx_decision_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_chk {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_frm_chk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t niberr:1;
                 uint64_t skperr:1;
@@ -588,22 +384,8 @@ union cvmx_agl_gmx_rxx_frm_chk {
                 uint64_t maxerr:1;
                 uint64_t carext:1;
                 uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t skperr:1;
                 uint64_t rcverr:1;
@@ -614,34 +396,17 @@ union cvmx_agl_gmx_rxx_frm_chk {
                 uint64_t maxerr:1;
                 uint64_t reserved_1_1:1;
                 uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t reserved_1_1:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_63:55;
-#endif
         } cn52xx;
         struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
         struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx;
         struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
         struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_frm_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_13_63:51;
                 uint64_t ptp_mode:1;
                 uint64_t reserved_11_11:1;
@@ -656,25 +421,8 @@ union cvmx_agl_gmx_rxx_frm_ctl {
                 uint64_t ctl_drp:1;
                 uint64_t pre_strp:1;
                 uint64_t pre_chk:1;
-#else
-                uint64_t pre_chk:1;
-                uint64_t pre_strp:1;
-                uint64_t ctl_drp:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_smac:1;
-                uint64_t pre_free:1;
-                uint64_t vlan_len:1;
-                uint64_t pad_len:1;
-                uint64_t pre_align:1;
-                uint64_t null_dis:1;
-                uint64_t reserved_11_11:1;
-                uint64_t ptp_mode:1;
-                uint64_t reserved_13_63:51;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t pre_align:1;
                 uint64_t pad_len:1;
@@ -686,104 +434,59 @@ union cvmx_agl_gmx_rxx_frm_ctl {
                 uint64_t ctl_drp:1;
                 uint64_t pre_strp:1;
                 uint64_t pre_chk:1;
-#else
-                uint64_t pre_chk:1;
-                uint64_t pre_strp:1;
-                uint64_t ctl_drp:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_smac:1;
-                uint64_t pre_free:1;
-                uint64_t vlan_len:1;
-                uint64_t pad_len:1;
-                uint64_t pre_align:1;
-                uint64_t reserved_10_63:54;
-#endif
         } cn52xx;
         struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
         struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx;
         struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
         struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_max {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_frm_max_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t len:16;
-#else
-                uint64_t len:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
         struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
         struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_frm_max_s cn61xx;
         struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
         struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_frm_max_s cn66xx;
-        struct cvmx_agl_gmx_rxx_frm_max_s cn68xx;
-        struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_min {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_frm_min_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t len:16;
-#else
-                uint64_t len:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
         struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
         struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_frm_min_s cn61xx;
         struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
         struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_frm_min_s cn66xx;
-        struct cvmx_agl_gmx_rxx_frm_min_s cn68xx;
-        struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_ifg {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_ifg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t ifg:4;
-#else
-                uint64_t ifg:4;
-                uint64_t reserved_4_63:60;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
         struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
         struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_ifg_s cn61xx;
         struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
         struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_ifg_s cn66xx;
-        struct cvmx_agl_gmx_rxx_ifg_s cn68xx;
-        struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_en {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t pause_drp:1;
                 uint64_t phy_dupx:1;
@@ -805,32 +508,8 @@ union cvmx_agl_gmx_rxx_int_en {
                 uint64_t maxerr:1;
                 uint64_t carext:1;
                 uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_int_en_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t pause_drp:1;
                 uint64_t reserved_16_18:3;
@@ -850,43 +529,17 @@ union cvmx_agl_gmx_rxx_int_en {
                 uint64_t maxerr:1;
                 uint64_t reserved_1_1:1;
                 uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t reserved_1_1:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t reserved_16_18:3;
-                uint64_t pause_drp:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
         struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
-        struct cvmx_agl_gmx_rxx_int_en_s cn61xx;
         struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
         struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_int_en_s cn66xx;
-        struct cvmx_agl_gmx_rxx_int_en_s cn68xx;
-        struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_reg {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t pause_drp:1;
                 uint64_t phy_dupx:1;
@@ -908,32 +561,8 @@ union cvmx_agl_gmx_rxx_int_reg {
                 uint64_t maxerr:1;
                 uint64_t carext:1;
                 uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t pause_drp:1;
                 uint64_t reserved_16_18:3;
@@ -953,1130 +582,666 @@ union cvmx_agl_gmx_rxx_int_reg {
                 uint64_t maxerr:1;
                 uint64_t reserved_1_1:1;
                 uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t reserved_1_1:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t reserved_16_18:3;
-                uint64_t pause_drp:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
         struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn61xx;
         struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
         struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn66xx;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn68xx;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_jabber {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_jabber_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt:16;
-#else
-                uint64_t cnt:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
         struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
         struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_jabber_s cn61xx;
         struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
         struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_jabber_s cn66xx;
-        struct cvmx_agl_gmx_rxx_jabber_s cn68xx;
-        struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_pause_drop_time {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t status:16;
-#else
-                uint64_t status:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx;
-        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx;
-        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_rx_inbnd {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_rx_inbnd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t duplex:1;
                 uint64_t speed:2;
                 uint64_t status:1;
-#else
-                uint64_t status:1;
-                uint64_t speed:2;
-                uint64_t duplex:1;
-                uint64_t reserved_4_63:60;
-#endif
         } s;
-        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx;
         struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
         struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx;
-        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx;
-        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t rd_clr:1;
-#else
-                uint64_t rd_clr:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_octs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t cnt:48;
-#else
-                uint64_t cnt:48;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t cnt:48;
-#else
-                uint64_t cnt:48;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_dmac {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t cnt:48;
-#else
-                uint64_t cnt:48;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_drp {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t cnt:48;
-#else
-                uint64_t cnt:48;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_pkts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_bad {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_dmac {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_drp {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx;
-        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rxx_udd_skp {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_udd_skp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t fcssel:1;
                 uint64_t reserved_7_7:1;
                 uint64_t len:7;
-#else
-                uint64_t len:7;
-                uint64_t reserved_7_7:1;
-                uint64_t fcssel:1;
-                uint64_t reserved_9_63:55;
-#endif
         } s;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
-        struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
-        struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx;
-        struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx;
-        struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_dropx {
         uint64_t u64;
         struct cvmx_agl_gmx_rx_bp_dropx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t mark:6;
-#else
-                uint64_t mark:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
-        struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
-        struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx;
-        struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx;
-        struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_offx {
         uint64_t u64;
         struct cvmx_agl_gmx_rx_bp_offx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t mark:6;
-#else
-                uint64_t mark:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
         struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
         struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
         struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
-        struct cvmx_agl_gmx_rx_bp_offx_s cn61xx;
         struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
         struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
-        struct cvmx_agl_gmx_rx_bp_offx_s cn66xx;
-        struct cvmx_agl_gmx_rx_bp_offx_s cn68xx;
-        struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_onx {
         uint64_t u64;
         struct cvmx_agl_gmx_rx_bp_onx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t mark:9;
-#else
-                uint64_t mark:9;
-                uint64_t reserved_9_63:55;
-#endif
         } s;
         struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
         struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
         struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
         struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
-        struct cvmx_agl_gmx_rx_bp_onx_s cn61xx;
         struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
         struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
-        struct cvmx_agl_gmx_rx_bp_onx_s cn66xx;
-        struct cvmx_agl_gmx_rx_bp_onx_s cn68xx;
-        struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_prt_info {
         uint64_t u64;
         struct cvmx_agl_gmx_rx_prt_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t drop:2;
                 uint64_t reserved_2_15:14;
                 uint64_t commit:2;
-#else
-                uint64_t commit:2;
-                uint64_t reserved_2_15:14;
-                uint64_t drop:2;
-                uint64_t reserved_18_63:46;
-#endif
         } s;
         struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
         struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
         struct cvmx_agl_gmx_rx_prt_info_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t drop:1;
                 uint64_t reserved_1_15:15;
                 uint64_t commit:1;
-#else
-                uint64_t commit:1;
-                uint64_t reserved_1_15:15;
-                uint64_t drop:1;
-                uint64_t reserved_17_63:47;
-#endif
         } cn56xx;
         struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
-        struct cvmx_agl_gmx_rx_prt_info_s cn61xx;
         struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
         struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
-        struct cvmx_agl_gmx_rx_prt_info_s cn66xx;
-        struct cvmx_agl_gmx_rx_prt_info_s cn68xx;
-        struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_rx_tx_status {
         uint64_t u64;
         struct cvmx_agl_gmx_rx_tx_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t tx:2;
                 uint64_t reserved_2_3:2;
                 uint64_t rx:2;
-#else
-                uint64_t rx:2;
-                uint64_t reserved_2_3:2;
-                uint64_t tx:2;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
         struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
         struct cvmx_agl_gmx_rx_tx_status_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t tx:1;
                 uint64_t reserved_1_3:3;
                 uint64_t rx:1;
-#else
-                uint64_t rx:1;
-                uint64_t reserved_1_3:3;
-                uint64_t tx:1;
-                uint64_t reserved_5_63:59;
-#endif
         } cn56xx;
         struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
-        struct cvmx_agl_gmx_rx_tx_status_s cn61xx;
         struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
         struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
-        struct cvmx_agl_gmx_rx_tx_status_s cn66xx;
-        struct cvmx_agl_gmx_rx_tx_status_s cn68xx;
-        struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_smacx {
         uint64_t u64;
         struct cvmx_agl_gmx_smacx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t smac:48;
-#else
-                uint64_t smac:48;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_agl_gmx_smacx_s cn52xx;
         struct cvmx_agl_gmx_smacx_s cn52xxp1;
         struct cvmx_agl_gmx_smacx_s cn56xx;
         struct cvmx_agl_gmx_smacx_s cn56xxp1;
-        struct cvmx_agl_gmx_smacx_s cn61xx;
         struct cvmx_agl_gmx_smacx_s cn63xx;
         struct cvmx_agl_gmx_smacx_s cn63xxp1;
-        struct cvmx_agl_gmx_smacx_s cn66xx;
-        struct cvmx_agl_gmx_smacx_s cn68xx;
-        struct cvmx_agl_gmx_smacx_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_stat_bp {
         uint64_t u64;
         struct cvmx_agl_gmx_stat_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t bp:1;
                 uint64_t cnt:16;
-#else
-                uint64_t cnt:16;
-                uint64_t bp:1;
-                uint64_t reserved_17_63:47;
-#endif
         } s;
         struct cvmx_agl_gmx_stat_bp_s cn52xx;
         struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
         struct cvmx_agl_gmx_stat_bp_s cn56xx;
         struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
-        struct cvmx_agl_gmx_stat_bp_s cn61xx;
         struct cvmx_agl_gmx_stat_bp_s cn63xx;
         struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
-        struct cvmx_agl_gmx_stat_bp_s cn66xx;
-        struct cvmx_agl_gmx_stat_bp_s cn68xx;
-        struct cvmx_agl_gmx_stat_bp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_append {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_append_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t force_fcs:1;
                 uint64_t fcs:1;
                 uint64_t pad:1;
                 uint64_t preamble:1;
-#else
-                uint64_t preamble:1;
-                uint64_t pad:1;
-                uint64_t fcs:1;
-                uint64_t force_fcs:1;
-                uint64_t reserved_4_63:60;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_append_s cn52xx;
         struct cvmx_agl_gmx_txx_append_s cn52xxp1;
         struct cvmx_agl_gmx_txx_append_s cn56xx;
         struct cvmx_agl_gmx_txx_append_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_append_s cn61xx;
         struct cvmx_agl_gmx_txx_append_s cn63xx;
         struct cvmx_agl_gmx_txx_append_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_append_s cn66xx;
-        struct cvmx_agl_gmx_txx_append_s cn68xx;
-        struct cvmx_agl_gmx_txx_append_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_clk {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_clk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t clk_cnt:6;
-#else
-                uint64_t clk_cnt:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
-        struct cvmx_agl_gmx_txx_clk_s cn61xx;
         struct cvmx_agl_gmx_txx_clk_s cn63xx;
         struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_clk_s cn66xx;
-        struct cvmx_agl_gmx_txx_clk_s cn68xx;
-        struct cvmx_agl_gmx_txx_clk_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t xsdef_en:1;
                 uint64_t xscol_en:1;
-#else
-                uint64_t xscol_en:1;
-                uint64_t xsdef_en:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_ctl_s cn52xx;
         struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_txx_ctl_s cn56xx;
         struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_ctl_s cn61xx;
         struct cvmx_agl_gmx_txx_ctl_s cn63xx;
         struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_ctl_s cn66xx;
-        struct cvmx_agl_gmx_txx_ctl_s cn68xx;
-        struct cvmx_agl_gmx_txx_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_min_pkt {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_min_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t min_size:8;
-#else
-                uint64_t min_size:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
         struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
         struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
         struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_min_pkt_s cn61xx;
         struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
         struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_min_pkt_s cn66xx;
-        struct cvmx_agl_gmx_txx_min_pkt_s cn68xx;
-        struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_pkt_interval {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t interval:16;
-#else
-                uint64_t interval:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx;
-        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx;
-        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_pkt_time {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t time:16;
-#else
-                uint64_t time:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx;
-        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx;
-        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_togo {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_pause_togo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t time:16;
-#else
-                uint64_t time:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
         struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_pause_togo_s cn61xx;
         struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
         struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_pause_togo_s cn66xx;
-        struct cvmx_agl_gmx_txx_pause_togo_s cn68xx;
-        struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_zero {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_pause_zero_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t send:1;
-#else
-                uint64_t send:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
         struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_pause_zero_s cn61xx;
         struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
         struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_pause_zero_s cn66xx;
-        struct cvmx_agl_gmx_txx_pause_zero_s cn68xx;
-        struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_soft_pause {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_soft_pause_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t time:16;
-#else
-                uint64_t time:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
         struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
         struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
         struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_soft_pause_s cn61xx;
         struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
         struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_soft_pause_s cn66xx;
-        struct cvmx_agl_gmx_txx_soft_pause_s cn68xx;
-        struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat0 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t xsdef:32;
                 uint64_t xscol:32;
-#else
-                uint64_t xscol:32;
-                uint64_t xsdef:32;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat0_s cn52xx;
         struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat0_s cn56xx;
         struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat0_s cn61xx;
         struct cvmx_agl_gmx_txx_stat0_s cn63xx;
         struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat0_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat0_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat0_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat1 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t scol:32;
                 uint64_t mcol:32;
-#else
-                uint64_t mcol:32;
-                uint64_t scol:32;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat1_s cn52xx;
         struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat1_s cn56xx;
         struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat1_s cn61xx;
         struct cvmx_agl_gmx_txx_stat1_s cn63xx;
         struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat1_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat1_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat1_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat2 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t octs:48;
-#else
-                uint64_t octs:48;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat2_s cn52xx;
         struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat2_s cn56xx;
         struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat2_s cn61xx;
         struct cvmx_agl_gmx_txx_stat2_s cn63xx;
         struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat2_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat2_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat2_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat3 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t pkts:32;
-#else
-                uint64_t pkts:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat3_s cn52xx;
         struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat3_s cn56xx;
         struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat3_s cn61xx;
         struct cvmx_agl_gmx_txx_stat3_s cn63xx;
         struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat3_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat3_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat3_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat4 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t hist1:32;
                 uint64_t hist0:32;
-#else
-                uint64_t hist0:32;
-                uint64_t hist1:32;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat4_s cn52xx;
         struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat4_s cn56xx;
         struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat4_s cn61xx;
         struct cvmx_agl_gmx_txx_stat4_s cn63xx;
         struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat4_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat4_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat4_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat5 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat5_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t hist3:32;
                 uint64_t hist2:32;
-#else
-                uint64_t hist2:32;
-                uint64_t hist3:32;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat5_s cn52xx;
         struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat5_s cn56xx;
         struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat5_s cn61xx;
         struct cvmx_agl_gmx_txx_stat5_s cn63xx;
         struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat5_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat5_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat5_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat6 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat6_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t hist5:32;
                 uint64_t hist4:32;
-#else
-                uint64_t hist4:32;
-                uint64_t hist5:32;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat6_s cn52xx;
         struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat6_s cn56xx;
         struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat6_s cn61xx;
         struct cvmx_agl_gmx_txx_stat6_s cn63xx;
         struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat6_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat6_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat6_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat7 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat7_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t hist7:32;
                 uint64_t hist6:32;
-#else
-                uint64_t hist6:32;
-                uint64_t hist7:32;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat7_s cn52xx;
         struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat7_s cn56xx;
         struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat7_s cn61xx;
         struct cvmx_agl_gmx_txx_stat7_s cn63xx;
         struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat7_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat7_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat7_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat8 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat8_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t mcst:32;
                 uint64_t bcst:32;
-#else
-                uint64_t bcst:32;
-                uint64_t mcst:32;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat8_s cn52xx;
         struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat8_s cn56xx;
         struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat8_s cn61xx;
         struct cvmx_agl_gmx_txx_stat8_s cn63xx;
         struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat8_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat8_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat8_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat9 {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stat9_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t undflw:32;
                 uint64_t ctl:32;
-#else
-                uint64_t ctl:32;
-                uint64_t undflw:32;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stat9_s cn52xx;
         struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat9_s cn56xx;
         struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stat9_s cn61xx;
         struct cvmx_agl_gmx_txx_stat9_s cn63xx;
         struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stat9_s cn66xx;
-        struct cvmx_agl_gmx_txx_stat9_s cn68xx;
-        struct cvmx_agl_gmx_txx_stat9_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_stats_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_stats_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t rd_clr:1;
-#else
-                uint64_t rd_clr:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx;
-        struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx;
-        struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_txx_thresh {
         uint64_t u64;
         struct cvmx_agl_gmx_txx_thresh_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t cnt:6;
-#else
-                uint64_t cnt:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_agl_gmx_txx_thresh_s cn52xx;
         struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
         struct cvmx_agl_gmx_txx_thresh_s cn56xx;
         struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
-        struct cvmx_agl_gmx_txx_thresh_s cn61xx;
         struct cvmx_agl_gmx_txx_thresh_s cn63xx;
         struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
-        struct cvmx_agl_gmx_txx_thresh_s cn66xx;
-        struct cvmx_agl_gmx_txx_thresh_s cn68xx;
-        struct cvmx_agl_gmx_txx_thresh_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_bp {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t bp:2;
-#else
-                uint64_t bp:2;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_bp_s cn52xx;
         struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
         struct cvmx_agl_gmx_tx_bp_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t bp:1;
-#else
-                uint64_t bp:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn56xx;
         struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
-        struct cvmx_agl_gmx_tx_bp_s cn61xx;
         struct cvmx_agl_gmx_tx_bp_s cn63xx;
         struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_bp_s cn66xx;
-        struct cvmx_agl_gmx_tx_bp_s cn68xx;
-        struct cvmx_agl_gmx_tx_bp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_col_attempt {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_col_attempt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t limit:5;
-#else
-                uint64_t limit:5;
-                uint64_t reserved_5_63:59;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
         struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
         struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
         struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
-        struct cvmx_agl_gmx_tx_col_attempt_s cn61xx;
         struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
         struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_col_attempt_s cn66xx;
-        struct cvmx_agl_gmx_tx_col_attempt_s cn68xx;
-        struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_ifg {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_ifg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t ifg2:4;
                 uint64_t ifg1:4;
-#else
-                uint64_t ifg1:4;
-                uint64_t ifg2:4;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_ifg_s cn52xx;
         struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
         struct cvmx_agl_gmx_tx_ifg_s cn56xx;
         struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
-        struct cvmx_agl_gmx_tx_ifg_s cn61xx;
         struct cvmx_agl_gmx_tx_ifg_s cn63xx;
         struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_ifg_s cn66xx;
-        struct cvmx_agl_gmx_tx_ifg_s cn68xx;
-        struct cvmx_agl_gmx_tx_ifg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_int_en {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_22_63:42;
                 uint64_t ptp_lost:2;
                 uint64_t reserved_18_19:2;
@@ -2089,23 +1254,8 @@ union cvmx_agl_gmx_tx_int_en {
                 uint64_t undflw:2;
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:2;
-                uint64_t reserved_4_7:4;
-                uint64_t xscol:2;
-                uint64_t reserved_10_11:2;
-                uint64_t xsdef:2;
-                uint64_t reserved_14_15:2;
-                uint64_t late_col:2;
-                uint64_t reserved_18_19:2;
-                uint64_t ptp_lost:2;
-                uint64_t reserved_22_63:42;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_int_en_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t late_col:2;
                 uint64_t reserved_14_15:2;
@@ -2116,22 +1266,9 @@ union cvmx_agl_gmx_tx_int_en {
                 uint64_t undflw:2;
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:2;
-                uint64_t reserved_4_7:4;
-                uint64_t xscol:2;
-                uint64_t reserved_10_11:2;
-                uint64_t xsdef:2;
-                uint64_t reserved_14_15:2;
-                uint64_t late_col:2;
-                uint64_t reserved_18_63:46;
-#endif
         } cn52xx;
         struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_tx_int_en_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t late_col:1;
                 uint64_t reserved_13_15:3;
@@ -2142,32 +1279,15 @@ union cvmx_agl_gmx_tx_int_en {
                 uint64_t undflw:1;
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:1;
-                uint64_t reserved_3_7:5;
-                uint64_t xscol:1;
-                uint64_t reserved_9_11:3;
-                uint64_t xsdef:1;
-                uint64_t reserved_13_15:3;
-                uint64_t late_col:1;
-                uint64_t reserved_17_63:47;
-#endif
         } cn56xx;
         struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
-        struct cvmx_agl_gmx_tx_int_en_s cn61xx;
         struct cvmx_agl_gmx_tx_int_en_s cn63xx;
         struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_int_en_s cn66xx;
-        struct cvmx_agl_gmx_tx_int_en_s cn68xx;
-        struct cvmx_agl_gmx_tx_int_en_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_int_reg {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_22_63:42;
                 uint64_t ptp_lost:2;
                 uint64_t reserved_18_19:2;
@@ -2180,23 +1300,8 @@ union cvmx_agl_gmx_tx_int_reg {
                 uint64_t undflw:2;
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:2;
-                uint64_t reserved_4_7:4;
-                uint64_t xscol:2;
-                uint64_t reserved_10_11:2;
-                uint64_t xsdef:2;
-                uint64_t reserved_14_15:2;
-                uint64_t late_col:2;
-                uint64_t reserved_18_19:2;
-                uint64_t ptp_lost:2;
-                uint64_t reserved_22_63:42;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_int_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t late_col:2;
                 uint64_t reserved_14_15:2;
@@ -2207,22 +1312,9 @@ union cvmx_agl_gmx_tx_int_reg {
                 uint64_t undflw:2;
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:2;
-                uint64_t reserved_4_7:4;
-                uint64_t xscol:2;
-                uint64_t reserved_10_11:2;
-                uint64_t xsdef:2;
-                uint64_t reserved_14_15:2;
-                uint64_t late_col:2;
-                uint64_t reserved_18_63:46;
-#endif
         } cn52xx;
         struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_tx_int_reg_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t late_col:1;
                 uint64_t reserved_13_15:3;
@@ -2233,171 +1325,96 @@ union cvmx_agl_gmx_tx_int_reg {
                 uint64_t undflw:1;
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:1;
-                uint64_t reserved_3_7:5;
-                uint64_t xscol:1;
-                uint64_t reserved_9_11:3;
-                uint64_t xsdef:1;
-                uint64_t reserved_13_15:3;
-                uint64_t late_col:1;
-                uint64_t reserved_17_63:47;
-#endif
         } cn56xx;
         struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
-        struct cvmx_agl_gmx_tx_int_reg_s cn61xx;
         struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
         struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_int_reg_s cn66xx;
-        struct cvmx_agl_gmx_tx_int_reg_s cn68xx;
-        struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_jam {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_jam_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t jam:8;
-#else
-                uint64_t jam:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_jam_s cn52xx;
         struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
         struct cvmx_agl_gmx_tx_jam_s cn56xx;
         struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
-        struct cvmx_agl_gmx_tx_jam_s cn61xx;
         struct cvmx_agl_gmx_tx_jam_s cn63xx;
         struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_jam_s cn66xx;
-        struct cvmx_agl_gmx_tx_jam_s cn68xx;
-        struct cvmx_agl_gmx_tx_jam_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_lfsr {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_lfsr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t lfsr:16;
-#else
-                uint64_t lfsr:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
         struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
         struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
         struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
-        struct cvmx_agl_gmx_tx_lfsr_s cn61xx;
         struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
         struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_lfsr_s cn66xx;
-        struct cvmx_agl_gmx_tx_lfsr_s cn68xx;
-        struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_ovr_bp {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_ovr_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t en:2;
                 uint64_t reserved_6_7:2;
                 uint64_t bp:2;
                 uint64_t reserved_2_3:2;
                 uint64_t ign_full:2;
-#else
-                uint64_t ign_full:2;
-                uint64_t reserved_2_3:2;
-                uint64_t bp:2;
-                uint64_t reserved_6_7:2;
-                uint64_t en:2;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
         struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
         struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t en:1;
                 uint64_t reserved_5_7:3;
                 uint64_t bp:1;
                 uint64_t reserved_1_3:3;
                 uint64_t ign_full:1;
-#else
-                uint64_t ign_full:1;
-                uint64_t reserved_1_3:3;
-                uint64_t bp:1;
-                uint64_t reserved_5_7:3;
-                uint64_t en:1;
-                uint64_t reserved_9_63:55;
-#endif
         } cn56xx;
         struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
-        struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx;
         struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
         struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx;
-        struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx;
-        struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_pause_pkt_dmac {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t dmac:48;
-#else
-                uint64_t dmac:48;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
-        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx;
-        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx;
-        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1;
 };
 
 union cvmx_agl_gmx_tx_pause_pkt_type {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t type:16;
-#else
-                uint64_t type:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
-        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
-        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx;
-        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx;
-        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1;
 };
 
 union cvmx_agl_prtx_ctl {
         uint64_t u64;
         struct cvmx_agl_prtx_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t drv_byp:1;
                 uint64_t reserved_62_62:1;
                 uint64_t cmp_pctl:6;
@@ -2421,38 +1438,9 @@ union cvmx_agl_prtx_ctl {
                 uint64_t enable:1;
                 uint64_t clkrst:1;
                 uint64_t mode:1;
-#else
-                uint64_t mode:1;
-                uint64_t clkrst:1;
-                uint64_t enable:1;
-                uint64_t comp:1;
-                uint64_t dllrst:1;
-                uint64_t reserved_5_7:3;
-                uint64_t clktx_set:5;
-                uint64_t reserved_13_14:2;
-                uint64_t clktx_byp:1;
-                uint64_t clkrx_set:5;
-                uint64_t reserved_21_22:2;
-                uint64_t clkrx_byp:1;
-                uint64_t clk_set:5;
-                uint64_t reserved_29_31:3;
-                uint64_t drv_nctl:6;
-                uint64_t reserved_38_39:2;
-                uint64_t drv_pctl:6;
-                uint64_t reserved_46_47:2;
-                uint64_t cmp_nctl:6;
-                uint64_t reserved_54_55:2;
-                uint64_t cmp_pctl:6;
-                uint64_t reserved_62_62:1;
-                uint64_t drv_byp:1;
-#endif
         } s;
-        struct cvmx_agl_prtx_ctl_s cn61xx;
         struct cvmx_agl_prtx_ctl_s cn63xx;
         struct cvmx_agl_prtx_ctl_s cn63xxp1;
-        struct cvmx_agl_prtx_ctl_s cn66xx;
-        struct cvmx_agl_prtx_ctl_s cn68xx;
-        struct cvmx_agl_prtx_ctl_s cn68xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
index 31eacc24b77..5de5de95311 100644
--- a/arch/mips/include/asm/octeon/cvmx-asm.h
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -32,7 +32,7 @@
 #ifndef __CVMX_ASM_H__
 #define __CVMX_ASM_H__
 
-#include <asm/octeon/octeon-model.h>
+#include "octeon-model.h"
 
 /* other useful stuff */
 #define CVMX_SYNC asm volatile ("sync" : : : "memory")
diff --git a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
deleted file mode 100644
index a1e21a3854c..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
+++ /dev/null
@@ -1,669 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_ASXX_DEFS_H__
-#define __CVMX_ASXX_DEFS_H__
-
-#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
-#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
-#define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
-#define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
-#define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
-#define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
-#define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
-
-union cvmx_asxx_gmii_rx_clk_set {
-        uint64_t u64;
-        struct cvmx_asxx_gmii_rx_clk_set_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t setting:5;
-#else
-                uint64_t setting:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
-        struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
-        struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
-};
-
-union cvmx_asxx_gmii_rx_dat_set {
-        uint64_t u64;
-        struct cvmx_asxx_gmii_rx_dat_set_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t setting:5;
-#else
-                uint64_t setting:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
-        struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
-        struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
-};
-
-union cvmx_asxx_int_en {
-        uint64_t u64;
-        struct cvmx_asxx_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t txpsh:4;
-                uint64_t txpop:4;
-                uint64_t ovrflw:4;
-#else
-                uint64_t ovrflw:4;
-                uint64_t txpop:4;
-                uint64_t txpsh:4;
-                uint64_t reserved_12_63:52;
-#endif
-        } s;
-        struct cvmx_asxx_int_en_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t txpsh:3;
-                uint64_t reserved_7_7:1;
-                uint64_t txpop:3;
-                uint64_t reserved_3_3:1;
-                uint64_t ovrflw:3;
-#else
-                uint64_t ovrflw:3;
-                uint64_t reserved_3_3:1;
-                uint64_t txpop:3;
-                uint64_t reserved_7_7:1;
-                uint64_t txpsh:3;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn30xx;
-        struct cvmx_asxx_int_en_cn30xx cn31xx;
-        struct cvmx_asxx_int_en_s cn38xx;
-        struct cvmx_asxx_int_en_s cn38xxp2;
-        struct cvmx_asxx_int_en_cn30xx cn50xx;
-        struct cvmx_asxx_int_en_s cn58xx;
-        struct cvmx_asxx_int_en_s cn58xxp1;
-};
-
-union cvmx_asxx_int_reg {
-        uint64_t u64;
-        struct cvmx_asxx_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t txpsh:4;
-                uint64_t txpop:4;
-                uint64_t ovrflw:4;
-#else
-                uint64_t ovrflw:4;
-                uint64_t txpop:4;
-                uint64_t txpsh:4;
-                uint64_t reserved_12_63:52;
-#endif
-        } s;
-        struct cvmx_asxx_int_reg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t txpsh:3;
-                uint64_t reserved_7_7:1;
-                uint64_t txpop:3;
-                uint64_t reserved_3_3:1;
-                uint64_t ovrflw:3;
-#else
-                uint64_t ovrflw:3;
-                uint64_t reserved_3_3:1;
-                uint64_t txpop:3;
-                uint64_t reserved_7_7:1;
-                uint64_t txpsh:3;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn30xx;
-        struct cvmx_asxx_int_reg_cn30xx cn31xx;
-        struct cvmx_asxx_int_reg_s cn38xx;
-        struct cvmx_asxx_int_reg_s cn38xxp2;
-        struct cvmx_asxx_int_reg_cn30xx cn50xx;
-        struct cvmx_asxx_int_reg_s cn58xx;
-        struct cvmx_asxx_int_reg_s cn58xxp1;
-};
-
-union cvmx_asxx_mii_rx_dat_set {
-        uint64_t u64;
-        struct cvmx_asxx_mii_rx_dat_set_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t setting:5;
-#else
-                uint64_t setting:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
-        struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
-};
-
-union cvmx_asxx_prt_loop {
-        uint64_t u64;
-        struct cvmx_asxx_prt_loop_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t ext_loop:4;
-                uint64_t int_loop:4;
-#else
-                uint64_t int_loop:4;
-                uint64_t ext_loop:4;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_asxx_prt_loop_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t ext_loop:3;
-                uint64_t reserved_3_3:1;
-                uint64_t int_loop:3;
-#else
-                uint64_t int_loop:3;
-                uint64_t reserved_3_3:1;
-                uint64_t ext_loop:3;
-                uint64_t reserved_7_63:57;
-#endif
-        } cn30xx;
-        struct cvmx_asxx_prt_loop_cn30xx cn31xx;
-        struct cvmx_asxx_prt_loop_s cn38xx;
-        struct cvmx_asxx_prt_loop_s cn38xxp2;
-        struct cvmx_asxx_prt_loop_cn30xx cn50xx;
-        struct cvmx_asxx_prt_loop_s cn58xx;
-        struct cvmx_asxx_prt_loop_s cn58xxp1;
-};
-
-union cvmx_asxx_rld_bypass {
-        uint64_t u64;
-        struct cvmx_asxx_rld_bypass_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t bypass:1;
-#else
-                uint64_t bypass:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_asxx_rld_bypass_s cn38xx;
-        struct cvmx_asxx_rld_bypass_s cn38xxp2;
-        struct cvmx_asxx_rld_bypass_s cn58xx;
-        struct cvmx_asxx_rld_bypass_s cn58xxp1;
-};
-
-union cvmx_asxx_rld_bypass_setting {
-        uint64_t u64;
-        struct cvmx_asxx_rld_bypass_setting_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t setting:5;
-#else
-                uint64_t setting:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_rld_bypass_setting_s cn38xx;
-        struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
-        struct cvmx_asxx_rld_bypass_setting_s cn58xx;
-        struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
-};
-
-union cvmx_asxx_rld_comp {
-        uint64_t u64;
-        struct cvmx_asxx_rld_comp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t pctl:5;
-                uint64_t nctl:4;
-#else
-                uint64_t nctl:4;
-                uint64_t pctl:5;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_asxx_rld_comp_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t pctl:4;
-                uint64_t nctl:4;
-#else
-                uint64_t nctl:4;
-                uint64_t pctl:4;
-                uint64_t reserved_8_63:56;
-#endif
-        } cn38xx;
-        struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
-        struct cvmx_asxx_rld_comp_s cn58xx;
-        struct cvmx_asxx_rld_comp_s cn58xxp1;
-};
-
-union cvmx_asxx_rld_data_drv {
-        uint64_t u64;
-        struct cvmx_asxx_rld_data_drv_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t pctl:4;
-                uint64_t nctl:4;
-#else
-                uint64_t nctl:4;
-                uint64_t pctl:4;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_asxx_rld_data_drv_s cn38xx;
-        struct cvmx_asxx_rld_data_drv_s cn38xxp2;
-        struct cvmx_asxx_rld_data_drv_s cn58xx;
-        struct cvmx_asxx_rld_data_drv_s cn58xxp1;
-};
-
-union cvmx_asxx_rld_fcram_mode {
-        uint64_t u64;
-        struct cvmx_asxx_rld_fcram_mode_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t mode:1;
-#else
-                uint64_t mode:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_asxx_rld_fcram_mode_s cn38xx;
-        struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
-};
-
-union cvmx_asxx_rld_nctl_strong {
-        uint64_t u64;
-        struct cvmx_asxx_rld_nctl_strong_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t nctl:5;
-#else
-                uint64_t nctl:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_rld_nctl_strong_s cn38xx;
-        struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
-        struct cvmx_asxx_rld_nctl_strong_s cn58xx;
-        struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
-};
-
-union cvmx_asxx_rld_nctl_weak {
-        uint64_t u64;
-        struct cvmx_asxx_rld_nctl_weak_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t nctl:5;
-#else
-                uint64_t nctl:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_rld_nctl_weak_s cn38xx;
-        struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
-        struct cvmx_asxx_rld_nctl_weak_s cn58xx;
-        struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
-};
-
-union cvmx_asxx_rld_pctl_strong {
-        uint64_t u64;
-        struct cvmx_asxx_rld_pctl_strong_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t pctl:5;
-#else
-                uint64_t pctl:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_rld_pctl_strong_s cn38xx;
-        struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
-        struct cvmx_asxx_rld_pctl_strong_s cn58xx;
-        struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
-};
-
-union cvmx_asxx_rld_pctl_weak {
-        uint64_t u64;
-        struct cvmx_asxx_rld_pctl_weak_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t pctl:5;
-#else
-                uint64_t pctl:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_rld_pctl_weak_s cn38xx;
-        struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
-        struct cvmx_asxx_rld_pctl_weak_s cn58xx;
-        struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
-};
-
-union cvmx_asxx_rld_setting {
-        uint64_t u64;
-        struct cvmx_asxx_rld_setting_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t dfaset:5;
-                uint64_t dfalag:1;
-                uint64_t dfalead:1;
-                uint64_t dfalock:1;
-                uint64_t setting:5;
-#else
-                uint64_t setting:5;
-                uint64_t dfalock:1;
-                uint64_t dfalead:1;
-                uint64_t dfalag:1;
-                uint64_t dfaset:5;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_asxx_rld_setting_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t setting:5;
-#else
-                uint64_t setting:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } cn38xx;
-        struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
-        struct cvmx_asxx_rld_setting_s cn58xx;
-        struct cvmx_asxx_rld_setting_s cn58xxp1;
-};
-
-union cvmx_asxx_rx_clk_setx {
-        uint64_t u64;
-        struct cvmx_asxx_rx_clk_setx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t setting:5;
-#else
-                uint64_t setting:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_rx_clk_setx_s cn30xx;
-        struct cvmx_asxx_rx_clk_setx_s cn31xx;
-        struct cvmx_asxx_rx_clk_setx_s cn38xx;
-        struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
-        struct cvmx_asxx_rx_clk_setx_s cn50xx;
-        struct cvmx_asxx_rx_clk_setx_s cn58xx;
-        struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
-};
-
-union cvmx_asxx_rx_prt_en {
-        uint64_t u64;
-        struct cvmx_asxx_rx_prt_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t prt_en:4;
-#else
-                uint64_t prt_en:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_asxx_rx_prt_en_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t prt_en:3;
-#else
-                uint64_t prt_en:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn30xx;
-        struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
-        struct cvmx_asxx_rx_prt_en_s cn38xx;
-        struct cvmx_asxx_rx_prt_en_s cn38xxp2;
-        struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
-        struct cvmx_asxx_rx_prt_en_s cn58xx;
-        struct cvmx_asxx_rx_prt_en_s cn58xxp1;
-};
-
-union cvmx_asxx_rx_wol {
-        uint64_t u64;
-        struct cvmx_asxx_rx_wol_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t status:1;
-                uint64_t enable:1;
-#else
-                uint64_t enable:1;
-                uint64_t status:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_asxx_rx_wol_s cn38xx;
-        struct cvmx_asxx_rx_wol_s cn38xxp2;
-};
-
-union cvmx_asxx_rx_wol_msk {
-        uint64_t u64;
-        struct cvmx_asxx_rx_wol_msk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t msk:64;
-#else
-                uint64_t msk:64;
-#endif
-        } s;
-        struct cvmx_asxx_rx_wol_msk_s cn38xx;
-        struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
-};
-
-union cvmx_asxx_rx_wol_powok {
-        uint64_t u64;
-        struct cvmx_asxx_rx_wol_powok_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t powerok:1;
-#else
-                uint64_t powerok:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_asxx_rx_wol_powok_s cn38xx;
-        struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
-};
-
-union cvmx_asxx_rx_wol_sig {
-        uint64_t u64;
-        struct cvmx_asxx_rx_wol_sig_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t sig:32;
-#else
-                uint64_t sig:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_asxx_rx_wol_sig_s cn38xx;
-        struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
-};
-
-union cvmx_asxx_tx_clk_setx {
-        uint64_t u64;
-        struct cvmx_asxx_tx_clk_setx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t setting:5;
-#else
-                uint64_t setting:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_asxx_tx_clk_setx_s cn30xx;
-        struct cvmx_asxx_tx_clk_setx_s cn31xx;
-        struct cvmx_asxx_tx_clk_setx_s cn38xx;
-        struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
-        struct cvmx_asxx_tx_clk_setx_s cn50xx;
-        struct cvmx_asxx_tx_clk_setx_s cn58xx;
-        struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
-};
-
-union cvmx_asxx_tx_comp_byp {
-        uint64_t u64;
-        struct cvmx_asxx_tx_comp_byp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_asxx_tx_comp_byp_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t bypass:1;
-                uint64_t pctl:4;
-                uint64_t nctl:4;
-#else
-                uint64_t nctl:4;
-                uint64_t pctl:4;
-                uint64_t bypass:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn30xx;
-        struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
-        struct cvmx_asxx_tx_comp_byp_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t pctl:4;
-                uint64_t nctl:4;
-#else
-                uint64_t nctl:4;
-                uint64_t pctl:4;
-                uint64_t reserved_8_63:56;
-#endif
-        } cn38xx;
-        struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
-        struct cvmx_asxx_tx_comp_byp_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t bypass:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pctl:5;
-                uint64_t reserved_5_7:3;
-                uint64_t nctl:5;
-#else
-                uint64_t nctl:5;
-                uint64_t reserved_5_7:3;
-                uint64_t pctl:5;
-                uint64_t reserved_13_15:3;
-                uint64_t bypass:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } cn50xx;
-        struct cvmx_asxx_tx_comp_byp_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t pctl:5;
-                uint64_t reserved_5_7:3;
-                uint64_t nctl:5;
-#else
-                uint64_t nctl:5;
-                uint64_t reserved_5_7:3;
-                uint64_t pctl:5;
-                uint64_t reserved_13_63:51;
-#endif
-        } cn58xx;
-        struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
-};
-
-union cvmx_asxx_tx_hi_waterx {
-        uint64_t u64;
-        struct cvmx_asxx_tx_hi_waterx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mark:4;
-#else
-                uint64_t mark:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_asxx_tx_hi_waterx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t mark:3;
-#else
-                uint64_t mark:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn30xx;
-        struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
-        struct cvmx_asxx_tx_hi_waterx_s cn38xx;
-        struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
-        struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
-        struct cvmx_asxx_tx_hi_waterx_s cn58xx;
-        struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
-};
-
-union cvmx_asxx_tx_prt_en {
-        uint64_t u64;
-        struct cvmx_asxx_tx_prt_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t prt_en:4;
-#else
-                uint64_t prt_en:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_asxx_tx_prt_en_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t prt_en:3;
-#else
-                uint64_t prt_en:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn30xx;
-        struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
-        struct cvmx_asxx_tx_prt_en_s cn38xx;
-        struct cvmx_asxx_tx_prt_en_s cn38xxp2;
-        struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
-        struct cvmx_asxx_tx_prt_en_s cn58xx;
-        struct cvmx_asxx_tx_prt_en_s cn58xxp1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 1db1dc2724c..4e4c3a8282d 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -39,7 +39,7 @@
  * versions.
  */
 #define CVMX_BOOTINFO_MAJ_VER 1
-#define CVMX_BOOTINFO_MIN_VER 3
+#define CVMX_BOOTINFO_MIN_VER 2
 
 #if (CVMX_BOOTINFO_MAJ_VER == 1)
 #define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
@@ -116,13 +116,7 @@ struct cvmx_bootinfo {
          */
         uint32_t config_flags;
 #endif
-#if (CVMX_BOOTINFO_MIN_VER >= 3)
-        /*
-         * Address of the OF Flattened Device Tree structure
-         * describing the board.
-         */
-        uint64_t fdt_addr;
-#endif
+
 };
 
 #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST                 (1ull << 0)
@@ -170,22 +164,6 @@ enum cvmx_board_types_enum {
         /* Special 'generic' board type, supports many boards */
         CVMX_BOARD_TYPE_GENERIC = 28,
         CVMX_BOARD_TYPE_EBH5610 = 29,
-        CVMX_BOARD_TYPE_LANAI2_A = 30,
-        CVMX_BOARD_TYPE_LANAI2_U = 31,
-        CVMX_BOARD_TYPE_EBB5600 = 32,
-        CVMX_BOARD_TYPE_EBB6300 = 33,
-        CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
-        CVMX_BOARD_TYPE_LANAI2_G = 35,
-        CVMX_BOARD_TYPE_EBT5810 = 36,
-        CVMX_BOARD_TYPE_NIC10E = 37,
-        CVMX_BOARD_TYPE_EP6300C = 38,
-        CVMX_BOARD_TYPE_EBB6800 = 39,
-        CVMX_BOARD_TYPE_NIC4E = 40,
-        CVMX_BOARD_TYPE_NIC2E = 41,
-        CVMX_BOARD_TYPE_EBB6600 = 42,
-        CVMX_BOARD_TYPE_REDWING = 43,
-        CVMX_BOARD_TYPE_NIC68_4 = 44,
-        CVMX_BOARD_TYPE_NIC10E_66 = 45,
         CVMX_BOARD_TYPE_MAX,
 
         /*
@@ -203,23 +181,6 @@ enum cvmx_board_types_enum {
         CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
         CVMX_BOARD_TYPE_CUST_NB5 = 10003,
         CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
-        CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
-        CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
-        CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
-        CVMX_BOARD_TYPE_CUST_GST104 = 10008,
-        CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
-        CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
-        CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
-        CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
-        CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
-        CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
-        CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
-        CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
-        CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
-        CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
-        CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
-        CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
-        CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
         CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
 
         /*
@@ -280,22 +241,6 @@ static inline const char *cvmx_board_type_to_string(enum
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
 
                         /* Customer boards listed here */
@@ -304,23 +249,6 @@ static inline const char *cvmx_board_type_to_string(enum
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX)
-                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
 
                     /* Customer private range */
@@ -337,9 +265,9 @@ static inline const char *cvmx_chip_type_to_string(enum
 {
         switch (type) {
                 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
-                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
-                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
-                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
+                    ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
+                    ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
+                    ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
         }
         return "Unsupported Chip";
 }
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 42db2be663f..877845b84b1 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -370,6 +370,4 @@ void cvmx_bootmem_lock(void);
  */
 void cvmx_bootmem_unlock(void);
 
-extern struct cvmx_bootmem_desc *cvmx_bootmem_get_desc(void);
-
 #endif /*   __CVMX_BOOTMEM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
index 0dd0e40c96d..27cead37041 100644
--- a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -31,18 +31,6 @@
 #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
 #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
 #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
-#define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8)
-#define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8)
-#define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8)
-#define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8)
 #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
 #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
 #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
@@ -62,378 +50,59 @@
 #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
 #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
 #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
-static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8;
-        }
-        return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8;
-}
-
-static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8;
-        }
-        return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8;
-}
-
+#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
 #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
 #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
-#define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
 #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
-static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8;
-        }
-        return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
-}
-
+#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
 #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
 #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
 #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
 #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
-#define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull))
-#define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull))
 #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
 #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
 #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
 #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
 #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
 #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
-#define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull))
-#define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
 #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
-#define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8)
-#define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8)
-#define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8)
-#define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull))
-static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8;
-        }
-        return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
-}
+#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
+#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
 
 union cvmx_ciu_bist {
         uint64_t u64;
         struct cvmx_ciu_bist_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t bist:7;
-#else
-                uint64_t bist:7;
-                uint64_t reserved_7_63:57;
-#endif
+                uint64_t reserved_5_63:59;
+                uint64_t bist:5;
         } s;
         struct cvmx_ciu_bist_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t bist:4;
-#else
-                uint64_t bist:4;
-                uint64_t reserved_4_63:60;
-#endif
         } cn30xx;
         struct cvmx_ciu_bist_cn30xx cn31xx;
         struct cvmx_ciu_bist_cn30xx cn38xx;
         struct cvmx_ciu_bist_cn30xx cn38xxp2;
         struct cvmx_ciu_bist_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t bist:2;
-#else
-                uint64_t bist:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn50xx;
         struct cvmx_ciu_bist_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t bist:3;
-#else
-                uint64_t bist:3;
-                uint64_t reserved_3_63:61;
-#endif
         } cn52xx;
         struct cvmx_ciu_bist_cn52xx cn52xxp1;
         struct cvmx_ciu_bist_cn30xx cn56xx;
         struct cvmx_ciu_bist_cn30xx cn56xxp1;
         struct cvmx_ciu_bist_cn30xx cn58xx;
         struct cvmx_ciu_bist_cn30xx cn58xxp1;
-        struct cvmx_ciu_bist_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t bist:6;
-#else
-                uint64_t bist:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_bist_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t bist:5;
-#else
-                uint64_t bist:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } cn63xx;
-        struct cvmx_ciu_bist_cn63xx cn63xxp1;
-        struct cvmx_ciu_bist_cn61xx cn66xx;
-        struct cvmx_ciu_bist_s cn68xx;
-        struct cvmx_ciu_bist_s cn68xxp1;
-        struct cvmx_ciu_bist_cn61xx cnf71xx;
+        struct cvmx_ciu_bist_s cn63xx;
+        struct cvmx_ciu_bist_s cn63xxp1;
 };
 
 union cvmx_ciu_block_int {
         uint64_t u64;
         struct cvmx_ciu_block_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_43_59:17;
-                uint64_t ptp:1;
-                uint64_t dpi:1;
-                uint64_t dfm:1;
-                uint64_t reserved_34_39:6;
-                uint64_t srio1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_31_31:1;
-                uint64_t iob:1;
-                uint64_t reserved_29_29:1;
-                uint64_t agl:1;
-                uint64_t reserved_27_27:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t reserved_24_24:1;
-                uint64_t asxpcs1:1;
-                uint64_t asxpcs0:1;
-                uint64_t reserved_21_21:1;
-                uint64_t pip:1;
-                uint64_t reserved_18_19:2;
-                uint64_t lmc0:1;
-                uint64_t l2c:1;
-                uint64_t reserved_15_15:1;
-                uint64_t rad:1;
-                uint64_t usb:1;
-                uint64_t pow:1;
-                uint64_t tim:1;
-                uint64_t pko:1;
-                uint64_t ipd:1;
-                uint64_t reserved_8_8:1;
-                uint64_t zip:1;
-                uint64_t dfa:1;
-                uint64_t fpa:1;
-                uint64_t key:1;
-                uint64_t sli:1;
-                uint64_t gmx1:1;
-                uint64_t gmx0:1;
-                uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t gmx1:1;
-                uint64_t sli:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t dfa:1;
-                uint64_t zip:1;
-                uint64_t reserved_8_8:1;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t usb:1;
-                uint64_t rad:1;
-                uint64_t reserved_15_15:1;
-                uint64_t l2c:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_18_19:2;
-                uint64_t pip:1;
-                uint64_t reserved_21_21:1;
-                uint64_t asxpcs0:1;
-                uint64_t asxpcs1:1;
-                uint64_t reserved_24_24:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_27_27:1;
-                uint64_t agl:1;
-                uint64_t reserved_29_29:1;
-                uint64_t iob:1;
-                uint64_t reserved_31_31:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfm:1;
-                uint64_t dpi:1;
-                uint64_t ptp:1;
-                uint64_t reserved_43_59:17;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_ciu_block_int_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_43_63:21;
-                uint64_t ptp:1;
-                uint64_t dpi:1;
-                uint64_t reserved_31_40:10;
-                uint64_t iob:1;
-                uint64_t reserved_29_29:1;
-                uint64_t agl:1;
-                uint64_t reserved_27_27:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t reserved_24_24:1;
-                uint64_t asxpcs1:1;
-                uint64_t asxpcs0:1;
-                uint64_t reserved_21_21:1;
-                uint64_t pip:1;
-                uint64_t reserved_18_19:2;
-                uint64_t lmc0:1;
-                uint64_t l2c:1;
-                uint64_t reserved_15_15:1;
-                uint64_t rad:1;
-                uint64_t usb:1;
-                uint64_t pow:1;
-                uint64_t tim:1;
-                uint64_t pko:1;
-                uint64_t ipd:1;
-                uint64_t reserved_8_8:1;
-                uint64_t zip:1;
-                uint64_t dfa:1;
-                uint64_t fpa:1;
-                uint64_t key:1;
-                uint64_t sli:1;
-                uint64_t gmx1:1;
-                uint64_t gmx0:1;
-                uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t gmx1:1;
-                uint64_t sli:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t dfa:1;
-                uint64_t zip:1;
-                uint64_t reserved_8_8:1;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t usb:1;
-                uint64_t rad:1;
-                uint64_t reserved_15_15:1;
-                uint64_t l2c:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_18_19:2;
-                uint64_t pip:1;
-                uint64_t reserved_21_21:1;
-                uint64_t asxpcs0:1;
-                uint64_t asxpcs1:1;
-                uint64_t reserved_24_24:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_27_27:1;
-                uint64_t agl:1;
-                uint64_t reserved_29_29:1;
-                uint64_t iob:1;
-                uint64_t reserved_31_40:10;
-                uint64_t dpi:1;
-                uint64_t ptp:1;
-                uint64_t reserved_43_63:21;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_block_int_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_43_63:21;
                 uint64_t ptp:1;
                 uint64_t dpi:1;
@@ -471,789 +140,88 @@ union cvmx_ciu_block_int {
                 uint64_t reserved_2_2:1;
                 uint64_t gmx0:1;
                 uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t reserved_2_2:1;
-                uint64_t sli:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t dfa:1;
-                uint64_t zip:1;
-                uint64_t reserved_8_8:1;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t usb:1;
-                uint64_t rad:1;
-                uint64_t reserved_15_15:1;
-                uint64_t l2c:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_18_19:2;
-                uint64_t pip:1;
-                uint64_t reserved_21_21:1;
-                uint64_t asxpcs0:1;
-                uint64_t reserved_23_24:2;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_27_27:1;
-                uint64_t agl:1;
-                uint64_t reserved_29_29:1;
-                uint64_t iob:1;
-                uint64_t reserved_31_31:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfm:1;
-                uint64_t dpi:1;
-                uint64_t ptp:1;
-                uint64_t reserved_43_63:21;
-#endif
-        } cn63xx;
-        struct cvmx_ciu_block_int_cn63xx cn63xxp1;
-        struct cvmx_ciu_block_int_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_43_59:17;
-                uint64_t ptp:1;
-                uint64_t dpi:1;
-                uint64_t dfm:1;
-                uint64_t reserved_33_39:7;
-                uint64_t srio0:1;
-                uint64_t reserved_31_31:1;
-                uint64_t iob:1;
-                uint64_t reserved_29_29:1;
-                uint64_t agl:1;
-                uint64_t reserved_27_27:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t reserved_24_24:1;
-                uint64_t asxpcs1:1;
-                uint64_t asxpcs0:1;
-                uint64_t reserved_21_21:1;
-                uint64_t pip:1;
-                uint64_t reserved_18_19:2;
-                uint64_t lmc0:1;
-                uint64_t l2c:1;
-                uint64_t reserved_15_15:1;
-                uint64_t rad:1;
-                uint64_t usb:1;
-                uint64_t pow:1;
-                uint64_t tim:1;
-                uint64_t pko:1;
-                uint64_t ipd:1;
-                uint64_t reserved_8_8:1;
-                uint64_t zip:1;
-                uint64_t dfa:1;
-                uint64_t fpa:1;
-                uint64_t key:1;
-                uint64_t sli:1;
-                uint64_t gmx1:1;
-                uint64_t gmx0:1;
-                uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t gmx1:1;
-                uint64_t sli:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t dfa:1;
-                uint64_t zip:1;
-                uint64_t reserved_8_8:1;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t usb:1;
-                uint64_t rad:1;
-                uint64_t reserved_15_15:1;
-                uint64_t l2c:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_18_19:2;
-                uint64_t pip:1;
-                uint64_t reserved_21_21:1;
-                uint64_t asxpcs0:1;
-                uint64_t asxpcs1:1;
-                uint64_t reserved_24_24:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_27_27:1;
-                uint64_t agl:1;
-                uint64_t reserved_29_29:1;
-                uint64_t iob:1;
-                uint64_t reserved_31_31:1;
-                uint64_t srio0:1;
-                uint64_t reserved_33_39:7;
-                uint64_t dfm:1;
-                uint64_t dpi:1;
-                uint64_t ptp:1;
-                uint64_t reserved_43_59:17;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_block_int_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_43_63:21;
-                uint64_t ptp:1;
-                uint64_t dpi:1;
-                uint64_t reserved_31_40:10;
-                uint64_t iob:1;
-                uint64_t reserved_27_29:3;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t reserved_23_24:2;
-                uint64_t asxpcs0:1;
-                uint64_t reserved_21_21:1;
-                uint64_t pip:1;
-                uint64_t reserved_18_19:2;
-                uint64_t lmc0:1;
-                uint64_t l2c:1;
-                uint64_t reserved_15_15:1;
-                uint64_t rad:1;
-                uint64_t usb:1;
-                uint64_t pow:1;
-                uint64_t tim:1;
-                uint64_t pko:1;
-                uint64_t ipd:1;
-                uint64_t reserved_6_8:3;
-                uint64_t fpa:1;
-                uint64_t key:1;
-                uint64_t sli:1;
-                uint64_t reserved_2_2:1;
-                uint64_t gmx0:1;
-                uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t reserved_2_2:1;
-                uint64_t sli:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t reserved_6_8:3;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t usb:1;
-                uint64_t rad:1;
-                uint64_t reserved_15_15:1;
-                uint64_t l2c:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_18_19:2;
-                uint64_t pip:1;
-                uint64_t reserved_21_21:1;
-                uint64_t asxpcs0:1;
-                uint64_t reserved_23_24:2;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_27_29:3;
-                uint64_t iob:1;
-                uint64_t reserved_31_40:10;
-                uint64_t dpi:1;
-                uint64_t ptp:1;
-                uint64_t reserved_43_63:21;
-#endif
-        } cnf71xx;
+        } s;
+        struct cvmx_ciu_block_int_s cn63xx;
+        struct cvmx_ciu_block_int_s cn63xxp1;
 };
 
 union cvmx_ciu_dint {
         uint64_t u64;
         struct cvmx_ciu_dint_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t dint:32;
-#else
-                uint64_t dint:32;
-                uint64_t reserved_32_63:32;
-#endif
+                uint64_t reserved_16_63:48;
+                uint64_t dint:16;
         } s;
         struct cvmx_ciu_dint_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t dint:1;
-#else
-                uint64_t dint:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn30xx;
         struct cvmx_ciu_dint_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t dint:2;
-#else
-                uint64_t dint:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn31xx;
-        struct cvmx_ciu_dint_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t dint:16;
-#else
-                uint64_t dint:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn38xx;
-        struct cvmx_ciu_dint_cn38xx cn38xxp2;
+        struct cvmx_ciu_dint_s cn38xx;
+        struct cvmx_ciu_dint_s cn38xxp2;
         struct cvmx_ciu_dint_cn31xx cn50xx;
         struct cvmx_ciu_dint_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t dint:4;
-#else
-                uint64_t dint:4;
-                uint64_t reserved_4_63:60;
-#endif
         } cn52xx;
         struct cvmx_ciu_dint_cn52xx cn52xxp1;
         struct cvmx_ciu_dint_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t dint:12;
-#else
-                uint64_t dint:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_dint_cn56xx cn56xxp1;
-        struct cvmx_ciu_dint_cn38xx cn58xx;
-        struct cvmx_ciu_dint_cn38xx cn58xxp1;
-        struct cvmx_ciu_dint_cn52xx cn61xx;
+        struct cvmx_ciu_dint_s cn58xx;
+        struct cvmx_ciu_dint_s cn58xxp1;
         struct cvmx_ciu_dint_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t dint:6;
-#else
-                uint64_t dint:6;
-                uint64_t reserved_6_63:58;
-#endif
         } cn63xx;
         struct cvmx_ciu_dint_cn63xx cn63xxp1;
-        struct cvmx_ciu_dint_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t dint:10;
-#else
-                uint64_t dint:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_dint_s cn68xx;
-        struct cvmx_ciu_dint_s cn68xxp1;
-        struct cvmx_ciu_dint_cn52xx cnf71xx;
-};
-
-union cvmx_ciu_en2_iox_int {
-        uint64_t u64;
-        struct cvmx_ciu_en2_iox_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_iox_int_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_iox_int_cn61xx cn66xx;
-        struct cvmx_ciu_en2_iox_int_s cnf71xx;
-};
-
-union cvmx_ciu_en2_iox_int_w1c {
-        uint64_t u64;
-        struct cvmx_ciu_en2_iox_int_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_iox_int_w1c_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx;
-        struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx;
-};
-
-union cvmx_ciu_en2_iox_int_w1s {
-        uint64_t u64;
-        struct cvmx_ciu_en2_iox_int_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_iox_int_w1s_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx;
-        struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx;
-};
-
-union cvmx_ciu_en2_ppx_ip2 {
-        uint64_t u64;
-        struct cvmx_ciu_en2_ppx_ip2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_ppx_ip2_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx;
-        struct cvmx_ciu_en2_ppx_ip2_s cnf71xx;
-};
-
-union cvmx_ciu_en2_ppx_ip2_w1c {
-        uint64_t u64;
-        struct cvmx_ciu_en2_ppx_ip2_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx;
-        struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx;
-};
-
-union cvmx_ciu_en2_ppx_ip2_w1s {
-        uint64_t u64;
-        struct cvmx_ciu_en2_ppx_ip2_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx;
-        struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx;
-};
-
-union cvmx_ciu_en2_ppx_ip3 {
-        uint64_t u64;
-        struct cvmx_ciu_en2_ppx_ip3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_ppx_ip3_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx;
-        struct cvmx_ciu_en2_ppx_ip3_s cnf71xx;
-};
-
-union cvmx_ciu_en2_ppx_ip3_w1c {
-        uint64_t u64;
-        struct cvmx_ciu_en2_ppx_ip3_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx;
-        struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx;
-};
-
-union cvmx_ciu_en2_ppx_ip3_w1s {
-        uint64_t u64;
-        struct cvmx_ciu_en2_ppx_ip3_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx;
-        struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx;
-};
-
-union cvmx_ciu_en2_ppx_ip4 {
-        uint64_t u64;
-        struct cvmx_ciu_en2_ppx_ip4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_ppx_ip4_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx;
-        struct cvmx_ciu_en2_ppx_ip4_s cnf71xx;
-};
-
-union cvmx_ciu_en2_ppx_ip4_w1c {
-        uint64_t u64;
-        struct cvmx_ciu_en2_ppx_ip4_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx;
-        struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx;
-};
-
-union cvmx_ciu_en2_ppx_ip4_w1s {
-        uint64_t u64;
-        struct cvmx_ciu_en2_ppx_ip4_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx;
-        struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx;
 };
 
 union cvmx_ciu_fuse {
         uint64_t u64;
         struct cvmx_ciu_fuse_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t fuse:32;
-#else
-                uint64_t fuse:32;
-                uint64_t reserved_32_63:32;
-#endif
+                uint64_t reserved_16_63:48;
+                uint64_t fuse:16;
         } s;
         struct cvmx_ciu_fuse_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t fuse:1;
-#else
-                uint64_t fuse:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn30xx;
         struct cvmx_ciu_fuse_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t fuse:2;
-#else
-                uint64_t fuse:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn31xx;
-        struct cvmx_ciu_fuse_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t fuse:16;
-#else
-                uint64_t fuse:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn38xx;
-        struct cvmx_ciu_fuse_cn38xx cn38xxp2;
+        struct cvmx_ciu_fuse_s cn38xx;
+        struct cvmx_ciu_fuse_s cn38xxp2;
         struct cvmx_ciu_fuse_cn31xx cn50xx;
         struct cvmx_ciu_fuse_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t fuse:4;
-#else
-                uint64_t fuse:4;
-                uint64_t reserved_4_63:60;
-#endif
         } cn52xx;
         struct cvmx_ciu_fuse_cn52xx cn52xxp1;
         struct cvmx_ciu_fuse_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t fuse:12;
-#else
-                uint64_t fuse:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_fuse_cn56xx cn56xxp1;
-        struct cvmx_ciu_fuse_cn38xx cn58xx;
-        struct cvmx_ciu_fuse_cn38xx cn58xxp1;
-        struct cvmx_ciu_fuse_cn52xx cn61xx;
+        struct cvmx_ciu_fuse_s cn58xx;
+        struct cvmx_ciu_fuse_s cn58xxp1;
         struct cvmx_ciu_fuse_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t fuse:6;
-#else
-                uint64_t fuse:6;
-                uint64_t reserved_6_63:58;
-#endif
         } cn63xx;
         struct cvmx_ciu_fuse_cn63xx cn63xxp1;
-        struct cvmx_ciu_fuse_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t fuse:10;
-#else
-                uint64_t fuse:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_fuse_s cn68xx;
-        struct cvmx_ciu_fuse_s cn68xxp1;
-        struct cvmx_ciu_fuse_cn52xx cnf71xx;
 };
 
 union cvmx_ciu_gstop {
         uint64_t u64;
         struct cvmx_ciu_gstop_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t gstop:1;
-#else
-                uint64_t gstop:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_ciu_gstop_s cn30xx;
         struct cvmx_ciu_gstop_s cn31xx;
@@ -1266,19 +234,13 @@ union cvmx_ciu_gstop {
         struct cvmx_ciu_gstop_s cn56xxp1;
         struct cvmx_ciu_gstop_s cn58xx;
         struct cvmx_ciu_gstop_s cn58xxp1;
-        struct cvmx_ciu_gstop_s cn61xx;
         struct cvmx_ciu_gstop_s cn63xx;
         struct cvmx_ciu_gstop_s cn63xxp1;
-        struct cvmx_ciu_gstop_s cn66xx;
-        struct cvmx_ciu_gstop_s cn68xx;
-        struct cvmx_ciu_gstop_s cn68xxp1;
-        struct cvmx_ciu_gstop_s cnf71xx;
 };
 
 union cvmx_ciu_intx_en0 {
         uint64_t u64;
         struct cvmx_ciu_intx_en0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -1301,33 +263,8 @@ union cvmx_ciu_intx_en0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en0_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_59_63:5;
                 uint64_t mpi:1;
                 uint64_t pcm:1;
@@ -1347,30 +284,8 @@ union cvmx_ciu_intx_en0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t reserved_47_47:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t reserved_59_63:5;
-#endif
         } cn30xx;
         struct cvmx_ciu_intx_en0_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_59_63:5;
                 uint64_t mpi:1;
                 uint64_t pcm:1;
@@ -1390,30 +305,8 @@ union cvmx_ciu_intx_en0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t reserved_59_63:5;
-#endif
         } cn31xx;
         struct cvmx_ciu_intx_en0_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -1429,28 +322,10 @@ union cvmx_ciu_intx_en0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t reserved_56_63:8;
-#endif
         } cn38xx;
         struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
         struct cvmx_ciu_intx_en0_cn30xx cn50xx;
         struct cvmx_ciu_intx_en0_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -1473,34 +348,9 @@ union cvmx_ciu_intx_en0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
         struct cvmx_ciu_intx_en0_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -1522,197 +372,23 @@ union cvmx_ciu_intx_en0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_en0_cn38xx cn58xx;
         struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
-        struct cvmx_ciu_intx_en0_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en0_cn52xx cn63xx;
         struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
-        struct cvmx_ciu_intx_en0_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t reserved_57_57:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_57:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en0_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t reserved_62_62:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t gmx_drp:1;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t reserved_62_62:1;
-                uint64_t bootdma:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en0_w1c {
         uint64_t u64;
         struct cvmx_ciu_intx_en0_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
                 uint64_t powiq:1;
                 uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
+                uint64_t reserved_57_58:2;
                 uint64_t usb:1;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -1728,33 +404,8 @@ union cvmx_ciu_intx_en0_w1c {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en0_w1c_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -1777,80 +428,9 @@ union cvmx_ciu_intx_en0_w1c {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn52xx;
-        struct cvmx_ciu_intx_en0_w1c_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t reserved_57_58:2;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t key_zero:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn56xx;
+        struct cvmx_ciu_intx_en0_w1c_s cn56xx;
         struct cvmx_ciu_intx_en0_w1c_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -1866,188 +446,20 @@ union cvmx_ciu_intx_en0_w1c {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t reserved_56_63:8;
-#endif
         } cn58xx;
-        struct cvmx_ciu_intx_en0_w1c_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
         struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
-        struct cvmx_ciu_intx_en0_w1c_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t reserved_57_57:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_57:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en0_w1c_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t reserved_62_62:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t gmx_drp:1;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t reserved_62_62:1;
-                uint64_t bootdma:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en0_w1s {
         uint64_t u64;
         struct cvmx_ciu_intx_en0_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
                 uint64_t powiq:1;
                 uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
+                uint64_t reserved_57_58:2;
                 uint64_t usb:1;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -2063,33 +475,8 @@ union cvmx_ciu_intx_en0_w1s {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en0_w1s_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -2112,80 +499,9 @@ union cvmx_ciu_intx_en0_w1s {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn52xx;
-        struct cvmx_ciu_intx_en0_w1s_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t reserved_57_58:2;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t key_zero:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn56xx;
+        struct cvmx_ciu_intx_en0_w1s_s cn56xx;
         struct cvmx_ciu_intx_en0_w1s_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -2201,186 +517,16 @@ union cvmx_ciu_intx_en0_w1s {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t reserved_56_63:8;
-#endif
         } cn58xx;
-        struct cvmx_ciu_intx_en0_w1s_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
         struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
-        struct cvmx_ciu_intx_en0_w1s_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t reserved_57_57:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_57:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en0_w1s_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t reserved_62_62:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t gmx_drp:1;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t reserved_62_62:1;
-                uint64_t bootdma:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en1 {
         uint64_t u64;
         struct cvmx_ciu_intx_en1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
+                uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
                 uint64_t reserved_53_55:3;
                 uint64_t lmc0:1;
@@ -2390,10 +536,7 @@ union cvmx_ciu_intx_en1 {
                 uint64_t pem0:1;
                 uint64_t ptp:1;
                 uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
+                uint64_t reserved_37_45:9;
                 uint64_t agx0:1;
                 uint64_t dpi:1;
                 uint64_t sli:1;
@@ -2416,80 +559,22 @@ union cvmx_ciu_intx_en1 {
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en1_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t wdog:1;
-#else
-                uint64_t wdog:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn30xx;
         struct cvmx_ciu_intx_en1_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t wdog:2;
-#else
-                uint64_t wdog:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn31xx;
         struct cvmx_ciu_intx_en1_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn38xx;
         struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
         struct cvmx_ciu_intx_en1_cn31xx cn50xx;
         struct cvmx_ciu_intx_en1_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t nand:1;
                 uint64_t mii1:1;
@@ -2497,118 +582,23 @@ union cvmx_ciu_intx_en1 {
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_en1_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t reserved_19_63:45;
-#endif
         } cn52xxp1;
         struct cvmx_ciu_intx_en1_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t wdog:12;
-#else
-                uint64_t wdog:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_en1_cn38xx cn58xx;
         struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
-        struct cvmx_ciu_intx_en1_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en1_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
                 uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
@@ -2642,198 +632,15 @@ union cvmx_ciu_intx_en1 {
                 uint64_t mii1:1;
                 uint64_t reserved_6_17:12;
                 uint64_t wdog:6;
-#else
-                uint64_t wdog:6;
-                uint64_t reserved_6_17:12;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_45:9;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_62:6;
-                uint64_t rst:1;
-#endif
         } cn63xx;
         struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
-        struct cvmx_ciu_intx_en1_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en1_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en1_w1c {
         uint64_t u64;
         struct cvmx_ciu_intx_en1_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
+                uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
                 uint64_t reserved_53_55:3;
                 uint64_t lmc0:1;
@@ -2843,10 +650,7 @@ union cvmx_ciu_intx_en1_w1c {
                 uint64_t pem0:1;
                 uint64_t ptp:1;
                 uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
+                uint64_t reserved_37_45:9;
                 uint64_t agx0:1;
                 uint64_t dpi:1;
                 uint64_t sli:1;
@@ -2869,51 +673,8 @@ union cvmx_ciu_intx_en1_w1c {
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en1_w1c_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t nand:1;
                 uint64_t mii1:1;
@@ -2921,107 +682,16 @@ union cvmx_ciu_intx_en1_w1c {
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_en1_w1c_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t wdog:12;
-#else
-                uint64_t wdog:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_en1_w1c_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn58xx;
-        struct cvmx_ciu_intx_en1_w1c_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en1_w1c_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
                 uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
@@ -3055,198 +725,15 @@ union cvmx_ciu_intx_en1_w1c {
                 uint64_t mii1:1;
                 uint64_t reserved_6_17:12;
                 uint64_t wdog:6;
-#else
-                uint64_t wdog:6;
-                uint64_t reserved_6_17:12;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_45:9;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_62:6;
-                uint64_t rst:1;
-#endif
         } cn63xx;
         struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
-        struct cvmx_ciu_intx_en1_w1c_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en1_w1c_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en1_w1s {
         uint64_t u64;
         struct cvmx_ciu_intx_en1_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
+                uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
                 uint64_t reserved_53_55:3;
                 uint64_t lmc0:1;
@@ -3256,10 +743,7 @@ union cvmx_ciu_intx_en1_w1s {
                 uint64_t pem0:1;
                 uint64_t ptp:1;
                 uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
+                uint64_t reserved_37_45:9;
                 uint64_t agx0:1;
                 uint64_t dpi:1;
                 uint64_t sli:1;
@@ -3282,51 +766,8 @@ union cvmx_ciu_intx_en1_w1s {
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en1_w1s_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t nand:1;
                 uint64_t mii1:1;
@@ -3334,107 +775,16 @@ union cvmx_ciu_intx_en1_w1s {
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_en1_w1s_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t wdog:12;
-#else
-                uint64_t wdog:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_en1_w1s_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn58xx;
-        struct cvmx_ciu_intx_en1_w1s_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en1_w1s_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
                 uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
@@ -3468,193 +818,13 @@ union cvmx_ciu_intx_en1_w1s {
                 uint64_t mii1:1;
                 uint64_t reserved_6_17:12;
                 uint64_t wdog:6;
-#else
-                uint64_t wdog:6;
-                uint64_t reserved_6_17:12;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_45:9;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_62:6;
-                uint64_t rst:1;
-#endif
         } cn63xx;
         struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
-        struct cvmx_ciu_intx_en1_w1s_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en1_w1s_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en4_0 {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -3677,33 +847,8 @@ union cvmx_ciu_intx_en4_0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en4_0_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_59_63:5;
                 uint64_t mpi:1;
                 uint64_t pcm:1;
@@ -3723,30 +868,8 @@ union cvmx_ciu_intx_en4_0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t reserved_47_47:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t reserved_59_63:5;
-#endif
         } cn50xx;
         struct cvmx_ciu_intx_en4_0_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -3769,34 +892,9 @@ union cvmx_ciu_intx_en4_0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
         struct cvmx_ciu_intx_en4_0_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -3818,33 +916,9 @@ union cvmx_ciu_intx_en4_0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_en4_0_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -3860,189 +934,21 @@ union cvmx_ciu_intx_en4_0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t reserved_56_63:8;
-#endif
         } cn58xx;
         struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
-        struct cvmx_ciu_intx_en4_0_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
         struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
-        struct cvmx_ciu_intx_en4_0_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t reserved_57_57:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_57:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en4_0_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t reserved_62_62:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t gmx_drp:1;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t reserved_62_62:1;
-                uint64_t bootdma:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en4_0_w1c {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_0_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
                 uint64_t powiq:1;
                 uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
+                uint64_t reserved_57_58:2;
                 uint64_t usb:1;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -4058,33 +964,8 @@ union cvmx_ciu_intx_en4_0_w1c {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -4107,80 +988,9 @@ union cvmx_ciu_intx_en4_0_w1c {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn52xx;
-        struct cvmx_ciu_intx_en4_0_w1c_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t reserved_57_58:2;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t key_zero:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn56xx;
+        struct cvmx_ciu_intx_en4_0_w1c_s cn56xx;
         struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -4196,188 +1006,20 @@ union cvmx_ciu_intx_en4_0_w1c {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t reserved_56_63:8;
-#endif
         } cn58xx;
-        struct cvmx_ciu_intx_en4_0_w1c_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
         struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
-        struct cvmx_ciu_intx_en4_0_w1c_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t reserved_57_57:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_57:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en4_0_w1c_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t reserved_62_62:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t gmx_drp:1;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t reserved_62_62:1;
-                uint64_t bootdma:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en4_0_w1s {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_0_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
                 uint64_t powiq:1;
                 uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
+                uint64_t reserved_57_58:2;
                 uint64_t usb:1;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -4393,33 +1035,8 @@ union cvmx_ciu_intx_en4_0_w1s {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -4442,80 +1059,9 @@ union cvmx_ciu_intx_en4_0_w1s {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn52xx;
-        struct cvmx_ciu_intx_en4_0_w1s_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t reserved_57_58:2;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t key_zero:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn56xx;
+        struct cvmx_ciu_intx_en4_0_w1s_s cn56xx;
         struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -4531,186 +1077,16 @@ union cvmx_ciu_intx_en4_0_w1s {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t reserved_56_63:8;
-#endif
         } cn58xx;
-        struct cvmx_ciu_intx_en4_0_w1s_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
         struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
-        struct cvmx_ciu_intx_en4_0_w1s_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t reserved_57_57:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_57:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en4_0_w1s_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t reserved_62_62:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t reserved_51_51:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t gmx_drp:1;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t reserved_44_44:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t reserved_44_44:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t reserved_62_62:1;
-                uint64_t bootdma:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en4_1 {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
+                uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
                 uint64_t reserved_53_55:3;
                 uint64_t lmc0:1;
@@ -4720,10 +1096,7 @@ union cvmx_ciu_intx_en4_1 {
                 uint64_t pem0:1;
                 uint64_t ptp:1;
                 uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
+                uint64_t reserved_37_45:9;
                 uint64_t agx0:1;
                 uint64_t dpi:1;
                 uint64_t sli:1;
@@ -4746,60 +1119,12 @@ union cvmx_ciu_intx_en4_1 {
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en4_1_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t wdog:2;
-#else
-                uint64_t wdog:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn50xx;
         struct cvmx_ciu_intx_en4_1_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t nand:1;
                 uint64_t mii1:1;
@@ -4807,126 +1132,26 @@ union cvmx_ciu_intx_en4_1 {
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_en4_1_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t reserved_19_63:45;
-#endif
         } cn52xxp1;
         struct cvmx_ciu_intx_en4_1_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t wdog:12;
-#else
-                uint64_t wdog:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_en4_1_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn58xx;
         struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
-        struct cvmx_ciu_intx_en4_1_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en4_1_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
                 uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
@@ -4960,198 +1185,15 @@ union cvmx_ciu_intx_en4_1 {
                 uint64_t mii1:1;
                 uint64_t reserved_6_17:12;
                 uint64_t wdog:6;
-#else
-                uint64_t wdog:6;
-                uint64_t reserved_6_17:12;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_45:9;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_62:6;
-                uint64_t rst:1;
-#endif
         } cn63xx;
         struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
-        struct cvmx_ciu_intx_en4_1_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en4_1_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en4_1_w1c {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_1_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
+                uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
                 uint64_t reserved_53_55:3;
                 uint64_t lmc0:1;
@@ -5161,10 +1203,7 @@ union cvmx_ciu_intx_en4_1_w1c {
                 uint64_t pem0:1;
                 uint64_t ptp:1;
                 uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
+                uint64_t reserved_37_45:9;
                 uint64_t agx0:1;
                 uint64_t dpi:1;
                 uint64_t sli:1;
@@ -5187,51 +1226,8 @@ union cvmx_ciu_intx_en4_1_w1c {
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t nand:1;
                 uint64_t mii1:1;
@@ -5239,107 +1235,16 @@ union cvmx_ciu_intx_en4_1_w1c {
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t wdog:12;
-#else
-                uint64_t wdog:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn58xx;
-        struct cvmx_ciu_intx_en4_1_w1c_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
                 uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
@@ -5373,198 +1278,15 @@ union cvmx_ciu_intx_en4_1_w1c {
                 uint64_t mii1:1;
                 uint64_t reserved_6_17:12;
                 uint64_t wdog:6;
-#else
-                uint64_t wdog:6;
-                uint64_t reserved_6_17:12;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_45:9;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_62:6;
-                uint64_t rst:1;
-#endif
         } cn63xx;
         struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
-        struct cvmx_ciu_intx_en4_1_w1c_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en4_1_w1c_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_en4_1_w1s {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_1_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
+                uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
                 uint64_t reserved_53_55:3;
                 uint64_t lmc0:1;
@@ -5574,10 +1296,7 @@ union cvmx_ciu_intx_en4_1_w1s {
                 uint64_t pem0:1;
                 uint64_t ptp:1;
                 uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
+                uint64_t reserved_37_45:9;
                 uint64_t agx0:1;
                 uint64_t dpi:1;
                 uint64_t sli:1;
@@ -5600,51 +1319,8 @@ union cvmx_ciu_intx_en4_1_w1s {
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
         } s;
         struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t nand:1;
                 uint64_t mii1:1;
@@ -5652,107 +1328,16 @@ union cvmx_ciu_intx_en4_1_w1s {
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t wdog:12;
-#else
-                uint64_t wdog:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn58xx;
-        struct cvmx_ciu_intx_en4_1_w1s_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
                 uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
@@ -5786,193 +1371,13 @@ union cvmx_ciu_intx_en4_1_w1s {
                 uint64_t mii1:1;
                 uint64_t reserved_6_17:12;
                 uint64_t wdog:6;
-#else
-                uint64_t wdog:6;
-                uint64_t reserved_6_17:12;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_45:9;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_62:6;
-                uint64_t rst:1;
-#endif
         } cn63xx;
         struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
-        struct cvmx_ciu_intx_en4_1_w1s_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_en4_1_w1s_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_sum0 {
         uint64_t u64;
         struct cvmx_ciu_intx_sum0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -5982,7 +1387,7 @@ union cvmx_ciu_intx_sum0 {
                 uint64_t pcm:1;
                 uint64_t usb:1;
                 uint64_t timer:4;
-                uint64_t reserved_51_51:1;
+                uint64_t key_zero:1;
                 uint64_t ipd_drp:1;
                 uint64_t gmx_drp:2;
                 uint64_t trace:1;
@@ -5995,33 +1400,8 @@ union cvmx_ciu_intx_sum0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } s;
         struct cvmx_ciu_intx_sum0_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_59_63:5;
                 uint64_t mpi:1;
                 uint64_t pcm:1;
@@ -6041,30 +1421,8 @@ union cvmx_ciu_intx_sum0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t reserved_47_47:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t reserved_59_63:5;
-#endif
         } cn30xx;
         struct cvmx_ciu_intx_sum0_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_59_63:5;
                 uint64_t mpi:1;
                 uint64_t pcm:1;
@@ -6084,30 +1442,8 @@ union cvmx_ciu_intx_sum0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t reserved_59_63:5;
-#endif
         } cn31xx;
         struct cvmx_ciu_intx_sum0_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -6123,28 +1459,10 @@ union cvmx_ciu_intx_sum0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t reserved_56_63:8;
-#endif
         } cn38xx;
         struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
         struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
         struct cvmx_ciu_intx_sum0_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -6167,34 +1485,9 @@ union cvmx_ciu_intx_sum0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
         struct cvmx_ciu_intx_sum0_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -6216,190 +1509,17 @@ union cvmx_ciu_intx_sum0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
         struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
-        struct cvmx_ciu_intx_sum0_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t sum2:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t wdog_sum:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t sum2:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
         struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
-        struct cvmx_ciu_intx_sum0_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t reserved_57_57:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t sum2:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t wdog_sum:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t sum2:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_57:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_sum0_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t reserved_62_62:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t sum2:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t gmx_drp:1;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t wdog_sum:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t sum2:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t reserved_62_62:1;
-                uint64_t bootdma:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_intx_sum4 {
         uint64_t u64;
         struct cvmx_ciu_intx_sum4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -6409,7 +1529,7 @@ union cvmx_ciu_intx_sum4 {
                 uint64_t pcm:1;
                 uint64_t usb:1;
                 uint64_t timer:4;
-                uint64_t reserved_51_51:1;
+                uint64_t key_zero:1;
                 uint64_t ipd_drp:1;
                 uint64_t gmx_drp:2;
                 uint64_t trace:1;
@@ -6422,33 +1542,8 @@ union cvmx_ciu_intx_sum4 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } s;
         struct cvmx_ciu_intx_sum4_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_59_63:5;
                 uint64_t mpi:1;
                 uint64_t pcm:1;
@@ -6468,30 +1563,8 @@ union cvmx_ciu_intx_sum4 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t reserved_47_47:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t reserved_59_63:5;
-#endif
         } cn50xx;
         struct cvmx_ciu_intx_sum4_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -6514,34 +1587,9 @@ union cvmx_ciu_intx_sum4 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn52xx;
         struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
         struct cvmx_ciu_intx_sum4_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -6563,33 +1611,9 @@ union cvmx_ciu_intx_sum4 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
         } cn56xx;
         struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_sum4_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t timer:4;
                 uint64_t key_zero:1;
@@ -6605,232 +1629,15 @@ union cvmx_ciu_intx_sum4 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t key_zero:1;
-                uint64_t timer:4;
-                uint64_t reserved_56_63:8;
-#endif
         } cn58xx;
         struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
-        struct cvmx_ciu_intx_sum4_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t sum2:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t wdog_sum:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t sum2:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
         struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
-        struct cvmx_ciu_intx_sum4_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t reserved_57_57:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t sum2:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t wdog_sum:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t sum2:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_57:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_intx_sum4_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t reserved_62_62:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t sum2:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t gmx_drp:1;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t wdog_sum:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t sum2:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t reserved_62_62:1;
-                uint64_t bootdma:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_int33_sum0 {
         uint64_t u64;
         struct cvmx_ciu_int33_sum0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t sum2:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t wdog_sum:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t sum2:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } s;
-        struct cvmx_ciu_int33_sum0_s cn61xx;
-        struct cvmx_ciu_int33_sum0_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bootdma:1;
                 uint64_t mii:1;
                 uint64_t ipdppthr:1;
@@ -6853,202 +1660,29 @@ union cvmx_ciu_int33_sum0 {
                 uint64_t mbox:2;
                 uint64_t gpio:16;
                 uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_51_51:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_58:2;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn63xx;
-        struct cvmx_ciu_int33_sum0_cn63xx cn63xxp1;
-        struct cvmx_ciu_int33_sum0_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t mii:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t reserved_57_57:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t sum2:1;
-                uint64_t ipd_drp:1;
-                uint64_t gmx_drp:2;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t wdog_sum:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:2;
-                uint64_t ipd_drp:1;
-                uint64_t sum2:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t reserved_57_57:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t mii:1;
-                uint64_t bootdma:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_int33_sum0_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bootdma:1;
-                uint64_t reserved_62_62:1;
-                uint64_t ipdppthr:1;
-                uint64_t powiq:1;
-                uint64_t twsi2:1;
-                uint64_t mpi:1;
-                uint64_t pcm:1;
-                uint64_t usb:1;
-                uint64_t timer:4;
-                uint64_t sum2:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t gmx_drp:1;
-                uint64_t trace:1;
-                uint64_t rml:1;
-                uint64_t twsi:1;
-                uint64_t wdog_sum:1;
-                uint64_t pci_msi:4;
-                uint64_t pci_int:4;
-                uint64_t uart:2;
-                uint64_t mbox:2;
-                uint64_t gpio:16;
-                uint64_t workq:16;
-#else
-                uint64_t workq:16;
-                uint64_t gpio:16;
-                uint64_t mbox:2;
-                uint64_t uart:2;
-                uint64_t pci_int:4;
-                uint64_t pci_msi:4;
-                uint64_t wdog_sum:1;
-                uint64_t twsi:1;
-                uint64_t rml:1;
-                uint64_t trace:1;
-                uint64_t gmx_drp:1;
-                uint64_t reserved_49_49:1;
-                uint64_t ipd_drp:1;
-                uint64_t sum2:1;
-                uint64_t timer:4;
-                uint64_t usb:1;
-                uint64_t pcm:1;
-                uint64_t mpi:1;
-                uint64_t twsi2:1;
-                uint64_t powiq:1;
-                uint64_t ipdppthr:1;
-                uint64_t reserved_62_62:1;
-                uint64_t bootdma:1;
-#endif
-        } cnf71xx;
+        } s;
+        struct cvmx_ciu_int33_sum0_s cn63xx;
+        struct cvmx_ciu_int33_sum0_s cn63xxp1;
 };
 
 union cvmx_ciu_int_dbg_sel {
         uint64_t u64;
         struct cvmx_ciu_int_dbg_sel_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t sel:3;
-                uint64_t reserved_10_15:6;
-                uint64_t irq:2;
-                uint64_t reserved_5_7:3;
-                uint64_t pp:5;
-#else
-                uint64_t pp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t irq:2;
-                uint64_t reserved_10_15:6;
-                uint64_t sel:3;
-                uint64_t reserved_19_63:45;
-#endif
-        } s;
-        struct cvmx_ciu_int_dbg_sel_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t sel:3;
-                uint64_t reserved_10_15:6;
-                uint64_t irq:2;
-                uint64_t reserved_4_7:4;
-                uint64_t pp:4;
-#else
-                uint64_t pp:4;
-                uint64_t reserved_4_7:4;
-                uint64_t irq:2;
-                uint64_t reserved_10_15:6;
-                uint64_t sel:3;
-                uint64_t reserved_19_63:45;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_int_dbg_sel_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t sel:3;
                 uint64_t reserved_10_15:6;
                 uint64_t irq:2;
                 uint64_t reserved_3_7:5;
                 uint64_t pp:3;
-#else
-                uint64_t pp:3;
-                uint64_t reserved_3_7:5;
-                uint64_t irq:2;
-                uint64_t reserved_10_15:6;
-                uint64_t sel:3;
-                uint64_t reserved_19_63:45;
-#endif
-        } cn63xx;
-        struct cvmx_ciu_int_dbg_sel_cn61xx cn66xx;
-        struct cvmx_ciu_int_dbg_sel_s cn68xx;
-        struct cvmx_ciu_int_dbg_sel_s cn68xxp1;
-        struct cvmx_ciu_int_dbg_sel_cn61xx cnf71xx;
+        } s;
+        struct cvmx_ciu_int_dbg_sel_s cn63xx;
 };
 
 union cvmx_ciu_int_sum1 {
         uint64_t u64;
         struct cvmx_ciu_int_sum1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
+                uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
                 uint64_t reserved_53_55:3;
                 uint64_t lmc0:1;
@@ -7058,8 +1692,7 @@ union cvmx_ciu_int_sum1 {
                 uint64_t pem0:1;
                 uint64_t ptp:1;
                 uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
+                uint64_t reserved_37_45:9;
                 uint64_t agx0:1;
                 uint64_t dpi:1;
                 uint64_t sli:1;
@@ -7082,78 +1715,22 @@ union cvmx_ciu_int_sum1 {
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
         } s;
         struct cvmx_ciu_int_sum1_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t wdog:1;
-#else
-                uint64_t wdog:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn30xx;
         struct cvmx_ciu_int_sum1_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t wdog:2;
-#else
-                uint64_t wdog:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn31xx;
         struct cvmx_ciu_int_sum1_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
-#else
-                uint64_t wdog:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn38xx;
         struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
         struct cvmx_ciu_int_sum1_cn31xx cn50xx;
         struct cvmx_ciu_int_sum1_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t nand:1;
                 uint64_t mii1:1;
@@ -7161,114 +1738,23 @@ union cvmx_ciu_int_sum1 {
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_ciu_int_sum1_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
                 uint64_t uart2:1;
                 uint64_t reserved_4_15:12;
                 uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_15:12;
-                uint64_t uart2:1;
-                uint64_t usb1:1;
-                uint64_t mii1:1;
-                uint64_t reserved_19_63:45;
-#endif
         } cn52xxp1;
         struct cvmx_ciu_int_sum1_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t wdog:12;
-#else
-                uint64_t wdog:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
         struct cvmx_ciu_int_sum1_cn38xx cn58xx;
         struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
-        struct cvmx_ciu_int_sum1_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
         struct cvmx_ciu_int_sum1_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rst:1;
                 uint64_t reserved_57_62:6;
                 uint64_t dfm:1;
@@ -7302,195 +1788,15 @@ union cvmx_ciu_int_sum1 {
                 uint64_t mii1:1;
                 uint64_t reserved_6_17:12;
                 uint64_t wdog:6;
-#else
-                uint64_t wdog:6;
-                uint64_t reserved_6_17:12;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_45:9;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t srio1:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_62:6;
-                uint64_t rst:1;
-#endif
         } cn63xx;
         struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
-        struct cvmx_ciu_int_sum1_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_int_sum1_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_37_46:10;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_46:10;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
 };
 
 union cvmx_ciu_mbox_clrx {
         uint64_t u64;
         struct cvmx_ciu_mbox_clrx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t bits:32;
-#else
-                uint64_t bits:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_ciu_mbox_clrx_s cn30xx;
         struct cvmx_ciu_mbox_clrx_s cn31xx;
@@ -7503,25 +1809,15 @@ union cvmx_ciu_mbox_clrx {
         struct cvmx_ciu_mbox_clrx_s cn56xxp1;
         struct cvmx_ciu_mbox_clrx_s cn58xx;
         struct cvmx_ciu_mbox_clrx_s cn58xxp1;
-        struct cvmx_ciu_mbox_clrx_s cn61xx;
         struct cvmx_ciu_mbox_clrx_s cn63xx;
         struct cvmx_ciu_mbox_clrx_s cn63xxp1;
-        struct cvmx_ciu_mbox_clrx_s cn66xx;
-        struct cvmx_ciu_mbox_clrx_s cn68xx;
-        struct cvmx_ciu_mbox_clrx_s cn68xxp1;
-        struct cvmx_ciu_mbox_clrx_s cnf71xx;
 };
 
 union cvmx_ciu_mbox_setx {
         uint64_t u64;
         struct cvmx_ciu_mbox_setx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t bits:32;
-#else
-                uint64_t bits:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_ciu_mbox_setx_s cn30xx;
         struct cvmx_ciu_mbox_setx_s cn31xx;
@@ -7534,112 +1830,51 @@ union cvmx_ciu_mbox_setx {
         struct cvmx_ciu_mbox_setx_s cn56xxp1;
         struct cvmx_ciu_mbox_setx_s cn58xx;
         struct cvmx_ciu_mbox_setx_s cn58xxp1;
-        struct cvmx_ciu_mbox_setx_s cn61xx;
         struct cvmx_ciu_mbox_setx_s cn63xx;
         struct cvmx_ciu_mbox_setx_s cn63xxp1;
-        struct cvmx_ciu_mbox_setx_s cn66xx;
-        struct cvmx_ciu_mbox_setx_s cn68xx;
-        struct cvmx_ciu_mbox_setx_s cn68xxp1;
-        struct cvmx_ciu_mbox_setx_s cnf71xx;
 };
 
 union cvmx_ciu_nmi {
         uint64_t u64;
         struct cvmx_ciu_nmi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t nmi:32;
-#else
-                uint64_t nmi:32;
-                uint64_t reserved_32_63:32;
-#endif
+                uint64_t reserved_16_63:48;
+                uint64_t nmi:16;
         } s;
         struct cvmx_ciu_nmi_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t nmi:1;
-#else
-                uint64_t nmi:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn30xx;
         struct cvmx_ciu_nmi_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t nmi:2;
-#else
-                uint64_t nmi:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn31xx;
-        struct cvmx_ciu_nmi_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t nmi:16;
-#else
-                uint64_t nmi:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn38xx;
-        struct cvmx_ciu_nmi_cn38xx cn38xxp2;
+        struct cvmx_ciu_nmi_s cn38xx;
+        struct cvmx_ciu_nmi_s cn38xxp2;
         struct cvmx_ciu_nmi_cn31xx cn50xx;
         struct cvmx_ciu_nmi_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t nmi:4;
-#else
-                uint64_t nmi:4;
-                uint64_t reserved_4_63:60;
-#endif
         } cn52xx;
         struct cvmx_ciu_nmi_cn52xx cn52xxp1;
         struct cvmx_ciu_nmi_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t nmi:12;
-#else
-                uint64_t nmi:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_nmi_cn56xx cn56xxp1;
-        struct cvmx_ciu_nmi_cn38xx cn58xx;
-        struct cvmx_ciu_nmi_cn38xx cn58xxp1;
-        struct cvmx_ciu_nmi_cn52xx cn61xx;
+        struct cvmx_ciu_nmi_s cn58xx;
+        struct cvmx_ciu_nmi_s cn58xxp1;
         struct cvmx_ciu_nmi_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t nmi:6;
-#else
-                uint64_t nmi:6;
-                uint64_t reserved_6_63:58;
-#endif
         } cn63xx;
         struct cvmx_ciu_nmi_cn63xx cn63xxp1;
-        struct cvmx_ciu_nmi_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t nmi:10;
-#else
-                uint64_t nmi:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_nmi_s cn68xx;
-        struct cvmx_ciu_nmi_s cn68xxp1;
-        struct cvmx_ciu_nmi_cn52xx cnf71xx;
 };
 
 union cvmx_ciu_pci_inta {
         uint64_t u64;
         struct cvmx_ciu_pci_inta_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t intr:2;
-#else
-                uint64_t intr:2;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_ciu_pci_inta_s cn30xx;
         struct cvmx_ciu_pci_inta_s cn31xx;
@@ -7652,125 +1887,50 @@ union cvmx_ciu_pci_inta {
         struct cvmx_ciu_pci_inta_s cn56xxp1;
         struct cvmx_ciu_pci_inta_s cn58xx;
         struct cvmx_ciu_pci_inta_s cn58xxp1;
-        struct cvmx_ciu_pci_inta_s cn61xx;
         struct cvmx_ciu_pci_inta_s cn63xx;
         struct cvmx_ciu_pci_inta_s cn63xxp1;
-        struct cvmx_ciu_pci_inta_s cn66xx;
-        struct cvmx_ciu_pci_inta_s cn68xx;
-        struct cvmx_ciu_pci_inta_s cn68xxp1;
-        struct cvmx_ciu_pci_inta_s cnf71xx;
-};
-
-union cvmx_ciu_pp_bist_stat {
-        uint64_t u64;
-        struct cvmx_ciu_pp_bist_stat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t pp_bist:32;
-#else
-                uint64_t pp_bist:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu_pp_bist_stat_s cn68xx;
-        struct cvmx_ciu_pp_bist_stat_s cn68xxp1;
 };
 
 union cvmx_ciu_pp_dbg {
         uint64_t u64;
         struct cvmx_ciu_pp_dbg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ppdbg:32;
-#else
-                uint64_t ppdbg:32;
-                uint64_t reserved_32_63:32;
-#endif
+                uint64_t reserved_16_63:48;
+                uint64_t ppdbg:16;
         } s;
         struct cvmx_ciu_pp_dbg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t ppdbg:1;
-#else
-                uint64_t ppdbg:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn30xx;
         struct cvmx_ciu_pp_dbg_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t ppdbg:2;
-#else
-                uint64_t ppdbg:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn31xx;
-        struct cvmx_ciu_pp_dbg_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t ppdbg:16;
-#else
-                uint64_t ppdbg:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn38xx;
-        struct cvmx_ciu_pp_dbg_cn38xx cn38xxp2;
+        struct cvmx_ciu_pp_dbg_s cn38xx;
+        struct cvmx_ciu_pp_dbg_s cn38xxp2;
         struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
         struct cvmx_ciu_pp_dbg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t ppdbg:4;
-#else
-                uint64_t ppdbg:4;
-                uint64_t reserved_4_63:60;
-#endif
         } cn52xx;
         struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
         struct cvmx_ciu_pp_dbg_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t ppdbg:12;
-#else
-                uint64_t ppdbg:12;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
-        struct cvmx_ciu_pp_dbg_cn38xx cn58xx;
-        struct cvmx_ciu_pp_dbg_cn38xx cn58xxp1;
-        struct cvmx_ciu_pp_dbg_cn52xx cn61xx;
+        struct cvmx_ciu_pp_dbg_s cn58xx;
+        struct cvmx_ciu_pp_dbg_s cn58xxp1;
         struct cvmx_ciu_pp_dbg_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t ppdbg:6;
-#else
-                uint64_t ppdbg:6;
-                uint64_t reserved_6_63:58;
-#endif
         } cn63xx;
         struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
-        struct cvmx_ciu_pp_dbg_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t ppdbg:10;
-#else
-                uint64_t ppdbg:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_pp_dbg_s cn68xx;
-        struct cvmx_ciu_pp_dbg_s cn68xxp1;
-        struct cvmx_ciu_pp_dbg_cn52xx cnf71xx;
 };
 
 union cvmx_ciu_pp_pokex {
         uint64_t u64;
         struct cvmx_ciu_pp_pokex_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t poke:64;
-#else
-                uint64_t poke:64;
-#endif
         } s;
         struct cvmx_ciu_pp_pokex_s cn30xx;
         struct cvmx_ciu_pp_pokex_s cn31xx;
@@ -7783,120 +1943,54 @@ union cvmx_ciu_pp_pokex {
         struct cvmx_ciu_pp_pokex_s cn56xxp1;
         struct cvmx_ciu_pp_pokex_s cn58xx;
         struct cvmx_ciu_pp_pokex_s cn58xxp1;
-        struct cvmx_ciu_pp_pokex_s cn61xx;
         struct cvmx_ciu_pp_pokex_s cn63xx;
         struct cvmx_ciu_pp_pokex_s cn63xxp1;
-        struct cvmx_ciu_pp_pokex_s cn66xx;
-        struct cvmx_ciu_pp_pokex_s cn68xx;
-        struct cvmx_ciu_pp_pokex_s cn68xxp1;
-        struct cvmx_ciu_pp_pokex_s cnf71xx;
 };
 
 union cvmx_ciu_pp_rst {
         uint64_t u64;
         struct cvmx_ciu_pp_rst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t rst:31;
-                uint64_t rst0:1;
-#else
+                uint64_t reserved_16_63:48;
+                uint64_t rst:15;
                 uint64_t rst0:1;
-                uint64_t rst:31;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_ciu_pp_rst_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t rst0:1;
-#else
-                uint64_t rst0:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn30xx;
         struct cvmx_ciu_pp_rst_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t rst:1;
                 uint64_t rst0:1;
-#else
-                uint64_t rst0:1;
-                uint64_t rst:1;
-                uint64_t reserved_2_63:62;
-#endif
         } cn31xx;
-        struct cvmx_ciu_pp_rst_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t rst:15;
-                uint64_t rst0:1;
-#else
-                uint64_t rst0:1;
-                uint64_t rst:15;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn38xx;
-        struct cvmx_ciu_pp_rst_cn38xx cn38xxp2;
+        struct cvmx_ciu_pp_rst_s cn38xx;
+        struct cvmx_ciu_pp_rst_s cn38xxp2;
         struct cvmx_ciu_pp_rst_cn31xx cn50xx;
         struct cvmx_ciu_pp_rst_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t rst:3;
                 uint64_t rst0:1;
-#else
-                uint64_t rst0:1;
-                uint64_t rst:3;
-                uint64_t reserved_4_63:60;
-#endif
         } cn52xx;
         struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
         struct cvmx_ciu_pp_rst_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t rst:11;
                 uint64_t rst0:1;
-#else
-                uint64_t rst0:1;
-                uint64_t rst:11;
-                uint64_t reserved_12_63:52;
-#endif
         } cn56xx;
         struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
-        struct cvmx_ciu_pp_rst_cn38xx cn58xx;
-        struct cvmx_ciu_pp_rst_cn38xx cn58xxp1;
-        struct cvmx_ciu_pp_rst_cn52xx cn61xx;
+        struct cvmx_ciu_pp_rst_s cn58xx;
+        struct cvmx_ciu_pp_rst_s cn58xxp1;
         struct cvmx_ciu_pp_rst_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t rst:5;
                 uint64_t rst0:1;
-#else
-                uint64_t rst0:1;
-                uint64_t rst:5;
-                uint64_t reserved_6_63:58;
-#endif
         } cn63xx;
         struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
-        struct cvmx_ciu_pp_rst_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t rst:9;
-                uint64_t rst0:1;
-#else
-                uint64_t rst0:1;
-                uint64_t rst:9;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_pp_rst_s cn68xx;
-        struct cvmx_ciu_pp_rst_s cn68xxp1;
-        struct cvmx_ciu_pp_rst_cn52xx cnf71xx;
 };
 
 union cvmx_ciu_qlm0 {
         uint64_t u64;
         struct cvmx_ciu_qlm0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t g2bypass:1;
                 uint64_t reserved_53_62:10;
                 uint64_t g2deemph:5;
@@ -7910,26 +2004,9 @@ union cvmx_ciu_qlm0 {
                 uint64_t txmargin:5;
                 uint64_t reserved_4_7:4;
                 uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:5;
-                uint64_t reserved_21_30:10;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_39:8;
-                uint64_t g2margin:5;
-                uint64_t reserved_45_47:3;
-                uint64_t g2deemph:5;
-                uint64_t reserved_53_62:10;
-                uint64_t g2bypass:1;
-#endif
         } s;
-        struct cvmx_ciu_qlm0_s cn61xx;
         struct cvmx_ciu_qlm0_s cn63xx;
         struct cvmx_ciu_qlm0_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t txbypass:1;
                 uint64_t reserved_20_30:11;
@@ -7938,47 +2015,12 @@ union cvmx_ciu_qlm0 {
                 uint64_t txmargin:5;
                 uint64_t reserved_4_7:4;
                 uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:4;
-                uint64_t reserved_20_30:11;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn63xxp1;
-        struct cvmx_ciu_qlm0_s cn66xx;
-        struct cvmx_ciu_qlm0_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t txbypass:1;
-                uint64_t reserved_21_30:10;
-                uint64_t txdeemph:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txmargin:5;
-                uint64_t reserved_4_7:4;
-                uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:5;
-                uint64_t reserved_21_30:10;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn68xx;
-        struct cvmx_ciu_qlm0_cn68xx cn68xxp1;
-        struct cvmx_ciu_qlm0_s cnf71xx;
 };
 
 union cvmx_ciu_qlm1 {
         uint64_t u64;
         struct cvmx_ciu_qlm1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t g2bypass:1;
                 uint64_t reserved_53_62:10;
                 uint64_t g2deemph:5;
@@ -7992,26 +2034,9 @@ union cvmx_ciu_qlm1 {
                 uint64_t txmargin:5;
                 uint64_t reserved_4_7:4;
                 uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:5;
-                uint64_t reserved_21_30:10;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_39:8;
-                uint64_t g2margin:5;
-                uint64_t reserved_45_47:3;
-                uint64_t g2deemph:5;
-                uint64_t reserved_53_62:10;
-                uint64_t g2bypass:1;
-#endif
         } s;
-        struct cvmx_ciu_qlm1_s cn61xx;
         struct cvmx_ciu_qlm1_s cn63xx;
         struct cvmx_ciu_qlm1_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t txbypass:1;
                 uint64_t reserved_20_30:11;
@@ -8020,58 +2045,12 @@ union cvmx_ciu_qlm1 {
                 uint64_t txmargin:5;
                 uint64_t reserved_4_7:4;
                 uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:4;
-                uint64_t reserved_20_30:11;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn63xxp1;
-        struct cvmx_ciu_qlm1_s cn66xx;
-        struct cvmx_ciu_qlm1_s cn68xx;
-        struct cvmx_ciu_qlm1_s cn68xxp1;
-        struct cvmx_ciu_qlm1_s cnf71xx;
 };
 
 union cvmx_ciu_qlm2 {
         uint64_t u64;
         struct cvmx_ciu_qlm2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t g2bypass:1;
-                uint64_t reserved_53_62:10;
-                uint64_t g2deemph:5;
-                uint64_t reserved_45_47:3;
-                uint64_t g2margin:5;
-                uint64_t reserved_32_39:8;
-                uint64_t txbypass:1;
-                uint64_t reserved_21_30:10;
-                uint64_t txdeemph:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txmargin:5;
-                uint64_t reserved_4_7:4;
-                uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:5;
-                uint64_t reserved_21_30:10;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_39:8;
-                uint64_t g2margin:5;
-                uint64_t reserved_45_47:3;
-                uint64_t g2deemph:5;
-                uint64_t reserved_53_62:10;
-                uint64_t g2bypass:1;
-#endif
-        } s;
-        struct cvmx_ciu_qlm2_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t txbypass:1;
                 uint64_t reserved_21_30:10;
@@ -8080,20 +2059,9 @@ union cvmx_ciu_qlm2 {
                 uint64_t txmargin:5;
                 uint64_t reserved_4_7:4;
                 uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:5;
-                uint64_t reserved_21_30:10;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_qlm2_cn61xx cn63xx;
+        } s;
+        struct cvmx_ciu_qlm2_s cn63xx;
         struct cvmx_ciu_qlm2_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t txbypass:1;
                 uint64_t reserved_20_30:11;
@@ -8102,116 +2070,18 @@ union cvmx_ciu_qlm2 {
                 uint64_t txmargin:5;
                 uint64_t reserved_4_7:4;
                 uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:4;
-                uint64_t reserved_20_30:11;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn63xxp1;
-        struct cvmx_ciu_qlm2_cn61xx cn66xx;
-        struct cvmx_ciu_qlm2_s cn68xx;
-        struct cvmx_ciu_qlm2_s cn68xxp1;
-        struct cvmx_ciu_qlm2_cn61xx cnf71xx;
-};
-
-union cvmx_ciu_qlm3 {
-        uint64_t u64;
-        struct cvmx_ciu_qlm3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t g2bypass:1;
-                uint64_t reserved_53_62:10;
-                uint64_t g2deemph:5;
-                uint64_t reserved_45_47:3;
-                uint64_t g2margin:5;
-                uint64_t reserved_32_39:8;
-                uint64_t txbypass:1;
-                uint64_t reserved_21_30:10;
-                uint64_t txdeemph:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txmargin:5;
-                uint64_t reserved_4_7:4;
-                uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:5;
-                uint64_t reserved_21_30:10;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_39:8;
-                uint64_t g2margin:5;
-                uint64_t reserved_45_47:3;
-                uint64_t g2deemph:5;
-                uint64_t reserved_53_62:10;
-                uint64_t g2bypass:1;
-#endif
-        } s;
-        struct cvmx_ciu_qlm3_s cn68xx;
-        struct cvmx_ciu_qlm3_s cn68xxp1;
-};
-
-union cvmx_ciu_qlm4 {
-        uint64_t u64;
-        struct cvmx_ciu_qlm4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t g2bypass:1;
-                uint64_t reserved_53_62:10;
-                uint64_t g2deemph:5;
-                uint64_t reserved_45_47:3;
-                uint64_t g2margin:5;
-                uint64_t reserved_32_39:8;
-                uint64_t txbypass:1;
-                uint64_t reserved_21_30:10;
-                uint64_t txdeemph:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txmargin:5;
-                uint64_t reserved_4_7:4;
-                uint64_t lane_en:4;
-#else
-                uint64_t lane_en:4;
-                uint64_t reserved_4_7:4;
-                uint64_t txmargin:5;
-                uint64_t reserved_13_15:3;
-                uint64_t txdeemph:5;
-                uint64_t reserved_21_30:10;
-                uint64_t txbypass:1;
-                uint64_t reserved_32_39:8;
-                uint64_t g2margin:5;
-                uint64_t reserved_45_47:3;
-                uint64_t g2deemph:5;
-                uint64_t reserved_53_62:10;
-                uint64_t g2bypass:1;
-#endif
-        } s;
-        struct cvmx_ciu_qlm4_s cn68xx;
-        struct cvmx_ciu_qlm4_s cn68xxp1;
 };
 
 union cvmx_ciu_qlm_dcok {
         uint64_t u64;
         struct cvmx_ciu_qlm_dcok_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t qlm_dcok:4;
-#else
-                uint64_t qlm_dcok:4;
-                uint64_t reserved_4_63:60;
-#endif
         } s;
         struct cvmx_ciu_qlm_dcok_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t qlm_dcok:2;
-#else
-                uint64_t qlm_dcok:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn52xx;
         struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
         struct cvmx_ciu_qlm_dcok_s cn56xx;
@@ -8221,108 +2091,47 @@ union cvmx_ciu_qlm_dcok {
 union cvmx_ciu_qlm_jtgc {
         uint64_t u64;
         struct cvmx_ciu_qlm_jtgc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t bypass_ext:1;
-                uint64_t reserved_11_15:5;
+                uint64_t reserved_11_63:53;
                 uint64_t clk_div:3;
-                uint64_t reserved_7_7:1;
-                uint64_t mux_sel:3;
-                uint64_t bypass:4;
-#else
+                uint64_t reserved_6_7:2;
+                uint64_t mux_sel:2;
                 uint64_t bypass:4;
-                uint64_t mux_sel:3;
-                uint64_t reserved_7_7:1;
-                uint64_t clk_div:3;
-                uint64_t reserved_11_15:5;
-                uint64_t bypass_ext:1;
-                uint64_t reserved_17_63:47;
-#endif
         } s;
         struct cvmx_ciu_qlm_jtgc_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_11_63:53;
                 uint64_t clk_div:3;
                 uint64_t reserved_5_7:3;
                 uint64_t mux_sel:1;
                 uint64_t reserved_2_3:2;
                 uint64_t bypass:2;
-#else
-                uint64_t bypass:2;
-                uint64_t reserved_2_3:2;
-                uint64_t mux_sel:1;
-                uint64_t reserved_5_7:3;
-                uint64_t clk_div:3;
-                uint64_t reserved_11_63:53;
-#endif
         } cn52xx;
         struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
-        struct cvmx_ciu_qlm_jtgc_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t clk_div:3;
-                uint64_t reserved_6_7:2;
-                uint64_t mux_sel:2;
-                uint64_t bypass:4;
-#else
-                uint64_t bypass:4;
-                uint64_t mux_sel:2;
-                uint64_t reserved_6_7:2;
-                uint64_t clk_div:3;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn56xx;
-        struct cvmx_ciu_qlm_jtgc_cn56xx cn56xxp1;
-        struct cvmx_ciu_qlm_jtgc_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
+        struct cvmx_ciu_qlm_jtgc_s cn56xx;
+        struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
+        struct cvmx_ciu_qlm_jtgc_cn63xx {
                 uint64_t reserved_11_63:53;
                 uint64_t clk_div:3;
                 uint64_t reserved_6_7:2;
                 uint64_t mux_sel:2;
                 uint64_t reserved_3_3:1;
                 uint64_t bypass:3;
-#else
-                uint64_t bypass:3;
-                uint64_t reserved_3_3:1;
-                uint64_t mux_sel:2;
-                uint64_t reserved_6_7:2;
-                uint64_t clk_div:3;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_qlm_jtgc_cn61xx cn63xx;
-        struct cvmx_ciu_qlm_jtgc_cn61xx cn63xxp1;
-        struct cvmx_ciu_qlm_jtgc_cn61xx cn66xx;
-        struct cvmx_ciu_qlm_jtgc_s cn68xx;
-        struct cvmx_ciu_qlm_jtgc_s cn68xxp1;
-        struct cvmx_ciu_qlm_jtgc_cn61xx cnf71xx;
+        } cn63xx;
+        struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_qlm_jtgd {
         uint64_t u64;
         struct cvmx_ciu_qlm_jtgd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t capture:1;
                 uint64_t shift:1;
                 uint64_t update:1;
-                uint64_t reserved_45_60:16;
-                uint64_t select:5;
+                uint64_t reserved_44_60:17;
+                uint64_t select:4;
                 uint64_t reserved_37_39:3;
                 uint64_t shft_cnt:5;
                 uint64_t shft_reg:32;
-#else
-                uint64_t shft_reg:32;
-                uint64_t shft_cnt:5;
-                uint64_t reserved_37_39:3;
-                uint64_t select:5;
-                uint64_t reserved_45_60:16;
-                uint64_t update:1;
-                uint64_t shift:1;
-                uint64_t capture:1;
-#endif
         } s;
         struct cvmx_ciu_qlm_jtgd_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t capture:1;
                 uint64_t shift:1;
                 uint64_t update:1;
@@ -8331,58 +2140,18 @@ union cvmx_ciu_qlm_jtgd {
                 uint64_t reserved_37_39:3;
                 uint64_t shft_cnt:5;
                 uint64_t shft_reg:32;
-#else
-                uint64_t shft_reg:32;
-                uint64_t shft_cnt:5;
-                uint64_t reserved_37_39:3;
-                uint64_t select:2;
-                uint64_t reserved_42_60:19;
-                uint64_t update:1;
-                uint64_t shift:1;
-                uint64_t capture:1;
-#endif
         } cn52xx;
         struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
-        struct cvmx_ciu_qlm_jtgd_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t capture:1;
-                uint64_t shift:1;
-                uint64_t update:1;
-                uint64_t reserved_44_60:17;
-                uint64_t select:4;
-                uint64_t reserved_37_39:3;
-                uint64_t shft_cnt:5;
-                uint64_t shft_reg:32;
-#else
-                uint64_t shft_reg:32;
-                uint64_t shft_cnt:5;
-                uint64_t reserved_37_39:3;
-                uint64_t select:4;
-                uint64_t reserved_44_60:17;
-                uint64_t update:1;
-                uint64_t shift:1;
-                uint64_t capture:1;
-#endif
-        } cn56xx;
+        struct cvmx_ciu_qlm_jtgd_s cn56xx;
         struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t capture:1;
                 uint64_t shift:1;
                 uint64_t update:1;
                 uint64_t reserved_37_60:24;
                 uint64_t shft_cnt:5;
                 uint64_t shft_reg:32;
-#else
-                uint64_t shft_reg:32;
-                uint64_t shft_cnt:5;
-                uint64_t reserved_37_60:24;
-                uint64_t update:1;
-                uint64_t shift:1;
-                uint64_t capture:1;
-#endif
         } cn56xxp1;
-        struct cvmx_ciu_qlm_jtgd_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
+        struct cvmx_ciu_qlm_jtgd_cn63xx {
                 uint64_t capture:1;
                 uint64_t shift:1;
                 uint64_t update:1;
@@ -8391,35 +2160,15 @@ union cvmx_ciu_qlm_jtgd {
                 uint64_t reserved_37_39:3;
                 uint64_t shft_cnt:5;
                 uint64_t shft_reg:32;
-#else
-                uint64_t shft_reg:32;
-                uint64_t shft_cnt:5;
-                uint64_t reserved_37_39:3;
-                uint64_t select:3;
-                uint64_t reserved_43_60:18;
-                uint64_t update:1;
-                uint64_t shift:1;
-                uint64_t capture:1;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_qlm_jtgd_cn61xx cn63xx;
-        struct cvmx_ciu_qlm_jtgd_cn61xx cn63xxp1;
-        struct cvmx_ciu_qlm_jtgd_cn61xx cn66xx;
-        struct cvmx_ciu_qlm_jtgd_s cn68xx;
-        struct cvmx_ciu_qlm_jtgd_s cn68xxp1;
-        struct cvmx_ciu_qlm_jtgd_cn61xx cnf71xx;
+        } cn63xx;
+        struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_soft_bist {
         uint64_t u64;
         struct cvmx_ciu_soft_bist_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t soft_bist:1;
-#else
-                uint64_t soft_bist:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_ciu_soft_bist_s cn30xx;
         struct cvmx_ciu_soft_bist_s cn31xx;
@@ -8432,29 +2181,17 @@ union cvmx_ciu_soft_bist {
         struct cvmx_ciu_soft_bist_s cn56xxp1;
         struct cvmx_ciu_soft_bist_s cn58xx;
         struct cvmx_ciu_soft_bist_s cn58xxp1;
-        struct cvmx_ciu_soft_bist_s cn61xx;
         struct cvmx_ciu_soft_bist_s cn63xx;
         struct cvmx_ciu_soft_bist_s cn63xxp1;
-        struct cvmx_ciu_soft_bist_s cn66xx;
-        struct cvmx_ciu_soft_bist_s cn68xx;
-        struct cvmx_ciu_soft_bist_s cn68xxp1;
-        struct cvmx_ciu_soft_bist_s cnf71xx;
 };
 
 union cvmx_ciu_soft_prst {
         uint64_t u64;
         struct cvmx_ciu_soft_prst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t host64:1;
                 uint64_t npi:1;
                 uint64_t soft_prst:1;
-#else
-                uint64_t soft_prst:1;
-                uint64_t npi:1;
-                uint64_t host64:1;
-                uint64_t reserved_3_63:61;
-#endif
         } s;
         struct cvmx_ciu_soft_prst_s cn30xx;
         struct cvmx_ciu_soft_prst_s cn31xx;
@@ -8462,90 +2199,37 @@ union cvmx_ciu_soft_prst {
         struct cvmx_ciu_soft_prst_s cn38xxp2;
         struct cvmx_ciu_soft_prst_s cn50xx;
         struct cvmx_ciu_soft_prst_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t soft_prst:1;
-#else
-                uint64_t soft_prst:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn52xx;
         struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
         struct cvmx_ciu_soft_prst_cn52xx cn56xx;
         struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
         struct cvmx_ciu_soft_prst_s cn58xx;
         struct cvmx_ciu_soft_prst_s cn58xxp1;
-        struct cvmx_ciu_soft_prst_cn52xx cn61xx;
         struct cvmx_ciu_soft_prst_cn52xx cn63xx;
         struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
-        struct cvmx_ciu_soft_prst_cn52xx cn66xx;
-        struct cvmx_ciu_soft_prst_cn52xx cn68xx;
-        struct cvmx_ciu_soft_prst_cn52xx cn68xxp1;
-        struct cvmx_ciu_soft_prst_cn52xx cnf71xx;
 };
 
 union cvmx_ciu_soft_prst1 {
         uint64_t u64;
         struct cvmx_ciu_soft_prst1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t soft_prst:1;
-#else
-                uint64_t soft_prst:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_ciu_soft_prst1_s cn52xx;
         struct cvmx_ciu_soft_prst1_s cn52xxp1;
         struct cvmx_ciu_soft_prst1_s cn56xx;
         struct cvmx_ciu_soft_prst1_s cn56xxp1;
-        struct cvmx_ciu_soft_prst1_s cn61xx;
         struct cvmx_ciu_soft_prst1_s cn63xx;
         struct cvmx_ciu_soft_prst1_s cn63xxp1;
-        struct cvmx_ciu_soft_prst1_s cn66xx;
-        struct cvmx_ciu_soft_prst1_s cn68xx;
-        struct cvmx_ciu_soft_prst1_s cn68xxp1;
-        struct cvmx_ciu_soft_prst1_s cnf71xx;
-};
-
-union cvmx_ciu_soft_prst2 {
-        uint64_t u64;
-        struct cvmx_ciu_soft_prst2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t soft_prst:1;
-#else
-                uint64_t soft_prst:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_ciu_soft_prst2_s cn66xx;
-};
-
-union cvmx_ciu_soft_prst3 {
-        uint64_t u64;
-        struct cvmx_ciu_soft_prst3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t soft_prst:1;
-#else
-                uint64_t soft_prst:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_ciu_soft_prst3_s cn66xx;
 };
 
 union cvmx_ciu_soft_rst {
         uint64_t u64;
         struct cvmx_ciu_soft_rst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t soft_rst:1;
-#else
-                uint64_t soft_rst:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_ciu_soft_rst_s cn30xx;
         struct cvmx_ciu_soft_rst_s cn31xx;
@@ -8558,1371 +2242,16 @@ union cvmx_ciu_soft_rst {
         struct cvmx_ciu_soft_rst_s cn56xxp1;
         struct cvmx_ciu_soft_rst_s cn58xx;
         struct cvmx_ciu_soft_rst_s cn58xxp1;
-        struct cvmx_ciu_soft_rst_s cn61xx;
         struct cvmx_ciu_soft_rst_s cn63xx;
         struct cvmx_ciu_soft_rst_s cn63xxp1;
-        struct cvmx_ciu_soft_rst_s cn66xx;
-        struct cvmx_ciu_soft_rst_s cn68xx;
-        struct cvmx_ciu_soft_rst_s cn68xxp1;
-        struct cvmx_ciu_soft_rst_s cnf71xx;
-};
-
-union cvmx_ciu_sum1_iox_int {
-        uint64_t u64;
-        struct cvmx_ciu_sum1_iox_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu_sum1_iox_int_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_sum1_iox_int_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_sum1_iox_int_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_ciu_sum1_ppx_ip2 {
-        uint64_t u64;
-        struct cvmx_ciu_sum1_ppx_ip2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu_sum1_ppx_ip2_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_sum1_ppx_ip2_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_sum1_ppx_ip2_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_ciu_sum1_ppx_ip3 {
-        uint64_t u64;
-        struct cvmx_ciu_sum1_ppx_ip3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu_sum1_ppx_ip3_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_sum1_ppx_ip3_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_sum1_ppx_ip3_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_ciu_sum1_ppx_ip4 {
-        uint64_t u64;
-        struct cvmx_ciu_sum1_ppx_ip4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu_sum1_ppx_ip4_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_41_45:5;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_38_39:2;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_4_17:14;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_17:14;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_39:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_45:5;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_sum1_ppx_ip4_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_62_62:1;
-                uint64_t srio3:1;
-                uint64_t srio2:1;
-                uint64_t reserved_57_59:3;
-                uint64_t dfm:1;
-                uint64_t reserved_53_55:3;
-                uint64_t lmc0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t srio0:1;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t agl:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agx1:1;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t dfa:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t zip:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t mii1:1;
-                uint64_t reserved_10_17:8;
-                uint64_t wdog:10;
-#else
-                uint64_t wdog:10;
-                uint64_t reserved_10_17:8;
-                uint64_t mii1:1;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t zip:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t dfa:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t agx1:1;
-                uint64_t reserved_38_45:8;
-                uint64_t agl:1;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t srio0:1;
-                uint64_t reserved_51_51:1;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_55:3;
-                uint64_t dfm:1;
-                uint64_t reserved_57_59:3;
-                uint64_t srio2:1;
-                uint64_t srio3:1;
-                uint64_t reserved_62_62:1;
-                uint64_t rst:1;
-#endif
-        } cn66xx;
-        struct cvmx_ciu_sum1_ppx_ip4_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_53_62:10;
-                uint64_t lmc0:1;
-                uint64_t reserved_50_51:2;
-                uint64_t pem1:1;
-                uint64_t pem0:1;
-                uint64_t ptp:1;
-                uint64_t reserved_41_46:6;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t agx0:1;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t usb:1;
-                uint64_t reserved_32_32:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_28_28:1;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t l2c:1;
-                uint64_t pow:1;
-                uint64_t fpa:1;
-                uint64_t iob:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_4_18:15;
-                uint64_t wdog:4;
-#else
-                uint64_t wdog:4;
-                uint64_t reserved_4_18:15;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t iob:1;
-                uint64_t fpa:1;
-                uint64_t pow:1;
-                uint64_t l2c:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_28_28:1;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_32_32:1;
-                uint64_t usb:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t agx0:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_41_46:6;
-                uint64_t ptp:1;
-                uint64_t pem0:1;
-                uint64_t pem1:1;
-                uint64_t reserved_50_51:2;
-                uint64_t lmc0:1;
-                uint64_t reserved_53_62:10;
-                uint64_t rst:1;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_ciu_sum2_iox_int {
-        uint64_t u64;
-        struct cvmx_ciu_sum2_iox_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_sum2_iox_int_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_sum2_iox_int_cn61xx cn66xx;
-        struct cvmx_ciu_sum2_iox_int_s cnf71xx;
-};
-
-union cvmx_ciu_sum2_ppx_ip2 {
-        uint64_t u64;
-        struct cvmx_ciu_sum2_ppx_ip2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_sum2_ppx_ip2_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_sum2_ppx_ip2_cn61xx cn66xx;
-        struct cvmx_ciu_sum2_ppx_ip2_s cnf71xx;
-};
-
-union cvmx_ciu_sum2_ppx_ip3 {
-        uint64_t u64;
-        struct cvmx_ciu_sum2_ppx_ip3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_sum2_ppx_ip3_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_sum2_ppx_ip3_cn61xx cn66xx;
-        struct cvmx_ciu_sum2_ppx_ip3_s cnf71xx;
-};
-
-union cvmx_ciu_sum2_ppx_ip4 {
-        uint64_t u64;
-        struct cvmx_ciu_sum2_ppx_ip4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t endor:2;
-                uint64_t eoi:1;
-                uint64_t reserved_10_11:2;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_11:2;
-                uint64_t eoi:1;
-                uint64_t endor:2;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_ciu_sum2_ppx_ip4_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t timer:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t timer:6;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_ciu_sum2_ppx_ip4_cn61xx cn66xx;
-        struct cvmx_ciu_sum2_ppx_ip4_s cnf71xx;
 };
 
 union cvmx_ciu_timx {
         uint64_t u64;
         struct cvmx_ciu_timx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_37_63:27;
                 uint64_t one_shot:1;
                 uint64_t len:36;
-#else
-                uint64_t len:36;
-                uint64_t one_shot:1;
-                uint64_t reserved_37_63:27;
-#endif
         } s;
         struct cvmx_ciu_timx_s cn30xx;
         struct cvmx_ciu_timx_s cn31xx;
@@ -9935,35 +2264,13 @@ union cvmx_ciu_timx {
         struct cvmx_ciu_timx_s cn56xxp1;
         struct cvmx_ciu_timx_s cn58xx;
         struct cvmx_ciu_timx_s cn58xxp1;
-        struct cvmx_ciu_timx_s cn61xx;
         struct cvmx_ciu_timx_s cn63xx;
         struct cvmx_ciu_timx_s cn63xxp1;
-        struct cvmx_ciu_timx_s cn66xx;
-        struct cvmx_ciu_timx_s cn68xx;
-        struct cvmx_ciu_timx_s cn68xxp1;
-        struct cvmx_ciu_timx_s cnf71xx;
-};
-
-union cvmx_ciu_tim_multi_cast {
-        uint64_t u64;
-        struct cvmx_ciu_tim_multi_cast_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_ciu_tim_multi_cast_s cn61xx;
-        struct cvmx_ciu_tim_multi_cast_s cn66xx;
-        struct cvmx_ciu_tim_multi_cast_s cnf71xx;
 };
 
 union cvmx_ciu_wdogx {
         uint64_t u64;
         struct cvmx_ciu_wdogx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_46_63:18;
                 uint64_t gstopen:1;
                 uint64_t dstop:1;
@@ -9971,15 +2278,6 @@ union cvmx_ciu_wdogx {
                 uint64_t len:16;
                 uint64_t state:2;
                 uint64_t mode:2;
-#else
-                uint64_t mode:2;
-                uint64_t state:2;
-                uint64_t len:16;
-                uint64_t cnt:24;
-                uint64_t dstop:1;
-                uint64_t gstopen:1;
-                uint64_t reserved_46_63:18;
-#endif
         } s;
         struct cvmx_ciu_wdogx_s cn30xx;
         struct cvmx_ciu_wdogx_s cn31xx;
@@ -9992,13 +2290,8 @@ union cvmx_ciu_wdogx {
         struct cvmx_ciu_wdogx_s cn56xxp1;
         struct cvmx_ciu_wdogx_s cn58xx;
         struct cvmx_ciu_wdogx_s cn58xxp1;
-        struct cvmx_ciu_wdogx_s cn61xx;
         struct cvmx_ciu_wdogx_s cn63xx;
         struct cvmx_ciu_wdogx_s cn63xxp1;
-        struct cvmx_ciu_wdogx_s cn66xx;
-        struct cvmx_ciu_wdogx_s cn68xx;
-        struct cvmx_ciu_wdogx_s cn68xxp1;
-        struct cvmx_ciu_wdogx_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
deleted file mode 100644
index 148bc9a0085..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
+++ /dev/null
@@ -1,7108 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_CIU2_DEFS_H__
-#define __CVMX_CIU2_DEFS_H__
-
-#define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull))
-#define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull))
-#define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull))
-#define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull))
-#define CVMX_CIU2_MSIRED_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_MSIRED_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_MSIRED_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8)
-#define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8)
-#define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8)
-#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8)
-#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8)
-#define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8)
-
-union cvmx_ciu2_ack_iox_int {
-        uint64_t u64;
-        struct cvmx_ciu2_ack_iox_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t ack:1;
-#else
-                uint64_t ack:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_ciu2_ack_iox_int_s cn68xx;
-        struct cvmx_ciu2_ack_iox_int_s cn68xxp1;
-};
-
-union cvmx_ciu2_ack_ppx_ip2 {
-        uint64_t u64;
-        struct cvmx_ciu2_ack_ppx_ip2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t ack:1;
-#else
-                uint64_t ack:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_ciu2_ack_ppx_ip2_s cn68xx;
-        struct cvmx_ciu2_ack_ppx_ip2_s cn68xxp1;
-};
-
-union cvmx_ciu2_ack_ppx_ip3 {
-        uint64_t u64;
-        struct cvmx_ciu2_ack_ppx_ip3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t ack:1;
-#else
-                uint64_t ack:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_ciu2_ack_ppx_ip3_s cn68xx;
-        struct cvmx_ciu2_ack_ppx_ip3_s cn68xxp1;
-};
-
-union cvmx_ciu2_ack_ppx_ip4 {
-        uint64_t u64;
-        struct cvmx_ciu2_ack_ppx_ip4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t ack:1;
-#else
-                uint64_t ack:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_ciu2_ack_ppx_ip4_s cn68xx;
-        struct cvmx_ciu2_ack_ppx_ip4_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_gpio_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_gpio_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_gpio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_gpio_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_gpio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_io {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_io_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_io_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_io_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_io_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_io_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mbox {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_mbox_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mbox_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_mbox_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mbox_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_mbox_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_mem_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mem_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_mem_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mem_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_mem_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_mio_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mio_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_mio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mio_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_mio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_pkt_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_pkt_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_pkt_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_pkt_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_pkt_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_rml_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_rml_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_rml_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_rml_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_rml_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_wdog_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wdog_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_wdog_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wdog_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_wdog_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_wrkq_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wrkq_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_wrkq_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wrkq_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_iox_int_wrkq_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx;
-        struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_gpio_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_gpio_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_io {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_io_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_io_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_io_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_io_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_io_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mbox {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mbox_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mbox_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mem_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mem_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mio_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mio_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_pkt_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_pkt_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_pkt_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_rml_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_rml_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_rml_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wdog_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wdog_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wrkq_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wrkq_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_gpio_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_gpio_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_io {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_io_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_io_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_io_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_io_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_io_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mbox {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mbox_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mbox_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mem_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mem_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mio_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mio_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_pkt_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_pkt_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_pkt_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_rml_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_rml_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_rml_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wdog_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wdog_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wrkq_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wrkq_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_gpio_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_gpio_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_io {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_io_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_io_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_io_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_io_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_io_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mbox {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mbox_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mbox_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mem_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mem_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mio_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mio_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_pkt_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_pkt_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_pkt_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_rml_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_rml_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_rml_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wdog_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wdog_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wrkq_w1c {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wrkq_w1s {
-        uint64_t u64;
-        struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx;
-        struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_intr_ciu_ready {
-        uint64_t u64;
-        struct cvmx_ciu2_intr_ciu_ready_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t ready:1;
-#else
-                uint64_t ready:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_ciu2_intr_ciu_ready_s cn68xx;
-        struct cvmx_ciu2_intr_ciu_ready_s cn68xxp1;
-};
-
-union cvmx_ciu2_intr_ram_ecc_ctl {
-        uint64_t u64;
-        struct cvmx_ciu2_intr_ram_ecc_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t flip_synd:2;
-                uint64_t ecc_ena:1;
-#else
-                uint64_t ecc_ena:1;
-                uint64_t flip_synd:2;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xx;
-        struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xxp1;
-};
-
-union cvmx_ciu2_intr_ram_ecc_st {
-        uint64_t u64;
-        struct cvmx_ciu2_intr_ram_ecc_st_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t addr:7;
-                uint64_t reserved_13_15:3;
-                uint64_t syndrom:9;
-                uint64_t reserved_2_3:2;
-                uint64_t dbe:1;
-                uint64_t sbe:1;
-#else
-                uint64_t sbe:1;
-                uint64_t dbe:1;
-                uint64_t reserved_2_3:2;
-                uint64_t syndrom:9;
-                uint64_t reserved_13_15:3;
-                uint64_t addr:7;
-                uint64_t reserved_23_63:41;
-#endif
-        } s;
-        struct cvmx_ciu2_intr_ram_ecc_st_s cn68xx;
-        struct cvmx_ciu2_intr_ram_ecc_st_s cn68xxp1;
-};
-
-union cvmx_ciu2_intr_slowdown {
-        uint64_t u64;
-        struct cvmx_ciu2_intr_slowdown_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t ctl:3;
-#else
-                uint64_t ctl:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_ciu2_intr_slowdown_s cn68xx;
-        struct cvmx_ciu2_intr_slowdown_s cn68xxp1;
-};
-
-union cvmx_ciu2_msi_rcvx {
-        uint64_t u64;
-        struct cvmx_ciu2_msi_rcvx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t msi_rcv:1;
-#else
-                uint64_t msi_rcv:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_ciu2_msi_rcvx_s cn68xx;
-        struct cvmx_ciu2_msi_rcvx_s cn68xxp1;
-};
-
-union cvmx_ciu2_msi_selx {
-        uint64_t u64;
-        struct cvmx_ciu2_msi_selx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t pp_num:5;
-                uint64_t reserved_6_7:2;
-                uint64_t ip_num:2;
-                uint64_t reserved_1_3:3;
-                uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t reserved_1_3:3;
-                uint64_t ip_num:2;
-                uint64_t reserved_6_7:2;
-                uint64_t pp_num:5;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_ciu2_msi_selx_s cn68xx;
-        struct cvmx_ciu2_msi_selx_s cn68xxp1;
-};
-
-union cvmx_ciu2_msired_ppx_ip2 {
-        uint64_t u64;
-        struct cvmx_ciu2_msired_ppx_ip2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_21_63:43;
-                uint64_t intr:1;
-                uint64_t reserved_17_19:3;
-                uint64_t newint:1;
-                uint64_t reserved_8_15:8;
-                uint64_t msi_num:8;
-#else
-                uint64_t msi_num:8;
-                uint64_t reserved_8_15:8;
-                uint64_t newint:1;
-                uint64_t reserved_17_19:3;
-                uint64_t intr:1;
-                uint64_t reserved_21_63:43;
-#endif
-        } s;
-        struct cvmx_ciu2_msired_ppx_ip2_s cn68xx;
-        struct cvmx_ciu2_msired_ppx_ip2_s cn68xxp1;
-};
-
-union cvmx_ciu2_msired_ppx_ip3 {
-        uint64_t u64;
-        struct cvmx_ciu2_msired_ppx_ip3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_21_63:43;
-                uint64_t intr:1;
-                uint64_t reserved_17_19:3;
-                uint64_t newint:1;
-                uint64_t reserved_8_15:8;
-                uint64_t msi_num:8;
-#else
-                uint64_t msi_num:8;
-                uint64_t reserved_8_15:8;
-                uint64_t newint:1;
-                uint64_t reserved_17_19:3;
-                uint64_t intr:1;
-                uint64_t reserved_21_63:43;
-#endif
-        } s;
-        struct cvmx_ciu2_msired_ppx_ip3_s cn68xx;
-        struct cvmx_ciu2_msired_ppx_ip3_s cn68xxp1;
-};
-
-union cvmx_ciu2_msired_ppx_ip4 {
-        uint64_t u64;
-        struct cvmx_ciu2_msired_ppx_ip4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_21_63:43;
-                uint64_t intr:1;
-                uint64_t reserved_17_19:3;
-                uint64_t newint:1;
-                uint64_t reserved_8_15:8;
-                uint64_t msi_num:8;
-#else
-                uint64_t msi_num:8;
-                uint64_t reserved_8_15:8;
-                uint64_t newint:1;
-                uint64_t reserved_17_19:3;
-                uint64_t intr:1;
-                uint64_t reserved_21_63:43;
-#endif
-        } s;
-        struct cvmx_ciu2_msired_ppx_ip4_s cn68xx;
-        struct cvmx_ciu2_msired_ppx_ip4_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_iox_int_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_iox_int_gpio_s cn68xx;
-        struct cvmx_ciu2_raw_iox_int_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_io {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_iox_int_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_iox_int_io_s cn68xx;
-        struct cvmx_ciu2_raw_iox_int_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_iox_int_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_iox_int_mem_s cn68xx;
-        struct cvmx_ciu2_raw_iox_int_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_iox_int_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_iox_int_mio_s cn68xx;
-        struct cvmx_ciu2_raw_iox_int_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_iox_int_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_iox_int_pkt_s cn68xx;
-        struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_iox_int_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_iox_int_rml_s cn68xx;
-        struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_iox_int_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_iox_int_wdog_s cn68xx;
-        struct cvmx_ciu2_raw_iox_int_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_iox_int_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xx;
-        struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip2_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_io {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip2_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip2_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip2_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip2_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip2_pkt_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip2_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip2_rml_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip2_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip2_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip3_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_io {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip3_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip3_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip3_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip3_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip3_pkt_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip3_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip3_rml_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip3_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip3_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip4_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_io {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip4_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip4_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip4_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip4_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip4_pkt_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip4_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip4_rml_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip4_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_raw_ppx_ip4_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xx;
-        struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_src_iox_int_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_src_iox_int_gpio_s cn68xx;
-        struct cvmx_ciu2_src_iox_int_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_io {
-        uint64_t u64;
-        struct cvmx_ciu2_src_iox_int_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_src_iox_int_io_s cn68xx;
-        struct cvmx_ciu2_src_iox_int_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_mbox {
-        uint64_t u64;
-        struct cvmx_ciu2_src_iox_int_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_src_iox_int_mbox_s cn68xx;
-        struct cvmx_ciu2_src_iox_int_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_src_iox_int_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_src_iox_int_mem_s cn68xx;
-        struct cvmx_ciu2_src_iox_int_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_src_iox_int_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_src_iox_int_mio_s cn68xx;
-        struct cvmx_ciu2_src_iox_int_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_src_iox_int_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_src_iox_int_pkt_s cn68xx;
-        struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_src_iox_int_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_src_iox_int_rml_s cn68xx;
-        struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_src_iox_int_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_src_iox_int_wdog_s cn68xx;
-        struct cvmx_ciu2_src_iox_int_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_src_iox_int_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_src_iox_int_wrkq_s cn68xx;
-        struct cvmx_ciu2_src_iox_int_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip2_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_io {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip2_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip2_io_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip2_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_mbox {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip2_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip2_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip2_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip2_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip2_pkt_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip2_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip2_rml_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip2_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip2_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip3_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_io {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip3_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip3_io_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip3_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_mbox {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip3_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip3_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip3_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip3_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip3_pkt_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip3_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip3_rml_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip3_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip3_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_gpio {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip4_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t gpio:16;
-#else
-                uint64_t gpio:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_io {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip4_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t pem:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pci_inta:2;
-                uint64_t reserved_13_15:3;
-                uint64_t msired:1;
-                uint64_t pci_msi:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_intr:4;
-#else
-                uint64_t pci_intr:4;
-                uint64_t reserved_4_7:4;
-                uint64_t pci_msi:4;
-                uint64_t msired:1;
-                uint64_t reserved_13_15:3;
-                uint64_t pci_inta:2;
-                uint64_t reserved_18_31:14;
-                uint64_t pem:2;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip4_io_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip4_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_mbox {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip4_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_mem {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip4_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lmc:4;
-#else
-                uint64_t lmc:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_mio {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip4_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rst:1;
-                uint64_t reserved_49_62:14;
-                uint64_t ptp:1;
-                uint64_t reserved_45_47:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_38_39:2;
-                uint64_t uart:2;
-                uint64_t reserved_34_35:2;
-                uint64_t twsi:2;
-                uint64_t reserved_19_31:13;
-                uint64_t bootdma:1;
-                uint64_t mio:1;
-                uint64_t nand:1;
-                uint64_t reserved_12_15:4;
-                uint64_t timer:4;
-                uint64_t reserved_3_7:5;
-                uint64_t ipd_drp:1;
-                uint64_t ssoiq:1;
-                uint64_t ipdppthr:1;
-#else
-                uint64_t ipdppthr:1;
-                uint64_t ssoiq:1;
-                uint64_t ipd_drp:1;
-                uint64_t reserved_3_7:5;
-                uint64_t timer:4;
-                uint64_t reserved_12_15:4;
-                uint64_t nand:1;
-                uint64_t mio:1;
-                uint64_t bootdma:1;
-                uint64_t reserved_19_31:13;
-                uint64_t twsi:2;
-                uint64_t reserved_34_35:2;
-                uint64_t uart:2;
-                uint64_t reserved_38_39:2;
-                uint64_t usb_uctl:1;
-                uint64_t reserved_41_43:3;
-                uint64_t usb_hci:1;
-                uint64_t reserved_45_47:3;
-                uint64_t ptp:1;
-                uint64_t reserved_49_62:14;
-                uint64_t rst:1;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_pkt {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip4_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_51:3;
-                uint64_t ilk_drp:2;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip4_pkt_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ilk:1;
-                uint64_t reserved_41_47:7;
-                uint64_t mii:1;
-                uint64_t reserved_33_39:7;
-                uint64_t agl:1;
-                uint64_t reserved_13_31:19;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_5_7:3;
-                uint64_t agx:5;
-#else
-                uint64_t agx:5;
-                uint64_t reserved_5_7:3;
-                uint64_t gmx_drp:5;
-                uint64_t reserved_13_31:19;
-                uint64_t agl:1;
-                uint64_t reserved_33_39:7;
-                uint64_t mii:1;
-                uint64_t reserved_41_47:7;
-                uint64_t ilk:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_rml {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip4_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_35:2;
-                uint64_t dpi_dma:1;
-                uint64_t reserved_37_39:3;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip4_rml_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t trace:4;
-                uint64_t reserved_49_51:3;
-                uint64_t l2c:1;
-                uint64_t reserved_41_47:7;
-                uint64_t dfa:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dpi:1;
-                uint64_t sli:1;
-                uint64_t reserved_31_31:1;
-                uint64_t key:1;
-                uint64_t rad:1;
-                uint64_t tim:1;
-                uint64_t reserved_25_27:3;
-                uint64_t zip:1;
-                uint64_t reserved_17_23:7;
-                uint64_t sso:1;
-                uint64_t reserved_8_15:8;
-                uint64_t pko:1;
-                uint64_t pip:1;
-                uint64_t ipd:1;
-                uint64_t fpa:1;
-                uint64_t reserved_1_3:3;
-                uint64_t iob:1;
-#else
-                uint64_t iob:1;
-                uint64_t reserved_1_3:3;
-                uint64_t fpa:1;
-                uint64_t ipd:1;
-                uint64_t pip:1;
-                uint64_t pko:1;
-                uint64_t reserved_8_15:8;
-                uint64_t sso:1;
-                uint64_t reserved_17_23:7;
-                uint64_t zip:1;
-                uint64_t reserved_25_27:3;
-                uint64_t tim:1;
-                uint64_t rad:1;
-                uint64_t key:1;
-                uint64_t reserved_31_31:1;
-                uint64_t sli:1;
-                uint64_t dpi:1;
-                uint64_t reserved_34_39:6;
-                uint64_t dfa:1;
-                uint64_t reserved_41_47:7;
-                uint64_t l2c:1;
-                uint64_t reserved_49_51:3;
-                uint64_t trace:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_wdog {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip4_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wdog:32;
-#else
-                uint64_t wdog:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_wrkq {
-        uint64_t u64;
-        struct cvmx_ciu2_src_ppx_ip4_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t workq:64;
-#else
-                uint64_t workq:64;
-#endif
-        } s;
-        struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xx;
-        struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_sum_iox_int {
-        uint64_t u64;
-        struct cvmx_ciu2_sum_iox_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t mbox:4;
-                uint64_t reserved_8_59:52;
-                uint64_t gpio:1;
-                uint64_t pkt:1;
-                uint64_t mem:1;
-                uint64_t io:1;
-                uint64_t mio:1;
-                uint64_t rml:1;
-                uint64_t wdog:1;
-                uint64_t workq:1;
-#else
-                uint64_t workq:1;
-                uint64_t wdog:1;
-                uint64_t rml:1;
-                uint64_t mio:1;
-                uint64_t io:1;
-                uint64_t mem:1;
-                uint64_t pkt:1;
-                uint64_t gpio:1;
-                uint64_t reserved_8_59:52;
-                uint64_t mbox:4;
-#endif
-        } s;
-        struct cvmx_ciu2_sum_iox_int_s cn68xx;
-        struct cvmx_ciu2_sum_iox_int_s cn68xxp1;
-};
-
-union cvmx_ciu2_sum_ppx_ip2 {
-        uint64_t u64;
-        struct cvmx_ciu2_sum_ppx_ip2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t mbox:4;
-                uint64_t reserved_8_59:52;
-                uint64_t gpio:1;
-                uint64_t pkt:1;
-                uint64_t mem:1;
-                uint64_t io:1;
-                uint64_t mio:1;
-                uint64_t rml:1;
-                uint64_t wdog:1;
-                uint64_t workq:1;
-#else
-                uint64_t workq:1;
-                uint64_t wdog:1;
-                uint64_t rml:1;
-                uint64_t mio:1;
-                uint64_t io:1;
-                uint64_t mem:1;
-                uint64_t pkt:1;
-                uint64_t gpio:1;
-                uint64_t reserved_8_59:52;
-                uint64_t mbox:4;
-#endif
-        } s;
-        struct cvmx_ciu2_sum_ppx_ip2_s cn68xx;
-        struct cvmx_ciu2_sum_ppx_ip2_s cn68xxp1;
-};
-
-union cvmx_ciu2_sum_ppx_ip3 {
-        uint64_t u64;
-        struct cvmx_ciu2_sum_ppx_ip3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t mbox:4;
-                uint64_t reserved_8_59:52;
-                uint64_t gpio:1;
-                uint64_t pkt:1;
-                uint64_t mem:1;
-                uint64_t io:1;
-                uint64_t mio:1;
-                uint64_t rml:1;
-                uint64_t wdog:1;
-                uint64_t workq:1;
-#else
-                uint64_t workq:1;
-                uint64_t wdog:1;
-                uint64_t rml:1;
-                uint64_t mio:1;
-                uint64_t io:1;
-                uint64_t mem:1;
-                uint64_t pkt:1;
-                uint64_t gpio:1;
-                uint64_t reserved_8_59:52;
-                uint64_t mbox:4;
-#endif
-        } s;
-        struct cvmx_ciu2_sum_ppx_ip3_s cn68xx;
-        struct cvmx_ciu2_sum_ppx_ip3_s cn68xxp1;
-};
-
-union cvmx_ciu2_sum_ppx_ip4 {
-        uint64_t u64;
-        struct cvmx_ciu2_sum_ppx_ip4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t mbox:4;
-                uint64_t reserved_8_59:52;
-                uint64_t gpio:1;
-                uint64_t pkt:1;
-                uint64_t mem:1;
-                uint64_t io:1;
-                uint64_t mio:1;
-                uint64_t rml:1;
-                uint64_t wdog:1;
-                uint64_t workq:1;
-#else
-                uint64_t workq:1;
-                uint64_t wdog:1;
-                uint64_t rml:1;
-                uint64_t mio:1;
-                uint64_t io:1;
-                uint64_t mem:1;
-                uint64_t pkt:1;
-                uint64_t gpio:1;
-                uint64_t reserved_8_59:52;
-                uint64_t mbox:4;
-#endif
-        } s;
-        struct cvmx_ciu2_sum_ppx_ip4_s cn68xx;
-        struct cvmx_ciu2_sum_ppx_ip4_s cn68xxp1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
deleted file mode 100644
index fed91125317..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
+++ /dev/null
@@ -1,617 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- *
- * Support functions for managing command queues used for
- * various hardware blocks.
- *
- * The common command queue infrastructure abstracts out the
- * software necessary for adding to Octeon's chained queue
- * structures. These structures are used for commands to the
- * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each
- * hardware unit takes commands and CSRs of different types,
- * they all use basic linked command buffers to store the
- * pending request. In general, users of the CVMX API don't
- * call cvmx-cmd-queue functions directly. Instead the hardware
- * unit specific wrapper should be used. The wrappers perform
- * unit specific validation and CSR writes to submit the
- * commands.
- *
- * Even though most software will never directly interact with
- * cvmx-cmd-queue, knowledge of its internal working can help
- * in diagnosing performance problems and help with debugging.
- *
- * Command queue pointers are stored in a global named block
- * called "cvmx_cmd_queues". Except for the PKO queues, each
- * hardware queue is stored in its own cache line to reduce SMP
- * contention on spin locks. The PKO queues are stored such that
- * every 16th queue is next to each other in memory. This scheme
- * allows for queues being in separate cache lines when there
- * are low number of queues per port. With 16 queues per port,
- * the first queue for each port is in the same cache area. The
- * second queues for each port are in another area, etc. This
- * allows software to implement very efficient lockless PKO with
- * 16 queues per port using a minimum of cache lines per core.
- * All queues for a given core will be isolated in the same
- * cache area.
- *
- * In addition to the memory pointer layout, cvmx-cmd-queue
- * provides an optimized fair ll/sc locking mechanism for the
- * queues. The lock uses a "ticket / now serving" model to
- * maintain fair order on contended locks. In addition, it uses
- * predicted locking time to limit cache contention. When a core
- * know it must wait in line for a lock, it spins on the
- * internal cycle counter to completely eliminate any causes of
- * bus traffic.
- *
- */
-
-#ifndef __CVMX_CMD_QUEUE_H__
-#define __CVMX_CMD_QUEUE_H__
-
-#include <linux/prefetch.h>
-
-#include <asm/octeon/cvmx-fpa.h>
-/**
- * By default we disable the max depth support. Most programs
- * don't use it and it slows down the command queue processing
- * significantly.
- */
-#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH
-#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0
-#endif
-
-/**
- * Enumeration representing all hardware blocks that use command
- * queues. Each hardware block has up to 65536 sub identifiers for
- * multiple command queues. Not all chips support all hardware
- * units.
- */
-typedef enum {
-        CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
-
-#define CVMX_CMD_QUEUE_PKO(queue) \
-        ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue))))
-
-        CVMX_CMD_QUEUE_ZIP = 0x10000,
-        CVMX_CMD_QUEUE_DFA = 0x20000,
-        CVMX_CMD_QUEUE_RAID = 0x30000,
-        CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
-
-#define CVMX_CMD_QUEUE_DMA(queue) \
-        ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue))))
-
-        CVMX_CMD_QUEUE_END = 0x50000,
-} cvmx_cmd_queue_id_t;
-
-/**
- * Command write operations can fail if the command queue needs
- * a new buffer and the associated FPA pool is empty. It can also
- * fail if the number of queued command words reaches the maximum
- * set at initialization.
- */
-typedef enum {
-        CVMX_CMD_QUEUE_SUCCESS = 0,
-        CVMX_CMD_QUEUE_NO_MEMORY = -1,
-        CVMX_CMD_QUEUE_FULL = -2,
-        CVMX_CMD_QUEUE_INVALID_PARAM = -3,
-        CVMX_CMD_QUEUE_ALREADY_SETUP = -4,
-} cvmx_cmd_queue_result_t;
-
-typedef struct {
-        /* You have lock when this is your ticket */
-        uint8_t now_serving;
-        uint64_t unused1:24;
-        /* Maximum outstanding command words */
-        uint32_t max_depth;
-        /* FPA pool buffers come from */
-        uint64_t fpa_pool:3;
-        /* Top of command buffer pointer shifted 7 */
-        uint64_t base_ptr_div128:29;
-        uint64_t unused2:6;
-        /* FPA buffer size in 64bit words minus 1 */
-        uint64_t pool_size_m1:13;
-        /* Number of commands already used in buffer */
-        uint64_t index:13;
-} __cvmx_cmd_queue_state_t;
-
-/**
- * This structure contains the global state of all command queues.
- * It is stored in a bootmem named block and shared by all
- * applications running on Octeon. Tickets are stored in a differnet
- * cahce line that queue information to reduce the contention on the
- * ll/sc used to get a ticket. If this is not the case, the update
- * of queue state causes the ll/sc to fail quite often.
- */
-typedef struct {
-        uint64_t ticket[(CVMX_CMD_QUEUE_END >> 16) * 256];
-        __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256];
-} __cvmx_cmd_queue_all_state_t;
-
-/**
- * Initialize a command queue for use. The initial FPA buffer is
- * allocated and the hardware unit is configured to point to the
- * new command queue.
- *
- * @queue_id:  Hardware command queue to initialize.
- * @max_depth: Maximum outstanding commands that can be queued.
- * @fpa_pool:  FPA pool the command queues should come from.
- * @pool_size: Size of each buffer in the FPA pool (bytes)
- *
- * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
- */
-cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
-                                                  int max_depth, int fpa_pool,
-                                                  int pool_size);
-
-/**
- * Shutdown a queue a free it's command buffers to the FPA. The
- * hardware connected to the queue must be stopped before this
- * function is called.
- *
- * @queue_id: Queue to shutdown
- *
- * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
- */
-cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id);
-
-/**
- * Return the number of command words pending in the queue. This
- * function may be relatively slow for some hardware units.
- *
- * @queue_id: Hardware command queue to query
- *
- * Returns Number of outstanding commands
- */
-int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
-
-/**
- * Return the command buffer to be written to. The purpose of this
- * function is to allow CVMX routine access t othe low level buffer
- * for initial hardware setup. User applications should not call this
- * function directly.
- *
- * @queue_id: Command queue to query
- *
- * Returns Command buffer or NULL on failure
- */
-void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
-
-/**
- * Get the index into the state arrays for the supplied queue id.
- *
- * @queue_id: Queue ID to get an index for
- *
- * Returns Index into the state arrays
- */
-static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
-{
-        /*
-         * Warning: This code currently only works with devices that
-         * have 256 queues or less. Devices with more than 16 queues
-         * are laid out in memory to allow cores quick access to
-         * every 16th queue. This reduces cache thrashing when you are
-         * running 16 queues per port to support lockless operation.
-         */
-        int unit = queue_id >> 16;
-        int q = (queue_id >> 4) & 0xf;
-        int core = queue_id & 0xf;
-        return unit * 256 + core * 16 + q;
-}
-
-/**
- * Lock the supplied queue so nobody else is updating it at the same
- * time as us.
- *
- * @queue_id: Queue ID to lock
- * @qptr:     Pointer to the queue's global state
- */
-static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id,
-                                         __cvmx_cmd_queue_state_t *qptr)
-{
-        extern __cvmx_cmd_queue_all_state_t
-            *__cvmx_cmd_queue_state_ptr;
-        int tmp;
-        int my_ticket;
-        prefetch(qptr);
-        asm volatile (
-                ".set push\n"
-                ".set noreorder\n"
-                "1:\n"
-                /* Atomic add one to ticket_ptr */
-                "ll     %[my_ticket], %[ticket_ptr]\n"
-                /* and store the original value */
-                "li     %[ticket], 1\n"
-                /* in my_ticket */
-                "baddu  %[ticket], %[my_ticket]\n"
-                "sc     %[ticket], %[ticket_ptr]\n"
-                "beqz   %[ticket], 1b\n"
-                " nop\n"
-                /* Load the current now_serving ticket */
-                "lbu    %[ticket], %[now_serving]\n"
-                "2:\n"
-                /* Jump out if now_serving == my_ticket */
-                "beq    %[ticket], %[my_ticket], 4f\n"
-                /* Find out how many tickets are in front of me */
-                " subu   %[ticket], %[my_ticket], %[ticket]\n"
-                /* Use tickets in front of me minus one to delay */
-                "subu  %[ticket], 1\n"
-                /* Delay will be ((tickets in front)-1)*32 loops */
-                "cins   %[ticket], %[ticket], 5, 7\n"
-                "3:\n"
-                /* Loop here until our ticket might be up */
-                "bnez   %[ticket], 3b\n"
-                " subu  %[ticket], 1\n"
-                /* Jump back up to check out ticket again */
-                "b      2b\n"
-                /* Load the current now_serving ticket */
-                " lbu   %[ticket], %[now_serving]\n"
-                "4:\n"
-                ".set pop\n" :
-                [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
-                [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp),
-                [my_ticket] "=r"(my_ticket)
-            );
-}
-
-/**
- * Unlock the queue, flushing all writes.
- *
- * @qptr:   Queue to unlock
- */
-static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr)
-{
-        qptr->now_serving++;
-        CVMX_SYNCWS;
-}
-
-/**
- * Get the queue state structure for the given queue id
- *
- * @queue_id: Queue id to get
- *
- * Returns Queue structure or NULL on failure
- */
-static inline __cvmx_cmd_queue_state_t
-    *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id)
-{
-        extern __cvmx_cmd_queue_all_state_t
-            *__cvmx_cmd_queue_state_ptr;
-        return &__cvmx_cmd_queue_state_ptr->
-            state[__cvmx_cmd_queue_get_index(queue_id)];
-}
-
-/**
- * Write an arbitrary number of command words to a command queue.
- * This is a generic function; the fixed number of command word
- * functions yield higher performance.
- *
- * @queue_id:  Hardware command queue to write to
- * @use_locking:
- *                  Use internal locking to ensure exclusive access for queue
- *                  updates. If you don't use this locking you must ensure
- *                  exclusivity some other way. Locking is strongly recommended.
- * @cmd_count: Number of command words to write
- * @cmds:      Array of commands to write
- *
- * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
- */
-static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t
-                                                           queue_id,
-                                                           int use_locking,
-                                                           int cmd_count,
-                                                           uint64_t *cmds)
-{
-        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
-
-        /* Make sure nobody else is updating the same queue */
-        if (likely(use_locking))
-                __cvmx_cmd_queue_lock(queue_id, qptr);
-
-        /*
-         * If a max queue length was specified then make sure we don't
-         * exceed it. If any part of the command would be below the
-         * limit we allow it.
-         */
-        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
-                if (unlikely
-                    (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
-                        if (likely(use_locking))
-                                __cvmx_cmd_queue_unlock(qptr);
-                        return CVMX_CMD_QUEUE_FULL;
-                }
-        }
-
-        /*
-         * Normally there is plenty of room in the current buffer for
-         * the command.
-         */
-        if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) {
-                uint64_t *ptr =
-                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
-                                                  base_ptr_div128 << 7);
-                ptr += qptr->index;
-                qptr->index += cmd_count;
-                while (cmd_count--)
-                        *ptr++ = *cmds++;
-        } else {
-                uint64_t *ptr;
-                int count;
-                /*
-                 * We need a new command buffer. Fail if there isn't
-                 * one available.
-                 */
-                uint64_t *new_buffer =
-                    (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
-                if (unlikely(new_buffer == NULL)) {
-                        if (likely(use_locking))
-                                __cvmx_cmd_queue_unlock(qptr);
-                        return CVMX_CMD_QUEUE_NO_MEMORY;
-                }
-                ptr =
-                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
-                                                  base_ptr_div128 << 7);
-                /*
-                 * Figure out how many command words will fit in this
-                 * buffer. One location will be needed for the next
-                 * buffer pointer.
-                 */
-                count = qptr->pool_size_m1 - qptr->index;
-                ptr += qptr->index;
-                cmd_count -= count;
-                while (count--)
-                        *ptr++ = *cmds++;
-                *ptr = cvmx_ptr_to_phys(new_buffer);
-                /*
-                 * The current buffer is full and has a link to the
-                 * next buffer. Time to write the rest of the commands
-                 * into the new buffer.
-                 */
-                qptr->base_ptr_div128 = *ptr >> 7;
-                qptr->index = cmd_count;
-                ptr = new_buffer;
-                while (cmd_count--)
-                        *ptr++ = *cmds++;
-        }
-
-        /* All updates are complete. Release the lock and return */
-        if (likely(use_locking))
-                __cvmx_cmd_queue_unlock(qptr);
-        return CVMX_CMD_QUEUE_SUCCESS;
-}
-
-/**
- * Simple function to write two command words to a command
- * queue.
- *
- * @queue_id: Hardware command queue to write to
- * @use_locking:
- *                 Use internal locking to ensure exclusive access for queue
- *                 updates. If you don't use this locking you must ensure
- *                 exclusivity some other way. Locking is strongly recommended.
- * @cmd1:     Command
- * @cmd2:     Command
- *
- * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
- */
-static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t
-                                                            queue_id,
-                                                            int use_locking,
-                                                            uint64_t cmd1,
-                                                            uint64_t cmd2)
-{
-        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
-
-        /* Make sure nobody else is updating the same queue */
-        if (likely(use_locking))
-                __cvmx_cmd_queue_lock(queue_id, qptr);
-
-        /*
-         * If a max queue length was specified then make sure we don't
-         * exceed it. If any part of the command would be below the
-         * limit we allow it.
-         */
-        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
-                if (unlikely
-                    (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
-                        if (likely(use_locking))
-                                __cvmx_cmd_queue_unlock(qptr);
-                        return CVMX_CMD_QUEUE_FULL;
-                }
-        }
-
-        /*
-         * Normally there is plenty of room in the current buffer for
-         * the command.
-         */
-        if (likely(qptr->index + 2 < qptr->pool_size_m1)) {
-                uint64_t *ptr =
-                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
-                                                  base_ptr_div128 << 7);
-                ptr += qptr->index;
-                qptr->index += 2;
-                ptr[0] = cmd1;
-                ptr[1] = cmd2;
-        } else {
-                uint64_t *ptr;
-                /*
-                 * Figure out how many command words will fit in this
-                 * buffer. One location will be needed for the next
-                 * buffer pointer.
-                 */
-                int count = qptr->pool_size_m1 - qptr->index;
-                /*
-                 * We need a new command buffer. Fail if there isn't
-                 * one available.
-                 */
-                uint64_t *new_buffer =
-                    (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
-                if (unlikely(new_buffer == NULL)) {
-                        if (likely(use_locking))
-                                __cvmx_cmd_queue_unlock(qptr);
-                        return CVMX_CMD_QUEUE_NO_MEMORY;
-                }
-                count--;
-                ptr =
-                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
-                                                  base_ptr_div128 << 7);
-                ptr += qptr->index;
-                *ptr++ = cmd1;
-                if (likely(count))
-                        *ptr++ = cmd2;
-                *ptr = cvmx_ptr_to_phys(new_buffer);
-                /*
-                 * The current buffer is full and has a link to the
-                 * next buffer. Time to write the rest of the commands
-                 * into the new buffer.
-                 */
-                qptr->base_ptr_div128 = *ptr >> 7;
-                qptr->index = 0;
-                if (unlikely(count == 0)) {
-                        qptr->index = 1;
-                        new_buffer[0] = cmd2;
-                }
-        }
-
-        /* All updates are complete. Release the lock and return */
-        if (likely(use_locking))
-                __cvmx_cmd_queue_unlock(qptr);
-        return CVMX_CMD_QUEUE_SUCCESS;
-}
-
-/**
- * Simple function to write three command words to a command
- * queue.
- *
- * @queue_id: Hardware command queue to write to
- * @use_locking:
- *                 Use internal locking to ensure exclusive access for queue
- *                 updates. If you don't use this locking you must ensure
- *                 exclusivity some other way. Locking is strongly recommended.
- * @cmd1:     Command
- * @cmd2:     Command
- * @cmd3:     Command
- *
- * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
- */
-static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t
-                                                            queue_id,
-                                                            int use_locking,
-                                                            uint64_t cmd1,
-                                                            uint64_t cmd2,
-                                                            uint64_t cmd3)
-{
-        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
-
-        /* Make sure nobody else is updating the same queue */
-        if (likely(use_locking))
-                __cvmx_cmd_queue_lock(queue_id, qptr);
-
-        /*
-         * If a max queue length was specified then make sure we don't
-         * exceed it. If any part of the command would be below the
-         * limit we allow it.
-         */
-        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
-                if (unlikely
-                    (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
-                        if (likely(use_locking))
-                                __cvmx_cmd_queue_unlock(qptr);
-                        return CVMX_CMD_QUEUE_FULL;
-                }
-        }
-
-        /*
-         * Normally there is plenty of room in the current buffer for
-         * the command.
-         */
-        if (likely(qptr->index + 3 < qptr->pool_size_m1)) {
-                uint64_t *ptr =
-                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
-                                                  base_ptr_div128 << 7);
-                ptr += qptr->index;
-                qptr->index += 3;
-                ptr[0] = cmd1;
-                ptr[1] = cmd2;
-                ptr[2] = cmd3;
-        } else {
-                uint64_t *ptr;
-                /*
-                 * Figure out how many command words will fit in this
-                 * buffer. One location will be needed for the next
-                 * buffer pointer
-                 */
-                int count = qptr->pool_size_m1 - qptr->index;
-                /*
-                 * We need a new command buffer. Fail if there isn't
-                 * one available
-                 */
-                uint64_t *new_buffer =
-                    (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
-                if (unlikely(new_buffer == NULL)) {
-                        if (likely(use_locking))
-                                __cvmx_cmd_queue_unlock(qptr);
-                        return CVMX_CMD_QUEUE_NO_MEMORY;
-                }
-                count--;
-                ptr =
-                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
-                                                  base_ptr_div128 << 7);
-                ptr += qptr->index;
-                *ptr++ = cmd1;
-                if (count) {
-                        *ptr++ = cmd2;
-                        if (count > 1)
-                                *ptr++ = cmd3;
-                }
-                *ptr = cvmx_ptr_to_phys(new_buffer);
-                /*
-                 * The current buffer is full and has a link to the
-                 * next buffer. Time to write the rest of the commands
-                 * into the new buffer.
-                 */
-                qptr->base_ptr_div128 = *ptr >> 7;
-                qptr->index = 0;
-                ptr = new_buffer;
-                if (count == 0) {
-                        *ptr++ = cmd2;
-                        qptr->index++;
-                }
-                if (count < 2) {
-                        *ptr++ = cmd3;
-                        qptr->index++;
-                }
-        }
-
-        /* All updates are complete. Release the lock and return */
-        if (likely(use_locking))
-                __cvmx_cmd_queue_unlock(qptr);
-        return CVMX_CMD_QUEUE_SUCCESS;
-}
-
-#endif /* __CVMX_CMD_QUEUE_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h
deleted file mode 100644
index 26835d1b43b..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-config.h
+++ /dev/null
@@ -1,168 +0,0 @@
-#ifndef __CVMX_CONFIG_H__
-#define __CVMX_CONFIG_H__
-
-/************************* Config Specific Defines ************************/
-#define CVMX_LLM_NUM_PORTS 1
-#define CVMX_NULL_POINTER_PROTECT 1
-#define CVMX_ENABLE_DEBUG_PRINTS 1
-/* PKO queues per port for interface 0 (ports 0-15) */
-#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
-/* PKO queues per port for interface 1 (ports 16-31) */
-#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
-/* Limit on the number of PKO ports enabled for interface 0 */
-#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
-/* Limit on the number of PKO ports enabled for interface 1 */
-#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
-/* PKO queues per port for PCI (ports 32-35) */
-#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
-/* PKO queues per port for Loop devices (ports 36-39) */
-#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
-
-/************************* FPA allocation *********************************/
-/* Pool sizes in bytes, must be multiple of a cache line */
-#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
-#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
-#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
-#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
-#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
-#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
-#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
-#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
-
-/* Pools in use */
-/* Packet buffers */
-#define CVMX_FPA_PACKET_POOL                (0)
-#define CVMX_FPA_PACKET_POOL_SIZE           CVMX_FPA_POOL_0_SIZE
-/* Work queue entrys */
-#define CVMX_FPA_WQE_POOL                   (1)
-#define CVMX_FPA_WQE_POOL_SIZE              CVMX_FPA_POOL_1_SIZE
-/* PKO queue command buffers */
-#define CVMX_FPA_OUTPUT_BUFFER_POOL         (2)
-#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    CVMX_FPA_POOL_2_SIZE
-
-/*************************  FAU allocation ********************************/
-/* The fetch and add registers are allocated here.  They are arranged
- * in order of descending size so that all alignment constraints are
- * automatically met.  The enums are linked so that the following enum
- * continues allocating where the previous one left off, so the
- * numbering within each enum always starts with zero.  The macros
- * take care of the address increment size, so the values entered
- * always increase by 1.  FAU registers are accessed with byte
- * addresses.
- */
-
-#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START)
-typedef enum {
-        CVMX_FAU_REG_64_START   = 0,
-        CVMX_FAU_REG_64_END     = CVMX_FAU_REG_64_ADDR(0),
-} cvmx_fau_reg_64_t;
-
-#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START)
-typedef enum {
-        CVMX_FAU_REG_32_START   = CVMX_FAU_REG_64_END,
-        CVMX_FAU_REG_32_END     = CVMX_FAU_REG_32_ADDR(0),
-} cvmx_fau_reg_32_t;
-
-#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START)
-typedef enum {
-        CVMX_FAU_REG_16_START   = CVMX_FAU_REG_32_END,
-        CVMX_FAU_REG_16_END     = CVMX_FAU_REG_16_ADDR(0),
-} cvmx_fau_reg_16_t;
-
-#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
-typedef enum {
-        CVMX_FAU_REG_8_START    = CVMX_FAU_REG_16_END,
-        CVMX_FAU_REG_8_END      = CVMX_FAU_REG_8_ADDR(0),
-} cvmx_fau_reg_8_t;
-
-/*
- * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first
- * available FAU address that is not allocated in cvmx-config.h. This
- * is 64 bit aligned.
- */
-#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
-#define CVMX_FAU_REG_END (2048)
-
-/********************** scratch memory allocation *************************/
-/* Scratchpad memory allocation.  Note that these are byte memory
- * addresses.  Some uses of scratchpad (IOBDMA for example) require
- * the use of 8-byte aligned addresses, so proper alignment needs to
- * be taken into account.
- */
-/* Generic scratch iobdma area */
-#define CVMX_SCR_SCRATCH               (0)
-/* First location available after cvmx-config.h allocated region. */
-#define CVMX_SCR_REG_AVAIL_BASE        (8)
-
-/*
- * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve
- * before the beginning of the packet. If necessary, override the
- * default here.  See the IPD section of the hardware manual for MBUFF
- * SKIP details.
- */
-#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
-
-/*
- * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve
- * in each chained packet element. If necessary, override the default
- * here.
- */
-#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
-
-/*
- * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is
- * enabled for all input ports. This controls if IPD sends
- * backpressure to all ports if Octeon's FPA pools don't have enough
- * packet or work queue entries. Even when this is off, it is still
- * possible to get backpressure from individual hardware ports. When
- * configuring backpressure, also check
- * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override
- * the default here.
- */
-#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
-
-/*
- * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
- * function. Once it is enabled the hardware starts accepting
- * packets. You might want to skip the IPD enable if configuration
- * changes are need from the default helper setup. If necessary,
- * override the default here.
- */
-#define CVMX_HELPER_ENABLE_IPD 0
-
-/*
- * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
- * to incoming packets.
- */
-#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
-
-#define CVMX_ENABLE_PARAMETER_CHECKING 0
-
-/*
- * The following select which fields are used by the PIP to generate
- * the tag on INPUT
- * 0: don't include
- * 1: include
- */
-#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP       0
-#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP       0
-#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT     0
-#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT     0
-#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER  0
-#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP       0
-#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP       0
-#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT     0
-#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT     0
-#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL     0
-#define CVMX_HELPER_INPUT_TAG_INPUT_PORT        1
-
-/* Select skip mode for input ports */
-#define CVMX_HELPER_INPUT_PORT_SKIP_MODE        CVMX_PIP_PORT_CFG_MODE_SKIPL2
-
-/*
- * Force backpressure to be disabled.  This overrides all other
- * backpressure configuration.
- */
-#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
-
-#endif /* __CVMX_CONFIG_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
deleted file mode 100644
index 40799cdae69..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_DBG_DEFS_H__
-#define __CVMX_DBG_DEFS_H__
-
-#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
-
-union cvmx_dbg_data {
-        uint64_t u64;
-        struct cvmx_dbg_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t c_mul:5;
-                uint64_t dsel_ext:1;
-                uint64_t data:17;
-#else
-                uint64_t data:17;
-                uint64_t dsel_ext:1;
-                uint64_t c_mul:5;
-                uint64_t reserved_23_63:41;
-#endif
-        } s;
-        struct cvmx_dbg_data_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_31_63:33;
-                uint64_t pll_mul:3;
-                uint64_t reserved_23_27:5;
-                uint64_t c_mul:5;
-                uint64_t dsel_ext:1;
-                uint64_t data:17;
-#else
-                uint64_t data:17;
-                uint64_t dsel_ext:1;
-                uint64_t c_mul:5;
-                uint64_t reserved_23_27:5;
-                uint64_t pll_mul:3;
-                uint64_t reserved_31_63:33;
-#endif
-        } cn30xx;
-        struct cvmx_dbg_data_cn30xx cn31xx;
-        struct cvmx_dbg_data_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t d_mul:4;
-                uint64_t dclk_mul2:1;
-                uint64_t cclk_div2:1;
-                uint64_t c_mul:5;
-                uint64_t dsel_ext:1;
-                uint64_t data:17;
-#else
-                uint64_t data:17;
-                uint64_t dsel_ext:1;
-                uint64_t c_mul:5;
-                uint64_t cclk_div2:1;
-                uint64_t dclk_mul2:1;
-                uint64_t d_mul:4;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn38xx;
-        struct cvmx_dbg_data_cn38xx cn38xxp2;
-        struct cvmx_dbg_data_cn30xx cn50xx;
-        struct cvmx_dbg_data_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t rem:6;
-                uint64_t c_mul:5;
-                uint64_t dsel_ext:1;
-                uint64_t data:17;
-#else
-                uint64_t data:17;
-                uint64_t dsel_ext:1;
-                uint64_t c_mul:5;
-                uint64_t rem:6;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn58xx;
-        struct cvmx_dbg_data_cn58xx cn58xxp1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
deleted file mode 100644
index dd5b0428de3..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
+++ /dev/null
@@ -1,1052 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_DPI_DEFS_H__
-#define __CVMX_DPI_DEFS_H__
-
-#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
-#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
-#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
-#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
-#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
-#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
-#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
-#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
-#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
-#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
-#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
-#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
-#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
-#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
-#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
-#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
-#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
-#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
-static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-
-                if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
-                        return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
-
-                if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
-                        return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
-                return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
-        }
-        return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
-}
-
-#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
-
-union cvmx_dpi_bist_status {
-        uint64_t u64;
-        struct cvmx_dpi_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_47_63:17;
-                uint64_t bist:47;
-#else
-                uint64_t bist:47;
-                uint64_t reserved_47_63:17;
-#endif
-        } s;
-        struct cvmx_dpi_bist_status_s cn61xx;
-        struct cvmx_dpi_bist_status_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_45_63:19;
-                uint64_t bist:45;
-#else
-                uint64_t bist:45;
-                uint64_t reserved_45_63:19;
-#endif
-        } cn63xx;
-        struct cvmx_dpi_bist_status_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_37_63:27;
-                uint64_t bist:37;
-#else
-                uint64_t bist:37;
-                uint64_t reserved_37_63:27;
-#endif
-        } cn63xxp1;
-        struct cvmx_dpi_bist_status_s cn66xx;
-        struct cvmx_dpi_bist_status_cn63xx cn68xx;
-        struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
-        struct cvmx_dpi_bist_status_s cnf71xx;
-};
-
-union cvmx_dpi_ctl {
-        uint64_t u64;
-        struct cvmx_dpi_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t clk:1;
-                uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t clk:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_dpi_ctl_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } cn61xx;
-        struct cvmx_dpi_ctl_s cn63xx;
-        struct cvmx_dpi_ctl_s cn63xxp1;
-        struct cvmx_dpi_ctl_s cn66xx;
-        struct cvmx_dpi_ctl_s cn68xx;
-        struct cvmx_dpi_ctl_s cn68xxp1;
-        struct cvmx_dpi_ctl_cn61xx cnf71xx;
-};
-
-union cvmx_dpi_dmax_counts {
-        uint64_t u64;
-        struct cvmx_dpi_dmax_counts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_39_63:25;
-                uint64_t fcnt:7;
-                uint64_t dbell:32;
-#else
-                uint64_t dbell:32;
-                uint64_t fcnt:7;
-                uint64_t reserved_39_63:25;
-#endif
-        } s;
-        struct cvmx_dpi_dmax_counts_s cn61xx;
-        struct cvmx_dpi_dmax_counts_s cn63xx;
-        struct cvmx_dpi_dmax_counts_s cn63xxp1;
-        struct cvmx_dpi_dmax_counts_s cn66xx;
-        struct cvmx_dpi_dmax_counts_s cn68xx;
-        struct cvmx_dpi_dmax_counts_s cn68xxp1;
-        struct cvmx_dpi_dmax_counts_s cnf71xx;
-};
-
-union cvmx_dpi_dmax_dbell {
-        uint64_t u64;
-        struct cvmx_dpi_dmax_dbell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t dbell:16;
-#else
-                uint64_t dbell:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_dpi_dmax_dbell_s cn61xx;
-        struct cvmx_dpi_dmax_dbell_s cn63xx;
-        struct cvmx_dpi_dmax_dbell_s cn63xxp1;
-        struct cvmx_dpi_dmax_dbell_s cn66xx;
-        struct cvmx_dpi_dmax_dbell_s cn68xx;
-        struct cvmx_dpi_dmax_dbell_s cn68xxp1;
-        struct cvmx_dpi_dmax_dbell_s cnf71xx;
-};
-
-union cvmx_dpi_dmax_err_rsp_status {
-        uint64_t u64;
-        struct cvmx_dpi_dmax_err_rsp_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t status:6;
-#else
-                uint64_t status:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
-        struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
-        struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
-        struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
-        struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
-};
-
-union cvmx_dpi_dmax_ibuff_saddr {
-        uint64_t u64;
-        struct cvmx_dpi_dmax_ibuff_saddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t csize:14;
-                uint64_t reserved_41_47:7;
-                uint64_t idle:1;
-                uint64_t saddr:33;
-                uint64_t reserved_0_6:7;
-#else
-                uint64_t reserved_0_6:7;
-                uint64_t saddr:33;
-                uint64_t idle:1;
-                uint64_t reserved_41_47:7;
-                uint64_t csize:14;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t csize:14;
-                uint64_t reserved_41_47:7;
-                uint64_t idle:1;
-                uint64_t reserved_36_39:4;
-                uint64_t saddr:29;
-                uint64_t reserved_0_6:7;
-#else
-                uint64_t reserved_0_6:7;
-                uint64_t saddr:29;
-                uint64_t reserved_36_39:4;
-                uint64_t idle:1;
-                uint64_t reserved_41_47:7;
-                uint64_t csize:14;
-                uint64_t reserved_62_63:2;
-#endif
-        } cn61xx;
-        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
-        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
-        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
-        struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
-        struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
-        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
-};
-
-union cvmx_dpi_dmax_iflight {
-        uint64_t u64;
-        struct cvmx_dpi_dmax_iflight_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t cnt:3;
-#else
-                uint64_t cnt:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_dpi_dmax_iflight_s cn61xx;
-        struct cvmx_dpi_dmax_iflight_s cn66xx;
-        struct cvmx_dpi_dmax_iflight_s cn68xx;
-        struct cvmx_dpi_dmax_iflight_s cn68xxp1;
-        struct cvmx_dpi_dmax_iflight_s cnf71xx;
-};
-
-union cvmx_dpi_dmax_naddr {
-        uint64_t u64;
-        struct cvmx_dpi_dmax_naddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_40_63:24;
-                uint64_t addr:40;
-#else
-                uint64_t addr:40;
-                uint64_t reserved_40_63:24;
-#endif
-        } s;
-        struct cvmx_dpi_dmax_naddr_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_36_63:28;
-                uint64_t addr:36;
-#else
-                uint64_t addr:36;
-                uint64_t reserved_36_63:28;
-#endif
-        } cn61xx;
-        struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
-        struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
-        struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
-        struct cvmx_dpi_dmax_naddr_s cn68xx;
-        struct cvmx_dpi_dmax_naddr_s cn68xxp1;
-        struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx;
-};
-
-union cvmx_dpi_dmax_reqbnk0 {
-        uint64_t u64;
-        struct cvmx_dpi_dmax_reqbnk0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t state:64;
-#else
-                uint64_t state:64;
-#endif
-        } s;
-        struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
-        struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
-        struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
-        struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
-        struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
-        struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
-        struct cvmx_dpi_dmax_reqbnk0_s cnf71xx;
-};
-
-union cvmx_dpi_dmax_reqbnk1 {
-        uint64_t u64;
-        struct cvmx_dpi_dmax_reqbnk1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t state:64;
-#else
-                uint64_t state:64;
-#endif
-        } s;
-        struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
-        struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
-        struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
-        struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
-        struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
-        struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
-        struct cvmx_dpi_dmax_reqbnk1_s cnf71xx;
-};
-
-union cvmx_dpi_dma_control {
-        uint64_t u64;
-        struct cvmx_dpi_dma_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t dici_mode:1;
-                uint64_t pkt_en1:1;
-                uint64_t ffp_dis:1;
-                uint64_t commit_mode:1;
-                uint64_t pkt_hp:1;
-                uint64_t pkt_en:1;
-                uint64_t reserved_54_55:2;
-                uint64_t dma_enb:6;
-                uint64_t reserved_34_47:14;
-                uint64_t b0_lend:1;
-                uint64_t dwb_denb:1;
-                uint64_t dwb_ichk:9;
-                uint64_t fpa_que:3;
-                uint64_t o_add1:1;
-                uint64_t o_ro:1;
-                uint64_t o_ns:1;
-                uint64_t o_es:2;
-                uint64_t o_mode:1;
-                uint64_t reserved_0_13:14;
-#else
-                uint64_t reserved_0_13:14;
-                uint64_t o_mode:1;
-                uint64_t o_es:2;
-                uint64_t o_ns:1;
-                uint64_t o_ro:1;
-                uint64_t o_add1:1;
-                uint64_t fpa_que:3;
-                uint64_t dwb_ichk:9;
-                uint64_t dwb_denb:1;
-                uint64_t b0_lend:1;
-                uint64_t reserved_34_47:14;
-                uint64_t dma_enb:6;
-                uint64_t reserved_54_55:2;
-                uint64_t pkt_en:1;
-                uint64_t pkt_hp:1;
-                uint64_t commit_mode:1;
-                uint64_t ffp_dis:1;
-                uint64_t pkt_en1:1;
-                uint64_t dici_mode:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_dpi_dma_control_s cn61xx;
-        struct cvmx_dpi_dma_control_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t pkt_en1:1;
-                uint64_t ffp_dis:1;
-                uint64_t commit_mode:1;
-                uint64_t pkt_hp:1;
-                uint64_t pkt_en:1;
-                uint64_t reserved_54_55:2;
-                uint64_t dma_enb:6;
-                uint64_t reserved_34_47:14;
-                uint64_t b0_lend:1;
-                uint64_t dwb_denb:1;
-                uint64_t dwb_ichk:9;
-                uint64_t fpa_que:3;
-                uint64_t o_add1:1;
-                uint64_t o_ro:1;
-                uint64_t o_ns:1;
-                uint64_t o_es:2;
-                uint64_t o_mode:1;
-                uint64_t reserved_0_13:14;
-#else
-                uint64_t reserved_0_13:14;
-                uint64_t o_mode:1;
-                uint64_t o_es:2;
-                uint64_t o_ns:1;
-                uint64_t o_ro:1;
-                uint64_t o_add1:1;
-                uint64_t fpa_que:3;
-                uint64_t dwb_ichk:9;
-                uint64_t dwb_denb:1;
-                uint64_t b0_lend:1;
-                uint64_t reserved_34_47:14;
-                uint64_t dma_enb:6;
-                uint64_t reserved_54_55:2;
-                uint64_t pkt_en:1;
-                uint64_t pkt_hp:1;
-                uint64_t commit_mode:1;
-                uint64_t ffp_dis:1;
-                uint64_t pkt_en1:1;
-                uint64_t reserved_61_63:3;
-#endif
-        } cn63xx;
-        struct cvmx_dpi_dma_control_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_59_63:5;
-                uint64_t commit_mode:1;
-                uint64_t pkt_hp:1;
-                uint64_t pkt_en:1;
-                uint64_t reserved_54_55:2;
-                uint64_t dma_enb:6;
-                uint64_t reserved_34_47:14;
-                uint64_t b0_lend:1;
-                uint64_t dwb_denb:1;
-                uint64_t dwb_ichk:9;
-                uint64_t fpa_que:3;
-                uint64_t o_add1:1;
-                uint64_t o_ro:1;
-                uint64_t o_ns:1;
-                uint64_t o_es:2;
-                uint64_t o_mode:1;
-                uint64_t reserved_0_13:14;
-#else
-                uint64_t reserved_0_13:14;
-                uint64_t o_mode:1;
-                uint64_t o_es:2;
-                uint64_t o_ns:1;
-                uint64_t o_ro:1;
-                uint64_t o_add1:1;
-                uint64_t fpa_que:3;
-                uint64_t dwb_ichk:9;
-                uint64_t dwb_denb:1;
-                uint64_t b0_lend:1;
-                uint64_t reserved_34_47:14;
-                uint64_t dma_enb:6;
-                uint64_t reserved_54_55:2;
-                uint64_t pkt_en:1;
-                uint64_t pkt_hp:1;
-                uint64_t commit_mode:1;
-                uint64_t reserved_59_63:5;
-#endif
-        } cn63xxp1;
-        struct cvmx_dpi_dma_control_cn63xx cn66xx;
-        struct cvmx_dpi_dma_control_s cn68xx;
-        struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
-        struct cvmx_dpi_dma_control_s cnf71xx;
-};
-
-union cvmx_dpi_dma_engx_en {
-        uint64_t u64;
-        struct cvmx_dpi_dma_engx_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t qen:8;
-#else
-                uint64_t qen:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_dpi_dma_engx_en_s cn61xx;
-        struct cvmx_dpi_dma_engx_en_s cn63xx;
-        struct cvmx_dpi_dma_engx_en_s cn63xxp1;
-        struct cvmx_dpi_dma_engx_en_s cn66xx;
-        struct cvmx_dpi_dma_engx_en_s cn68xx;
-        struct cvmx_dpi_dma_engx_en_s cn68xxp1;
-        struct cvmx_dpi_dma_engx_en_s cnf71xx;
-};
-
-union cvmx_dpi_dma_ppx_cnt {
-        uint64_t u64;
-        struct cvmx_dpi_dma_ppx_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t cnt:16;
-#else
-                uint64_t cnt:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
-        struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
-        struct cvmx_dpi_dma_ppx_cnt_s cnf71xx;
-};
-
-union cvmx_dpi_engx_buf {
-        uint64_t u64;
-        struct cvmx_dpi_engx_buf_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_37_63:27;
-                uint64_t compblks:5;
-                uint64_t reserved_9_31:23;
-                uint64_t base:5;
-                uint64_t blks:4;
-#else
-                uint64_t blks:4;
-                uint64_t base:5;
-                uint64_t reserved_9_31:23;
-                uint64_t compblks:5;
-                uint64_t reserved_37_63:27;
-#endif
-        } s;
-        struct cvmx_dpi_engx_buf_s cn61xx;
-        struct cvmx_dpi_engx_buf_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t base:4;
-                uint64_t blks:4;
-#else
-                uint64_t blks:4;
-                uint64_t base:4;
-                uint64_t reserved_8_63:56;
-#endif
-        } cn63xx;
-        struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
-        struct cvmx_dpi_engx_buf_s cn66xx;
-        struct cvmx_dpi_engx_buf_s cn68xx;
-        struct cvmx_dpi_engx_buf_s cn68xxp1;
-        struct cvmx_dpi_engx_buf_s cnf71xx;
-};
-
-union cvmx_dpi_info_reg {
-        uint64_t u64;
-        struct cvmx_dpi_info_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t ffp:4;
-                uint64_t reserved_2_3:2;
-                uint64_t ncb:1;
-                uint64_t rsl:1;
-#else
-                uint64_t rsl:1;
-                uint64_t ncb:1;
-                uint64_t reserved_2_3:2;
-                uint64_t ffp:4;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_dpi_info_reg_s cn61xx;
-        struct cvmx_dpi_info_reg_s cn63xx;
-        struct cvmx_dpi_info_reg_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t ncb:1;
-                uint64_t rsl:1;
-#else
-                uint64_t rsl:1;
-                uint64_t ncb:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } cn63xxp1;
-        struct cvmx_dpi_info_reg_s cn66xx;
-        struct cvmx_dpi_info_reg_s cn68xx;
-        struct cvmx_dpi_info_reg_s cn68xxp1;
-        struct cvmx_dpi_info_reg_s cnf71xx;
-};
-
-union cvmx_dpi_int_en {
-        uint64_t u64;
-        struct cvmx_dpi_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t sprt3_rst:1;
-                uint64_t sprt2_rst:1;
-                uint64_t sprt1_rst:1;
-                uint64_t sprt0_rst:1;
-                uint64_t reserved_23_23:1;
-                uint64_t req_badfil:1;
-                uint64_t req_inull:1;
-                uint64_t req_anull:1;
-                uint64_t req_undflw:1;
-                uint64_t req_ovrflw:1;
-                uint64_t req_badlen:1;
-                uint64_t req_badadr:1;
-                uint64_t dmadbo:8;
-                uint64_t reserved_2_7:6;
-                uint64_t nfovr:1;
-                uint64_t nderr:1;
-#else
-                uint64_t nderr:1;
-                uint64_t nfovr:1;
-                uint64_t reserved_2_7:6;
-                uint64_t dmadbo:8;
-                uint64_t req_badadr:1;
-                uint64_t req_badlen:1;
-                uint64_t req_ovrflw:1;
-                uint64_t req_undflw:1;
-                uint64_t req_anull:1;
-                uint64_t req_inull:1;
-                uint64_t req_badfil:1;
-                uint64_t reserved_23_23:1;
-                uint64_t sprt0_rst:1;
-                uint64_t sprt1_rst:1;
-                uint64_t sprt2_rst:1;
-                uint64_t sprt3_rst:1;
-                uint64_t reserved_28_63:36;
-#endif
-        } s;
-        struct cvmx_dpi_int_en_s cn61xx;
-        struct cvmx_dpi_int_en_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_26_63:38;
-                uint64_t sprt1_rst:1;
-                uint64_t sprt0_rst:1;
-                uint64_t reserved_23_23:1;
-                uint64_t req_badfil:1;
-                uint64_t req_inull:1;
-                uint64_t req_anull:1;
-                uint64_t req_undflw:1;
-                uint64_t req_ovrflw:1;
-                uint64_t req_badlen:1;
-                uint64_t req_badadr:1;
-                uint64_t dmadbo:8;
-                uint64_t reserved_2_7:6;
-                uint64_t nfovr:1;
-                uint64_t nderr:1;
-#else
-                uint64_t nderr:1;
-                uint64_t nfovr:1;
-                uint64_t reserved_2_7:6;
-                uint64_t dmadbo:8;
-                uint64_t req_badadr:1;
-                uint64_t req_badlen:1;
-                uint64_t req_ovrflw:1;
-                uint64_t req_undflw:1;
-                uint64_t req_anull:1;
-                uint64_t req_inull:1;
-                uint64_t req_badfil:1;
-                uint64_t reserved_23_23:1;
-                uint64_t sprt0_rst:1;
-                uint64_t sprt1_rst:1;
-                uint64_t reserved_26_63:38;
-#endif
-        } cn63xx;
-        struct cvmx_dpi_int_en_cn63xx cn63xxp1;
-        struct cvmx_dpi_int_en_s cn66xx;
-        struct cvmx_dpi_int_en_cn63xx cn68xx;
-        struct cvmx_dpi_int_en_cn63xx cn68xxp1;
-        struct cvmx_dpi_int_en_s cnf71xx;
-};
-
-union cvmx_dpi_int_reg {
-        uint64_t u64;
-        struct cvmx_dpi_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t sprt3_rst:1;
-                uint64_t sprt2_rst:1;
-                uint64_t sprt1_rst:1;
-                uint64_t sprt0_rst:1;
-                uint64_t reserved_23_23:1;
-                uint64_t req_badfil:1;
-                uint64_t req_inull:1;
-                uint64_t req_anull:1;
-                uint64_t req_undflw:1;
-                uint64_t req_ovrflw:1;
-                uint64_t req_badlen:1;
-                uint64_t req_badadr:1;
-                uint64_t dmadbo:8;
-                uint64_t reserved_2_7:6;
-                uint64_t nfovr:1;
-                uint64_t nderr:1;
-#else
-                uint64_t nderr:1;
-                uint64_t nfovr:1;
-                uint64_t reserved_2_7:6;
-                uint64_t dmadbo:8;
-                uint64_t req_badadr:1;
-                uint64_t req_badlen:1;
-                uint64_t req_ovrflw:1;
-                uint64_t req_undflw:1;
-                uint64_t req_anull:1;
-                uint64_t req_inull:1;
-                uint64_t req_badfil:1;
-                uint64_t reserved_23_23:1;
-                uint64_t sprt0_rst:1;
-                uint64_t sprt1_rst:1;
-                uint64_t sprt2_rst:1;
-                uint64_t sprt3_rst:1;
-                uint64_t reserved_28_63:36;
-#endif
-        } s;
-        struct cvmx_dpi_int_reg_s cn61xx;
-        struct cvmx_dpi_int_reg_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_26_63:38;
-                uint64_t sprt1_rst:1;
-                uint64_t sprt0_rst:1;
-                uint64_t reserved_23_23:1;
-                uint64_t req_badfil:1;
-                uint64_t req_inull:1;
-                uint64_t req_anull:1;
-                uint64_t req_undflw:1;
-                uint64_t req_ovrflw:1;
-                uint64_t req_badlen:1;
-                uint64_t req_badadr:1;
-                uint64_t dmadbo:8;
-                uint64_t reserved_2_7:6;
-                uint64_t nfovr:1;
-                uint64_t nderr:1;
-#else
-                uint64_t nderr:1;
-                uint64_t nfovr:1;
-                uint64_t reserved_2_7:6;
-                uint64_t dmadbo:8;
-                uint64_t req_badadr:1;
-                uint64_t req_badlen:1;
-                uint64_t req_ovrflw:1;
-                uint64_t req_undflw:1;
-                uint64_t req_anull:1;
-                uint64_t req_inull:1;
-                uint64_t req_badfil:1;
-                uint64_t reserved_23_23:1;
-                uint64_t sprt0_rst:1;
-                uint64_t sprt1_rst:1;
-                uint64_t reserved_26_63:38;
-#endif
-        } cn63xx;
-        struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
-        struct cvmx_dpi_int_reg_s cn66xx;
-        struct cvmx_dpi_int_reg_cn63xx cn68xx;
-        struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
-        struct cvmx_dpi_int_reg_s cnf71xx;
-};
-
-union cvmx_dpi_ncbx_cfg {
-        uint64_t u64;
-        struct cvmx_dpi_ncbx_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t molr:6;
-#else
-                uint64_t molr:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_dpi_ncbx_cfg_s cn61xx;
-        struct cvmx_dpi_ncbx_cfg_s cn66xx;
-        struct cvmx_dpi_ncbx_cfg_s cn68xx;
-        struct cvmx_dpi_ncbx_cfg_s cnf71xx;
-};
-
-union cvmx_dpi_pint_info {
-        uint64_t u64;
-        struct cvmx_dpi_pint_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t iinfo:6;
-                uint64_t reserved_6_7:2;
-                uint64_t sinfo:6;
-#else
-                uint64_t sinfo:6;
-                uint64_t reserved_6_7:2;
-                uint64_t iinfo:6;
-                uint64_t reserved_14_63:50;
-#endif
-        } s;
-        struct cvmx_dpi_pint_info_s cn61xx;
-        struct cvmx_dpi_pint_info_s cn63xx;
-        struct cvmx_dpi_pint_info_s cn63xxp1;
-        struct cvmx_dpi_pint_info_s cn66xx;
-        struct cvmx_dpi_pint_info_s cn68xx;
-        struct cvmx_dpi_pint_info_s cn68xxp1;
-        struct cvmx_dpi_pint_info_s cnf71xx;
-};
-
-union cvmx_dpi_pkt_err_rsp {
-        uint64_t u64;
-        struct cvmx_dpi_pkt_err_rsp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t pkterr:1;
-#else
-                uint64_t pkterr:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_dpi_pkt_err_rsp_s cn61xx;
-        struct cvmx_dpi_pkt_err_rsp_s cn63xx;
-        struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
-        struct cvmx_dpi_pkt_err_rsp_s cn66xx;
-        struct cvmx_dpi_pkt_err_rsp_s cn68xx;
-        struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
-        struct cvmx_dpi_pkt_err_rsp_s cnf71xx;
-};
-
-union cvmx_dpi_req_err_rsp {
-        uint64_t u64;
-        struct cvmx_dpi_req_err_rsp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t qerr:8;
-#else
-                uint64_t qerr:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_dpi_req_err_rsp_s cn61xx;
-        struct cvmx_dpi_req_err_rsp_s cn63xx;
-        struct cvmx_dpi_req_err_rsp_s cn63xxp1;
-        struct cvmx_dpi_req_err_rsp_s cn66xx;
-        struct cvmx_dpi_req_err_rsp_s cn68xx;
-        struct cvmx_dpi_req_err_rsp_s cn68xxp1;
-        struct cvmx_dpi_req_err_rsp_s cnf71xx;
-};
-
-union cvmx_dpi_req_err_rsp_en {
-        uint64_t u64;
-        struct cvmx_dpi_req_err_rsp_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t en:8;
-#else
-                uint64_t en:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_dpi_req_err_rsp_en_s cn61xx;
-        struct cvmx_dpi_req_err_rsp_en_s cn63xx;
-        struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
-        struct cvmx_dpi_req_err_rsp_en_s cn66xx;
-        struct cvmx_dpi_req_err_rsp_en_s cn68xx;
-        struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
-        struct cvmx_dpi_req_err_rsp_en_s cnf71xx;
-};
-
-union cvmx_dpi_req_err_rst {
-        uint64_t u64;
-        struct cvmx_dpi_req_err_rst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t qerr:8;
-#else
-                uint64_t qerr:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_dpi_req_err_rst_s cn61xx;
-        struct cvmx_dpi_req_err_rst_s cn63xx;
-        struct cvmx_dpi_req_err_rst_s cn63xxp1;
-        struct cvmx_dpi_req_err_rst_s cn66xx;
-        struct cvmx_dpi_req_err_rst_s cn68xx;
-        struct cvmx_dpi_req_err_rst_s cn68xxp1;
-        struct cvmx_dpi_req_err_rst_s cnf71xx;
-};
-
-union cvmx_dpi_req_err_rst_en {
-        uint64_t u64;
-        struct cvmx_dpi_req_err_rst_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t en:8;
-#else
-                uint64_t en:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_dpi_req_err_rst_en_s cn61xx;
-        struct cvmx_dpi_req_err_rst_en_s cn63xx;
-        struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
-        struct cvmx_dpi_req_err_rst_en_s cn66xx;
-        struct cvmx_dpi_req_err_rst_en_s cn68xx;
-        struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
-        struct cvmx_dpi_req_err_rst_en_s cnf71xx;
-};
-
-union cvmx_dpi_req_err_skip_comp {
-        uint64_t u64;
-        struct cvmx_dpi_req_err_skip_comp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t en_rst:8;
-                uint64_t reserved_8_15:8;
-                uint64_t en_rsp:8;
-#else
-                uint64_t en_rsp:8;
-                uint64_t reserved_8_15:8;
-                uint64_t en_rst:8;
-                uint64_t reserved_24_63:40;
-#endif
-        } s;
-        struct cvmx_dpi_req_err_skip_comp_s cn61xx;
-        struct cvmx_dpi_req_err_skip_comp_s cn66xx;
-        struct cvmx_dpi_req_err_skip_comp_s cn68xx;
-        struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
-        struct cvmx_dpi_req_err_skip_comp_s cnf71xx;
-};
-
-union cvmx_dpi_req_gbl_en {
-        uint64_t u64;
-        struct cvmx_dpi_req_gbl_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t qen:8;
-#else
-                uint64_t qen:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_dpi_req_gbl_en_s cn61xx;
-        struct cvmx_dpi_req_gbl_en_s cn63xx;
-        struct cvmx_dpi_req_gbl_en_s cn63xxp1;
-        struct cvmx_dpi_req_gbl_en_s cn66xx;
-        struct cvmx_dpi_req_gbl_en_s cn68xx;
-        struct cvmx_dpi_req_gbl_en_s cn68xxp1;
-        struct cvmx_dpi_req_gbl_en_s cnf71xx;
-};
-
-union cvmx_dpi_sli_prtx_cfg {
-        uint64_t u64;
-        struct cvmx_dpi_sli_prtx_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t halt:1;
-                uint64_t qlm_cfg:4;
-                uint64_t reserved_17_19:3;
-                uint64_t rd_mode:1;
-                uint64_t reserved_14_15:2;
-                uint64_t molr:6;
-                uint64_t mps_lim:1;
-                uint64_t reserved_5_6:2;
-                uint64_t mps:1;
-                uint64_t mrrs_lim:1;
-                uint64_t reserved_2_2:1;
-                uint64_t mrrs:2;
-#else
-                uint64_t mrrs:2;
-                uint64_t reserved_2_2:1;
-                uint64_t mrrs_lim:1;
-                uint64_t mps:1;
-                uint64_t reserved_5_6:2;
-                uint64_t mps_lim:1;
-                uint64_t molr:6;
-                uint64_t reserved_14_15:2;
-                uint64_t rd_mode:1;
-                uint64_t reserved_17_19:3;
-                uint64_t qlm_cfg:4;
-                uint64_t halt:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
-        struct cvmx_dpi_sli_prtx_cfg_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t halt:1;
-                uint64_t reserved_21_23:3;
-                uint64_t qlm_cfg:1;
-                uint64_t reserved_17_19:3;
-                uint64_t rd_mode:1;
-                uint64_t reserved_14_15:2;
-                uint64_t molr:6;
-                uint64_t mps_lim:1;
-                uint64_t reserved_5_6:2;
-                uint64_t mps:1;
-                uint64_t mrrs_lim:1;
-                uint64_t reserved_2_2:1;
-                uint64_t mrrs:2;
-#else
-                uint64_t mrrs:2;
-                uint64_t reserved_2_2:1;
-                uint64_t mrrs_lim:1;
-                uint64_t mps:1;
-                uint64_t reserved_5_6:2;
-                uint64_t mps_lim:1;
-                uint64_t molr:6;
-                uint64_t reserved_14_15:2;
-                uint64_t rd_mode:1;
-                uint64_t reserved_17_19:3;
-                uint64_t qlm_cfg:1;
-                uint64_t reserved_21_23:3;
-                uint64_t halt:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } cn63xx;
-        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
-        struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
-        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
-        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
-        struct cvmx_dpi_sli_prtx_cfg_s cnf71xx;
-};
-
-union cvmx_dpi_sli_prtx_err {
-        uint64_t u64;
-        struct cvmx_dpi_sli_prtx_err_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t addr:61;
-                uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t addr:61;
-#endif
-        } s;
-        struct cvmx_dpi_sli_prtx_err_s cn61xx;
-        struct cvmx_dpi_sli_prtx_err_s cn63xx;
-        struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
-        struct cvmx_dpi_sli_prtx_err_s cn66xx;
-        struct cvmx_dpi_sli_prtx_err_s cn68xx;
-        struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
-        struct cvmx_dpi_sli_prtx_err_s cnf71xx;
-};
-
-union cvmx_dpi_sli_prtx_err_info {
-        uint64_t u64;
-        struct cvmx_dpi_sli_prtx_err_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t lock:1;
-                uint64_t reserved_5_7:3;
-                uint64_t type:1;
-                uint64_t reserved_3_3:1;
-                uint64_t reqq:3;
-#else
-                uint64_t reqq:3;
-                uint64_t reserved_3_3:1;
-                uint64_t type:1;
-                uint64_t reserved_5_7:3;
-                uint64_t lock:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
-        struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
-        struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
-        struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
-        struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
-        struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
-        struct cvmx_dpi_sli_prtx_err_info_s cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h
deleted file mode 100644
index a6939fc8ba1..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-fau.h
+++ /dev/null
@@ -1,597 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- * Interface to the hardware Fetch and Add Unit.
- */
-
-#ifndef __CVMX_FAU_H__
-#define __CVMX_FAU_H__
-
-/*
- * Octeon Fetch and Add Unit (FAU)
- */
-
-#define CVMX_FAU_LOAD_IO_ADDRESS    cvmx_build_io_address(0x1e, 0)
-#define CVMX_FAU_BITS_SCRADDR       63, 56
-#define CVMX_FAU_BITS_LEN           55, 48
-#define CVMX_FAU_BITS_INEVAL        35, 14
-#define CVMX_FAU_BITS_TAGWAIT       13, 13
-#define CVMX_FAU_BITS_NOADD         13, 13
-#define CVMX_FAU_BITS_SIZE          12, 11
-#define CVMX_FAU_BITS_REGISTER      10, 0
-
-typedef enum {
-        CVMX_FAU_OP_SIZE_8 = 0,
-        CVMX_FAU_OP_SIZE_16 = 1,
-        CVMX_FAU_OP_SIZE_32 = 2,
-        CVMX_FAU_OP_SIZE_64 = 3
-} cvmx_fau_op_size_t;
-
-/**
- * Tagwait return definition. If a timeout occurs, the error
- * bit will be set. Otherwise the value of the register before
- * the update will be returned.
- */
-typedef struct {
-        uint64_t error:1;
-        int64_t value:63;
-} cvmx_fau_tagwait64_t;
-
-/**
- * Tagwait return definition. If a timeout occurs, the error
- * bit will be set. Otherwise the value of the register before
- * the update will be returned.
- */
-typedef struct {
-        uint64_t error:1;
-        int32_t value:31;
-} cvmx_fau_tagwait32_t;
-
-/**
- * Tagwait return definition. If a timeout occurs, the error
- * bit will be set. Otherwise the value of the register before
- * the update will be returned.
- */
-typedef struct {
-        uint64_t error:1;
-        int16_t value:15;
-} cvmx_fau_tagwait16_t;
-
-/**
- * Tagwait return definition. If a timeout occurs, the error
- * bit will be set. Otherwise the value of the register before
- * the update will be returned.
- */
-typedef struct {
-        uint64_t error:1;
-        int8_t value:7;
-} cvmx_fau_tagwait8_t;
-
-/**
- * Asynchronous tagwait return definition. If a timeout occurs,
- * the error bit will be set. Otherwise the value of the
- * register before the update will be returned.
- */
-typedef union {
-        uint64_t u64;
-        struct {
-                uint64_t invalid:1;
-                uint64_t data:63;       /* unpredictable if invalid is set */
-        } s;
-} cvmx_fau_async_tagwait_result_t;
-
-/**
- * Builds a store I/O address for writing to the FAU
- *
- * @noadd:  0 = Store value is atomically added to the current value
- *               1 = Store value is atomically written over the current value
- * @reg:    FAU atomic register to access. 0 <= reg < 2048.
- *               - Step by 2 for 16 bit access.
- *               - Step by 4 for 32 bit access.
- *               - Step by 8 for 64 bit access.
- * Returns Address to store for atomic update
- */
-static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
-{
-        return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
-               cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
-               cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
-}
-
-/**
- * Builds a I/O address for accessing the FAU
- *
- * @tagwait: Should the atomic add wait for the current tag switch
- *                operation to complete.
- *                - 0 = Don't wait
- *                - 1 = Wait for tag switch to complete
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 2 for 16 bit access.
- *                - Step by 4 for 32 bit access.
- *                - Step by 8 for 64 bit access.
- * @value:   Signed value to add.
- *                Note: When performing 32 and 64 bit access, only the low
- *                22 bits are available.
- * Returns Address to read from for atomic update
- */
-static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
-                                                 int64_t value)
-{
-        return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
-               cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
-               cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
-               cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
-}
-
-/**
- * Perform an atomic 64 bit add
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 8 for 64 bit access.
- * @value:   Signed value to add.
- *                Note: Only the low 22 bits are available.
- * Returns Value of the register before the update
- */
-static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
-                                               int64_t value)
-{
-        return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
-}
-
-/**
- * Perform an atomic 32 bit add
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 4 for 32 bit access.
- * @value:   Signed value to add.
- *                Note: Only the low 22 bits are available.
- * Returns Value of the register before the update
- */
-static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
-                                               int32_t value)
-{
-        return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
-}
-
-/**
- * Perform an atomic 16 bit add
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 2 for 16 bit access.
- * @value:   Signed value to add.
- * Returns Value of the register before the update
- */
-static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
-                                               int16_t value)
-{
-        return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
-}
-
-/**
- * Perform an atomic 8 bit add
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- * @value:   Signed value to add.
- * Returns Value of the register before the update
- */
-static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
-{
-        return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
-}
-
-/**
- * Perform an atomic 64 bit add after the current tag switch
- * completes
- *
- * @reg:    FAU atomic register to access. 0 <= reg < 2048.
- *               - Step by 8 for 64 bit access.
- * @value:  Signed value to add.
- *               Note: Only the low 22 bits are available.
- * Returns If a timeout occurs, the error bit will be set. Otherwise
- *         the value of the register before the update will be
- *         returned
- */
-static inline cvmx_fau_tagwait64_t
-cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
-{
-        union {
-                uint64_t i64;
-                cvmx_fau_tagwait64_t t;
-        } result;
-        result.i64 =
-            cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
-        return result.t;
-}
-
-/**
- * Perform an atomic 32 bit add after the current tag switch
- * completes
- *
- * @reg:    FAU atomic register to access. 0 <= reg < 2048.
- *               - Step by 4 for 32 bit access.
- * @value:  Signed value to add.
- *               Note: Only the low 22 bits are available.
- * Returns If a timeout occurs, the error bit will be set. Otherwise
- *         the value of the register before the update will be
- *         returned
- */
-static inline cvmx_fau_tagwait32_t
-cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
-{
-        union {
-                uint64_t i32;
-                cvmx_fau_tagwait32_t t;
-        } result;
-        result.i32 =
-            cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
-        return result.t;
-}
-
-/**
- * Perform an atomic 16 bit add after the current tag switch
- * completes
- *
- * @reg:    FAU atomic register to access. 0 <= reg < 2048.
- *               - Step by 2 for 16 bit access.
- * @value:  Signed value to add.
- * Returns If a timeout occurs, the error bit will be set. Otherwise
- *         the value of the register before the update will be
- *         returned
- */
-static inline cvmx_fau_tagwait16_t
-cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
-{
-        union {
-                uint64_t i16;
-                cvmx_fau_tagwait16_t t;
-        } result;
-        result.i16 =
-            cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
-        return result.t;
-}
-
-/**
- * Perform an atomic 8 bit add after the current tag switch
- * completes
- *
- * @reg:    FAU atomic register to access. 0 <= reg < 2048.
- * @value:  Signed value to add.
- * Returns If a timeout occurs, the error bit will be set. Otherwise
- *         the value of the register before the update will be
- *         returned
- */
-static inline cvmx_fau_tagwait8_t
-cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
-{
-        union {
-                uint64_t i8;
-                cvmx_fau_tagwait8_t t;
-        } result;
-        result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
-        return result.t;
-}
-
-/**
- * Builds I/O data for async operations
- *
- * @scraddr: Scratch pad byte address to write to.  Must be 8 byte aligned
- * @value:   Signed value to add.
- *                Note: When performing 32 and 64 bit access, only the low
- *                22 bits are available.
- * @tagwait: Should the atomic add wait for the current tag switch
- *                operation to complete.
- *                - 0 = Don't wait
- *                - 1 = Wait for tag switch to complete
- * @size:    The size of the operation:
- *                - CVMX_FAU_OP_SIZE_8  (0) = 8 bits
- *                - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
- *                - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
- *                - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 2 for 16 bit access.
- *                - Step by 4 for 32 bit access.
- *                - Step by 8 for 64 bit access.
- * Returns Data to write using cvmx_send_single
- */
-static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value,
-                                              uint64_t tagwait,
-                                              cvmx_fau_op_size_t size,
-                                              uint64_t reg)
-{
-        return CVMX_FAU_LOAD_IO_ADDRESS |
-               cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) |
-               cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
-               cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
-               cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
-               cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
-               cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
-}
-
-/**
- * Perform an async atomic 64 bit add. The old value is
- * placed in the scratch memory at byte address scraddr.
- *
- * @scraddr: Scratch memory byte address to put response in.
- *                Must be 8 byte aligned.
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 8 for 64 bit access.
- * @value:   Signed value to add.
- *                Note: Only the low 22 bits are available.
- * Returns Placed in the scratch pad register
- */
-static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr,
-                                                  cvmx_fau_reg_64_t reg,
-                                                  int64_t value)
-{
-        cvmx_send_single(__cvmx_fau_iobdma_data
-                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
-}
-
-/**
- * Perform an async atomic 32 bit add. The old value is
- * placed in the scratch memory at byte address scraddr.
- *
- * @scraddr: Scratch memory byte address to put response in.
- *                Must be 8 byte aligned.
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 4 for 32 bit access.
- * @value:   Signed value to add.
- *                Note: Only the low 22 bits are available.
- * Returns Placed in the scratch pad register
- */
-static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
-                                                  cvmx_fau_reg_32_t reg,
-                                                  int32_t value)
-{
-        cvmx_send_single(__cvmx_fau_iobdma_data
-                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
-}
-
-/**
- * Perform an async atomic 16 bit add. The old value is
- * placed in the scratch memory at byte address scraddr.
- *
- * @scraddr: Scratch memory byte address to put response in.
- *                Must be 8 byte aligned.
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 2 for 16 bit access.
- * @value:   Signed value to add.
- * Returns Placed in the scratch pad register
- */
-static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr,
-                                                  cvmx_fau_reg_16_t reg,
-                                                  int16_t value)
-{
-        cvmx_send_single(__cvmx_fau_iobdma_data
-                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
-}
-
-/**
- * Perform an async atomic 8 bit add. The old value is
- * placed in the scratch memory at byte address scraddr.
- *
- * @scraddr: Scratch memory byte address to put response in.
- *                Must be 8 byte aligned.
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- * @value:   Signed value to add.
- * Returns Placed in the scratch pad register
- */
-static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr,
-                                                 cvmx_fau_reg_8_t reg,
-                                                 int8_t value)
-{
-        cvmx_send_single(__cvmx_fau_iobdma_data
-                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
-}
-
-/**
- * Perform an async atomic 64 bit add after the current tag
- * switch completes.
- *
- * @scraddr: Scratch memory byte address to put response in.  Must be
- *           8 byte aligned.  If a timeout occurs, the error bit (63)
- *           will be set. Otherwise the value of the register before
- *           the update will be returned
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 8 for 64 bit access.
- * @value:   Signed value to add.
- *                Note: Only the low 22 bits are available.
- * Returns Placed in the scratch pad register
- */
-static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr,
-                                                          cvmx_fau_reg_64_t reg,
-                                                          int64_t value)
-{
-        cvmx_send_single(__cvmx_fau_iobdma_data
-                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
-}
-
-/**
- * Perform an async atomic 32 bit add after the current tag
- * switch completes.
- *
- * @scraddr: Scratch memory byte address to put response in.  Must be
- *           8 byte aligned.  If a timeout occurs, the error bit (63)
- *           will be set. Otherwise the value of the register before
- *           the update will be returned
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 4 for 32 bit access.
- * @value:   Signed value to add.
- *                Note: Only the low 22 bits are available.
- * Returns Placed in the scratch pad register
- */
-static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr,
-                                                          cvmx_fau_reg_32_t reg,
-                                                          int32_t value)
-{
-        cvmx_send_single(__cvmx_fau_iobdma_data
-                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
-}
-
-/**
- * Perform an async atomic 16 bit add after the current tag
- * switch completes.
- *
- * @scraddr: Scratch memory byte address to put response in.  Must be
- *           8 byte aligned.  If a timeout occurs, the error bit (63)
- *           will be set. Otherwise the value of the register before
- *           the update will be returned
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 2 for 16 bit access.
- * @value:   Signed value to add.
- *
- * Returns Placed in the scratch pad register
- */
-static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr,
-                                                          cvmx_fau_reg_16_t reg,
-                                                          int16_t value)
-{
-        cvmx_send_single(__cvmx_fau_iobdma_data
-                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
-}
-
-/**
- * Perform an async atomic 8 bit add after the current tag
- * switch completes.
- *
- * @scraddr: Scratch memory byte address to put response in.  Must be
- *           8 byte aligned.  If a timeout occurs, the error bit (63)
- *           will be set. Otherwise the value of the register before
- *           the update will be returned
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- * @value:   Signed value to add.
- *
- * Returns Placed in the scratch pad register
- */
-static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr,
-                                                         cvmx_fau_reg_8_t reg,
-                                                         int8_t value)
-{
-        cvmx_send_single(__cvmx_fau_iobdma_data
-                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
-}
-
-/**
- * Perform an atomic 64 bit add
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 8 for 64 bit access.
- * @value:   Signed value to add.
- */
-static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
-{
-        cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
-}
-
-/**
- * Perform an atomic 32 bit add
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 4 for 32 bit access.
- * @value:   Signed value to add.
- */
-static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
-{
-        cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
-}
-
-/**
- * Perform an atomic 16 bit add
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 2 for 16 bit access.
- * @value:   Signed value to add.
- */
-static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
-{
-        cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
-}
-
-/**
- * Perform an atomic 8 bit add
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- * @value:   Signed value to add.
- */
-static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
-{
-        cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
-}
-
-/**
- * Perform an atomic 64 bit write
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 8 for 64 bit access.
- * @value:   Signed value to write.
- */
-static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
-{
-        cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
-}
-
-/**
- * Perform an atomic 32 bit write
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 4 for 32 bit access.
- * @value:   Signed value to write.
- */
-static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
-{
-        cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
-}
-
-/**
- * Perform an atomic 16 bit write
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- *                - Step by 2 for 16 bit access.
- * @value:   Signed value to write.
- */
-static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
-{
-        cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
-}
-
-/**
- * Perform an atomic 8 bit write
- *
- * @reg:     FAU atomic register to access. 0 <= reg < 2048.
- * @value:   Signed value to write.
- */
-static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
-{
-        cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
-}
-
-#endif /* __CVMX_FAU_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
deleted file mode 100644
index 1d79e3c7040..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
+++ /dev/null
@@ -1,1498 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_FPA_DEFS_H__
-#define __CVMX_FPA_DEFS_H__
-
-#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull))
-#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull))
-#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull))
-#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull))
-#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull))
-#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
-#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
-#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
-#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
-#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
-#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
-#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
-#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull))
-#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull))
-#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1)
-#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1)
-#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull))
-#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull))
-#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull))
-#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8)
-#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8)
-#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8)
-#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
-#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
-#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
-#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
-#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
-#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
-#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
-#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
-#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull))
-#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8)
-#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8)
-#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull))
-#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull))
-#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull))
-#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull))
-#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull))
-
-union cvmx_fpa_addr_range_error {
-        uint64_t u64;
-        struct cvmx_fpa_addr_range_error_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_38_63:26;
-                uint64_t pool:5;
-                uint64_t addr:33;
-#else
-                uint64_t addr:33;
-                uint64_t pool:5;
-                uint64_t reserved_38_63:26;
-#endif
-        } s;
-        struct cvmx_fpa_addr_range_error_s cn61xx;
-        struct cvmx_fpa_addr_range_error_s cn66xx;
-        struct cvmx_fpa_addr_range_error_s cn68xx;
-        struct cvmx_fpa_addr_range_error_s cn68xxp1;
-        struct cvmx_fpa_addr_range_error_s cnf71xx;
-};
-
-union cvmx_fpa_bist_status {
-        uint64_t u64;
-        struct cvmx_fpa_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t frd:1;
-                uint64_t fpf0:1;
-                uint64_t fpf1:1;
-                uint64_t ffr:1;
-                uint64_t fdr:1;
-#else
-                uint64_t fdr:1;
-                uint64_t ffr:1;
-                uint64_t fpf1:1;
-                uint64_t fpf0:1;
-                uint64_t frd:1;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_fpa_bist_status_s cn30xx;
-        struct cvmx_fpa_bist_status_s cn31xx;
-        struct cvmx_fpa_bist_status_s cn38xx;
-        struct cvmx_fpa_bist_status_s cn38xxp2;
-        struct cvmx_fpa_bist_status_s cn50xx;
-        struct cvmx_fpa_bist_status_s cn52xx;
-        struct cvmx_fpa_bist_status_s cn52xxp1;
-        struct cvmx_fpa_bist_status_s cn56xx;
-        struct cvmx_fpa_bist_status_s cn56xxp1;
-        struct cvmx_fpa_bist_status_s cn58xx;
-        struct cvmx_fpa_bist_status_s cn58xxp1;
-        struct cvmx_fpa_bist_status_s cn61xx;
-        struct cvmx_fpa_bist_status_s cn63xx;
-        struct cvmx_fpa_bist_status_s cn63xxp1;
-        struct cvmx_fpa_bist_status_s cn66xx;
-        struct cvmx_fpa_bist_status_s cn68xx;
-        struct cvmx_fpa_bist_status_s cn68xxp1;
-        struct cvmx_fpa_bist_status_s cnf71xx;
-};
-
-union cvmx_fpa_ctl_status {
-        uint64_t u64;
-        struct cvmx_fpa_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_21_63:43;
-                uint64_t free_en:1;
-                uint64_t ret_off:1;
-                uint64_t req_off:1;
-                uint64_t reset:1;
-                uint64_t use_ldt:1;
-                uint64_t use_stt:1;
-                uint64_t enb:1;
-                uint64_t mem1_err:7;
-                uint64_t mem0_err:7;
-#else
-                uint64_t mem0_err:7;
-                uint64_t mem1_err:7;
-                uint64_t enb:1;
-                uint64_t use_stt:1;
-                uint64_t use_ldt:1;
-                uint64_t reset:1;
-                uint64_t req_off:1;
-                uint64_t ret_off:1;
-                uint64_t free_en:1;
-                uint64_t reserved_21_63:43;
-#endif
-        } s;
-        struct cvmx_fpa_ctl_status_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_18_63:46;
-                uint64_t reset:1;
-                uint64_t use_ldt:1;
-                uint64_t use_stt:1;
-                uint64_t enb:1;
-                uint64_t mem1_err:7;
-                uint64_t mem0_err:7;
-#else
-                uint64_t mem0_err:7;
-                uint64_t mem1_err:7;
-                uint64_t enb:1;
-                uint64_t use_stt:1;
-                uint64_t use_ldt:1;
-                uint64_t reset:1;
-                uint64_t reserved_18_63:46;
-#endif
-        } cn30xx;
-        struct cvmx_fpa_ctl_status_cn30xx cn31xx;
-        struct cvmx_fpa_ctl_status_cn30xx cn38xx;
-        struct cvmx_fpa_ctl_status_cn30xx cn38xxp2;
-        struct cvmx_fpa_ctl_status_cn30xx cn50xx;
-        struct cvmx_fpa_ctl_status_cn30xx cn52xx;
-        struct cvmx_fpa_ctl_status_cn30xx cn52xxp1;
-        struct cvmx_fpa_ctl_status_cn30xx cn56xx;
-        struct cvmx_fpa_ctl_status_cn30xx cn56xxp1;
-        struct cvmx_fpa_ctl_status_cn30xx cn58xx;
-        struct cvmx_fpa_ctl_status_cn30xx cn58xxp1;
-        struct cvmx_fpa_ctl_status_s cn61xx;
-        struct cvmx_fpa_ctl_status_s cn63xx;
-        struct cvmx_fpa_ctl_status_cn30xx cn63xxp1;
-        struct cvmx_fpa_ctl_status_s cn66xx;
-        struct cvmx_fpa_ctl_status_s cn68xx;
-        struct cvmx_fpa_ctl_status_s cn68xxp1;
-        struct cvmx_fpa_ctl_status_s cnf71xx;
-};
-
-union cvmx_fpa_fpfx_marks {
-        uint64_t u64;
-        struct cvmx_fpa_fpfx_marks_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t fpf_wr:11;
-                uint64_t fpf_rd:11;
-#else
-                uint64_t fpf_rd:11;
-                uint64_t fpf_wr:11;
-                uint64_t reserved_22_63:42;
-#endif
-        } s;
-        struct cvmx_fpa_fpfx_marks_s cn38xx;
-        struct cvmx_fpa_fpfx_marks_s cn38xxp2;
-        struct cvmx_fpa_fpfx_marks_s cn56xx;
-        struct cvmx_fpa_fpfx_marks_s cn56xxp1;
-        struct cvmx_fpa_fpfx_marks_s cn58xx;
-        struct cvmx_fpa_fpfx_marks_s cn58xxp1;
-        struct cvmx_fpa_fpfx_marks_s cn61xx;
-        struct cvmx_fpa_fpfx_marks_s cn63xx;
-        struct cvmx_fpa_fpfx_marks_s cn63xxp1;
-        struct cvmx_fpa_fpfx_marks_s cn66xx;
-        struct cvmx_fpa_fpfx_marks_s cn68xx;
-        struct cvmx_fpa_fpfx_marks_s cn68xxp1;
-        struct cvmx_fpa_fpfx_marks_s cnf71xx;
-};
-
-union cvmx_fpa_fpfx_size {
-        uint64_t u64;
-        struct cvmx_fpa_fpfx_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t fpf_siz:11;
-#else
-                uint64_t fpf_siz:11;
-                uint64_t reserved_11_63:53;
-#endif
-        } s;
-        struct cvmx_fpa_fpfx_size_s cn38xx;
-        struct cvmx_fpa_fpfx_size_s cn38xxp2;
-        struct cvmx_fpa_fpfx_size_s cn56xx;
-        struct cvmx_fpa_fpfx_size_s cn56xxp1;
-        struct cvmx_fpa_fpfx_size_s cn58xx;
-        struct cvmx_fpa_fpfx_size_s cn58xxp1;
-        struct cvmx_fpa_fpfx_size_s cn61xx;
-        struct cvmx_fpa_fpfx_size_s cn63xx;
-        struct cvmx_fpa_fpfx_size_s cn63xxp1;
-        struct cvmx_fpa_fpfx_size_s cn66xx;
-        struct cvmx_fpa_fpfx_size_s cn68xx;
-        struct cvmx_fpa_fpfx_size_s cn68xxp1;
-        struct cvmx_fpa_fpfx_size_s cnf71xx;
-};
-
-union cvmx_fpa_fpf0_marks {
-        uint64_t u64;
-        struct cvmx_fpa_fpf0_marks_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t fpf_wr:12;
-                uint64_t fpf_rd:12;
-#else
-                uint64_t fpf_rd:12;
-                uint64_t fpf_wr:12;
-                uint64_t reserved_24_63:40;
-#endif
-        } s;
-        struct cvmx_fpa_fpf0_marks_s cn38xx;
-        struct cvmx_fpa_fpf0_marks_s cn38xxp2;
-        struct cvmx_fpa_fpf0_marks_s cn56xx;
-        struct cvmx_fpa_fpf0_marks_s cn56xxp1;
-        struct cvmx_fpa_fpf0_marks_s cn58xx;
-        struct cvmx_fpa_fpf0_marks_s cn58xxp1;
-        struct cvmx_fpa_fpf0_marks_s cn61xx;
-        struct cvmx_fpa_fpf0_marks_s cn63xx;
-        struct cvmx_fpa_fpf0_marks_s cn63xxp1;
-        struct cvmx_fpa_fpf0_marks_s cn66xx;
-        struct cvmx_fpa_fpf0_marks_s cn68xx;
-        struct cvmx_fpa_fpf0_marks_s cn68xxp1;
-        struct cvmx_fpa_fpf0_marks_s cnf71xx;
-};
-
-union cvmx_fpa_fpf0_size {
-        uint64_t u64;
-        struct cvmx_fpa_fpf0_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t fpf_siz:12;
-#else
-                uint64_t fpf_siz:12;
-                uint64_t reserved_12_63:52;
-#endif
-        } s;
-        struct cvmx_fpa_fpf0_size_s cn38xx;
-        struct cvmx_fpa_fpf0_size_s cn38xxp2;
-        struct cvmx_fpa_fpf0_size_s cn56xx;
-        struct cvmx_fpa_fpf0_size_s cn56xxp1;
-        struct cvmx_fpa_fpf0_size_s cn58xx;
-        struct cvmx_fpa_fpf0_size_s cn58xxp1;
-        struct cvmx_fpa_fpf0_size_s cn61xx;
-        struct cvmx_fpa_fpf0_size_s cn63xx;
-        struct cvmx_fpa_fpf0_size_s cn63xxp1;
-        struct cvmx_fpa_fpf0_size_s cn66xx;
-        struct cvmx_fpa_fpf0_size_s cn68xx;
-        struct cvmx_fpa_fpf0_size_s cn68xxp1;
-        struct cvmx_fpa_fpf0_size_s cnf71xx;
-};
-
-union cvmx_fpa_fpf8_marks {
-        uint64_t u64;
-        struct cvmx_fpa_fpf8_marks_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t fpf_wr:11;
-                uint64_t fpf_rd:11;
-#else
-                uint64_t fpf_rd:11;
-                uint64_t fpf_wr:11;
-                uint64_t reserved_22_63:42;
-#endif
-        } s;
-        struct cvmx_fpa_fpf8_marks_s cn68xx;
-        struct cvmx_fpa_fpf8_marks_s cn68xxp1;
-};
-
-union cvmx_fpa_fpf8_size {
-        uint64_t u64;
-        struct cvmx_fpa_fpf8_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t fpf_siz:12;
-#else
-                uint64_t fpf_siz:12;
-                uint64_t reserved_12_63:52;
-#endif
-        } s;
-        struct cvmx_fpa_fpf8_size_s cn68xx;
-        struct cvmx_fpa_fpf8_size_s cn68xxp1;
-};
-
-union cvmx_fpa_int_enb {
-        uint64_t u64;
-        struct cvmx_fpa_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_50_63:14;
-                uint64_t paddr_e:1;
-                uint64_t reserved_44_48:5;
-                uint64_t free7:1;
-                uint64_t free6:1;
-                uint64_t free5:1;
-                uint64_t free4:1;
-                uint64_t free3:1;
-                uint64_t free2:1;
-                uint64_t free1:1;
-                uint64_t free0:1;
-                uint64_t pool7th:1;
-                uint64_t pool6th:1;
-                uint64_t pool5th:1;
-                uint64_t pool4th:1;
-                uint64_t pool3th:1;
-                uint64_t pool2th:1;
-                uint64_t pool1th:1;
-                uint64_t pool0th:1;
-                uint64_t q7_perr:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_und:1;
-                uint64_t q6_perr:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_und:1;
-                uint64_t q5_perr:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_und:1;
-                uint64_t q4_perr:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_und:1;
-                uint64_t q3_perr:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_und:1;
-                uint64_t q2_perr:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_und:1;
-                uint64_t q1_perr:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_und:1;
-                uint64_t q0_perr:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_und:1;
-                uint64_t fed1_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed0_sbe:1;
-#else
-                uint64_t fed0_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed1_dbe:1;
-                uint64_t q0_und:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_perr:1;
-                uint64_t q1_und:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_perr:1;
-                uint64_t q2_und:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_perr:1;
-                uint64_t q3_und:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_perr:1;
-                uint64_t q4_und:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_perr:1;
-                uint64_t q5_und:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_perr:1;
-                uint64_t q6_und:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_perr:1;
-                uint64_t q7_und:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_perr:1;
-                uint64_t pool0th:1;
-                uint64_t pool1th:1;
-                uint64_t pool2th:1;
-                uint64_t pool3th:1;
-                uint64_t pool4th:1;
-                uint64_t pool5th:1;
-                uint64_t pool6th:1;
-                uint64_t pool7th:1;
-                uint64_t free0:1;
-                uint64_t free1:1;
-                uint64_t free2:1;
-                uint64_t free3:1;
-                uint64_t free4:1;
-                uint64_t free5:1;
-                uint64_t free6:1;
-                uint64_t free7:1;
-                uint64_t reserved_44_48:5;
-                uint64_t paddr_e:1;
-                uint64_t reserved_50_63:14;
-#endif
-        } s;
-        struct cvmx_fpa_int_enb_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t q7_perr:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_und:1;
-                uint64_t q6_perr:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_und:1;
-                uint64_t q5_perr:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_und:1;
-                uint64_t q4_perr:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_und:1;
-                uint64_t q3_perr:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_und:1;
-                uint64_t q2_perr:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_und:1;
-                uint64_t q1_perr:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_und:1;
-                uint64_t q0_perr:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_und:1;
-                uint64_t fed1_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed0_sbe:1;
-#else
-                uint64_t fed0_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed1_dbe:1;
-                uint64_t q0_und:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_perr:1;
-                uint64_t q1_und:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_perr:1;
-                uint64_t q2_und:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_perr:1;
-                uint64_t q3_und:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_perr:1;
-                uint64_t q4_und:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_perr:1;
-                uint64_t q5_und:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_perr:1;
-                uint64_t q6_und:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_perr:1;
-                uint64_t q7_und:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_perr:1;
-                uint64_t reserved_28_63:36;
-#endif
-        } cn30xx;
-        struct cvmx_fpa_int_enb_cn30xx cn31xx;
-        struct cvmx_fpa_int_enb_cn30xx cn38xx;
-        struct cvmx_fpa_int_enb_cn30xx cn38xxp2;
-        struct cvmx_fpa_int_enb_cn30xx cn50xx;
-        struct cvmx_fpa_int_enb_cn30xx cn52xx;
-        struct cvmx_fpa_int_enb_cn30xx cn52xxp1;
-        struct cvmx_fpa_int_enb_cn30xx cn56xx;
-        struct cvmx_fpa_int_enb_cn30xx cn56xxp1;
-        struct cvmx_fpa_int_enb_cn30xx cn58xx;
-        struct cvmx_fpa_int_enb_cn30xx cn58xxp1;
-        struct cvmx_fpa_int_enb_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_50_63:14;
-                uint64_t paddr_e:1;
-                uint64_t res_44:5;
-                uint64_t free7:1;
-                uint64_t free6:1;
-                uint64_t free5:1;
-                uint64_t free4:1;
-                uint64_t free3:1;
-                uint64_t free2:1;
-                uint64_t free1:1;
-                uint64_t free0:1;
-                uint64_t pool7th:1;
-                uint64_t pool6th:1;
-                uint64_t pool5th:1;
-                uint64_t pool4th:1;
-                uint64_t pool3th:1;
-                uint64_t pool2th:1;
-                uint64_t pool1th:1;
-                uint64_t pool0th:1;
-                uint64_t q7_perr:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_und:1;
-                uint64_t q6_perr:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_und:1;
-                uint64_t q5_perr:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_und:1;
-                uint64_t q4_perr:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_und:1;
-                uint64_t q3_perr:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_und:1;
-                uint64_t q2_perr:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_und:1;
-                uint64_t q1_perr:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_und:1;
-                uint64_t q0_perr:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_und:1;
-                uint64_t fed1_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed0_sbe:1;
-#else
-                uint64_t fed0_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed1_dbe:1;
-                uint64_t q0_und:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_perr:1;
-                uint64_t q1_und:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_perr:1;
-                uint64_t q2_und:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_perr:1;
-                uint64_t q3_und:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_perr:1;
-                uint64_t q4_und:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_perr:1;
-                uint64_t q5_und:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_perr:1;
-                uint64_t q6_und:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_perr:1;
-                uint64_t q7_und:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_perr:1;
-                uint64_t pool0th:1;
-                uint64_t pool1th:1;
-                uint64_t pool2th:1;
-                uint64_t pool3th:1;
-                uint64_t pool4th:1;
-                uint64_t pool5th:1;
-                uint64_t pool6th:1;
-                uint64_t pool7th:1;
-                uint64_t free0:1;
-                uint64_t free1:1;
-                uint64_t free2:1;
-                uint64_t free3:1;
-                uint64_t free4:1;
-                uint64_t free5:1;
-                uint64_t free6:1;
-                uint64_t free7:1;
-                uint64_t res_44:5;
-                uint64_t paddr_e:1;
-                uint64_t reserved_50_63:14;
-#endif
-        } cn61xx;
-        struct cvmx_fpa_int_enb_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t free7:1;
-                uint64_t free6:1;
-                uint64_t free5:1;
-                uint64_t free4:1;
-                uint64_t free3:1;
-                uint64_t free2:1;
-                uint64_t free1:1;
-                uint64_t free0:1;
-                uint64_t pool7th:1;
-                uint64_t pool6th:1;
-                uint64_t pool5th:1;
-                uint64_t pool4th:1;
-                uint64_t pool3th:1;
-                uint64_t pool2th:1;
-                uint64_t pool1th:1;
-                uint64_t pool0th:1;
-                uint64_t q7_perr:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_und:1;
-                uint64_t q6_perr:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_und:1;
-                uint64_t q5_perr:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_und:1;
-                uint64_t q4_perr:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_und:1;
-                uint64_t q3_perr:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_und:1;
-                uint64_t q2_perr:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_und:1;
-                uint64_t q1_perr:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_und:1;
-                uint64_t q0_perr:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_und:1;
-                uint64_t fed1_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed0_sbe:1;
-#else
-                uint64_t fed0_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed1_dbe:1;
-                uint64_t q0_und:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_perr:1;
-                uint64_t q1_und:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_perr:1;
-                uint64_t q2_und:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_perr:1;
-                uint64_t q3_und:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_perr:1;
-                uint64_t q4_und:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_perr:1;
-                uint64_t q5_und:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_perr:1;
-                uint64_t q6_und:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_perr:1;
-                uint64_t q7_und:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_perr:1;
-                uint64_t pool0th:1;
-                uint64_t pool1th:1;
-                uint64_t pool2th:1;
-                uint64_t pool3th:1;
-                uint64_t pool4th:1;
-                uint64_t pool5th:1;
-                uint64_t pool6th:1;
-                uint64_t pool7th:1;
-                uint64_t free0:1;
-                uint64_t free1:1;
-                uint64_t free2:1;
-                uint64_t free3:1;
-                uint64_t free4:1;
-                uint64_t free5:1;
-                uint64_t free6:1;
-                uint64_t free7:1;
-                uint64_t reserved_44_63:20;
-#endif
-        } cn63xx;
-        struct cvmx_fpa_int_enb_cn30xx cn63xxp1;
-        struct cvmx_fpa_int_enb_cn61xx cn66xx;
-        struct cvmx_fpa_int_enb_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_50_63:14;
-                uint64_t paddr_e:1;
-                uint64_t pool8th:1;
-                uint64_t q8_perr:1;
-                uint64_t q8_coff:1;
-                uint64_t q8_und:1;
-                uint64_t free8:1;
-                uint64_t free7:1;
-                uint64_t free6:1;
-                uint64_t free5:1;
-                uint64_t free4:1;
-                uint64_t free3:1;
-                uint64_t free2:1;
-                uint64_t free1:1;
-                uint64_t free0:1;
-                uint64_t pool7th:1;
-                uint64_t pool6th:1;
-                uint64_t pool5th:1;
-                uint64_t pool4th:1;
-                uint64_t pool3th:1;
-                uint64_t pool2th:1;
-                uint64_t pool1th:1;
-                uint64_t pool0th:1;
-                uint64_t q7_perr:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_und:1;
-                uint64_t q6_perr:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_und:1;
-                uint64_t q5_perr:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_und:1;
-                uint64_t q4_perr:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_und:1;
-                uint64_t q3_perr:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_und:1;
-                uint64_t q2_perr:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_und:1;
-                uint64_t q1_perr:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_und:1;
-                uint64_t q0_perr:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_und:1;
-                uint64_t fed1_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed0_sbe:1;
-#else
-                uint64_t fed0_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed1_dbe:1;
-                uint64_t q0_und:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_perr:1;
-                uint64_t q1_und:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_perr:1;
-                uint64_t q2_und:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_perr:1;
-                uint64_t q3_und:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_perr:1;
-                uint64_t q4_und:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_perr:1;
-                uint64_t q5_und:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_perr:1;
-                uint64_t q6_und:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_perr:1;
-                uint64_t q7_und:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_perr:1;
-                uint64_t pool0th:1;
-                uint64_t pool1th:1;
-                uint64_t pool2th:1;
-                uint64_t pool3th:1;
-                uint64_t pool4th:1;
-                uint64_t pool5th:1;
-                uint64_t pool6th:1;
-                uint64_t pool7th:1;
-                uint64_t free0:1;
-                uint64_t free1:1;
-                uint64_t free2:1;
-                uint64_t free3:1;
-                uint64_t free4:1;
-                uint64_t free5:1;
-                uint64_t free6:1;
-                uint64_t free7:1;
-                uint64_t free8:1;
-                uint64_t q8_und:1;
-                uint64_t q8_coff:1;
-                uint64_t q8_perr:1;
-                uint64_t pool8th:1;
-                uint64_t paddr_e:1;
-                uint64_t reserved_50_63:14;
-#endif
-        } cn68xx;
-        struct cvmx_fpa_int_enb_cn68xx cn68xxp1;
-        struct cvmx_fpa_int_enb_cn61xx cnf71xx;
-};
-
-union cvmx_fpa_int_sum {
-        uint64_t u64;
-        struct cvmx_fpa_int_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_50_63:14;
-                uint64_t paddr_e:1;
-                uint64_t pool8th:1;
-                uint64_t q8_perr:1;
-                uint64_t q8_coff:1;
-                uint64_t q8_und:1;
-                uint64_t free8:1;
-                uint64_t free7:1;
-                uint64_t free6:1;
-                uint64_t free5:1;
-                uint64_t free4:1;
-                uint64_t free3:1;
-                uint64_t free2:1;
-                uint64_t free1:1;
-                uint64_t free0:1;
-                uint64_t pool7th:1;
-                uint64_t pool6th:1;
-                uint64_t pool5th:1;
-                uint64_t pool4th:1;
-                uint64_t pool3th:1;
-                uint64_t pool2th:1;
-                uint64_t pool1th:1;
-                uint64_t pool0th:1;
-                uint64_t q7_perr:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_und:1;
-                uint64_t q6_perr:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_und:1;
-                uint64_t q5_perr:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_und:1;
-                uint64_t q4_perr:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_und:1;
-                uint64_t q3_perr:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_und:1;
-                uint64_t q2_perr:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_und:1;
-                uint64_t q1_perr:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_und:1;
-                uint64_t q0_perr:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_und:1;
-                uint64_t fed1_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed0_sbe:1;
-#else
-                uint64_t fed0_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed1_dbe:1;
-                uint64_t q0_und:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_perr:1;
-                uint64_t q1_und:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_perr:1;
-                uint64_t q2_und:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_perr:1;
-                uint64_t q3_und:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_perr:1;
-                uint64_t q4_und:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_perr:1;
-                uint64_t q5_und:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_perr:1;
-                uint64_t q6_und:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_perr:1;
-                uint64_t q7_und:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_perr:1;
-                uint64_t pool0th:1;
-                uint64_t pool1th:1;
-                uint64_t pool2th:1;
-                uint64_t pool3th:1;
-                uint64_t pool4th:1;
-                uint64_t pool5th:1;
-                uint64_t pool6th:1;
-                uint64_t pool7th:1;
-                uint64_t free0:1;
-                uint64_t free1:1;
-                uint64_t free2:1;
-                uint64_t free3:1;
-                uint64_t free4:1;
-                uint64_t free5:1;
-                uint64_t free6:1;
-                uint64_t free7:1;
-                uint64_t free8:1;
-                uint64_t q8_und:1;
-                uint64_t q8_coff:1;
-                uint64_t q8_perr:1;
-                uint64_t pool8th:1;
-                uint64_t paddr_e:1;
-                uint64_t reserved_50_63:14;
-#endif
-        } s;
-        struct cvmx_fpa_int_sum_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t q7_perr:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_und:1;
-                uint64_t q6_perr:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_und:1;
-                uint64_t q5_perr:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_und:1;
-                uint64_t q4_perr:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_und:1;
-                uint64_t q3_perr:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_und:1;
-                uint64_t q2_perr:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_und:1;
-                uint64_t q1_perr:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_und:1;
-                uint64_t q0_perr:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_und:1;
-                uint64_t fed1_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed0_sbe:1;
-#else
-                uint64_t fed0_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed1_dbe:1;
-                uint64_t q0_und:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_perr:1;
-                uint64_t q1_und:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_perr:1;
-                uint64_t q2_und:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_perr:1;
-                uint64_t q3_und:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_perr:1;
-                uint64_t q4_und:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_perr:1;
-                uint64_t q5_und:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_perr:1;
-                uint64_t q6_und:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_perr:1;
-                uint64_t q7_und:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_perr:1;
-                uint64_t reserved_28_63:36;
-#endif
-        } cn30xx;
-        struct cvmx_fpa_int_sum_cn30xx cn31xx;
-        struct cvmx_fpa_int_sum_cn30xx cn38xx;
-        struct cvmx_fpa_int_sum_cn30xx cn38xxp2;
-        struct cvmx_fpa_int_sum_cn30xx cn50xx;
-        struct cvmx_fpa_int_sum_cn30xx cn52xx;
-        struct cvmx_fpa_int_sum_cn30xx cn52xxp1;
-        struct cvmx_fpa_int_sum_cn30xx cn56xx;
-        struct cvmx_fpa_int_sum_cn30xx cn56xxp1;
-        struct cvmx_fpa_int_sum_cn30xx cn58xx;
-        struct cvmx_fpa_int_sum_cn30xx cn58xxp1;
-        struct cvmx_fpa_int_sum_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_50_63:14;
-                uint64_t paddr_e:1;
-                uint64_t reserved_44_48:5;
-                uint64_t free7:1;
-                uint64_t free6:1;
-                uint64_t free5:1;
-                uint64_t free4:1;
-                uint64_t free3:1;
-                uint64_t free2:1;
-                uint64_t free1:1;
-                uint64_t free0:1;
-                uint64_t pool7th:1;
-                uint64_t pool6th:1;
-                uint64_t pool5th:1;
-                uint64_t pool4th:1;
-                uint64_t pool3th:1;
-                uint64_t pool2th:1;
-                uint64_t pool1th:1;
-                uint64_t pool0th:1;
-                uint64_t q7_perr:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_und:1;
-                uint64_t q6_perr:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_und:1;
-                uint64_t q5_perr:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_und:1;
-                uint64_t q4_perr:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_und:1;
-                uint64_t q3_perr:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_und:1;
-                uint64_t q2_perr:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_und:1;
-                uint64_t q1_perr:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_und:1;
-                uint64_t q0_perr:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_und:1;
-                uint64_t fed1_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed0_sbe:1;
-#else
-                uint64_t fed0_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed1_dbe:1;
-                uint64_t q0_und:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_perr:1;
-                uint64_t q1_und:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_perr:1;
-                uint64_t q2_und:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_perr:1;
-                uint64_t q3_und:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_perr:1;
-                uint64_t q4_und:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_perr:1;
-                uint64_t q5_und:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_perr:1;
-                uint64_t q6_und:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_perr:1;
-                uint64_t q7_und:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_perr:1;
-                uint64_t pool0th:1;
-                uint64_t pool1th:1;
-                uint64_t pool2th:1;
-                uint64_t pool3th:1;
-                uint64_t pool4th:1;
-                uint64_t pool5th:1;
-                uint64_t pool6th:1;
-                uint64_t pool7th:1;
-                uint64_t free0:1;
-                uint64_t free1:1;
-                uint64_t free2:1;
-                uint64_t free3:1;
-                uint64_t free4:1;
-                uint64_t free5:1;
-                uint64_t free6:1;
-                uint64_t free7:1;
-                uint64_t reserved_44_48:5;
-                uint64_t paddr_e:1;
-                uint64_t reserved_50_63:14;
-#endif
-        } cn61xx;
-        struct cvmx_fpa_int_sum_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t free7:1;
-                uint64_t free6:1;
-                uint64_t free5:1;
-                uint64_t free4:1;
-                uint64_t free3:1;
-                uint64_t free2:1;
-                uint64_t free1:1;
-                uint64_t free0:1;
-                uint64_t pool7th:1;
-                uint64_t pool6th:1;
-                uint64_t pool5th:1;
-                uint64_t pool4th:1;
-                uint64_t pool3th:1;
-                uint64_t pool2th:1;
-                uint64_t pool1th:1;
-                uint64_t pool0th:1;
-                uint64_t q7_perr:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_und:1;
-                uint64_t q6_perr:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_und:1;
-                uint64_t q5_perr:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_und:1;
-                uint64_t q4_perr:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_und:1;
-                uint64_t q3_perr:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_und:1;
-                uint64_t q2_perr:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_und:1;
-                uint64_t q1_perr:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_und:1;
-                uint64_t q0_perr:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_und:1;
-                uint64_t fed1_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed0_sbe:1;
-#else
-                uint64_t fed0_sbe:1;
-                uint64_t fed0_dbe:1;
-                uint64_t fed1_sbe:1;
-                uint64_t fed1_dbe:1;
-                uint64_t q0_und:1;
-                uint64_t q0_coff:1;
-                uint64_t q0_perr:1;
-                uint64_t q1_und:1;
-                uint64_t q1_coff:1;
-                uint64_t q1_perr:1;
-                uint64_t q2_und:1;
-                uint64_t q2_coff:1;
-                uint64_t q2_perr:1;
-                uint64_t q3_und:1;
-                uint64_t q3_coff:1;
-                uint64_t q3_perr:1;
-                uint64_t q4_und:1;
-                uint64_t q4_coff:1;
-                uint64_t q4_perr:1;
-                uint64_t q5_und:1;
-                uint64_t q5_coff:1;
-                uint64_t q5_perr:1;
-                uint64_t q6_und:1;
-                uint64_t q6_coff:1;
-                uint64_t q6_perr:1;
-                uint64_t q7_und:1;
-                uint64_t q7_coff:1;
-                uint64_t q7_perr:1;
-                uint64_t pool0th:1;
-                uint64_t pool1th:1;
-                uint64_t pool2th:1;
-                uint64_t pool3th:1;
-                uint64_t pool4th:1;
-                uint64_t pool5th:1;
-                uint64_t pool6th:1;
-                uint64_t pool7th:1;
-                uint64_t free0:1;
-                uint64_t free1:1;
-                uint64_t free2:1;
-                uint64_t free3:1;
-                uint64_t free4:1;
-                uint64_t free5:1;
-                uint64_t free6:1;
-                uint64_t free7:1;
-                uint64_t reserved_44_63:20;
-#endif
-        } cn63xx;
-        struct cvmx_fpa_int_sum_cn30xx cn63xxp1;
-        struct cvmx_fpa_int_sum_cn61xx cn66xx;
-        struct cvmx_fpa_int_sum_s cn68xx;
-        struct cvmx_fpa_int_sum_s cn68xxp1;
-        struct cvmx_fpa_int_sum_cn61xx cnf71xx;
-};
-
-union cvmx_fpa_packet_threshold {
-        uint64_t u64;
-        struct cvmx_fpa_packet_threshold_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t thresh:32;
-#else
-                uint64_t thresh:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_fpa_packet_threshold_s cn61xx;
-        struct cvmx_fpa_packet_threshold_s cn63xx;
-        struct cvmx_fpa_packet_threshold_s cn66xx;
-        struct cvmx_fpa_packet_threshold_s cn68xx;
-        struct cvmx_fpa_packet_threshold_s cn68xxp1;
-        struct cvmx_fpa_packet_threshold_s cnf71xx;
-};
-
-union cvmx_fpa_poolx_end_addr {
-        uint64_t u64;
-        struct cvmx_fpa_poolx_end_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t addr:33;
-#else
-                uint64_t addr:33;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_fpa_poolx_end_addr_s cn61xx;
-        struct cvmx_fpa_poolx_end_addr_s cn66xx;
-        struct cvmx_fpa_poolx_end_addr_s cn68xx;
-        struct cvmx_fpa_poolx_end_addr_s cn68xxp1;
-        struct cvmx_fpa_poolx_end_addr_s cnf71xx;
-};
-
-union cvmx_fpa_poolx_start_addr {
-        uint64_t u64;
-        struct cvmx_fpa_poolx_start_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t addr:33;
-#else
-                uint64_t addr:33;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_fpa_poolx_start_addr_s cn61xx;
-        struct cvmx_fpa_poolx_start_addr_s cn66xx;
-        struct cvmx_fpa_poolx_start_addr_s cn68xx;
-        struct cvmx_fpa_poolx_start_addr_s cn68xxp1;
-        struct cvmx_fpa_poolx_start_addr_s cnf71xx;
-};
-
-union cvmx_fpa_poolx_threshold {
-        uint64_t u64;
-        struct cvmx_fpa_poolx_threshold_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t thresh:32;
-#else
-                uint64_t thresh:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_fpa_poolx_threshold_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t thresh:29;
-#else
-                uint64_t thresh:29;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn61xx;
-        struct cvmx_fpa_poolx_threshold_cn61xx cn63xx;
-        struct cvmx_fpa_poolx_threshold_cn61xx cn66xx;
-        struct cvmx_fpa_poolx_threshold_s cn68xx;
-        struct cvmx_fpa_poolx_threshold_s cn68xxp1;
-        struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx;
-};
-
-union cvmx_fpa_quex_available {
-        uint64_t u64;
-        struct cvmx_fpa_quex_available_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t que_siz:32;
-#else
-                uint64_t que_siz:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_fpa_quex_available_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t que_siz:29;
-#else
-                uint64_t que_siz:29;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn30xx;
-        struct cvmx_fpa_quex_available_cn30xx cn31xx;
-        struct cvmx_fpa_quex_available_cn30xx cn38xx;
-        struct cvmx_fpa_quex_available_cn30xx cn38xxp2;
-        struct cvmx_fpa_quex_available_cn30xx cn50xx;
-        struct cvmx_fpa_quex_available_cn30xx cn52xx;
-        struct cvmx_fpa_quex_available_cn30xx cn52xxp1;
-        struct cvmx_fpa_quex_available_cn30xx cn56xx;
-        struct cvmx_fpa_quex_available_cn30xx cn56xxp1;
-        struct cvmx_fpa_quex_available_cn30xx cn58xx;
-        struct cvmx_fpa_quex_available_cn30xx cn58xxp1;
-        struct cvmx_fpa_quex_available_cn30xx cn61xx;
-        struct cvmx_fpa_quex_available_cn30xx cn63xx;
-        struct cvmx_fpa_quex_available_cn30xx cn63xxp1;
-        struct cvmx_fpa_quex_available_cn30xx cn66xx;
-        struct cvmx_fpa_quex_available_s cn68xx;
-        struct cvmx_fpa_quex_available_s cn68xxp1;
-        struct cvmx_fpa_quex_available_cn30xx cnf71xx;
-};
-
-union cvmx_fpa_quex_page_index {
-        uint64_t u64;
-        struct cvmx_fpa_quex_page_index_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t pg_num:25;
-#else
-                uint64_t pg_num:25;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_fpa_quex_page_index_s cn30xx;
-        struct cvmx_fpa_quex_page_index_s cn31xx;
-        struct cvmx_fpa_quex_page_index_s cn38xx;
-        struct cvmx_fpa_quex_page_index_s cn38xxp2;
-        struct cvmx_fpa_quex_page_index_s cn50xx;
-        struct cvmx_fpa_quex_page_index_s cn52xx;
-        struct cvmx_fpa_quex_page_index_s cn52xxp1;
-        struct cvmx_fpa_quex_page_index_s cn56xx;
-        struct cvmx_fpa_quex_page_index_s cn56xxp1;
-        struct cvmx_fpa_quex_page_index_s cn58xx;
-        struct cvmx_fpa_quex_page_index_s cn58xxp1;
-        struct cvmx_fpa_quex_page_index_s cn61xx;
-        struct cvmx_fpa_quex_page_index_s cn63xx;
-        struct cvmx_fpa_quex_page_index_s cn63xxp1;
-        struct cvmx_fpa_quex_page_index_s cn66xx;
-        struct cvmx_fpa_quex_page_index_s cn68xx;
-        struct cvmx_fpa_quex_page_index_s cn68xxp1;
-        struct cvmx_fpa_quex_page_index_s cnf71xx;
-};
-
-union cvmx_fpa_que8_page_index {
-        uint64_t u64;
-        struct cvmx_fpa_que8_page_index_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t pg_num:25;
-#else
-                uint64_t pg_num:25;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_fpa_que8_page_index_s cn68xx;
-        struct cvmx_fpa_que8_page_index_s cn68xxp1;
-};
-
-union cvmx_fpa_que_act {
-        uint64_t u64;
-        struct cvmx_fpa_que_act_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t act_que:3;
-                uint64_t act_indx:26;
-#else
-                uint64_t act_indx:26;
-                uint64_t act_que:3;
-                uint64_t reserved_29_63:35;
-#endif
-        } s;
-        struct cvmx_fpa_que_act_s cn30xx;
-        struct cvmx_fpa_que_act_s cn31xx;
-        struct cvmx_fpa_que_act_s cn38xx;
-        struct cvmx_fpa_que_act_s cn38xxp2;
-        struct cvmx_fpa_que_act_s cn50xx;
-        struct cvmx_fpa_que_act_s cn52xx;
-        struct cvmx_fpa_que_act_s cn52xxp1;
-        struct cvmx_fpa_que_act_s cn56xx;
-        struct cvmx_fpa_que_act_s cn56xxp1;
-        struct cvmx_fpa_que_act_s cn58xx;
-        struct cvmx_fpa_que_act_s cn58xxp1;
-        struct cvmx_fpa_que_act_s cn61xx;
-        struct cvmx_fpa_que_act_s cn63xx;
-        struct cvmx_fpa_que_act_s cn63xxp1;
-        struct cvmx_fpa_que_act_s cn66xx;
-        struct cvmx_fpa_que_act_s cn68xx;
-        struct cvmx_fpa_que_act_s cn68xxp1;
-        struct cvmx_fpa_que_act_s cnf71xx;
-};
-
-union cvmx_fpa_que_exp {
-        uint64_t u64;
-        struct cvmx_fpa_que_exp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t exp_que:3;
-                uint64_t exp_indx:26;
-#else
-                uint64_t exp_indx:26;
-                uint64_t exp_que:3;
-                uint64_t reserved_29_63:35;
-#endif
-        } s;
-        struct cvmx_fpa_que_exp_s cn30xx;
-        struct cvmx_fpa_que_exp_s cn31xx;
-        struct cvmx_fpa_que_exp_s cn38xx;
-        struct cvmx_fpa_que_exp_s cn38xxp2;
-        struct cvmx_fpa_que_exp_s cn50xx;
-        struct cvmx_fpa_que_exp_s cn52xx;
-        struct cvmx_fpa_que_exp_s cn52xxp1;
-        struct cvmx_fpa_que_exp_s cn56xx;
-        struct cvmx_fpa_que_exp_s cn56xxp1;
-        struct cvmx_fpa_que_exp_s cn58xx;
-        struct cvmx_fpa_que_exp_s cn58xxp1;
-        struct cvmx_fpa_que_exp_s cn61xx;
-        struct cvmx_fpa_que_exp_s cn63xx;
-        struct cvmx_fpa_que_exp_s cn63xxp1;
-        struct cvmx_fpa_que_exp_s cn66xx;
-        struct cvmx_fpa_que_exp_s cn68xx;
-        struct cvmx_fpa_que_exp_s cn68xxp1;
-        struct cvmx_fpa_que_exp_s cnf71xx;
-};
-
-union cvmx_fpa_wart_ctl {
-        uint64_t u64;
-        struct cvmx_fpa_wart_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t ctl:16;
-#else
-                uint64_t ctl:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_fpa_wart_ctl_s cn30xx;
-        struct cvmx_fpa_wart_ctl_s cn31xx;
-        struct cvmx_fpa_wart_ctl_s cn38xx;
-        struct cvmx_fpa_wart_ctl_s cn38xxp2;
-        struct cvmx_fpa_wart_ctl_s cn50xx;
-        struct cvmx_fpa_wart_ctl_s cn52xx;
-        struct cvmx_fpa_wart_ctl_s cn52xxp1;
-        struct cvmx_fpa_wart_ctl_s cn56xx;
-        struct cvmx_fpa_wart_ctl_s cn56xxp1;
-        struct cvmx_fpa_wart_ctl_s cn58xx;
-        struct cvmx_fpa_wart_ctl_s cn58xxp1;
-};
-
-union cvmx_fpa_wart_status {
-        uint64_t u64;
-        struct cvmx_fpa_wart_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t status:32;
-#else
-                uint64_t status:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_fpa_wart_status_s cn30xx;
-        struct cvmx_fpa_wart_status_s cn31xx;
-        struct cvmx_fpa_wart_status_s cn38xx;
-        struct cvmx_fpa_wart_status_s cn38xxp2;
-        struct cvmx_fpa_wart_status_s cn50xx;
-        struct cvmx_fpa_wart_status_s cn52xx;
-        struct cvmx_fpa_wart_status_s cn52xxp1;
-        struct cvmx_fpa_wart_status_s cn56xx;
-        struct cvmx_fpa_wart_status_s cn56xxp1;
-        struct cvmx_fpa_wart_status_s cn58xx;
-        struct cvmx_fpa_wart_status_s cn58xxp1;
-};
-
-union cvmx_fpa_wqe_threshold {
-        uint64_t u64;
-        struct cvmx_fpa_wqe_threshold_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t thresh:32;
-#else
-                uint64_t thresh:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_fpa_wqe_threshold_s cn61xx;
-        struct cvmx_fpa_wqe_threshold_s cn63xx;
-        struct cvmx_fpa_wqe_threshold_s cn66xx;
-        struct cvmx_fpa_wqe_threshold_s cn68xx;
-        struct cvmx_fpa_wqe_threshold_s cn68xxp1;
-        struct cvmx_fpa_wqe_threshold_s cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
deleted file mode 100644
index 541a1ae02b6..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-fpa.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Interface to the hardware Free Pool Allocator.
- *
- *
- */
-
-#ifndef __CVMX_FPA_H__
-#define __CVMX_FPA_H__
-
-#include <asm/octeon/cvmx-address.h>
-#include <asm/octeon/cvmx-fpa-defs.h>
-
-#define CVMX_FPA_NUM_POOLS      8
-#define CVMX_FPA_MIN_BLOCK_SIZE 128
-#define CVMX_FPA_ALIGNMENT      128
-
-/**
- * Structure describing the data format used for stores to the FPA.
- */
-typedef union {
-        uint64_t u64;
-        struct {
-                /*
-                 * the (64-bit word) location in scratchpad to write
-                 * to (if len != 0)
-                 */
-                uint64_t scraddr:8;
-                /* the number of words in the response (0 => no response) */
-                uint64_t len:8;
-                /* the ID of the device on the non-coherent bus */
-                uint64_t did:8;
-                /*
-                 * the address that will appear in the first tick on
-                 * the NCB bus.
-                 */
-                uint64_t addr:40;
-        } s;
-} cvmx_fpa_iobdma_data_t;
-
-/**
- * Structure describing the current state of a FPA pool.
- */
-typedef struct {
-        /* Name it was created under */
-        const char *name;
-        /* Size of each block */
-        uint64_t size;
-        /* The base memory address of whole block */
-        void *base;
-        /* The number of elements in the pool at creation */
-        uint64_t starting_element_count;
-} cvmx_fpa_pool_info_t;
-
-/**
- * Current state of all the pools. Use access functions
- * instead of using it directly.
- */
-extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-/**
- * Return the name of the pool
- *
- * @pool:   Pool to get the name of
- * Returns The name
- */
-static inline const char *cvmx_fpa_get_name(uint64_t pool)
-{
-        return cvmx_fpa_pool_info[pool].name;
-}
-
-/**
- * Return the base of the pool
- *
- * @pool:   Pool to get the base of
- * Returns The base
- */
-static inline void *cvmx_fpa_get_base(uint64_t pool)
-{
-        return cvmx_fpa_pool_info[pool].base;
-}
-
-/**
- * Check if a pointer belongs to an FPA pool. Return non-zero
- * if the supplied pointer is inside the memory controlled by
- * an FPA pool.
- *
- * @pool:   Pool to check
- * @ptr:    Pointer to check
- * Returns Non-zero if pointer is in the pool. Zero if not
- */
-static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
-{
-        return ((ptr >= cvmx_fpa_pool_info[pool].base) &&
-                ((char *)ptr <
-                 ((char *)(cvmx_fpa_pool_info[pool].base)) +
-                 cvmx_fpa_pool_info[pool].size *
-                 cvmx_fpa_pool_info[pool].starting_element_count));
-}
-
-/**
- * Enable the FPA for use. Must be performed after any CSR
- * configuration but before any other FPA functions.
- */
-static inline void cvmx_fpa_enable(void)
-{
-        union cvmx_fpa_ctl_status status;
-
-        status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
-        if (status.s.enb) {
-                cvmx_dprintf
-                    ("Warning: Enabling FPA when FPA already enabled.\n");
-        }
-
-        /*
-         * Do runtime check as we allow pass1 compiled code to run on
-         * pass2 chips.
-         */
-        if (cvmx_octeon_is_pass1()) {
-                union cvmx_fpa_fpfx_marks marks;
-                int i;
-                for (i = 1; i < 8; i++) {
-                        marks.u64 =
-                            cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull);
-                        marks.s.fpf_wr = 0xe0;
-                        cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull,
-                                       marks.u64);
-                }
-
-                /* Enforce a 10 cycle delay between config and enable */
-                cvmx_wait(10);
-        }
-
-        /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
-        status.u64 = 0;
-        status.s.enb = 1;
-        cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
-}
-
-/**
- * Get a new block from the FPA
- *
- * @pool:   Pool to get the block from
- * Returns Pointer to the block or NULL on failure
- */
-static inline void *cvmx_fpa_alloc(uint64_t pool)
-{
-        uint64_t address =
-            cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));
-        if (address)
-                return cvmx_phys_to_ptr(address);
-        else
-                return NULL;
-}
-
-/**
- * Asynchronously get a new block from the FPA
- *
- * @scr_addr: Local scratch address to put response in.  This is a byte address,
- *                  but must be 8 byte aligned.
- * @pool:      Pool to get the block from
- */
-static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
-{
-        cvmx_fpa_iobdma_data_t data;
-
-        /*
-         * Hardware only uses 64 bit aligned locations, so convert
-         * from byte address to 64-bit index
-         */
-        data.s.scraddr = scr_addr >> 3;
-        data.s.len = 1;
-        data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool);
-        data.s.addr = 0;
-        cvmx_send_single(data.u64);
-}
-
-/**
- * Free a block allocated with a FPA pool.  Does NOT provide memory
- * ordering in cases where the memory block was modified by the core.
- *
- * @ptr:    Block to free
- * @pool:   Pool to put it in
- * @num_cache_lines:
- *               Cache lines to invalidate
- */
-static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
-                                        uint64_t num_cache_lines)
-{
-        cvmx_addr_t newptr;
-        newptr.u64 = cvmx_ptr_to_phys(ptr);
-        newptr.sfilldidspace.didspace =
-            CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
-        /* Prevent GCC from reordering around free */
-        barrier();
-        /* value written is number of cache lines not written back */
-        cvmx_write_io(newptr.u64, num_cache_lines);
-}
-
-/**
- * Free a block allocated with a FPA pool.  Provides required memory
- * ordering in cases where memory block was modified by core.
- *
- * @ptr:    Block to free
- * @pool:   Pool to put it in
- * @num_cache_lines:
- *               Cache lines to invalidate
- */
-static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
-                                 uint64_t num_cache_lines)
-{
-        cvmx_addr_t newptr;
-        newptr.u64 = cvmx_ptr_to_phys(ptr);
-        newptr.sfilldidspace.didspace =
-            CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
-        /*
-         * Make sure that any previous writes to memory go out before
-         * we free this buffer.  This also serves as a barrier to
-         * prevent GCC from reordering operations to after the
-         * free.
-         */
-        CVMX_SYNCWS;
-        /* value written is number of cache lines not written back */
-        cvmx_write_io(newptr.u64, num_cache_lines);
-}
-
-/**
- * Setup a FPA pool to control a new block of memory.
- * This can only be called once per pool. Make sure proper
- * locking enforces this.
- *
- * @pool:       Pool to initialize
- *                   0 <= pool < 8
- * @name:       Constant character string to name this pool.
- *                   String is not copied.
- * @buffer:     Pointer to the block of memory to use. This must be
- *                   accessible by all processors and external hardware.
- * @block_size: Size for each block controlled by the FPA
- * @num_blocks: Number of blocks
- *
- * Returns 0 on Success,
- *         -1 on failure
- */
-extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
-                               uint64_t block_size, uint64_t num_blocks);
-
-/**
- * Shutdown a Memory pool and validate that it had all of
- * the buffers originally placed in it. This should only be
- * called by one processor after all hardware has finished
- * using the pool.
- *
- * @pool:   Pool to shutdown
- * Returns Zero on success
- *         - Positive is count of missing buffers
- *         - Negative is too many buffers or corrupted pointers
- */
-extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
-
-/**
- * Get the size of blocks controlled by the pool
- * This is resolved to a constant at compile time.
- *
- * @pool:   Pool to access
- * Returns Size of the block in bytes
- */
-uint64_t cvmx_fpa_get_block_size(uint64_t pool);
-
-#endif /*  __CVM_FPA_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
deleted file mode 100644
index e347496a33c..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
+++ /dev/null
@@ -1,6929 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_GMXX_DEFS_H__
-#define __CVMX_GMXX_DEFS_H__
-
-static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8)
-#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull)
-static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull)
-#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull)
-static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull)
-static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull)
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x0ull) * 8;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x200000ull) * 8;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x0ull) * 8;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x200000ull) * 8;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x0ull) * 8;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x200000ull) * 8;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8)
-static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull))
-static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-#define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048)
-static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
-static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_GMXX_TX_SPI_DRAIN(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
-#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
-static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
-}
-
-union cvmx_gmxx_bad_reg {
-        uint64_t u64;
-        struct cvmx_gmxx_bad_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_31_63:33;
-                uint64_t inb_nxa:4;
-                uint64_t statovr:1;
-                uint64_t loststat:4;
-                uint64_t reserved_18_21:4;
-                uint64_t out_ovr:16;
-                uint64_t ncb_ovr:1;
-                uint64_t out_col:1;
-#else
-                uint64_t out_col:1;
-                uint64_t ncb_ovr:1;
-                uint64_t out_ovr:16;
-                uint64_t reserved_18_21:4;
-                uint64_t loststat:4;
-                uint64_t statovr:1;
-                uint64_t inb_nxa:4;
-                uint64_t reserved_31_63:33;
-#endif
-        } s;
-        struct cvmx_gmxx_bad_reg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_31_63:33;
-                uint64_t inb_nxa:4;
-                uint64_t statovr:1;
-                uint64_t reserved_25_25:1;
-                uint64_t loststat:3;
-                uint64_t reserved_5_21:17;
-                uint64_t out_ovr:3;
-                uint64_t reserved_0_1:2;
-#else
-                uint64_t reserved_0_1:2;
-                uint64_t out_ovr:3;
-                uint64_t reserved_5_21:17;
-                uint64_t loststat:3;
-                uint64_t reserved_25_25:1;
-                uint64_t statovr:1;
-                uint64_t inb_nxa:4;
-                uint64_t reserved_31_63:33;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
-        struct cvmx_gmxx_bad_reg_s cn38xx;
-        struct cvmx_gmxx_bad_reg_s cn38xxp2;
-        struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
-        struct cvmx_gmxx_bad_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_31_63:33;
-                uint64_t inb_nxa:4;
-                uint64_t statovr:1;
-                uint64_t loststat:4;
-                uint64_t reserved_6_21:16;
-                uint64_t out_ovr:4;
-                uint64_t reserved_0_1:2;
-#else
-                uint64_t reserved_0_1:2;
-                uint64_t out_ovr:4;
-                uint64_t reserved_6_21:16;
-                uint64_t loststat:4;
-                uint64_t statovr:1;
-                uint64_t inb_nxa:4;
-                uint64_t reserved_31_63:33;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
-        struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
-        struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
-        struct cvmx_gmxx_bad_reg_s cn58xx;
-        struct cvmx_gmxx_bad_reg_s cn58xxp1;
-        struct cvmx_gmxx_bad_reg_cn52xx cn61xx;
-        struct cvmx_gmxx_bad_reg_cn52xx cn63xx;
-        struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1;
-        struct cvmx_gmxx_bad_reg_cn52xx cn66xx;
-        struct cvmx_gmxx_bad_reg_cn52xx cn68xx;
-        struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1;
-        struct cvmx_gmxx_bad_reg_cn52xx cnf71xx;
-};
-
-union cvmx_gmxx_bist {
-        uint64_t u64;
-        struct cvmx_gmxx_bist_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t status:25;
-#else
-                uint64_t status:25;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_gmxx_bist_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t status:10;
-#else
-                uint64_t status:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_bist_cn30xx cn31xx;
-        struct cvmx_gmxx_bist_cn30xx cn38xx;
-        struct cvmx_gmxx_bist_cn30xx cn38xxp2;
-        struct cvmx_gmxx_bist_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t status:12;
-#else
-                uint64_t status:12;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn50xx;
-        struct cvmx_gmxx_bist_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t status:16;
-#else
-                uint64_t status:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_bist_cn52xx cn52xxp1;
-        struct cvmx_gmxx_bist_cn52xx cn56xx;
-        struct cvmx_gmxx_bist_cn52xx cn56xxp1;
-        struct cvmx_gmxx_bist_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t status:17;
-#else
-                uint64_t status:17;
-                uint64_t reserved_17_63:47;
-#endif
-        } cn58xx;
-        struct cvmx_gmxx_bist_cn58xx cn58xxp1;
-        struct cvmx_gmxx_bist_s cn61xx;
-        struct cvmx_gmxx_bist_s cn63xx;
-        struct cvmx_gmxx_bist_s cn63xxp1;
-        struct cvmx_gmxx_bist_s cn66xx;
-        struct cvmx_gmxx_bist_s cn68xx;
-        struct cvmx_gmxx_bist_s cn68xxp1;
-        struct cvmx_gmxx_bist_s cnf71xx;
-};
-
-union cvmx_gmxx_bpid_mapx {
-        uint64_t u64;
-        struct cvmx_gmxx_bpid_mapx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t status:1;
-                uint64_t reserved_9_15:7;
-                uint64_t val:1;
-                uint64_t reserved_6_7:2;
-                uint64_t bpid:6;
-#else
-                uint64_t bpid:6;
-                uint64_t reserved_6_7:2;
-                uint64_t val:1;
-                uint64_t reserved_9_15:7;
-                uint64_t status:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_gmxx_bpid_mapx_s cn68xx;
-        struct cvmx_gmxx_bpid_mapx_s cn68xxp1;
-};
-
-union cvmx_gmxx_bpid_msk {
-        uint64_t u64;
-        struct cvmx_gmxx_bpid_msk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t msk_or:16;
-                uint64_t reserved_16_31:16;
-                uint64_t msk_and:16;
-#else
-                uint64_t msk_and:16;
-                uint64_t reserved_16_31:16;
-                uint64_t msk_or:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_bpid_msk_s cn68xx;
-        struct cvmx_gmxx_bpid_msk_s cn68xxp1;
-};
-
-union cvmx_gmxx_clk_en {
-        uint64_t u64;
-        struct cvmx_gmxx_clk_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t clk_en:1;
-#else
-                uint64_t clk_en:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_gmxx_clk_en_s cn52xx;
-        struct cvmx_gmxx_clk_en_s cn52xxp1;
-        struct cvmx_gmxx_clk_en_s cn56xx;
-        struct cvmx_gmxx_clk_en_s cn56xxp1;
-        struct cvmx_gmxx_clk_en_s cn61xx;
-        struct cvmx_gmxx_clk_en_s cn63xx;
-        struct cvmx_gmxx_clk_en_s cn63xxp1;
-        struct cvmx_gmxx_clk_en_s cn66xx;
-        struct cvmx_gmxx_clk_en_s cn68xx;
-        struct cvmx_gmxx_clk_en_s cn68xxp1;
-        struct cvmx_gmxx_clk_en_s cnf71xx;
-};
-
-union cvmx_gmxx_ebp_dis {
-        uint64_t u64;
-        struct cvmx_gmxx_ebp_dis_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t dis:16;
-#else
-                uint64_t dis:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_ebp_dis_s cn68xx;
-        struct cvmx_gmxx_ebp_dis_s cn68xxp1;
-};
-
-union cvmx_gmxx_ebp_msk {
-        uint64_t u64;
-        struct cvmx_gmxx_ebp_msk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t msk:16;
-#else
-                uint64_t msk:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_ebp_msk_s cn68xx;
-        struct cvmx_gmxx_ebp_msk_s cn68xxp1;
-};
-
-union cvmx_gmxx_hg2_control {
-        uint64_t u64;
-        struct cvmx_gmxx_hg2_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t hg2tx_en:1;
-                uint64_t hg2rx_en:1;
-                uint64_t phys_en:1;
-                uint64_t logl_en:16;
-#else
-                uint64_t logl_en:16;
-                uint64_t phys_en:1;
-                uint64_t hg2rx_en:1;
-                uint64_t hg2tx_en:1;
-                uint64_t reserved_19_63:45;
-#endif
-        } s;
-        struct cvmx_gmxx_hg2_control_s cn52xx;
-        struct cvmx_gmxx_hg2_control_s cn52xxp1;
-        struct cvmx_gmxx_hg2_control_s cn56xx;
-        struct cvmx_gmxx_hg2_control_s cn61xx;
-        struct cvmx_gmxx_hg2_control_s cn63xx;
-        struct cvmx_gmxx_hg2_control_s cn63xxp1;
-        struct cvmx_gmxx_hg2_control_s cn66xx;
-        struct cvmx_gmxx_hg2_control_s cn68xx;
-        struct cvmx_gmxx_hg2_control_s cn68xxp1;
-        struct cvmx_gmxx_hg2_control_s cnf71xx;
-};
-
-union cvmx_gmxx_inf_mode {
-        uint64_t u64;
-        struct cvmx_gmxx_inf_mode_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t rate:4;
-                uint64_t reserved_12_15:4;
-                uint64_t speed:4;
-                uint64_t reserved_7_7:1;
-                uint64_t mode:3;
-                uint64_t reserved_3_3:1;
-                uint64_t p0mii:1;
-                uint64_t en:1;
-                uint64_t type:1;
-#else
-                uint64_t type:1;
-                uint64_t en:1;
-                uint64_t p0mii:1;
-                uint64_t reserved_3_3:1;
-                uint64_t mode:3;
-                uint64_t reserved_7_7:1;
-                uint64_t speed:4;
-                uint64_t reserved_12_15:4;
-                uint64_t rate:4;
-                uint64_t reserved_20_63:44;
-#endif
-        } s;
-        struct cvmx_gmxx_inf_mode_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t p0mii:1;
-                uint64_t en:1;
-                uint64_t type:1;
-#else
-                uint64_t type:1;
-                uint64_t en:1;
-                uint64_t p0mii:1;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_inf_mode_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t en:1;
-                uint64_t type:1;
-#else
-                uint64_t type:1;
-                uint64_t en:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } cn31xx;
-        struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
-        struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
-        struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
-        struct cvmx_gmxx_inf_mode_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t speed:2;
-                uint64_t reserved_6_7:2;
-                uint64_t mode:2;
-                uint64_t reserved_2_3:2;
-                uint64_t en:1;
-                uint64_t type:1;
-#else
-                uint64_t type:1;
-                uint64_t en:1;
-                uint64_t reserved_2_3:2;
-                uint64_t mode:2;
-                uint64_t reserved_6_7:2;
-                uint64_t speed:2;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
-        struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
-        struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
-        struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
-        struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
-        struct cvmx_gmxx_inf_mode_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t speed:4;
-                uint64_t reserved_5_7:3;
-                uint64_t mode:1;
-                uint64_t reserved_2_3:2;
-                uint64_t en:1;
-                uint64_t type:1;
-#else
-                uint64_t type:1;
-                uint64_t en:1;
-                uint64_t reserved_2_3:2;
-                uint64_t mode:1;
-                uint64_t reserved_5_7:3;
-                uint64_t speed:4;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn61xx;
-        struct cvmx_gmxx_inf_mode_cn61xx cn63xx;
-        struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1;
-        struct cvmx_gmxx_inf_mode_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t rate:4;
-                uint64_t reserved_12_15:4;
-                uint64_t speed:4;
-                uint64_t reserved_5_7:3;
-                uint64_t mode:1;
-                uint64_t reserved_2_3:2;
-                uint64_t en:1;
-                uint64_t type:1;
-#else
-                uint64_t type:1;
-                uint64_t en:1;
-                uint64_t reserved_2_3:2;
-                uint64_t mode:1;
-                uint64_t reserved_5_7:3;
-                uint64_t speed:4;
-                uint64_t reserved_12_15:4;
-                uint64_t rate:4;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn66xx;
-        struct cvmx_gmxx_inf_mode_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t speed:4;
-                uint64_t reserved_7_7:1;
-                uint64_t mode:3;
-                uint64_t reserved_2_3:2;
-                uint64_t en:1;
-                uint64_t type:1;
-#else
-                uint64_t type:1;
-                uint64_t en:1;
-                uint64_t reserved_2_3:2;
-                uint64_t mode:3;
-                uint64_t reserved_7_7:1;
-                uint64_t speed:4;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn68xx;
-        struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1;
-        struct cvmx_gmxx_inf_mode_cn61xx cnf71xx;
-};
-
-union cvmx_gmxx_nxa_adr {
-        uint64_t u64;
-        struct cvmx_gmxx_nxa_adr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t pipe:7;
-                uint64_t reserved_6_15:10;
-                uint64_t prt:6;
-#else
-                uint64_t prt:6;
-                uint64_t reserved_6_15:10;
-                uint64_t pipe:7;
-                uint64_t reserved_23_63:41;
-#endif
-        } s;
-        struct cvmx_gmxx_nxa_adr_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t prt:6;
-#else
-                uint64_t prt:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn31xx;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn38xx;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn50xx;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn52xx;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn56xx;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn58xx;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn61xx;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn63xx;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1;
-        struct cvmx_gmxx_nxa_adr_cn30xx cn66xx;
-        struct cvmx_gmxx_nxa_adr_s cn68xx;
-        struct cvmx_gmxx_nxa_adr_s cn68xxp1;
-        struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx;
-};
-
-union cvmx_gmxx_pipe_status {
-        uint64_t u64;
-        struct cvmx_gmxx_pipe_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t ovr:4;
-                uint64_t reserved_12_15:4;
-                uint64_t bp:4;
-                uint64_t reserved_4_7:4;
-                uint64_t stop:4;
-#else
-                uint64_t stop:4;
-                uint64_t reserved_4_7:4;
-                uint64_t bp:4;
-                uint64_t reserved_12_15:4;
-                uint64_t ovr:4;
-                uint64_t reserved_20_63:44;
-#endif
-        } s;
-        struct cvmx_gmxx_pipe_status_s cn68xx;
-        struct cvmx_gmxx_pipe_status_s cn68xxp1;
-};
-
-union cvmx_gmxx_prtx_cbfc_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t phys_en:16;
-                uint64_t logl_en:16;
-                uint64_t phys_bp:16;
-                uint64_t reserved_4_15:12;
-                uint64_t bck_en:1;
-                uint64_t drp_en:1;
-                uint64_t tx_en:1;
-                uint64_t rx_en:1;
-#else
-                uint64_t rx_en:1;
-                uint64_t tx_en:1;
-                uint64_t drp_en:1;
-                uint64_t bck_en:1;
-                uint64_t reserved_4_15:12;
-                uint64_t phys_bp:16;
-                uint64_t logl_en:16;
-                uint64_t phys_en:16;
-#endif
-        } s;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1;
-        struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_prtx_cfg {
-        uint64_t u64;
-        struct cvmx_gmxx_prtx_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t pknd:6;
-                uint64_t reserved_14_15:2;
-                uint64_t tx_idle:1;
-                uint64_t rx_idle:1;
-                uint64_t reserved_9_11:3;
-                uint64_t speed_msb:1;
-                uint64_t reserved_4_7:4;
-                uint64_t slottime:1;
-                uint64_t duplex:1;
-                uint64_t speed:1;
-                uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t speed:1;
-                uint64_t duplex:1;
-                uint64_t slottime:1;
-                uint64_t reserved_4_7:4;
-                uint64_t speed_msb:1;
-                uint64_t reserved_9_11:3;
-                uint64_t rx_idle:1;
-                uint64_t tx_idle:1;
-                uint64_t reserved_14_15:2;
-                uint64_t pknd:6;
-                uint64_t reserved_22_63:42;
-#endif
-        } s;
-        struct cvmx_gmxx_prtx_cfg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t slottime:1;
-                uint64_t duplex:1;
-                uint64_t speed:1;
-                uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t speed:1;
-                uint64_t duplex:1;
-                uint64_t slottime:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
-        struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
-        struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
-        struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
-        struct cvmx_gmxx_prtx_cfg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t tx_idle:1;
-                uint64_t rx_idle:1;
-                uint64_t reserved_9_11:3;
-                uint64_t speed_msb:1;
-                uint64_t reserved_4_7:4;
-                uint64_t slottime:1;
-                uint64_t duplex:1;
-                uint64_t speed:1;
-                uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t speed:1;
-                uint64_t duplex:1;
-                uint64_t slottime:1;
-                uint64_t reserved_4_7:4;
-                uint64_t speed_msb:1;
-                uint64_t reserved_9_11:3;
-                uint64_t rx_idle:1;
-                uint64_t tx_idle:1;
-                uint64_t reserved_14_63:50;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1;
-        struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx;
-        struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1;
-        struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
-        struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
-        struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx;
-        struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx;
-        struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1;
-        struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx;
-        struct cvmx_gmxx_prtx_cfg_s cn68xx;
-        struct cvmx_gmxx_prtx_cfg_s cn68xxp1;
-        struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam0 {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_adr_cam0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn61xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn63xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn66xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn68xx;
-        struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1;
-        struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam1 {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_adr_cam1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn61xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn63xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn66xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn68xx;
-        struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1;
-        struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam2 {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_adr_cam2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn61xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn63xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn66xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn68xx;
-        struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1;
-        struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam3 {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_adr_cam3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn61xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn63xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn66xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn68xx;
-        struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1;
-        struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam4 {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_adr_cam4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn61xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn63xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn66xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn68xx;
-        struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1;
-        struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam5 {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_adr_cam5_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t adr:64;
-#else
-                uint64_t adr:64;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn61xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn63xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn66xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn68xx;
-        struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1;
-        struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam_all_en {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_adr_cam_all_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t en:32;
-#else
-                uint64_t en:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx;
-        struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx;
-        struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx;
-        struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam_en {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_adr_cam_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t en:8;
-#else
-                uint64_t en:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1;
-        struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_adr_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t cam_mode:1;
-                uint64_t mcst:2;
-                uint64_t bcst:1;
-#else
-                uint64_t bcst:1;
-                uint64_t mcst:2;
-                uint64_t cam_mode:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn61xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn63xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn66xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn68xx;
-        struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1;
-        struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_decision {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_decision_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t cnt:5;
-#else
-                uint64_t cnt:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_decision_s cn30xx;
-        struct cvmx_gmxx_rxx_decision_s cn31xx;
-        struct cvmx_gmxx_rxx_decision_s cn38xx;
-        struct cvmx_gmxx_rxx_decision_s cn38xxp2;
-        struct cvmx_gmxx_rxx_decision_s cn50xx;
-        struct cvmx_gmxx_rxx_decision_s cn52xx;
-        struct cvmx_gmxx_rxx_decision_s cn52xxp1;
-        struct cvmx_gmxx_rxx_decision_s cn56xx;
-        struct cvmx_gmxx_rxx_decision_s cn56xxp1;
-        struct cvmx_gmxx_rxx_decision_s cn58xx;
-        struct cvmx_gmxx_rxx_decision_s cn58xxp1;
-        struct cvmx_gmxx_rxx_decision_s cn61xx;
-        struct cvmx_gmxx_rxx_decision_s cn63xx;
-        struct cvmx_gmxx_rxx_decision_s cn63xxp1;
-        struct cvmx_gmxx_rxx_decision_s cn66xx;
-        struct cvmx_gmxx_rxx_decision_s cn68xx;
-        struct cvmx_gmxx_rxx_decision_s cn68xxp1;
-        struct cvmx_gmxx_rxx_decision_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_frm_chk {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_frm_chk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t lenerr:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t maxerr:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
-        struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
-        struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
-        struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
-        struct cvmx_gmxx_rxx_frm_chk_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_6_6:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t reserved_6_6:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn50xx;
-        struct cvmx_gmxx_rxx_frm_chk_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
-        struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
-        struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
-        struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
-        struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
-        struct cvmx_gmxx_rxx_frm_chk_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn61xx;
-        struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx;
-        struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1;
-        struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx;
-        struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx;
-        struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1;
-        struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx;
-};
-
-union cvmx_gmxx_rxx_frm_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_frm_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t ptp_mode:1;
-                uint64_t reserved_11_11:1;
-                uint64_t null_dis:1;
-                uint64_t pre_align:1;
-                uint64_t pad_len:1;
-                uint64_t vlan_len:1;
-                uint64_t pre_free:1;
-                uint64_t ctl_smac:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_drp:1;
-                uint64_t pre_strp:1;
-                uint64_t pre_chk:1;
-#else
-                uint64_t pre_chk:1;
-                uint64_t pre_strp:1;
-                uint64_t ctl_drp:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_smac:1;
-                uint64_t pre_free:1;
-                uint64_t vlan_len:1;
-                uint64_t pad_len:1;
-                uint64_t pre_align:1;
-                uint64_t null_dis:1;
-                uint64_t reserved_11_11:1;
-                uint64_t ptp_mode:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t pad_len:1;
-                uint64_t vlan_len:1;
-                uint64_t pre_free:1;
-                uint64_t ctl_smac:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_drp:1;
-                uint64_t pre_strp:1;
-                uint64_t pre_chk:1;
-#else
-                uint64_t pre_chk:1;
-                uint64_t pre_strp:1;
-                uint64_t ctl_drp:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_smac:1;
-                uint64_t pre_free:1;
-                uint64_t vlan_len:1;
-                uint64_t pad_len:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t vlan_len:1;
-                uint64_t pre_free:1;
-                uint64_t ctl_smac:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_drp:1;
-                uint64_t pre_strp:1;
-                uint64_t pre_chk:1;
-#else
-                uint64_t pre_chk:1;
-                uint64_t pre_strp:1;
-                uint64_t ctl_drp:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_smac:1;
-                uint64_t pre_free:1;
-                uint64_t vlan_len:1;
-                uint64_t reserved_8_63:56;
-#endif
-        } cn31xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
-        struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t null_dis:1;
-                uint64_t pre_align:1;
-                uint64_t reserved_7_8:2;
-                uint64_t pre_free:1;
-                uint64_t ctl_smac:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_drp:1;
-                uint64_t pre_strp:1;
-                uint64_t pre_chk:1;
-#else
-                uint64_t pre_chk:1;
-                uint64_t pre_strp:1;
-                uint64_t ctl_drp:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_smac:1;
-                uint64_t pre_free:1;
-                uint64_t reserved_7_8:2;
-                uint64_t pre_align:1;
-                uint64_t null_dis:1;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn50xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
-        struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t pre_align:1;
-                uint64_t reserved_7_8:2;
-                uint64_t pre_free:1;
-                uint64_t ctl_smac:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_drp:1;
-                uint64_t pre_strp:1;
-                uint64_t pre_chk:1;
-#else
-                uint64_t pre_chk:1;
-                uint64_t pre_strp:1;
-                uint64_t ctl_drp:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_smac:1;
-                uint64_t pre_free:1;
-                uint64_t reserved_7_8:2;
-                uint64_t pre_align:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn56xxp1;
-        struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t null_dis:1;
-                uint64_t pre_align:1;
-                uint64_t pad_len:1;
-                uint64_t vlan_len:1;
-                uint64_t pre_free:1;
-                uint64_t ctl_smac:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_drp:1;
-                uint64_t pre_strp:1;
-                uint64_t pre_chk:1;
-#else
-                uint64_t pre_chk:1;
-                uint64_t pre_strp:1;
-                uint64_t ctl_drp:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_smac:1;
-                uint64_t pre_free:1;
-                uint64_t vlan_len:1;
-                uint64_t pad_len:1;
-                uint64_t pre_align:1;
-                uint64_t null_dis:1;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn58xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
-        struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t ptp_mode:1;
-                uint64_t reserved_11_11:1;
-                uint64_t null_dis:1;
-                uint64_t pre_align:1;
-                uint64_t reserved_7_8:2;
-                uint64_t pre_free:1;
-                uint64_t ctl_smac:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_drp:1;
-                uint64_t pre_strp:1;
-                uint64_t pre_chk:1;
-#else
-                uint64_t pre_chk:1;
-                uint64_t pre_strp:1;
-                uint64_t ctl_drp:1;
-                uint64_t ctl_bck:1;
-                uint64_t ctl_mcst:1;
-                uint64_t ctl_smac:1;
-                uint64_t pre_free:1;
-                uint64_t reserved_7_8:2;
-                uint64_t pre_align:1;
-                uint64_t null_dis:1;
-                uint64_t reserved_11_11:1;
-                uint64_t ptp_mode:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } cn61xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1;
-        struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx;
-        struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1;
-        struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx;
-};
-
-union cvmx_gmxx_rxx_frm_max {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_frm_max_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t len:16;
-#else
-                uint64_t len:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_frm_max_s cn30xx;
-        struct cvmx_gmxx_rxx_frm_max_s cn31xx;
-        struct cvmx_gmxx_rxx_frm_max_s cn38xx;
-        struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
-        struct cvmx_gmxx_rxx_frm_max_s cn58xx;
-        struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
-};
-
-union cvmx_gmxx_rxx_frm_min {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_frm_min_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t len:16;
-#else
-                uint64_t len:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_frm_min_s cn30xx;
-        struct cvmx_gmxx_rxx_frm_min_s cn31xx;
-        struct cvmx_gmxx_rxx_frm_min_s cn38xx;
-        struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
-        struct cvmx_gmxx_rxx_frm_min_s cn58xx;
-        struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
-};
-
-union cvmx_gmxx_rxx_ifg {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_ifg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t ifg:4;
-#else
-                uint64_t ifg:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_ifg_s cn30xx;
-        struct cvmx_gmxx_rxx_ifg_s cn31xx;
-        struct cvmx_gmxx_rxx_ifg_s cn38xx;
-        struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
-        struct cvmx_gmxx_rxx_ifg_s cn50xx;
-        struct cvmx_gmxx_rxx_ifg_s cn52xx;
-        struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
-        struct cvmx_gmxx_rxx_ifg_s cn56xx;
-        struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
-        struct cvmx_gmxx_rxx_ifg_s cn58xx;
-        struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
-        struct cvmx_gmxx_rxx_ifg_s cn61xx;
-        struct cvmx_gmxx_rxx_ifg_s cn63xx;
-        struct cvmx_gmxx_rxx_ifg_s cn63xxp1;
-        struct cvmx_gmxx_rxx_ifg_s cn66xx;
-        struct cvmx_gmxx_rxx_ifg_s cn68xx;
-        struct cvmx_gmxx_rxx_ifg_s cn68xxp1;
-        struct cvmx_gmxx_rxx_ifg_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_int_en {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t hg2cc:1;
-                uint64_t hg2fld:1;
-                uint64_t undat:1;
-                uint64_t uneop:1;
-                uint64_t unsop:1;
-                uint64_t bad_term:1;
-                uint64_t bad_seq:1;
-                uint64_t rem_fault:1;
-                uint64_t loc_fault:1;
-                uint64_t pause_drp:1;
-                uint64_t phy_dupx:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_link:1;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t lenerr:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t maxerr:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t pause_drp:1;
-                uint64_t loc_fault:1;
-                uint64_t rem_fault:1;
-                uint64_t bad_seq:1;
-                uint64_t bad_term:1;
-                uint64_t unsop:1;
-                uint64_t uneop:1;
-                uint64_t undat:1;
-                uint64_t hg2fld:1;
-                uint64_t hg2cc:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_int_en_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t phy_dupx:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_link:1;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t lenerr:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t maxerr:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t reserved_19_63:45;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
-        struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
-        struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
-        struct cvmx_gmxx_rxx_int_en_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t pause_drp:1;
-                uint64_t phy_dupx:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_link:1;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_6_6:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t reserved_6_6:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn50xx;
-        struct cvmx_gmxx_rxx_int_en_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t hg2cc:1;
-                uint64_t hg2fld:1;
-                uint64_t undat:1;
-                uint64_t uneop:1;
-                uint64_t unsop:1;
-                uint64_t bad_term:1;
-                uint64_t bad_seq:1;
-                uint64_t rem_fault:1;
-                uint64_t loc_fault:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_16_18:3;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t reserved_16_18:3;
-                uint64_t pause_drp:1;
-                uint64_t loc_fault:1;
-                uint64_t rem_fault:1;
-                uint64_t bad_seq:1;
-                uint64_t bad_term:1;
-                uint64_t unsop:1;
-                uint64_t uneop:1;
-                uint64_t undat:1;
-                uint64_t hg2fld:1;
-                uint64_t hg2cc:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
-        struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
-        struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_27_63:37;
-                uint64_t undat:1;
-                uint64_t uneop:1;
-                uint64_t unsop:1;
-                uint64_t bad_term:1;
-                uint64_t bad_seq:1;
-                uint64_t rem_fault:1;
-                uint64_t loc_fault:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_16_18:3;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t reserved_16_18:3;
-                uint64_t pause_drp:1;
-                uint64_t loc_fault:1;
-                uint64_t rem_fault:1;
-                uint64_t bad_seq:1;
-                uint64_t bad_term:1;
-                uint64_t unsop:1;
-                uint64_t uneop:1;
-                uint64_t undat:1;
-                uint64_t reserved_27_63:37;
-#endif
-        } cn56xxp1;
-        struct cvmx_gmxx_rxx_int_en_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t pause_drp:1;
-                uint64_t phy_dupx:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_link:1;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t lenerr:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t maxerr:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn58xx;
-        struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
-        struct cvmx_gmxx_rxx_int_en_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t hg2cc:1;
-                uint64_t hg2fld:1;
-                uint64_t undat:1;
-                uint64_t uneop:1;
-                uint64_t unsop:1;
-                uint64_t bad_term:1;
-                uint64_t bad_seq:1;
-                uint64_t rem_fault:1;
-                uint64_t loc_fault:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_16_18:3;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t reserved_16_18:3;
-                uint64_t pause_drp:1;
-                uint64_t loc_fault:1;
-                uint64_t rem_fault:1;
-                uint64_t bad_seq:1;
-                uint64_t bad_term:1;
-                uint64_t unsop:1;
-                uint64_t uneop:1;
-                uint64_t undat:1;
-                uint64_t hg2fld:1;
-                uint64_t hg2cc:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn61xx;
-        struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx;
-        struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1;
-        struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx;
-        struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx;
-        struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1;
-        struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx;
-};
-
-union cvmx_gmxx_rxx_int_reg {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t hg2cc:1;
-                uint64_t hg2fld:1;
-                uint64_t undat:1;
-                uint64_t uneop:1;
-                uint64_t unsop:1;
-                uint64_t bad_term:1;
-                uint64_t bad_seq:1;
-                uint64_t rem_fault:1;
-                uint64_t loc_fault:1;
-                uint64_t pause_drp:1;
-                uint64_t phy_dupx:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_link:1;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t lenerr:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t maxerr:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t pause_drp:1;
-                uint64_t loc_fault:1;
-                uint64_t rem_fault:1;
-                uint64_t bad_seq:1;
-                uint64_t bad_term:1;
-                uint64_t unsop:1;
-                uint64_t uneop:1;
-                uint64_t undat:1;
-                uint64_t hg2fld:1;
-                uint64_t hg2cc:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_int_reg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t phy_dupx:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_link:1;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t lenerr:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t maxerr:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t reserved_19_63:45;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
-        struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
-        struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
-        struct cvmx_gmxx_rxx_int_reg_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t pause_drp:1;
-                uint64_t phy_dupx:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_link:1;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_6_6:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t reserved_6_6:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn50xx;
-        struct cvmx_gmxx_rxx_int_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t hg2cc:1;
-                uint64_t hg2fld:1;
-                uint64_t undat:1;
-                uint64_t uneop:1;
-                uint64_t unsop:1;
-                uint64_t bad_term:1;
-                uint64_t bad_seq:1;
-                uint64_t rem_fault:1;
-                uint64_t loc_fault:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_16_18:3;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t reserved_16_18:3;
-                uint64_t pause_drp:1;
-                uint64_t loc_fault:1;
-                uint64_t rem_fault:1;
-                uint64_t bad_seq:1;
-                uint64_t bad_term:1;
-                uint64_t unsop:1;
-                uint64_t uneop:1;
-                uint64_t undat:1;
-                uint64_t hg2fld:1;
-                uint64_t hg2cc:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
-        struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
-        struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_27_63:37;
-                uint64_t undat:1;
-                uint64_t uneop:1;
-                uint64_t unsop:1;
-                uint64_t bad_term:1;
-                uint64_t bad_seq:1;
-                uint64_t rem_fault:1;
-                uint64_t loc_fault:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_16_18:3;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t reserved_16_18:3;
-                uint64_t pause_drp:1;
-                uint64_t loc_fault:1;
-                uint64_t rem_fault:1;
-                uint64_t bad_seq:1;
-                uint64_t bad_term:1;
-                uint64_t unsop:1;
-                uint64_t uneop:1;
-                uint64_t undat:1;
-                uint64_t reserved_27_63:37;
-#endif
-        } cn56xxp1;
-        struct cvmx_gmxx_rxx_int_reg_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t pause_drp:1;
-                uint64_t phy_dupx:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_link:1;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t niberr:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t lenerr:1;
-                uint64_t alnerr:1;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t maxerr:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t maxerr:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t alnerr:1;
-                uint64_t lenerr:1;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t niberr:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t phy_link:1;
-                uint64_t phy_spd:1;
-                uint64_t phy_dupx:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn58xx;
-        struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
-        struct cvmx_gmxx_rxx_int_reg_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t hg2cc:1;
-                uint64_t hg2fld:1;
-                uint64_t undat:1;
-                uint64_t uneop:1;
-                uint64_t unsop:1;
-                uint64_t bad_term:1;
-                uint64_t bad_seq:1;
-                uint64_t rem_fault:1;
-                uint64_t loc_fault:1;
-                uint64_t pause_drp:1;
-                uint64_t reserved_16_18:3;
-                uint64_t ifgerr:1;
-                uint64_t coldet:1;
-                uint64_t falerr:1;
-                uint64_t rsverr:1;
-                uint64_t pcterr:1;
-                uint64_t ovrerr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t skperr:1;
-                uint64_t rcverr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t fcserr:1;
-                uint64_t jabber:1;
-                uint64_t reserved_2_2:1;
-                uint64_t carext:1;
-                uint64_t minerr:1;
-#else
-                uint64_t minerr:1;
-                uint64_t carext:1;
-                uint64_t reserved_2_2:1;
-                uint64_t jabber:1;
-                uint64_t fcserr:1;
-                uint64_t reserved_5_6:2;
-                uint64_t rcverr:1;
-                uint64_t skperr:1;
-                uint64_t reserved_9_9:1;
-                uint64_t ovrerr:1;
-                uint64_t pcterr:1;
-                uint64_t rsverr:1;
-                uint64_t falerr:1;
-                uint64_t coldet:1;
-                uint64_t ifgerr:1;
-                uint64_t reserved_16_18:3;
-                uint64_t pause_drp:1;
-                uint64_t loc_fault:1;
-                uint64_t rem_fault:1;
-                uint64_t bad_seq:1;
-                uint64_t bad_term:1;
-                uint64_t unsop:1;
-                uint64_t uneop:1;
-                uint64_t undat:1;
-                uint64_t hg2fld:1;
-                uint64_t hg2cc:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn61xx;
-        struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx;
-        struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1;
-        struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx;
-        struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx;
-        struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1;
-        struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx;
-};
-
-union cvmx_gmxx_rxx_jabber {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_jabber_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t cnt:16;
-#else
-                uint64_t cnt:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_jabber_s cn30xx;
-        struct cvmx_gmxx_rxx_jabber_s cn31xx;
-        struct cvmx_gmxx_rxx_jabber_s cn38xx;
-        struct cvmx_gmxx_rxx_jabber_s cn38xxp2;
-        struct cvmx_gmxx_rxx_jabber_s cn50xx;
-        struct cvmx_gmxx_rxx_jabber_s cn52xx;
-        struct cvmx_gmxx_rxx_jabber_s cn52xxp1;
-        struct cvmx_gmxx_rxx_jabber_s cn56xx;
-        struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
-        struct cvmx_gmxx_rxx_jabber_s cn58xx;
-        struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
-        struct cvmx_gmxx_rxx_jabber_s cn61xx;
-        struct cvmx_gmxx_rxx_jabber_s cn63xx;
-        struct cvmx_gmxx_rxx_jabber_s cn63xxp1;
-        struct cvmx_gmxx_rxx_jabber_s cn66xx;
-        struct cvmx_gmxx_rxx_jabber_s cn68xx;
-        struct cvmx_gmxx_rxx_jabber_s cn68xxp1;
-        struct cvmx_gmxx_rxx_jabber_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_pause_drop_time {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_pause_drop_time_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t status:16;
-#else
-                uint64_t status:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1;
-        struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_rx_inbnd {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_rx_inbnd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t duplex:1;
-                uint64_t speed:2;
-                uint64_t status:1;
-#else
-                uint64_t status:1;
-                uint64_t speed:2;
-                uint64_t duplex:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;
-        struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;
-        struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;
-        struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;
-        struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;
-        struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;
-        struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;
-};
-
-union cvmx_gmxx_rxx_stats_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t rd_clr:1;
-#else
-                uint64_t rd_clr:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_octs {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_octs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t cnt:48;
-#else
-                uint64_t cnt:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_octs_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_octs_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_octs_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t cnt:48;
-#else
-                uint64_t cnt:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_octs_dmac {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t cnt:48;
-#else
-                uint64_t cnt:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_octs_drp {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t cnt:48;
-#else
-                uint64_t cnt:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_pkts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts_bad {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts_dmac {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts_drp {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1;
-        struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_udd_skp {
-        uint64_t u64;
-        struct cvmx_gmxx_rxx_udd_skp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t fcssel:1;
-                uint64_t reserved_7_7:1;
-                uint64_t len:7;
-#else
-                uint64_t len:7;
-                uint64_t reserved_7_7:1;
-                uint64_t fcssel:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_gmxx_rxx_udd_skp_s cn30xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn31xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn38xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;
-        struct cvmx_gmxx_rxx_udd_skp_s cn50xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn52xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;
-        struct cvmx_gmxx_rxx_udd_skp_s cn56xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
-        struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
-        struct cvmx_gmxx_rxx_udd_skp_s cn61xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn63xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1;
-        struct cvmx_gmxx_rxx_udd_skp_s cn66xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn68xx;
-        struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1;
-        struct cvmx_gmxx_rxx_udd_skp_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_bp_dropx {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_bp_dropx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t mark:6;
-#else
-                uint64_t mark:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_bp_dropx_s cn30xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn31xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn38xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;
-        struct cvmx_gmxx_rx_bp_dropx_s cn50xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn52xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;
-        struct cvmx_gmxx_rx_bp_dropx_s cn56xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
-        struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
-        struct cvmx_gmxx_rx_bp_dropx_s cn61xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn63xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1;
-        struct cvmx_gmxx_rx_bp_dropx_s cn66xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn68xx;
-        struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1;
-        struct cvmx_gmxx_rx_bp_dropx_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_bp_offx {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_bp_offx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t mark:6;
-#else
-                uint64_t mark:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_bp_offx_s cn30xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn31xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn38xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn38xxp2;
-        struct cvmx_gmxx_rx_bp_offx_s cn50xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn52xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn52xxp1;
-        struct cvmx_gmxx_rx_bp_offx_s cn56xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
-        struct cvmx_gmxx_rx_bp_offx_s cn58xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
-        struct cvmx_gmxx_rx_bp_offx_s cn61xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn63xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn63xxp1;
-        struct cvmx_gmxx_rx_bp_offx_s cn66xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn68xx;
-        struct cvmx_gmxx_rx_bp_offx_s cn68xxp1;
-        struct cvmx_gmxx_rx_bp_offx_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_bp_onx {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_bp_onx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t mark:11;
-#else
-                uint64_t mark:11;
-                uint64_t reserved_11_63:53;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t mark:9;
-#else
-                uint64_t mark:9;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx;
-        struct cvmx_gmxx_rx_bp_onx_s cn68xx;
-        struct cvmx_gmxx_rx_bp_onx_s cn68xxp1;
-        struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx;
-};
-
-union cvmx_gmxx_rx_hg2_status {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_hg2_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t phtim2go:16;
-                uint64_t xof:16;
-                uint64_t lgtim2go:16;
-#else
-                uint64_t lgtim2go:16;
-                uint64_t xof:16;
-                uint64_t phtim2go:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_hg2_status_s cn52xx;
-        struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
-        struct cvmx_gmxx_rx_hg2_status_s cn56xx;
-        struct cvmx_gmxx_rx_hg2_status_s cn61xx;
-        struct cvmx_gmxx_rx_hg2_status_s cn63xx;
-        struct cvmx_gmxx_rx_hg2_status_s cn63xxp1;
-        struct cvmx_gmxx_rx_hg2_status_s cn66xx;
-        struct cvmx_gmxx_rx_hg2_status_s cn68xx;
-        struct cvmx_gmxx_rx_hg2_status_s cn68xxp1;
-        struct cvmx_gmxx_rx_hg2_status_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_pass_en {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_pass_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t en:16;
-#else
-                uint64_t en:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_pass_en_s cn38xx;
-        struct cvmx_gmxx_rx_pass_en_s cn38xxp2;
-        struct cvmx_gmxx_rx_pass_en_s cn58xx;
-        struct cvmx_gmxx_rx_pass_en_s cn58xxp1;
-};
-
-union cvmx_gmxx_rx_pass_mapx {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_pass_mapx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t dprt:4;
-#else
-                uint64_t dprt:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_pass_mapx_s cn38xx;
-        struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;
-        struct cvmx_gmxx_rx_pass_mapx_s cn58xx;
-        struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;
-};
-
-union cvmx_gmxx_rx_prt_info {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_prt_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t drop:16;
-                uint64_t commit:16;
-#else
-                uint64_t commit:16;
-                uint64_t drop:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_prt_info_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t drop:3;
-                uint64_t reserved_3_15:13;
-                uint64_t commit:3;
-#else
-                uint64_t commit:3;
-                uint64_t reserved_3_15:13;
-                uint64_t drop:3;
-                uint64_t reserved_19_63:45;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
-        struct cvmx_gmxx_rx_prt_info_s cn38xx;
-        struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
-        struct cvmx_gmxx_rx_prt_info_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t drop:4;
-                uint64_t reserved_4_15:12;
-                uint64_t commit:4;
-#else
-                uint64_t commit:4;
-                uint64_t reserved_4_15:12;
-                uint64_t drop:4;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;
-        struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;
-        struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
-        struct cvmx_gmxx_rx_prt_info_s cn58xx;
-        struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
-        struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx;
-        struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx;
-        struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1;
-        struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx;
-        struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx;
-        struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1;
-        struct cvmx_gmxx_rx_prt_info_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_18_63:46;
-                uint64_t drop:2;
-                uint64_t reserved_2_15:14;
-                uint64_t commit:2;
-#else
-                uint64_t commit:2;
-                uint64_t reserved_2_15:14;
-                uint64_t drop:2;
-                uint64_t reserved_18_63:46;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_gmxx_rx_prts {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_prts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t prts:3;
-#else
-                uint64_t prts:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_prts_s cn30xx;
-        struct cvmx_gmxx_rx_prts_s cn31xx;
-        struct cvmx_gmxx_rx_prts_s cn38xx;
-        struct cvmx_gmxx_rx_prts_s cn38xxp2;
-        struct cvmx_gmxx_rx_prts_s cn50xx;
-        struct cvmx_gmxx_rx_prts_s cn52xx;
-        struct cvmx_gmxx_rx_prts_s cn52xxp1;
-        struct cvmx_gmxx_rx_prts_s cn56xx;
-        struct cvmx_gmxx_rx_prts_s cn56xxp1;
-        struct cvmx_gmxx_rx_prts_s cn58xx;
-        struct cvmx_gmxx_rx_prts_s cn58xxp1;
-        struct cvmx_gmxx_rx_prts_s cn61xx;
-        struct cvmx_gmxx_rx_prts_s cn63xx;
-        struct cvmx_gmxx_rx_prts_s cn63xxp1;
-        struct cvmx_gmxx_rx_prts_s cn66xx;
-        struct cvmx_gmxx_rx_prts_s cn68xx;
-        struct cvmx_gmxx_rx_prts_s cn68xxp1;
-        struct cvmx_gmxx_rx_prts_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_tx_status {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_tx_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t tx:3;
-                uint64_t reserved_3_3:1;
-                uint64_t rx:3;
-#else
-                uint64_t rx:3;
-                uint64_t reserved_3_3:1;
-                uint64_t tx:3;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_tx_status_s cn30xx;
-        struct cvmx_gmxx_rx_tx_status_s cn31xx;
-        struct cvmx_gmxx_rx_tx_status_s cn50xx;
-};
-
-union cvmx_gmxx_rx_xaui_bad_col {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_xaui_bad_col_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_40_63:24;
-                uint64_t val:1;
-                uint64_t state:3;
-                uint64_t lane_rxc:4;
-                uint64_t lane_rxd:32;
-#else
-                uint64_t lane_rxd:32;
-                uint64_t lane_rxc:4;
-                uint64_t state:3;
-                uint64_t val:1;
-                uint64_t reserved_40_63:24;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1;
-        struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_xaui_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_rx_xaui_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t status:2;
-#else
-                uint64_t status:2;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn52xx;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn61xx;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn63xx;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn66xx;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn68xx;
-        struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1;
-        struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxaui_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_rxaui_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t disparity:1;
-#else
-                uint64_t disparity:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_gmxx_rxaui_ctl_s cn68xx;
-        struct cvmx_gmxx_rxaui_ctl_s cn68xxp1;
-};
-
-union cvmx_gmxx_smacx {
-        uint64_t u64;
-        struct cvmx_gmxx_smacx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t smac:48;
-#else
-                uint64_t smac:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_smacx_s cn30xx;
-        struct cvmx_gmxx_smacx_s cn31xx;
-        struct cvmx_gmxx_smacx_s cn38xx;
-        struct cvmx_gmxx_smacx_s cn38xxp2;
-        struct cvmx_gmxx_smacx_s cn50xx;
-        struct cvmx_gmxx_smacx_s cn52xx;
-        struct cvmx_gmxx_smacx_s cn52xxp1;
-        struct cvmx_gmxx_smacx_s cn56xx;
-        struct cvmx_gmxx_smacx_s cn56xxp1;
-        struct cvmx_gmxx_smacx_s cn58xx;
-        struct cvmx_gmxx_smacx_s cn58xxp1;
-        struct cvmx_gmxx_smacx_s cn61xx;
-        struct cvmx_gmxx_smacx_s cn63xx;
-        struct cvmx_gmxx_smacx_s cn63xxp1;
-        struct cvmx_gmxx_smacx_s cn66xx;
-        struct cvmx_gmxx_smacx_s cn68xx;
-        struct cvmx_gmxx_smacx_s cn68xxp1;
-        struct cvmx_gmxx_smacx_s cnf71xx;
-};
-
-union cvmx_gmxx_soft_bist {
-        uint64_t u64;
-        struct cvmx_gmxx_soft_bist_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t start_bist:1;
-                uint64_t clear_bist:1;
-#else
-                uint64_t clear_bist:1;
-                uint64_t start_bist:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_gmxx_soft_bist_s cn63xx;
-        struct cvmx_gmxx_soft_bist_s cn63xxp1;
-        struct cvmx_gmxx_soft_bist_s cn66xx;
-        struct cvmx_gmxx_soft_bist_s cn68xx;
-        struct cvmx_gmxx_soft_bist_s cn68xxp1;
-};
-
-union cvmx_gmxx_stat_bp {
-        uint64_t u64;
-        struct cvmx_gmxx_stat_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t bp:1;
-                uint64_t cnt:16;
-#else
-                uint64_t cnt:16;
-                uint64_t bp:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_gmxx_stat_bp_s cn30xx;
-        struct cvmx_gmxx_stat_bp_s cn31xx;
-        struct cvmx_gmxx_stat_bp_s cn38xx;
-        struct cvmx_gmxx_stat_bp_s cn38xxp2;
-        struct cvmx_gmxx_stat_bp_s cn50xx;
-        struct cvmx_gmxx_stat_bp_s cn52xx;
-        struct cvmx_gmxx_stat_bp_s cn52xxp1;
-        struct cvmx_gmxx_stat_bp_s cn56xx;
-        struct cvmx_gmxx_stat_bp_s cn56xxp1;
-        struct cvmx_gmxx_stat_bp_s cn58xx;
-        struct cvmx_gmxx_stat_bp_s cn58xxp1;
-        struct cvmx_gmxx_stat_bp_s cn61xx;
-        struct cvmx_gmxx_stat_bp_s cn63xx;
-        struct cvmx_gmxx_stat_bp_s cn63xxp1;
-        struct cvmx_gmxx_stat_bp_s cn66xx;
-        struct cvmx_gmxx_stat_bp_s cn68xx;
-        struct cvmx_gmxx_stat_bp_s cn68xxp1;
-        struct cvmx_gmxx_stat_bp_s cnf71xx;
-};
-
-union cvmx_gmxx_tb_reg {
-        uint64_t u64;
-        struct cvmx_gmxx_tb_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t wr_magic:1;
-#else
-                uint64_t wr_magic:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_gmxx_tb_reg_s cn61xx;
-        struct cvmx_gmxx_tb_reg_s cn66xx;
-        struct cvmx_gmxx_tb_reg_s cn68xx;
-        struct cvmx_gmxx_tb_reg_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_append {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_append_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t force_fcs:1;
-                uint64_t fcs:1;
-                uint64_t pad:1;
-                uint64_t preamble:1;
-#else
-                uint64_t preamble:1;
-                uint64_t pad:1;
-                uint64_t fcs:1;
-                uint64_t force_fcs:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_append_s cn30xx;
-        struct cvmx_gmxx_txx_append_s cn31xx;
-        struct cvmx_gmxx_txx_append_s cn38xx;
-        struct cvmx_gmxx_txx_append_s cn38xxp2;
-        struct cvmx_gmxx_txx_append_s cn50xx;
-        struct cvmx_gmxx_txx_append_s cn52xx;
-        struct cvmx_gmxx_txx_append_s cn52xxp1;
-        struct cvmx_gmxx_txx_append_s cn56xx;
-        struct cvmx_gmxx_txx_append_s cn56xxp1;
-        struct cvmx_gmxx_txx_append_s cn58xx;
-        struct cvmx_gmxx_txx_append_s cn58xxp1;
-        struct cvmx_gmxx_txx_append_s cn61xx;
-        struct cvmx_gmxx_txx_append_s cn63xx;
-        struct cvmx_gmxx_txx_append_s cn63xxp1;
-        struct cvmx_gmxx_txx_append_s cn66xx;
-        struct cvmx_gmxx_txx_append_s cn68xx;
-        struct cvmx_gmxx_txx_append_s cn68xxp1;
-        struct cvmx_gmxx_txx_append_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_burst {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_burst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t burst:16;
-#else
-                uint64_t burst:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_burst_s cn30xx;
-        struct cvmx_gmxx_txx_burst_s cn31xx;
-        struct cvmx_gmxx_txx_burst_s cn38xx;
-        struct cvmx_gmxx_txx_burst_s cn38xxp2;
-        struct cvmx_gmxx_txx_burst_s cn50xx;
-        struct cvmx_gmxx_txx_burst_s cn52xx;
-        struct cvmx_gmxx_txx_burst_s cn52xxp1;
-        struct cvmx_gmxx_txx_burst_s cn56xx;
-        struct cvmx_gmxx_txx_burst_s cn56xxp1;
-        struct cvmx_gmxx_txx_burst_s cn58xx;
-        struct cvmx_gmxx_txx_burst_s cn58xxp1;
-        struct cvmx_gmxx_txx_burst_s cn61xx;
-        struct cvmx_gmxx_txx_burst_s cn63xx;
-        struct cvmx_gmxx_txx_burst_s cn63xxp1;
-        struct cvmx_gmxx_txx_burst_s cn66xx;
-        struct cvmx_gmxx_txx_burst_s cn68xx;
-        struct cvmx_gmxx_txx_burst_s cn68xxp1;
-        struct cvmx_gmxx_txx_burst_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_cbfc_xoff {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_cbfc_xoff_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t xoff:16;
-#else
-                uint64_t xoff:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
-        struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
-        struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx;
-        struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx;
-        struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1;
-        struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx;
-        struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx;
-        struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1;
-        struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_cbfc_xon {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_cbfc_xon_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t xon:16;
-#else
-                uint64_t xon:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
-        struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
-        struct cvmx_gmxx_txx_cbfc_xon_s cn61xx;
-        struct cvmx_gmxx_txx_cbfc_xon_s cn63xx;
-        struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1;
-        struct cvmx_gmxx_txx_cbfc_xon_s cn66xx;
-        struct cvmx_gmxx_txx_cbfc_xon_s cn68xx;
-        struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1;
-        struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_clk {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_clk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t clk_cnt:6;
-#else
-                uint64_t clk_cnt:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_clk_s cn30xx;
-        struct cvmx_gmxx_txx_clk_s cn31xx;
-        struct cvmx_gmxx_txx_clk_s cn38xx;
-        struct cvmx_gmxx_txx_clk_s cn38xxp2;
-        struct cvmx_gmxx_txx_clk_s cn50xx;
-        struct cvmx_gmxx_txx_clk_s cn58xx;
-        struct cvmx_gmxx_txx_clk_s cn58xxp1;
-};
-
-union cvmx_gmxx_txx_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t xsdef_en:1;
-                uint64_t xscol_en:1;
-#else
-                uint64_t xscol_en:1;
-                uint64_t xsdef_en:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_ctl_s cn30xx;
-        struct cvmx_gmxx_txx_ctl_s cn31xx;
-        struct cvmx_gmxx_txx_ctl_s cn38xx;
-        struct cvmx_gmxx_txx_ctl_s cn38xxp2;
-        struct cvmx_gmxx_txx_ctl_s cn50xx;
-        struct cvmx_gmxx_txx_ctl_s cn52xx;
-        struct cvmx_gmxx_txx_ctl_s cn52xxp1;
-        struct cvmx_gmxx_txx_ctl_s cn56xx;
-        struct cvmx_gmxx_txx_ctl_s cn56xxp1;
-        struct cvmx_gmxx_txx_ctl_s cn58xx;
-        struct cvmx_gmxx_txx_ctl_s cn58xxp1;
-        struct cvmx_gmxx_txx_ctl_s cn61xx;
-        struct cvmx_gmxx_txx_ctl_s cn63xx;
-        struct cvmx_gmxx_txx_ctl_s cn63xxp1;
-        struct cvmx_gmxx_txx_ctl_s cn66xx;
-        struct cvmx_gmxx_txx_ctl_s cn68xx;
-        struct cvmx_gmxx_txx_ctl_s cn68xxp1;
-        struct cvmx_gmxx_txx_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_min_pkt {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_min_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t min_size:8;
-#else
-                uint64_t min_size:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_min_pkt_s cn30xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn31xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn38xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn38xxp2;
-        struct cvmx_gmxx_txx_min_pkt_s cn50xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn52xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn52xxp1;
-        struct cvmx_gmxx_txx_min_pkt_s cn56xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
-        struct cvmx_gmxx_txx_min_pkt_s cn58xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
-        struct cvmx_gmxx_txx_min_pkt_s cn61xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn63xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn63xxp1;
-        struct cvmx_gmxx_txx_min_pkt_s cn66xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn68xx;
-        struct cvmx_gmxx_txx_min_pkt_s cn68xxp1;
-        struct cvmx_gmxx_txx_min_pkt_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pause_pkt_interval {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t interval:16;
-#else
-                uint64_t interval:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pause_pkt_time {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_pause_pkt_time_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t time:16;
-#else
-                uint64_t time:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1;
-        struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pause_togo {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_pause_togo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t msg_time:16;
-                uint64_t time:16;
-#else
-                uint64_t time:16;
-                uint64_t msg_time:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_pause_togo_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t time:16;
-#else
-                uint64_t time:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
-        struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
-        struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
-        struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
-        struct cvmx_gmxx_txx_pause_togo_s cn52xx;
-        struct cvmx_gmxx_txx_pause_togo_s cn52xxp1;
-        struct cvmx_gmxx_txx_pause_togo_s cn56xx;
-        struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
-        struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
-        struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
-        struct cvmx_gmxx_txx_pause_togo_s cn61xx;
-        struct cvmx_gmxx_txx_pause_togo_s cn63xx;
-        struct cvmx_gmxx_txx_pause_togo_s cn63xxp1;
-        struct cvmx_gmxx_txx_pause_togo_s cn66xx;
-        struct cvmx_gmxx_txx_pause_togo_s cn68xx;
-        struct cvmx_gmxx_txx_pause_togo_s cn68xxp1;
-        struct cvmx_gmxx_txx_pause_togo_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pause_zero {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_pause_zero_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t send:1;
-#else
-                uint64_t send:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_pause_zero_s cn30xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn31xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn38xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn38xxp2;
-        struct cvmx_gmxx_txx_pause_zero_s cn50xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn52xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn52xxp1;
-        struct cvmx_gmxx_txx_pause_zero_s cn56xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
-        struct cvmx_gmxx_txx_pause_zero_s cn58xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
-        struct cvmx_gmxx_txx_pause_zero_s cn61xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn63xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn63xxp1;
-        struct cvmx_gmxx_txx_pause_zero_s cn66xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn68xx;
-        struct cvmx_gmxx_txx_pause_zero_s cn68xxp1;
-        struct cvmx_gmxx_txx_pause_zero_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pipe {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_pipe_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t ign_bp:1;
-                uint64_t reserved_21_31:11;
-                uint64_t nump:5;
-                uint64_t reserved_7_15:9;
-                uint64_t base:7;
-#else
-                uint64_t base:7;
-                uint64_t reserved_7_15:9;
-                uint64_t nump:5;
-                uint64_t reserved_21_31:11;
-                uint64_t ign_bp:1;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_pipe_s cn68xx;
-        struct cvmx_gmxx_txx_pipe_s cn68xxp1;
-};
-
-union cvmx_gmxx_txx_sgmii_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_sgmii_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t align:1;
-#else
-                uint64_t align:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1;
-        struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_slot {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_slot_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t slot:10;
-#else
-                uint64_t slot:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_slot_s cn30xx;
-        struct cvmx_gmxx_txx_slot_s cn31xx;
-        struct cvmx_gmxx_txx_slot_s cn38xx;
-        struct cvmx_gmxx_txx_slot_s cn38xxp2;
-        struct cvmx_gmxx_txx_slot_s cn50xx;
-        struct cvmx_gmxx_txx_slot_s cn52xx;
-        struct cvmx_gmxx_txx_slot_s cn52xxp1;
-        struct cvmx_gmxx_txx_slot_s cn56xx;
-        struct cvmx_gmxx_txx_slot_s cn56xxp1;
-        struct cvmx_gmxx_txx_slot_s cn58xx;
-        struct cvmx_gmxx_txx_slot_s cn58xxp1;
-        struct cvmx_gmxx_txx_slot_s cn61xx;
-        struct cvmx_gmxx_txx_slot_s cn63xx;
-        struct cvmx_gmxx_txx_slot_s cn63xxp1;
-        struct cvmx_gmxx_txx_slot_s cn66xx;
-        struct cvmx_gmxx_txx_slot_s cn68xx;
-        struct cvmx_gmxx_txx_slot_s cn68xxp1;
-        struct cvmx_gmxx_txx_slot_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_soft_pause {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_soft_pause_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t time:16;
-#else
-                uint64_t time:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_soft_pause_s cn30xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn31xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn38xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn38xxp2;
-        struct cvmx_gmxx_txx_soft_pause_s cn50xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn52xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn52xxp1;
-        struct cvmx_gmxx_txx_soft_pause_s cn56xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
-        struct cvmx_gmxx_txx_soft_pause_s cn58xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
-        struct cvmx_gmxx_txx_soft_pause_s cn61xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn63xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn63xxp1;
-        struct cvmx_gmxx_txx_soft_pause_s cn66xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn68xx;
-        struct cvmx_gmxx_txx_soft_pause_s cn68xxp1;
-        struct cvmx_gmxx_txx_soft_pause_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat0 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t xsdef:32;
-                uint64_t xscol:32;
-#else
-                uint64_t xscol:32;
-                uint64_t xsdef:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat0_s cn30xx;
-        struct cvmx_gmxx_txx_stat0_s cn31xx;
-        struct cvmx_gmxx_txx_stat0_s cn38xx;
-        struct cvmx_gmxx_txx_stat0_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat0_s cn50xx;
-        struct cvmx_gmxx_txx_stat0_s cn52xx;
-        struct cvmx_gmxx_txx_stat0_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat0_s cn56xx;
-        struct cvmx_gmxx_txx_stat0_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat0_s cn58xx;
-        struct cvmx_gmxx_txx_stat0_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat0_s cn61xx;
-        struct cvmx_gmxx_txx_stat0_s cn63xx;
-        struct cvmx_gmxx_txx_stat0_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat0_s cn66xx;
-        struct cvmx_gmxx_txx_stat0_s cn68xx;
-        struct cvmx_gmxx_txx_stat0_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat0_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat1 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t scol:32;
-                uint64_t mcol:32;
-#else
-                uint64_t mcol:32;
-                uint64_t scol:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat1_s cn30xx;
-        struct cvmx_gmxx_txx_stat1_s cn31xx;
-        struct cvmx_gmxx_txx_stat1_s cn38xx;
-        struct cvmx_gmxx_txx_stat1_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat1_s cn50xx;
-        struct cvmx_gmxx_txx_stat1_s cn52xx;
-        struct cvmx_gmxx_txx_stat1_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat1_s cn56xx;
-        struct cvmx_gmxx_txx_stat1_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat1_s cn58xx;
-        struct cvmx_gmxx_txx_stat1_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat1_s cn61xx;
-        struct cvmx_gmxx_txx_stat1_s cn63xx;
-        struct cvmx_gmxx_txx_stat1_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat1_s cn66xx;
-        struct cvmx_gmxx_txx_stat1_s cn68xx;
-        struct cvmx_gmxx_txx_stat1_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat1_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat2 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t octs:48;
-#else
-                uint64_t octs:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat2_s cn30xx;
-        struct cvmx_gmxx_txx_stat2_s cn31xx;
-        struct cvmx_gmxx_txx_stat2_s cn38xx;
-        struct cvmx_gmxx_txx_stat2_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat2_s cn50xx;
-        struct cvmx_gmxx_txx_stat2_s cn52xx;
-        struct cvmx_gmxx_txx_stat2_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat2_s cn56xx;
-        struct cvmx_gmxx_txx_stat2_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat2_s cn58xx;
-        struct cvmx_gmxx_txx_stat2_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat2_s cn61xx;
-        struct cvmx_gmxx_txx_stat2_s cn63xx;
-        struct cvmx_gmxx_txx_stat2_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat2_s cn66xx;
-        struct cvmx_gmxx_txx_stat2_s cn68xx;
-        struct cvmx_gmxx_txx_stat2_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat2_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat3 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t pkts:32;
-#else
-                uint64_t pkts:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat3_s cn30xx;
-        struct cvmx_gmxx_txx_stat3_s cn31xx;
-        struct cvmx_gmxx_txx_stat3_s cn38xx;
-        struct cvmx_gmxx_txx_stat3_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat3_s cn50xx;
-        struct cvmx_gmxx_txx_stat3_s cn52xx;
-        struct cvmx_gmxx_txx_stat3_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat3_s cn56xx;
-        struct cvmx_gmxx_txx_stat3_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat3_s cn58xx;
-        struct cvmx_gmxx_txx_stat3_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat3_s cn61xx;
-        struct cvmx_gmxx_txx_stat3_s cn63xx;
-        struct cvmx_gmxx_txx_stat3_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat3_s cn66xx;
-        struct cvmx_gmxx_txx_stat3_s cn68xx;
-        struct cvmx_gmxx_txx_stat3_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat3_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat4 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t hist1:32;
-                uint64_t hist0:32;
-#else
-                uint64_t hist0:32;
-                uint64_t hist1:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat4_s cn30xx;
-        struct cvmx_gmxx_txx_stat4_s cn31xx;
-        struct cvmx_gmxx_txx_stat4_s cn38xx;
-        struct cvmx_gmxx_txx_stat4_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat4_s cn50xx;
-        struct cvmx_gmxx_txx_stat4_s cn52xx;
-        struct cvmx_gmxx_txx_stat4_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat4_s cn56xx;
-        struct cvmx_gmxx_txx_stat4_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat4_s cn58xx;
-        struct cvmx_gmxx_txx_stat4_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat4_s cn61xx;
-        struct cvmx_gmxx_txx_stat4_s cn63xx;
-        struct cvmx_gmxx_txx_stat4_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat4_s cn66xx;
-        struct cvmx_gmxx_txx_stat4_s cn68xx;
-        struct cvmx_gmxx_txx_stat4_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat4_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat5 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat5_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t hist3:32;
-                uint64_t hist2:32;
-#else
-                uint64_t hist2:32;
-                uint64_t hist3:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat5_s cn30xx;
-        struct cvmx_gmxx_txx_stat5_s cn31xx;
-        struct cvmx_gmxx_txx_stat5_s cn38xx;
-        struct cvmx_gmxx_txx_stat5_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat5_s cn50xx;
-        struct cvmx_gmxx_txx_stat5_s cn52xx;
-        struct cvmx_gmxx_txx_stat5_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat5_s cn56xx;
-        struct cvmx_gmxx_txx_stat5_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat5_s cn58xx;
-        struct cvmx_gmxx_txx_stat5_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat5_s cn61xx;
-        struct cvmx_gmxx_txx_stat5_s cn63xx;
-        struct cvmx_gmxx_txx_stat5_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat5_s cn66xx;
-        struct cvmx_gmxx_txx_stat5_s cn68xx;
-        struct cvmx_gmxx_txx_stat5_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat5_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat6 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat6_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t hist5:32;
-                uint64_t hist4:32;
-#else
-                uint64_t hist4:32;
-                uint64_t hist5:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat6_s cn30xx;
-        struct cvmx_gmxx_txx_stat6_s cn31xx;
-        struct cvmx_gmxx_txx_stat6_s cn38xx;
-        struct cvmx_gmxx_txx_stat6_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat6_s cn50xx;
-        struct cvmx_gmxx_txx_stat6_s cn52xx;
-        struct cvmx_gmxx_txx_stat6_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat6_s cn56xx;
-        struct cvmx_gmxx_txx_stat6_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat6_s cn58xx;
-        struct cvmx_gmxx_txx_stat6_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat6_s cn61xx;
-        struct cvmx_gmxx_txx_stat6_s cn63xx;
-        struct cvmx_gmxx_txx_stat6_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat6_s cn66xx;
-        struct cvmx_gmxx_txx_stat6_s cn68xx;
-        struct cvmx_gmxx_txx_stat6_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat6_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat7 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat7_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t hist7:32;
-                uint64_t hist6:32;
-#else
-                uint64_t hist6:32;
-                uint64_t hist7:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat7_s cn30xx;
-        struct cvmx_gmxx_txx_stat7_s cn31xx;
-        struct cvmx_gmxx_txx_stat7_s cn38xx;
-        struct cvmx_gmxx_txx_stat7_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat7_s cn50xx;
-        struct cvmx_gmxx_txx_stat7_s cn52xx;
-        struct cvmx_gmxx_txx_stat7_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat7_s cn56xx;
-        struct cvmx_gmxx_txx_stat7_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat7_s cn58xx;
-        struct cvmx_gmxx_txx_stat7_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat7_s cn61xx;
-        struct cvmx_gmxx_txx_stat7_s cn63xx;
-        struct cvmx_gmxx_txx_stat7_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat7_s cn66xx;
-        struct cvmx_gmxx_txx_stat7_s cn68xx;
-        struct cvmx_gmxx_txx_stat7_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat7_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat8 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat8_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t mcst:32;
-                uint64_t bcst:32;
-#else
-                uint64_t bcst:32;
-                uint64_t mcst:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat8_s cn30xx;
-        struct cvmx_gmxx_txx_stat8_s cn31xx;
-        struct cvmx_gmxx_txx_stat8_s cn38xx;
-        struct cvmx_gmxx_txx_stat8_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat8_s cn50xx;
-        struct cvmx_gmxx_txx_stat8_s cn52xx;
-        struct cvmx_gmxx_txx_stat8_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat8_s cn56xx;
-        struct cvmx_gmxx_txx_stat8_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat8_s cn58xx;
-        struct cvmx_gmxx_txx_stat8_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat8_s cn61xx;
-        struct cvmx_gmxx_txx_stat8_s cn63xx;
-        struct cvmx_gmxx_txx_stat8_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat8_s cn66xx;
-        struct cvmx_gmxx_txx_stat8_s cn68xx;
-        struct cvmx_gmxx_txx_stat8_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat8_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat9 {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stat9_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t undflw:32;
-                uint64_t ctl:32;
-#else
-                uint64_t ctl:32;
-                uint64_t undflw:32;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stat9_s cn30xx;
-        struct cvmx_gmxx_txx_stat9_s cn31xx;
-        struct cvmx_gmxx_txx_stat9_s cn38xx;
-        struct cvmx_gmxx_txx_stat9_s cn38xxp2;
-        struct cvmx_gmxx_txx_stat9_s cn50xx;
-        struct cvmx_gmxx_txx_stat9_s cn52xx;
-        struct cvmx_gmxx_txx_stat9_s cn52xxp1;
-        struct cvmx_gmxx_txx_stat9_s cn56xx;
-        struct cvmx_gmxx_txx_stat9_s cn56xxp1;
-        struct cvmx_gmxx_txx_stat9_s cn58xx;
-        struct cvmx_gmxx_txx_stat9_s cn58xxp1;
-        struct cvmx_gmxx_txx_stat9_s cn61xx;
-        struct cvmx_gmxx_txx_stat9_s cn63xx;
-        struct cvmx_gmxx_txx_stat9_s cn63xxp1;
-        struct cvmx_gmxx_txx_stat9_s cn66xx;
-        struct cvmx_gmxx_txx_stat9_s cn68xx;
-        struct cvmx_gmxx_txx_stat9_s cn68xxp1;
-        struct cvmx_gmxx_txx_stat9_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stats_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_stats_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t rd_clr:1;
-#else
-                uint64_t rd_clr:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_stats_ctl_s cn30xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn31xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn38xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;
-        struct cvmx_gmxx_txx_stats_ctl_s cn50xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn52xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;
-        struct cvmx_gmxx_txx_stats_ctl_s cn56xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
-        struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
-        struct cvmx_gmxx_txx_stats_ctl_s cn61xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn63xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1;
-        struct cvmx_gmxx_txx_stats_ctl_s cn66xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn68xx;
-        struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1;
-        struct cvmx_gmxx_txx_stats_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_thresh {
-        uint64_t u64;
-        struct cvmx_gmxx_txx_thresh_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t cnt:10;
-#else
-                uint64_t cnt:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } s;
-        struct cvmx_gmxx_txx_thresh_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t cnt:7;
-#else
-                uint64_t cnt:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
-        struct cvmx_gmxx_txx_thresh_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t cnt:9;
-#else
-                uint64_t cnt:9;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn38xx;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2;
-        struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn52xx;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn56xx;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn58xx;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn61xx;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn63xx;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1;
-        struct cvmx_gmxx_txx_thresh_cn38xx cn66xx;
-        struct cvmx_gmxx_txx_thresh_s cn68xx;
-        struct cvmx_gmxx_txx_thresh_s cn68xxp1;
-        struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx;
-};
-
-union cvmx_gmxx_tx_bp {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t bp:4;
-#else
-                uint64_t bp:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_bp_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t bp:3;
-#else
-                uint64_t bp:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_tx_bp_cn30xx cn31xx;
-        struct cvmx_gmxx_tx_bp_s cn38xx;
-        struct cvmx_gmxx_tx_bp_s cn38xxp2;
-        struct cvmx_gmxx_tx_bp_cn30xx cn50xx;
-        struct cvmx_gmxx_tx_bp_s cn52xx;
-        struct cvmx_gmxx_tx_bp_s cn52xxp1;
-        struct cvmx_gmxx_tx_bp_s cn56xx;
-        struct cvmx_gmxx_tx_bp_s cn56xxp1;
-        struct cvmx_gmxx_tx_bp_s cn58xx;
-        struct cvmx_gmxx_tx_bp_s cn58xxp1;
-        struct cvmx_gmxx_tx_bp_s cn61xx;
-        struct cvmx_gmxx_tx_bp_s cn63xx;
-        struct cvmx_gmxx_tx_bp_s cn63xxp1;
-        struct cvmx_gmxx_tx_bp_s cn66xx;
-        struct cvmx_gmxx_tx_bp_s cn68xx;
-        struct cvmx_gmxx_tx_bp_s cn68xxp1;
-        struct cvmx_gmxx_tx_bp_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t bp:2;
-#else
-                uint64_t bp:2;
-                uint64_t reserved_2_63:62;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_gmxx_tx_clk_mskx {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_clk_mskx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t msk:1;
-#else
-                uint64_t msk:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_clk_mskx_s cn30xx;
-        struct cvmx_gmxx_tx_clk_mskx_s cn50xx;
-};
-
-union cvmx_gmxx_tx_col_attempt {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_col_attempt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t limit:5;
-#else
-                uint64_t limit:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_col_attempt_s cn30xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn31xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn38xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn38xxp2;
-        struct cvmx_gmxx_tx_col_attempt_s cn50xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn52xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn52xxp1;
-        struct cvmx_gmxx_tx_col_attempt_s cn56xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
-        struct cvmx_gmxx_tx_col_attempt_s cn58xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
-        struct cvmx_gmxx_tx_col_attempt_s cn61xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn63xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn63xxp1;
-        struct cvmx_gmxx_tx_col_attempt_s cn66xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn68xx;
-        struct cvmx_gmxx_tx_col_attempt_s cn68xxp1;
-        struct cvmx_gmxx_tx_col_attempt_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_corrupt {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_corrupt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t corrupt:4;
-#else
-                uint64_t corrupt:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_corrupt_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t corrupt:3;
-#else
-                uint64_t corrupt:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;
-        struct cvmx_gmxx_tx_corrupt_s cn38xx;
-        struct cvmx_gmxx_tx_corrupt_s cn38xxp2;
-        struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;
-        struct cvmx_gmxx_tx_corrupt_s cn52xx;
-        struct cvmx_gmxx_tx_corrupt_s cn52xxp1;
-        struct cvmx_gmxx_tx_corrupt_s cn56xx;
-        struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
-        struct cvmx_gmxx_tx_corrupt_s cn58xx;
-        struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
-        struct cvmx_gmxx_tx_corrupt_s cn61xx;
-        struct cvmx_gmxx_tx_corrupt_s cn63xx;
-        struct cvmx_gmxx_tx_corrupt_s cn63xxp1;
-        struct cvmx_gmxx_tx_corrupt_s cn66xx;
-        struct cvmx_gmxx_tx_corrupt_s cn68xx;
-        struct cvmx_gmxx_tx_corrupt_s cn68xxp1;
-        struct cvmx_gmxx_tx_corrupt_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t corrupt:2;
-#else
-                uint64_t corrupt:2;
-                uint64_t reserved_2_63:62;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_gmxx_tx_hg2_reg1 {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_hg2_reg1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t tx_xof:16;
-#else
-                uint64_t tx_xof:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
-        struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
-        struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
-        struct cvmx_gmxx_tx_hg2_reg1_s cn61xx;
-        struct cvmx_gmxx_tx_hg2_reg1_s cn63xx;
-        struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1;
-        struct cvmx_gmxx_tx_hg2_reg1_s cn66xx;
-        struct cvmx_gmxx_tx_hg2_reg1_s cn68xx;
-        struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1;
-        struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_hg2_reg2 {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_hg2_reg2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t tx_xon:16;
-#else
-                uint64_t tx_xon:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
-        struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
-        struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
-        struct cvmx_gmxx_tx_hg2_reg2_s cn61xx;
-        struct cvmx_gmxx_tx_hg2_reg2_s cn63xx;
-        struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1;
-        struct cvmx_gmxx_tx_hg2_reg2_s cn66xx;
-        struct cvmx_gmxx_tx_hg2_reg2_s cn68xx;
-        struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1;
-        struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_ifg {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_ifg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t ifg2:4;
-                uint64_t ifg1:4;
-#else
-                uint64_t ifg1:4;
-                uint64_t ifg2:4;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_ifg_s cn30xx;
-        struct cvmx_gmxx_tx_ifg_s cn31xx;
-        struct cvmx_gmxx_tx_ifg_s cn38xx;
-        struct cvmx_gmxx_tx_ifg_s cn38xxp2;
-        struct cvmx_gmxx_tx_ifg_s cn50xx;
-        struct cvmx_gmxx_tx_ifg_s cn52xx;
-        struct cvmx_gmxx_tx_ifg_s cn52xxp1;
-        struct cvmx_gmxx_tx_ifg_s cn56xx;
-        struct cvmx_gmxx_tx_ifg_s cn56xxp1;
-        struct cvmx_gmxx_tx_ifg_s cn58xx;
-        struct cvmx_gmxx_tx_ifg_s cn58xxp1;
-        struct cvmx_gmxx_tx_ifg_s cn61xx;
-        struct cvmx_gmxx_tx_ifg_s cn63xx;
-        struct cvmx_gmxx_tx_ifg_s cn63xxp1;
-        struct cvmx_gmxx_tx_ifg_s cn66xx;
-        struct cvmx_gmxx_tx_ifg_s cn68xx;
-        struct cvmx_gmxx_tx_ifg_s cn68xxp1;
-        struct cvmx_gmxx_tx_ifg_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_int_en {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t xchange:1;
-                uint64_t ptp_lost:4;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t ptp_lost:4;
-                uint64_t xchange:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_int_en_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t late_col:3;
-                uint64_t reserved_15_15:1;
-                uint64_t xsdef:3;
-                uint64_t reserved_11_11:1;
-                uint64_t xscol:3;
-                uint64_t reserved_5_7:3;
-                uint64_t undflw:3;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:3;
-                uint64_t reserved_5_7:3;
-                uint64_t xscol:3;
-                uint64_t reserved_11_11:1;
-                uint64_t xsdef:3;
-                uint64_t reserved_15_15:1;
-                uint64_t late_col:3;
-                uint64_t reserved_19_63:45;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_tx_int_en_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t xsdef:3;
-                uint64_t reserved_11_11:1;
-                uint64_t xscol:3;
-                uint64_t reserved_5_7:3;
-                uint64_t undflw:3;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:3;
-                uint64_t reserved_5_7:3;
-                uint64_t xscol:3;
-                uint64_t reserved_11_11:1;
-                uint64_t xsdef:3;
-                uint64_t reserved_15_63:49;
-#endif
-        } cn31xx;
-        struct cvmx_gmxx_tx_int_en_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t ncb_nxa:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t ncb_nxa:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn38xx;
-        struct cvmx_gmxx_tx_int_en_cn38xxp2 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t ncb_nxa:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t ncb_nxa:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn38xxp2;
-        struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
-        struct cvmx_gmxx_tx_int_en_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;
-        struct cvmx_gmxx_tx_int_en_cn52xx cn56xx;
-        struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
-        struct cvmx_gmxx_tx_int_en_cn38xx cn58xx;
-        struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1;
-        struct cvmx_gmxx_tx_int_en_s cn61xx;
-        struct cvmx_gmxx_tx_int_en_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t ptp_lost:4;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t ptp_lost:4;
-                uint64_t reserved_24_63:40;
-#endif
-        } cn63xx;
-        struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1;
-        struct cvmx_gmxx_tx_int_en_s cn66xx;
-        struct cvmx_gmxx_tx_int_en_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t xchange:1;
-                uint64_t ptp_lost:4;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t pko_nxp:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t pko_nxp:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t ptp_lost:4;
-                uint64_t xchange:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } cn68xx;
-        struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1;
-        struct cvmx_gmxx_tx_int_en_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t xchange:1;
-                uint64_t reserved_22_23:2;
-                uint64_t ptp_lost:2;
-                uint64_t reserved_18_19:2;
-                uint64_t late_col:2;
-                uint64_t reserved_14_15:2;
-                uint64_t xsdef:2;
-                uint64_t reserved_10_11:2;
-                uint64_t xscol:2;
-                uint64_t reserved_4_7:4;
-                uint64_t undflw:2;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:2;
-                uint64_t reserved_4_7:4;
-                uint64_t xscol:2;
-                uint64_t reserved_10_11:2;
-                uint64_t xsdef:2;
-                uint64_t reserved_14_15:2;
-                uint64_t late_col:2;
-                uint64_t reserved_18_19:2;
-                uint64_t ptp_lost:2;
-                uint64_t reserved_22_23:2;
-                uint64_t xchange:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_gmxx_tx_int_reg {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t xchange:1;
-                uint64_t ptp_lost:4;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t ptp_lost:4;
-                uint64_t xchange:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_int_reg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t late_col:3;
-                uint64_t reserved_15_15:1;
-                uint64_t xsdef:3;
-                uint64_t reserved_11_11:1;
-                uint64_t xscol:3;
-                uint64_t reserved_5_7:3;
-                uint64_t undflw:3;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:3;
-                uint64_t reserved_5_7:3;
-                uint64_t xscol:3;
-                uint64_t reserved_11_11:1;
-                uint64_t xsdef:3;
-                uint64_t reserved_15_15:1;
-                uint64_t late_col:3;
-                uint64_t reserved_19_63:45;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_tx_int_reg_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t xsdef:3;
-                uint64_t reserved_11_11:1;
-                uint64_t xscol:3;
-                uint64_t reserved_5_7:3;
-                uint64_t undflw:3;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:3;
-                uint64_t reserved_5_7:3;
-                uint64_t xscol:3;
-                uint64_t reserved_11_11:1;
-                uint64_t xsdef:3;
-                uint64_t reserved_15_63:49;
-#endif
-        } cn31xx;
-        struct cvmx_gmxx_tx_int_reg_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t ncb_nxa:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t ncb_nxa:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn38xx;
-        struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t ncb_nxa:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t ncb_nxa:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn38xxp2;
-        struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
-        struct cvmx_gmxx_tx_int_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn52xx;
-        struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;
-        struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;
-        struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
-        struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx;
-        struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1;
-        struct cvmx_gmxx_tx_int_reg_s cn61xx;
-        struct cvmx_gmxx_tx_int_reg_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t ptp_lost:4;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t ptp_lost:4;
-                uint64_t reserved_24_63:40;
-#endif
-        } cn63xx;
-        struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1;
-        struct cvmx_gmxx_tx_int_reg_s cn66xx;
-        struct cvmx_gmxx_tx_int_reg_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t xchange:1;
-                uint64_t ptp_lost:4;
-                uint64_t late_col:4;
-                uint64_t xsdef:4;
-                uint64_t xscol:4;
-                uint64_t reserved_6_7:2;
-                uint64_t undflw:4;
-                uint64_t pko_nxp:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t pko_nxp:1;
-                uint64_t undflw:4;
-                uint64_t reserved_6_7:2;
-                uint64_t xscol:4;
-                uint64_t xsdef:4;
-                uint64_t late_col:4;
-                uint64_t ptp_lost:4;
-                uint64_t xchange:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } cn68xx;
-        struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1;
-        struct cvmx_gmxx_tx_int_reg_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t xchange:1;
-                uint64_t reserved_22_23:2;
-                uint64_t ptp_lost:2;
-                uint64_t reserved_18_19:2;
-                uint64_t late_col:2;
-                uint64_t reserved_14_15:2;
-                uint64_t xsdef:2;
-                uint64_t reserved_10_11:2;
-                uint64_t xscol:2;
-                uint64_t reserved_4_7:4;
-                uint64_t undflw:2;
-                uint64_t reserved_1_1:1;
-                uint64_t pko_nxa:1;
-#else
-                uint64_t pko_nxa:1;
-                uint64_t reserved_1_1:1;
-                uint64_t undflw:2;
-                uint64_t reserved_4_7:4;
-                uint64_t xscol:2;
-                uint64_t reserved_10_11:2;
-                uint64_t xsdef:2;
-                uint64_t reserved_14_15:2;
-                uint64_t late_col:2;
-                uint64_t reserved_18_19:2;
-                uint64_t ptp_lost:2;
-                uint64_t reserved_22_23:2;
-                uint64_t xchange:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_gmxx_tx_jam {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_jam_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t jam:8;
-#else
-                uint64_t jam:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_jam_s cn30xx;
-        struct cvmx_gmxx_tx_jam_s cn31xx;
-        struct cvmx_gmxx_tx_jam_s cn38xx;
-        struct cvmx_gmxx_tx_jam_s cn38xxp2;
-        struct cvmx_gmxx_tx_jam_s cn50xx;
-        struct cvmx_gmxx_tx_jam_s cn52xx;
-        struct cvmx_gmxx_tx_jam_s cn52xxp1;
-        struct cvmx_gmxx_tx_jam_s cn56xx;
-        struct cvmx_gmxx_tx_jam_s cn56xxp1;
-        struct cvmx_gmxx_tx_jam_s cn58xx;
-        struct cvmx_gmxx_tx_jam_s cn58xxp1;
-        struct cvmx_gmxx_tx_jam_s cn61xx;
-        struct cvmx_gmxx_tx_jam_s cn63xx;
-        struct cvmx_gmxx_tx_jam_s cn63xxp1;
-        struct cvmx_gmxx_tx_jam_s cn66xx;
-        struct cvmx_gmxx_tx_jam_s cn68xx;
-        struct cvmx_gmxx_tx_jam_s cn68xxp1;
-        struct cvmx_gmxx_tx_jam_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_lfsr {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_lfsr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t lfsr:16;
-#else
-                uint64_t lfsr:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_lfsr_s cn30xx;
-        struct cvmx_gmxx_tx_lfsr_s cn31xx;
-        struct cvmx_gmxx_tx_lfsr_s cn38xx;
-        struct cvmx_gmxx_tx_lfsr_s cn38xxp2;
-        struct cvmx_gmxx_tx_lfsr_s cn50xx;
-        struct cvmx_gmxx_tx_lfsr_s cn52xx;
-        struct cvmx_gmxx_tx_lfsr_s cn52xxp1;
-        struct cvmx_gmxx_tx_lfsr_s cn56xx;
-        struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
-        struct cvmx_gmxx_tx_lfsr_s cn58xx;
-        struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
-        struct cvmx_gmxx_tx_lfsr_s cn61xx;
-        struct cvmx_gmxx_tx_lfsr_s cn63xx;
-        struct cvmx_gmxx_tx_lfsr_s cn63xxp1;
-        struct cvmx_gmxx_tx_lfsr_s cn66xx;
-        struct cvmx_gmxx_tx_lfsr_s cn68xx;
-        struct cvmx_gmxx_tx_lfsr_s cn68xxp1;
-        struct cvmx_gmxx_tx_lfsr_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_ovr_bp {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_ovr_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t tx_prt_bp:16;
-                uint64_t reserved_12_31:20;
-                uint64_t en:4;
-                uint64_t bp:4;
-                uint64_t ign_full:4;
-#else
-                uint64_t ign_full:4;
-                uint64_t bp:4;
-                uint64_t en:4;
-                uint64_t reserved_12_31:20;
-                uint64_t tx_prt_bp:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_ovr_bp_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t en:3;
-                uint64_t reserved_7_7:1;
-                uint64_t bp:3;
-                uint64_t reserved_3_3:1;
-                uint64_t ign_full:3;
-#else
-                uint64_t ign_full:3;
-                uint64_t reserved_3_3:1;
-                uint64_t bp:3;
-                uint64_t reserved_7_7:1;
-                uint64_t en:3;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn30xx;
-        struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
-        struct cvmx_gmxx_tx_ovr_bp_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t en:4;
-                uint64_t bp:4;
-                uint64_t ign_full:4;
-#else
-                uint64_t ign_full:4;
-                uint64_t bp:4;
-                uint64_t en:4;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn38xx;
-        struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;
-        struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;
-        struct cvmx_gmxx_tx_ovr_bp_s cn52xx;
-        struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;
-        struct cvmx_gmxx_tx_ovr_bp_s cn56xx;
-        struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
-        struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
-        struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
-        struct cvmx_gmxx_tx_ovr_bp_s cn61xx;
-        struct cvmx_gmxx_tx_ovr_bp_s cn63xx;
-        struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1;
-        struct cvmx_gmxx_tx_ovr_bp_s cn66xx;
-        struct cvmx_gmxx_tx_ovr_bp_s cn68xx;
-        struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1;
-        struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t tx_prt_bp:16;
-                uint64_t reserved_10_31:22;
-                uint64_t en:2;
-                uint64_t reserved_6_7:2;
-                uint64_t bp:2;
-                uint64_t reserved_2_3:2;
-                uint64_t ign_full:2;
-#else
-                uint64_t ign_full:2;
-                uint64_t reserved_2_3:2;
-                uint64_t bp:2;
-                uint64_t reserved_6_7:2;
-                uint64_t en:2;
-                uint64_t reserved_10_31:22;
-                uint64_t tx_prt_bp:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } cnf71xx;
-};
-
-union cvmx_gmxx_tx_pause_pkt_dmac {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t dmac:48;
-#else
-                uint64_t dmac:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_pause_pkt_type {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_pause_pkt_type_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t type:16;
-#else
-                uint64_t type:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1;
-        struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_prts {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_prts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t prts:5;
-#else
-                uint64_t prts:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_prts_s cn30xx;
-        struct cvmx_gmxx_tx_prts_s cn31xx;
-        struct cvmx_gmxx_tx_prts_s cn38xx;
-        struct cvmx_gmxx_tx_prts_s cn38xxp2;
-        struct cvmx_gmxx_tx_prts_s cn50xx;
-        struct cvmx_gmxx_tx_prts_s cn52xx;
-        struct cvmx_gmxx_tx_prts_s cn52xxp1;
-        struct cvmx_gmxx_tx_prts_s cn56xx;
-        struct cvmx_gmxx_tx_prts_s cn56xxp1;
-        struct cvmx_gmxx_tx_prts_s cn58xx;
-        struct cvmx_gmxx_tx_prts_s cn58xxp1;
-        struct cvmx_gmxx_tx_prts_s cn61xx;
-        struct cvmx_gmxx_tx_prts_s cn63xx;
-        struct cvmx_gmxx_tx_prts_s cn63xxp1;
-        struct cvmx_gmxx_tx_prts_s cn66xx;
-        struct cvmx_gmxx_tx_prts_s cn68xx;
-        struct cvmx_gmxx_tx_prts_s cn68xxp1;
-        struct cvmx_gmxx_tx_prts_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_spi_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_spi_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t tpa_clr:1;
-                uint64_t cont_pkt:1;
-#else
-                uint64_t cont_pkt:1;
-                uint64_t tpa_clr:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_spi_ctl_s cn38xx;
-        struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;
-        struct cvmx_gmxx_tx_spi_ctl_s cn58xx;
-        struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;
-};
-
-union cvmx_gmxx_tx_spi_drain {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_spi_drain_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t drain:16;
-#else
-                uint64_t drain:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_spi_drain_s cn38xx;
-        struct cvmx_gmxx_tx_spi_drain_s cn58xx;
-        struct cvmx_gmxx_tx_spi_drain_s cn58xxp1;
-};
-
-union cvmx_gmxx_tx_spi_max {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_spi_max_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t slice:7;
-                uint64_t max2:8;
-                uint64_t max1:8;
-#else
-                uint64_t max1:8;
-                uint64_t max2:8;
-                uint64_t slice:7;
-                uint64_t reserved_23_63:41;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_spi_max_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t max2:8;
-                uint64_t max1:8;
-#else
-                uint64_t max1:8;
-                uint64_t max2:8;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn38xx;
-        struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;
-        struct cvmx_gmxx_tx_spi_max_s cn58xx;
-        struct cvmx_gmxx_tx_spi_max_s cn58xxp1;
-};
-
-union cvmx_gmxx_tx_spi_roundx {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_spi_roundx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t round:16;
-#else
-                uint64_t round:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_spi_roundx_s cn58xx;
-        struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;
-};
-
-union cvmx_gmxx_tx_spi_thresh {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_spi_thresh_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t thresh:6;
-#else
-                uint64_t thresh:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_spi_thresh_s cn38xx;
-        struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;
-        struct cvmx_gmxx_tx_spi_thresh_s cn58xx;
-        struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;
-};
-
-union cvmx_gmxx_tx_xaui_ctl {
-        uint64_t u64;
-        struct cvmx_gmxx_tx_xaui_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t hg_pause_hgi:2;
-                uint64_t hg_en:1;
-                uint64_t reserved_7_7:1;
-                uint64_t ls_byp:1;
-                uint64_t ls:2;
-                uint64_t reserved_2_3:2;
-                uint64_t uni_en:1;
-                uint64_t dic_en:1;
-#else
-                uint64_t dic_en:1;
-                uint64_t uni_en:1;
-                uint64_t reserved_2_3:2;
-                uint64_t ls:2;
-                uint64_t ls_byp:1;
-                uint64_t reserved_7_7:1;
-                uint64_t hg_en:1;
-                uint64_t hg_pause_hgi:2;
-                uint64_t reserved_11_63:53;
-#endif
-        } s;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn52xx;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn61xx;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn63xx;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn66xx;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn68xx;
-        struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1;
-        struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_xaui_ext_loopback {
-        uint64_t u64;
-        struct cvmx_gmxx_xaui_ext_loopback_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t en:1;
-                uint64_t thresh:4;
-#else
-                uint64_t thresh:4;
-                uint64_t en:1;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn61xx;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn63xx;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn66xx;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn68xx;
-        struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1;
-        struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
index 4719fcfa886..395564e8d1f 100644
--- a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -34,10 +34,7 @@
 #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
 #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
 #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
-#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
-#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
 #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
-#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
 #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
 #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
 #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
@@ -45,7 +42,6 @@
 union cvmx_gpio_bit_cfgx {
         uint64_t u64;
         struct cvmx_gpio_bit_cfgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t synce_sel:2;
                 uint64_t clk_gen:1;
@@ -56,21 +52,8 @@ union cvmx_gpio_bit_cfgx {
                 uint64_t int_en:1;
                 uint64_t rx_xor:1;
                 uint64_t tx_oe:1;
-#else
-                uint64_t tx_oe:1;
-                uint64_t rx_xor:1;
-                uint64_t int_en:1;
-                uint64_t int_type:1;
-                uint64_t fil_cnt:4;
-                uint64_t fil_sel:4;
-                uint64_t clk_sel:2;
-                uint64_t clk_gen:1;
-                uint64_t synce_sel:2;
-                uint64_t reserved_17_63:47;
-#endif
         } s;
         struct cvmx_gpio_bit_cfgx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t fil_sel:4;
                 uint64_t fil_cnt:4;
@@ -78,22 +61,12 @@ union cvmx_gpio_bit_cfgx {
                 uint64_t int_en:1;
                 uint64_t rx_xor:1;
                 uint64_t tx_oe:1;
-#else
-                uint64_t tx_oe:1;
-                uint64_t rx_xor:1;
-                uint64_t int_en:1;
-                uint64_t int_type:1;
-                uint64_t fil_cnt:4;
-                uint64_t fil_sel:4;
-                uint64_t reserved_12_63:52;
-#endif
         } cn30xx;
         struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
         struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
         struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
         struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
         struct cvmx_gpio_bit_cfgx_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_15_63:49;
                 uint64_t clk_gen:1;
                 uint64_t clk_sel:2;
@@ -103,44 +76,22 @@ union cvmx_gpio_bit_cfgx {
                 uint64_t int_en:1;
                 uint64_t rx_xor:1;
                 uint64_t tx_oe:1;
-#else
-                uint64_t tx_oe:1;
-                uint64_t rx_xor:1;
-                uint64_t int_en:1;
-                uint64_t int_type:1;
-                uint64_t fil_cnt:4;
-                uint64_t fil_sel:4;
-                uint64_t clk_sel:2;
-                uint64_t clk_gen:1;
-                uint64_t reserved_15_63:49;
-#endif
         } cn52xx;
         struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
         struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
         struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
         struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
         struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
-        struct cvmx_gpio_bit_cfgx_s cn61xx;
         struct cvmx_gpio_bit_cfgx_s cn63xx;
         struct cvmx_gpio_bit_cfgx_s cn63xxp1;
-        struct cvmx_gpio_bit_cfgx_s cn66xx;
-        struct cvmx_gpio_bit_cfgx_s cn68xx;
-        struct cvmx_gpio_bit_cfgx_s cn68xxp1;
-        struct cvmx_gpio_bit_cfgx_s cnf71xx;
 };
 
 union cvmx_gpio_boot_ena {
         uint64_t u64;
         struct cvmx_gpio_boot_ena_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t boot_ena:4;
                 uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t boot_ena:4;
-                uint64_t reserved_12_63:52;
-#endif
         } s;
         struct cvmx_gpio_boot_ena_s cn30xx;
         struct cvmx_gpio_boot_ena_s cn31xx;
@@ -150,87 +101,33 @@ union cvmx_gpio_boot_ena {
 union cvmx_gpio_clk_genx {
         uint64_t u64;
         struct cvmx_gpio_clk_genx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t n:32;
-#else
-                uint64_t n:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_gpio_clk_genx_s cn52xx;
         struct cvmx_gpio_clk_genx_s cn52xxp1;
         struct cvmx_gpio_clk_genx_s cn56xx;
         struct cvmx_gpio_clk_genx_s cn56xxp1;
-        struct cvmx_gpio_clk_genx_s cn61xx;
         struct cvmx_gpio_clk_genx_s cn63xx;
         struct cvmx_gpio_clk_genx_s cn63xxp1;
-        struct cvmx_gpio_clk_genx_s cn66xx;
-        struct cvmx_gpio_clk_genx_s cn68xx;
-        struct cvmx_gpio_clk_genx_s cn68xxp1;
-        struct cvmx_gpio_clk_genx_s cnf71xx;
 };
 
 union cvmx_gpio_clk_qlmx {
         uint64_t u64;
         struct cvmx_gpio_clk_qlmx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t qlm_sel:3;
-                uint64_t reserved_3_7:5;
-                uint64_t div:1;
-                uint64_t lane_sel:2;
-#else
-                uint64_t lane_sel:2;
-                uint64_t div:1;
-                uint64_t reserved_3_7:5;
-                uint64_t qlm_sel:3;
-                uint64_t reserved_11_63:53;
-#endif
-        } s;
-        struct cvmx_gpio_clk_qlmx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t qlm_sel:2;
-                uint64_t reserved_3_7:5;
-                uint64_t div:1;
-                uint64_t lane_sel:2;
-#else
-                uint64_t lane_sel:2;
-                uint64_t div:1;
-                uint64_t reserved_3_7:5;
-                uint64_t qlm_sel:2;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_gpio_clk_qlmx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t div:1;
                 uint64_t lane_sel:2;
-#else
-                uint64_t lane_sel:2;
-                uint64_t div:1;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn63xx;
-        struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1;
-        struct cvmx_gpio_clk_qlmx_cn61xx cn66xx;
-        struct cvmx_gpio_clk_qlmx_s cn68xx;
-        struct cvmx_gpio_clk_qlmx_s cn68xxp1;
-        struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx;
+        } s;
+        struct cvmx_gpio_clk_qlmx_s cn63xx;
+        struct cvmx_gpio_clk_qlmx_s cn63xxp1;
 };
 
 union cvmx_gpio_dbg_ena {
         uint64_t u64;
         struct cvmx_gpio_dbg_ena_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_21_63:43;
                 uint64_t dbg_ena:21;
-#else
-                uint64_t dbg_ena:21;
-                uint64_t reserved_21_63:43;
-#endif
         } s;
         struct cvmx_gpio_dbg_ena_s cn30xx;
         struct cvmx_gpio_dbg_ena_s cn31xx;
@@ -240,13 +137,8 @@ union cvmx_gpio_dbg_ena {
 union cvmx_gpio_int_clr {
         uint64_t u64;
         struct cvmx_gpio_int_clr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t type:16;
-#else
-                uint64_t type:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_gpio_int_clr_s cn30xx;
         struct cvmx_gpio_int_clr_s cn31xx;
@@ -259,69 +151,21 @@ union cvmx_gpio_int_clr {
         struct cvmx_gpio_int_clr_s cn56xxp1;
         struct cvmx_gpio_int_clr_s cn58xx;
         struct cvmx_gpio_int_clr_s cn58xxp1;
-        struct cvmx_gpio_int_clr_s cn61xx;
         struct cvmx_gpio_int_clr_s cn63xx;
         struct cvmx_gpio_int_clr_s cn63xxp1;
-        struct cvmx_gpio_int_clr_s cn66xx;
-        struct cvmx_gpio_int_clr_s cn68xx;
-        struct cvmx_gpio_int_clr_s cn68xxp1;
-        struct cvmx_gpio_int_clr_s cnf71xx;
-};
-
-union cvmx_gpio_multi_cast {
-        uint64_t u64;
-        struct cvmx_gpio_multi_cast_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_gpio_multi_cast_s cn61xx;
-        struct cvmx_gpio_multi_cast_s cnf71xx;
-};
-
-union cvmx_gpio_pin_ena {
-        uint64_t u64;
-        struct cvmx_gpio_pin_ena_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t ena19:1;
-                uint64_t ena18:1;
-                uint64_t reserved_0_17:18;
-#else
-                uint64_t reserved_0_17:18;
-                uint64_t ena18:1;
-                uint64_t ena19:1;
-                uint64_t reserved_20_63:44;
-#endif
-        } s;
-        struct cvmx_gpio_pin_ena_s cn66xx;
 };
 
 union cvmx_gpio_rx_dat {
         uint64_t u64;
         struct cvmx_gpio_rx_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t dat:24;
-#else
-                uint64_t dat:24;
-                uint64_t reserved_24_63:40;
-#endif
         } s;
         struct cvmx_gpio_rx_dat_s cn30xx;
         struct cvmx_gpio_rx_dat_s cn31xx;
         struct cvmx_gpio_rx_dat_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t dat:16;
-#else
-                uint64_t dat:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn38xx;
         struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
         struct cvmx_gpio_rx_dat_s cn50xx;
@@ -331,59 +175,21 @@ union cvmx_gpio_rx_dat {
         struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
         struct cvmx_gpio_rx_dat_cn38xx cn58xx;
         struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
-        struct cvmx_gpio_rx_dat_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t dat:20;
-#else
-                uint64_t dat:20;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn61xx;
         struct cvmx_gpio_rx_dat_cn38xx cn63xx;
         struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
-        struct cvmx_gpio_rx_dat_cn61xx cn66xx;
-        struct cvmx_gpio_rx_dat_cn38xx cn68xx;
-        struct cvmx_gpio_rx_dat_cn38xx cn68xxp1;
-        struct cvmx_gpio_rx_dat_cn61xx cnf71xx;
-};
-
-union cvmx_gpio_tim_ctl {
-        uint64_t u64;
-        struct cvmx_gpio_tim_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t sel:4;
-#else
-                uint64_t sel:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_gpio_tim_ctl_s cn68xx;
-        struct cvmx_gpio_tim_ctl_s cn68xxp1;
 };
 
 union cvmx_gpio_tx_clr {
         uint64_t u64;
         struct cvmx_gpio_tx_clr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t clr:24;
-#else
-                uint64_t clr:24;
-                uint64_t reserved_24_63:40;
-#endif
         } s;
         struct cvmx_gpio_tx_clr_s cn30xx;
         struct cvmx_gpio_tx_clr_s cn31xx;
         struct cvmx_gpio_tx_clr_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t clr:16;
-#else
-                uint64_t clr:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn38xx;
         struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
         struct cvmx_gpio_tx_clr_s cn50xx;
@@ -393,44 +199,21 @@ union cvmx_gpio_tx_clr {
         struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
         struct cvmx_gpio_tx_clr_cn38xx cn58xx;
         struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
-        struct cvmx_gpio_tx_clr_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t clr:20;
-#else
-                uint64_t clr:20;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn61xx;
         struct cvmx_gpio_tx_clr_cn38xx cn63xx;
         struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
-        struct cvmx_gpio_tx_clr_cn61xx cn66xx;
-        struct cvmx_gpio_tx_clr_cn38xx cn68xx;
-        struct cvmx_gpio_tx_clr_cn38xx cn68xxp1;
-        struct cvmx_gpio_tx_clr_cn61xx cnf71xx;
 };
 
 union cvmx_gpio_tx_set {
         uint64_t u64;
         struct cvmx_gpio_tx_set_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t set:24;
-#else
-                uint64_t set:24;
-                uint64_t reserved_24_63:40;
-#endif
         } s;
         struct cvmx_gpio_tx_set_s cn30xx;
         struct cvmx_gpio_tx_set_s cn31xx;
         struct cvmx_gpio_tx_set_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t set:16;
-#else
-                uint64_t set:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn38xx;
         struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
         struct cvmx_gpio_tx_set_s cn50xx;
@@ -440,72 +223,23 @@ union cvmx_gpio_tx_set {
         struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
         struct cvmx_gpio_tx_set_cn38xx cn58xx;
         struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
-        struct cvmx_gpio_tx_set_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t set:20;
-#else
-                uint64_t set:20;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn61xx;
         struct cvmx_gpio_tx_set_cn38xx cn63xx;
         struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
-        struct cvmx_gpio_tx_set_cn61xx cn66xx;
-        struct cvmx_gpio_tx_set_cn38xx cn68xx;
-        struct cvmx_gpio_tx_set_cn38xx cn68xxp1;
-        struct cvmx_gpio_tx_set_cn61xx cnf71xx;
 };
 
 union cvmx_gpio_xbit_cfgx {
         uint64_t u64;
         struct cvmx_gpio_xbit_cfgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t synce_sel:2;
-                uint64_t clk_gen:1;
-                uint64_t clk_sel:2;
-                uint64_t fil_sel:4;
-                uint64_t fil_cnt:4;
-                uint64_t int_type:1;
-                uint64_t int_en:1;
-                uint64_t rx_xor:1;
-                uint64_t tx_oe:1;
-#else
-                uint64_t tx_oe:1;
-                uint64_t rx_xor:1;
-                uint64_t int_en:1;
-                uint64_t int_type:1;
-                uint64_t fil_cnt:4;
-                uint64_t fil_sel:4;
-                uint64_t clk_sel:2;
-                uint64_t clk_gen:1;
-                uint64_t synce_sel:2;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_gpio_xbit_cfgx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t fil_sel:4;
                 uint64_t fil_cnt:4;
                 uint64_t reserved_2_3:2;
                 uint64_t rx_xor:1;
                 uint64_t tx_oe:1;
-#else
-                uint64_t tx_oe:1;
-                uint64_t rx_xor:1;
-                uint64_t reserved_2_3:2;
-                uint64_t fil_cnt:4;
-                uint64_t fil_sel:4;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn30xx;
-        struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx;
-        struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx;
-        struct cvmx_gpio_xbit_cfgx_s cn61xx;
-        struct cvmx_gpio_xbit_cfgx_s cn66xx;
-        struct cvmx_gpio_xbit_cfgx_s cnf71xx;
+        } s;
+        struct cvmx_gpio_xbit_cfgx_s cn30xx;
+        struct cvmx_gpio_xbit_cfgx_s cn31xx;
+        struct cvmx_gpio_xbit_cfgx_s cn50xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
deleted file mode 100644
index 442f508eaac..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-board.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- *
- * Helper functions to abstract board specific data about
- * network ports from the rest of the cvmx-helper files.
- *
- */
-#ifndef __CVMX_HELPER_BOARD_H__
-#define __CVMX_HELPER_BOARD_H__
-
-#include <asm/octeon/cvmx-helper.h>
-
-typedef enum {
-        set_phy_link_flags_autoneg = 0x1,
-        set_phy_link_flags_flow_control_dont_touch = 0x0 << 1,
-        set_phy_link_flags_flow_control_enable = 0x1 << 1,
-        set_phy_link_flags_flow_control_disable = 0x2 << 1,
-        set_phy_link_flags_flow_control_mask = 0x3 << 1,        /* Mask for 2 bit wide flow control field */
-} cvmx_helper_board_set_phy_link_flags_types_t;
-
-/*
- * Fake IPD port, the RGMII/MII interface may use different PHY, use
- * this macro to return appropriate MIX address to read the PHY.
- */
-#define CVMX_HELPER_BOARD_MGMT_IPD_PORT     -10
-
-/**
- * cvmx_override_board_link_get(int ipd_port) is a function
- * pointer. It is meant to allow customization of the process of
- * talking to a PHY to determine link speed. It is called every
- * time a PHY must be polled for link status. Users should set
- * this pointer to a function before calling any cvmx-helper
- * operations.
- */
-extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port);
-
-/**
- * Return the MII PHY address associated with the given IPD
- * port. A result of -1 means there isn't a MII capable PHY
- * connected to this port. On chips supporting multiple MII
- * busses the bus number is encoded in bits <15:8>.
- *
- * This function must be modifed for every new Octeon board.
- * Internally it uses switch statements based on the cvmx_sysinfo
- * data to determine board types and revisions. It relys on the
- * fact that every Octeon board receives a unique board type
- * enumeration from the bootloader.
- *
- * @ipd_port: Octeon IPD port to get the MII address for.
- *
- * Returns MII PHY address and bus number or -1.
- */
-extern int cvmx_helper_board_get_mii_address(int ipd_port);
-
-/**
- * This function as a board specific method of changing the PHY
- * speed, duplex, and autonegotiation. This programs the PHY and
- * not Octeon. This can be used to force Octeon's links to
- * specific settings.
- *
- * @phy_addr:  The address of the PHY to program
- * @link_flags:
- *                  Flags to control autonegotiation.  Bit 0 is autonegotiation
- *                  enable/disable to maintain backware compatibility.
- * @link_info: Link speed to program. If the speed is zero and autonegotiation
- *                  is enabled, all possible negotiation speeds are advertised.
- *
- * Returns Zero on success, negative on failure
- */
-int cvmx_helper_board_link_set_phy(int phy_addr,
-                                   cvmx_helper_board_set_phy_link_flags_types_t
-                                   link_flags,
-                                   cvmx_helper_link_info_t link_info);
-
-/**
- * This function is the board specific method of determining an
- * ethernet ports link speed. Most Octeon boards have Marvell PHYs
- * and are handled by the fall through case. This function must be
- * updated for boards that don't have the normal Marvell PHYs.
- *
- * This function must be modifed for every new Octeon board.
- * Internally it uses switch statements based on the cvmx_sysinfo
- * data to determine board types and revisions. It relys on the
- * fact that every Octeon board receives a unique board type
- * enumeration from the bootloader.
- *
- * @ipd_port: IPD input port associated with the port we want to get link
- *                 status for.
- *
- * Returns The ports link status. If the link isn't fully resolved, this must
- *         return zero.
- */
-extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
-
-/**
- * This function is called by cvmx_helper_interface_probe() after it
- * determines the number of ports Octeon can support on a specific
- * interface. This function is the per board location to override
- * this value. It is called with the number of ports Octeon might
- * support and should return the number of actual ports on the
- * board.
- *
- * This function must be modifed for every new Octeon board.
- * Internally it uses switch statements based on the cvmx_sysinfo
- * data to determine board types and revisions. It relys on the
- * fact that every Octeon board receives a unique board type
- * enumeration from the bootloader.
- *
- * @interface: Interface to probe
- * @supported_ports:
- *                  Number of ports Octeon supports.
- *
- * Returns Number of ports the actual board supports. Many times this will
- *         simple be "support_ports".
- */
-extern int __cvmx_helper_board_interface_probe(int interface,
-                                               int supported_ports);
-
-/**
- * Enable packet input/output from the hardware. This function is
- * called after by cvmx_helper_packet_hardware_enable() to
- * perform board specific initialization. For most boards
- * nothing is needed.
- *
- * @interface: Interface to enable
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_board_hardware_enable(int interface);
-
-#endif /* __CVMX_HELPER_BOARD_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
deleted file mode 100644
index 077f0e9d3b2..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-loop.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as published by
- * the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
- * See the GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Functions for LOOP initialization, configuration,
- * and monitoring.
- *
- */
-#ifndef __CVMX_HELPER_LOOP_H__
-#define __CVMX_HELPER_LOOP_H__
-
-/**
- * Probe a LOOP interface and determine the number of ports
- * connected to it. The LOOP interface should still be down after
- * this call.
- *
- * @interface: Interface to probe
- *
- * Returns Number of ports on the interface. Zero to disable.
- */
-extern int __cvmx_helper_loop_probe(int interface);
-static inline int __cvmx_helper_loop_enumerate(int interface) {return 4; }
-
-/**
- * Bringup and enable a LOOP interface. After this call packet
- * I/O should be fully functional. This is called with IPD
- * enabled but PKO disabled.
- *
- * @interface: Interface to bring up
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_loop_enable(int interface);
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
deleted file mode 100644
index 8df4c7fafdb..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-npi.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Functions for NPI initialization, configuration,
- * and monitoring.
- *
- */
-#ifndef __CVMX_HELPER_NPI_H__
-#define __CVMX_HELPER_NPI_H__
-
-/**
- * Probe a NPI interface and determine the number of ports
- * connected to it. The NPI interface should still be down after
- * this call.
- *
- * @interface: Interface to probe
- *
- * Returns Number of ports on the interface. Zero to disable.
- */
-extern int __cvmx_helper_npi_probe(int interface);
-#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe
-
-/**
- * Bringup and enable a NPI interface. After this call packet
- * I/O should be fully functional. This is called with IPD
- * enabled but PKO disabled.
- *
- * @interface: Interface to bring up
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_npi_enable(int interface);
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
deleted file mode 100644
index 78295ba0050..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Functions for RGMII/GMII/MII initialization, configuration,
- * and monitoring.
- *
- */
-#ifndef __CVMX_HELPER_RGMII_H__
-#define __CVMX_HELPER_RGMII_H__
-
-/**
- * Probe RGMII ports and determine the number present
- *
- * @interface: Interface to probe
- *
- * Returns Number of RGMII/GMII/MII ports (0-4).
- */
-extern int __cvmx_helper_rgmii_probe(int interface);
-#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe
-
-/**
- * Put an RGMII interface in loopback mode. Internal packets sent
- * out will be received back again on the same port. Externally
- * received packets will echo back out.
- *
- * @port:   IPD port number to loop.
- */
-extern void cvmx_helper_rgmii_internal_loopback(int port);
-
-/**
- * Configure all of the ASX, GMX, and PKO regsiters required
- * to get RGMII to function on the supplied interface.
- *
- * @interface: PKO Interface to configure (0 or 1)
- *
- * Returns Zero on success
- */
-extern int __cvmx_helper_rgmii_enable(int interface);
-
-/**
- * Return the link state of an IPD/PKO port as returned by
- * auto negotiation. The result of this function may not match
- * Octeon's link config if auto negotiation has changed since
- * the last call to cvmx_helper_link_set().
- *
- * @ipd_port: IPD/PKO port to query
- *
- * Returns Link state
- */
-extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port);
-
-/**
- * Configure an IPD/PKO port for the specified link state. This
- * function does not influence auto negotiation at the PHY level.
- * The passed link state must always match the link state returned
- * by cvmx_helper_link_get(). It is normally best to use
- * cvmx_helper_link_autoconf() instead.
- *
- * @ipd_port:  IPD/PKO port to configure
- * @link_info: The new link state
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_rgmii_link_set(int ipd_port,
-                                        cvmx_helper_link_info_t link_info);
-
-/**
- * Configure a port for internal and/or external loopback. Internal loopback
- * causes packets sent by the port to be received by Octeon. External loopback
- * causes packets received from the wire to sent out again.
- *
- * @ipd_port: IPD/PKO port to loopback.
- * @enable_internal:
- *                 Non zero if you want internal loopback
- * @enable_external:
- *                 Non zero if you want external loopback
- *
- * Returns Zero on success, negative on failure.
- */
-extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port,
-                                                  int enable_internal,
-                                                  int enable_external);
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
deleted file mode 100644
index 9a9b6c103ed..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Functions for SGMII initialization, configuration,
- * and monitoring.
- *
- */
-#ifndef __CVMX_HELPER_SGMII_H__
-#define __CVMX_HELPER_SGMII_H__
-
-/**
- * Probe a SGMII interface and determine the number of ports
- * connected to it. The SGMII interface should still be down after
- * this call.
- *
- * @interface: Interface to probe
- *
- * Returns Number of ports on the interface. Zero to disable.
- */
-extern int __cvmx_helper_sgmii_probe(int interface);
-extern int __cvmx_helper_sgmii_enumerate(int interface);
-
-/**
- * Bringup and enable a SGMII interface. After this call packet
- * I/O should be fully functional. This is called with IPD
- * enabled but PKO disabled.
- *
- * @interface: Interface to bring up
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_sgmii_enable(int interface);
-
-/**
- * Return the link state of an IPD/PKO port as returned by
- * auto negotiation. The result of this function may not match
- * Octeon's link config if auto negotiation has changed since
- * the last call to cvmx_helper_link_set().
- *
- * @ipd_port: IPD/PKO port to query
- *
- * Returns Link state
- */
-extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port);
-
-/**
- * Configure an IPD/PKO port for the specified link state. This
- * function does not influence auto negotiation at the PHY level.
- * The passed link state must always match the link state returned
- * by cvmx_helper_link_get(). It is normally best to use
- * cvmx_helper_link_autoconf() instead.
- *
- * @ipd_port:  IPD/PKO port to configure
- * @link_info: The new link state
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_sgmii_link_set(int ipd_port,
-                                        cvmx_helper_link_info_t link_info);
-
-/**
- * Configure a port for internal and/or external loopback. Internal loopback
- * causes packets sent by the port to be received by Octeon. External loopback
- * causes packets received from the wire to sent out again.
- *
- * @ipd_port: IPD/PKO port to loopback.
- * @enable_internal:
- *                 Non zero if you want internal loopback
- * @enable_external:
- *                 Non zero if you want external loopback
- *
- * Returns Zero on success, negative on failure.
- */
-extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port,
-                                                  int enable_internal,
-                                                  int enable_external);
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
deleted file mode 100644
index 9f1c6b968f9..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-spi.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- * Functions for SPI initialization, configuration,
- * and monitoring.
- */
-#ifndef __CVMX_HELPER_SPI_H__
-#define __CVMX_HELPER_SPI_H__
-
-/**
- * Probe a SPI interface and determine the number of ports
- * connected to it. The SPI interface should still be down after
- * this call.
- *
- * @interface: Interface to probe
- *
- * Returns Number of ports on the interface. Zero to disable.
- */
-extern int __cvmx_helper_spi_probe(int interface);
-extern int __cvmx_helper_spi_enumerate(int interface);
-
-/**
- * Bringup and enable a SPI interface. After this call packet I/O
- * should be fully functional. This is called with IPD enabled but
- * PKO disabled.
- *
- * @interface: Interface to bring up
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_spi_enable(int interface);
-
-/**
- * Return the link state of an IPD/PKO port as returned by
- * auto negotiation. The result of this function may not match
- * Octeon's link config if auto negotiation has changed since
- * the last call to cvmx_helper_link_set().
- *
- * @ipd_port: IPD/PKO port to query
- *
- * Returns Link state
- */
-extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port);
-
-/**
- * Configure an IPD/PKO port for the specified link state. This
- * function does not influence auto negotiation at the PHY level.
- * The passed link state must always match the link state returned
- * by cvmx_helper_link_get(). It is normally best to use
- * cvmx_helper_link_autoconf() instead.
- *
- * @ipd_port:  IPD/PKO port to configure
- * @link_info: The new link state
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_spi_link_set(int ipd_port,
-                                      cvmx_helper_link_info_t link_info);
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
deleted file mode 100644
index 6a6e52fc22c..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-util.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- *
- * Small helper utilities.
- *
- */
-
-#ifndef __CVMX_HELPER_UTIL_H__
-#define __CVMX_HELPER_UTIL_H__
-
-/**
- * Convert a interface mode into a human readable string
- *
- * @mode:   Mode to convert
- *
- * Returns String
- */
-extern const char
-    *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
-
-/**
- * Debug routine to dump the packet structure to the console
- *
- * @work:   Work queue entry containing the packet to dump
- * Returns
- */
-extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
-
-/**
- * Setup Random Early Drop on a specific input queue
- *
- * @queue:  Input queue to setup RED on (0-7)
- * @pass_thresh:
- *               Packets will begin slowly dropping when there are less than
- *               this many packet buffers free in FPA 0.
- * @drop_thresh:
- *               All incomming packets will be dropped when there are less
- *               than this many free packet buffers in FPA 0.
- * Returns Zero on success. Negative on failure
- */
-extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
-                                       int drop_thresh);
-
-/**
- * Setup Random Early Drop to automatically begin dropping packets.
- *
- * @pass_thresh:
- *               Packets will begin slowly dropping when there are less than
- *               this many packet buffers free in FPA 0.
- * @drop_thresh:
- *               All incomming packets will be dropped when there are less
- *               than this many free packet buffers in FPA 0.
- * Returns Zero on success. Negative on failure
- */
-extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
-
-/**
- * Get the version of the CVMX libraries.
- *
- * Returns Version string. Note this buffer is allocated statically
- *         and will be shared by all callers.
- */
-extern const char *cvmx_helper_get_version(void);
-
-/**
- * Setup the common GMX settings that determine the number of
- * ports. These setting apply to almost all configurations of all
- * chips.
- *
- * @interface: Interface to configure
- * @num_ports: Number of ports on the interface
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
-
-/**
- * Returns the IPD/PKO port number for a port on the given
- * interface.
- *
- * @interface: Interface to use
- * @port:      Port on the interface
- *
- * Returns IPD/PKO port number
- */
-extern int cvmx_helper_get_ipd_port(int interface, int port);
-
-/**
- * Returns the IPD/PKO port number for the first port on the given
- * interface.
- *
- * @interface: Interface to use
- *
- * Returns IPD/PKO port number
- */
-static inline int cvmx_helper_get_first_ipd_port(int interface)
-{
-        return cvmx_helper_get_ipd_port(interface, 0);
-}
-
-/**
- * Returns the IPD/PKO port number for the last port on the given
- * interface.
- *
- * @interface: Interface to use
- *
- * Returns IPD/PKO port number
- */
-static inline int cvmx_helper_get_last_ipd_port(int interface)
-{
-        extern int cvmx_helper_ports_on_interface(int interface);
-
-        return cvmx_helper_get_first_ipd_port(interface) +
-               cvmx_helper_ports_on_interface(interface) - 1;
-}
-
-/**
- * Free the packet buffers contained in a work queue entry.
- * The work queue entry is not freed.
- *
- * @work:   Work queue entry with packet to free
- */
-static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work)
-{
-        uint64_t number_buffers;
-        union cvmx_buf_ptr buffer_ptr;
-        union cvmx_buf_ptr next_buffer_ptr;
-        uint64_t start_of_buffer;
-
-        number_buffers = work->word2.s.bufs;
-        if (number_buffers == 0)
-                return;
-        buffer_ptr = work->packet_ptr;
-
-        /*
-         * Since the number of buffers is not zero, we know this is
-         * not a dynamic short packet. We need to check if it is a
-         * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is
-         * true, we need to free all buffers except for the first
-         * one. The caller doesn't expect their WQE pointer to be
-         * freed
-         */
-        start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
-        if (cvmx_ptr_to_phys(work) == start_of_buffer) {
-                next_buffer_ptr =
-                    *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
-                buffer_ptr = next_buffer_ptr;
-                number_buffers--;
-        }
-
-        while (number_buffers--) {
-                /*
-                 * Remember the back pointer is in cache lines, not
-                 * 64bit words
-                 */
-                start_of_buffer =
-                    ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
-                /*
-                 * Read pointer to next buffer before we free the
-                 * current buffer.
-                 */
-                next_buffer_ptr =
-                    *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
-                cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer),
-                              buffer_ptr.s.pool, 0);
-                buffer_ptr = next_buffer_ptr;
-        }
-}
-
-/**
- * Returns the interface number for an IPD/PKO port number.
- *
- * @ipd_port: IPD/PKO port number
- *
- * Returns Interface number
- */
-extern int cvmx_helper_get_interface_num(int ipd_port);
-
-/**
- * Returns the interface index number for an IPD/PKO port
- * number.
- *
- * @ipd_port: IPD/PKO port number
- *
- * Returns Interface index number
- */
-extern int cvmx_helper_get_interface_index_num(int ipd_port);
-
-#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
deleted file mode 100644
index f6fbc4f45b5..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Functions for XAUI initialization, configuration,
- * and monitoring.
- *
- */
-#ifndef __CVMX_HELPER_XAUI_H__
-#define __CVMX_HELPER_XAUI_H__
-
-/**
- * Probe a XAUI interface and determine the number of ports
- * connected to it. The XAUI interface should still be down
- * after this call.
- *
- * @interface: Interface to probe
- *
- * Returns Number of ports on the interface. Zero to disable.
- */
-extern int __cvmx_helper_xaui_probe(int interface);
-extern int __cvmx_helper_xaui_enumerate(int interface);
-
-/**
- * Bringup and enable a XAUI interface. After this call packet
- * I/O should be fully functional. This is called with IPD
- * enabled but PKO disabled.
- *
- * @interface: Interface to bring up
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_xaui_enable(int interface);
-
-/**
- * Return the link state of an IPD/PKO port as returned by
- * auto negotiation. The result of this function may not match
- * Octeon's link config if auto negotiation has changed since
- * the last call to cvmx_helper_link_set().
- *
- * @ipd_port: IPD/PKO port to query
- *
- * Returns Link state
- */
-extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port);
-
-/**
- * Configure an IPD/PKO port for the specified link state. This
- * function does not influence auto negotiation at the PHY level.
- * The passed link state must always match the link state returned
- * by cvmx_helper_link_get(). It is normally best to use
- * cvmx_helper_link_autoconf() instead.
- *
- * @ipd_port:  IPD/PKO port to configure
- * @link_info: The new link state
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_xaui_link_set(int ipd_port,
-                                       cvmx_helper_link_info_t link_info);
-
-/**
- * Configure a port for internal and/or external loopback. Internal loopback
- * causes packets sent by the port to be received by Octeon. External loopback
- * causes packets received from the wire to sent out again.
- *
- * @ipd_port: IPD/PKO port to loopback.
- * @enable_internal:
- *                 Non zero if you want internal loopback
- * @enable_external:
- *                 Non zero if you want external loopback
- *
- * Returns Zero on success, negative on failure.
- */
-extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
-                                                 int enable_internal,
-                                                 int enable_external);
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
deleted file mode 100644
index 691c8142cd4..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- *
- * Helper functions for common, but complicated tasks.
- *
- */
-
-#ifndef __CVMX_HELPER_H__
-#define __CVMX_HELPER_H__
-
-#include <asm/octeon/cvmx-config.h>
-#include <asm/octeon/cvmx-fpa.h>
-#include <asm/octeon/cvmx-wqe.h>
-
-typedef enum {
-        CVMX_HELPER_INTERFACE_MODE_DISABLED,
-        CVMX_HELPER_INTERFACE_MODE_RGMII,
-        CVMX_HELPER_INTERFACE_MODE_GMII,
-        CVMX_HELPER_INTERFACE_MODE_SPI,
-        CVMX_HELPER_INTERFACE_MODE_PCIE,
-        CVMX_HELPER_INTERFACE_MODE_XAUI,
-        CVMX_HELPER_INTERFACE_MODE_SGMII,
-        CVMX_HELPER_INTERFACE_MODE_PICMG,
-        CVMX_HELPER_INTERFACE_MODE_NPI,
-        CVMX_HELPER_INTERFACE_MODE_LOOP,
-} cvmx_helper_interface_mode_t;
-
-typedef union {
-        uint64_t u64;
-        struct {
-                uint64_t reserved_20_63:44;
-                uint64_t link_up:1;         /**< Is the physical link up? */
-                uint64_t full_duplex:1;     /**< 1 if the link is full duplex */
-                uint64_t speed:18;          /**< Speed of the link in Mbps */
-        } s;
-} cvmx_helper_link_info_t;
-
-#include <asm/octeon/cvmx-helper-errata.h>
-#include <asm/octeon/cvmx-helper-loop.h>
-#include <asm/octeon/cvmx-helper-npi.h>
-#include <asm/octeon/cvmx-helper-rgmii.h>
-#include <asm/octeon/cvmx-helper-sgmii.h>
-#include <asm/octeon/cvmx-helper-spi.h>
-#include <asm/octeon/cvmx-helper-util.h>
-#include <asm/octeon/cvmx-helper-xaui.h>
-
-/**
- * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
- * priorities[16]) is a function pointer. It is meant to allow
- * customization of the PKO queue priorities based on the port
- * number. Users should set this pointer to a function before
- * calling any cvmx-helper operations.
- */
-extern void (*cvmx_override_pko_queue_priority) (int pko_port,
-                                                 uint64_t priorities[16]);
-
-/**
- * cvmx_override_ipd_port_setup(int ipd_port) is a function
- * pointer. It is meant to allow customization of the IPD port
- * setup before packet input/output comes online. It is called
- * after cvmx-helper does the default IPD configuration, but
- * before IPD is enabled. Users should set this pointer to a
- * function before calling any cvmx-helper operations.
- */
-extern void (*cvmx_override_ipd_port_setup) (int ipd_port);
-
-/**
- * This function enables the IPD and also enables the packet interfaces.
- * The packet interfaces (RGMII and SPI) must be enabled after the
- * IPD.  This should be called by the user program after any additional
- * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD
- * is not set in the executive-config.h file.
- *
- * Returns 0 on success
- *         -1 on failure
- */
-extern int cvmx_helper_ipd_and_packet_input_enable(void);
-
-/**
- * Initialize the PIP, IPD, and PKO hardware to support
- * simple priority based queues for the ethernet ports. Each
- * port is configured with a number of priority queues based
- * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower
- * priority than the previous.
- *
- * Returns Zero on success, non-zero on failure
- */
-extern int cvmx_helper_initialize_packet_io_global(void);
-
-/**
- * Does core local initialization for packet io
- *
- * Returns Zero on success, non-zero on failure
- */
-extern int cvmx_helper_initialize_packet_io_local(void);
-
-/**
- * Returns the number of ports on the given interface.
- * The interface must be initialized before the port count
- * can be returned.
- *
- * @interface: Which interface to return port count for.
- *
- * Returns Port count for interface
- *         -1 for uninitialized interface
- */
-extern int cvmx_helper_ports_on_interface(int interface);
-
-/**
- * Return the number of interfaces the chip has. Each interface
- * may have multiple ports. Most chips support two interfaces,
- * but the CNX0XX and CNX1XX are exceptions. These only support
- * one interface.
- *
- * Returns Number of interfaces on chip
- */
-extern int cvmx_helper_get_number_of_interfaces(void);
-
-/**
- * Get the operating mode of an interface. Depending on the Octeon
- * chip and configuration, this function returns an enumeration
- * of the type of packet I/O supported by an interface.
- *
- * @interface: Interface to probe
- *
- * Returns Mode of the interface. Unknown or unsupported interfaces return
- *         DISABLED.
- */
-extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
-                                                                   interface);
-
-/**
- * Auto configure an IPD/PKO port link state and speed. This
- * function basically does the equivalent of:
- * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
- *
- * @ipd_port: IPD/PKO port to auto configure
- *
- * Returns Link state after configure
- */
-extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port);
-
-/**
- * Return the link state of an IPD/PKO port as returned by
- * auto negotiation. The result of this function may not match
- * Octeon's link config if auto negotiation has changed since
- * the last call to cvmx_helper_link_set().
- *
- * @ipd_port: IPD/PKO port to query
- *
- * Returns Link state
- */
-extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port);
-
-/**
- * Configure an IPD/PKO port for the specified link state. This
- * function does not influence auto negotiation at the PHY level.
- * The passed link state must always match the link state returned
- * by cvmx_helper_link_get(). It is normally best to use
- * cvmx_helper_link_autoconf() instead.
- *
- * @ipd_port:  IPD/PKO port to configure
- * @link_info: The new link state
- *
- * Returns Zero on success, negative on failure
- */
-extern int cvmx_helper_link_set(int ipd_port,
-                                cvmx_helper_link_info_t link_info);
-
-/**
- * This function probes an interface to determine the actual
- * number of hardware ports connected to it. It doesn't setup the
- * ports or enable them. The main goal here is to set the global
- * interface_port_count[interface] correctly. Hardware setup of the
- * ports will be performed later.
- *
- * @interface: Interface to probe
- *
- * Returns Zero on success, negative on failure
- */
-extern int cvmx_helper_interface_probe(int interface);
-extern int cvmx_helper_interface_enumerate(int interface);
-
-/**
- * Configure a port for internal and/or external loopback. Internal loopback
- * causes packets sent by the port to be received by Octeon. External loopback
- * causes packets received from the wire to sent out again.
- *
- * @ipd_port: IPD/PKO port to loopback.
- * @enable_internal:
- *                 Non zero if you want internal loopback
- * @enable_external:
- *                 Non zero if you want external loopback
- *
- * Returns Zero on success, negative on failure.
- */
-extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal,
-                                          int enable_external);
-
-#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
index 7936f816e93..d7d856c2483 100644
--- a/arch/mips/include/asm/octeon/cvmx-iob-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -51,86 +51,10 @@
 #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
 #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
 #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
-#define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull))
-#define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull))
-#define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull))
-#define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull))
-#define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull))
-#define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull))
-#define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull))
-#define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull))
-#define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull))
-#define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull))
-#define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull))
 
 union cvmx_iob_bist_status {
         uint64_t u64;
         struct cvmx_iob_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t ibd:1;
-                uint64_t icd:1;
-#else
-                uint64_t icd:1;
-                uint64_t ibd:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_iob_bist_status_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_18_63:46;
-                uint64_t icnrcb:1;
-                uint64_t icr0:1;
-                uint64_t icr1:1;
-                uint64_t icnr1:1;
-                uint64_t icnr0:1;
-                uint64_t ibdr0:1;
-                uint64_t ibdr1:1;
-                uint64_t ibr0:1;
-                uint64_t ibr1:1;
-                uint64_t icnrt:1;
-                uint64_t ibrq0:1;
-                uint64_t ibrq1:1;
-                uint64_t icrn0:1;
-                uint64_t icrn1:1;
-                uint64_t icrp0:1;
-                uint64_t icrp1:1;
-                uint64_t ibd:1;
-                uint64_t icd:1;
-#else
-                uint64_t icd:1;
-                uint64_t ibd:1;
-                uint64_t icrp1:1;
-                uint64_t icrp0:1;
-                uint64_t icrn1:1;
-                uint64_t icrn0:1;
-                uint64_t ibrq1:1;
-                uint64_t ibrq0:1;
-                uint64_t icnrt:1;
-                uint64_t ibr1:1;
-                uint64_t ibr0:1;
-                uint64_t ibdr1:1;
-                uint64_t ibdr0:1;
-                uint64_t icnr0:1;
-                uint64_t icnr1:1;
-                uint64_t icr1:1;
-                uint64_t icr0:1;
-                uint64_t icnrcb:1;
-                uint64_t reserved_18_63:46;
-#endif
-        } cn30xx;
-        struct cvmx_iob_bist_status_cn30xx cn31xx;
-        struct cvmx_iob_bist_status_cn30xx cn38xx;
-        struct cvmx_iob_bist_status_cn30xx cn38xxp2;
-        struct cvmx_iob_bist_status_cn30xx cn50xx;
-        struct cvmx_iob_bist_status_cn30xx cn52xx;
-        struct cvmx_iob_bist_status_cn30xx cn52xxp1;
-        struct cvmx_iob_bist_status_cn30xx cn56xx;
-        struct cvmx_iob_bist_status_cn30xx cn56xxp1;
-        struct cvmx_iob_bist_status_cn30xx cn58xx;
-        struct cvmx_iob_bist_status_cn30xx cn58xxp1;
-        struct cvmx_iob_bist_status_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_23_63:41;
                 uint64_t xmdfif:1;
                 uint64_t xmcfif:1;
@@ -155,48 +79,16 @@ union cvmx_iob_bist_status {
                 uint64_t icrp1:1;
                 uint64_t ibd:1;
                 uint64_t icd:1;
-#else
-                uint64_t icd:1;
-                uint64_t ibd:1;
-                uint64_t icrp1:1;
-                uint64_t icrp0:1;
-                uint64_t icrn1:1;
-                uint64_t icrn0:1;
-                uint64_t ibrq1:1;
-                uint64_t ibrq0:1;
-                uint64_t icnrt:1;
-                uint64_t ibr1:1;
-                uint64_t ibr0:1;
-                uint64_t ibdr1:1;
-                uint64_t ibdr0:1;
-                uint64_t icnr0:1;
-                uint64_t icnr1:1;
-                uint64_t icr1:1;
-                uint64_t icr0:1;
-                uint64_t icnrcb:1;
-                uint64_t iocfif:1;
-                uint64_t rsdfif:1;
-                uint64_t iorfif:1;
-                uint64_t xmcfif:1;
-                uint64_t xmdfif:1;
-                uint64_t reserved_23_63:41;
-#endif
-        } cn61xx;
-        struct cvmx_iob_bist_status_cn61xx cn63xx;
-        struct cvmx_iob_bist_status_cn61xx cn63xxp1;
-        struct cvmx_iob_bist_status_cn61xx cn66xx;
-        struct cvmx_iob_bist_status_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
+        } s;
+        struct cvmx_iob_bist_status_cn30xx {
                 uint64_t reserved_18_63:46;
-                uint64_t xmdfif:1;
-                uint64_t xmcfif:1;
-                uint64_t iorfif:1;
-                uint64_t rsdfif:1;
-                uint64_t iocfif:1;
                 uint64_t icnrcb:1;
                 uint64_t icr0:1;
                 uint64_t icr1:1;
+                uint64_t icnr1:1;
                 uint64_t icnr0:1;
+                uint64_t ibdr0:1;
+                uint64_t ibdr1:1;
                 uint64_t ibr0:1;
                 uint64_t ibr1:1;
                 uint64_t icnrt:1;
@@ -204,82 +96,50 @@ union cvmx_iob_bist_status {
                 uint64_t ibrq1:1;
                 uint64_t icrn0:1;
                 uint64_t icrn1:1;
+                uint64_t icrp0:1;
+                uint64_t icrp1:1;
                 uint64_t ibd:1;
                 uint64_t icd:1;
-#else
-                uint64_t icd:1;
-                uint64_t ibd:1;
-                uint64_t icrn1:1;
-                uint64_t icrn0:1;
-                uint64_t ibrq1:1;
-                uint64_t ibrq0:1;
-                uint64_t icnrt:1;
-                uint64_t ibr1:1;
-                uint64_t ibr0:1;
-                uint64_t icnr0:1;
-                uint64_t icr1:1;
-                uint64_t icr0:1;
-                uint64_t icnrcb:1;
-                uint64_t iocfif:1;
-                uint64_t rsdfif:1;
-                uint64_t iorfif:1;
-                uint64_t xmcfif:1;
-                uint64_t xmdfif:1;
-                uint64_t reserved_18_63:46;
-#endif
-        } cn68xx;
-        struct cvmx_iob_bist_status_cn68xx cn68xxp1;
-        struct cvmx_iob_bist_status_cn61xx cnf71xx;
+        } cn30xx;
+        struct cvmx_iob_bist_status_cn30xx cn31xx;
+        struct cvmx_iob_bist_status_cn30xx cn38xx;
+        struct cvmx_iob_bist_status_cn30xx cn38xxp2;
+        struct cvmx_iob_bist_status_cn30xx cn50xx;
+        struct cvmx_iob_bist_status_cn30xx cn52xx;
+        struct cvmx_iob_bist_status_cn30xx cn52xxp1;
+        struct cvmx_iob_bist_status_cn30xx cn56xx;
+        struct cvmx_iob_bist_status_cn30xx cn56xxp1;
+        struct cvmx_iob_bist_status_cn30xx cn58xx;
+        struct cvmx_iob_bist_status_cn30xx cn58xxp1;
+        struct cvmx_iob_bist_status_s cn63xx;
+        struct cvmx_iob_bist_status_s cn63xxp1;
 };
 
 union cvmx_iob_ctl_status {
         uint64_t u64;
         struct cvmx_iob_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t fif_dly:1;
+                uint64_t reserved_10_63:54;
                 uint64_t xmc_per:4;
-                uint64_t reserved_5_5:1;
+                uint64_t rr_mode:1;
                 uint64_t outb_mat:1;
                 uint64_t inb_mat:1;
                 uint64_t pko_enb:1;
                 uint64_t dwb_enb:1;
                 uint64_t fau_end:1;
-#else
-                uint64_t fau_end:1;
-                uint64_t dwb_enb:1;
-                uint64_t pko_enb:1;
-                uint64_t inb_mat:1;
-                uint64_t outb_mat:1;
-                uint64_t reserved_5_5:1;
-                uint64_t xmc_per:4;
-                uint64_t fif_dly:1;
-                uint64_t reserved_11_63:53;
-#endif
         } s;
         struct cvmx_iob_ctl_status_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t outb_mat:1;
                 uint64_t inb_mat:1;
                 uint64_t pko_enb:1;
                 uint64_t dwb_enb:1;
                 uint64_t fau_end:1;
-#else
-                uint64_t fau_end:1;
-                uint64_t dwb_enb:1;
-                uint64_t pko_enb:1;
-                uint64_t inb_mat:1;
-                uint64_t outb_mat:1;
-                uint64_t reserved_5_63:59;
-#endif
         } cn30xx;
         struct cvmx_iob_ctl_status_cn30xx cn31xx;
         struct cvmx_iob_ctl_status_cn30xx cn38xx;
         struct cvmx_iob_ctl_status_cn30xx cn38xxp2;
         struct cvmx_iob_ctl_status_cn30xx cn50xx;
         struct cvmx_iob_ctl_status_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t rr_mode:1;
                 uint64_t outb_mat:1;
@@ -287,106 +147,22 @@ union cvmx_iob_ctl_status {
                 uint64_t pko_enb:1;
                 uint64_t dwb_enb:1;
                 uint64_t fau_end:1;
-#else
-                uint64_t fau_end:1;
-                uint64_t dwb_enb:1;
-                uint64_t pko_enb:1;
-                uint64_t inb_mat:1;
-                uint64_t outb_mat:1;
-                uint64_t rr_mode:1;
-                uint64_t reserved_6_63:58;
-#endif
         } cn52xx;
         struct cvmx_iob_ctl_status_cn30xx cn52xxp1;
         struct cvmx_iob_ctl_status_cn30xx cn56xx;
         struct cvmx_iob_ctl_status_cn30xx cn56xxp1;
         struct cvmx_iob_ctl_status_cn30xx cn58xx;
         struct cvmx_iob_ctl_status_cn30xx cn58xxp1;
-        struct cvmx_iob_ctl_status_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t fif_dly:1;
-                uint64_t xmc_per:4;
-                uint64_t rr_mode:1;
-                uint64_t outb_mat:1;
-                uint64_t inb_mat:1;
-                uint64_t pko_enb:1;
-                uint64_t dwb_enb:1;
-                uint64_t fau_end:1;
-#else
-                uint64_t fau_end:1;
-                uint64_t dwb_enb:1;
-                uint64_t pko_enb:1;
-                uint64_t inb_mat:1;
-                uint64_t outb_mat:1;
-                uint64_t rr_mode:1;
-                uint64_t xmc_per:4;
-                uint64_t fif_dly:1;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn61xx;
-        struct cvmx_iob_ctl_status_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t xmc_per:4;
-                uint64_t rr_mode:1;
-                uint64_t outb_mat:1;
-                uint64_t inb_mat:1;
-                uint64_t pko_enb:1;
-                uint64_t dwb_enb:1;
-                uint64_t fau_end:1;
-#else
-                uint64_t fau_end:1;
-                uint64_t dwb_enb:1;
-                uint64_t pko_enb:1;
-                uint64_t inb_mat:1;
-                uint64_t outb_mat:1;
-                uint64_t rr_mode:1;
-                uint64_t xmc_per:4;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn63xx;
-        struct cvmx_iob_ctl_status_cn63xx cn63xxp1;
-        struct cvmx_iob_ctl_status_cn61xx cn66xx;
-        struct cvmx_iob_ctl_status_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t fif_dly:1;
-                uint64_t xmc_per:4;
-                uint64_t rsvr5:1;
-                uint64_t outb_mat:1;
-                uint64_t inb_mat:1;
-                uint64_t pko_enb:1;
-                uint64_t dwb_enb:1;
-                uint64_t fau_end:1;
-#else
-                uint64_t fau_end:1;
-                uint64_t dwb_enb:1;
-                uint64_t pko_enb:1;
-                uint64_t inb_mat:1;
-                uint64_t outb_mat:1;
-                uint64_t rsvr5:1;
-                uint64_t xmc_per:4;
-                uint64_t fif_dly:1;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn68xx;
-        struct cvmx_iob_ctl_status_cn68xx cn68xxp1;
-        struct cvmx_iob_ctl_status_cn61xx cnf71xx;
+        struct cvmx_iob_ctl_status_s cn63xx;
+        struct cvmx_iob_ctl_status_s cn63xxp1;
 };
 
 union cvmx_iob_dwb_pri_cnt {
         uint64_t u64;
         struct cvmx_iob_dwb_pri_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt_enb:1;
                 uint64_t cnt_val:15;
-#else
-                uint64_t cnt_val:15;
-                uint64_t cnt_enb:1;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_iob_dwb_pri_cnt_s cn38xx;
         struct cvmx_iob_dwb_pri_cnt_s cn38xxp2;
@@ -396,25 +172,16 @@ union cvmx_iob_dwb_pri_cnt {
         struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
         struct cvmx_iob_dwb_pri_cnt_s cn58xx;
         struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
-        struct cvmx_iob_dwb_pri_cnt_s cn61xx;
         struct cvmx_iob_dwb_pri_cnt_s cn63xx;
         struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;
-        struct cvmx_iob_dwb_pri_cnt_s cn66xx;
-        struct cvmx_iob_dwb_pri_cnt_s cnf71xx;
 };
 
 union cvmx_iob_fau_timeout {
         uint64_t u64;
         struct cvmx_iob_fau_timeout_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_13_63:51;
                 uint64_t tout_enb:1;
                 uint64_t tout_val:12;
-#else
-                uint64_t tout_val:12;
-                uint64_t tout_enb:1;
-                uint64_t reserved_13_63:51;
-#endif
         } s;
         struct cvmx_iob_fau_timeout_s cn30xx;
         struct cvmx_iob_fau_timeout_s cn31xx;
@@ -427,27 +194,16 @@ union cvmx_iob_fau_timeout {
         struct cvmx_iob_fau_timeout_s cn56xxp1;
         struct cvmx_iob_fau_timeout_s cn58xx;
         struct cvmx_iob_fau_timeout_s cn58xxp1;
-        struct cvmx_iob_fau_timeout_s cn61xx;
         struct cvmx_iob_fau_timeout_s cn63xx;
         struct cvmx_iob_fau_timeout_s cn63xxp1;
-        struct cvmx_iob_fau_timeout_s cn66xx;
-        struct cvmx_iob_fau_timeout_s cn68xx;
-        struct cvmx_iob_fau_timeout_s cn68xxp1;
-        struct cvmx_iob_fau_timeout_s cnf71xx;
 };
 
 union cvmx_iob_i2c_pri_cnt {
         uint64_t u64;
         struct cvmx_iob_i2c_pri_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt_enb:1;
                 uint64_t cnt_val:15;
-#else
-                uint64_t cnt_val:15;
-                uint64_t cnt_enb:1;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_iob_i2c_pri_cnt_s cn38xx;
         struct cvmx_iob_i2c_pri_cnt_s cn38xxp2;
@@ -457,29 +213,18 @@ union cvmx_iob_i2c_pri_cnt {
         struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
         struct cvmx_iob_i2c_pri_cnt_s cn58xx;
         struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
-        struct cvmx_iob_i2c_pri_cnt_s cn61xx;
         struct cvmx_iob_i2c_pri_cnt_s cn63xx;
         struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;
-        struct cvmx_iob_i2c_pri_cnt_s cn66xx;
-        struct cvmx_iob_i2c_pri_cnt_s cnf71xx;
 };
 
 union cvmx_iob_inb_control_match {
         uint64_t u64;
         struct cvmx_iob_inb_control_match_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t mask:8;
                 uint64_t opc:4;
                 uint64_t dst:9;
                 uint64_t src:8;
-#else
-                uint64_t src:8;
-                uint64_t dst:9;
-                uint64_t opc:4;
-                uint64_t mask:8;
-                uint64_t reserved_29_63:35;
-#endif
         } s;
         struct cvmx_iob_inb_control_match_s cn30xx;
         struct cvmx_iob_inb_control_match_s cn31xx;
@@ -492,31 +237,18 @@ union cvmx_iob_inb_control_match {
         struct cvmx_iob_inb_control_match_s cn56xxp1;
         struct cvmx_iob_inb_control_match_s cn58xx;
         struct cvmx_iob_inb_control_match_s cn58xxp1;
-        struct cvmx_iob_inb_control_match_s cn61xx;
         struct cvmx_iob_inb_control_match_s cn63xx;
         struct cvmx_iob_inb_control_match_s cn63xxp1;
-        struct cvmx_iob_inb_control_match_s cn66xx;
-        struct cvmx_iob_inb_control_match_s cn68xx;
-        struct cvmx_iob_inb_control_match_s cn68xxp1;
-        struct cvmx_iob_inb_control_match_s cnf71xx;
 };
 
 union cvmx_iob_inb_control_match_enb {
         uint64_t u64;
         struct cvmx_iob_inb_control_match_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t mask:8;
                 uint64_t opc:4;
                 uint64_t dst:9;
                 uint64_t src:8;
-#else
-                uint64_t src:8;
-                uint64_t dst:9;
-                uint64_t opc:4;
-                uint64_t mask:8;
-                uint64_t reserved_29_63:35;
-#endif
         } s;
         struct cvmx_iob_inb_control_match_enb_s cn30xx;
         struct cvmx_iob_inb_control_match_enb_s cn31xx;
@@ -529,23 +261,14 @@ union cvmx_iob_inb_control_match_enb {
         struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
         struct cvmx_iob_inb_control_match_enb_s cn58xx;
         struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
-        struct cvmx_iob_inb_control_match_enb_s cn61xx;
         struct cvmx_iob_inb_control_match_enb_s cn63xx;
         struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
-        struct cvmx_iob_inb_control_match_enb_s cn66xx;
-        struct cvmx_iob_inb_control_match_enb_s cn68xx;
-        struct cvmx_iob_inb_control_match_enb_s cn68xxp1;
-        struct cvmx_iob_inb_control_match_enb_s cnf71xx;
 };
 
 union cvmx_iob_inb_data_match {
         uint64_t u64;
         struct cvmx_iob_inb_data_match_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
                 uint64_t data:64;
-#endif
         } s;
         struct cvmx_iob_inb_data_match_s cn30xx;
         struct cvmx_iob_inb_data_match_s cn31xx;
@@ -558,23 +281,14 @@ union cvmx_iob_inb_data_match {
         struct cvmx_iob_inb_data_match_s cn56xxp1;
         struct cvmx_iob_inb_data_match_s cn58xx;
         struct cvmx_iob_inb_data_match_s cn58xxp1;
-        struct cvmx_iob_inb_data_match_s cn61xx;
         struct cvmx_iob_inb_data_match_s cn63xx;
         struct cvmx_iob_inb_data_match_s cn63xxp1;
-        struct cvmx_iob_inb_data_match_s cn66xx;
-        struct cvmx_iob_inb_data_match_s cn68xx;
-        struct cvmx_iob_inb_data_match_s cn68xxp1;
-        struct cvmx_iob_inb_data_match_s cnf71xx;
 };
 
 union cvmx_iob_inb_data_match_enb {
         uint64_t u64;
         struct cvmx_iob_inb_data_match_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
         } s;
         struct cvmx_iob_inb_data_match_enb_s cn30xx;
         struct cvmx_iob_inb_data_match_enb_s cn31xx;
@@ -587,19 +301,13 @@ union cvmx_iob_inb_data_match_enb {
         struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
         struct cvmx_iob_inb_data_match_enb_s cn58xx;
         struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
-        struct cvmx_iob_inb_data_match_enb_s cn61xx;
         struct cvmx_iob_inb_data_match_enb_s cn63xx;
         struct cvmx_iob_inb_data_match_enb_s cn63xxp1;
-        struct cvmx_iob_inb_data_match_enb_s cn66xx;
-        struct cvmx_iob_inb_data_match_enb_s cn68xx;
-        struct cvmx_iob_inb_data_match_enb_s cn68xxp1;
-        struct cvmx_iob_inb_data_match_enb_s cnf71xx;
 };
 
 union cvmx_iob_int_enb {
         uint64_t u64;
         struct cvmx_iob_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t p_dat:1;
                 uint64_t np_dat:1;
@@ -607,30 +315,13 @@ union cvmx_iob_int_enb {
                 uint64_t p_sop:1;
                 uint64_t np_eop:1;
                 uint64_t np_sop:1;
-#else
-                uint64_t np_sop:1;
-                uint64_t np_eop:1;
-                uint64_t p_sop:1;
-                uint64_t p_eop:1;
-                uint64_t np_dat:1;
-                uint64_t p_dat:1;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_iob_int_enb_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t p_eop:1;
                 uint64_t p_sop:1;
                 uint64_t np_eop:1;
                 uint64_t np_sop:1;
-#else
-                uint64_t np_sop:1;
-                uint64_t np_eop:1;
-                uint64_t p_sop:1;
-                uint64_t p_eop:1;
-                uint64_t reserved_4_63:60;
-#endif
         } cn30xx;
         struct cvmx_iob_int_enb_cn30xx cn31xx;
         struct cvmx_iob_int_enb_cn30xx cn38xx;
@@ -642,25 +333,13 @@ union cvmx_iob_int_enb {
         struct cvmx_iob_int_enb_s cn56xxp1;
         struct cvmx_iob_int_enb_s cn58xx;
         struct cvmx_iob_int_enb_s cn58xxp1;
-        struct cvmx_iob_int_enb_s cn61xx;
         struct cvmx_iob_int_enb_s cn63xx;
         struct cvmx_iob_int_enb_s cn63xxp1;
-        struct cvmx_iob_int_enb_s cn66xx;
-        struct cvmx_iob_int_enb_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } cn68xx;
-        struct cvmx_iob_int_enb_cn68xx cn68xxp1;
-        struct cvmx_iob_int_enb_s cnf71xx;
 };
 
 union cvmx_iob_int_sum {
         uint64_t u64;
         struct cvmx_iob_int_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t p_dat:1;
                 uint64_t np_dat:1;
@@ -668,30 +347,13 @@ union cvmx_iob_int_sum {
                 uint64_t p_sop:1;
                 uint64_t np_eop:1;
                 uint64_t np_sop:1;
-#else
-                uint64_t np_sop:1;
-                uint64_t np_eop:1;
-                uint64_t p_sop:1;
-                uint64_t p_eop:1;
-                uint64_t np_dat:1;
-                uint64_t p_dat:1;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_iob_int_sum_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t p_eop:1;
                 uint64_t p_sop:1;
                 uint64_t np_eop:1;
                 uint64_t np_sop:1;
-#else
-                uint64_t np_sop:1;
-                uint64_t np_eop:1;
-                uint64_t p_sop:1;
-                uint64_t p_eop:1;
-                uint64_t reserved_4_63:60;
-#endif
         } cn30xx;
         struct cvmx_iob_int_sum_cn30xx cn31xx;
         struct cvmx_iob_int_sum_cn30xx cn38xx;
@@ -703,33 +365,16 @@ union cvmx_iob_int_sum {
         struct cvmx_iob_int_sum_s cn56xxp1;
         struct cvmx_iob_int_sum_s cn58xx;
         struct cvmx_iob_int_sum_s cn58xxp1;
-        struct cvmx_iob_int_sum_s cn61xx;
         struct cvmx_iob_int_sum_s cn63xx;
         struct cvmx_iob_int_sum_s cn63xxp1;
-        struct cvmx_iob_int_sum_s cn66xx;
-        struct cvmx_iob_int_sum_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } cn68xx;
-        struct cvmx_iob_int_sum_cn68xx cn68xxp1;
-        struct cvmx_iob_int_sum_s cnf71xx;
 };
 
 union cvmx_iob_n2c_l2c_pri_cnt {
         uint64_t u64;
         struct cvmx_iob_n2c_l2c_pri_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt_enb:1;
                 uint64_t cnt_val:15;
-#else
-                uint64_t cnt_val:15;
-                uint64_t cnt_enb:1;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2;
@@ -739,25 +384,16 @@ union cvmx_iob_n2c_l2c_pri_cnt {
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
-        struct cvmx_iob_n2c_l2c_pri_cnt_s cn61xx;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;
-        struct cvmx_iob_n2c_l2c_pri_cnt_s cn66xx;
-        struct cvmx_iob_n2c_l2c_pri_cnt_s cnf71xx;
 };
 
 union cvmx_iob_n2c_rsp_pri_cnt {
         uint64_t u64;
         struct cvmx_iob_n2c_rsp_pri_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt_enb:1;
                 uint64_t cnt_val:15;
-#else
-                uint64_t cnt_val:15;
-                uint64_t cnt_enb:1;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2;
@@ -767,25 +403,16 @@ union cvmx_iob_n2c_rsp_pri_cnt {
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
-        struct cvmx_iob_n2c_rsp_pri_cnt_s cn61xx;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;
-        struct cvmx_iob_n2c_rsp_pri_cnt_s cn66xx;
-        struct cvmx_iob_n2c_rsp_pri_cnt_s cnf71xx;
 };
 
 union cvmx_iob_outb_com_pri_cnt {
         uint64_t u64;
         struct cvmx_iob_outb_com_pri_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt_enb:1;
                 uint64_t cnt_val:15;
-#else
-                uint64_t cnt_val:15;
-                uint64_t cnt_enb:1;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_iob_outb_com_pri_cnt_s cn38xx;
         struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2;
@@ -795,31 +422,18 @@ union cvmx_iob_outb_com_pri_cnt {
         struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
         struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
         struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
-        struct cvmx_iob_outb_com_pri_cnt_s cn61xx;
         struct cvmx_iob_outb_com_pri_cnt_s cn63xx;
         struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;
-        struct cvmx_iob_outb_com_pri_cnt_s cn66xx;
-        struct cvmx_iob_outb_com_pri_cnt_s cn68xx;
-        struct cvmx_iob_outb_com_pri_cnt_s cn68xxp1;
-        struct cvmx_iob_outb_com_pri_cnt_s cnf71xx;
 };
 
 union cvmx_iob_outb_control_match {
         uint64_t u64;
         struct cvmx_iob_outb_control_match_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_26_63:38;
                 uint64_t mask:8;
                 uint64_t eot:1;
                 uint64_t dst:8;
                 uint64_t src:9;
-#else
-                uint64_t src:9;
-                uint64_t dst:8;
-                uint64_t eot:1;
-                uint64_t mask:8;
-                uint64_t reserved_26_63:38;
-#endif
         } s;
         struct cvmx_iob_outb_control_match_s cn30xx;
         struct cvmx_iob_outb_control_match_s cn31xx;
@@ -832,31 +446,18 @@ union cvmx_iob_outb_control_match {
         struct cvmx_iob_outb_control_match_s cn56xxp1;
         struct cvmx_iob_outb_control_match_s cn58xx;
         struct cvmx_iob_outb_control_match_s cn58xxp1;
-        struct cvmx_iob_outb_control_match_s cn61xx;
         struct cvmx_iob_outb_control_match_s cn63xx;
         struct cvmx_iob_outb_control_match_s cn63xxp1;
-        struct cvmx_iob_outb_control_match_s cn66xx;
-        struct cvmx_iob_outb_control_match_s cn68xx;
-        struct cvmx_iob_outb_control_match_s cn68xxp1;
-        struct cvmx_iob_outb_control_match_s cnf71xx;
 };
 
 union cvmx_iob_outb_control_match_enb {
         uint64_t u64;
         struct cvmx_iob_outb_control_match_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_26_63:38;
                 uint64_t mask:8;
                 uint64_t eot:1;
                 uint64_t dst:8;
                 uint64_t src:9;
-#else
-                uint64_t src:9;
-                uint64_t dst:8;
-                uint64_t eot:1;
-                uint64_t mask:8;
-                uint64_t reserved_26_63:38;
-#endif
         } s;
         struct cvmx_iob_outb_control_match_enb_s cn30xx;
         struct cvmx_iob_outb_control_match_enb_s cn31xx;
@@ -869,23 +470,14 @@ union cvmx_iob_outb_control_match_enb {
         struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
         struct cvmx_iob_outb_control_match_enb_s cn58xx;
         struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
-        struct cvmx_iob_outb_control_match_enb_s cn61xx;
         struct cvmx_iob_outb_control_match_enb_s cn63xx;
         struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
-        struct cvmx_iob_outb_control_match_enb_s cn66xx;
-        struct cvmx_iob_outb_control_match_enb_s cn68xx;
-        struct cvmx_iob_outb_control_match_enb_s cn68xxp1;
-        struct cvmx_iob_outb_control_match_enb_s cnf71xx;
 };
 
 union cvmx_iob_outb_data_match {
         uint64_t u64;
         struct cvmx_iob_outb_data_match_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
         } s;
         struct cvmx_iob_outb_data_match_s cn30xx;
         struct cvmx_iob_outb_data_match_s cn31xx;
@@ -898,23 +490,14 @@ union cvmx_iob_outb_data_match {
         struct cvmx_iob_outb_data_match_s cn56xxp1;
         struct cvmx_iob_outb_data_match_s cn58xx;
         struct cvmx_iob_outb_data_match_s cn58xxp1;
-        struct cvmx_iob_outb_data_match_s cn61xx;
         struct cvmx_iob_outb_data_match_s cn63xx;
         struct cvmx_iob_outb_data_match_s cn63xxp1;
-        struct cvmx_iob_outb_data_match_s cn66xx;
-        struct cvmx_iob_outb_data_match_s cn68xx;
-        struct cvmx_iob_outb_data_match_s cn68xxp1;
-        struct cvmx_iob_outb_data_match_s cnf71xx;
 };
 
 union cvmx_iob_outb_data_match_enb {
         uint64_t u64;
         struct cvmx_iob_outb_data_match_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
                 uint64_t data:64;
-#endif
         } s;
         struct cvmx_iob_outb_data_match_enb_s cn30xx;
         struct cvmx_iob_outb_data_match_enb_s cn31xx;
@@ -927,27 +510,16 @@ union cvmx_iob_outb_data_match_enb {
         struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
         struct cvmx_iob_outb_data_match_enb_s cn58xx;
         struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
-        struct cvmx_iob_outb_data_match_enb_s cn61xx;
         struct cvmx_iob_outb_data_match_enb_s cn63xx;
         struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
-        struct cvmx_iob_outb_data_match_enb_s cn66xx;
-        struct cvmx_iob_outb_data_match_enb_s cn68xx;
-        struct cvmx_iob_outb_data_match_enb_s cn68xxp1;
-        struct cvmx_iob_outb_data_match_enb_s cnf71xx;
 };
 
 union cvmx_iob_outb_fpa_pri_cnt {
         uint64_t u64;
         struct cvmx_iob_outb_fpa_pri_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt_enb:1;
                 uint64_t cnt_val:15;
-#else
-                uint64_t cnt_val:15;
-                uint64_t cnt_enb:1;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2;
@@ -957,27 +529,16 @@ union cvmx_iob_outb_fpa_pri_cnt {
         struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
-        struct cvmx_iob_outb_fpa_pri_cnt_s cn61xx;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;
-        struct cvmx_iob_outb_fpa_pri_cnt_s cn66xx;
-        struct cvmx_iob_outb_fpa_pri_cnt_s cn68xx;
-        struct cvmx_iob_outb_fpa_pri_cnt_s cn68xxp1;
-        struct cvmx_iob_outb_fpa_pri_cnt_s cnf71xx;
 };
 
 union cvmx_iob_outb_req_pri_cnt {
         uint64_t u64;
         struct cvmx_iob_outb_req_pri_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt_enb:1;
                 uint64_t cnt_val:15;
-#else
-                uint64_t cnt_val:15;
-                uint64_t cnt_enb:1;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_iob_outb_req_pri_cnt_s cn38xx;
         struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2;
@@ -987,27 +548,16 @@ union cvmx_iob_outb_req_pri_cnt {
         struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
         struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
         struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
-        struct cvmx_iob_outb_req_pri_cnt_s cn61xx;
         struct cvmx_iob_outb_req_pri_cnt_s cn63xx;
         struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;
-        struct cvmx_iob_outb_req_pri_cnt_s cn66xx;
-        struct cvmx_iob_outb_req_pri_cnt_s cn68xx;
-        struct cvmx_iob_outb_req_pri_cnt_s cn68xxp1;
-        struct cvmx_iob_outb_req_pri_cnt_s cnf71xx;
 };
 
 union cvmx_iob_p2c_req_pri_cnt {
         uint64_t u64;
         struct cvmx_iob_p2c_req_pri_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t cnt_enb:1;
                 uint64_t cnt_val:15;
-#else
-                uint64_t cnt_val:15;
-                uint64_t cnt_enb:1;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_iob_p2c_req_pri_cnt_s cn38xx;
         struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2;
@@ -1017,34 +567,20 @@ union cvmx_iob_p2c_req_pri_cnt {
         struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
         struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
         struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
-        struct cvmx_iob_p2c_req_pri_cnt_s cn61xx;
         struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;
         struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;
-        struct cvmx_iob_p2c_req_pri_cnt_s cn66xx;
-        struct cvmx_iob_p2c_req_pri_cnt_s cnf71xx;
 };
 
 union cvmx_iob_pkt_err {
         uint64_t u64;
         struct cvmx_iob_pkt_err_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t vport:6;
                 uint64_t port:6;
-#else
-                uint64_t port:6;
-                uint64_t vport:6;
-                uint64_t reserved_12_63:52;
-#endif
         } s;
         struct cvmx_iob_pkt_err_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t port:6;
-#else
-                uint64_t port:6;
-                uint64_t reserved_6_63:58;
-#endif
         } cn30xx;
         struct cvmx_iob_pkt_err_cn30xx cn31xx;
         struct cvmx_iob_pkt_err_cn30xx cn38xx;
@@ -1056,223 +592,21 @@ union cvmx_iob_pkt_err {
         struct cvmx_iob_pkt_err_cn30xx cn56xxp1;
         struct cvmx_iob_pkt_err_cn30xx cn58xx;
         struct cvmx_iob_pkt_err_cn30xx cn58xxp1;
-        struct cvmx_iob_pkt_err_s cn61xx;
         struct cvmx_iob_pkt_err_s cn63xx;
         struct cvmx_iob_pkt_err_s cn63xxp1;
-        struct cvmx_iob_pkt_err_s cn66xx;
-        struct cvmx_iob_pkt_err_s cnf71xx;
 };
 
 union cvmx_iob_to_cmb_credits {
         uint64_t u64;
         struct cvmx_iob_to_cmb_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t ncb_rd:3;
-                uint64_t ncb_wr:3;
-#else
-                uint64_t ncb_wr:3;
-                uint64_t ncb_rd:3;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_iob_to_cmb_credits_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t pko_rd:3;
                 uint64_t ncb_rd:3;
                 uint64_t ncb_wr:3;
-#else
-                uint64_t ncb_wr:3;
-                uint64_t ncb_rd:3;
-                uint64_t pko_rd:3;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn52xx;
-        struct cvmx_iob_to_cmb_credits_cn52xx cn61xx;
-        struct cvmx_iob_to_cmb_credits_cn52xx cn63xx;
-        struct cvmx_iob_to_cmb_credits_cn52xx cn63xxp1;
-        struct cvmx_iob_to_cmb_credits_cn52xx cn66xx;
-        struct cvmx_iob_to_cmb_credits_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t dwb:3;
-                uint64_t ncb_rd:3;
-                uint64_t ncb_wr:3;
-#else
-                uint64_t ncb_wr:3;
-                uint64_t ncb_rd:3;
-                uint64_t dwb:3;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn68xx;
-        struct cvmx_iob_to_cmb_credits_cn68xx cn68xxp1;
-        struct cvmx_iob_to_cmb_credits_cn52xx cnf71xx;
-};
-
-union cvmx_iob_to_ncb_did_00_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_00_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_00_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_00_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_111_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_111_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_111_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_111_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_223_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_223_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_223_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_223_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_24_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_24_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_24_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_24_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_32_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_32_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_32_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_32_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_40_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_40_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_40_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_40_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_55_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_55_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_55_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_55_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_64_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_64_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_64_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_64_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_79_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_79_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_79_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_79_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_96_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_96_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_iob_to_ncb_did_96_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_96_credits_s cn68xxp1;
-};
-
-union cvmx_iob_to_ncb_did_98_credits {
-        uint64_t u64;
-        struct cvmx_iob_to_ncb_did_98_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t crd:7;
-#else
-                uint64_t crd:7;
-                uint64_t reserved_7_63:57;
-#endif
         } s;
-        struct cvmx_iob_to_ncb_did_98_credits_s cn68xx;
-        struct cvmx_iob_to_ncb_did_98_credits_s cn68xxp1;
+        struct cvmx_iob_to_cmb_credits_s cn52xx;
+        struct cvmx_iob_to_cmb_credits_s cn63xx;
+        struct cvmx_iob_to_cmb_credits_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
index 1193f73bb74..e0a5bfe88d0 100644
--- a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -32,37 +32,23 @@
 #define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
 #define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
 #define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
-#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8)
-#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8)
 #define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
 #define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
-#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull))
 #define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
-#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull))
-#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull))
-#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull))
-#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull))
 #define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
 #define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
-#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull))
-#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull))
 #define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
-#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull))
 #define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
-#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull))
 #define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
 #define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
 #define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
 #define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
 #define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
 #define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
-#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44)
 #define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
-#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull))
 #define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
 #define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
 #define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
-#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull))
 #define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
 #define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
 #define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
@@ -77,8 +63,6 @@
 #define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
 #define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
 #define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
-#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull))
-#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull))
 #define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
 #define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
 #define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
@@ -90,7 +74,6 @@
 #define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
 #define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
 #define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
-#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull))
 #define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
 #define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
 #define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
@@ -100,13 +83,8 @@
 union cvmx_ipd_1st_mbuff_skip {
         uint64_t u64;
         struct cvmx_ipd_1st_mbuff_skip_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t skip_sz:6;
-#else
-                uint64_t skip_sz:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_ipd_1st_mbuff_skip_s cn30xx;
         struct cvmx_ipd_1st_mbuff_skip_s cn31xx;
@@ -119,25 +97,15 @@ union cvmx_ipd_1st_mbuff_skip {
         struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
         struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
         struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
-        struct cvmx_ipd_1st_mbuff_skip_s cn61xx;
         struct cvmx_ipd_1st_mbuff_skip_s cn63xx;
         struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1;
-        struct cvmx_ipd_1st_mbuff_skip_s cn66xx;
-        struct cvmx_ipd_1st_mbuff_skip_s cn68xx;
-        struct cvmx_ipd_1st_mbuff_skip_s cn68xxp1;
-        struct cvmx_ipd_1st_mbuff_skip_s cnf71xx;
 };
 
 union cvmx_ipd_1st_next_ptr_back {
         uint64_t u64;
         struct cvmx_ipd_1st_next_ptr_back_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t back:4;
-#else
-                uint64_t back:4;
-                uint64_t reserved_4_63:60;
-#endif
         } s;
         struct cvmx_ipd_1st_next_ptr_back_s cn30xx;
         struct cvmx_ipd_1st_next_ptr_back_s cn31xx;
@@ -150,25 +118,15 @@ union cvmx_ipd_1st_next_ptr_back {
         struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
         struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
         struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
-        struct cvmx_ipd_1st_next_ptr_back_s cn61xx;
         struct cvmx_ipd_1st_next_ptr_back_s cn63xx;
         struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1;
-        struct cvmx_ipd_1st_next_ptr_back_s cn66xx;
-        struct cvmx_ipd_1st_next_ptr_back_s cn68xx;
-        struct cvmx_ipd_1st_next_ptr_back_s cn68xxp1;
-        struct cvmx_ipd_1st_next_ptr_back_s cnf71xx;
 };
 
 union cvmx_ipd_2nd_next_ptr_back {
         uint64_t u64;
         struct cvmx_ipd_2nd_next_ptr_back_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t back:4;
-#else
-                uint64_t back:4;
-                uint64_t reserved_4_63:60;
-#endif
         } s;
         struct cvmx_ipd_2nd_next_ptr_back_s cn30xx;
         struct cvmx_ipd_2nd_next_ptr_back_s cn31xx;
@@ -181,25 +139,14 @@ union cvmx_ipd_2nd_next_ptr_back {
         struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
         struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
         struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
-        struct cvmx_ipd_2nd_next_ptr_back_s cn61xx;
         struct cvmx_ipd_2nd_next_ptr_back_s cn63xx;
         struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1;
-        struct cvmx_ipd_2nd_next_ptr_back_s cn66xx;
-        struct cvmx_ipd_2nd_next_ptr_back_s cn68xx;
-        struct cvmx_ipd_2nd_next_ptr_back_s cn68xxp1;
-        struct cvmx_ipd_2nd_next_ptr_back_s cnf71xx;
 };
 
 union cvmx_ipd_bist_status {
         uint64_t u64;
         struct cvmx_ipd_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t iiwo1:1;
-                uint64_t iiwo0:1;
-                uint64_t iio1:1;
-                uint64_t iio0:1;
-                uint64_t pbm4:1;
+                uint64_t reserved_18_63:46;
                 uint64_t csr_mem:1;
                 uint64_t csr_ncmd:1;
                 uint64_t pwq_wqed:1;
@@ -218,35 +165,8 @@ union cvmx_ipd_bist_status {
                 uint64_t ipd_old:1;
                 uint64_t ipd_new:1;
                 uint64_t pwp:1;
-#else
-                uint64_t pwp:1;
-                uint64_t ipd_new:1;
-                uint64_t ipd_old:1;
-                uint64_t prc_off:1;
-                uint64_t pwq0:1;
-                uint64_t pwq1:1;
-                uint64_t pbm_word:1;
-                uint64_t pbm0:1;
-                uint64_t pbm1:1;
-                uint64_t pbm2:1;
-                uint64_t pbm3:1;
-                uint64_t ipq_pbe0:1;
-                uint64_t ipq_pbe1:1;
-                uint64_t pwq_pow:1;
-                uint64_t pwq_wp1:1;
-                uint64_t pwq_wqed:1;
-                uint64_t csr_ncmd:1;
-                uint64_t csr_mem:1;
-                uint64_t pbm4:1;
-                uint64_t iio0:1;
-                uint64_t iio1:1;
-                uint64_t iiwo0:1;
-                uint64_t iiwo1:1;
-                uint64_t reserved_23_63:41;
-#endif
         } s;
         struct cvmx_ipd_bist_status_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t pwq_wqed:1;
                 uint64_t pwq_wp1:1;
@@ -264,180 +184,52 @@ union cvmx_ipd_bist_status {
                 uint64_t ipd_old:1;
                 uint64_t ipd_new:1;
                 uint64_t pwp:1;
-#else
-                uint64_t pwp:1;
-                uint64_t ipd_new:1;
-                uint64_t ipd_old:1;
-                uint64_t prc_off:1;
-                uint64_t pwq0:1;
-                uint64_t pwq1:1;
-                uint64_t pbm_word:1;
-                uint64_t pbm0:1;
-                uint64_t pbm1:1;
-                uint64_t pbm2:1;
-                uint64_t pbm3:1;
-                uint64_t ipq_pbe0:1;
-                uint64_t ipq_pbe1:1;
-                uint64_t pwq_pow:1;
-                uint64_t pwq_wp1:1;
-                uint64_t pwq_wqed:1;
-                uint64_t reserved_16_63:48;
-#endif
         } cn30xx;
         struct cvmx_ipd_bist_status_cn30xx cn31xx;
         struct cvmx_ipd_bist_status_cn30xx cn38xx;
         struct cvmx_ipd_bist_status_cn30xx cn38xxp2;
         struct cvmx_ipd_bist_status_cn30xx cn50xx;
-        struct cvmx_ipd_bist_status_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_18_63:46;
-                uint64_t csr_mem:1;
-                uint64_t csr_ncmd:1;
-                uint64_t pwq_wqed:1;
-                uint64_t pwq_wp1:1;
-                uint64_t pwq_pow:1;
-                uint64_t ipq_pbe1:1;
-                uint64_t ipq_pbe0:1;
-                uint64_t pbm3:1;
-                uint64_t pbm2:1;
-                uint64_t pbm1:1;
-                uint64_t pbm0:1;
-                uint64_t pbm_word:1;
-                uint64_t pwq1:1;
-                uint64_t pwq0:1;
-                uint64_t prc_off:1;
-                uint64_t ipd_old:1;
-                uint64_t ipd_new:1;
-                uint64_t pwp:1;
-#else
-                uint64_t pwp:1;
-                uint64_t ipd_new:1;
-                uint64_t ipd_old:1;
-                uint64_t prc_off:1;
-                uint64_t pwq0:1;
-                uint64_t pwq1:1;
-                uint64_t pbm_word:1;
-                uint64_t pbm0:1;
-                uint64_t pbm1:1;
-                uint64_t pbm2:1;
-                uint64_t pbm3:1;
-                uint64_t ipq_pbe0:1;
-                uint64_t ipq_pbe1:1;
-                uint64_t pwq_pow:1;
-                uint64_t pwq_wp1:1;
-                uint64_t pwq_wqed:1;
-                uint64_t csr_ncmd:1;
-                uint64_t csr_mem:1;
-                uint64_t reserved_18_63:46;
-#endif
-        } cn52xx;
-        struct cvmx_ipd_bist_status_cn52xx cn52xxp1;
-        struct cvmx_ipd_bist_status_cn52xx cn56xx;
-        struct cvmx_ipd_bist_status_cn52xx cn56xxp1;
+        struct cvmx_ipd_bist_status_s cn52xx;
+        struct cvmx_ipd_bist_status_s cn52xxp1;
+        struct cvmx_ipd_bist_status_s cn56xx;
+        struct cvmx_ipd_bist_status_s cn56xxp1;
         struct cvmx_ipd_bist_status_cn30xx cn58xx;
         struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
-        struct cvmx_ipd_bist_status_cn52xx cn61xx;
-        struct cvmx_ipd_bist_status_cn52xx cn63xx;
-        struct cvmx_ipd_bist_status_cn52xx cn63xxp1;
-        struct cvmx_ipd_bist_status_cn52xx cn66xx;
-        struct cvmx_ipd_bist_status_s cn68xx;
-        struct cvmx_ipd_bist_status_s cn68xxp1;
-        struct cvmx_ipd_bist_status_cn52xx cnf71xx;
+        struct cvmx_ipd_bist_status_s cn63xx;
+        struct cvmx_ipd_bist_status_s cn63xxp1;
 };
 
 union cvmx_ipd_bp_prt_red_end {
         uint64_t u64;
         struct cvmx_ipd_bp_prt_red_end_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t prt_enb:48;
-#else
-                uint64_t prt_enb:48;
-                uint64_t reserved_48_63:16;
-#endif
+                uint64_t reserved_44_63:20;
+                uint64_t prt_enb:44;
         } s;
         struct cvmx_ipd_bp_prt_red_end_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t prt_enb:36;
-#else
-                uint64_t prt_enb:36;
-                uint64_t reserved_36_63:28;
-#endif
         } cn30xx;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
         struct cvmx_ipd_bp_prt_red_end_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t prt_enb:40;
-#else
-                uint64_t prt_enb:40;
-                uint64_t reserved_40_63:24;
-#endif
         } cn52xx;
         struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1;
         struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx;
         struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
-        struct cvmx_ipd_bp_prt_red_end_s cn61xx;
-        struct cvmx_ipd_bp_prt_red_end_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t prt_enb:44;
-#else
-                uint64_t prt_enb:44;
-                uint64_t reserved_44_63:20;
-#endif
-        } cn63xx;
-        struct cvmx_ipd_bp_prt_red_end_cn63xx cn63xxp1;
-        struct cvmx_ipd_bp_prt_red_end_s cn66xx;
-        struct cvmx_ipd_bp_prt_red_end_s cnf71xx;
-};
-
-union cvmx_ipd_bpidx_mbuf_th {
-        uint64_t u64;
-        struct cvmx_ipd_bpidx_mbuf_th_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_18_63:46;
-                uint64_t bp_enb:1;
-                uint64_t page_cnt:17;
-#else
-                uint64_t page_cnt:17;
-                uint64_t bp_enb:1;
-                uint64_t reserved_18_63:46;
-#endif
-        } s;
-        struct cvmx_ipd_bpidx_mbuf_th_s cn68xx;
-        struct cvmx_ipd_bpidx_mbuf_th_s cn68xxp1;
-};
-
-union cvmx_ipd_bpid_bp_counterx {
-        uint64_t u64;
-        struct cvmx_ipd_bpid_bp_counterx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t cnt_val:25;
-#else
-                uint64_t cnt_val:25;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_ipd_bpid_bp_counterx_s cn68xx;
-        struct cvmx_ipd_bpid_bp_counterx_s cn68xxp1;
+        struct cvmx_ipd_bp_prt_red_end_s cn63xx;
+        struct cvmx_ipd_bp_prt_red_end_s cn63xxp1;
 };
 
 union cvmx_ipd_clk_count {
         uint64_t u64;
         struct cvmx_ipd_clk_count_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t clk_cnt:64;
-#else
-                uint64_t clk_cnt:64;
-#endif
         } s;
         struct cvmx_ipd_clk_count_s cn30xx;
         struct cvmx_ipd_clk_count_s cn31xx;
@@ -450,36 +242,13 @@ union cvmx_ipd_clk_count {
         struct cvmx_ipd_clk_count_s cn56xxp1;
         struct cvmx_ipd_clk_count_s cn58xx;
         struct cvmx_ipd_clk_count_s cn58xxp1;
-        struct cvmx_ipd_clk_count_s cn61xx;
         struct cvmx_ipd_clk_count_s cn63xx;
         struct cvmx_ipd_clk_count_s cn63xxp1;
-        struct cvmx_ipd_clk_count_s cn66xx;
-        struct cvmx_ipd_clk_count_s cn68xx;
-        struct cvmx_ipd_clk_count_s cn68xxp1;
-        struct cvmx_ipd_clk_count_s cnf71xx;
-};
-
-union cvmx_ipd_credits {
-        uint64_t u64;
-        struct cvmx_ipd_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t iob_wrc:8;
-                uint64_t iob_wr:8;
-#else
-                uint64_t iob_wr:8;
-                uint64_t iob_wrc:8;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_ipd_credits_s cn68xx;
-        struct cvmx_ipd_credits_s cn68xxp1;
 };
 
 union cvmx_ipd_ctl_status {
         uint64_t u64;
         struct cvmx_ipd_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t use_sop:1;
                 uint64_t rst_done:1;
@@ -498,29 +267,8 @@ union cvmx_ipd_ctl_status {
                 uint64_t pbp_en:1;
                 uint64_t opc_mode:2;
                 uint64_t ipd_en:1;
-#else
-                uint64_t ipd_en:1;
-                uint64_t opc_mode:2;
-                uint64_t pbp_en:1;
-                uint64_t wqe_lend:1;
-                uint64_t pkt_lend:1;
-                uint64_t naddbuf:1;
-                uint64_t addpkt:1;
-                uint64_t reset:1;
-                uint64_t len_m8:1;
-                uint64_t pkt_off:1;
-                uint64_t ipd_full:1;
-                uint64_t pq_nabuf:1;
-                uint64_t pq_apkt:1;
-                uint64_t no_wptr:1;
-                uint64_t clken:1;
-                uint64_t rst_done:1;
-                uint64_t use_sop:1;
-                uint64_t reserved_18_63:46;
-#endif
         } s;
         struct cvmx_ipd_ctl_status_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t len_m8:1;
                 uint64_t reset:1;
@@ -531,23 +279,10 @@ union cvmx_ipd_ctl_status {
                 uint64_t pbp_en:1;
                 uint64_t opc_mode:2;
                 uint64_t ipd_en:1;
-#else
-                uint64_t ipd_en:1;
-                uint64_t opc_mode:2;
-                uint64_t pbp_en:1;
-                uint64_t wqe_lend:1;
-                uint64_t pkt_lend:1;
-                uint64_t naddbuf:1;
-                uint64_t addpkt:1;
-                uint64_t reset:1;
-                uint64_t len_m8:1;
-                uint64_t reserved_10_63:54;
-#endif
         } cn30xx;
         struct cvmx_ipd_ctl_status_cn30xx cn31xx;
         struct cvmx_ipd_ctl_status_cn30xx cn38xx;
         struct cvmx_ipd_ctl_status_cn38xxp2 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t reset:1;
                 uint64_t addpkt:1;
@@ -557,20 +292,8 @@ union cvmx_ipd_ctl_status {
                 uint64_t pbp_en:1;
                 uint64_t opc_mode:2;
                 uint64_t ipd_en:1;
-#else
-                uint64_t ipd_en:1;
-                uint64_t opc_mode:2;
-                uint64_t pbp_en:1;
-                uint64_t wqe_lend:1;
-                uint64_t pkt_lend:1;
-                uint64_t naddbuf:1;
-                uint64_t addpkt:1;
-                uint64_t reset:1;
-                uint64_t reserved_9_63:55;
-#endif
         } cn38xxp2;
         struct cvmx_ipd_ctl_status_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_15_63:49;
                 uint64_t no_wptr:1;
                 uint64_t pq_apkt:1;
@@ -586,30 +309,12 @@ union cvmx_ipd_ctl_status {
                 uint64_t pbp_en:1;
                 uint64_t opc_mode:2;
                 uint64_t ipd_en:1;
-#else
-                uint64_t ipd_en:1;
-                uint64_t opc_mode:2;
-                uint64_t pbp_en:1;
-                uint64_t wqe_lend:1;
-                uint64_t pkt_lend:1;
-                uint64_t naddbuf:1;
-                uint64_t addpkt:1;
-                uint64_t reset:1;
-                uint64_t len_m8:1;
-                uint64_t pkt_off:1;
-                uint64_t ipd_full:1;
-                uint64_t pq_nabuf:1;
-                uint64_t pq_apkt:1;
-                uint64_t no_wptr:1;
-                uint64_t reserved_15_63:49;
-#endif
         } cn50xx;
         struct cvmx_ipd_ctl_status_cn50xx cn52xx;
         struct cvmx_ipd_ctl_status_cn50xx cn52xxp1;
         struct cvmx_ipd_ctl_status_cn50xx cn56xx;
         struct cvmx_ipd_ctl_status_cn50xx cn56xxp1;
         struct cvmx_ipd_ctl_status_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t ipd_full:1;
                 uint64_t pkt_off:1;
@@ -622,26 +327,10 @@ union cvmx_ipd_ctl_status {
                 uint64_t pbp_en:1;
                 uint64_t opc_mode:2;
                 uint64_t ipd_en:1;
-#else
-                uint64_t ipd_en:1;
-                uint64_t opc_mode:2;
-                uint64_t pbp_en:1;
-                uint64_t wqe_lend:1;
-                uint64_t pkt_lend:1;
-                uint64_t naddbuf:1;
-                uint64_t addpkt:1;
-                uint64_t reset:1;
-                uint64_t len_m8:1;
-                uint64_t pkt_off:1;
-                uint64_t ipd_full:1;
-                uint64_t reserved_12_63:52;
-#endif
         } cn58xx;
         struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
-        struct cvmx_ipd_ctl_status_s cn61xx;
         struct cvmx_ipd_ctl_status_s cn63xx;
         struct cvmx_ipd_ctl_status_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t clken:1;
                 uint64_t no_wptr:1;
@@ -658,129 +347,13 @@ union cvmx_ipd_ctl_status {
                 uint64_t pbp_en:1;
                 uint64_t opc_mode:2;
                 uint64_t ipd_en:1;
-#else
-                uint64_t ipd_en:1;
-                uint64_t opc_mode:2;
-                uint64_t pbp_en:1;
-                uint64_t wqe_lend:1;
-                uint64_t pkt_lend:1;
-                uint64_t naddbuf:1;
-                uint64_t addpkt:1;
-                uint64_t reset:1;
-                uint64_t len_m8:1;
-                uint64_t pkt_off:1;
-                uint64_t ipd_full:1;
-                uint64_t pq_nabuf:1;
-                uint64_t pq_apkt:1;
-                uint64_t no_wptr:1;
-                uint64_t clken:1;
-                uint64_t reserved_16_63:48;
-#endif
         } cn63xxp1;
-        struct cvmx_ipd_ctl_status_s cn66xx;
-        struct cvmx_ipd_ctl_status_s cn68xx;
-        struct cvmx_ipd_ctl_status_s cn68xxp1;
-        struct cvmx_ipd_ctl_status_s cnf71xx;
-};
-
-union cvmx_ipd_ecc_ctl {
-        uint64_t u64;
-        struct cvmx_ipd_ecc_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t pm3_syn:2;
-                uint64_t pm2_syn:2;
-                uint64_t pm1_syn:2;
-                uint64_t pm0_syn:2;
-#else
-                uint64_t pm0_syn:2;
-                uint64_t pm1_syn:2;
-                uint64_t pm2_syn:2;
-                uint64_t pm3_syn:2;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_ipd_ecc_ctl_s cn68xx;
-        struct cvmx_ipd_ecc_ctl_s cn68xxp1;
-};
-
-union cvmx_ipd_free_ptr_fifo_ctl {
-        uint64_t u64;
-        struct cvmx_ipd_free_ptr_fifo_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t max_cnts:7;
-                uint64_t wraddr:8;
-                uint64_t praddr:8;
-                uint64_t cena:1;
-                uint64_t raddr:8;
-#else
-                uint64_t raddr:8;
-                uint64_t cena:1;
-                uint64_t praddr:8;
-                uint64_t wraddr:8;
-                uint64_t max_cnts:7;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xx;
-        struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xxp1;
-};
-
-union cvmx_ipd_free_ptr_value {
-        uint64_t u64;
-        struct cvmx_ipd_free_ptr_value_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t ptr:33;
-#else
-                uint64_t ptr:33;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_ipd_free_ptr_value_s cn68xx;
-        struct cvmx_ipd_free_ptr_value_s cn68xxp1;
-};
-
-union cvmx_ipd_hold_ptr_fifo_ctl {
-        uint64_t u64;
-        struct cvmx_ipd_hold_ptr_fifo_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_43_63:21;
-                uint64_t ptr:33;
-                uint64_t max_pkt:3;
-                uint64_t praddr:3;
-                uint64_t cena:1;
-                uint64_t raddr:3;
-#else
-                uint64_t raddr:3;
-                uint64_t cena:1;
-                uint64_t praddr:3;
-                uint64_t max_pkt:3;
-                uint64_t ptr:33;
-                uint64_t reserved_43_63:21;
-#endif
-        } s;
-        struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xx;
-        struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xxp1;
 };
 
 union cvmx_ipd_int_enb {
         uint64_t u64;
         struct cvmx_ipd_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t pw3_dbe:1;
-                uint64_t pw3_sbe:1;
-                uint64_t pw2_dbe:1;
-                uint64_t pw2_sbe:1;
-                uint64_t pw1_dbe:1;
-                uint64_t pw1_sbe:1;
-                uint64_t pw0_dbe:1;
-                uint64_t pw0_sbe:1;
-                uint64_t dat:1;
-                uint64_t eop:1;
-                uint64_t sop:1;
+                uint64_t reserved_12_63:52;
                 uint64_t pq_sub:1;
                 uint64_t pq_add:1;
                 uint64_t bc_ovr:1;
@@ -793,53 +366,17 @@ union cvmx_ipd_int_enb {
                 uint64_t prc_par2:1;
                 uint64_t prc_par1:1;
                 uint64_t prc_par0:1;
-#else
-                uint64_t prc_par0:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par3:1;
-                uint64_t bp_sub:1;
-                uint64_t dc_ovr:1;
-                uint64_t cc_ovr:1;
-                uint64_t c_coll:1;
-                uint64_t d_coll:1;
-                uint64_t bc_ovr:1;
-                uint64_t pq_add:1;
-                uint64_t pq_sub:1;
-                uint64_t sop:1;
-                uint64_t eop:1;
-                uint64_t dat:1;
-                uint64_t pw0_sbe:1;
-                uint64_t pw0_dbe:1;
-                uint64_t pw1_sbe:1;
-                uint64_t pw1_dbe:1;
-                uint64_t pw2_sbe:1;
-                uint64_t pw2_dbe:1;
-                uint64_t pw3_sbe:1;
-                uint64_t pw3_dbe:1;
-                uint64_t reserved_23_63:41;
-#endif
         } s;
         struct cvmx_ipd_int_enb_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t bp_sub:1;
                 uint64_t prc_par3:1;
                 uint64_t prc_par2:1;
                 uint64_t prc_par1:1;
                 uint64_t prc_par0:1;
-#else
-                uint64_t prc_par0:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par3:1;
-                uint64_t bp_sub:1;
-                uint64_t reserved_5_63:59;
-#endif
         } cn30xx;
         struct cvmx_ipd_int_enb_cn30xx cn31xx;
         struct cvmx_ipd_int_enb_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t bc_ovr:1;
                 uint64_t d_coll:1;
@@ -851,83 +388,23 @@ union cvmx_ipd_int_enb {
                 uint64_t prc_par2:1;
                 uint64_t prc_par1:1;
                 uint64_t prc_par0:1;
-#else
-                uint64_t prc_par0:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par3:1;
-                uint64_t bp_sub:1;
-                uint64_t dc_ovr:1;
-                uint64_t cc_ovr:1;
-                uint64_t c_coll:1;
-                uint64_t d_coll:1;
-                uint64_t bc_ovr:1;
-                uint64_t reserved_10_63:54;
-#endif
         } cn38xx;
         struct cvmx_ipd_int_enb_cn30xx cn38xxp2;
         struct cvmx_ipd_int_enb_cn38xx cn50xx;
-        struct cvmx_ipd_int_enb_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t pq_sub:1;
-                uint64_t pq_add:1;
-                uint64_t bc_ovr:1;
-                uint64_t d_coll:1;
-                uint64_t c_coll:1;
-                uint64_t cc_ovr:1;
-                uint64_t dc_ovr:1;
-                uint64_t bp_sub:1;
-                uint64_t prc_par3:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par0:1;
-#else
-                uint64_t prc_par0:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par3:1;
-                uint64_t bp_sub:1;
-                uint64_t dc_ovr:1;
-                uint64_t cc_ovr:1;
-                uint64_t c_coll:1;
-                uint64_t d_coll:1;
-                uint64_t bc_ovr:1;
-                uint64_t pq_add:1;
-                uint64_t pq_sub:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn52xx;
-        struct cvmx_ipd_int_enb_cn52xx cn52xxp1;
-        struct cvmx_ipd_int_enb_cn52xx cn56xx;
-        struct cvmx_ipd_int_enb_cn52xx cn56xxp1;
+        struct cvmx_ipd_int_enb_s cn52xx;
+        struct cvmx_ipd_int_enb_s cn52xxp1;
+        struct cvmx_ipd_int_enb_s cn56xx;
+        struct cvmx_ipd_int_enb_s cn56xxp1;
         struct cvmx_ipd_int_enb_cn38xx cn58xx;
         struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
-        struct cvmx_ipd_int_enb_cn52xx cn61xx;
-        struct cvmx_ipd_int_enb_cn52xx cn63xx;
-        struct cvmx_ipd_int_enb_cn52xx cn63xxp1;
-        struct cvmx_ipd_int_enb_cn52xx cn66xx;
-        struct cvmx_ipd_int_enb_s cn68xx;
-        struct cvmx_ipd_int_enb_s cn68xxp1;
-        struct cvmx_ipd_int_enb_cn52xx cnf71xx;
+        struct cvmx_ipd_int_enb_s cn63xx;
+        struct cvmx_ipd_int_enb_s cn63xxp1;
 };
 
 union cvmx_ipd_int_sum {
         uint64_t u64;
         struct cvmx_ipd_int_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t pw3_dbe:1;
-                uint64_t pw3_sbe:1;
-                uint64_t pw2_dbe:1;
-                uint64_t pw2_sbe:1;
-                uint64_t pw1_dbe:1;
-                uint64_t pw1_sbe:1;
-                uint64_t pw0_dbe:1;
-                uint64_t pw0_sbe:1;
-                uint64_t dat:1;
-                uint64_t eop:1;
-                uint64_t sop:1;
+                uint64_t reserved_12_63:52;
                 uint64_t pq_sub:1;
                 uint64_t pq_add:1;
                 uint64_t bc_ovr:1;
@@ -940,53 +417,17 @@ union cvmx_ipd_int_sum {
                 uint64_t prc_par2:1;
                 uint64_t prc_par1:1;
                 uint64_t prc_par0:1;
-#else
-                uint64_t prc_par0:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par3:1;
-                uint64_t bp_sub:1;
-                uint64_t dc_ovr:1;
-                uint64_t cc_ovr:1;
-                uint64_t c_coll:1;
-                uint64_t d_coll:1;
-                uint64_t bc_ovr:1;
-                uint64_t pq_add:1;
-                uint64_t pq_sub:1;
-                uint64_t sop:1;
-                uint64_t eop:1;
-                uint64_t dat:1;
-                uint64_t pw0_sbe:1;
-                uint64_t pw0_dbe:1;
-                uint64_t pw1_sbe:1;
-                uint64_t pw1_dbe:1;
-                uint64_t pw2_sbe:1;
-                uint64_t pw2_dbe:1;
-                uint64_t pw3_sbe:1;
-                uint64_t pw3_dbe:1;
-                uint64_t reserved_23_63:41;
-#endif
         } s;
         struct cvmx_ipd_int_sum_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t bp_sub:1;
                 uint64_t prc_par3:1;
                 uint64_t prc_par2:1;
                 uint64_t prc_par1:1;
                 uint64_t prc_par0:1;
-#else
-                uint64_t prc_par0:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par3:1;
-                uint64_t bp_sub:1;
-                uint64_t reserved_5_63:59;
-#endif
         } cn30xx;
         struct cvmx_ipd_int_sum_cn30xx cn31xx;
         struct cvmx_ipd_int_sum_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t bc_ovr:1;
                 uint64_t d_coll:1;
@@ -998,107 +439,24 @@ union cvmx_ipd_int_sum {
                 uint64_t prc_par2:1;
                 uint64_t prc_par1:1;
                 uint64_t prc_par0:1;
-#else
-                uint64_t prc_par0:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par3:1;
-                uint64_t bp_sub:1;
-                uint64_t dc_ovr:1;
-                uint64_t cc_ovr:1;
-                uint64_t c_coll:1;
-                uint64_t d_coll:1;
-                uint64_t bc_ovr:1;
-                uint64_t reserved_10_63:54;
-#endif
         } cn38xx;
         struct cvmx_ipd_int_sum_cn30xx cn38xxp2;
         struct cvmx_ipd_int_sum_cn38xx cn50xx;
-        struct cvmx_ipd_int_sum_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t pq_sub:1;
-                uint64_t pq_add:1;
-                uint64_t bc_ovr:1;
-                uint64_t d_coll:1;
-                uint64_t c_coll:1;
-                uint64_t cc_ovr:1;
-                uint64_t dc_ovr:1;
-                uint64_t bp_sub:1;
-                uint64_t prc_par3:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par0:1;
-#else
-                uint64_t prc_par0:1;
-                uint64_t prc_par1:1;
-                uint64_t prc_par2:1;
-                uint64_t prc_par3:1;
-                uint64_t bp_sub:1;
-                uint64_t dc_ovr:1;
-                uint64_t cc_ovr:1;
-                uint64_t c_coll:1;
-                uint64_t d_coll:1;
-                uint64_t bc_ovr:1;
-                uint64_t pq_add:1;
-                uint64_t pq_sub:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn52xx;
-        struct cvmx_ipd_int_sum_cn52xx cn52xxp1;
-        struct cvmx_ipd_int_sum_cn52xx cn56xx;
-        struct cvmx_ipd_int_sum_cn52xx cn56xxp1;
+        struct cvmx_ipd_int_sum_s cn52xx;
+        struct cvmx_ipd_int_sum_s cn52xxp1;
+        struct cvmx_ipd_int_sum_s cn56xx;
+        struct cvmx_ipd_int_sum_s cn56xxp1;
         struct cvmx_ipd_int_sum_cn38xx cn58xx;
         struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
-        struct cvmx_ipd_int_sum_cn52xx cn61xx;
-        struct cvmx_ipd_int_sum_cn52xx cn63xx;
-        struct cvmx_ipd_int_sum_cn52xx cn63xxp1;
-        struct cvmx_ipd_int_sum_cn52xx cn66xx;
-        struct cvmx_ipd_int_sum_s cn68xx;
-        struct cvmx_ipd_int_sum_s cn68xxp1;
-        struct cvmx_ipd_int_sum_cn52xx cnf71xx;
-};
-
-union cvmx_ipd_next_pkt_ptr {
-        uint64_t u64;
-        struct cvmx_ipd_next_pkt_ptr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t ptr:33;
-#else
-                uint64_t ptr:33;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_ipd_next_pkt_ptr_s cn68xx;
-        struct cvmx_ipd_next_pkt_ptr_s cn68xxp1;
-};
-
-union cvmx_ipd_next_wqe_ptr {
-        uint64_t u64;
-        struct cvmx_ipd_next_wqe_ptr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t ptr:33;
-#else
-                uint64_t ptr:33;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_ipd_next_wqe_ptr_s cn68xx;
-        struct cvmx_ipd_next_wqe_ptr_s cn68xxp1;
+        struct cvmx_ipd_int_sum_s cn63xx;
+        struct cvmx_ipd_int_sum_s cn63xxp1;
 };
 
 union cvmx_ipd_not_1st_mbuff_skip {
         uint64_t u64;
         struct cvmx_ipd_not_1st_mbuff_skip_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t skip_sz:6;
-#else
-                uint64_t skip_sz:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx;
@@ -1111,38 +469,15 @@ union cvmx_ipd_not_1st_mbuff_skip {
         struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
-        struct cvmx_ipd_not_1st_mbuff_skip_s cn61xx;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1;
-        struct cvmx_ipd_not_1st_mbuff_skip_s cn66xx;
-        struct cvmx_ipd_not_1st_mbuff_skip_s cn68xx;
-        struct cvmx_ipd_not_1st_mbuff_skip_s cn68xxp1;
-        struct cvmx_ipd_not_1st_mbuff_skip_s cnf71xx;
-};
-
-union cvmx_ipd_on_bp_drop_pktx {
-        uint64_t u64;
-        struct cvmx_ipd_on_bp_drop_pktx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t prt_enb:64;
-#else
-                uint64_t prt_enb:64;
-#endif
-        } s;
-        struct cvmx_ipd_on_bp_drop_pktx_s cn68xx;
-        struct cvmx_ipd_on_bp_drop_pktx_s cn68xxp1;
 };
 
 union cvmx_ipd_packet_mbuff_size {
         uint64_t u64;
         struct cvmx_ipd_packet_mbuff_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t mb_size:12;
-#else
-                uint64_t mb_size:12;
-                uint64_t reserved_12_63:52;
-#endif
         } s;
         struct cvmx_ipd_packet_mbuff_size_s cn30xx;
         struct cvmx_ipd_packet_mbuff_size_s cn31xx;
@@ -1155,40 +490,15 @@ union cvmx_ipd_packet_mbuff_size {
         struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
         struct cvmx_ipd_packet_mbuff_size_s cn58xx;
         struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
-        struct cvmx_ipd_packet_mbuff_size_s cn61xx;
         struct cvmx_ipd_packet_mbuff_size_s cn63xx;
         struct cvmx_ipd_packet_mbuff_size_s cn63xxp1;
-        struct cvmx_ipd_packet_mbuff_size_s cn66xx;
-        struct cvmx_ipd_packet_mbuff_size_s cn68xx;
-        struct cvmx_ipd_packet_mbuff_size_s cn68xxp1;
-        struct cvmx_ipd_packet_mbuff_size_s cnf71xx;
-};
-
-union cvmx_ipd_pkt_err {
-        uint64_t u64;
-        struct cvmx_ipd_pkt_err_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t reasm:6;
-#else
-                uint64_t reasm:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_ipd_pkt_err_s cn68xx;
-        struct cvmx_ipd_pkt_err_s cn68xxp1;
 };
 
 union cvmx_ipd_pkt_ptr_valid {
         uint64_t u64;
         struct cvmx_ipd_pkt_ptr_valid_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t ptr:29;
-#else
-                uint64_t ptr:29;
-                uint64_t reserved_29_63:35;
-#endif
         } s;
         struct cvmx_ipd_pkt_ptr_valid_s cn30xx;
         struct cvmx_ipd_pkt_ptr_valid_s cn31xx;
@@ -1200,25 +510,16 @@ union cvmx_ipd_pkt_ptr_valid {
         struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
         struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
         struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
-        struct cvmx_ipd_pkt_ptr_valid_s cn61xx;
         struct cvmx_ipd_pkt_ptr_valid_s cn63xx;
         struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1;
-        struct cvmx_ipd_pkt_ptr_valid_s cn66xx;
-        struct cvmx_ipd_pkt_ptr_valid_s cnf71xx;
 };
 
 union cvmx_ipd_portx_bp_page_cnt {
         uint64_t u64;
         struct cvmx_ipd_portx_bp_page_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t bp_enb:1;
                 uint64_t page_cnt:17;
-#else
-                uint64_t page_cnt:17;
-                uint64_t bp_enb:1;
-                uint64_t reserved_18_63:46;
-#endif
         } s;
         struct cvmx_ipd_portx_bp_page_cnt_s cn30xx;
         struct cvmx_ipd_portx_bp_page_cnt_s cn31xx;
@@ -1231,123 +532,65 @@ union cvmx_ipd_portx_bp_page_cnt {
         struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
         struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
         struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
-        struct cvmx_ipd_portx_bp_page_cnt_s cn61xx;
         struct cvmx_ipd_portx_bp_page_cnt_s cn63xx;
         struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1;
-        struct cvmx_ipd_portx_bp_page_cnt_s cn66xx;
-        struct cvmx_ipd_portx_bp_page_cnt_s cnf71xx;
 };
 
 union cvmx_ipd_portx_bp_page_cnt2 {
         uint64_t u64;
         struct cvmx_ipd_portx_bp_page_cnt2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t bp_enb:1;
                 uint64_t page_cnt:17;
-#else
-                uint64_t page_cnt:17;
-                uint64_t bp_enb:1;
-                uint64_t reserved_18_63:46;
-#endif
         } s;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
-        struct cvmx_ipd_portx_bp_page_cnt2_s cn61xx;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1;
-        struct cvmx_ipd_portx_bp_page_cnt2_s cn66xx;
-        struct cvmx_ipd_portx_bp_page_cnt2_s cnf71xx;
 };
 
 union cvmx_ipd_portx_bp_page_cnt3 {
         uint64_t u64;
         struct cvmx_ipd_portx_bp_page_cnt3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t bp_enb:1;
                 uint64_t page_cnt:17;
-#else
-                uint64_t page_cnt:17;
-                uint64_t bp_enb:1;
-                uint64_t reserved_18_63:46;
-#endif
         } s;
-        struct cvmx_ipd_portx_bp_page_cnt3_s cn61xx;
         struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx;
         struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1;
-        struct cvmx_ipd_portx_bp_page_cnt3_s cn66xx;
-        struct cvmx_ipd_portx_bp_page_cnt3_s cnf71xx;
 };
 
 union cvmx_ipd_port_bp_counters2_pairx {
         uint64_t u64;
         struct cvmx_ipd_port_bp_counters2_pairx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_25_63:39;
                 uint64_t cnt_val:25;
-#else
-                uint64_t cnt_val:25;
-                uint64_t reserved_25_63:39;
-#endif
         } s;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
-        struct cvmx_ipd_port_bp_counters2_pairx_s cn61xx;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;
-        struct cvmx_ipd_port_bp_counters2_pairx_s cn66xx;
-        struct cvmx_ipd_port_bp_counters2_pairx_s cnf71xx;
 };
 
 union cvmx_ipd_port_bp_counters3_pairx {
         uint64_t u64;
         struct cvmx_ipd_port_bp_counters3_pairx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_25_63:39;
                 uint64_t cnt_val:25;
-#else
-                uint64_t cnt_val:25;
-                uint64_t reserved_25_63:39;
-#endif
         } s;
-        struct cvmx_ipd_port_bp_counters3_pairx_s cn61xx;
         struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;
         struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;
-        struct cvmx_ipd_port_bp_counters3_pairx_s cn66xx;
-        struct cvmx_ipd_port_bp_counters3_pairx_s cnf71xx;
-};
-
-union cvmx_ipd_port_bp_counters4_pairx {
-        uint64_t u64;
-        struct cvmx_ipd_port_bp_counters4_pairx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t cnt_val:25;
-#else
-                uint64_t cnt_val:25;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_ipd_port_bp_counters4_pairx_s cn61xx;
-        struct cvmx_ipd_port_bp_counters4_pairx_s cn66xx;
-        struct cvmx_ipd_port_bp_counters4_pairx_s cnf71xx;
 };
 
 union cvmx_ipd_port_bp_counters_pairx {
         uint64_t u64;
         struct cvmx_ipd_port_bp_counters_pairx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_25_63:39;
                 uint64_t cnt_val:25;
-#else
-                uint64_t cnt_val:25;
-                uint64_t reserved_25_63:39;
-#endif
         } s;
         struct cvmx_ipd_port_bp_counters_pairx_s cn30xx;
         struct cvmx_ipd_port_bp_counters_pairx_s cn31xx;
@@ -1360,133 +603,59 @@ union cvmx_ipd_port_bp_counters_pairx {
         struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
         struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
         struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
-        struct cvmx_ipd_port_bp_counters_pairx_s cn61xx;
         struct cvmx_ipd_port_bp_counters_pairx_s cn63xx;
         struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;
-        struct cvmx_ipd_port_bp_counters_pairx_s cn66xx;
-        struct cvmx_ipd_port_bp_counters_pairx_s cnf71xx;
-};
-
-union cvmx_ipd_port_ptr_fifo_ctl {
-        uint64_t u64;
-        struct cvmx_ipd_port_ptr_fifo_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t ptr:33;
-                uint64_t max_pkt:7;
-                uint64_t cena:1;
-                uint64_t raddr:7;
-#else
-                uint64_t raddr:7;
-                uint64_t cena:1;
-                uint64_t max_pkt:7;
-                uint64_t ptr:33;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xx;
-        struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xxp1;
 };
 
 union cvmx_ipd_port_qos_x_cnt {
         uint64_t u64;
         struct cvmx_ipd_port_qos_x_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t wmark:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t wmark:32;
-#endif
         } s;
         struct cvmx_ipd_port_qos_x_cnt_s cn52xx;
         struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
         struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
         struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
-        struct cvmx_ipd_port_qos_x_cnt_s cn61xx;
         struct cvmx_ipd_port_qos_x_cnt_s cn63xx;
         struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1;
-        struct cvmx_ipd_port_qos_x_cnt_s cn66xx;
-        struct cvmx_ipd_port_qos_x_cnt_s cn68xx;
-        struct cvmx_ipd_port_qos_x_cnt_s cn68xxp1;
-        struct cvmx_ipd_port_qos_x_cnt_s cnf71xx;
 };
 
 union cvmx_ipd_port_qos_intx {
         uint64_t u64;
         struct cvmx_ipd_port_qos_intx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t intr:64;
-#else
                 uint64_t intr:64;
-#endif
         } s;
         struct cvmx_ipd_port_qos_intx_s cn52xx;
         struct cvmx_ipd_port_qos_intx_s cn52xxp1;
         struct cvmx_ipd_port_qos_intx_s cn56xx;
         struct cvmx_ipd_port_qos_intx_s cn56xxp1;
-        struct cvmx_ipd_port_qos_intx_s cn61xx;
         struct cvmx_ipd_port_qos_intx_s cn63xx;
         struct cvmx_ipd_port_qos_intx_s cn63xxp1;
-        struct cvmx_ipd_port_qos_intx_s cn66xx;
-        struct cvmx_ipd_port_qos_intx_s cn68xx;
-        struct cvmx_ipd_port_qos_intx_s cn68xxp1;
-        struct cvmx_ipd_port_qos_intx_s cnf71xx;
 };
 
 union cvmx_ipd_port_qos_int_enbx {
         uint64_t u64;
         struct cvmx_ipd_port_qos_int_enbx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t enb:64;
-#else
                 uint64_t enb:64;
-#endif
         } s;
         struct cvmx_ipd_port_qos_int_enbx_s cn52xx;
         struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
         struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
         struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
-        struct cvmx_ipd_port_qos_int_enbx_s cn61xx;
         struct cvmx_ipd_port_qos_int_enbx_s cn63xx;
         struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1;
-        struct cvmx_ipd_port_qos_int_enbx_s cn66xx;
-        struct cvmx_ipd_port_qos_int_enbx_s cn68xx;
-        struct cvmx_ipd_port_qos_int_enbx_s cn68xxp1;
-        struct cvmx_ipd_port_qos_int_enbx_s cnf71xx;
-};
-
-union cvmx_ipd_port_sopx {
-        uint64_t u64;
-        struct cvmx_ipd_port_sopx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t sop:64;
-#else
-                uint64_t sop:64;
-#endif
-        } s;
-        struct cvmx_ipd_port_sopx_s cn68xx;
-        struct cvmx_ipd_port_sopx_s cn68xxp1;
 };
 
 union cvmx_ipd_prc_hold_ptr_fifo_ctl {
         uint64_t u64;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_39_63:25;
                 uint64_t max_pkt:3;
                 uint64_t praddr:3;
                 uint64_t ptr:29;
                 uint64_t cena:1;
                 uint64_t raddr:3;
-#else
-                uint64_t raddr:3;
-                uint64_t cena:1;
-                uint64_t ptr:29;
-                uint64_t praddr:3;
-                uint64_t max_pkt:3;
-                uint64_t reserved_39_63:25;
-#endif
         } s;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;
@@ -1498,29 +667,18 @@ union cvmx_ipd_prc_hold_ptr_fifo_ctl {
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
-        struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn61xx;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;
-        struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn66xx;
-        struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cnf71xx;
 };
 
 union cvmx_ipd_prc_port_ptr_fifo_ctl {
         uint64_t u64;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t max_pkt:7;
                 uint64_t ptr:29;
                 uint64_t cena:1;
                 uint64_t raddr:7;
-#else
-                uint64_t raddr:7;
-                uint64_t cena:1;
-                uint64_t ptr:29;
-                uint64_t max_pkt:7;
-                uint64_t reserved_44_63:20;
-#endif
         } s;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;
@@ -1532,31 +690,19 @@ union cvmx_ipd_prc_port_ptr_fifo_ctl {
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
-        struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn61xx;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;
-        struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn66xx;
-        struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cnf71xx;
 };
 
 union cvmx_ipd_ptr_count {
         uint64_t u64;
         struct cvmx_ipd_ptr_count_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t pktv_cnt:1;
                 uint64_t wqev_cnt:1;
                 uint64_t pfif_cnt:3;
                 uint64_t pkt_pcnt:7;
                 uint64_t wqe_pcnt:7;
-#else
-                uint64_t wqe_pcnt:7;
-                uint64_t pkt_pcnt:7;
-                uint64_t pfif_cnt:3;
-                uint64_t wqev_cnt:1;
-                uint64_t pktv_cnt:1;
-                uint64_t reserved_19_63:45;
-#endif
         } s;
         struct cvmx_ipd_ptr_count_s cn30xx;
         struct cvmx_ipd_ptr_count_s cn31xx;
@@ -1569,19 +715,13 @@ union cvmx_ipd_ptr_count {
         struct cvmx_ipd_ptr_count_s cn56xxp1;
         struct cvmx_ipd_ptr_count_s cn58xx;
         struct cvmx_ipd_ptr_count_s cn58xxp1;
-        struct cvmx_ipd_ptr_count_s cn61xx;
         struct cvmx_ipd_ptr_count_s cn63xx;
         struct cvmx_ipd_ptr_count_s cn63xxp1;
-        struct cvmx_ipd_ptr_count_s cn66xx;
-        struct cvmx_ipd_ptr_count_s cn68xx;
-        struct cvmx_ipd_ptr_count_s cn68xxp1;
-        struct cvmx_ipd_ptr_count_s cnf71xx;
 };
 
 union cvmx_ipd_pwp_ptr_fifo_ctl {
         uint64_t u64;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_61_63:3;
                 uint64_t max_cnts:7;
                 uint64_t wraddr:8;
@@ -1589,15 +729,6 @@ union cvmx_ipd_pwp_ptr_fifo_ctl {
                 uint64_t ptr:29;
                 uint64_t cena:1;
                 uint64_t raddr:8;
-#else
-                uint64_t raddr:8;
-                uint64_t cena:1;
-                uint64_t ptr:29;
-                uint64_t praddr:8;
-                uint64_t wraddr:8;
-                uint64_t max_cnts:7;
-                uint64_t reserved_61_63:3;
-#endif
         } s;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx;
@@ -1609,23 +740,15 @@ union cvmx_ipd_pwp_ptr_fifo_ctl {
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
-        struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn61xx;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1;
-        struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn66xx;
-        struct cvmx_ipd_pwp_ptr_fifo_ctl_s cnf71xx;
 };
 
 union cvmx_ipd_qosx_red_marks {
         uint64_t u64;
         struct cvmx_ipd_qosx_red_marks_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t drop:32;
                 uint64_t pass:32;
-#else
-                uint64_t pass:32;
-                uint64_t drop:32;
-#endif
         } s;
         struct cvmx_ipd_qosx_red_marks_s cn30xx;
         struct cvmx_ipd_qosx_red_marks_s cn31xx;
@@ -1638,25 +761,15 @@ union cvmx_ipd_qosx_red_marks {
         struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
         struct cvmx_ipd_qosx_red_marks_s cn58xx;
         struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
-        struct cvmx_ipd_qosx_red_marks_s cn61xx;
         struct cvmx_ipd_qosx_red_marks_s cn63xx;
         struct cvmx_ipd_qosx_red_marks_s cn63xxp1;
-        struct cvmx_ipd_qosx_red_marks_s cn66xx;
-        struct cvmx_ipd_qosx_red_marks_s cn68xx;
-        struct cvmx_ipd_qosx_red_marks_s cn68xxp1;
-        struct cvmx_ipd_qosx_red_marks_s cnf71xx;
 };
 
 union cvmx_ipd_que0_free_page_cnt {
         uint64_t u64;
         struct cvmx_ipd_que0_free_page_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t q0_pcnt:32;
-#else
-                uint64_t q0_pcnt:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_ipd_que0_free_page_cnt_s cn30xx;
         struct cvmx_ipd_que0_free_page_cnt_s cn31xx;
@@ -1669,57 +782,16 @@ union cvmx_ipd_que0_free_page_cnt {
         struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
         struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
         struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
-        struct cvmx_ipd_que0_free_page_cnt_s cn61xx;
         struct cvmx_ipd_que0_free_page_cnt_s cn63xx;
         struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1;
-        struct cvmx_ipd_que0_free_page_cnt_s cn66xx;
-        struct cvmx_ipd_que0_free_page_cnt_s cn68xx;
-        struct cvmx_ipd_que0_free_page_cnt_s cn68xxp1;
-        struct cvmx_ipd_que0_free_page_cnt_s cnf71xx;
-};
-
-union cvmx_ipd_red_bpid_enablex {
-        uint64_t u64;
-        struct cvmx_ipd_red_bpid_enablex_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t prt_enb:64;
-#else
-                uint64_t prt_enb:64;
-#endif
-        } s;
-        struct cvmx_ipd_red_bpid_enablex_s cn68xx;
-        struct cvmx_ipd_red_bpid_enablex_s cn68xxp1;
-};
-
-union cvmx_ipd_red_delay {
-        uint64_t u64;
-        struct cvmx_ipd_red_delay_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t prb_dly:14;
-                uint64_t avg_dly:14;
-#else
-                uint64_t avg_dly:14;
-                uint64_t prb_dly:14;
-                uint64_t reserved_28_63:36;
-#endif
-        } s;
-        struct cvmx_ipd_red_delay_s cn68xx;
-        struct cvmx_ipd_red_delay_s cn68xxp1;
 };
 
 union cvmx_ipd_red_port_enable {
         uint64_t u64;
         struct cvmx_ipd_red_port_enable_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t prb_dly:14;
                 uint64_t avg_dly:14;
                 uint64_t prt_enb:36;
-#else
-                uint64_t prt_enb:36;
-                uint64_t avg_dly:14;
-                uint64_t prb_dly:14;
-#endif
         } s;
         struct cvmx_ipd_red_port_enable_s cn30xx;
         struct cvmx_ipd_red_port_enable_s cn31xx;
@@ -1732,67 +804,35 @@ union cvmx_ipd_red_port_enable {
         struct cvmx_ipd_red_port_enable_s cn56xxp1;
         struct cvmx_ipd_red_port_enable_s cn58xx;
         struct cvmx_ipd_red_port_enable_s cn58xxp1;
-        struct cvmx_ipd_red_port_enable_s cn61xx;
         struct cvmx_ipd_red_port_enable_s cn63xx;
         struct cvmx_ipd_red_port_enable_s cn63xxp1;
-        struct cvmx_ipd_red_port_enable_s cn66xx;
-        struct cvmx_ipd_red_port_enable_s cnf71xx;
 };
 
 union cvmx_ipd_red_port_enable2 {
         uint64_t u64;
         struct cvmx_ipd_red_port_enable2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t prt_enb:12;
-#else
-                uint64_t prt_enb:12;
-                uint64_t reserved_12_63:52;
-#endif
+                uint64_t reserved_8_63:56;
+                uint64_t prt_enb:8;
         } s;
         struct cvmx_ipd_red_port_enable2_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t prt_enb:4;
-#else
-                uint64_t prt_enb:4;
-                uint64_t reserved_4_63:60;
-#endif
         } cn52xx;
         struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;
         struct cvmx_ipd_red_port_enable2_cn52xx cn56xx;
         struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;
-        struct cvmx_ipd_red_port_enable2_s cn61xx;
-        struct cvmx_ipd_red_port_enable2_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t prt_enb:8;
-#else
-                uint64_t prt_enb:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } cn63xx;
-        struct cvmx_ipd_red_port_enable2_cn63xx cn63xxp1;
-        struct cvmx_ipd_red_port_enable2_s cn66xx;
-        struct cvmx_ipd_red_port_enable2_s cnf71xx;
+        struct cvmx_ipd_red_port_enable2_s cn63xx;
+        struct cvmx_ipd_red_port_enable2_s cn63xxp1;
 };
 
 union cvmx_ipd_red_quex_param {
         uint64_t u64;
         struct cvmx_ipd_red_quex_param_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_49_63:15;
                 uint64_t use_pcnt:1;
                 uint64_t new_con:8;
                 uint64_t avg_con:8;
                 uint64_t prb_con:32;
-#else
-                uint64_t prb_con:32;
-                uint64_t avg_con:8;
-                uint64_t new_con:8;
-                uint64_t use_pcnt:1;
-                uint64_t reserved_49_63:15;
-#endif
         } s;
         struct cvmx_ipd_red_quex_param_s cn30xx;
         struct cvmx_ipd_red_quex_param_s cn31xx;
@@ -1805,53 +845,16 @@ union cvmx_ipd_red_quex_param {
         struct cvmx_ipd_red_quex_param_s cn56xxp1;
         struct cvmx_ipd_red_quex_param_s cn58xx;
         struct cvmx_ipd_red_quex_param_s cn58xxp1;
-        struct cvmx_ipd_red_quex_param_s cn61xx;
         struct cvmx_ipd_red_quex_param_s cn63xx;
         struct cvmx_ipd_red_quex_param_s cn63xxp1;
-        struct cvmx_ipd_red_quex_param_s cn66xx;
-        struct cvmx_ipd_red_quex_param_s cn68xx;
-        struct cvmx_ipd_red_quex_param_s cn68xxp1;
-        struct cvmx_ipd_red_quex_param_s cnf71xx;
-};
-
-union cvmx_ipd_req_wgt {
-        uint64_t u64;
-        struct cvmx_ipd_req_wgt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t wgt7:8;
-                uint64_t wgt6:8;
-                uint64_t wgt5:8;
-                uint64_t wgt4:8;
-                uint64_t wgt3:8;
-                uint64_t wgt2:8;
-                uint64_t wgt1:8;
-                uint64_t wgt0:8;
-#else
-                uint64_t wgt0:8;
-                uint64_t wgt1:8;
-                uint64_t wgt2:8;
-                uint64_t wgt3:8;
-                uint64_t wgt4:8;
-                uint64_t wgt5:8;
-                uint64_t wgt6:8;
-                uint64_t wgt7:8;
-#endif
-        } s;
-        struct cvmx_ipd_req_wgt_s cn68xx;
 };
 
 union cvmx_ipd_sub_port_bp_page_cnt {
         uint64_t u64;
         struct cvmx_ipd_sub_port_bp_page_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_31_63:33;
                 uint64_t port:6;
                 uint64_t page_cnt:25;
-#else
-                uint64_t page_cnt:25;
-                uint64_t port:6;
-                uint64_t reserved_31_63:33;
-#endif
         } s;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;
@@ -1864,48 +867,26 @@ union cvmx_ipd_sub_port_bp_page_cnt {
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
-        struct cvmx_ipd_sub_port_bp_page_cnt_s cn61xx;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;
-        struct cvmx_ipd_sub_port_bp_page_cnt_s cn66xx;
-        struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xx;
-        struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xxp1;
-        struct cvmx_ipd_sub_port_bp_page_cnt_s cnf71xx;
 };
 
 union cvmx_ipd_sub_port_fcs {
         uint64_t u64;
         struct cvmx_ipd_sub_port_fcs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t port_bit2:4;
                 uint64_t reserved_32_35:4;
                 uint64_t port_bit:32;
-#else
-                uint64_t port_bit:32;
-                uint64_t reserved_32_35:4;
-                uint64_t port_bit2:4;
-                uint64_t reserved_40_63:24;
-#endif
         } s;
         struct cvmx_ipd_sub_port_fcs_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t port_bit:3;
-#else
-                uint64_t port_bit:3;
-                uint64_t reserved_3_63:61;
-#endif
         } cn30xx;
         struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx;
         struct cvmx_ipd_sub_port_fcs_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t port_bit:32;
-#else
-                uint64_t port_bit:32;
-                uint64_t reserved_32_63:32;
-#endif
         } cn38xx;
         struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2;
         struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx;
@@ -1915,49 +896,30 @@ union cvmx_ipd_sub_port_fcs {
         struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
         struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
         struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
-        struct cvmx_ipd_sub_port_fcs_s cn61xx;
         struct cvmx_ipd_sub_port_fcs_s cn63xx;
         struct cvmx_ipd_sub_port_fcs_s cn63xxp1;
-        struct cvmx_ipd_sub_port_fcs_s cn66xx;
-        struct cvmx_ipd_sub_port_fcs_s cnf71xx;
 };
 
 union cvmx_ipd_sub_port_qos_cnt {
         uint64_t u64;
         struct cvmx_ipd_sub_port_qos_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_41_63:23;
                 uint64_t port_qos:9;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t port_qos:9;
-                uint64_t reserved_41_63:23;
-#endif
         } s;
         struct cvmx_ipd_sub_port_qos_cnt_s cn52xx;
         struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
         struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
         struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
-        struct cvmx_ipd_sub_port_qos_cnt_s cn61xx;
         struct cvmx_ipd_sub_port_qos_cnt_s cn63xx;
         struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1;
-        struct cvmx_ipd_sub_port_qos_cnt_s cn66xx;
-        struct cvmx_ipd_sub_port_qos_cnt_s cn68xx;
-        struct cvmx_ipd_sub_port_qos_cnt_s cn68xxp1;
-        struct cvmx_ipd_sub_port_qos_cnt_s cnf71xx;
 };
 
 union cvmx_ipd_wqe_fpa_queue {
         uint64_t u64;
         struct cvmx_ipd_wqe_fpa_queue_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t wqe_pool:3;
-#else
-                uint64_t wqe_pool:3;
-                uint64_t reserved_3_63:61;
-#endif
         } s;
         struct cvmx_ipd_wqe_fpa_queue_s cn30xx;
         struct cvmx_ipd_wqe_fpa_queue_s cn31xx;
@@ -1970,25 +932,15 @@ union cvmx_ipd_wqe_fpa_queue {
         struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
         struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
         struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
-        struct cvmx_ipd_wqe_fpa_queue_s cn61xx;
         struct cvmx_ipd_wqe_fpa_queue_s cn63xx;
         struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1;
-        struct cvmx_ipd_wqe_fpa_queue_s cn66xx;
-        struct cvmx_ipd_wqe_fpa_queue_s cn68xx;
-        struct cvmx_ipd_wqe_fpa_queue_s cn68xxp1;
-        struct cvmx_ipd_wqe_fpa_queue_s cnf71xx;
 };
 
 union cvmx_ipd_wqe_ptr_valid {
         uint64_t u64;
         struct cvmx_ipd_wqe_ptr_valid_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t ptr:29;
-#else
-                uint64_t ptr:29;
-                uint64_t reserved_29_63:35;
-#endif
         } s;
         struct cvmx_ipd_wqe_ptr_valid_s cn30xx;
         struct cvmx_ipd_wqe_ptr_valid_s cn31xx;
@@ -2000,11 +952,8 @@ union cvmx_ipd_wqe_ptr_valid {
         struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
         struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
         struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
-        struct cvmx_ipd_wqe_ptr_valid_s cn61xx;
         struct cvmx_ipd_wqe_ptr_valid_s cn63xx;
         struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1;
-        struct cvmx_ipd_wqe_ptr_valid_s cn66xx;
-        struct cvmx_ipd_wqe_ptr_valid_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h
deleted file mode 100644
index 115a552c5c7..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-ipd.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- *
- * Interface to the hardware Input Packet Data unit.
- */
-
-#ifndef __CVMX_IPD_H__
-#define __CVMX_IPD_H__
-
-#include <asm/octeon/octeon-feature.h>
-
-#include <asm/octeon/cvmx-ipd-defs.h>
-
-enum cvmx_ipd_mode {
-   CVMX_IPD_OPC_MODE_STT = 0LL,   /* All blocks DRAM, not cached in L2 */
-   CVMX_IPD_OPC_MODE_STF = 1LL,   /* All bloccks into  L2 */
-   CVMX_IPD_OPC_MODE_STF1_STT = 2LL,   /* 1st block L2, rest DRAM */
-   CVMX_IPD_OPC_MODE_STF2_STT = 3LL    /* 1st, 2nd blocks L2, rest DRAM */
-};
-
-#ifndef CVMX_ENABLE_LEN_M8_FIX
-#define CVMX_ENABLE_LEN_M8_FIX 0
-#endif
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t;
-typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t;
-
-typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
-typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
-
-/**
- * Configure IPD
- *
- * @mbuff_size: Packets buffer size in 8 byte words
- * @first_mbuff_skip:
- *                   Number of 8 byte words to skip in the first buffer
- * @not_first_mbuff_skip:
- *                   Number of 8 byte words to skip in each following buffer
- * @first_back: Must be same as first_mbuff_skip / 128
- * @second_back:
- *                   Must be same as not_first_mbuff_skip / 128
- * @wqe_fpa_pool:
- *                   FPA pool to get work entries from
- * @cache_mode:
- * @back_pres_enable_flag:
- *                   Enable or disable port back pressure
- */
-static inline void cvmx_ipd_config(uint64_t mbuff_size,
-                                   uint64_t first_mbuff_skip,
-                                   uint64_t not_first_mbuff_skip,
-                                   uint64_t first_back,
-                                   uint64_t second_back,
-                                   uint64_t wqe_fpa_pool,
-                                   enum cvmx_ipd_mode cache_mode,
-                                   uint64_t back_pres_enable_flag)
-{
-        cvmx_ipd_mbuff_first_skip_t first_skip;
-        cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
-        union cvmx_ipd_packet_mbuff_size size;
-        cvmx_ipd_first_next_ptr_back_t first_back_struct;
-        cvmx_ipd_second_next_ptr_back_t second_back_struct;
-        union cvmx_ipd_wqe_fpa_queue wqe_pool;
-        union cvmx_ipd_ctl_status ipd_ctl_reg;
-
-        first_skip.u64 = 0;
-        first_skip.s.skip_sz = first_mbuff_skip;
-        cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
-
-        not_first_skip.u64 = 0;
-        not_first_skip.s.skip_sz = not_first_mbuff_skip;
-        cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
-
-        size.u64 = 0;
-        size.s.mb_size = mbuff_size;
-        cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
-
-        first_back_struct.u64 = 0;
-        first_back_struct.s.back = first_back;
-        cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
-
-        second_back_struct.u64 = 0;
-        second_back_struct.s.back = second_back;
-        cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64);
-
-        wqe_pool.u64 = 0;
-        wqe_pool.s.wqe_pool = wqe_fpa_pool;
-        cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
-
-        ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
-        ipd_ctl_reg.s.opc_mode = cache_mode;
-        ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
-        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
-
-        /* Note: the example RED code that used to be here has been moved to
-           cvmx_helper_setup_red */
-}
-
-/**
- * Enable IPD
- */
-static inline void cvmx_ipd_enable(void)
-{
-        union cvmx_ipd_ctl_status ipd_reg;
-        ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
-        if (ipd_reg.s.ipd_en) {
-                cvmx_dprintf
-                    ("Warning: Enabling IPD when IPD already enabled.\n");
-        }
-        ipd_reg.s.ipd_en = 1;
-#if  CVMX_ENABLE_LEN_M8_FIX
-        if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
-                ipd_reg.s.len_m8 = TRUE;
-#endif
-        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
-}
-
-/**
- * Disable IPD
- */
-static inline void cvmx_ipd_disable(void)
-{
-        union cvmx_ipd_ctl_status ipd_reg;
-        ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
-        ipd_reg.s.ipd_en = 0;
-        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
-}
-
-/**
- * Supportive function for cvmx_fpa_shutdown_pool.
- */
-static inline void cvmx_ipd_free_ptr(void)
-{
-        /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
-        if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)
-            && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
-                int no_wptr = 0;
-                union cvmx_ipd_ptr_count ipd_ptr_count;
-                ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
-
-                /* Handle Work Queue Entry in cn56xx and cn52xx */
-                if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
-                        union cvmx_ipd_ctl_status ipd_ctl_status;
-                        ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
-                        if (ipd_ctl_status.s.no_wptr)
-                                no_wptr = 1;
-                }
-
-                /* Free the prefetched WQE */
-                if (ipd_ptr_count.s.wqev_cnt) {
-                        union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid;
-                        ipd_wqe_ptr_valid.u64 =
-                            cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
-                        if (no_wptr)
-                                cvmx_fpa_free(cvmx_phys_to_ptr
-                                              ((uint64_t) ipd_wqe_ptr_valid.s.
-                                               ptr << 7), CVMX_FPA_PACKET_POOL,
-                                              0);
-                        else
-                                cvmx_fpa_free(cvmx_phys_to_ptr
-                                              ((uint64_t) ipd_wqe_ptr_valid.s.
-                                               ptr << 7), CVMX_FPA_WQE_POOL, 0);
-                }
-
-                /* Free all WQE in the fifo */
-                if (ipd_ptr_count.s.wqe_pcnt) {
-                        int i;
-                        union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
-                        ipd_pwp_ptr_fifo_ctl.u64 =
-                            cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
-                        for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
-                                ipd_pwp_ptr_fifo_ctl.s.cena = 0;
-                                ipd_pwp_ptr_fifo_ctl.s.raddr =
-                                    ipd_pwp_ptr_fifo_ctl.s.max_cnts +
-                                    (ipd_pwp_ptr_fifo_ctl.s.wraddr +
-                                     i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
-                                cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
-                                               ipd_pwp_ptr_fifo_ctl.u64);
-                                ipd_pwp_ptr_fifo_ctl.u64 =
-                                    cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
-                                if (no_wptr)
-                                        cvmx_fpa_free(cvmx_phys_to_ptr
-                                                      ((uint64_t)
-                                                       ipd_pwp_ptr_fifo_ctl.s.
-                                                       ptr << 7),
-                                                      CVMX_FPA_PACKET_POOL, 0);
-                                else
-                                        cvmx_fpa_free(cvmx_phys_to_ptr
-                                                      ((uint64_t)
-                                                       ipd_pwp_ptr_fifo_ctl.s.
-                                                       ptr << 7),
-                                                      CVMX_FPA_WQE_POOL, 0);
-                        }
-                        ipd_pwp_ptr_fifo_ctl.s.cena = 1;
-                        cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
-                                       ipd_pwp_ptr_fifo_ctl.u64);
-                }
-
-                /* Free the prefetched packet */
-                if (ipd_ptr_count.s.pktv_cnt) {
-                        union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid;
-                        ipd_pkt_ptr_valid.u64 =
-                            cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
-                        cvmx_fpa_free(cvmx_phys_to_ptr
-                                      (ipd_pkt_ptr_valid.s.ptr << 7),
-                                      CVMX_FPA_PACKET_POOL, 0);
-                }
-
-                /* Free the per port prefetched packets */
-                if (1) {
-                        int i;
-                        union cvmx_ipd_prc_port_ptr_fifo_ctl
-                            ipd_prc_port_ptr_fifo_ctl;
-                        ipd_prc_port_ptr_fifo_ctl.u64 =
-                            cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
-
-                        for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
-                             i++) {
-                                ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
-                                ipd_prc_port_ptr_fifo_ctl.s.raddr =
-                                    i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
-                                cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
-                                               ipd_prc_port_ptr_fifo_ctl.u64);
-                                ipd_prc_port_ptr_fifo_ctl.u64 =
-                                    cvmx_read_csr
-                                    (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
-                                cvmx_fpa_free(cvmx_phys_to_ptr
-                                              ((uint64_t)
-                                               ipd_prc_port_ptr_fifo_ctl.s.
-                                               ptr << 7), CVMX_FPA_PACKET_POOL,
-                                              0);
-                        }
-                        ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
-                        cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
-                                       ipd_prc_port_ptr_fifo_ctl.u64);
-                }
-
-                /* Free all packets in the holding fifo */
-                if (ipd_ptr_count.s.pfif_cnt) {
-                        int i;
-                        union cvmx_ipd_prc_hold_ptr_fifo_ctl
-                            ipd_prc_hold_ptr_fifo_ctl;
-
-                        ipd_prc_hold_ptr_fifo_ctl.u64 =
-                            cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
-
-                        for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
-                                ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
-                                ipd_prc_hold_ptr_fifo_ctl.s.raddr =
-                                    (ipd_prc_hold_ptr_fifo_ctl.s.praddr +
-                                     i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
-                                cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
-                                               ipd_prc_hold_ptr_fifo_ctl.u64);
-                                ipd_prc_hold_ptr_fifo_ctl.u64 =
-                                    cvmx_read_csr
-                                    (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
-                                cvmx_fpa_free(cvmx_phys_to_ptr
-                                              ((uint64_t)
-                                               ipd_prc_hold_ptr_fifo_ctl.s.
-                                               ptr << 7), CVMX_FPA_PACKET_POOL,
-                                              0);
-                        }
-                        ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
-                        cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
-                                       ipd_prc_hold_ptr_fifo_ctl.u64);
-                }
-
-                /* Free all packets in the fifo */
-                if (ipd_ptr_count.s.pkt_pcnt) {
-                        int i;
-                        union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
-                        ipd_pwp_ptr_fifo_ctl.u64 =
-                            cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
-
-                        for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
-                                ipd_pwp_ptr_fifo_ctl.s.cena = 0;
-                                ipd_pwp_ptr_fifo_ctl.s.raddr =
-                                    (ipd_pwp_ptr_fifo_ctl.s.praddr +
-                                     i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
-                                cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
-                                               ipd_pwp_ptr_fifo_ctl.u64);
-                                ipd_pwp_ptr_fifo_ctl.u64 =
-                                    cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
-                                cvmx_fpa_free(cvmx_phys_to_ptr
-                                              ((uint64_t) ipd_pwp_ptr_fifo_ctl.
-                                               s.ptr << 7),
-                                              CVMX_FPA_PACKET_POOL, 0);
-                        }
-                        ipd_pwp_ptr_fifo_ctl.s.cena = 1;
-                        cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
-                                       ipd_pwp_ptr_fifo_ctl.u64);
-                }
-
-                /* Reset the IPD to get all buffers out of it */
-                {
-                        union cvmx_ipd_ctl_status ipd_ctl_status;
-                        ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
-                        ipd_ctl_status.s.reset = 1;
-                        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
-                }
-
-                /* Reset the PIP */
-                {
-                        union cvmx_pip_sft_rst pip_sft_rst;
-                        pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
-                        pip_sft_rst.s.rst = 1;
-                        cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
-                }
-        }
-}
-
-#endif /*  __CVMX_IPD_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
index 10262cb6ff5..7a50a0beb47 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -33,18 +33,18 @@
 #define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
 #define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
 #define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull))
-#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull))
+#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull))
+#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull))
 #define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
 #define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8)
 #define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
 #define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
 #define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull))
-#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8)
-#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8)
+#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull))
+#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull))
+#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull))
 #define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull))
 #define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull))
 #define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull))
@@ -71,119 +71,54 @@
 #define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
 #define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8)
 #define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
-#define CVMX_L2C_QOS_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8)
-#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8)
+#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull))
+#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8)
 #define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
-#define CVMX_L2C_RSCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64)
-#define CVMX_L2C_RSDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64)
+#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull))
+#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull))
 #define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
 #define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
 #define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
 #define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
 #define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
-#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull)
-#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull)
+#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull))
+#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull))
+#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull))
+#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull))
+#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull))
+#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull))
+#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull))
+#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull))
+#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull))
+#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull))
 #define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull))
 #define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull))
 #define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull))
 #define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull))
-#define CVMX_L2C_VIRTID_IOBX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8)
-#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8)
+#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull))
+#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8)
 #define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull))
 #define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8)
-#define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8)
-#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8)
-#define CVMX_L2C_XMCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64)
+#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull))
+#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull))
 #define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
-#define CVMX_L2C_XMDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64)
+#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull))
 
 union cvmx_l2c_big_ctl {
         uint64_t u64;
         struct cvmx_l2c_big_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t maxdram:4;
                 uint64_t reserved_1_3:3;
                 uint64_t disable:1;
-#else
-                uint64_t disable:1;
-                uint64_t reserved_1_3:3;
-                uint64_t maxdram:4;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
-        struct cvmx_l2c_big_ctl_s cn61xx;
         struct cvmx_l2c_big_ctl_s cn63xx;
-        struct cvmx_l2c_big_ctl_s cn66xx;
-        struct cvmx_l2c_big_ctl_s cn68xx;
-        struct cvmx_l2c_big_ctl_s cn68xxp1;
-        struct cvmx_l2c_big_ctl_s cnf71xx;
 };
 
 union cvmx_l2c_bst {
         uint64_t u64;
         struct cvmx_l2c_bst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dutfl:32;
-                uint64_t rbffl:4;
-                uint64_t xbffl:4;
-                uint64_t tdpfl:4;
-                uint64_t ioccmdfl:4;
-                uint64_t iocdatfl:4;
-                uint64_t dutresfl:4;
-                uint64_t vrtfl:4;
-                uint64_t tdffl:4;
-#else
-                uint64_t tdffl:4;
-                uint64_t vrtfl:4;
-                uint64_t dutresfl:4;
-                uint64_t iocdatfl:4;
-                uint64_t ioccmdfl:4;
-                uint64_t tdpfl:4;
-                uint64_t xbffl:4;
-                uint64_t rbffl:4;
-                uint64_t dutfl:32;
-#endif
-        } s;
-        struct cvmx_l2c_bst_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_36_63:28;
-                uint64_t dutfl:4;
-                uint64_t reserved_17_31:15;
-                uint64_t ioccmdfl:1;
-                uint64_t reserved_13_15:3;
-                uint64_t iocdatfl:1;
-                uint64_t reserved_9_11:3;
-                uint64_t dutresfl:1;
-                uint64_t reserved_5_7:3;
-                uint64_t vrtfl:1;
-                uint64_t reserved_1_3:3;
-                uint64_t tdffl:1;
-#else
-                uint64_t tdffl:1;
-                uint64_t reserved_1_3:3;
-                uint64_t vrtfl:1;
-                uint64_t reserved_5_7:3;
-                uint64_t dutresfl:1;
-                uint64_t reserved_9_11:3;
-                uint64_t iocdatfl:1;
-                uint64_t reserved_13_15:3;
-                uint64_t ioccmdfl:1;
-                uint64_t reserved_17_31:15;
-                uint64_t dutfl:4;
-                uint64_t reserved_36_63:28;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_bst_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_38_63:26;
                 uint64_t dutfl:6;
                 uint64_t reserved_17_31:15;
@@ -196,60 +131,14 @@ union cvmx_l2c_bst {
                 uint64_t vrtfl:1;
                 uint64_t reserved_1_3:3;
                 uint64_t tdffl:1;
-#else
-                uint64_t tdffl:1;
-                uint64_t reserved_1_3:3;
-                uint64_t vrtfl:1;
-                uint64_t reserved_5_7:3;
-                uint64_t dutresfl:1;
-                uint64_t reserved_9_11:3;
-                uint64_t iocdatfl:1;
-                uint64_t reserved_13_15:3;
-                uint64_t ioccmdfl:1;
-                uint64_t reserved_17_31:15;
-                uint64_t dutfl:6;
-                uint64_t reserved_38_63:26;
-#endif
-        } cn63xx;
-        struct cvmx_l2c_bst_cn63xx cn63xxp1;
-        struct cvmx_l2c_bst_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_42_63:22;
-                uint64_t dutfl:10;
-                uint64_t reserved_17_31:15;
-                uint64_t ioccmdfl:1;
-                uint64_t reserved_13_15:3;
-                uint64_t iocdatfl:1;
-                uint64_t reserved_9_11:3;
-                uint64_t dutresfl:1;
-                uint64_t reserved_5_7:3;
-                uint64_t vrtfl:1;
-                uint64_t reserved_1_3:3;
-                uint64_t tdffl:1;
-#else
-                uint64_t tdffl:1;
-                uint64_t reserved_1_3:3;
-                uint64_t vrtfl:1;
-                uint64_t reserved_5_7:3;
-                uint64_t dutresfl:1;
-                uint64_t reserved_9_11:3;
-                uint64_t iocdatfl:1;
-                uint64_t reserved_13_15:3;
-                uint64_t ioccmdfl:1;
-                uint64_t reserved_17_31:15;
-                uint64_t dutfl:10;
-                uint64_t reserved_42_63:22;
-#endif
-        } cn66xx;
-        struct cvmx_l2c_bst_s cn68xx;
-        struct cvmx_l2c_bst_s cn68xxp1;
-        struct cvmx_l2c_bst_cn61xx cnf71xx;
+        } s;
+        struct cvmx_l2c_bst_s cn63xx;
+        struct cvmx_l2c_bst_s cn63xxp1;
 };
 
 union cvmx_l2c_bst0 {
         uint64_t u64;
         struct cvmx_l2c_bst0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t dtbnk:1;
                 uint64_t wlb_msk:4;
@@ -257,18 +146,8 @@ union cvmx_l2c_bst0 {
                 uint64_t dt:1;
                 uint64_t stin_msk:1;
                 uint64_t wlb_dat:4;
-#else
-                uint64_t wlb_dat:4;
-                uint64_t stin_msk:1;
-                uint64_t dt:1;
-                uint64_t dtcnt:13;
-                uint64_t wlb_msk:4;
-                uint64_t dtbnk:1;
-                uint64_t reserved_24_63:40;
-#endif
         } s;
         struct cvmx_l2c_bst0_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_23_63:41;
                 uint64_t wlb_msk:4;
                 uint64_t reserved_15_18:4;
@@ -276,18 +155,8 @@ union cvmx_l2c_bst0 {
                 uint64_t dt:1;
                 uint64_t reserved_4_4:1;
                 uint64_t wlb_dat:4;
-#else
-                uint64_t wlb_dat:4;
-                uint64_t reserved_4_4:1;
-                uint64_t dt:1;
-                uint64_t dtcnt:9;
-                uint64_t reserved_15_18:4;
-                uint64_t wlb_msk:4;
-                uint64_t reserved_23_63:41;
-#endif
         } cn30xx;
         struct cvmx_l2c_bst0_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_23_63:41;
                 uint64_t wlb_msk:4;
                 uint64_t reserved_16_18:3;
@@ -295,34 +164,16 @@ union cvmx_l2c_bst0 {
                 uint64_t dt:1;
                 uint64_t stin_msk:1;
                 uint64_t wlb_dat:4;
-#else
-                uint64_t wlb_dat:4;
-                uint64_t stin_msk:1;
-                uint64_t dt:1;
-                uint64_t dtcnt:10;
-                uint64_t reserved_16_18:3;
-                uint64_t wlb_msk:4;
-                uint64_t reserved_23_63:41;
-#endif
         } cn31xx;
         struct cvmx_l2c_bst0_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t dtcnt:13;
                 uint64_t dt:1;
                 uint64_t stin_msk:1;
                 uint64_t wlb_dat:4;
-#else
-                uint64_t wlb_dat:4;
-                uint64_t stin_msk:1;
-                uint64_t dt:1;
-                uint64_t dtcnt:13;
-                uint64_t reserved_19_63:45;
-#endif
         } cn38xx;
         struct cvmx_l2c_bst0_cn38xx cn38xxp2;
         struct cvmx_l2c_bst0_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t dtbnk:1;
                 uint64_t wlb_msk:4;
@@ -331,16 +182,6 @@ union cvmx_l2c_bst0 {
                 uint64_t dt:1;
                 uint64_t stin_msk:1;
                 uint64_t wlb_dat:4;
-#else
-                uint64_t wlb_dat:4;
-                uint64_t stin_msk:1;
-                uint64_t dt:1;
-                uint64_t dtcnt:10;
-                uint64_t reserved_16_18:3;
-                uint64_t wlb_msk:4;
-                uint64_t dtbnk:1;
-                uint64_t reserved_24_63:40;
-#endif
         } cn50xx;
         struct cvmx_l2c_bst0_cn50xx cn52xx;
         struct cvmx_l2c_bst0_cn50xx cn52xxp1;
@@ -353,51 +194,28 @@ union cvmx_l2c_bst0 {
 union cvmx_l2c_bst1 {
         uint64_t u64;
         struct cvmx_l2c_bst1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t l2t:9;
-#else
-                uint64_t l2t:9;
-                uint64_t reserved_9_63:55;
-#endif
         } s;
         struct cvmx_l2c_bst1_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t vwdf:4;
                 uint64_t lrf:2;
                 uint64_t vab_vwcf:1;
                 uint64_t reserved_5_8:4;
                 uint64_t l2t:5;
-#else
-                uint64_t l2t:5;
-                uint64_t reserved_5_8:4;
-                uint64_t vab_vwcf:1;
-                uint64_t lrf:2;
-                uint64_t vwdf:4;
-                uint64_t reserved_16_63:48;
-#endif
         } cn30xx;
         struct cvmx_l2c_bst1_cn30xx cn31xx;
         struct cvmx_l2c_bst1_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t vwdf:4;
                 uint64_t lrf:2;
                 uint64_t vab_vwcf:1;
                 uint64_t l2t:9;
-#else
-                uint64_t l2t:9;
-                uint64_t vab_vwcf:1;
-                uint64_t lrf:2;
-                uint64_t vwdf:4;
-                uint64_t reserved_16_63:48;
-#endif
         } cn38xx;
         struct cvmx_l2c_bst1_cn38xx cn38xxp2;
         struct cvmx_l2c_bst1_cn38xx cn50xx;
         struct cvmx_l2c_bst1_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t plc2:1;
                 uint64_t plc1:1;
@@ -407,21 +225,9 @@ union cvmx_l2c_bst1 {
                 uint64_t ilc:1;
                 uint64_t vab_vwcf:1;
                 uint64_t l2t:9;
-#else
-                uint64_t l2t:9;
-                uint64_t vab_vwcf:1;
-                uint64_t ilc:1;
-                uint64_t reserved_11_11:1;
-                uint64_t vwdf:4;
-                uint64_t plc0:1;
-                uint64_t plc1:1;
-                uint64_t plc2:1;
-                uint64_t reserved_19_63:45;
-#endif
         } cn52xx;
         struct cvmx_l2c_bst1_cn52xx cn52xxp1;
         struct cvmx_l2c_bst1_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t plc2:1;
                 uint64_t plc1:1;
@@ -433,19 +239,6 @@ union cvmx_l2c_bst1 {
                 uint64_t reserved_10_10:1;
                 uint64_t vab_vwcf0:1;
                 uint64_t l2t:9;
-#else
-                uint64_t l2t:9;
-                uint64_t vab_vwcf0:1;
-                uint64_t reserved_10_10:1;
-                uint64_t vab_vwcf1:1;
-                uint64_t vwdf0:4;
-                uint64_t vwdf1:4;
-                uint64_t ilc:1;
-                uint64_t plc0:1;
-                uint64_t plc1:1;
-                uint64_t plc2:1;
-                uint64_t reserved_24_63:40;
-#endif
         } cn56xx;
         struct cvmx_l2c_bst1_cn56xx cn56xxp1;
         struct cvmx_l2c_bst1_cn38xx cn58xx;
@@ -455,7 +248,6 @@ union cvmx_l2c_bst1 {
 union cvmx_l2c_bst2 {
         uint64_t u64;
         struct cvmx_l2c_bst2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t mrb:4;
                 uint64_t reserved_4_11:8;
@@ -463,18 +255,8 @@ union cvmx_l2c_bst2 {
                 uint64_t picbst:1;
                 uint64_t xrdmsk:1;
                 uint64_t xrddat:1;
-#else
-                uint64_t xrddat:1;
-                uint64_t xrdmsk:1;
-                uint64_t picbst:1;
-                uint64_t ipcbst:1;
-                uint64_t reserved_4_11:8;
-                uint64_t mrb:4;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_l2c_bst2_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t mrb:4;
                 uint64_t rmdf:4;
@@ -483,20 +265,9 @@ union cvmx_l2c_bst2 {
                 uint64_t reserved_2_2:1;
                 uint64_t xrdmsk:1;
                 uint64_t xrddat:1;
-#else
-                uint64_t xrddat:1;
-                uint64_t xrdmsk:1;
-                uint64_t reserved_2_2:1;
-                uint64_t ipcbst:1;
-                uint64_t reserved_4_7:4;
-                uint64_t rmdf:4;
-                uint64_t mrb:4;
-                uint64_t reserved_16_63:48;
-#endif
         } cn30xx;
         struct cvmx_l2c_bst2_cn30xx cn31xx;
         struct cvmx_l2c_bst2_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t mrb:4;
                 uint64_t rmdf:4;
@@ -505,23 +276,12 @@ union cvmx_l2c_bst2 {
                 uint64_t picbst:1;
                 uint64_t xrdmsk:1;
                 uint64_t xrddat:1;
-#else
-                uint64_t xrddat:1;
-                uint64_t xrdmsk:1;
-                uint64_t picbst:1;
-                uint64_t ipcbst:1;
-                uint64_t rhdf:4;
-                uint64_t rmdf:4;
-                uint64_t mrb:4;
-                uint64_t reserved_16_63:48;
-#endif
         } cn38xx;
         struct cvmx_l2c_bst2_cn38xx cn38xxp2;
         struct cvmx_l2c_bst2_cn30xx cn50xx;
         struct cvmx_l2c_bst2_cn30xx cn52xx;
         struct cvmx_l2c_bst2_cn30xx cn52xxp1;
         struct cvmx_l2c_bst2_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t mrb:4;
                 uint64_t rmdb:4;
@@ -530,16 +290,6 @@ union cvmx_l2c_bst2 {
                 uint64_t picbst:1;
                 uint64_t xrdmsk:1;
                 uint64_t xrddat:1;
-#else
-                uint64_t xrddat:1;
-                uint64_t xrdmsk:1;
-                uint64_t picbst:1;
-                uint64_t ipcbst:1;
-                uint64_t rhdb:4;
-                uint64_t rmdb:4;
-                uint64_t mrb:4;
-                uint64_t reserved_16_63:48;
-#endif
         } cn56xx;
         struct cvmx_l2c_bst2_cn56xx cn56xxp1;
         struct cvmx_l2c_bst2_cn56xx cn58xx;
@@ -549,93 +299,48 @@ union cvmx_l2c_bst2 {
 union cvmx_l2c_bst_memx {
         uint64_t u64;
         struct cvmx_l2c_bst_memx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t start_bist:1;
                 uint64_t clear_bist:1;
                 uint64_t reserved_5_61:57;
                 uint64_t rdffl:1;
                 uint64_t vbffl:4;
-#else
-                uint64_t vbffl:4;
-                uint64_t rdffl:1;
-                uint64_t reserved_5_61:57;
-                uint64_t clear_bist:1;
-                uint64_t start_bist:1;
-#endif
         } s;
-        struct cvmx_l2c_bst_memx_s cn61xx;
         struct cvmx_l2c_bst_memx_s cn63xx;
         struct cvmx_l2c_bst_memx_s cn63xxp1;
-        struct cvmx_l2c_bst_memx_s cn66xx;
-        struct cvmx_l2c_bst_memx_s cn68xx;
-        struct cvmx_l2c_bst_memx_s cn68xxp1;
-        struct cvmx_l2c_bst_memx_s cnf71xx;
 };
 
 union cvmx_l2c_bst_tdtx {
         uint64_t u64;
         struct cvmx_l2c_bst_tdtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t fbfrspfl:8;
                 uint64_t sbffl:8;
                 uint64_t fbffl:8;
                 uint64_t l2dfl:8;
-#else
-                uint64_t l2dfl:8;
-                uint64_t fbffl:8;
-                uint64_t sbffl:8;
-                uint64_t fbfrspfl:8;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
-        struct cvmx_l2c_bst_tdtx_s cn61xx;
         struct cvmx_l2c_bst_tdtx_s cn63xx;
         struct cvmx_l2c_bst_tdtx_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t sbffl:8;
                 uint64_t fbffl:8;
                 uint64_t l2dfl:8;
-#else
-                uint64_t l2dfl:8;
-                uint64_t fbffl:8;
-                uint64_t sbffl:8;
-                uint64_t reserved_24_63:40;
-#endif
         } cn63xxp1;
-        struct cvmx_l2c_bst_tdtx_s cn66xx;
-        struct cvmx_l2c_bst_tdtx_s cn68xx;
-        struct cvmx_l2c_bst_tdtx_s cn68xxp1;
-        struct cvmx_l2c_bst_tdtx_s cnf71xx;
 };
 
 union cvmx_l2c_bst_ttgx {
         uint64_t u64;
         struct cvmx_l2c_bst_ttgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t lrufl:1;
                 uint64_t tagfl:16;
-#else
-                uint64_t tagfl:16;
-                uint64_t lrufl:1;
-                uint64_t reserved_17_63:47;
-#endif
         } s;
-        struct cvmx_l2c_bst_ttgx_s cn61xx;
         struct cvmx_l2c_bst_ttgx_s cn63xx;
         struct cvmx_l2c_bst_ttgx_s cn63xxp1;
-        struct cvmx_l2c_bst_ttgx_s cn66xx;
-        struct cvmx_l2c_bst_ttgx_s cn68xx;
-        struct cvmx_l2c_bst_ttgx_s cn68xxp1;
-        struct cvmx_l2c_bst_ttgx_s cnf71xx;
 };
 
 union cvmx_l2c_cfg {
         uint64_t u64;
         struct cvmx_l2c_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t bstrun:1;
                 uint64_t lbist:1;
@@ -651,26 +356,8 @@ union cvmx_l2c_cfg {
                 uint64_t rsp_arb_mode:1;
                 uint64_t rfb_arb_mode:1;
                 uint64_t lrf_arb_mode:1;
-#else
-                uint64_t lrf_arb_mode:1;
-                uint64_t rfb_arb_mode:1;
-                uint64_t rsp_arb_mode:1;
-                uint64_t mwf_crd:4;
-                uint64_t idxalias:1;
-                uint64_t fpen:1;
-                uint64_t fpempty:1;
-                uint64_t fpexp:4;
-                uint64_t dfill_dis:1;
-                uint64_t dpres0:1;
-                uint64_t dpres1:1;
-                uint64_t xor_bank:1;
-                uint64_t lbist:1;
-                uint64_t bstrun:1;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
         struct cvmx_l2c_cfg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t fpexp:4;
                 uint64_t fpempty:1;
@@ -680,23 +367,11 @@ union cvmx_l2c_cfg {
                 uint64_t rsp_arb_mode:1;
                 uint64_t rfb_arb_mode:1;
                 uint64_t lrf_arb_mode:1;
-#else
-                uint64_t lrf_arb_mode:1;
-                uint64_t rfb_arb_mode:1;
-                uint64_t rsp_arb_mode:1;
-                uint64_t mwf_crd:4;
-                uint64_t idxalias:1;
-                uint64_t fpen:1;
-                uint64_t fpempty:1;
-                uint64_t fpexp:4;
-                uint64_t reserved_14_63:50;
-#endif
         } cn30xx;
         struct cvmx_l2c_cfg_cn30xx cn31xx;
         struct cvmx_l2c_cfg_cn30xx cn38xx;
         struct cvmx_l2c_cfg_cn30xx cn38xxp2;
         struct cvmx_l2c_cfg_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t bstrun:1;
                 uint64_t lbist:1;
@@ -709,27 +384,12 @@ union cvmx_l2c_cfg {
                 uint64_t rsp_arb_mode:1;
                 uint64_t rfb_arb_mode:1;
                 uint64_t lrf_arb_mode:1;
-#else
-                uint64_t lrf_arb_mode:1;
-                uint64_t rfb_arb_mode:1;
-                uint64_t rsp_arb_mode:1;
-                uint64_t mwf_crd:4;
-                uint64_t idxalias:1;
-                uint64_t fpen:1;
-                uint64_t fpempty:1;
-                uint64_t fpexp:4;
-                uint64_t reserved_14_17:4;
-                uint64_t lbist:1;
-                uint64_t bstrun:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn50xx;
         struct cvmx_l2c_cfg_cn50xx cn52xx;
         struct cvmx_l2c_cfg_cn50xx cn52xxp1;
         struct cvmx_l2c_cfg_s cn56xx;
         struct cvmx_l2c_cfg_s cn56xxp1;
         struct cvmx_l2c_cfg_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t bstrun:1;
                 uint64_t lbist:1;
@@ -743,24 +403,8 @@ union cvmx_l2c_cfg {
                 uint64_t rsp_arb_mode:1;
                 uint64_t rfb_arb_mode:1;
                 uint64_t lrf_arb_mode:1;
-#else
-                uint64_t lrf_arb_mode:1;
-                uint64_t rfb_arb_mode:1;
-                uint64_t rsp_arb_mode:1;
-                uint64_t mwf_crd:4;
-                uint64_t idxalias:1;
-                uint64_t fpen:1;
-                uint64_t fpempty:1;
-                uint64_t fpexp:4;
-                uint64_t dfill_dis:1;
-                uint64_t reserved_15_17:3;
-                uint64_t lbist:1;
-                uint64_t bstrun:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn58xx;
         struct cvmx_l2c_cfg_cn58xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_15_63:49;
                 uint64_t dfill_dis:1;
                 uint64_t fpexp:4;
@@ -771,115 +415,21 @@ union cvmx_l2c_cfg {
                 uint64_t rsp_arb_mode:1;
                 uint64_t rfb_arb_mode:1;
                 uint64_t lrf_arb_mode:1;
-#else
-                uint64_t lrf_arb_mode:1;
-                uint64_t rfb_arb_mode:1;
-                uint64_t rsp_arb_mode:1;
-                uint64_t mwf_crd:4;
-                uint64_t idxalias:1;
-                uint64_t fpen:1;
-                uint64_t fpempty:1;
-                uint64_t fpexp:4;
-                uint64_t dfill_dis:1;
-                uint64_t reserved_15_63:49;
-#endif
         } cn58xxp1;
 };
 
 union cvmx_l2c_cop0_mapx {
         uint64_t u64;
         struct cvmx_l2c_cop0_mapx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
         } s;
-        struct cvmx_l2c_cop0_mapx_s cn61xx;
         struct cvmx_l2c_cop0_mapx_s cn63xx;
         struct cvmx_l2c_cop0_mapx_s cn63xxp1;
-        struct cvmx_l2c_cop0_mapx_s cn66xx;
-        struct cvmx_l2c_cop0_mapx_s cn68xx;
-        struct cvmx_l2c_cop0_mapx_s cn68xxp1;
-        struct cvmx_l2c_cop0_mapx_s cnf71xx;
 };
 
 union cvmx_l2c_ctl {
         uint64_t u64;
         struct cvmx_l2c_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_30_63:34;
-                uint64_t sepcmt:1;
-                uint64_t rdf_fast:1;
-                uint64_t disstgl2i:1;
-                uint64_t l2dfsbe:1;
-                uint64_t l2dfdbe:1;
-                uint64_t discclk:1;
-                uint64_t maxvab:4;
-                uint64_t maxlfb:4;
-                uint64_t rsp_arb_mode:1;
-                uint64_t xmc_arb_mode:1;
-                uint64_t ef_ena:1;
-                uint64_t ef_cnt:7;
-                uint64_t vab_thresh:4;
-                uint64_t disecc:1;
-                uint64_t disidxalias:1;
-#else
-                uint64_t disidxalias:1;
-                uint64_t disecc:1;
-                uint64_t vab_thresh:4;
-                uint64_t ef_cnt:7;
-                uint64_t ef_ena:1;
-                uint64_t xmc_arb_mode:1;
-                uint64_t rsp_arb_mode:1;
-                uint64_t maxlfb:4;
-                uint64_t maxvab:4;
-                uint64_t discclk:1;
-                uint64_t l2dfdbe:1;
-                uint64_t l2dfsbe:1;
-                uint64_t disstgl2i:1;
-                uint64_t rdf_fast:1;
-                uint64_t sepcmt:1;
-                uint64_t reserved_30_63:34;
-#endif
-        } s;
-        struct cvmx_l2c_ctl_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t rdf_fast:1;
-                uint64_t disstgl2i:1;
-                uint64_t l2dfsbe:1;
-                uint64_t l2dfdbe:1;
-                uint64_t discclk:1;
-                uint64_t maxvab:4;
-                uint64_t maxlfb:4;
-                uint64_t rsp_arb_mode:1;
-                uint64_t xmc_arb_mode:1;
-                uint64_t ef_ena:1;
-                uint64_t ef_cnt:7;
-                uint64_t vab_thresh:4;
-                uint64_t disecc:1;
-                uint64_t disidxalias:1;
-#else
-                uint64_t disidxalias:1;
-                uint64_t disecc:1;
-                uint64_t vab_thresh:4;
-                uint64_t ef_cnt:7;
-                uint64_t ef_ena:1;
-                uint64_t xmc_arb_mode:1;
-                uint64_t rsp_arb_mode:1;
-                uint64_t maxlfb:4;
-                uint64_t maxvab:4;
-                uint64_t discclk:1;
-                uint64_t l2dfdbe:1;
-                uint64_t l2dfsbe:1;
-                uint64_t disstgl2i:1;
-                uint64_t rdf_fast:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_ctl_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t disstgl2i:1;
                 uint64_t l2dfsbe:1;
@@ -894,25 +444,9 @@ union cvmx_l2c_ctl {
                 uint64_t vab_thresh:4;
                 uint64_t disecc:1;
                 uint64_t disidxalias:1;
-#else
-                uint64_t disidxalias:1;
-                uint64_t disecc:1;
-                uint64_t vab_thresh:4;
-                uint64_t ef_cnt:7;
-                uint64_t ef_ena:1;
-                uint64_t xmc_arb_mode:1;
-                uint64_t rsp_arb_mode:1;
-                uint64_t maxlfb:4;
-                uint64_t maxvab:4;
-                uint64_t discclk:1;
-                uint64_t l2dfdbe:1;
-                uint64_t l2dfsbe:1;
-                uint64_t disstgl2i:1;
-                uint64_t reserved_28_63:36;
-#endif
-        } cn63xx;
+        } s;
+        struct cvmx_l2c_ctl_s cn63xx;
         struct cvmx_l2c_ctl_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_25_63:39;
                 uint64_t discclk:1;
                 uint64_t maxvab:4;
@@ -924,30 +458,12 @@ union cvmx_l2c_ctl {
                 uint64_t vab_thresh:4;
                 uint64_t disecc:1;
                 uint64_t disidxalias:1;
-#else
-                uint64_t disidxalias:1;
-                uint64_t disecc:1;
-                uint64_t vab_thresh:4;
-                uint64_t ef_cnt:7;
-                uint64_t ef_ena:1;
-                uint64_t xmc_arb_mode:1;
-                uint64_t rsp_arb_mode:1;
-                uint64_t maxlfb:4;
-                uint64_t maxvab:4;
-                uint64_t discclk:1;
-                uint64_t reserved_25_63:39;
-#endif
         } cn63xxp1;
-        struct cvmx_l2c_ctl_cn61xx cn66xx;
-        struct cvmx_l2c_ctl_s cn68xx;
-        struct cvmx_l2c_ctl_cn63xx cn68xxp1;
-        struct cvmx_l2c_ctl_cn61xx cnf71xx;
 };
 
 union cvmx_l2c_dbg {
         uint64_t u64;
         struct cvmx_l2c_dbg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_15_63:49;
                 uint64_t lfb_enum:4;
                 uint64_t lfb_dmp:1;
@@ -956,19 +472,8 @@ union cvmx_l2c_dbg {
                 uint64_t finv:1;
                 uint64_t l2d:1;
                 uint64_t l2t:1;
-#else
-                uint64_t l2t:1;
-                uint64_t l2d:1;
-                uint64_t finv:1;
-                uint64_t set:3;
-                uint64_t ppnum:4;
-                uint64_t lfb_dmp:1;
-                uint64_t lfb_enum:4;
-                uint64_t reserved_15_63:49;
-#endif
         } s;
         struct cvmx_l2c_dbg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_13_63:51;
                 uint64_t lfb_enum:2;
                 uint64_t lfb_dmp:1;
@@ -979,21 +484,8 @@ union cvmx_l2c_dbg {
                 uint64_t finv:1;
                 uint64_t l2d:1;
                 uint64_t l2t:1;
-#else
-                uint64_t l2t:1;
-                uint64_t l2d:1;
-                uint64_t finv:1;
-                uint64_t set:2;
-                uint64_t reserved_5_5:1;
-                uint64_t ppnum:1;
-                uint64_t reserved_7_9:3;
-                uint64_t lfb_dmp:1;
-                uint64_t lfb_enum:2;
-                uint64_t reserved_13_63:51;
-#endif
         } cn30xx;
         struct cvmx_l2c_dbg_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t lfb_enum:3;
                 uint64_t lfb_dmp:1;
@@ -1004,23 +496,10 @@ union cvmx_l2c_dbg {
                 uint64_t finv:1;
                 uint64_t l2d:1;
                 uint64_t l2t:1;
-#else
-                uint64_t l2t:1;
-                uint64_t l2d:1;
-                uint64_t finv:1;
-                uint64_t set:2;
-                uint64_t reserved_5_5:1;
-                uint64_t ppnum:1;
-                uint64_t reserved_7_9:3;
-                uint64_t lfb_dmp:1;
-                uint64_t lfb_enum:3;
-                uint64_t reserved_14_63:50;
-#endif
         } cn31xx;
         struct cvmx_l2c_dbg_s cn38xx;
         struct cvmx_l2c_dbg_s cn38xxp2;
         struct cvmx_l2c_dbg_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t lfb_enum:3;
                 uint64_t lfb_dmp:1;
@@ -1030,20 +509,8 @@ union cvmx_l2c_dbg {
                 uint64_t finv:1;
                 uint64_t l2d:1;
                 uint64_t l2t:1;
-#else
-                uint64_t l2t:1;
-                uint64_t l2d:1;
-                uint64_t finv:1;
-                uint64_t set:3;
-                uint64_t ppnum:1;
-                uint64_t reserved_7_9:3;
-                uint64_t lfb_dmp:1;
-                uint64_t lfb_enum:3;
-                uint64_t reserved_14_63:50;
-#endif
         } cn50xx;
         struct cvmx_l2c_dbg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t lfb_enum:3;
                 uint64_t lfb_dmp:1;
@@ -1053,17 +520,6 @@ union cvmx_l2c_dbg {
                 uint64_t finv:1;
                 uint64_t l2d:1;
                 uint64_t l2t:1;
-#else
-                uint64_t l2t:1;
-                uint64_t l2d:1;
-                uint64_t finv:1;
-                uint64_t set:3;
-                uint64_t ppnum:2;
-                uint64_t reserved_8_9:2;
-                uint64_t lfb_dmp:1;
-                uint64_t lfb_enum:3;
-                uint64_t reserved_14_63:50;
-#endif
         } cn52xx;
         struct cvmx_l2c_dbg_cn52xx cn52xxp1;
         struct cvmx_l2c_dbg_s cn56xx;
@@ -1075,19 +531,11 @@ union cvmx_l2c_dbg {
 union cvmx_l2c_dut {
         uint64_t u64;
         struct cvmx_l2c_dut_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t dtena:1;
                 uint64_t reserved_30_30:1;
                 uint64_t dt_vld:1;
                 uint64_t dt_tag:29;
-#else
-                uint64_t dt_tag:29;
-                uint64_t dt_vld:1;
-                uint64_t reserved_30_30:1;
-                uint64_t dtena:1;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_l2c_dut_s cn30xx;
         struct cvmx_l2c_dut_s cn31xx;
@@ -1105,77 +553,18 @@ union cvmx_l2c_dut {
 union cvmx_l2c_dut_mapx {
         uint64_t u64;
         struct cvmx_l2c_dut_mapx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_38_63:26;
                 uint64_t tag:28;
                 uint64_t reserved_1_9:9;
                 uint64_t valid:1;
-#else
-                uint64_t valid:1;
-                uint64_t reserved_1_9:9;
-                uint64_t tag:28;
-                uint64_t reserved_38_63:26;
-#endif
         } s;
-        struct cvmx_l2c_dut_mapx_s cn61xx;
         struct cvmx_l2c_dut_mapx_s cn63xx;
         struct cvmx_l2c_dut_mapx_s cn63xxp1;
-        struct cvmx_l2c_dut_mapx_s cn66xx;
-        struct cvmx_l2c_dut_mapx_s cn68xx;
-        struct cvmx_l2c_dut_mapx_s cn68xxp1;
-        struct cvmx_l2c_dut_mapx_s cnf71xx;
 };
 
 union cvmx_l2c_err_tdtx {
         uint64_t u64;
         struct cvmx_l2c_err_tdtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dbe:1;
-                uint64_t sbe:1;
-                uint64_t vdbe:1;
-                uint64_t vsbe:1;
-                uint64_t syn:10;
-                uint64_t reserved_22_49:28;
-                uint64_t wayidx:18;
-                uint64_t reserved_2_3:2;
-                uint64_t type:2;
-#else
-                uint64_t type:2;
-                uint64_t reserved_2_3:2;
-                uint64_t wayidx:18;
-                uint64_t reserved_22_49:28;
-                uint64_t syn:10;
-                uint64_t vsbe:1;
-                uint64_t vdbe:1;
-                uint64_t sbe:1;
-                uint64_t dbe:1;
-#endif
-        } s;
-        struct cvmx_l2c_err_tdtx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dbe:1;
-                uint64_t sbe:1;
-                uint64_t vdbe:1;
-                uint64_t vsbe:1;
-                uint64_t syn:10;
-                uint64_t reserved_20_49:30;
-                uint64_t wayidx:16;
-                uint64_t reserved_2_3:2;
-                uint64_t type:2;
-#else
-                uint64_t type:2;
-                uint64_t reserved_2_3:2;
-                uint64_t wayidx:16;
-                uint64_t reserved_20_49:30;
-                uint64_t syn:10;
-                uint64_t vsbe:1;
-                uint64_t vdbe:1;
-                uint64_t sbe:1;
-                uint64_t dbe:1;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_err_tdtx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t dbe:1;
                 uint64_t sbe:1;
                 uint64_t vdbe:1;
@@ -1185,75 +574,14 @@ union cvmx_l2c_err_tdtx {
                 uint64_t wayidx:17;
                 uint64_t reserved_2_3:2;
                 uint64_t type:2;
-#else
-                uint64_t type:2;
-                uint64_t reserved_2_3:2;
-                uint64_t wayidx:17;
-                uint64_t reserved_21_49:29;
-                uint64_t syn:10;
-                uint64_t vsbe:1;
-                uint64_t vdbe:1;
-                uint64_t sbe:1;
-                uint64_t dbe:1;
-#endif
-        } cn63xx;
-        struct cvmx_l2c_err_tdtx_cn63xx cn63xxp1;
-        struct cvmx_l2c_err_tdtx_cn63xx cn66xx;
-        struct cvmx_l2c_err_tdtx_s cn68xx;
-        struct cvmx_l2c_err_tdtx_s cn68xxp1;
-        struct cvmx_l2c_err_tdtx_cn61xx cnf71xx;
+        } s;
+        struct cvmx_l2c_err_tdtx_s cn63xx;
+        struct cvmx_l2c_err_tdtx_s cn63xxp1;
 };
 
 union cvmx_l2c_err_ttgx {
         uint64_t u64;
         struct cvmx_l2c_err_ttgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dbe:1;
-                uint64_t sbe:1;
-                uint64_t noway:1;
-                uint64_t reserved_56_60:5;
-                uint64_t syn:6;
-                uint64_t reserved_22_49:28;
-                uint64_t wayidx:15;
-                uint64_t reserved_2_6:5;
-                uint64_t type:2;
-#else
-                uint64_t type:2;
-                uint64_t reserved_2_6:5;
-                uint64_t wayidx:15;
-                uint64_t reserved_22_49:28;
-                uint64_t syn:6;
-                uint64_t reserved_56_60:5;
-                uint64_t noway:1;
-                uint64_t sbe:1;
-                uint64_t dbe:1;
-#endif
-        } s;
-        struct cvmx_l2c_err_ttgx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dbe:1;
-                uint64_t sbe:1;
-                uint64_t noway:1;
-                uint64_t reserved_56_60:5;
-                uint64_t syn:6;
-                uint64_t reserved_20_49:30;
-                uint64_t wayidx:13;
-                uint64_t reserved_2_6:5;
-                uint64_t type:2;
-#else
-                uint64_t type:2;
-                uint64_t reserved_2_6:5;
-                uint64_t wayidx:13;
-                uint64_t reserved_20_49:30;
-                uint64_t syn:6;
-                uint64_t reserved_56_60:5;
-                uint64_t noway:1;
-                uint64_t sbe:1;
-                uint64_t dbe:1;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_err_ttgx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t dbe:1;
                 uint64_t sbe:1;
                 uint64_t noway:1;
@@ -1263,117 +591,43 @@ union cvmx_l2c_err_ttgx {
                 uint64_t wayidx:14;
                 uint64_t reserved_2_6:5;
                 uint64_t type:2;
-#else
-                uint64_t type:2;
-                uint64_t reserved_2_6:5;
-                uint64_t wayidx:14;
-                uint64_t reserved_21_49:29;
-                uint64_t syn:6;
-                uint64_t reserved_56_60:5;
-                uint64_t noway:1;
-                uint64_t sbe:1;
-                uint64_t dbe:1;
-#endif
-        } cn63xx;
-        struct cvmx_l2c_err_ttgx_cn63xx cn63xxp1;
-        struct cvmx_l2c_err_ttgx_cn63xx cn66xx;
-        struct cvmx_l2c_err_ttgx_s cn68xx;
-        struct cvmx_l2c_err_ttgx_s cn68xxp1;
-        struct cvmx_l2c_err_ttgx_cn61xx cnf71xx;
+        } s;
+        struct cvmx_l2c_err_ttgx_s cn63xx;
+        struct cvmx_l2c_err_ttgx_s cn63xxp1;
 };
 
 union cvmx_l2c_err_vbfx {
         uint64_t u64;
         struct cvmx_l2c_err_vbfx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t vdbe:1;
                 uint64_t vsbe:1;
                 uint64_t vsyn:10;
                 uint64_t reserved_2_49:48;
                 uint64_t type:2;
-#else
-                uint64_t type:2;
-                uint64_t reserved_2_49:48;
-                uint64_t vsyn:10;
-                uint64_t vsbe:1;
-                uint64_t vdbe:1;
-                uint64_t reserved_62_63:2;
-#endif
         } s;
-        struct cvmx_l2c_err_vbfx_s cn61xx;
         struct cvmx_l2c_err_vbfx_s cn63xx;
         struct cvmx_l2c_err_vbfx_s cn63xxp1;
-        struct cvmx_l2c_err_vbfx_s cn66xx;
-        struct cvmx_l2c_err_vbfx_s cn68xx;
-        struct cvmx_l2c_err_vbfx_s cn68xxp1;
-        struct cvmx_l2c_err_vbfx_s cnf71xx;
 };
 
 union cvmx_l2c_err_xmc {
         uint64_t u64;
         struct cvmx_l2c_err_xmc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t cmd:6;
-                uint64_t reserved_54_57:4;
-                uint64_t sid:6;
-                uint64_t reserved_38_47:10;
-                uint64_t addr:38;
-#else
-                uint64_t addr:38;
-                uint64_t reserved_38_47:10;
-                uint64_t sid:6;
-                uint64_t reserved_54_57:4;
-                uint64_t cmd:6;
-#endif
-        } s;
-        struct cvmx_l2c_err_xmc_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t cmd:6;
                 uint64_t reserved_52_57:6;
                 uint64_t sid:4;
                 uint64_t reserved_38_47:10;
                 uint64_t addr:38;
-#else
-                uint64_t addr:38;
-                uint64_t reserved_38_47:10;
-                uint64_t sid:4;
-                uint64_t reserved_52_57:6;
-                uint64_t cmd:6;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_err_xmc_cn61xx cn63xx;
-        struct cvmx_l2c_err_xmc_cn61xx cn63xxp1;
-        struct cvmx_l2c_err_xmc_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t cmd:6;
-                uint64_t reserved_53_57:5;
-                uint64_t sid:5;
-                uint64_t reserved_38_47:10;
-                uint64_t addr:38;
-#else
-                uint64_t addr:38;
-                uint64_t reserved_38_47:10;
-                uint64_t sid:5;
-                uint64_t reserved_53_57:5;
-                uint64_t cmd:6;
-#endif
-        } cn66xx;
-        struct cvmx_l2c_err_xmc_s cn68xx;
-        struct cvmx_l2c_err_xmc_s cn68xxp1;
-        struct cvmx_l2c_err_xmc_cn61xx cnf71xx;
+        } s;
+        struct cvmx_l2c_err_xmc_s cn63xx;
+        struct cvmx_l2c_err_xmc_s cn63xxp1;
 };
 
 union cvmx_l2c_grpwrr0 {
         uint64_t u64;
         struct cvmx_l2c_grpwrr0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t plc1rmsk:32;
                 uint64_t plc0rmsk:32;
-#else
-                uint64_t plc0rmsk:32;
-                uint64_t plc1rmsk:32;
-#endif
         } s;
         struct cvmx_l2c_grpwrr0_s cn52xx;
         struct cvmx_l2c_grpwrr0_s cn52xxp1;
@@ -1384,13 +638,8 @@ union cvmx_l2c_grpwrr0 {
 union cvmx_l2c_grpwrr1 {
         uint64_t u64;
         struct cvmx_l2c_grpwrr1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t ilcrmsk:32;
                 uint64_t plc2rmsk:32;
-#else
-                uint64_t plc2rmsk:32;
-                uint64_t ilcrmsk:32;
-#endif
         } s;
         struct cvmx_l2c_grpwrr1_s cn52xx;
         struct cvmx_l2c_grpwrr1_s cn52xxp1;
@@ -1401,7 +650,6 @@ union cvmx_l2c_grpwrr1 {
 union cvmx_l2c_int_en {
         uint64_t u64;
         struct cvmx_l2c_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t lck2ena:1;
                 uint64_t lckena:1;
@@ -1412,18 +660,6 @@ union cvmx_l2c_int_en {
                 uint64_t oob3en:1;
                 uint64_t oob2en:1;
                 uint64_t oob1en:1;
-#else
-                uint64_t oob1en:1;
-                uint64_t oob2en:1;
-                uint64_t oob3en:1;
-                uint64_t l2tsecen:1;
-                uint64_t l2tdeden:1;
-                uint64_t l2dsecen:1;
-                uint64_t l2ddeden:1;
-                uint64_t lckena:1;
-                uint64_t lck2ena:1;
-                uint64_t reserved_9_63:55;
-#endif
         } s;
         struct cvmx_l2c_int_en_s cn52xx;
         struct cvmx_l2c_int_en_s cn52xxp1;
@@ -1434,7 +670,6 @@ union cvmx_l2c_int_en {
 union cvmx_l2c_int_ena {
         uint64_t u64;
         struct cvmx_l2c_int_ena_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t bigrd:1;
                 uint64_t bigwr:1;
@@ -1444,22 +679,9 @@ union cvmx_l2c_int_ena {
                 uint64_t vrtwr:1;
                 uint64_t holewr:1;
                 uint64_t holerd:1;
-#else
-                uint64_t holerd:1;
-                uint64_t holewr:1;
-                uint64_t vrtwr:1;
-                uint64_t vrtidrng:1;
-                uint64_t vrtadrng:1;
-                uint64_t vrtpe:1;
-                uint64_t bigwr:1;
-                uint64_t bigrd:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
-        struct cvmx_l2c_int_ena_s cn61xx;
         struct cvmx_l2c_int_ena_s cn63xx;
         struct cvmx_l2c_int_ena_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t vrtpe:1;
                 uint64_t vrtadrng:1;
@@ -1467,59 +689,12 @@ union cvmx_l2c_int_ena {
                 uint64_t vrtwr:1;
                 uint64_t holewr:1;
                 uint64_t holerd:1;
-#else
-                uint64_t holerd:1;
-                uint64_t holewr:1;
-                uint64_t vrtwr:1;
-                uint64_t vrtidrng:1;
-                uint64_t vrtadrng:1;
-                uint64_t vrtpe:1;
-                uint64_t reserved_6_63:58;
-#endif
         } cn63xxp1;
-        struct cvmx_l2c_int_ena_s cn66xx;
-        struct cvmx_l2c_int_ena_s cn68xx;
-        struct cvmx_l2c_int_ena_s cn68xxp1;
-        struct cvmx_l2c_int_ena_s cnf71xx;
 };
 
 union cvmx_l2c_int_reg {
         uint64_t u64;
         struct cvmx_l2c_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t tad3:1;
-                uint64_t tad2:1;
-                uint64_t tad1:1;
-                uint64_t tad0:1;
-                uint64_t reserved_8_15:8;
-                uint64_t bigrd:1;
-                uint64_t bigwr:1;
-                uint64_t vrtpe:1;
-                uint64_t vrtadrng:1;
-                uint64_t vrtidrng:1;
-                uint64_t vrtwr:1;
-                uint64_t holewr:1;
-                uint64_t holerd:1;
-#else
-                uint64_t holerd:1;
-                uint64_t holewr:1;
-                uint64_t vrtwr:1;
-                uint64_t vrtidrng:1;
-                uint64_t vrtadrng:1;
-                uint64_t vrtpe:1;
-                uint64_t bigwr:1;
-                uint64_t bigrd:1;
-                uint64_t reserved_8_15:8;
-                uint64_t tad0:1;
-                uint64_t tad1:1;
-                uint64_t tad2:1;
-                uint64_t tad3:1;
-                uint64_t reserved_20_63:44;
-#endif
-        } s;
-        struct cvmx_l2c_int_reg_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t tad0:1;
                 uint64_t reserved_8_15:8;
@@ -1531,23 +706,9 @@ union cvmx_l2c_int_reg {
                 uint64_t vrtwr:1;
                 uint64_t holewr:1;
                 uint64_t holerd:1;
-#else
-                uint64_t holerd:1;
-                uint64_t holewr:1;
-                uint64_t vrtwr:1;
-                uint64_t vrtidrng:1;
-                uint64_t vrtadrng:1;
-                uint64_t vrtpe:1;
-                uint64_t bigwr:1;
-                uint64_t bigrd:1;
-                uint64_t reserved_8_15:8;
-                uint64_t tad0:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_int_reg_cn61xx cn63xx;
+        } s;
+        struct cvmx_l2c_int_reg_s cn63xx;
         struct cvmx_l2c_int_reg_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t tad0:1;
                 uint64_t reserved_6_15:10;
@@ -1557,28 +718,12 @@ union cvmx_l2c_int_reg {
                 uint64_t vrtwr:1;
                 uint64_t holewr:1;
                 uint64_t holerd:1;
-#else
-                uint64_t holerd:1;
-                uint64_t holewr:1;
-                uint64_t vrtwr:1;
-                uint64_t vrtidrng:1;
-                uint64_t vrtadrng:1;
-                uint64_t vrtpe:1;
-                uint64_t reserved_6_15:10;
-                uint64_t tad0:1;
-                uint64_t reserved_17_63:47;
-#endif
         } cn63xxp1;
-        struct cvmx_l2c_int_reg_cn61xx cn66xx;
-        struct cvmx_l2c_int_reg_s cn68xx;
-        struct cvmx_l2c_int_reg_s cn68xxp1;
-        struct cvmx_l2c_int_reg_cn61xx cnf71xx;
 };
 
 union cvmx_l2c_int_stat {
         uint64_t u64;
         struct cvmx_l2c_int_stat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t lck2:1;
                 uint64_t lck:1;
@@ -1589,18 +734,6 @@ union cvmx_l2c_int_stat {
                 uint64_t oob3:1;
                 uint64_t oob2:1;
                 uint64_t oob1:1;
-#else
-                uint64_t oob1:1;
-                uint64_t oob2:1;
-                uint64_t oob3:1;
-                uint64_t l2tsec:1;
-                uint64_t l2tded:1;
-                uint64_t l2dsec:1;
-                uint64_t l2dded:1;
-                uint64_t lck:1;
-                uint64_t lck2:1;
-                uint64_t reserved_9_63:55;
-#endif
         } s;
         struct cvmx_l2c_int_stat_s cn52xx;
         struct cvmx_l2c_int_stat_s cn52xxp1;
@@ -1611,53 +744,28 @@ union cvmx_l2c_int_stat {
 union cvmx_l2c_iocx_pfc {
         uint64_t u64;
         struct cvmx_l2c_iocx_pfc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t count:64;
-#else
                 uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_iocx_pfc_s cn61xx;
         struct cvmx_l2c_iocx_pfc_s cn63xx;
         struct cvmx_l2c_iocx_pfc_s cn63xxp1;
-        struct cvmx_l2c_iocx_pfc_s cn66xx;
-        struct cvmx_l2c_iocx_pfc_s cn68xx;
-        struct cvmx_l2c_iocx_pfc_s cn68xxp1;
-        struct cvmx_l2c_iocx_pfc_s cnf71xx;
 };
 
 union cvmx_l2c_iorx_pfc {
         uint64_t u64;
         struct cvmx_l2c_iorx_pfc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t count:64;
-#else
                 uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_iorx_pfc_s cn61xx;
         struct cvmx_l2c_iorx_pfc_s cn63xx;
         struct cvmx_l2c_iorx_pfc_s cn63xxp1;
-        struct cvmx_l2c_iorx_pfc_s cn66xx;
-        struct cvmx_l2c_iorx_pfc_s cn68xx;
-        struct cvmx_l2c_iorx_pfc_s cn68xxp1;
-        struct cvmx_l2c_iorx_pfc_s cnf71xx;
 };
 
 union cvmx_l2c_lckbase {
         uint64_t u64;
         struct cvmx_l2c_lckbase_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_31_63:33;
                 uint64_t lck_base:27;
                 uint64_t reserved_1_3:3;
                 uint64_t lck_ena:1;
-#else
-                uint64_t lck_ena:1;
-                uint64_t reserved_1_3:3;
-                uint64_t lck_base:27;
-                uint64_t reserved_31_63:33;
-#endif
         } s;
         struct cvmx_l2c_lckbase_s cn30xx;
         struct cvmx_l2c_lckbase_s cn31xx;
@@ -1675,13 +783,8 @@ union cvmx_l2c_lckbase {
 union cvmx_l2c_lckoff {
         uint64_t u64;
         struct cvmx_l2c_lckoff_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t lck_offset:10;
-#else
-                uint64_t lck_offset:10;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_l2c_lckoff_s cn30xx;
         struct cvmx_l2c_lckoff_s cn31xx;
@@ -1699,7 +802,6 @@ union cvmx_l2c_lckoff {
 union cvmx_l2c_lfb0 {
         uint64_t u64;
         struct cvmx_l2c_lfb0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t stcpnd:1;
                 uint64_t stpnd:1;
@@ -1714,25 +816,8 @@ union cvmx_l2c_lfb0 {
                 uint64_t sid:9;
                 uint64_t cmd:4;
                 uint64_t vld:1;
-#else
-                uint64_t vld:1;
-                uint64_t cmd:4;
-                uint64_t sid:9;
-                uint64_t vabnum:4;
-                uint64_t set:3;
-                uint64_t ihd:1;
-                uint64_t itl:1;
-                uint64_t inxt:4;
-                uint64_t vam:1;
-                uint64_t stcfl:1;
-                uint64_t stinv:1;
-                uint64_t stpnd:1;
-                uint64_t stcpnd:1;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_l2c_lfb0_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t stcpnd:1;
                 uint64_t stpnd:1;
@@ -1750,28 +835,8 @@ union cvmx_l2c_lfb0 {
                 uint64_t sid:9;
                 uint64_t cmd:4;
                 uint64_t vld:1;
-#else
-                uint64_t vld:1;
-                uint64_t cmd:4;
-                uint64_t sid:9;
-                uint64_t vabnum:2;
-                uint64_t reserved_16_17:2;
-                uint64_t set:2;
-                uint64_t reserved_20_20:1;
-                uint64_t ihd:1;
-                uint64_t itl:1;
-                uint64_t inxt:2;
-                uint64_t reserved_25_26:2;
-                uint64_t vam:1;
-                uint64_t stcfl:1;
-                uint64_t stinv:1;
-                uint64_t stpnd:1;
-                uint64_t stcpnd:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn30xx;
         struct cvmx_l2c_lfb0_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t stcpnd:1;
                 uint64_t stpnd:1;
@@ -1789,30 +854,10 @@ union cvmx_l2c_lfb0 {
                 uint64_t sid:9;
                 uint64_t cmd:4;
                 uint64_t vld:1;
-#else
-                uint64_t vld:1;
-                uint64_t cmd:4;
-                uint64_t sid:9;
-                uint64_t vabnum:3;
-                uint64_t reserved_17_17:1;
-                uint64_t set:2;
-                uint64_t reserved_20_20:1;
-                uint64_t ihd:1;
-                uint64_t itl:1;
-                uint64_t inxt:3;
-                uint64_t reserved_26_26:1;
-                uint64_t vam:1;
-                uint64_t stcfl:1;
-                uint64_t stinv:1;
-                uint64_t stpnd:1;
-                uint64_t stcpnd:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn31xx;
         struct cvmx_l2c_lfb0_s cn38xx;
         struct cvmx_l2c_lfb0_s cn38xxp2;
         struct cvmx_l2c_lfb0_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t stcpnd:1;
                 uint64_t stpnd:1;
@@ -1829,24 +874,6 @@ union cvmx_l2c_lfb0 {
                 uint64_t sid:9;
                 uint64_t cmd:4;
                 uint64_t vld:1;
-#else
-                uint64_t vld:1;
-                uint64_t cmd:4;
-                uint64_t sid:9;
-                uint64_t vabnum:3;
-                uint64_t reserved_17_17:1;
-                uint64_t set:3;
-                uint64_t ihd:1;
-                uint64_t itl:1;
-                uint64_t inxt:3;
-                uint64_t reserved_26_26:1;
-                uint64_t vam:1;
-                uint64_t stcfl:1;
-                uint64_t stinv:1;
-                uint64_t stpnd:1;
-                uint64_t stcpnd:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn50xx;
         struct cvmx_l2c_lfb0_cn50xx cn52xx;
         struct cvmx_l2c_lfb0_cn50xx cn52xxp1;
@@ -1859,7 +886,6 @@ union cvmx_l2c_lfb0 {
 union cvmx_l2c_lfb1 {
         uint64_t u64;
         struct cvmx_l2c_lfb1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t dsgoing:1;
                 uint64_t bid:2;
@@ -1879,27 +905,6 @@ union cvmx_l2c_lfb1 {
                 uint64_t prbrty:1;
                 uint64_t wtprb:1;
                 uint64_t vld:1;
-#else
-                uint64_t vld:1;
-                uint64_t wtprb:1;
-                uint64_t prbrty:1;
-                uint64_t wtmfl:1;
-                uint64_t wtvtm:1;
-                uint64_t wtstrsc:1;
-                uint64_t wtstrsp:1;
-                uint64_t wtstdt:1;
-                uint64_t wtrda:1;
-                uint64_t wtstm:1;
-                uint64_t wtwrm:1;
-                uint64_t wtwhf:1;
-                uint64_t wtwhp:1;
-                uint64_t wtdq:1;
-                uint64_t wtdw:1;
-                uint64_t wtrsp:1;
-                uint64_t bid:2;
-                uint64_t dsgoing:1;
-                uint64_t reserved_19_63:45;
-#endif
         } s;
         struct cvmx_l2c_lfb1_s cn30xx;
         struct cvmx_l2c_lfb1_s cn31xx;
@@ -1917,69 +922,35 @@ union cvmx_l2c_lfb1 {
 union cvmx_l2c_lfb2 {
         uint64_t u64;
         struct cvmx_l2c_lfb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
         } s;
         struct cvmx_l2c_lfb2_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_27_63:37;
                 uint64_t lfb_tag:19;
                 uint64_t lfb_idx:8;
-#else
-                uint64_t lfb_idx:8;
-                uint64_t lfb_tag:19;
-                uint64_t reserved_27_63:37;
-#endif
         } cn30xx;
         struct cvmx_l2c_lfb2_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_27_63:37;
                 uint64_t lfb_tag:17;
                 uint64_t lfb_idx:10;
-#else
-                uint64_t lfb_idx:10;
-                uint64_t lfb_tag:17;
-                uint64_t reserved_27_63:37;
-#endif
         } cn31xx;
         struct cvmx_l2c_lfb2_cn31xx cn38xx;
         struct cvmx_l2c_lfb2_cn31xx cn38xxp2;
         struct cvmx_l2c_lfb2_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_27_63:37;
                 uint64_t lfb_tag:20;
                 uint64_t lfb_idx:7;
-#else
-                uint64_t lfb_idx:7;
-                uint64_t lfb_tag:20;
-                uint64_t reserved_27_63:37;
-#endif
         } cn50xx;
         struct cvmx_l2c_lfb2_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_27_63:37;
                 uint64_t lfb_tag:18;
                 uint64_t lfb_idx:9;
-#else
-                uint64_t lfb_idx:9;
-                uint64_t lfb_tag:18;
-                uint64_t reserved_27_63:37;
-#endif
         } cn52xx;
         struct cvmx_l2c_lfb2_cn52xx cn52xxp1;
         struct cvmx_l2c_lfb2_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_27_63:37;
                 uint64_t lfb_tag:16;
                 uint64_t lfb_idx:11;
-#else
-                uint64_t lfb_idx:11;
-                uint64_t lfb_tag:16;
-                uint64_t reserved_27_63:37;
-#endif
         } cn56xx;
         struct cvmx_l2c_lfb2_cn56xx cn56xxp1;
         struct cvmx_l2c_lfb2_cn56xx cn58xx;
@@ -1989,41 +960,21 @@ union cvmx_l2c_lfb2 {
 union cvmx_l2c_lfb3 {
         uint64_t u64;
         struct cvmx_l2c_lfb3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t stpartdis:1;
                 uint64_t lfb_hwm:4;
-#else
-                uint64_t lfb_hwm:4;
-                uint64_t stpartdis:1;
-                uint64_t reserved_5_63:59;
-#endif
         } s;
         struct cvmx_l2c_lfb3_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t stpartdis:1;
                 uint64_t reserved_2_3:2;
                 uint64_t lfb_hwm:2;
-#else
-                uint64_t lfb_hwm:2;
-                uint64_t reserved_2_3:2;
-                uint64_t stpartdis:1;
-                uint64_t reserved_5_63:59;
-#endif
         } cn30xx;
         struct cvmx_l2c_lfb3_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t stpartdis:1;
                 uint64_t reserved_3_3:1;
                 uint64_t lfb_hwm:3;
-#else
-                uint64_t lfb_hwm:3;
-                uint64_t reserved_3_3:1;
-                uint64_t stpartdis:1;
-                uint64_t reserved_5_63:59;
-#endif
         } cn31xx;
         struct cvmx_l2c_lfb3_s cn38xx;
         struct cvmx_l2c_lfb3_s cn38xxp2;
@@ -2039,15 +990,9 @@ union cvmx_l2c_lfb3 {
 union cvmx_l2c_oob {
         uint64_t u64;
         struct cvmx_l2c_oob_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t dwbena:1;
                 uint64_t stena:1;
-#else
-                uint64_t stena:1;
-                uint64_t dwbena:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_l2c_oob_s cn52xx;
         struct cvmx_l2c_oob_s cn52xxp1;
@@ -2058,21 +1003,12 @@ union cvmx_l2c_oob {
 union cvmx_l2c_oob1 {
         uint64_t u64;
         struct cvmx_l2c_oob1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t fadr:27;
                 uint64_t fsrc:1;
                 uint64_t reserved_34_35:2;
                 uint64_t sadr:14;
                 uint64_t reserved_14_19:6;
                 uint64_t size:14;
-#else
-                uint64_t size:14;
-                uint64_t reserved_14_19:6;
-                uint64_t sadr:14;
-                uint64_t reserved_34_35:2;
-                uint64_t fsrc:1;
-                uint64_t fadr:27;
-#endif
         } s;
         struct cvmx_l2c_oob1_s cn52xx;
         struct cvmx_l2c_oob1_s cn52xxp1;
@@ -2083,21 +1019,12 @@ union cvmx_l2c_oob1 {
 union cvmx_l2c_oob2 {
         uint64_t u64;
         struct cvmx_l2c_oob2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t fadr:27;
                 uint64_t fsrc:1;
                 uint64_t reserved_34_35:2;
                 uint64_t sadr:14;
                 uint64_t reserved_14_19:6;
                 uint64_t size:14;
-#else
-                uint64_t size:14;
-                uint64_t reserved_14_19:6;
-                uint64_t sadr:14;
-                uint64_t reserved_34_35:2;
-                uint64_t fsrc:1;
-                uint64_t fadr:27;
-#endif
         } s;
         struct cvmx_l2c_oob2_s cn52xx;
         struct cvmx_l2c_oob2_s cn52xxp1;
@@ -2108,21 +1035,12 @@ union cvmx_l2c_oob2 {
 union cvmx_l2c_oob3 {
         uint64_t u64;
         struct cvmx_l2c_oob3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t fadr:27;
                 uint64_t fsrc:1;
                 uint64_t reserved_34_35:2;
                 uint64_t sadr:14;
                 uint64_t reserved_14_19:6;
                 uint64_t size:14;
-#else
-                uint64_t size:14;
-                uint64_t reserved_14_19:6;
-                uint64_t sadr:14;
-                uint64_t reserved_34_35:2;
-                uint64_t fsrc:1;
-                uint64_t fadr:27;
-#endif
         } s;
         struct cvmx_l2c_oob3_s cn52xx;
         struct cvmx_l2c_oob3_s cn52xxp1;
@@ -2133,13 +1051,8 @@ union cvmx_l2c_oob3 {
 union cvmx_l2c_pfcx {
         uint64_t u64;
         struct cvmx_l2c_pfcx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t pfcnt0:36;
-#else
-                uint64_t pfcnt0:36;
-                uint64_t reserved_36_63:28;
-#endif
         } s;
         struct cvmx_l2c_pfcx_s cn30xx;
         struct cvmx_l2c_pfcx_s cn31xx;
@@ -2157,7 +1070,6 @@ union cvmx_l2c_pfcx {
 union cvmx_l2c_pfctl {
         uint64_t u64;
         struct cvmx_l2c_pfctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t cnt3rdclr:1;
                 uint64_t cnt2rdclr:1;
@@ -2175,25 +1087,6 @@ union cvmx_l2c_pfctl {
                 uint64_t cnt0ena:1;
                 uint64_t cnt0clr:1;
                 uint64_t cnt0sel:6;
-#else
-                uint64_t cnt0sel:6;
-                uint64_t cnt0clr:1;
-                uint64_t cnt0ena:1;
-                uint64_t cnt1sel:6;
-                uint64_t cnt1clr:1;
-                uint64_t cnt1ena:1;
-                uint64_t cnt2sel:6;
-                uint64_t cnt2clr:1;
-                uint64_t cnt2ena:1;
-                uint64_t cnt3sel:6;
-                uint64_t cnt3clr:1;
-                uint64_t cnt3ena:1;
-                uint64_t cnt0rdclr:1;
-                uint64_t cnt1rdclr:1;
-                uint64_t cnt2rdclr:1;
-                uint64_t cnt3rdclr:1;
-                uint64_t reserved_36_63:28;
-#endif
         } s;
         struct cvmx_l2c_pfctl_s cn30xx;
         struct cvmx_l2c_pfctl_s cn31xx;
@@ -2211,7 +1104,6 @@ union cvmx_l2c_pfctl {
 union cvmx_l2c_ppgrp {
         uint64_t u64;
         struct cvmx_l2c_ppgrp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t pp11grp:2;
                 uint64_t pp10grp:2;
@@ -2225,36 +1117,13 @@ union cvmx_l2c_ppgrp {
                 uint64_t pp2grp:2;
                 uint64_t pp1grp:2;
                 uint64_t pp0grp:2;
-#else
-                uint64_t pp0grp:2;
-                uint64_t pp1grp:2;
-                uint64_t pp2grp:2;
-                uint64_t pp3grp:2;
-                uint64_t pp4grp:2;
-                uint64_t pp5grp:2;
-                uint64_t pp6grp:2;
-                uint64_t pp7grp:2;
-                uint64_t pp8grp:2;
-                uint64_t pp9grp:2;
-                uint64_t pp10grp:2;
-                uint64_t pp11grp:2;
-                uint64_t reserved_24_63:40;
-#endif
         } s;
         struct cvmx_l2c_ppgrp_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t pp3grp:2;
                 uint64_t pp2grp:2;
                 uint64_t pp1grp:2;
                 uint64_t pp0grp:2;
-#else
-                uint64_t pp0grp:2;
-                uint64_t pp1grp:2;
-                uint64_t pp2grp:2;
-                uint64_t pp3grp:2;
-                uint64_t reserved_8_63:56;
-#endif
         } cn52xx;
         struct cvmx_l2c_ppgrp_cn52xx cn52xxp1;
         struct cvmx_l2c_ppgrp_s cn56xx;
@@ -2264,200 +1133,81 @@ union cvmx_l2c_ppgrp {
 union cvmx_l2c_qos_iobx {
         uint64_t u64;
         struct cvmx_l2c_qos_iobx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t dwblvl:3;
-                uint64_t reserved_3_3:1;
-                uint64_t lvl:3;
-#else
-                uint64_t lvl:3;
-                uint64_t reserved_3_3:1;
-                uint64_t dwblvl:3;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_l2c_qos_iobx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t dwblvl:2;
                 uint64_t reserved_2_3:2;
                 uint64_t lvl:2;
-#else
-                uint64_t lvl:2;
-                uint64_t reserved_2_3:2;
-                uint64_t dwblvl:2;
-                uint64_t reserved_6_63:58;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_qos_iobx_cn61xx cn63xx;
-        struct cvmx_l2c_qos_iobx_cn61xx cn63xxp1;
-        struct cvmx_l2c_qos_iobx_cn61xx cn66xx;
-        struct cvmx_l2c_qos_iobx_s cn68xx;
-        struct cvmx_l2c_qos_iobx_s cn68xxp1;
-        struct cvmx_l2c_qos_iobx_cn61xx cnf71xx;
+        } s;
+        struct cvmx_l2c_qos_iobx_s cn63xx;
+        struct cvmx_l2c_qos_iobx_s cn63xxp1;
 };
 
 union cvmx_l2c_qos_ppx {
         uint64_t u64;
         struct cvmx_l2c_qos_ppx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t lvl:3;
-#else
-                uint64_t lvl:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_l2c_qos_ppx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t lvl:2;
-#else
-                uint64_t lvl:2;
-                uint64_t reserved_2_63:62;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_qos_ppx_cn61xx cn63xx;
-        struct cvmx_l2c_qos_ppx_cn61xx cn63xxp1;
-        struct cvmx_l2c_qos_ppx_cn61xx cn66xx;
-        struct cvmx_l2c_qos_ppx_s cn68xx;
-        struct cvmx_l2c_qos_ppx_s cn68xxp1;
-        struct cvmx_l2c_qos_ppx_cn61xx cnf71xx;
+        } s;
+        struct cvmx_l2c_qos_ppx_s cn63xx;
+        struct cvmx_l2c_qos_ppx_s cn63xxp1;
 };
 
 union cvmx_l2c_qos_wgt {
         uint64_t u64;
         struct cvmx_l2c_qos_wgt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t wgt7:8;
-                uint64_t wgt6:8;
-                uint64_t wgt5:8;
-                uint64_t wgt4:8;
-                uint64_t wgt3:8;
-                uint64_t wgt2:8;
-                uint64_t wgt1:8;
-                uint64_t wgt0:8;
-#else
-                uint64_t wgt0:8;
-                uint64_t wgt1:8;
-                uint64_t wgt2:8;
-                uint64_t wgt3:8;
-                uint64_t wgt4:8;
-                uint64_t wgt5:8;
-                uint64_t wgt6:8;
-                uint64_t wgt7:8;
-#endif
-        } s;
-        struct cvmx_l2c_qos_wgt_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t wgt3:8;
                 uint64_t wgt2:8;
                 uint64_t wgt1:8;
                 uint64_t wgt0:8;
-#else
-                uint64_t wgt0:8;
-                uint64_t wgt1:8;
-                uint64_t wgt2:8;
-                uint64_t wgt3:8;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_qos_wgt_cn61xx cn63xx;
-        struct cvmx_l2c_qos_wgt_cn61xx cn63xxp1;
-        struct cvmx_l2c_qos_wgt_cn61xx cn66xx;
-        struct cvmx_l2c_qos_wgt_s cn68xx;
-        struct cvmx_l2c_qos_wgt_s cn68xxp1;
-        struct cvmx_l2c_qos_wgt_cn61xx cnf71xx;
+        } s;
+        struct cvmx_l2c_qos_wgt_s cn63xx;
+        struct cvmx_l2c_qos_wgt_s cn63xxp1;
 };
 
 union cvmx_l2c_rscx_pfc {
         uint64_t u64;
         struct cvmx_l2c_rscx_pfc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t count:64;
-#else
-                uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_rscx_pfc_s cn61xx;
         struct cvmx_l2c_rscx_pfc_s cn63xx;
         struct cvmx_l2c_rscx_pfc_s cn63xxp1;
-        struct cvmx_l2c_rscx_pfc_s cn66xx;
-        struct cvmx_l2c_rscx_pfc_s cn68xx;
-        struct cvmx_l2c_rscx_pfc_s cn68xxp1;
-        struct cvmx_l2c_rscx_pfc_s cnf71xx;
 };
 
 union cvmx_l2c_rsdx_pfc {
         uint64_t u64;
         struct cvmx_l2c_rsdx_pfc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t count:64;
-#else
-                uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_rsdx_pfc_s cn61xx;
         struct cvmx_l2c_rsdx_pfc_s cn63xx;
         struct cvmx_l2c_rsdx_pfc_s cn63xxp1;
-        struct cvmx_l2c_rsdx_pfc_s cn66xx;
-        struct cvmx_l2c_rsdx_pfc_s cn68xx;
-        struct cvmx_l2c_rsdx_pfc_s cn68xxp1;
-        struct cvmx_l2c_rsdx_pfc_s cnf71xx;
 };
 
 union cvmx_l2c_spar0 {
         uint64_t u64;
         struct cvmx_l2c_spar0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t umsk3:8;
                 uint64_t umsk2:8;
                 uint64_t umsk1:8;
                 uint64_t umsk0:8;
-#else
-                uint64_t umsk0:8;
-                uint64_t umsk1:8;
-                uint64_t umsk2:8;
-                uint64_t umsk3:8;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_l2c_spar0_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t umsk0:4;
-#else
-                uint64_t umsk0:4;
-                uint64_t reserved_4_63:60;
-#endif
         } cn30xx;
         struct cvmx_l2c_spar0_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t umsk1:4;
                 uint64_t reserved_4_7:4;
                 uint64_t umsk0:4;
-#else
-                uint64_t umsk0:4;
-                uint64_t reserved_4_7:4;
-                uint64_t umsk1:4;
-                uint64_t reserved_12_63:52;
-#endif
         } cn31xx;
         struct cvmx_l2c_spar0_s cn38xx;
         struct cvmx_l2c_spar0_s cn38xxp2;
         struct cvmx_l2c_spar0_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t umsk1:8;
                 uint64_t umsk0:8;
-#else
-                uint64_t umsk0:8;
-                uint64_t umsk1:8;
-                uint64_t reserved_16_63:48;
-#endif
         } cn50xx;
         struct cvmx_l2c_spar0_s cn52xx;
         struct cvmx_l2c_spar0_s cn52xxp1;
@@ -2470,19 +1220,11 @@ union cvmx_l2c_spar0 {
 union cvmx_l2c_spar1 {
         uint64_t u64;
         struct cvmx_l2c_spar1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t umsk7:8;
                 uint64_t umsk6:8;
                 uint64_t umsk5:8;
                 uint64_t umsk4:8;
-#else
-                uint64_t umsk4:8;
-                uint64_t umsk5:8;
-                uint64_t umsk6:8;
-                uint64_t umsk7:8;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_l2c_spar1_s cn38xx;
         struct cvmx_l2c_spar1_s cn38xxp2;
@@ -2495,19 +1237,11 @@ union cvmx_l2c_spar1 {
 union cvmx_l2c_spar2 {
         uint64_t u64;
         struct cvmx_l2c_spar2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t umsk11:8;
                 uint64_t umsk10:8;
                 uint64_t umsk9:8;
                 uint64_t umsk8:8;
-#else
-                uint64_t umsk8:8;
-                uint64_t umsk9:8;
-                uint64_t umsk10:8;
-                uint64_t umsk11:8;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_l2c_spar2_s cn38xx;
         struct cvmx_l2c_spar2_s cn38xxp2;
@@ -2520,19 +1254,11 @@ union cvmx_l2c_spar2 {
 union cvmx_l2c_spar3 {
         uint64_t u64;
         struct cvmx_l2c_spar3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t umsk15:8;
                 uint64_t umsk14:8;
                 uint64_t umsk13:8;
                 uint64_t umsk12:8;
-#else
-                uint64_t umsk12:8;
-                uint64_t umsk13:8;
-                uint64_t umsk14:8;
-                uint64_t umsk15:8;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_l2c_spar3_s cn38xx;
         struct cvmx_l2c_spar3_s cn38xxp2;
@@ -2543,22 +1269,12 @@ union cvmx_l2c_spar3 {
 union cvmx_l2c_spar4 {
         uint64_t u64;
         struct cvmx_l2c_spar4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t umskiob:8;
-#else
-                uint64_t umskiob:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_l2c_spar4_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t umskiob:4;
-#else
-                uint64_t umskiob:4;
-                uint64_t reserved_4_63:60;
-#endif
         } cn30xx;
         struct cvmx_l2c_spar4_cn30xx cn31xx;
         struct cvmx_l2c_spar4_s cn38xx;
@@ -2575,7 +1291,6 @@ union cvmx_l2c_spar4 {
 union cvmx_l2c_tadx_ecc0 {
         uint64_t u64;
         struct cvmx_l2c_tadx_ecc0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_58_63:6;
                 uint64_t ow3ecc:10;
                 uint64_t reserved_42_47:6;
@@ -2584,30 +1299,14 @@ union cvmx_l2c_tadx_ecc0 {
                 uint64_t ow1ecc:10;
                 uint64_t reserved_10_15:6;
                 uint64_t ow0ecc:10;
-#else
-                uint64_t ow0ecc:10;
-                uint64_t reserved_10_15:6;
-                uint64_t ow1ecc:10;
-                uint64_t reserved_26_31:6;
-                uint64_t ow2ecc:10;
-                uint64_t reserved_42_47:6;
-                uint64_t ow3ecc:10;
-                uint64_t reserved_58_63:6;
-#endif
         } s;
-        struct cvmx_l2c_tadx_ecc0_s cn61xx;
         struct cvmx_l2c_tadx_ecc0_s cn63xx;
         struct cvmx_l2c_tadx_ecc0_s cn63xxp1;
-        struct cvmx_l2c_tadx_ecc0_s cn66xx;
-        struct cvmx_l2c_tadx_ecc0_s cn68xx;
-        struct cvmx_l2c_tadx_ecc0_s cn68xxp1;
-        struct cvmx_l2c_tadx_ecc0_s cnf71xx;
 };
 
 union cvmx_l2c_tadx_ecc1 {
         uint64_t u64;
         struct cvmx_l2c_tadx_ecc1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_58_63:6;
                 uint64_t ow7ecc:10;
                 uint64_t reserved_42_47:6;
@@ -2616,30 +1315,14 @@ union cvmx_l2c_tadx_ecc1 {
                 uint64_t ow5ecc:10;
                 uint64_t reserved_10_15:6;
                 uint64_t ow4ecc:10;
-#else
-                uint64_t ow4ecc:10;
-                uint64_t reserved_10_15:6;
-                uint64_t ow5ecc:10;
-                uint64_t reserved_26_31:6;
-                uint64_t ow6ecc:10;
-                uint64_t reserved_42_47:6;
-                uint64_t ow7ecc:10;
-                uint64_t reserved_58_63:6;
-#endif
         } s;
-        struct cvmx_l2c_tadx_ecc1_s cn61xx;
         struct cvmx_l2c_tadx_ecc1_s cn63xx;
         struct cvmx_l2c_tadx_ecc1_s cn63xxp1;
-        struct cvmx_l2c_tadx_ecc1_s cn66xx;
-        struct cvmx_l2c_tadx_ecc1_s cn68xx;
-        struct cvmx_l2c_tadx_ecc1_s cn68xxp1;
-        struct cvmx_l2c_tadx_ecc1_s cnf71xx;
 };
 
 union cvmx_l2c_tadx_ien {
         uint64_t u64;
         struct cvmx_l2c_tadx_ien_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t wrdislmc:1;
                 uint64_t rddislmc:1;
@@ -2650,23 +1333,9 @@ union cvmx_l2c_tadx_ien {
                 uint64_t tagsbe:1;
                 uint64_t l2ddbe:1;
                 uint64_t l2dsbe:1;
-#else
-                uint64_t l2dsbe:1;
-                uint64_t l2ddbe:1;
-                uint64_t tagsbe:1;
-                uint64_t tagdbe:1;
-                uint64_t vbfsbe:1;
-                uint64_t vbfdbe:1;
-                uint64_t noway:1;
-                uint64_t rddislmc:1;
-                uint64_t wrdislmc:1;
-                uint64_t reserved_9_63:55;
-#endif
         } s;
-        struct cvmx_l2c_tadx_ien_s cn61xx;
         struct cvmx_l2c_tadx_ien_s cn63xx;
         struct cvmx_l2c_tadx_ien_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t noway:1;
                 uint64_t vbfdbe:1;
@@ -2675,27 +1344,12 @@ union cvmx_l2c_tadx_ien {
                 uint64_t tagsbe:1;
                 uint64_t l2ddbe:1;
                 uint64_t l2dsbe:1;
-#else
-                uint64_t l2dsbe:1;
-                uint64_t l2ddbe:1;
-                uint64_t tagsbe:1;
-                uint64_t tagdbe:1;
-                uint64_t vbfsbe:1;
-                uint64_t vbfdbe:1;
-                uint64_t noway:1;
-                uint64_t reserved_7_63:57;
-#endif
         } cn63xxp1;
-        struct cvmx_l2c_tadx_ien_s cn66xx;
-        struct cvmx_l2c_tadx_ien_s cn68xx;
-        struct cvmx_l2c_tadx_ien_s cn68xxp1;
-        struct cvmx_l2c_tadx_ien_s cnf71xx;
 };
 
 union cvmx_l2c_tadx_int {
         uint64_t u64;
         struct cvmx_l2c_tadx_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t wrdislmc:1;
                 uint64_t rddislmc:1;
@@ -2706,129 +1360,62 @@ union cvmx_l2c_tadx_int {
                 uint64_t tagsbe:1;
                 uint64_t l2ddbe:1;
                 uint64_t l2dsbe:1;
-#else
-                uint64_t l2dsbe:1;
-                uint64_t l2ddbe:1;
-                uint64_t tagsbe:1;
-                uint64_t tagdbe:1;
-                uint64_t vbfsbe:1;
-                uint64_t vbfdbe:1;
-                uint64_t noway:1;
-                uint64_t rddislmc:1;
-                uint64_t wrdislmc:1;
-                uint64_t reserved_9_63:55;
-#endif
         } s;
-        struct cvmx_l2c_tadx_int_s cn61xx;
         struct cvmx_l2c_tadx_int_s cn63xx;
-        struct cvmx_l2c_tadx_int_s cn66xx;
-        struct cvmx_l2c_tadx_int_s cn68xx;
-        struct cvmx_l2c_tadx_int_s cn68xxp1;
-        struct cvmx_l2c_tadx_int_s cnf71xx;
 };
 
 union cvmx_l2c_tadx_pfc0 {
         uint64_t u64;
         struct cvmx_l2c_tadx_pfc0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t count:64;
-#else
-                uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_tadx_pfc0_s cn61xx;
         struct cvmx_l2c_tadx_pfc0_s cn63xx;
         struct cvmx_l2c_tadx_pfc0_s cn63xxp1;
-        struct cvmx_l2c_tadx_pfc0_s cn66xx;
-        struct cvmx_l2c_tadx_pfc0_s cn68xx;
-        struct cvmx_l2c_tadx_pfc0_s cn68xxp1;
-        struct cvmx_l2c_tadx_pfc0_s cnf71xx;
 };
 
 union cvmx_l2c_tadx_pfc1 {
         uint64_t u64;
         struct cvmx_l2c_tadx_pfc1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t count:64;
-#else
-                uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_tadx_pfc1_s cn61xx;
         struct cvmx_l2c_tadx_pfc1_s cn63xx;
         struct cvmx_l2c_tadx_pfc1_s cn63xxp1;
-        struct cvmx_l2c_tadx_pfc1_s cn66xx;
-        struct cvmx_l2c_tadx_pfc1_s cn68xx;
-        struct cvmx_l2c_tadx_pfc1_s cn68xxp1;
-        struct cvmx_l2c_tadx_pfc1_s cnf71xx;
 };
 
 union cvmx_l2c_tadx_pfc2 {
         uint64_t u64;
         struct cvmx_l2c_tadx_pfc2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t count:64;
-#else
-                uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_tadx_pfc2_s cn61xx;
         struct cvmx_l2c_tadx_pfc2_s cn63xx;
         struct cvmx_l2c_tadx_pfc2_s cn63xxp1;
-        struct cvmx_l2c_tadx_pfc2_s cn66xx;
-        struct cvmx_l2c_tadx_pfc2_s cn68xx;
-        struct cvmx_l2c_tadx_pfc2_s cn68xxp1;
-        struct cvmx_l2c_tadx_pfc2_s cnf71xx;
 };
 
 union cvmx_l2c_tadx_pfc3 {
         uint64_t u64;
         struct cvmx_l2c_tadx_pfc3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t count:64;
-#else
-                uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_tadx_pfc3_s cn61xx;
         struct cvmx_l2c_tadx_pfc3_s cn63xx;
         struct cvmx_l2c_tadx_pfc3_s cn63xxp1;
-        struct cvmx_l2c_tadx_pfc3_s cn66xx;
-        struct cvmx_l2c_tadx_pfc3_s cn68xx;
-        struct cvmx_l2c_tadx_pfc3_s cn68xxp1;
-        struct cvmx_l2c_tadx_pfc3_s cnf71xx;
 };
 
 union cvmx_l2c_tadx_prf {
         uint64_t u64;
         struct cvmx_l2c_tadx_prf_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t cnt3sel:8;
                 uint64_t cnt2sel:8;
                 uint64_t cnt1sel:8;
                 uint64_t cnt0sel:8;
-#else
-                uint64_t cnt0sel:8;
-                uint64_t cnt1sel:8;
-                uint64_t cnt2sel:8;
-                uint64_t cnt3sel:8;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
-        struct cvmx_l2c_tadx_prf_s cn61xx;
         struct cvmx_l2c_tadx_prf_s cn63xx;
         struct cvmx_l2c_tadx_prf_s cn63xxp1;
-        struct cvmx_l2c_tadx_prf_s cn66xx;
-        struct cvmx_l2c_tadx_prf_s cn68xx;
-        struct cvmx_l2c_tadx_prf_s cn68xxp1;
-        struct cvmx_l2c_tadx_prf_s cnf71xx;
 };
 
 union cvmx_l2c_tadx_tag {
         uint64_t u64;
         struct cvmx_l2c_tadx_tag_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_46_63:18;
                 uint64_t ecc:6;
                 uint64_t reserved_36_39:4;
@@ -2838,330 +1425,145 @@ union cvmx_l2c_tadx_tag {
                 uint64_t valid:1;
                 uint64_t dirty:1;
                 uint64_t lock:1;
-#else
-                uint64_t lock:1;
-                uint64_t dirty:1;
-                uint64_t valid:1;
-                uint64_t use:1;
-                uint64_t reserved_4_16:13;
-                uint64_t tag:19;
-                uint64_t reserved_36_39:4;
-                uint64_t ecc:6;
-                uint64_t reserved_46_63:18;
-#endif
         } s;
-        struct cvmx_l2c_tadx_tag_s cn61xx;
         struct cvmx_l2c_tadx_tag_s cn63xx;
         struct cvmx_l2c_tadx_tag_s cn63xxp1;
-        struct cvmx_l2c_tadx_tag_s cn66xx;
-        struct cvmx_l2c_tadx_tag_s cn68xx;
-        struct cvmx_l2c_tadx_tag_s cn68xxp1;
-        struct cvmx_l2c_tadx_tag_s cnf71xx;
 };
 
 union cvmx_l2c_ver_id {
         uint64_t u64;
         struct cvmx_l2c_ver_id_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t mask:64;
-#else
-                uint64_t mask:64;
-#endif
         } s;
-        struct cvmx_l2c_ver_id_s cn61xx;
         struct cvmx_l2c_ver_id_s cn63xx;
         struct cvmx_l2c_ver_id_s cn63xxp1;
-        struct cvmx_l2c_ver_id_s cn66xx;
-        struct cvmx_l2c_ver_id_s cn68xx;
-        struct cvmx_l2c_ver_id_s cn68xxp1;
-        struct cvmx_l2c_ver_id_s cnf71xx;
 };
 
 union cvmx_l2c_ver_iob {
         uint64_t u64;
         struct cvmx_l2c_ver_iob_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t mask:2;
-#else
-                uint64_t mask:2;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_l2c_ver_iob_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t mask:1;
-#else
-                uint64_t mask:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_ver_iob_cn61xx cn63xx;
-        struct cvmx_l2c_ver_iob_cn61xx cn63xxp1;
-        struct cvmx_l2c_ver_iob_cn61xx cn66xx;
-        struct cvmx_l2c_ver_iob_s cn68xx;
-        struct cvmx_l2c_ver_iob_s cn68xxp1;
-        struct cvmx_l2c_ver_iob_cn61xx cnf71xx;
+        } s;
+        struct cvmx_l2c_ver_iob_s cn63xx;
+        struct cvmx_l2c_ver_iob_s cn63xxp1;
 };
 
 union cvmx_l2c_ver_msc {
         uint64_t u64;
         struct cvmx_l2c_ver_msc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t invl2:1;
                 uint64_t dwb:1;
-#else
-                uint64_t dwb:1;
-                uint64_t invl2:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
-        struct cvmx_l2c_ver_msc_s cn61xx;
         struct cvmx_l2c_ver_msc_s cn63xx;
-        struct cvmx_l2c_ver_msc_s cn66xx;
-        struct cvmx_l2c_ver_msc_s cn68xx;
-        struct cvmx_l2c_ver_msc_s cn68xxp1;
-        struct cvmx_l2c_ver_msc_s cnf71xx;
 };
 
 union cvmx_l2c_ver_pp {
         uint64_t u64;
         struct cvmx_l2c_ver_pp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t mask:32;
-#else
-                uint64_t mask:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_l2c_ver_pp_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t mask:4;
-#else
-                uint64_t mask:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } cn61xx;
-        struct cvmx_l2c_ver_pp_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t mask:6;
-#else
-                uint64_t mask:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } cn63xx;
-        struct cvmx_l2c_ver_pp_cn63xx cn63xxp1;
-        struct cvmx_l2c_ver_pp_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t mask:10;
-#else
-                uint64_t mask:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn66xx;
-        struct cvmx_l2c_ver_pp_s cn68xx;
-        struct cvmx_l2c_ver_pp_s cn68xxp1;
-        struct cvmx_l2c_ver_pp_cn61xx cnf71xx;
+        } s;
+        struct cvmx_l2c_ver_pp_s cn63xx;
+        struct cvmx_l2c_ver_pp_s cn63xxp1;
 };
 
 union cvmx_l2c_virtid_iobx {
         uint64_t u64;
         struct cvmx_l2c_virtid_iobx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t dwbid:6;
                 uint64_t reserved_6_7:2;
                 uint64_t id:6;
-#else
-                uint64_t id:6;
-                uint64_t reserved_6_7:2;
-                uint64_t dwbid:6;
-                uint64_t reserved_14_63:50;
-#endif
         } s;
-        struct cvmx_l2c_virtid_iobx_s cn61xx;
         struct cvmx_l2c_virtid_iobx_s cn63xx;
         struct cvmx_l2c_virtid_iobx_s cn63xxp1;
-        struct cvmx_l2c_virtid_iobx_s cn66xx;
-        struct cvmx_l2c_virtid_iobx_s cn68xx;
-        struct cvmx_l2c_virtid_iobx_s cn68xxp1;
-        struct cvmx_l2c_virtid_iobx_s cnf71xx;
 };
 
 union cvmx_l2c_virtid_ppx {
         uint64_t u64;
         struct cvmx_l2c_virtid_ppx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t id:6;
-#else
-                uint64_t id:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
-        struct cvmx_l2c_virtid_ppx_s cn61xx;
         struct cvmx_l2c_virtid_ppx_s cn63xx;
         struct cvmx_l2c_virtid_ppx_s cn63xxp1;
-        struct cvmx_l2c_virtid_ppx_s cn66xx;
-        struct cvmx_l2c_virtid_ppx_s cn68xx;
-        struct cvmx_l2c_virtid_ppx_s cn68xxp1;
-        struct cvmx_l2c_virtid_ppx_s cnf71xx;
 };
 
 union cvmx_l2c_vrt_ctl {
         uint64_t u64;
         struct cvmx_l2c_vrt_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t ooberr:1;
                 uint64_t reserved_7_7:1;
                 uint64_t memsz:3;
                 uint64_t numid:3;
                 uint64_t enable:1;
-#else
-                uint64_t enable:1;
-                uint64_t numid:3;
-                uint64_t memsz:3;
-                uint64_t reserved_7_7:1;
-                uint64_t ooberr:1;
-                uint64_t reserved_9_63:55;
-#endif
         } s;
-        struct cvmx_l2c_vrt_ctl_s cn61xx;
         struct cvmx_l2c_vrt_ctl_s cn63xx;
         struct cvmx_l2c_vrt_ctl_s cn63xxp1;
-        struct cvmx_l2c_vrt_ctl_s cn66xx;
-        struct cvmx_l2c_vrt_ctl_s cn68xx;
-        struct cvmx_l2c_vrt_ctl_s cn68xxp1;
-        struct cvmx_l2c_vrt_ctl_s cnf71xx;
 };
 
 union cvmx_l2c_vrt_memx {
         uint64_t u64;
         struct cvmx_l2c_vrt_memx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t parity:4;
                 uint64_t data:32;
-#else
-                uint64_t data:32;
-                uint64_t parity:4;
-                uint64_t reserved_36_63:28;
-#endif
         } s;
-        struct cvmx_l2c_vrt_memx_s cn61xx;
         struct cvmx_l2c_vrt_memx_s cn63xx;
         struct cvmx_l2c_vrt_memx_s cn63xxp1;
-        struct cvmx_l2c_vrt_memx_s cn66xx;
-        struct cvmx_l2c_vrt_memx_s cn68xx;
-        struct cvmx_l2c_vrt_memx_s cn68xxp1;
-        struct cvmx_l2c_vrt_memx_s cnf71xx;
 };
 
 union cvmx_l2c_wpar_iobx {
         uint64_t u64;
         struct cvmx_l2c_wpar_iobx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t mask:16;
-#else
-                uint64_t mask:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
-        struct cvmx_l2c_wpar_iobx_s cn61xx;
         struct cvmx_l2c_wpar_iobx_s cn63xx;
         struct cvmx_l2c_wpar_iobx_s cn63xxp1;
-        struct cvmx_l2c_wpar_iobx_s cn66xx;
-        struct cvmx_l2c_wpar_iobx_s cn68xx;
-        struct cvmx_l2c_wpar_iobx_s cn68xxp1;
-        struct cvmx_l2c_wpar_iobx_s cnf71xx;
 };
 
 union cvmx_l2c_wpar_ppx {
         uint64_t u64;
         struct cvmx_l2c_wpar_ppx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t mask:16;
-#else
-                uint64_t mask:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
-        struct cvmx_l2c_wpar_ppx_s cn61xx;
         struct cvmx_l2c_wpar_ppx_s cn63xx;
         struct cvmx_l2c_wpar_ppx_s cn63xxp1;
-        struct cvmx_l2c_wpar_ppx_s cn66xx;
-        struct cvmx_l2c_wpar_ppx_s cn68xx;
-        struct cvmx_l2c_wpar_ppx_s cn68xxp1;
-        struct cvmx_l2c_wpar_ppx_s cnf71xx;
 };
 
 union cvmx_l2c_xmcx_pfc {
         uint64_t u64;
         struct cvmx_l2c_xmcx_pfc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t count:64;
-#else
                 uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_xmcx_pfc_s cn61xx;
         struct cvmx_l2c_xmcx_pfc_s cn63xx;
         struct cvmx_l2c_xmcx_pfc_s cn63xxp1;
-        struct cvmx_l2c_xmcx_pfc_s cn66xx;
-        struct cvmx_l2c_xmcx_pfc_s cn68xx;
-        struct cvmx_l2c_xmcx_pfc_s cn68xxp1;
-        struct cvmx_l2c_xmcx_pfc_s cnf71xx;
 };
 
 union cvmx_l2c_xmc_cmd {
         uint64_t u64;
         struct cvmx_l2c_xmc_cmd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t inuse:1;
                 uint64_t cmd:6;
                 uint64_t reserved_38_56:19;
                 uint64_t addr:38;
-#else
-                uint64_t addr:38;
-                uint64_t reserved_38_56:19;
-                uint64_t cmd:6;
-                uint64_t inuse:1;
-#endif
         } s;
-        struct cvmx_l2c_xmc_cmd_s cn61xx;
         struct cvmx_l2c_xmc_cmd_s cn63xx;
         struct cvmx_l2c_xmc_cmd_s cn63xxp1;
-        struct cvmx_l2c_xmc_cmd_s cn66xx;
-        struct cvmx_l2c_xmc_cmd_s cn68xx;
-        struct cvmx_l2c_xmc_cmd_s cn68xxp1;
-        struct cvmx_l2c_xmc_cmd_s cnf71xx;
 };
 
 union cvmx_l2c_xmdx_pfc {
         uint64_t u64;
         struct cvmx_l2c_xmdx_pfc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t count:64;
-#else
-                uint64_t count:64;
-#endif
         } s;
-        struct cvmx_l2c_xmdx_pfc_s cn61xx;
         struct cvmx_l2c_xmdx_pfc_s cn63xx;
         struct cvmx_l2c_xmdx_pfc_s cn63xxp1;
-        struct cvmx_l2c_xmdx_pfc_s cn66xx;
-        struct cvmx_l2c_xmdx_pfc_s cn68xx;
-        struct cvmx_l2c_xmdx_pfc_s cn68xxp1;
-        struct cvmx_l2c_xmdx_pfc_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
index 11a45621563..60543e0e77f 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -44,15 +44,9 @@
 union cvmx_l2d_bst0 {
         uint64_t u64;
         struct cvmx_l2d_bst0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_35_63:29;
                 uint64_t ftl:1;
                 uint64_t q0stat:34;
-#else
-                uint64_t q0stat:34;
-                uint64_t ftl:1;
-                uint64_t reserved_35_63:29;
-#endif
         } s;
         struct cvmx_l2d_bst0_s cn30xx;
         struct cvmx_l2d_bst0_s cn31xx;
@@ -70,13 +64,8 @@ union cvmx_l2d_bst0 {
 union cvmx_l2d_bst1 {
         uint64_t u64;
         struct cvmx_l2d_bst1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t q1stat:34;
-#else
-                uint64_t q1stat:34;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_l2d_bst1_s cn30xx;
         struct cvmx_l2d_bst1_s cn31xx;
@@ -94,13 +83,8 @@ union cvmx_l2d_bst1 {
 union cvmx_l2d_bst2 {
         uint64_t u64;
         struct cvmx_l2d_bst2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t q2stat:34;
-#else
-                uint64_t q2stat:34;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_l2d_bst2_s cn30xx;
         struct cvmx_l2d_bst2_s cn31xx;
@@ -118,13 +102,8 @@ union cvmx_l2d_bst2 {
 union cvmx_l2d_bst3 {
         uint64_t u64;
         struct cvmx_l2d_bst3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t q3stat:34;
-#else
-                uint64_t q3stat:34;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_l2d_bst3_s cn30xx;
         struct cvmx_l2d_bst3_s cn31xx;
@@ -142,7 +121,6 @@ union cvmx_l2d_bst3 {
 union cvmx_l2d_err {
         uint64_t u64;
         struct cvmx_l2d_err_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t bmhclsel:1;
                 uint64_t ded_err:1;
@@ -150,15 +128,6 @@ union cvmx_l2d_err {
                 uint64_t ded_intena:1;
                 uint64_t sec_intena:1;
                 uint64_t ecc_ena:1;
-#else
-                uint64_t ecc_ena:1;
-                uint64_t sec_intena:1;
-                uint64_t ded_intena:1;
-                uint64_t sec_err:1;
-                uint64_t ded_err:1;
-                uint64_t bmhclsel:1;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_l2d_err_s cn30xx;
         struct cvmx_l2d_err_s cn31xx;
@@ -176,97 +145,48 @@ union cvmx_l2d_err {
 union cvmx_l2d_fadr {
         uint64_t u64;
         struct cvmx_l2d_fadr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t fadru:1;
                 uint64_t fowmsk:4;
                 uint64_t fset:3;
                 uint64_t fadr:11;
-#else
-                uint64_t fadr:11;
-                uint64_t fset:3;
-                uint64_t fowmsk:4;
-                uint64_t fadru:1;
-                uint64_t reserved_19_63:45;
-#endif
         } s;
         struct cvmx_l2d_fadr_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t fowmsk:4;
                 uint64_t reserved_13_13:1;
                 uint64_t fset:2;
                 uint64_t reserved_9_10:2;
                 uint64_t fadr:9;
-#else
-                uint64_t fadr:9;
-                uint64_t reserved_9_10:2;
-                uint64_t fset:2;
-                uint64_t reserved_13_13:1;
-                uint64_t fowmsk:4;
-                uint64_t reserved_18_63:46;
-#endif
         } cn30xx;
         struct cvmx_l2d_fadr_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t fowmsk:4;
                 uint64_t reserved_13_13:1;
                 uint64_t fset:2;
                 uint64_t reserved_10_10:1;
                 uint64_t fadr:10;
-#else
-                uint64_t fadr:10;
-                uint64_t reserved_10_10:1;
-                uint64_t fset:2;
-                uint64_t reserved_13_13:1;
-                uint64_t fowmsk:4;
-                uint64_t reserved_18_63:46;
-#endif
         } cn31xx;
         struct cvmx_l2d_fadr_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t fowmsk:4;
                 uint64_t fset:3;
                 uint64_t fadr:11;
-#else
-                uint64_t fadr:11;
-                uint64_t fset:3;
-                uint64_t fowmsk:4;
-                uint64_t reserved_18_63:46;
-#endif
         } cn38xx;
         struct cvmx_l2d_fadr_cn38xx cn38xxp2;
         struct cvmx_l2d_fadr_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t fowmsk:4;
                 uint64_t fset:3;
                 uint64_t reserved_8_10:3;
                 uint64_t fadr:8;
-#else
-                uint64_t fadr:8;
-                uint64_t reserved_8_10:3;
-                uint64_t fset:3;
-                uint64_t fowmsk:4;
-                uint64_t reserved_18_63:46;
-#endif
         } cn50xx;
         struct cvmx_l2d_fadr_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t fowmsk:4;
                 uint64_t fset:3;
                 uint64_t reserved_10_10:1;
                 uint64_t fadr:10;
-#else
-                uint64_t fadr:10;
-                uint64_t reserved_10_10:1;
-                uint64_t fset:3;
-                uint64_t fowmsk:4;
-                uint64_t reserved_18_63:46;
-#endif
         } cn52xx;
         struct cvmx_l2d_fadr_cn52xx cn52xxp1;
         struct cvmx_l2d_fadr_s cn56xx;
@@ -278,15 +198,9 @@ union cvmx_l2d_fadr {
 union cvmx_l2d_fsyn0 {
         uint64_t u64;
         struct cvmx_l2d_fsyn0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t fsyn_ow1:10;
                 uint64_t fsyn_ow0:10;
-#else
-                uint64_t fsyn_ow0:10;
-                uint64_t fsyn_ow1:10;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
         struct cvmx_l2d_fsyn0_s cn30xx;
         struct cvmx_l2d_fsyn0_s cn31xx;
@@ -304,15 +218,9 @@ union cvmx_l2d_fsyn0 {
 union cvmx_l2d_fsyn1 {
         uint64_t u64;
         struct cvmx_l2d_fsyn1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t fsyn_ow3:10;
                 uint64_t fsyn_ow2:10;
-#else
-                uint64_t fsyn_ow2:10;
-                uint64_t fsyn_ow3:10;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
         struct cvmx_l2d_fsyn1_s cn30xx;
         struct cvmx_l2d_fsyn1_s cn31xx;
@@ -330,13 +238,8 @@ union cvmx_l2d_fsyn1 {
 union cvmx_l2d_fus0 {
         uint64_t u64;
         struct cvmx_l2d_fus0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t q0fus:34;
-#else
-                uint64_t q0fus:34;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_l2d_fus0_s cn30xx;
         struct cvmx_l2d_fus0_s cn31xx;
@@ -354,13 +257,8 @@ union cvmx_l2d_fus0 {
 union cvmx_l2d_fus1 {
         uint64_t u64;
         struct cvmx_l2d_fus1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t q1fus:34;
-#else
-                uint64_t q1fus:34;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_l2d_fus1_s cn30xx;
         struct cvmx_l2d_fus1_s cn31xx;
@@ -378,13 +276,8 @@ union cvmx_l2d_fus1 {
 union cvmx_l2d_fus2 {
         uint64_t u64;
         struct cvmx_l2d_fus2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t q2fus:34;
-#else
-                uint64_t q2fus:34;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_l2d_fus2_s cn30xx;
         struct cvmx_l2d_fus2_s cn31xx;
@@ -402,123 +295,61 @@ union cvmx_l2d_fus2 {
 union cvmx_l2d_fus3 {
         uint64_t u64;
         struct cvmx_l2d_fus3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t ema_ctl:3;
                 uint64_t reserved_34_36:3;
                 uint64_t q3fus:34;
-#else
-                uint64_t q3fus:34;
-                uint64_t reserved_34_36:3;
-                uint64_t ema_ctl:3;
-                uint64_t reserved_40_63:24;
-#endif
         } s;
         struct cvmx_l2d_fus3_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_35_63:29;
                 uint64_t crip_64k:1;
                 uint64_t q3fus:34;
-#else
-                uint64_t q3fus:34;
-                uint64_t crip_64k:1;
-                uint64_t reserved_35_63:29;
-#endif
         } cn30xx;
         struct cvmx_l2d_fus3_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_35_63:29;
                 uint64_t crip_128k:1;
                 uint64_t q3fus:34;
-#else
-                uint64_t q3fus:34;
-                uint64_t crip_128k:1;
-                uint64_t reserved_35_63:29;
-#endif
         } cn31xx;
         struct cvmx_l2d_fus3_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t crip_256k:1;
                 uint64_t crip_512k:1;
                 uint64_t q3fus:34;
-#else
-                uint64_t q3fus:34;
-                uint64_t crip_512k:1;
-                uint64_t crip_256k:1;
-                uint64_t reserved_36_63:28;
-#endif
         } cn38xx;
         struct cvmx_l2d_fus3_cn38xx cn38xxp2;
         struct cvmx_l2d_fus3_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t ema_ctl:3;
                 uint64_t reserved_36_36:1;
                 uint64_t crip_32k:1;
                 uint64_t crip_64k:1;
                 uint64_t q3fus:34;
-#else
-                uint64_t q3fus:34;
-                uint64_t crip_64k:1;
-                uint64_t crip_32k:1;
-                uint64_t reserved_36_36:1;
-                uint64_t ema_ctl:3;
-                uint64_t reserved_40_63:24;
-#endif
         } cn50xx;
         struct cvmx_l2d_fus3_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t ema_ctl:3;
                 uint64_t reserved_36_36:1;
                 uint64_t crip_128k:1;
                 uint64_t crip_256k:1;
                 uint64_t q3fus:34;
-#else
-                uint64_t q3fus:34;
-                uint64_t crip_256k:1;
-                uint64_t crip_128k:1;
-                uint64_t reserved_36_36:1;
-                uint64_t ema_ctl:3;
-                uint64_t reserved_40_63:24;
-#endif
         } cn52xx;
         struct cvmx_l2d_fus3_cn52xx cn52xxp1;
         struct cvmx_l2d_fus3_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t ema_ctl:3;
                 uint64_t reserved_36_36:1;
                 uint64_t crip_512k:1;
                 uint64_t crip_1024k:1;
                 uint64_t q3fus:34;
-#else
-                uint64_t q3fus:34;
-                uint64_t crip_1024k:1;
-                uint64_t crip_512k:1;
-                uint64_t reserved_36_36:1;
-                uint64_t ema_ctl:3;
-                uint64_t reserved_40_63:24;
-#endif
         } cn56xx;
         struct cvmx_l2d_fus3_cn56xx cn56xxp1;
         struct cvmx_l2d_fus3_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_39_63:25;
                 uint64_t ema_ctl:2;
                 uint64_t reserved_36_36:1;
                 uint64_t crip_512k:1;
                 uint64_t crip_1024k:1;
                 uint64_t q3fus:34;
-#else
-                uint64_t q3fus:34;
-                uint64_t crip_1024k:1;
-                uint64_t crip_512k:1;
-                uint64_t reserved_36_36:1;
-                uint64_t ema_ctl:2;
-                uint64_t reserved_39_63:25;
-#endif
         } cn58xx;
         struct cvmx_l2d_fus3_cn58xx cn58xxp1;
 };
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
index 83ce22c080e..873968f55ee 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -33,7 +33,6 @@
 union cvmx_l2t_err {
         uint64_t u64;
         struct cvmx_l2t_err_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t fadru:1;
                 uint64_t lck_intena2:1;
@@ -48,25 +47,8 @@ union cvmx_l2t_err {
                 uint64_t ded_intena:1;
                 uint64_t sec_intena:1;
                 uint64_t ecc_ena:1;
-#else
-                uint64_t ecc_ena:1;
-                uint64_t sec_intena:1;
-                uint64_t ded_intena:1;
-                uint64_t sec_err:1;
-                uint64_t ded_err:1;
-                uint64_t fsyn:6;
-                uint64_t fadr:10;
-                uint64_t fset:3;
-                uint64_t lckerr:1;
-                uint64_t lck_intena:1;
-                uint64_t lckerr2:1;
-                uint64_t lck_intena2:1;
-                uint64_t fadru:1;
-                uint64_t reserved_29_63:35;
-#endif
         } s;
         struct cvmx_l2t_err_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t lck_intena2:1;
                 uint64_t lckerr2:1;
@@ -82,26 +64,8 @@ union cvmx_l2t_err {
                 uint64_t ded_intena:1;
                 uint64_t sec_intena:1;
                 uint64_t ecc_ena:1;
-#else
-                uint64_t ecc_ena:1;
-                uint64_t sec_intena:1;
-                uint64_t ded_intena:1;
-                uint64_t sec_err:1;
-                uint64_t ded_err:1;
-                uint64_t fsyn:6;
-                uint64_t fadr:8;
-                uint64_t reserved_19_20:2;
-                uint64_t fset:2;
-                uint64_t reserved_23_23:1;
-                uint64_t lckerr:1;
-                uint64_t lck_intena:1;
-                uint64_t lckerr2:1;
-                uint64_t lck_intena2:1;
-                uint64_t reserved_28_63:36;
-#endif
         } cn30xx;
         struct cvmx_l2t_err_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t lck_intena2:1;
                 uint64_t lckerr2:1;
@@ -117,26 +81,8 @@ union cvmx_l2t_err {
                 uint64_t ded_intena:1;
                 uint64_t sec_intena:1;
                 uint64_t ecc_ena:1;
-#else
-                uint64_t ecc_ena:1;
-                uint64_t sec_intena:1;
-                uint64_t ded_intena:1;
-                uint64_t sec_err:1;
-                uint64_t ded_err:1;
-                uint64_t fsyn:6;
-                uint64_t fadr:9;
-                uint64_t reserved_20_20:1;
-                uint64_t fset:2;
-                uint64_t reserved_23_23:1;
-                uint64_t lckerr:1;
-                uint64_t lck_intena:1;
-                uint64_t lckerr2:1;
-                uint64_t lck_intena2:1;
-                uint64_t reserved_28_63:36;
-#endif
         } cn31xx;
         struct cvmx_l2t_err_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t lck_intena2:1;
                 uint64_t lckerr2:1;
@@ -150,25 +96,9 @@ union cvmx_l2t_err {
                 uint64_t ded_intena:1;
                 uint64_t sec_intena:1;
                 uint64_t ecc_ena:1;
-#else
-                uint64_t ecc_ena:1;
-                uint64_t sec_intena:1;
-                uint64_t ded_intena:1;
-                uint64_t sec_err:1;
-                uint64_t ded_err:1;
-                uint64_t fsyn:6;
-                uint64_t fadr:10;
-                uint64_t fset:3;
-                uint64_t lckerr:1;
-                uint64_t lck_intena:1;
-                uint64_t lckerr2:1;
-                uint64_t lck_intena2:1;
-                uint64_t reserved_28_63:36;
-#endif
         } cn38xx;
         struct cvmx_l2t_err_cn38xx cn38xxp2;
         struct cvmx_l2t_err_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t lck_intena2:1;
                 uint64_t lckerr2:1;
@@ -183,25 +113,8 @@ union cvmx_l2t_err {
                 uint64_t ded_intena:1;
                 uint64_t sec_intena:1;
                 uint64_t ecc_ena:1;
-#else
-                uint64_t ecc_ena:1;
-                uint64_t sec_intena:1;
-                uint64_t ded_intena:1;
-                uint64_t sec_err:1;
-                uint64_t ded_err:1;
-                uint64_t fsyn:6;
-                uint64_t fadr:7;
-                uint64_t reserved_18_20:3;
-                uint64_t fset:3;
-                uint64_t lckerr:1;
-                uint64_t lck_intena:1;
-                uint64_t lckerr2:1;
-                uint64_t lck_intena2:1;
-                uint64_t reserved_28_63:36;
-#endif
         } cn50xx;
         struct cvmx_l2t_err_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t lck_intena2:1;
                 uint64_t lckerr2:1;
@@ -216,22 +129,6 @@ union cvmx_l2t_err {
                 uint64_t ded_intena:1;
                 uint64_t sec_intena:1;
                 uint64_t ecc_ena:1;
-#else
-                uint64_t ecc_ena:1;
-                uint64_t sec_intena:1;
-                uint64_t ded_intena:1;
-                uint64_t sec_err:1;
-                uint64_t ded_err:1;
-                uint64_t fsyn:6;
-                uint64_t fadr:9;
-                uint64_t reserved_20_20:1;
-                uint64_t fset:3;
-                uint64_t lckerr:1;
-                uint64_t lck_intena:1;
-                uint64_t lckerr2:1;
-                uint64_t lck_intena2:1;
-                uint64_t reserved_28_63:36;
-#endif
         } cn52xx;
         struct cvmx_l2t_err_cn52xx cn52xxp1;
         struct cvmx_l2t_err_s cn56xx;
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h
index d36d42b8307..e25173bb8bb 100644
--- a/arch/mips/include/asm/octeon/cvmx-led-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -45,13 +45,8 @@
 union cvmx_led_blink {
         uint64_t u64;
         struct cvmx_led_blink_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t rate:8;
-#else
-                uint64_t rate:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_led_blink_s cn38xx;
         struct cvmx_led_blink_s cn38xxp2;
@@ -64,13 +59,8 @@ union cvmx_led_blink {
 union cvmx_led_clk_phase {
         uint64_t u64;
         struct cvmx_led_clk_phase_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t phase:7;
-#else
-                uint64_t phase:7;
-                uint64_t reserved_7_63:57;
-#endif
         } s;
         struct cvmx_led_clk_phase_s cn38xx;
         struct cvmx_led_clk_phase_s cn38xxp2;
@@ -83,13 +73,8 @@ union cvmx_led_clk_phase {
 union cvmx_led_cylon {
         uint64_t u64;
         struct cvmx_led_cylon_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t rate:16;
-#else
-                uint64_t rate:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_led_cylon_s cn38xx;
         struct cvmx_led_cylon_s cn38xxp2;
@@ -102,13 +87,8 @@ union cvmx_led_cylon {
 union cvmx_led_dbg {
         uint64_t u64;
         struct cvmx_led_dbg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t dbg_en:1;
-#else
-                uint64_t dbg_en:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_led_dbg_s cn38xx;
         struct cvmx_led_dbg_s cn38xxp2;
@@ -121,13 +101,8 @@ union cvmx_led_dbg {
 union cvmx_led_en {
         uint64_t u64;
         struct cvmx_led_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_led_en_s cn38xx;
         struct cvmx_led_en_s cn38xxp2;
@@ -140,13 +115,8 @@ union cvmx_led_en {
 union cvmx_led_polarity {
         uint64_t u64;
         struct cvmx_led_polarity_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t polarity:1;
-#else
-                uint64_t polarity:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_led_polarity_s cn38xx;
         struct cvmx_led_polarity_s cn38xxp2;
@@ -159,13 +129,8 @@ union cvmx_led_polarity {
 union cvmx_led_prt {
         uint64_t u64;
         struct cvmx_led_prt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t prt_en:8;
-#else
-                uint64_t prt_en:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_led_prt_s cn38xx;
         struct cvmx_led_prt_s cn38xxp2;
@@ -178,13 +143,8 @@ union cvmx_led_prt {
 union cvmx_led_prt_fmt {
         uint64_t u64;
         struct cvmx_led_prt_fmt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t format:4;
-#else
-                uint64_t format:4;
-                uint64_t reserved_4_63:60;
-#endif
         } s;
         struct cvmx_led_prt_fmt_s cn38xx;
         struct cvmx_led_prt_fmt_s cn38xxp2;
@@ -197,13 +157,8 @@ union cvmx_led_prt_fmt {
 union cvmx_led_prt_statusx {
         uint64_t u64;
         struct cvmx_led_prt_statusx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t status:6;
-#else
-                uint64_t status:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_led_prt_statusx_s cn38xx;
         struct cvmx_led_prt_statusx_s cn38xxp2;
@@ -216,13 +171,8 @@ union cvmx_led_prt_statusx {
 union cvmx_led_udd_cntx {
         uint64_t u64;
         struct cvmx_led_udd_cntx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t cnt:6;
-#else
-                uint64_t cnt:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_led_udd_cntx_s cn38xx;
         struct cvmx_led_udd_cntx_s cn38xxp2;
@@ -235,13 +185,8 @@ union cvmx_led_udd_cntx {
 union cvmx_led_udd_datx {
         uint64_t u64;
         struct cvmx_led_udd_datx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t dat:32;
-#else
-                uint64_t dat:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_led_udd_datx_s cn38xx;
         struct cvmx_led_udd_datx_s cn38xxp2;
@@ -254,13 +199,8 @@ union cvmx_led_udd_datx {
 union cvmx_led_udd_dat_clrx {
         uint64_t u64;
         struct cvmx_led_udd_dat_clrx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t clr:32;
-#else
-                uint64_t clr:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_led_udd_dat_clrx_s cn38xx;
         struct cvmx_led_udd_dat_clrx_s cn38xxp2;
@@ -273,13 +213,8 @@ union cvmx_led_udd_dat_clrx {
 union cvmx_led_udd_dat_setx {
         uint64_t u64;
         struct cvmx_led_udd_dat_setx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t set:32;
-#else
-                uint64_t set:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_led_udd_dat_setx_s cn38xx;
         struct cvmx_led_udd_dat_setx_s cn38xxp2;
diff --git a/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
deleted file mode 100644
index 36f51072114..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
+++ /dev/null
@@ -1,3457 +0,0 @@
-/***********************license start***************
- * Author: Cavium Inc.
- *
- * Contact: support@cavium.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Inc.
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Inc. for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_LMCX_DEFS_H__
-#define __CVMX_LMCX_DEFS_H__
-
-#define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
-#define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull)
-static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull;
-}
-
-static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull;
-}
-
-#define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull)
-static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull;
-}
-
-#define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull))
-#define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8)
-#define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
-#define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull))
-#define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull))
-#define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull))
-#define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
-#define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull)
-#define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull)
-
-union cvmx_lmcx_bist_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_bist_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t start:1;
-#else
-                uint64_t start:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_lmcx_bist_ctl_s cn50xx;
-        struct cvmx_lmcx_bist_ctl_s cn52xx;
-        struct cvmx_lmcx_bist_ctl_s cn52xxp1;
-        struct cvmx_lmcx_bist_ctl_s cn56xx;
-        struct cvmx_lmcx_bist_ctl_s cn56xxp1;
-};
-
-union cvmx_lmcx_bist_result {
-        uint64_t u64;
-        struct cvmx_lmcx_bist_result_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t csrd2e:1;
-                uint64_t csre2d:1;
-                uint64_t mwf:1;
-                uint64_t mwd:3;
-                uint64_t mwc:1;
-                uint64_t mrf:1;
-                uint64_t mrd:3;
-#else
-                uint64_t mrd:3;
-                uint64_t mrf:1;
-                uint64_t mwc:1;
-                uint64_t mwd:3;
-                uint64_t mwf:1;
-                uint64_t csre2d:1;
-                uint64_t csrd2e:1;
-                uint64_t reserved_11_63:53;
-#endif
-        } s;
-        struct cvmx_lmcx_bist_result_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t mwf:1;
-                uint64_t mwd:3;
-                uint64_t mwc:1;
-                uint64_t mrf:1;
-                uint64_t mrd:3;
-#else
-                uint64_t mrd:3;
-                uint64_t mrf:1;
-                uint64_t mwc:1;
-                uint64_t mwd:3;
-                uint64_t mwf:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn50xx;
-        struct cvmx_lmcx_bist_result_s cn52xx;
-        struct cvmx_lmcx_bist_result_s cn52xxp1;
-        struct cvmx_lmcx_bist_result_s cn56xx;
-        struct cvmx_lmcx_bist_result_s cn56xxp1;
-};
-
-union cvmx_lmcx_char_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_char_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t dr:1;
-                uint64_t skew_on:1;
-                uint64_t en:1;
-                uint64_t sel:1;
-                uint64_t prog:8;
-                uint64_t prbs:32;
-#else
-                uint64_t prbs:32;
-                uint64_t prog:8;
-                uint64_t sel:1;
-                uint64_t en:1;
-                uint64_t skew_on:1;
-                uint64_t dr:1;
-                uint64_t reserved_44_63:20;
-#endif
-        } s;
-        struct cvmx_lmcx_char_ctl_s cn61xx;
-        struct cvmx_lmcx_char_ctl_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_42_63:22;
-                uint64_t en:1;
-                uint64_t sel:1;
-                uint64_t prog:8;
-                uint64_t prbs:32;
-#else
-                uint64_t prbs:32;
-                uint64_t prog:8;
-                uint64_t sel:1;
-                uint64_t en:1;
-                uint64_t reserved_42_63:22;
-#endif
-        } cn63xx;
-        struct cvmx_lmcx_char_ctl_cn63xx cn63xxp1;
-        struct cvmx_lmcx_char_ctl_s cn66xx;
-        struct cvmx_lmcx_char_ctl_s cn68xx;
-        struct cvmx_lmcx_char_ctl_cn63xx cn68xxp1;
-        struct cvmx_lmcx_char_ctl_s cnf71xx;
-};
-
-union cvmx_lmcx_char_mask0 {
-        uint64_t u64;
-        struct cvmx_lmcx_char_mask0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t mask:64;
-#else
-                uint64_t mask:64;
-#endif
-        } s;
-        struct cvmx_lmcx_char_mask0_s cn61xx;
-        struct cvmx_lmcx_char_mask0_s cn63xx;
-        struct cvmx_lmcx_char_mask0_s cn63xxp1;
-        struct cvmx_lmcx_char_mask0_s cn66xx;
-        struct cvmx_lmcx_char_mask0_s cn68xx;
-        struct cvmx_lmcx_char_mask0_s cn68xxp1;
-        struct cvmx_lmcx_char_mask0_s cnf71xx;
-};
-
-union cvmx_lmcx_char_mask1 {
-        uint64_t u64;
-        struct cvmx_lmcx_char_mask1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t mask:8;
-#else
-                uint64_t mask:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_lmcx_char_mask1_s cn61xx;
-        struct cvmx_lmcx_char_mask1_s cn63xx;
-        struct cvmx_lmcx_char_mask1_s cn63xxp1;
-        struct cvmx_lmcx_char_mask1_s cn66xx;
-        struct cvmx_lmcx_char_mask1_s cn68xx;
-        struct cvmx_lmcx_char_mask1_s cn68xxp1;
-        struct cvmx_lmcx_char_mask1_s cnf71xx;
-};
-
-union cvmx_lmcx_char_mask2 {
-        uint64_t u64;
-        struct cvmx_lmcx_char_mask2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t mask:64;
-#else
-                uint64_t mask:64;
-#endif
-        } s;
-        struct cvmx_lmcx_char_mask2_s cn61xx;
-        struct cvmx_lmcx_char_mask2_s cn63xx;
-        struct cvmx_lmcx_char_mask2_s cn63xxp1;
-        struct cvmx_lmcx_char_mask2_s cn66xx;
-        struct cvmx_lmcx_char_mask2_s cn68xx;
-        struct cvmx_lmcx_char_mask2_s cn68xxp1;
-        struct cvmx_lmcx_char_mask2_s cnf71xx;
-};
-
-union cvmx_lmcx_char_mask3 {
-        uint64_t u64;
-        struct cvmx_lmcx_char_mask3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t mask:8;
-#else
-                uint64_t mask:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_lmcx_char_mask3_s cn61xx;
-        struct cvmx_lmcx_char_mask3_s cn63xx;
-        struct cvmx_lmcx_char_mask3_s cn63xxp1;
-        struct cvmx_lmcx_char_mask3_s cn66xx;
-        struct cvmx_lmcx_char_mask3_s cn68xx;
-        struct cvmx_lmcx_char_mask3_s cn68xxp1;
-        struct cvmx_lmcx_char_mask3_s cnf71xx;
-};
-
-union cvmx_lmcx_char_mask4 {
-        uint64_t u64;
-        struct cvmx_lmcx_char_mask4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t reset_n_mask:1;
-                uint64_t a_mask:16;
-                uint64_t ba_mask:3;
-                uint64_t we_n_mask:1;
-                uint64_t cas_n_mask:1;
-                uint64_t ras_n_mask:1;
-                uint64_t odt1_mask:2;
-                uint64_t odt0_mask:2;
-                uint64_t cs1_n_mask:2;
-                uint64_t cs0_n_mask:2;
-                uint64_t cke_mask:2;
-#else
-                uint64_t cke_mask:2;
-                uint64_t cs0_n_mask:2;
-                uint64_t cs1_n_mask:2;
-                uint64_t odt0_mask:2;
-                uint64_t odt1_mask:2;
-                uint64_t ras_n_mask:1;
-                uint64_t cas_n_mask:1;
-                uint64_t we_n_mask:1;
-                uint64_t ba_mask:3;
-                uint64_t a_mask:16;
-                uint64_t reset_n_mask:1;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_lmcx_char_mask4_s cn61xx;
-        struct cvmx_lmcx_char_mask4_s cn63xx;
-        struct cvmx_lmcx_char_mask4_s cn63xxp1;
-        struct cvmx_lmcx_char_mask4_s cn66xx;
-        struct cvmx_lmcx_char_mask4_s cn68xx;
-        struct cvmx_lmcx_char_mask4_s cn68xxp1;
-        struct cvmx_lmcx_char_mask4_s cnf71xx;
-};
-
-union cvmx_lmcx_comp_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_comp_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t nctl_csr:4;
-                uint64_t nctl_clk:4;
-                uint64_t nctl_cmd:4;
-                uint64_t nctl_dat:4;
-                uint64_t pctl_csr:4;
-                uint64_t pctl_clk:4;
-                uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t pctl_clk:4;
-                uint64_t pctl_csr:4;
-                uint64_t nctl_dat:4;
-                uint64_t nctl_cmd:4;
-                uint64_t nctl_clk:4;
-                uint64_t nctl_csr:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_comp_ctl_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t nctl_csr:4;
-                uint64_t nctl_clk:4;
-                uint64_t nctl_cmd:4;
-                uint64_t nctl_dat:4;
-                uint64_t pctl_csr:4;
-                uint64_t pctl_clk:4;
-                uint64_t pctl_cmd:4;
-                uint64_t pctl_dat:4;
-#else
-                uint64_t pctl_dat:4;
-                uint64_t pctl_cmd:4;
-                uint64_t pctl_clk:4;
-                uint64_t pctl_csr:4;
-                uint64_t nctl_dat:4;
-                uint64_t nctl_cmd:4;
-                uint64_t nctl_clk:4;
-                uint64_t nctl_csr:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn30xx;
-        struct cvmx_lmcx_comp_ctl_cn30xx cn31xx;
-        struct cvmx_lmcx_comp_ctl_cn30xx cn38xx;
-        struct cvmx_lmcx_comp_ctl_cn30xx cn38xxp2;
-        struct cvmx_lmcx_comp_ctl_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t nctl_csr:4;
-                uint64_t reserved_20_27:8;
-                uint64_t nctl_dat:4;
-                uint64_t pctl_csr:4;
-                uint64_t reserved_5_11:7;
-                uint64_t pctl_dat:5;
-#else
-                uint64_t pctl_dat:5;
-                uint64_t reserved_5_11:7;
-                uint64_t pctl_csr:4;
-                uint64_t nctl_dat:4;
-                uint64_t reserved_20_27:8;
-                uint64_t nctl_csr:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn50xx;
-        struct cvmx_lmcx_comp_ctl_cn50xx cn52xx;
-        struct cvmx_lmcx_comp_ctl_cn50xx cn52xxp1;
-        struct cvmx_lmcx_comp_ctl_cn50xx cn56xx;
-        struct cvmx_lmcx_comp_ctl_cn50xx cn56xxp1;
-        struct cvmx_lmcx_comp_ctl_cn50xx cn58xx;
-        struct cvmx_lmcx_comp_ctl_cn58xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t nctl_csr:4;
-                uint64_t reserved_20_27:8;
-                uint64_t nctl_dat:4;
-                uint64_t pctl_csr:4;
-                uint64_t reserved_4_11:8;
-                uint64_t pctl_dat:4;
-#else
-                uint64_t pctl_dat:4;
-                uint64_t reserved_4_11:8;
-                uint64_t pctl_csr:4;
-                uint64_t nctl_dat:4;
-                uint64_t reserved_20_27:8;
-                uint64_t nctl_csr:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn58xxp1;
-};
-
-union cvmx_lmcx_comp_ctl2 {
-        uint64_t u64;
-        struct cvmx_lmcx_comp_ctl2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_34_63:30;
-                uint64_t ddr__ptune:4;
-                uint64_t ddr__ntune:4;
-                uint64_t m180:1;
-                uint64_t byp:1;
-                uint64_t ptune:4;
-                uint64_t ntune:4;
-                uint64_t rodt_ctl:4;
-                uint64_t cmd_ctl:4;
-                uint64_t ck_ctl:4;
-                uint64_t dqx_ctl:4;
-#else
-                uint64_t dqx_ctl:4;
-                uint64_t ck_ctl:4;
-                uint64_t cmd_ctl:4;
-                uint64_t rodt_ctl:4;
-                uint64_t ntune:4;
-                uint64_t ptune:4;
-                uint64_t byp:1;
-                uint64_t m180:1;
-                uint64_t ddr__ntune:4;
-                uint64_t ddr__ptune:4;
-                uint64_t reserved_34_63:30;
-#endif
-        } s;
-        struct cvmx_lmcx_comp_ctl2_s cn61xx;
-        struct cvmx_lmcx_comp_ctl2_s cn63xx;
-        struct cvmx_lmcx_comp_ctl2_s cn63xxp1;
-        struct cvmx_lmcx_comp_ctl2_s cn66xx;
-        struct cvmx_lmcx_comp_ctl2_s cn68xx;
-        struct cvmx_lmcx_comp_ctl2_s cn68xxp1;
-        struct cvmx_lmcx_comp_ctl2_s cnf71xx;
-};
-
-union cvmx_lmcx_config {
-        uint64_t u64;
-        struct cvmx_lmcx_config_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t mode32b:1;
-                uint64_t scrz:1;
-                uint64_t early_unload_d1_r1:1;
-                uint64_t early_unload_d1_r0:1;
-                uint64_t early_unload_d0_r1:1;
-                uint64_t early_unload_d0_r0:1;
-                uint64_t init_status:4;
-                uint64_t mirrmask:4;
-                uint64_t rankmask:4;
-                uint64_t rank_ena:1;
-                uint64_t sref_with_dll:1;
-                uint64_t early_dqx:1;
-                uint64_t sequence:3;
-                uint64_t ref_zqcs_int:19;
-                uint64_t reset:1;
-                uint64_t ecc_adr:1;
-                uint64_t forcewrite:4;
-                uint64_t idlepower:3;
-                uint64_t pbank_lsb:4;
-                uint64_t row_lsb:3;
-                uint64_t ecc_ena:1;
-                uint64_t init_start:1;
-#else
-                uint64_t init_start:1;
-                uint64_t ecc_ena:1;
-                uint64_t row_lsb:3;
-                uint64_t pbank_lsb:4;
-                uint64_t idlepower:3;
-                uint64_t forcewrite:4;
-                uint64_t ecc_adr:1;
-                uint64_t reset:1;
-                uint64_t ref_zqcs_int:19;
-                uint64_t sequence:3;
-                uint64_t early_dqx:1;
-                uint64_t sref_with_dll:1;
-                uint64_t rank_ena:1;
-                uint64_t rankmask:4;
-                uint64_t mirrmask:4;
-                uint64_t init_status:4;
-                uint64_t early_unload_d0_r0:1;
-                uint64_t early_unload_d0_r1:1;
-                uint64_t early_unload_d1_r0:1;
-                uint64_t early_unload_d1_r1:1;
-                uint64_t scrz:1;
-                uint64_t mode32b:1;
-                uint64_t reserved_61_63:3;
-#endif
-        } s;
-        struct cvmx_lmcx_config_s cn61xx;
-        struct cvmx_lmcx_config_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_59_63:5;
-                uint64_t early_unload_d1_r1:1;
-                uint64_t early_unload_d1_r0:1;
-                uint64_t early_unload_d0_r1:1;
-                uint64_t early_unload_d0_r0:1;
-                uint64_t init_status:4;
-                uint64_t mirrmask:4;
-                uint64_t rankmask:4;
-                uint64_t rank_ena:1;
-                uint64_t sref_with_dll:1;
-                uint64_t early_dqx:1;
-                uint64_t sequence:3;
-                uint64_t ref_zqcs_int:19;
-                uint64_t reset:1;
-                uint64_t ecc_adr:1;
-                uint64_t forcewrite:4;
-                uint64_t idlepower:3;
-                uint64_t pbank_lsb:4;
-                uint64_t row_lsb:3;
-                uint64_t ecc_ena:1;
-                uint64_t init_start:1;
-#else
-                uint64_t init_start:1;
-                uint64_t ecc_ena:1;
-                uint64_t row_lsb:3;
-                uint64_t pbank_lsb:4;
-                uint64_t idlepower:3;
-                uint64_t forcewrite:4;
-                uint64_t ecc_adr:1;
-                uint64_t reset:1;
-                uint64_t ref_zqcs_int:19;
-                uint64_t sequence:3;
-                uint64_t early_dqx:1;
-                uint64_t sref_with_dll:1;
-                uint64_t rank_ena:1;
-                uint64_t rankmask:4;
-                uint64_t mirrmask:4;
-                uint64_t init_status:4;
-                uint64_t early_unload_d0_r0:1;
-                uint64_t early_unload_d0_r1:1;
-                uint64_t early_unload_d1_r0:1;
-                uint64_t early_unload_d1_r1:1;
-                uint64_t reserved_59_63:5;
-#endif
-        } cn63xx;
-        struct cvmx_lmcx_config_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_55_63:9;
-                uint64_t init_status:4;
-                uint64_t mirrmask:4;
-                uint64_t rankmask:4;
-                uint64_t rank_ena:1;
-                uint64_t sref_with_dll:1;
-                uint64_t early_dqx:1;
-                uint64_t sequence:3;
-                uint64_t ref_zqcs_int:19;
-                uint64_t reset:1;
-                uint64_t ecc_adr:1;
-                uint64_t forcewrite:4;
-                uint64_t idlepower:3;
-                uint64_t pbank_lsb:4;
-                uint64_t row_lsb:3;
-                uint64_t ecc_ena:1;
-                uint64_t init_start:1;
-#else
-                uint64_t init_start:1;
-                uint64_t ecc_ena:1;
-                uint64_t row_lsb:3;
-                uint64_t pbank_lsb:4;
-                uint64_t idlepower:3;
-                uint64_t forcewrite:4;
-                uint64_t ecc_adr:1;
-                uint64_t reset:1;
-                uint64_t ref_zqcs_int:19;
-                uint64_t sequence:3;
-                uint64_t early_dqx:1;
-                uint64_t sref_with_dll:1;
-                uint64_t rank_ena:1;
-                uint64_t rankmask:4;
-                uint64_t mirrmask:4;
-                uint64_t init_status:4;
-                uint64_t reserved_55_63:9;
-#endif
-        } cn63xxp1;
-        struct cvmx_lmcx_config_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_60_63:4;
-                uint64_t scrz:1;
-                uint64_t early_unload_d1_r1:1;
-                uint64_t early_unload_d1_r0:1;
-                uint64_t early_unload_d0_r1:1;
-                uint64_t early_unload_d0_r0:1;
-                uint64_t init_status:4;
-                uint64_t mirrmask:4;
-                uint64_t rankmask:4;
-                uint64_t rank_ena:1;
-                uint64_t sref_with_dll:1;
-                uint64_t early_dqx:1;
-                uint64_t sequence:3;
-                uint64_t ref_zqcs_int:19;
-                uint64_t reset:1;
-                uint64_t ecc_adr:1;
-                uint64_t forcewrite:4;
-                uint64_t idlepower:3;
-                uint64_t pbank_lsb:4;
-                uint64_t row_lsb:3;
-                uint64_t ecc_ena:1;
-                uint64_t init_start:1;
-#else
-                uint64_t init_start:1;
-                uint64_t ecc_ena:1;
-                uint64_t row_lsb:3;
-                uint64_t pbank_lsb:4;
-                uint64_t idlepower:3;
-                uint64_t forcewrite:4;
-                uint64_t ecc_adr:1;
-                uint64_t reset:1;
-                uint64_t ref_zqcs_int:19;
-                uint64_t sequence:3;
-                uint64_t early_dqx:1;
-                uint64_t sref_with_dll:1;
-                uint64_t rank_ena:1;
-                uint64_t rankmask:4;
-                uint64_t mirrmask:4;
-                uint64_t init_status:4;
-                uint64_t early_unload_d0_r0:1;
-                uint64_t early_unload_d0_r1:1;
-                uint64_t early_unload_d1_r0:1;
-                uint64_t early_unload_d1_r1:1;
-                uint64_t scrz:1;
-                uint64_t reserved_60_63:4;
-#endif
-        } cn66xx;
-        struct cvmx_lmcx_config_cn63xx cn68xx;
-        struct cvmx_lmcx_config_cn63xx cn68xxp1;
-        struct cvmx_lmcx_config_s cnf71xx;
-};
-
-union cvmx_lmcx_control {
-        uint64_t u64;
-        struct cvmx_lmcx_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t scramble_ena:1;
-                uint64_t thrcnt:12;
-                uint64_t persub:8;
-                uint64_t thrmax:4;
-                uint64_t crm_cnt:5;
-                uint64_t crm_thr:5;
-                uint64_t crm_max:5;
-                uint64_t rodt_bprch:1;
-                uint64_t wodt_bprch:1;
-                uint64_t bprch:2;
-                uint64_t ext_zqcs_dis:1;
-                uint64_t int_zqcs_dis:1;
-                uint64_t auto_dclkdis:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t nxm_write_en:1;
-                uint64_t elev_prio_dis:1;
-                uint64_t inorder_wr:1;
-                uint64_t inorder_rd:1;
-                uint64_t throttle_wr:1;
-                uint64_t throttle_rd:1;
-                uint64_t fprch2:2;
-                uint64_t pocas:1;
-                uint64_t ddr2t:1;
-                uint64_t bwcnt:1;
-                uint64_t rdimm_ena:1;
-#else
-                uint64_t rdimm_ena:1;
-                uint64_t bwcnt:1;
-                uint64_t ddr2t:1;
-                uint64_t pocas:1;
-                uint64_t fprch2:2;
-                uint64_t throttle_rd:1;
-                uint64_t throttle_wr:1;
-                uint64_t inorder_rd:1;
-                uint64_t inorder_wr:1;
-                uint64_t elev_prio_dis:1;
-                uint64_t nxm_write_en:1;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t auto_dclkdis:1;
-                uint64_t int_zqcs_dis:1;
-                uint64_t ext_zqcs_dis:1;
-                uint64_t bprch:2;
-                uint64_t wodt_bprch:1;
-                uint64_t rodt_bprch:1;
-                uint64_t crm_max:5;
-                uint64_t crm_thr:5;
-                uint64_t crm_cnt:5;
-                uint64_t thrmax:4;
-                uint64_t persub:8;
-                uint64_t thrcnt:12;
-                uint64_t scramble_ena:1;
-#endif
-        } s;
-        struct cvmx_lmcx_control_s cn61xx;
-        struct cvmx_lmcx_control_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t rodt_bprch:1;
-                uint64_t wodt_bprch:1;
-                uint64_t bprch:2;
-                uint64_t ext_zqcs_dis:1;
-                uint64_t int_zqcs_dis:1;
-                uint64_t auto_dclkdis:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t nxm_write_en:1;
-                uint64_t elev_prio_dis:1;
-                uint64_t inorder_wr:1;
-                uint64_t inorder_rd:1;
-                uint64_t throttle_wr:1;
-                uint64_t throttle_rd:1;
-                uint64_t fprch2:2;
-                uint64_t pocas:1;
-                uint64_t ddr2t:1;
-                uint64_t bwcnt:1;
-                uint64_t rdimm_ena:1;
-#else
-                uint64_t rdimm_ena:1;
-                uint64_t bwcnt:1;
-                uint64_t ddr2t:1;
-                uint64_t pocas:1;
-                uint64_t fprch2:2;
-                uint64_t throttle_rd:1;
-                uint64_t throttle_wr:1;
-                uint64_t inorder_rd:1;
-                uint64_t inorder_wr:1;
-                uint64_t elev_prio_dis:1;
-                uint64_t nxm_write_en:1;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t auto_dclkdis:1;
-                uint64_t int_zqcs_dis:1;
-                uint64_t ext_zqcs_dis:1;
-                uint64_t bprch:2;
-                uint64_t wodt_bprch:1;
-                uint64_t rodt_bprch:1;
-                uint64_t reserved_24_63:40;
-#endif
-        } cn63xx;
-        struct cvmx_lmcx_control_cn63xx cn63xxp1;
-        struct cvmx_lmcx_control_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t scramble_ena:1;
-                uint64_t reserved_24_62:39;
-                uint64_t rodt_bprch:1;
-                uint64_t wodt_bprch:1;
-                uint64_t bprch:2;
-                uint64_t ext_zqcs_dis:1;
-                uint64_t int_zqcs_dis:1;
-                uint64_t auto_dclkdis:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t nxm_write_en:1;
-                uint64_t elev_prio_dis:1;
-                uint64_t inorder_wr:1;
-                uint64_t inorder_rd:1;
-                uint64_t throttle_wr:1;
-                uint64_t throttle_rd:1;
-                uint64_t fprch2:2;
-                uint64_t pocas:1;
-                uint64_t ddr2t:1;
-                uint64_t bwcnt:1;
-                uint64_t rdimm_ena:1;
-#else
-                uint64_t rdimm_ena:1;
-                uint64_t bwcnt:1;
-                uint64_t ddr2t:1;
-                uint64_t pocas:1;
-                uint64_t fprch2:2;
-                uint64_t throttle_rd:1;
-                uint64_t throttle_wr:1;
-                uint64_t inorder_rd:1;
-                uint64_t inorder_wr:1;
-                uint64_t elev_prio_dis:1;
-                uint64_t nxm_write_en:1;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t auto_dclkdis:1;
-                uint64_t int_zqcs_dis:1;
-                uint64_t ext_zqcs_dis:1;
-                uint64_t bprch:2;
-                uint64_t wodt_bprch:1;
-                uint64_t rodt_bprch:1;
-                uint64_t reserved_24_62:39;
-                uint64_t scramble_ena:1;
-#endif
-        } cn66xx;
-        struct cvmx_lmcx_control_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_63_63:1;
-                uint64_t thrcnt:12;
-                uint64_t persub:8;
-                uint64_t thrmax:4;
-                uint64_t crm_cnt:5;
-                uint64_t crm_thr:5;
-                uint64_t crm_max:5;
-                uint64_t rodt_bprch:1;
-                uint64_t wodt_bprch:1;
-                uint64_t bprch:2;
-                uint64_t ext_zqcs_dis:1;
-                uint64_t int_zqcs_dis:1;
-                uint64_t auto_dclkdis:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t nxm_write_en:1;
-                uint64_t elev_prio_dis:1;
-                uint64_t inorder_wr:1;
-                uint64_t inorder_rd:1;
-                uint64_t throttle_wr:1;
-                uint64_t throttle_rd:1;
-                uint64_t fprch2:2;
-                uint64_t pocas:1;
-                uint64_t ddr2t:1;
-                uint64_t bwcnt:1;
-                uint64_t rdimm_ena:1;
-#else
-                uint64_t rdimm_ena:1;
-                uint64_t bwcnt:1;
-                uint64_t ddr2t:1;
-                uint64_t pocas:1;
-                uint64_t fprch2:2;
-                uint64_t throttle_rd:1;
-                uint64_t throttle_wr:1;
-                uint64_t inorder_rd:1;
-                uint64_t inorder_wr:1;
-                uint64_t elev_prio_dis:1;
-                uint64_t nxm_write_en:1;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t auto_dclkdis:1;
-                uint64_t int_zqcs_dis:1;
-                uint64_t ext_zqcs_dis:1;
-                uint64_t bprch:2;
-                uint64_t wodt_bprch:1;
-                uint64_t rodt_bprch:1;
-                uint64_t crm_max:5;
-                uint64_t crm_thr:5;
-                uint64_t crm_cnt:5;
-                uint64_t thrmax:4;
-                uint64_t persub:8;
-                uint64_t thrcnt:12;
-                uint64_t reserved_63_63:1;
-#endif
-        } cn68xx;
-        struct cvmx_lmcx_control_cn68xx cn68xxp1;
-        struct cvmx_lmcx_control_cn66xx cnf71xx;
-};
-
-union cvmx_lmcx_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ddr__nctl:4;
-                uint64_t ddr__pctl:4;
-                uint64_t slow_scf:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t pll_div2:1;
-                uint64_t pll_bypass:1;
-                uint64_t rdimm_ena:1;
-                uint64_t r2r_slot:1;
-                uint64_t inorder_mwf:1;
-                uint64_t inorder_mrf:1;
-                uint64_t reserved_10_11:2;
-                uint64_t fprch2:1;
-                uint64_t bprch:1;
-                uint64_t sil_lat:2;
-                uint64_t tskw:2;
-                uint64_t qs_dic:2;
-                uint64_t dic:2;
-#else
-                uint64_t dic:2;
-                uint64_t qs_dic:2;
-                uint64_t tskw:2;
-                uint64_t sil_lat:2;
-                uint64_t bprch:1;
-                uint64_t fprch2:1;
-                uint64_t reserved_10_11:2;
-                uint64_t inorder_mrf:1;
-                uint64_t inorder_mwf:1;
-                uint64_t r2r_slot:1;
-                uint64_t rdimm_ena:1;
-                uint64_t pll_bypass:1;
-                uint64_t pll_div2:1;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t slow_scf:1;
-                uint64_t ddr__pctl:4;
-                uint64_t ddr__nctl:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_ctl_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ddr__nctl:4;
-                uint64_t ddr__pctl:4;
-                uint64_t slow_scf:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t pll_div2:1;
-                uint64_t pll_bypass:1;
-                uint64_t rdimm_ena:1;
-                uint64_t r2r_slot:1;
-                uint64_t inorder_mwf:1;
-                uint64_t inorder_mrf:1;
-                uint64_t dreset:1;
-                uint64_t mode32b:1;
-                uint64_t fprch2:1;
-                uint64_t bprch:1;
-                uint64_t sil_lat:2;
-                uint64_t tskw:2;
-                uint64_t qs_dic:2;
-                uint64_t dic:2;
-#else
-                uint64_t dic:2;
-                uint64_t qs_dic:2;
-                uint64_t tskw:2;
-                uint64_t sil_lat:2;
-                uint64_t bprch:1;
-                uint64_t fprch2:1;
-                uint64_t mode32b:1;
-                uint64_t dreset:1;
-                uint64_t inorder_mrf:1;
-                uint64_t inorder_mwf:1;
-                uint64_t r2r_slot:1;
-                uint64_t rdimm_ena:1;
-                uint64_t pll_bypass:1;
-                uint64_t pll_div2:1;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t slow_scf:1;
-                uint64_t ddr__pctl:4;
-                uint64_t ddr__nctl:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn30xx;
-        struct cvmx_lmcx_ctl_cn30xx cn31xx;
-        struct cvmx_lmcx_ctl_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ddr__nctl:4;
-                uint64_t ddr__pctl:4;
-                uint64_t slow_scf:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t reserved_16_17:2;
-                uint64_t rdimm_ena:1;
-                uint64_t r2r_slot:1;
-                uint64_t inorder_mwf:1;
-                uint64_t inorder_mrf:1;
-                uint64_t set_zero:1;
-                uint64_t mode128b:1;
-                uint64_t fprch2:1;
-                uint64_t bprch:1;
-                uint64_t sil_lat:2;
-                uint64_t tskw:2;
-                uint64_t qs_dic:2;
-                uint64_t dic:2;
-#else
-                uint64_t dic:2;
-                uint64_t qs_dic:2;
-                uint64_t tskw:2;
-                uint64_t sil_lat:2;
-                uint64_t bprch:1;
-                uint64_t fprch2:1;
-                uint64_t mode128b:1;
-                uint64_t set_zero:1;
-                uint64_t inorder_mrf:1;
-                uint64_t inorder_mwf:1;
-                uint64_t r2r_slot:1;
-                uint64_t rdimm_ena:1;
-                uint64_t reserved_16_17:2;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t slow_scf:1;
-                uint64_t ddr__pctl:4;
-                uint64_t ddr__nctl:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn38xx;
-        struct cvmx_lmcx_ctl_cn38xx cn38xxp2;
-        struct cvmx_lmcx_ctl_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ddr__nctl:4;
-                uint64_t ddr__pctl:4;
-                uint64_t slow_scf:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t reserved_17_17:1;
-                uint64_t pll_bypass:1;
-                uint64_t rdimm_ena:1;
-                uint64_t r2r_slot:1;
-                uint64_t inorder_mwf:1;
-                uint64_t inorder_mrf:1;
-                uint64_t dreset:1;
-                uint64_t mode32b:1;
-                uint64_t fprch2:1;
-                uint64_t bprch:1;
-                uint64_t sil_lat:2;
-                uint64_t tskw:2;
-                uint64_t qs_dic:2;
-                uint64_t dic:2;
-#else
-                uint64_t dic:2;
-                uint64_t qs_dic:2;
-                uint64_t tskw:2;
-                uint64_t sil_lat:2;
-                uint64_t bprch:1;
-                uint64_t fprch2:1;
-                uint64_t mode32b:1;
-                uint64_t dreset:1;
-                uint64_t inorder_mrf:1;
-                uint64_t inorder_mwf:1;
-                uint64_t r2r_slot:1;
-                uint64_t rdimm_ena:1;
-                uint64_t pll_bypass:1;
-                uint64_t reserved_17_17:1;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t slow_scf:1;
-                uint64_t ddr__pctl:4;
-                uint64_t ddr__nctl:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn50xx;
-        struct cvmx_lmcx_ctl_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ddr__nctl:4;
-                uint64_t ddr__pctl:4;
-                uint64_t slow_scf:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t reserved_16_17:2;
-                uint64_t rdimm_ena:1;
-                uint64_t r2r_slot:1;
-                uint64_t inorder_mwf:1;
-                uint64_t inorder_mrf:1;
-                uint64_t dreset:1;
-                uint64_t mode32b:1;
-                uint64_t fprch2:1;
-                uint64_t bprch:1;
-                uint64_t sil_lat:2;
-                uint64_t tskw:2;
-                uint64_t qs_dic:2;
-                uint64_t dic:2;
-#else
-                uint64_t dic:2;
-                uint64_t qs_dic:2;
-                uint64_t tskw:2;
-                uint64_t sil_lat:2;
-                uint64_t bprch:1;
-                uint64_t fprch2:1;
-                uint64_t mode32b:1;
-                uint64_t dreset:1;
-                uint64_t inorder_mrf:1;
-                uint64_t inorder_mwf:1;
-                uint64_t r2r_slot:1;
-                uint64_t rdimm_ena:1;
-                uint64_t reserved_16_17:2;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t slow_scf:1;
-                uint64_t ddr__pctl:4;
-                uint64_t ddr__nctl:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn52xx;
-        struct cvmx_lmcx_ctl_cn52xx cn52xxp1;
-        struct cvmx_lmcx_ctl_cn52xx cn56xx;
-        struct cvmx_lmcx_ctl_cn52xx cn56xxp1;
-        struct cvmx_lmcx_ctl_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ddr__nctl:4;
-                uint64_t ddr__pctl:4;
-                uint64_t slow_scf:1;
-                uint64_t xor_bank:1;
-                uint64_t max_write_batch:4;
-                uint64_t reserved_16_17:2;
-                uint64_t rdimm_ena:1;
-                uint64_t r2r_slot:1;
-                uint64_t inorder_mwf:1;
-                uint64_t inorder_mrf:1;
-                uint64_t dreset:1;
-                uint64_t mode128b:1;
-                uint64_t fprch2:1;
-                uint64_t bprch:1;
-                uint64_t sil_lat:2;
-                uint64_t tskw:2;
-                uint64_t qs_dic:2;
-                uint64_t dic:2;
-#else
-                uint64_t dic:2;
-                uint64_t qs_dic:2;
-                uint64_t tskw:2;
-                uint64_t sil_lat:2;
-                uint64_t bprch:1;
-                uint64_t fprch2:1;
-                uint64_t mode128b:1;
-                uint64_t dreset:1;
-                uint64_t inorder_mrf:1;
-                uint64_t inorder_mwf:1;
-                uint64_t r2r_slot:1;
-                uint64_t rdimm_ena:1;
-                uint64_t reserved_16_17:2;
-                uint64_t max_write_batch:4;
-                uint64_t xor_bank:1;
-                uint64_t slow_scf:1;
-                uint64_t ddr__pctl:4;
-                uint64_t ddr__nctl:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn58xx;
-        struct cvmx_lmcx_ctl_cn58xx cn58xxp1;
-};
-
-union cvmx_lmcx_ctl1 {
-        uint64_t u64;
-        struct cvmx_lmcx_ctl1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_21_63:43;
-                uint64_t ecc_adr:1;
-                uint64_t forcewrite:4;
-                uint64_t idlepower:3;
-                uint64_t sequence:3;
-                uint64_t sil_mode:1;
-                uint64_t dcc_enable:1;
-                uint64_t reserved_2_7:6;
-                uint64_t data_layout:2;
-#else
-                uint64_t data_layout:2;
-                uint64_t reserved_2_7:6;
-                uint64_t dcc_enable:1;
-                uint64_t sil_mode:1;
-                uint64_t sequence:3;
-                uint64_t idlepower:3;
-                uint64_t forcewrite:4;
-                uint64_t ecc_adr:1;
-                uint64_t reserved_21_63:43;
-#endif
-        } s;
-        struct cvmx_lmcx_ctl1_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t data_layout:2;
-#else
-                uint64_t data_layout:2;
-                uint64_t reserved_2_63:62;
-#endif
-        } cn30xx;
-        struct cvmx_lmcx_ctl1_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t sil_mode:1;
-                uint64_t dcc_enable:1;
-                uint64_t reserved_2_7:6;
-                uint64_t data_layout:2;
-#else
-                uint64_t data_layout:2;
-                uint64_t reserved_2_7:6;
-                uint64_t dcc_enable:1;
-                uint64_t sil_mode:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn50xx;
-        struct cvmx_lmcx_ctl1_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_21_63:43;
-                uint64_t ecc_adr:1;
-                uint64_t forcewrite:4;
-                uint64_t idlepower:3;
-                uint64_t sequence:3;
-                uint64_t sil_mode:1;
-                uint64_t dcc_enable:1;
-                uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t dcc_enable:1;
-                uint64_t sil_mode:1;
-                uint64_t sequence:3;
-                uint64_t idlepower:3;
-                uint64_t forcewrite:4;
-                uint64_t ecc_adr:1;
-                uint64_t reserved_21_63:43;
-#endif
-        } cn52xx;
-        struct cvmx_lmcx_ctl1_cn52xx cn52xxp1;
-        struct cvmx_lmcx_ctl1_cn52xx cn56xx;
-        struct cvmx_lmcx_ctl1_cn52xx cn56xxp1;
-        struct cvmx_lmcx_ctl1_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t sil_mode:1;
-                uint64_t dcc_enable:1;
-                uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t dcc_enable:1;
-                uint64_t sil_mode:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn58xx;
-        struct cvmx_lmcx_ctl1_cn58xx cn58xxp1;
-};
-
-union cvmx_lmcx_dclk_cnt {
-        uint64_t u64;
-        struct cvmx_lmcx_dclk_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dclkcnt:64;
-#else
-                uint64_t dclkcnt:64;
-#endif
-        } s;
-        struct cvmx_lmcx_dclk_cnt_s cn61xx;
-        struct cvmx_lmcx_dclk_cnt_s cn63xx;
-        struct cvmx_lmcx_dclk_cnt_s cn63xxp1;
-        struct cvmx_lmcx_dclk_cnt_s cn66xx;
-        struct cvmx_lmcx_dclk_cnt_s cn68xx;
-        struct cvmx_lmcx_dclk_cnt_s cn68xxp1;
-        struct cvmx_lmcx_dclk_cnt_s cnf71xx;
-};
-
-union cvmx_lmcx_dclk_cnt_hi {
-        uint64_t u64;
-        struct cvmx_lmcx_dclk_cnt_hi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t dclkcnt_hi:32;
-#else
-                uint64_t dclkcnt_hi:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn30xx;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn31xx;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn38xx;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn38xxp2;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn50xx;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn52xx;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn52xxp1;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn56xx;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn56xxp1;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn58xx;
-        struct cvmx_lmcx_dclk_cnt_hi_s cn58xxp1;
-};
-
-union cvmx_lmcx_dclk_cnt_lo {
-        uint64_t u64;
-        struct cvmx_lmcx_dclk_cnt_lo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t dclkcnt_lo:32;
-#else
-                uint64_t dclkcnt_lo:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn30xx;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn31xx;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn38xx;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn38xxp2;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn50xx;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn52xx;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn52xxp1;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn56xx;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn56xxp1;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn58xx;
-        struct cvmx_lmcx_dclk_cnt_lo_s cn58xxp1;
-};
-
-union cvmx_lmcx_dclk_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_dclk_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t off90_ena:1;
-                uint64_t dclk90_byp:1;
-                uint64_t dclk90_ld:1;
-                uint64_t dclk90_vlu:5;
-#else
-                uint64_t dclk90_vlu:5;
-                uint64_t dclk90_ld:1;
-                uint64_t dclk90_byp:1;
-                uint64_t off90_ena:1;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_lmcx_dclk_ctl_s cn56xx;
-        struct cvmx_lmcx_dclk_ctl_s cn56xxp1;
-};
-
-union cvmx_lmcx_ddr2_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_ddr2_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t bank8:1;
-                uint64_t burst8:1;
-                uint64_t addlat:3;
-                uint64_t pocas:1;
-                uint64_t bwcnt:1;
-                uint64_t twr:3;
-                uint64_t silo_hc:1;
-                uint64_t ddr_eof:4;
-                uint64_t tfaw:5;
-                uint64_t crip_mode:1;
-                uint64_t ddr2t:1;
-                uint64_t odt_ena:1;
-                uint64_t qdll_ena:1;
-                uint64_t dll90_vlu:5;
-                uint64_t dll90_byp:1;
-                uint64_t rdqs:1;
-                uint64_t ddr2:1;
-#else
-                uint64_t ddr2:1;
-                uint64_t rdqs:1;
-                uint64_t dll90_byp:1;
-                uint64_t dll90_vlu:5;
-                uint64_t qdll_ena:1;
-                uint64_t odt_ena:1;
-                uint64_t ddr2t:1;
-                uint64_t crip_mode:1;
-                uint64_t tfaw:5;
-                uint64_t ddr_eof:4;
-                uint64_t silo_hc:1;
-                uint64_t twr:3;
-                uint64_t bwcnt:1;
-                uint64_t pocas:1;
-                uint64_t addlat:3;
-                uint64_t burst8:1;
-                uint64_t bank8:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_ddr2_ctl_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t bank8:1;
-                uint64_t burst8:1;
-                uint64_t addlat:3;
-                uint64_t pocas:1;
-                uint64_t bwcnt:1;
-                uint64_t twr:3;
-                uint64_t silo_hc:1;
-                uint64_t ddr_eof:4;
-                uint64_t tfaw:5;
-                uint64_t crip_mode:1;
-                uint64_t ddr2t:1;
-                uint64_t odt_ena:1;
-                uint64_t qdll_ena:1;
-                uint64_t dll90_vlu:5;
-                uint64_t dll90_byp:1;
-                uint64_t reserved_1_1:1;
-                uint64_t ddr2:1;
-#else
-                uint64_t ddr2:1;
-                uint64_t reserved_1_1:1;
-                uint64_t dll90_byp:1;
-                uint64_t dll90_vlu:5;
-                uint64_t qdll_ena:1;
-                uint64_t odt_ena:1;
-                uint64_t ddr2t:1;
-                uint64_t crip_mode:1;
-                uint64_t tfaw:5;
-                uint64_t ddr_eof:4;
-                uint64_t silo_hc:1;
-                uint64_t twr:3;
-                uint64_t bwcnt:1;
-                uint64_t pocas:1;
-                uint64_t addlat:3;
-                uint64_t burst8:1;
-                uint64_t bank8:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn30xx;
-        struct cvmx_lmcx_ddr2_ctl_cn30xx cn31xx;
-        struct cvmx_lmcx_ddr2_ctl_s cn38xx;
-        struct cvmx_lmcx_ddr2_ctl_s cn38xxp2;
-        struct cvmx_lmcx_ddr2_ctl_s cn50xx;
-        struct cvmx_lmcx_ddr2_ctl_s cn52xx;
-        struct cvmx_lmcx_ddr2_ctl_s cn52xxp1;
-        struct cvmx_lmcx_ddr2_ctl_s cn56xx;
-        struct cvmx_lmcx_ddr2_ctl_s cn56xxp1;
-        struct cvmx_lmcx_ddr2_ctl_s cn58xx;
-        struct cvmx_lmcx_ddr2_ctl_s cn58xxp1;
-};
-
-union cvmx_lmcx_ddr_pll_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_ddr_pll_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_27_63:37;
-                uint64_t jtg_test_mode:1;
-                uint64_t dfm_div_reset:1;
-                uint64_t dfm_ps_en:3;
-                uint64_t ddr_div_reset:1;
-                uint64_t ddr_ps_en:3;
-                uint64_t diffamp:4;
-                uint64_t cps:3;
-                uint64_t cpb:3;
-                uint64_t reset_n:1;
-                uint64_t clkf:7;
-#else
-                uint64_t clkf:7;
-                uint64_t reset_n:1;
-                uint64_t cpb:3;
-                uint64_t cps:3;
-                uint64_t diffamp:4;
-                uint64_t ddr_ps_en:3;
-                uint64_t ddr_div_reset:1;
-                uint64_t dfm_ps_en:3;
-                uint64_t dfm_div_reset:1;
-                uint64_t jtg_test_mode:1;
-                uint64_t reserved_27_63:37;
-#endif
-        } s;
-        struct cvmx_lmcx_ddr_pll_ctl_s cn61xx;
-        struct cvmx_lmcx_ddr_pll_ctl_s cn63xx;
-        struct cvmx_lmcx_ddr_pll_ctl_s cn63xxp1;
-        struct cvmx_lmcx_ddr_pll_ctl_s cn66xx;
-        struct cvmx_lmcx_ddr_pll_ctl_s cn68xx;
-        struct cvmx_lmcx_ddr_pll_ctl_s cn68xxp1;
-        struct cvmx_lmcx_ddr_pll_ctl_s cnf71xx;
-};
-
-union cvmx_lmcx_delay_cfg {
-        uint64_t u64;
-        struct cvmx_lmcx_delay_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t dq:5;
-                uint64_t cmd:5;
-                uint64_t clk:5;
-#else
-                uint64_t clk:5;
-                uint64_t cmd:5;
-                uint64_t dq:5;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_lmcx_delay_cfg_s cn30xx;
-        struct cvmx_lmcx_delay_cfg_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t dq:4;
-                uint64_t reserved_9_9:1;
-                uint64_t cmd:4;
-                uint64_t reserved_4_4:1;
-                uint64_t clk:4;
-#else
-                uint64_t clk:4;
-                uint64_t reserved_4_4:1;
-                uint64_t cmd:4;
-                uint64_t reserved_9_9:1;
-                uint64_t dq:4;
-                uint64_t reserved_14_63:50;
-#endif
-        } cn38xx;
-        struct cvmx_lmcx_delay_cfg_cn38xx cn50xx;
-        struct cvmx_lmcx_delay_cfg_cn38xx cn52xx;
-        struct cvmx_lmcx_delay_cfg_cn38xx cn52xxp1;
-        struct cvmx_lmcx_delay_cfg_cn38xx cn56xx;
-        struct cvmx_lmcx_delay_cfg_cn38xx cn56xxp1;
-        struct cvmx_lmcx_delay_cfg_cn38xx cn58xx;
-        struct cvmx_lmcx_delay_cfg_cn38xx cn58xxp1;
-};
-
-union cvmx_lmcx_dimmx_params {
-        uint64_t u64;
-        struct cvmx_lmcx_dimmx_params_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rc15:4;
-                uint64_t rc14:4;
-                uint64_t rc13:4;
-                uint64_t rc12:4;
-                uint64_t rc11:4;
-                uint64_t rc10:4;
-                uint64_t rc9:4;
-                uint64_t rc8:4;
-                uint64_t rc7:4;
-                uint64_t rc6:4;
-                uint64_t rc5:4;
-                uint64_t rc4:4;
-                uint64_t rc3:4;
-                uint64_t rc2:4;
-                uint64_t rc1:4;
-                uint64_t rc0:4;
-#else
-                uint64_t rc0:4;
-                uint64_t rc1:4;
-                uint64_t rc2:4;
-                uint64_t rc3:4;
-                uint64_t rc4:4;
-                uint64_t rc5:4;
-                uint64_t rc6:4;
-                uint64_t rc7:4;
-                uint64_t rc8:4;
-                uint64_t rc9:4;
-                uint64_t rc10:4;
-                uint64_t rc11:4;
-                uint64_t rc12:4;
-                uint64_t rc13:4;
-                uint64_t rc14:4;
-                uint64_t rc15:4;
-#endif
-        } s;
-        struct cvmx_lmcx_dimmx_params_s cn61xx;
-        struct cvmx_lmcx_dimmx_params_s cn63xx;
-        struct cvmx_lmcx_dimmx_params_s cn63xxp1;
-        struct cvmx_lmcx_dimmx_params_s cn66xx;
-        struct cvmx_lmcx_dimmx_params_s cn68xx;
-        struct cvmx_lmcx_dimmx_params_s cn68xxp1;
-        struct cvmx_lmcx_dimmx_params_s cnf71xx;
-};
-
-union cvmx_lmcx_dimm_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_dimm_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_46_63:18;
-                uint64_t parity:1;
-                uint64_t tcws:13;
-                uint64_t dimm1_wmask:16;
-                uint64_t dimm0_wmask:16;
-#else
-                uint64_t dimm0_wmask:16;
-                uint64_t dimm1_wmask:16;
-                uint64_t tcws:13;
-                uint64_t parity:1;
-                uint64_t reserved_46_63:18;
-#endif
-        } s;
-        struct cvmx_lmcx_dimm_ctl_s cn61xx;
-        struct cvmx_lmcx_dimm_ctl_s cn63xx;
-        struct cvmx_lmcx_dimm_ctl_s cn63xxp1;
-        struct cvmx_lmcx_dimm_ctl_s cn66xx;
-        struct cvmx_lmcx_dimm_ctl_s cn68xx;
-        struct cvmx_lmcx_dimm_ctl_s cn68xxp1;
-        struct cvmx_lmcx_dimm_ctl_s cnf71xx;
-};
-
-union cvmx_lmcx_dll_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_dll_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t dreset:1;
-                uint64_t dll90_byp:1;
-                uint64_t dll90_ena:1;
-                uint64_t dll90_vlu:5;
-#else
-                uint64_t dll90_vlu:5;
-                uint64_t dll90_ena:1;
-                uint64_t dll90_byp:1;
-                uint64_t dreset:1;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_lmcx_dll_ctl_s cn52xx;
-        struct cvmx_lmcx_dll_ctl_s cn52xxp1;
-        struct cvmx_lmcx_dll_ctl_s cn56xx;
-        struct cvmx_lmcx_dll_ctl_s cn56xxp1;
-};
-
-union cvmx_lmcx_dll_ctl2 {
-        uint64_t u64;
-        struct cvmx_lmcx_dll_ctl2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t intf_en:1;
-                uint64_t dll_bringup:1;
-                uint64_t dreset:1;
-                uint64_t quad_dll_ena:1;
-                uint64_t byp_sel:4;
-                uint64_t byp_setting:8;
-#else
-                uint64_t byp_setting:8;
-                uint64_t byp_sel:4;
-                uint64_t quad_dll_ena:1;
-                uint64_t dreset:1;
-                uint64_t dll_bringup:1;
-                uint64_t intf_en:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_lmcx_dll_ctl2_s cn61xx;
-        struct cvmx_lmcx_dll_ctl2_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t dll_bringup:1;
-                uint64_t dreset:1;
-                uint64_t quad_dll_ena:1;
-                uint64_t byp_sel:4;
-                uint64_t byp_setting:8;
-#else
-                uint64_t byp_setting:8;
-                uint64_t byp_sel:4;
-                uint64_t quad_dll_ena:1;
-                uint64_t dreset:1;
-                uint64_t dll_bringup:1;
-                uint64_t reserved_15_63:49;
-#endif
-        } cn63xx;
-        struct cvmx_lmcx_dll_ctl2_cn63xx cn63xxp1;
-        struct cvmx_lmcx_dll_ctl2_cn63xx cn66xx;
-        struct cvmx_lmcx_dll_ctl2_s cn68xx;
-        struct cvmx_lmcx_dll_ctl2_s cn68xxp1;
-        struct cvmx_lmcx_dll_ctl2_s cnf71xx;
-};
-
-union cvmx_lmcx_dll_ctl3 {
-        uint64_t u64;
-        struct cvmx_lmcx_dll_ctl3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_41_63:23;
-                uint64_t dclk90_fwd:1;
-                uint64_t ddr_90_dly_byp:1;
-                uint64_t dclk90_recal_dis:1;
-                uint64_t dclk90_byp_sel:1;
-                uint64_t dclk90_byp_setting:8;
-                uint64_t dll_fast:1;
-                uint64_t dll90_setting:8;
-                uint64_t fine_tune_mode:1;
-                uint64_t dll_mode:1;
-                uint64_t dll90_byte_sel:4;
-                uint64_t offset_ena:1;
-                uint64_t load_offset:1;
-                uint64_t mode_sel:2;
-                uint64_t byte_sel:4;
-                uint64_t offset:6;
-#else
-                uint64_t offset:6;
-                uint64_t byte_sel:4;
-                uint64_t mode_sel:2;
-                uint64_t load_offset:1;
-                uint64_t offset_ena:1;
-                uint64_t dll90_byte_sel:4;
-                uint64_t dll_mode:1;
-                uint64_t fine_tune_mode:1;
-                uint64_t dll90_setting:8;
-                uint64_t dll_fast:1;
-                uint64_t dclk90_byp_setting:8;
-                uint64_t dclk90_byp_sel:1;
-                uint64_t dclk90_recal_dis:1;
-                uint64_t ddr_90_dly_byp:1;
-                uint64_t dclk90_fwd:1;
-                uint64_t reserved_41_63:23;
-#endif
-        } s;
-        struct cvmx_lmcx_dll_ctl3_s cn61xx;
-        struct cvmx_lmcx_dll_ctl3_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t dll_fast:1;
-                uint64_t dll90_setting:8;
-                uint64_t fine_tune_mode:1;
-                uint64_t dll_mode:1;
-                uint64_t dll90_byte_sel:4;
-                uint64_t offset_ena:1;
-                uint64_t load_offset:1;
-                uint64_t mode_sel:2;
-                uint64_t byte_sel:4;
-                uint64_t offset:6;
-#else
-                uint64_t offset:6;
-                uint64_t byte_sel:4;
-                uint64_t mode_sel:2;
-                uint64_t load_offset:1;
-                uint64_t offset_ena:1;
-                uint64_t dll90_byte_sel:4;
-                uint64_t dll_mode:1;
-                uint64_t fine_tune_mode:1;
-                uint64_t dll90_setting:8;
-                uint64_t dll_fast:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn63xx;
-        struct cvmx_lmcx_dll_ctl3_cn63xx cn63xxp1;
-        struct cvmx_lmcx_dll_ctl3_cn63xx cn66xx;
-        struct cvmx_lmcx_dll_ctl3_s cn68xx;
-        struct cvmx_lmcx_dll_ctl3_s cn68xxp1;
-        struct cvmx_lmcx_dll_ctl3_s cnf71xx;
-};
-
-union cvmx_lmcx_dual_memcfg {
-        uint64_t u64;
-        struct cvmx_lmcx_dual_memcfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t bank8:1;
-                uint64_t row_lsb:3;
-                uint64_t reserved_8_15:8;
-                uint64_t cs_mask:8;
-#else
-                uint64_t cs_mask:8;
-                uint64_t reserved_8_15:8;
-                uint64_t row_lsb:3;
-                uint64_t bank8:1;
-                uint64_t reserved_20_63:44;
-#endif
-        } s;
-        struct cvmx_lmcx_dual_memcfg_s cn50xx;
-        struct cvmx_lmcx_dual_memcfg_s cn52xx;
-        struct cvmx_lmcx_dual_memcfg_s cn52xxp1;
-        struct cvmx_lmcx_dual_memcfg_s cn56xx;
-        struct cvmx_lmcx_dual_memcfg_s cn56xxp1;
-        struct cvmx_lmcx_dual_memcfg_s cn58xx;
-        struct cvmx_lmcx_dual_memcfg_s cn58xxp1;
-        struct cvmx_lmcx_dual_memcfg_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t row_lsb:3;
-                uint64_t reserved_8_15:8;
-                uint64_t cs_mask:8;
-#else
-                uint64_t cs_mask:8;
-                uint64_t reserved_8_15:8;
-                uint64_t row_lsb:3;
-                uint64_t reserved_19_63:45;
-#endif
-        } cn61xx;
-        struct cvmx_lmcx_dual_memcfg_cn61xx cn63xx;
-        struct cvmx_lmcx_dual_memcfg_cn61xx cn63xxp1;
-        struct cvmx_lmcx_dual_memcfg_cn61xx cn66xx;
-        struct cvmx_lmcx_dual_memcfg_cn61xx cn68xx;
-        struct cvmx_lmcx_dual_memcfg_cn61xx cn68xxp1;
-        struct cvmx_lmcx_dual_memcfg_cn61xx cnf71xx;
-};
-
-union cvmx_lmcx_ecc_synd {
-        uint64_t u64;
-        struct cvmx_lmcx_ecc_synd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t mrdsyn3:8;
-                uint64_t mrdsyn2:8;
-                uint64_t mrdsyn1:8;
-                uint64_t mrdsyn0:8;
-#else
-                uint64_t mrdsyn0:8;
-                uint64_t mrdsyn1:8;
-                uint64_t mrdsyn2:8;
-                uint64_t mrdsyn3:8;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_ecc_synd_s cn30xx;
-        struct cvmx_lmcx_ecc_synd_s cn31xx;
-        struct cvmx_lmcx_ecc_synd_s cn38xx;
-        struct cvmx_lmcx_ecc_synd_s cn38xxp2;
-        struct cvmx_lmcx_ecc_synd_s cn50xx;
-        struct cvmx_lmcx_ecc_synd_s cn52xx;
-        struct cvmx_lmcx_ecc_synd_s cn52xxp1;
-        struct cvmx_lmcx_ecc_synd_s cn56xx;
-        struct cvmx_lmcx_ecc_synd_s cn56xxp1;
-        struct cvmx_lmcx_ecc_synd_s cn58xx;
-        struct cvmx_lmcx_ecc_synd_s cn58xxp1;
-        struct cvmx_lmcx_ecc_synd_s cn61xx;
-        struct cvmx_lmcx_ecc_synd_s cn63xx;
-        struct cvmx_lmcx_ecc_synd_s cn63xxp1;
-        struct cvmx_lmcx_ecc_synd_s cn66xx;
-        struct cvmx_lmcx_ecc_synd_s cn68xx;
-        struct cvmx_lmcx_ecc_synd_s cn68xxp1;
-        struct cvmx_lmcx_ecc_synd_s cnf71xx;
-};
-
-union cvmx_lmcx_fadr {
-        uint64_t u64;
-        struct cvmx_lmcx_fadr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_lmcx_fadr_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t fdimm:2;
-                uint64_t fbunk:1;
-                uint64_t fbank:3;
-                uint64_t frow:14;
-                uint64_t fcol:12;
-#else
-                uint64_t fcol:12;
-                uint64_t frow:14;
-                uint64_t fbank:3;
-                uint64_t fbunk:1;
-                uint64_t fdimm:2;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn30xx;
-        struct cvmx_lmcx_fadr_cn30xx cn31xx;
-        struct cvmx_lmcx_fadr_cn30xx cn38xx;
-        struct cvmx_lmcx_fadr_cn30xx cn38xxp2;
-        struct cvmx_lmcx_fadr_cn30xx cn50xx;
-        struct cvmx_lmcx_fadr_cn30xx cn52xx;
-        struct cvmx_lmcx_fadr_cn30xx cn52xxp1;
-        struct cvmx_lmcx_fadr_cn30xx cn56xx;
-        struct cvmx_lmcx_fadr_cn30xx cn56xxp1;
-        struct cvmx_lmcx_fadr_cn30xx cn58xx;
-        struct cvmx_lmcx_fadr_cn30xx cn58xxp1;
-        struct cvmx_lmcx_fadr_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_36_63:28;
-                uint64_t fdimm:2;
-                uint64_t fbunk:1;
-                uint64_t fbank:3;
-                uint64_t frow:16;
-                uint64_t fcol:14;
-#else
-                uint64_t fcol:14;
-                uint64_t frow:16;
-                uint64_t fbank:3;
-                uint64_t fbunk:1;
-                uint64_t fdimm:2;
-                uint64_t reserved_36_63:28;
-#endif
-        } cn61xx;
-        struct cvmx_lmcx_fadr_cn61xx cn63xx;
-        struct cvmx_lmcx_fadr_cn61xx cn63xxp1;
-        struct cvmx_lmcx_fadr_cn61xx cn66xx;
-        struct cvmx_lmcx_fadr_cn61xx cn68xx;
-        struct cvmx_lmcx_fadr_cn61xx cn68xxp1;
-        struct cvmx_lmcx_fadr_cn61xx cnf71xx;
-};
-
-union cvmx_lmcx_ifb_cnt {
-        uint64_t u64;
-        struct cvmx_lmcx_ifb_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t ifbcnt:64;
-#else
-                uint64_t ifbcnt:64;
-#endif
-        } s;
-        struct cvmx_lmcx_ifb_cnt_s cn61xx;
-        struct cvmx_lmcx_ifb_cnt_s cn63xx;
-        struct cvmx_lmcx_ifb_cnt_s cn63xxp1;
-        struct cvmx_lmcx_ifb_cnt_s cn66xx;
-        struct cvmx_lmcx_ifb_cnt_s cn68xx;
-        struct cvmx_lmcx_ifb_cnt_s cn68xxp1;
-        struct cvmx_lmcx_ifb_cnt_s cnf71xx;
-};
-
-union cvmx_lmcx_ifb_cnt_hi {
-        uint64_t u64;
-        struct cvmx_lmcx_ifb_cnt_hi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ifbcnt_hi:32;
-#else
-                uint64_t ifbcnt_hi:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn30xx;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn31xx;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn38xx;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn38xxp2;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn50xx;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn52xx;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn52xxp1;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn56xx;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn56xxp1;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn58xx;
-        struct cvmx_lmcx_ifb_cnt_hi_s cn58xxp1;
-};
-
-union cvmx_lmcx_ifb_cnt_lo {
-        uint64_t u64;
-        struct cvmx_lmcx_ifb_cnt_lo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ifbcnt_lo:32;
-#else
-                uint64_t ifbcnt_lo:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn30xx;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn31xx;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn38xx;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn38xxp2;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn50xx;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn52xx;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn52xxp1;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn56xx;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn56xxp1;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn58xx;
-        struct cvmx_lmcx_ifb_cnt_lo_s cn58xxp1;
-};
-
-union cvmx_lmcx_int {
-        uint64_t u64;
-        struct cvmx_lmcx_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t ded_err:4;
-                uint64_t sec_err:4;
-                uint64_t nxm_wr_err:1;
-#else
-                uint64_t nxm_wr_err:1;
-                uint64_t sec_err:4;
-                uint64_t ded_err:4;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_lmcx_int_s cn61xx;
-        struct cvmx_lmcx_int_s cn63xx;
-        struct cvmx_lmcx_int_s cn63xxp1;
-        struct cvmx_lmcx_int_s cn66xx;
-        struct cvmx_lmcx_int_s cn68xx;
-        struct cvmx_lmcx_int_s cn68xxp1;
-        struct cvmx_lmcx_int_s cnf71xx;
-};
-
-union cvmx_lmcx_int_en {
-        uint64_t u64;
-        struct cvmx_lmcx_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t intr_ded_ena:1;
-                uint64_t intr_sec_ena:1;
-                uint64_t intr_nxm_wr_ena:1;
-#else
-                uint64_t intr_nxm_wr_ena:1;
-                uint64_t intr_sec_ena:1;
-                uint64_t intr_ded_ena:1;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_lmcx_int_en_s cn61xx;
-        struct cvmx_lmcx_int_en_s cn63xx;
-        struct cvmx_lmcx_int_en_s cn63xxp1;
-        struct cvmx_lmcx_int_en_s cn66xx;
-        struct cvmx_lmcx_int_en_s cn68xx;
-        struct cvmx_lmcx_int_en_s cn68xxp1;
-        struct cvmx_lmcx_int_en_s cnf71xx;
-};
-
-union cvmx_lmcx_mem_cfg0 {
-        uint64_t u64;
-        struct cvmx_lmcx_mem_cfg0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t reset:1;
-                uint64_t silo_qc:1;
-                uint64_t bunk_ena:1;
-                uint64_t ded_err:4;
-                uint64_t sec_err:4;
-                uint64_t intr_ded_ena:1;
-                uint64_t intr_sec_ena:1;
-                uint64_t tcl:4;
-                uint64_t ref_int:6;
-                uint64_t pbank_lsb:4;
-                uint64_t row_lsb:3;
-                uint64_t ecc_ena:1;
-                uint64_t init_start:1;
-#else
-                uint64_t init_start:1;
-                uint64_t ecc_ena:1;
-                uint64_t row_lsb:3;
-                uint64_t pbank_lsb:4;
-                uint64_t ref_int:6;
-                uint64_t tcl:4;
-                uint64_t intr_sec_ena:1;
-                uint64_t intr_ded_ena:1;
-                uint64_t sec_err:4;
-                uint64_t ded_err:4;
-                uint64_t bunk_ena:1;
-                uint64_t silo_qc:1;
-                uint64_t reset:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_mem_cfg0_s cn30xx;
-        struct cvmx_lmcx_mem_cfg0_s cn31xx;
-        struct cvmx_lmcx_mem_cfg0_s cn38xx;
-        struct cvmx_lmcx_mem_cfg0_s cn38xxp2;
-        struct cvmx_lmcx_mem_cfg0_s cn50xx;
-        struct cvmx_lmcx_mem_cfg0_s cn52xx;
-        struct cvmx_lmcx_mem_cfg0_s cn52xxp1;
-        struct cvmx_lmcx_mem_cfg0_s cn56xx;
-        struct cvmx_lmcx_mem_cfg0_s cn56xxp1;
-        struct cvmx_lmcx_mem_cfg0_s cn58xx;
-        struct cvmx_lmcx_mem_cfg0_s cn58xxp1;
-};
-
-union cvmx_lmcx_mem_cfg1 {
-        uint64_t u64;
-        struct cvmx_lmcx_mem_cfg1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t comp_bypass:1;
-                uint64_t trrd:3;
-                uint64_t caslat:3;
-                uint64_t tmrd:3;
-                uint64_t trfc:5;
-                uint64_t trp:4;
-                uint64_t twtr:4;
-                uint64_t trcd:4;
-                uint64_t tras:5;
-#else
-                uint64_t tras:5;
-                uint64_t trcd:4;
-                uint64_t twtr:4;
-                uint64_t trp:4;
-                uint64_t trfc:5;
-                uint64_t tmrd:3;
-                uint64_t caslat:3;
-                uint64_t trrd:3;
-                uint64_t comp_bypass:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_mem_cfg1_s cn30xx;
-        struct cvmx_lmcx_mem_cfg1_s cn31xx;
-        struct cvmx_lmcx_mem_cfg1_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_31_63:33;
-                uint64_t trrd:3;
-                uint64_t caslat:3;
-                uint64_t tmrd:3;
-                uint64_t trfc:5;
-                uint64_t trp:4;
-                uint64_t twtr:4;
-                uint64_t trcd:4;
-                uint64_t tras:5;
-#else
-                uint64_t tras:5;
-                uint64_t trcd:4;
-                uint64_t twtr:4;
-                uint64_t trp:4;
-                uint64_t trfc:5;
-                uint64_t tmrd:3;
-                uint64_t caslat:3;
-                uint64_t trrd:3;
-                uint64_t reserved_31_63:33;
-#endif
-        } cn38xx;
-        struct cvmx_lmcx_mem_cfg1_cn38xx cn38xxp2;
-        struct cvmx_lmcx_mem_cfg1_s cn50xx;
-        struct cvmx_lmcx_mem_cfg1_cn38xx cn52xx;
-        struct cvmx_lmcx_mem_cfg1_cn38xx cn52xxp1;
-        struct cvmx_lmcx_mem_cfg1_cn38xx cn56xx;
-        struct cvmx_lmcx_mem_cfg1_cn38xx cn56xxp1;
-        struct cvmx_lmcx_mem_cfg1_cn38xx cn58xx;
-        struct cvmx_lmcx_mem_cfg1_cn38xx cn58xxp1;
-};
-
-union cvmx_lmcx_modereg_params0 {
-        uint64_t u64;
-        struct cvmx_lmcx_modereg_params0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t ppd:1;
-                uint64_t wrp:3;
-                uint64_t dllr:1;
-                uint64_t tm:1;
-                uint64_t rbt:1;
-                uint64_t cl:4;
-                uint64_t bl:2;
-                uint64_t qoff:1;
-                uint64_t tdqs:1;
-                uint64_t wlev:1;
-                uint64_t al:2;
-                uint64_t dll:1;
-                uint64_t mpr:1;
-                uint64_t mprloc:2;
-                uint64_t cwl:3;
-#else
-                uint64_t cwl:3;
-                uint64_t mprloc:2;
-                uint64_t mpr:1;
-                uint64_t dll:1;
-                uint64_t al:2;
-                uint64_t wlev:1;
-                uint64_t tdqs:1;
-                uint64_t qoff:1;
-                uint64_t bl:2;
-                uint64_t cl:4;
-                uint64_t rbt:1;
-                uint64_t tm:1;
-                uint64_t dllr:1;
-                uint64_t wrp:3;
-                uint64_t ppd:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_lmcx_modereg_params0_s cn61xx;
-        struct cvmx_lmcx_modereg_params0_s cn63xx;
-        struct cvmx_lmcx_modereg_params0_s cn63xxp1;
-        struct cvmx_lmcx_modereg_params0_s cn66xx;
-        struct cvmx_lmcx_modereg_params0_s cn68xx;
-        struct cvmx_lmcx_modereg_params0_s cn68xxp1;
-        struct cvmx_lmcx_modereg_params0_s cnf71xx;
-};
-
-union cvmx_lmcx_modereg_params1 {
-        uint64_t u64;
-        struct cvmx_lmcx_modereg_params1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t rtt_nom_11:3;
-                uint64_t dic_11:2;
-                uint64_t rtt_wr_11:2;
-                uint64_t srt_11:1;
-                uint64_t asr_11:1;
-                uint64_t pasr_11:3;
-                uint64_t rtt_nom_10:3;
-                uint64_t dic_10:2;
-                uint64_t rtt_wr_10:2;
-                uint64_t srt_10:1;
-                uint64_t asr_10:1;
-                uint64_t pasr_10:3;
-                uint64_t rtt_nom_01:3;
-                uint64_t dic_01:2;
-                uint64_t rtt_wr_01:2;
-                uint64_t srt_01:1;
-                uint64_t asr_01:1;
-                uint64_t pasr_01:3;
-                uint64_t rtt_nom_00:3;
-                uint64_t dic_00:2;
-                uint64_t rtt_wr_00:2;
-                uint64_t srt_00:1;
-                uint64_t asr_00:1;
-                uint64_t pasr_00:3;
-#else
-                uint64_t pasr_00:3;
-                uint64_t asr_00:1;
-                uint64_t srt_00:1;
-                uint64_t rtt_wr_00:2;
-                uint64_t dic_00:2;
-                uint64_t rtt_nom_00:3;
-                uint64_t pasr_01:3;
-                uint64_t asr_01:1;
-                uint64_t srt_01:1;
-                uint64_t rtt_wr_01:2;
-                uint64_t dic_01:2;
-                uint64_t rtt_nom_01:3;
-                uint64_t pasr_10:3;
-                uint64_t asr_10:1;
-                uint64_t srt_10:1;
-                uint64_t rtt_wr_10:2;
-                uint64_t dic_10:2;
-                uint64_t rtt_nom_10:3;
-                uint64_t pasr_11:3;
-                uint64_t asr_11:1;
-                uint64_t srt_11:1;
-                uint64_t rtt_wr_11:2;
-                uint64_t dic_11:2;
-                uint64_t rtt_nom_11:3;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_lmcx_modereg_params1_s cn61xx;
-        struct cvmx_lmcx_modereg_params1_s cn63xx;
-        struct cvmx_lmcx_modereg_params1_s cn63xxp1;
-        struct cvmx_lmcx_modereg_params1_s cn66xx;
-        struct cvmx_lmcx_modereg_params1_s cn68xx;
-        struct cvmx_lmcx_modereg_params1_s cn68xxp1;
-        struct cvmx_lmcx_modereg_params1_s cnf71xx;
-};
-
-union cvmx_lmcx_nxm {
-        uint64_t u64;
-        struct cvmx_lmcx_nxm_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_40_63:24;
-                uint64_t mem_msb_d3_r1:4;
-                uint64_t mem_msb_d3_r0:4;
-                uint64_t mem_msb_d2_r1:4;
-                uint64_t mem_msb_d2_r0:4;
-                uint64_t mem_msb_d1_r1:4;
-                uint64_t mem_msb_d1_r0:4;
-                uint64_t mem_msb_d0_r1:4;
-                uint64_t mem_msb_d0_r0:4;
-                uint64_t cs_mask:8;
-#else
-                uint64_t cs_mask:8;
-                uint64_t mem_msb_d0_r0:4;
-                uint64_t mem_msb_d0_r1:4;
-                uint64_t mem_msb_d1_r0:4;
-                uint64_t mem_msb_d1_r1:4;
-                uint64_t mem_msb_d2_r0:4;
-                uint64_t mem_msb_d2_r1:4;
-                uint64_t mem_msb_d3_r0:4;
-                uint64_t mem_msb_d3_r1:4;
-                uint64_t reserved_40_63:24;
-#endif
-        } s;
-        struct cvmx_lmcx_nxm_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t cs_mask:8;
-#else
-                uint64_t cs_mask:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } cn52xx;
-        struct cvmx_lmcx_nxm_cn52xx cn56xx;
-        struct cvmx_lmcx_nxm_cn52xx cn58xx;
-        struct cvmx_lmcx_nxm_s cn61xx;
-        struct cvmx_lmcx_nxm_s cn63xx;
-        struct cvmx_lmcx_nxm_s cn63xxp1;
-        struct cvmx_lmcx_nxm_s cn66xx;
-        struct cvmx_lmcx_nxm_s cn68xx;
-        struct cvmx_lmcx_nxm_s cn68xxp1;
-        struct cvmx_lmcx_nxm_s cnf71xx;
-};
-
-union cvmx_lmcx_ops_cnt {
-        uint64_t u64;
-        struct cvmx_lmcx_ops_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t opscnt:64;
-#else
-                uint64_t opscnt:64;
-#endif
-        } s;
-        struct cvmx_lmcx_ops_cnt_s cn61xx;
-        struct cvmx_lmcx_ops_cnt_s cn63xx;
-        struct cvmx_lmcx_ops_cnt_s cn63xxp1;
-        struct cvmx_lmcx_ops_cnt_s cn66xx;
-        struct cvmx_lmcx_ops_cnt_s cn68xx;
-        struct cvmx_lmcx_ops_cnt_s cn68xxp1;
-        struct cvmx_lmcx_ops_cnt_s cnf71xx;
-};
-
-union cvmx_lmcx_ops_cnt_hi {
-        uint64_t u64;
-        struct cvmx_lmcx_ops_cnt_hi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t opscnt_hi:32;
-#else
-                uint64_t opscnt_hi:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_ops_cnt_hi_s cn30xx;
-        struct cvmx_lmcx_ops_cnt_hi_s cn31xx;
-        struct cvmx_lmcx_ops_cnt_hi_s cn38xx;
-        struct cvmx_lmcx_ops_cnt_hi_s cn38xxp2;
-        struct cvmx_lmcx_ops_cnt_hi_s cn50xx;
-        struct cvmx_lmcx_ops_cnt_hi_s cn52xx;
-        struct cvmx_lmcx_ops_cnt_hi_s cn52xxp1;
-        struct cvmx_lmcx_ops_cnt_hi_s cn56xx;
-        struct cvmx_lmcx_ops_cnt_hi_s cn56xxp1;
-        struct cvmx_lmcx_ops_cnt_hi_s cn58xx;
-        struct cvmx_lmcx_ops_cnt_hi_s cn58xxp1;
-};
-
-union cvmx_lmcx_ops_cnt_lo {
-        uint64_t u64;
-        struct cvmx_lmcx_ops_cnt_lo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t opscnt_lo:32;
-#else
-                uint64_t opscnt_lo:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_ops_cnt_lo_s cn30xx;
-        struct cvmx_lmcx_ops_cnt_lo_s cn31xx;
-        struct cvmx_lmcx_ops_cnt_lo_s cn38xx;
-        struct cvmx_lmcx_ops_cnt_lo_s cn38xxp2;
-        struct cvmx_lmcx_ops_cnt_lo_s cn50xx;
-        struct cvmx_lmcx_ops_cnt_lo_s cn52xx;
-        struct cvmx_lmcx_ops_cnt_lo_s cn52xxp1;
-        struct cvmx_lmcx_ops_cnt_lo_s cn56xx;
-        struct cvmx_lmcx_ops_cnt_lo_s cn56xxp1;
-        struct cvmx_lmcx_ops_cnt_lo_s cn58xx;
-        struct cvmx_lmcx_ops_cnt_lo_s cn58xxp1;
-};
-
-union cvmx_lmcx_phy_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_phy_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t rx_always_on:1;
-                uint64_t lv_mode:1;
-                uint64_t ck_tune1:1;
-                uint64_t ck_dlyout1:4;
-                uint64_t ck_tune0:1;
-                uint64_t ck_dlyout0:4;
-                uint64_t loopback:1;
-                uint64_t loopback_pos:1;
-                uint64_t ts_stagger:1;
-#else
-                uint64_t ts_stagger:1;
-                uint64_t loopback_pos:1;
-                uint64_t loopback:1;
-                uint64_t ck_dlyout0:4;
-                uint64_t ck_tune0:1;
-                uint64_t ck_dlyout1:4;
-                uint64_t ck_tune1:1;
-                uint64_t lv_mode:1;
-                uint64_t rx_always_on:1;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_lmcx_phy_ctl_s cn61xx;
-        struct cvmx_lmcx_phy_ctl_s cn63xx;
-        struct cvmx_lmcx_phy_ctl_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t lv_mode:1;
-                uint64_t ck_tune1:1;
-                uint64_t ck_dlyout1:4;
-                uint64_t ck_tune0:1;
-                uint64_t ck_dlyout0:4;
-                uint64_t loopback:1;
-                uint64_t loopback_pos:1;
-                uint64_t ts_stagger:1;
-#else
-                uint64_t ts_stagger:1;
-                uint64_t loopback_pos:1;
-                uint64_t loopback:1;
-                uint64_t ck_dlyout0:4;
-                uint64_t ck_tune0:1;
-                uint64_t ck_dlyout1:4;
-                uint64_t ck_tune1:1;
-                uint64_t lv_mode:1;
-                uint64_t reserved_14_63:50;
-#endif
-        } cn63xxp1;
-        struct cvmx_lmcx_phy_ctl_s cn66xx;
-        struct cvmx_lmcx_phy_ctl_s cn68xx;
-        struct cvmx_lmcx_phy_ctl_s cn68xxp1;
-        struct cvmx_lmcx_phy_ctl_s cnf71xx;
-};
-
-union cvmx_lmcx_pll_bwctl {
-        uint64_t u64;
-        struct cvmx_lmcx_pll_bwctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t bwupd:1;
-                uint64_t bwctl:4;
-#else
-                uint64_t bwctl:4;
-                uint64_t bwupd:1;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_lmcx_pll_bwctl_s cn30xx;
-        struct cvmx_lmcx_pll_bwctl_s cn31xx;
-        struct cvmx_lmcx_pll_bwctl_s cn38xx;
-        struct cvmx_lmcx_pll_bwctl_s cn38xxp2;
-};
-
-union cvmx_lmcx_pll_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_pll_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_30_63:34;
-                uint64_t bypass:1;
-                uint64_t fasten_n:1;
-                uint64_t div_reset:1;
-                uint64_t reset_n:1;
-                uint64_t clkf:12;
-                uint64_t clkr:6;
-                uint64_t reserved_6_7:2;
-                uint64_t en16:1;
-                uint64_t en12:1;
-                uint64_t en8:1;
-                uint64_t en6:1;
-                uint64_t en4:1;
-                uint64_t en2:1;
-#else
-                uint64_t en2:1;
-                uint64_t en4:1;
-                uint64_t en6:1;
-                uint64_t en8:1;
-                uint64_t en12:1;
-                uint64_t en16:1;
-                uint64_t reserved_6_7:2;
-                uint64_t clkr:6;
-                uint64_t clkf:12;
-                uint64_t reset_n:1;
-                uint64_t div_reset:1;
-                uint64_t fasten_n:1;
-                uint64_t bypass:1;
-                uint64_t reserved_30_63:34;
-#endif
-        } s;
-        struct cvmx_lmcx_pll_ctl_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t fasten_n:1;
-                uint64_t div_reset:1;
-                uint64_t reset_n:1;
-                uint64_t clkf:12;
-                uint64_t clkr:6;
-                uint64_t reserved_6_7:2;
-                uint64_t en16:1;
-                uint64_t en12:1;
-                uint64_t en8:1;
-                uint64_t en6:1;
-                uint64_t en4:1;
-                uint64_t en2:1;
-#else
-                uint64_t en2:1;
-                uint64_t en4:1;
-                uint64_t en6:1;
-                uint64_t en8:1;
-                uint64_t en12:1;
-                uint64_t en16:1;
-                uint64_t reserved_6_7:2;
-                uint64_t clkr:6;
-                uint64_t clkf:12;
-                uint64_t reset_n:1;
-                uint64_t div_reset:1;
-                uint64_t fasten_n:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn50xx;
-        struct cvmx_lmcx_pll_ctl_s cn52xx;
-        struct cvmx_lmcx_pll_ctl_s cn52xxp1;
-        struct cvmx_lmcx_pll_ctl_cn50xx cn56xx;
-        struct cvmx_lmcx_pll_ctl_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t div_reset:1;
-                uint64_t reset_n:1;
-                uint64_t clkf:12;
-                uint64_t clkr:6;
-                uint64_t reserved_6_7:2;
-                uint64_t en16:1;
-                uint64_t en12:1;
-                uint64_t en8:1;
-                uint64_t en6:1;
-                uint64_t en4:1;
-                uint64_t en2:1;
-#else
-                uint64_t en2:1;
-                uint64_t en4:1;
-                uint64_t en6:1;
-                uint64_t en8:1;
-                uint64_t en12:1;
-                uint64_t en16:1;
-                uint64_t reserved_6_7:2;
-                uint64_t clkr:6;
-                uint64_t clkf:12;
-                uint64_t reset_n:1;
-                uint64_t div_reset:1;
-                uint64_t reserved_28_63:36;
-#endif
-        } cn56xxp1;
-        struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xx;
-        struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xxp1;
-};
-
-union cvmx_lmcx_pll_status {
-        uint64_t u64;
-        struct cvmx_lmcx_pll_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ddr__nctl:5;
-                uint64_t ddr__pctl:5;
-                uint64_t reserved_2_21:20;
-                uint64_t rfslip:1;
-                uint64_t fbslip:1;
-#else
-                uint64_t fbslip:1;
-                uint64_t rfslip:1;
-                uint64_t reserved_2_21:20;
-                uint64_t ddr__pctl:5;
-                uint64_t ddr__nctl:5;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_pll_status_s cn50xx;
-        struct cvmx_lmcx_pll_status_s cn52xx;
-        struct cvmx_lmcx_pll_status_s cn52xxp1;
-        struct cvmx_lmcx_pll_status_s cn56xx;
-        struct cvmx_lmcx_pll_status_s cn56xxp1;
-        struct cvmx_lmcx_pll_status_s cn58xx;
-        struct cvmx_lmcx_pll_status_cn58xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t rfslip:1;
-                uint64_t fbslip:1;
-#else
-                uint64_t fbslip:1;
-                uint64_t rfslip:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } cn58xxp1;
-};
-
-union cvmx_lmcx_read_level_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_read_level_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t rankmask:4;
-                uint64_t pattern:8;
-                uint64_t row:16;
-                uint64_t col:12;
-                uint64_t reserved_3_3:1;
-                uint64_t bnk:3;
-#else
-                uint64_t bnk:3;
-                uint64_t reserved_3_3:1;
-                uint64_t col:12;
-                uint64_t row:16;
-                uint64_t pattern:8;
-                uint64_t rankmask:4;
-                uint64_t reserved_44_63:20;
-#endif
-        } s;
-        struct cvmx_lmcx_read_level_ctl_s cn52xx;
-        struct cvmx_lmcx_read_level_ctl_s cn52xxp1;
-        struct cvmx_lmcx_read_level_ctl_s cn56xx;
-        struct cvmx_lmcx_read_level_ctl_s cn56xxp1;
-};
-
-union cvmx_lmcx_read_level_dbg {
-        uint64_t u64;
-        struct cvmx_lmcx_read_level_dbg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t bitmask:16;
-                uint64_t reserved_4_15:12;
-                uint64_t byte:4;
-#else
-                uint64_t byte:4;
-                uint64_t reserved_4_15:12;
-                uint64_t bitmask:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_read_level_dbg_s cn52xx;
-        struct cvmx_lmcx_read_level_dbg_s cn52xxp1;
-        struct cvmx_lmcx_read_level_dbg_s cn56xx;
-        struct cvmx_lmcx_read_level_dbg_s cn56xxp1;
-};
-
-union cvmx_lmcx_read_level_rankx {
-        uint64_t u64;
-        struct cvmx_lmcx_read_level_rankx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_38_63:26;
-                uint64_t status:2;
-                uint64_t byte8:4;
-                uint64_t byte7:4;
-                uint64_t byte6:4;
-                uint64_t byte5:4;
-                uint64_t byte4:4;
-                uint64_t byte3:4;
-                uint64_t byte2:4;
-                uint64_t byte1:4;
-                uint64_t byte0:4;
-#else
-                uint64_t byte0:4;
-                uint64_t byte1:4;
-                uint64_t byte2:4;
-                uint64_t byte3:4;
-                uint64_t byte4:4;
-                uint64_t byte5:4;
-                uint64_t byte6:4;
-                uint64_t byte7:4;
-                uint64_t byte8:4;
-                uint64_t status:2;
-                uint64_t reserved_38_63:26;
-#endif
-        } s;
-        struct cvmx_lmcx_read_level_rankx_s cn52xx;
-        struct cvmx_lmcx_read_level_rankx_s cn52xxp1;
-        struct cvmx_lmcx_read_level_rankx_s cn56xx;
-        struct cvmx_lmcx_read_level_rankx_s cn56xxp1;
-};
-
-union cvmx_lmcx_reset_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_reset_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t ddr3psv:1;
-                uint64_t ddr3psoft:1;
-                uint64_t ddr3pwarm:1;
-                uint64_t ddr3rst:1;
-#else
-                uint64_t ddr3rst:1;
-                uint64_t ddr3pwarm:1;
-                uint64_t ddr3psoft:1;
-                uint64_t ddr3psv:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_lmcx_reset_ctl_s cn61xx;
-        struct cvmx_lmcx_reset_ctl_s cn63xx;
-        struct cvmx_lmcx_reset_ctl_s cn63xxp1;
-        struct cvmx_lmcx_reset_ctl_s cn66xx;
-        struct cvmx_lmcx_reset_ctl_s cn68xx;
-        struct cvmx_lmcx_reset_ctl_s cn68xxp1;
-        struct cvmx_lmcx_reset_ctl_s cnf71xx;
-};
-
-union cvmx_lmcx_rlevel_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_rlevel_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t delay_unload_3:1;
-                uint64_t delay_unload_2:1;
-                uint64_t delay_unload_1:1;
-                uint64_t delay_unload_0:1;
-                uint64_t bitmask:8;
-                uint64_t or_dis:1;
-                uint64_t offset_en:1;
-                uint64_t offset:4;
-                uint64_t byte:4;
-#else
-                uint64_t byte:4;
-                uint64_t offset:4;
-                uint64_t offset_en:1;
-                uint64_t or_dis:1;
-                uint64_t bitmask:8;
-                uint64_t delay_unload_0:1;
-                uint64_t delay_unload_1:1;
-                uint64_t delay_unload_2:1;
-                uint64_t delay_unload_3:1;
-                uint64_t reserved_22_63:42;
-#endif
-        } s;
-        struct cvmx_lmcx_rlevel_ctl_s cn61xx;
-        struct cvmx_lmcx_rlevel_ctl_s cn63xx;
-        struct cvmx_lmcx_rlevel_ctl_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t offset_en:1;
-                uint64_t offset:4;
-                uint64_t byte:4;
-#else
-                uint64_t byte:4;
-                uint64_t offset:4;
-                uint64_t offset_en:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn63xxp1;
-        struct cvmx_lmcx_rlevel_ctl_s cn66xx;
-        struct cvmx_lmcx_rlevel_ctl_s cn68xx;
-        struct cvmx_lmcx_rlevel_ctl_s cn68xxp1;
-        struct cvmx_lmcx_rlevel_ctl_s cnf71xx;
-};
-
-union cvmx_lmcx_rlevel_dbg {
-        uint64_t u64;
-        struct cvmx_lmcx_rlevel_dbg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bitmask:64;
-#else
-                uint64_t bitmask:64;
-#endif
-        } s;
-        struct cvmx_lmcx_rlevel_dbg_s cn61xx;
-        struct cvmx_lmcx_rlevel_dbg_s cn63xx;
-        struct cvmx_lmcx_rlevel_dbg_s cn63xxp1;
-        struct cvmx_lmcx_rlevel_dbg_s cn66xx;
-        struct cvmx_lmcx_rlevel_dbg_s cn68xx;
-        struct cvmx_lmcx_rlevel_dbg_s cn68xxp1;
-        struct cvmx_lmcx_rlevel_dbg_s cnf71xx;
-};
-
-union cvmx_lmcx_rlevel_rankx {
-        uint64_t u64;
-        struct cvmx_lmcx_rlevel_rankx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t status:2;
-                uint64_t byte8:6;
-                uint64_t byte7:6;
-                uint64_t byte6:6;
-                uint64_t byte5:6;
-                uint64_t byte4:6;
-                uint64_t byte3:6;
-                uint64_t byte2:6;
-                uint64_t byte1:6;
-                uint64_t byte0:6;
-#else
-                uint64_t byte0:6;
-                uint64_t byte1:6;
-                uint64_t byte2:6;
-                uint64_t byte3:6;
-                uint64_t byte4:6;
-                uint64_t byte5:6;
-                uint64_t byte6:6;
-                uint64_t byte7:6;
-                uint64_t byte8:6;
-                uint64_t status:2;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_lmcx_rlevel_rankx_s cn61xx;
-        struct cvmx_lmcx_rlevel_rankx_s cn63xx;
-        struct cvmx_lmcx_rlevel_rankx_s cn63xxp1;
-        struct cvmx_lmcx_rlevel_rankx_s cn66xx;
-        struct cvmx_lmcx_rlevel_rankx_s cn68xx;
-        struct cvmx_lmcx_rlevel_rankx_s cn68xxp1;
-        struct cvmx_lmcx_rlevel_rankx_s cnf71xx;
-};
-
-union cvmx_lmcx_rodt_comp_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_rodt_comp_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t enable:1;
-                uint64_t reserved_12_15:4;
-                uint64_t nctl:4;
-                uint64_t reserved_5_7:3;
-                uint64_t pctl:5;
-#else
-                uint64_t pctl:5;
-                uint64_t reserved_5_7:3;
-                uint64_t nctl:4;
-                uint64_t reserved_12_15:4;
-                uint64_t enable:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_lmcx_rodt_comp_ctl_s cn50xx;
-        struct cvmx_lmcx_rodt_comp_ctl_s cn52xx;
-        struct cvmx_lmcx_rodt_comp_ctl_s cn52xxp1;
-        struct cvmx_lmcx_rodt_comp_ctl_s cn56xx;
-        struct cvmx_lmcx_rodt_comp_ctl_s cn56xxp1;
-        struct cvmx_lmcx_rodt_comp_ctl_s cn58xx;
-        struct cvmx_lmcx_rodt_comp_ctl_s cn58xxp1;
-};
-
-union cvmx_lmcx_rodt_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_rodt_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t rodt_hi3:4;
-                uint64_t rodt_hi2:4;
-                uint64_t rodt_hi1:4;
-                uint64_t rodt_hi0:4;
-                uint64_t rodt_lo3:4;
-                uint64_t rodt_lo2:4;
-                uint64_t rodt_lo1:4;
-                uint64_t rodt_lo0:4;
-#else
-                uint64_t rodt_lo0:4;
-                uint64_t rodt_lo1:4;
-                uint64_t rodt_lo2:4;
-                uint64_t rodt_lo3:4;
-                uint64_t rodt_hi0:4;
-                uint64_t rodt_hi1:4;
-                uint64_t rodt_hi2:4;
-                uint64_t rodt_hi3:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_rodt_ctl_s cn30xx;
-        struct cvmx_lmcx_rodt_ctl_s cn31xx;
-        struct cvmx_lmcx_rodt_ctl_s cn38xx;
-        struct cvmx_lmcx_rodt_ctl_s cn38xxp2;
-        struct cvmx_lmcx_rodt_ctl_s cn50xx;
-        struct cvmx_lmcx_rodt_ctl_s cn52xx;
-        struct cvmx_lmcx_rodt_ctl_s cn52xxp1;
-        struct cvmx_lmcx_rodt_ctl_s cn56xx;
-        struct cvmx_lmcx_rodt_ctl_s cn56xxp1;
-        struct cvmx_lmcx_rodt_ctl_s cn58xx;
-        struct cvmx_lmcx_rodt_ctl_s cn58xxp1;
-};
-
-union cvmx_lmcx_rodt_mask {
-        uint64_t u64;
-        struct cvmx_lmcx_rodt_mask_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rodt_d3_r1:8;
-                uint64_t rodt_d3_r0:8;
-                uint64_t rodt_d2_r1:8;
-                uint64_t rodt_d2_r0:8;
-                uint64_t rodt_d1_r1:8;
-                uint64_t rodt_d1_r0:8;
-                uint64_t rodt_d0_r1:8;
-                uint64_t rodt_d0_r0:8;
-#else
-                uint64_t rodt_d0_r0:8;
-                uint64_t rodt_d0_r1:8;
-                uint64_t rodt_d1_r0:8;
-                uint64_t rodt_d1_r1:8;
-                uint64_t rodt_d2_r0:8;
-                uint64_t rodt_d2_r1:8;
-                uint64_t rodt_d3_r0:8;
-                uint64_t rodt_d3_r1:8;
-#endif
-        } s;
-        struct cvmx_lmcx_rodt_mask_s cn61xx;
-        struct cvmx_lmcx_rodt_mask_s cn63xx;
-        struct cvmx_lmcx_rodt_mask_s cn63xxp1;
-        struct cvmx_lmcx_rodt_mask_s cn66xx;
-        struct cvmx_lmcx_rodt_mask_s cn68xx;
-        struct cvmx_lmcx_rodt_mask_s cn68xxp1;
-        struct cvmx_lmcx_rodt_mask_s cnf71xx;
-};
-
-union cvmx_lmcx_scramble_cfg0 {
-        uint64_t u64;
-        struct cvmx_lmcx_scramble_cfg0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t key:64;
-#else
-                uint64_t key:64;
-#endif
-        } s;
-        struct cvmx_lmcx_scramble_cfg0_s cn61xx;
-        struct cvmx_lmcx_scramble_cfg0_s cn66xx;
-        struct cvmx_lmcx_scramble_cfg0_s cnf71xx;
-};
-
-union cvmx_lmcx_scramble_cfg1 {
-        uint64_t u64;
-        struct cvmx_lmcx_scramble_cfg1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t key:64;
-#else
-                uint64_t key:64;
-#endif
-        } s;
-        struct cvmx_lmcx_scramble_cfg1_s cn61xx;
-        struct cvmx_lmcx_scramble_cfg1_s cn66xx;
-        struct cvmx_lmcx_scramble_cfg1_s cnf71xx;
-};
-
-union cvmx_lmcx_scrambled_fadr {
-        uint64_t u64;
-        struct cvmx_lmcx_scrambled_fadr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_36_63:28;
-                uint64_t fdimm:2;
-                uint64_t fbunk:1;
-                uint64_t fbank:3;
-                uint64_t frow:16;
-                uint64_t fcol:14;
-#else
-                uint64_t fcol:14;
-                uint64_t frow:16;
-                uint64_t fbank:3;
-                uint64_t fbunk:1;
-                uint64_t fdimm:2;
-                uint64_t reserved_36_63:28;
-#endif
-        } s;
-        struct cvmx_lmcx_scrambled_fadr_s cn61xx;
-        struct cvmx_lmcx_scrambled_fadr_s cn66xx;
-        struct cvmx_lmcx_scrambled_fadr_s cnf71xx;
-};
-
-union cvmx_lmcx_slot_ctl0 {
-        uint64_t u64;
-        struct cvmx_lmcx_slot_ctl0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t w2w_init:6;
-                uint64_t w2r_init:6;
-                uint64_t r2w_init:6;
-                uint64_t r2r_init:6;
-#else
-                uint64_t r2r_init:6;
-                uint64_t r2w_init:6;
-                uint64_t w2r_init:6;
-                uint64_t w2w_init:6;
-                uint64_t reserved_24_63:40;
-#endif
-        } s;
-        struct cvmx_lmcx_slot_ctl0_s cn61xx;
-        struct cvmx_lmcx_slot_ctl0_s cn63xx;
-        struct cvmx_lmcx_slot_ctl0_s cn63xxp1;
-        struct cvmx_lmcx_slot_ctl0_s cn66xx;
-        struct cvmx_lmcx_slot_ctl0_s cn68xx;
-        struct cvmx_lmcx_slot_ctl0_s cn68xxp1;
-        struct cvmx_lmcx_slot_ctl0_s cnf71xx;
-};
-
-union cvmx_lmcx_slot_ctl1 {
-        uint64_t u64;
-        struct cvmx_lmcx_slot_ctl1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t w2w_xrank_init:6;
-                uint64_t w2r_xrank_init:6;
-                uint64_t r2w_xrank_init:6;
-                uint64_t r2r_xrank_init:6;
-#else
-                uint64_t r2r_xrank_init:6;
-                uint64_t r2w_xrank_init:6;
-                uint64_t w2r_xrank_init:6;
-                uint64_t w2w_xrank_init:6;
-                uint64_t reserved_24_63:40;
-#endif
-        } s;
-        struct cvmx_lmcx_slot_ctl1_s cn61xx;
-        struct cvmx_lmcx_slot_ctl1_s cn63xx;
-        struct cvmx_lmcx_slot_ctl1_s cn63xxp1;
-        struct cvmx_lmcx_slot_ctl1_s cn66xx;
-        struct cvmx_lmcx_slot_ctl1_s cn68xx;
-        struct cvmx_lmcx_slot_ctl1_s cn68xxp1;
-        struct cvmx_lmcx_slot_ctl1_s cnf71xx;
-};
-
-union cvmx_lmcx_slot_ctl2 {
-        uint64_t u64;
-        struct cvmx_lmcx_slot_ctl2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t w2w_xdimm_init:6;
-                uint64_t w2r_xdimm_init:6;
-                uint64_t r2w_xdimm_init:6;
-                uint64_t r2r_xdimm_init:6;
-#else
-                uint64_t r2r_xdimm_init:6;
-                uint64_t r2w_xdimm_init:6;
-                uint64_t w2r_xdimm_init:6;
-                uint64_t w2w_xdimm_init:6;
-                uint64_t reserved_24_63:40;
-#endif
-        } s;
-        struct cvmx_lmcx_slot_ctl2_s cn61xx;
-        struct cvmx_lmcx_slot_ctl2_s cn63xx;
-        struct cvmx_lmcx_slot_ctl2_s cn63xxp1;
-        struct cvmx_lmcx_slot_ctl2_s cn66xx;
-        struct cvmx_lmcx_slot_ctl2_s cn68xx;
-        struct cvmx_lmcx_slot_ctl2_s cn68xxp1;
-        struct cvmx_lmcx_slot_ctl2_s cnf71xx;
-};
-
-union cvmx_lmcx_timing_params0 {
-        uint64_t u64;
-        struct cvmx_lmcx_timing_params0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_47_63:17;
-                uint64_t trp_ext:1;
-                uint64_t tcksre:4;
-                uint64_t trp:4;
-                uint64_t tzqinit:4;
-                uint64_t tdllk:4;
-                uint64_t tmod:4;
-                uint64_t tmrd:4;
-                uint64_t txpr:4;
-                uint64_t tcke:4;
-                uint64_t tzqcs:4;
-                uint64_t tckeon:10;
-#else
-                uint64_t tckeon:10;
-                uint64_t tzqcs:4;
-                uint64_t tcke:4;
-                uint64_t txpr:4;
-                uint64_t tmrd:4;
-                uint64_t tmod:4;
-                uint64_t tdllk:4;
-                uint64_t tzqinit:4;
-                uint64_t trp:4;
-                uint64_t tcksre:4;
-                uint64_t trp_ext:1;
-                uint64_t reserved_47_63:17;
-#endif
-        } s;
-        struct cvmx_lmcx_timing_params0_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_47_63:17;
-                uint64_t trp_ext:1;
-                uint64_t tcksre:4;
-                uint64_t trp:4;
-                uint64_t tzqinit:4;
-                uint64_t tdllk:4;
-                uint64_t tmod:4;
-                uint64_t tmrd:4;
-                uint64_t txpr:4;
-                uint64_t tcke:4;
-                uint64_t tzqcs:4;
-                uint64_t reserved_0_9:10;
-#else
-                uint64_t reserved_0_9:10;
-                uint64_t tzqcs:4;
-                uint64_t tcke:4;
-                uint64_t txpr:4;
-                uint64_t tmrd:4;
-                uint64_t tmod:4;
-                uint64_t tdllk:4;
-                uint64_t tzqinit:4;
-                uint64_t trp:4;
-                uint64_t tcksre:4;
-                uint64_t trp_ext:1;
-                uint64_t reserved_47_63:17;
-#endif
-        } cn61xx;
-        struct cvmx_lmcx_timing_params0_cn61xx cn63xx;
-        struct cvmx_lmcx_timing_params0_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_46_63:18;
-                uint64_t tcksre:4;
-                uint64_t trp:4;
-                uint64_t tzqinit:4;
-                uint64_t tdllk:4;
-                uint64_t tmod:4;
-                uint64_t tmrd:4;
-                uint64_t txpr:4;
-                uint64_t tcke:4;
-                uint64_t tzqcs:4;
-                uint64_t tckeon:10;
-#else
-                uint64_t tckeon:10;
-                uint64_t tzqcs:4;
-                uint64_t tcke:4;
-                uint64_t txpr:4;
-                uint64_t tmrd:4;
-                uint64_t tmod:4;
-                uint64_t tdllk:4;
-                uint64_t tzqinit:4;
-                uint64_t trp:4;
-                uint64_t tcksre:4;
-                uint64_t reserved_46_63:18;
-#endif
-        } cn63xxp1;
-        struct cvmx_lmcx_timing_params0_cn61xx cn66xx;
-        struct cvmx_lmcx_timing_params0_cn61xx cn68xx;
-        struct cvmx_lmcx_timing_params0_cn61xx cn68xxp1;
-        struct cvmx_lmcx_timing_params0_cn61xx cnf71xx;
-};
-
-union cvmx_lmcx_timing_params1 {
-        uint64_t u64;
-        struct cvmx_lmcx_timing_params1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_47_63:17;
-                uint64_t tras_ext:1;
-                uint64_t txpdll:5;
-                uint64_t tfaw:5;
-                uint64_t twldqsen:4;
-                uint64_t twlmrd:4;
-                uint64_t txp:3;
-                uint64_t trrd:3;
-                uint64_t trfc:5;
-                uint64_t twtr:4;
-                uint64_t trcd:4;
-                uint64_t tras:5;
-                uint64_t tmprr:4;
-#else
-                uint64_t tmprr:4;
-                uint64_t tras:5;
-                uint64_t trcd:4;
-                uint64_t twtr:4;
-                uint64_t trfc:5;
-                uint64_t trrd:3;
-                uint64_t txp:3;
-                uint64_t twlmrd:4;
-                uint64_t twldqsen:4;
-                uint64_t tfaw:5;
-                uint64_t txpdll:5;
-                uint64_t tras_ext:1;
-                uint64_t reserved_47_63:17;
-#endif
-        } s;
-        struct cvmx_lmcx_timing_params1_s cn61xx;
-        struct cvmx_lmcx_timing_params1_s cn63xx;
-        struct cvmx_lmcx_timing_params1_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_46_63:18;
-                uint64_t txpdll:5;
-                uint64_t tfaw:5;
-                uint64_t twldqsen:4;
-                uint64_t twlmrd:4;
-                uint64_t txp:3;
-                uint64_t trrd:3;
-                uint64_t trfc:5;
-                uint64_t twtr:4;
-                uint64_t trcd:4;
-                uint64_t tras:5;
-                uint64_t tmprr:4;
-#else
-                uint64_t tmprr:4;
-                uint64_t tras:5;
-                uint64_t trcd:4;
-                uint64_t twtr:4;
-                uint64_t trfc:5;
-                uint64_t trrd:3;
-                uint64_t txp:3;
-                uint64_t twlmrd:4;
-                uint64_t twldqsen:4;
-                uint64_t tfaw:5;
-                uint64_t txpdll:5;
-                uint64_t reserved_46_63:18;
-#endif
-        } cn63xxp1;
-        struct cvmx_lmcx_timing_params1_s cn66xx;
-        struct cvmx_lmcx_timing_params1_s cn68xx;
-        struct cvmx_lmcx_timing_params1_s cn68xxp1;
-        struct cvmx_lmcx_timing_params1_s cnf71xx;
-};
-
-union cvmx_lmcx_tro_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_tro_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t rclk_cnt:32;
-                uint64_t treset:1;
-#else
-                uint64_t treset:1;
-                uint64_t rclk_cnt:32;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_lmcx_tro_ctl_s cn61xx;
-        struct cvmx_lmcx_tro_ctl_s cn63xx;
-        struct cvmx_lmcx_tro_ctl_s cn63xxp1;
-        struct cvmx_lmcx_tro_ctl_s cn66xx;
-        struct cvmx_lmcx_tro_ctl_s cn68xx;
-        struct cvmx_lmcx_tro_ctl_s cn68xxp1;
-        struct cvmx_lmcx_tro_ctl_s cnf71xx;
-};
-
-union cvmx_lmcx_tro_stat {
-        uint64_t u64;
-        struct cvmx_lmcx_tro_stat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ring_cnt:32;
-#else
-                uint64_t ring_cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_tro_stat_s cn61xx;
-        struct cvmx_lmcx_tro_stat_s cn63xx;
-        struct cvmx_lmcx_tro_stat_s cn63xxp1;
-        struct cvmx_lmcx_tro_stat_s cn66xx;
-        struct cvmx_lmcx_tro_stat_s cn68xx;
-        struct cvmx_lmcx_tro_stat_s cn68xxp1;
-        struct cvmx_lmcx_tro_stat_s cnf71xx;
-};
-
-union cvmx_lmcx_wlevel_ctl {
-        uint64_t u64;
-        struct cvmx_lmcx_wlevel_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t rtt_nom:3;
-                uint64_t bitmask:8;
-                uint64_t or_dis:1;
-                uint64_t sset:1;
-                uint64_t lanemask:9;
-#else
-                uint64_t lanemask:9;
-                uint64_t sset:1;
-                uint64_t or_dis:1;
-                uint64_t bitmask:8;
-                uint64_t rtt_nom:3;
-                uint64_t reserved_22_63:42;
-#endif
-        } s;
-        struct cvmx_lmcx_wlevel_ctl_s cn61xx;
-        struct cvmx_lmcx_wlevel_ctl_s cn63xx;
-        struct cvmx_lmcx_wlevel_ctl_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t sset:1;
-                uint64_t lanemask:9;
-#else
-                uint64_t lanemask:9;
-                uint64_t sset:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn63xxp1;
-        struct cvmx_lmcx_wlevel_ctl_s cn66xx;
-        struct cvmx_lmcx_wlevel_ctl_s cn68xx;
-        struct cvmx_lmcx_wlevel_ctl_s cn68xxp1;
-        struct cvmx_lmcx_wlevel_ctl_s cnf71xx;
-};
-
-union cvmx_lmcx_wlevel_dbg {
-        uint64_t u64;
-        struct cvmx_lmcx_wlevel_dbg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t bitmask:8;
-                uint64_t byte:4;
-#else
-                uint64_t byte:4;
-                uint64_t bitmask:8;
-                uint64_t reserved_12_63:52;
-#endif
-        } s;
-        struct cvmx_lmcx_wlevel_dbg_s cn61xx;
-        struct cvmx_lmcx_wlevel_dbg_s cn63xx;
-        struct cvmx_lmcx_wlevel_dbg_s cn63xxp1;
-        struct cvmx_lmcx_wlevel_dbg_s cn66xx;
-        struct cvmx_lmcx_wlevel_dbg_s cn68xx;
-        struct cvmx_lmcx_wlevel_dbg_s cn68xxp1;
-        struct cvmx_lmcx_wlevel_dbg_s cnf71xx;
-};
-
-union cvmx_lmcx_wlevel_rankx {
-        uint64_t u64;
-        struct cvmx_lmcx_wlevel_rankx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_47_63:17;
-                uint64_t status:2;
-                uint64_t byte8:5;
-                uint64_t byte7:5;
-                uint64_t byte6:5;
-                uint64_t byte5:5;
-                uint64_t byte4:5;
-                uint64_t byte3:5;
-                uint64_t byte2:5;
-                uint64_t byte1:5;
-                uint64_t byte0:5;
-#else
-                uint64_t byte0:5;
-                uint64_t byte1:5;
-                uint64_t byte2:5;
-                uint64_t byte3:5;
-                uint64_t byte4:5;
-                uint64_t byte5:5;
-                uint64_t byte6:5;
-                uint64_t byte7:5;
-                uint64_t byte8:5;
-                uint64_t status:2;
-                uint64_t reserved_47_63:17;
-#endif
-        } s;
-        struct cvmx_lmcx_wlevel_rankx_s cn61xx;
-        struct cvmx_lmcx_wlevel_rankx_s cn63xx;
-        struct cvmx_lmcx_wlevel_rankx_s cn63xxp1;
-        struct cvmx_lmcx_wlevel_rankx_s cn66xx;
-        struct cvmx_lmcx_wlevel_rankx_s cn68xx;
-        struct cvmx_lmcx_wlevel_rankx_s cn68xxp1;
-        struct cvmx_lmcx_wlevel_rankx_s cnf71xx;
-};
-
-union cvmx_lmcx_wodt_ctl0 {
-        uint64_t u64;
-        struct cvmx_lmcx_wodt_ctl0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_lmcx_wodt_ctl0_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wodt_d1_r1:8;
-                uint64_t wodt_d1_r0:8;
-                uint64_t wodt_d0_r1:8;
-                uint64_t wodt_d0_r0:8;
-#else
-                uint64_t wodt_d0_r0:8;
-                uint64_t wodt_d0_r1:8;
-                uint64_t wodt_d1_r0:8;
-                uint64_t wodt_d1_r1:8;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn30xx;
-        struct cvmx_lmcx_wodt_ctl0_cn30xx cn31xx;
-        struct cvmx_lmcx_wodt_ctl0_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wodt_hi3:4;
-                uint64_t wodt_hi2:4;
-                uint64_t wodt_hi1:4;
-                uint64_t wodt_hi0:4;
-                uint64_t wodt_lo3:4;
-                uint64_t wodt_lo2:4;
-                uint64_t wodt_lo1:4;
-                uint64_t wodt_lo0:4;
-#else
-                uint64_t wodt_lo0:4;
-                uint64_t wodt_lo1:4;
-                uint64_t wodt_lo2:4;
-                uint64_t wodt_lo3:4;
-                uint64_t wodt_hi0:4;
-                uint64_t wodt_hi1:4;
-                uint64_t wodt_hi2:4;
-                uint64_t wodt_hi3:4;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn38xx;
-        struct cvmx_lmcx_wodt_ctl0_cn38xx cn38xxp2;
-        struct cvmx_lmcx_wodt_ctl0_cn38xx cn50xx;
-        struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xx;
-        struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xxp1;
-        struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xx;
-        struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xxp1;
-        struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xx;
-        struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xxp1;
-};
-
-union cvmx_lmcx_wodt_ctl1 {
-        uint64_t u64;
-        struct cvmx_lmcx_wodt_ctl1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wodt_d3_r1:8;
-                uint64_t wodt_d3_r0:8;
-                uint64_t wodt_d2_r1:8;
-                uint64_t wodt_d2_r0:8;
-#else
-                uint64_t wodt_d2_r0:8;
-                uint64_t wodt_d2_r1:8;
-                uint64_t wodt_d3_r0:8;
-                uint64_t wodt_d3_r1:8;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_lmcx_wodt_ctl1_s cn30xx;
-        struct cvmx_lmcx_wodt_ctl1_s cn31xx;
-        struct cvmx_lmcx_wodt_ctl1_s cn52xx;
-        struct cvmx_lmcx_wodt_ctl1_s cn52xxp1;
-        struct cvmx_lmcx_wodt_ctl1_s cn56xx;
-        struct cvmx_lmcx_wodt_ctl1_s cn56xxp1;
-};
-
-union cvmx_lmcx_wodt_mask {
-        uint64_t u64;
-        struct cvmx_lmcx_wodt_mask_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t wodt_d3_r1:8;
-                uint64_t wodt_d3_r0:8;
-                uint64_t wodt_d2_r1:8;
-                uint64_t wodt_d2_r0:8;
-                uint64_t wodt_d1_r1:8;
-                uint64_t wodt_d1_r0:8;
-                uint64_t wodt_d0_r1:8;
-                uint64_t wodt_d0_r0:8;
-#else
-                uint64_t wodt_d0_r0:8;
-                uint64_t wodt_d0_r1:8;
-                uint64_t wodt_d1_r0:8;
-                uint64_t wodt_d1_r1:8;
-                uint64_t wodt_d2_r0:8;
-                uint64_t wodt_d2_r1:8;
-                uint64_t wodt_d3_r0:8;
-                uint64_t wodt_d3_r1:8;
-#endif
-        } s;
-        struct cvmx_lmcx_wodt_mask_s cn61xx;
-        struct cvmx_lmcx_wodt_mask_s cn63xx;
-        struct cvmx_lmcx_wodt_mask_s cn63xxp1;
-        struct cvmx_lmcx_wodt_mask_s cn66xx;
-        struct cvmx_lmcx_wodt_mask_s cn68xx;
-        struct cvmx_lmcx_wodt_mask_s cn68xxp1;
-        struct cvmx_lmcx_wodt_mask_s cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h
deleted file mode 100644
index 6f0cd182cec..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-mdio.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- *
- * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
- * clause 22 and clause 45 operations.
- *
- */
-
-#ifndef __CVMX_MIO_H__
-#define __CVMX_MIO_H__
-
-#include <asm/octeon/cvmx-smix-defs.h>
-
-/**
- * PHY register 0 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_CONTROL 0
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t reset:1;
-                uint16_t loopback:1;
-                uint16_t speed_lsb:1;
-                uint16_t autoneg_enable:1;
-                uint16_t power_down:1;
-                uint16_t isolate:1;
-                uint16_t restart_autoneg:1;
-                uint16_t duplex:1;
-                uint16_t collision_test:1;
-                uint16_t speed_msb:1;
-                uint16_t unidirectional_enable:1;
-                uint16_t reserved_0_4:5;
-        } s;
-} cvmx_mdio_phy_reg_control_t;
-
-/**
- * PHY register 1 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_STATUS 1
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t capable_100base_t4:1;
-                uint16_t capable_100base_x_full:1;
-                uint16_t capable_100base_x_half:1;
-                uint16_t capable_10_full:1;
-                uint16_t capable_10_half:1;
-                uint16_t capable_100base_t2_full:1;
-                uint16_t capable_100base_t2_half:1;
-                uint16_t capable_extended_status:1;
-                uint16_t capable_unidirectional:1;
-                uint16_t capable_mf_preamble_suppression:1;
-                uint16_t autoneg_complete:1;
-                uint16_t remote_fault:1;
-                uint16_t capable_autoneg:1;
-                uint16_t link_status:1;
-                uint16_t jabber_detect:1;
-                uint16_t capable_extended_registers:1;
-
-        } s;
-} cvmx_mdio_phy_reg_status_t;
-
-/**
- * PHY register 2 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_ID1 2
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t oui_bits_3_18;
-        } s;
-} cvmx_mdio_phy_reg_id1_t;
-
-/**
- * PHY register 3 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_ID2 3
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t oui_bits_19_24:6;
-                uint16_t model:6;
-                uint16_t revision:4;
-        } s;
-} cvmx_mdio_phy_reg_id2_t;
-
-/**
- * PHY register 4 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t next_page:1;
-                uint16_t reserved_14:1;
-                uint16_t remote_fault:1;
-                uint16_t reserved_12:1;
-                uint16_t asymmetric_pause:1;
-                uint16_t pause:1;
-                uint16_t advert_100base_t4:1;
-                uint16_t advert_100base_tx_full:1;
-                uint16_t advert_100base_tx_half:1;
-                uint16_t advert_10base_tx_full:1;
-                uint16_t advert_10base_tx_half:1;
-                uint16_t selector:5;
-        } s;
-} cvmx_mdio_phy_reg_autoneg_adver_t;
-
-/**
- * PHY register 5 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t next_page:1;
-                uint16_t ack:1;
-                uint16_t remote_fault:1;
-                uint16_t reserved_12:1;
-                uint16_t asymmetric_pause:1;
-                uint16_t pause:1;
-                uint16_t advert_100base_t4:1;
-                uint16_t advert_100base_tx_full:1;
-                uint16_t advert_100base_tx_half:1;
-                uint16_t advert_10base_tx_full:1;
-                uint16_t advert_10base_tx_half:1;
-                uint16_t selector:5;
-        } s;
-} cvmx_mdio_phy_reg_link_partner_ability_t;
-
-/**
- * PHY register 6 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t reserved_5_15:11;
-                uint16_t parallel_detection_fault:1;
-                uint16_t link_partner_next_page_capable:1;
-                uint16_t local_next_page_capable:1;
-                uint16_t page_received:1;
-                uint16_t link_partner_autoneg_capable:1;
-
-        } s;
-} cvmx_mdio_phy_reg_autoneg_expansion_t;
-
-/**
- * PHY register 9 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t test_mode:3;
-                uint16_t manual_master_slave:1;
-                uint16_t master:1;
-                uint16_t port_type:1;
-                uint16_t advert_1000base_t_full:1;
-                uint16_t advert_1000base_t_half:1;
-                uint16_t reserved_0_7:8;
-        } s;
-} cvmx_mdio_phy_reg_control_1000_t;
-
-/**
- * PHY register 10 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_STATUS_1000 10
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t master_slave_fault:1;
-                uint16_t is_master:1;
-                uint16_t local_receiver_ok:1;
-                uint16_t remote_receiver_ok:1;
-                uint16_t remote_capable_1000base_t_full:1;
-                uint16_t remote_capable_1000base_t_half:1;
-                uint16_t reserved_8_9:2;
-                uint16_t idle_error_count:8;
-        } s;
-} cvmx_mdio_phy_reg_status_1000_t;
-
-/**
- * PHY register 15 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t capable_1000base_x_full:1;
-                uint16_t capable_1000base_x_half:1;
-                uint16_t capable_1000base_t_full:1;
-                uint16_t capable_1000base_t_half:1;
-                uint16_t reserved_0_11:12;
-        } s;
-} cvmx_mdio_phy_reg_extended_status_t;
-
-/**
- * PHY register 13 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t function:2;
-                uint16_t reserved_5_13:9;
-                uint16_t devad:5;
-        } s;
-} cvmx_mdio_phy_reg_mmd_control_t;
-
-/**
- * PHY register 14 from the 802.3 spec
- */
-#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
-typedef union {
-        uint16_t u16;
-        struct {
-                uint16_t address_data:16;
-        } s;
-} cvmx_mdio_phy_reg_mmd_address_data_t;
-
-/* Operating request encodings. */
-#define MDIO_CLAUSE_22_WRITE    0
-#define MDIO_CLAUSE_22_READ     1
-
-#define MDIO_CLAUSE_45_ADDRESS  0
-#define MDIO_CLAUSE_45_WRITE    1
-#define MDIO_CLAUSE_45_READ_INC 2
-#define MDIO_CLAUSE_45_READ     3
-
-/* MMD identifiers, mostly for accessing devices within XENPAK modules. */
-#define CVMX_MMD_DEVICE_PMA_PMD      1
-#define CVMX_MMD_DEVICE_WIS          2
-#define CVMX_MMD_DEVICE_PCS          3
-#define CVMX_MMD_DEVICE_PHY_XS       4
-#define CVMX_MMD_DEVICE_DTS_XS       5
-#define CVMX_MMD_DEVICE_TC           6
-#define CVMX_MMD_DEVICE_CL22_EXT     29
-#define CVMX_MMD_DEVICE_VENDOR_1     30
-#define CVMX_MMD_DEVICE_VENDOR_2     31
-
-/* Helper function to put MDIO interface into clause 45 mode */
-static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
-{
-        union cvmx_smix_clk smi_clk;
-        /* Put bus into clause 45 mode */
-        smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
-        smi_clk.s.mode = 1;
-        smi_clk.s.preamble = 1;
-        cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
-}
-
-/* Helper function to put MDIO interface into clause 22 mode */
-static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
-{
-        union cvmx_smix_clk smi_clk;
-        /* Put bus into clause 22 mode */
-        smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
-        smi_clk.s.mode = 0;
-        cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
-}
-
-/**
- * Perform an MII read. This function is used to read PHY
- * registers controlling auto negotiation.
- *
- * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
- *                 support multiple busses.
- * @phy_id:   The MII phy id
- * @location: Register location to read
- *
- * Returns Result from the read or -1 on failure
- */
-static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
-{
-        union cvmx_smix_cmd smi_cmd;
-        union cvmx_smix_rd_dat smi_rd;
-        int timeout = 1000;
-
-        if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
-                __cvmx_mdio_set_clause22_mode(bus_id);
-
-        smi_cmd.u64 = 0;
-        smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
-        smi_cmd.s.phy_adr = phy_id;
-        smi_cmd.s.reg_adr = location;
-        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
-
-        do {
-                cvmx_wait(1000);
-                smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
-        } while (smi_rd.s.pending && timeout--);
-
-        if (smi_rd.s.val)
-                return smi_rd.s.dat;
-        else
-                return -1;
-}
-
-/**
- * Perform an MII write. This function is used to write PHY
- * registers controlling auto negotiation.
- *
- * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
- *                 support multiple busses.
- * @phy_id:   The MII phy id
- * @location: Register location to write
- * @val:      Value to write
- *
- * Returns -1 on error
- *         0 on success
- */
-static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
-{
-        union cvmx_smix_cmd smi_cmd;
-        union cvmx_smix_wr_dat smi_wr;
-        int timeout = 1000;
-
-        if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
-                __cvmx_mdio_set_clause22_mode(bus_id);
-
-        smi_wr.u64 = 0;
-        smi_wr.s.dat = val;
-        cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
-
-        smi_cmd.u64 = 0;
-        smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
-        smi_cmd.s.phy_adr = phy_id;
-        smi_cmd.s.reg_adr = location;
-        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
-
-        do {
-                cvmx_wait(1000);
-                smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
-        } while (smi_wr.s.pending && --timeout);
-        if (timeout <= 0)
-                return -1;
-
-        return 0;
-}
-
-/**
- * Perform an IEEE 802.3 clause 45 MII read. This function is used to
- * read PHY registers controlling auto negotiation.
- *
- * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
- *                 support multiple busses.
- * @phy_id:   The MII phy id
- * @device:   MDIO Managable Device (MMD) id
- * @location: Register location to read
- *
- * Returns Result from the read or -1 on failure
- */
-
-static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
-                                    int location)
-{
-        union cvmx_smix_cmd smi_cmd;
-        union cvmx_smix_rd_dat smi_rd;
-        union cvmx_smix_wr_dat smi_wr;
-        int timeout = 1000;
-
-        if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
-                return -1;
-
-        __cvmx_mdio_set_clause45_mode(bus_id);
-
-        smi_wr.u64 = 0;
-        smi_wr.s.dat = location;
-        cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
-
-        smi_cmd.u64 = 0;
-        smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
-        smi_cmd.s.phy_adr = phy_id;
-        smi_cmd.s.reg_adr = device;
-        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
-
-        do {
-                cvmx_wait(1000);
-                smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
-        } while (smi_wr.s.pending && --timeout);
-        if (timeout <= 0) {
-                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
-                             "device %2d register %2d   TIME OUT(address)\n",
-                     bus_id, phy_id, device, location);
-                return -1;
-        }
-
-        smi_cmd.u64 = 0;
-        smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
-        smi_cmd.s.phy_adr = phy_id;
-        smi_cmd.s.reg_adr = device;
-        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
-
-        do {
-                cvmx_wait(1000);
-                smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
-        } while (smi_rd.s.pending && --timeout);
-
-        if (timeout <= 0) {
-                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
-                             "device %2d register %2d   TIME OUT(data)\n",
-                     bus_id, phy_id, device, location);
-                return -1;
-        }
-
-        if (smi_rd.s.val)
-                return smi_rd.s.dat;
-        else {
-                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
-                             "device %2d register %2d   INVALID READ\n",
-                     bus_id, phy_id, device, location);
-                return -1;
-        }
-}
-
-/**
- * Perform an IEEE 802.3 clause 45 MII write. This function is used to
- * write PHY registers controlling auto negotiation.
- *
- * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
- *                 support multiple busses.
- * @phy_id:   The MII phy id
- * @device:   MDIO Managable Device (MMD) id
- * @location: Register location to write
- * @val:      Value to write
- *
- * Returns -1 on error
- *         0 on success
- */
-static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
-                                     int location, int val)
-{
-        union cvmx_smix_cmd smi_cmd;
-        union cvmx_smix_wr_dat smi_wr;
-        int timeout = 1000;
-
-        if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
-                return -1;
-
-        __cvmx_mdio_set_clause45_mode(bus_id);
-
-        smi_wr.u64 = 0;
-        smi_wr.s.dat = location;
-        cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
-
-        smi_cmd.u64 = 0;
-        smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
-        smi_cmd.s.phy_adr = phy_id;
-        smi_cmd.s.reg_adr = device;
-        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
-
-        do {
-                cvmx_wait(1000);
-                smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
-        } while (smi_wr.s.pending && --timeout);
-        if (timeout <= 0)
-                return -1;
-
-        smi_wr.u64 = 0;
-        smi_wr.s.dat = val;
-        cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
-
-        smi_cmd.u64 = 0;
-        smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
-        smi_cmd.s.phy_adr = phy_id;
-        smi_cmd.s.reg_adr = device;
-        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
-
-        do {
-                cvmx_wait(1000);
-                smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
-        } while (smi_wr.s.pending && --timeout);
-        if (timeout <= 0)
-                return -1;
-
-        return 0;
-}
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index bb0ae338a46..52b14a333ad 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -43,22 +43,6 @@
 #define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
 #define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
 #define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
-#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
-#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
-#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
-#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
-#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
-#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
-#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
-#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
-#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
-#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
-#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
-#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
-#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
-#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
-#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
-#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
 #define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
 #define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
 #define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
@@ -76,7 +60,6 @@
 #define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
 #define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
 #define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
-#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
 #define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
 #define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
 #define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
@@ -85,26 +68,14 @@
 #define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
 #define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
 #define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
-#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
-#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
-#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
-#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
 #define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
 #define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
 #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
 #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
 #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
-#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull))
-#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
-#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
-#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
-#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
 #define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
-#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
 #define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
 #define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
-#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
-#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
 #define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
 #define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
 #define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
@@ -167,44 +138,24 @@
 union cvmx_mio_boot_bist_stat {
         uint64_t u64;
         struct cvmx_mio_boot_bist_stat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
         } s;
         struct cvmx_mio_boot_bist_stat_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t ncbo_1:1;
                 uint64_t ncbo_0:1;
                 uint64_t loc:1;
                 uint64_t ncbi:1;
-#else
-                uint64_t ncbi:1;
-                uint64_t loc:1;
-                uint64_t ncbo_0:1;
-                uint64_t ncbo_1:1;
-                uint64_t reserved_4_63:60;
-#endif
         } cn30xx;
         struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
         struct cvmx_mio_boot_bist_stat_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t ncbo_0:1;
                 uint64_t loc:1;
                 uint64_t ncbi:1;
-#else
-                uint64_t ncbi:1;
-                uint64_t loc:1;
-                uint64_t ncbo_0:1;
-                uint64_t reserved_3_63:61;
-#endif
         } cn38xx;
         struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
         struct cvmx_mio_boot_bist_stat_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t pcm_1:1;
                 uint64_t pcm_0:1;
@@ -212,132 +163,58 @@ union cvmx_mio_boot_bist_stat {
                 uint64_t ncbo_0:1;
                 uint64_t loc:1;
                 uint64_t ncbi:1;
-#else
-                uint64_t ncbi:1;
-                uint64_t loc:1;
-                uint64_t ncbo_0:1;
-                uint64_t ncbo_1:1;
-                uint64_t pcm_0:1;
-                uint64_t pcm_1:1;
-                uint64_t reserved_6_63:58;
-#endif
         } cn50xx;
         struct cvmx_mio_boot_bist_stat_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t ndf:2;
                 uint64_t ncbo_0:1;
                 uint64_t dma:1;
                 uint64_t loc:1;
                 uint64_t ncbi:1;
-#else
-                uint64_t ncbi:1;
-                uint64_t loc:1;
-                uint64_t dma:1;
-                uint64_t ncbo_0:1;
-                uint64_t ndf:2;
-                uint64_t reserved_6_63:58;
-#endif
         } cn52xx;
         struct cvmx_mio_boot_bist_stat_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t ncbo_0:1;
                 uint64_t dma:1;
                 uint64_t loc:1;
                 uint64_t ncbi:1;
-#else
-                uint64_t ncbi:1;
-                uint64_t loc:1;
-                uint64_t dma:1;
-                uint64_t ncbo_0:1;
-                uint64_t reserved_4_63:60;
-#endif
         } cn52xxp1;
         struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
         struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
-        struct cvmx_mio_boot_bist_stat_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t stat:12;
-#else
-                uint64_t stat:12;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn61xx;
         struct cvmx_mio_boot_bist_stat_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t stat:9;
-#else
-                uint64_t stat:9;
-                uint64_t reserved_9_63:55;
-#endif
         } cn63xx;
         struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
-        struct cvmx_mio_boot_bist_stat_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t stat:10;
-#else
-                uint64_t stat:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn66xx;
-        struct cvmx_mio_boot_bist_stat_cn66xx cn68xx;
-        struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1;
-        struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx;
 };
 
 union cvmx_mio_boot_comp {
         uint64_t u64;
         struct cvmx_mio_boot_comp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
                 uint64_t reserved_0_63:64;
-#endif
         } s;
         struct cvmx_mio_boot_comp_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t pctl:5;
                 uint64_t nctl:5;
-#else
-                uint64_t nctl:5;
-                uint64_t pctl:5;
-                uint64_t reserved_10_63:54;
-#endif
         } cn50xx;
         struct cvmx_mio_boot_comp_cn50xx cn52xx;
         struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
         struct cvmx_mio_boot_comp_cn50xx cn56xx;
         struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
-        struct cvmx_mio_boot_comp_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
+        struct cvmx_mio_boot_comp_cn63xx {
                 uint64_t reserved_12_63:52;
                 uint64_t pctl:6;
                 uint64_t nctl:6;
-#else
-                uint64_t nctl:6;
-                uint64_t pctl:6;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn61xx;
-        struct cvmx_mio_boot_comp_cn61xx cn63xx;
-        struct cvmx_mio_boot_comp_cn61xx cn63xxp1;
-        struct cvmx_mio_boot_comp_cn61xx cn66xx;
-        struct cvmx_mio_boot_comp_cn61xx cn68xx;
-        struct cvmx_mio_boot_comp_cn61xx cn68xxp1;
-        struct cvmx_mio_boot_comp_cn61xx cnf71xx;
+        } cn63xx;
+        struct cvmx_mio_boot_comp_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_boot_dma_cfgx {
         uint64_t u64;
         struct cvmx_mio_boot_dma_cfgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t en:1;
                 uint64_t rw:1;
                 uint64_t clr:1;
@@ -348,88 +225,48 @@ union cvmx_mio_boot_dma_cfgx {
                 uint64_t endian:1;
                 uint64_t size:20;
                 uint64_t adr:36;
-#else
-                uint64_t adr:36;
-                uint64_t size:20;
-                uint64_t endian:1;
-                uint64_t swap8:1;
-                uint64_t swap16:1;
-                uint64_t swap32:1;
-                uint64_t reserved_60_60:1;
-                uint64_t clr:1;
-                uint64_t rw:1;
-                uint64_t en:1;
-#endif
         } s;
         struct cvmx_mio_boot_dma_cfgx_s cn52xx;
         struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
         struct cvmx_mio_boot_dma_cfgx_s cn56xx;
         struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
-        struct cvmx_mio_boot_dma_cfgx_s cn61xx;
         struct cvmx_mio_boot_dma_cfgx_s cn63xx;
         struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
-        struct cvmx_mio_boot_dma_cfgx_s cn66xx;
-        struct cvmx_mio_boot_dma_cfgx_s cn68xx;
-        struct cvmx_mio_boot_dma_cfgx_s cn68xxp1;
-        struct cvmx_mio_boot_dma_cfgx_s cnf71xx;
 };
 
 union cvmx_mio_boot_dma_intx {
         uint64_t u64;
         struct cvmx_mio_boot_dma_intx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t dmarq:1;
                 uint64_t done:1;
-#else
-                uint64_t done:1;
-                uint64_t dmarq:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_mio_boot_dma_intx_s cn52xx;
         struct cvmx_mio_boot_dma_intx_s cn52xxp1;
         struct cvmx_mio_boot_dma_intx_s cn56xx;
         struct cvmx_mio_boot_dma_intx_s cn56xxp1;
-        struct cvmx_mio_boot_dma_intx_s cn61xx;
         struct cvmx_mio_boot_dma_intx_s cn63xx;
         struct cvmx_mio_boot_dma_intx_s cn63xxp1;
-        struct cvmx_mio_boot_dma_intx_s cn66xx;
-        struct cvmx_mio_boot_dma_intx_s cn68xx;
-        struct cvmx_mio_boot_dma_intx_s cn68xxp1;
-        struct cvmx_mio_boot_dma_intx_s cnf71xx;
 };
 
 union cvmx_mio_boot_dma_int_enx {
         uint64_t u64;
         struct cvmx_mio_boot_dma_int_enx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t dmarq:1;
                 uint64_t done:1;
-#else
-                uint64_t done:1;
-                uint64_t dmarq:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_mio_boot_dma_int_enx_s cn52xx;
         struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
         struct cvmx_mio_boot_dma_int_enx_s cn56xx;
         struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
-        struct cvmx_mio_boot_dma_int_enx_s cn61xx;
         struct cvmx_mio_boot_dma_int_enx_s cn63xx;
         struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
-        struct cvmx_mio_boot_dma_int_enx_s cn66xx;
-        struct cvmx_mio_boot_dma_int_enx_s cn68xx;
-        struct cvmx_mio_boot_dma_int_enx_s cn68xxp1;
-        struct cvmx_mio_boot_dma_int_enx_s cnf71xx;
 };
 
 union cvmx_mio_boot_dma_timx {
         uint64_t u64;
         struct cvmx_mio_boot_dma_timx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t dmack_pi:1;
                 uint64_t dmarq_pi:1;
                 uint64_t tim_mult:2;
@@ -445,49 +282,21 @@ union cvmx_mio_boot_dma_timx {
                 uint64_t oe_a:6;
                 uint64_t dmack_s:6;
                 uint64_t dmarq:6;
-#else
-                uint64_t dmarq:6;
-                uint64_t dmack_s:6;
-                uint64_t oe_a:6;
-                uint64_t oe_n:6;
-                uint64_t we_a:6;
-                uint64_t we_n:6;
-                uint64_t dmack_h:6;
-                uint64_t pause:6;
-                uint64_t reserved_48_54:7;
-                uint64_t width:1;
-                uint64_t ddr:1;
-                uint64_t rd_dly:3;
-                uint64_t tim_mult:2;
-                uint64_t dmarq_pi:1;
-                uint64_t dmack_pi:1;
-#endif
         } s;
         struct cvmx_mio_boot_dma_timx_s cn52xx;
         struct cvmx_mio_boot_dma_timx_s cn52xxp1;
         struct cvmx_mio_boot_dma_timx_s cn56xx;
         struct cvmx_mio_boot_dma_timx_s cn56xxp1;
-        struct cvmx_mio_boot_dma_timx_s cn61xx;
         struct cvmx_mio_boot_dma_timx_s cn63xx;
         struct cvmx_mio_boot_dma_timx_s cn63xxp1;
-        struct cvmx_mio_boot_dma_timx_s cn66xx;
-        struct cvmx_mio_boot_dma_timx_s cn68xx;
-        struct cvmx_mio_boot_dma_timx_s cn68xxp1;
-        struct cvmx_mio_boot_dma_timx_s cnf71xx;
 };
 
 union cvmx_mio_boot_err {
         uint64_t u64;
         struct cvmx_mio_boot_err_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t wait_err:1;
                 uint64_t adr_err:1;
-#else
-                uint64_t adr_err:1;
-                uint64_t wait_err:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_mio_boot_err_s cn30xx;
         struct cvmx_mio_boot_err_s cn31xx;
@@ -500,27 +309,16 @@ union cvmx_mio_boot_err {
         struct cvmx_mio_boot_err_s cn56xxp1;
         struct cvmx_mio_boot_err_s cn58xx;
         struct cvmx_mio_boot_err_s cn58xxp1;
-        struct cvmx_mio_boot_err_s cn61xx;
         struct cvmx_mio_boot_err_s cn63xx;
         struct cvmx_mio_boot_err_s cn63xxp1;
-        struct cvmx_mio_boot_err_s cn66xx;
-        struct cvmx_mio_boot_err_s cn68xx;
-        struct cvmx_mio_boot_err_s cn68xxp1;
-        struct cvmx_mio_boot_err_s cnf71xx;
 };
 
 union cvmx_mio_boot_int {
         uint64_t u64;
         struct cvmx_mio_boot_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t wait_int:1;
                 uint64_t adr_int:1;
-#else
-                uint64_t adr_int:1;
-                uint64_t wait_int:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_mio_boot_int_s cn30xx;
         struct cvmx_mio_boot_int_s cn31xx;
@@ -533,27 +331,16 @@ union cvmx_mio_boot_int {
         struct cvmx_mio_boot_int_s cn56xxp1;
         struct cvmx_mio_boot_int_s cn58xx;
         struct cvmx_mio_boot_int_s cn58xxp1;
-        struct cvmx_mio_boot_int_s cn61xx;
         struct cvmx_mio_boot_int_s cn63xx;
         struct cvmx_mio_boot_int_s cn63xxp1;
-        struct cvmx_mio_boot_int_s cn66xx;
-        struct cvmx_mio_boot_int_s cn68xx;
-        struct cvmx_mio_boot_int_s cn68xxp1;
-        struct cvmx_mio_boot_int_s cnf71xx;
 };
 
 union cvmx_mio_boot_loc_adr {
         uint64_t u64;
         struct cvmx_mio_boot_loc_adr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t adr:5;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t adr:5;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_boot_loc_adr_s cn30xx;
         struct cvmx_mio_boot_loc_adr_s cn31xx;
@@ -566,31 +353,18 @@ union cvmx_mio_boot_loc_adr {
         struct cvmx_mio_boot_loc_adr_s cn56xxp1;
         struct cvmx_mio_boot_loc_adr_s cn58xx;
         struct cvmx_mio_boot_loc_adr_s cn58xxp1;
-        struct cvmx_mio_boot_loc_adr_s cn61xx;
         struct cvmx_mio_boot_loc_adr_s cn63xx;
         struct cvmx_mio_boot_loc_adr_s cn63xxp1;
-        struct cvmx_mio_boot_loc_adr_s cn66xx;
-        struct cvmx_mio_boot_loc_adr_s cn68xx;
-        struct cvmx_mio_boot_loc_adr_s cn68xxp1;
-        struct cvmx_mio_boot_loc_adr_s cnf71xx;
 };
 
 union cvmx_mio_boot_loc_cfgx {
         uint64_t u64;
         struct cvmx_mio_boot_loc_cfgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t en:1;
                 uint64_t reserved_28_30:3;
                 uint64_t base:25;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t base:25;
-                uint64_t reserved_28_30:3;
-                uint64_t en:1;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_mio_boot_loc_cfgx_s cn30xx;
         struct cvmx_mio_boot_loc_cfgx_s cn31xx;
@@ -603,23 +377,14 @@ union cvmx_mio_boot_loc_cfgx {
         struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_loc_cfgx_s cn58xx;
         struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
-        struct cvmx_mio_boot_loc_cfgx_s cn61xx;
         struct cvmx_mio_boot_loc_cfgx_s cn63xx;
         struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
-        struct cvmx_mio_boot_loc_cfgx_s cn66xx;
-        struct cvmx_mio_boot_loc_cfgx_s cn68xx;
-        struct cvmx_mio_boot_loc_cfgx_s cn68xxp1;
-        struct cvmx_mio_boot_loc_cfgx_s cnf71xx;
 };
 
 union cvmx_mio_boot_loc_dat {
         uint64_t u64;
         struct cvmx_mio_boot_loc_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
                 uint64_t data:64;
-#endif
         } s;
         struct cvmx_mio_boot_loc_dat_s cn30xx;
         struct cvmx_mio_boot_loc_dat_s cn31xx;
@@ -632,21 +397,14 @@ union cvmx_mio_boot_loc_dat {
         struct cvmx_mio_boot_loc_dat_s cn56xxp1;
         struct cvmx_mio_boot_loc_dat_s cn58xx;
         struct cvmx_mio_boot_loc_dat_s cn58xxp1;
-        struct cvmx_mio_boot_loc_dat_s cn61xx;
         struct cvmx_mio_boot_loc_dat_s cn63xx;
         struct cvmx_mio_boot_loc_dat_s cn63xxp1;
-        struct cvmx_mio_boot_loc_dat_s cn66xx;
-        struct cvmx_mio_boot_loc_dat_s cn68xx;
-        struct cvmx_mio_boot_loc_dat_s cn68xxp1;
-        struct cvmx_mio_boot_loc_dat_s cnf71xx;
 };
 
 union cvmx_mio_boot_pin_defs {
         uint64_t u64;
         struct cvmx_mio_boot_pin_defs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t user1:16;
+                uint64_t reserved_16_63:48;
                 uint64_t ale:1;
                 uint64_t width:1;
                 uint64_t dmack_p2:1;
@@ -654,22 +412,9 @@ union cvmx_mio_boot_pin_defs {
                 uint64_t dmack_p0:1;
                 uint64_t term:2;
                 uint64_t nand:1;
-                uint64_t user0:8;
-#else
-                uint64_t user0:8;
-                uint64_t nand:1;
-                uint64_t term:2;
-                uint64_t dmack_p0:1;
-                uint64_t dmack_p1:1;
-                uint64_t dmack_p2:1;
-                uint64_t width:1;
-                uint64_t ale:1;
-                uint64_t user1:16;
-                uint64_t reserved_32_63:32;
-#endif
+                uint64_t reserved_0_7:8;
         } s;
         struct cvmx_mio_boot_pin_defs_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t ale:1;
                 uint64_t width:1;
@@ -679,20 +424,8 @@ union cvmx_mio_boot_pin_defs {
                 uint64_t term:2;
                 uint64_t nand:1;
                 uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t nand:1;
-                uint64_t term:2;
-                uint64_t dmack_p0:1;
-                uint64_t dmack_p1:1;
-                uint64_t reserved_13_13:1;
-                uint64_t width:1;
-                uint64_t ale:1;
-                uint64_t reserved_16_63:48;
-#endif
         } cn52xx;
         struct cvmx_mio_boot_pin_defs_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t ale:1;
                 uint64_t width:1;
@@ -701,54 +434,14 @@ union cvmx_mio_boot_pin_defs {
                 uint64_t dmack_p0:1;
                 uint64_t term:2;
                 uint64_t reserved_0_8:9;
-#else
-                uint64_t reserved_0_8:9;
-                uint64_t term:2;
-                uint64_t dmack_p0:1;
-                uint64_t dmack_p1:1;
-                uint64_t dmack_p2:1;
-                uint64_t width:1;
-                uint64_t ale:1;
-                uint64_t reserved_16_63:48;
-#endif
         } cn56xx;
-        struct cvmx_mio_boot_pin_defs_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t user1:16;
-                uint64_t ale:1;
-                uint64_t width:1;
-                uint64_t reserved_13_13:1;
-                uint64_t dmack_p1:1;
-                uint64_t dmack_p0:1;
-                uint64_t term:2;
-                uint64_t nand:1;
-                uint64_t user0:8;
-#else
-                uint64_t user0:8;
-                uint64_t nand:1;
-                uint64_t term:2;
-                uint64_t dmack_p0:1;
-                uint64_t dmack_p1:1;
-                uint64_t reserved_13_13:1;
-                uint64_t width:1;
-                uint64_t ale:1;
-                uint64_t user1:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn61xx;
         struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
         struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
-        struct cvmx_mio_boot_pin_defs_cn52xx cn66xx;
-        struct cvmx_mio_boot_pin_defs_cn52xx cn68xx;
-        struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1;
-        struct cvmx_mio_boot_pin_defs_cn61xx cnf71xx;
 };
 
 union cvmx_mio_boot_reg_cfgx {
         uint64_t u64;
         struct cvmx_mio_boot_reg_cfgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t dmack:2;
                 uint64_t tim_mult:2;
@@ -762,24 +455,8 @@ union cvmx_mio_boot_reg_cfgx {
                 uint64_t width:1;
                 uint64_t size:12;
                 uint64_t base:16;
-#else
-                uint64_t base:16;
-                uint64_t size:12;
-                uint64_t width:1;
-                uint64_t ale:1;
-                uint64_t orbit:1;
-                uint64_t en:1;
-                uint64_t oe_ext:2;
-                uint64_t we_ext:2;
-                uint64_t sam:1;
-                uint64_t rd_dly:3;
-                uint64_t tim_mult:2;
-                uint64_t dmack:2;
-                uint64_t reserved_44_63:20;
-#endif
         } s;
         struct cvmx_mio_boot_reg_cfgx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_37_63:27;
                 uint64_t sam:1;
                 uint64_t we_ext:2;
@@ -790,40 +467,18 @@ union cvmx_mio_boot_reg_cfgx {
                 uint64_t width:1;
                 uint64_t size:12;
                 uint64_t base:16;
-#else
-                uint64_t base:16;
-                uint64_t size:12;
-                uint64_t width:1;
-                uint64_t ale:1;
-                uint64_t orbit:1;
-                uint64_t en:1;
-                uint64_t oe_ext:2;
-                uint64_t we_ext:2;
-                uint64_t sam:1;
-                uint64_t reserved_37_63:27;
-#endif
         } cn30xx;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
         struct cvmx_mio_boot_reg_cfgx_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t en:1;
                 uint64_t orbit:1;
                 uint64_t reserved_28_29:2;
                 uint64_t size:12;
                 uint64_t base:16;
-#else
-                uint64_t base:16;
-                uint64_t size:12;
-                uint64_t reserved_28_29:2;
-                uint64_t orbit:1;
-                uint64_t en:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn38xx;
         struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
         struct cvmx_mio_boot_reg_cfgx_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_42_63:22;
                 uint64_t tim_mult:2;
                 uint64_t rd_dly:3;
@@ -836,20 +491,6 @@ union cvmx_mio_boot_reg_cfgx {
                 uint64_t width:1;
                 uint64_t size:12;
                 uint64_t base:16;
-#else
-                uint64_t base:16;
-                uint64_t size:12;
-                uint64_t width:1;
-                uint64_t ale:1;
-                uint64_t orbit:1;
-                uint64_t en:1;
-                uint64_t oe_ext:2;
-                uint64_t we_ext:2;
-                uint64_t sam:1;
-                uint64_t rd_dly:3;
-                uint64_t tim_mult:2;
-                uint64_t reserved_42_63:22;
-#endif
         } cn50xx;
         struct cvmx_mio_boot_reg_cfgx_s cn52xx;
         struct cvmx_mio_boot_reg_cfgx_s cn52xxp1;
@@ -857,19 +498,13 @@ union cvmx_mio_boot_reg_cfgx {
         struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
-        struct cvmx_mio_boot_reg_cfgx_s cn61xx;
         struct cvmx_mio_boot_reg_cfgx_s cn63xx;
         struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
-        struct cvmx_mio_boot_reg_cfgx_s cn66xx;
-        struct cvmx_mio_boot_reg_cfgx_s cn68xx;
-        struct cvmx_mio_boot_reg_cfgx_s cn68xxp1;
-        struct cvmx_mio_boot_reg_cfgx_s cnf71xx;
 };
 
 union cvmx_mio_boot_reg_timx {
         uint64_t u64;
         struct cvmx_mio_boot_reg_timx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t pagem:1;
                 uint64_t waitm:1;
                 uint64_t pages:2;
@@ -883,26 +518,10 @@ union cvmx_mio_boot_reg_timx {
                 uint64_t oe:6;
                 uint64_t ce:6;
                 uint64_t adr:6;
-#else
-                uint64_t adr:6;
-                uint64_t ce:6;
-                uint64_t oe:6;
-                uint64_t we:6;
-                uint64_t rd_hld:6;
-                uint64_t wr_hld:6;
-                uint64_t pause:6;
-                uint64_t wait:6;
-                uint64_t page:6;
-                uint64_t ale:6;
-                uint64_t pages:2;
-                uint64_t waitm:1;
-                uint64_t pagem:1;
-#endif
         } s;
         struct cvmx_mio_boot_reg_timx_s cn30xx;
         struct cvmx_mio_boot_reg_timx_s cn31xx;
         struct cvmx_mio_boot_reg_timx_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t pagem:1;
                 uint64_t waitm:1;
                 uint64_t pages:2;
@@ -916,21 +535,6 @@ union cvmx_mio_boot_reg_timx {
                 uint64_t oe:6;
                 uint64_t ce:6;
                 uint64_t adr:6;
-#else
-                uint64_t adr:6;
-                uint64_t ce:6;
-                uint64_t oe:6;
-                uint64_t we:6;
-                uint64_t rd_hld:6;
-                uint64_t wr_hld:6;
-                uint64_t pause:6;
-                uint64_t wait:6;
-                uint64_t page:6;
-                uint64_t reserved_54_59:6;
-                uint64_t pages:2;
-                uint64_t waitm:1;
-                uint64_t pagem:1;
-#endif
         } cn38xx;
         struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
         struct cvmx_mio_boot_reg_timx_s cn50xx;
@@ -940,46 +544,25 @@ union cvmx_mio_boot_reg_timx {
         struct cvmx_mio_boot_reg_timx_s cn56xxp1;
         struct cvmx_mio_boot_reg_timx_s cn58xx;
         struct cvmx_mio_boot_reg_timx_s cn58xxp1;
-        struct cvmx_mio_boot_reg_timx_s cn61xx;
         struct cvmx_mio_boot_reg_timx_s cn63xx;
         struct cvmx_mio_boot_reg_timx_s cn63xxp1;
-        struct cvmx_mio_boot_reg_timx_s cn66xx;
-        struct cvmx_mio_boot_reg_timx_s cn68xx;
-        struct cvmx_mio_boot_reg_timx_s cn68xxp1;
-        struct cvmx_mio_boot_reg_timx_s cnf71xx;
 };
 
 union cvmx_mio_boot_thr {
         uint64_t u64;
         struct cvmx_mio_boot_thr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_22_63:42;
                 uint64_t dma_thr:6;
                 uint64_t reserved_14_15:2;
                 uint64_t fif_cnt:6;
                 uint64_t reserved_6_7:2;
                 uint64_t fif_thr:6;
-#else
-                uint64_t fif_thr:6;
-                uint64_t reserved_6_7:2;
-                uint64_t fif_cnt:6;
-                uint64_t reserved_14_15:2;
-                uint64_t dma_thr:6;
-                uint64_t reserved_22_63:42;
-#endif
         } s;
         struct cvmx_mio_boot_thr_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t fif_cnt:6;
                 uint64_t reserved_6_7:2;
                 uint64_t fif_thr:6;
-#else
-                uint64_t fif_thr:6;
-                uint64_t reserved_6_7:2;
-                uint64_t fif_cnt:6;
-                uint64_t reserved_14_63:50;
-#endif
         } cn30xx;
         struct cvmx_mio_boot_thr_cn30xx cn31xx;
         struct cvmx_mio_boot_thr_cn30xx cn38xx;
@@ -991,413 +574,14 @@ union cvmx_mio_boot_thr {
         struct cvmx_mio_boot_thr_s cn56xxp1;
         struct cvmx_mio_boot_thr_cn30xx cn58xx;
         struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
-        struct cvmx_mio_boot_thr_s cn61xx;
         struct cvmx_mio_boot_thr_s cn63xx;
         struct cvmx_mio_boot_thr_s cn63xxp1;
-        struct cvmx_mio_boot_thr_s cn66xx;
-        struct cvmx_mio_boot_thr_s cn68xx;
-        struct cvmx_mio_boot_thr_s cn68xxp1;
-        struct cvmx_mio_boot_thr_s cnf71xx;
-};
-
-union cvmx_mio_emm_buf_dat {
-        uint64_t u64;
-        struct cvmx_mio_emm_buf_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dat:64;
-#else
-                uint64_t dat:64;
-#endif
-        } s;
-        struct cvmx_mio_emm_buf_dat_s cn61xx;
-        struct cvmx_mio_emm_buf_dat_s cnf71xx;
-};
-
-union cvmx_mio_emm_buf_idx {
-        uint64_t u64;
-        struct cvmx_mio_emm_buf_idx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t inc:1;
-                uint64_t reserved_7_15:9;
-                uint64_t buf_num:1;
-                uint64_t offset:6;
-#else
-                uint64_t offset:6;
-                uint64_t buf_num:1;
-                uint64_t reserved_7_15:9;
-                uint64_t inc:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_mio_emm_buf_idx_s cn61xx;
-        struct cvmx_mio_emm_buf_idx_s cnf71xx;
-};
-
-union cvmx_mio_emm_cfg {
-        uint64_t u64;
-        struct cvmx_mio_emm_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t boot_fail:1;
-                uint64_t reserved_4_15:12;
-                uint64_t bus_ena:4;
-#else
-                uint64_t bus_ena:4;
-                uint64_t reserved_4_15:12;
-                uint64_t boot_fail:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_mio_emm_cfg_s cn61xx;
-        struct cvmx_mio_emm_cfg_s cnf71xx;
-};
-
-union cvmx_mio_emm_cmd {
-        uint64_t u64;
-        struct cvmx_mio_emm_cmd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t bus_id:2;
-                uint64_t cmd_val:1;
-                uint64_t reserved_56_58:3;
-                uint64_t dbuf:1;
-                uint64_t offset:6;
-                uint64_t reserved_43_48:6;
-                uint64_t ctype_xor:2;
-                uint64_t rtype_xor:3;
-                uint64_t cmd_idx:6;
-                uint64_t arg:32;
-#else
-                uint64_t arg:32;
-                uint64_t cmd_idx:6;
-                uint64_t rtype_xor:3;
-                uint64_t ctype_xor:2;
-                uint64_t reserved_43_48:6;
-                uint64_t offset:6;
-                uint64_t dbuf:1;
-                uint64_t reserved_56_58:3;
-                uint64_t cmd_val:1;
-                uint64_t bus_id:2;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_mio_emm_cmd_s cn61xx;
-        struct cvmx_mio_emm_cmd_s cnf71xx;
-};
-
-union cvmx_mio_emm_dma {
-        uint64_t u64;
-        struct cvmx_mio_emm_dma_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t bus_id:2;
-                uint64_t dma_val:1;
-                uint64_t sector:1;
-                uint64_t dat_null:1;
-                uint64_t thres:6;
-                uint64_t rel_wr:1;
-                uint64_t rw:1;
-                uint64_t multi:1;
-                uint64_t block_cnt:16;
-                uint64_t card_addr:32;
-#else
-                uint64_t card_addr:32;
-                uint64_t block_cnt:16;
-                uint64_t multi:1;
-                uint64_t rw:1;
-                uint64_t rel_wr:1;
-                uint64_t thres:6;
-                uint64_t dat_null:1;
-                uint64_t sector:1;
-                uint64_t dma_val:1;
-                uint64_t bus_id:2;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_mio_emm_dma_s cn61xx;
-        struct cvmx_mio_emm_dma_s cnf71xx;
-};
-
-union cvmx_mio_emm_int {
-        uint64_t u64;
-        struct cvmx_mio_emm_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t switch_err:1;
-                uint64_t switch_done:1;
-                uint64_t dma_err:1;
-                uint64_t cmd_err:1;
-                uint64_t dma_done:1;
-                uint64_t cmd_done:1;
-                uint64_t buf_done:1;
-#else
-                uint64_t buf_done:1;
-                uint64_t cmd_done:1;
-                uint64_t dma_done:1;
-                uint64_t cmd_err:1;
-                uint64_t dma_err:1;
-                uint64_t switch_done:1;
-                uint64_t switch_err:1;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_mio_emm_int_s cn61xx;
-        struct cvmx_mio_emm_int_s cnf71xx;
-};
-
-union cvmx_mio_emm_int_en {
-        uint64_t u64;
-        struct cvmx_mio_emm_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t switch_err:1;
-                uint64_t switch_done:1;
-                uint64_t dma_err:1;
-                uint64_t cmd_err:1;
-                uint64_t dma_done:1;
-                uint64_t cmd_done:1;
-                uint64_t buf_done:1;
-#else
-                uint64_t buf_done:1;
-                uint64_t cmd_done:1;
-                uint64_t dma_done:1;
-                uint64_t cmd_err:1;
-                uint64_t dma_err:1;
-                uint64_t switch_done:1;
-                uint64_t switch_err:1;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_mio_emm_int_en_s cn61xx;
-        struct cvmx_mio_emm_int_en_s cnf71xx;
-};
-
-union cvmx_mio_emm_modex {
-        uint64_t u64;
-        struct cvmx_mio_emm_modex_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t hs_timing:1;
-                uint64_t reserved_43_47:5;
-                uint64_t bus_width:3;
-                uint64_t reserved_36_39:4;
-                uint64_t power_class:4;
-                uint64_t clk_hi:16;
-                uint64_t clk_lo:16;
-#else
-                uint64_t clk_lo:16;
-                uint64_t clk_hi:16;
-                uint64_t power_class:4;
-                uint64_t reserved_36_39:4;
-                uint64_t bus_width:3;
-                uint64_t reserved_43_47:5;
-                uint64_t hs_timing:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } s;
-        struct cvmx_mio_emm_modex_s cn61xx;
-        struct cvmx_mio_emm_modex_s cnf71xx;
-};
-
-union cvmx_mio_emm_rca {
-        uint64_t u64;
-        struct cvmx_mio_emm_rca_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t card_rca:16;
-#else
-                uint64_t card_rca:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_mio_emm_rca_s cn61xx;
-        struct cvmx_mio_emm_rca_s cnf71xx;
-};
-
-union cvmx_mio_emm_rsp_hi {
-        uint64_t u64;
-        struct cvmx_mio_emm_rsp_hi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dat:64;
-#else
-                uint64_t dat:64;
-#endif
-        } s;
-        struct cvmx_mio_emm_rsp_hi_s cn61xx;
-        struct cvmx_mio_emm_rsp_hi_s cnf71xx;
-};
-
-union cvmx_mio_emm_rsp_lo {
-        uint64_t u64;
-        struct cvmx_mio_emm_rsp_lo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dat:64;
-#else
-                uint64_t dat:64;
-#endif
-        } s;
-        struct cvmx_mio_emm_rsp_lo_s cn61xx;
-        struct cvmx_mio_emm_rsp_lo_s cnf71xx;
-};
-
-union cvmx_mio_emm_rsp_sts {
-        uint64_t u64;
-        struct cvmx_mio_emm_rsp_sts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t bus_id:2;
-                uint64_t cmd_val:1;
-                uint64_t switch_val:1;
-                uint64_t dma_val:1;
-                uint64_t dma_pend:1;
-                uint64_t reserved_29_55:27;
-                uint64_t dbuf_err:1;
-                uint64_t reserved_24_27:4;
-                uint64_t dbuf:1;
-                uint64_t blk_timeout:1;
-                uint64_t blk_crc_err:1;
-                uint64_t rsp_busybit:1;
-                uint64_t stp_timeout:1;
-                uint64_t stp_crc_err:1;
-                uint64_t stp_bad_sts:1;
-                uint64_t stp_val:1;
-                uint64_t rsp_timeout:1;
-                uint64_t rsp_crc_err:1;
-                uint64_t rsp_bad_sts:1;
-                uint64_t rsp_val:1;
-                uint64_t rsp_type:3;
-                uint64_t cmd_type:2;
-                uint64_t cmd_idx:6;
-                uint64_t cmd_done:1;
-#else
-                uint64_t cmd_done:1;
-                uint64_t cmd_idx:6;
-                uint64_t cmd_type:2;
-                uint64_t rsp_type:3;
-                uint64_t rsp_val:1;
-                uint64_t rsp_bad_sts:1;
-                uint64_t rsp_crc_err:1;
-                uint64_t rsp_timeout:1;
-                uint64_t stp_val:1;
-                uint64_t stp_bad_sts:1;
-                uint64_t stp_crc_err:1;
-                uint64_t stp_timeout:1;
-                uint64_t rsp_busybit:1;
-                uint64_t blk_crc_err:1;
-                uint64_t blk_timeout:1;
-                uint64_t dbuf:1;
-                uint64_t reserved_24_27:4;
-                uint64_t dbuf_err:1;
-                uint64_t reserved_29_55:27;
-                uint64_t dma_pend:1;
-                uint64_t dma_val:1;
-                uint64_t switch_val:1;
-                uint64_t cmd_val:1;
-                uint64_t bus_id:2;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_mio_emm_rsp_sts_s cn61xx;
-        struct cvmx_mio_emm_rsp_sts_s cnf71xx;
-};
-
-union cvmx_mio_emm_sample {
-        uint64_t u64;
-        struct cvmx_mio_emm_sample_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_26_63:38;
-                uint64_t cmd_cnt:10;
-                uint64_t reserved_10_15:6;
-                uint64_t dat_cnt:10;
-#else
-                uint64_t dat_cnt:10;
-                uint64_t reserved_10_15:6;
-                uint64_t cmd_cnt:10;
-                uint64_t reserved_26_63:38;
-#endif
-        } s;
-        struct cvmx_mio_emm_sample_s cn61xx;
-        struct cvmx_mio_emm_sample_s cnf71xx;
-};
-
-union cvmx_mio_emm_sts_mask {
-        uint64_t u64;
-        struct cvmx_mio_emm_sts_mask_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t sts_msk:32;
-#else
-                uint64_t sts_msk:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_mio_emm_sts_mask_s cn61xx;
-        struct cvmx_mio_emm_sts_mask_s cnf71xx;
-};
-
-union cvmx_mio_emm_switch {
-        uint64_t u64;
-        struct cvmx_mio_emm_switch_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t bus_id:2;
-                uint64_t switch_exe:1;
-                uint64_t switch_err0:1;
-                uint64_t switch_err1:1;
-                uint64_t switch_err2:1;
-                uint64_t reserved_49_55:7;
-                uint64_t hs_timing:1;
-                uint64_t reserved_43_47:5;
-                uint64_t bus_width:3;
-                uint64_t reserved_36_39:4;
-                uint64_t power_class:4;
-                uint64_t clk_hi:16;
-                uint64_t clk_lo:16;
-#else
-                uint64_t clk_lo:16;
-                uint64_t clk_hi:16;
-                uint64_t power_class:4;
-                uint64_t reserved_36_39:4;
-                uint64_t bus_width:3;
-                uint64_t reserved_43_47:5;
-                uint64_t hs_timing:1;
-                uint64_t reserved_49_55:7;
-                uint64_t switch_err2:1;
-                uint64_t switch_err1:1;
-                uint64_t switch_err0:1;
-                uint64_t switch_exe:1;
-                uint64_t bus_id:2;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_mio_emm_switch_s cn61xx;
-        struct cvmx_mio_emm_switch_s cnf71xx;
-};
-
-union cvmx_mio_emm_wdog {
-        uint64_t u64;
-        struct cvmx_mio_emm_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_26_63:38;
-                uint64_t clk_cnt:26;
-#else
-                uint64_t clk_cnt:26;
-                uint64_t reserved_26_63:38;
-#endif
-        } s;
-        struct cvmx_mio_emm_wdog_s cn61xx;
-        struct cvmx_mio_emm_wdog_s cnf71xx;
 };
 
 union cvmx_mio_fus_bnk_datx {
         uint64_t u64;
         struct cvmx_mio_fus_bnk_datx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dat:64;
-#else
                 uint64_t dat:64;
-#endif
         } s;
         struct cvmx_mio_fus_bnk_datx_s cn50xx;
         struct cvmx_mio_fus_bnk_datx_s cn52xx;
@@ -1406,25 +590,15 @@ union cvmx_mio_fus_bnk_datx {
         struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
         struct cvmx_mio_fus_bnk_datx_s cn58xx;
         struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
-        struct cvmx_mio_fus_bnk_datx_s cn61xx;
         struct cvmx_mio_fus_bnk_datx_s cn63xx;
         struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
-        struct cvmx_mio_fus_bnk_datx_s cn66xx;
-        struct cvmx_mio_fus_bnk_datx_s cn68xx;
-        struct cvmx_mio_fus_bnk_datx_s cn68xxp1;
-        struct cvmx_mio_fus_bnk_datx_s cnf71xx;
 };
 
 union cvmx_mio_fus_dat0 {
         uint64_t u64;
         struct cvmx_mio_fus_dat0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t man_info:32;
-#else
-                uint64_t man_info:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_mio_fus_dat0_s cn30xx;
         struct cvmx_mio_fus_dat0_s cn31xx;
@@ -1437,25 +611,15 @@ union cvmx_mio_fus_dat0 {
         struct cvmx_mio_fus_dat0_s cn56xxp1;
         struct cvmx_mio_fus_dat0_s cn58xx;
         struct cvmx_mio_fus_dat0_s cn58xxp1;
-        struct cvmx_mio_fus_dat0_s cn61xx;
         struct cvmx_mio_fus_dat0_s cn63xx;
         struct cvmx_mio_fus_dat0_s cn63xxp1;
-        struct cvmx_mio_fus_dat0_s cn66xx;
-        struct cvmx_mio_fus_dat0_s cn68xx;
-        struct cvmx_mio_fus_dat0_s cn68xxp1;
-        struct cvmx_mio_fus_dat0_s cnf71xx;
 };
 
 union cvmx_mio_fus_dat1 {
         uint64_t u64;
         struct cvmx_mio_fus_dat1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t man_info:32;
-#else
-                uint64_t man_info:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_mio_fus_dat1_s cn30xx;
         struct cvmx_mio_fus_dat1_s cn31xx;
@@ -1468,23 +632,14 @@ union cvmx_mio_fus_dat1 {
         struct cvmx_mio_fus_dat1_s cn56xxp1;
         struct cvmx_mio_fus_dat1_s cn58xx;
         struct cvmx_mio_fus_dat1_s cn58xxp1;
-        struct cvmx_mio_fus_dat1_s cn61xx;
         struct cvmx_mio_fus_dat1_s cn63xx;
         struct cvmx_mio_fus_dat1_s cn63xxp1;
-        struct cvmx_mio_fus_dat1_s cn66xx;
-        struct cvmx_mio_fus_dat1_s cn68xx;
-        struct cvmx_mio_fus_dat1_s cn68xxp1;
-        struct cvmx_mio_fus_dat1_s cnf71xx;
 };
 
 union cvmx_mio_fus_dat2 {
         uint64_t u64;
         struct cvmx_mio_fus_dat2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t fus118:1;
-                uint64_t rom_info:10;
-                uint64_t power_limit:2;
+                uint64_t reserved_35_63:29;
                 uint64_t dorm_crypto:1;
                 uint64_t fus318:1;
                 uint64_t raid_en:1;
@@ -1497,27 +652,8 @@ union cvmx_mio_fus_dat2 {
                 uint64_t bist_dis:1;
                 uint64_t chip_id:8;
                 uint64_t reserved_0_15:16;
-#else
-                uint64_t reserved_0_15:16;
-                uint64_t chip_id:8;
-                uint64_t bist_dis:1;
-                uint64_t rst_sht:1;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t nokasu:1;
-                uint64_t reserved_30_31:2;
-                uint64_t raid_en:1;
-                uint64_t fus318:1;
-                uint64_t dorm_crypto:1;
-                uint64_t power_limit:2;
-                uint64_t rom_info:10;
-                uint64_t fus118:1;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_mio_fus_dat2_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t nodfa_cp2:1;
                 uint64_t nomul:1;
@@ -1528,21 +664,8 @@ union cvmx_mio_fus_dat2 {
                 uint64_t pll_off:4;
                 uint64_t reserved_1_11:11;
                 uint64_t pp_dis:1;
-#else
-                uint64_t pp_dis:1;
-                uint64_t reserved_1_11:11;
-                uint64_t pll_off:4;
-                uint64_t chip_id:8;
-                uint64_t bist_dis:1;
-                uint64_t rst_sht:1;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn30xx;
         struct cvmx_mio_fus_dat2_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t nodfa_cp2:1;
                 uint64_t nomul:1;
@@ -1553,21 +676,8 @@ union cvmx_mio_fus_dat2 {
                 uint64_t pll_off:4;
                 uint64_t reserved_2_11:10;
                 uint64_t pp_dis:2;
-#else
-                uint64_t pp_dis:2;
-                uint64_t reserved_2_11:10;
-                uint64_t pll_off:4;
-                uint64_t chip_id:8;
-                uint64_t bist_dis:1;
-                uint64_t rst_sht:1;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn31xx;
         struct cvmx_mio_fus_dat2_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t nodfa_cp2:1;
                 uint64_t nomul:1;
@@ -1576,20 +686,9 @@ union cvmx_mio_fus_dat2 {
                 uint64_t bist_dis:1;
                 uint64_t chip_id:8;
                 uint64_t pp_dis:16;
-#else
-                uint64_t pp_dis:16;
-                uint64_t chip_id:8;
-                uint64_t bist_dis:1;
-                uint64_t rst_sht:1;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn38xx;
         struct cvmx_mio_fus_dat2_cn38xx cn38xxp2;
         struct cvmx_mio_fus_dat2_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t fus318:1;
                 uint64_t raid_en:1;
@@ -1603,24 +702,8 @@ union cvmx_mio_fus_dat2 {
                 uint64_t chip_id:8;
                 uint64_t reserved_2_15:14;
                 uint64_t pp_dis:2;
-#else
-                uint64_t pp_dis:2;
-                uint64_t reserved_2_15:14;
-                uint64_t chip_id:8;
-                uint64_t bist_dis:1;
-                uint64_t rst_sht:1;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t nokasu:1;
-                uint64_t reserved_30_31:2;
-                uint64_t raid_en:1;
-                uint64_t fus318:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn50xx;
         struct cvmx_mio_fus_dat2_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t fus318:1;
                 uint64_t raid_en:1;
@@ -1634,25 +717,9 @@ union cvmx_mio_fus_dat2 {
                 uint64_t chip_id:8;
                 uint64_t reserved_4_15:12;
                 uint64_t pp_dis:4;
-#else
-                uint64_t pp_dis:4;
-                uint64_t reserved_4_15:12;
-                uint64_t chip_id:8;
-                uint64_t bist_dis:1;
-                uint64_t rst_sht:1;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t nokasu:1;
-                uint64_t reserved_30_31:2;
-                uint64_t raid_en:1;
-                uint64_t fus318:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn52xx;
         struct cvmx_mio_fus_dat2_cn52xx cn52xxp1;
         struct cvmx_mio_fus_dat2_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t fus318:1;
                 uint64_t raid_en:1;
@@ -1666,25 +733,9 @@ union cvmx_mio_fus_dat2 {
                 uint64_t chip_id:8;
                 uint64_t reserved_12_15:4;
                 uint64_t pp_dis:12;
-#else
-                uint64_t pp_dis:12;
-                uint64_t reserved_12_15:4;
-                uint64_t chip_id:8;
-                uint64_t bist_dis:1;
-                uint64_t rst_sht:1;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t nokasu:1;
-                uint64_t reserved_30_31:2;
-                uint64_t raid_en:1;
-                uint64_t fus318:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn56xx;
         struct cvmx_mio_fus_dat2_cn56xx cn56xxp1;
         struct cvmx_mio_fus_dat2_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_30_63:34;
                 uint64_t nokasu:1;
                 uint64_t nodfa_cp2:1;
@@ -1694,56 +745,9 @@ union cvmx_mio_fus_dat2 {
                 uint64_t bist_dis:1;
                 uint64_t chip_id:8;
                 uint64_t pp_dis:16;
-#else
-                uint64_t pp_dis:16;
-                uint64_t chip_id:8;
-                uint64_t bist_dis:1;
-                uint64_t rst_sht:1;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t nokasu:1;
-                uint64_t reserved_30_63:34;
-#endif
         } cn58xx;
         struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
-        struct cvmx_mio_fus_dat2_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t fus118:1;
-                uint64_t rom_info:10;
-                uint64_t power_limit:2;
-                uint64_t dorm_crypto:1;
-                uint64_t fus318:1;
-                uint64_t raid_en:1;
-                uint64_t reserved_29_31:3;
-                uint64_t nodfa_cp2:1;
-                uint64_t nomul:1;
-                uint64_t nocrypto:1;
-                uint64_t reserved_24_25:2;
-                uint64_t chip_id:8;
-                uint64_t reserved_4_15:12;
-                uint64_t pp_dis:4;
-#else
-                uint64_t pp_dis:4;
-                uint64_t reserved_4_15:12;
-                uint64_t chip_id:8;
-                uint64_t reserved_24_25:2;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t reserved_29_31:3;
-                uint64_t raid_en:1;
-                uint64_t fus318:1;
-                uint64_t dorm_crypto:1;
-                uint64_t power_limit:2;
-                uint64_t rom_info:10;
-                uint64_t fus118:1;
-                uint64_t reserved_48_63:16;
-#endif
-        } cn61xx;
         struct cvmx_mio_fus_dat2_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_35_63:29;
                 uint64_t dorm_crypto:1;
                 uint64_t fus318:1;
@@ -1756,94 +760,13 @@ union cvmx_mio_fus_dat2 {
                 uint64_t chip_id:8;
                 uint64_t reserved_6_15:10;
                 uint64_t pp_dis:6;
-#else
-                uint64_t pp_dis:6;
-                uint64_t reserved_6_15:10;
-                uint64_t chip_id:8;
-                uint64_t reserved_24_25:2;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t reserved_29_31:3;
-                uint64_t raid_en:1;
-                uint64_t fus318:1;
-                uint64_t dorm_crypto:1;
-                uint64_t reserved_35_63:29;
-#endif
         } cn63xx;
         struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
-        struct cvmx_mio_fus_dat2_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t fus118:1;
-                uint64_t rom_info:10;
-                uint64_t power_limit:2;
-                uint64_t dorm_crypto:1;
-                uint64_t fus318:1;
-                uint64_t raid_en:1;
-                uint64_t reserved_29_31:3;
-                uint64_t nodfa_cp2:1;
-                uint64_t nomul:1;
-                uint64_t nocrypto:1;
-                uint64_t reserved_24_25:2;
-                uint64_t chip_id:8;
-                uint64_t reserved_10_15:6;
-                uint64_t pp_dis:10;
-#else
-                uint64_t pp_dis:10;
-                uint64_t reserved_10_15:6;
-                uint64_t chip_id:8;
-                uint64_t reserved_24_25:2;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t reserved_29_31:3;
-                uint64_t raid_en:1;
-                uint64_t fus318:1;
-                uint64_t dorm_crypto:1;
-                uint64_t power_limit:2;
-                uint64_t rom_info:10;
-                uint64_t fus118:1;
-                uint64_t reserved_48_63:16;
-#endif
-        } cn66xx;
-        struct cvmx_mio_fus_dat2_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_37_63:27;
-                uint64_t power_limit:2;
-                uint64_t dorm_crypto:1;
-                uint64_t fus318:1;
-                uint64_t raid_en:1;
-                uint64_t reserved_29_31:3;
-                uint64_t nodfa_cp2:1;
-                uint64_t nomul:1;
-                uint64_t nocrypto:1;
-                uint64_t reserved_24_25:2;
-                uint64_t chip_id:8;
-                uint64_t reserved_0_15:16;
-#else
-                uint64_t reserved_0_15:16;
-                uint64_t chip_id:8;
-                uint64_t reserved_24_25:2;
-                uint64_t nocrypto:1;
-                uint64_t nomul:1;
-                uint64_t nodfa_cp2:1;
-                uint64_t reserved_29_31:3;
-                uint64_t raid_en:1;
-                uint64_t fus318:1;
-                uint64_t dorm_crypto:1;
-                uint64_t power_limit:2;
-                uint64_t reserved_37_63:27;
-#endif
-        } cn68xx;
-        struct cvmx_mio_fus_dat2_cn68xx cn68xxp1;
-        struct cvmx_mio_fus_dat2_cn61xx cnf71xx;
 };
 
 union cvmx_mio_fus_dat3 {
         uint64_t u64;
         struct cvmx_mio_fus_dat3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_58_63:6;
                 uint64_t pll_ctl:10;
                 uint64_t dfa_info_dte:3;
@@ -1862,29 +785,8 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nozip:1;
                 uint64_t nodfa_dte:1;
                 uint64_t icache:24;
-#else
-                uint64_t icache:24;
-                uint64_t nodfa_dte:1;
-                uint64_t nozip:1;
-                uint64_t efus_ign:1;
-                uint64_t efus_lck:1;
-                uint64_t bar2_en:1;
-                uint64_t reserved_29_30:2;
-                uint64_t pll_div4:1;
-                uint64_t l2c_crip:3;
-                uint64_t pll_half_dis:1;
-                uint64_t efus_lck_man:1;
-                uint64_t efus_lck_rsv:1;
-                uint64_t ema:2;
-                uint64_t reserved_40_40:1;
-                uint64_t dfa_info_clm:4;
-                uint64_t dfa_info_dte:3;
-                uint64_t pll_ctl:10;
-                uint64_t reserved_58_63:6;
-#endif
         } s;
         struct cvmx_mio_fus_dat3_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t pll_div4:1;
                 uint64_t reserved_29_30:2;
@@ -1894,20 +796,8 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nozip:1;
                 uint64_t nodfa_dte:1;
                 uint64_t icache:24;
-#else
-                uint64_t icache:24;
-                uint64_t nodfa_dte:1;
-                uint64_t nozip:1;
-                uint64_t efus_ign:1;
-                uint64_t efus_lck:1;
-                uint64_t bar2_en:1;
-                uint64_t reserved_29_30:2;
-                uint64_t pll_div4:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn30xx;
         struct cvmx_mio_fus_dat3_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t pll_div4:1;
                 uint64_t zip_crip:2;
@@ -1917,20 +807,8 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nozip:1;
                 uint64_t nodfa_dte:1;
                 uint64_t icache:24;
-#else
-                uint64_t icache:24;
-                uint64_t nodfa_dte:1;
-                uint64_t nozip:1;
-                uint64_t efus_ign:1;
-                uint64_t efus_lck:1;
-                uint64_t bar2_en:1;
-                uint64_t zip_crip:2;
-                uint64_t pll_div4:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn31xx;
         struct cvmx_mio_fus_dat3_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_31_63:33;
                 uint64_t zip_crip:2;
                 uint64_t bar2_en:1;
@@ -1939,19 +817,8 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nozip:1;
                 uint64_t nodfa_dte:1;
                 uint64_t icache:24;
-#else
-                uint64_t icache:24;
-                uint64_t nodfa_dte:1;
-                uint64_t nozip:1;
-                uint64_t efus_ign:1;
-                uint64_t efus_lck:1;
-                uint64_t bar2_en:1;
-                uint64_t zip_crip:2;
-                uint64_t reserved_31_63:33;
-#endif
         } cn38xx;
         struct cvmx_mio_fus_dat3_cn38xxp2 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t bar2_en:1;
                 uint64_t efus_lck:1;
@@ -1959,15 +826,6 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nozip:1;
                 uint64_t nodfa_dte:1;
                 uint64_t icache:24;
-#else
-                uint64_t icache:24;
-                uint64_t nodfa_dte:1;
-                uint64_t nozip:1;
-                uint64_t efus_ign:1;
-                uint64_t efus_lck:1;
-                uint64_t bar2_en:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn38xxp2;
         struct cvmx_mio_fus_dat3_cn38xx cn50xx;
         struct cvmx_mio_fus_dat3_cn38xx cn52xx;
@@ -1976,8 +834,7 @@ union cvmx_mio_fus_dat3 {
         struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
         struct cvmx_mio_fus_dat3_cn38xx cn58xx;
         struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
-        struct cvmx_mio_fus_dat3_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
+        struct cvmx_mio_fus_dat3_cn63xx {
                 uint64_t reserved_58_63:6;
                 uint64_t pll_ctl:10;
                 uint64_t dfa_info_dte:3;
@@ -1996,49 +853,17 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nozip:1;
                 uint64_t nodfa_dte:1;
                 uint64_t reserved_0_23:24;
-#else
-                uint64_t reserved_0_23:24;
-                uint64_t nodfa_dte:1;
-                uint64_t nozip:1;
-                uint64_t efus_ign:1;
-                uint64_t efus_lck:1;
-                uint64_t bar2_en:1;
-                uint64_t zip_info:2;
-                uint64_t reserved_31_31:1;
-                uint64_t l2c_crip:3;
-                uint64_t pll_half_dis:1;
-                uint64_t efus_lck_man:1;
-                uint64_t efus_lck_rsv:1;
-                uint64_t ema:2;
-                uint64_t reserved_40_40:1;
-                uint64_t dfa_info_clm:4;
-                uint64_t dfa_info_dte:3;
-                uint64_t pll_ctl:10;
-                uint64_t reserved_58_63:6;
-#endif
-        } cn61xx;
-        struct cvmx_mio_fus_dat3_cn61xx cn63xx;
-        struct cvmx_mio_fus_dat3_cn61xx cn63xxp1;
-        struct cvmx_mio_fus_dat3_cn61xx cn66xx;
-        struct cvmx_mio_fus_dat3_cn61xx cn68xx;
-        struct cvmx_mio_fus_dat3_cn61xx cn68xxp1;
-        struct cvmx_mio_fus_dat3_cn61xx cnf71xx;
+        } cn63xx;
+        struct cvmx_mio_fus_dat3_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_fus_ema {
         uint64_t u64;
         struct cvmx_mio_fus_ema_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t eff_ema:3;
                 uint64_t reserved_3_3:1;
                 uint64_t ema:3;
-#else
-                uint64_t ema:3;
-                uint64_t reserved_3_3:1;
-                uint64_t eff_ema:3;
-                uint64_t reserved_7_63:57;
-#endif
         } s;
         struct cvmx_mio_fus_ema_s cn50xx;
         struct cvmx_mio_fus_ema_s cn52xx;
@@ -2046,32 +871,18 @@ union cvmx_mio_fus_ema {
         struct cvmx_mio_fus_ema_s cn56xx;
         struct cvmx_mio_fus_ema_s cn56xxp1;
         struct cvmx_mio_fus_ema_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t ema:2;
-#else
-                uint64_t ema:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn58xx;
         struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
-        struct cvmx_mio_fus_ema_s cn61xx;
         struct cvmx_mio_fus_ema_s cn63xx;
         struct cvmx_mio_fus_ema_s cn63xxp1;
-        struct cvmx_mio_fus_ema_s cn66xx;
-        struct cvmx_mio_fus_ema_s cn68xx;
-        struct cvmx_mio_fus_ema_s cn68xxp1;
-        struct cvmx_mio_fus_ema_s cnf71xx;
 };
 
 union cvmx_mio_fus_pdf {
         uint64_t u64;
         struct cvmx_mio_fus_pdf_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t pdf:64;
-#else
-                uint64_t pdf:64;
-#endif
         } s;
         struct cvmx_mio_fus_pdf_s cn50xx;
         struct cvmx_mio_fus_pdf_s cn52xx;
@@ -2079,52 +890,25 @@ union cvmx_mio_fus_pdf {
         struct cvmx_mio_fus_pdf_s cn56xx;
         struct cvmx_mio_fus_pdf_s cn56xxp1;
         struct cvmx_mio_fus_pdf_s cn58xx;
-        struct cvmx_mio_fus_pdf_s cn61xx;
         struct cvmx_mio_fus_pdf_s cn63xx;
         struct cvmx_mio_fus_pdf_s cn63xxp1;
-        struct cvmx_mio_fus_pdf_s cn66xx;
-        struct cvmx_mio_fus_pdf_s cn68xx;
-        struct cvmx_mio_fus_pdf_s cn68xxp1;
-        struct cvmx_mio_fus_pdf_s cnf71xx;
 };
 
 union cvmx_mio_fus_pll {
         uint64_t u64;
         struct cvmx_mio_fus_pll_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t rclk_align_r:8;
-                uint64_t rclk_align_l:8;
-                uint64_t reserved_8_31:24;
+                uint64_t reserved_8_63:56;
                 uint64_t c_cout_rst:1;
                 uint64_t c_cout_sel:2;
                 uint64_t pnr_cout_rst:1;
                 uint64_t pnr_cout_sel:2;
                 uint64_t rfslip:1;
                 uint64_t fbslip:1;
-#else
-                uint64_t fbslip:1;
-                uint64_t rfslip:1;
-                uint64_t pnr_cout_sel:2;
-                uint64_t pnr_cout_rst:1;
-                uint64_t c_cout_sel:2;
-                uint64_t c_cout_rst:1;
-                uint64_t reserved_8_31:24;
-                uint64_t rclk_align_l:8;
-                uint64_t rclk_align_r:8;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_mio_fus_pll_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t rfslip:1;
                 uint64_t fbslip:1;
-#else
-                uint64_t fbslip:1;
-                uint64_t rfslip:1;
-                uint64_t reserved_2_63:62;
-#endif
         } cn50xx;
         struct cvmx_mio_fus_pll_cn50xx cn52xx;
         struct cvmx_mio_fus_pll_cn50xx cn52xxp1;
@@ -2132,54 +916,20 @@ union cvmx_mio_fus_pll {
         struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
         struct cvmx_mio_fus_pll_cn50xx cn58xx;
         struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
-        struct cvmx_mio_fus_pll_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t c_cout_rst:1;
-                uint64_t c_cout_sel:2;
-                uint64_t pnr_cout_rst:1;
-                uint64_t pnr_cout_sel:2;
-                uint64_t rfslip:1;
-                uint64_t fbslip:1;
-#else
-                uint64_t fbslip:1;
-                uint64_t rfslip:1;
-                uint64_t pnr_cout_sel:2;
-                uint64_t pnr_cout_rst:1;
-                uint64_t c_cout_sel:2;
-                uint64_t c_cout_rst:1;
-                uint64_t reserved_8_63:56;
-#endif
-        } cn61xx;
-        struct cvmx_mio_fus_pll_cn61xx cn63xx;
-        struct cvmx_mio_fus_pll_cn61xx cn63xxp1;
-        struct cvmx_mio_fus_pll_cn61xx cn66xx;
-        struct cvmx_mio_fus_pll_s cn68xx;
-        struct cvmx_mio_fus_pll_s cn68xxp1;
-        struct cvmx_mio_fus_pll_cn61xx cnf71xx;
+        struct cvmx_mio_fus_pll_s cn63xx;
+        struct cvmx_mio_fus_pll_s cn63xxp1;
 };
 
 union cvmx_mio_fus_prog {
         uint64_t u64;
         struct cvmx_mio_fus_prog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t soft:1;
                 uint64_t prog:1;
-#else
-                uint64_t prog:1;
-                uint64_t soft:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_mio_fus_prog_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t prog:1;
-#else
-                uint64_t prog:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn30xx;
         struct cvmx_mio_fus_prog_cn30xx cn31xx;
         struct cvmx_mio_fus_prog_cn30xx cn38xx;
@@ -2191,50 +941,27 @@ union cvmx_mio_fus_prog {
         struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
         struct cvmx_mio_fus_prog_cn30xx cn58xx;
         struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
-        struct cvmx_mio_fus_prog_s cn61xx;
         struct cvmx_mio_fus_prog_s cn63xx;
         struct cvmx_mio_fus_prog_s cn63xxp1;
-        struct cvmx_mio_fus_prog_s cn66xx;
-        struct cvmx_mio_fus_prog_s cn68xx;
-        struct cvmx_mio_fus_prog_s cn68xxp1;
-        struct cvmx_mio_fus_prog_s cnf71xx;
 };
 
 union cvmx_mio_fus_prog_times {
         uint64_t u64;
         struct cvmx_mio_fus_prog_times_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_35_63:29;
                 uint64_t vgate_pin:1;
                 uint64_t fsrc_pin:1;
                 uint64_t prog_pin:1;
                 uint64_t reserved_6_31:26;
                 uint64_t setup:6;
-#else
-                uint64_t setup:6;
-                uint64_t reserved_6_31:26;
-                uint64_t prog_pin:1;
-                uint64_t fsrc_pin:1;
-                uint64_t vgate_pin:1;
-                uint64_t reserved_35_63:29;
-#endif
         } s;
         struct cvmx_mio_fus_prog_times_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_33_63:31;
                 uint64_t prog_pin:1;
                 uint64_t out:8;
                 uint64_t sclk_lo:4;
                 uint64_t sclk_hi:12;
                 uint64_t setup:8;
-#else
-                uint64_t setup:8;
-                uint64_t sclk_hi:12;
-                uint64_t sclk_lo:4;
-                uint64_t out:8;
-                uint64_t prog_pin:1;
-                uint64_t reserved_33_63:31;
-#endif
         } cn50xx;
         struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
         struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
@@ -2242,8 +969,7 @@ union cvmx_mio_fus_prog_times {
         struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
         struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
         struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
-        struct cvmx_mio_fus_prog_times_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
+        struct cvmx_mio_fus_prog_times_cn63xx {
                 uint64_t reserved_35_63:29;
                 uint64_t vgate_pin:1;
                 uint64_t fsrc_pin:1;
@@ -2252,29 +978,13 @@ union cvmx_mio_fus_prog_times {
                 uint64_t sclk_lo:4;
                 uint64_t sclk_hi:15;
                 uint64_t setup:6;
-#else
-                uint64_t setup:6;
-                uint64_t sclk_hi:15;
-                uint64_t sclk_lo:4;
-                uint64_t out:7;
-                uint64_t prog_pin:1;
-                uint64_t fsrc_pin:1;
-                uint64_t vgate_pin:1;
-                uint64_t reserved_35_63:29;
-#endif
-        } cn61xx;
-        struct cvmx_mio_fus_prog_times_cn61xx cn63xx;
-        struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1;
-        struct cvmx_mio_fus_prog_times_cn61xx cn66xx;
-        struct cvmx_mio_fus_prog_times_cn61xx cn68xx;
-        struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1;
-        struct cvmx_mio_fus_prog_times_cn61xx cnf71xx;
+        } cn63xx;
+        struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_fus_rcmd {
         uint64_t u64;
         struct cvmx_mio_fus_rcmd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t dat:8;
                 uint64_t reserved_13_15:3;
@@ -2282,18 +992,8 @@ union cvmx_mio_fus_rcmd {
                 uint64_t reserved_9_11:3;
                 uint64_t efuse:1;
                 uint64_t addr:8;
-#else
-                uint64_t addr:8;
-                uint64_t efuse:1;
-                uint64_t reserved_9_11:3;
-                uint64_t pend:1;
-                uint64_t reserved_13_15:3;
-                uint64_t dat:8;
-                uint64_t reserved_24_63:40;
-#endif
         } s;
         struct cvmx_mio_fus_rcmd_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t dat:8;
                 uint64_t reserved_13_15:3;
@@ -2302,16 +1002,6 @@ union cvmx_mio_fus_rcmd {
                 uint64_t efuse:1;
                 uint64_t reserved_7_7:1;
                 uint64_t addr:7;
-#else
-                uint64_t addr:7;
-                uint64_t reserved_7_7:1;
-                uint64_t efuse:1;
-                uint64_t reserved_9_11:3;
-                uint64_t pend:1;
-                uint64_t reserved_13_15:3;
-                uint64_t dat:8;
-                uint64_t reserved_24_63:40;
-#endif
         } cn30xx;
         struct cvmx_mio_fus_rcmd_cn30xx cn31xx;
         struct cvmx_mio_fus_rcmd_cn30xx cn38xx;
@@ -2323,127 +1013,66 @@ union cvmx_mio_fus_rcmd {
         struct cvmx_mio_fus_rcmd_s cn56xxp1;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
-        struct cvmx_mio_fus_rcmd_s cn61xx;
         struct cvmx_mio_fus_rcmd_s cn63xx;
         struct cvmx_mio_fus_rcmd_s cn63xxp1;
-        struct cvmx_mio_fus_rcmd_s cn66xx;
-        struct cvmx_mio_fus_rcmd_s cn68xx;
-        struct cvmx_mio_fus_rcmd_s cn68xxp1;
-        struct cvmx_mio_fus_rcmd_s cnf71xx;
 };
 
 union cvmx_mio_fus_read_times {
         uint64_t u64;
         struct cvmx_mio_fus_read_times_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_26_63:38;
                 uint64_t sch:4;
                 uint64_t fsh:4;
                 uint64_t prh:4;
                 uint64_t sdh:4;
                 uint64_t setup:10;
-#else
-                uint64_t setup:10;
-                uint64_t sdh:4;
-                uint64_t prh:4;
-                uint64_t fsh:4;
-                uint64_t sch:4;
-                uint64_t reserved_26_63:38;
-#endif
         } s;
-        struct cvmx_mio_fus_read_times_s cn61xx;
         struct cvmx_mio_fus_read_times_s cn63xx;
         struct cvmx_mio_fus_read_times_s cn63xxp1;
-        struct cvmx_mio_fus_read_times_s cn66xx;
-        struct cvmx_mio_fus_read_times_s cn68xx;
-        struct cvmx_mio_fus_read_times_s cn68xxp1;
-        struct cvmx_mio_fus_read_times_s cnf71xx;
 };
 
 union cvmx_mio_fus_repair_res0 {
         uint64_t u64;
         struct cvmx_mio_fus_repair_res0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_55_63:9;
                 uint64_t too_many:1;
                 uint64_t repair2:18;
                 uint64_t repair1:18;
                 uint64_t repair0:18;
-#else
-                uint64_t repair0:18;
-                uint64_t repair1:18;
-                uint64_t repair2:18;
-                uint64_t too_many:1;
-                uint64_t reserved_55_63:9;
-#endif
         } s;
-        struct cvmx_mio_fus_repair_res0_s cn61xx;
         struct cvmx_mio_fus_repair_res0_s cn63xx;
         struct cvmx_mio_fus_repair_res0_s cn63xxp1;
-        struct cvmx_mio_fus_repair_res0_s cn66xx;
-        struct cvmx_mio_fus_repair_res0_s cn68xx;
-        struct cvmx_mio_fus_repair_res0_s cn68xxp1;
-        struct cvmx_mio_fus_repair_res0_s cnf71xx;
 };
 
 union cvmx_mio_fus_repair_res1 {
         uint64_t u64;
         struct cvmx_mio_fus_repair_res1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_54_63:10;
                 uint64_t repair5:18;
                 uint64_t repair4:18;
                 uint64_t repair3:18;
-#else
-                uint64_t repair3:18;
-                uint64_t repair4:18;
-                uint64_t repair5:18;
-                uint64_t reserved_54_63:10;
-#endif
         } s;
-        struct cvmx_mio_fus_repair_res1_s cn61xx;
         struct cvmx_mio_fus_repair_res1_s cn63xx;
         struct cvmx_mio_fus_repair_res1_s cn63xxp1;
-        struct cvmx_mio_fus_repair_res1_s cn66xx;
-        struct cvmx_mio_fus_repair_res1_s cn68xx;
-        struct cvmx_mio_fus_repair_res1_s cn68xxp1;
-        struct cvmx_mio_fus_repair_res1_s cnf71xx;
 };
 
 union cvmx_mio_fus_repair_res2 {
         uint64_t u64;
         struct cvmx_mio_fus_repair_res2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t repair6:18;
-#else
-                uint64_t repair6:18;
-                uint64_t reserved_18_63:46;
-#endif
         } s;
-        struct cvmx_mio_fus_repair_res2_s cn61xx;
         struct cvmx_mio_fus_repair_res2_s cn63xx;
         struct cvmx_mio_fus_repair_res2_s cn63xxp1;
-        struct cvmx_mio_fus_repair_res2_s cn66xx;
-        struct cvmx_mio_fus_repair_res2_s cn68xx;
-        struct cvmx_mio_fus_repair_res2_s cn68xxp1;
-        struct cvmx_mio_fus_repair_res2_s cnf71xx;
 };
 
 union cvmx_mio_fus_spr_repair_res {
         uint64_t u64;
         struct cvmx_mio_fus_spr_repair_res_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_42_63:22;
                 uint64_t repair2:14;
                 uint64_t repair1:14;
                 uint64_t repair0:14;
-#else
-                uint64_t repair0:14;
-                uint64_t repair1:14;
-                uint64_t repair2:14;
-                uint64_t reserved_42_63:22;
-#endif
         } s;
         struct cvmx_mio_fus_spr_repair_res_s cn30xx;
         struct cvmx_mio_fus_spr_repair_res_s cn31xx;
@@ -2455,25 +1084,15 @@ union cvmx_mio_fus_spr_repair_res {
         struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_res_s cn58xx;
         struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
-        struct cvmx_mio_fus_spr_repair_res_s cn61xx;
         struct cvmx_mio_fus_spr_repair_res_s cn63xx;
         struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
-        struct cvmx_mio_fus_spr_repair_res_s cn66xx;
-        struct cvmx_mio_fus_spr_repair_res_s cn68xx;
-        struct cvmx_mio_fus_spr_repair_res_s cn68xxp1;
-        struct cvmx_mio_fus_spr_repair_res_s cnf71xx;
 };
 
 union cvmx_mio_fus_spr_repair_sum {
         uint64_t u64;
         struct cvmx_mio_fus_spr_repair_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t too_many:1;
-#else
-                uint64_t too_many:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
@@ -2485,41 +1104,15 @@ union cvmx_mio_fus_spr_repair_sum {
         struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
-        struct cvmx_mio_fus_spr_repair_sum_s cn61xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
-        struct cvmx_mio_fus_spr_repair_sum_s cn66xx;
-        struct cvmx_mio_fus_spr_repair_sum_s cn68xx;
-        struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1;
-        struct cvmx_mio_fus_spr_repair_sum_s cnf71xx;
-};
-
-union cvmx_mio_fus_tgg {
-        uint64_t u64;
-        struct cvmx_mio_fus_tgg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t val:1;
-                uint64_t dat:63;
-#else
-                uint64_t dat:63;
-                uint64_t val:1;
-#endif
-        } s;
-        struct cvmx_mio_fus_tgg_s cn61xx;
-        struct cvmx_mio_fus_tgg_s cn66xx;
-        struct cvmx_mio_fus_tgg_s cnf71xx;
 };
 
 union cvmx_mio_fus_unlock {
         uint64_t u64;
         struct cvmx_mio_fus_unlock_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t key:24;
-#else
-                uint64_t key:24;
-                uint64_t reserved_24_63:40;
-#endif
         } s;
         struct cvmx_mio_fus_unlock_s cn30xx;
         struct cvmx_mio_fus_unlock_s cn31xx;
@@ -2528,84 +1121,47 @@ union cvmx_mio_fus_unlock {
 union cvmx_mio_fus_wadr {
         uint64_t u64;
         struct cvmx_mio_fus_wadr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t addr:10;
-#else
-                uint64_t addr:10;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_mio_fus_wadr_s cn30xx;
         struct cvmx_mio_fus_wadr_s cn31xx;
         struct cvmx_mio_fus_wadr_s cn38xx;
         struct cvmx_mio_fus_wadr_s cn38xxp2;
         struct cvmx_mio_fus_wadr_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t addr:2;
-#else
-                uint64_t addr:2;
-                uint64_t reserved_2_63:62;
-#endif
         } cn50xx;
         struct cvmx_mio_fus_wadr_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t addr:3;
-#else
-                uint64_t addr:3;
-                uint64_t reserved_3_63:61;
-#endif
         } cn52xx;
         struct cvmx_mio_fus_wadr_cn52xx cn52xxp1;
         struct cvmx_mio_fus_wadr_cn52xx cn56xx;
         struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
         struct cvmx_mio_fus_wadr_cn50xx cn58xx;
         struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
-        struct cvmx_mio_fus_wadr_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
+        struct cvmx_mio_fus_wadr_cn63xx {
                 uint64_t reserved_4_63:60;
                 uint64_t addr:4;
-#else
-                uint64_t addr:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } cn61xx;
-        struct cvmx_mio_fus_wadr_cn61xx cn63xx;
-        struct cvmx_mio_fus_wadr_cn61xx cn63xxp1;
-        struct cvmx_mio_fus_wadr_cn61xx cn66xx;
-        struct cvmx_mio_fus_wadr_cn61xx cn68xx;
-        struct cvmx_mio_fus_wadr_cn61xx cn68xxp1;
-        struct cvmx_mio_fus_wadr_cn61xx cnf71xx;
+        } cn63xx;
+        struct cvmx_mio_fus_wadr_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_gpio_comp {
         uint64_t u64;
         struct cvmx_mio_gpio_comp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t pctl:6;
                 uint64_t nctl:6;
-#else
-                uint64_t nctl:6;
-                uint64_t pctl:6;
-                uint64_t reserved_12_63:52;
-#endif
         } s;
-        struct cvmx_mio_gpio_comp_s cn61xx;
         struct cvmx_mio_gpio_comp_s cn63xx;
         struct cvmx_mio_gpio_comp_s cn63xxp1;
-        struct cvmx_mio_gpio_comp_s cn66xx;
-        struct cvmx_mio_gpio_comp_s cn68xx;
-        struct cvmx_mio_gpio_comp_s cn68xxp1;
-        struct cvmx_mio_gpio_comp_s cnf71xx;
 };
 
 union cvmx_mio_ndf_dma_cfg {
         uint64_t u64;
         struct cvmx_mio_ndf_dma_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t en:1;
                 uint64_t rw:1;
                 uint64_t clr:1;
@@ -2616,81 +1172,39 @@ union cvmx_mio_ndf_dma_cfg {
                 uint64_t endian:1;
                 uint64_t size:20;
                 uint64_t adr:36;
-#else
-                uint64_t adr:36;
-                uint64_t size:20;
-                uint64_t endian:1;
-                uint64_t swap8:1;
-                uint64_t swap16:1;
-                uint64_t swap32:1;
-                uint64_t reserved_60_60:1;
-                uint64_t clr:1;
-                uint64_t rw:1;
-                uint64_t en:1;
-#endif
         } s;
         struct cvmx_mio_ndf_dma_cfg_s cn52xx;
-        struct cvmx_mio_ndf_dma_cfg_s cn61xx;
         struct cvmx_mio_ndf_dma_cfg_s cn63xx;
         struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
-        struct cvmx_mio_ndf_dma_cfg_s cn66xx;
-        struct cvmx_mio_ndf_dma_cfg_s cn68xx;
-        struct cvmx_mio_ndf_dma_cfg_s cn68xxp1;
-        struct cvmx_mio_ndf_dma_cfg_s cnf71xx;
 };
 
 union cvmx_mio_ndf_dma_int {
         uint64_t u64;
         struct cvmx_mio_ndf_dma_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t done:1;
-#else
-                uint64_t done:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_ndf_dma_int_s cn52xx;
-        struct cvmx_mio_ndf_dma_int_s cn61xx;
         struct cvmx_mio_ndf_dma_int_s cn63xx;
         struct cvmx_mio_ndf_dma_int_s cn63xxp1;
-        struct cvmx_mio_ndf_dma_int_s cn66xx;
-        struct cvmx_mio_ndf_dma_int_s cn68xx;
-        struct cvmx_mio_ndf_dma_int_s cn68xxp1;
-        struct cvmx_mio_ndf_dma_int_s cnf71xx;
 };
 
 union cvmx_mio_ndf_dma_int_en {
         uint64_t u64;
         struct cvmx_mio_ndf_dma_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t done:1;
-#else
-                uint64_t done:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_ndf_dma_int_en_s cn52xx;
-        struct cvmx_mio_ndf_dma_int_en_s cn61xx;
         struct cvmx_mio_ndf_dma_int_en_s cn63xx;
         struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
-        struct cvmx_mio_ndf_dma_int_en_s cn66xx;
-        struct cvmx_mio_ndf_dma_int_en_s cn68xx;
-        struct cvmx_mio_ndf_dma_int_en_s cn68xxp1;
-        struct cvmx_mio_ndf_dma_int_en_s cnf71xx;
 };
 
 union cvmx_mio_pll_ctl {
         uint64_t u64;
         struct cvmx_mio_pll_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t bw_ctl:5;
-#else
-                uint64_t bw_ctl:5;
-                uint64_t reserved_5_63:59;
-#endif
         } s;
         struct cvmx_mio_pll_ctl_s cn30xx;
         struct cvmx_mio_pll_ctl_s cn31xx;
@@ -2699,134 +1213,16 @@ union cvmx_mio_pll_ctl {
 union cvmx_mio_pll_setting {
         uint64_t u64;
         struct cvmx_mio_pll_setting_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t setting:17;
-#else
-                uint64_t setting:17;
-                uint64_t reserved_17_63:47;
-#endif
         } s;
         struct cvmx_mio_pll_setting_s cn30xx;
         struct cvmx_mio_pll_setting_s cn31xx;
 };
 
-union cvmx_mio_ptp_ckout_hi_incr {
-        uint64_t u64;
-        struct cvmx_mio_ptp_ckout_hi_incr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t nanosec:32;
-                uint64_t frnanosec:32;
-#else
-                uint64_t frnanosec:32;
-                uint64_t nanosec:32;
-#endif
-        } s;
-        struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx;
-        struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx;
-        struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx;
-        struct cvmx_mio_ptp_ckout_hi_incr_s cnf71xx;
-};
-
-union cvmx_mio_ptp_ckout_lo_incr {
-        uint64_t u64;
-        struct cvmx_mio_ptp_ckout_lo_incr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t nanosec:32;
-                uint64_t frnanosec:32;
-#else
-                uint64_t frnanosec:32;
-                uint64_t nanosec:32;
-#endif
-        } s;
-        struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx;
-        struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx;
-        struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx;
-        struct cvmx_mio_ptp_ckout_lo_incr_s cnf71xx;
-};
-
-union cvmx_mio_ptp_ckout_thresh_hi {
-        uint64_t u64;
-        struct cvmx_mio_ptp_ckout_thresh_hi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t nanosec:64;
-#else
-                uint64_t nanosec:64;
-#endif
-        } s;
-        struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx;
-        struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx;
-        struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx;
-        struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx;
-};
-
-union cvmx_mio_ptp_ckout_thresh_lo {
-        uint64_t u64;
-        struct cvmx_mio_ptp_ckout_thresh_lo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t frnanosec:32;
-#else
-                uint64_t frnanosec:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx;
-        struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx;
-        struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx;
-        struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx;
-};
-
 union cvmx_mio_ptp_clock_cfg {
         uint64_t u64;
         struct cvmx_mio_ptp_clock_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_42_63:22;
-                uint64_t pps:1;
-                uint64_t ckout:1;
-                uint64_t ext_clk_edge:2;
-                uint64_t ckout_out4:1;
-                uint64_t pps_out:5;
-                uint64_t pps_inv:1;
-                uint64_t pps_en:1;
-                uint64_t ckout_out:4;
-                uint64_t ckout_inv:1;
-                uint64_t ckout_en:1;
-                uint64_t evcnt_in:6;
-                uint64_t evcnt_edge:1;
-                uint64_t evcnt_en:1;
-                uint64_t tstmp_in:6;
-                uint64_t tstmp_edge:1;
-                uint64_t tstmp_en:1;
-                uint64_t ext_clk_in:6;
-                uint64_t ext_clk_en:1;
-                uint64_t ptp_en:1;
-#else
-                uint64_t ptp_en:1;
-                uint64_t ext_clk_en:1;
-                uint64_t ext_clk_in:6;
-                uint64_t tstmp_en:1;
-                uint64_t tstmp_edge:1;
-                uint64_t tstmp_in:6;
-                uint64_t evcnt_en:1;
-                uint64_t evcnt_edge:1;
-                uint64_t evcnt_in:6;
-                uint64_t ckout_en:1;
-                uint64_t ckout_inv:1;
-                uint64_t ckout_out:4;
-                uint64_t pps_en:1;
-                uint64_t pps_inv:1;
-                uint64_t pps_out:5;
-                uint64_t ckout_out4:1;
-                uint64_t ext_clk_edge:2;
-                uint64_t ckout:1;
-                uint64_t pps:1;
-                uint64_t reserved_42_63:22;
-#endif
-        } s;
-        struct cvmx_mio_ptp_clock_cfg_s cn61xx;
-        struct cvmx_mio_ptp_clock_cfg_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t evcnt_in:6;
                 uint64_t evcnt_edge:1;
@@ -2837,487 +1233,62 @@ union cvmx_mio_ptp_clock_cfg {
                 uint64_t ext_clk_in:6;
                 uint64_t ext_clk_en:1;
                 uint64_t ptp_en:1;
-#else
-                uint64_t ptp_en:1;
-                uint64_t ext_clk_en:1;
-                uint64_t ext_clk_in:6;
-                uint64_t tstmp_en:1;
-                uint64_t tstmp_edge:1;
-                uint64_t tstmp_in:6;
-                uint64_t evcnt_en:1;
-                uint64_t evcnt_edge:1;
-                uint64_t evcnt_in:6;
-                uint64_t reserved_24_63:40;
-#endif
-        } cn63xx;
-        struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
-        struct cvmx_mio_ptp_clock_cfg_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_40_63:24;
-                uint64_t ext_clk_edge:2;
-                uint64_t ckout_out4:1;
-                uint64_t pps_out:5;
-                uint64_t pps_inv:1;
-                uint64_t pps_en:1;
-                uint64_t ckout_out:4;
-                uint64_t ckout_inv:1;
-                uint64_t ckout_en:1;
-                uint64_t evcnt_in:6;
-                uint64_t evcnt_edge:1;
-                uint64_t evcnt_en:1;
-                uint64_t tstmp_in:6;
-                uint64_t tstmp_edge:1;
-                uint64_t tstmp_en:1;
-                uint64_t ext_clk_in:6;
-                uint64_t ext_clk_en:1;
-                uint64_t ptp_en:1;
-#else
-                uint64_t ptp_en:1;
-                uint64_t ext_clk_en:1;
-                uint64_t ext_clk_in:6;
-                uint64_t tstmp_en:1;
-                uint64_t tstmp_edge:1;
-                uint64_t tstmp_in:6;
-                uint64_t evcnt_en:1;
-                uint64_t evcnt_edge:1;
-                uint64_t evcnt_in:6;
-                uint64_t ckout_en:1;
-                uint64_t ckout_inv:1;
-                uint64_t ckout_out:4;
-                uint64_t pps_en:1;
-                uint64_t pps_inv:1;
-                uint64_t pps_out:5;
-                uint64_t ckout_out4:1;
-                uint64_t ext_clk_edge:2;
-                uint64_t reserved_40_63:24;
-#endif
-        } cn66xx;
-        struct cvmx_mio_ptp_clock_cfg_s cn68xx;
-        struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
-        struct cvmx_mio_ptp_clock_cfg_s cnf71xx;
+        } s;
+        struct cvmx_mio_ptp_clock_cfg_s cn63xx;
+        struct cvmx_mio_ptp_clock_cfg_s cn63xxp1;
 };
 
 union cvmx_mio_ptp_clock_comp {
         uint64_t u64;
         struct cvmx_mio_ptp_clock_comp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t nanosec:32;
                 uint64_t frnanosec:32;
-#else
-                uint64_t frnanosec:32;
-                uint64_t nanosec:32;
-#endif
         } s;
-        struct cvmx_mio_ptp_clock_comp_s cn61xx;
         struct cvmx_mio_ptp_clock_comp_s cn63xx;
         struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
-        struct cvmx_mio_ptp_clock_comp_s cn66xx;
-        struct cvmx_mio_ptp_clock_comp_s cn68xx;
-        struct cvmx_mio_ptp_clock_comp_s cn68xxp1;
-        struct cvmx_mio_ptp_clock_comp_s cnf71xx;
 };
 
 union cvmx_mio_ptp_clock_hi {
         uint64_t u64;
         struct cvmx_mio_ptp_clock_hi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t nanosec:64;
-#else
                 uint64_t nanosec:64;
-#endif
         } s;
-        struct cvmx_mio_ptp_clock_hi_s cn61xx;
         struct cvmx_mio_ptp_clock_hi_s cn63xx;
         struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
-        struct cvmx_mio_ptp_clock_hi_s cn66xx;
-        struct cvmx_mio_ptp_clock_hi_s cn68xx;
-        struct cvmx_mio_ptp_clock_hi_s cn68xxp1;
-        struct cvmx_mio_ptp_clock_hi_s cnf71xx;
 };
 
 union cvmx_mio_ptp_clock_lo {
         uint64_t u64;
         struct cvmx_mio_ptp_clock_lo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t frnanosec:32;
-#else
-                uint64_t frnanosec:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
-        struct cvmx_mio_ptp_clock_lo_s cn61xx;
         struct cvmx_mio_ptp_clock_lo_s cn63xx;
         struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
-        struct cvmx_mio_ptp_clock_lo_s cn66xx;
-        struct cvmx_mio_ptp_clock_lo_s cn68xx;
-        struct cvmx_mio_ptp_clock_lo_s cn68xxp1;
-        struct cvmx_mio_ptp_clock_lo_s cnf71xx;
 };
 
 union cvmx_mio_ptp_evt_cnt {
         uint64_t u64;
         struct cvmx_mio_ptp_evt_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t cntr:64;
-#else
                 uint64_t cntr:64;
-#endif
         } s;
-        struct cvmx_mio_ptp_evt_cnt_s cn61xx;
         struct cvmx_mio_ptp_evt_cnt_s cn63xx;
         struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
-        struct cvmx_mio_ptp_evt_cnt_s cn66xx;
-        struct cvmx_mio_ptp_evt_cnt_s cn68xx;
-        struct cvmx_mio_ptp_evt_cnt_s cn68xxp1;
-        struct cvmx_mio_ptp_evt_cnt_s cnf71xx;
-};
-
-union cvmx_mio_ptp_phy_1pps_in {
-        uint64_t u64;
-        struct cvmx_mio_ptp_phy_1pps_in_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t sel:5;
-#else
-                uint64_t sel:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_mio_ptp_phy_1pps_in_s cnf71xx;
-};
-
-union cvmx_mio_ptp_pps_hi_incr {
-        uint64_t u64;
-        struct cvmx_mio_ptp_pps_hi_incr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t nanosec:32;
-                uint64_t frnanosec:32;
-#else
-                uint64_t frnanosec:32;
-                uint64_t nanosec:32;
-#endif
-        } s;
-        struct cvmx_mio_ptp_pps_hi_incr_s cn61xx;
-        struct cvmx_mio_ptp_pps_hi_incr_s cn66xx;
-        struct cvmx_mio_ptp_pps_hi_incr_s cn68xx;
-        struct cvmx_mio_ptp_pps_hi_incr_s cnf71xx;
-};
-
-union cvmx_mio_ptp_pps_lo_incr {
-        uint64_t u64;
-        struct cvmx_mio_ptp_pps_lo_incr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t nanosec:32;
-                uint64_t frnanosec:32;
-#else
-                uint64_t frnanosec:32;
-                uint64_t nanosec:32;
-#endif
-        } s;
-        struct cvmx_mio_ptp_pps_lo_incr_s cn61xx;
-        struct cvmx_mio_ptp_pps_lo_incr_s cn66xx;
-        struct cvmx_mio_ptp_pps_lo_incr_s cn68xx;
-        struct cvmx_mio_ptp_pps_lo_incr_s cnf71xx;
-};
-
-union cvmx_mio_ptp_pps_thresh_hi {
-        uint64_t u64;
-        struct cvmx_mio_ptp_pps_thresh_hi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t nanosec:64;
-#else
-                uint64_t nanosec:64;
-#endif
-        } s;
-        struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx;
-        struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx;
-        struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx;
-        struct cvmx_mio_ptp_pps_thresh_hi_s cnf71xx;
-};
-
-union cvmx_mio_ptp_pps_thresh_lo {
-        uint64_t u64;
-        struct cvmx_mio_ptp_pps_thresh_lo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t frnanosec:32;
-#else
-                uint64_t frnanosec:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx;
-        struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx;
-        struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx;
-        struct cvmx_mio_ptp_pps_thresh_lo_s cnf71xx;
 };
 
 union cvmx_mio_ptp_timestamp {
         uint64_t u64;
         struct cvmx_mio_ptp_timestamp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t nanosec:64;
-#else
                 uint64_t nanosec:64;
-#endif
         } s;
-        struct cvmx_mio_ptp_timestamp_s cn61xx;
         struct cvmx_mio_ptp_timestamp_s cn63xx;
         struct cvmx_mio_ptp_timestamp_s cn63xxp1;
-        struct cvmx_mio_ptp_timestamp_s cn66xx;
-        struct cvmx_mio_ptp_timestamp_s cn68xx;
-        struct cvmx_mio_ptp_timestamp_s cn68xxp1;
-        struct cvmx_mio_ptp_timestamp_s cnf71xx;
-};
-
-union cvmx_mio_qlmx_cfg {
-        uint64_t u64;
-        struct cvmx_mio_qlmx_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t prtmode:1;
-                uint64_t reserved_12_13:2;
-                uint64_t qlm_spd:4;
-                uint64_t reserved_4_7:4;
-                uint64_t qlm_cfg:4;
-#else
-                uint64_t qlm_cfg:4;
-                uint64_t reserved_4_7:4;
-                uint64_t qlm_spd:4;
-                uint64_t reserved_12_13:2;
-                uint64_t prtmode:1;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_mio_qlmx_cfg_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t prtmode:1;
-                uint64_t reserved_12_13:2;
-                uint64_t qlm_spd:4;
-                uint64_t reserved_2_7:6;
-                uint64_t qlm_cfg:2;
-#else
-                uint64_t qlm_cfg:2;
-                uint64_t reserved_2_7:6;
-                uint64_t qlm_spd:4;
-                uint64_t reserved_12_13:2;
-                uint64_t prtmode:1;
-                uint64_t reserved_15_63:49;
-#endif
-        } cn61xx;
-        struct cvmx_mio_qlmx_cfg_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t qlm_spd:4;
-                uint64_t reserved_4_7:4;
-                uint64_t qlm_cfg:4;
-#else
-                uint64_t qlm_cfg:4;
-                uint64_t reserved_4_7:4;
-                uint64_t qlm_spd:4;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn66xx;
-        struct cvmx_mio_qlmx_cfg_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t qlm_spd:4;
-                uint64_t reserved_3_7:5;
-                uint64_t qlm_cfg:3;
-#else
-                uint64_t qlm_cfg:3;
-                uint64_t reserved_3_7:5;
-                uint64_t qlm_spd:4;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn68xx;
-        struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;
-        struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx;
 };
 
 union cvmx_mio_rst_boot {
         uint64_t u64;
         struct cvmx_mio_rst_boot_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t chipkill:1;
-                uint64_t jtcsrdis:1;
-                uint64_t ejtagdis:1;
-                uint64_t romen:1;
-                uint64_t ckill_ppdis:1;
-                uint64_t jt_tstmode:1;
-                uint64_t reserved_50_57:8;
-                uint64_t lboot_ext:2;
-                uint64_t reserved_44_47:4;
-                uint64_t qlm4_spd:4;
-                uint64_t qlm3_spd:4;
-                uint64_t c_mul:6;
-                uint64_t pnr_mul:6;
-                uint64_t qlm2_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm0_spd:4;
-                uint64_t lboot:10;
-                uint64_t rboot:1;
-                uint64_t rboot_pin:1;
-#else
-                uint64_t rboot_pin:1;
-                uint64_t rboot:1;
-                uint64_t lboot:10;
-                uint64_t qlm0_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm2_spd:4;
-                uint64_t pnr_mul:6;
-                uint64_t c_mul:6;
-                uint64_t qlm3_spd:4;
-                uint64_t qlm4_spd:4;
-                uint64_t reserved_44_47:4;
-                uint64_t lboot_ext:2;
-                uint64_t reserved_50_57:8;
-                uint64_t jt_tstmode:1;
-                uint64_t ckill_ppdis:1;
-                uint64_t romen:1;
-                uint64_t ejtagdis:1;
-                uint64_t jtcsrdis:1;
-                uint64_t chipkill:1;
-#endif
-        } s;
-        struct cvmx_mio_rst_boot_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t chipkill:1;
-                uint64_t jtcsrdis:1;
-                uint64_t ejtagdis:1;
-                uint64_t romen:1;
-                uint64_t ckill_ppdis:1;
-                uint64_t jt_tstmode:1;
-                uint64_t reserved_50_57:8;
-                uint64_t lboot_ext:2;
-                uint64_t reserved_36_47:12;
-                uint64_t c_mul:6;
-                uint64_t pnr_mul:6;
-                uint64_t qlm2_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm0_spd:4;
-                uint64_t lboot:10;
-                uint64_t rboot:1;
-                uint64_t rboot_pin:1;
-#else
-                uint64_t rboot_pin:1;
-                uint64_t rboot:1;
-                uint64_t lboot:10;
-                uint64_t qlm0_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm2_spd:4;
-                uint64_t pnr_mul:6;
-                uint64_t c_mul:6;
-                uint64_t reserved_36_47:12;
-                uint64_t lboot_ext:2;
-                uint64_t reserved_50_57:8;
-                uint64_t jt_tstmode:1;
-                uint64_t ckill_ppdis:1;
-                uint64_t romen:1;
-                uint64_t ejtagdis:1;
-                uint64_t jtcsrdis:1;
-                uint64_t chipkill:1;
-#endif
-        } cn61xx;
-        struct cvmx_mio_rst_boot_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_36_63:28;
-                uint64_t c_mul:6;
-                uint64_t pnr_mul:6;
-                uint64_t qlm2_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm0_spd:4;
-                uint64_t lboot:10;
-                uint64_t rboot:1;
-                uint64_t rboot_pin:1;
-#else
-                uint64_t rboot_pin:1;
-                uint64_t rboot:1;
-                uint64_t lboot:10;
-                uint64_t qlm0_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm2_spd:4;
-                uint64_t pnr_mul:6;
-                uint64_t c_mul:6;
                 uint64_t reserved_36_63:28;
-#endif
-        } cn63xx;
-        struct cvmx_mio_rst_boot_cn63xx cn63xxp1;
-        struct cvmx_mio_rst_boot_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t chipkill:1;
-                uint64_t jtcsrdis:1;
-                uint64_t ejtagdis:1;
-                uint64_t romen:1;
-                uint64_t ckill_ppdis:1;
-                uint64_t reserved_50_58:9;
-                uint64_t lboot_ext:2;
-                uint64_t reserved_36_47:12;
-                uint64_t c_mul:6;
-                uint64_t pnr_mul:6;
-                uint64_t qlm2_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm0_spd:4;
-                uint64_t lboot:10;
-                uint64_t rboot:1;
-                uint64_t rboot_pin:1;
-#else
-                uint64_t rboot_pin:1;
-                uint64_t rboot:1;
-                uint64_t lboot:10;
-                uint64_t qlm0_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm2_spd:4;
-                uint64_t pnr_mul:6;
-                uint64_t c_mul:6;
-                uint64_t reserved_36_47:12;
-                uint64_t lboot_ext:2;
-                uint64_t reserved_50_58:9;
-                uint64_t ckill_ppdis:1;
-                uint64_t romen:1;
-                uint64_t ejtagdis:1;
-                uint64_t jtcsrdis:1;
-                uint64_t chipkill:1;
-#endif
-        } cn66xx;
-        struct cvmx_mio_rst_boot_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_59_63:5;
-                uint64_t jt_tstmode:1;
-                uint64_t reserved_44_57:14;
-                uint64_t qlm4_spd:4;
-                uint64_t qlm3_spd:4;
-                uint64_t c_mul:6;
-                uint64_t pnr_mul:6;
-                uint64_t qlm2_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm0_spd:4;
-                uint64_t lboot:10;
-                uint64_t rboot:1;
-                uint64_t rboot_pin:1;
-#else
-                uint64_t rboot_pin:1;
-                uint64_t rboot:1;
-                uint64_t lboot:10;
-                uint64_t qlm0_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm2_spd:4;
-                uint64_t pnr_mul:6;
-                uint64_t c_mul:6;
-                uint64_t qlm3_spd:4;
-                uint64_t qlm4_spd:4;
-                uint64_t reserved_44_57:14;
-                uint64_t jt_tstmode:1;
-                uint64_t reserved_59_63:5;
-#endif
-        } cn68xx;
-        struct cvmx_mio_rst_boot_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t qlm4_spd:4;
-                uint64_t qlm3_spd:4;
                 uint64_t c_mul:6;
                 uint64_t pnr_mul:6;
                 uint64_t qlm2_spd:4;
@@ -3326,202 +1297,32 @@ union cvmx_mio_rst_boot {
                 uint64_t lboot:10;
                 uint64_t rboot:1;
                 uint64_t rboot_pin:1;
-#else
-                uint64_t rboot_pin:1;
-                uint64_t rboot:1;
-                uint64_t lboot:10;
-                uint64_t qlm0_spd:4;
-                uint64_t qlm1_spd:4;
-                uint64_t qlm2_spd:4;
-                uint64_t pnr_mul:6;
-                uint64_t c_mul:6;
-                uint64_t qlm3_spd:4;
-                uint64_t qlm4_spd:4;
-                uint64_t reserved_44_63:20;
-#endif
-        } cn68xxp1;
-        struct cvmx_mio_rst_boot_cn61xx cnf71xx;
+        } s;
+        struct cvmx_mio_rst_boot_s cn63xx;
+        struct cvmx_mio_rst_boot_s cn63xxp1;
 };
 
 union cvmx_mio_rst_cfg {
         uint64_t u64;
         struct cvmx_mio_rst_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t cntl_clr_bist:1;
-                uint64_t warm_clr_bist:1;
-                uint64_t soft_clr_bist:1;
-#else
-                uint64_t soft_clr_bist:1;
-                uint64_t warm_clr_bist:1;
-                uint64_t cntl_clr_bist:1;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_mio_rst_cfg_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bist_delay:58;
                 uint64_t reserved_3_5:3;
                 uint64_t cntl_clr_bist:1;
                 uint64_t warm_clr_bist:1;
                 uint64_t soft_clr_bist:1;
-#else
-                uint64_t soft_clr_bist:1;
-                uint64_t warm_clr_bist:1;
-                uint64_t cntl_clr_bist:1;
-                uint64_t reserved_3_5:3;
-                uint64_t bist_delay:58;
-#endif
-        } cn61xx;
-        struct cvmx_mio_rst_cfg_cn61xx cn63xx;
+        } s;
+        struct cvmx_mio_rst_cfg_s cn63xx;
         struct cvmx_mio_rst_cfg_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t bist_delay:58;
                 uint64_t reserved_2_5:4;
                 uint64_t warm_clr_bist:1;
                 uint64_t soft_clr_bist:1;
-#else
-                uint64_t soft_clr_bist:1;
-                uint64_t warm_clr_bist:1;
-                uint64_t reserved_2_5:4;
-                uint64_t bist_delay:58;
-#endif
         } cn63xxp1;
-        struct cvmx_mio_rst_cfg_cn61xx cn66xx;
-        struct cvmx_mio_rst_cfg_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bist_delay:56;
-                uint64_t reserved_3_7:5;
-                uint64_t cntl_clr_bist:1;
-                uint64_t warm_clr_bist:1;
-                uint64_t soft_clr_bist:1;
-#else
-                uint64_t soft_clr_bist:1;
-                uint64_t warm_clr_bist:1;
-                uint64_t cntl_clr_bist:1;
-                uint64_t reserved_3_7:5;
-                uint64_t bist_delay:56;
-#endif
-        } cn68xx;
-        struct cvmx_mio_rst_cfg_cn68xx cn68xxp1;
-        struct cvmx_mio_rst_cfg_cn61xx cnf71xx;
-};
-
-union cvmx_mio_rst_ckill {
-        uint64_t u64;
-        struct cvmx_mio_rst_ckill_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_47_63:17;
-                uint64_t timer:47;
-#else
-                uint64_t timer:47;
-                uint64_t reserved_47_63:17;
-#endif
-        } s;
-        struct cvmx_mio_rst_ckill_s cn61xx;
-        struct cvmx_mio_rst_ckill_s cn66xx;
-        struct cvmx_mio_rst_ckill_s cnf71xx;
-};
-
-union cvmx_mio_rst_cntlx {
-        uint64_t u64;
-        struct cvmx_mio_rst_cntlx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t in_rev_ln:1;
-                uint64_t rev_lanes:1;
-                uint64_t gen1_only:1;
-                uint64_t prst_link:1;
-                uint64_t rst_done:1;
-                uint64_t rst_link:1;
-                uint64_t host_mode:1;
-                uint64_t prtmode:2;
-                uint64_t rst_drv:1;
-                uint64_t rst_rcv:1;
-                uint64_t rst_chip:1;
-                uint64_t rst_val:1;
-#else
-                uint64_t rst_val:1;
-                uint64_t rst_chip:1;
-                uint64_t rst_rcv:1;
-                uint64_t rst_drv:1;
-                uint64_t prtmode:2;
-                uint64_t host_mode:1;
-                uint64_t rst_link:1;
-                uint64_t rst_done:1;
-                uint64_t prst_link:1;
-                uint64_t gen1_only:1;
-                uint64_t rev_lanes:1;
-                uint64_t in_rev_ln:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_mio_rst_cntlx_s cn61xx;
-        struct cvmx_mio_rst_cntlx_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t prst_link:1;
-                uint64_t rst_done:1;
-                uint64_t rst_link:1;
-                uint64_t host_mode:1;
-                uint64_t prtmode:2;
-                uint64_t rst_drv:1;
-                uint64_t rst_rcv:1;
-                uint64_t rst_chip:1;
-                uint64_t rst_val:1;
-#else
-                uint64_t rst_val:1;
-                uint64_t rst_chip:1;
-                uint64_t rst_rcv:1;
-                uint64_t rst_drv:1;
-                uint64_t prtmode:2;
-                uint64_t host_mode:1;
-                uint64_t rst_link:1;
-                uint64_t rst_done:1;
-                uint64_t prst_link:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn66xx;
-        struct cvmx_mio_rst_cntlx_cn66xx cn68xx;
-        struct cvmx_mio_rst_cntlx_s cnf71xx;
 };
 
 union cvmx_mio_rst_ctlx {
         uint64_t u64;
         struct cvmx_mio_rst_ctlx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t in_rev_ln:1;
-                uint64_t rev_lanes:1;
-                uint64_t gen1_only:1;
-                uint64_t prst_link:1;
-                uint64_t rst_done:1;
-                uint64_t rst_link:1;
-                uint64_t host_mode:1;
-                uint64_t prtmode:2;
-                uint64_t rst_drv:1;
-                uint64_t rst_rcv:1;
-                uint64_t rst_chip:1;
-                uint64_t rst_val:1;
-#else
-                uint64_t rst_val:1;
-                uint64_t rst_chip:1;
-                uint64_t rst_rcv:1;
-                uint64_t rst_drv:1;
-                uint64_t prtmode:2;
-                uint64_t host_mode:1;
-                uint64_t rst_link:1;
-                uint64_t rst_done:1;
-                uint64_t prst_link:1;
-                uint64_t gen1_only:1;
-                uint64_t rev_lanes:1;
-                uint64_t in_rev_ln:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_mio_rst_ctlx_s cn61xx;
-        struct cvmx_mio_rst_ctlx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t prst_link:1;
                 uint64_t rst_done:1;
@@ -3532,21 +1333,9 @@ union cvmx_mio_rst_ctlx {
                 uint64_t rst_rcv:1;
                 uint64_t rst_chip:1;
                 uint64_t rst_val:1;
-#else
-                uint64_t rst_val:1;
-                uint64_t rst_chip:1;
-                uint64_t rst_rcv:1;
-                uint64_t rst_drv:1;
-                uint64_t prtmode:2;
-                uint64_t host_mode:1;
-                uint64_t rst_link:1;
-                uint64_t rst_done:1;
-                uint64_t prst_link:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn63xx;
+        } s;
+        struct cvmx_mio_rst_ctlx_s cn63xx;
         struct cvmx_mio_rst_ctlx_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t rst_done:1;
                 uint64_t rst_link:1;
@@ -3556,146 +1345,51 @@ union cvmx_mio_rst_ctlx {
                 uint64_t rst_rcv:1;
                 uint64_t rst_chip:1;
                 uint64_t rst_val:1;
-#else
-                uint64_t rst_val:1;
-                uint64_t rst_chip:1;
-                uint64_t rst_rcv:1;
-                uint64_t rst_drv:1;
-                uint64_t prtmode:2;
-                uint64_t host_mode:1;
-                uint64_t rst_link:1;
-                uint64_t rst_done:1;
-                uint64_t reserved_9_63:55;
-#endif
         } cn63xxp1;
-        struct cvmx_mio_rst_ctlx_cn63xx cn66xx;
-        struct cvmx_mio_rst_ctlx_cn63xx cn68xx;
-        struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;
-        struct cvmx_mio_rst_ctlx_s cnf71xx;
 };
 
 union cvmx_mio_rst_delay {
         uint64_t u64;
         struct cvmx_mio_rst_delay_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
-                uint64_t warm_rst_dly:16;
-                uint64_t soft_rst_dly:16;
-#else
                 uint64_t soft_rst_dly:16;
                 uint64_t warm_rst_dly:16;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
-        struct cvmx_mio_rst_delay_s cn61xx;
         struct cvmx_mio_rst_delay_s cn63xx;
         struct cvmx_mio_rst_delay_s cn63xxp1;
-        struct cvmx_mio_rst_delay_s cn66xx;
-        struct cvmx_mio_rst_delay_s cn68xx;
-        struct cvmx_mio_rst_delay_s cn68xxp1;
-        struct cvmx_mio_rst_delay_s cnf71xx;
 };
 
 union cvmx_mio_rst_int {
         uint64_t u64;
         struct cvmx_mio_rst_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t perst1:1;
-                uint64_t perst0:1;
-                uint64_t reserved_4_7:4;
-                uint64_t rst_link3:1;
-                uint64_t rst_link2:1;
-                uint64_t rst_link1:1;
-                uint64_t rst_link0:1;
-#else
-                uint64_t rst_link0:1;
-                uint64_t rst_link1:1;
-                uint64_t rst_link2:1;
-                uint64_t rst_link3:1;
-                uint64_t reserved_4_7:4;
-                uint64_t perst0:1;
-                uint64_t perst1:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } s;
-        struct cvmx_mio_rst_int_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t perst1:1;
                 uint64_t perst0:1;
                 uint64_t reserved_2_7:6;
                 uint64_t rst_link1:1;
                 uint64_t rst_link0:1;
-#else
-                uint64_t rst_link0:1;
-                uint64_t rst_link1:1;
-                uint64_t reserved_2_7:6;
-                uint64_t perst0:1;
-                uint64_t perst1:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_mio_rst_int_cn61xx cn63xx;
-        struct cvmx_mio_rst_int_cn61xx cn63xxp1;
-        struct cvmx_mio_rst_int_s cn66xx;
-        struct cvmx_mio_rst_int_cn61xx cn68xx;
-        struct cvmx_mio_rst_int_cn61xx cn68xxp1;
-        struct cvmx_mio_rst_int_cn61xx cnf71xx;
+        } s;
+        struct cvmx_mio_rst_int_s cn63xx;
+        struct cvmx_mio_rst_int_s cn63xxp1;
 };
 
 union cvmx_mio_rst_int_en {
         uint64_t u64;
         struct cvmx_mio_rst_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t perst1:1;
-                uint64_t perst0:1;
-                uint64_t reserved_4_7:4;
-                uint64_t rst_link3:1;
-                uint64_t rst_link2:1;
-                uint64_t rst_link1:1;
-                uint64_t rst_link0:1;
-#else
-                uint64_t rst_link0:1;
-                uint64_t rst_link1:1;
-                uint64_t rst_link2:1;
-                uint64_t rst_link3:1;
-                uint64_t reserved_4_7:4;
-                uint64_t perst0:1;
-                uint64_t perst1:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } s;
-        struct cvmx_mio_rst_int_en_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t perst1:1;
                 uint64_t perst0:1;
                 uint64_t reserved_2_7:6;
                 uint64_t rst_link1:1;
                 uint64_t rst_link0:1;
-#else
-                uint64_t rst_link0:1;
-                uint64_t rst_link1:1;
-                uint64_t reserved_2_7:6;
-                uint64_t perst0:1;
-                uint64_t perst1:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn61xx;
-        struct cvmx_mio_rst_int_en_cn61xx cn63xx;
-        struct cvmx_mio_rst_int_en_cn61xx cn63xxp1;
-        struct cvmx_mio_rst_int_en_s cn66xx;
-        struct cvmx_mio_rst_int_en_cn61xx cn68xx;
-        struct cvmx_mio_rst_int_en_cn61xx cn68xxp1;
-        struct cvmx_mio_rst_int_en_cn61xx cnf71xx;
+        } s;
+        struct cvmx_mio_rst_int_en_s cn63xx;
+        struct cvmx_mio_rst_int_en_s cn63xxp1;
 };
 
 union cvmx_mio_twsx_int {
         uint64_t u64;
         struct cvmx_mio_twsx_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t scl:1;
                 uint64_t sda:1;
@@ -3709,27 +1403,11 @@ union cvmx_mio_twsx_int {
                 uint64_t core_int:1;
                 uint64_t ts_int:1;
                 uint64_t st_int:1;
-#else
-                uint64_t st_int:1;
-                uint64_t ts_int:1;
-                uint64_t core_int:1;
-                uint64_t reserved_3_3:1;
-                uint64_t st_en:1;
-                uint64_t ts_en:1;
-                uint64_t core_en:1;
-                uint64_t reserved_7_7:1;
-                uint64_t sda_ovr:1;
-                uint64_t scl_ovr:1;
-                uint64_t sda:1;
-                uint64_t scl:1;
-                uint64_t reserved_12_63:52;
-#endif
         } s;
         struct cvmx_mio_twsx_int_s cn30xx;
         struct cvmx_mio_twsx_int_s cn31xx;
         struct cvmx_mio_twsx_int_s cn38xx;
         struct cvmx_mio_twsx_int_cn38xxp2 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t core_en:1;
                 uint64_t ts_en:1;
@@ -3738,16 +1416,6 @@ union cvmx_mio_twsx_int {
                 uint64_t core_int:1;
                 uint64_t ts_int:1;
                 uint64_t st_int:1;
-#else
-                uint64_t st_int:1;
-                uint64_t ts_int:1;
-                uint64_t core_int:1;
-                uint64_t reserved_3_3:1;
-                uint64_t st_en:1;
-                uint64_t ts_en:1;
-                uint64_t core_en:1;
-                uint64_t reserved_7_63:57;
-#endif
         } cn38xxp2;
         struct cvmx_mio_twsx_int_s cn50xx;
         struct cvmx_mio_twsx_int_s cn52xx;
@@ -3756,19 +1424,13 @@ union cvmx_mio_twsx_int {
         struct cvmx_mio_twsx_int_s cn56xxp1;
         struct cvmx_mio_twsx_int_s cn58xx;
         struct cvmx_mio_twsx_int_s cn58xxp1;
-        struct cvmx_mio_twsx_int_s cn61xx;
         struct cvmx_mio_twsx_int_s cn63xx;
         struct cvmx_mio_twsx_int_s cn63xxp1;
-        struct cvmx_mio_twsx_int_s cn66xx;
-        struct cvmx_mio_twsx_int_s cn68xx;
-        struct cvmx_mio_twsx_int_s cn68xxp1;
-        struct cvmx_mio_twsx_int_s cnf71xx;
 };
 
 union cvmx_mio_twsx_sw_twsi {
         uint64_t u64;
         struct cvmx_mio_twsx_sw_twsi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t v:1;
                 uint64_t slonly:1;
                 uint64_t eia:1;
@@ -3781,20 +1443,6 @@ union cvmx_mio_twsx_sw_twsi {
                 uint64_t ia:5;
                 uint64_t eop_ia:3;
                 uint64_t d:32;
-#else
-                uint64_t d:32;
-                uint64_t eop_ia:3;
-                uint64_t ia:5;
-                uint64_t a:10;
-                uint64_t scr:2;
-                uint64_t size:3;
-                uint64_t sovr:1;
-                uint64_t r:1;
-                uint64_t op:4;
-                uint64_t eia:1;
-                uint64_t slonly:1;
-                uint64_t v:1;
-#endif
         } s;
         struct cvmx_mio_twsx_sw_twsi_s cn30xx;
         struct cvmx_mio_twsx_sw_twsi_s cn31xx;
@@ -3807,27 +1455,16 @@ union cvmx_mio_twsx_sw_twsi {
         struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
-        struct cvmx_mio_twsx_sw_twsi_s cn61xx;
         struct cvmx_mio_twsx_sw_twsi_s cn63xx;
         struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
-        struct cvmx_mio_twsx_sw_twsi_s cn66xx;
-        struct cvmx_mio_twsx_sw_twsi_s cn68xx;
-        struct cvmx_mio_twsx_sw_twsi_s cn68xxp1;
-        struct cvmx_mio_twsx_sw_twsi_s cnf71xx;
 };
 
 union cvmx_mio_twsx_sw_twsi_ext {
         uint64_t u64;
         struct cvmx_mio_twsx_sw_twsi_ext_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t ia:8;
                 uint64_t d:32;
-#else
-                uint64_t d:32;
-                uint64_t ia:8;
-                uint64_t reserved_40_63:24;
-#endif
         } s;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx;
@@ -3840,27 +1477,16 @@ union cvmx_mio_twsx_sw_twsi_ext {
         struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
-        struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
-        struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx;
-        struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx;
-        struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1;
-        struct cvmx_mio_twsx_sw_twsi_ext_s cnf71xx;
 };
 
 union cvmx_mio_twsx_twsi_sw {
         uint64_t u64;
         struct cvmx_mio_twsx_twsi_sw_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t v:2;
                 uint64_t reserved_32_61:30;
                 uint64_t d:32;
-#else
-                uint64_t d:32;
-                uint64_t reserved_32_61:30;
-                uint64_t v:2;
-#endif
         } s;
         struct cvmx_mio_twsx_twsi_sw_s cn30xx;
         struct cvmx_mio_twsx_twsi_sw_s cn31xx;
@@ -3873,25 +1499,15 @@ union cvmx_mio_twsx_twsi_sw {
         struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
         struct cvmx_mio_twsx_twsi_sw_s cn58xx;
         struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
-        struct cvmx_mio_twsx_twsi_sw_s cn61xx;
         struct cvmx_mio_twsx_twsi_sw_s cn63xx;
         struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
-        struct cvmx_mio_twsx_twsi_sw_s cn66xx;
-        struct cvmx_mio_twsx_twsi_sw_s cn68xx;
-        struct cvmx_mio_twsx_twsi_sw_s cn68xxp1;
-        struct cvmx_mio_twsx_twsi_sw_s cnf71xx;
 };
 
 union cvmx_mio_uartx_dlh {
         uint64_t u64;
         struct cvmx_mio_uartx_dlh_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t dlh:8;
-#else
-                uint64_t dlh:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_dlh_s cn30xx;
         struct cvmx_mio_uartx_dlh_s cn31xx;
@@ -3904,25 +1520,15 @@ union cvmx_mio_uartx_dlh {
         struct cvmx_mio_uartx_dlh_s cn56xxp1;
         struct cvmx_mio_uartx_dlh_s cn58xx;
         struct cvmx_mio_uartx_dlh_s cn58xxp1;
-        struct cvmx_mio_uartx_dlh_s cn61xx;
         struct cvmx_mio_uartx_dlh_s cn63xx;
         struct cvmx_mio_uartx_dlh_s cn63xxp1;
-        struct cvmx_mio_uartx_dlh_s cn66xx;
-        struct cvmx_mio_uartx_dlh_s cn68xx;
-        struct cvmx_mio_uartx_dlh_s cn68xxp1;
-        struct cvmx_mio_uartx_dlh_s cnf71xx;
 };
 
 union cvmx_mio_uartx_dll {
         uint64_t u64;
         struct cvmx_mio_uartx_dll_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t dll:8;
-#else
-                uint64_t dll:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_dll_s cn30xx;
         struct cvmx_mio_uartx_dll_s cn31xx;
@@ -3935,25 +1541,15 @@ union cvmx_mio_uartx_dll {
         struct cvmx_mio_uartx_dll_s cn56xxp1;
         struct cvmx_mio_uartx_dll_s cn58xx;
         struct cvmx_mio_uartx_dll_s cn58xxp1;
-        struct cvmx_mio_uartx_dll_s cn61xx;
         struct cvmx_mio_uartx_dll_s cn63xx;
         struct cvmx_mio_uartx_dll_s cn63xxp1;
-        struct cvmx_mio_uartx_dll_s cn66xx;
-        struct cvmx_mio_uartx_dll_s cn68xx;
-        struct cvmx_mio_uartx_dll_s cn68xxp1;
-        struct cvmx_mio_uartx_dll_s cnf71xx;
 };
 
 union cvmx_mio_uartx_far {
         uint64_t u64;
         struct cvmx_mio_uartx_far_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t far:1;
-#else
-                uint64_t far:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uartx_far_s cn30xx;
         struct cvmx_mio_uartx_far_s cn31xx;
@@ -3966,19 +1562,13 @@ union cvmx_mio_uartx_far {
         struct cvmx_mio_uartx_far_s cn56xxp1;
         struct cvmx_mio_uartx_far_s cn58xx;
         struct cvmx_mio_uartx_far_s cn58xxp1;
-        struct cvmx_mio_uartx_far_s cn61xx;
         struct cvmx_mio_uartx_far_s cn63xx;
         struct cvmx_mio_uartx_far_s cn63xxp1;
-        struct cvmx_mio_uartx_far_s cn66xx;
-        struct cvmx_mio_uartx_far_s cn68xx;
-        struct cvmx_mio_uartx_far_s cn68xxp1;
-        struct cvmx_mio_uartx_far_s cnf71xx;
 };
 
 union cvmx_mio_uartx_fcr {
         uint64_t u64;
         struct cvmx_mio_uartx_fcr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t rxtrig:2;
                 uint64_t txtrig:2;
@@ -3986,15 +1576,6 @@ union cvmx_mio_uartx_fcr {
                 uint64_t txfr:1;
                 uint64_t rxfr:1;
                 uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t rxfr:1;
-                uint64_t txfr:1;
-                uint64_t reserved_3_3:1;
-                uint64_t txtrig:2;
-                uint64_t rxtrig:2;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_fcr_s cn30xx;
         struct cvmx_mio_uartx_fcr_s cn31xx;
@@ -4007,25 +1588,15 @@ union cvmx_mio_uartx_fcr {
         struct cvmx_mio_uartx_fcr_s cn56xxp1;
         struct cvmx_mio_uartx_fcr_s cn58xx;
         struct cvmx_mio_uartx_fcr_s cn58xxp1;
-        struct cvmx_mio_uartx_fcr_s cn61xx;
         struct cvmx_mio_uartx_fcr_s cn63xx;
         struct cvmx_mio_uartx_fcr_s cn63xxp1;
-        struct cvmx_mio_uartx_fcr_s cn66xx;
-        struct cvmx_mio_uartx_fcr_s cn68xx;
-        struct cvmx_mio_uartx_fcr_s cn68xxp1;
-        struct cvmx_mio_uartx_fcr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_htx {
         uint64_t u64;
         struct cvmx_mio_uartx_htx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t htx:1;
-#else
-                uint64_t htx:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uartx_htx_s cn30xx;
         struct cvmx_mio_uartx_htx_s cn31xx;
@@ -4038,19 +1609,13 @@ union cvmx_mio_uartx_htx {
         struct cvmx_mio_uartx_htx_s cn56xxp1;
         struct cvmx_mio_uartx_htx_s cn58xx;
         struct cvmx_mio_uartx_htx_s cn58xxp1;
-        struct cvmx_mio_uartx_htx_s cn61xx;
         struct cvmx_mio_uartx_htx_s cn63xx;
         struct cvmx_mio_uartx_htx_s cn63xxp1;
-        struct cvmx_mio_uartx_htx_s cn66xx;
-        struct cvmx_mio_uartx_htx_s cn68xx;
-        struct cvmx_mio_uartx_htx_s cn68xxp1;
-        struct cvmx_mio_uartx_htx_s cnf71xx;
 };
 
 union cvmx_mio_uartx_ier {
         uint64_t u64;
         struct cvmx_mio_uartx_ier_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t ptime:1;
                 uint64_t reserved_4_6:3;
@@ -4058,15 +1623,6 @@ union cvmx_mio_uartx_ier {
                 uint64_t elsi:1;
                 uint64_t etbei:1;
                 uint64_t erbfi:1;
-#else
-                uint64_t erbfi:1;
-                uint64_t etbei:1;
-                uint64_t elsi:1;
-                uint64_t edssi:1;
-                uint64_t reserved_4_6:3;
-                uint64_t ptime:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_ier_s cn30xx;
         struct cvmx_mio_uartx_ier_s cn31xx;
@@ -4079,29 +1635,17 @@ union cvmx_mio_uartx_ier {
         struct cvmx_mio_uartx_ier_s cn56xxp1;
         struct cvmx_mio_uartx_ier_s cn58xx;
         struct cvmx_mio_uartx_ier_s cn58xxp1;
-        struct cvmx_mio_uartx_ier_s cn61xx;
         struct cvmx_mio_uartx_ier_s cn63xx;
         struct cvmx_mio_uartx_ier_s cn63xxp1;
-        struct cvmx_mio_uartx_ier_s cn66xx;
-        struct cvmx_mio_uartx_ier_s cn68xx;
-        struct cvmx_mio_uartx_ier_s cn68xxp1;
-        struct cvmx_mio_uartx_ier_s cnf71xx;
 };
 
 union cvmx_mio_uartx_iir {
         uint64_t u64;
         struct cvmx_mio_uartx_iir_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t fen:2;
                 uint64_t reserved_4_5:2;
                 uint64_t iid:4;
-#else
-                uint64_t iid:4;
-                uint64_t reserved_4_5:2;
-                uint64_t fen:2;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_iir_s cn30xx;
         struct cvmx_mio_uartx_iir_s cn31xx;
@@ -4114,19 +1658,13 @@ union cvmx_mio_uartx_iir {
         struct cvmx_mio_uartx_iir_s cn56xxp1;
         struct cvmx_mio_uartx_iir_s cn58xx;
         struct cvmx_mio_uartx_iir_s cn58xxp1;
-        struct cvmx_mio_uartx_iir_s cn61xx;
         struct cvmx_mio_uartx_iir_s cn63xx;
         struct cvmx_mio_uartx_iir_s cn63xxp1;
-        struct cvmx_mio_uartx_iir_s cn66xx;
-        struct cvmx_mio_uartx_iir_s cn68xx;
-        struct cvmx_mio_uartx_iir_s cn68xxp1;
-        struct cvmx_mio_uartx_iir_s cnf71xx;
 };
 
 union cvmx_mio_uartx_lcr {
         uint64_t u64;
         struct cvmx_mio_uartx_lcr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t dlab:1;
                 uint64_t brk:1;
@@ -4135,16 +1673,6 @@ union cvmx_mio_uartx_lcr {
                 uint64_t pen:1;
                 uint64_t stop:1;
                 uint64_t cls:2;
-#else
-                uint64_t cls:2;
-                uint64_t stop:1;
-                uint64_t pen:1;
-                uint64_t eps:1;
-                uint64_t reserved_5_5:1;
-                uint64_t brk:1;
-                uint64_t dlab:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_lcr_s cn30xx;
         struct cvmx_mio_uartx_lcr_s cn31xx;
@@ -4157,19 +1685,13 @@ union cvmx_mio_uartx_lcr {
         struct cvmx_mio_uartx_lcr_s cn56xxp1;
         struct cvmx_mio_uartx_lcr_s cn58xx;
         struct cvmx_mio_uartx_lcr_s cn58xxp1;
-        struct cvmx_mio_uartx_lcr_s cn61xx;
         struct cvmx_mio_uartx_lcr_s cn63xx;
         struct cvmx_mio_uartx_lcr_s cn63xxp1;
-        struct cvmx_mio_uartx_lcr_s cn66xx;
-        struct cvmx_mio_uartx_lcr_s cn68xx;
-        struct cvmx_mio_uartx_lcr_s cn68xxp1;
-        struct cvmx_mio_uartx_lcr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_lsr {
         uint64_t u64;
         struct cvmx_mio_uartx_lsr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t ferr:1;
                 uint64_t temt:1;
@@ -4179,17 +1701,6 @@ union cvmx_mio_uartx_lsr {
                 uint64_t pe:1;
                 uint64_t oe:1;
                 uint64_t dr:1;
-#else
-                uint64_t dr:1;
-                uint64_t oe:1;
-                uint64_t pe:1;
-                uint64_t fe:1;
-                uint64_t bi:1;
-                uint64_t thre:1;
-                uint64_t temt:1;
-                uint64_t ferr:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_lsr_s cn30xx;
         struct cvmx_mio_uartx_lsr_s cn31xx;
@@ -4202,19 +1713,13 @@ union cvmx_mio_uartx_lsr {
         struct cvmx_mio_uartx_lsr_s cn56xxp1;
         struct cvmx_mio_uartx_lsr_s cn58xx;
         struct cvmx_mio_uartx_lsr_s cn58xxp1;
-        struct cvmx_mio_uartx_lsr_s cn61xx;
         struct cvmx_mio_uartx_lsr_s cn63xx;
         struct cvmx_mio_uartx_lsr_s cn63xxp1;
-        struct cvmx_mio_uartx_lsr_s cn66xx;
-        struct cvmx_mio_uartx_lsr_s cn68xx;
-        struct cvmx_mio_uartx_lsr_s cn68xxp1;
-        struct cvmx_mio_uartx_lsr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_mcr {
         uint64_t u64;
         struct cvmx_mio_uartx_mcr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t afce:1;
                 uint64_t loop:1;
@@ -4222,15 +1727,6 @@ union cvmx_mio_uartx_mcr {
                 uint64_t out1:1;
                 uint64_t rts:1;
                 uint64_t dtr:1;
-#else
-                uint64_t dtr:1;
-                uint64_t rts:1;
-                uint64_t out1:1;
-                uint64_t out2:1;
-                uint64_t loop:1;
-                uint64_t afce:1;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_mio_uartx_mcr_s cn30xx;
         struct cvmx_mio_uartx_mcr_s cn31xx;
@@ -4243,19 +1739,13 @@ union cvmx_mio_uartx_mcr {
         struct cvmx_mio_uartx_mcr_s cn56xxp1;
         struct cvmx_mio_uartx_mcr_s cn58xx;
         struct cvmx_mio_uartx_mcr_s cn58xxp1;
-        struct cvmx_mio_uartx_mcr_s cn61xx;
         struct cvmx_mio_uartx_mcr_s cn63xx;
         struct cvmx_mio_uartx_mcr_s cn63xxp1;
-        struct cvmx_mio_uartx_mcr_s cn66xx;
-        struct cvmx_mio_uartx_mcr_s cn68xx;
-        struct cvmx_mio_uartx_mcr_s cn68xxp1;
-        struct cvmx_mio_uartx_mcr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_msr {
         uint64_t u64;
         struct cvmx_mio_uartx_msr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t dcd:1;
                 uint64_t ri:1;
@@ -4265,17 +1755,6 @@ union cvmx_mio_uartx_msr {
                 uint64_t teri:1;
                 uint64_t ddsr:1;
                 uint64_t dcts:1;
-#else
-                uint64_t dcts:1;
-                uint64_t ddsr:1;
-                uint64_t teri:1;
-                uint64_t ddcd:1;
-                uint64_t cts:1;
-                uint64_t dsr:1;
-                uint64_t ri:1;
-                uint64_t dcd:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_msr_s cn30xx;
         struct cvmx_mio_uartx_msr_s cn31xx;
@@ -4288,25 +1767,15 @@ union cvmx_mio_uartx_msr {
         struct cvmx_mio_uartx_msr_s cn56xxp1;
         struct cvmx_mio_uartx_msr_s cn58xx;
         struct cvmx_mio_uartx_msr_s cn58xxp1;
-        struct cvmx_mio_uartx_msr_s cn61xx;
         struct cvmx_mio_uartx_msr_s cn63xx;
         struct cvmx_mio_uartx_msr_s cn63xxp1;
-        struct cvmx_mio_uartx_msr_s cn66xx;
-        struct cvmx_mio_uartx_msr_s cn68xx;
-        struct cvmx_mio_uartx_msr_s cn68xxp1;
-        struct cvmx_mio_uartx_msr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_rbr {
         uint64_t u64;
         struct cvmx_mio_uartx_rbr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t rbr:8;
-#else
-                uint64_t rbr:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_rbr_s cn30xx;
         struct cvmx_mio_uartx_rbr_s cn31xx;
@@ -4319,25 +1788,15 @@ union cvmx_mio_uartx_rbr {
         struct cvmx_mio_uartx_rbr_s cn56xxp1;
         struct cvmx_mio_uartx_rbr_s cn58xx;
         struct cvmx_mio_uartx_rbr_s cn58xxp1;
-        struct cvmx_mio_uartx_rbr_s cn61xx;
         struct cvmx_mio_uartx_rbr_s cn63xx;
         struct cvmx_mio_uartx_rbr_s cn63xxp1;
-        struct cvmx_mio_uartx_rbr_s cn66xx;
-        struct cvmx_mio_uartx_rbr_s cn68xx;
-        struct cvmx_mio_uartx_rbr_s cn68xxp1;
-        struct cvmx_mio_uartx_rbr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_rfl {
         uint64_t u64;
         struct cvmx_mio_uartx_rfl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t rfl:7;
-#else
-                uint64_t rfl:7;
-                uint64_t reserved_7_63:57;
-#endif
         } s;
         struct cvmx_mio_uartx_rfl_s cn30xx;
         struct cvmx_mio_uartx_rfl_s cn31xx;
@@ -4350,29 +1809,17 @@ union cvmx_mio_uartx_rfl {
         struct cvmx_mio_uartx_rfl_s cn56xxp1;
         struct cvmx_mio_uartx_rfl_s cn58xx;
         struct cvmx_mio_uartx_rfl_s cn58xxp1;
-        struct cvmx_mio_uartx_rfl_s cn61xx;
         struct cvmx_mio_uartx_rfl_s cn63xx;
         struct cvmx_mio_uartx_rfl_s cn63xxp1;
-        struct cvmx_mio_uartx_rfl_s cn66xx;
-        struct cvmx_mio_uartx_rfl_s cn68xx;
-        struct cvmx_mio_uartx_rfl_s cn68xxp1;
-        struct cvmx_mio_uartx_rfl_s cnf71xx;
 };
 
 union cvmx_mio_uartx_rfw {
         uint64_t u64;
         struct cvmx_mio_uartx_rfw_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t rffe:1;
                 uint64_t rfpe:1;
                 uint64_t rfwd:8;
-#else
-                uint64_t rfwd:8;
-                uint64_t rfpe:1;
-                uint64_t rffe:1;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_mio_uartx_rfw_s cn30xx;
         struct cvmx_mio_uartx_rfw_s cn31xx;
@@ -4385,25 +1832,15 @@ union cvmx_mio_uartx_rfw {
         struct cvmx_mio_uartx_rfw_s cn56xxp1;
         struct cvmx_mio_uartx_rfw_s cn58xx;
         struct cvmx_mio_uartx_rfw_s cn58xxp1;
-        struct cvmx_mio_uartx_rfw_s cn61xx;
         struct cvmx_mio_uartx_rfw_s cn63xx;
         struct cvmx_mio_uartx_rfw_s cn63xxp1;
-        struct cvmx_mio_uartx_rfw_s cn66xx;
-        struct cvmx_mio_uartx_rfw_s cn68xx;
-        struct cvmx_mio_uartx_rfw_s cn68xxp1;
-        struct cvmx_mio_uartx_rfw_s cnf71xx;
 };
 
 union cvmx_mio_uartx_sbcr {
         uint64_t u64;
         struct cvmx_mio_uartx_sbcr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t sbcr:1;
-#else
-                uint64_t sbcr:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uartx_sbcr_s cn30xx;
         struct cvmx_mio_uartx_sbcr_s cn31xx;
@@ -4416,25 +1853,15 @@ union cvmx_mio_uartx_sbcr {
         struct cvmx_mio_uartx_sbcr_s cn56xxp1;
         struct cvmx_mio_uartx_sbcr_s cn58xx;
         struct cvmx_mio_uartx_sbcr_s cn58xxp1;
-        struct cvmx_mio_uartx_sbcr_s cn61xx;
         struct cvmx_mio_uartx_sbcr_s cn63xx;
         struct cvmx_mio_uartx_sbcr_s cn63xxp1;
-        struct cvmx_mio_uartx_sbcr_s cn66xx;
-        struct cvmx_mio_uartx_sbcr_s cn68xx;
-        struct cvmx_mio_uartx_sbcr_s cn68xxp1;
-        struct cvmx_mio_uartx_sbcr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_scr {
         uint64_t u64;
         struct cvmx_mio_uartx_scr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t scr:8;
-#else
-                uint64_t scr:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_scr_s cn30xx;
         struct cvmx_mio_uartx_scr_s cn31xx;
@@ -4447,25 +1874,15 @@ union cvmx_mio_uartx_scr {
         struct cvmx_mio_uartx_scr_s cn56xxp1;
         struct cvmx_mio_uartx_scr_s cn58xx;
         struct cvmx_mio_uartx_scr_s cn58xxp1;
-        struct cvmx_mio_uartx_scr_s cn61xx;
         struct cvmx_mio_uartx_scr_s cn63xx;
         struct cvmx_mio_uartx_scr_s cn63xxp1;
-        struct cvmx_mio_uartx_scr_s cn66xx;
-        struct cvmx_mio_uartx_scr_s cn68xx;
-        struct cvmx_mio_uartx_scr_s cn68xxp1;
-        struct cvmx_mio_uartx_scr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_sfe {
         uint64_t u64;
         struct cvmx_mio_uartx_sfe_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t sfe:1;
-#else
-                uint64_t sfe:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uartx_sfe_s cn30xx;
         struct cvmx_mio_uartx_sfe_s cn31xx;
@@ -4478,29 +1895,17 @@ union cvmx_mio_uartx_sfe {
         struct cvmx_mio_uartx_sfe_s cn56xxp1;
         struct cvmx_mio_uartx_sfe_s cn58xx;
         struct cvmx_mio_uartx_sfe_s cn58xxp1;
-        struct cvmx_mio_uartx_sfe_s cn61xx;
         struct cvmx_mio_uartx_sfe_s cn63xx;
         struct cvmx_mio_uartx_sfe_s cn63xxp1;
-        struct cvmx_mio_uartx_sfe_s cn66xx;
-        struct cvmx_mio_uartx_sfe_s cn68xx;
-        struct cvmx_mio_uartx_sfe_s cn68xxp1;
-        struct cvmx_mio_uartx_sfe_s cnf71xx;
 };
 
 union cvmx_mio_uartx_srr {
         uint64_t u64;
         struct cvmx_mio_uartx_srr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t stfr:1;
                 uint64_t srfr:1;
                 uint64_t usr:1;
-#else
-                uint64_t usr:1;
-                uint64_t srfr:1;
-                uint64_t stfr:1;
-                uint64_t reserved_3_63:61;
-#endif
         } s;
         struct cvmx_mio_uartx_srr_s cn30xx;
         struct cvmx_mio_uartx_srr_s cn31xx;
@@ -4513,25 +1918,15 @@ union cvmx_mio_uartx_srr {
         struct cvmx_mio_uartx_srr_s cn56xxp1;
         struct cvmx_mio_uartx_srr_s cn58xx;
         struct cvmx_mio_uartx_srr_s cn58xxp1;
-        struct cvmx_mio_uartx_srr_s cn61xx;
         struct cvmx_mio_uartx_srr_s cn63xx;
         struct cvmx_mio_uartx_srr_s cn63xxp1;
-        struct cvmx_mio_uartx_srr_s cn66xx;
-        struct cvmx_mio_uartx_srr_s cn68xx;
-        struct cvmx_mio_uartx_srr_s cn68xxp1;
-        struct cvmx_mio_uartx_srr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_srt {
         uint64_t u64;
         struct cvmx_mio_uartx_srt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t srt:2;
-#else
-                uint64_t srt:2;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_mio_uartx_srt_s cn30xx;
         struct cvmx_mio_uartx_srt_s cn31xx;
@@ -4544,25 +1939,15 @@ union cvmx_mio_uartx_srt {
         struct cvmx_mio_uartx_srt_s cn56xxp1;
         struct cvmx_mio_uartx_srt_s cn58xx;
         struct cvmx_mio_uartx_srt_s cn58xxp1;
-        struct cvmx_mio_uartx_srt_s cn61xx;
         struct cvmx_mio_uartx_srt_s cn63xx;
         struct cvmx_mio_uartx_srt_s cn63xxp1;
-        struct cvmx_mio_uartx_srt_s cn66xx;
-        struct cvmx_mio_uartx_srt_s cn68xx;
-        struct cvmx_mio_uartx_srt_s cn68xxp1;
-        struct cvmx_mio_uartx_srt_s cnf71xx;
 };
 
 union cvmx_mio_uartx_srts {
         uint64_t u64;
         struct cvmx_mio_uartx_srts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t srts:1;
-#else
-                uint64_t srts:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uartx_srts_s cn30xx;
         struct cvmx_mio_uartx_srts_s cn31xx;
@@ -4575,25 +1960,15 @@ union cvmx_mio_uartx_srts {
         struct cvmx_mio_uartx_srts_s cn56xxp1;
         struct cvmx_mio_uartx_srts_s cn58xx;
         struct cvmx_mio_uartx_srts_s cn58xxp1;
-        struct cvmx_mio_uartx_srts_s cn61xx;
         struct cvmx_mio_uartx_srts_s cn63xx;
         struct cvmx_mio_uartx_srts_s cn63xxp1;
-        struct cvmx_mio_uartx_srts_s cn66xx;
-        struct cvmx_mio_uartx_srts_s cn68xx;
-        struct cvmx_mio_uartx_srts_s cn68xxp1;
-        struct cvmx_mio_uartx_srts_s cnf71xx;
 };
 
 union cvmx_mio_uartx_stt {
         uint64_t u64;
         struct cvmx_mio_uartx_stt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t stt:2;
-#else
-                uint64_t stt:2;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_mio_uartx_stt_s cn30xx;
         struct cvmx_mio_uartx_stt_s cn31xx;
@@ -4606,25 +1981,15 @@ union cvmx_mio_uartx_stt {
         struct cvmx_mio_uartx_stt_s cn56xxp1;
         struct cvmx_mio_uartx_stt_s cn58xx;
         struct cvmx_mio_uartx_stt_s cn58xxp1;
-        struct cvmx_mio_uartx_stt_s cn61xx;
         struct cvmx_mio_uartx_stt_s cn63xx;
         struct cvmx_mio_uartx_stt_s cn63xxp1;
-        struct cvmx_mio_uartx_stt_s cn66xx;
-        struct cvmx_mio_uartx_stt_s cn68xx;
-        struct cvmx_mio_uartx_stt_s cn68xxp1;
-        struct cvmx_mio_uartx_stt_s cnf71xx;
 };
 
 union cvmx_mio_uartx_tfl {
         uint64_t u64;
         struct cvmx_mio_uartx_tfl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t tfl:7;
-#else
-                uint64_t tfl:7;
-                uint64_t reserved_7_63:57;
-#endif
         } s;
         struct cvmx_mio_uartx_tfl_s cn30xx;
         struct cvmx_mio_uartx_tfl_s cn31xx;
@@ -4637,25 +2002,15 @@ union cvmx_mio_uartx_tfl {
         struct cvmx_mio_uartx_tfl_s cn56xxp1;
         struct cvmx_mio_uartx_tfl_s cn58xx;
         struct cvmx_mio_uartx_tfl_s cn58xxp1;
-        struct cvmx_mio_uartx_tfl_s cn61xx;
         struct cvmx_mio_uartx_tfl_s cn63xx;
         struct cvmx_mio_uartx_tfl_s cn63xxp1;
-        struct cvmx_mio_uartx_tfl_s cn66xx;
-        struct cvmx_mio_uartx_tfl_s cn68xx;
-        struct cvmx_mio_uartx_tfl_s cn68xxp1;
-        struct cvmx_mio_uartx_tfl_s cnf71xx;
 };
 
 union cvmx_mio_uartx_tfr {
         uint64_t u64;
         struct cvmx_mio_uartx_tfr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t tfr:8;
-#else
-                uint64_t tfr:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_tfr_s cn30xx;
         struct cvmx_mio_uartx_tfr_s cn31xx;
@@ -4668,25 +2023,15 @@ union cvmx_mio_uartx_tfr {
         struct cvmx_mio_uartx_tfr_s cn56xxp1;
         struct cvmx_mio_uartx_tfr_s cn58xx;
         struct cvmx_mio_uartx_tfr_s cn58xxp1;
-        struct cvmx_mio_uartx_tfr_s cn61xx;
         struct cvmx_mio_uartx_tfr_s cn63xx;
         struct cvmx_mio_uartx_tfr_s cn63xxp1;
-        struct cvmx_mio_uartx_tfr_s cn66xx;
-        struct cvmx_mio_uartx_tfr_s cn68xx;
-        struct cvmx_mio_uartx_tfr_s cn68xxp1;
-        struct cvmx_mio_uartx_tfr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_thr {
         uint64_t u64;
         struct cvmx_mio_uartx_thr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t thr:8;
-#else
-                uint64_t thr:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uartx_thr_s cn30xx;
         struct cvmx_mio_uartx_thr_s cn31xx;
@@ -4699,33 +2044,19 @@ union cvmx_mio_uartx_thr {
         struct cvmx_mio_uartx_thr_s cn56xxp1;
         struct cvmx_mio_uartx_thr_s cn58xx;
         struct cvmx_mio_uartx_thr_s cn58xxp1;
-        struct cvmx_mio_uartx_thr_s cn61xx;
         struct cvmx_mio_uartx_thr_s cn63xx;
         struct cvmx_mio_uartx_thr_s cn63xxp1;
-        struct cvmx_mio_uartx_thr_s cn66xx;
-        struct cvmx_mio_uartx_thr_s cn68xx;
-        struct cvmx_mio_uartx_thr_s cn68xxp1;
-        struct cvmx_mio_uartx_thr_s cnf71xx;
 };
 
 union cvmx_mio_uartx_usr {
         uint64_t u64;
         struct cvmx_mio_uartx_usr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t rff:1;
                 uint64_t rfne:1;
                 uint64_t tfe:1;
                 uint64_t tfnf:1;
                 uint64_t busy:1;
-#else
-                uint64_t busy:1;
-                uint64_t tfnf:1;
-                uint64_t tfe:1;
-                uint64_t rfne:1;
-                uint64_t rff:1;
-                uint64_t reserved_5_63:59;
-#endif
         } s;
         struct cvmx_mio_uartx_usr_s cn30xx;
         struct cvmx_mio_uartx_usr_s cn31xx;
@@ -4738,25 +2069,15 @@ union cvmx_mio_uartx_usr {
         struct cvmx_mio_uartx_usr_s cn56xxp1;
         struct cvmx_mio_uartx_usr_s cn58xx;
         struct cvmx_mio_uartx_usr_s cn58xxp1;
-        struct cvmx_mio_uartx_usr_s cn61xx;
         struct cvmx_mio_uartx_usr_s cn63xx;
         struct cvmx_mio_uartx_usr_s cn63xxp1;
-        struct cvmx_mio_uartx_usr_s cn66xx;
-        struct cvmx_mio_uartx_usr_s cn68xx;
-        struct cvmx_mio_uartx_usr_s cn68xxp1;
-        struct cvmx_mio_uartx_usr_s cnf71xx;
 };
 
 union cvmx_mio_uart2_dlh {
         uint64_t u64;
         struct cvmx_mio_uart2_dlh_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t dlh:8;
-#else
-                uint64_t dlh:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_dlh_s cn52xx;
         struct cvmx_mio_uart2_dlh_s cn52xxp1;
@@ -4765,13 +2086,8 @@ union cvmx_mio_uart2_dlh {
 union cvmx_mio_uart2_dll {
         uint64_t u64;
         struct cvmx_mio_uart2_dll_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t dll:8;
-#else
-                uint64_t dll:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_dll_s cn52xx;
         struct cvmx_mio_uart2_dll_s cn52xxp1;
@@ -4780,13 +2096,8 @@ union cvmx_mio_uart2_dll {
 union cvmx_mio_uart2_far {
         uint64_t u64;
         struct cvmx_mio_uart2_far_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t far:1;
-#else
-                uint64_t far:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uart2_far_s cn52xx;
         struct cvmx_mio_uart2_far_s cn52xxp1;
@@ -4795,7 +2106,6 @@ union cvmx_mio_uart2_far {
 union cvmx_mio_uart2_fcr {
         uint64_t u64;
         struct cvmx_mio_uart2_fcr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t rxtrig:2;
                 uint64_t txtrig:2;
@@ -4803,15 +2113,6 @@ union cvmx_mio_uart2_fcr {
                 uint64_t txfr:1;
                 uint64_t rxfr:1;
                 uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t rxfr:1;
-                uint64_t txfr:1;
-                uint64_t reserved_3_3:1;
-                uint64_t txtrig:2;
-                uint64_t rxtrig:2;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_fcr_s cn52xx;
         struct cvmx_mio_uart2_fcr_s cn52xxp1;
@@ -4820,13 +2121,8 @@ union cvmx_mio_uart2_fcr {
 union cvmx_mio_uart2_htx {
         uint64_t u64;
         struct cvmx_mio_uart2_htx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t htx:1;
-#else
-                uint64_t htx:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uart2_htx_s cn52xx;
         struct cvmx_mio_uart2_htx_s cn52xxp1;
@@ -4835,7 +2131,6 @@ union cvmx_mio_uart2_htx {
 union cvmx_mio_uart2_ier {
         uint64_t u64;
         struct cvmx_mio_uart2_ier_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t ptime:1;
                 uint64_t reserved_4_6:3;
@@ -4843,15 +2138,6 @@ union cvmx_mio_uart2_ier {
                 uint64_t elsi:1;
                 uint64_t etbei:1;
                 uint64_t erbfi:1;
-#else
-                uint64_t erbfi:1;
-                uint64_t etbei:1;
-                uint64_t elsi:1;
-                uint64_t edssi:1;
-                uint64_t reserved_4_6:3;
-                uint64_t ptime:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_ier_s cn52xx;
         struct cvmx_mio_uart2_ier_s cn52xxp1;
@@ -4860,17 +2146,10 @@ union cvmx_mio_uart2_ier {
 union cvmx_mio_uart2_iir {
         uint64_t u64;
         struct cvmx_mio_uart2_iir_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t fen:2;
                 uint64_t reserved_4_5:2;
                 uint64_t iid:4;
-#else
-                uint64_t iid:4;
-                uint64_t reserved_4_5:2;
-                uint64_t fen:2;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_iir_s cn52xx;
         struct cvmx_mio_uart2_iir_s cn52xxp1;
@@ -4879,7 +2158,6 @@ union cvmx_mio_uart2_iir {
 union cvmx_mio_uart2_lcr {
         uint64_t u64;
         struct cvmx_mio_uart2_lcr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t dlab:1;
                 uint64_t brk:1;
@@ -4888,16 +2166,6 @@ union cvmx_mio_uart2_lcr {
                 uint64_t pen:1;
                 uint64_t stop:1;
                 uint64_t cls:2;
-#else
-                uint64_t cls:2;
-                uint64_t stop:1;
-                uint64_t pen:1;
-                uint64_t eps:1;
-                uint64_t reserved_5_5:1;
-                uint64_t brk:1;
-                uint64_t dlab:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_lcr_s cn52xx;
         struct cvmx_mio_uart2_lcr_s cn52xxp1;
@@ -4906,7 +2174,6 @@ union cvmx_mio_uart2_lcr {
 union cvmx_mio_uart2_lsr {
         uint64_t u64;
         struct cvmx_mio_uart2_lsr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t ferr:1;
                 uint64_t temt:1;
@@ -4916,17 +2183,6 @@ union cvmx_mio_uart2_lsr {
                 uint64_t pe:1;
                 uint64_t oe:1;
                 uint64_t dr:1;
-#else
-                uint64_t dr:1;
-                uint64_t oe:1;
-                uint64_t pe:1;
-                uint64_t fe:1;
-                uint64_t bi:1;
-                uint64_t thre:1;
-                uint64_t temt:1;
-                uint64_t ferr:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_lsr_s cn52xx;
         struct cvmx_mio_uart2_lsr_s cn52xxp1;
@@ -4935,7 +2191,6 @@ union cvmx_mio_uart2_lsr {
 union cvmx_mio_uart2_mcr {
         uint64_t u64;
         struct cvmx_mio_uart2_mcr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t afce:1;
                 uint64_t loop:1;
@@ -4943,15 +2198,6 @@ union cvmx_mio_uart2_mcr {
                 uint64_t out1:1;
                 uint64_t rts:1;
                 uint64_t dtr:1;
-#else
-                uint64_t dtr:1;
-                uint64_t rts:1;
-                uint64_t out1:1;
-                uint64_t out2:1;
-                uint64_t loop:1;
-                uint64_t afce:1;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_mio_uart2_mcr_s cn52xx;
         struct cvmx_mio_uart2_mcr_s cn52xxp1;
@@ -4960,7 +2206,6 @@ union cvmx_mio_uart2_mcr {
 union cvmx_mio_uart2_msr {
         uint64_t u64;
         struct cvmx_mio_uart2_msr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t dcd:1;
                 uint64_t ri:1;
@@ -4970,17 +2215,6 @@ union cvmx_mio_uart2_msr {
                 uint64_t teri:1;
                 uint64_t ddsr:1;
                 uint64_t dcts:1;
-#else
-                uint64_t dcts:1;
-                uint64_t ddsr:1;
-                uint64_t teri:1;
-                uint64_t ddcd:1;
-                uint64_t cts:1;
-                uint64_t dsr:1;
-                uint64_t ri:1;
-                uint64_t dcd:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_msr_s cn52xx;
         struct cvmx_mio_uart2_msr_s cn52xxp1;
@@ -4989,13 +2223,8 @@ union cvmx_mio_uart2_msr {
 union cvmx_mio_uart2_rbr {
         uint64_t u64;
         struct cvmx_mio_uart2_rbr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t rbr:8;
-#else
-                uint64_t rbr:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_rbr_s cn52xx;
         struct cvmx_mio_uart2_rbr_s cn52xxp1;
@@ -5004,13 +2233,8 @@ union cvmx_mio_uart2_rbr {
 union cvmx_mio_uart2_rfl {
         uint64_t u64;
         struct cvmx_mio_uart2_rfl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t rfl:7;
-#else
-                uint64_t rfl:7;
-                uint64_t reserved_7_63:57;
-#endif
         } s;
         struct cvmx_mio_uart2_rfl_s cn52xx;
         struct cvmx_mio_uart2_rfl_s cn52xxp1;
@@ -5019,17 +2243,10 @@ union cvmx_mio_uart2_rfl {
 union cvmx_mio_uart2_rfw {
         uint64_t u64;
         struct cvmx_mio_uart2_rfw_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t rffe:1;
                 uint64_t rfpe:1;
                 uint64_t rfwd:8;
-#else
-                uint64_t rfwd:8;
-                uint64_t rfpe:1;
-                uint64_t rffe:1;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_mio_uart2_rfw_s cn52xx;
         struct cvmx_mio_uart2_rfw_s cn52xxp1;
@@ -5038,13 +2255,8 @@ union cvmx_mio_uart2_rfw {
 union cvmx_mio_uart2_sbcr {
         uint64_t u64;
         struct cvmx_mio_uart2_sbcr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t sbcr:1;
-#else
-                uint64_t sbcr:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uart2_sbcr_s cn52xx;
         struct cvmx_mio_uart2_sbcr_s cn52xxp1;
@@ -5053,13 +2265,8 @@ union cvmx_mio_uart2_sbcr {
 union cvmx_mio_uart2_scr {
         uint64_t u64;
         struct cvmx_mio_uart2_scr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t scr:8;
-#else
-                uint64_t scr:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_scr_s cn52xx;
         struct cvmx_mio_uart2_scr_s cn52xxp1;
@@ -5068,13 +2275,8 @@ union cvmx_mio_uart2_scr {
 union cvmx_mio_uart2_sfe {
         uint64_t u64;
         struct cvmx_mio_uart2_sfe_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t sfe:1;
-#else
-                uint64_t sfe:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uart2_sfe_s cn52xx;
         struct cvmx_mio_uart2_sfe_s cn52xxp1;
@@ -5083,17 +2285,10 @@ union cvmx_mio_uart2_sfe {
 union cvmx_mio_uart2_srr {
         uint64_t u64;
         struct cvmx_mio_uart2_srr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_3_63:61;
                 uint64_t stfr:1;
                 uint64_t srfr:1;
                 uint64_t usr:1;
-#else
-                uint64_t usr:1;
-                uint64_t srfr:1;
-                uint64_t stfr:1;
-                uint64_t reserved_3_63:61;
-#endif
         } s;
         struct cvmx_mio_uart2_srr_s cn52xx;
         struct cvmx_mio_uart2_srr_s cn52xxp1;
@@ -5102,13 +2297,8 @@ union cvmx_mio_uart2_srr {
 union cvmx_mio_uart2_srt {
         uint64_t u64;
         struct cvmx_mio_uart2_srt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t srt:2;
-#else
-                uint64_t srt:2;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_mio_uart2_srt_s cn52xx;
         struct cvmx_mio_uart2_srt_s cn52xxp1;
@@ -5117,13 +2307,8 @@ union cvmx_mio_uart2_srt {
 union cvmx_mio_uart2_srts {
         uint64_t u64;
         struct cvmx_mio_uart2_srts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t srts:1;
-#else
-                uint64_t srts:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_mio_uart2_srts_s cn52xx;
         struct cvmx_mio_uart2_srts_s cn52xxp1;
@@ -5132,13 +2317,8 @@ union cvmx_mio_uart2_srts {
 union cvmx_mio_uart2_stt {
         uint64_t u64;
         struct cvmx_mio_uart2_stt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t stt:2;
-#else
-                uint64_t stt:2;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_mio_uart2_stt_s cn52xx;
         struct cvmx_mio_uart2_stt_s cn52xxp1;
@@ -5147,13 +2327,8 @@ union cvmx_mio_uart2_stt {
 union cvmx_mio_uart2_tfl {
         uint64_t u64;
         struct cvmx_mio_uart2_tfl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t tfl:7;
-#else
-                uint64_t tfl:7;
-                uint64_t reserved_7_63:57;
-#endif
         } s;
         struct cvmx_mio_uart2_tfl_s cn52xx;
         struct cvmx_mio_uart2_tfl_s cn52xxp1;
@@ -5162,13 +2337,8 @@ union cvmx_mio_uart2_tfl {
 union cvmx_mio_uart2_tfr {
         uint64_t u64;
         struct cvmx_mio_uart2_tfr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t tfr:8;
-#else
-                uint64_t tfr:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_tfr_s cn52xx;
         struct cvmx_mio_uart2_tfr_s cn52xxp1;
@@ -5177,13 +2347,8 @@ union cvmx_mio_uart2_tfr {
 union cvmx_mio_uart2_thr {
         uint64_t u64;
         struct cvmx_mio_uart2_thr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t thr:8;
-#else
-                uint64_t thr:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mio_uart2_thr_s cn52xx;
         struct cvmx_mio_uart2_thr_s cn52xxp1;
@@ -5192,21 +2357,12 @@ union cvmx_mio_uart2_thr {
 union cvmx_mio_uart2_usr {
         uint64_t u64;
         struct cvmx_mio_uart2_usr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t rff:1;
                 uint64_t rfne:1;
                 uint64_t tfe:1;
                 uint64_t tfnf:1;
                 uint64_t busy:1;
-#else
-                uint64_t busy:1;
-                uint64_t tfnf:1;
-                uint64_t tfe:1;
-                uint64_t rfne:1;
-                uint64_t rff:1;
-                uint64_t reserved_5_63:59;
-#endif
         } s;
         struct cvmx_mio_uart2_usr_s cn52xx;
         struct cvmx_mio_uart2_usr_s cn52xxp1;
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
index 3155e6019dc..7057c447e69 100644
--- a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -47,7 +47,6 @@
 union cvmx_mixx_bist {
         uint64_t u64;
         struct cvmx_mixx_bist_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t opfdat:1;
                 uint64_t mrgdat:1;
@@ -55,46 +54,24 @@ union cvmx_mixx_bist {
                 uint64_t ipfdat:1;
                 uint64_t irfdat:1;
                 uint64_t orfdat:1;
-#else
-                uint64_t orfdat:1;
-                uint64_t irfdat:1;
-                uint64_t ipfdat:1;
-                uint64_t mrqdat:1;
-                uint64_t mrgdat:1;
-                uint64_t opfdat:1;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_mixx_bist_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t mrqdat:1;
                 uint64_t ipfdat:1;
                 uint64_t irfdat:1;
                 uint64_t orfdat:1;
-#else
-                uint64_t orfdat:1;
-                uint64_t irfdat:1;
-                uint64_t ipfdat:1;
-                uint64_t mrqdat:1;
-                uint64_t reserved_4_63:60;
-#endif
         } cn52xx;
         struct cvmx_mixx_bist_cn52xx cn52xxp1;
         struct cvmx_mixx_bist_cn52xx cn56xx;
         struct cvmx_mixx_bist_cn52xx cn56xxp1;
-        struct cvmx_mixx_bist_s cn61xx;
         struct cvmx_mixx_bist_s cn63xx;
         struct cvmx_mixx_bist_s cn63xxp1;
-        struct cvmx_mixx_bist_s cn66xx;
-        struct cvmx_mixx_bist_s cn68xx;
-        struct cvmx_mixx_bist_s cn68xxp1;
 };
 
 union cvmx_mixx_ctl {
         uint64_t u64;
         struct cvmx_mixx_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t ts_thresh:4;
                 uint64_t crc_strip:1;
@@ -104,20 +81,8 @@ union cvmx_mixx_ctl {
                 uint64_t lendian:1;
                 uint64_t nbtarb:1;
                 uint64_t mrq_hwm:2;
-#else
-                uint64_t mrq_hwm:2;
-                uint64_t nbtarb:1;
-                uint64_t lendian:1;
-                uint64_t reset:1;
-                uint64_t en:1;
-                uint64_t busy:1;
-                uint64_t crc_strip:1;
-                uint64_t ts_thresh:4;
-                uint64_t reserved_12_63:52;
-#endif
         } s;
         struct cvmx_mixx_ctl_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t crc_strip:1;
                 uint64_t busy:1;
@@ -126,32 +91,17 @@ union cvmx_mixx_ctl {
                 uint64_t lendian:1;
                 uint64_t nbtarb:1;
                 uint64_t mrq_hwm:2;
-#else
-                uint64_t mrq_hwm:2;
-                uint64_t nbtarb:1;
-                uint64_t lendian:1;
-                uint64_t reset:1;
-                uint64_t en:1;
-                uint64_t busy:1;
-                uint64_t crc_strip:1;
-                uint64_t reserved_8_63:56;
-#endif
         } cn52xx;
         struct cvmx_mixx_ctl_cn52xx cn52xxp1;
         struct cvmx_mixx_ctl_cn52xx cn56xx;
         struct cvmx_mixx_ctl_cn52xx cn56xxp1;
-        struct cvmx_mixx_ctl_s cn61xx;
         struct cvmx_mixx_ctl_s cn63xx;
         struct cvmx_mixx_ctl_s cn63xxp1;
-        struct cvmx_mixx_ctl_s cn66xx;
-        struct cvmx_mixx_ctl_s cn68xx;
-        struct cvmx_mixx_ctl_s cn68xxp1;
 };
 
 union cvmx_mixx_intena {
         uint64_t u64;
         struct cvmx_mixx_intena_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t tsena:1;
                 uint64_t orunena:1;
@@ -161,20 +111,8 @@ union cvmx_mixx_intena {
                 uint64_t othena:1;
                 uint64_t ivfena:1;
                 uint64_t ovfena:1;
-#else
-                uint64_t ovfena:1;
-                uint64_t ivfena:1;
-                uint64_t othena:1;
-                uint64_t ithena:1;
-                uint64_t data_drpena:1;
-                uint64_t irunena:1;
-                uint64_t orunena:1;
-                uint64_t tsena:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mixx_intena_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t orunena:1;
                 uint64_t irunena:1;
@@ -183,148 +121,84 @@ union cvmx_mixx_intena {
                 uint64_t othena:1;
                 uint64_t ivfena:1;
                 uint64_t ovfena:1;
-#else
-                uint64_t ovfena:1;
-                uint64_t ivfena:1;
-                uint64_t othena:1;
-                uint64_t ithena:1;
-                uint64_t data_drpena:1;
-                uint64_t irunena:1;
-                uint64_t orunena:1;
-                uint64_t reserved_7_63:57;
-#endif
         } cn52xx;
         struct cvmx_mixx_intena_cn52xx cn52xxp1;
         struct cvmx_mixx_intena_cn52xx cn56xx;
         struct cvmx_mixx_intena_cn52xx cn56xxp1;
-        struct cvmx_mixx_intena_s cn61xx;
         struct cvmx_mixx_intena_s cn63xx;
         struct cvmx_mixx_intena_s cn63xxp1;
-        struct cvmx_mixx_intena_s cn66xx;
-        struct cvmx_mixx_intena_s cn68xx;
-        struct cvmx_mixx_intena_s cn68xxp1;
 };
 
 union cvmx_mixx_ircnt {
         uint64_t u64;
         struct cvmx_mixx_ircnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t ircnt:20;
-#else
-                uint64_t ircnt:20;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
         struct cvmx_mixx_ircnt_s cn52xx;
         struct cvmx_mixx_ircnt_s cn52xxp1;
         struct cvmx_mixx_ircnt_s cn56xx;
         struct cvmx_mixx_ircnt_s cn56xxp1;
-        struct cvmx_mixx_ircnt_s cn61xx;
         struct cvmx_mixx_ircnt_s cn63xx;
         struct cvmx_mixx_ircnt_s cn63xxp1;
-        struct cvmx_mixx_ircnt_s cn66xx;
-        struct cvmx_mixx_ircnt_s cn68xx;
-        struct cvmx_mixx_ircnt_s cn68xxp1;
 };
 
 union cvmx_mixx_irhwm {
         uint64_t u64;
         struct cvmx_mixx_irhwm_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t ibplwm:20;
                 uint64_t irhwm:20;
-#else
-                uint64_t irhwm:20;
-                uint64_t ibplwm:20;
-                uint64_t reserved_40_63:24;
-#endif
         } s;
         struct cvmx_mixx_irhwm_s cn52xx;
         struct cvmx_mixx_irhwm_s cn52xxp1;
         struct cvmx_mixx_irhwm_s cn56xx;
         struct cvmx_mixx_irhwm_s cn56xxp1;
-        struct cvmx_mixx_irhwm_s cn61xx;
         struct cvmx_mixx_irhwm_s cn63xx;
         struct cvmx_mixx_irhwm_s cn63xxp1;
-        struct cvmx_mixx_irhwm_s cn66xx;
-        struct cvmx_mixx_irhwm_s cn68xx;
-        struct cvmx_mixx_irhwm_s cn68xxp1;
 };
 
 union cvmx_mixx_iring1 {
         uint64_t u64;
         struct cvmx_mixx_iring1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_60_63:4;
                 uint64_t isize:20;
                 uint64_t ibase:37;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t ibase:37;
-                uint64_t isize:20;
-                uint64_t reserved_60_63:4;
-#endif
         } s;
         struct cvmx_mixx_iring1_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_60_63:4;
                 uint64_t isize:20;
                 uint64_t reserved_36_39:4;
                 uint64_t ibase:33;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t ibase:33;
-                uint64_t reserved_36_39:4;
-                uint64_t isize:20;
-                uint64_t reserved_60_63:4;
-#endif
         } cn52xx;
         struct cvmx_mixx_iring1_cn52xx cn52xxp1;
         struct cvmx_mixx_iring1_cn52xx cn56xx;
         struct cvmx_mixx_iring1_cn52xx cn56xxp1;
-        struct cvmx_mixx_iring1_s cn61xx;
         struct cvmx_mixx_iring1_s cn63xx;
         struct cvmx_mixx_iring1_s cn63xxp1;
-        struct cvmx_mixx_iring1_s cn66xx;
-        struct cvmx_mixx_iring1_s cn68xx;
-        struct cvmx_mixx_iring1_s cn68xxp1;
 };
 
 union cvmx_mixx_iring2 {
         uint64_t u64;
         struct cvmx_mixx_iring2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_52_63:12;
                 uint64_t itlptr:20;
                 uint64_t reserved_20_31:12;
                 uint64_t idbell:20;
-#else
-                uint64_t idbell:20;
-                uint64_t reserved_20_31:12;
-                uint64_t itlptr:20;
-                uint64_t reserved_52_63:12;
-#endif
         } s;
         struct cvmx_mixx_iring2_s cn52xx;
         struct cvmx_mixx_iring2_s cn52xxp1;
         struct cvmx_mixx_iring2_s cn56xx;
         struct cvmx_mixx_iring2_s cn56xxp1;
-        struct cvmx_mixx_iring2_s cn61xx;
         struct cvmx_mixx_iring2_s cn63xx;
         struct cvmx_mixx_iring2_s cn63xxp1;
-        struct cvmx_mixx_iring2_s cn66xx;
-        struct cvmx_mixx_iring2_s cn68xx;
-        struct cvmx_mixx_iring2_s cn68xxp1;
 };
 
 union cvmx_mixx_isr {
         uint64_t u64;
         struct cvmx_mixx_isr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t ts:1;
                 uint64_t orun:1;
@@ -334,20 +208,8 @@ union cvmx_mixx_isr {
                 uint64_t orthresh:1;
                 uint64_t idblovf:1;
                 uint64_t odblovf:1;
-#else
-                uint64_t odblovf:1;
-                uint64_t idblovf:1;
-                uint64_t orthresh:1;
-                uint64_t irthresh:1;
-                uint64_t data_drp:1;
-                uint64_t irun:1;
-                uint64_t orun:1;
-                uint64_t ts:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_mixx_isr_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t orun:1;
                 uint64_t irun:1;
@@ -356,211 +218,117 @@ union cvmx_mixx_isr {
                 uint64_t orthresh:1;
                 uint64_t idblovf:1;
                 uint64_t odblovf:1;
-#else
-                uint64_t odblovf:1;
-                uint64_t idblovf:1;
-                uint64_t orthresh:1;
-                uint64_t irthresh:1;
-                uint64_t data_drp:1;
-                uint64_t irun:1;
-                uint64_t orun:1;
-                uint64_t reserved_7_63:57;
-#endif
         } cn52xx;
         struct cvmx_mixx_isr_cn52xx cn52xxp1;
         struct cvmx_mixx_isr_cn52xx cn56xx;
         struct cvmx_mixx_isr_cn52xx cn56xxp1;
-        struct cvmx_mixx_isr_s cn61xx;
         struct cvmx_mixx_isr_s cn63xx;
         struct cvmx_mixx_isr_s cn63xxp1;
-        struct cvmx_mixx_isr_s cn66xx;
-        struct cvmx_mixx_isr_s cn68xx;
-        struct cvmx_mixx_isr_s cn68xxp1;
 };
 
 union cvmx_mixx_orcnt {
         uint64_t u64;
         struct cvmx_mixx_orcnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t orcnt:20;
-#else
-                uint64_t orcnt:20;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
         struct cvmx_mixx_orcnt_s cn52xx;
         struct cvmx_mixx_orcnt_s cn52xxp1;
         struct cvmx_mixx_orcnt_s cn56xx;
         struct cvmx_mixx_orcnt_s cn56xxp1;
-        struct cvmx_mixx_orcnt_s cn61xx;
         struct cvmx_mixx_orcnt_s cn63xx;
         struct cvmx_mixx_orcnt_s cn63xxp1;
-        struct cvmx_mixx_orcnt_s cn66xx;
-        struct cvmx_mixx_orcnt_s cn68xx;
-        struct cvmx_mixx_orcnt_s cn68xxp1;
 };
 
 union cvmx_mixx_orhwm {
         uint64_t u64;
         struct cvmx_mixx_orhwm_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t orhwm:20;
-#else
-                uint64_t orhwm:20;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
         struct cvmx_mixx_orhwm_s cn52xx;
         struct cvmx_mixx_orhwm_s cn52xxp1;
         struct cvmx_mixx_orhwm_s cn56xx;
         struct cvmx_mixx_orhwm_s cn56xxp1;
-        struct cvmx_mixx_orhwm_s cn61xx;
         struct cvmx_mixx_orhwm_s cn63xx;
         struct cvmx_mixx_orhwm_s cn63xxp1;
-        struct cvmx_mixx_orhwm_s cn66xx;
-        struct cvmx_mixx_orhwm_s cn68xx;
-        struct cvmx_mixx_orhwm_s cn68xxp1;
 };
 
 union cvmx_mixx_oring1 {
         uint64_t u64;
         struct cvmx_mixx_oring1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_60_63:4;
                 uint64_t osize:20;
                 uint64_t obase:37;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t obase:37;
-                uint64_t osize:20;
-                uint64_t reserved_60_63:4;
-#endif
         } s;
         struct cvmx_mixx_oring1_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_60_63:4;
                 uint64_t osize:20;
                 uint64_t reserved_36_39:4;
                 uint64_t obase:33;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t obase:33;
-                uint64_t reserved_36_39:4;
-                uint64_t osize:20;
-                uint64_t reserved_60_63:4;
-#endif
         } cn52xx;
         struct cvmx_mixx_oring1_cn52xx cn52xxp1;
         struct cvmx_mixx_oring1_cn52xx cn56xx;
         struct cvmx_mixx_oring1_cn52xx cn56xxp1;
-        struct cvmx_mixx_oring1_s cn61xx;
         struct cvmx_mixx_oring1_s cn63xx;
         struct cvmx_mixx_oring1_s cn63xxp1;
-        struct cvmx_mixx_oring1_s cn66xx;
-        struct cvmx_mixx_oring1_s cn68xx;
-        struct cvmx_mixx_oring1_s cn68xxp1;
 };
 
 union cvmx_mixx_oring2 {
         uint64_t u64;
         struct cvmx_mixx_oring2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_52_63:12;
                 uint64_t otlptr:20;
                 uint64_t reserved_20_31:12;
                 uint64_t odbell:20;
-#else
-                uint64_t odbell:20;
-                uint64_t reserved_20_31:12;
-                uint64_t otlptr:20;
-                uint64_t reserved_52_63:12;
-#endif
         } s;
         struct cvmx_mixx_oring2_s cn52xx;
         struct cvmx_mixx_oring2_s cn52xxp1;
         struct cvmx_mixx_oring2_s cn56xx;
         struct cvmx_mixx_oring2_s cn56xxp1;
-        struct cvmx_mixx_oring2_s cn61xx;
         struct cvmx_mixx_oring2_s cn63xx;
         struct cvmx_mixx_oring2_s cn63xxp1;
-        struct cvmx_mixx_oring2_s cn66xx;
-        struct cvmx_mixx_oring2_s cn68xx;
-        struct cvmx_mixx_oring2_s cn68xxp1;
 };
 
 union cvmx_mixx_remcnt {
         uint64_t u64;
         struct cvmx_mixx_remcnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_52_63:12;
                 uint64_t iremcnt:20;
                 uint64_t reserved_20_31:12;
                 uint64_t oremcnt:20;
-#else
-                uint64_t oremcnt:20;
-                uint64_t reserved_20_31:12;
-                uint64_t iremcnt:20;
-                uint64_t reserved_52_63:12;
-#endif
         } s;
         struct cvmx_mixx_remcnt_s cn52xx;
         struct cvmx_mixx_remcnt_s cn52xxp1;
         struct cvmx_mixx_remcnt_s cn56xx;
         struct cvmx_mixx_remcnt_s cn56xxp1;
-        struct cvmx_mixx_remcnt_s cn61xx;
         struct cvmx_mixx_remcnt_s cn63xx;
         struct cvmx_mixx_remcnt_s cn63xxp1;
-        struct cvmx_mixx_remcnt_s cn66xx;
-        struct cvmx_mixx_remcnt_s cn68xx;
-        struct cvmx_mixx_remcnt_s cn68xxp1;
 };
 
 union cvmx_mixx_tsctl {
         uint64_t u64;
         struct cvmx_mixx_tsctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_21_63:43;
                 uint64_t tsavl:5;
                 uint64_t reserved_13_15:3;
                 uint64_t tstot:5;
                 uint64_t reserved_5_7:3;
                 uint64_t tscnt:5;
-#else
-                uint64_t tscnt:5;
-                uint64_t reserved_5_7:3;
-                uint64_t tstot:5;
-                uint64_t reserved_13_15:3;
-                uint64_t tsavl:5;
-                uint64_t reserved_21_63:43;
-#endif
         } s;
-        struct cvmx_mixx_tsctl_s cn61xx;
         struct cvmx_mixx_tsctl_s cn63xx;
         struct cvmx_mixx_tsctl_s cn63xxp1;
-        struct cvmx_mixx_tsctl_s cn66xx;
-        struct cvmx_mixx_tsctl_s cn68xx;
-        struct cvmx_mixx_tsctl_s cn68xxp1;
 };
 
 union cvmx_mixx_tstamp {
         uint64_t u64;
         struct cvmx_mixx_tstamp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t tstamp:64;
-#else
-                uint64_t tstamp:64;
-#endif
         } s;
-        struct cvmx_mixx_tstamp_s cn61xx;
         struct cvmx_mixx_tstamp_s cn63xx;
         struct cvmx_mixx_tstamp_s cn63xxp1;
-        struct cvmx_mixx_tstamp_s cn66xx;
-        struct cvmx_mixx_tstamp_s cn68xx;
-        struct cvmx_mixx_tstamp_s cn68xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mpi-defs.h b/arch/mips/include/asm/octeon/cvmx-mpi-defs.h
deleted file mode 100644
index 4615b102625..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-mpi-defs.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_MPI_DEFS_H__
-#define __CVMX_MPI_DEFS_H__
-
-#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
-#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
-#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
-#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
-
-union cvmx_mpi_cfg {
-        uint64_t u64;
-        struct cvmx_mpi_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t clkdiv:13;
-                uint64_t csena3:1;
-                uint64_t csena2:1;
-                uint64_t csena1:1;
-                uint64_t csena0:1;
-                uint64_t cslate:1;
-                uint64_t tritx:1;
-                uint64_t idleclks:2;
-                uint64_t cshi:1;
-                uint64_t csena:1;
-                uint64_t int_ena:1;
-                uint64_t lsbfirst:1;
-                uint64_t wireor:1;
-                uint64_t clk_cont:1;
-                uint64_t idlelo:1;
-                uint64_t enable:1;
-#else
-                uint64_t enable:1;
-                uint64_t idlelo:1;
-                uint64_t clk_cont:1;
-                uint64_t wireor:1;
-                uint64_t lsbfirst:1;
-                uint64_t int_ena:1;
-                uint64_t csena:1;
-                uint64_t cshi:1;
-                uint64_t idleclks:2;
-                uint64_t tritx:1;
-                uint64_t cslate:1;
-                uint64_t csena0:1;
-                uint64_t csena1:1;
-                uint64_t csena2:1;
-                uint64_t csena3:1;
-                uint64_t clkdiv:13;
-                uint64_t reserved_29_63:35;
-#endif
-        } s;
-        struct cvmx_mpi_cfg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t clkdiv:13;
-                uint64_t reserved_12_15:4;
-                uint64_t cslate:1;
-                uint64_t tritx:1;
-                uint64_t idleclks:2;
-                uint64_t cshi:1;
-                uint64_t csena:1;
-                uint64_t int_ena:1;
-                uint64_t lsbfirst:1;
-                uint64_t wireor:1;
-                uint64_t clk_cont:1;
-                uint64_t idlelo:1;
-                uint64_t enable:1;
-#else
-                uint64_t enable:1;
-                uint64_t idlelo:1;
-                uint64_t clk_cont:1;
-                uint64_t wireor:1;
-                uint64_t lsbfirst:1;
-                uint64_t int_ena:1;
-                uint64_t csena:1;
-                uint64_t cshi:1;
-                uint64_t idleclks:2;
-                uint64_t tritx:1;
-                uint64_t cslate:1;
-                uint64_t reserved_12_15:4;
-                uint64_t clkdiv:13;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn30xx;
-        struct cvmx_mpi_cfg_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t clkdiv:13;
-                uint64_t reserved_11_15:5;
-                uint64_t tritx:1;
-                uint64_t idleclks:2;
-                uint64_t cshi:1;
-                uint64_t csena:1;
-                uint64_t int_ena:1;
-                uint64_t lsbfirst:1;
-                uint64_t wireor:1;
-                uint64_t clk_cont:1;
-                uint64_t idlelo:1;
-                uint64_t enable:1;
-#else
-                uint64_t enable:1;
-                uint64_t idlelo:1;
-                uint64_t clk_cont:1;
-                uint64_t wireor:1;
-                uint64_t lsbfirst:1;
-                uint64_t int_ena:1;
-                uint64_t csena:1;
-                uint64_t cshi:1;
-                uint64_t idleclks:2;
-                uint64_t tritx:1;
-                uint64_t reserved_11_15:5;
-                uint64_t clkdiv:13;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn31xx;
-        struct cvmx_mpi_cfg_cn30xx cn50xx;
-        struct cvmx_mpi_cfg_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t clkdiv:13;
-                uint64_t reserved_14_15:2;
-                uint64_t csena1:1;
-                uint64_t csena0:1;
-                uint64_t cslate:1;
-                uint64_t tritx:1;
-                uint64_t idleclks:2;
-                uint64_t cshi:1;
-                uint64_t reserved_6_6:1;
-                uint64_t int_ena:1;
-                uint64_t lsbfirst:1;
-                uint64_t wireor:1;
-                uint64_t clk_cont:1;
-                uint64_t idlelo:1;
-                uint64_t enable:1;
-#else
-                uint64_t enable:1;
-                uint64_t idlelo:1;
-                uint64_t clk_cont:1;
-                uint64_t wireor:1;
-                uint64_t lsbfirst:1;
-                uint64_t int_ena:1;
-                uint64_t reserved_6_6:1;
-                uint64_t cshi:1;
-                uint64_t idleclks:2;
-                uint64_t tritx:1;
-                uint64_t cslate:1;
-                uint64_t csena0:1;
-                uint64_t csena1:1;
-                uint64_t reserved_14_15:2;
-                uint64_t clkdiv:13;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn61xx;
-        struct cvmx_mpi_cfg_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t clkdiv:13;
-                uint64_t csena3:1;
-                uint64_t csena2:1;
-                uint64_t reserved_12_13:2;
-                uint64_t cslate:1;
-                uint64_t tritx:1;
-                uint64_t idleclks:2;
-                uint64_t cshi:1;
-                uint64_t reserved_6_6:1;
-                uint64_t int_ena:1;
-                uint64_t lsbfirst:1;
-                uint64_t wireor:1;
-                uint64_t clk_cont:1;
-                uint64_t idlelo:1;
-                uint64_t enable:1;
-#else
-                uint64_t enable:1;
-                uint64_t idlelo:1;
-                uint64_t clk_cont:1;
-                uint64_t wireor:1;
-                uint64_t lsbfirst:1;
-                uint64_t int_ena:1;
-                uint64_t reserved_6_6:1;
-                uint64_t cshi:1;
-                uint64_t idleclks:2;
-                uint64_t tritx:1;
-                uint64_t cslate:1;
-                uint64_t reserved_12_13:2;
-                uint64_t csena2:1;
-                uint64_t csena3:1;
-                uint64_t clkdiv:13;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn66xx;
-        struct cvmx_mpi_cfg_cn61xx cnf71xx;
-};
-
-union cvmx_mpi_datx {
-        uint64_t u64;
-        struct cvmx_mpi_datx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t data:8;
-#else
-                uint64_t data:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_mpi_datx_s cn30xx;
-        struct cvmx_mpi_datx_s cn31xx;
-        struct cvmx_mpi_datx_s cn50xx;
-        struct cvmx_mpi_datx_s cn61xx;
-        struct cvmx_mpi_datx_s cn66xx;
-        struct cvmx_mpi_datx_s cnf71xx;
-};
-
-union cvmx_mpi_sts {
-        uint64_t u64;
-        struct cvmx_mpi_sts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t rxnum:5;
-                uint64_t reserved_1_7:7;
-                uint64_t busy:1;
-#else
-                uint64_t busy:1;
-                uint64_t reserved_1_7:7;
-                uint64_t rxnum:5;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_mpi_sts_s cn30xx;
-        struct cvmx_mpi_sts_s cn31xx;
-        struct cvmx_mpi_sts_s cn50xx;
-        struct cvmx_mpi_sts_s cn61xx;
-        struct cvmx_mpi_sts_s cn66xx;
-        struct cvmx_mpi_sts_s cnf71xx;
-};
-
-union cvmx_mpi_tx {
-        uint64_t u64;
-        struct cvmx_mpi_tx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t csid:2;
-                uint64_t reserved_17_19:3;
-                uint64_t leavecs:1;
-                uint64_t reserved_13_15:3;
-                uint64_t txnum:5;
-                uint64_t reserved_5_7:3;
-                uint64_t totnum:5;
-#else
-                uint64_t totnum:5;
-                uint64_t reserved_5_7:3;
-                uint64_t txnum:5;
-                uint64_t reserved_13_15:3;
-                uint64_t leavecs:1;
-                uint64_t reserved_17_19:3;
-                uint64_t csid:2;
-                uint64_t reserved_22_63:42;
-#endif
-        } s;
-        struct cvmx_mpi_tx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t leavecs:1;
-                uint64_t reserved_13_15:3;
-                uint64_t txnum:5;
-                uint64_t reserved_5_7:3;
-                uint64_t totnum:5;
-#else
-                uint64_t totnum:5;
-                uint64_t reserved_5_7:3;
-                uint64_t txnum:5;
-                uint64_t reserved_13_15:3;
-                uint64_t leavecs:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } cn30xx;
-        struct cvmx_mpi_tx_cn30xx cn31xx;
-        struct cvmx_mpi_tx_cn30xx cn50xx;
-        struct cvmx_mpi_tx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_21_63:43;
-                uint64_t csid:1;
-                uint64_t reserved_17_19:3;
-                uint64_t leavecs:1;
-                uint64_t reserved_13_15:3;
-                uint64_t txnum:5;
-                uint64_t reserved_5_7:3;
-                uint64_t totnum:5;
-#else
-                uint64_t totnum:5;
-                uint64_t reserved_5_7:3;
-                uint64_t txnum:5;
-                uint64_t reserved_13_15:3;
-                uint64_t leavecs:1;
-                uint64_t reserved_17_19:3;
-                uint64_t csid:1;
-                uint64_t reserved_21_63:43;
-#endif
-        } cn61xx;
-        struct cvmx_mpi_tx_s cn66xx;
-        struct cvmx_mpi_tx_cn61xx cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 58114d41435..9899a9d2ba7 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -65,7 +65,7 @@
 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
-#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
@@ -140,19 +140,11 @@
 union cvmx_npei_bar1_indexx {
         uint32_t u32;
         struct cvmx_npei_bar1_indexx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_18_31:14;
                 uint32_t addr_idx:14;
                 uint32_t ca:1;
                 uint32_t end_swp:2;
                 uint32_t addr_v:1;
-#else
-                uint32_t addr_v:1;
-                uint32_t end_swp:2;
-                uint32_t ca:1;
-                uint32_t addr_idx:14;
-                uint32_t reserved_18_31:14;
-#endif
         } s;
         struct cvmx_npei_bar1_indexx_s cn52xx;
         struct cvmx_npei_bar1_indexx_s cn52xxp1;
@@ -163,7 +155,6 @@ union cvmx_npei_bar1_indexx {
 union cvmx_npei_bist_status {
         uint64_t u64;
         struct cvmx_npei_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t pkt_rdf:1;
                 uint64_t reserved_60_62:3;
                 uint64_t pcr_gim:1;
@@ -213,60 +204,8 @@ union cvmx_npei_bist_status {
                 uint64_t reserved_2_2:1;
                 uint64_t msi:1;
                 uint64_t ncb_cmd:1;
-#else
-                uint64_t ncb_cmd:1;
-                uint64_t msi:1;
-                uint64_t reserved_2_2:1;
-                uint64_t dif3:1;
-                uint64_t dif2:1;
-                uint64_t dif1:1;
-                uint64_t dif0:1;
-                uint64_t csm1:1;
-                uint64_t csm0:1;
-                uint64_t p2n1_p1:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_c0:1;
-                uint64_t p2n0_co:1;
-                uint64_t p2n0_no:1;
-                uint64_t p2n0_po:1;
-                uint64_t p2n1_co:1;
-                uint64_t p2n1_no:1;
-                uint64_t p2n1_po:1;
-                uint64_t cpl_p1:1;
-                uint64_t cpl_p0:1;
-                uint64_t n2p1_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p0_c:1;
-                uint64_t reserved_31_31:1;
-                uint64_t d3_pst:1;
-                uint64_t d2_pst:1;
-                uint64_t d1_pst:1;
-                uint64_t d0_pst:1;
-                uint64_t reserved_36_47:12;
-                uint64_t pkt_slm:1;
-                uint64_t pkt_ind:1;
-                uint64_t reserved_50_52:3;
-                uint64_t pcsr_sl:1;
-                uint64_t pcsr_id:1;
-                uint64_t pcsr_cnt:1;
-                uint64_t pcsr_im:1;
-                uint64_t pcsr_int:1;
-                uint64_t pkt_pif:1;
-                uint64_t pcr_gim:1;
-                uint64_t reserved_60_62:3;
-                uint64_t pkt_rdf:1;
-#endif
         } s;
         struct cvmx_npei_bist_status_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t pkt_rdf:1;
                 uint64_t reserved_60_62:3;
                 uint64_t pcr_gim:1;
@@ -325,69 +264,8 @@ union cvmx_npei_bist_status {
                 uint64_t dif4:1;
                 uint64_t msi:1;
                 uint64_t ncb_cmd:1;
-#else
-                uint64_t ncb_cmd:1;
-                uint64_t msi:1;
-                uint64_t dif4:1;
-                uint64_t dif3:1;
-                uint64_t dif2:1;
-                uint64_t dif1:1;
-                uint64_t dif0:1;
-                uint64_t csm1:1;
-                uint64_t csm0:1;
-                uint64_t p2n1_p1:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_c0:1;
-                uint64_t p2n0_co:1;
-                uint64_t p2n0_no:1;
-                uint64_t p2n0_po:1;
-                uint64_t p2n1_co:1;
-                uint64_t p2n1_no:1;
-                uint64_t p2n1_po:1;
-                uint64_t cpl_p1:1;
-                uint64_t cpl_p0:1;
-                uint64_t n2p1_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p0_c:1;
-                uint64_t d4_pst:1;
-                uint64_t d3_pst:1;
-                uint64_t d2_pst:1;
-                uint64_t d1_pst:1;
-                uint64_t d0_pst:1;
-                uint64_t reserved_36_39:4;
-                uint64_t ds_mem:1;
-                uint64_t d4_mem:1;
-                uint64_t d3_mem:1;
-                uint64_t d2_mem:1;
-                uint64_t d1_mem:1;
-                uint64_t d0_mem:1;
-                uint64_t pkt_pop1:1;
-                uint64_t pkt_pop0:1;
-                uint64_t reserved_48_49:2;
-                uint64_t pkt_pof:1;
-                uint64_t pkt_pfm:1;
-                uint64_t pkt_imem:1;
-                uint64_t pcsr_sl:1;
-                uint64_t pcsr_id:1;
-                uint64_t pcsr_cnt:1;
-                uint64_t pcsr_im:1;
-                uint64_t pcsr_int:1;
-                uint64_t pkt_pif:1;
-                uint64_t pcr_gim:1;
-                uint64_t reserved_60_62:3;
-                uint64_t pkt_rdf:1;
-#endif
         } cn52xx;
         struct cvmx_npei_bist_status_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_46_63:18;
                 uint64_t d0_mem0:1;
                 uint64_t d1_mem1:1;
@@ -435,59 +313,9 @@ union cvmx_npei_bist_status {
                 uint64_t dr3_mem:1;
                 uint64_t msi:1;
                 uint64_t ncb_cmd:1;
-#else
-                uint64_t ncb_cmd:1;
-                uint64_t msi:1;
-                uint64_t dr3_mem:1;
-                uint64_t dif3:1;
-                uint64_t dif2:1;
-                uint64_t dif1:1;
-                uint64_t dif0:1;
-                uint64_t csm1:1;
-                uint64_t csm0:1;
-                uint64_t p2n1_p1:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_c0:1;
-                uint64_t p2n0_co:1;
-                uint64_t p2n0_no:1;
-                uint64_t p2n0_po:1;
-                uint64_t p2n1_co:1;
-                uint64_t p2n1_no:1;
-                uint64_t p2n1_po:1;
-                uint64_t cpl_p1:1;
-                uint64_t cpl_p0:1;
-                uint64_t n2p1_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p0_c:1;
-                uint64_t dr2_mem:1;
-                uint64_t d3_pst:1;
-                uint64_t d2_pst:1;
-                uint64_t d1_pst:1;
-                uint64_t d0_pst:1;
-                uint64_t dr1_mem:1;
-                uint64_t d3_mem:1;
-                uint64_t d2_mem:1;
-                uint64_t d1_mem:1;
-                uint64_t d0_mem:1;
-                uint64_t dr0_mem:1;
-                uint64_t d3_mem3:1;
-                uint64_t d2_mem2:1;
-                uint64_t d1_mem1:1;
-                uint64_t d0_mem0:1;
-                uint64_t reserved_46_63:18;
-#endif
         } cn52xxp1;
         struct cvmx_npei_bist_status_cn52xx cn56xx;
         struct cvmx_npei_bist_status_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_58_63:6;
                 uint64_t pcsr_int:1;
                 uint64_t pcsr_im:1;
@@ -547,74 +375,12 @@ union cvmx_npei_bist_status {
                 uint64_t dif4:1;
                 uint64_t msi:1;
                 uint64_t ncb_cmd:1;
-#else
-                uint64_t ncb_cmd:1;
-                uint64_t msi:1;
-                uint64_t dif4:1;
-                uint64_t dif3:1;
-                uint64_t dif2:1;
-                uint64_t dif1:1;
-                uint64_t dif0:1;
-                uint64_t csm1:1;
-                uint64_t csm0:1;
-                uint64_t p2n1_p1:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_c0:1;
-                uint64_t p2n0_co:1;
-                uint64_t p2n0_no:1;
-                uint64_t p2n0_po:1;
-                uint64_t p2n1_co:1;
-                uint64_t p2n1_no:1;
-                uint64_t p2n1_po:1;
-                uint64_t cpl_p1:1;
-                uint64_t cpl_p0:1;
-                uint64_t n2p1_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p0_c:1;
-                uint64_t d4_pst:1;
-                uint64_t d3_pst:1;
-                uint64_t d2_pst:1;
-                uint64_t d1_pst:1;
-                uint64_t d0_pst:1;
-                uint64_t d4_mem:1;
-                uint64_t d3_mem:1;
-                uint64_t d2_mem:1;
-                uint64_t d1_mem:1;
-                uint64_t d0_mem:1;
-                uint64_t pkt_s1:1;
-                uint64_t pkt_s0:1;
-                uint64_t pkt_i1:1;
-                uint64_t pkt_i0:1;
-                uint64_t pkt_out:1;
-                uint64_t pkt_oif:1;
-                uint64_t pkt_odf:1;
-                uint64_t pkt_slm:1;
-                uint64_t pkt_ind:1;
-                uint64_t pkt_cntm:1;
-                uint64_t pkt_imem:1;
-                uint64_t pkt_pout:1;
-                uint64_t pcsr_sl:1;
-                uint64_t pcsr_id:1;
-                uint64_t pcsr_cnt:1;
-                uint64_t pcsr_im:1;
-                uint64_t pcsr_int:1;
-                uint64_t reserved_58_63:6;
-#endif
         } cn56xxp1;
 };
 
 union cvmx_npei_bist_status2 {
         uint64_t u64;
         struct cvmx_npei_bist_status2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t prd_tag:1;
                 uint64_t prd_st0:1;
@@ -630,23 +396,6 @@ union cvmx_npei_bist_status2 {
                 uint64_t pkt_gd:1;
                 uint64_t pkt_gl:1;
                 uint64_t pkt_blk:1;
-#else
-                uint64_t pkt_blk:1;
-                uint64_t pkt_gl:1;
-                uint64_t pkt_gd:1;
-                uint64_t psc_p1:1;
-                uint64_t psc_p0:1;
-                uint64_t pkt_rd:1;
-                uint64_t nwe_wr1:1;
-                uint64_t nwe_wr0:1;
-                uint64_t nwe_st:1;
-                uint64_t nrd_st:1;
-                uint64_t prd_err:1;
-                uint64_t prd_st1:1;
-                uint64_t prd_st0:1;
-                uint64_t prd_tag:1;
-                uint64_t reserved_14_63:50;
-#endif
         } s;
         struct cvmx_npei_bist_status2_s cn52xx;
         struct cvmx_npei_bist_status2_s cn56xx;
@@ -655,7 +404,6 @@ union cvmx_npei_bist_status2 {
 union cvmx_npei_ctl_port0 {
         uint64_t u64;
         struct cvmx_npei_ctl_port0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_21_63:43;
                 uint64_t waitl_com:1;
                 uint64_t intd:1;
@@ -673,25 +421,6 @@ union cvmx_npei_ctl_port0 {
                 uint64_t bar2_esx:2;
                 uint64_t bar2_cax:1;
                 uint64_t wait_com:1;
-#else
-                uint64_t wait_com:1;
-                uint64_t bar2_cax:1;
-                uint64_t bar2_esx:2;
-                uint64_t bar2_enb:1;
-                uint64_t ptlp_ro:1;
-                uint64_t reserved_6_6:1;
-                uint64_t ctlp_ro:1;
-                uint64_t inta_map:2;
-                uint64_t intb_map:2;
-                uint64_t intc_map:2;
-                uint64_t intd_map:2;
-                uint64_t inta:1;
-                uint64_t intb:1;
-                uint64_t intc:1;
-                uint64_t intd:1;
-                uint64_t waitl_com:1;
-                uint64_t reserved_21_63:43;
-#endif
         } s;
         struct cvmx_npei_ctl_port0_s cn52xx;
         struct cvmx_npei_ctl_port0_s cn52xxp1;
@@ -702,7 +431,6 @@ union cvmx_npei_ctl_port0 {
 union cvmx_npei_ctl_port1 {
         uint64_t u64;
         struct cvmx_npei_ctl_port1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_21_63:43;
                 uint64_t waitl_com:1;
                 uint64_t intd:1;
@@ -720,25 +448,6 @@ union cvmx_npei_ctl_port1 {
                 uint64_t bar2_esx:2;
                 uint64_t bar2_cax:1;
                 uint64_t wait_com:1;
-#else
-                uint64_t wait_com:1;
-                uint64_t bar2_cax:1;
-                uint64_t bar2_esx:2;
-                uint64_t bar2_enb:1;
-                uint64_t ptlp_ro:1;
-                uint64_t reserved_6_6:1;
-                uint64_t ctlp_ro:1;
-                uint64_t inta_map:2;
-                uint64_t intb_map:2;
-                uint64_t intc_map:2;
-                uint64_t intd_map:2;
-                uint64_t inta:1;
-                uint64_t intb:1;
-                uint64_t intc:1;
-                uint64_t intd:1;
-                uint64_t waitl_com:1;
-                uint64_t reserved_21_63:43;
-#endif
         } s;
         struct cvmx_npei_ctl_port1_s cn52xx;
         struct cvmx_npei_ctl_port1_s cn52xxp1;
@@ -749,7 +458,6 @@ union cvmx_npei_ctl_port1 {
 union cvmx_npei_ctl_status {
         uint64_t u64;
         struct cvmx_npei_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t p1_ntags:6;
                 uint64_t p0_ntags:6;
@@ -760,22 +468,9 @@ union cvmx_npei_ctl_status {
                 uint64_t pkt_bp:4;
                 uint64_t host_mode:1;
                 uint64_t chip_rev:8;
-#else
-                uint64_t chip_rev:8;
-                uint64_t host_mode:1;
-                uint64_t pkt_bp:4;
-                uint64_t arb:1;
-                uint64_t lnk_rst:1;
-                uint64_t ring_en:1;
-                uint64_t cfg_rtry:16;
-                uint64_t p0_ntags:6;
-                uint64_t p1_ntags:6;
-                uint64_t reserved_44_63:20;
-#endif
         } s;
         struct cvmx_npei_ctl_status_s cn52xx;
         struct cvmx_npei_ctl_status_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t p1_ntags:6;
                 uint64_t p0_ntags:6;
@@ -786,43 +481,21 @@ union cvmx_npei_ctl_status {
                 uint64_t reserved_9_12:4;
                 uint64_t host_mode:1;
                 uint64_t chip_rev:8;
-#else
-                uint64_t chip_rev:8;
-                uint64_t host_mode:1;
-                uint64_t reserved_9_12:4;
-                uint64_t arb:1;
-                uint64_t lnk_rst:1;
-                uint64_t reserved_15_15:1;
-                uint64_t cfg_rtry:16;
-                uint64_t p0_ntags:6;
-                uint64_t p1_ntags:6;
-                uint64_t reserved_44_63:20;
-#endif
         } cn52xxp1;
         struct cvmx_npei_ctl_status_s cn56xx;
         struct cvmx_npei_ctl_status_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_15_63:49;
                 uint64_t lnk_rst:1;
                 uint64_t arb:1;
                 uint64_t pkt_bp:4;
                 uint64_t host_mode:1;
                 uint64_t chip_rev:8;
-#else
-                uint64_t chip_rev:8;
-                uint64_t host_mode:1;
-                uint64_t pkt_bp:4;
-                uint64_t arb:1;
-                uint64_t lnk_rst:1;
-                uint64_t reserved_15_63:49;
-#endif
         } cn56xxp1;
 };
 
 union cvmx_npei_ctl_status2 {
         uint64_t u64;
         struct cvmx_npei_ctl_status2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t mps:1;
                 uint64_t mrrs:3;
@@ -834,19 +507,6 @@ union cvmx_npei_ctl_status2 {
                 uint64_t c1_b0_d:1;
                 uint64_t c0_wi_d:1;
                 uint64_t c0_b0_d:1;
-#else
-                uint64_t c0_b0_d:1;
-                uint64_t c0_wi_d:1;
-                uint64_t c1_b0_d:1;
-                uint64_t c1_wi_d:1;
-                uint64_t c0_b1_s:3;
-                uint64_t c1_b1_s:3;
-                uint64_t c0_w_flt:1;
-                uint64_t c1_w_flt:1;
-                uint64_t mrrs:3;
-                uint64_t mps:1;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_npei_ctl_status2_s cn52xx;
         struct cvmx_npei_ctl_status2_s cn52xxp1;
@@ -857,19 +517,11 @@ union cvmx_npei_ctl_status2 {
 union cvmx_npei_data_out_cnt {
         uint64_t u64;
         struct cvmx_npei_data_out_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t p1_ucnt:16;
                 uint64_t p1_fcnt:6;
                 uint64_t p0_ucnt:16;
                 uint64_t p0_fcnt:6;
-#else
-                uint64_t p0_fcnt:6;
-                uint64_t p0_ucnt:16;
-                uint64_t p1_fcnt:6;
-                uint64_t p1_ucnt:16;
-                uint64_t reserved_44_63:20;
-#endif
         } s;
         struct cvmx_npei_data_out_cnt_s cn52xx;
         struct cvmx_npei_data_out_cnt_s cn52xxp1;
@@ -880,7 +532,6 @@ union cvmx_npei_data_out_cnt {
 union cvmx_npei_dbg_data {
         uint64_t u64;
         struct cvmx_npei_dbg_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t qlm0_rev_lanes:1;
                 uint64_t reserved_25_26:2;
@@ -888,18 +539,8 @@ union cvmx_npei_dbg_data {
                 uint64_t c_mul:5;
                 uint64_t dsel_ext:1;
                 uint64_t data:17;
-#else
-                uint64_t data:17;
-                uint64_t dsel_ext:1;
-                uint64_t c_mul:5;
-                uint64_t qlm1_spd:2;
-                uint64_t reserved_25_26:2;
-                uint64_t qlm0_rev_lanes:1;
-                uint64_t reserved_28_63:36;
-#endif
         } s;
         struct cvmx_npei_dbg_data_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t qlm0_link_width:1;
                 uint64_t qlm0_rev_lanes:1;
@@ -908,20 +549,9 @@ union cvmx_npei_dbg_data {
                 uint64_t c_mul:5;
                 uint64_t dsel_ext:1;
                 uint64_t data:17;
-#else
-                uint64_t data:17;
-                uint64_t dsel_ext:1;
-                uint64_t c_mul:5;
-                uint64_t qlm1_spd:2;
-                uint64_t qlm1_mode:2;
-                uint64_t qlm0_rev_lanes:1;
-                uint64_t qlm0_link_width:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn52xx;
         struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
         struct cvmx_npei_dbg_data_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t qlm2_rev_lanes:1;
                 uint64_t qlm0_rev_lanes:1;
@@ -930,16 +560,6 @@ union cvmx_npei_dbg_data {
                 uint64_t c_mul:5;
                 uint64_t dsel_ext:1;
                 uint64_t data:17;
-#else
-                uint64_t data:17;
-                uint64_t dsel_ext:1;
-                uint64_t c_mul:5;
-                uint64_t qlm1_spd:2;
-                uint64_t qlm3_spd:2;
-                uint64_t qlm0_rev_lanes:1;
-                uint64_t qlm2_rev_lanes:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn56xx;
         struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
 };
@@ -947,13 +567,8 @@ union cvmx_npei_dbg_data {
 union cvmx_npei_dbg_select {
         uint64_t u64;
         struct cvmx_npei_dbg_select_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t dbg_sel:16;
-#else
-                uint64_t dbg_sel:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_npei_dbg_select_s cn52xx;
         struct cvmx_npei_dbg_select_s cn52xxp1;
@@ -964,15 +579,9 @@ union cvmx_npei_dbg_select {
 union cvmx_npei_dmax_counts {
         uint64_t u64;
         struct cvmx_npei_dmax_counts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_39_63:25;
                 uint64_t fcnt:7;
                 uint64_t dbell:32;
-#else
-                uint64_t dbell:32;
-                uint64_t fcnt:7;
-                uint64_t reserved_39_63:25;
-#endif
         } s;
         struct cvmx_npei_dmax_counts_s cn52xx;
         struct cvmx_npei_dmax_counts_s cn52xxp1;
@@ -983,13 +592,8 @@ union cvmx_npei_dmax_counts {
 union cvmx_npei_dmax_dbell {
         uint32_t u32;
         struct cvmx_npei_dmax_dbell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_16_31:16;
                 uint32_t dbell:16;
-#else
-                uint32_t dbell:16;
-                uint32_t reserved_16_31:16;
-#endif
         } s;
         struct cvmx_npei_dmax_dbell_s cn52xx;
         struct cvmx_npei_dmax_dbell_s cn52xxp1;
@@ -1000,29 +604,16 @@ union cvmx_npei_dmax_dbell {
 union cvmx_npei_dmax_ibuff_saddr {
         uint64_t u64;
         struct cvmx_npei_dmax_ibuff_saddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_37_63:27;
                 uint64_t idle:1;
                 uint64_t saddr:29;
                 uint64_t reserved_0_6:7;
-#else
-                uint64_t reserved_0_6:7;
-                uint64_t saddr:29;
-                uint64_t idle:1;
-                uint64_t reserved_37_63:27;
-#endif
         } s;
         struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
         struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t saddr:29;
                 uint64_t reserved_0_6:7;
-#else
-                uint64_t reserved_0_6:7;
-                uint64_t saddr:29;
-                uint64_t reserved_36_63:28;
-#endif
         } cn52xxp1;
         struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
         struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
@@ -1031,13 +622,8 @@ union cvmx_npei_dmax_ibuff_saddr {
 union cvmx_npei_dmax_naddr {
         uint64_t u64;
         struct cvmx_npei_dmax_naddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t addr:36;
-#else
-                uint64_t addr:36;
-                uint64_t reserved_36_63:28;
-#endif
         } s;
         struct cvmx_npei_dmax_naddr_s cn52xx;
         struct cvmx_npei_dmax_naddr_s cn52xxp1;
@@ -1048,13 +634,8 @@ union cvmx_npei_dmax_naddr {
 union cvmx_npei_dma0_int_level {
         uint64_t u64;
         struct cvmx_npei_dma0_int_level_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t time:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t time:32;
-#endif
         } s;
         struct cvmx_npei_dma0_int_level_s cn52xx;
         struct cvmx_npei_dma0_int_level_s cn52xxp1;
@@ -1065,13 +646,8 @@ union cvmx_npei_dma0_int_level {
 union cvmx_npei_dma1_int_level {
         uint64_t u64;
         struct cvmx_npei_dma1_int_level_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t time:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t time:32;
-#endif
         } s;
         struct cvmx_npei_dma1_int_level_s cn52xx;
         struct cvmx_npei_dma1_int_level_s cn52xxp1;
@@ -1082,13 +658,8 @@ union cvmx_npei_dma1_int_level {
 union cvmx_npei_dma_cnts {
         uint64_t u64;
         struct cvmx_npei_dma_cnts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t dma1:32;
                 uint64_t dma0:32;
-#else
-                uint64_t dma0:32;
-                uint64_t dma1:32;
-#endif
         } s;
         struct cvmx_npei_dma_cnts_s cn52xx;
         struct cvmx_npei_dma_cnts_s cn52xxp1;
@@ -1099,7 +670,6 @@ union cvmx_npei_dma_cnts {
 union cvmx_npei_dma_control {
         uint64_t u64;
         struct cvmx_npei_dma_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t p_32b_m:1;
                 uint64_t dma4_enb:1;
@@ -1117,29 +687,9 @@ union cvmx_npei_dma_control {
                 uint64_t o_es:2;
                 uint64_t o_mode:1;
                 uint64_t csize:14;
-#else
-                uint64_t csize:14;
-                uint64_t o_mode:1;
-                uint64_t o_es:2;
-                uint64_t o_ns:1;
-                uint64_t o_ro:1;
-                uint64_t o_add1:1;
-                uint64_t fpa_que:3;
-                uint64_t dwb_ichk:9;
-                uint64_t dwb_denb:1;
-                uint64_t b0_lend:1;
-                uint64_t dma0_enb:1;
-                uint64_t dma1_enb:1;
-                uint64_t dma2_enb:1;
-                uint64_t dma3_enb:1;
-                uint64_t dma4_enb:1;
-                uint64_t p_32b_m:1;
-                uint64_t reserved_40_63:24;
-#endif
         } s;
         struct cvmx_npei_dma_control_s cn52xx;
         struct cvmx_npei_dma_control_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_38_63:26;
                 uint64_t dma3_enb:1;
                 uint64_t dma2_enb:1;
@@ -1155,27 +705,9 @@ union cvmx_npei_dma_control {
                 uint64_t o_es:2;
                 uint64_t o_mode:1;
                 uint64_t csize:14;
-#else
-                uint64_t csize:14;
-                uint64_t o_mode:1;
-                uint64_t o_es:2;
-                uint64_t o_ns:1;
-                uint64_t o_ro:1;
-                uint64_t o_add1:1;
-                uint64_t fpa_que:3;
-                uint64_t dwb_ichk:9;
-                uint64_t dwb_denb:1;
-                uint64_t b0_lend:1;
-                uint64_t dma0_enb:1;
-                uint64_t dma1_enb:1;
-                uint64_t dma2_enb:1;
-                uint64_t dma3_enb:1;
-                uint64_t reserved_38_63:26;
-#endif
         } cn52xxp1;
         struct cvmx_npei_dma_control_s cn56xx;
         struct cvmx_npei_dma_control_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_39_63:25;
                 uint64_t dma4_enb:1;
                 uint64_t dma3_enb:1;
@@ -1192,31 +724,12 @@ union cvmx_npei_dma_control {
                 uint64_t o_es:2;
                 uint64_t o_mode:1;
                 uint64_t csize:14;
-#else
-                uint64_t csize:14;
-                uint64_t o_mode:1;
-                uint64_t o_es:2;
-                uint64_t o_ns:1;
-                uint64_t o_ro:1;
-                uint64_t o_add1:1;
-                uint64_t fpa_que:3;
-                uint64_t dwb_ichk:9;
-                uint64_t dwb_denb:1;
-                uint64_t b0_lend:1;
-                uint64_t dma0_enb:1;
-                uint64_t dma1_enb:1;
-                uint64_t dma2_enb:1;
-                uint64_t dma3_enb:1;
-                uint64_t dma4_enb:1;
-                uint64_t reserved_39_63:25;
-#endif
         } cn56xxp1;
 };
 
 union cvmx_npei_dma_pcie_req_num {
         uint64_t u64;
         struct cvmx_npei_dma_pcie_req_num_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t dma_arb:1;
                 uint64_t reserved_53_62:10;
                 uint64_t pkt_cnt:5;
@@ -1232,23 +745,6 @@ union cvmx_npei_dma_pcie_req_num {
                 uint64_t dma0_cnt:5;
                 uint64_t reserved_5_7:3;
                 uint64_t dma_cnt:5;
-#else
-                uint64_t dma_cnt:5;
-                uint64_t reserved_5_7:3;
-                uint64_t dma0_cnt:5;
-                uint64_t reserved_13_15:3;
-                uint64_t dma1_cnt:5;
-                uint64_t reserved_21_23:3;
-                uint64_t dma2_cnt:5;
-                uint64_t reserved_29_31:3;
-                uint64_t dma3_cnt:5;
-                uint64_t reserved_37_39:3;
-                uint64_t dma4_cnt:5;
-                uint64_t reserved_45_47:3;
-                uint64_t pkt_cnt:5;
-                uint64_t reserved_53_62:10;
-                uint64_t dma_arb:1;
-#endif
         } s;
         struct cvmx_npei_dma_pcie_req_num_s cn52xx;
         struct cvmx_npei_dma_pcie_req_num_s cn56xx;
@@ -1257,21 +753,12 @@ union cvmx_npei_dma_pcie_req_num {
 union cvmx_npei_dma_state1 {
         uint64_t u64;
         struct cvmx_npei_dma_state1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t d4_dwe:8;
                 uint64_t d3_dwe:8;
                 uint64_t d2_dwe:8;
                 uint64_t d1_dwe:8;
                 uint64_t d0_dwe:8;
-#else
-                uint64_t d0_dwe:8;
-                uint64_t d1_dwe:8;
-                uint64_t d2_dwe:8;
-                uint64_t d3_dwe:8;
-                uint64_t d4_dwe:8;
-                uint64_t reserved_40_63:24;
-#endif
         } s;
         struct cvmx_npei_dma_state1_s cn52xx;
 };
@@ -1279,7 +766,6 @@ union cvmx_npei_dma_state1 {
 union cvmx_npei_dma_state1_p1 {
         uint64_t u64;
         struct cvmx_npei_dma_state1_p1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_60_63:4;
                 uint64_t d0_difst:7;
                 uint64_t d1_difst:7;
@@ -1291,22 +777,8 @@ union cvmx_npei_dma_state1_p1 {
                 uint64_t d2_reqst:5;
                 uint64_t d3_reqst:5;
                 uint64_t d4_reqst:5;
-#else
-                uint64_t d4_reqst:5;
-                uint64_t d3_reqst:5;
-                uint64_t d2_reqst:5;
-                uint64_t d1_reqst:5;
-                uint64_t d0_reqst:5;
-                uint64_t d4_difst:7;
-                uint64_t d3_difst:7;
-                uint64_t d2_difst:7;
-                uint64_t d1_difst:7;
-                uint64_t d0_difst:7;
-                uint64_t reserved_60_63:4;
-#endif
         } s;
         struct cvmx_npei_dma_state1_p1_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_60_63:4;
                 uint64_t d0_difst:7;
                 uint64_t d1_difst:7;
@@ -1318,19 +790,6 @@ union cvmx_npei_dma_state1_p1 {
                 uint64_t d2_reqst:5;
                 uint64_t d3_reqst:5;
                 uint64_t reserved_0_4:5;
-#else
-                uint64_t reserved_0_4:5;
-                uint64_t d3_reqst:5;
-                uint64_t d2_reqst:5;
-                uint64_t d1_reqst:5;
-                uint64_t d0_reqst:5;
-                uint64_t reserved_25_31:7;
-                uint64_t d3_difst:7;
-                uint64_t d2_difst:7;
-                uint64_t d1_difst:7;
-                uint64_t d0_difst:7;
-                uint64_t reserved_60_63:4;
-#endif
         } cn52xxp1;
         struct cvmx_npei_dma_state1_p1_s cn56xxp1;
 };
@@ -1338,21 +797,12 @@ union cvmx_npei_dma_state1_p1 {
 union cvmx_npei_dma_state2 {
         uint64_t u64;
         struct cvmx_npei_dma_state2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t ndwe:4;
                 uint64_t reserved_21_23:3;
                 uint64_t ndre:5;
                 uint64_t reserved_10_15:6;
                 uint64_t prd:10;
-#else
-                uint64_t prd:10;
-                uint64_t reserved_10_15:6;
-                uint64_t ndre:5;
-                uint64_t reserved_21_23:3;
-                uint64_t ndwe:4;
-                uint64_t reserved_28_63:36;
-#endif
         } s;
         struct cvmx_npei_dma_state2_s cn52xx;
 };
@@ -1360,38 +810,20 @@ union cvmx_npei_dma_state2 {
 union cvmx_npei_dma_state2_p1 {
         uint64_t u64;
         struct cvmx_npei_dma_state2_p1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_45_63:19;
                 uint64_t d0_dffst:9;
                 uint64_t d1_dffst:9;
                 uint64_t d2_dffst:9;
                 uint64_t d3_dffst:9;
                 uint64_t d4_dffst:9;
-#else
-                uint64_t d4_dffst:9;
-                uint64_t d3_dffst:9;
-                uint64_t d2_dffst:9;
-                uint64_t d1_dffst:9;
-                uint64_t d0_dffst:9;
-                uint64_t reserved_45_63:19;
-#endif
         } s;
         struct cvmx_npei_dma_state2_p1_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_45_63:19;
                 uint64_t d0_dffst:9;
                 uint64_t d1_dffst:9;
                 uint64_t d2_dffst:9;
                 uint64_t d3_dffst:9;
                 uint64_t reserved_0_8:9;
-#else
-                uint64_t reserved_0_8:9;
-                uint64_t d3_dffst:9;
-                uint64_t d2_dffst:9;
-                uint64_t d1_dffst:9;
-                uint64_t d0_dffst:9;
-                uint64_t reserved_45_63:19;
-#endif
         } cn52xxp1;
         struct cvmx_npei_dma_state2_p1_s cn56xxp1;
 };
@@ -1399,19 +831,11 @@ union cvmx_npei_dma_state2_p1 {
 union cvmx_npei_dma_state3_p1 {
         uint64_t u64;
         struct cvmx_npei_dma_state3_p1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_60_63:4;
                 uint64_t d0_drest:15;
                 uint64_t d1_drest:15;
                 uint64_t d2_drest:15;
                 uint64_t d3_drest:15;
-#else
-                uint64_t d3_drest:15;
-                uint64_t d2_drest:15;
-                uint64_t d1_drest:15;
-                uint64_t d0_drest:15;
-                uint64_t reserved_60_63:4;
-#endif
         } s;
         struct cvmx_npei_dma_state3_p1_s cn52xxp1;
         struct cvmx_npei_dma_state3_p1_s cn56xxp1;
@@ -1420,19 +844,11 @@ union cvmx_npei_dma_state3_p1 {
 union cvmx_npei_dma_state4_p1 {
         uint64_t u64;
         struct cvmx_npei_dma_state4_p1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_52_63:12;
                 uint64_t d0_dwest:13;
                 uint64_t d1_dwest:13;
                 uint64_t d2_dwest:13;
                 uint64_t d3_dwest:13;
-#else
-                uint64_t d3_dwest:13;
-                uint64_t d2_dwest:13;
-                uint64_t d1_dwest:13;
-                uint64_t d0_dwest:13;
-                uint64_t reserved_52_63:12;
-#endif
         } s;
         struct cvmx_npei_dma_state4_p1_s cn52xxp1;
         struct cvmx_npei_dma_state4_p1_s cn56xxp1;
@@ -1441,15 +857,9 @@ union cvmx_npei_dma_state4_p1 {
 union cvmx_npei_dma_state5_p1 {
         uint64_t u64;
         struct cvmx_npei_dma_state5_p1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t d4_drest:15;
                 uint64_t d4_dwest:13;
-#else
-                uint64_t d4_dwest:13;
-                uint64_t d4_drest:15;
-                uint64_t reserved_28_63:36;
-#endif
         } s;
         struct cvmx_npei_dma_state5_p1_s cn56xxp1;
 };
@@ -1457,7 +867,6 @@ union cvmx_npei_dma_state5_p1 {
 union cvmx_npei_int_a_enb {
         uint64_t u64;
         struct cvmx_npei_int_a_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t pout_err:1;
                 uint64_t pin_bp:1;
@@ -1469,31 +878,12 @@ union cvmx_npei_int_a_enb {
                 uint64_t pins_err:1;
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
-#else
-                uint64_t dma0_cpl:1;
-                uint64_t dma1_cpl:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t p0_rdlk:1;
-                uint64_t p1_rdlk:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_npei_int_a_enb_s cn52xx;
         struct cvmx_npei_int_a_enb_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
-#else
-                uint64_t dma0_cpl:1;
-                uint64_t dma1_cpl:1;
-                uint64_t reserved_2_63:62;
-#endif
         } cn52xxp1;
         struct cvmx_npei_int_a_enb_s cn56xx;
 };
@@ -1501,7 +891,6 @@ union cvmx_npei_int_a_enb {
 union cvmx_npei_int_a_enb2 {
         uint64_t u64;
         struct cvmx_npei_int_a_enb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t pout_err:1;
                 uint64_t pin_bp:1;
@@ -1513,31 +902,12 @@ union cvmx_npei_int_a_enb2 {
                 uint64_t pins_err:1;
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
-#else
-                uint64_t dma0_cpl:1;
-                uint64_t dma1_cpl:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t p0_rdlk:1;
-                uint64_t p1_rdlk:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_npei_int_a_enb2_s cn52xx;
         struct cvmx_npei_int_a_enb2_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
-#else
-                uint64_t dma0_cpl:1;
-                uint64_t dma1_cpl:1;
-                uint64_t reserved_2_63:62;
-#endif
         } cn52xxp1;
         struct cvmx_npei_int_a_enb2_s cn56xx;
 };
@@ -1545,7 +915,6 @@ union cvmx_npei_int_a_enb2 {
 union cvmx_npei_int_a_sum {
         uint64_t u64;
         struct cvmx_npei_int_a_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t pout_err:1;
                 uint64_t pin_bp:1;
@@ -1557,31 +926,12 @@ union cvmx_npei_int_a_sum {
                 uint64_t pins_err:1;
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
-#else
-                uint64_t dma0_cpl:1;
-                uint64_t dma1_cpl:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t p0_rdlk:1;
-                uint64_t p1_rdlk:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_npei_int_a_sum_s cn52xx;
         struct cvmx_npei_int_a_sum_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
-#else
-                uint64_t dma0_cpl:1;
-                uint64_t dma1_cpl:1;
-                uint64_t reserved_2_63:62;
-#endif
         } cn52xxp1;
         struct cvmx_npei_int_a_sum_s cn56xx;
 };
@@ -1589,7 +939,6 @@ union cvmx_npei_int_a_sum {
 union cvmx_npei_int_enb {
         uint64_t u64;
         struct cvmx_npei_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t mio_inta:1;
                 uint64_t reserved_62_62:1;
                 uint64_t int_a:1;
@@ -1654,76 +1003,9 @@ union cvmx_npei_int_enb {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t dma4dbo:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t c0_aeri:1;
-                uint64_t crs0_er:1;
-                uint64_t c0_se:1;
-                uint64_t crs0_dr:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t crs1_er:1;
-                uint64_t c1_se:1;
-                uint64_t crs1_dr:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t int_a:1;
-                uint64_t reserved_62_62:1;
-                uint64_t mio_inta:1;
-#endif
         } s;
         struct cvmx_npei_int_enb_s cn52xx;
         struct cvmx_npei_int_enb_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t mio_inta:1;
                 uint64_t reserved_62_62:1;
                 uint64_t int_a:1;
@@ -1788,76 +1070,9 @@ union cvmx_npei_int_enb {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t reserved_8_8:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t c0_aeri:1;
-                uint64_t crs0_er:1;
-                uint64_t c0_se:1;
-                uint64_t crs0_dr:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t crs1_er:1;
-                uint64_t c1_se:1;
-                uint64_t crs1_dr:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t int_a:1;
-                uint64_t reserved_62_62:1;
-                uint64_t mio_inta:1;
-#endif
         } cn52xxp1;
         struct cvmx_npei_int_enb_s cn56xx;
         struct cvmx_npei_int_enb_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t mio_inta:1;
                 uint64_t reserved_61_62:2;
                 uint64_t c1_ldwn:1;
@@ -1921,78 +1136,12 @@ union cvmx_npei_int_enb {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t dma4dbo:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t c0_aeri:1;
-                uint64_t reserved_20_20:1;
-                uint64_t c0_se:1;
-                uint64_t reserved_22_22:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t reserved_27_27:1;
-                uint64_t c1_se:1;
-                uint64_t reserved_29_29:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t reserved_61_62:2;
-                uint64_t mio_inta:1;
-#endif
         } cn56xxp1;
 };
 
 union cvmx_npei_int_enb2 {
         uint64_t u64;
         struct cvmx_npei_int_enb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t int_a:1;
                 uint64_t c1_ldwn:1;
@@ -2056,75 +1205,9 @@ union cvmx_npei_int_enb2 {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t dma4dbo:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t c0_aeri:1;
-                uint64_t crs0_er:1;
-                uint64_t c0_se:1;
-                uint64_t crs0_dr:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t crs1_er:1;
-                uint64_t c1_se:1;
-                uint64_t crs1_dr:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t int_a:1;
-                uint64_t reserved_62_63:2;
-#endif
         } s;
         struct cvmx_npei_int_enb2_s cn52xx;
         struct cvmx_npei_int_enb2_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t int_a:1;
                 uint64_t c1_ldwn:1;
@@ -2188,75 +1271,9 @@ union cvmx_npei_int_enb2 {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t reserved_8_8:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t c0_aeri:1;
-                uint64_t crs0_er:1;
-                uint64_t c0_se:1;
-                uint64_t crs0_dr:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t crs1_er:1;
-                uint64_t c1_se:1;
-                uint64_t crs1_dr:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t int_a:1;
-                uint64_t reserved_62_63:2;
-#endif
         } cn52xxp1;
         struct cvmx_npei_int_enb2_s cn56xx;
         struct cvmx_npei_int_enb2_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_61_63:3;
                 uint64_t c1_ldwn:1;
                 uint64_t c0_ldwn:1;
@@ -2319,85 +1336,15 @@ union cvmx_npei_int_enb2 {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t dma4dbo:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t c0_aeri:1;
-                uint64_t reserved_20_20:1;
-                uint64_t c0_se:1;
-                uint64_t reserved_22_22:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t reserved_27_27:1;
-                uint64_t c1_se:1;
-                uint64_t reserved_29_29:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t reserved_61_63:3;
-#endif
         } cn56xxp1;
 };
 
 union cvmx_npei_int_info {
         uint64_t u64;
         struct cvmx_npei_int_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t pidbof:6;
                 uint64_t psldbof:6;
-#else
-                uint64_t psldbof:6;
-                uint64_t pidbof:6;
-                uint64_t reserved_12_63:52;
-#endif
         } s;
         struct cvmx_npei_int_info_s cn52xx;
         struct cvmx_npei_int_info_s cn56xx;
@@ -2407,7 +1354,6 @@ union cvmx_npei_int_info {
 union cvmx_npei_int_sum {
         uint64_t u64;
         struct cvmx_npei_int_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t mio_inta:1;
                 uint64_t reserved_62_62:1;
                 uint64_t int_a:1;
@@ -2472,76 +1418,9 @@ union cvmx_npei_int_sum {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t dma4dbo:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t c0_aeri:1;
-                uint64_t crs0_er:1;
-                uint64_t c0_se:1;
-                uint64_t crs0_dr:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t crs1_er:1;
-                uint64_t c1_se:1;
-                uint64_t crs1_dr:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t int_a:1;
-                uint64_t reserved_62_62:1;
-                uint64_t mio_inta:1;
-#endif
         } s;
         struct cvmx_npei_int_sum_s cn52xx;
         struct cvmx_npei_int_sum_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t mio_inta:1;
                 uint64_t reserved_62_62:1;
                 uint64_t int_a:1;
@@ -2603,73 +1482,9 @@ union cvmx_npei_int_sum {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t reserved_8_8:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t reserved_15_18:4;
-                uint64_t c0_aeri:1;
-                uint64_t crs0_er:1;
-                uint64_t c0_se:1;
-                uint64_t crs0_dr:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t crs1_er:1;
-                uint64_t c1_se:1;
-                uint64_t crs1_dr:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t int_a:1;
-                uint64_t reserved_62_62:1;
-                uint64_t mio_inta:1;
-#endif
         } cn52xxp1;
         struct cvmx_npei_int_sum_s cn56xx;
         struct cvmx_npei_int_sum_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t mio_inta:1;
                 uint64_t reserved_61_62:2;
                 uint64_t c1_ldwn:1;
@@ -2730,75 +1545,12 @@ union cvmx_npei_int_sum {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t dma4dbo:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t reserved_15_18:4;
-                uint64_t c0_aeri:1;
-                uint64_t reserved_20_20:1;
-                uint64_t c0_se:1;
-                uint64_t reserved_22_22:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t reserved_27_27:1;
-                uint64_t c1_se:1;
-                uint64_t reserved_29_29:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t reserved_61_62:2;
-                uint64_t mio_inta:1;
-#endif
         } cn56xxp1;
 };
 
 union cvmx_npei_int_sum2 {
         uint64_t u64;
         struct cvmx_npei_int_sum2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t mio_inta:1;
                 uint64_t reserved_62_62:1;
                 uint64_t int_a:1;
@@ -2860,69 +1612,6 @@ union cvmx_npei_int_sum2 {
                 uint64_t bar0_to:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t dma0dbo:1;
-                uint64_t dma1dbo:1;
-                uint64_t dma2dbo:1;
-                uint64_t dma3dbo:1;
-                uint64_t reserved_8_8:1;
-                uint64_t dma0fi:1;
-                uint64_t dma1fi:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t reserved_15_18:4;
-                uint64_t c0_aeri:1;
-                uint64_t crs0_er:1;
-                uint64_t c0_se:1;
-                uint64_t crs0_dr:1;
-                uint64_t c0_wake:1;
-                uint64_t c0_pmei:1;
-                uint64_t c0_hpint:1;
-                uint64_t c1_aeri:1;
-                uint64_t crs1_er:1;
-                uint64_t c1_se:1;
-                uint64_t crs1_dr:1;
-                uint64_t c1_wake:1;
-                uint64_t c1_pmei:1;
-                uint64_t c1_hpint:1;
-                uint64_t c0_up_b0:1;
-                uint64_t c0_up_b1:1;
-                uint64_t c0_up_b2:1;
-                uint64_t c0_up_wi:1;
-                uint64_t c0_up_bx:1;
-                uint64_t c0_un_b0:1;
-                uint64_t c0_un_b1:1;
-                uint64_t c0_un_b2:1;
-                uint64_t c0_un_wi:1;
-                uint64_t c0_un_bx:1;
-                uint64_t c1_up_b0:1;
-                uint64_t c1_up_b1:1;
-                uint64_t c1_up_b2:1;
-                uint64_t c1_up_wi:1;
-                uint64_t c1_up_bx:1;
-                uint64_t c1_un_b0:1;
-                uint64_t c1_un_b1:1;
-                uint64_t c1_un_b2:1;
-                uint64_t c1_un_wi:1;
-                uint64_t c1_un_bx:1;
-                uint64_t c0_un_wf:1;
-                uint64_t c1_un_wf:1;
-                uint64_t c0_up_wf:1;
-                uint64_t c1_up_wf:1;
-                uint64_t c0_exc:1;
-                uint64_t c1_exc:1;
-                uint64_t c0_ldwn:1;
-                uint64_t c1_ldwn:1;
-                uint64_t int_a:1;
-                uint64_t reserved_62_62:1;
-                uint64_t mio_inta:1;
-#endif
         } s;
         struct cvmx_npei_int_sum2_s cn52xx;
         struct cvmx_npei_int_sum2_s cn52xxp1;
@@ -2932,11 +1621,7 @@ union cvmx_npei_int_sum2 {
 union cvmx_npei_last_win_rdata0 {
         uint64_t u64;
         struct cvmx_npei_last_win_rdata0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
         } s;
         struct cvmx_npei_last_win_rdata0_s cn52xx;
         struct cvmx_npei_last_win_rdata0_s cn52xxp1;
@@ -2947,11 +1632,7 @@ union cvmx_npei_last_win_rdata0 {
 union cvmx_npei_last_win_rdata1 {
         uint64_t u64;
         struct cvmx_npei_last_win_rdata1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
                 uint64_t data:64;
-#endif
         } s;
         struct cvmx_npei_last_win_rdata1_s cn52xx;
         struct cvmx_npei_last_win_rdata1_s cn52xxp1;
@@ -2962,15 +1643,9 @@ union cvmx_npei_last_win_rdata1 {
 union cvmx_npei_mem_access_ctl {
         uint64_t u64;
         struct cvmx_npei_mem_access_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t max_word:4;
                 uint64_t timer:10;
-#else
-                uint64_t timer:10;
-                uint64_t max_word:4;
-                uint64_t reserved_14_63:50;
-#endif
         } s;
         struct cvmx_npei_mem_access_ctl_s cn52xx;
         struct cvmx_npei_mem_access_ctl_s cn52xxp1;
@@ -2981,7 +1656,6 @@ union cvmx_npei_mem_access_ctl {
 union cvmx_npei_mem_access_subidx {
         uint64_t u64;
         struct cvmx_npei_mem_access_subidx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_42_63:22;
                 uint64_t zero:1;
                 uint64_t port:2;
@@ -2993,19 +1667,6 @@ union cvmx_npei_mem_access_subidx {
                 uint64_t ror:1;
                 uint64_t row:1;
                 uint64_t ba:30;
-#else
-                uint64_t ba:30;
-                uint64_t row:1;
-                uint64_t ror:1;
-                uint64_t nsw:1;
-                uint64_t nsr:1;
-                uint64_t esw:2;
-                uint64_t esr:2;
-                uint64_t nmerge:1;
-                uint64_t port:2;
-                uint64_t zero:1;
-                uint64_t reserved_42_63:22;
-#endif
         } s;
         struct cvmx_npei_mem_access_subidx_s cn52xx;
         struct cvmx_npei_mem_access_subidx_s cn52xxp1;
@@ -3016,11 +1677,7 @@ union cvmx_npei_mem_access_subidx {
 union cvmx_npei_msi_enb0 {
         uint64_t u64;
         struct cvmx_npei_msi_enb0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t enb:64;
-#else
-                uint64_t enb:64;
-#endif
         } s;
         struct cvmx_npei_msi_enb0_s cn52xx;
         struct cvmx_npei_msi_enb0_s cn52xxp1;
@@ -3031,11 +1688,7 @@ union cvmx_npei_msi_enb0 {
 union cvmx_npei_msi_enb1 {
         uint64_t u64;
         struct cvmx_npei_msi_enb1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t enb:64;
-#else
                 uint64_t enb:64;
-#endif
         } s;
         struct cvmx_npei_msi_enb1_s cn52xx;
         struct cvmx_npei_msi_enb1_s cn52xxp1;
@@ -3046,11 +1699,7 @@ union cvmx_npei_msi_enb1 {
 union cvmx_npei_msi_enb2 {
         uint64_t u64;
         struct cvmx_npei_msi_enb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t enb:64;
-#else
                 uint64_t enb:64;
-#endif
         } s;
         struct cvmx_npei_msi_enb2_s cn52xx;
         struct cvmx_npei_msi_enb2_s cn52xxp1;
@@ -3061,11 +1710,7 @@ union cvmx_npei_msi_enb2 {
 union cvmx_npei_msi_enb3 {
         uint64_t u64;
         struct cvmx_npei_msi_enb3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t enb:64;
-#else
-                uint64_t enb:64;
-#endif
         } s;
         struct cvmx_npei_msi_enb3_s cn52xx;
         struct cvmx_npei_msi_enb3_s cn52xxp1;
@@ -3076,11 +1721,7 @@ union cvmx_npei_msi_enb3 {
 union cvmx_npei_msi_rcv0 {
         uint64_t u64;
         struct cvmx_npei_msi_rcv0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t intr:64;
-#else
-                uint64_t intr:64;
-#endif
         } s;
         struct cvmx_npei_msi_rcv0_s cn52xx;
         struct cvmx_npei_msi_rcv0_s cn52xxp1;
@@ -3091,11 +1732,7 @@ union cvmx_npei_msi_rcv0 {
 union cvmx_npei_msi_rcv1 {
         uint64_t u64;
         struct cvmx_npei_msi_rcv1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t intr:64;
-#else
                 uint64_t intr:64;
-#endif
         } s;
         struct cvmx_npei_msi_rcv1_s cn52xx;
         struct cvmx_npei_msi_rcv1_s cn52xxp1;
@@ -3106,11 +1743,7 @@ union cvmx_npei_msi_rcv1 {
 union cvmx_npei_msi_rcv2 {
         uint64_t u64;
         struct cvmx_npei_msi_rcv2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t intr:64;
-#else
                 uint64_t intr:64;
-#endif
         } s;
         struct cvmx_npei_msi_rcv2_s cn52xx;
         struct cvmx_npei_msi_rcv2_s cn52xxp1;
@@ -3121,11 +1754,7 @@ union cvmx_npei_msi_rcv2 {
 union cvmx_npei_msi_rcv3 {
         uint64_t u64;
         struct cvmx_npei_msi_rcv3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t intr:64;
-#else
-                uint64_t intr:64;
-#endif
         } s;
         struct cvmx_npei_msi_rcv3_s cn52xx;
         struct cvmx_npei_msi_rcv3_s cn52xxp1;
@@ -3136,15 +1765,9 @@ union cvmx_npei_msi_rcv3 {
 union cvmx_npei_msi_rd_map {
         uint64_t u64;
         struct cvmx_npei_msi_rd_map_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t rd_int:8;
                 uint64_t msi_int:8;
-#else
-                uint64_t msi_int:8;
-                uint64_t rd_int:8;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_npei_msi_rd_map_s cn52xx;
         struct cvmx_npei_msi_rd_map_s cn52xxp1;
@@ -3155,11 +1778,7 @@ union cvmx_npei_msi_rd_map {
 union cvmx_npei_msi_w1c_enb0 {
         uint64_t u64;
         struct cvmx_npei_msi_w1c_enb0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t clr:64;
-#else
-                uint64_t clr:64;
-#endif
         } s;
         struct cvmx_npei_msi_w1c_enb0_s cn52xx;
         struct cvmx_npei_msi_w1c_enb0_s cn56xx;
@@ -3168,11 +1787,7 @@ union cvmx_npei_msi_w1c_enb0 {
 union cvmx_npei_msi_w1c_enb1 {
         uint64_t u64;
         struct cvmx_npei_msi_w1c_enb1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t clr:64;
-#else
                 uint64_t clr:64;
-#endif
         } s;
         struct cvmx_npei_msi_w1c_enb1_s cn52xx;
         struct cvmx_npei_msi_w1c_enb1_s cn56xx;
@@ -3181,11 +1796,7 @@ union cvmx_npei_msi_w1c_enb1 {
 union cvmx_npei_msi_w1c_enb2 {
         uint64_t u64;
         struct cvmx_npei_msi_w1c_enb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t clr:64;
-#else
                 uint64_t clr:64;
-#endif
         } s;
         struct cvmx_npei_msi_w1c_enb2_s cn52xx;
         struct cvmx_npei_msi_w1c_enb2_s cn56xx;
@@ -3194,11 +1805,7 @@ union cvmx_npei_msi_w1c_enb2 {
 union cvmx_npei_msi_w1c_enb3 {
         uint64_t u64;
         struct cvmx_npei_msi_w1c_enb3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t clr:64;
-#else
-                uint64_t clr:64;
-#endif
         } s;
         struct cvmx_npei_msi_w1c_enb3_s cn52xx;
         struct cvmx_npei_msi_w1c_enb3_s cn56xx;
@@ -3207,11 +1814,7 @@ union cvmx_npei_msi_w1c_enb3 {
 union cvmx_npei_msi_w1s_enb0 {
         uint64_t u64;
         struct cvmx_npei_msi_w1s_enb0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t set:64;
-#else
                 uint64_t set:64;
-#endif
         } s;
         struct cvmx_npei_msi_w1s_enb0_s cn52xx;
         struct cvmx_npei_msi_w1s_enb0_s cn56xx;
@@ -3220,11 +1823,7 @@ union cvmx_npei_msi_w1s_enb0 {
 union cvmx_npei_msi_w1s_enb1 {
         uint64_t u64;
         struct cvmx_npei_msi_w1s_enb1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t set:64;
-#else
                 uint64_t set:64;
-#endif
         } s;
         struct cvmx_npei_msi_w1s_enb1_s cn52xx;
         struct cvmx_npei_msi_w1s_enb1_s cn56xx;
@@ -3233,11 +1832,7 @@ union cvmx_npei_msi_w1s_enb1 {
 union cvmx_npei_msi_w1s_enb2 {
         uint64_t u64;
         struct cvmx_npei_msi_w1s_enb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t set:64;
-#else
                 uint64_t set:64;
-#endif
         } s;
         struct cvmx_npei_msi_w1s_enb2_s cn52xx;
         struct cvmx_npei_msi_w1s_enb2_s cn56xx;
@@ -3246,11 +1841,7 @@ union cvmx_npei_msi_w1s_enb2 {
 union cvmx_npei_msi_w1s_enb3 {
         uint64_t u64;
         struct cvmx_npei_msi_w1s_enb3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t set:64;
-#else
-                uint64_t set:64;
-#endif
         } s;
         struct cvmx_npei_msi_w1s_enb3_s cn52xx;
         struct cvmx_npei_msi_w1s_enb3_s cn56xx;
@@ -3259,15 +1850,9 @@ union cvmx_npei_msi_w1s_enb3 {
 union cvmx_npei_msi_wr_map {
         uint64_t u64;
         struct cvmx_npei_msi_wr_map_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t ciu_int:8;
                 uint64_t msi_int:8;
-#else
-                uint64_t msi_int:8;
-                uint64_t ciu_int:8;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_npei_msi_wr_map_s cn52xx;
         struct cvmx_npei_msi_wr_map_s cn52xxp1;
@@ -3278,7 +1863,6 @@ union cvmx_npei_msi_wr_map {
 union cvmx_npei_pcie_credit_cnt {
         uint64_t u64;
         struct cvmx_npei_pcie_credit_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t p1_ccnt:8;
                 uint64_t p1_ncnt:8;
@@ -3286,15 +1870,6 @@ union cvmx_npei_pcie_credit_cnt {
                 uint64_t p0_ccnt:8;
                 uint64_t p0_ncnt:8;
                 uint64_t p0_pcnt:8;
-#else
-                uint64_t p0_pcnt:8;
-                uint64_t p0_ncnt:8;
-                uint64_t p0_ccnt:8;
-                uint64_t p1_pcnt:8;
-                uint64_t p1_ncnt:8;
-                uint64_t p1_ccnt:8;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_npei_pcie_credit_cnt_s cn52xx;
         struct cvmx_npei_pcie_credit_cnt_s cn56xx;
@@ -3303,13 +1878,8 @@ union cvmx_npei_pcie_credit_cnt {
 union cvmx_npei_pcie_msi_rcv {
         uint64_t u64;
         struct cvmx_npei_pcie_msi_rcv_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t intr:8;
-#else
-                uint64_t intr:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_npei_pcie_msi_rcv_s cn52xx;
         struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
@@ -3320,15 +1890,9 @@ union cvmx_npei_pcie_msi_rcv {
 union cvmx_npei_pcie_msi_rcv_b1 {
         uint64_t u64;
         struct cvmx_npei_pcie_msi_rcv_b1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t intr:8;
                 uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t intr:8;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
         struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
@@ -3339,15 +1903,9 @@ union cvmx_npei_pcie_msi_rcv_b1 {
 union cvmx_npei_pcie_msi_rcv_b2 {
         uint64_t u64;
         struct cvmx_npei_pcie_msi_rcv_b2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_24_63:40;
                 uint64_t intr:8;
                 uint64_t reserved_0_15:16;
-#else
-                uint64_t reserved_0_15:16;
-                uint64_t intr:8;
-                uint64_t reserved_24_63:40;
-#endif
         } s;
         struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
         struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
@@ -3358,15 +1916,9 @@ union cvmx_npei_pcie_msi_rcv_b2 {
 union cvmx_npei_pcie_msi_rcv_b3 {
         uint64_t u64;
         struct cvmx_npei_pcie_msi_rcv_b3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t intr:8;
                 uint64_t reserved_0_23:24;
-#else
-                uint64_t reserved_0_23:24;
-                uint64_t intr:8;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
         struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
@@ -3377,15 +1929,9 @@ union cvmx_npei_pcie_msi_rcv_b3 {
 union cvmx_npei_pktx_cnts {
         uint64_t u64;
         struct cvmx_npei_pktx_cnts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_54_63:10;
                 uint64_t timer:22;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t timer:22;
-                uint64_t reserved_54_63:10;
-#endif
         } s;
         struct cvmx_npei_pktx_cnts_s cn52xx;
         struct cvmx_npei_pktx_cnts_s cn56xx;
@@ -3394,13 +1940,8 @@ union cvmx_npei_pktx_cnts {
 union cvmx_npei_pktx_in_bp {
         uint64_t u64;
         struct cvmx_npei_pktx_in_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t wmark:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t wmark:32;
-#endif
         } s;
         struct cvmx_npei_pktx_in_bp_s cn52xx;
         struct cvmx_npei_pktx_in_bp_s cn56xx;
@@ -3409,13 +1950,8 @@ union cvmx_npei_pktx_in_bp {
 union cvmx_npei_pktx_instr_baddr {
         uint64_t u64;
         struct cvmx_npei_pktx_instr_baddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t addr:61;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t addr:61;
-#endif
         } s;
         struct cvmx_npei_pktx_instr_baddr_s cn52xx;
         struct cvmx_npei_pktx_instr_baddr_s cn56xx;
@@ -3424,13 +1960,8 @@ union cvmx_npei_pktx_instr_baddr {
 union cvmx_npei_pktx_instr_baoff_dbell {
         uint64_t u64;
         struct cvmx_npei_pktx_instr_baoff_dbell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t aoff:32;
                 uint64_t dbell:32;
-#else
-                uint64_t dbell:32;
-                uint64_t aoff:32;
-#endif
         } s;
         struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
         struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
@@ -3439,19 +1970,11 @@ union cvmx_npei_pktx_instr_baoff_dbell {
 union cvmx_npei_pktx_instr_fifo_rsize {
         uint64_t u64;
         struct cvmx_npei_pktx_instr_fifo_rsize_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t max:9;
                 uint64_t rrp:9;
                 uint64_t wrp:9;
                 uint64_t fcnt:5;
                 uint64_t rsize:32;
-#else
-                uint64_t rsize:32;
-                uint64_t fcnt:5;
-                uint64_t wrp:9;
-                uint64_t rrp:9;
-                uint64_t max:9;
-#endif
         } s;
         struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
         struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
@@ -3460,7 +1983,6 @@ union cvmx_npei_pktx_instr_fifo_rsize {
 union cvmx_npei_pktx_instr_header {
         uint64_t u64;
         struct cvmx_npei_pktx_instr_header_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t pbp:1;
                 uint64_t reserved_38_42:5;
@@ -3474,21 +1996,6 @@ union cvmx_npei_pktx_instr_header {
                 uint64_t reserved_13_13:1;
                 uint64_t skp_len:7;
                 uint64_t reserved_0_5:6;
-#else
-                uint64_t reserved_0_5:6;
-                uint64_t skp_len:7;
-                uint64_t reserved_13_13:1;
-                uint64_t par_mode:2;
-                uint64_t reserved_16_20:5;
-                uint64_t use_ihdr:1;
-                uint64_t reserved_22_27:6;
-                uint64_t rskp_len:7;
-                uint64_t reserved_35_35:1;
-                uint64_t rparmode:2;
-                uint64_t reserved_38_42:5;
-                uint64_t pbp:1;
-                uint64_t reserved_44_63:20;
-#endif
         } s;
         struct cvmx_npei_pktx_instr_header_s cn52xx;
         struct cvmx_npei_pktx_instr_header_s cn56xx;
@@ -3497,13 +2004,8 @@ union cvmx_npei_pktx_instr_header {
 union cvmx_npei_pktx_slist_baddr {
         uint64_t u64;
         struct cvmx_npei_pktx_slist_baddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t addr:60;
                 uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t addr:60;
-#endif
         } s;
         struct cvmx_npei_pktx_slist_baddr_s cn52xx;
         struct cvmx_npei_pktx_slist_baddr_s cn56xx;
@@ -3512,13 +2014,8 @@ union cvmx_npei_pktx_slist_baddr {
 union cvmx_npei_pktx_slist_baoff_dbell {
         uint64_t u64;
         struct cvmx_npei_pktx_slist_baoff_dbell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t aoff:32;
                 uint64_t dbell:32;
-#else
-                uint64_t dbell:32;
-                uint64_t aoff:32;
-#endif
         } s;
         struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
         struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
@@ -3527,13 +2024,8 @@ union cvmx_npei_pktx_slist_baoff_dbell {
 union cvmx_npei_pktx_slist_fifo_rsize {
         uint64_t u64;
         struct cvmx_npei_pktx_slist_fifo_rsize_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t rsize:32;
-#else
-                uint64_t rsize:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
         struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
@@ -3542,13 +2034,8 @@ union cvmx_npei_pktx_slist_fifo_rsize {
 union cvmx_npei_pkt_cnt_int {
         uint64_t u64;
         struct cvmx_npei_pkt_cnt_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t port:32;
-#else
-                uint64_t port:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_cnt_int_s cn52xx;
         struct cvmx_npei_pkt_cnt_int_s cn56xx;
@@ -3557,13 +2044,8 @@ union cvmx_npei_pkt_cnt_int {
 union cvmx_npei_pkt_cnt_int_enb {
         uint64_t u64;
         struct cvmx_npei_pkt_cnt_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t port:32;
-#else
-                uint64_t port:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
         struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
@@ -3572,11 +2054,7 @@ union cvmx_npei_pkt_cnt_int_enb {
 union cvmx_npei_pkt_data_out_es {
         uint64_t u64;
         struct cvmx_npei_pkt_data_out_es_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t es:64;
-#else
                 uint64_t es:64;
-#endif
         } s;
         struct cvmx_npei_pkt_data_out_es_s cn52xx;
         struct cvmx_npei_pkt_data_out_es_s cn56xx;
@@ -3585,13 +2063,8 @@ union cvmx_npei_pkt_data_out_es {
 union cvmx_npei_pkt_data_out_ns {
         uint64_t u64;
         struct cvmx_npei_pkt_data_out_ns_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t nsr:32;
-#else
-                uint64_t nsr:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_data_out_ns_s cn52xx;
         struct cvmx_npei_pkt_data_out_ns_s cn56xx;
@@ -3600,13 +2073,8 @@ union cvmx_npei_pkt_data_out_ns {
 union cvmx_npei_pkt_data_out_ror {
         uint64_t u64;
         struct cvmx_npei_pkt_data_out_ror_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t ror:32;
-#else
-                uint64_t ror:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_data_out_ror_s cn52xx;
         struct cvmx_npei_pkt_data_out_ror_s cn56xx;
@@ -3615,13 +2083,8 @@ union cvmx_npei_pkt_data_out_ror {
 union cvmx_npei_pkt_dpaddr {
         uint64_t u64;
         struct cvmx_npei_pkt_dpaddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t dptr:32;
-#else
-                uint64_t dptr:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_dpaddr_s cn52xx;
         struct cvmx_npei_pkt_dpaddr_s cn56xx;
@@ -3630,13 +2093,8 @@ union cvmx_npei_pkt_dpaddr {
 union cvmx_npei_pkt_in_bp {
         uint64_t u64;
         struct cvmx_npei_pkt_in_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t bp:32;
-#else
-                uint64_t bp:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_in_bp_s cn52xx;
         struct cvmx_npei_pkt_in_bp_s cn56xx;
@@ -3645,13 +2103,8 @@ union cvmx_npei_pkt_in_bp {
 union cvmx_npei_pkt_in_donex_cnts {
         uint64_t u64;
         struct cvmx_npei_pkt_in_donex_cnts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
         struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
@@ -3660,13 +2113,8 @@ union cvmx_npei_pkt_in_donex_cnts {
 union cvmx_npei_pkt_in_instr_counts {
         uint64_t u64;
         struct cvmx_npei_pkt_in_instr_counts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t wr_cnt:32;
                 uint64_t rd_cnt:32;
-#else
-                uint64_t rd_cnt:32;
-                uint64_t wr_cnt:32;
-#endif
         } s;
         struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
         struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
@@ -3675,11 +2123,7 @@ union cvmx_npei_pkt_in_instr_counts {
 union cvmx_npei_pkt_in_pcie_port {
         uint64_t u64;
         struct cvmx_npei_pkt_in_pcie_port_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t pp:64;
-#else
                 uint64_t pp:64;
-#endif
         } s;
         struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
         struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
@@ -3688,7 +2132,6 @@ union cvmx_npei_pkt_in_pcie_port {
 union cvmx_npei_pkt_input_control {
         uint64_t u64;
         struct cvmx_npei_pkt_input_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_23_63:41;
                 uint64_t pkt_rr:1;
                 uint64_t pbp_dhi:13;
@@ -3699,18 +2142,6 @@ union cvmx_npei_pkt_input_control {
                 uint64_t nsr:1;
                 uint64_t esr:2;
                 uint64_t ror:1;
-#else
-                uint64_t ror:1;
-                uint64_t esr:2;
-                uint64_t nsr:1;
-                uint64_t use_csr:1;
-                uint64_t d_ror:1;
-                uint64_t d_esr:2;
-                uint64_t d_nsr:1;
-                uint64_t pbp_dhi:13;
-                uint64_t pkt_rr:1;
-                uint64_t reserved_23_63:41;
-#endif
         } s;
         struct cvmx_npei_pkt_input_control_s cn52xx;
         struct cvmx_npei_pkt_input_control_s cn56xx;
@@ -3719,13 +2150,8 @@ union cvmx_npei_pkt_input_control {
 union cvmx_npei_pkt_instr_enb {
         uint64_t u64;
         struct cvmx_npei_pkt_instr_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t enb:32;
-#else
-                uint64_t enb:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_instr_enb_s cn52xx;
         struct cvmx_npei_pkt_instr_enb_s cn56xx;
@@ -3734,11 +2160,7 @@ union cvmx_npei_pkt_instr_enb {
 union cvmx_npei_pkt_instr_rd_size {
         uint64_t u64;
         struct cvmx_npei_pkt_instr_rd_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t rdsize:64;
-#else
-                uint64_t rdsize:64;
-#endif
         } s;
         struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
         struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
@@ -3747,13 +2169,8 @@ union cvmx_npei_pkt_instr_rd_size {
 union cvmx_npei_pkt_instr_size {
         uint64_t u64;
         struct cvmx_npei_pkt_instr_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t is_64b:32;
-#else
-                uint64_t is_64b:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_instr_size_s cn52xx;
         struct cvmx_npei_pkt_instr_size_s cn56xx;
@@ -3762,15 +2179,9 @@ union cvmx_npei_pkt_instr_size {
 union cvmx_npei_pkt_int_levels {
         uint64_t u64;
         struct cvmx_npei_pkt_int_levels_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_54_63:10;
                 uint64_t time:22;
                 uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t time:22;
-                uint64_t reserved_54_63:10;
-#endif
         } s;
         struct cvmx_npei_pkt_int_levels_s cn52xx;
         struct cvmx_npei_pkt_int_levels_s cn56xx;
@@ -3779,13 +2190,8 @@ union cvmx_npei_pkt_int_levels {
 union cvmx_npei_pkt_iptr {
         uint64_t u64;
         struct cvmx_npei_pkt_iptr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t iptr:32;
-#else
-                uint64_t iptr:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_iptr_s cn52xx;
         struct cvmx_npei_pkt_iptr_s cn56xx;
@@ -3794,13 +2200,8 @@ union cvmx_npei_pkt_iptr {
 union cvmx_npei_pkt_out_bmode {
         uint64_t u64;
         struct cvmx_npei_pkt_out_bmode_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t bmode:32;
-#else
-                uint64_t bmode:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_out_bmode_s cn52xx;
         struct cvmx_npei_pkt_out_bmode_s cn56xx;
@@ -3809,13 +2210,8 @@ union cvmx_npei_pkt_out_bmode {
 union cvmx_npei_pkt_out_enb {
         uint64_t u64;
         struct cvmx_npei_pkt_out_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t enb:32;
-#else
-                uint64_t enb:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_out_enb_s cn52xx;
         struct cvmx_npei_pkt_out_enb_s cn56xx;
@@ -3824,13 +2220,8 @@ union cvmx_npei_pkt_out_enb {
 union cvmx_npei_pkt_output_wmark {
         uint64_t u64;
         struct cvmx_npei_pkt_output_wmark_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t wmark:32;
-#else
-                uint64_t wmark:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_output_wmark_s cn52xx;
         struct cvmx_npei_pkt_output_wmark_s cn56xx;
@@ -3839,11 +2230,7 @@ union cvmx_npei_pkt_output_wmark {
 union cvmx_npei_pkt_pcie_port {
         uint64_t u64;
         struct cvmx_npei_pkt_pcie_port_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t pp:64;
-#else
-                uint64_t pp:64;
-#endif
         } s;
         struct cvmx_npei_pkt_pcie_port_s cn52xx;
         struct cvmx_npei_pkt_pcie_port_s cn56xx;
@@ -3852,13 +2239,8 @@ union cvmx_npei_pkt_pcie_port {
 union cvmx_npei_pkt_port_in_rst {
         uint64_t u64;
         struct cvmx_npei_pkt_port_in_rst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t in_rst:32;
                 uint64_t out_rst:32;
-#else
-                uint64_t out_rst:32;
-                uint64_t in_rst:32;
-#endif
         } s;
         struct cvmx_npei_pkt_port_in_rst_s cn52xx;
         struct cvmx_npei_pkt_port_in_rst_s cn56xx;
@@ -3867,11 +2249,7 @@ union cvmx_npei_pkt_port_in_rst {
 union cvmx_npei_pkt_slist_es {
         uint64_t u64;
         struct cvmx_npei_pkt_slist_es_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t es:64;
-#else
-                uint64_t es:64;
-#endif
         } s;
         struct cvmx_npei_pkt_slist_es_s cn52xx;
         struct cvmx_npei_pkt_slist_es_s cn56xx;
@@ -3880,15 +2258,9 @@ union cvmx_npei_pkt_slist_es {
 union cvmx_npei_pkt_slist_id_size {
         uint64_t u64;
         struct cvmx_npei_pkt_slist_id_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_23_63:41;
                 uint64_t isize:7;
                 uint64_t bsize:16;
-#else
-                uint64_t bsize:16;
-                uint64_t isize:7;
-                uint64_t reserved_23_63:41;
-#endif
         } s;
         struct cvmx_npei_pkt_slist_id_size_s cn52xx;
         struct cvmx_npei_pkt_slist_id_size_s cn56xx;
@@ -3897,13 +2269,8 @@ union cvmx_npei_pkt_slist_id_size {
 union cvmx_npei_pkt_slist_ns {
         uint64_t u64;
         struct cvmx_npei_pkt_slist_ns_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t nsr:32;
-#else
-                uint64_t nsr:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_slist_ns_s cn52xx;
         struct cvmx_npei_pkt_slist_ns_s cn56xx;
@@ -3912,13 +2279,8 @@ union cvmx_npei_pkt_slist_ns {
 union cvmx_npei_pkt_slist_ror {
         uint64_t u64;
         struct cvmx_npei_pkt_slist_ror_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t ror:32;
-#else
-                uint64_t ror:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_slist_ror_s cn52xx;
         struct cvmx_npei_pkt_slist_ror_s cn56xx;
@@ -3927,13 +2289,8 @@ union cvmx_npei_pkt_slist_ror {
 union cvmx_npei_pkt_time_int {
         uint64_t u64;
         struct cvmx_npei_pkt_time_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t port:32;
-#else
-                uint64_t port:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_time_int_s cn52xx;
         struct cvmx_npei_pkt_time_int_s cn56xx;
@@ -3942,13 +2299,8 @@ union cvmx_npei_pkt_time_int {
 union cvmx_npei_pkt_time_int_enb {
         uint64_t u64;
         struct cvmx_npei_pkt_time_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t port:32;
-#else
-                uint64_t port:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_pkt_time_int_enb_s cn52xx;
         struct cvmx_npei_pkt_time_int_enb_s cn56xx;
@@ -3957,7 +2309,6 @@ union cvmx_npei_pkt_time_int_enb {
 union cvmx_npei_rsl_int_blocks {
         uint64_t u64;
         struct cvmx_npei_rsl_int_blocks_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_31_63:33;
                 uint64_t iob:1;
                 uint64_t lmc1:1;
@@ -3987,37 +2338,6 @@ union cvmx_npei_rsl_int_blocks {
                 uint64_t gmx1:1;
                 uint64_t gmx0:1;
                 uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t gmx1:1;
-                uint64_t npei:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t dfa:1;
-                uint64_t zip:1;
-                uint64_t reserved_8_8:1;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t usb:1;
-                uint64_t rad:1;
-                uint64_t usb1:1;
-                uint64_t l2c:1;
-                uint64_t lmc0:1;
-                uint64_t spx0:1;
-                uint64_t spx1:1;
-                uint64_t pip:1;
-                uint64_t reserved_21_21:1;
-                uint64_t asxpcs0:1;
-                uint64_t asxpcs1:1;
-                uint64_t reserved_24_27:4;
-                uint64_t agl:1;
-                uint64_t lmc1:1;
-                uint64_t iob:1;
-                uint64_t reserved_31_63:33;
-#endif
         } s;
         struct cvmx_npei_rsl_int_blocks_s cn52xx;
         struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
@@ -4028,11 +2348,7 @@ union cvmx_npei_rsl_int_blocks {
 union cvmx_npei_scratch_1 {
         uint64_t u64;
         struct cvmx_npei_scratch_1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
                 uint64_t data:64;
-#endif
         } s;
         struct cvmx_npei_scratch_1_s cn52xx;
         struct cvmx_npei_scratch_1_s cn52xxp1;
@@ -4043,17 +2359,10 @@ union cvmx_npei_scratch_1 {
 union cvmx_npei_state1 {
         uint64_t u64;
         struct cvmx_npei_state1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t cpl1:12;
                 uint64_t cpl0:12;
                 uint64_t arb:1;
                 uint64_t csr:39;
-#else
-                uint64_t csr:39;
-                uint64_t arb:1;
-                uint64_t cpl0:12;
-                uint64_t cpl1:12;
-#endif
         } s;
         struct cvmx_npei_state1_s cn52xx;
         struct cvmx_npei_state1_s cn52xxp1;
@@ -4064,7 +2373,6 @@ union cvmx_npei_state1 {
 union cvmx_npei_state2 {
         uint64_t u64;
         struct cvmx_npei_state2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t npei:1;
                 uint64_t rac:1;
@@ -4072,15 +2380,6 @@ union cvmx_npei_state2 {
                 uint64_t csm0:15;
                 uint64_t nnp0:8;
                 uint64_t nnd:8;
-#else
-                uint64_t nnd:8;
-                uint64_t nnp0:8;
-                uint64_t csm0:15;
-                uint64_t csm1:15;
-                uint64_t rac:1;
-                uint64_t npei:1;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_npei_state2_s cn52xx;
         struct cvmx_npei_state2_s cn52xxp1;
@@ -4091,19 +2390,11 @@ union cvmx_npei_state2 {
 union cvmx_npei_state3 {
         uint64_t u64;
         struct cvmx_npei_state3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t psm1:15;
                 uint64_t psm0:15;
                 uint64_t nsm1:13;
                 uint64_t nsm0:13;
-#else
-                uint64_t nsm0:13;
-                uint64_t nsm1:13;
-                uint64_t psm0:15;
-                uint64_t psm1:15;
-                uint64_t reserved_56_63:8;
-#endif
         } s;
         struct cvmx_npei_state3_s cn52xx;
         struct cvmx_npei_state3_s cn52xxp1;
@@ -4114,17 +2405,10 @@ union cvmx_npei_state3 {
 union cvmx_npei_win_rd_addr {
         uint64_t u64;
         struct cvmx_npei_win_rd_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_51_63:13;
                 uint64_t ld_cmd:2;
                 uint64_t iobit:1;
                 uint64_t rd_addr:48;
-#else
-                uint64_t rd_addr:48;
-                uint64_t iobit:1;
-                uint64_t ld_cmd:2;
-                uint64_t reserved_51_63:13;
-#endif
         } s;
         struct cvmx_npei_win_rd_addr_s cn52xx;
         struct cvmx_npei_win_rd_addr_s cn52xxp1;
@@ -4135,11 +2419,7 @@ union cvmx_npei_win_rd_addr {
 union cvmx_npei_win_rd_data {
         uint64_t u64;
         struct cvmx_npei_win_rd_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rd_data:64;
-#else
                 uint64_t rd_data:64;
-#endif
         } s;
         struct cvmx_npei_win_rd_data_s cn52xx;
         struct cvmx_npei_win_rd_data_s cn52xxp1;
@@ -4150,17 +2430,10 @@ union cvmx_npei_win_rd_data {
 union cvmx_npei_win_wr_addr {
         uint64_t u64;
         struct cvmx_npei_win_wr_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_49_63:15;
                 uint64_t iobit:1;
                 uint64_t wr_addr:46;
                 uint64_t reserved_0_1:2;
-#else
-                uint64_t reserved_0_1:2;
-                uint64_t wr_addr:46;
-                uint64_t iobit:1;
-                uint64_t reserved_49_63:15;
-#endif
         } s;
         struct cvmx_npei_win_wr_addr_s cn52xx;
         struct cvmx_npei_win_wr_addr_s cn52xxp1;
@@ -4171,11 +2444,7 @@ union cvmx_npei_win_wr_addr {
 union cvmx_npei_win_wr_data {
         uint64_t u64;
         struct cvmx_npei_win_wr_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t wr_data:64;
-#else
-                uint64_t wr_data:64;
-#endif
         } s;
         struct cvmx_npei_win_wr_data_s cn52xx;
         struct cvmx_npei_win_wr_data_s cn52xxp1;
@@ -4186,13 +2455,8 @@ union cvmx_npei_win_wr_data {
 union cvmx_npei_win_wr_mask {
         uint64_t u64;
         struct cvmx_npei_win_wr_mask_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t wr_mask:8;
-#else
-                uint64_t wr_mask:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_npei_win_wr_mask_s cn52xx;
         struct cvmx_npei_win_wr_mask_s cn52xxp1;
@@ -4203,13 +2467,8 @@ union cvmx_npei_win_wr_mask {
 union cvmx_npei_window_ctl {
         uint64_t u64;
         struct cvmx_npei_window_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t time:32;
-#else
-                uint64_t time:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npei_window_ctl_s cn52xx;
         struct cvmx_npei_window_ctl_s cn52xxp1;
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
index 129bb250e53..f089c780060 100644
--- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -152,13 +152,8 @@
 union cvmx_npi_base_addr_inputx {
         uint64_t u64;
         struct cvmx_npi_base_addr_inputx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t baddr:61;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t baddr:61;
-#endif
         } s;
         struct cvmx_npi_base_addr_inputx_s cn30xx;
         struct cvmx_npi_base_addr_inputx_s cn31xx;
@@ -172,13 +167,8 @@ union cvmx_npi_base_addr_inputx {
 union cvmx_npi_base_addr_outputx {
         uint64_t u64;
         struct cvmx_npi_base_addr_outputx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t baddr:61;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t baddr:61;
-#endif
         } s;
         struct cvmx_npi_base_addr_outputx_s cn30xx;
         struct cvmx_npi_base_addr_outputx_s cn31xx;
@@ -192,7 +182,6 @@ union cvmx_npi_base_addr_outputx {
 union cvmx_npi_bist_status {
         uint64_t u64;
         struct cvmx_npi_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t csr_bs:1;
                 uint64_t dif_bs:1;
@@ -214,32 +203,8 @@ union cvmx_npi_bist_status {
                 uint64_t dob_bs:1;
                 uint64_t pdf_bs:1;
                 uint64_t dpi_bs:1;
-#else
-                uint64_t dpi_bs:1;
-                uint64_t pdf_bs:1;
-                uint64_t dob_bs:1;
-                uint64_t nus_bs:1;
-                uint64_t pos_bs:1;
-                uint64_t pof3_bs:1;
-                uint64_t pof2_bs:1;
-                uint64_t pof1_bs:1;
-                uint64_t pof0_bs:1;
-                uint64_t pig_bs:1;
-                uint64_t pgf_bs:1;
-                uint64_t rdnl_bs:1;
-                uint64_t pcad_bs:1;
-                uint64_t pcac_bs:1;
-                uint64_t rdn_bs:1;
-                uint64_t pcn_bs:1;
-                uint64_t pcnc_bs:1;
-                uint64_t rdp_bs:1;
-                uint64_t dif_bs:1;
-                uint64_t csr_bs:1;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
         struct cvmx_npi_bist_status_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t csr_bs:1;
                 uint64_t dif_bs:1;
@@ -259,33 +224,11 @@ union cvmx_npi_bist_status {
                 uint64_t dob_bs:1;
                 uint64_t pdf_bs:1;
                 uint64_t dpi_bs:1;
-#else
-                uint64_t dpi_bs:1;
-                uint64_t pdf_bs:1;
-                uint64_t dob_bs:1;
-                uint64_t nus_bs:1;
-                uint64_t pos_bs:1;
-                uint64_t reserved_5_7:3;
-                uint64_t pof0_bs:1;
-                uint64_t pig_bs:1;
-                uint64_t pgf_bs:1;
-                uint64_t rdnl_bs:1;
-                uint64_t pcad_bs:1;
-                uint64_t pcac_bs:1;
-                uint64_t rdn_bs:1;
-                uint64_t pcn_bs:1;
-                uint64_t pcnc_bs:1;
-                uint64_t rdp_bs:1;
-                uint64_t dif_bs:1;
-                uint64_t csr_bs:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn30xx;
         struct cvmx_npi_bist_status_s cn31xx;
         struct cvmx_npi_bist_status_s cn38xx;
         struct cvmx_npi_bist_status_s cn38xxp2;
         struct cvmx_npi_bist_status_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t csr_bs:1;
                 uint64_t dif_bs:1;
@@ -306,28 +249,6 @@ union cvmx_npi_bist_status {
                 uint64_t dob_bs:1;
                 uint64_t pdf_bs:1;
                 uint64_t dpi_bs:1;
-#else
-                uint64_t dpi_bs:1;
-                uint64_t pdf_bs:1;
-                uint64_t dob_bs:1;
-                uint64_t nus_bs:1;
-                uint64_t pos_bs:1;
-                uint64_t reserved_5_6:2;
-                uint64_t pof1_bs:1;
-                uint64_t pof0_bs:1;
-                uint64_t pig_bs:1;
-                uint64_t pgf_bs:1;
-                uint64_t rdnl_bs:1;
-                uint64_t pcad_bs:1;
-                uint64_t pcac_bs:1;
-                uint64_t rdn_bs:1;
-                uint64_t pcn_bs:1;
-                uint64_t pcnc_bs:1;
-                uint64_t rdp_bs:1;
-                uint64_t dif_bs:1;
-                uint64_t csr_bs:1;
-                uint64_t reserved_20_63:44;
-#endif
         } cn50xx;
         struct cvmx_npi_bist_status_s cn58xx;
         struct cvmx_npi_bist_status_s cn58xxp1;
@@ -336,15 +257,9 @@ union cvmx_npi_bist_status {
 union cvmx_npi_buff_size_outputx {
         uint64_t u64;
         struct cvmx_npi_buff_size_outputx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_23_63:41;
                 uint64_t isize:7;
                 uint64_t bsize:16;
-#else
-                uint64_t bsize:16;
-                uint64_t isize:7;
-                uint64_t reserved_23_63:41;
-#endif
         } s;
         struct cvmx_npi_buff_size_outputx_s cn30xx;
         struct cvmx_npi_buff_size_outputx_s cn31xx;
@@ -358,15 +273,9 @@ union cvmx_npi_buff_size_outputx {
 union cvmx_npi_comp_ctl {
         uint64_t u64;
         struct cvmx_npi_comp_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t pctl:5;
                 uint64_t nctl:5;
-#else
-                uint64_t nctl:5;
-                uint64_t pctl:5;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_npi_comp_ctl_s cn50xx;
         struct cvmx_npi_comp_ctl_s cn58xx;
@@ -376,7 +285,6 @@ union cvmx_npi_comp_ctl {
 union cvmx_npi_ctl_status {
         uint64_t u64;
         struct cvmx_npi_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_63_63:1;
                 uint64_t chip_rev:8;
                 uint64_t dis_pniw:1;
@@ -398,32 +306,8 @@ union cvmx_npi_ctl_status {
                 uint64_t max_word:5;
                 uint64_t reserved_10_31:22;
                 uint64_t timer:10;
-#else
-                uint64_t timer:10;
-                uint64_t reserved_10_31:22;
-                uint64_t max_word:5;
-                uint64_t reserved_37_39:3;
-                uint64_t wait_com:1;
-                uint64_t pci_wdis:1;
-                uint64_t ins0_64b:1;
-                uint64_t ins1_64b:1;
-                uint64_t ins2_64b:1;
-                uint64_t ins3_64b:1;
-                uint64_t ins0_enb:1;
-                uint64_t ins1_enb:1;
-                uint64_t ins2_enb:1;
-                uint64_t ins3_enb:1;
-                uint64_t out0_enb:1;
-                uint64_t out1_enb:1;
-                uint64_t out2_enb:1;
-                uint64_t out3_enb:1;
-                uint64_t dis_pniw:1;
-                uint64_t chip_rev:8;
-                uint64_t reserved_63_63:1;
-#endif
         } s;
         struct cvmx_npi_ctl_status_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_63_63:1;
                 uint64_t chip_rev:8;
                 uint64_t dis_pniw:1;
@@ -439,26 +323,8 @@ union cvmx_npi_ctl_status {
                 uint64_t max_word:5;
                 uint64_t reserved_10_31:22;
                 uint64_t timer:10;
-#else
-                uint64_t timer:10;
-                uint64_t reserved_10_31:22;
-                uint64_t max_word:5;
-                uint64_t reserved_37_39:3;
-                uint64_t wait_com:1;
-                uint64_t pci_wdis:1;
-                uint64_t ins0_64b:1;
-                uint64_t reserved_43_45:3;
-                uint64_t ins0_enb:1;
-                uint64_t reserved_47_49:3;
-                uint64_t out0_enb:1;
-                uint64_t reserved_51_53:3;
-                uint64_t dis_pniw:1;
-                uint64_t chip_rev:8;
-                uint64_t reserved_63_63:1;
-#endif
         } cn30xx;
         struct cvmx_npi_ctl_status_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_63_63:1;
                 uint64_t chip_rev:8;
                 uint64_t dis_pniw:1;
@@ -477,26 +343,6 @@ union cvmx_npi_ctl_status {
                 uint64_t max_word:5;
                 uint64_t reserved_10_31:22;
                 uint64_t timer:10;
-#else
-                uint64_t timer:10;
-                uint64_t reserved_10_31:22;
-                uint64_t max_word:5;
-                uint64_t reserved_37_39:3;
-                uint64_t wait_com:1;
-                uint64_t pci_wdis:1;
-                uint64_t ins0_64b:1;
-                uint64_t ins1_64b:1;
-                uint64_t reserved_44_45:2;
-                uint64_t ins0_enb:1;
-                uint64_t ins1_enb:1;
-                uint64_t reserved_48_49:2;
-                uint64_t out0_enb:1;
-                uint64_t out1_enb:1;
-                uint64_t reserved_52_53:2;
-                uint64_t dis_pniw:1;
-                uint64_t chip_rev:8;
-                uint64_t reserved_63_63:1;
-#endif
         } cn31xx;
         struct cvmx_npi_ctl_status_s cn38xx;
         struct cvmx_npi_ctl_status_s cn38xxp2;
@@ -508,13 +354,8 @@ union cvmx_npi_ctl_status {
 union cvmx_npi_dbg_select {
         uint64_t u64;
         struct cvmx_npi_dbg_select_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t dbg_sel:16;
-#else
-                uint64_t dbg_sel:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_npi_dbg_select_s cn30xx;
         struct cvmx_npi_dbg_select_s cn31xx;
@@ -528,7 +369,6 @@ union cvmx_npi_dbg_select {
 union cvmx_npi_dma_control {
         uint64_t u64;
         struct cvmx_npi_dma_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t b0_lend:1;
                 uint64_t dwb_denb:1;
@@ -542,21 +382,6 @@ union cvmx_npi_dma_control {
                 uint64_t hp_enb:1;
                 uint64_t lp_enb:1;
                 uint64_t csize:14;
-#else
-                uint64_t csize:14;
-                uint64_t lp_enb:1;
-                uint64_t hp_enb:1;
-                uint64_t o_mode:1;
-                uint64_t o_es:2;
-                uint64_t o_ns:1;
-                uint64_t o_ro:1;
-                uint64_t o_add1:1;
-                uint64_t fpa_que:3;
-                uint64_t dwb_ichk:9;
-                uint64_t dwb_denb:1;
-                uint64_t b0_lend:1;
-                uint64_t reserved_36_63:28;
-#endif
         } s;
         struct cvmx_npi_dma_control_s cn30xx;
         struct cvmx_npi_dma_control_s cn31xx;
@@ -570,15 +395,9 @@ union cvmx_npi_dma_control {
 union cvmx_npi_dma_highp_counts {
         uint64_t u64;
         struct cvmx_npi_dma_highp_counts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_39_63:25;
                 uint64_t fcnt:7;
                 uint64_t dbell:32;
-#else
-                uint64_t dbell:32;
-                uint64_t fcnt:7;
-                uint64_t reserved_39_63:25;
-#endif
         } s;
         struct cvmx_npi_dma_highp_counts_s cn30xx;
         struct cvmx_npi_dma_highp_counts_s cn31xx;
@@ -592,15 +411,9 @@ union cvmx_npi_dma_highp_counts {
 union cvmx_npi_dma_highp_naddr {
         uint64_t u64;
         struct cvmx_npi_dma_highp_naddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t state:4;
                 uint64_t addr:36;
-#else
-                uint64_t addr:36;
-                uint64_t state:4;
-                uint64_t reserved_40_63:24;
-#endif
         } s;
         struct cvmx_npi_dma_highp_naddr_s cn30xx;
         struct cvmx_npi_dma_highp_naddr_s cn31xx;
@@ -614,15 +427,9 @@ union cvmx_npi_dma_highp_naddr {
 union cvmx_npi_dma_lowp_counts {
         uint64_t u64;
         struct cvmx_npi_dma_lowp_counts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_39_63:25;
                 uint64_t fcnt:7;
                 uint64_t dbell:32;
-#else
-                uint64_t dbell:32;
-                uint64_t fcnt:7;
-                uint64_t reserved_39_63:25;
-#endif
         } s;
         struct cvmx_npi_dma_lowp_counts_s cn30xx;
         struct cvmx_npi_dma_lowp_counts_s cn31xx;
@@ -636,15 +443,9 @@ union cvmx_npi_dma_lowp_counts {
 union cvmx_npi_dma_lowp_naddr {
         uint64_t u64;
         struct cvmx_npi_dma_lowp_naddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_40_63:24;
                 uint64_t state:4;
                 uint64_t addr:36;
-#else
-                uint64_t addr:36;
-                uint64_t state:4;
-                uint64_t reserved_40_63:24;
-#endif
         } s;
         struct cvmx_npi_dma_lowp_naddr_s cn30xx;
         struct cvmx_npi_dma_lowp_naddr_s cn31xx;
@@ -658,13 +459,8 @@ union cvmx_npi_dma_lowp_naddr {
 union cvmx_npi_highp_dbell {
         uint64_t u64;
         struct cvmx_npi_highp_dbell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t dbell:16;
-#else
-                uint64_t dbell:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_npi_highp_dbell_s cn30xx;
         struct cvmx_npi_highp_dbell_s cn31xx;
@@ -678,13 +474,8 @@ union cvmx_npi_highp_dbell {
 union cvmx_npi_highp_ibuff_saddr {
         uint64_t u64;
         struct cvmx_npi_highp_ibuff_saddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t saddr:36;
-#else
-                uint64_t saddr:36;
-                uint64_t reserved_36_63:28;
-#endif
         } s;
         struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
         struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
@@ -698,7 +489,6 @@ union cvmx_npi_highp_ibuff_saddr {
 union cvmx_npi_input_control {
         uint64_t u64;
         struct cvmx_npi_input_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_23_63:41;
                 uint64_t pkt_rr:1;
                 uint64_t pbp_dhi:13;
@@ -709,21 +499,8 @@ union cvmx_npi_input_control {
                 uint64_t nsr:1;
                 uint64_t esr:2;
                 uint64_t ror:1;
-#else
-                uint64_t ror:1;
-                uint64_t esr:2;
-                uint64_t nsr:1;
-                uint64_t use_csr:1;
-                uint64_t d_ror:1;
-                uint64_t d_esr:2;
-                uint64_t d_nsr:1;
-                uint64_t pbp_dhi:13;
-                uint64_t pkt_rr:1;
-                uint64_t reserved_23_63:41;
-#endif
         } s;
         struct cvmx_npi_input_control_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_22_63:42;
                 uint64_t pbp_dhi:13;
                 uint64_t d_nsr:1;
@@ -733,17 +510,6 @@ union cvmx_npi_input_control {
                 uint64_t nsr:1;
                 uint64_t esr:2;
                 uint64_t ror:1;
-#else
-                uint64_t ror:1;
-                uint64_t esr:2;
-                uint64_t nsr:1;
-                uint64_t use_csr:1;
-                uint64_t d_ror:1;
-                uint64_t d_esr:2;
-                uint64_t d_nsr:1;
-                uint64_t pbp_dhi:13;
-                uint64_t reserved_22_63:42;
-#endif
         } cn30xx;
         struct cvmx_npi_input_control_cn30xx cn31xx;
         struct cvmx_npi_input_control_s cn38xx;
@@ -756,7 +522,6 @@ union cvmx_npi_input_control {
 union cvmx_npi_int_enb {
         uint64_t u64;
         struct cvmx_npi_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t q1_a_f:1;
                 uint64_t q1_s_e:1;
@@ -820,74 +585,8 @@ union cvmx_npi_int_enb {
                 uint64_t pci_rsl:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t pci_rsl:1;
-                uint64_t po0_2sml:1;
-                uint64_t po1_2sml:1;
-                uint64_t po2_2sml:1;
-                uint64_t po3_2sml:1;
-                uint64_t i0_rtout:1;
-                uint64_t i1_rtout:1;
-                uint64_t i2_rtout:1;
-                uint64_t i3_rtout:1;
-                uint64_t i0_overf:1;
-                uint64_t i1_overf:1;
-                uint64_t i2_overf:1;
-                uint64_t i3_overf:1;
-                uint64_t p0_rtout:1;
-                uint64_t p1_rtout:1;
-                uint64_t p2_rtout:1;
-                uint64_t p3_rtout:1;
-                uint64_t p0_perr:1;
-                uint64_t p1_perr:1;
-                uint64_t p2_perr:1;
-                uint64_t p3_perr:1;
-                uint64_t g0_rtout:1;
-                uint64_t g1_rtout:1;
-                uint64_t g2_rtout:1;
-                uint64_t g3_rtout:1;
-                uint64_t p0_pperr:1;
-                uint64_t p1_pperr:1;
-                uint64_t p2_pperr:1;
-                uint64_t p3_pperr:1;
-                uint64_t p0_ptout:1;
-                uint64_t p1_ptout:1;
-                uint64_t p2_ptout:1;
-                uint64_t p3_ptout:1;
-                uint64_t i0_pperr:1;
-                uint64_t i1_pperr:1;
-                uint64_t i2_pperr:1;
-                uint64_t i3_pperr:1;
-                uint64_t win_rto:1;
-                uint64_t p_dperr:1;
-                uint64_t iobdma:1;
-                uint64_t fcr_s_e:1;
-                uint64_t fcr_a_f:1;
-                uint64_t pcr_s_e:1;
-                uint64_t pcr_a_f:1;
-                uint64_t q2_s_e:1;
-                uint64_t q2_a_f:1;
-                uint64_t q3_s_e:1;
-                uint64_t q3_a_f:1;
-                uint64_t com_s_e:1;
-                uint64_t com_a_f:1;
-                uint64_t pnc_s_e:1;
-                uint64_t pnc_a_f:1;
-                uint64_t rwx_s_e:1;
-                uint64_t rdx_s_e:1;
-                uint64_t pcf_p_e:1;
-                uint64_t pcf_p_f:1;
-                uint64_t pdf_p_e:1;
-                uint64_t pdf_p_f:1;
-                uint64_t q1_s_e:1;
-                uint64_t q1_a_f:1;
-                uint64_t reserved_62_63:2;
-#endif
         } s;
         struct cvmx_npi_int_enb_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t q1_a_f:1;
                 uint64_t q1_s_e:1;
@@ -933,56 +632,8 @@ union cvmx_npi_int_enb {
                 uint64_t pci_rsl:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t pci_rsl:1;
-                uint64_t po0_2sml:1;
-                uint64_t reserved_4_6:3;
-                uint64_t i0_rtout:1;
-                uint64_t reserved_8_10:3;
-                uint64_t i0_overf:1;
-                uint64_t reserved_12_14:3;
-                uint64_t p0_rtout:1;
-                uint64_t reserved_16_18:3;
-                uint64_t p0_perr:1;
-                uint64_t reserved_20_22:3;
-                uint64_t g0_rtout:1;
-                uint64_t reserved_24_26:3;
-                uint64_t p0_pperr:1;
-                uint64_t reserved_28_30:3;
-                uint64_t p0_ptout:1;
-                uint64_t reserved_32_34:3;
-                uint64_t i0_pperr:1;
-                uint64_t reserved_36_38:3;
-                uint64_t win_rto:1;
-                uint64_t p_dperr:1;
-                uint64_t iobdma:1;
-                uint64_t fcr_s_e:1;
-                uint64_t fcr_a_f:1;
-                uint64_t pcr_s_e:1;
-                uint64_t pcr_a_f:1;
-                uint64_t q2_s_e:1;
-                uint64_t q2_a_f:1;
-                uint64_t q3_s_e:1;
-                uint64_t q3_a_f:1;
-                uint64_t com_s_e:1;
-                uint64_t com_a_f:1;
-                uint64_t pnc_s_e:1;
-                uint64_t pnc_a_f:1;
-                uint64_t rwx_s_e:1;
-                uint64_t rdx_s_e:1;
-                uint64_t pcf_p_e:1;
-                uint64_t pcf_p_f:1;
-                uint64_t pdf_p_e:1;
-                uint64_t pdf_p_f:1;
-                uint64_t q1_s_e:1;
-                uint64_t q1_a_f:1;
-                uint64_t reserved_62_63:2;
-#endif
         } cn30xx;
         struct cvmx_npi_int_enb_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t q1_a_f:1;
                 uint64_t q1_s_e:1;
@@ -1037,66 +688,9 @@ union cvmx_npi_int_enb {
                 uint64_t pci_rsl:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t pci_rsl:1;
-                uint64_t po0_2sml:1;
-                uint64_t po1_2sml:1;
-                uint64_t reserved_5_6:2;
-                uint64_t i0_rtout:1;
-                uint64_t i1_rtout:1;
-                uint64_t reserved_9_10:2;
-                uint64_t i0_overf:1;
-                uint64_t i1_overf:1;
-                uint64_t reserved_13_14:2;
-                uint64_t p0_rtout:1;
-                uint64_t p1_rtout:1;
-                uint64_t reserved_17_18:2;
-                uint64_t p0_perr:1;
-                uint64_t p1_perr:1;
-                uint64_t reserved_21_22:2;
-                uint64_t g0_rtout:1;
-                uint64_t g1_rtout:1;
-                uint64_t reserved_25_26:2;
-                uint64_t p0_pperr:1;
-                uint64_t p1_pperr:1;
-                uint64_t reserved_29_30:2;
-                uint64_t p0_ptout:1;
-                uint64_t p1_ptout:1;
-                uint64_t reserved_33_34:2;
-                uint64_t i0_pperr:1;
-                uint64_t i1_pperr:1;
-                uint64_t reserved_37_38:2;
-                uint64_t win_rto:1;
-                uint64_t p_dperr:1;
-                uint64_t iobdma:1;
-                uint64_t fcr_s_e:1;
-                uint64_t fcr_a_f:1;
-                uint64_t pcr_s_e:1;
-                uint64_t pcr_a_f:1;
-                uint64_t q2_s_e:1;
-                uint64_t q2_a_f:1;
-                uint64_t q3_s_e:1;
-                uint64_t q3_a_f:1;
-                uint64_t com_s_e:1;
-                uint64_t com_a_f:1;
-                uint64_t pnc_s_e:1;
-                uint64_t pnc_a_f:1;
-                uint64_t rwx_s_e:1;
-                uint64_t rdx_s_e:1;
-                uint64_t pcf_p_e:1;
-                uint64_t pcf_p_f:1;
-                uint64_t pdf_p_e:1;
-                uint64_t pdf_p_f:1;
-                uint64_t q1_s_e:1;
-                uint64_t q1_a_f:1;
-                uint64_t reserved_62_63:2;
-#endif
         } cn31xx;
         struct cvmx_npi_int_enb_s cn38xx;
         struct cvmx_npi_int_enb_cn38xxp2 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_42_63:22;
                 uint64_t iobdma:1;
                 uint64_t p_dperr:1;
@@ -1140,51 +734,6 @@ union cvmx_npi_int_enb {
                 uint64_t pci_rsl:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t pci_rsl:1;
-                uint64_t po0_2sml:1;
-                uint64_t po1_2sml:1;
-                uint64_t po2_2sml:1;
-                uint64_t po3_2sml:1;
-                uint64_t i0_rtout:1;
-                uint64_t i1_rtout:1;
-                uint64_t i2_rtout:1;
-                uint64_t i3_rtout:1;
-                uint64_t i0_overf:1;
-                uint64_t i1_overf:1;
-                uint64_t i2_overf:1;
-                uint64_t i3_overf:1;
-                uint64_t p0_rtout:1;
-                uint64_t p1_rtout:1;
-                uint64_t p2_rtout:1;
-                uint64_t p3_rtout:1;
-                uint64_t p0_perr:1;
-                uint64_t p1_perr:1;
-                uint64_t p2_perr:1;
-                uint64_t p3_perr:1;
-                uint64_t g0_rtout:1;
-                uint64_t g1_rtout:1;
-                uint64_t g2_rtout:1;
-                uint64_t g3_rtout:1;
-                uint64_t p0_pperr:1;
-                uint64_t p1_pperr:1;
-                uint64_t p2_pperr:1;
-                uint64_t p3_pperr:1;
-                uint64_t p0_ptout:1;
-                uint64_t p1_ptout:1;
-                uint64_t p2_ptout:1;
-                uint64_t p3_ptout:1;
-                uint64_t i0_pperr:1;
-                uint64_t i1_pperr:1;
-                uint64_t i2_pperr:1;
-                uint64_t i3_pperr:1;
-                uint64_t win_rto:1;
-                uint64_t p_dperr:1;
-                uint64_t iobdma:1;
-                uint64_t reserved_42_63:22;
-#endif
         } cn38xxp2;
         struct cvmx_npi_int_enb_cn31xx cn50xx;
         struct cvmx_npi_int_enb_s cn58xx;
@@ -1194,7 +743,6 @@ union cvmx_npi_int_enb {
 union cvmx_npi_int_sum {
         uint64_t u64;
         struct cvmx_npi_int_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t q1_a_f:1;
                 uint64_t q1_s_e:1;
@@ -1258,74 +806,8 @@ union cvmx_npi_int_sum {
                 uint64_t pci_rsl:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t pci_rsl:1;
-                uint64_t po0_2sml:1;
-                uint64_t po1_2sml:1;
-                uint64_t po2_2sml:1;
-                uint64_t po3_2sml:1;
-                uint64_t i0_rtout:1;
-                uint64_t i1_rtout:1;
-                uint64_t i2_rtout:1;
-                uint64_t i3_rtout:1;
-                uint64_t i0_overf:1;
-                uint64_t i1_overf:1;
-                uint64_t i2_overf:1;
-                uint64_t i3_overf:1;
-                uint64_t p0_rtout:1;
-                uint64_t p1_rtout:1;
-                uint64_t p2_rtout:1;
-                uint64_t p3_rtout:1;
-                uint64_t p0_perr:1;
-                uint64_t p1_perr:1;
-                uint64_t p2_perr:1;
-                uint64_t p3_perr:1;
-                uint64_t g0_rtout:1;
-                uint64_t g1_rtout:1;
-                uint64_t g2_rtout:1;
-                uint64_t g3_rtout:1;
-                uint64_t p0_pperr:1;
-                uint64_t p1_pperr:1;
-                uint64_t p2_pperr:1;
-                uint64_t p3_pperr:1;
-                uint64_t p0_ptout:1;
-                uint64_t p1_ptout:1;
-                uint64_t p2_ptout:1;
-                uint64_t p3_ptout:1;
-                uint64_t i0_pperr:1;
-                uint64_t i1_pperr:1;
-                uint64_t i2_pperr:1;
-                uint64_t i3_pperr:1;
-                uint64_t win_rto:1;
-                uint64_t p_dperr:1;
-                uint64_t iobdma:1;
-                uint64_t fcr_s_e:1;
-                uint64_t fcr_a_f:1;
-                uint64_t pcr_s_e:1;
-                uint64_t pcr_a_f:1;
-                uint64_t q2_s_e:1;
-                uint64_t q2_a_f:1;
-                uint64_t q3_s_e:1;
-                uint64_t q3_a_f:1;
-                uint64_t com_s_e:1;
-                uint64_t com_a_f:1;
-                uint64_t pnc_s_e:1;
-                uint64_t pnc_a_f:1;
-                uint64_t rwx_s_e:1;
-                uint64_t rdx_s_e:1;
-                uint64_t pcf_p_e:1;
-                uint64_t pcf_p_f:1;
-                uint64_t pdf_p_e:1;
-                uint64_t pdf_p_f:1;
-                uint64_t q1_s_e:1;
-                uint64_t q1_a_f:1;
-                uint64_t reserved_62_63:2;
-#endif
         } s;
         struct cvmx_npi_int_sum_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t q1_a_f:1;
                 uint64_t q1_s_e:1;
@@ -1371,56 +853,8 @@ union cvmx_npi_int_sum {
                 uint64_t pci_rsl:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t pci_rsl:1;
-                uint64_t po0_2sml:1;
-                uint64_t reserved_4_6:3;
-                uint64_t i0_rtout:1;
-                uint64_t reserved_8_10:3;
-                uint64_t i0_overf:1;
-                uint64_t reserved_12_14:3;
-                uint64_t p0_rtout:1;
-                uint64_t reserved_16_18:3;
-                uint64_t p0_perr:1;
-                uint64_t reserved_20_22:3;
-                uint64_t g0_rtout:1;
-                uint64_t reserved_24_26:3;
-                uint64_t p0_pperr:1;
-                uint64_t reserved_28_30:3;
-                uint64_t p0_ptout:1;
-                uint64_t reserved_32_34:3;
-                uint64_t i0_pperr:1;
-                uint64_t reserved_36_38:3;
-                uint64_t win_rto:1;
-                uint64_t p_dperr:1;
-                uint64_t iobdma:1;
-                uint64_t fcr_s_e:1;
-                uint64_t fcr_a_f:1;
-                uint64_t pcr_s_e:1;
-                uint64_t pcr_a_f:1;
-                uint64_t q2_s_e:1;
-                uint64_t q2_a_f:1;
-                uint64_t q3_s_e:1;
-                uint64_t q3_a_f:1;
-                uint64_t com_s_e:1;
-                uint64_t com_a_f:1;
-                uint64_t pnc_s_e:1;
-                uint64_t pnc_a_f:1;
-                uint64_t rwx_s_e:1;
-                uint64_t rdx_s_e:1;
-                uint64_t pcf_p_e:1;
-                uint64_t pcf_p_f:1;
-                uint64_t pdf_p_e:1;
-                uint64_t pdf_p_f:1;
-                uint64_t q1_s_e:1;
-                uint64_t q1_a_f:1;
-                uint64_t reserved_62_63:2;
-#endif
         } cn30xx;
         struct cvmx_npi_int_sum_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_62_63:2;
                 uint64_t q1_a_f:1;
                 uint64_t q1_s_e:1;
@@ -1475,66 +909,9 @@ union cvmx_npi_int_sum {
                 uint64_t pci_rsl:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t pci_rsl:1;
-                uint64_t po0_2sml:1;
-                uint64_t po1_2sml:1;
-                uint64_t reserved_5_6:2;
-                uint64_t i0_rtout:1;
-                uint64_t i1_rtout:1;
-                uint64_t reserved_9_10:2;
-                uint64_t i0_overf:1;
-                uint64_t i1_overf:1;
-                uint64_t reserved_13_14:2;
-                uint64_t p0_rtout:1;
-                uint64_t p1_rtout:1;
-                uint64_t reserved_17_18:2;
-                uint64_t p0_perr:1;
-                uint64_t p1_perr:1;
-                uint64_t reserved_21_22:2;
-                uint64_t g0_rtout:1;
-                uint64_t g1_rtout:1;
-                uint64_t reserved_25_26:2;
-                uint64_t p0_pperr:1;
-                uint64_t p1_pperr:1;
-                uint64_t reserved_29_30:2;
-                uint64_t p0_ptout:1;
-                uint64_t p1_ptout:1;
-                uint64_t reserved_33_34:2;
-                uint64_t i0_pperr:1;
-                uint64_t i1_pperr:1;
-                uint64_t reserved_37_38:2;
-                uint64_t win_rto:1;
-                uint64_t p_dperr:1;
-                uint64_t iobdma:1;
-                uint64_t fcr_s_e:1;
-                uint64_t fcr_a_f:1;
-                uint64_t pcr_s_e:1;
-                uint64_t pcr_a_f:1;
-                uint64_t q2_s_e:1;
-                uint64_t q2_a_f:1;
-                uint64_t q3_s_e:1;
-                uint64_t q3_a_f:1;
-                uint64_t com_s_e:1;
-                uint64_t com_a_f:1;
-                uint64_t pnc_s_e:1;
-                uint64_t pnc_a_f:1;
-                uint64_t rwx_s_e:1;
-                uint64_t rdx_s_e:1;
-                uint64_t pcf_p_e:1;
-                uint64_t pcf_p_f:1;
-                uint64_t pdf_p_e:1;
-                uint64_t pdf_p_f:1;
-                uint64_t q1_s_e:1;
-                uint64_t q1_a_f:1;
-                uint64_t reserved_62_63:2;
-#endif
         } cn31xx;
         struct cvmx_npi_int_sum_s cn38xx;
         struct cvmx_npi_int_sum_cn38xxp2 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_42_63:22;
                 uint64_t iobdma:1;
                 uint64_t p_dperr:1;
@@ -1578,51 +955,6 @@ union cvmx_npi_int_sum {
                 uint64_t pci_rsl:1;
                 uint64_t rml_wto:1;
                 uint64_t rml_rto:1;
-#else
-                uint64_t rml_rto:1;
-                uint64_t rml_wto:1;
-                uint64_t pci_rsl:1;
-                uint64_t po0_2sml:1;
-                uint64_t po1_2sml:1;
-                uint64_t po2_2sml:1;
-                uint64_t po3_2sml:1;
-                uint64_t i0_rtout:1;
-                uint64_t i1_rtout:1;
-                uint64_t i2_rtout:1;
-                uint64_t i3_rtout:1;
-                uint64_t i0_overf:1;
-                uint64_t i1_overf:1;
-                uint64_t i2_overf:1;
-                uint64_t i3_overf:1;
-                uint64_t p0_rtout:1;
-                uint64_t p1_rtout:1;
-                uint64_t p2_rtout:1;
-                uint64_t p3_rtout:1;
-                uint64_t p0_perr:1;
-                uint64_t p1_perr:1;
-                uint64_t p2_perr:1;
-                uint64_t p3_perr:1;
-                uint64_t g0_rtout:1;
-                uint64_t g1_rtout:1;
-                uint64_t g2_rtout:1;
-                uint64_t g3_rtout:1;
-                uint64_t p0_pperr:1;
-                uint64_t p1_pperr:1;
-                uint64_t p2_pperr:1;
-                uint64_t p3_pperr:1;
-                uint64_t p0_ptout:1;
-                uint64_t p1_ptout:1;
-                uint64_t p2_ptout:1;
-                uint64_t p3_ptout:1;
-                uint64_t i0_pperr:1;
-                uint64_t i1_pperr:1;
-                uint64_t i2_pperr:1;
-                uint64_t i3_pperr:1;
-                uint64_t win_rto:1;
-                uint64_t p_dperr:1;
-                uint64_t iobdma:1;
-                uint64_t reserved_42_63:22;
-#endif
         } cn38xxp2;
         struct cvmx_npi_int_sum_cn31xx cn50xx;
         struct cvmx_npi_int_sum_s cn58xx;
@@ -1632,13 +964,8 @@ union cvmx_npi_int_sum {
 union cvmx_npi_lowp_dbell {
         uint64_t u64;
         struct cvmx_npi_lowp_dbell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t dbell:16;
-#else
-                uint64_t dbell:16;
-                uint64_t reserved_16_63:48;
-#endif
         } s;
         struct cvmx_npi_lowp_dbell_s cn30xx;
         struct cvmx_npi_lowp_dbell_s cn31xx;
@@ -1652,13 +979,8 @@ union cvmx_npi_lowp_dbell {
 union cvmx_npi_lowp_ibuff_saddr {
         uint64_t u64;
         struct cvmx_npi_lowp_ibuff_saddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t saddr:36;
-#else
-                uint64_t saddr:36;
-                uint64_t reserved_36_63:28;
-#endif
         } s;
         struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
         struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
@@ -1672,7 +994,6 @@ union cvmx_npi_lowp_ibuff_saddr {
 union cvmx_npi_mem_access_subidx {
         uint64_t u64;
         struct cvmx_npi_mem_access_subidx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_38_63:26;
                 uint64_t shortl:1;
                 uint64_t nmerge:1;
@@ -1683,22 +1004,9 @@ union cvmx_npi_mem_access_subidx {
                 uint64_t ror:1;
                 uint64_t row:1;
                 uint64_t ba:28;
-#else
-                uint64_t ba:28;
-                uint64_t row:1;
-                uint64_t ror:1;
-                uint64_t nsw:1;
-                uint64_t nsr:1;
-                uint64_t esw:2;
-                uint64_t esr:2;
-                uint64_t nmerge:1;
-                uint64_t shortl:1;
-                uint64_t reserved_38_63:26;
-#endif
         } s;
         struct cvmx_npi_mem_access_subidx_s cn30xx;
         struct cvmx_npi_mem_access_subidx_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t esr:2;
                 uint64_t esw:2;
@@ -1707,16 +1015,6 @@ union cvmx_npi_mem_access_subidx {
                 uint64_t ror:1;
                 uint64_t row:1;
                 uint64_t ba:28;
-#else
-                uint64_t ba:28;
-                uint64_t row:1;
-                uint64_t ror:1;
-                uint64_t nsw:1;
-                uint64_t nsr:1;
-                uint64_t esw:2;
-                uint64_t esr:2;
-                uint64_t reserved_36_63:28;
-#endif
         } cn31xx;
         struct cvmx_npi_mem_access_subidx_s cn38xx;
         struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
@@ -1728,11 +1026,7 @@ union cvmx_npi_mem_access_subidx {
 union cvmx_npi_msi_rcv {
         uint64_t u64;
         struct cvmx_npi_msi_rcv_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t int_vec:64;
-#else
                 uint64_t int_vec:64;
-#endif
         } s;
         struct cvmx_npi_msi_rcv_s cn30xx;
         struct cvmx_npi_msi_rcv_s cn31xx;
@@ -1746,13 +1040,8 @@ union cvmx_npi_msi_rcv {
 union cvmx_npi_num_desc_outputx {
         uint64_t u64;
         struct cvmx_npi_num_desc_outputx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t size:32;
-#else
-                uint64_t size:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npi_num_desc_outputx_s cn30xx;
         struct cvmx_npi_num_desc_outputx_s cn31xx;
@@ -1766,7 +1055,6 @@ union cvmx_npi_num_desc_outputx {
 union cvmx_npi_output_control {
         uint64_t u64;
         struct cvmx_npi_output_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_49_63:15;
                 uint64_t pkt_rr:1;
                 uint64_t p3_bmode:1;
@@ -1806,50 +1094,8 @@ union cvmx_npi_output_control {
                 uint64_t esr_sl0:2;
                 uint64_t nsr_sl0:1;
                 uint64_t ror_sl0:1;
-#else
-                uint64_t ror_sl0:1;
-                uint64_t nsr_sl0:1;
-                uint64_t esr_sl0:2;
-                uint64_t ror_sl1:1;
-                uint64_t nsr_sl1:1;
-                uint64_t esr_sl1:2;
-                uint64_t ror_sl2:1;
-                uint64_t nsr_sl2:1;
-                uint64_t esr_sl2:2;
-                uint64_t ror_sl3:1;
-                uint64_t nsr_sl3:1;
-                uint64_t esr_sl3:2;
-                uint64_t iptr_o0:1;
-                uint64_t iptr_o1:1;
-                uint64_t iptr_o2:1;
-                uint64_t iptr_o3:1;
-                uint64_t reserved_20_23:4;
-                uint64_t o0_csrm:1;
-                uint64_t o1_csrm:1;
-                uint64_t o2_csrm:1;
-                uint64_t o3_csrm:1;
-                uint64_t o0_ro:1;
-                uint64_t o0_ns:1;
-                uint64_t o0_es:2;
-                uint64_t o1_ro:1;
-                uint64_t o1_ns:1;
-                uint64_t o1_es:2;
-                uint64_t o2_ro:1;
-                uint64_t o2_ns:1;
-                uint64_t o2_es:2;
-                uint64_t o3_ro:1;
-                uint64_t o3_ns:1;
-                uint64_t o3_es:2;
-                uint64_t p0_bmode:1;
-                uint64_t p1_bmode:1;
-                uint64_t p2_bmode:1;
-                uint64_t p3_bmode:1;
-                uint64_t pkt_rr:1;
-                uint64_t reserved_49_63:15;
-#endif
         } s;
         struct cvmx_npi_output_control_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_45_63:19;
                 uint64_t p0_bmode:1;
                 uint64_t reserved_32_43:12;
@@ -1864,25 +1110,8 @@ union cvmx_npi_output_control {
                 uint64_t esr_sl0:2;
                 uint64_t nsr_sl0:1;
                 uint64_t ror_sl0:1;
-#else
-                uint64_t ror_sl0:1;
-                uint64_t nsr_sl0:1;
-                uint64_t esr_sl0:2;
-                uint64_t reserved_4_15:12;
-                uint64_t iptr_o0:1;
-                uint64_t reserved_17_23:7;
-                uint64_t o0_csrm:1;
-                uint64_t reserved_25_27:3;
-                uint64_t o0_ro:1;
-                uint64_t o0_ns:1;
-                uint64_t o0_es:2;
-                uint64_t reserved_32_43:12;
-                uint64_t p0_bmode:1;
-                uint64_t reserved_45_63:19;
-#endif
         } cn30xx;
         struct cvmx_npi_output_control_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_46_63:18;
                 uint64_t p1_bmode:1;
                 uint64_t p0_bmode:1;
@@ -1906,35 +1135,9 @@ union cvmx_npi_output_control {
                 uint64_t esr_sl0:2;
                 uint64_t nsr_sl0:1;
                 uint64_t ror_sl0:1;
-#else
-                uint64_t ror_sl0:1;
-                uint64_t nsr_sl0:1;
-                uint64_t esr_sl0:2;
-                uint64_t ror_sl1:1;
-                uint64_t nsr_sl1:1;
-                uint64_t esr_sl1:2;
-                uint64_t reserved_8_15:8;
-                uint64_t iptr_o0:1;
-                uint64_t iptr_o1:1;
-                uint64_t reserved_18_23:6;
-                uint64_t o0_csrm:1;
-                uint64_t o1_csrm:1;
-                uint64_t reserved_26_27:2;
-                uint64_t o0_ro:1;
-                uint64_t o0_ns:1;
-                uint64_t o0_es:2;
-                uint64_t o1_ro:1;
-                uint64_t o1_ns:1;
-                uint64_t o1_es:2;
-                uint64_t reserved_36_43:8;
-                uint64_t p0_bmode:1;
-                uint64_t p1_bmode:1;
-                uint64_t reserved_46_63:18;
-#endif
         } cn31xx;
         struct cvmx_npi_output_control_s cn38xx;
         struct cvmx_npi_output_control_cn38xxp2 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t p3_bmode:1;
                 uint64_t p2_bmode:1;
@@ -1973,49 +1176,8 @@ union cvmx_npi_output_control {
                 uint64_t esr_sl0:2;
                 uint64_t nsr_sl0:1;
                 uint64_t ror_sl0:1;
-#else
-                uint64_t ror_sl0:1;
-                uint64_t nsr_sl0:1;
-                uint64_t esr_sl0:2;
-                uint64_t ror_sl1:1;
-                uint64_t nsr_sl1:1;
-                uint64_t esr_sl1:2;
-                uint64_t ror_sl2:1;
-                uint64_t nsr_sl2:1;
-                uint64_t esr_sl2:2;
-                uint64_t ror_sl3:1;
-                uint64_t nsr_sl3:1;
-                uint64_t esr_sl3:2;
-                uint64_t iptr_o0:1;
-                uint64_t iptr_o1:1;
-                uint64_t iptr_o2:1;
-                uint64_t iptr_o3:1;
-                uint64_t reserved_20_23:4;
-                uint64_t o0_csrm:1;
-                uint64_t o1_csrm:1;
-                uint64_t o2_csrm:1;
-                uint64_t o3_csrm:1;
-                uint64_t o0_ro:1;
-                uint64_t o0_ns:1;
-                uint64_t o0_es:2;
-                uint64_t o1_ro:1;
-                uint64_t o1_ns:1;
-                uint64_t o1_es:2;
-                uint64_t o2_ro:1;
-                uint64_t o2_ns:1;
-                uint64_t o2_es:2;
-                uint64_t o3_ro:1;
-                uint64_t o3_ns:1;
-                uint64_t o3_es:2;
-                uint64_t p0_bmode:1;
-                uint64_t p1_bmode:1;
-                uint64_t p2_bmode:1;
-                uint64_t p3_bmode:1;
-                uint64_t reserved_48_63:16;
-#endif
         } cn38xxp2;
         struct cvmx_npi_output_control_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_49_63:15;
                 uint64_t pkt_rr:1;
                 uint64_t reserved_46_47:2;
@@ -2041,33 +1203,6 @@ union cvmx_npi_output_control {
                 uint64_t esr_sl0:2;
                 uint64_t nsr_sl0:1;
                 uint64_t ror_sl0:1;
-#else
-                uint64_t ror_sl0:1;
-                uint64_t nsr_sl0:1;
-                uint64_t esr_sl0:2;
-                uint64_t ror_sl1:1;
-                uint64_t nsr_sl1:1;
-                uint64_t esr_sl1:2;
-                uint64_t reserved_8_15:8;
-                uint64_t iptr_o0:1;
-                uint64_t iptr_o1:1;
-                uint64_t reserved_18_23:6;
-                uint64_t o0_csrm:1;
-                uint64_t o1_csrm:1;
-                uint64_t reserved_26_27:2;
-                uint64_t o0_ro:1;
-                uint64_t o0_ns:1;
-                uint64_t o0_es:2;
-                uint64_t o1_ro:1;
-                uint64_t o1_ns:1;
-                uint64_t o1_es:2;
-                uint64_t reserved_36_43:8;
-                uint64_t p0_bmode:1;
-                uint64_t p1_bmode:1;
-                uint64_t reserved_46_47:2;
-                uint64_t pkt_rr:1;
-                uint64_t reserved_49_63:15;
-#endif
         } cn50xx;
         struct cvmx_npi_output_control_s cn58xx;
         struct cvmx_npi_output_control_s cn58xxp1;
@@ -2076,15 +1211,9 @@ union cvmx_npi_output_control {
 union cvmx_npi_px_dbpair_addr {
         uint64_t u64;
         struct cvmx_npi_px_dbpair_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_63_63:1;
                 uint64_t state:2;
                 uint64_t naddr:61;
-#else
-                uint64_t naddr:61;
-                uint64_t state:2;
-                uint64_t reserved_63_63:1;
-#endif
         } s;
         struct cvmx_npi_px_dbpair_addr_s cn30xx;
         struct cvmx_npi_px_dbpair_addr_s cn31xx;
@@ -2098,13 +1227,8 @@ union cvmx_npi_px_dbpair_addr {
 union cvmx_npi_px_instr_addr {
         uint64_t u64;
         struct cvmx_npi_px_instr_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t state:3;
                 uint64_t naddr:61;
-#else
-                uint64_t naddr:61;
-                uint64_t state:3;
-#endif
         } s;
         struct cvmx_npi_px_instr_addr_s cn30xx;
         struct cvmx_npi_px_instr_addr_s cn31xx;
@@ -2118,15 +1242,9 @@ union cvmx_npi_px_instr_addr {
 union cvmx_npi_px_instr_cnts {
         uint64_t u64;
         struct cvmx_npi_px_instr_cnts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_38_63:26;
                 uint64_t fcnt:6;
                 uint64_t avail:32;
-#else
-                uint64_t avail:32;
-                uint64_t fcnt:6;
-                uint64_t reserved_38_63:26;
-#endif
         } s;
         struct cvmx_npi_px_instr_cnts_s cn30xx;
         struct cvmx_npi_px_instr_cnts_s cn31xx;
@@ -2140,15 +1258,9 @@ union cvmx_npi_px_instr_cnts {
 union cvmx_npi_px_pair_cnts {
         uint64_t u64;
         struct cvmx_npi_px_pair_cnts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_37_63:27;
                 uint64_t fcnt:5;
                 uint64_t avail:32;
-#else
-                uint64_t avail:32;
-                uint64_t fcnt:5;
-                uint64_t reserved_37_63:27;
-#endif
         } s;
         struct cvmx_npi_px_pair_cnts_s cn30xx;
         struct cvmx_npi_px_pair_cnts_s cn31xx;
@@ -2162,15 +1274,9 @@ union cvmx_npi_px_pair_cnts {
 union cvmx_npi_pci_burst_size {
         uint64_t u64;
         struct cvmx_npi_pci_burst_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t wr_brst:7;
                 uint64_t rd_brst:7;
-#else
-                uint64_t rd_brst:7;
-                uint64_t wr_brst:7;
-                uint64_t reserved_14_63:50;
-#endif
         } s;
         struct cvmx_npi_pci_burst_size_s cn30xx;
         struct cvmx_npi_pci_burst_size_s cn31xx;
@@ -2184,7 +1290,6 @@ union cvmx_npi_pci_burst_size {
 union cvmx_npi_pci_int_arb_cfg {
         uint64_t u64;
         struct cvmx_npi_pci_int_arb_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_13_63:51;
                 uint64_t hostmode:1;
                 uint64_t pci_ovr:4;
@@ -2192,28 +1297,12 @@ union cvmx_npi_pci_int_arb_cfg {
                 uint64_t en:1;
                 uint64_t park_mod:1;
                 uint64_t park_dev:3;
-#else
-                uint64_t park_dev:3;
-                uint64_t park_mod:1;
-                uint64_t en:1;
-                uint64_t reserved_5_7:3;
-                uint64_t pci_ovr:4;
-                uint64_t hostmode:1;
-                uint64_t reserved_13_63:51;
-#endif
         } s;
         struct cvmx_npi_pci_int_arb_cfg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t en:1;
                 uint64_t park_mod:1;
                 uint64_t park_dev:3;
-#else
-                uint64_t park_dev:3;
-                uint64_t park_mod:1;
-                uint64_t en:1;
-                uint64_t reserved_5_63:59;
-#endif
         } cn30xx;
         struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
         struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
@@ -2226,13 +1315,8 @@ union cvmx_npi_pci_int_arb_cfg {
 union cvmx_npi_pci_read_cmd {
         uint64_t u64;
         struct cvmx_npi_pci_read_cmd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_11_63:53;
                 uint64_t cmd_size:11;
-#else
-                uint64_t cmd_size:11;
-                uint64_t reserved_11_63:53;
-#endif
         } s;
         struct cvmx_npi_pci_read_cmd_s cn30xx;
         struct cvmx_npi_pci_read_cmd_s cn31xx;
@@ -2246,7 +1330,6 @@ union cvmx_npi_pci_read_cmd {
 union cvmx_npi_port32_instr_hdr {
         uint64_t u64;
         struct cvmx_npi_port32_instr_hdr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t pbp:1;
                 uint64_t rsv_f:5;
@@ -2260,21 +1343,6 @@ union cvmx_npi_port32_instr_hdr {
                 uint64_t rsv_b:1;
                 uint64_t skp_len:7;
                 uint64_t rsv_a:6;
-#else
-                uint64_t rsv_a:6;
-                uint64_t skp_len:7;
-                uint64_t rsv_b:1;
-                uint64_t par_mode:2;
-                uint64_t rsv_c:5;
-                uint64_t use_ihdr:1;
-                uint64_t rsv_d:6;
-                uint64_t rskp_len:7;
-                uint64_t rsv_e:1;
-                uint64_t rparmode:2;
-                uint64_t rsv_f:5;
-                uint64_t pbp:1;
-                uint64_t reserved_44_63:20;
-#endif
         } s;
         struct cvmx_npi_port32_instr_hdr_s cn30xx;
         struct cvmx_npi_port32_instr_hdr_s cn31xx;
@@ -2288,7 +1356,6 @@ union cvmx_npi_port32_instr_hdr {
 union cvmx_npi_port33_instr_hdr {
         uint64_t u64;
         struct cvmx_npi_port33_instr_hdr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t pbp:1;
                 uint64_t rsv_f:5;
@@ -2302,21 +1369,6 @@ union cvmx_npi_port33_instr_hdr {
                 uint64_t rsv_b:1;
                 uint64_t skp_len:7;
                 uint64_t rsv_a:6;
-#else
-                uint64_t rsv_a:6;
-                uint64_t skp_len:7;
-                uint64_t rsv_b:1;
-                uint64_t par_mode:2;
-                uint64_t rsv_c:5;
-                uint64_t use_ihdr:1;
-                uint64_t rsv_d:6;
-                uint64_t rskp_len:7;
-                uint64_t rsv_e:1;
-                uint64_t rparmode:2;
-                uint64_t rsv_f:5;
-                uint64_t pbp:1;
-                uint64_t reserved_44_63:20;
-#endif
         } s;
         struct cvmx_npi_port33_instr_hdr_s cn31xx;
         struct cvmx_npi_port33_instr_hdr_s cn38xx;
@@ -2329,7 +1381,6 @@ union cvmx_npi_port33_instr_hdr {
 union cvmx_npi_port34_instr_hdr {
         uint64_t u64;
         struct cvmx_npi_port34_instr_hdr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t pbp:1;
                 uint64_t rsv_f:5;
@@ -2343,21 +1394,6 @@ union cvmx_npi_port34_instr_hdr {
                 uint64_t rsv_b:1;
                 uint64_t skp_len:7;
                 uint64_t rsv_a:6;
-#else
-                uint64_t rsv_a:6;
-                uint64_t skp_len:7;
-                uint64_t rsv_b:1;
-                uint64_t par_mode:2;
-                uint64_t rsv_c:5;
-                uint64_t use_ihdr:1;
-                uint64_t rsv_d:6;
-                uint64_t rskp_len:7;
-                uint64_t rsv_e:1;
-                uint64_t rparmode:2;
-                uint64_t rsv_f:5;
-                uint64_t pbp:1;
-                uint64_t reserved_44_63:20;
-#endif
         } s;
         struct cvmx_npi_port34_instr_hdr_s cn38xx;
         struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
@@ -2368,7 +1404,6 @@ union cvmx_npi_port34_instr_hdr {
 union cvmx_npi_port35_instr_hdr {
         uint64_t u64;
         struct cvmx_npi_port35_instr_hdr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_44_63:20;
                 uint64_t pbp:1;
                 uint64_t rsv_f:5;
@@ -2382,21 +1417,6 @@ union cvmx_npi_port35_instr_hdr {
                 uint64_t rsv_b:1;
                 uint64_t skp_len:7;
                 uint64_t rsv_a:6;
-#else
-                uint64_t rsv_a:6;
-                uint64_t skp_len:7;
-                uint64_t rsv_b:1;
-                uint64_t par_mode:2;
-                uint64_t rsv_c:5;
-                uint64_t use_ihdr:1;
-                uint64_t rsv_d:6;
-                uint64_t rskp_len:7;
-                uint64_t rsv_e:1;
-                uint64_t rparmode:2;
-                uint64_t rsv_f:5;
-                uint64_t pbp:1;
-                uint64_t reserved_44_63:20;
-#endif
         } s;
         struct cvmx_npi_port35_instr_hdr_s cn38xx;
         struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
@@ -2407,15 +1427,9 @@ union cvmx_npi_port35_instr_hdr {
 union cvmx_npi_port_bp_control {
         uint64_t u64;
         struct cvmx_npi_port_bp_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t bp_on:4;
                 uint64_t enb:4;
-#else
-                uint64_t enb:4;
-                uint64_t bp_on:4;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_npi_port_bp_control_s cn30xx;
         struct cvmx_npi_port_bp_control_s cn31xx;
@@ -2429,7 +1443,6 @@ union cvmx_npi_port_bp_control {
 union cvmx_npi_rsl_int_blocks {
         uint64_t u64;
         struct cvmx_npi_rsl_int_blocks_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t rint_31:1;
                 uint64_t iob:1;
@@ -2461,42 +1474,8 @@ union cvmx_npi_rsl_int_blocks {
                 uint64_t gmx1:1;
                 uint64_t gmx0:1;
                 uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t gmx1:1;
-                uint64_t npi:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t dfa:1;
-                uint64_t zip:1;
-                uint64_t rint_8:1;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t reserved_13_14:2;
-                uint64_t rint_15:1;
-                uint64_t l2c:1;
-                uint64_t lmc:1;
-                uint64_t spx0:1;
-                uint64_t spx1:1;
-                uint64_t pip:1;
-                uint64_t rint_21:1;
-                uint64_t asx0:1;
-                uint64_t asx1:1;
-                uint64_t rint_24:1;
-                uint64_t rint_25:1;
-                uint64_t rint_26:1;
-                uint64_t rint_27:1;
-                uint64_t reserved_28_29:2;
-                uint64_t iob:1;
-                uint64_t rint_31:1;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npi_rsl_int_blocks_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t rint_31:1;
                 uint64_t iob:1;
@@ -2530,45 +1509,9 @@ union cvmx_npi_rsl_int_blocks {
                 uint64_t gmx1:1;
                 uint64_t gmx0:1;
                 uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t gmx1:1;
-                uint64_t npi:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t dfa:1;
-                uint64_t zip:1;
-                uint64_t rint_8:1;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t usb:1;
-                uint64_t rint_14:1;
-                uint64_t rint_15:1;
-                uint64_t l2c:1;
-                uint64_t lmc:1;
-                uint64_t spx0:1;
-                uint64_t spx1:1;
-                uint64_t pip:1;
-                uint64_t rint_21:1;
-                uint64_t asx0:1;
-                uint64_t asx1:1;
-                uint64_t rint_24:1;
-                uint64_t rint_25:1;
-                uint64_t rint_26:1;
-                uint64_t rint_27:1;
-                uint64_t rint_28:1;
-                uint64_t rint_29:1;
-                uint64_t iob:1;
-                uint64_t rint_31:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn30xx;
         struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
         struct cvmx_npi_rsl_int_blocks_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t rint_31:1;
                 uint64_t iob:1;
@@ -2602,45 +1545,9 @@ union cvmx_npi_rsl_int_blocks {
                 uint64_t gmx1:1;
                 uint64_t gmx0:1;
                 uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t gmx1:1;
-                uint64_t npi:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t dfa:1;
-                uint64_t zip:1;
-                uint64_t rint_8:1;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t rint_13:1;
-                uint64_t rint_14:1;
-                uint64_t rint_15:1;
-                uint64_t l2c:1;
-                uint64_t lmc:1;
-                uint64_t spx0:1;
-                uint64_t spx1:1;
-                uint64_t pip:1;
-                uint64_t rint_21:1;
-                uint64_t asx0:1;
-                uint64_t asx1:1;
-                uint64_t rint_24:1;
-                uint64_t rint_25:1;
-                uint64_t rint_26:1;
-                uint64_t rint_27:1;
-                uint64_t rint_28:1;
-                uint64_t rint_29:1;
-                uint64_t iob:1;
-                uint64_t rint_31:1;
-                uint64_t reserved_32_63:32;
-#endif
         } cn38xx;
         struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
         struct cvmx_npi_rsl_int_blocks_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_31_63:33;
                 uint64_t iob:1;
                 uint64_t lmc1:1;
@@ -2670,37 +1577,6 @@ union cvmx_npi_rsl_int_blocks {
                 uint64_t gmx1:1;
                 uint64_t gmx0:1;
                 uint64_t mio:1;
-#else
-                uint64_t mio:1;
-                uint64_t gmx0:1;
-                uint64_t gmx1:1;
-                uint64_t npi:1;
-                uint64_t key:1;
-                uint64_t fpa:1;
-                uint64_t dfa:1;
-                uint64_t zip:1;
-                uint64_t reserved_8_8:1;
-                uint64_t ipd:1;
-                uint64_t pko:1;
-                uint64_t tim:1;
-                uint64_t pow:1;
-                uint64_t usb:1;
-                uint64_t rad:1;
-                uint64_t reserved_15_15:1;
-                uint64_t l2c:1;
-                uint64_t lmc:1;
-                uint64_t spx0:1;
-                uint64_t spx1:1;
-                uint64_t pip:1;
-                uint64_t reserved_21_21:1;
-                uint64_t asx0:1;
-                uint64_t asx1:1;
-                uint64_t reserved_24_27:4;
-                uint64_t agl:1;
-                uint64_t lmc1:1;
-                uint64_t iob:1;
-                uint64_t reserved_31_63:33;
-#endif
         } cn50xx;
         struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
         struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
@@ -2709,13 +1585,8 @@ union cvmx_npi_rsl_int_blocks {
 union cvmx_npi_size_inputx {
         uint64_t u64;
         struct cvmx_npi_size_inputx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t size:32;
-#else
-                uint64_t size:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npi_size_inputx_s cn30xx;
         struct cvmx_npi_size_inputx_s cn31xx;
@@ -2729,13 +1600,8 @@ union cvmx_npi_size_inputx {
 union cvmx_npi_win_read_to {
         uint64_t u64;
         struct cvmx_npi_win_read_to_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t time:32;
-#else
-                uint64_t time:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_npi_win_read_to_s cn30xx;
         struct cvmx_npi_win_read_to_s cn31xx;
diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
index 25d603f1829..6ff6d9d357b 100644
--- a/arch/mips/include/asm/octeon/cvmx-pci-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -117,19 +117,11 @@
 union cvmx_pci_bar1_indexx {
         uint32_t u32;
         struct cvmx_pci_bar1_indexx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_18_31:14;
                 uint32_t addr_idx:14;
                 uint32_t ca:1;
                 uint32_t end_swp:2;
                 uint32_t addr_v:1;
-#else
-                uint32_t addr_v:1;
-                uint32_t end_swp:2;
-                uint32_t ca:1;
-                uint32_t addr_idx:14;
-                uint32_t reserved_18_31:14;
-#endif
         } s;
         struct cvmx_pci_bar1_indexx_s cn30xx;
         struct cvmx_pci_bar1_indexx_s cn31xx;
@@ -143,7 +135,6 @@ union cvmx_pci_bar1_indexx {
 union cvmx_pci_bist_reg {
         uint64_t u64;
         struct cvmx_pci_bist_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t rsp_bs:1;
                 uint64_t dma0_bs:1;
@@ -155,19 +146,6 @@ union cvmx_pci_bist_reg {
                 uint64_t csr2n_bs:1;
                 uint64_t dat2n_bs:1;
                 uint64_t dbg2n_bs:1;
-#else
-                uint64_t dbg2n_bs:1;
-                uint64_t dat2n_bs:1;
-                uint64_t csr2n_bs:1;
-                uint64_t rsp2p_bs:1;
-                uint64_t csrr_bs:1;
-                uint64_t csr2p_bs:1;
-                uint64_t cmd_bs:1;
-                uint64_t cmd0_bs:1;
-                uint64_t dma0_bs:1;
-                uint64_t rsp_bs:1;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_pci_bist_reg_s cn50xx;
 };
@@ -175,13 +153,8 @@ union cvmx_pci_bist_reg {
 union cvmx_pci_cfg00 {
         uint32_t u32;
         struct cvmx_pci_cfg00_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t devid:16;
                 uint32_t vendid:16;
-#else
-                uint32_t vendid:16;
-                uint32_t devid:16;
-#endif
         } s;
         struct cvmx_pci_cfg00_s cn30xx;
         struct cvmx_pci_cfg00_s cn31xx;
@@ -195,7 +168,6 @@ union cvmx_pci_cfg00 {
 union cvmx_pci_cfg01 {
         uint32_t u32;
         struct cvmx_pci_cfg01_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t dpe:1;
                 uint32_t sse:1;
                 uint32_t rma:1;
@@ -220,32 +192,6 @@ union cvmx_pci_cfg01 {
                 uint32_t me:1;
                 uint32_t msae:1;
                 uint32_t isae:1;
-#else
-                uint32_t isae:1;
-                uint32_t msae:1;
-                uint32_t me:1;
-                uint32_t scse:1;
-                uint32_t mwice:1;
-                uint32_t vps:1;
-                uint32_t pee:1;
-                uint32_t ads:1;
-                uint32_t see:1;
-                uint32_t fbbe:1;
-                uint32_t i_dis:1;
-                uint32_t reserved_11_18:8;
-                uint32_t i_stat:1;
-                uint32_t cle:1;
-                uint32_t m66:1;
-                uint32_t reserved_22_22:1;
-                uint32_t fbb:1;
-                uint32_t mdpe:1;
-                uint32_t devt:2;
-                uint32_t sta:1;
-                uint32_t rta:1;
-                uint32_t rma:1;
-                uint32_t sse:1;
-                uint32_t dpe:1;
-#endif
         } s;
         struct cvmx_pci_cfg01_s cn30xx;
         struct cvmx_pci_cfg01_s cn31xx;
@@ -259,13 +205,8 @@ union cvmx_pci_cfg01 {
 union cvmx_pci_cfg02 {
         uint32_t u32;
         struct cvmx_pci_cfg02_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t cc:24;
                 uint32_t rid:8;
-#else
-                uint32_t rid:8;
-                uint32_t cc:24;
-#endif
         } s;
         struct cvmx_pci_cfg02_s cn30xx;
         struct cvmx_pci_cfg02_s cn31xx;
@@ -279,7 +220,6 @@ union cvmx_pci_cfg02 {
 union cvmx_pci_cfg03 {
         uint32_t u32;
         struct cvmx_pci_cfg03_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t bcap:1;
                 uint32_t brb:1;
                 uint32_t reserved_28_29:2;
@@ -287,15 +227,6 @@ union cvmx_pci_cfg03 {
                 uint32_t ht:8;
                 uint32_t lt:8;
                 uint32_t cls:8;
-#else
-                uint32_t cls:8;
-                uint32_t lt:8;
-                uint32_t ht:8;
-                uint32_t bcod:4;
-                uint32_t reserved_28_29:2;
-                uint32_t brb:1;
-                uint32_t bcap:1;
-#endif
         } s;
         struct cvmx_pci_cfg03_s cn30xx;
         struct cvmx_pci_cfg03_s cn31xx;
@@ -309,19 +240,11 @@ union cvmx_pci_cfg03 {
 union cvmx_pci_cfg04 {
         uint32_t u32;
         struct cvmx_pci_cfg04_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t lbase:20;
                 uint32_t lbasez:8;
                 uint32_t pf:1;
                 uint32_t typ:2;
                 uint32_t mspc:1;
-#else
-                uint32_t mspc:1;
-                uint32_t typ:2;
-                uint32_t pf:1;
-                uint32_t lbasez:8;
-                uint32_t lbase:20;
-#endif
         } s;
         struct cvmx_pci_cfg04_s cn30xx;
         struct cvmx_pci_cfg04_s cn31xx;
@@ -335,11 +258,7 @@ union cvmx_pci_cfg04 {
 union cvmx_pci_cfg05 {
         uint32_t u32;
         struct cvmx_pci_cfg05_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t hbase:32;
-#else
                 uint32_t hbase:32;
-#endif
         } s;
         struct cvmx_pci_cfg05_s cn30xx;
         struct cvmx_pci_cfg05_s cn31xx;
@@ -353,19 +272,11 @@ union cvmx_pci_cfg05 {
 union cvmx_pci_cfg06 {
         uint32_t u32;
         struct cvmx_pci_cfg06_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t lbase:5;
                 uint32_t lbasez:23;
                 uint32_t pf:1;
                 uint32_t typ:2;
                 uint32_t mspc:1;
-#else
-                uint32_t mspc:1;
-                uint32_t typ:2;
-                uint32_t pf:1;
-                uint32_t lbasez:23;
-                uint32_t lbase:5;
-#endif
         } s;
         struct cvmx_pci_cfg06_s cn30xx;
         struct cvmx_pci_cfg06_s cn31xx;
@@ -379,11 +290,7 @@ union cvmx_pci_cfg06 {
 union cvmx_pci_cfg07 {
         uint32_t u32;
         struct cvmx_pci_cfg07_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t hbase:32;
-#else
                 uint32_t hbase:32;
-#endif
         } s;
         struct cvmx_pci_cfg07_s cn30xx;
         struct cvmx_pci_cfg07_s cn31xx;
@@ -397,17 +304,10 @@ union cvmx_pci_cfg07 {
 union cvmx_pci_cfg08 {
         uint32_t u32;
         struct cvmx_pci_cfg08_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t lbasez:28;
                 uint32_t pf:1;
                 uint32_t typ:2;
                 uint32_t mspc:1;
-#else
-                uint32_t mspc:1;
-                uint32_t typ:2;
-                uint32_t pf:1;
-                uint32_t lbasez:28;
-#endif
         } s;
         struct cvmx_pci_cfg08_s cn30xx;
         struct cvmx_pci_cfg08_s cn31xx;
@@ -421,13 +321,8 @@ union cvmx_pci_cfg08 {
 union cvmx_pci_cfg09 {
         uint32_t u32;
         struct cvmx_pci_cfg09_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t hbase:25;
                 uint32_t hbasez:7;
-#else
-                uint32_t hbasez:7;
-                uint32_t hbase:25;
-#endif
         } s;
         struct cvmx_pci_cfg09_s cn30xx;
         struct cvmx_pci_cfg09_s cn31xx;
@@ -441,11 +336,7 @@ union cvmx_pci_cfg09 {
 union cvmx_pci_cfg10 {
         uint32_t u32;
         struct cvmx_pci_cfg10_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t cisp:32;
-#else
                 uint32_t cisp:32;
-#endif
         } s;
         struct cvmx_pci_cfg10_s cn30xx;
         struct cvmx_pci_cfg10_s cn31xx;
@@ -459,13 +350,8 @@ union cvmx_pci_cfg10 {
 union cvmx_pci_cfg11 {
         uint32_t u32;
         struct cvmx_pci_cfg11_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t ssid:16;
                 uint32_t ssvid:16;
-#else
-                uint32_t ssvid:16;
-                uint32_t ssid:16;
-#endif
         } s;
         struct cvmx_pci_cfg11_s cn30xx;
         struct cvmx_pci_cfg11_s cn31xx;
@@ -479,17 +365,10 @@ union cvmx_pci_cfg11 {
 union cvmx_pci_cfg12 {
         uint32_t u32;
         struct cvmx_pci_cfg12_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t erbar:16;
                 uint32_t erbarz:5;
                 uint32_t reserved_1_10:10;
                 uint32_t erbar_en:1;
-#else
-                uint32_t erbar_en:1;
-                uint32_t reserved_1_10:10;
-                uint32_t erbarz:5;
-                uint32_t erbar:16;
-#endif
         } s;
         struct cvmx_pci_cfg12_s cn30xx;
         struct cvmx_pci_cfg12_s cn31xx;
@@ -503,13 +382,8 @@ union cvmx_pci_cfg12 {
 union cvmx_pci_cfg13 {
         uint32_t u32;
         struct cvmx_pci_cfg13_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_8_31:24;
                 uint32_t cp:8;
-#else
-                uint32_t cp:8;
-                uint32_t reserved_8_31:24;
-#endif
         } s;
         struct cvmx_pci_cfg13_s cn30xx;
         struct cvmx_pci_cfg13_s cn31xx;
@@ -523,17 +397,10 @@ union cvmx_pci_cfg13 {
 union cvmx_pci_cfg15 {
         uint32_t u32;
         struct cvmx_pci_cfg15_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t ml:8;
                 uint32_t mg:8;
                 uint32_t inta:8;
                 uint32_t il:8;
-#else
-                uint32_t il:8;
-                uint32_t inta:8;
-                uint32_t mg:8;
-                uint32_t ml:8;
-#endif
         } s;
         struct cvmx_pci_cfg15_s cn30xx;
         struct cvmx_pci_cfg15_s cn31xx;
@@ -547,7 +414,6 @@ union cvmx_pci_cfg15 {
 union cvmx_pci_cfg16 {
         uint32_t u32;
         struct cvmx_pci_cfg16_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t trdnpr:1;
                 uint32_t trdard:1;
                 uint32_t rdsati:1;
@@ -564,24 +430,6 @@ union cvmx_pci_cfg16 {
                 uint32_t reserved_2_2:1;
                 uint32_t tswc:1;
                 uint32_t mltd:1;
-#else
-                uint32_t mltd:1;
-                uint32_t tswc:1;
-                uint32_t reserved_2_2:1;
-                uint32_t dppmr:1;
-                uint32_t pbe:12;
-                uint32_t tilt:4;
-                uint32_t tslte:3;
-                uint32_t tmae:1;
-                uint32_t twtae:1;
-                uint32_t twsen:1;
-                uint32_t twsei:1;
-                uint32_t trtae:1;
-                uint32_t trdrs:1;
-                uint32_t rdsati:1;
-                uint32_t trdard:1;
-                uint32_t trdnpr:1;
-#endif
         } s;
         struct cvmx_pci_cfg16_s cn30xx;
         struct cvmx_pci_cfg16_s cn31xx;
@@ -595,11 +443,7 @@ union cvmx_pci_cfg16 {
 union cvmx_pci_cfg17 {
         uint32_t u32;
         struct cvmx_pci_cfg17_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t tscme:32;
-#else
-                uint32_t tscme:32;
-#endif
         } s;
         struct cvmx_pci_cfg17_s cn30xx;
         struct cvmx_pci_cfg17_s cn31xx;
@@ -613,11 +457,7 @@ union cvmx_pci_cfg17 {
 union cvmx_pci_cfg18 {
         uint32_t u32;
         struct cvmx_pci_cfg18_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t tdsrps:32;
-#else
                 uint32_t tdsrps:32;
-#endif
         } s;
         struct cvmx_pci_cfg18_s cn30xx;
         struct cvmx_pci_cfg18_s cn31xx;
@@ -631,7 +471,6 @@ union cvmx_pci_cfg18 {
 union cvmx_pci_cfg19 {
         uint32_t u32;
         struct cvmx_pci_cfg19_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t mrbcm:1;
                 uint32_t mrbci:1;
                 uint32_t mdwe:1;
@@ -650,26 +489,6 @@ union cvmx_pci_cfg19 {
                 uint32_t reserved_6_6:1;
                 uint32_t tidomc:1;
                 uint32_t tdomc:5;
-#else
-                uint32_t tdomc:5;
-                uint32_t tidomc:1;
-                uint32_t reserved_6_6:1;
-                uint32_t tibde:1;
-                uint32_t tibcd:1;
-                uint32_t reserved_9_10:2;
-                uint32_t tmapes:1;
-                uint32_t tmdpes:1;
-                uint32_t tmse:1;
-                uint32_t tmei:1;
-                uint32_t teci:1;
-                uint32_t tmes:8;
-                uint32_t mdrrmc:3;
-                uint32_t mdrimc:1;
-                uint32_t mdre:1;
-                uint32_t mdwe:1;
-                uint32_t mrbci:1;
-                uint32_t mrbcm:1;
-#endif
         } s;
         struct cvmx_pci_cfg19_s cn30xx;
         struct cvmx_pci_cfg19_s cn31xx;
@@ -683,11 +502,7 @@ union cvmx_pci_cfg19 {
 union cvmx_pci_cfg20 {
         uint32_t u32;
         struct cvmx_pci_cfg20_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t mdsp:32;
-#else
-                uint32_t mdsp:32;
-#endif
         } s;
         struct cvmx_pci_cfg20_s cn30xx;
         struct cvmx_pci_cfg20_s cn31xx;
@@ -701,11 +516,7 @@ union cvmx_pci_cfg20 {
 union cvmx_pci_cfg21 {
         uint32_t u32;
         struct cvmx_pci_cfg21_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t scmre:32;
-#else
                 uint32_t scmre:32;
-#endif
         } s;
         struct cvmx_pci_cfg21_s cn30xx;
         struct cvmx_pci_cfg21_s cn31xx;
@@ -719,7 +530,6 @@ union cvmx_pci_cfg21 {
 union cvmx_pci_cfg22 {
         uint32_t u32;
         struct cvmx_pci_cfg22_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t mac:7;
                 uint32_t reserved_19_24:6;
                 uint32_t flush:1;
@@ -727,15 +537,6 @@ union cvmx_pci_cfg22 {
                 uint32_t mtta:1;
                 uint32_t mrv:8;
                 uint32_t mttv:8;
-#else
-                uint32_t mttv:8;
-                uint32_t mrv:8;
-                uint32_t mtta:1;
-                uint32_t mra:1;
-                uint32_t flush:1;
-                uint32_t reserved_19_24:6;
-                uint32_t mac:7;
-#endif
         } s;
         struct cvmx_pci_cfg22_s cn30xx;
         struct cvmx_pci_cfg22_s cn31xx;
@@ -749,7 +550,6 @@ union cvmx_pci_cfg22 {
 union cvmx_pci_cfg56 {
         uint32_t u32;
         struct cvmx_pci_cfg56_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_23_31:9;
                 uint32_t most:3;
                 uint32_t mmbc:2;
@@ -757,15 +557,6 @@ union cvmx_pci_cfg56 {
                 uint32_t dpere:1;
                 uint32_t ncp:8;
                 uint32_t pxcid:8;
-#else
-                uint32_t pxcid:8;
-                uint32_t ncp:8;
-                uint32_t dpere:1;
-                uint32_t roe:1;
-                uint32_t mmbc:2;
-                uint32_t most:3;
-                uint32_t reserved_23_31:9;
-#endif
         } s;
         struct cvmx_pci_cfg56_s cn30xx;
         struct cvmx_pci_cfg56_s cn31xx;
@@ -779,7 +570,6 @@ union cvmx_pci_cfg56 {
 union cvmx_pci_cfg57 {
         uint32_t u32;
         struct cvmx_pci_cfg57_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_30_31:2;
                 uint32_t scemr:1;
                 uint32_t mcrsd:3;
@@ -793,21 +583,6 @@ union cvmx_pci_cfg57 {
                 uint32_t bn:8;
                 uint32_t dn:5;
                 uint32_t fn:3;
-#else
-                uint32_t fn:3;
-                uint32_t dn:5;
-                uint32_t bn:8;
-                uint32_t w64:1;
-                uint32_t m133:1;
-                uint32_t scd:1;
-                uint32_t usc:1;
-                uint32_t dc:1;
-                uint32_t mmrbcd:2;
-                uint32_t mostd:3;
-                uint32_t mcrsd:3;
-                uint32_t scemr:1;
-                uint32_t reserved_30_31:2;
-#endif
         } s;
         struct cvmx_pci_cfg57_s cn30xx;
         struct cvmx_pci_cfg57_s cn31xx;
@@ -821,7 +596,6 @@ union cvmx_pci_cfg57 {
 union cvmx_pci_cfg58 {
         uint32_t u32;
         struct cvmx_pci_cfg58_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t pmes:5;
                 uint32_t d2s:1;
                 uint32_t d1s:1;
@@ -832,18 +606,6 @@ union cvmx_pci_cfg58 {
                 uint32_t pcimiv:3;
                 uint32_t ncp:8;
                 uint32_t pmcid:8;
-#else
-                uint32_t pmcid:8;
-                uint32_t ncp:8;
-                uint32_t pcimiv:3;
-                uint32_t pmec:1;
-                uint32_t reserved_20_20:1;
-                uint32_t dsi:1;
-                uint32_t auxc:3;
-                uint32_t d1s:1;
-                uint32_t d2s:1;
-                uint32_t pmes:5;
-#endif
         } s;
         struct cvmx_pci_cfg58_s cn30xx;
         struct cvmx_pci_cfg58_s cn31xx;
@@ -857,7 +619,6 @@ union cvmx_pci_cfg58 {
 union cvmx_pci_cfg59 {
         uint32_t u32;
         struct cvmx_pci_cfg59_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t pmdia:8;
                 uint32_t bpccen:1;
                 uint32_t bd3h:1;
@@ -868,18 +629,6 @@ union cvmx_pci_cfg59 {
                 uint32_t pmeens:1;
                 uint32_t reserved_2_7:6;
                 uint32_t ps:2;
-#else
-                uint32_t ps:2;
-                uint32_t reserved_2_7:6;
-                uint32_t pmeens:1;
-                uint32_t pmds:4;
-                uint32_t pmedsia:2;
-                uint32_t pmess:1;
-                uint32_t reserved_16_21:6;
-                uint32_t bd3h:1;
-                uint32_t bpccen:1;
-                uint32_t pmdia:8;
-#endif
         } s;
         struct cvmx_pci_cfg59_s cn30xx;
         struct cvmx_pci_cfg59_s cn31xx;
@@ -893,7 +642,6 @@ union cvmx_pci_cfg59 {
 union cvmx_pci_cfg60 {
         uint32_t u32;
         struct cvmx_pci_cfg60_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_24_31:8;
                 uint32_t m64:1;
                 uint32_t mme:3;
@@ -901,15 +649,6 @@ union cvmx_pci_cfg60 {
                 uint32_t msien:1;
                 uint32_t ncp:8;
                 uint32_t msicid:8;
-#else
-                uint32_t msicid:8;
-                uint32_t ncp:8;
-                uint32_t msien:1;
-                uint32_t mmc:3;
-                uint32_t mme:3;
-                uint32_t m64:1;
-                uint32_t reserved_24_31:8;
-#endif
         } s;
         struct cvmx_pci_cfg60_s cn30xx;
         struct cvmx_pci_cfg60_s cn31xx;
@@ -923,13 +662,8 @@ union cvmx_pci_cfg60 {
 union cvmx_pci_cfg61 {
         uint32_t u32;
         struct cvmx_pci_cfg61_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t msi31t2:30;
                 uint32_t reserved_0_1:2;
-#else
-                uint32_t reserved_0_1:2;
-                uint32_t msi31t2:30;
-#endif
         } s;
         struct cvmx_pci_cfg61_s cn30xx;
         struct cvmx_pci_cfg61_s cn31xx;
@@ -943,11 +677,7 @@ union cvmx_pci_cfg61 {
 union cvmx_pci_cfg62 {
         uint32_t u32;
         struct cvmx_pci_cfg62_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t msi:32;
-#else
-                uint32_t msi:32;
-#endif
         } s;
         struct cvmx_pci_cfg62_s cn30xx;
         struct cvmx_pci_cfg62_s cn31xx;
@@ -961,13 +691,8 @@ union cvmx_pci_cfg62 {
 union cvmx_pci_cfg63 {
         uint32_t u32;
         struct cvmx_pci_cfg63_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_16_31:16;
                 uint32_t msimd:16;
-#else
-                uint32_t msimd:16;
-                uint32_t reserved_16_31:16;
-#endif
         } s;
         struct cvmx_pci_cfg63_s cn30xx;
         struct cvmx_pci_cfg63_s cn31xx;
@@ -981,21 +706,12 @@ union cvmx_pci_cfg63 {
 union cvmx_pci_cnt_reg {
         uint64_t u64;
         struct cvmx_pci_cnt_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_38_63:26;
                 uint64_t hm_pcix:1;
                 uint64_t hm_speed:2;
                 uint64_t ap_pcix:1;
                 uint64_t ap_speed:2;
                 uint64_t pcicnt:32;
-#else
-                uint64_t pcicnt:32;
-                uint64_t ap_speed:2;
-                uint64_t ap_pcix:1;
-                uint64_t hm_speed:2;
-                uint64_t hm_pcix:1;
-                uint64_t reserved_38_63:26;
-#endif
         } s;
         struct cvmx_pci_cnt_reg_s cn50xx;
         struct cvmx_pci_cnt_reg_s cn58xx;
@@ -1005,7 +721,6 @@ union cvmx_pci_cnt_reg {
 union cvmx_pci_ctl_status_2 {
         uint32_t u32;
         struct cvmx_pci_ctl_status_2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_29_31:3;
                 uint32_t bb1_hole:3;
                 uint32_t bb1_siz:1;
@@ -1028,34 +743,9 @@ union cvmx_pci_ctl_status_2 {
                 uint32_t bar2_enb:1;
                 uint32_t bar2_esx:2;
                 uint32_t bar2_cax:1;
-#else
-                uint32_t bar2_cax:1;
-                uint32_t bar2_esx:2;
-                uint32_t bar2_enb:1;
-                uint32_t tsr_hwm:3;
-                uint32_t pmo_fpc:3;
-                uint32_t pmo_amod:1;
-                uint32_t b12_bist:1;
-                uint32_t ap_64ad:1;
-                uint32_t ap_pcix:1;
-                uint32_t reserved_14_14:1;
-                uint32_t en_wfilt:1;
-                uint32_t scm:1;
-                uint32_t scmtyp:1;
-                uint32_t bar2pres:1;
-                uint32_t erst_n:1;
-                uint32_t bb0:1;
-                uint32_t bb1:1;
-                uint32_t bb_es:2;
-                uint32_t bb_ca:1;
-                uint32_t bb1_siz:1;
-                uint32_t bb1_hole:3;
-                uint32_t reserved_29_31:3;
-#endif
         } s;
         struct cvmx_pci_ctl_status_2_s cn30xx;
         struct cvmx_pci_ctl_status_2_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_20_31:12;
                 uint32_t erst_n:1;
                 uint32_t bar2pres:1;
@@ -1072,24 +762,6 @@ union cvmx_pci_ctl_status_2 {
                 uint32_t bar2_enb:1;
                 uint32_t bar2_esx:2;
                 uint32_t bar2_cax:1;
-#else
-                uint32_t bar2_cax:1;
-                uint32_t bar2_esx:2;
-                uint32_t bar2_enb:1;
-                uint32_t tsr_hwm:3;
-                uint32_t pmo_fpc:3;
-                uint32_t pmo_amod:1;
-                uint32_t b12_bist:1;
-                uint32_t ap_64ad:1;
-                uint32_t ap_pcix:1;
-                uint32_t reserved_14_14:1;
-                uint32_t en_wfilt:1;
-                uint32_t scm:1;
-                uint32_t scmtyp:1;
-                uint32_t bar2pres:1;
-                uint32_t erst_n:1;
-                uint32_t reserved_20_31:12;
-#endif
         } cn31xx;
         struct cvmx_pci_ctl_status_2_s cn38xx;
         struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2;
@@ -1101,13 +773,8 @@ union cvmx_pci_ctl_status_2 {
 union cvmx_pci_dbellx {
         uint32_t u32;
         struct cvmx_pci_dbellx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_16_31:16;
                 uint32_t inc_val:16;
-#else
-                uint32_t inc_val:16;
-                uint32_t reserved_16_31:16;
-#endif
         } s;
         struct cvmx_pci_dbellx_s cn30xx;
         struct cvmx_pci_dbellx_s cn31xx;
@@ -1121,11 +788,7 @@ union cvmx_pci_dbellx {
 union cvmx_pci_dma_cntx {
         uint32_t u32;
         struct cvmx_pci_dma_cntx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t dma_cnt:32;
-#else
                 uint32_t dma_cnt:32;
-#endif
         } s;
         struct cvmx_pci_dma_cntx_s cn30xx;
         struct cvmx_pci_dma_cntx_s cn31xx;
@@ -1139,11 +802,7 @@ union cvmx_pci_dma_cntx {
 union cvmx_pci_dma_int_levx {
         uint32_t u32;
         struct cvmx_pci_dma_int_levx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t pkt_cnt:32;
-#else
-                uint32_t pkt_cnt:32;
-#endif
         } s;
         struct cvmx_pci_dma_int_levx_s cn30xx;
         struct cvmx_pci_dma_int_levx_s cn31xx;
@@ -1157,11 +816,7 @@ union cvmx_pci_dma_int_levx {
 union cvmx_pci_dma_timex {
         uint32_t u32;
         struct cvmx_pci_dma_timex_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t dma_time:32;
-#else
                 uint32_t dma_time:32;
-#endif
         } s;
         struct cvmx_pci_dma_timex_s cn30xx;
         struct cvmx_pci_dma_timex_s cn31xx;
@@ -1175,11 +830,7 @@ union cvmx_pci_dma_timex {
 union cvmx_pci_instr_countx {
         uint32_t u32;
         struct cvmx_pci_instr_countx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t icnt:32;
-#else
                 uint32_t icnt:32;
-#endif
         } s;
         struct cvmx_pci_instr_countx_s cn30xx;
         struct cvmx_pci_instr_countx_s cn31xx;
@@ -1193,7 +844,6 @@ union cvmx_pci_instr_countx {
 union cvmx_pci_int_enb {
         uint64_t u64;
         struct cvmx_pci_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1229,46 +879,8 @@ union cvmx_pci_int_enb {
                 uint64_t imr_wtto:1;
                 uint64_t imr_wabt:1;
                 uint64_t itr_wabt:1;
-#else
-                uint64_t itr_wabt:1;
-                uint64_t imr_wabt:1;
-                uint64_t imr_wtto:1;
-                uint64_t itr_abt:1;
-                uint64_t imr_abt:1;
-                uint64_t imr_tto:1;
-                uint64_t imsi_per:1;
-                uint64_t imsi_tabt:1;
-                uint64_t imsi_mabt:1;
-                uint64_t imsc_msg:1;
-                uint64_t itsr_abt:1;
-                uint64_t iserr:1;
-                uint64_t iaperr:1;
-                uint64_t idperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t irsl_int:1;
-                uint64_t ipcnt0:1;
-                uint64_t ipcnt1:1;
-                uint64_t ipcnt2:1;
-                uint64_t ipcnt3:1;
-                uint64_t iptime0:1;
-                uint64_t iptime1:1;
-                uint64_t iptime2:1;
-                uint64_t iptime3:1;
-                uint64_t idcnt0:1;
-                uint64_t idcnt1:1;
-                uint64_t idtime0:1;
-                uint64_t idtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_pci_int_enb_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1300,42 +912,8 @@ union cvmx_pci_int_enb {
                 uint64_t imr_wtto:1;
                 uint64_t imr_wabt:1;
                 uint64_t itr_wabt:1;
-#else
-                uint64_t itr_wabt:1;
-                uint64_t imr_wabt:1;
-                uint64_t imr_wtto:1;
-                uint64_t itr_abt:1;
-                uint64_t imr_abt:1;
-                uint64_t imr_tto:1;
-                uint64_t imsi_per:1;
-                uint64_t imsi_tabt:1;
-                uint64_t imsi_mabt:1;
-                uint64_t imsc_msg:1;
-                uint64_t itsr_abt:1;
-                uint64_t iserr:1;
-                uint64_t iaperr:1;
-                uint64_t idperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t irsl_int:1;
-                uint64_t ipcnt0:1;
-                uint64_t reserved_18_20:3;
-                uint64_t iptime0:1;
-                uint64_t reserved_22_24:3;
-                uint64_t idcnt0:1;
-                uint64_t idcnt1:1;
-                uint64_t idtime0:1;
-                uint64_t idtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn30xx;
         struct cvmx_pci_int_enb_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1369,41 +947,6 @@ union cvmx_pci_int_enb {
                 uint64_t imr_wtto:1;
                 uint64_t imr_wabt:1;
                 uint64_t itr_wabt:1;
-#else
-                uint64_t itr_wabt:1;
-                uint64_t imr_wabt:1;
-                uint64_t imr_wtto:1;
-                uint64_t itr_abt:1;
-                uint64_t imr_abt:1;
-                uint64_t imr_tto:1;
-                uint64_t imsi_per:1;
-                uint64_t imsi_tabt:1;
-                uint64_t imsi_mabt:1;
-                uint64_t imsc_msg:1;
-                uint64_t itsr_abt:1;
-                uint64_t iserr:1;
-                uint64_t iaperr:1;
-                uint64_t idperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t irsl_int:1;
-                uint64_t ipcnt0:1;
-                uint64_t ipcnt1:1;
-                uint64_t reserved_19_20:2;
-                uint64_t iptime0:1;
-                uint64_t iptime1:1;
-                uint64_t reserved_23_24:2;
-                uint64_t idcnt0:1;
-                uint64_t idcnt1:1;
-                uint64_t idtime0:1;
-                uint64_t idtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn31xx;
         struct cvmx_pci_int_enb_s cn38xx;
         struct cvmx_pci_int_enb_s cn38xxp2;
@@ -1415,7 +958,6 @@ union cvmx_pci_int_enb {
 union cvmx_pci_int_enb2 {
         uint64_t u64;
         struct cvmx_pci_int_enb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1451,46 +993,8 @@ union cvmx_pci_int_enb2 {
                 uint64_t rmr_wtto:1;
                 uint64_t rmr_wabt:1;
                 uint64_t rtr_wabt:1;
-#else
-                uint64_t rtr_wabt:1;
-                uint64_t rmr_wabt:1;
-                uint64_t rmr_wtto:1;
-                uint64_t rtr_abt:1;
-                uint64_t rmr_abt:1;
-                uint64_t rmr_tto:1;
-                uint64_t rmsi_per:1;
-                uint64_t rmsi_tabt:1;
-                uint64_t rmsi_mabt:1;
-                uint64_t rmsc_msg:1;
-                uint64_t rtsr_abt:1;
-                uint64_t rserr:1;
-                uint64_t raperr:1;
-                uint64_t rdperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t rrsl_int:1;
-                uint64_t rpcnt0:1;
-                uint64_t rpcnt1:1;
-                uint64_t rpcnt2:1;
-                uint64_t rpcnt3:1;
-                uint64_t rptime0:1;
-                uint64_t rptime1:1;
-                uint64_t rptime2:1;
-                uint64_t rptime3:1;
-                uint64_t rdcnt0:1;
-                uint64_t rdcnt1:1;
-                uint64_t rdtime0:1;
-                uint64_t rdtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_pci_int_enb2_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1522,42 +1026,8 @@ union cvmx_pci_int_enb2 {
                 uint64_t rmr_wtto:1;
                 uint64_t rmr_wabt:1;
                 uint64_t rtr_wabt:1;
-#else
-                uint64_t rtr_wabt:1;
-                uint64_t rmr_wabt:1;
-                uint64_t rmr_wtto:1;
-                uint64_t rtr_abt:1;
-                uint64_t rmr_abt:1;
-                uint64_t rmr_tto:1;
-                uint64_t rmsi_per:1;
-                uint64_t rmsi_tabt:1;
-                uint64_t rmsi_mabt:1;
-                uint64_t rmsc_msg:1;
-                uint64_t rtsr_abt:1;
-                uint64_t rserr:1;
-                uint64_t raperr:1;
-                uint64_t rdperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t rrsl_int:1;
-                uint64_t rpcnt0:1;
-                uint64_t reserved_18_20:3;
-                uint64_t rptime0:1;
-                uint64_t reserved_22_24:3;
-                uint64_t rdcnt0:1;
-                uint64_t rdcnt1:1;
-                uint64_t rdtime0:1;
-                uint64_t rdtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn30xx;
         struct cvmx_pci_int_enb2_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1591,41 +1061,6 @@ union cvmx_pci_int_enb2 {
                 uint64_t rmr_wtto:1;
                 uint64_t rmr_wabt:1;
                 uint64_t rtr_wabt:1;
-#else
-                uint64_t rtr_wabt:1;
-                uint64_t rmr_wabt:1;
-                uint64_t rmr_wtto:1;
-                uint64_t rtr_abt:1;
-                uint64_t rmr_abt:1;
-                uint64_t rmr_tto:1;
-                uint64_t rmsi_per:1;
-                uint64_t rmsi_tabt:1;
-                uint64_t rmsi_mabt:1;
-                uint64_t rmsc_msg:1;
-                uint64_t rtsr_abt:1;
-                uint64_t rserr:1;
-                uint64_t raperr:1;
-                uint64_t rdperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t rrsl_int:1;
-                uint64_t rpcnt0:1;
-                uint64_t rpcnt1:1;
-                uint64_t reserved_19_20:2;
-                uint64_t rptime0:1;
-                uint64_t rptime1:1;
-                uint64_t reserved_23_24:2;
-                uint64_t rdcnt0:1;
-                uint64_t rdcnt1:1;
-                uint64_t rdtime0:1;
-                uint64_t rdtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn31xx;
         struct cvmx_pci_int_enb2_s cn38xx;
         struct cvmx_pci_int_enb2_s cn38xxp2;
@@ -1637,7 +1072,6 @@ union cvmx_pci_int_enb2 {
 union cvmx_pci_int_sum {
         uint64_t u64;
         struct cvmx_pci_int_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1673,46 +1107,8 @@ union cvmx_pci_int_sum {
                 uint64_t mr_wtto:1;
                 uint64_t mr_wabt:1;
                 uint64_t tr_wabt:1;
-#else
-                uint64_t tr_wabt:1;
-                uint64_t mr_wabt:1;
-                uint64_t mr_wtto:1;
-                uint64_t tr_abt:1;
-                uint64_t mr_abt:1;
-                uint64_t mr_tto:1;
-                uint64_t msi_per:1;
-                uint64_t msi_tabt:1;
-                uint64_t msi_mabt:1;
-                uint64_t msc_msg:1;
-                uint64_t tsr_abt:1;
-                uint64_t serr:1;
-                uint64_t aperr:1;
-                uint64_t dperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t rsl_int:1;
-                uint64_t pcnt0:1;
-                uint64_t pcnt1:1;
-                uint64_t pcnt2:1;
-                uint64_t pcnt3:1;
-                uint64_t ptime0:1;
-                uint64_t ptime1:1;
-                uint64_t ptime2:1;
-                uint64_t ptime3:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_pci_int_sum_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1744,42 +1140,8 @@ union cvmx_pci_int_sum {
                 uint64_t mr_wtto:1;
                 uint64_t mr_wabt:1;
                 uint64_t tr_wabt:1;
-#else
-                uint64_t tr_wabt:1;
-                uint64_t mr_wabt:1;
-                uint64_t mr_wtto:1;
-                uint64_t tr_abt:1;
-                uint64_t mr_abt:1;
-                uint64_t mr_tto:1;
-                uint64_t msi_per:1;
-                uint64_t msi_tabt:1;
-                uint64_t msi_mabt:1;
-                uint64_t msc_msg:1;
-                uint64_t tsr_abt:1;
-                uint64_t serr:1;
-                uint64_t aperr:1;
-                uint64_t dperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t rsl_int:1;
-                uint64_t pcnt0:1;
-                uint64_t reserved_18_20:3;
-                uint64_t ptime0:1;
-                uint64_t reserved_22_24:3;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn30xx;
         struct cvmx_pci_int_sum_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1813,41 +1175,6 @@ union cvmx_pci_int_sum {
                 uint64_t mr_wtto:1;
                 uint64_t mr_wabt:1;
                 uint64_t tr_wabt:1;
-#else
-                uint64_t tr_wabt:1;
-                uint64_t mr_wabt:1;
-                uint64_t mr_wtto:1;
-                uint64_t tr_abt:1;
-                uint64_t mr_abt:1;
-                uint64_t mr_tto:1;
-                uint64_t msi_per:1;
-                uint64_t msi_tabt:1;
-                uint64_t msi_mabt:1;
-                uint64_t msc_msg:1;
-                uint64_t tsr_abt:1;
-                uint64_t serr:1;
-                uint64_t aperr:1;
-                uint64_t dperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t rsl_int:1;
-                uint64_t pcnt0:1;
-                uint64_t pcnt1:1;
-                uint64_t reserved_19_20:2;
-                uint64_t ptime0:1;
-                uint64_t ptime1:1;
-                uint64_t reserved_23_24:2;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn31xx;
         struct cvmx_pci_int_sum_s cn38xx;
         struct cvmx_pci_int_sum_s cn38xxp2;
@@ -1859,7 +1186,6 @@ union cvmx_pci_int_sum {
 union cvmx_pci_int_sum2 {
         uint64_t u64;
         struct cvmx_pci_int_sum2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1895,46 +1221,8 @@ union cvmx_pci_int_sum2 {
                 uint64_t mr_wtto:1;
                 uint64_t mr_wabt:1;
                 uint64_t tr_wabt:1;
-#else
-                uint64_t tr_wabt:1;
-                uint64_t mr_wabt:1;
-                uint64_t mr_wtto:1;
-                uint64_t tr_abt:1;
-                uint64_t mr_abt:1;
-                uint64_t mr_tto:1;
-                uint64_t msi_per:1;
-                uint64_t msi_tabt:1;
-                uint64_t msi_mabt:1;
-                uint64_t msc_msg:1;
-                uint64_t tsr_abt:1;
-                uint64_t serr:1;
-                uint64_t aperr:1;
-                uint64_t dperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t rsl_int:1;
-                uint64_t pcnt0:1;
-                uint64_t pcnt1:1;
-                uint64_t pcnt2:1;
-                uint64_t pcnt3:1;
-                uint64_t ptime0:1;
-                uint64_t ptime1:1;
-                uint64_t ptime2:1;
-                uint64_t ptime3:1;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } s;
         struct cvmx_pci_int_sum2_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -1966,42 +1254,8 @@ union cvmx_pci_int_sum2 {
                 uint64_t mr_wtto:1;
                 uint64_t mr_wabt:1;
                 uint64_t tr_wabt:1;
-#else
-                uint64_t tr_wabt:1;
-                uint64_t mr_wabt:1;
-                uint64_t mr_wtto:1;
-                uint64_t tr_abt:1;
-                uint64_t mr_abt:1;
-                uint64_t mr_tto:1;
-                uint64_t msi_per:1;
-                uint64_t msi_tabt:1;
-                uint64_t msi_mabt:1;
-                uint64_t msc_msg:1;
-                uint64_t tsr_abt:1;
-                uint64_t serr:1;
-                uint64_t aperr:1;
-                uint64_t dperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t rsl_int:1;
-                uint64_t pcnt0:1;
-                uint64_t reserved_18_20:3;
-                uint64_t ptime0:1;
-                uint64_t reserved_22_24:3;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn30xx;
         struct cvmx_pci_int_sum2_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_34_63:30;
                 uint64_t ill_rd:1;
                 uint64_t ill_wr:1;
@@ -2035,41 +1289,6 @@ union cvmx_pci_int_sum2 {
                 uint64_t mr_wtto:1;
                 uint64_t mr_wabt:1;
                 uint64_t tr_wabt:1;
-#else
-                uint64_t tr_wabt:1;
-                uint64_t mr_wabt:1;
-                uint64_t mr_wtto:1;
-                uint64_t tr_abt:1;
-                uint64_t mr_abt:1;
-                uint64_t mr_tto:1;
-                uint64_t msi_per:1;
-                uint64_t msi_tabt:1;
-                uint64_t msi_mabt:1;
-                uint64_t msc_msg:1;
-                uint64_t tsr_abt:1;
-                uint64_t serr:1;
-                uint64_t aperr:1;
-                uint64_t dperr:1;
-                uint64_t ill_rwr:1;
-                uint64_t ill_rrd:1;
-                uint64_t rsl_int:1;
-                uint64_t pcnt0:1;
-                uint64_t pcnt1:1;
-                uint64_t reserved_19_20:2;
-                uint64_t ptime0:1;
-                uint64_t ptime1:1;
-                uint64_t reserved_23_24:2;
-                uint64_t dcnt0:1;
-                uint64_t dcnt1:1;
-                uint64_t dtime0:1;
-                uint64_t dtime1:1;
-                uint64_t dma0_fi:1;
-                uint64_t dma1_fi:1;
-                uint64_t win_wr:1;
-                uint64_t ill_wr:1;
-                uint64_t ill_rd:1;
-                uint64_t reserved_34_63:30;
-#endif
         } cn31xx;
         struct cvmx_pci_int_sum2_s cn38xx;
         struct cvmx_pci_int_sum2_s cn38xxp2;
@@ -2081,13 +1300,8 @@ union cvmx_pci_int_sum2 {
 union cvmx_pci_msi_rcv {
         uint32_t u32;
         struct cvmx_pci_msi_rcv_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_6_31:26;
                 uint32_t intr:6;
-#else
-                uint32_t intr:6;
-                uint32_t reserved_6_31:26;
-#endif
         } s;
         struct cvmx_pci_msi_rcv_s cn30xx;
         struct cvmx_pci_msi_rcv_s cn31xx;
@@ -2101,13 +1315,8 @@ union cvmx_pci_msi_rcv {
 union cvmx_pci_pkt_creditsx {
         uint32_t u32;
         struct cvmx_pci_pkt_creditsx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t pkt_cnt:16;
                 uint32_t ptr_cnt:16;
-#else
-                uint32_t ptr_cnt:16;
-                uint32_t pkt_cnt:16;
-#endif
         } s;
         struct cvmx_pci_pkt_creditsx_s cn30xx;
         struct cvmx_pci_pkt_creditsx_s cn31xx;
@@ -2121,11 +1330,7 @@ union cvmx_pci_pkt_creditsx {
 union cvmx_pci_pkts_sentx {
         uint32_t u32;
         struct cvmx_pci_pkts_sentx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t pkt_cnt:32;
-#else
-                uint32_t pkt_cnt:32;
-#endif
         } s;
         struct cvmx_pci_pkts_sentx_s cn30xx;
         struct cvmx_pci_pkts_sentx_s cn31xx;
@@ -2139,11 +1344,7 @@ union cvmx_pci_pkts_sentx {
 union cvmx_pci_pkts_sent_int_levx {
         uint32_t u32;
         struct cvmx_pci_pkts_sent_int_levx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t pkt_cnt:32;
-#else
                 uint32_t pkt_cnt:32;
-#endif
         } s;
         struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
         struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
@@ -2157,11 +1358,7 @@ union cvmx_pci_pkts_sent_int_levx {
 union cvmx_pci_pkts_sent_timex {
         uint32_t u32;
         struct cvmx_pci_pkts_sent_timex_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t pkt_time:32;
-#else
                 uint32_t pkt_time:32;
-#endif
         } s;
         struct cvmx_pci_pkts_sent_timex_s cn30xx;
         struct cvmx_pci_pkts_sent_timex_s cn31xx;
@@ -2175,15 +1372,9 @@ union cvmx_pci_pkts_sent_timex {
 union cvmx_pci_read_cmd_6 {
         uint32_t u32;
         struct cvmx_pci_read_cmd_6_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_9_31:23;
                 uint32_t min_data:6;
                 uint32_t prefetch:3;
-#else
-                uint32_t prefetch:3;
-                uint32_t min_data:6;
-                uint32_t reserved_9_31:23;
-#endif
         } s;
         struct cvmx_pci_read_cmd_6_s cn30xx;
         struct cvmx_pci_read_cmd_6_s cn31xx;
@@ -2197,15 +1388,9 @@ union cvmx_pci_read_cmd_6 {
 union cvmx_pci_read_cmd_c {
         uint32_t u32;
         struct cvmx_pci_read_cmd_c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_9_31:23;
                 uint32_t min_data:6;
                 uint32_t prefetch:3;
-#else
-                uint32_t prefetch:3;
-                uint32_t min_data:6;
-                uint32_t reserved_9_31:23;
-#endif
         } s;
         struct cvmx_pci_read_cmd_c_s cn30xx;
         struct cvmx_pci_read_cmd_c_s cn31xx;
@@ -2219,15 +1404,9 @@ union cvmx_pci_read_cmd_c {
 union cvmx_pci_read_cmd_e {
         uint32_t u32;
         struct cvmx_pci_read_cmd_e_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_9_31:23;
                 uint32_t min_data:6;
                 uint32_t prefetch:3;
-#else
-                uint32_t prefetch:3;
-                uint32_t min_data:6;
-                uint32_t reserved_9_31:23;
-#endif
         } s;
         struct cvmx_pci_read_cmd_e_s cn30xx;
         struct cvmx_pci_read_cmd_e_s cn31xx;
@@ -2241,15 +1420,9 @@ union cvmx_pci_read_cmd_e {
 union cvmx_pci_read_timeout {
         uint64_t u64;
         struct cvmx_pci_read_timeout_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t enb:1;
                 uint64_t cnt:31;
-#else
-                uint64_t cnt:31;
-                uint64_t enb:1;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pci_read_timeout_s cn30xx;
         struct cvmx_pci_read_timeout_s cn31xx;
@@ -2263,13 +1436,8 @@ union cvmx_pci_read_timeout {
 union cvmx_pci_scm_reg {
         uint64_t u64;
         struct cvmx_pci_scm_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t scm:32;
-#else
-                uint64_t scm:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pci_scm_reg_s cn30xx;
         struct cvmx_pci_scm_reg_s cn31xx;
@@ -2283,13 +1451,8 @@ union cvmx_pci_scm_reg {
 union cvmx_pci_tsr_reg {
         uint64_t u64;
         struct cvmx_pci_tsr_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_36_63:28;
                 uint64_t tsr:36;
-#else
-                uint64_t tsr:36;
-                uint64_t reserved_36_63:28;
-#endif
         } s;
         struct cvmx_pci_tsr_reg_s cn30xx;
         struct cvmx_pci_tsr_reg_s cn31xx;
@@ -2303,42 +1466,22 @@ union cvmx_pci_tsr_reg {
 union cvmx_pci_win_rd_addr {
         uint64_t u64;
         struct cvmx_pci_win_rd_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_49_63:15;
                 uint64_t iobit:1;
                 uint64_t reserved_0_47:48;
-#else
-                uint64_t reserved_0_47:48;
-                uint64_t iobit:1;
-                uint64_t reserved_49_63:15;
-#endif
         } s;
         struct cvmx_pci_win_rd_addr_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_49_63:15;
                 uint64_t iobit:1;
                 uint64_t rd_addr:46;
                 uint64_t reserved_0_1:2;
-#else
-                uint64_t reserved_0_1:2;
-                uint64_t rd_addr:46;
-                uint64_t iobit:1;
-                uint64_t reserved_49_63:15;
-#endif
         } cn30xx;
         struct cvmx_pci_win_rd_addr_cn30xx cn31xx;
         struct cvmx_pci_win_rd_addr_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_49_63:15;
                 uint64_t iobit:1;
                 uint64_t rd_addr:45;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t rd_addr:45;
-                uint64_t iobit:1;
-                uint64_t reserved_49_63:15;
-#endif
         } cn38xx;
         struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2;
         struct cvmx_pci_win_rd_addr_cn30xx cn50xx;
@@ -2349,11 +1492,7 @@ union cvmx_pci_win_rd_addr {
 union cvmx_pci_win_rd_data {
         uint64_t u64;
         struct cvmx_pci_win_rd_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rd_data:64;
-#else
                 uint64_t rd_data:64;
-#endif
         } s;
         struct cvmx_pci_win_rd_data_s cn30xx;
         struct cvmx_pci_win_rd_data_s cn31xx;
@@ -2367,17 +1506,10 @@ union cvmx_pci_win_rd_data {
 union cvmx_pci_win_wr_addr {
         uint64_t u64;
         struct cvmx_pci_win_wr_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_49_63:15;
                 uint64_t iobit:1;
                 uint64_t wr_addr:45;
                 uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t wr_addr:45;
-                uint64_t iobit:1;
-                uint64_t reserved_49_63:15;
-#endif
         } s;
         struct cvmx_pci_win_wr_addr_s cn30xx;
         struct cvmx_pci_win_wr_addr_s cn31xx;
@@ -2391,11 +1523,7 @@ union cvmx_pci_win_wr_addr {
 union cvmx_pci_win_wr_data {
         uint64_t u64;
         struct cvmx_pci_win_wr_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t wr_data:64;
-#else
-                uint64_t wr_data:64;
-#endif
         } s;
         struct cvmx_pci_win_wr_data_s cn30xx;
         struct cvmx_pci_win_wr_data_s cn31xx;
@@ -2409,13 +1537,8 @@ union cvmx_pci_win_wr_data {
 union cvmx_pci_win_wr_mask {
         uint64_t u64;
         struct cvmx_pci_win_wr_mask_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t wr_mask:8;
-#else
-                uint64_t wr_mask:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_pci_win_wr_mask_s cn30xx;
         struct cvmx_pci_win_wr_mask_s cn31xx;
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index 4bce393391e..f8cb88902ef 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -109,31 +109,20 @@
 union cvmx_pciercx_cfg000 {
         uint32_t u32;
         struct cvmx_pciercx_cfg000_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t devid:16;
                 uint32_t vendid:16;
-#else
-                uint32_t vendid:16;
-                uint32_t devid:16;
-#endif
         } s;
         struct cvmx_pciercx_cfg000_s cn52xx;
         struct cvmx_pciercx_cfg000_s cn52xxp1;
         struct cvmx_pciercx_cfg000_s cn56xx;
         struct cvmx_pciercx_cfg000_s cn56xxp1;
-        struct cvmx_pciercx_cfg000_s cn61xx;
         struct cvmx_pciercx_cfg000_s cn63xx;
         struct cvmx_pciercx_cfg000_s cn63xxp1;
-        struct cvmx_pciercx_cfg000_s cn66xx;
-        struct cvmx_pciercx_cfg000_s cn68xx;
-        struct cvmx_pciercx_cfg000_s cn68xxp1;
-        struct cvmx_pciercx_cfg000_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg001 {
         uint32_t u32;
         struct cvmx_pciercx_cfg001_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t dpe:1;
                 uint32_t sse:1;
                 uint32_t rma:1;
@@ -158,180 +147,93 @@ union cvmx_pciercx_cfg001 {
                 uint32_t me:1;
                 uint32_t msae:1;
                 uint32_t isae:1;
-#else
-                uint32_t isae:1;
-                uint32_t msae:1;
-                uint32_t me:1;
-                uint32_t scse:1;
-                uint32_t mwice:1;
-                uint32_t vps:1;
-                uint32_t per:1;
-                uint32_t ids_wcc:1;
-                uint32_t see:1;
-                uint32_t fbbe:1;
-                uint32_t i_dis:1;
-                uint32_t reserved_11_18:8;
-                uint32_t i_stat:1;
-                uint32_t cl:1;
-                uint32_t m66:1;
-                uint32_t reserved_22_22:1;
-                uint32_t fbb:1;
-                uint32_t mdpe:1;
-                uint32_t devt:2;
-                uint32_t sta:1;
-                uint32_t rta:1;
-                uint32_t rma:1;
-                uint32_t sse:1;
-                uint32_t dpe:1;
-#endif
         } s;
         struct cvmx_pciercx_cfg001_s cn52xx;
         struct cvmx_pciercx_cfg001_s cn52xxp1;
         struct cvmx_pciercx_cfg001_s cn56xx;
         struct cvmx_pciercx_cfg001_s cn56xxp1;
-        struct cvmx_pciercx_cfg001_s cn61xx;
         struct cvmx_pciercx_cfg001_s cn63xx;
         struct cvmx_pciercx_cfg001_s cn63xxp1;
-        struct cvmx_pciercx_cfg001_s cn66xx;
-        struct cvmx_pciercx_cfg001_s cn68xx;
-        struct cvmx_pciercx_cfg001_s cn68xxp1;
-        struct cvmx_pciercx_cfg001_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg002 {
         uint32_t u32;
         struct cvmx_pciercx_cfg002_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t bcc:8;
                 uint32_t sc:8;
                 uint32_t pi:8;
                 uint32_t rid:8;
-#else
-                uint32_t rid:8;
-                uint32_t pi:8;
-                uint32_t sc:8;
-                uint32_t bcc:8;
-#endif
         } s;
         struct cvmx_pciercx_cfg002_s cn52xx;
         struct cvmx_pciercx_cfg002_s cn52xxp1;
         struct cvmx_pciercx_cfg002_s cn56xx;
         struct cvmx_pciercx_cfg002_s cn56xxp1;
-        struct cvmx_pciercx_cfg002_s cn61xx;
         struct cvmx_pciercx_cfg002_s cn63xx;
         struct cvmx_pciercx_cfg002_s cn63xxp1;
-        struct cvmx_pciercx_cfg002_s cn66xx;
-        struct cvmx_pciercx_cfg002_s cn68xx;
-        struct cvmx_pciercx_cfg002_s cn68xxp1;
-        struct cvmx_pciercx_cfg002_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg003 {
         uint32_t u32;
         struct cvmx_pciercx_cfg003_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t bist:8;
                 uint32_t mfd:1;
                 uint32_t chf:7;
                 uint32_t lt:8;
                 uint32_t cls:8;
-#else
-                uint32_t cls:8;
-                uint32_t lt:8;
-                uint32_t chf:7;
-                uint32_t mfd:1;
-                uint32_t bist:8;
-#endif
         } s;
         struct cvmx_pciercx_cfg003_s cn52xx;
         struct cvmx_pciercx_cfg003_s cn52xxp1;
         struct cvmx_pciercx_cfg003_s cn56xx;
         struct cvmx_pciercx_cfg003_s cn56xxp1;
-        struct cvmx_pciercx_cfg003_s cn61xx;
         struct cvmx_pciercx_cfg003_s cn63xx;
         struct cvmx_pciercx_cfg003_s cn63xxp1;
-        struct cvmx_pciercx_cfg003_s cn66xx;
-        struct cvmx_pciercx_cfg003_s cn68xx;
-        struct cvmx_pciercx_cfg003_s cn68xxp1;
-        struct cvmx_pciercx_cfg003_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg004 {
         uint32_t u32;
         struct cvmx_pciercx_cfg004_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_0_31:32;
-#else
                 uint32_t reserved_0_31:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg004_s cn52xx;
         struct cvmx_pciercx_cfg004_s cn52xxp1;
         struct cvmx_pciercx_cfg004_s cn56xx;
         struct cvmx_pciercx_cfg004_s cn56xxp1;
-        struct cvmx_pciercx_cfg004_s cn61xx;
         struct cvmx_pciercx_cfg004_s cn63xx;
         struct cvmx_pciercx_cfg004_s cn63xxp1;
-        struct cvmx_pciercx_cfg004_s cn66xx;
-        struct cvmx_pciercx_cfg004_s cn68xx;
-        struct cvmx_pciercx_cfg004_s cn68xxp1;
-        struct cvmx_pciercx_cfg004_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg005 {
         uint32_t u32;
         struct cvmx_pciercx_cfg005_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_0_31:32;
-#else
                 uint32_t reserved_0_31:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg005_s cn52xx;
         struct cvmx_pciercx_cfg005_s cn52xxp1;
         struct cvmx_pciercx_cfg005_s cn56xx;
         struct cvmx_pciercx_cfg005_s cn56xxp1;
-        struct cvmx_pciercx_cfg005_s cn61xx;
         struct cvmx_pciercx_cfg005_s cn63xx;
         struct cvmx_pciercx_cfg005_s cn63xxp1;
-        struct cvmx_pciercx_cfg005_s cn66xx;
-        struct cvmx_pciercx_cfg005_s cn68xx;
-        struct cvmx_pciercx_cfg005_s cn68xxp1;
-        struct cvmx_pciercx_cfg005_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg006 {
         uint32_t u32;
         struct cvmx_pciercx_cfg006_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t slt:8;
                 uint32_t subbnum:8;
                 uint32_t sbnum:8;
                 uint32_t pbnum:8;
-#else
-                uint32_t pbnum:8;
-                uint32_t sbnum:8;
-                uint32_t subbnum:8;
-                uint32_t slt:8;
-#endif
         } s;
         struct cvmx_pciercx_cfg006_s cn52xx;
         struct cvmx_pciercx_cfg006_s cn52xxp1;
         struct cvmx_pciercx_cfg006_s cn56xx;
         struct cvmx_pciercx_cfg006_s cn56xxp1;
-        struct cvmx_pciercx_cfg006_s cn61xx;
         struct cvmx_pciercx_cfg006_s cn63xx;
         struct cvmx_pciercx_cfg006_s cn63xxp1;
-        struct cvmx_pciercx_cfg006_s cn66xx;
-        struct cvmx_pciercx_cfg006_s cn68xx;
-        struct cvmx_pciercx_cfg006_s cn68xxp1;
-        struct cvmx_pciercx_cfg006_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg007 {
         uint32_t u32;
         struct cvmx_pciercx_cfg007_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t dpe:1;
                 uint32_t sse:1;
                 uint32_t rma:1;
@@ -349,217 +251,119 @@ union cvmx_pciercx_cfg007 {
                 uint32_t lio_base:4;
                 uint32_t reserved_1_3:3;
                 uint32_t io32a:1;
-#else
-                uint32_t io32a:1;
-                uint32_t reserved_1_3:3;
-                uint32_t lio_base:4;
-                uint32_t io32b:1;
-                uint32_t reserved_9_11:3;
-                uint32_t lio_limi:4;
-                uint32_t reserved_16_20:5;
-                uint32_t m66:1;
-                uint32_t reserved_22_22:1;
-                uint32_t fbb:1;
-                uint32_t mdpe:1;
-                uint32_t devt:2;
-                uint32_t sta:1;
-                uint32_t rta:1;
-                uint32_t rma:1;
-                uint32_t sse:1;
-                uint32_t dpe:1;
-#endif
         } s;
         struct cvmx_pciercx_cfg007_s cn52xx;
         struct cvmx_pciercx_cfg007_s cn52xxp1;
         struct cvmx_pciercx_cfg007_s cn56xx;
         struct cvmx_pciercx_cfg007_s cn56xxp1;
-        struct cvmx_pciercx_cfg007_s cn61xx;
         struct cvmx_pciercx_cfg007_s cn63xx;
         struct cvmx_pciercx_cfg007_s cn63xxp1;
-        struct cvmx_pciercx_cfg007_s cn66xx;
-        struct cvmx_pciercx_cfg007_s cn68xx;
-        struct cvmx_pciercx_cfg007_s cn68xxp1;
-        struct cvmx_pciercx_cfg007_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg008 {
         uint32_t u32;
         struct cvmx_pciercx_cfg008_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t ml_addr:12;
                 uint32_t reserved_16_19:4;
                 uint32_t mb_addr:12;
                 uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t mb_addr:12;
-                uint32_t reserved_16_19:4;
-                uint32_t ml_addr:12;
-#endif
         } s;
         struct cvmx_pciercx_cfg008_s cn52xx;
         struct cvmx_pciercx_cfg008_s cn52xxp1;
         struct cvmx_pciercx_cfg008_s cn56xx;
         struct cvmx_pciercx_cfg008_s cn56xxp1;
-        struct cvmx_pciercx_cfg008_s cn61xx;
         struct cvmx_pciercx_cfg008_s cn63xx;
         struct cvmx_pciercx_cfg008_s cn63xxp1;
-        struct cvmx_pciercx_cfg008_s cn66xx;
-        struct cvmx_pciercx_cfg008_s cn68xx;
-        struct cvmx_pciercx_cfg008_s cn68xxp1;
-        struct cvmx_pciercx_cfg008_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg009 {
         uint32_t u32;
         struct cvmx_pciercx_cfg009_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t lmem_limit:12;
                 uint32_t reserved_17_19:3;
                 uint32_t mem64b:1;
                 uint32_t lmem_base:12;
                 uint32_t reserved_1_3:3;
                 uint32_t mem64a:1;
-#else
-                uint32_t mem64a:1;
-                uint32_t reserved_1_3:3;
-                uint32_t lmem_base:12;
-                uint32_t mem64b:1;
-                uint32_t reserved_17_19:3;
-                uint32_t lmem_limit:12;
-#endif
         } s;
         struct cvmx_pciercx_cfg009_s cn52xx;
         struct cvmx_pciercx_cfg009_s cn52xxp1;
         struct cvmx_pciercx_cfg009_s cn56xx;
         struct cvmx_pciercx_cfg009_s cn56xxp1;
-        struct cvmx_pciercx_cfg009_s cn61xx;
         struct cvmx_pciercx_cfg009_s cn63xx;
         struct cvmx_pciercx_cfg009_s cn63xxp1;
-        struct cvmx_pciercx_cfg009_s cn66xx;
-        struct cvmx_pciercx_cfg009_s cn68xx;
-        struct cvmx_pciercx_cfg009_s cn68xxp1;
-        struct cvmx_pciercx_cfg009_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg010 {
         uint32_t u32;
         struct cvmx_pciercx_cfg010_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t umem_base:32;
-#else
-                uint32_t umem_base:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg010_s cn52xx;
         struct cvmx_pciercx_cfg010_s cn52xxp1;
         struct cvmx_pciercx_cfg010_s cn56xx;
         struct cvmx_pciercx_cfg010_s cn56xxp1;
-        struct cvmx_pciercx_cfg010_s cn61xx;
         struct cvmx_pciercx_cfg010_s cn63xx;
         struct cvmx_pciercx_cfg010_s cn63xxp1;
-        struct cvmx_pciercx_cfg010_s cn66xx;
-        struct cvmx_pciercx_cfg010_s cn68xx;
-        struct cvmx_pciercx_cfg010_s cn68xxp1;
-        struct cvmx_pciercx_cfg010_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg011 {
         uint32_t u32;
         struct cvmx_pciercx_cfg011_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t umem_limit:32;
-#else
                 uint32_t umem_limit:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg011_s cn52xx;
         struct cvmx_pciercx_cfg011_s cn52xxp1;
         struct cvmx_pciercx_cfg011_s cn56xx;
         struct cvmx_pciercx_cfg011_s cn56xxp1;
-        struct cvmx_pciercx_cfg011_s cn61xx;
         struct cvmx_pciercx_cfg011_s cn63xx;
         struct cvmx_pciercx_cfg011_s cn63xxp1;
-        struct cvmx_pciercx_cfg011_s cn66xx;
-        struct cvmx_pciercx_cfg011_s cn68xx;
-        struct cvmx_pciercx_cfg011_s cn68xxp1;
-        struct cvmx_pciercx_cfg011_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg012 {
         uint32_t u32;
         struct cvmx_pciercx_cfg012_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t uio_limit:16;
                 uint32_t uio_base:16;
-#else
-                uint32_t uio_base:16;
-                uint32_t uio_limit:16;
-#endif
         } s;
         struct cvmx_pciercx_cfg012_s cn52xx;
         struct cvmx_pciercx_cfg012_s cn52xxp1;
         struct cvmx_pciercx_cfg012_s cn56xx;
         struct cvmx_pciercx_cfg012_s cn56xxp1;
-        struct cvmx_pciercx_cfg012_s cn61xx;
         struct cvmx_pciercx_cfg012_s cn63xx;
         struct cvmx_pciercx_cfg012_s cn63xxp1;
-        struct cvmx_pciercx_cfg012_s cn66xx;
-        struct cvmx_pciercx_cfg012_s cn68xx;
-        struct cvmx_pciercx_cfg012_s cn68xxp1;
-        struct cvmx_pciercx_cfg012_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg013 {
         uint32_t u32;
         struct cvmx_pciercx_cfg013_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_8_31:24;
                 uint32_t cp:8;
-#else
-                uint32_t cp:8;
-                uint32_t reserved_8_31:24;
-#endif
         } s;
         struct cvmx_pciercx_cfg013_s cn52xx;
         struct cvmx_pciercx_cfg013_s cn52xxp1;
         struct cvmx_pciercx_cfg013_s cn56xx;
         struct cvmx_pciercx_cfg013_s cn56xxp1;
-        struct cvmx_pciercx_cfg013_s cn61xx;
         struct cvmx_pciercx_cfg013_s cn63xx;
         struct cvmx_pciercx_cfg013_s cn63xxp1;
-        struct cvmx_pciercx_cfg013_s cn66xx;
-        struct cvmx_pciercx_cfg013_s cn68xx;
-        struct cvmx_pciercx_cfg013_s cn68xxp1;
-        struct cvmx_pciercx_cfg013_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg014 {
         uint32_t u32;
         struct cvmx_pciercx_cfg014_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_0_31:32;
-#else
-                uint32_t reserved_0_31:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg014_s cn52xx;
         struct cvmx_pciercx_cfg014_s cn52xxp1;
         struct cvmx_pciercx_cfg014_s cn56xx;
         struct cvmx_pciercx_cfg014_s cn56xxp1;
-        struct cvmx_pciercx_cfg014_s cn61xx;
         struct cvmx_pciercx_cfg014_s cn63xx;
         struct cvmx_pciercx_cfg014_s cn63xxp1;
-        struct cvmx_pciercx_cfg014_s cn66xx;
-        struct cvmx_pciercx_cfg014_s cn68xx;
-        struct cvmx_pciercx_cfg014_s cn68xxp1;
-        struct cvmx_pciercx_cfg014_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg015 {
         uint32_t u32;
         struct cvmx_pciercx_cfg015_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_28_31:4;
                 uint32_t dtsees:1;
                 uint32_t dts:1;
@@ -575,41 +379,18 @@ union cvmx_pciercx_cfg015 {
                 uint32_t pere:1;
                 uint32_t inta:8;
                 uint32_t il:8;
-#else
-                uint32_t il:8;
-                uint32_t inta:8;
-                uint32_t pere:1;
-                uint32_t see:1;
-                uint32_t isae:1;
-                uint32_t vgae:1;
-                uint32_t vga16d:1;
-                uint32_t mam:1;
-                uint32_t sbrst:1;
-                uint32_t fbbe:1;
-                uint32_t pdt:1;
-                uint32_t sdt:1;
-                uint32_t dts:1;
-                uint32_t dtsees:1;
-                uint32_t reserved_28_31:4;
-#endif
         } s;
         struct cvmx_pciercx_cfg015_s cn52xx;
         struct cvmx_pciercx_cfg015_s cn52xxp1;
         struct cvmx_pciercx_cfg015_s cn56xx;
         struct cvmx_pciercx_cfg015_s cn56xxp1;
-        struct cvmx_pciercx_cfg015_s cn61xx;
         struct cvmx_pciercx_cfg015_s cn63xx;
         struct cvmx_pciercx_cfg015_s cn63xxp1;
-        struct cvmx_pciercx_cfg015_s cn66xx;
-        struct cvmx_pciercx_cfg015_s cn68xx;
-        struct cvmx_pciercx_cfg015_s cn68xxp1;
-        struct cvmx_pciercx_cfg015_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg016 {
         uint32_t u32;
         struct cvmx_pciercx_cfg016_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t pmes:5;
                 uint32_t d2s:1;
                 uint32_t d1s:1;
@@ -620,36 +401,18 @@ union cvmx_pciercx_cfg016 {
                 uint32_t pmsv:3;
                 uint32_t ncp:8;
                 uint32_t pmcid:8;
-#else
-                uint32_t pmcid:8;
-                uint32_t ncp:8;
-                uint32_t pmsv:3;
-                uint32_t pme_clock:1;
-                uint32_t reserved_20_20:1;
-                uint32_t dsi:1;
-                uint32_t auxc:3;
-                uint32_t d1s:1;
-                uint32_t d2s:1;
-                uint32_t pmes:5;
-#endif
         } s;
         struct cvmx_pciercx_cfg016_s cn52xx;
         struct cvmx_pciercx_cfg016_s cn52xxp1;
         struct cvmx_pciercx_cfg016_s cn56xx;
         struct cvmx_pciercx_cfg016_s cn56xxp1;
-        struct cvmx_pciercx_cfg016_s cn61xx;
         struct cvmx_pciercx_cfg016_s cn63xx;
         struct cvmx_pciercx_cfg016_s cn63xxp1;
-        struct cvmx_pciercx_cfg016_s cn66xx;
-        struct cvmx_pciercx_cfg016_s cn68xx;
-        struct cvmx_pciercx_cfg016_s cn68xxp1;
-        struct cvmx_pciercx_cfg016_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg017 {
         uint32_t u32;
         struct cvmx_pciercx_cfg017_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t pmdia:8;
                 uint32_t bpccee:1;
                 uint32_t bd3h:1;
@@ -662,59 +425,18 @@ union cvmx_pciercx_cfg017 {
                 uint32_t nsr:1;
                 uint32_t reserved_2_2:1;
                 uint32_t ps:2;
-#else
-                uint32_t ps:2;
-                uint32_t reserved_2_2:1;
-                uint32_t nsr:1;
-                uint32_t reserved_4_7:4;
-                uint32_t pmeens:1;
-                uint32_t pmds:4;
-                uint32_t pmedsia:2;
-                uint32_t pmess:1;
-                uint32_t reserved_16_21:6;
-                uint32_t bd3h:1;
-                uint32_t bpccee:1;
-                uint32_t pmdia:8;
-#endif
         } s;
         struct cvmx_pciercx_cfg017_s cn52xx;
         struct cvmx_pciercx_cfg017_s cn52xxp1;
         struct cvmx_pciercx_cfg017_s cn56xx;
         struct cvmx_pciercx_cfg017_s cn56xxp1;
-        struct cvmx_pciercx_cfg017_s cn61xx;
         struct cvmx_pciercx_cfg017_s cn63xx;
         struct cvmx_pciercx_cfg017_s cn63xxp1;
-        struct cvmx_pciercx_cfg017_s cn66xx;
-        struct cvmx_pciercx_cfg017_s cn68xx;
-        struct cvmx_pciercx_cfg017_s cn68xxp1;
-        struct cvmx_pciercx_cfg017_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg020 {
         uint32_t u32;
         struct cvmx_pciercx_cfg020_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_25_31:7;
-                uint32_t pvm:1;
-                uint32_t m64:1;
-                uint32_t mme:3;
-                uint32_t mmc:3;
-                uint32_t msien:1;
-                uint32_t ncp:8;
-                uint32_t msicid:8;
-#else
-                uint32_t msicid:8;
-                uint32_t ncp:8;
-                uint32_t msien:1;
-                uint32_t mmc:3;
-                uint32_t mme:3;
-                uint32_t m64:1;
-                uint32_t pvm:1;
-                uint32_t reserved_25_31:7;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg020_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_24_31:8;
                 uint32_t m64:1;
                 uint32_t mme:3;
@@ -722,102 +444,59 @@ union cvmx_pciercx_cfg020 {
                 uint32_t msien:1;
                 uint32_t ncp:8;
                 uint32_t msicid:8;
-#else
-                uint32_t msicid:8;
-                uint32_t ncp:8;
-                uint32_t msien:1;
-                uint32_t mmc:3;
-                uint32_t mme:3;
-                uint32_t m64:1;
-                uint32_t reserved_24_31:8;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg020_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg020_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg020_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg020_s cn61xx;
-        struct cvmx_pciercx_cfg020_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg020_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg020_cn52xx cn66xx;
-        struct cvmx_pciercx_cfg020_cn52xx cn68xx;
-        struct cvmx_pciercx_cfg020_cn52xx cn68xxp1;
-        struct cvmx_pciercx_cfg020_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg020_s cn52xx;
+        struct cvmx_pciercx_cfg020_s cn52xxp1;
+        struct cvmx_pciercx_cfg020_s cn56xx;
+        struct cvmx_pciercx_cfg020_s cn56xxp1;
+        struct cvmx_pciercx_cfg020_s cn63xx;
+        struct cvmx_pciercx_cfg020_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg021 {
         uint32_t u32;
         struct cvmx_pciercx_cfg021_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t lmsi:30;
                 uint32_t reserved_0_1:2;
-#else
-                uint32_t reserved_0_1:2;
-                uint32_t lmsi:30;
-#endif
         } s;
         struct cvmx_pciercx_cfg021_s cn52xx;
         struct cvmx_pciercx_cfg021_s cn52xxp1;
         struct cvmx_pciercx_cfg021_s cn56xx;
         struct cvmx_pciercx_cfg021_s cn56xxp1;
-        struct cvmx_pciercx_cfg021_s cn61xx;
         struct cvmx_pciercx_cfg021_s cn63xx;
         struct cvmx_pciercx_cfg021_s cn63xxp1;
-        struct cvmx_pciercx_cfg021_s cn66xx;
-        struct cvmx_pciercx_cfg021_s cn68xx;
-        struct cvmx_pciercx_cfg021_s cn68xxp1;
-        struct cvmx_pciercx_cfg021_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg022 {
         uint32_t u32;
         struct cvmx_pciercx_cfg022_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t umsi:32;
-#else
                 uint32_t umsi:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg022_s cn52xx;
         struct cvmx_pciercx_cfg022_s cn52xxp1;
         struct cvmx_pciercx_cfg022_s cn56xx;
         struct cvmx_pciercx_cfg022_s cn56xxp1;
-        struct cvmx_pciercx_cfg022_s cn61xx;
         struct cvmx_pciercx_cfg022_s cn63xx;
         struct cvmx_pciercx_cfg022_s cn63xxp1;
-        struct cvmx_pciercx_cfg022_s cn66xx;
-        struct cvmx_pciercx_cfg022_s cn68xx;
-        struct cvmx_pciercx_cfg022_s cn68xxp1;
-        struct cvmx_pciercx_cfg022_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg023 {
         uint32_t u32;
         struct cvmx_pciercx_cfg023_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_16_31:16;
                 uint32_t msimd:16;
-#else
-                uint32_t msimd:16;
-                uint32_t reserved_16_31:16;
-#endif
         } s;
         struct cvmx_pciercx_cfg023_s cn52xx;
         struct cvmx_pciercx_cfg023_s cn52xxp1;
         struct cvmx_pciercx_cfg023_s cn56xx;
         struct cvmx_pciercx_cfg023_s cn56xxp1;
-        struct cvmx_pciercx_cfg023_s cn61xx;
         struct cvmx_pciercx_cfg023_s cn63xx;
         struct cvmx_pciercx_cfg023_s cn63xxp1;
-        struct cvmx_pciercx_cfg023_s cn66xx;
-        struct cvmx_pciercx_cfg023_s cn68xx;
-        struct cvmx_pciercx_cfg023_s cn68xxp1;
-        struct cvmx_pciercx_cfg023_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg028 {
         uint32_t u32;
         struct cvmx_pciercx_cfg028_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_30_31:2;
                 uint32_t imn:5;
                 uint32_t si:1;
@@ -825,33 +504,18 @@ union cvmx_pciercx_cfg028 {
                 uint32_t pciecv:4;
                 uint32_t ncp:8;
                 uint32_t pcieid:8;
-#else
-                uint32_t pcieid:8;
-                uint32_t ncp:8;
-                uint32_t pciecv:4;
-                uint32_t dpt:4;
-                uint32_t si:1;
-                uint32_t imn:5;
-                uint32_t reserved_30_31:2;
-#endif
         } s;
         struct cvmx_pciercx_cfg028_s cn52xx;
         struct cvmx_pciercx_cfg028_s cn52xxp1;
         struct cvmx_pciercx_cfg028_s cn56xx;
         struct cvmx_pciercx_cfg028_s cn56xxp1;
-        struct cvmx_pciercx_cfg028_s cn61xx;
         struct cvmx_pciercx_cfg028_s cn63xx;
         struct cvmx_pciercx_cfg028_s cn63xxp1;
-        struct cvmx_pciercx_cfg028_s cn66xx;
-        struct cvmx_pciercx_cfg028_s cn68xx;
-        struct cvmx_pciercx_cfg028_s cn68xxp1;
-        struct cvmx_pciercx_cfg028_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg029 {
         uint32_t u32;
         struct cvmx_pciercx_cfg029_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_28_31:4;
                 uint32_t cspls:2;
                 uint32_t csplv:8;
@@ -863,37 +527,18 @@ union cvmx_pciercx_cfg029 {
                 uint32_t etfs:1;
                 uint32_t pfs:2;
                 uint32_t mpss:3;
-#else
-                uint32_t mpss:3;
-                uint32_t pfs:2;
-                uint32_t etfs:1;
-                uint32_t el0al:3;
-                uint32_t el1al:3;
-                uint32_t reserved_12_14:3;
-                uint32_t rber:1;
-                uint32_t reserved_16_17:2;
-                uint32_t csplv:8;
-                uint32_t cspls:2;
-                uint32_t reserved_28_31:4;
-#endif
         } s;
         struct cvmx_pciercx_cfg029_s cn52xx;
         struct cvmx_pciercx_cfg029_s cn52xxp1;
         struct cvmx_pciercx_cfg029_s cn56xx;
         struct cvmx_pciercx_cfg029_s cn56xxp1;
-        struct cvmx_pciercx_cfg029_s cn61xx;
         struct cvmx_pciercx_cfg029_s cn63xx;
         struct cvmx_pciercx_cfg029_s cn63xxp1;
-        struct cvmx_pciercx_cfg029_s cn66xx;
-        struct cvmx_pciercx_cfg029_s cn68xx;
-        struct cvmx_pciercx_cfg029_s cn68xxp1;
-        struct cvmx_pciercx_cfg029_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg030 {
         uint32_t u32;
         struct cvmx_pciercx_cfg030_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_22_31:10;
                 uint32_t tp:1;
                 uint32_t ap_d:1;
@@ -913,74 +558,18 @@ union cvmx_pciercx_cfg030 {
                 uint32_t fe_en:1;
                 uint32_t nfe_en:1;
                 uint32_t ce_en:1;
-#else
-                uint32_t ce_en:1;
-                uint32_t nfe_en:1;
-                uint32_t fe_en:1;
-                uint32_t ur_en:1;
-                uint32_t ro_en:1;
-                uint32_t mps:3;
-                uint32_t etf_en:1;
-                uint32_t pf_en:1;
-                uint32_t ap_en:1;
-                uint32_t ns_en:1;
-                uint32_t mrrs:3;
-                uint32_t reserved_15_15:1;
-                uint32_t ce_d:1;
-                uint32_t nfe_d:1;
-                uint32_t fe_d:1;
-                uint32_t ur_d:1;
-                uint32_t ap_d:1;
-                uint32_t tp:1;
-                uint32_t reserved_22_31:10;
-#endif
         } s;
         struct cvmx_pciercx_cfg030_s cn52xx;
         struct cvmx_pciercx_cfg030_s cn52xxp1;
         struct cvmx_pciercx_cfg030_s cn56xx;
         struct cvmx_pciercx_cfg030_s cn56xxp1;
-        struct cvmx_pciercx_cfg030_s cn61xx;
         struct cvmx_pciercx_cfg030_s cn63xx;
         struct cvmx_pciercx_cfg030_s cn63xxp1;
-        struct cvmx_pciercx_cfg030_s cn66xx;
-        struct cvmx_pciercx_cfg030_s cn68xx;
-        struct cvmx_pciercx_cfg030_s cn68xxp1;
-        struct cvmx_pciercx_cfg030_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg031 {
         uint32_t u32;
         struct cvmx_pciercx_cfg031_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t pnum:8;
-                uint32_t reserved_23_23:1;
-                uint32_t aspm:1;
-                uint32_t lbnc:1;
-                uint32_t dllarc:1;
-                uint32_t sderc:1;
-                uint32_t cpm:1;
-                uint32_t l1el:3;
-                uint32_t l0el:3;
-                uint32_t aslpms:2;
-                uint32_t mlw:6;
-                uint32_t mls:4;
-#else
-                uint32_t mls:4;
-                uint32_t mlw:6;
-                uint32_t aslpms:2;
-                uint32_t l0el:3;
-                uint32_t l1el:3;
-                uint32_t cpm:1;
-                uint32_t sderc:1;
-                uint32_t dllarc:1;
-                uint32_t lbnc:1;
-                uint32_t aspm:1;
-                uint32_t reserved_23_23:1;
-                uint32_t pnum:8;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg031_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t pnum:8;
                 uint32_t reserved_22_23:2;
                 uint32_t lbnc:1;
@@ -992,36 +581,18 @@ union cvmx_pciercx_cfg031 {
                 uint32_t aslpms:2;
                 uint32_t mlw:6;
                 uint32_t mls:4;
-#else
-                uint32_t mls:4;
-                uint32_t mlw:6;
-                uint32_t aslpms:2;
-                uint32_t l0el:3;
-                uint32_t l1el:3;
-                uint32_t cpm:1;
-                uint32_t sderc:1;
-                uint32_t dllarc:1;
-                uint32_t lbnc:1;
-                uint32_t reserved_22_23:2;
-                uint32_t pnum:8;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg031_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg031_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg031_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg031_s cn61xx;
-        struct cvmx_pciercx_cfg031_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg031_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg031_s cn66xx;
-        struct cvmx_pciercx_cfg031_s cn68xx;
-        struct cvmx_pciercx_cfg031_cn52xx cn68xxp1;
-        struct cvmx_pciercx_cfg031_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg031_s cn52xx;
+        struct cvmx_pciercx_cfg031_s cn52xxp1;
+        struct cvmx_pciercx_cfg031_s cn56xx;
+        struct cvmx_pciercx_cfg031_s cn56xxp1;
+        struct cvmx_pciercx_cfg031_s cn63xx;
+        struct cvmx_pciercx_cfg031_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg032 {
         uint32_t u32;
         struct cvmx_pciercx_cfg032_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t lab:1;
                 uint32_t lbm:1;
                 uint32_t dlla:1;
@@ -1042,46 +613,18 @@ union cvmx_pciercx_cfg032 {
                 uint32_t rcb:1;
                 uint32_t reserved_2_2:1;
                 uint32_t aslpc:2;
-#else
-                uint32_t aslpc:2;
-                uint32_t reserved_2_2:1;
-                uint32_t rcb:1;
-                uint32_t ld:1;
-                uint32_t rl:1;
-                uint32_t ccc:1;
-                uint32_t es:1;
-                uint32_t ecpm:1;
-                uint32_t hawd:1;
-                uint32_t lbm_int_enb:1;
-                uint32_t lab_int_enb:1;
-                uint32_t reserved_12_15:4;
-                uint32_t ls:4;
-                uint32_t nlw:6;
-                uint32_t reserved_26_26:1;
-                uint32_t lt:1;
-                uint32_t scc:1;
-                uint32_t dlla:1;
-                uint32_t lbm:1;
-                uint32_t lab:1;
-#endif
         } s;
         struct cvmx_pciercx_cfg032_s cn52xx;
         struct cvmx_pciercx_cfg032_s cn52xxp1;
         struct cvmx_pciercx_cfg032_s cn56xx;
         struct cvmx_pciercx_cfg032_s cn56xxp1;
-        struct cvmx_pciercx_cfg032_s cn61xx;
         struct cvmx_pciercx_cfg032_s cn63xx;
         struct cvmx_pciercx_cfg032_s cn63xxp1;
-        struct cvmx_pciercx_cfg032_s cn66xx;
-        struct cvmx_pciercx_cfg032_s cn68xx;
-        struct cvmx_pciercx_cfg032_s cn68xxp1;
-        struct cvmx_pciercx_cfg032_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg033 {
         uint32_t u32;
         struct cvmx_pciercx_cfg033_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t ps_num:13;
                 uint32_t nccs:1;
                 uint32_t emip:1;
@@ -1094,38 +637,18 @@ union cvmx_pciercx_cfg033 {
                 uint32_t mrlsp:1;
                 uint32_t pcp:1;
                 uint32_t abp:1;
-#else
-                uint32_t abp:1;
-                uint32_t pcp:1;
-                uint32_t mrlsp:1;
-                uint32_t aip:1;
-                uint32_t pip:1;
-                uint32_t hp_s:1;
-                uint32_t hp_c:1;
-                uint32_t sp_lv:8;
-                uint32_t sp_ls:2;
-                uint32_t emip:1;
-                uint32_t nccs:1;
-                uint32_t ps_num:13;
-#endif
         } s;
         struct cvmx_pciercx_cfg033_s cn52xx;
         struct cvmx_pciercx_cfg033_s cn52xxp1;
         struct cvmx_pciercx_cfg033_s cn56xx;
         struct cvmx_pciercx_cfg033_s cn56xxp1;
-        struct cvmx_pciercx_cfg033_s cn61xx;
         struct cvmx_pciercx_cfg033_s cn63xx;
         struct cvmx_pciercx_cfg033_s cn63xxp1;
-        struct cvmx_pciercx_cfg033_s cn66xx;
-        struct cvmx_pciercx_cfg033_s cn68xx;
-        struct cvmx_pciercx_cfg033_s cn68xxp1;
-        struct cvmx_pciercx_cfg033_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg034 {
         uint32_t u32;
         struct cvmx_pciercx_cfg034_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_25_31:7;
                 uint32_t dlls_c:1;
                 uint32_t emis:1;
@@ -1148,48 +671,18 @@ union cvmx_pciercx_cfg034 {
                 uint32_t mrls_en:1;
                 uint32_t pf_en:1;
                 uint32_t abp_en:1;
-#else
-                uint32_t abp_en:1;
-                uint32_t pf_en:1;
-                uint32_t mrls_en:1;
-                uint32_t pd_en:1;
-                uint32_t ccint_en:1;
-                uint32_t hpint_en:1;
-                uint32_t aic:2;
-                uint32_t pic:2;
-                uint32_t pcc:1;
-                uint32_t emic:1;
-                uint32_t dlls_en:1;
-                uint32_t reserved_13_15:3;
-                uint32_t abp_d:1;
-                uint32_t pf_d:1;
-                uint32_t mrls_c:1;
-                uint32_t pd_c:1;
-                uint32_t ccint_d:1;
-                uint32_t mrlss:1;
-                uint32_t pds:1;
-                uint32_t emis:1;
-                uint32_t dlls_c:1;
-                uint32_t reserved_25_31:7;
-#endif
         } s;
         struct cvmx_pciercx_cfg034_s cn52xx;
         struct cvmx_pciercx_cfg034_s cn52xxp1;
         struct cvmx_pciercx_cfg034_s cn56xx;
         struct cvmx_pciercx_cfg034_s cn56xxp1;
-        struct cvmx_pciercx_cfg034_s cn61xx;
         struct cvmx_pciercx_cfg034_s cn63xx;
         struct cvmx_pciercx_cfg034_s cn63xxp1;
-        struct cvmx_pciercx_cfg034_s cn66xx;
-        struct cvmx_pciercx_cfg034_s cn68xx;
-        struct cvmx_pciercx_cfg034_s cn68xxp1;
-        struct cvmx_pciercx_cfg034_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg035 {
         uint32_t u32;
         struct cvmx_pciercx_cfg035_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_17_31:15;
                 uint32_t crssv:1;
                 uint32_t reserved_5_15:11;
@@ -1198,304 +691,82 @@ union cvmx_pciercx_cfg035 {
                 uint32_t sefee:1;
                 uint32_t senfee:1;
                 uint32_t secee:1;
-#else
-                uint32_t secee:1;
-                uint32_t senfee:1;
-                uint32_t sefee:1;
-                uint32_t pmeie:1;
-                uint32_t crssve:1;
-                uint32_t reserved_5_15:11;
-                uint32_t crssv:1;
-                uint32_t reserved_17_31:15;
-#endif
         } s;
         struct cvmx_pciercx_cfg035_s cn52xx;
         struct cvmx_pciercx_cfg035_s cn52xxp1;
         struct cvmx_pciercx_cfg035_s cn56xx;
         struct cvmx_pciercx_cfg035_s cn56xxp1;
-        struct cvmx_pciercx_cfg035_s cn61xx;
         struct cvmx_pciercx_cfg035_s cn63xx;
         struct cvmx_pciercx_cfg035_s cn63xxp1;
-        struct cvmx_pciercx_cfg035_s cn66xx;
-        struct cvmx_pciercx_cfg035_s cn68xx;
-        struct cvmx_pciercx_cfg035_s cn68xxp1;
-        struct cvmx_pciercx_cfg035_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg036 {
         uint32_t u32;
         struct cvmx_pciercx_cfg036_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_18_31:14;
                 uint32_t pme_pend:1;
                 uint32_t pme_stat:1;
                 uint32_t pme_rid:16;
-#else
-                uint32_t pme_rid:16;
-                uint32_t pme_stat:1;
-                uint32_t pme_pend:1;
-                uint32_t reserved_18_31:14;
-#endif
         } s;
         struct cvmx_pciercx_cfg036_s cn52xx;
         struct cvmx_pciercx_cfg036_s cn52xxp1;
         struct cvmx_pciercx_cfg036_s cn56xx;
         struct cvmx_pciercx_cfg036_s cn56xxp1;
-        struct cvmx_pciercx_cfg036_s cn61xx;
         struct cvmx_pciercx_cfg036_s cn63xx;
         struct cvmx_pciercx_cfg036_s cn63xxp1;
-        struct cvmx_pciercx_cfg036_s cn66xx;
-        struct cvmx_pciercx_cfg036_s cn68xx;
-        struct cvmx_pciercx_cfg036_s cn68xxp1;
-        struct cvmx_pciercx_cfg036_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg037 {
         uint32_t u32;
         struct cvmx_pciercx_cfg037_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_20_31:12;
-                uint32_t obffs:2;
-                uint32_t reserved_12_17:6;
-                uint32_t ltrs:1;
-                uint32_t noroprpr:1;
-                uint32_t atom128s:1;
-                uint32_t atom64s:1;
-                uint32_t atom32s:1;
-                uint32_t atom_ops:1;
-                uint32_t reserved_5_5:1;
-                uint32_t ctds:1;
-                uint32_t ctrs:4;
-#else
-                uint32_t ctrs:4;
-                uint32_t ctds:1;
-                uint32_t reserved_5_5:1;
-                uint32_t atom_ops:1;
-                uint32_t atom32s:1;
-                uint32_t atom64s:1;
-                uint32_t atom128s:1;
-                uint32_t noroprpr:1;
-                uint32_t ltrs:1;
-                uint32_t reserved_12_17:6;
-                uint32_t obffs:2;
-                uint32_t reserved_20_31:12;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg037_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_5_31:27;
-                uint32_t ctds:1;
-                uint32_t ctrs:4;
-#else
-                uint32_t ctrs:4;
-                uint32_t ctds:1;
                 uint32_t reserved_5_31:27;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg037_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg037_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg037_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg037_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_14_31:18;
-                uint32_t tph:2;
-                uint32_t reserved_11_11:1;
-                uint32_t noroprpr:1;
-                uint32_t atom128s:1;
-                uint32_t atom64s:1;
-                uint32_t atom32s:1;
-                uint32_t atom_ops:1;
-                uint32_t ari_fw:1;
                 uint32_t ctds:1;
                 uint32_t ctrs:4;
-#else
-                uint32_t ctrs:4;
-                uint32_t ctds:1;
-                uint32_t ari_fw:1;
-                uint32_t atom_ops:1;
-                uint32_t atom32s:1;
-                uint32_t atom64s:1;
-                uint32_t atom128s:1;
-                uint32_t noroprpr:1;
-                uint32_t reserved_11_11:1;
-                uint32_t tph:2;
-                uint32_t reserved_14_31:18;
-#endif
-        } cn61xx;
-        struct cvmx_pciercx_cfg037_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg037_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg037_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_14_31:18;
-                uint32_t tph:2;
-                uint32_t reserved_11_11:1;
-                uint32_t noroprpr:1;
-                uint32_t atom128s:1;
-                uint32_t atom64s:1;
-                uint32_t atom32s:1;
-                uint32_t atom_ops:1;
-                uint32_t ari:1;
-                uint32_t ctds:1;
-                uint32_t ctrs:4;
-#else
-                uint32_t ctrs:4;
-                uint32_t ctds:1;
-                uint32_t ari:1;
-                uint32_t atom_ops:1;
-                uint32_t atom32s:1;
-                uint32_t atom64s:1;
-                uint32_t atom128s:1;
-                uint32_t noroprpr:1;
-                uint32_t reserved_11_11:1;
-                uint32_t tph:2;
-                uint32_t reserved_14_31:18;
-#endif
-        } cn66xx;
-        struct cvmx_pciercx_cfg037_cn66xx cn68xx;
-        struct cvmx_pciercx_cfg037_cn66xx cn68xxp1;
-        struct cvmx_pciercx_cfg037_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_20_31:12;
-                uint32_t obffs:2;
-                uint32_t reserved_14_17:4;
-                uint32_t tphs:2;
-                uint32_t ltrs:1;
-                uint32_t noroprpr:1;
-                uint32_t atom128s:1;
-                uint32_t atom64s:1;
-                uint32_t atom32s:1;
-                uint32_t atom_ops:1;
-                uint32_t ari_fw:1;
-                uint32_t ctds:1;
-                uint32_t ctrs:4;
-#else
-                uint32_t ctrs:4;
-                uint32_t ctds:1;
-                uint32_t ari_fw:1;
-                uint32_t atom_ops:1;
-                uint32_t atom32s:1;
-                uint32_t atom64s:1;
-                uint32_t atom128s:1;
-                uint32_t noroprpr:1;
-                uint32_t ltrs:1;
-                uint32_t tphs:2;
-                uint32_t reserved_14_17:4;
-                uint32_t obffs:2;
-                uint32_t reserved_20_31:12;
-#endif
-        } cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg037_s cn52xx;
+        struct cvmx_pciercx_cfg037_s cn52xxp1;
+        struct cvmx_pciercx_cfg037_s cn56xx;
+        struct cvmx_pciercx_cfg037_s cn56xxp1;
+        struct cvmx_pciercx_cfg037_s cn63xx;
+        struct cvmx_pciercx_cfg037_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg038 {
         uint32_t u32;
         struct cvmx_pciercx_cfg038_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_15_31:17;
-                uint32_t obffe:2;
-                uint32_t reserved_11_12:2;
-                uint32_t ltre:1;
-                uint32_t id0_cp:1;
-                uint32_t id0_rq:1;
-                uint32_t atom_op_eb:1;
-                uint32_t atom_op:1;
-                uint32_t ari:1;
-                uint32_t ctd:1;
-                uint32_t ctv:4;
-#else
-                uint32_t ctv:4;
-                uint32_t ctd:1;
-                uint32_t ari:1;
-                uint32_t atom_op:1;
-                uint32_t atom_op_eb:1;
-                uint32_t id0_rq:1;
-                uint32_t id0_cp:1;
-                uint32_t ltre:1;
-                uint32_t reserved_11_12:2;
-                uint32_t obffe:2;
-                uint32_t reserved_15_31:17;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg038_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_5_31:27;
                 uint32_t ctd:1;
                 uint32_t ctv:4;
-#else
-                uint32_t ctv:4;
-                uint32_t ctd:1;
-                uint32_t reserved_5_31:27;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg038_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg038_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg038_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg038_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_10_31:22;
-                uint32_t id0_cp:1;
-                uint32_t id0_rq:1;
-                uint32_t atom_op_eb:1;
-                uint32_t atom_op:1;
-                uint32_t ari:1;
-                uint32_t ctd:1;
-                uint32_t ctv:4;
-#else
-                uint32_t ctv:4;
-                uint32_t ctd:1;
-                uint32_t ari:1;
-                uint32_t atom_op:1;
-                uint32_t atom_op_eb:1;
-                uint32_t id0_rq:1;
-                uint32_t id0_cp:1;
-                uint32_t reserved_10_31:22;
-#endif
-        } cn61xx;
-        struct cvmx_pciercx_cfg038_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg038_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg038_cn61xx cn66xx;
-        struct cvmx_pciercx_cfg038_cn61xx cn68xx;
-        struct cvmx_pciercx_cfg038_cn61xx cn68xxp1;
-        struct cvmx_pciercx_cfg038_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg038_s cn52xx;
+        struct cvmx_pciercx_cfg038_s cn52xxp1;
+        struct cvmx_pciercx_cfg038_s cn56xx;
+        struct cvmx_pciercx_cfg038_s cn56xxp1;
+        struct cvmx_pciercx_cfg038_s cn63xx;
+        struct cvmx_pciercx_cfg038_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg039 {
         uint32_t u32;
         struct cvmx_pciercx_cfg039_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_9_31:23;
                 uint32_t cls:1;
                 uint32_t slsv:7;
                 uint32_t reserved_0_0:1;
-#else
-                uint32_t reserved_0_0:1;
-                uint32_t slsv:7;
-                uint32_t cls:1;
-                uint32_t reserved_9_31:23;
-#endif
         } s;
         struct cvmx_pciercx_cfg039_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_0_31:32;
-#else
-                uint32_t reserved_0_31:32;
-#endif
         } cn52xx;
         struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
         struct cvmx_pciercx_cfg039_cn52xx cn56xx;
         struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg039_s cn61xx;
         struct cvmx_pciercx_cfg039_s cn63xx;
         struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg039_s cn66xx;
-        struct cvmx_pciercx_cfg039_s cn68xx;
-        struct cvmx_pciercx_cfg039_s cn68xxp1;
-        struct cvmx_pciercx_cfg039_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg040 {
         uint32_t u32;
         struct cvmx_pciercx_cfg040_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_17_31:15;
                 uint32_t cdl:1;
                 uint32_t reserved_13_15:3;
@@ -1507,193 +778,62 @@ union cvmx_pciercx_cfg040 {
                 uint32_t hasd:1;
                 uint32_t ec:1;
                 uint32_t tls:4;
-#else
-                uint32_t tls:4;
-                uint32_t ec:1;
-                uint32_t hasd:1;
-                uint32_t sde:1;
-                uint32_t tm:3;
-                uint32_t emc:1;
-                uint32_t csos:1;
-                uint32_t cde:1;
-                uint32_t reserved_13_15:3;
-                uint32_t cdl:1;
-                uint32_t reserved_17_31:15;
-#endif
         } s;
         struct cvmx_pciercx_cfg040_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_0_31:32;
-#else
-                uint32_t reserved_0_31:32;
-#endif
         } cn52xx;
         struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
         struct cvmx_pciercx_cfg040_cn52xx cn56xx;
         struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg040_s cn61xx;
         struct cvmx_pciercx_cfg040_s cn63xx;
         struct cvmx_pciercx_cfg040_s cn63xxp1;
-        struct cvmx_pciercx_cfg040_s cn66xx;
-        struct cvmx_pciercx_cfg040_s cn68xx;
-        struct cvmx_pciercx_cfg040_s cn68xxp1;
-        struct cvmx_pciercx_cfg040_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg041 {
         uint32_t u32;
         struct cvmx_pciercx_cfg041_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_0_31:32;
-#else
-                uint32_t reserved_0_31:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg041_s cn52xx;
         struct cvmx_pciercx_cfg041_s cn52xxp1;
         struct cvmx_pciercx_cfg041_s cn56xx;
         struct cvmx_pciercx_cfg041_s cn56xxp1;
-        struct cvmx_pciercx_cfg041_s cn61xx;
         struct cvmx_pciercx_cfg041_s cn63xx;
         struct cvmx_pciercx_cfg041_s cn63xxp1;
-        struct cvmx_pciercx_cfg041_s cn66xx;
-        struct cvmx_pciercx_cfg041_s cn68xx;
-        struct cvmx_pciercx_cfg041_s cn68xxp1;
-        struct cvmx_pciercx_cfg041_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg042 {
         uint32_t u32;
         struct cvmx_pciercx_cfg042_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_0_31:32;
-#else
-                uint32_t reserved_0_31:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg042_s cn52xx;
         struct cvmx_pciercx_cfg042_s cn52xxp1;
         struct cvmx_pciercx_cfg042_s cn56xx;
         struct cvmx_pciercx_cfg042_s cn56xxp1;
-        struct cvmx_pciercx_cfg042_s cn61xx;
         struct cvmx_pciercx_cfg042_s cn63xx;
         struct cvmx_pciercx_cfg042_s cn63xxp1;
-        struct cvmx_pciercx_cfg042_s cn66xx;
-        struct cvmx_pciercx_cfg042_s cn68xx;
-        struct cvmx_pciercx_cfg042_s cn68xxp1;
-        struct cvmx_pciercx_cfg042_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg064 {
         uint32_t u32;
         struct cvmx_pciercx_cfg064_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t nco:12;
                 uint32_t cv:4;
                 uint32_t pcieec:16;
-#else
-                uint32_t pcieec:16;
-                uint32_t cv:4;
-                uint32_t nco:12;
-#endif
         } s;
         struct cvmx_pciercx_cfg064_s cn52xx;
         struct cvmx_pciercx_cfg064_s cn52xxp1;
         struct cvmx_pciercx_cfg064_s cn56xx;
         struct cvmx_pciercx_cfg064_s cn56xxp1;
-        struct cvmx_pciercx_cfg064_s cn61xx;
         struct cvmx_pciercx_cfg064_s cn63xx;
         struct cvmx_pciercx_cfg064_s cn63xxp1;
-        struct cvmx_pciercx_cfg064_s cn66xx;
-        struct cvmx_pciercx_cfg064_s cn68xx;
-        struct cvmx_pciercx_cfg064_s cn68xxp1;
-        struct cvmx_pciercx_cfg064_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg065 {
         uint32_t u32;
         struct cvmx_pciercx_cfg065_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_25_31:7;
-                uint32_t uatombs:1;
-                uint32_t reserved_23_23:1;
-                uint32_t ucies:1;
-                uint32_t reserved_21_21:1;
-                uint32_t ures:1;
-                uint32_t ecrces:1;
-                uint32_t mtlps:1;
-                uint32_t ros:1;
-                uint32_t ucs:1;
-                uint32_t cas:1;
-                uint32_t cts:1;
-                uint32_t fcpes:1;
-                uint32_t ptlps:1;
-                uint32_t reserved_6_11:6;
-                uint32_t sdes:1;
-                uint32_t dlpes:1;
-                uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t dlpes:1;
-                uint32_t sdes:1;
-                uint32_t reserved_6_11:6;
-                uint32_t ptlps:1;
-                uint32_t fcpes:1;
-                uint32_t cts:1;
-                uint32_t cas:1;
-                uint32_t ucs:1;
-                uint32_t ros:1;
-                uint32_t mtlps:1;
-                uint32_t ecrces:1;
-                uint32_t ures:1;
-                uint32_t reserved_21_21:1;
-                uint32_t ucies:1;
-                uint32_t reserved_23_23:1;
-                uint32_t uatombs:1;
-                uint32_t reserved_25_31:7;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg065_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_21_31:11;
-                uint32_t ures:1;
-                uint32_t ecrces:1;
-                uint32_t mtlps:1;
-                uint32_t ros:1;
-                uint32_t ucs:1;
-                uint32_t cas:1;
-                uint32_t cts:1;
-                uint32_t fcpes:1;
-                uint32_t ptlps:1;
-                uint32_t reserved_6_11:6;
-                uint32_t sdes:1;
-                uint32_t dlpes:1;
-                uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t dlpes:1;
-                uint32_t sdes:1;
-                uint32_t reserved_6_11:6;
-                uint32_t ptlps:1;
-                uint32_t fcpes:1;
-                uint32_t cts:1;
-                uint32_t cas:1;
-                uint32_t ucs:1;
-                uint32_t ros:1;
-                uint32_t mtlps:1;
-                uint32_t ecrces:1;
-                uint32_t ures:1;
                 uint32_t reserved_21_31:11;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg065_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg065_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg065_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg065_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_25_31:7;
-                uint32_t uatombs:1;
-                uint32_t reserved_21_23:3;
                 uint32_t ures:1;
                 uint32_t ecrces:1;
                 uint32_t mtlps:1;
@@ -1707,117 +847,19 @@ union cvmx_pciercx_cfg065 {
                 uint32_t sdes:1;
                 uint32_t dlpes:1;
                 uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t dlpes:1;
-                uint32_t sdes:1;
-                uint32_t reserved_6_11:6;
-                uint32_t ptlps:1;
-                uint32_t fcpes:1;
-                uint32_t cts:1;
-                uint32_t cas:1;
-                uint32_t ucs:1;
-                uint32_t ros:1;
-                uint32_t mtlps:1;
-                uint32_t ecrces:1;
-                uint32_t ures:1;
-                uint32_t reserved_21_23:3;
-                uint32_t uatombs:1;
-                uint32_t reserved_25_31:7;
-#endif
-        } cn61xx;
-        struct cvmx_pciercx_cfg065_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg065_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg065_cn61xx cn66xx;
-        struct cvmx_pciercx_cfg065_cn61xx cn68xx;
-        struct cvmx_pciercx_cfg065_cn52xx cn68xxp1;
-        struct cvmx_pciercx_cfg065_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg065_s cn52xx;
+        struct cvmx_pciercx_cfg065_s cn52xxp1;
+        struct cvmx_pciercx_cfg065_s cn56xx;
+        struct cvmx_pciercx_cfg065_s cn56xxp1;
+        struct cvmx_pciercx_cfg065_s cn63xx;
+        struct cvmx_pciercx_cfg065_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg066 {
         uint32_t u32;
         struct cvmx_pciercx_cfg066_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_25_31:7;
-                uint32_t uatombm:1;
-                uint32_t reserved_23_23:1;
-                uint32_t uciem:1;
-                uint32_t reserved_21_21:1;
-                uint32_t urem:1;
-                uint32_t ecrcem:1;
-                uint32_t mtlpm:1;
-                uint32_t rom:1;
-                uint32_t ucm:1;
-                uint32_t cam:1;
-                uint32_t ctm:1;
-                uint32_t fcpem:1;
-                uint32_t ptlpm:1;
-                uint32_t reserved_6_11:6;
-                uint32_t sdem:1;
-                uint32_t dlpem:1;
-                uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t dlpem:1;
-                uint32_t sdem:1;
-                uint32_t reserved_6_11:6;
-                uint32_t ptlpm:1;
-                uint32_t fcpem:1;
-                uint32_t ctm:1;
-                uint32_t cam:1;
-                uint32_t ucm:1;
-                uint32_t rom:1;
-                uint32_t mtlpm:1;
-                uint32_t ecrcem:1;
-                uint32_t urem:1;
-                uint32_t reserved_21_21:1;
-                uint32_t uciem:1;
-                uint32_t reserved_23_23:1;
-                uint32_t uatombm:1;
-                uint32_t reserved_25_31:7;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg066_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_21_31:11;
-                uint32_t urem:1;
-                uint32_t ecrcem:1;
-                uint32_t mtlpm:1;
-                uint32_t rom:1;
-                uint32_t ucm:1;
-                uint32_t cam:1;
-                uint32_t ctm:1;
-                uint32_t fcpem:1;
-                uint32_t ptlpm:1;
-                uint32_t reserved_6_11:6;
-                uint32_t sdem:1;
-                uint32_t dlpem:1;
-                uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t dlpem:1;
-                uint32_t sdem:1;
-                uint32_t reserved_6_11:6;
-                uint32_t ptlpm:1;
-                uint32_t fcpem:1;
-                uint32_t ctm:1;
-                uint32_t cam:1;
-                uint32_t ucm:1;
-                uint32_t rom:1;
-                uint32_t mtlpm:1;
-                uint32_t ecrcem:1;
-                uint32_t urem:1;
                 uint32_t reserved_21_31:11;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg066_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg066_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg066_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg066_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_25_31:7;
-                uint32_t uatombm:1;
-                uint32_t reserved_21_23:3;
                 uint32_t urem:1;
                 uint32_t ecrcem:1;
                 uint32_t mtlpm:1;
@@ -1831,117 +873,19 @@ union cvmx_pciercx_cfg066 {
                 uint32_t sdem:1;
                 uint32_t dlpem:1;
                 uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t dlpem:1;
-                uint32_t sdem:1;
-                uint32_t reserved_6_11:6;
-                uint32_t ptlpm:1;
-                uint32_t fcpem:1;
-                uint32_t ctm:1;
-                uint32_t cam:1;
-                uint32_t ucm:1;
-                uint32_t rom:1;
-                uint32_t mtlpm:1;
-                uint32_t ecrcem:1;
-                uint32_t urem:1;
-                uint32_t reserved_21_23:3;
-                uint32_t uatombm:1;
-                uint32_t reserved_25_31:7;
-#endif
-        } cn61xx;
-        struct cvmx_pciercx_cfg066_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg066_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg066_cn61xx cn66xx;
-        struct cvmx_pciercx_cfg066_cn61xx cn68xx;
-        struct cvmx_pciercx_cfg066_cn52xx cn68xxp1;
-        struct cvmx_pciercx_cfg066_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg066_s cn52xx;
+        struct cvmx_pciercx_cfg066_s cn52xxp1;
+        struct cvmx_pciercx_cfg066_s cn56xx;
+        struct cvmx_pciercx_cfg066_s cn56xxp1;
+        struct cvmx_pciercx_cfg066_s cn63xx;
+        struct cvmx_pciercx_cfg066_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg067 {
         uint32_t u32;
         struct cvmx_pciercx_cfg067_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_25_31:7;
-                uint32_t uatombs:1;
-                uint32_t reserved_23_23:1;
-                uint32_t ucies:1;
-                uint32_t reserved_21_21:1;
-                uint32_t ures:1;
-                uint32_t ecrces:1;
-                uint32_t mtlps:1;
-                uint32_t ros:1;
-                uint32_t ucs:1;
-                uint32_t cas:1;
-                uint32_t cts:1;
-                uint32_t fcpes:1;
-                uint32_t ptlps:1;
-                uint32_t reserved_6_11:6;
-                uint32_t sdes:1;
-                uint32_t dlpes:1;
-                uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t dlpes:1;
-                uint32_t sdes:1;
-                uint32_t reserved_6_11:6;
-                uint32_t ptlps:1;
-                uint32_t fcpes:1;
-                uint32_t cts:1;
-                uint32_t cas:1;
-                uint32_t ucs:1;
-                uint32_t ros:1;
-                uint32_t mtlps:1;
-                uint32_t ecrces:1;
-                uint32_t ures:1;
-                uint32_t reserved_21_21:1;
-                uint32_t ucies:1;
-                uint32_t reserved_23_23:1;
-                uint32_t uatombs:1;
-                uint32_t reserved_25_31:7;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg067_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_21_31:11;
-                uint32_t ures:1;
-                uint32_t ecrces:1;
-                uint32_t mtlps:1;
-                uint32_t ros:1;
-                uint32_t ucs:1;
-                uint32_t cas:1;
-                uint32_t cts:1;
-                uint32_t fcpes:1;
-                uint32_t ptlps:1;
-                uint32_t reserved_6_11:6;
-                uint32_t sdes:1;
-                uint32_t dlpes:1;
-                uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t dlpes:1;
-                uint32_t sdes:1;
-                uint32_t reserved_6_11:6;
-                uint32_t ptlps:1;
-                uint32_t fcpes:1;
-                uint32_t cts:1;
-                uint32_t cas:1;
-                uint32_t ucs:1;
-                uint32_t ros:1;
-                uint32_t mtlps:1;
-                uint32_t ecrces:1;
-                uint32_t ures:1;
                 uint32_t reserved_21_31:11;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg067_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg067_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg067_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg067_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_25_31:7;
-                uint32_t uatombs:1;
-                uint32_t reserved_21_23:3;
                 uint32_t ures:1;
                 uint32_t ecrces:1;
                 uint32_t mtlps:1;
@@ -1955,62 +899,18 @@ union cvmx_pciercx_cfg067 {
                 uint32_t sdes:1;
                 uint32_t dlpes:1;
                 uint32_t reserved_0_3:4;
-#else
-                uint32_t reserved_0_3:4;
-                uint32_t dlpes:1;
-                uint32_t sdes:1;
-                uint32_t reserved_6_11:6;
-                uint32_t ptlps:1;
-                uint32_t fcpes:1;
-                uint32_t cts:1;
-                uint32_t cas:1;
-                uint32_t ucs:1;
-                uint32_t ros:1;
-                uint32_t mtlps:1;
-                uint32_t ecrces:1;
-                uint32_t ures:1;
-                uint32_t reserved_21_23:3;
-                uint32_t uatombs:1;
-                uint32_t reserved_25_31:7;
-#endif
-        } cn61xx;
-        struct cvmx_pciercx_cfg067_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg067_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg067_cn61xx cn66xx;
-        struct cvmx_pciercx_cfg067_cn61xx cn68xx;
-        struct cvmx_pciercx_cfg067_cn52xx cn68xxp1;
-        struct cvmx_pciercx_cfg067_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg067_s cn52xx;
+        struct cvmx_pciercx_cfg067_s cn52xxp1;
+        struct cvmx_pciercx_cfg067_s cn56xx;
+        struct cvmx_pciercx_cfg067_s cn56xxp1;
+        struct cvmx_pciercx_cfg067_s cn63xx;
+        struct cvmx_pciercx_cfg067_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg068 {
         uint32_t u32;
         struct cvmx_pciercx_cfg068_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_15_31:17;
-                uint32_t cies:1;
-                uint32_t anfes:1;
-                uint32_t rtts:1;
-                uint32_t reserved_9_11:3;
-                uint32_t rnrs:1;
-                uint32_t bdllps:1;
-                uint32_t btlps:1;
-                uint32_t reserved_1_5:5;
-                uint32_t res:1;
-#else
-                uint32_t res:1;
-                uint32_t reserved_1_5:5;
-                uint32_t btlps:1;
-                uint32_t bdllps:1;
-                uint32_t rnrs:1;
-                uint32_t reserved_9_11:3;
-                uint32_t rtts:1;
-                uint32_t anfes:1;
-                uint32_t cies:1;
-                uint32_t reserved_15_31:17;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg068_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_14_31:18;
                 uint32_t anfes:1;
                 uint32_t rtts:1;
@@ -2020,59 +920,18 @@ union cvmx_pciercx_cfg068 {
                 uint32_t btlps:1;
                 uint32_t reserved_1_5:5;
                 uint32_t res:1;
-#else
-                uint32_t res:1;
-                uint32_t reserved_1_5:5;
-                uint32_t btlps:1;
-                uint32_t bdllps:1;
-                uint32_t rnrs:1;
-                uint32_t reserved_9_11:3;
-                uint32_t rtts:1;
-                uint32_t anfes:1;
-                uint32_t reserved_14_31:18;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg068_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg068_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg068_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg068_cn52xx cn61xx;
-        struct cvmx_pciercx_cfg068_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg068_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg068_cn52xx cn66xx;
-        struct cvmx_pciercx_cfg068_cn52xx cn68xx;
-        struct cvmx_pciercx_cfg068_cn52xx cn68xxp1;
-        struct cvmx_pciercx_cfg068_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg068_s cn52xx;
+        struct cvmx_pciercx_cfg068_s cn52xxp1;
+        struct cvmx_pciercx_cfg068_s cn56xx;
+        struct cvmx_pciercx_cfg068_s cn56xxp1;
+        struct cvmx_pciercx_cfg068_s cn63xx;
+        struct cvmx_pciercx_cfg068_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg069 {
         uint32_t u32;
         struct cvmx_pciercx_cfg069_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_15_31:17;
-                uint32_t ciem:1;
-                uint32_t anfem:1;
-                uint32_t rttm:1;
-                uint32_t reserved_9_11:3;
-                uint32_t rnrm:1;
-                uint32_t bdllpm:1;
-                uint32_t btlpm:1;
-                uint32_t reserved_1_5:5;
-                uint32_t rem:1;
-#else
-                uint32_t rem:1;
-                uint32_t reserved_1_5:5;
-                uint32_t btlpm:1;
-                uint32_t bdllpm:1;
-                uint32_t rnrm:1;
-                uint32_t reserved_9_11:3;
-                uint32_t rttm:1;
-                uint32_t anfem:1;
-                uint32_t ciem:1;
-                uint32_t reserved_15_31:17;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg069_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_14_31:18;
                 uint32_t anfem:1;
                 uint32_t rttm:1;
@@ -2082,182 +941,104 @@ union cvmx_pciercx_cfg069 {
                 uint32_t btlpm:1;
                 uint32_t reserved_1_5:5;
                 uint32_t rem:1;
-#else
-                uint32_t rem:1;
-                uint32_t reserved_1_5:5;
-                uint32_t btlpm:1;
-                uint32_t bdllpm:1;
-                uint32_t rnrm:1;
-                uint32_t reserved_9_11:3;
-                uint32_t rttm:1;
-                uint32_t anfem:1;
-                uint32_t reserved_14_31:18;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg069_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg069_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg069_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg069_cn52xx cn61xx;
-        struct cvmx_pciercx_cfg069_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg069_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg069_cn52xx cn66xx;
-        struct cvmx_pciercx_cfg069_cn52xx cn68xx;
-        struct cvmx_pciercx_cfg069_cn52xx cn68xxp1;
-        struct cvmx_pciercx_cfg069_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg069_s cn52xx;
+        struct cvmx_pciercx_cfg069_s cn52xxp1;
+        struct cvmx_pciercx_cfg069_s cn56xx;
+        struct cvmx_pciercx_cfg069_s cn56xxp1;
+        struct cvmx_pciercx_cfg069_s cn63xx;
+        struct cvmx_pciercx_cfg069_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg070 {
         uint32_t u32;
         struct cvmx_pciercx_cfg070_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_9_31:23;
                 uint32_t ce:1;
                 uint32_t cc:1;
                 uint32_t ge:1;
                 uint32_t gc:1;
                 uint32_t fep:5;
-#else
-                uint32_t fep:5;
-                uint32_t gc:1;
-                uint32_t ge:1;
-                uint32_t cc:1;
-                uint32_t ce:1;
-                uint32_t reserved_9_31:23;
-#endif
         } s;
         struct cvmx_pciercx_cfg070_s cn52xx;
         struct cvmx_pciercx_cfg070_s cn52xxp1;
         struct cvmx_pciercx_cfg070_s cn56xx;
         struct cvmx_pciercx_cfg070_s cn56xxp1;
-        struct cvmx_pciercx_cfg070_s cn61xx;
         struct cvmx_pciercx_cfg070_s cn63xx;
         struct cvmx_pciercx_cfg070_s cn63xxp1;
-        struct cvmx_pciercx_cfg070_s cn66xx;
-        struct cvmx_pciercx_cfg070_s cn68xx;
-        struct cvmx_pciercx_cfg070_s cn68xxp1;
-        struct cvmx_pciercx_cfg070_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg071 {
         uint32_t u32;
         struct cvmx_pciercx_cfg071_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t dword1:32;
-#else
-                uint32_t dword1:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg071_s cn52xx;
         struct cvmx_pciercx_cfg071_s cn52xxp1;
         struct cvmx_pciercx_cfg071_s cn56xx;
         struct cvmx_pciercx_cfg071_s cn56xxp1;
-        struct cvmx_pciercx_cfg071_s cn61xx;
         struct cvmx_pciercx_cfg071_s cn63xx;
         struct cvmx_pciercx_cfg071_s cn63xxp1;
-        struct cvmx_pciercx_cfg071_s cn66xx;
-        struct cvmx_pciercx_cfg071_s cn68xx;
-        struct cvmx_pciercx_cfg071_s cn68xxp1;
-        struct cvmx_pciercx_cfg071_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg072 {
         uint32_t u32;
         struct cvmx_pciercx_cfg072_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t dword2:32;
-#else
                 uint32_t dword2:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg072_s cn52xx;
         struct cvmx_pciercx_cfg072_s cn52xxp1;
         struct cvmx_pciercx_cfg072_s cn56xx;
         struct cvmx_pciercx_cfg072_s cn56xxp1;
-        struct cvmx_pciercx_cfg072_s cn61xx;
         struct cvmx_pciercx_cfg072_s cn63xx;
         struct cvmx_pciercx_cfg072_s cn63xxp1;
-        struct cvmx_pciercx_cfg072_s cn66xx;
-        struct cvmx_pciercx_cfg072_s cn68xx;
-        struct cvmx_pciercx_cfg072_s cn68xxp1;
-        struct cvmx_pciercx_cfg072_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg073 {
         uint32_t u32;
         struct cvmx_pciercx_cfg073_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t dword3:32;
-#else
                 uint32_t dword3:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg073_s cn52xx;
         struct cvmx_pciercx_cfg073_s cn52xxp1;
         struct cvmx_pciercx_cfg073_s cn56xx;
         struct cvmx_pciercx_cfg073_s cn56xxp1;
-        struct cvmx_pciercx_cfg073_s cn61xx;
         struct cvmx_pciercx_cfg073_s cn63xx;
         struct cvmx_pciercx_cfg073_s cn63xxp1;
-        struct cvmx_pciercx_cfg073_s cn66xx;
-        struct cvmx_pciercx_cfg073_s cn68xx;
-        struct cvmx_pciercx_cfg073_s cn68xxp1;
-        struct cvmx_pciercx_cfg073_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg074 {
         uint32_t u32;
         struct cvmx_pciercx_cfg074_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t dword4:32;
-#else
                 uint32_t dword4:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg074_s cn52xx;
         struct cvmx_pciercx_cfg074_s cn52xxp1;
         struct cvmx_pciercx_cfg074_s cn56xx;
         struct cvmx_pciercx_cfg074_s cn56xxp1;
-        struct cvmx_pciercx_cfg074_s cn61xx;
         struct cvmx_pciercx_cfg074_s cn63xx;
         struct cvmx_pciercx_cfg074_s cn63xxp1;
-        struct cvmx_pciercx_cfg074_s cn66xx;
-        struct cvmx_pciercx_cfg074_s cn68xx;
-        struct cvmx_pciercx_cfg074_s cn68xxp1;
-        struct cvmx_pciercx_cfg074_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg075 {
         uint32_t u32;
         struct cvmx_pciercx_cfg075_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_3_31:29;
                 uint32_t fere:1;
                 uint32_t nfere:1;
                 uint32_t cere:1;
-#else
-                uint32_t cere:1;
-                uint32_t nfere:1;
-                uint32_t fere:1;
-                uint32_t reserved_3_31:29;
-#endif
         } s;
         struct cvmx_pciercx_cfg075_s cn52xx;
         struct cvmx_pciercx_cfg075_s cn52xxp1;
         struct cvmx_pciercx_cfg075_s cn56xx;
         struct cvmx_pciercx_cfg075_s cn56xxp1;
-        struct cvmx_pciercx_cfg075_s cn61xx;
         struct cvmx_pciercx_cfg075_s cn63xx;
         struct cvmx_pciercx_cfg075_s cn63xxp1;
-        struct cvmx_pciercx_cfg075_s cn66xx;
-        struct cvmx_pciercx_cfg075_s cn68xx;
-        struct cvmx_pciercx_cfg075_s cn68xxp1;
-        struct cvmx_pciercx_cfg075_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg076 {
         uint32_t u32;
         struct cvmx_pciercx_cfg076_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t aeimn:5;
                 uint32_t reserved_7_26:20;
                 uint32_t femr:1;
@@ -2267,187 +1048,95 @@ union cvmx_pciercx_cfg076 {
                 uint32_t efnfr:1;
                 uint32_t multi_ecr:1;
                 uint32_t ecr:1;
-#else
-                uint32_t ecr:1;
-                uint32_t multi_ecr:1;
-                uint32_t efnfr:1;
-                uint32_t multi_efnfr:1;
-                uint32_t fuf:1;
-                uint32_t nfemr:1;
-                uint32_t femr:1;
-                uint32_t reserved_7_26:20;
-                uint32_t aeimn:5;
-#endif
         } s;
         struct cvmx_pciercx_cfg076_s cn52xx;
         struct cvmx_pciercx_cfg076_s cn52xxp1;
         struct cvmx_pciercx_cfg076_s cn56xx;
         struct cvmx_pciercx_cfg076_s cn56xxp1;
-        struct cvmx_pciercx_cfg076_s cn61xx;
         struct cvmx_pciercx_cfg076_s cn63xx;
         struct cvmx_pciercx_cfg076_s cn63xxp1;
-        struct cvmx_pciercx_cfg076_s cn66xx;
-        struct cvmx_pciercx_cfg076_s cn68xx;
-        struct cvmx_pciercx_cfg076_s cn68xxp1;
-        struct cvmx_pciercx_cfg076_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg077 {
         uint32_t u32;
         struct cvmx_pciercx_cfg077_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t efnfsi:16;
                 uint32_t ecsi:16;
-#else
-                uint32_t ecsi:16;
-                uint32_t efnfsi:16;
-#endif
         } s;
         struct cvmx_pciercx_cfg077_s cn52xx;
         struct cvmx_pciercx_cfg077_s cn52xxp1;
         struct cvmx_pciercx_cfg077_s cn56xx;
         struct cvmx_pciercx_cfg077_s cn56xxp1;
-        struct cvmx_pciercx_cfg077_s cn61xx;
         struct cvmx_pciercx_cfg077_s cn63xx;
         struct cvmx_pciercx_cfg077_s cn63xxp1;
-        struct cvmx_pciercx_cfg077_s cn66xx;
-        struct cvmx_pciercx_cfg077_s cn68xx;
-        struct cvmx_pciercx_cfg077_s cn68xxp1;
-        struct cvmx_pciercx_cfg077_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg448 {
         uint32_t u32;
         struct cvmx_pciercx_cfg448_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t rtl:16;
                 uint32_t rtltl:16;
-#else
-                uint32_t rtltl:16;
-                uint32_t rtl:16;
-#endif
         } s;
         struct cvmx_pciercx_cfg448_s cn52xx;
         struct cvmx_pciercx_cfg448_s cn52xxp1;
         struct cvmx_pciercx_cfg448_s cn56xx;
         struct cvmx_pciercx_cfg448_s cn56xxp1;
-        struct cvmx_pciercx_cfg448_s cn61xx;
         struct cvmx_pciercx_cfg448_s cn63xx;
         struct cvmx_pciercx_cfg448_s cn63xxp1;
-        struct cvmx_pciercx_cfg448_s cn66xx;
-        struct cvmx_pciercx_cfg448_s cn68xx;
-        struct cvmx_pciercx_cfg448_s cn68xxp1;
-        struct cvmx_pciercx_cfg448_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg449 {
         uint32_t u32;
         struct cvmx_pciercx_cfg449_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t omr:32;
-#else
-                uint32_t omr:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg449_s cn52xx;
         struct cvmx_pciercx_cfg449_s cn52xxp1;
         struct cvmx_pciercx_cfg449_s cn56xx;
         struct cvmx_pciercx_cfg449_s cn56xxp1;
-        struct cvmx_pciercx_cfg449_s cn61xx;
         struct cvmx_pciercx_cfg449_s cn63xx;
         struct cvmx_pciercx_cfg449_s cn63xxp1;
-        struct cvmx_pciercx_cfg449_s cn66xx;
-        struct cvmx_pciercx_cfg449_s cn68xx;
-        struct cvmx_pciercx_cfg449_s cn68xxp1;
-        struct cvmx_pciercx_cfg449_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg450 {
         uint32_t u32;
         struct cvmx_pciercx_cfg450_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t lpec:8;
                 uint32_t reserved_22_23:2;
                 uint32_t link_state:6;
                 uint32_t force_link:1;
                 uint32_t reserved_8_14:7;
                 uint32_t link_num:8;
-#else
-                uint32_t link_num:8;
-                uint32_t reserved_8_14:7;
-                uint32_t force_link:1;
-                uint32_t link_state:6;
-                uint32_t reserved_22_23:2;
-                uint32_t lpec:8;
-#endif
         } s;
         struct cvmx_pciercx_cfg450_s cn52xx;
         struct cvmx_pciercx_cfg450_s cn52xxp1;
         struct cvmx_pciercx_cfg450_s cn56xx;
         struct cvmx_pciercx_cfg450_s cn56xxp1;
-        struct cvmx_pciercx_cfg450_s cn61xx;
         struct cvmx_pciercx_cfg450_s cn63xx;
         struct cvmx_pciercx_cfg450_s cn63xxp1;
-        struct cvmx_pciercx_cfg450_s cn66xx;
-        struct cvmx_pciercx_cfg450_s cn68xx;
-        struct cvmx_pciercx_cfg450_s cn68xxp1;
-        struct cvmx_pciercx_cfg450_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg451 {
         uint32_t u32;
         struct cvmx_pciercx_cfg451_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_31_31:1;
-                uint32_t easpml1:1;
-                uint32_t l1el:3;
-                uint32_t l0el:3;
-                uint32_t n_fts_cc:8;
-                uint32_t n_fts:8;
-                uint32_t ack_freq:8;
-#else
-                uint32_t ack_freq:8;
-                uint32_t n_fts:8;
-                uint32_t n_fts_cc:8;
-                uint32_t l0el:3;
-                uint32_t l1el:3;
-                uint32_t easpml1:1;
-                uint32_t reserved_31_31:1;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg451_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_30_31:2;
                 uint32_t l1el:3;
                 uint32_t l0el:3;
                 uint32_t n_fts_cc:8;
                 uint32_t n_fts:8;
                 uint32_t ack_freq:8;
-#else
-                uint32_t ack_freq:8;
-                uint32_t n_fts:8;
-                uint32_t n_fts_cc:8;
-                uint32_t l0el:3;
-                uint32_t l1el:3;
-                uint32_t reserved_30_31:2;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg451_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg451_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg451_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg451_s cn61xx;
-        struct cvmx_pciercx_cfg451_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg451_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg451_s cn66xx;
-        struct cvmx_pciercx_cfg451_s cn68xx;
-        struct cvmx_pciercx_cfg451_s cn68xxp1;
-        struct cvmx_pciercx_cfg451_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg451_s cn52xx;
+        struct cvmx_pciercx_cfg451_s cn52xxp1;
+        struct cvmx_pciercx_cfg451_s cn56xx;
+        struct cvmx_pciercx_cfg451_s cn56xxp1;
+        struct cvmx_pciercx_cfg451_s cn63xx;
+        struct cvmx_pciercx_cfg451_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg452 {
         uint32_t u32;
         struct cvmx_pciercx_cfg452_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_26_31:6;
                 uint32_t eccrc:1;
                 uint32_t reserved_22_24:3;
@@ -2461,114 +1150,35 @@ union cvmx_pciercx_cfg452 {
                 uint32_t le:1;
                 uint32_t sd:1;
                 uint32_t omr:1;
-#else
-                uint32_t omr:1;
-                uint32_t sd:1;
-                uint32_t le:1;
-                uint32_t ra:1;
-                uint32_t reserved_4_4:1;
-                uint32_t dllle:1;
-                uint32_t reserved_6_6:1;
-                uint32_t flm:1;
-                uint32_t reserved_8_15:8;
-                uint32_t lme:6;
-                uint32_t reserved_22_24:3;
-                uint32_t eccrc:1;
-                uint32_t reserved_26_31:6;
-#endif
         } s;
         struct cvmx_pciercx_cfg452_s cn52xx;
         struct cvmx_pciercx_cfg452_s cn52xxp1;
         struct cvmx_pciercx_cfg452_s cn56xx;
         struct cvmx_pciercx_cfg452_s cn56xxp1;
-        struct cvmx_pciercx_cfg452_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_22_31:10;
-                uint32_t lme:6;
-                uint32_t reserved_8_15:8;
-                uint32_t flm:1;
-                uint32_t reserved_6_6:1;
-                uint32_t dllle:1;
-                uint32_t reserved_4_4:1;
-                uint32_t ra:1;
-                uint32_t le:1;
-                uint32_t sd:1;
-                uint32_t omr:1;
-#else
-                uint32_t omr:1;
-                uint32_t sd:1;
-                uint32_t le:1;
-                uint32_t ra:1;
-                uint32_t reserved_4_4:1;
-                uint32_t dllle:1;
-                uint32_t reserved_6_6:1;
-                uint32_t flm:1;
-                uint32_t reserved_8_15:8;
-                uint32_t lme:6;
-                uint32_t reserved_22_31:10;
-#endif
-        } cn61xx;
         struct cvmx_pciercx_cfg452_s cn63xx;
         struct cvmx_pciercx_cfg452_s cn63xxp1;
-        struct cvmx_pciercx_cfg452_cn61xx cn66xx;
-        struct cvmx_pciercx_cfg452_cn61xx cn68xx;
-        struct cvmx_pciercx_cfg452_cn61xx cn68xxp1;
-        struct cvmx_pciercx_cfg452_cn61xx cnf71xx;
 };
 
 union cvmx_pciercx_cfg453 {
         uint32_t u32;
         struct cvmx_pciercx_cfg453_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t dlld:1;
                 uint32_t reserved_26_30:5;
                 uint32_t ack_nak:1;
                 uint32_t fcd:1;
                 uint32_t ilst:24;
-#else
-                uint32_t ilst:24;
-                uint32_t fcd:1;
-                uint32_t ack_nak:1;
-                uint32_t reserved_26_30:5;
-                uint32_t dlld:1;
-#endif
         } s;
         struct cvmx_pciercx_cfg453_s cn52xx;
         struct cvmx_pciercx_cfg453_s cn52xxp1;
         struct cvmx_pciercx_cfg453_s cn56xx;
         struct cvmx_pciercx_cfg453_s cn56xxp1;
-        struct cvmx_pciercx_cfg453_s cn61xx;
         struct cvmx_pciercx_cfg453_s cn63xx;
         struct cvmx_pciercx_cfg453_s cn63xxp1;
-        struct cvmx_pciercx_cfg453_s cn66xx;
-        struct cvmx_pciercx_cfg453_s cn68xx;
-        struct cvmx_pciercx_cfg453_s cn68xxp1;
-        struct cvmx_pciercx_cfg453_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg454 {
         uint32_t u32;
         struct cvmx_pciercx_cfg454_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t cx_nfunc:3;
-                uint32_t tmfcwt:5;
-                uint32_t tmanlt:5;
-                uint32_t tmrt:5;
-                uint32_t reserved_11_13:3;
-                uint32_t nskps:3;
-                uint32_t reserved_0_7:8;
-#else
-                uint32_t reserved_0_7:8;
-                uint32_t nskps:3;
-                uint32_t reserved_11_13:3;
-                uint32_t tmrt:5;
-                uint32_t tmanlt:5;
-                uint32_t tmfcwt:5;
-                uint32_t cx_nfunc:3;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg454_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_29_31:3;
                 uint32_t tmfcwt:5;
                 uint32_t tmanlt:5;
@@ -2577,49 +1187,18 @@ union cvmx_pciercx_cfg454 {
                 uint32_t nskps:3;
                 uint32_t reserved_4_7:4;
                 uint32_t ntss:4;
-#else
-                uint32_t ntss:4;
-                uint32_t reserved_4_7:4;
-                uint32_t nskps:3;
-                uint32_t reserved_11_13:3;
-                uint32_t tmrt:5;
-                uint32_t tmanlt:5;
-                uint32_t tmfcwt:5;
-                uint32_t reserved_29_31:3;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg454_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg454_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg454_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg454_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t cx_nfunc:3;
-                uint32_t tmfcwt:5;
-                uint32_t tmanlt:5;
-                uint32_t tmrt:5;
-                uint32_t reserved_8_13:6;
-                uint32_t mfuncn:8;
-#else
-                uint32_t mfuncn:8;
-                uint32_t reserved_8_13:6;
-                uint32_t tmrt:5;
-                uint32_t tmanlt:5;
-                uint32_t tmfcwt:5;
-                uint32_t cx_nfunc:3;
-#endif
-        } cn61xx;
-        struct cvmx_pciercx_cfg454_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg454_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg454_cn61xx cn66xx;
-        struct cvmx_pciercx_cfg454_cn61xx cn68xx;
-        struct cvmx_pciercx_cfg454_cn52xx cn68xxp1;
-        struct cvmx_pciercx_cfg454_cn61xx cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg454_s cn52xx;
+        struct cvmx_pciercx_cfg454_s cn52xxp1;
+        struct cvmx_pciercx_cfg454_s cn56xx;
+        struct cvmx_pciercx_cfg454_s cn56xxp1;
+        struct cvmx_pciercx_cfg454_s cn63xx;
+        struct cvmx_pciercx_cfg454_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg455 {
         uint32_t u32;
         struct cvmx_pciercx_cfg455_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t m_cfg0_filt:1;
                 uint32_t m_io_filt:1;
                 uint32_t msg_ctrl:1;
@@ -2639,291 +1218,152 @@ union cvmx_pciercx_cfg455 {
                 uint32_t dfcwt:1;
                 uint32_t reserved_11_14:4;
                 uint32_t skpiv:11;
-#else
-                uint32_t skpiv:11;
-                uint32_t reserved_11_14:4;
-                uint32_t dfcwt:1;
-                uint32_t m_fun:1;
-                uint32_t m_pois_filt:1;
-                uint32_t m_bar_match:1;
-                uint32_t m_cfg1_filt:1;
-                uint32_t m_lk_filt:1;
-                uint32_t m_cpl_tag_err:1;
-                uint32_t m_cpl_rid_err:1;
-                uint32_t m_cpl_fun_err:1;
-                uint32_t m_cpl_tc_err:1;
-                uint32_t m_cpl_attr_err:1;
-                uint32_t m_cpl_len_err:1;
-                uint32_t m_ecrc_filt:1;
-                uint32_t m_cpl_ecrc_filt:1;
-                uint32_t msg_ctrl:1;
-                uint32_t m_io_filt:1;
-                uint32_t m_cfg0_filt:1;
-#endif
         } s;
         struct cvmx_pciercx_cfg455_s cn52xx;
         struct cvmx_pciercx_cfg455_s cn52xxp1;
         struct cvmx_pciercx_cfg455_s cn56xx;
         struct cvmx_pciercx_cfg455_s cn56xxp1;
-        struct cvmx_pciercx_cfg455_s cn61xx;
         struct cvmx_pciercx_cfg455_s cn63xx;
         struct cvmx_pciercx_cfg455_s cn63xxp1;
-        struct cvmx_pciercx_cfg455_s cn66xx;
-        struct cvmx_pciercx_cfg455_s cn68xx;
-        struct cvmx_pciercx_cfg455_s cn68xxp1;
-        struct cvmx_pciercx_cfg455_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg456 {
         uint32_t u32;
         struct cvmx_pciercx_cfg456_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t reserved_4_31:28;
-                uint32_t m_handle_flush:1;
-                uint32_t m_dabort_4ucpl:1;
-                uint32_t m_vend1_drp:1;
-                uint32_t m_vend0_drp:1;
-#else
-                uint32_t m_vend0_drp:1;
-                uint32_t m_vend1_drp:1;
-                uint32_t m_dabort_4ucpl:1;
-                uint32_t m_handle_flush:1;
-                uint32_t reserved_4_31:28;
-#endif
-        } s;
-        struct cvmx_pciercx_cfg456_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_2_31:30;
                 uint32_t m_vend1_drp:1;
                 uint32_t m_vend0_drp:1;
-#else
-                uint32_t m_vend0_drp:1;
-                uint32_t m_vend1_drp:1;
-                uint32_t reserved_2_31:30;
-#endif
-        } cn52xx;
-        struct cvmx_pciercx_cfg456_cn52xx cn52xxp1;
-        struct cvmx_pciercx_cfg456_cn52xx cn56xx;
-        struct cvmx_pciercx_cfg456_cn52xx cn56xxp1;
-        struct cvmx_pciercx_cfg456_s cn61xx;
-        struct cvmx_pciercx_cfg456_cn52xx cn63xx;
-        struct cvmx_pciercx_cfg456_cn52xx cn63xxp1;
-        struct cvmx_pciercx_cfg456_s cn66xx;
-        struct cvmx_pciercx_cfg456_s cn68xx;
-        struct cvmx_pciercx_cfg456_cn52xx cn68xxp1;
-        struct cvmx_pciercx_cfg456_s cnf71xx;
+        } s;
+        struct cvmx_pciercx_cfg456_s cn52xx;
+        struct cvmx_pciercx_cfg456_s cn52xxp1;
+        struct cvmx_pciercx_cfg456_s cn56xx;
+        struct cvmx_pciercx_cfg456_s cn56xxp1;
+        struct cvmx_pciercx_cfg456_s cn63xx;
+        struct cvmx_pciercx_cfg456_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg458 {
         uint32_t u32;
         struct cvmx_pciercx_cfg458_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t dbg_info_l32:32;
-#else
                 uint32_t dbg_info_l32:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg458_s cn52xx;
         struct cvmx_pciercx_cfg458_s cn52xxp1;
         struct cvmx_pciercx_cfg458_s cn56xx;
         struct cvmx_pciercx_cfg458_s cn56xxp1;
-        struct cvmx_pciercx_cfg458_s cn61xx;
         struct cvmx_pciercx_cfg458_s cn63xx;
         struct cvmx_pciercx_cfg458_s cn63xxp1;
-        struct cvmx_pciercx_cfg458_s cn66xx;
-        struct cvmx_pciercx_cfg458_s cn68xx;
-        struct cvmx_pciercx_cfg458_s cn68xxp1;
-        struct cvmx_pciercx_cfg458_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg459 {
         uint32_t u32;
         struct cvmx_pciercx_cfg459_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t dbg_info_u32:32;
-#else
                 uint32_t dbg_info_u32:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg459_s cn52xx;
         struct cvmx_pciercx_cfg459_s cn52xxp1;
         struct cvmx_pciercx_cfg459_s cn56xx;
         struct cvmx_pciercx_cfg459_s cn56xxp1;
-        struct cvmx_pciercx_cfg459_s cn61xx;
         struct cvmx_pciercx_cfg459_s cn63xx;
         struct cvmx_pciercx_cfg459_s cn63xxp1;
-        struct cvmx_pciercx_cfg459_s cn66xx;
-        struct cvmx_pciercx_cfg459_s cn68xx;
-        struct cvmx_pciercx_cfg459_s cn68xxp1;
-        struct cvmx_pciercx_cfg459_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg460 {
         uint32_t u32;
         struct cvmx_pciercx_cfg460_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_20_31:12;
                 uint32_t tphfcc:8;
                 uint32_t tpdfcc:12;
-#else
-                uint32_t tpdfcc:12;
-                uint32_t tphfcc:8;
-                uint32_t reserved_20_31:12;
-#endif
         } s;
         struct cvmx_pciercx_cfg460_s cn52xx;
         struct cvmx_pciercx_cfg460_s cn52xxp1;
         struct cvmx_pciercx_cfg460_s cn56xx;
         struct cvmx_pciercx_cfg460_s cn56xxp1;
-        struct cvmx_pciercx_cfg460_s cn61xx;
         struct cvmx_pciercx_cfg460_s cn63xx;
         struct cvmx_pciercx_cfg460_s cn63xxp1;
-        struct cvmx_pciercx_cfg460_s cn66xx;
-        struct cvmx_pciercx_cfg460_s cn68xx;
-        struct cvmx_pciercx_cfg460_s cn68xxp1;
-        struct cvmx_pciercx_cfg460_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg461 {
         uint32_t u32;
         struct cvmx_pciercx_cfg461_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_20_31:12;
                 uint32_t tchfcc:8;
                 uint32_t tcdfcc:12;
-#else
-                uint32_t tcdfcc:12;
-                uint32_t tchfcc:8;
-                uint32_t reserved_20_31:12;
-#endif
         } s;
         struct cvmx_pciercx_cfg461_s cn52xx;
         struct cvmx_pciercx_cfg461_s cn52xxp1;
         struct cvmx_pciercx_cfg461_s cn56xx;
         struct cvmx_pciercx_cfg461_s cn56xxp1;
-        struct cvmx_pciercx_cfg461_s cn61xx;
         struct cvmx_pciercx_cfg461_s cn63xx;
         struct cvmx_pciercx_cfg461_s cn63xxp1;
-        struct cvmx_pciercx_cfg461_s cn66xx;
-        struct cvmx_pciercx_cfg461_s cn68xx;
-        struct cvmx_pciercx_cfg461_s cn68xxp1;
-        struct cvmx_pciercx_cfg461_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg462 {
         uint32_t u32;
         struct cvmx_pciercx_cfg462_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_20_31:12;
                 uint32_t tchfcc:8;
                 uint32_t tcdfcc:12;
-#else
-                uint32_t tcdfcc:12;
-                uint32_t tchfcc:8;
-                uint32_t reserved_20_31:12;
-#endif
         } s;
         struct cvmx_pciercx_cfg462_s cn52xx;
         struct cvmx_pciercx_cfg462_s cn52xxp1;
         struct cvmx_pciercx_cfg462_s cn56xx;
         struct cvmx_pciercx_cfg462_s cn56xxp1;
-        struct cvmx_pciercx_cfg462_s cn61xx;
         struct cvmx_pciercx_cfg462_s cn63xx;
         struct cvmx_pciercx_cfg462_s cn63xxp1;
-        struct cvmx_pciercx_cfg462_s cn66xx;
-        struct cvmx_pciercx_cfg462_s cn68xx;
-        struct cvmx_pciercx_cfg462_s cn68xxp1;
-        struct cvmx_pciercx_cfg462_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg463 {
         uint32_t u32;
         struct cvmx_pciercx_cfg463_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_3_31:29;
                 uint32_t rqne:1;
                 uint32_t trbne:1;
                 uint32_t rtlpfccnr:1;
-#else
-                uint32_t rtlpfccnr:1;
-                uint32_t trbne:1;
-                uint32_t rqne:1;
-                uint32_t reserved_3_31:29;
-#endif
         } s;
         struct cvmx_pciercx_cfg463_s cn52xx;
         struct cvmx_pciercx_cfg463_s cn52xxp1;
         struct cvmx_pciercx_cfg463_s cn56xx;
         struct cvmx_pciercx_cfg463_s cn56xxp1;
-        struct cvmx_pciercx_cfg463_s cn61xx;
         struct cvmx_pciercx_cfg463_s cn63xx;
         struct cvmx_pciercx_cfg463_s cn63xxp1;
-        struct cvmx_pciercx_cfg463_s cn66xx;
-        struct cvmx_pciercx_cfg463_s cn68xx;
-        struct cvmx_pciercx_cfg463_s cn68xxp1;
-        struct cvmx_pciercx_cfg463_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg464 {
         uint32_t u32;
         struct cvmx_pciercx_cfg464_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t wrr_vc3:8;
                 uint32_t wrr_vc2:8;
                 uint32_t wrr_vc1:8;
                 uint32_t wrr_vc0:8;
-#else
-                uint32_t wrr_vc0:8;
-                uint32_t wrr_vc1:8;
-                uint32_t wrr_vc2:8;
-                uint32_t wrr_vc3:8;
-#endif
         } s;
         struct cvmx_pciercx_cfg464_s cn52xx;
         struct cvmx_pciercx_cfg464_s cn52xxp1;
         struct cvmx_pciercx_cfg464_s cn56xx;
         struct cvmx_pciercx_cfg464_s cn56xxp1;
-        struct cvmx_pciercx_cfg464_s cn61xx;
         struct cvmx_pciercx_cfg464_s cn63xx;
         struct cvmx_pciercx_cfg464_s cn63xxp1;
-        struct cvmx_pciercx_cfg464_s cn66xx;
-        struct cvmx_pciercx_cfg464_s cn68xx;
-        struct cvmx_pciercx_cfg464_s cn68xxp1;
-        struct cvmx_pciercx_cfg464_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg465 {
         uint32_t u32;
         struct cvmx_pciercx_cfg465_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t wrr_vc7:8;
                 uint32_t wrr_vc6:8;
                 uint32_t wrr_vc5:8;
                 uint32_t wrr_vc4:8;
-#else
-                uint32_t wrr_vc4:8;
-                uint32_t wrr_vc5:8;
-                uint32_t wrr_vc6:8;
-                uint32_t wrr_vc7:8;
-#endif
         } s;
         struct cvmx_pciercx_cfg465_s cn52xx;
         struct cvmx_pciercx_cfg465_s cn52xxp1;
         struct cvmx_pciercx_cfg465_s cn56xx;
         struct cvmx_pciercx_cfg465_s cn56xxp1;
-        struct cvmx_pciercx_cfg465_s cn61xx;
         struct cvmx_pciercx_cfg465_s cn63xx;
         struct cvmx_pciercx_cfg465_s cn63xxp1;
-        struct cvmx_pciercx_cfg465_s cn66xx;
-        struct cvmx_pciercx_cfg465_s cn68xx;
-        struct cvmx_pciercx_cfg465_s cn68xxp1;
-        struct cvmx_pciercx_cfg465_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg466 {
         uint32_t u32;
         struct cvmx_pciercx_cfg466_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t rx_queue_order:1;
                 uint32_t type_ordering:1;
                 uint32_t reserved_24_29:6;
@@ -2931,177 +1371,100 @@ union cvmx_pciercx_cfg466 {
                 uint32_t reserved_20_20:1;
                 uint32_t header_credits:8;
                 uint32_t data_credits:12;
-#else
-                uint32_t data_credits:12;
-                uint32_t header_credits:8;
-                uint32_t reserved_20_20:1;
-                uint32_t queue_mode:3;
-                uint32_t reserved_24_29:6;
-                uint32_t type_ordering:1;
-                uint32_t rx_queue_order:1;
-#endif
         } s;
         struct cvmx_pciercx_cfg466_s cn52xx;
         struct cvmx_pciercx_cfg466_s cn52xxp1;
         struct cvmx_pciercx_cfg466_s cn56xx;
         struct cvmx_pciercx_cfg466_s cn56xxp1;
-        struct cvmx_pciercx_cfg466_s cn61xx;
         struct cvmx_pciercx_cfg466_s cn63xx;
         struct cvmx_pciercx_cfg466_s cn63xxp1;
-        struct cvmx_pciercx_cfg466_s cn66xx;
-        struct cvmx_pciercx_cfg466_s cn68xx;
-        struct cvmx_pciercx_cfg466_s cn68xxp1;
-        struct cvmx_pciercx_cfg466_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg467 {
         uint32_t u32;
         struct cvmx_pciercx_cfg467_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_24_31:8;
                 uint32_t queue_mode:3;
                 uint32_t reserved_20_20:1;
                 uint32_t header_credits:8;
                 uint32_t data_credits:12;
-#else
-                uint32_t data_credits:12;
-                uint32_t header_credits:8;
-                uint32_t reserved_20_20:1;
-                uint32_t queue_mode:3;
-                uint32_t reserved_24_31:8;
-#endif
         } s;
         struct cvmx_pciercx_cfg467_s cn52xx;
         struct cvmx_pciercx_cfg467_s cn52xxp1;
         struct cvmx_pciercx_cfg467_s cn56xx;
         struct cvmx_pciercx_cfg467_s cn56xxp1;
-        struct cvmx_pciercx_cfg467_s cn61xx;
         struct cvmx_pciercx_cfg467_s cn63xx;
         struct cvmx_pciercx_cfg467_s cn63xxp1;
-        struct cvmx_pciercx_cfg467_s cn66xx;
-        struct cvmx_pciercx_cfg467_s cn68xx;
-        struct cvmx_pciercx_cfg467_s cn68xxp1;
-        struct cvmx_pciercx_cfg467_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg468 {
         uint32_t u32;
         struct cvmx_pciercx_cfg468_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_24_31:8;
                 uint32_t queue_mode:3;
                 uint32_t reserved_20_20:1;
                 uint32_t header_credits:8;
                 uint32_t data_credits:12;
-#else
-                uint32_t data_credits:12;
-                uint32_t header_credits:8;
-                uint32_t reserved_20_20:1;
-                uint32_t queue_mode:3;
-                uint32_t reserved_24_31:8;
-#endif
         } s;
         struct cvmx_pciercx_cfg468_s cn52xx;
         struct cvmx_pciercx_cfg468_s cn52xxp1;
         struct cvmx_pciercx_cfg468_s cn56xx;
         struct cvmx_pciercx_cfg468_s cn56xxp1;
-        struct cvmx_pciercx_cfg468_s cn61xx;
         struct cvmx_pciercx_cfg468_s cn63xx;
         struct cvmx_pciercx_cfg468_s cn63xxp1;
-        struct cvmx_pciercx_cfg468_s cn66xx;
-        struct cvmx_pciercx_cfg468_s cn68xx;
-        struct cvmx_pciercx_cfg468_s cn68xxp1;
-        struct cvmx_pciercx_cfg468_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg490 {
         uint32_t u32;
         struct cvmx_pciercx_cfg490_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_26_31:6;
                 uint32_t header_depth:10;
                 uint32_t reserved_14_15:2;
                 uint32_t data_depth:14;
-#else
-                uint32_t data_depth:14;
-                uint32_t reserved_14_15:2;
-                uint32_t header_depth:10;
-                uint32_t reserved_26_31:6;
-#endif
         } s;
         struct cvmx_pciercx_cfg490_s cn52xx;
         struct cvmx_pciercx_cfg490_s cn52xxp1;
         struct cvmx_pciercx_cfg490_s cn56xx;
         struct cvmx_pciercx_cfg490_s cn56xxp1;
-        struct cvmx_pciercx_cfg490_s cn61xx;
         struct cvmx_pciercx_cfg490_s cn63xx;
         struct cvmx_pciercx_cfg490_s cn63xxp1;
-        struct cvmx_pciercx_cfg490_s cn66xx;
-        struct cvmx_pciercx_cfg490_s cn68xx;
-        struct cvmx_pciercx_cfg490_s cn68xxp1;
-        struct cvmx_pciercx_cfg490_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg491 {
         uint32_t u32;
         struct cvmx_pciercx_cfg491_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_26_31:6;
                 uint32_t header_depth:10;
                 uint32_t reserved_14_15:2;
                 uint32_t data_depth:14;
-#else
-                uint32_t data_depth:14;
-                uint32_t reserved_14_15:2;
-                uint32_t header_depth:10;
-                uint32_t reserved_26_31:6;
-#endif
         } s;
         struct cvmx_pciercx_cfg491_s cn52xx;
         struct cvmx_pciercx_cfg491_s cn52xxp1;
         struct cvmx_pciercx_cfg491_s cn56xx;
         struct cvmx_pciercx_cfg491_s cn56xxp1;
-        struct cvmx_pciercx_cfg491_s cn61xx;
         struct cvmx_pciercx_cfg491_s cn63xx;
         struct cvmx_pciercx_cfg491_s cn63xxp1;
-        struct cvmx_pciercx_cfg491_s cn66xx;
-        struct cvmx_pciercx_cfg491_s cn68xx;
-        struct cvmx_pciercx_cfg491_s cn68xxp1;
-        struct cvmx_pciercx_cfg491_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg492 {
         uint32_t u32;
         struct cvmx_pciercx_cfg492_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_26_31:6;
                 uint32_t header_depth:10;
                 uint32_t reserved_14_15:2;
                 uint32_t data_depth:14;
-#else
-                uint32_t data_depth:14;
-                uint32_t reserved_14_15:2;
-                uint32_t header_depth:10;
-                uint32_t reserved_26_31:6;
-#endif
         } s;
         struct cvmx_pciercx_cfg492_s cn52xx;
         struct cvmx_pciercx_cfg492_s cn52xxp1;
         struct cvmx_pciercx_cfg492_s cn56xx;
         struct cvmx_pciercx_cfg492_s cn56xxp1;
-        struct cvmx_pciercx_cfg492_s cn61xx;
         struct cvmx_pciercx_cfg492_s cn63xx;
         struct cvmx_pciercx_cfg492_s cn63xxp1;
-        struct cvmx_pciercx_cfg492_s cn66xx;
-        struct cvmx_pciercx_cfg492_s cn68xx;
-        struct cvmx_pciercx_cfg492_s cn68xxp1;
-        struct cvmx_pciercx_cfg492_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg515 {
         uint32_t u32;
         struct cvmx_pciercx_cfg515_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint32_t reserved_21_31:11;
                 uint32_t s_d_e:1;
                 uint32_t ctcrb:1;
@@ -3109,67 +1472,35 @@ union cvmx_pciercx_cfg515 {
                 uint32_t dsc:1;
                 uint32_t le:9;
                 uint32_t n_fts:8;
-#else
-                uint32_t n_fts:8;
-                uint32_t le:9;
-                uint32_t dsc:1;
-                uint32_t cpyts:1;
-                uint32_t ctcrb:1;
-                uint32_t s_d_e:1;
-                uint32_t reserved_21_31:11;
-#endif
         } s;
-        struct cvmx_pciercx_cfg515_s cn61xx;
         struct cvmx_pciercx_cfg515_s cn63xx;
         struct cvmx_pciercx_cfg515_s cn63xxp1;
-        struct cvmx_pciercx_cfg515_s cn66xx;
-        struct cvmx_pciercx_cfg515_s cn68xx;
-        struct cvmx_pciercx_cfg515_s cn68xxp1;
-        struct cvmx_pciercx_cfg515_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg516 {
         uint32_t u32;
         struct cvmx_pciercx_cfg516_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t phy_stat:32;
-#else
                 uint32_t phy_stat:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg516_s cn52xx;
         struct cvmx_pciercx_cfg516_s cn52xxp1;
         struct cvmx_pciercx_cfg516_s cn56xx;
         struct cvmx_pciercx_cfg516_s cn56xxp1;
-        struct cvmx_pciercx_cfg516_s cn61xx;
         struct cvmx_pciercx_cfg516_s cn63xx;
         struct cvmx_pciercx_cfg516_s cn63xxp1;
-        struct cvmx_pciercx_cfg516_s cn66xx;
-        struct cvmx_pciercx_cfg516_s cn68xx;
-        struct cvmx_pciercx_cfg516_s cn68xxp1;
-        struct cvmx_pciercx_cfg516_s cnf71xx;
 };
 
 union cvmx_pciercx_cfg517 {
         uint32_t u32;
         struct cvmx_pciercx_cfg517_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint32_t phy_ctrl:32;
-#else
                 uint32_t phy_ctrl:32;
-#endif
         } s;
         struct cvmx_pciercx_cfg517_s cn52xx;
         struct cvmx_pciercx_cfg517_s cn52xxp1;
         struct cvmx_pciercx_cfg517_s cn56xx;
         struct cvmx_pciercx_cfg517_s cn56xxp1;
-        struct cvmx_pciercx_cfg517_s cn61xx;
         struct cvmx_pciercx_cfg517_s cn63xx;
         struct cvmx_pciercx_cfg517_s cn63xxp1;
-        struct cvmx_pciercx_cfg517_s cn66xx;
-        struct cvmx_pciercx_cfg517_s cn68xx;
-        struct cvmx_pciercx_cfg517_s cn68xxp1;
-        struct cvmx_pciercx_cfg517_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
deleted file mode 100644
index a5e8fd861c3..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
+++ /dev/null
@@ -1,1009 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_PCSX_DEFS_H__
-#define __CVMX_PCSX_DEFS_H__
-
-static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
-}
-
-union cvmx_pcsx_anx_adv_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_anx_adv_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t np:1;
-                uint64_t reserved_14_14:1;
-                uint64_t rem_flt:2;
-                uint64_t reserved_9_11:3;
-                uint64_t pause:2;
-                uint64_t hfd:1;
-                uint64_t fd:1;
-                uint64_t reserved_0_4:5;
-#else
-                uint64_t reserved_0_4:5;
-                uint64_t fd:1;
-                uint64_t hfd:1;
-                uint64_t pause:2;
-                uint64_t reserved_9_11:3;
-                uint64_t rem_flt:2;
-                uint64_t reserved_14_14:1;
-                uint64_t np:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsx_anx_adv_reg_s cn52xx;
-        struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
-        struct cvmx_pcsx_anx_adv_reg_s cn56xx;
-        struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
-        struct cvmx_pcsx_anx_adv_reg_s cn61xx;
-        struct cvmx_pcsx_anx_adv_reg_s cn63xx;
-        struct cvmx_pcsx_anx_adv_reg_s cn63xxp1;
-        struct cvmx_pcsx_anx_adv_reg_s cn66xx;
-        struct cvmx_pcsx_anx_adv_reg_s cn68xx;
-        struct cvmx_pcsx_anx_adv_reg_s cn68xxp1;
-        struct cvmx_pcsx_anx_adv_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_anx_ext_st_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_anx_ext_st_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t thou_xfd:1;
-                uint64_t thou_xhd:1;
-                uint64_t thou_tfd:1;
-                uint64_t thou_thd:1;
-                uint64_t reserved_0_11:12;
-#else
-                uint64_t reserved_0_11:12;
-                uint64_t thou_thd:1;
-                uint64_t thou_tfd:1;
-                uint64_t thou_xhd:1;
-                uint64_t thou_xfd:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn61xx;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn63xx;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn66xx;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn68xx;
-        struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1;
-        struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_anx_lp_abil_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_anx_lp_abil_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t np:1;
-                uint64_t ack:1;
-                uint64_t rem_flt:2;
-                uint64_t reserved_9_11:3;
-                uint64_t pause:2;
-                uint64_t hfd:1;
-                uint64_t fd:1;
-                uint64_t reserved_0_4:5;
-#else
-                uint64_t reserved_0_4:5;
-                uint64_t fd:1;
-                uint64_t hfd:1;
-                uint64_t pause:2;
-                uint64_t reserved_9_11:3;
-                uint64_t rem_flt:2;
-                uint64_t ack:1;
-                uint64_t np:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1;
-        struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_anx_results_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_anx_results_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t pause:2;
-                uint64_t spd:2;
-                uint64_t an_cpt:1;
-                uint64_t dup:1;
-                uint64_t link_ok:1;
-#else
-                uint64_t link_ok:1;
-                uint64_t dup:1;
-                uint64_t an_cpt:1;
-                uint64_t spd:2;
-                uint64_t pause:2;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_pcsx_anx_results_reg_s cn52xx;
-        struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
-        struct cvmx_pcsx_anx_results_reg_s cn56xx;
-        struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
-        struct cvmx_pcsx_anx_results_reg_s cn61xx;
-        struct cvmx_pcsx_anx_results_reg_s cn63xx;
-        struct cvmx_pcsx_anx_results_reg_s cn63xxp1;
-        struct cvmx_pcsx_anx_results_reg_s cn66xx;
-        struct cvmx_pcsx_anx_results_reg_s cn68xx;
-        struct cvmx_pcsx_anx_results_reg_s cn68xxp1;
-        struct cvmx_pcsx_anx_results_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_intx_en_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_intx_en_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t dbg_sync_en:1;
-                uint64_t dup:1;
-                uint64_t sync_bad_en:1;
-                uint64_t an_bad_en:1;
-                uint64_t rxlock_en:1;
-                uint64_t rxbad_en:1;
-                uint64_t rxerr_en:1;
-                uint64_t txbad_en:1;
-                uint64_t txfifo_en:1;
-                uint64_t txfifu_en:1;
-                uint64_t an_err_en:1;
-                uint64_t xmit_en:1;
-                uint64_t lnkspd_en:1;
-#else
-                uint64_t lnkspd_en:1;
-                uint64_t xmit_en:1;
-                uint64_t an_err_en:1;
-                uint64_t txfifu_en:1;
-                uint64_t txfifo_en:1;
-                uint64_t txbad_en:1;
-                uint64_t rxerr_en:1;
-                uint64_t rxbad_en:1;
-                uint64_t rxlock_en:1;
-                uint64_t an_bad_en:1;
-                uint64_t sync_bad_en:1;
-                uint64_t dup:1;
-                uint64_t dbg_sync_en:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_pcsx_intx_en_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t dup:1;
-                uint64_t sync_bad_en:1;
-                uint64_t an_bad_en:1;
-                uint64_t rxlock_en:1;
-                uint64_t rxbad_en:1;
-                uint64_t rxerr_en:1;
-                uint64_t txbad_en:1;
-                uint64_t txfifo_en:1;
-                uint64_t txfifu_en:1;
-                uint64_t an_err_en:1;
-                uint64_t xmit_en:1;
-                uint64_t lnkspd_en:1;
-#else
-                uint64_t lnkspd_en:1;
-                uint64_t xmit_en:1;
-                uint64_t an_err_en:1;
-                uint64_t txfifu_en:1;
-                uint64_t txfifo_en:1;
-                uint64_t txbad_en:1;
-                uint64_t rxerr_en:1;
-                uint64_t rxbad_en:1;
-                uint64_t rxlock_en:1;
-                uint64_t an_bad_en:1;
-                uint64_t sync_bad_en:1;
-                uint64_t dup:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn52xx;
-        struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1;
-        struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx;
-        struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1;
-        struct cvmx_pcsx_intx_en_reg_s cn61xx;
-        struct cvmx_pcsx_intx_en_reg_s cn63xx;
-        struct cvmx_pcsx_intx_en_reg_s cn63xxp1;
-        struct cvmx_pcsx_intx_en_reg_s cn66xx;
-        struct cvmx_pcsx_intx_en_reg_s cn68xx;
-        struct cvmx_pcsx_intx_en_reg_s cn68xxp1;
-        struct cvmx_pcsx_intx_en_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_intx_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_intx_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t dbg_sync:1;
-                uint64_t dup:1;
-                uint64_t sync_bad:1;
-                uint64_t an_bad:1;
-                uint64_t rxlock:1;
-                uint64_t rxbad:1;
-                uint64_t rxerr:1;
-                uint64_t txbad:1;
-                uint64_t txfifo:1;
-                uint64_t txfifu:1;
-                uint64_t an_err:1;
-                uint64_t xmit:1;
-                uint64_t lnkspd:1;
-#else
-                uint64_t lnkspd:1;
-                uint64_t xmit:1;
-                uint64_t an_err:1;
-                uint64_t txfifu:1;
-                uint64_t txfifo:1;
-                uint64_t txbad:1;
-                uint64_t rxerr:1;
-                uint64_t rxbad:1;
-                uint64_t rxlock:1;
-                uint64_t an_bad:1;
-                uint64_t sync_bad:1;
-                uint64_t dup:1;
-                uint64_t dbg_sync:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_pcsx_intx_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t dup:1;
-                uint64_t sync_bad:1;
-                uint64_t an_bad:1;
-                uint64_t rxlock:1;
-                uint64_t rxbad:1;
-                uint64_t rxerr:1;
-                uint64_t txbad:1;
-                uint64_t txfifo:1;
-                uint64_t txfifu:1;
-                uint64_t an_err:1;
-                uint64_t xmit:1;
-                uint64_t lnkspd:1;
-#else
-                uint64_t lnkspd:1;
-                uint64_t xmit:1;
-                uint64_t an_err:1;
-                uint64_t txfifu:1;
-                uint64_t txfifo:1;
-                uint64_t txbad:1;
-                uint64_t rxerr:1;
-                uint64_t rxbad:1;
-                uint64_t rxlock:1;
-                uint64_t an_bad:1;
-                uint64_t sync_bad:1;
-                uint64_t dup:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn52xx;
-        struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1;
-        struct cvmx_pcsx_intx_reg_cn52xx cn56xx;
-        struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1;
-        struct cvmx_pcsx_intx_reg_s cn61xx;
-        struct cvmx_pcsx_intx_reg_s cn63xx;
-        struct cvmx_pcsx_intx_reg_s cn63xxp1;
-        struct cvmx_pcsx_intx_reg_s cn66xx;
-        struct cvmx_pcsx_intx_reg_s cn68xx;
-        struct cvmx_pcsx_intx_reg_s cn68xxp1;
-        struct cvmx_pcsx_intx_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_linkx_timer_count_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_linkx_timer_count_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t count:16;
-#else
-                uint64_t count:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;
-        struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_log_anlx_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_log_anlx_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t lafifovfl:1;
-                uint64_t la_en:1;
-                uint64_t pkt_sz:2;
-#else
-                uint64_t pkt_sz:2;
-                uint64_t la_en:1;
-                uint64_t lafifovfl:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_pcsx_log_anlx_reg_s cn52xx;
-        struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
-        struct cvmx_pcsx_log_anlx_reg_s cn56xx;
-        struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
-        struct cvmx_pcsx_log_anlx_reg_s cn61xx;
-        struct cvmx_pcsx_log_anlx_reg_s cn63xx;
-        struct cvmx_pcsx_log_anlx_reg_s cn63xxp1;
-        struct cvmx_pcsx_log_anlx_reg_s cn66xx;
-        struct cvmx_pcsx_log_anlx_reg_s cn68xx;
-        struct cvmx_pcsx_log_anlx_reg_s cn68xxp1;
-        struct cvmx_pcsx_log_anlx_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_miscx_ctl_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_miscx_ctl_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t sgmii:1;
-                uint64_t gmxeno:1;
-                uint64_t loopbck2:1;
-                uint64_t mac_phy:1;
-                uint64_t mode:1;
-                uint64_t an_ovrd:1;
-                uint64_t samp_pt:7;
-#else
-                uint64_t samp_pt:7;
-                uint64_t an_ovrd:1;
-                uint64_t mode:1;
-                uint64_t mac_phy:1;
-                uint64_t loopbck2:1;
-                uint64_t gmxeno:1;
-                uint64_t sgmii:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn61xx;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn63xx;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn66xx;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn68xx;
-        struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1;
-        struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_mrx_control_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_mrx_control_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t reset:1;
-                uint64_t loopbck1:1;
-                uint64_t spdlsb:1;
-                uint64_t an_en:1;
-                uint64_t pwr_dn:1;
-                uint64_t reserved_10_10:1;
-                uint64_t rst_an:1;
-                uint64_t dup:1;
-                uint64_t coltst:1;
-                uint64_t spdmsb:1;
-                uint64_t uni:1;
-                uint64_t reserved_0_4:5;
-#else
-                uint64_t reserved_0_4:5;
-                uint64_t uni:1;
-                uint64_t spdmsb:1;
-                uint64_t coltst:1;
-                uint64_t dup:1;
-                uint64_t rst_an:1;
-                uint64_t reserved_10_10:1;
-                uint64_t pwr_dn:1;
-                uint64_t an_en:1;
-                uint64_t spdlsb:1;
-                uint64_t loopbck1:1;
-                uint64_t reset:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsx_mrx_control_reg_s cn52xx;
-        struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
-        struct cvmx_pcsx_mrx_control_reg_s cn56xx;
-        struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
-        struct cvmx_pcsx_mrx_control_reg_s cn61xx;
-        struct cvmx_pcsx_mrx_control_reg_s cn63xx;
-        struct cvmx_pcsx_mrx_control_reg_s cn63xxp1;
-        struct cvmx_pcsx_mrx_control_reg_s cn66xx;
-        struct cvmx_pcsx_mrx_control_reg_s cn68xx;
-        struct cvmx_pcsx_mrx_control_reg_s cn68xxp1;
-        struct cvmx_pcsx_mrx_control_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_mrx_status_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_mrx_status_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t hun_t4:1;
-                uint64_t hun_xfd:1;
-                uint64_t hun_xhd:1;
-                uint64_t ten_fd:1;
-                uint64_t ten_hd:1;
-                uint64_t hun_t2fd:1;
-                uint64_t hun_t2hd:1;
-                uint64_t ext_st:1;
-                uint64_t reserved_7_7:1;
-                uint64_t prb_sup:1;
-                uint64_t an_cpt:1;
-                uint64_t rm_flt:1;
-                uint64_t an_abil:1;
-                uint64_t lnk_st:1;
-                uint64_t reserved_1_1:1;
-                uint64_t extnd:1;
-#else
-                uint64_t extnd:1;
-                uint64_t reserved_1_1:1;
-                uint64_t lnk_st:1;
-                uint64_t an_abil:1;
-                uint64_t rm_flt:1;
-                uint64_t an_cpt:1;
-                uint64_t prb_sup:1;
-                uint64_t reserved_7_7:1;
-                uint64_t ext_st:1;
-                uint64_t hun_t2hd:1;
-                uint64_t hun_t2fd:1;
-                uint64_t ten_hd:1;
-                uint64_t ten_fd:1;
-                uint64_t hun_xhd:1;
-                uint64_t hun_xfd:1;
-                uint64_t hun_t4:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsx_mrx_status_reg_s cn52xx;
-        struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
-        struct cvmx_pcsx_mrx_status_reg_s cn56xx;
-        struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
-        struct cvmx_pcsx_mrx_status_reg_s cn61xx;
-        struct cvmx_pcsx_mrx_status_reg_s cn63xx;
-        struct cvmx_pcsx_mrx_status_reg_s cn63xxp1;
-        struct cvmx_pcsx_mrx_status_reg_s cn66xx;
-        struct cvmx_pcsx_mrx_status_reg_s cn68xx;
-        struct cvmx_pcsx_mrx_status_reg_s cn68xxp1;
-        struct cvmx_pcsx_mrx_status_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_rxx_states_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_rxx_states_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t rx_bad:1;
-                uint64_t rx_st:5;
-                uint64_t sync_bad:1;
-                uint64_t sync:4;
-                uint64_t an_bad:1;
-                uint64_t an_st:4;
-#else
-                uint64_t an_st:4;
-                uint64_t an_bad:1;
-                uint64_t sync:4;
-                uint64_t sync_bad:1;
-                uint64_t rx_st:5;
-                uint64_t rx_bad:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsx_rxx_states_reg_s cn52xx;
-        struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
-        struct cvmx_pcsx_rxx_states_reg_s cn56xx;
-        struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
-        struct cvmx_pcsx_rxx_states_reg_s cn61xx;
-        struct cvmx_pcsx_rxx_states_reg_s cn63xx;
-        struct cvmx_pcsx_rxx_states_reg_s cn63xxp1;
-        struct cvmx_pcsx_rxx_states_reg_s cn66xx;
-        struct cvmx_pcsx_rxx_states_reg_s cn68xx;
-        struct cvmx_pcsx_rxx_states_reg_s cn68xxp1;
-        struct cvmx_pcsx_rxx_states_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_rxx_sync_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_rxx_sync_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t sync:1;
-                uint64_t bit_lock:1;
-#else
-                uint64_t bit_lock:1;
-                uint64_t sync:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
-        struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
-        struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
-        struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
-        struct cvmx_pcsx_rxx_sync_reg_s cn61xx;
-        struct cvmx_pcsx_rxx_sync_reg_s cn63xx;
-        struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1;
-        struct cvmx_pcsx_rxx_sync_reg_s cn66xx;
-        struct cvmx_pcsx_rxx_sync_reg_s cn68xx;
-        struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1;
-        struct cvmx_pcsx_rxx_sync_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_sgmx_an_adv_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t link:1;
-                uint64_t ack:1;
-                uint64_t reserved_13_13:1;
-                uint64_t dup:1;
-                uint64_t speed:2;
-                uint64_t reserved_1_9:9;
-                uint64_t one:1;
-#else
-                uint64_t one:1;
-                uint64_t reserved_1_9:9;
-                uint64_t speed:2;
-                uint64_t dup:1;
-                uint64_t reserved_13_13:1;
-                uint64_t ack:1;
-                uint64_t link:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1;
-        struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_sgmx_lp_adv_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t link:1;
-                uint64_t reserved_13_14:2;
-                uint64_t dup:1;
-                uint64_t speed:2;
-                uint64_t reserved_1_9:9;
-                uint64_t one:1;
-#else
-                uint64_t one:1;
-                uint64_t reserved_1_9:9;
-                uint64_t speed:2;
-                uint64_t dup:1;
-                uint64_t reserved_13_14:2;
-                uint64_t link:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1;
-        struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_txx_states_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_txx_states_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t xmit:2;
-                uint64_t tx_bad:1;
-                uint64_t ord_st:4;
-#else
-                uint64_t ord_st:4;
-                uint64_t tx_bad:1;
-                uint64_t xmit:2;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_pcsx_txx_states_reg_s cn52xx;
-        struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
-        struct cvmx_pcsx_txx_states_reg_s cn56xx;
-        struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
-        struct cvmx_pcsx_txx_states_reg_s cn61xx;
-        struct cvmx_pcsx_txx_states_reg_s cn63xx;
-        struct cvmx_pcsx_txx_states_reg_s cn63xxp1;
-        struct cvmx_pcsx_txx_states_reg_s cn66xx;
-        struct cvmx_pcsx_txx_states_reg_s cn68xx;
-        struct cvmx_pcsx_txx_states_reg_s cn68xxp1;
-        struct cvmx_pcsx_txx_states_reg_s cnf71xx;
-};
-
-union cvmx_pcsx_tx_rxx_polarity_reg {
-        uint64_t u64;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t rxovrd:1;
-                uint64_t autorxpl:1;
-                uint64_t rxplrt:1;
-                uint64_t txplrt:1;
-#else
-                uint64_t txplrt:1;
-                uint64_t rxplrt:1;
-                uint64_t autorxpl:1;
-                uint64_t rxovrd:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;
-        struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
deleted file mode 100644
index b5b45d26f1c..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
+++ /dev/null
@@ -1,808 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_PCSXX_DEFS_H__
-#define __CVMX_PCSXX_DEFS_H__
-
-static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
-        }
-        return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
-}
-
-union cvmx_pcsxx_10gbx_status_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_10gbx_status_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t alignd:1;
-                uint64_t pattst:1;
-                uint64_t reserved_4_10:7;
-                uint64_t l3sync:1;
-                uint64_t l2sync:1;
-                uint64_t l1sync:1;
-                uint64_t l0sync:1;
-#else
-                uint64_t l0sync:1;
-                uint64_t l1sync:1;
-                uint64_t l2sync:1;
-                uint64_t l3sync:1;
-                uint64_t reserved_4_10:7;
-                uint64_t pattst:1;
-                uint64_t alignd:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn61xx;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn63xx;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn66xx;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn68xx;
-        struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_bist_status_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_bist_status_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t bist_status:1;
-#else
-                uint64_t bist_status:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_pcsxx_bist_status_reg_s cn52xx;
-        struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
-        struct cvmx_pcsxx_bist_status_reg_s cn56xx;
-        struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
-        struct cvmx_pcsxx_bist_status_reg_s cn61xx;
-        struct cvmx_pcsxx_bist_status_reg_s cn63xx;
-        struct cvmx_pcsxx_bist_status_reg_s cn63xxp1;
-        struct cvmx_pcsxx_bist_status_reg_s cn66xx;
-        struct cvmx_pcsxx_bist_status_reg_s cn68xx;
-        struct cvmx_pcsxx_bist_status_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_bit_lock_status_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_bit_lock_status_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t bitlck3:1;
-                uint64_t bitlck2:1;
-                uint64_t bitlck1:1;
-                uint64_t bitlck0:1;
-#else
-                uint64_t bitlck0:1;
-                uint64_t bitlck1:1;
-                uint64_t bitlck2:1;
-                uint64_t bitlck3:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx;
-        struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_control1_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_control1_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t reset:1;
-                uint64_t loopbck1:1;
-                uint64_t spdsel1:1;
-                uint64_t reserved_12_12:1;
-                uint64_t lo_pwr:1;
-                uint64_t reserved_7_10:4;
-                uint64_t spdsel0:1;
-                uint64_t spd:4;
-                uint64_t reserved_0_1:2;
-#else
-                uint64_t reserved_0_1:2;
-                uint64_t spd:4;
-                uint64_t spdsel0:1;
-                uint64_t reserved_7_10:4;
-                uint64_t lo_pwr:1;
-                uint64_t reserved_12_12:1;
-                uint64_t spdsel1:1;
-                uint64_t loopbck1:1;
-                uint64_t reset:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsxx_control1_reg_s cn52xx;
-        struct cvmx_pcsxx_control1_reg_s cn52xxp1;
-        struct cvmx_pcsxx_control1_reg_s cn56xx;
-        struct cvmx_pcsxx_control1_reg_s cn56xxp1;
-        struct cvmx_pcsxx_control1_reg_s cn61xx;
-        struct cvmx_pcsxx_control1_reg_s cn63xx;
-        struct cvmx_pcsxx_control1_reg_s cn63xxp1;
-        struct cvmx_pcsxx_control1_reg_s cn66xx;
-        struct cvmx_pcsxx_control1_reg_s cn68xx;
-        struct cvmx_pcsxx_control1_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_control2_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_control2_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t type:2;
-#else
-                uint64_t type:2;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_pcsxx_control2_reg_s cn52xx;
-        struct cvmx_pcsxx_control2_reg_s cn52xxp1;
-        struct cvmx_pcsxx_control2_reg_s cn56xx;
-        struct cvmx_pcsxx_control2_reg_s cn56xxp1;
-        struct cvmx_pcsxx_control2_reg_s cn61xx;
-        struct cvmx_pcsxx_control2_reg_s cn63xx;
-        struct cvmx_pcsxx_control2_reg_s cn63xxp1;
-        struct cvmx_pcsxx_control2_reg_s cn66xx;
-        struct cvmx_pcsxx_control2_reg_s cn68xx;
-        struct cvmx_pcsxx_control2_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_int_en_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_int_en_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t dbg_sync_en:1;
-                uint64_t algnlos_en:1;
-                uint64_t synlos_en:1;
-                uint64_t bitlckls_en:1;
-                uint64_t rxsynbad_en:1;
-                uint64_t rxbad_en:1;
-                uint64_t txflt_en:1;
-#else
-                uint64_t txflt_en:1;
-                uint64_t rxbad_en:1;
-                uint64_t rxsynbad_en:1;
-                uint64_t bitlckls_en:1;
-                uint64_t synlos_en:1;
-                uint64_t algnlos_en:1;
-                uint64_t dbg_sync_en:1;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_pcsxx_int_en_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t algnlos_en:1;
-                uint64_t synlos_en:1;
-                uint64_t bitlckls_en:1;
-                uint64_t rxsynbad_en:1;
-                uint64_t rxbad_en:1;
-                uint64_t txflt_en:1;
-#else
-                uint64_t txflt_en:1;
-                uint64_t rxbad_en:1;
-                uint64_t rxsynbad_en:1;
-                uint64_t bitlckls_en:1;
-                uint64_t synlos_en:1;
-                uint64_t algnlos_en:1;
-                uint64_t reserved_6_63:58;
-#endif
-        } cn52xx;
-        struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1;
-        struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx;
-        struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1;
-        struct cvmx_pcsxx_int_en_reg_s cn61xx;
-        struct cvmx_pcsxx_int_en_reg_s cn63xx;
-        struct cvmx_pcsxx_int_en_reg_s cn63xxp1;
-        struct cvmx_pcsxx_int_en_reg_s cn66xx;
-        struct cvmx_pcsxx_int_en_reg_s cn68xx;
-        struct cvmx_pcsxx_int_en_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_int_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t dbg_sync:1;
-                uint64_t algnlos:1;
-                uint64_t synlos:1;
-                uint64_t bitlckls:1;
-                uint64_t rxsynbad:1;
-                uint64_t rxbad:1;
-                uint64_t txflt:1;
-#else
-                uint64_t txflt:1;
-                uint64_t rxbad:1;
-                uint64_t rxsynbad:1;
-                uint64_t bitlckls:1;
-                uint64_t synlos:1;
-                uint64_t algnlos:1;
-                uint64_t dbg_sync:1;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_pcsxx_int_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t algnlos:1;
-                uint64_t synlos:1;
-                uint64_t bitlckls:1;
-                uint64_t rxsynbad:1;
-                uint64_t rxbad:1;
-                uint64_t txflt:1;
-#else
-                uint64_t txflt:1;
-                uint64_t rxbad:1;
-                uint64_t rxsynbad:1;
-                uint64_t bitlckls:1;
-                uint64_t synlos:1;
-                uint64_t algnlos:1;
-                uint64_t reserved_6_63:58;
-#endif
-        } cn52xx;
-        struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1;
-        struct cvmx_pcsxx_int_reg_cn52xx cn56xx;
-        struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1;
-        struct cvmx_pcsxx_int_reg_s cn61xx;
-        struct cvmx_pcsxx_int_reg_s cn63xx;
-        struct cvmx_pcsxx_int_reg_s cn63xxp1;
-        struct cvmx_pcsxx_int_reg_s cn66xx;
-        struct cvmx_pcsxx_int_reg_s cn68xx;
-        struct cvmx_pcsxx_int_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_log_anl_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_log_anl_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t enc_mode:1;
-                uint64_t drop_ln:2;
-                uint64_t lafifovfl:1;
-                uint64_t la_en:1;
-                uint64_t pkt_sz:2;
-#else
-                uint64_t pkt_sz:2;
-                uint64_t la_en:1;
-                uint64_t lafifovfl:1;
-                uint64_t drop_ln:2;
-                uint64_t enc_mode:1;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_pcsxx_log_anl_reg_s cn52xx;
-        struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
-        struct cvmx_pcsxx_log_anl_reg_s cn56xx;
-        struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
-        struct cvmx_pcsxx_log_anl_reg_s cn61xx;
-        struct cvmx_pcsxx_log_anl_reg_s cn63xx;
-        struct cvmx_pcsxx_log_anl_reg_s cn63xxp1;
-        struct cvmx_pcsxx_log_anl_reg_s cn66xx;
-        struct cvmx_pcsxx_log_anl_reg_s cn68xx;
-        struct cvmx_pcsxx_log_anl_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_misc_ctl_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_misc_ctl_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t tx_swap:1;
-                uint64_t rx_swap:1;
-                uint64_t xaui:1;
-                uint64_t gmxeno:1;
-#else
-                uint64_t gmxeno:1;
-                uint64_t xaui:1;
-                uint64_t rx_swap:1;
-                uint64_t tx_swap:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn61xx;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn63xx;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn66xx;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn68xx;
-        struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_rx_sync_states_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_rx_sync_states_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t sync3st:4;
-                uint64_t sync2st:4;
-                uint64_t sync1st:4;
-                uint64_t sync0st:4;
-#else
-                uint64_t sync0st:4;
-                uint64_t sync1st:4;
-                uint64_t sync2st:4;
-                uint64_t sync3st:4;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx;
-        struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_spd_abil_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_spd_abil_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t tenpasst:1;
-                uint64_t tengb:1;
-#else
-                uint64_t tengb:1;
-                uint64_t tenpasst:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
-        struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
-        struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
-        struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
-        struct cvmx_pcsxx_spd_abil_reg_s cn61xx;
-        struct cvmx_pcsxx_spd_abil_reg_s cn63xx;
-        struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1;
-        struct cvmx_pcsxx_spd_abil_reg_s cn66xx;
-        struct cvmx_pcsxx_spd_abil_reg_s cn68xx;
-        struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_status1_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_status1_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t flt:1;
-                uint64_t reserved_3_6:4;
-                uint64_t rcv_lnk:1;
-                uint64_t lpable:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t lpable:1;
-                uint64_t rcv_lnk:1;
-                uint64_t reserved_3_6:4;
-                uint64_t flt:1;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_pcsxx_status1_reg_s cn52xx;
-        struct cvmx_pcsxx_status1_reg_s cn52xxp1;
-        struct cvmx_pcsxx_status1_reg_s cn56xx;
-        struct cvmx_pcsxx_status1_reg_s cn56xxp1;
-        struct cvmx_pcsxx_status1_reg_s cn61xx;
-        struct cvmx_pcsxx_status1_reg_s cn63xx;
-        struct cvmx_pcsxx_status1_reg_s cn63xxp1;
-        struct cvmx_pcsxx_status1_reg_s cn66xx;
-        struct cvmx_pcsxx_status1_reg_s cn68xx;
-        struct cvmx_pcsxx_status1_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_status2_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_status2_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t dev:2;
-                uint64_t reserved_12_13:2;
-                uint64_t xmtflt:1;
-                uint64_t rcvflt:1;
-                uint64_t reserved_3_9:7;
-                uint64_t tengb_w:1;
-                uint64_t tengb_x:1;
-                uint64_t tengb_r:1;
-#else
-                uint64_t tengb_r:1;
-                uint64_t tengb_x:1;
-                uint64_t tengb_w:1;
-                uint64_t reserved_3_9:7;
-                uint64_t rcvflt:1;
-                uint64_t xmtflt:1;
-                uint64_t reserved_12_13:2;
-                uint64_t dev:2;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pcsxx_status2_reg_s cn52xx;
-        struct cvmx_pcsxx_status2_reg_s cn52xxp1;
-        struct cvmx_pcsxx_status2_reg_s cn56xx;
-        struct cvmx_pcsxx_status2_reg_s cn56xxp1;
-        struct cvmx_pcsxx_status2_reg_s cn61xx;
-        struct cvmx_pcsxx_status2_reg_s cn63xx;
-        struct cvmx_pcsxx_status2_reg_s cn63xxp1;
-        struct cvmx_pcsxx_status2_reg_s cn66xx;
-        struct cvmx_pcsxx_status2_reg_s cn68xx;
-        struct cvmx_pcsxx_status2_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_tx_rx_polarity_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t xor_rxplrt:4;
-                uint64_t xor_txplrt:4;
-                uint64_t rxplrt:1;
-                uint64_t txplrt:1;
-#else
-                uint64_t txplrt:1;
-                uint64_t rxplrt:1;
-                uint64_t xor_txplrt:4;
-                uint64_t xor_rxplrt:4;
-                uint64_t reserved_10_63:54;
-#endif
-        } s;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t rxplrt:1;
-                uint64_t txplrt:1;
-#else
-                uint64_t txplrt:1;
-                uint64_t rxplrt:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } cn52xxp1;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx;
-        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1;
-};
-
-union cvmx_pcsxx_tx_rx_states_reg {
-        uint64_t u64;
-        struct cvmx_pcsxx_tx_rx_states_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t term_err:1;
-                uint64_t syn3bad:1;
-                uint64_t syn2bad:1;
-                uint64_t syn1bad:1;
-                uint64_t syn0bad:1;
-                uint64_t rxbad:1;
-                uint64_t algn_st:3;
-                uint64_t rx_st:2;
-                uint64_t tx_st:3;
-#else
-                uint64_t tx_st:3;
-                uint64_t rx_st:2;
-                uint64_t algn_st:3;
-                uint64_t rxbad:1;
-                uint64_t syn0bad:1;
-                uint64_t syn1bad:1;
-                uint64_t syn2bad:1;
-                uint64_t syn3bad:1;
-                uint64_t term_err:1;
-                uint64_t reserved_14_63:50;
-#endif
-        } s;
-        struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
-        struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t syn3bad:1;
-                uint64_t syn2bad:1;
-                uint64_t syn1bad:1;
-                uint64_t syn0bad:1;
-                uint64_t rxbad:1;
-                uint64_t algn_st:3;
-                uint64_t rx_st:2;
-                uint64_t tx_st:3;
-#else
-                uint64_t tx_st:3;
-                uint64_t rx_st:2;
-                uint64_t algn_st:3;
-                uint64_t rxbad:1;
-                uint64_t syn0bad:1;
-                uint64_t syn1bad:1;
-                uint64_t syn2bad:1;
-                uint64_t syn3bad:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } cn52xxp1;
-        struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
-        struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
-        struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx;
-        struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx;
-        struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1;
-        struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx;
-        struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx;
-        struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
deleted file mode 100644
index 50a916f892f..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
+++ /dev/null
@@ -1,795 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_PEMX_DEFS_H__
-#define __CVMX_PEMX_DEFS_H__
-
-#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
-#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
-#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
-#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
-#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
-
-union cvmx_pemx_bar1_indexx {
-        uint64_t u64;
-        struct cvmx_pemx_bar1_indexx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t addr_idx:16;
-                uint64_t ca:1;
-                uint64_t end_swp:2;
-                uint64_t addr_v:1;
-#else
-                uint64_t addr_v:1;
-                uint64_t end_swp:2;
-                uint64_t ca:1;
-                uint64_t addr_idx:16;
-                uint64_t reserved_20_63:44;
-#endif
-        } s;
-        struct cvmx_pemx_bar1_indexx_s cn61xx;
-        struct cvmx_pemx_bar1_indexx_s cn63xx;
-        struct cvmx_pemx_bar1_indexx_s cn63xxp1;
-        struct cvmx_pemx_bar1_indexx_s cn66xx;
-        struct cvmx_pemx_bar1_indexx_s cn68xx;
-        struct cvmx_pemx_bar1_indexx_s cn68xxp1;
-        struct cvmx_pemx_bar1_indexx_s cnf71xx;
-};
-
-union cvmx_pemx_bar2_mask {
-        uint64_t u64;
-        struct cvmx_pemx_bar2_mask_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_38_63:26;
-                uint64_t mask:35;
-                uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t mask:35;
-                uint64_t reserved_38_63:26;
-#endif
-        } s;
-        struct cvmx_pemx_bar2_mask_s cn61xx;
-        struct cvmx_pemx_bar2_mask_s cn66xx;
-        struct cvmx_pemx_bar2_mask_s cn68xx;
-        struct cvmx_pemx_bar2_mask_s cn68xxp1;
-        struct cvmx_pemx_bar2_mask_s cnf71xx;
-};
-
-union cvmx_pemx_bar_ctl {
-        uint64_t u64;
-        struct cvmx_pemx_bar_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t bar1_siz:3;
-                uint64_t bar2_enb:1;
-                uint64_t bar2_esx:2;
-                uint64_t bar2_cax:1;
-#else
-                uint64_t bar2_cax:1;
-                uint64_t bar2_esx:2;
-                uint64_t bar2_enb:1;
-                uint64_t bar1_siz:3;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_pemx_bar_ctl_s cn61xx;
-        struct cvmx_pemx_bar_ctl_s cn63xx;
-        struct cvmx_pemx_bar_ctl_s cn63xxp1;
-        struct cvmx_pemx_bar_ctl_s cn66xx;
-        struct cvmx_pemx_bar_ctl_s cn68xx;
-        struct cvmx_pemx_bar_ctl_s cn68xxp1;
-        struct cvmx_pemx_bar_ctl_s cnf71xx;
-};
-
-union cvmx_pemx_bist_status {
-        uint64_t u64;
-        struct cvmx_pemx_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t retry:1;
-                uint64_t rqdata0:1;
-                uint64_t rqdata1:1;
-                uint64_t rqdata2:1;
-                uint64_t rqdata3:1;
-                uint64_t rqhdr1:1;
-                uint64_t rqhdr0:1;
-                uint64_t sot:1;
-#else
-                uint64_t sot:1;
-                uint64_t rqhdr0:1;
-                uint64_t rqhdr1:1;
-                uint64_t rqdata3:1;
-                uint64_t rqdata2:1;
-                uint64_t rqdata1:1;
-                uint64_t rqdata0:1;
-                uint64_t retry:1;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_pemx_bist_status_s cn61xx;
-        struct cvmx_pemx_bist_status_s cn63xx;
-        struct cvmx_pemx_bist_status_s cn63xxp1;
-        struct cvmx_pemx_bist_status_s cn66xx;
-        struct cvmx_pemx_bist_status_s cn68xx;
-        struct cvmx_pemx_bist_status_s cn68xxp1;
-        struct cvmx_pemx_bist_status_s cnf71xx;
-};
-
-union cvmx_pemx_bist_status2 {
-        uint64_t u64;
-        struct cvmx_pemx_bist_status2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t e2p_cpl:1;
-                uint64_t e2p_n:1;
-                uint64_t e2p_p:1;
-                uint64_t peai_p2e:1;
-                uint64_t pef_tpf1:1;
-                uint64_t pef_tpf0:1;
-                uint64_t pef_tnf:1;
-                uint64_t pef_tcf1:1;
-                uint64_t pef_tc0:1;
-                uint64_t ppf:1;
-#else
-                uint64_t ppf:1;
-                uint64_t pef_tc0:1;
-                uint64_t pef_tcf1:1;
-                uint64_t pef_tnf:1;
-                uint64_t pef_tpf0:1;
-                uint64_t pef_tpf1:1;
-                uint64_t peai_p2e:1;
-                uint64_t e2p_p:1;
-                uint64_t e2p_n:1;
-                uint64_t e2p_cpl:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } s;
-        struct cvmx_pemx_bist_status2_s cn61xx;
-        struct cvmx_pemx_bist_status2_s cn63xx;
-        struct cvmx_pemx_bist_status2_s cn63xxp1;
-        struct cvmx_pemx_bist_status2_s cn66xx;
-        struct cvmx_pemx_bist_status2_s cn68xx;
-        struct cvmx_pemx_bist_status2_s cn68xxp1;
-        struct cvmx_pemx_bist_status2_s cnf71xx;
-};
-
-union cvmx_pemx_cfg_rd {
-        uint64_t u64;
-        struct cvmx_pemx_cfg_rd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:32;
-                uint64_t addr:32;
-#else
-                uint64_t addr:32;
-                uint64_t data:32;
-#endif
-        } s;
-        struct cvmx_pemx_cfg_rd_s cn61xx;
-        struct cvmx_pemx_cfg_rd_s cn63xx;
-        struct cvmx_pemx_cfg_rd_s cn63xxp1;
-        struct cvmx_pemx_cfg_rd_s cn66xx;
-        struct cvmx_pemx_cfg_rd_s cn68xx;
-        struct cvmx_pemx_cfg_rd_s cn68xxp1;
-        struct cvmx_pemx_cfg_rd_s cnf71xx;
-};
-
-union cvmx_pemx_cfg_wr {
-        uint64_t u64;
-        struct cvmx_pemx_cfg_wr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:32;
-                uint64_t addr:32;
-#else
-                uint64_t addr:32;
-                uint64_t data:32;
-#endif
-        } s;
-        struct cvmx_pemx_cfg_wr_s cn61xx;
-        struct cvmx_pemx_cfg_wr_s cn63xx;
-        struct cvmx_pemx_cfg_wr_s cn63xxp1;
-        struct cvmx_pemx_cfg_wr_s cn66xx;
-        struct cvmx_pemx_cfg_wr_s cn68xx;
-        struct cvmx_pemx_cfg_wr_s cn68xxp1;
-        struct cvmx_pemx_cfg_wr_s cnf71xx;
-};
-
-union cvmx_pemx_cpl_lut_valid {
-        uint64_t u64;
-        struct cvmx_pemx_cpl_lut_valid_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t tag:32;
-#else
-                uint64_t tag:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pemx_cpl_lut_valid_s cn61xx;
-        struct cvmx_pemx_cpl_lut_valid_s cn63xx;
-        struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
-        struct cvmx_pemx_cpl_lut_valid_s cn66xx;
-        struct cvmx_pemx_cpl_lut_valid_s cn68xx;
-        struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
-        struct cvmx_pemx_cpl_lut_valid_s cnf71xx;
-};
-
-union cvmx_pemx_ctl_status {
-        uint64_t u64;
-        struct cvmx_pemx_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t auto_sd:1;
-                uint64_t dnum:5;
-                uint64_t pbus:8;
-                uint64_t reserved_32_33:2;
-                uint64_t cfg_rtry:16;
-                uint64_t reserved_12_15:4;
-                uint64_t pm_xtoff:1;
-                uint64_t pm_xpme:1;
-                uint64_t ob_p_cmd:1;
-                uint64_t reserved_7_8:2;
-                uint64_t nf_ecrc:1;
-                uint64_t dly_one:1;
-                uint64_t lnk_enb:1;
-                uint64_t ro_ctlp:1;
-                uint64_t fast_lm:1;
-                uint64_t inv_ecrc:1;
-                uint64_t inv_lcrc:1;
-#else
-                uint64_t inv_lcrc:1;
-                uint64_t inv_ecrc:1;
-                uint64_t fast_lm:1;
-                uint64_t ro_ctlp:1;
-                uint64_t lnk_enb:1;
-                uint64_t dly_one:1;
-                uint64_t nf_ecrc:1;
-                uint64_t reserved_7_8:2;
-                uint64_t ob_p_cmd:1;
-                uint64_t pm_xpme:1;
-                uint64_t pm_xtoff:1;
-                uint64_t reserved_12_15:4;
-                uint64_t cfg_rtry:16;
-                uint64_t reserved_32_33:2;
-                uint64_t pbus:8;
-                uint64_t dnum:5;
-                uint64_t auto_sd:1;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_pemx_ctl_status_s cn61xx;
-        struct cvmx_pemx_ctl_status_s cn63xx;
-        struct cvmx_pemx_ctl_status_s cn63xxp1;
-        struct cvmx_pemx_ctl_status_s cn66xx;
-        struct cvmx_pemx_ctl_status_s cn68xx;
-        struct cvmx_pemx_ctl_status_s cn68xxp1;
-        struct cvmx_pemx_ctl_status_s cnf71xx;
-};
-
-union cvmx_pemx_dbg_info {
-        uint64_t u64;
-        struct cvmx_pemx_dbg_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_31_63:33;
-                uint64_t ecrc_e:1;
-                uint64_t rawwpp:1;
-                uint64_t racpp:1;
-                uint64_t ramtlp:1;
-                uint64_t rarwdns:1;
-                uint64_t caar:1;
-                uint64_t racca:1;
-                uint64_t racur:1;
-                uint64_t rauc:1;
-                uint64_t rqo:1;
-                uint64_t fcuv:1;
-                uint64_t rpe:1;
-                uint64_t fcpvwt:1;
-                uint64_t dpeoosd:1;
-                uint64_t rtwdle:1;
-                uint64_t rdwdle:1;
-                uint64_t mre:1;
-                uint64_t rte:1;
-                uint64_t acto:1;
-                uint64_t rvdm:1;
-                uint64_t rumep:1;
-                uint64_t rptamrc:1;
-                uint64_t rpmerc:1;
-                uint64_t rfemrc:1;
-                uint64_t rnfemrc:1;
-                uint64_t rcemrc:1;
-                uint64_t rpoison:1;
-                uint64_t recrce:1;
-                uint64_t rtlplle:1;
-                uint64_t rtlpmal:1;
-                uint64_t spoison:1;
-#else
-                uint64_t spoison:1;
-                uint64_t rtlpmal:1;
-                uint64_t rtlplle:1;
-                uint64_t recrce:1;
-                uint64_t rpoison:1;
-                uint64_t rcemrc:1;
-                uint64_t rnfemrc:1;
-                uint64_t rfemrc:1;
-                uint64_t rpmerc:1;
-                uint64_t rptamrc:1;
-                uint64_t rumep:1;
-                uint64_t rvdm:1;
-                uint64_t acto:1;
-                uint64_t rte:1;
-                uint64_t mre:1;
-                uint64_t rdwdle:1;
-                uint64_t rtwdle:1;
-                uint64_t dpeoosd:1;
-                uint64_t fcpvwt:1;
-                uint64_t rpe:1;
-                uint64_t fcuv:1;
-                uint64_t rqo:1;
-                uint64_t rauc:1;
-                uint64_t racur:1;
-                uint64_t racca:1;
-                uint64_t caar:1;
-                uint64_t rarwdns:1;
-                uint64_t ramtlp:1;
-                uint64_t racpp:1;
-                uint64_t rawwpp:1;
-                uint64_t ecrc_e:1;
-                uint64_t reserved_31_63:33;
-#endif
-        } s;
-        struct cvmx_pemx_dbg_info_s cn61xx;
-        struct cvmx_pemx_dbg_info_s cn63xx;
-        struct cvmx_pemx_dbg_info_s cn63xxp1;
-        struct cvmx_pemx_dbg_info_s cn66xx;
-        struct cvmx_pemx_dbg_info_s cn68xx;
-        struct cvmx_pemx_dbg_info_s cn68xxp1;
-        struct cvmx_pemx_dbg_info_s cnf71xx;
-};
-
-union cvmx_pemx_dbg_info_en {
-        uint64_t u64;
-        struct cvmx_pemx_dbg_info_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_31_63:33;
-                uint64_t ecrc_e:1;
-                uint64_t rawwpp:1;
-                uint64_t racpp:1;
-                uint64_t ramtlp:1;
-                uint64_t rarwdns:1;
-                uint64_t caar:1;
-                uint64_t racca:1;
-                uint64_t racur:1;
-                uint64_t rauc:1;
-                uint64_t rqo:1;
-                uint64_t fcuv:1;
-                uint64_t rpe:1;
-                uint64_t fcpvwt:1;
-                uint64_t dpeoosd:1;
-                uint64_t rtwdle:1;
-                uint64_t rdwdle:1;
-                uint64_t mre:1;
-                uint64_t rte:1;
-                uint64_t acto:1;
-                uint64_t rvdm:1;
-                uint64_t rumep:1;
-                uint64_t rptamrc:1;
-                uint64_t rpmerc:1;
-                uint64_t rfemrc:1;
-                uint64_t rnfemrc:1;
-                uint64_t rcemrc:1;
-                uint64_t rpoison:1;
-                uint64_t recrce:1;
-                uint64_t rtlplle:1;
-                uint64_t rtlpmal:1;
-                uint64_t spoison:1;
-#else
-                uint64_t spoison:1;
-                uint64_t rtlpmal:1;
-                uint64_t rtlplle:1;
-                uint64_t recrce:1;
-                uint64_t rpoison:1;
-                uint64_t rcemrc:1;
-                uint64_t rnfemrc:1;
-                uint64_t rfemrc:1;
-                uint64_t rpmerc:1;
-                uint64_t rptamrc:1;
-                uint64_t rumep:1;
-                uint64_t rvdm:1;
-                uint64_t acto:1;
-                uint64_t rte:1;
-                uint64_t mre:1;
-                uint64_t rdwdle:1;
-                uint64_t rtwdle:1;
-                uint64_t dpeoosd:1;
-                uint64_t fcpvwt:1;
-                uint64_t rpe:1;
-                uint64_t fcuv:1;
-                uint64_t rqo:1;
-                uint64_t rauc:1;
-                uint64_t racur:1;
-                uint64_t racca:1;
-                uint64_t caar:1;
-                uint64_t rarwdns:1;
-                uint64_t ramtlp:1;
-                uint64_t racpp:1;
-                uint64_t rawwpp:1;
-                uint64_t ecrc_e:1;
-                uint64_t reserved_31_63:33;
-#endif
-        } s;
-        struct cvmx_pemx_dbg_info_en_s cn61xx;
-        struct cvmx_pemx_dbg_info_en_s cn63xx;
-        struct cvmx_pemx_dbg_info_en_s cn63xxp1;
-        struct cvmx_pemx_dbg_info_en_s cn66xx;
-        struct cvmx_pemx_dbg_info_en_s cn68xx;
-        struct cvmx_pemx_dbg_info_en_s cn68xxp1;
-        struct cvmx_pemx_dbg_info_en_s cnf71xx;
-};
-
-union cvmx_pemx_diag_status {
-        uint64_t u64;
-        struct cvmx_pemx_diag_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t pm_dst:1;
-                uint64_t pm_stat:1;
-                uint64_t pm_en:1;
-                uint64_t aux_en:1;
-#else
-                uint64_t aux_en:1;
-                uint64_t pm_en:1;
-                uint64_t pm_stat:1;
-                uint64_t pm_dst:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_pemx_diag_status_s cn61xx;
-        struct cvmx_pemx_diag_status_s cn63xx;
-        struct cvmx_pemx_diag_status_s cn63xxp1;
-        struct cvmx_pemx_diag_status_s cn66xx;
-        struct cvmx_pemx_diag_status_s cn68xx;
-        struct cvmx_pemx_diag_status_s cn68xxp1;
-        struct cvmx_pemx_diag_status_s cnf71xx;
-};
-
-union cvmx_pemx_inb_read_credits {
-        uint64_t u64;
-        struct cvmx_pemx_inb_read_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t num:6;
-#else
-                uint64_t num:6;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_pemx_inb_read_credits_s cn61xx;
-        struct cvmx_pemx_inb_read_credits_s cn66xx;
-        struct cvmx_pemx_inb_read_credits_s cn68xx;
-        struct cvmx_pemx_inb_read_credits_s cnf71xx;
-};
-
-union cvmx_pemx_int_enb {
-        uint64_t u64;
-        struct cvmx_pemx_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t crs_dr:1;
-                uint64_t crs_er:1;
-                uint64_t rdlk:1;
-                uint64_t exc:1;
-                uint64_t un_bx:1;
-                uint64_t un_b2:1;
-                uint64_t un_b1:1;
-                uint64_t up_bx:1;
-                uint64_t up_b2:1;
-                uint64_t up_b1:1;
-                uint64_t pmem:1;
-                uint64_t pmei:1;
-                uint64_t se:1;
-                uint64_t aeri:1;
-#else
-                uint64_t aeri:1;
-                uint64_t se:1;
-                uint64_t pmei:1;
-                uint64_t pmem:1;
-                uint64_t up_b1:1;
-                uint64_t up_b2:1;
-                uint64_t up_bx:1;
-                uint64_t un_b1:1;
-                uint64_t un_b2:1;
-                uint64_t un_bx:1;
-                uint64_t exc:1;
-                uint64_t rdlk:1;
-                uint64_t crs_er:1;
-                uint64_t crs_dr:1;
-                uint64_t reserved_14_63:50;
-#endif
-        } s;
-        struct cvmx_pemx_int_enb_s cn61xx;
-        struct cvmx_pemx_int_enb_s cn63xx;
-        struct cvmx_pemx_int_enb_s cn63xxp1;
-        struct cvmx_pemx_int_enb_s cn66xx;
-        struct cvmx_pemx_int_enb_s cn68xx;
-        struct cvmx_pemx_int_enb_s cn68xxp1;
-        struct cvmx_pemx_int_enb_s cnf71xx;
-};
-
-union cvmx_pemx_int_enb_int {
-        uint64_t u64;
-        struct cvmx_pemx_int_enb_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t crs_dr:1;
-                uint64_t crs_er:1;
-                uint64_t rdlk:1;
-                uint64_t exc:1;
-                uint64_t un_bx:1;
-                uint64_t un_b2:1;
-                uint64_t un_b1:1;
-                uint64_t up_bx:1;
-                uint64_t up_b2:1;
-                uint64_t up_b1:1;
-                uint64_t pmem:1;
-                uint64_t pmei:1;
-                uint64_t se:1;
-                uint64_t aeri:1;
-#else
-                uint64_t aeri:1;
-                uint64_t se:1;
-                uint64_t pmei:1;
-                uint64_t pmem:1;
-                uint64_t up_b1:1;
-                uint64_t up_b2:1;
-                uint64_t up_bx:1;
-                uint64_t un_b1:1;
-                uint64_t un_b2:1;
-                uint64_t un_bx:1;
-                uint64_t exc:1;
-                uint64_t rdlk:1;
-                uint64_t crs_er:1;
-                uint64_t crs_dr:1;
-                uint64_t reserved_14_63:50;
-#endif
-        } s;
-        struct cvmx_pemx_int_enb_int_s cn61xx;
-        struct cvmx_pemx_int_enb_int_s cn63xx;
-        struct cvmx_pemx_int_enb_int_s cn63xxp1;
-        struct cvmx_pemx_int_enb_int_s cn66xx;
-        struct cvmx_pemx_int_enb_int_s cn68xx;
-        struct cvmx_pemx_int_enb_int_s cn68xxp1;
-        struct cvmx_pemx_int_enb_int_s cnf71xx;
-};
-
-union cvmx_pemx_int_sum {
-        uint64_t u64;
-        struct cvmx_pemx_int_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t crs_dr:1;
-                uint64_t crs_er:1;
-                uint64_t rdlk:1;
-                uint64_t exc:1;
-                uint64_t un_bx:1;
-                uint64_t un_b2:1;
-                uint64_t un_b1:1;
-                uint64_t up_bx:1;
-                uint64_t up_b2:1;
-                uint64_t up_b1:1;
-                uint64_t pmem:1;
-                uint64_t pmei:1;
-                uint64_t se:1;
-                uint64_t aeri:1;
-#else
-                uint64_t aeri:1;
-                uint64_t se:1;
-                uint64_t pmei:1;
-                uint64_t pmem:1;
-                uint64_t up_b1:1;
-                uint64_t up_b2:1;
-                uint64_t up_bx:1;
-                uint64_t un_b1:1;
-                uint64_t un_b2:1;
-                uint64_t un_bx:1;
-                uint64_t exc:1;
-                uint64_t rdlk:1;
-                uint64_t crs_er:1;
-                uint64_t crs_dr:1;
-                uint64_t reserved_14_63:50;
-#endif
-        } s;
-        struct cvmx_pemx_int_sum_s cn61xx;
-        struct cvmx_pemx_int_sum_s cn63xx;
-        struct cvmx_pemx_int_sum_s cn63xxp1;
-        struct cvmx_pemx_int_sum_s cn66xx;
-        struct cvmx_pemx_int_sum_s cn68xx;
-        struct cvmx_pemx_int_sum_s cn68xxp1;
-        struct cvmx_pemx_int_sum_s cnf71xx;
-};
-
-union cvmx_pemx_p2n_bar0_start {
-        uint64_t u64;
-        struct cvmx_pemx_p2n_bar0_start_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t addr:50;
-                uint64_t reserved_0_13:14;
-#else
-                uint64_t reserved_0_13:14;
-                uint64_t addr:50;
-#endif
-        } s;
-        struct cvmx_pemx_p2n_bar0_start_s cn61xx;
-        struct cvmx_pemx_p2n_bar0_start_s cn63xx;
-        struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
-        struct cvmx_pemx_p2n_bar0_start_s cn66xx;
-        struct cvmx_pemx_p2n_bar0_start_s cn68xx;
-        struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
-        struct cvmx_pemx_p2n_bar0_start_s cnf71xx;
-};
-
-union cvmx_pemx_p2n_bar1_start {
-        uint64_t u64;
-        struct cvmx_pemx_p2n_bar1_start_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t addr:38;
-                uint64_t reserved_0_25:26;
-#else
-                uint64_t reserved_0_25:26;
-                uint64_t addr:38;
-#endif
-        } s;
-        struct cvmx_pemx_p2n_bar1_start_s cn61xx;
-        struct cvmx_pemx_p2n_bar1_start_s cn63xx;
-        struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
-        struct cvmx_pemx_p2n_bar1_start_s cn66xx;
-        struct cvmx_pemx_p2n_bar1_start_s cn68xx;
-        struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
-        struct cvmx_pemx_p2n_bar1_start_s cnf71xx;
-};
-
-union cvmx_pemx_p2n_bar2_start {
-        uint64_t u64;
-        struct cvmx_pemx_p2n_bar2_start_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t addr:23;
-                uint64_t reserved_0_40:41;
-#else
-                uint64_t reserved_0_40:41;
-                uint64_t addr:23;
-#endif
-        } s;
-        struct cvmx_pemx_p2n_bar2_start_s cn61xx;
-        struct cvmx_pemx_p2n_bar2_start_s cn63xx;
-        struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
-        struct cvmx_pemx_p2n_bar2_start_s cn66xx;
-        struct cvmx_pemx_p2n_bar2_start_s cn68xx;
-        struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
-        struct cvmx_pemx_p2n_bar2_start_s cnf71xx;
-};
-
-union cvmx_pemx_p2p_barx_end {
-        uint64_t u64;
-        struct cvmx_pemx_p2p_barx_end_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t addr:52;
-                uint64_t reserved_0_11:12;
-#else
-                uint64_t reserved_0_11:12;
-                uint64_t addr:52;
-#endif
-        } s;
-        struct cvmx_pemx_p2p_barx_end_s cn63xx;
-        struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
-        struct cvmx_pemx_p2p_barx_end_s cn66xx;
-        struct cvmx_pemx_p2p_barx_end_s cn68xx;
-        struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
-};
-
-union cvmx_pemx_p2p_barx_start {
-        uint64_t u64;
-        struct cvmx_pemx_p2p_barx_start_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t addr:52;
-                uint64_t reserved_0_11:12;
-#else
-                uint64_t reserved_0_11:12;
-                uint64_t addr:52;
-#endif
-        } s;
-        struct cvmx_pemx_p2p_barx_start_s cn63xx;
-        struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
-        struct cvmx_pemx_p2p_barx_start_s cn66xx;
-        struct cvmx_pemx_p2p_barx_start_s cn68xx;
-        struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
-};
-
-union cvmx_pemx_tlp_credits {
-        uint64_t u64;
-        struct cvmx_pemx_tlp_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t peai_ppf:8;
-                uint64_t pem_cpl:8;
-                uint64_t pem_np:8;
-                uint64_t pem_p:8;
-                uint64_t sli_cpl:8;
-                uint64_t sli_np:8;
-                uint64_t sli_p:8;
-#else
-                uint64_t sli_p:8;
-                uint64_t sli_np:8;
-                uint64_t sli_cpl:8;
-                uint64_t pem_p:8;
-                uint64_t pem_np:8;
-                uint64_t pem_cpl:8;
-                uint64_t peai_ppf:8;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_pemx_tlp_credits_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t peai_ppf:8;
-                uint64_t reserved_24_47:24;
-                uint64_t sli_cpl:8;
-                uint64_t sli_np:8;
-                uint64_t sli_p:8;
-#else
-                uint64_t sli_p:8;
-                uint64_t sli_np:8;
-                uint64_t sli_cpl:8;
-                uint64_t reserved_24_47:24;
-                uint64_t peai_ppf:8;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn61xx;
-        struct cvmx_pemx_tlp_credits_s cn63xx;
-        struct cvmx_pemx_tlp_credits_s cn63xxp1;
-        struct cvmx_pemx_tlp_credits_s cn66xx;
-        struct cvmx_pemx_tlp_credits_s cn68xx;
-        struct cvmx_pemx_tlp_credits_s cn68xxp1;
-        struct cvmx_pemx_tlp_credits_cn61xx cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
index 59b3dc56544..aef84851a94 100644
--- a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -48,7 +48,6 @@
 union cvmx_pescx_bist_status {
         uint64_t u64;
         struct cvmx_pescx_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_13_63:51;
                 uint64_t rqdata5:1;
                 uint64_t ctlp_or:1;
@@ -63,26 +62,9 @@ union cvmx_pescx_bist_status {
                 uint64_t rqhdr1:1;
                 uint64_t rqhdr0:1;
                 uint64_t sot:1;
-#else
-                uint64_t sot:1;
-                uint64_t rqhdr0:1;
-                uint64_t rqhdr1:1;
-                uint64_t rqdata4:1;
-                uint64_t rqdata3:1;
-                uint64_t rqdata2:1;
-                uint64_t rqdata1:1;
-                uint64_t rqdata0:1;
-                uint64_t retry:1;
-                uint64_t ptlp_or:1;
-                uint64_t ntlp_or:1;
-                uint64_t ctlp_or:1;
-                uint64_t rqdata5:1;
-                uint64_t reserved_13_63:51;
-#endif
         } s;
         struct cvmx_pescx_bist_status_s cn52xx;
         struct cvmx_pescx_bist_status_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t ctlp_or:1;
                 uint64_t ntlp_or:1;
@@ -96,21 +78,6 @@ union cvmx_pescx_bist_status {
                 uint64_t rqhdr1:1;
                 uint64_t rqhdr0:1;
                 uint64_t sot:1;
-#else
-                uint64_t sot:1;
-                uint64_t rqhdr0:1;
-                uint64_t rqhdr1:1;
-                uint64_t rqdata4:1;
-                uint64_t rqdata3:1;
-                uint64_t rqdata2:1;
-                uint64_t rqdata1:1;
-                uint64_t rqdata0:1;
-                uint64_t retry:1;
-                uint64_t ptlp_or:1;
-                uint64_t ntlp_or:1;
-                uint64_t ctlp_or:1;
-                uint64_t reserved_12_63:52;
-#endif
         } cn52xxp1;
         struct cvmx_pescx_bist_status_s cn56xx;
         struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
@@ -119,7 +86,6 @@ union cvmx_pescx_bist_status {
 union cvmx_pescx_bist_status2 {
         uint64_t u64;
         struct cvmx_pescx_bist_status2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t cto_p2e:1;
                 uint64_t e2p_cpl:1;
@@ -135,23 +101,6 @@ union cvmx_pescx_bist_status2 {
                 uint64_t pef_tcf1:1;
                 uint64_t pef_tc0:1;
                 uint64_t ppf:1;
-#else
-                uint64_t ppf:1;
-                uint64_t pef_tc0:1;
-                uint64_t pef_tcf1:1;
-                uint64_t pef_tnf:1;
-                uint64_t pef_tpf0:1;
-                uint64_t pef_tpf1:1;
-                uint64_t rsl_p2e:1;
-                uint64_t peai_p2e:1;
-                uint64_t dbg_p2e:1;
-                uint64_t e2p_rsl:1;
-                uint64_t e2p_p:1;
-                uint64_t e2p_n:1;
-                uint64_t e2p_cpl:1;
-                uint64_t cto_p2e:1;
-                uint64_t reserved_14_63:50;
-#endif
         } s;
         struct cvmx_pescx_bist_status2_s cn52xx;
         struct cvmx_pescx_bist_status2_s cn52xxp1;
@@ -162,13 +111,8 @@ union cvmx_pescx_bist_status2 {
 union cvmx_pescx_cfg_rd {
         uint64_t u64;
         struct cvmx_pescx_cfg_rd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t data:32;
                 uint64_t addr:32;
-#else
-                uint64_t addr:32;
-                uint64_t data:32;
-#endif
         } s;
         struct cvmx_pescx_cfg_rd_s cn52xx;
         struct cvmx_pescx_cfg_rd_s cn52xxp1;
@@ -179,13 +123,8 @@ union cvmx_pescx_cfg_rd {
 union cvmx_pescx_cfg_wr {
         uint64_t u64;
         struct cvmx_pescx_cfg_wr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t data:32;
                 uint64_t addr:32;
-#else
-                uint64_t addr:32;
-                uint64_t data:32;
-#endif
         } s;
         struct cvmx_pescx_cfg_wr_s cn52xx;
         struct cvmx_pescx_cfg_wr_s cn52xxp1;
@@ -196,13 +135,8 @@ union cvmx_pescx_cfg_wr {
 union cvmx_pescx_cpl_lut_valid {
         uint64_t u64;
         struct cvmx_pescx_cpl_lut_valid_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t tag:32;
-#else
-                uint64_t tag:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pescx_cpl_lut_valid_s cn52xx;
         struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
@@ -213,7 +147,6 @@ union cvmx_pescx_cpl_lut_valid {
 union cvmx_pescx_ctl_status {
         uint64_t u64;
         struct cvmx_pescx_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t dnum:5;
                 uint64_t pbus:8;
@@ -230,29 +163,10 @@ union cvmx_pescx_ctl_status {
                 uint64_t reserved_2_2:1;
                 uint64_t inv_ecrc:1;
                 uint64_t inv_lcrc:1;
-#else
-                uint64_t inv_lcrc:1;
-                uint64_t inv_ecrc:1;
-                uint64_t reserved_2_2:1;
-                uint64_t ro_ctlp:1;
-                uint64_t lnk_enb:1;
-                uint64_t dly_one:1;
-                uint64_t nf_ecrc:1;
-                uint64_t reserved_7_8:2;
-                uint64_t ob_p_cmd:1;
-                uint64_t pm_xpme:1;
-                uint64_t pm_xtoff:1;
-                uint64_t lane_swp:1;
-                uint64_t qlm_cfg:2;
-                uint64_t pbus:8;
-                uint64_t dnum:5;
-                uint64_t reserved_28_63:36;
-#endif
         } s;
         struct cvmx_pescx_ctl_status_s cn52xx;
         struct cvmx_pescx_ctl_status_s cn52xxp1;
         struct cvmx_pescx_ctl_status_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t dnum:5;
                 uint64_t pbus:8;
@@ -269,24 +183,6 @@ union cvmx_pescx_ctl_status {
                 uint64_t reserved_2_2:1;
                 uint64_t inv_ecrc:1;
                 uint64_t inv_lcrc:1;
-#else
-                uint64_t inv_lcrc:1;
-                uint64_t inv_ecrc:1;
-                uint64_t reserved_2_2:1;
-                uint64_t ro_ctlp:1;
-                uint64_t lnk_enb:1;
-                uint64_t dly_one:1;
-                uint64_t nf_ecrc:1;
-                uint64_t reserved_7_8:2;
-                uint64_t ob_p_cmd:1;
-                uint64_t pm_xpme:1;
-                uint64_t pm_xtoff:1;
-                uint64_t reserved_12_12:1;
-                uint64_t qlm_cfg:2;
-                uint64_t pbus:8;
-                uint64_t dnum:5;
-                uint64_t reserved_28_63:36;
-#endif
         } cn56xx;
         struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
 };
@@ -294,25 +190,14 @@ union cvmx_pescx_ctl_status {
 union cvmx_pescx_ctl_status2 {
         uint64_t u64;
         struct cvmx_pescx_ctl_status2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t pclk_run:1;
                 uint64_t pcierst:1;
-#else
-                uint64_t pcierst:1;
-                uint64_t pclk_run:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_pescx_ctl_status2_s cn52xx;
         struct cvmx_pescx_ctl_status2_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t pcierst:1;
-#else
-                uint64_t pcierst:1;
-                uint64_t reserved_1_63:63;
-#endif
         } cn52xxp1;
         struct cvmx_pescx_ctl_status2_s cn56xx;
         struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
@@ -321,7 +206,6 @@ union cvmx_pescx_ctl_status2 {
 union cvmx_pescx_dbg_info {
         uint64_t u64;
         struct cvmx_pescx_dbg_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_31_63:33;
                 uint64_t ecrc_e:1;
                 uint64_t rawwpp:1;
@@ -354,40 +238,6 @@ union cvmx_pescx_dbg_info {
                 uint64_t rtlplle:1;
                 uint64_t rtlpmal:1;
                 uint64_t spoison:1;
-#else
-                uint64_t spoison:1;
-                uint64_t rtlpmal:1;
-                uint64_t rtlplle:1;
-                uint64_t recrce:1;
-                uint64_t rpoison:1;
-                uint64_t rcemrc:1;
-                uint64_t rnfemrc:1;
-                uint64_t rfemrc:1;
-                uint64_t rpmerc:1;
-                uint64_t rptamrc:1;
-                uint64_t rumep:1;
-                uint64_t rvdm:1;
-                uint64_t acto:1;
-                uint64_t rte:1;
-                uint64_t mre:1;
-                uint64_t rdwdle:1;
-                uint64_t rtwdle:1;
-                uint64_t dpeoosd:1;
-                uint64_t fcpvwt:1;
-                uint64_t rpe:1;
-                uint64_t fcuv:1;
-                uint64_t rqo:1;
-                uint64_t rauc:1;
-                uint64_t racur:1;
-                uint64_t racca:1;
-                uint64_t caar:1;
-                uint64_t rarwdns:1;
-                uint64_t ramtlp:1;
-                uint64_t racpp:1;
-                uint64_t rawwpp:1;
-                uint64_t ecrc_e:1;
-                uint64_t reserved_31_63:33;
-#endif
         } s;
         struct cvmx_pescx_dbg_info_s cn52xx;
         struct cvmx_pescx_dbg_info_s cn52xxp1;
@@ -398,7 +248,6 @@ union cvmx_pescx_dbg_info {
 union cvmx_pescx_dbg_info_en {
         uint64_t u64;
         struct cvmx_pescx_dbg_info_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_31_63:33;
                 uint64_t ecrc_e:1;
                 uint64_t rawwpp:1;
@@ -431,40 +280,6 @@ union cvmx_pescx_dbg_info_en {
                 uint64_t rtlplle:1;
                 uint64_t rtlpmal:1;
                 uint64_t spoison:1;
-#else
-                uint64_t spoison:1;
-                uint64_t rtlpmal:1;
-                uint64_t rtlplle:1;
-                uint64_t recrce:1;
-                uint64_t rpoison:1;
-                uint64_t rcemrc:1;
-                uint64_t rnfemrc:1;
-                uint64_t rfemrc:1;
-                uint64_t rpmerc:1;
-                uint64_t rptamrc:1;
-                uint64_t rumep:1;
-                uint64_t rvdm:1;
-                uint64_t acto:1;
-                uint64_t rte:1;
-                uint64_t mre:1;
-                uint64_t rdwdle:1;
-                uint64_t rtwdle:1;
-                uint64_t dpeoosd:1;
-                uint64_t fcpvwt:1;
-                uint64_t rpe:1;
-                uint64_t fcuv:1;
-                uint64_t rqo:1;
-                uint64_t rauc:1;
-                uint64_t racur:1;
-                uint64_t racca:1;
-                uint64_t caar:1;
-                uint64_t rarwdns:1;
-                uint64_t ramtlp:1;
-                uint64_t racpp:1;
-                uint64_t rawwpp:1;
-                uint64_t ecrc_e:1;
-                uint64_t reserved_31_63:33;
-#endif
         } s;
         struct cvmx_pescx_dbg_info_en_s cn52xx;
         struct cvmx_pescx_dbg_info_en_s cn52xxp1;
@@ -475,19 +290,11 @@ union cvmx_pescx_dbg_info_en {
 union cvmx_pescx_diag_status {
         uint64_t u64;
         struct cvmx_pescx_diag_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t pm_dst:1;
                 uint64_t pm_stat:1;
                 uint64_t pm_en:1;
                 uint64_t aux_en:1;
-#else
-                uint64_t aux_en:1;
-                uint64_t pm_en:1;
-                uint64_t pm_stat:1;
-                uint64_t pm_dst:1;
-                uint64_t reserved_4_63:60;
-#endif
         } s;
         struct cvmx_pescx_diag_status_s cn52xx;
         struct cvmx_pescx_diag_status_s cn52xxp1;
@@ -498,13 +305,8 @@ union cvmx_pescx_diag_status {
 union cvmx_pescx_p2n_bar0_start {
         uint64_t u64;
         struct cvmx_pescx_p2n_bar0_start_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t addr:50;
                 uint64_t reserved_0_13:14;
-#else
-                uint64_t reserved_0_13:14;
-                uint64_t addr:50;
-#endif
         } s;
         struct cvmx_pescx_p2n_bar0_start_s cn52xx;
         struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
@@ -515,13 +317,8 @@ union cvmx_pescx_p2n_bar0_start {
 union cvmx_pescx_p2n_bar1_start {
         uint64_t u64;
         struct cvmx_pescx_p2n_bar1_start_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t addr:38;
                 uint64_t reserved_0_25:26;
-#else
-                uint64_t reserved_0_25:26;
-                uint64_t addr:38;
-#endif
         } s;
         struct cvmx_pescx_p2n_bar1_start_s cn52xx;
         struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
@@ -532,13 +329,8 @@ union cvmx_pescx_p2n_bar1_start {
 union cvmx_pescx_p2n_bar2_start {
         uint64_t u64;
         struct cvmx_pescx_p2n_bar2_start_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t addr:25;
                 uint64_t reserved_0_38:39;
-#else
-                uint64_t reserved_0_38:39;
-                uint64_t addr:25;
-#endif
         } s;
         struct cvmx_pescx_p2n_bar2_start_s cn52xx;
         struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
@@ -549,13 +341,8 @@ union cvmx_pescx_p2n_bar2_start {
 union cvmx_pescx_p2p_barx_end {
         uint64_t u64;
         struct cvmx_pescx_p2p_barx_end_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t addr:52;
                 uint64_t reserved_0_11:12;
-#else
-                uint64_t reserved_0_11:12;
-                uint64_t addr:52;
-#endif
         } s;
         struct cvmx_pescx_p2p_barx_end_s cn52xx;
         struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
@@ -566,13 +353,8 @@ union cvmx_pescx_p2p_barx_end {
 union cvmx_pescx_p2p_barx_start {
         uint64_t u64;
         struct cvmx_pescx_p2p_barx_start_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t addr:52;
                 uint64_t reserved_0_11:12;
-#else
-                uint64_t reserved_0_11:12;
-                uint64_t addr:52;
-#endif
         } s;
         struct cvmx_pescx_p2p_barx_start_s cn52xx;
         struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
@@ -583,14 +365,9 @@ union cvmx_pescx_p2p_barx_start {
 union cvmx_pescx_tlp_credits {
         uint64_t u64;
         struct cvmx_pescx_tlp_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
                 uint64_t reserved_0_63:64;
-#endif
         } s;
         struct cvmx_pescx_tlp_credits_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_56_63:8;
                 uint64_t peai_ppf:8;
                 uint64_t pesc_cpl:8;
@@ -599,19 +376,8 @@ union cvmx_pescx_tlp_credits {
                 uint64_t npei_cpl:8;
                 uint64_t npei_np:8;
                 uint64_t npei_p:8;
-#else
-                uint64_t npei_p:8;
-                uint64_t npei_np:8;
-                uint64_t npei_cpl:8;
-                uint64_t pesc_p:8;
-                uint64_t pesc_np:8;
-                uint64_t pesc_cpl:8;
-                uint64_t peai_ppf:8;
-                uint64_t reserved_56_63:8;
-#endif
         } cn52xx;
         struct cvmx_pescx_tlp_credits_cn52xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_38_63:26;
                 uint64_t peai_ppf:8;
                 uint64_t pesc_cpl:5;
@@ -620,16 +386,6 @@ union cvmx_pescx_tlp_credits {
                 uint64_t npei_cpl:5;
                 uint64_t npei_np:5;
                 uint64_t npei_p:5;
-#else
-                uint64_t npei_p:5;
-                uint64_t npei_np:5;
-                uint64_t npei_cpl:5;
-                uint64_t pesc_p:5;
-                uint64_t pesc_np:5;
-                uint64_t pesc_cpl:5;
-                uint64_t peai_ppf:8;
-                uint64_t reserved_38_63:26;
-#endif
         } cn52xxp1;
         struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
         struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index eb673f3514d..5ab8679d89a 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -25,6 +25,13 @@
  * Contact Cavium Networks for more information
  ***********************license end**************************************/
 
+/**
+ * cvmx-pexp-defs.h
+ *
+ * Configuration and status register (CSR) definitions for
+ * OCTEON PEXP.
+ *
+ */
 #ifndef __CVMX_PEXP_DEFS_H__
 #define __CVMX_PEXP_DEFS_H__
 
@@ -132,7 +139,7 @@
 #define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
 #define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
 #define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
-#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
 #define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
 #define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
 #define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
@@ -145,10 +152,7 @@
 #define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
-#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
-#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
-#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
 #define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
 #define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
@@ -202,7 +206,6 @@
 #define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
 #define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
-#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
 #define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
 #define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
@@ -211,14 +214,12 @@
 #define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
 #define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
-#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
-#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
 #define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
 #define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
 #define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
 #define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
 #define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
-#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
 #define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
deleted file mode 100644
index 05a917d6ebe..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-pip-defs.h
+++ /dev/null
@@ -1,3422 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_PIP_DEFS_H__
-#define __CVMX_PIP_DEFS_H__
-
-/*
- * Enumeration representing the amount of packet processing
- * and validation performed by the input hardware.
- */
-enum cvmx_pip_port_parse_mode {
-        /*
-         * Packet input doesn't perform any processing of the input
-         * packet.
-         */
-        CVMX_PIP_PORT_CFG_MODE_NONE = 0ull,
-        /*
-         * Full packet processing is performed with pointer starting
-         * at the L2 (ethernet MAC) header.
-         */
-        CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,
-        /*
-         * Input packets are assumed to be IP.  Results from non IP
-         * packets is undefined. Pointers reference the beginning of
-         * the IP header.
-         */
-        CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull
-};
-
-#define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8)
-#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull))
-#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull))
-#define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16)
-#define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16)
-#define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8)
-#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull))
-#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8)
-#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8)
-#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8)
-#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull))
-#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull))
-#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8)
-#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull))
-#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull))
-#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull))
-#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull))
-#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull))
-#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull))
-#define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8)
-#define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
-#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
-#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
-#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
-#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8)
-#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8)
-#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull))
-#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull))
-#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
-#define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16)
-#define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80)
-#define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128)
-#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull))
-#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32)
-#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32)
-#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32)
-#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32)
-#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32)
-#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32)
-#define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull))
-#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8)
-#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull))
-#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull))
-#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull))
-#define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8)
-#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40)
-#define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40)
-#define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40)
-#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40)
-#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40)
-#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40)
-#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40)
-#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40)
-#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40)
-#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40)
-#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40)
-#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40)
-
-union cvmx_pip_alt_skip_cfgx {
-        uint64_t u64;
-        struct cvmx_pip_alt_skip_cfgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_57_63:7;
-                uint64_t len:1;
-                uint64_t reserved_46_55:10;
-                uint64_t bit1:6;
-                uint64_t reserved_38_39:2;
-                uint64_t bit0:6;
-                uint64_t reserved_23_31:9;
-                uint64_t skip3:7;
-                uint64_t reserved_15_15:1;
-                uint64_t skip2:7;
-                uint64_t reserved_7_7:1;
-                uint64_t skip1:7;
-#else
-                uint64_t skip1:7;
-                uint64_t reserved_7_7:1;
-                uint64_t skip2:7;
-                uint64_t reserved_15_15:1;
-                uint64_t skip3:7;
-                uint64_t reserved_23_31:9;
-                uint64_t bit0:6;
-                uint64_t reserved_38_39:2;
-                uint64_t bit1:6;
-                uint64_t reserved_46_55:10;
-                uint64_t len:1;
-                uint64_t reserved_57_63:7;
-#endif
-        } s;
-        struct cvmx_pip_alt_skip_cfgx_s cn61xx;
-        struct cvmx_pip_alt_skip_cfgx_s cn66xx;
-        struct cvmx_pip_alt_skip_cfgx_s cn68xx;
-        struct cvmx_pip_alt_skip_cfgx_s cnf71xx;
-};
-
-union cvmx_pip_bck_prs {
-        uint64_t u64;
-        struct cvmx_pip_bck_prs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bckprs:1;
-                uint64_t reserved_13_62:50;
-                uint64_t hiwater:5;
-                uint64_t reserved_5_7:3;
-                uint64_t lowater:5;
-#else
-                uint64_t lowater:5;
-                uint64_t reserved_5_7:3;
-                uint64_t hiwater:5;
-                uint64_t reserved_13_62:50;
-                uint64_t bckprs:1;
-#endif
-        } s;
-        struct cvmx_pip_bck_prs_s cn38xx;
-        struct cvmx_pip_bck_prs_s cn38xxp2;
-        struct cvmx_pip_bck_prs_s cn56xx;
-        struct cvmx_pip_bck_prs_s cn56xxp1;
-        struct cvmx_pip_bck_prs_s cn58xx;
-        struct cvmx_pip_bck_prs_s cn58xxp1;
-        struct cvmx_pip_bck_prs_s cn61xx;
-        struct cvmx_pip_bck_prs_s cn63xx;
-        struct cvmx_pip_bck_prs_s cn63xxp1;
-        struct cvmx_pip_bck_prs_s cn66xx;
-        struct cvmx_pip_bck_prs_s cn68xx;
-        struct cvmx_pip_bck_prs_s cn68xxp1;
-        struct cvmx_pip_bck_prs_s cnf71xx;
-};
-
-union cvmx_pip_bist_status {
-        uint64_t u64;
-        struct cvmx_pip_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t bist:22;
-#else
-                uint64_t bist:22;
-                uint64_t reserved_22_63:42;
-#endif
-        } s;
-        struct cvmx_pip_bist_status_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_18_63:46;
-                uint64_t bist:18;
-#else
-                uint64_t bist:18;
-                uint64_t reserved_18_63:46;
-#endif
-        } cn30xx;
-        struct cvmx_pip_bist_status_cn30xx cn31xx;
-        struct cvmx_pip_bist_status_cn30xx cn38xx;
-        struct cvmx_pip_bist_status_cn30xx cn38xxp2;
-        struct cvmx_pip_bist_status_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t bist:17;
-#else
-                uint64_t bist:17;
-                uint64_t reserved_17_63:47;
-#endif
-        } cn50xx;
-        struct cvmx_pip_bist_status_cn30xx cn52xx;
-        struct cvmx_pip_bist_status_cn30xx cn52xxp1;
-        struct cvmx_pip_bist_status_cn30xx cn56xx;
-        struct cvmx_pip_bist_status_cn30xx cn56xxp1;
-        struct cvmx_pip_bist_status_cn30xx cn58xx;
-        struct cvmx_pip_bist_status_cn30xx cn58xxp1;
-        struct cvmx_pip_bist_status_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t bist:20;
-#else
-                uint64_t bist:20;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn61xx;
-        struct cvmx_pip_bist_status_cn30xx cn63xx;
-        struct cvmx_pip_bist_status_cn30xx cn63xxp1;
-        struct cvmx_pip_bist_status_cn61xx cn66xx;
-        struct cvmx_pip_bist_status_s cn68xx;
-        struct cvmx_pip_bist_status_cn61xx cn68xxp1;
-        struct cvmx_pip_bist_status_cn61xx cnf71xx;
-};
-
-union cvmx_pip_bsel_ext_cfgx {
-        uint64_t u64;
-        struct cvmx_pip_bsel_ext_cfgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t upper_tag:16;
-                uint64_t tag:8;
-                uint64_t reserved_25_31:7;
-                uint64_t offset:9;
-                uint64_t reserved_7_15:9;
-                uint64_t skip:7;
-#else
-                uint64_t skip:7;
-                uint64_t reserved_7_15:9;
-                uint64_t offset:9;
-                uint64_t reserved_25_31:7;
-                uint64_t tag:8;
-                uint64_t upper_tag:16;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_pip_bsel_ext_cfgx_s cn61xx;
-        struct cvmx_pip_bsel_ext_cfgx_s cn68xx;
-        struct cvmx_pip_bsel_ext_cfgx_s cnf71xx;
-};
-
-union cvmx_pip_bsel_ext_posx {
-        uint64_t u64;
-        struct cvmx_pip_bsel_ext_posx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t pos7_val:1;
-                uint64_t pos7:7;
-                uint64_t pos6_val:1;
-                uint64_t pos6:7;
-                uint64_t pos5_val:1;
-                uint64_t pos5:7;
-                uint64_t pos4_val:1;
-                uint64_t pos4:7;
-                uint64_t pos3_val:1;
-                uint64_t pos3:7;
-                uint64_t pos2_val:1;
-                uint64_t pos2:7;
-                uint64_t pos1_val:1;
-                uint64_t pos1:7;
-                uint64_t pos0_val:1;
-                uint64_t pos0:7;
-#else
-                uint64_t pos0:7;
-                uint64_t pos0_val:1;
-                uint64_t pos1:7;
-                uint64_t pos1_val:1;
-                uint64_t pos2:7;
-                uint64_t pos2_val:1;
-                uint64_t pos3:7;
-                uint64_t pos3_val:1;
-                uint64_t pos4:7;
-                uint64_t pos4_val:1;
-                uint64_t pos5:7;
-                uint64_t pos5_val:1;
-                uint64_t pos6:7;
-                uint64_t pos6_val:1;
-                uint64_t pos7:7;
-                uint64_t pos7_val:1;
-#endif
-        } s;
-        struct cvmx_pip_bsel_ext_posx_s cn61xx;
-        struct cvmx_pip_bsel_ext_posx_s cn68xx;
-        struct cvmx_pip_bsel_ext_posx_s cnf71xx;
-};
-
-union cvmx_pip_bsel_tbl_entx {
-        uint64_t u64;
-        struct cvmx_pip_bsel_tbl_entx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t tag_en:1;
-                uint64_t grp_en:1;
-                uint64_t tt_en:1;
-                uint64_t qos_en:1;
-                uint64_t reserved_40_59:20;
-                uint64_t tag:8;
-                uint64_t reserved_22_31:10;
-                uint64_t grp:6;
-                uint64_t reserved_10_15:6;
-                uint64_t tt:2;
-                uint64_t reserved_3_7:5;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t reserved_3_7:5;
-                uint64_t tt:2;
-                uint64_t reserved_10_15:6;
-                uint64_t grp:6;
-                uint64_t reserved_22_31:10;
-                uint64_t tag:8;
-                uint64_t reserved_40_59:20;
-                uint64_t qos_en:1;
-                uint64_t tt_en:1;
-                uint64_t grp_en:1;
-                uint64_t tag_en:1;
-#endif
-        } s;
-        struct cvmx_pip_bsel_tbl_entx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t tag_en:1;
-                uint64_t grp_en:1;
-                uint64_t tt_en:1;
-                uint64_t qos_en:1;
-                uint64_t reserved_40_59:20;
-                uint64_t tag:8;
-                uint64_t reserved_20_31:12;
-                uint64_t grp:4;
-                uint64_t reserved_10_15:6;
-                uint64_t tt:2;
-                uint64_t reserved_3_7:5;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t reserved_3_7:5;
-                uint64_t tt:2;
-                uint64_t reserved_10_15:6;
-                uint64_t grp:4;
-                uint64_t reserved_20_31:12;
-                uint64_t tag:8;
-                uint64_t reserved_40_59:20;
-                uint64_t qos_en:1;
-                uint64_t tt_en:1;
-                uint64_t grp_en:1;
-                uint64_t tag_en:1;
-#endif
-        } cn61xx;
-        struct cvmx_pip_bsel_tbl_entx_s cn68xx;
-        struct cvmx_pip_bsel_tbl_entx_cn61xx cnf71xx;
-};
-
-union cvmx_pip_clken {
-        uint64_t u64;
-        struct cvmx_pip_clken_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t clken:1;
-#else
-                uint64_t clken:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_pip_clken_s cn61xx;
-        struct cvmx_pip_clken_s cn63xx;
-        struct cvmx_pip_clken_s cn63xxp1;
-        struct cvmx_pip_clken_s cn66xx;
-        struct cvmx_pip_clken_s cn68xx;
-        struct cvmx_pip_clken_s cn68xxp1;
-        struct cvmx_pip_clken_s cnf71xx;
-};
-
-union cvmx_pip_crc_ctlx {
-        uint64_t u64;
-        struct cvmx_pip_crc_ctlx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t invres:1;
-                uint64_t reflect:1;
-#else
-                uint64_t reflect:1;
-                uint64_t invres:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_pip_crc_ctlx_s cn38xx;
-        struct cvmx_pip_crc_ctlx_s cn38xxp2;
-        struct cvmx_pip_crc_ctlx_s cn58xx;
-        struct cvmx_pip_crc_ctlx_s cn58xxp1;
-};
-
-union cvmx_pip_crc_ivx {
-        uint64_t u64;
-        struct cvmx_pip_crc_ivx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t iv:32;
-#else
-                uint64_t iv:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pip_crc_ivx_s cn38xx;
-        struct cvmx_pip_crc_ivx_s cn38xxp2;
-        struct cvmx_pip_crc_ivx_s cn58xx;
-        struct cvmx_pip_crc_ivx_s cn58xxp1;
-};
-
-union cvmx_pip_dec_ipsecx {
-        uint64_t u64;
-        struct cvmx_pip_dec_ipsecx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_18_63:46;
-                uint64_t tcp:1;
-                uint64_t udp:1;
-                uint64_t dprt:16;
-#else
-                uint64_t dprt:16;
-                uint64_t udp:1;
-                uint64_t tcp:1;
-                uint64_t reserved_18_63:46;
-#endif
-        } s;
-        struct cvmx_pip_dec_ipsecx_s cn30xx;
-        struct cvmx_pip_dec_ipsecx_s cn31xx;
-        struct cvmx_pip_dec_ipsecx_s cn38xx;
-        struct cvmx_pip_dec_ipsecx_s cn38xxp2;
-        struct cvmx_pip_dec_ipsecx_s cn50xx;
-        struct cvmx_pip_dec_ipsecx_s cn52xx;
-        struct cvmx_pip_dec_ipsecx_s cn52xxp1;
-        struct cvmx_pip_dec_ipsecx_s cn56xx;
-        struct cvmx_pip_dec_ipsecx_s cn56xxp1;
-        struct cvmx_pip_dec_ipsecx_s cn58xx;
-        struct cvmx_pip_dec_ipsecx_s cn58xxp1;
-        struct cvmx_pip_dec_ipsecx_s cn61xx;
-        struct cvmx_pip_dec_ipsecx_s cn63xx;
-        struct cvmx_pip_dec_ipsecx_s cn63xxp1;
-        struct cvmx_pip_dec_ipsecx_s cn66xx;
-        struct cvmx_pip_dec_ipsecx_s cn68xx;
-        struct cvmx_pip_dec_ipsecx_s cn68xxp1;
-        struct cvmx_pip_dec_ipsecx_s cnf71xx;
-};
-
-union cvmx_pip_dsa_src_grp {
-        uint64_t u64;
-        struct cvmx_pip_dsa_src_grp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t map15:4;
-                uint64_t map14:4;
-                uint64_t map13:4;
-                uint64_t map12:4;
-                uint64_t map11:4;
-                uint64_t map10:4;
-                uint64_t map9:4;
-                uint64_t map8:4;
-                uint64_t map7:4;
-                uint64_t map6:4;
-                uint64_t map5:4;
-                uint64_t map4:4;
-                uint64_t map3:4;
-                uint64_t map2:4;
-                uint64_t map1:4;
-                uint64_t map0:4;
-#else
-                uint64_t map0:4;
-                uint64_t map1:4;
-                uint64_t map2:4;
-                uint64_t map3:4;
-                uint64_t map4:4;
-                uint64_t map5:4;
-                uint64_t map6:4;
-                uint64_t map7:4;
-                uint64_t map8:4;
-                uint64_t map9:4;
-                uint64_t map10:4;
-                uint64_t map11:4;
-                uint64_t map12:4;
-                uint64_t map13:4;
-                uint64_t map14:4;
-                uint64_t map15:4;
-#endif
-        } s;
-        struct cvmx_pip_dsa_src_grp_s cn52xx;
-        struct cvmx_pip_dsa_src_grp_s cn52xxp1;
-        struct cvmx_pip_dsa_src_grp_s cn56xx;
-        struct cvmx_pip_dsa_src_grp_s cn61xx;
-        struct cvmx_pip_dsa_src_grp_s cn63xx;
-        struct cvmx_pip_dsa_src_grp_s cn63xxp1;
-        struct cvmx_pip_dsa_src_grp_s cn66xx;
-        struct cvmx_pip_dsa_src_grp_s cn68xx;
-        struct cvmx_pip_dsa_src_grp_s cn68xxp1;
-        struct cvmx_pip_dsa_src_grp_s cnf71xx;
-};
-
-union cvmx_pip_dsa_vid_grp {
-        uint64_t u64;
-        struct cvmx_pip_dsa_vid_grp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t map15:4;
-                uint64_t map14:4;
-                uint64_t map13:4;
-                uint64_t map12:4;
-                uint64_t map11:4;
-                uint64_t map10:4;
-                uint64_t map9:4;
-                uint64_t map8:4;
-                uint64_t map7:4;
-                uint64_t map6:4;
-                uint64_t map5:4;
-                uint64_t map4:4;
-                uint64_t map3:4;
-                uint64_t map2:4;
-                uint64_t map1:4;
-                uint64_t map0:4;
-#else
-                uint64_t map0:4;
-                uint64_t map1:4;
-                uint64_t map2:4;
-                uint64_t map3:4;
-                uint64_t map4:4;
-                uint64_t map5:4;
-                uint64_t map6:4;
-                uint64_t map7:4;
-                uint64_t map8:4;
-                uint64_t map9:4;
-                uint64_t map10:4;
-                uint64_t map11:4;
-                uint64_t map12:4;
-                uint64_t map13:4;
-                uint64_t map14:4;
-                uint64_t map15:4;
-#endif
-        } s;
-        struct cvmx_pip_dsa_vid_grp_s cn52xx;
-        struct cvmx_pip_dsa_vid_grp_s cn52xxp1;
-        struct cvmx_pip_dsa_vid_grp_s cn56xx;
-        struct cvmx_pip_dsa_vid_grp_s cn61xx;
-        struct cvmx_pip_dsa_vid_grp_s cn63xx;
-        struct cvmx_pip_dsa_vid_grp_s cn63xxp1;
-        struct cvmx_pip_dsa_vid_grp_s cn66xx;
-        struct cvmx_pip_dsa_vid_grp_s cn68xx;
-        struct cvmx_pip_dsa_vid_grp_s cn68xxp1;
-        struct cvmx_pip_dsa_vid_grp_s cnf71xx;
-};
-
-union cvmx_pip_frm_len_chkx {
-        uint64_t u64;
-        struct cvmx_pip_frm_len_chkx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t maxlen:16;
-                uint64_t minlen:16;
-#else
-                uint64_t minlen:16;
-                uint64_t maxlen:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pip_frm_len_chkx_s cn50xx;
-        struct cvmx_pip_frm_len_chkx_s cn52xx;
-        struct cvmx_pip_frm_len_chkx_s cn52xxp1;
-        struct cvmx_pip_frm_len_chkx_s cn56xx;
-        struct cvmx_pip_frm_len_chkx_s cn56xxp1;
-        struct cvmx_pip_frm_len_chkx_s cn61xx;
-        struct cvmx_pip_frm_len_chkx_s cn63xx;
-        struct cvmx_pip_frm_len_chkx_s cn63xxp1;
-        struct cvmx_pip_frm_len_chkx_s cn66xx;
-        struct cvmx_pip_frm_len_chkx_s cn68xx;
-        struct cvmx_pip_frm_len_chkx_s cn68xxp1;
-        struct cvmx_pip_frm_len_chkx_s cnf71xx;
-};
-
-union cvmx_pip_gbl_cfg {
-        uint64_t u64;
-        struct cvmx_pip_gbl_cfg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t tag_syn:1;
-                uint64_t ip6_udp:1;
-                uint64_t max_l2:1;
-                uint64_t reserved_11_15:5;
-                uint64_t raw_shf:3;
-                uint64_t reserved_3_7:5;
-                uint64_t nip_shf:3;
-#else
-                uint64_t nip_shf:3;
-                uint64_t reserved_3_7:5;
-                uint64_t raw_shf:3;
-                uint64_t reserved_11_15:5;
-                uint64_t max_l2:1;
-                uint64_t ip6_udp:1;
-                uint64_t tag_syn:1;
-                uint64_t reserved_19_63:45;
-#endif
-        } s;
-        struct cvmx_pip_gbl_cfg_s cn30xx;
-        struct cvmx_pip_gbl_cfg_s cn31xx;
-        struct cvmx_pip_gbl_cfg_s cn38xx;
-        struct cvmx_pip_gbl_cfg_s cn38xxp2;
-        struct cvmx_pip_gbl_cfg_s cn50xx;
-        struct cvmx_pip_gbl_cfg_s cn52xx;
-        struct cvmx_pip_gbl_cfg_s cn52xxp1;
-        struct cvmx_pip_gbl_cfg_s cn56xx;
-        struct cvmx_pip_gbl_cfg_s cn56xxp1;
-        struct cvmx_pip_gbl_cfg_s cn58xx;
-        struct cvmx_pip_gbl_cfg_s cn58xxp1;
-        struct cvmx_pip_gbl_cfg_s cn61xx;
-        struct cvmx_pip_gbl_cfg_s cn63xx;
-        struct cvmx_pip_gbl_cfg_s cn63xxp1;
-        struct cvmx_pip_gbl_cfg_s cn66xx;
-        struct cvmx_pip_gbl_cfg_s cn68xx;
-        struct cvmx_pip_gbl_cfg_s cn68xxp1;
-        struct cvmx_pip_gbl_cfg_s cnf71xx;
-};
-
-union cvmx_pip_gbl_ctl {
-        uint64_t u64;
-        struct cvmx_pip_gbl_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t egrp_dis:1;
-                uint64_t ihmsk_dis:1;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_sid:1;
-                uint64_t reserved_21_23:3;
-                uint64_t ring_en:1;
-                uint64_t reserved_17_19:3;
-                uint64_t ignrs:1;
-                uint64_t vs_wqe:1;
-                uint64_t vs_qos:1;
-                uint64_t l2_mal:1;
-                uint64_t tcp_flag:1;
-                uint64_t l4_len:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_mal:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ip6_eext:2;
-                uint64_t ip4_opts:1;
-                uint64_t ip_hop:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_chk:1;
-#else
-                uint64_t ip_chk:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_hop:1;
-                uint64_t ip4_opts:1;
-                uint64_t ip6_eext:2;
-                uint64_t reserved_6_7:2;
-                uint64_t l4_mal:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_len:1;
-                uint64_t tcp_flag:1;
-                uint64_t l2_mal:1;
-                uint64_t vs_qos:1;
-                uint64_t vs_wqe:1;
-                uint64_t ignrs:1;
-                uint64_t reserved_17_19:3;
-                uint64_t ring_en:1;
-                uint64_t reserved_21_23:3;
-                uint64_t dsa_grp_sid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t ihmsk_dis:1;
-                uint64_t egrp_dis:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } s;
-        struct cvmx_pip_gbl_ctl_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t ignrs:1;
-                uint64_t vs_wqe:1;
-                uint64_t vs_qos:1;
-                uint64_t l2_mal:1;
-                uint64_t tcp_flag:1;
-                uint64_t l4_len:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_mal:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ip6_eext:2;
-                uint64_t ip4_opts:1;
-                uint64_t ip_hop:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_chk:1;
-#else
-                uint64_t ip_chk:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_hop:1;
-                uint64_t ip4_opts:1;
-                uint64_t ip6_eext:2;
-                uint64_t reserved_6_7:2;
-                uint64_t l4_mal:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_len:1;
-                uint64_t tcp_flag:1;
-                uint64_t l2_mal:1;
-                uint64_t vs_qos:1;
-                uint64_t vs_wqe:1;
-                uint64_t ignrs:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } cn30xx;
-        struct cvmx_pip_gbl_ctl_cn30xx cn31xx;
-        struct cvmx_pip_gbl_ctl_cn30xx cn38xx;
-        struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2;
-        struct cvmx_pip_gbl_ctl_cn30xx cn50xx;
-        struct cvmx_pip_gbl_ctl_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_27_63:37;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_sid:1;
-                uint64_t reserved_21_23:3;
-                uint64_t ring_en:1;
-                uint64_t reserved_17_19:3;
-                uint64_t ignrs:1;
-                uint64_t vs_wqe:1;
-                uint64_t vs_qos:1;
-                uint64_t l2_mal:1;
-                uint64_t tcp_flag:1;
-                uint64_t l4_len:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_mal:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ip6_eext:2;
-                uint64_t ip4_opts:1;
-                uint64_t ip_hop:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_chk:1;
-#else
-                uint64_t ip_chk:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_hop:1;
-                uint64_t ip4_opts:1;
-                uint64_t ip6_eext:2;
-                uint64_t reserved_6_7:2;
-                uint64_t l4_mal:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_len:1;
-                uint64_t tcp_flag:1;
-                uint64_t l2_mal:1;
-                uint64_t vs_qos:1;
-                uint64_t vs_wqe:1;
-                uint64_t ignrs:1;
-                uint64_t reserved_17_19:3;
-                uint64_t ring_en:1;
-                uint64_t reserved_21_23:3;
-                uint64_t dsa_grp_sid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t reserved_27_63:37;
-#endif
-        } cn52xx;
-        struct cvmx_pip_gbl_ctl_cn52xx cn52xxp1;
-        struct cvmx_pip_gbl_ctl_cn52xx cn56xx;
-        struct cvmx_pip_gbl_ctl_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_21_63:43;
-                uint64_t ring_en:1;
-                uint64_t reserved_17_19:3;
-                uint64_t ignrs:1;
-                uint64_t vs_wqe:1;
-                uint64_t vs_qos:1;
-                uint64_t l2_mal:1;
-                uint64_t tcp_flag:1;
-                uint64_t l4_len:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_mal:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ip6_eext:2;
-                uint64_t ip4_opts:1;
-                uint64_t ip_hop:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_chk:1;
-#else
-                uint64_t ip_chk:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_hop:1;
-                uint64_t ip4_opts:1;
-                uint64_t ip6_eext:2;
-                uint64_t reserved_6_7:2;
-                uint64_t l4_mal:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_len:1;
-                uint64_t tcp_flag:1;
-                uint64_t l2_mal:1;
-                uint64_t vs_qos:1;
-                uint64_t vs_wqe:1;
-                uint64_t ignrs:1;
-                uint64_t reserved_17_19:3;
-                uint64_t ring_en:1;
-                uint64_t reserved_21_63:43;
-#endif
-        } cn56xxp1;
-        struct cvmx_pip_gbl_ctl_cn30xx cn58xx;
-        struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1;
-        struct cvmx_pip_gbl_ctl_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t ihmsk_dis:1;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_sid:1;
-                uint64_t reserved_21_23:3;
-                uint64_t ring_en:1;
-                uint64_t reserved_17_19:3;
-                uint64_t ignrs:1;
-                uint64_t vs_wqe:1;
-                uint64_t vs_qos:1;
-                uint64_t l2_mal:1;
-                uint64_t tcp_flag:1;
-                uint64_t l4_len:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_mal:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ip6_eext:2;
-                uint64_t ip4_opts:1;
-                uint64_t ip_hop:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_chk:1;
-#else
-                uint64_t ip_chk:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_hop:1;
-                uint64_t ip4_opts:1;
-                uint64_t ip6_eext:2;
-                uint64_t reserved_6_7:2;
-                uint64_t l4_mal:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_len:1;
-                uint64_t tcp_flag:1;
-                uint64_t l2_mal:1;
-                uint64_t vs_qos:1;
-                uint64_t vs_wqe:1;
-                uint64_t ignrs:1;
-                uint64_t reserved_17_19:3;
-                uint64_t ring_en:1;
-                uint64_t reserved_21_23:3;
-                uint64_t dsa_grp_sid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t ihmsk_dis:1;
-                uint64_t reserved_28_63:36;
-#endif
-        } cn61xx;
-        struct cvmx_pip_gbl_ctl_cn61xx cn63xx;
-        struct cvmx_pip_gbl_ctl_cn61xx cn63xxp1;
-        struct cvmx_pip_gbl_ctl_cn61xx cn66xx;
-        struct cvmx_pip_gbl_ctl_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t egrp_dis:1;
-                uint64_t ihmsk_dis:1;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_sid:1;
-                uint64_t reserved_17_23:7;
-                uint64_t ignrs:1;
-                uint64_t vs_wqe:1;
-                uint64_t vs_qos:1;
-                uint64_t l2_mal:1;
-                uint64_t tcp_flag:1;
-                uint64_t l4_len:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_mal:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ip6_eext:2;
-                uint64_t ip4_opts:1;
-                uint64_t ip_hop:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_chk:1;
-#else
-                uint64_t ip_chk:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_hop:1;
-                uint64_t ip4_opts:1;
-                uint64_t ip6_eext:2;
-                uint64_t reserved_6_7:2;
-                uint64_t l4_mal:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_len:1;
-                uint64_t tcp_flag:1;
-                uint64_t l2_mal:1;
-                uint64_t vs_qos:1;
-                uint64_t vs_wqe:1;
-                uint64_t ignrs:1;
-                uint64_t reserved_17_23:7;
-                uint64_t dsa_grp_sid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t ihmsk_dis:1;
-                uint64_t egrp_dis:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn68xx;
-        struct cvmx_pip_gbl_ctl_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t ihmsk_dis:1;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_sid:1;
-                uint64_t reserved_17_23:7;
-                uint64_t ignrs:1;
-                uint64_t vs_wqe:1;
-                uint64_t vs_qos:1;
-                uint64_t l2_mal:1;
-                uint64_t tcp_flag:1;
-                uint64_t l4_len:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_mal:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ip6_eext:2;
-                uint64_t ip4_opts:1;
-                uint64_t ip_hop:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_chk:1;
-#else
-                uint64_t ip_chk:1;
-                uint64_t ip_mal:1;
-                uint64_t ip_hop:1;
-                uint64_t ip4_opts:1;
-                uint64_t ip6_eext:2;
-                uint64_t reserved_6_7:2;
-                uint64_t l4_mal:1;
-                uint64_t l4_prt:1;
-                uint64_t l4_chk:1;
-                uint64_t l4_len:1;
-                uint64_t tcp_flag:1;
-                uint64_t l2_mal:1;
-                uint64_t vs_qos:1;
-                uint64_t vs_wqe:1;
-                uint64_t ignrs:1;
-                uint64_t reserved_17_23:7;
-                uint64_t dsa_grp_sid:1;
-                uint64_t dsa_grp_scmd:1;
-                uint64_t dsa_grp_tvid:1;
-                uint64_t ihmsk_dis:1;
-                uint64_t reserved_28_63:36;
-#endif
-        } cn68xxp1;
-        struct cvmx_pip_gbl_ctl_cn61xx cnf71xx;
-};
-
-union cvmx_pip_hg_pri_qos {
-        uint64_t u64;
-        struct cvmx_pip_hg_pri_qos_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t up_qos:1;
-                uint64_t reserved_11_11:1;
-                uint64_t qos:3;
-                uint64_t reserved_6_7:2;
-                uint64_t pri:6;
-#else
-                uint64_t pri:6;
-                uint64_t reserved_6_7:2;
-                uint64_t qos:3;
-                uint64_t reserved_11_11:1;
-                uint64_t up_qos:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_pip_hg_pri_qos_s cn52xx;
-        struct cvmx_pip_hg_pri_qos_s cn52xxp1;
-        struct cvmx_pip_hg_pri_qos_s cn56xx;
-        struct cvmx_pip_hg_pri_qos_s cn61xx;
-        struct cvmx_pip_hg_pri_qos_s cn63xx;
-        struct cvmx_pip_hg_pri_qos_s cn63xxp1;
-        struct cvmx_pip_hg_pri_qos_s cn66xx;
-        struct cvmx_pip_hg_pri_qos_s cnf71xx;
-};
-
-union cvmx_pip_int_en {
-        uint64_t u64;
-        struct cvmx_pip_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t punyerr:1;
-                uint64_t lenerr:1;
-                uint64_t maxerr:1;
-                uint64_t minerr:1;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t crcerr:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t crcerr:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t minerr:1;
-                uint64_t maxerr:1;
-                uint64_t lenerr:1;
-                uint64_t punyerr:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_pip_int_en_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t crcerr:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t crcerr:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn30xx;
-        struct cvmx_pip_int_en_cn30xx cn31xx;
-        struct cvmx_pip_int_en_cn30xx cn38xx;
-        struct cvmx_pip_int_en_cn30xx cn38xxp2;
-        struct cvmx_pip_int_en_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t lenerr:1;
-                uint64_t maxerr:1;
-                uint64_t minerr:1;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t reserved_1_1:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t minerr:1;
-                uint64_t maxerr:1;
-                uint64_t lenerr:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn50xx;
-        struct cvmx_pip_int_en_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t punyerr:1;
-                uint64_t lenerr:1;
-                uint64_t maxerr:1;
-                uint64_t minerr:1;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t reserved_1_1:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t minerr:1;
-                uint64_t maxerr:1;
-                uint64_t lenerr:1;
-                uint64_t punyerr:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } cn52xx;
-        struct cvmx_pip_int_en_cn52xx cn52xxp1;
-        struct cvmx_pip_int_en_s cn56xx;
-        struct cvmx_pip_int_en_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t lenerr:1;
-                uint64_t maxerr:1;
-                uint64_t minerr:1;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t crcerr:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t crcerr:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t minerr:1;
-                uint64_t maxerr:1;
-                uint64_t lenerr:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn56xxp1;
-        struct cvmx_pip_int_en_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t punyerr:1;
-                uint64_t reserved_9_11:3;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t crcerr:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t crcerr:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t reserved_9_11:3;
-                uint64_t punyerr:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } cn58xx;
-        struct cvmx_pip_int_en_cn30xx cn58xxp1;
-        struct cvmx_pip_int_en_s cn61xx;
-        struct cvmx_pip_int_en_s cn63xx;
-        struct cvmx_pip_int_en_s cn63xxp1;
-        struct cvmx_pip_int_en_s cn66xx;
-        struct cvmx_pip_int_en_s cn68xx;
-        struct cvmx_pip_int_en_s cn68xxp1;
-        struct cvmx_pip_int_en_s cnf71xx;
-};
-
-union cvmx_pip_int_reg {
-        uint64_t u64;
-        struct cvmx_pip_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t punyerr:1;
-                uint64_t lenerr:1;
-                uint64_t maxerr:1;
-                uint64_t minerr:1;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t crcerr:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t crcerr:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t minerr:1;
-                uint64_t maxerr:1;
-                uint64_t lenerr:1;
-                uint64_t punyerr:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_pip_int_reg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t crcerr:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t crcerr:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn30xx;
-        struct cvmx_pip_int_reg_cn30xx cn31xx;
-        struct cvmx_pip_int_reg_cn30xx cn38xx;
-        struct cvmx_pip_int_reg_cn30xx cn38xxp2;
-        struct cvmx_pip_int_reg_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t lenerr:1;
-                uint64_t maxerr:1;
-                uint64_t minerr:1;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t reserved_1_1:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t minerr:1;
-                uint64_t maxerr:1;
-                uint64_t lenerr:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn50xx;
-        struct cvmx_pip_int_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t punyerr:1;
-                uint64_t lenerr:1;
-                uint64_t maxerr:1;
-                uint64_t minerr:1;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t reserved_1_1:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t minerr:1;
-                uint64_t maxerr:1;
-                uint64_t lenerr:1;
-                uint64_t punyerr:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } cn52xx;
-        struct cvmx_pip_int_reg_cn52xx cn52xxp1;
-        struct cvmx_pip_int_reg_s cn56xx;
-        struct cvmx_pip_int_reg_cn56xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t lenerr:1;
-                uint64_t maxerr:1;
-                uint64_t minerr:1;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t crcerr:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t crcerr:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t minerr:1;
-                uint64_t maxerr:1;
-                uint64_t lenerr:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn56xxp1;
-        struct cvmx_pip_int_reg_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t punyerr:1;
-                uint64_t reserved_9_11:3;
-                uint64_t beperr:1;
-                uint64_t feperr:1;
-                uint64_t todoovr:1;
-                uint64_t skprunt:1;
-                uint64_t badtag:1;
-                uint64_t prtnxa:1;
-                uint64_t bckprs:1;
-                uint64_t crcerr:1;
-                uint64_t pktdrp:1;
-#else
-                uint64_t pktdrp:1;
-                uint64_t crcerr:1;
-                uint64_t bckprs:1;
-                uint64_t prtnxa:1;
-                uint64_t badtag:1;
-                uint64_t skprunt:1;
-                uint64_t todoovr:1;
-                uint64_t feperr:1;
-                uint64_t beperr:1;
-                uint64_t reserved_9_11:3;
-                uint64_t punyerr:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } cn58xx;
-        struct cvmx_pip_int_reg_cn30xx cn58xxp1;
-        struct cvmx_pip_int_reg_s cn61xx;
-        struct cvmx_pip_int_reg_s cn63xx;
-        struct cvmx_pip_int_reg_s cn63xxp1;
-        struct cvmx_pip_int_reg_s cn66xx;
-        struct cvmx_pip_int_reg_s cn68xx;
-        struct cvmx_pip_int_reg_s cn68xxp1;
-        struct cvmx_pip_int_reg_s cnf71xx;
-};
-
-union cvmx_pip_ip_offset {
-        uint64_t u64;
-        struct cvmx_pip_ip_offset_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t offset:3;
-#else
-                uint64_t offset:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_pip_ip_offset_s cn30xx;
-        struct cvmx_pip_ip_offset_s cn31xx;
-        struct cvmx_pip_ip_offset_s cn38xx;
-        struct cvmx_pip_ip_offset_s cn38xxp2;
-        struct cvmx_pip_ip_offset_s cn50xx;
-        struct cvmx_pip_ip_offset_s cn52xx;
-        struct cvmx_pip_ip_offset_s cn52xxp1;
-        struct cvmx_pip_ip_offset_s cn56xx;
-        struct cvmx_pip_ip_offset_s cn56xxp1;
-        struct cvmx_pip_ip_offset_s cn58xx;
-        struct cvmx_pip_ip_offset_s cn58xxp1;
-        struct cvmx_pip_ip_offset_s cn61xx;
-        struct cvmx_pip_ip_offset_s cn63xx;
-        struct cvmx_pip_ip_offset_s cn63xxp1;
-        struct cvmx_pip_ip_offset_s cn66xx;
-        struct cvmx_pip_ip_offset_s cn68xx;
-        struct cvmx_pip_ip_offset_s cn68xxp1;
-        struct cvmx_pip_ip_offset_s cnf71xx;
-};
-
-union cvmx_pip_pri_tblx {
-        uint64_t u64;
-        struct cvmx_pip_pri_tblx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t diff2_padd:8;
-                uint64_t hg2_padd:8;
-                uint64_t vlan2_padd:8;
-                uint64_t reserved_38_39:2;
-                uint64_t diff2_bpid:6;
-                uint64_t reserved_30_31:2;
-                uint64_t hg2_bpid:6;
-                uint64_t reserved_22_23:2;
-                uint64_t vlan2_bpid:6;
-                uint64_t reserved_11_15:5;
-                uint64_t diff2_qos:3;
-                uint64_t reserved_7_7:1;
-                uint64_t hg2_qos:3;
-                uint64_t reserved_3_3:1;
-                uint64_t vlan2_qos:3;
-#else
-                uint64_t vlan2_qos:3;
-                uint64_t reserved_3_3:1;
-                uint64_t hg2_qos:3;
-                uint64_t reserved_7_7:1;
-                uint64_t diff2_qos:3;
-                uint64_t reserved_11_15:5;
-                uint64_t vlan2_bpid:6;
-                uint64_t reserved_22_23:2;
-                uint64_t hg2_bpid:6;
-                uint64_t reserved_30_31:2;
-                uint64_t diff2_bpid:6;
-                uint64_t reserved_38_39:2;
-                uint64_t vlan2_padd:8;
-                uint64_t hg2_padd:8;
-                uint64_t diff2_padd:8;
-#endif
-        } s;
-        struct cvmx_pip_pri_tblx_s cn68xx;
-        struct cvmx_pip_pri_tblx_s cn68xxp1;
-};
-
-union cvmx_pip_prt_cfgx {
-        uint64_t u64;
-        struct cvmx_pip_prt_cfgx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_55_63:9;
-                uint64_t ih_pri:1;
-                uint64_t len_chk_sel:1;
-                uint64_t pad_len:1;
-                uint64_t vlan_len:1;
-                uint64_t lenerr_en:1;
-                uint64_t maxerr_en:1;
-                uint64_t minerr_en:1;
-                uint64_t grp_wat_47:4;
-                uint64_t qos_wat_47:4;
-                uint64_t reserved_37_39:3;
-                uint64_t rawdrp:1;
-                uint64_t tag_inc:2;
-                uint64_t dyn_rs:1;
-                uint64_t inst_hdr:1;
-                uint64_t grp_wat:4;
-                uint64_t hg_qos:1;
-                uint64_t qos:3;
-                uint64_t qos_wat:4;
-                uint64_t qos_vsel:1;
-                uint64_t qos_vod:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vlan:1;
-                uint64_t reserved_13_15:3;
-                uint64_t crc_en:1;
-                uint64_t higig_en:1;
-                uint64_t dsa_en:1;
-                uint64_t mode:2;
-                uint64_t reserved_7_7:1;
-                uint64_t skip:7;
-#else
-                uint64_t skip:7;
-                uint64_t reserved_7_7:1;
-                uint64_t mode:2;
-                uint64_t dsa_en:1;
-                uint64_t higig_en:1;
-                uint64_t crc_en:1;
-                uint64_t reserved_13_15:3;
-                uint64_t qos_vlan:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vod:1;
-                uint64_t qos_vsel:1;
-                uint64_t qos_wat:4;
-                uint64_t qos:3;
-                uint64_t hg_qos:1;
-                uint64_t grp_wat:4;
-                uint64_t inst_hdr:1;
-                uint64_t dyn_rs:1;
-                uint64_t tag_inc:2;
-                uint64_t rawdrp:1;
-                uint64_t reserved_37_39:3;
-                uint64_t qos_wat_47:4;
-                uint64_t grp_wat_47:4;
-                uint64_t minerr_en:1;
-                uint64_t maxerr_en:1;
-                uint64_t lenerr_en:1;
-                uint64_t vlan_len:1;
-                uint64_t pad_len:1;
-                uint64_t len_chk_sel:1;
-                uint64_t ih_pri:1;
-                uint64_t reserved_55_63:9;
-#endif
-        } s;
-        struct cvmx_pip_prt_cfgx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_37_63:27;
-                uint64_t rawdrp:1;
-                uint64_t tag_inc:2;
-                uint64_t dyn_rs:1;
-                uint64_t inst_hdr:1;
-                uint64_t grp_wat:4;
-                uint64_t reserved_27_27:1;
-                uint64_t qos:3;
-                uint64_t qos_wat:4;
-                uint64_t reserved_18_19:2;
-                uint64_t qos_diff:1;
-                uint64_t qos_vlan:1;
-                uint64_t reserved_10_15:6;
-                uint64_t mode:2;
-                uint64_t reserved_7_7:1;
-                uint64_t skip:7;
-#else
-                uint64_t skip:7;
-                uint64_t reserved_7_7:1;
-                uint64_t mode:2;
-                uint64_t reserved_10_15:6;
-                uint64_t qos_vlan:1;
-                uint64_t qos_diff:1;
-                uint64_t reserved_18_19:2;
-                uint64_t qos_wat:4;
-                uint64_t qos:3;
-                uint64_t reserved_27_27:1;
-                uint64_t grp_wat:4;
-                uint64_t inst_hdr:1;
-                uint64_t dyn_rs:1;
-                uint64_t tag_inc:2;
-                uint64_t rawdrp:1;
-                uint64_t reserved_37_63:27;
-#endif
-        } cn30xx;
-        struct cvmx_pip_prt_cfgx_cn30xx cn31xx;
-        struct cvmx_pip_prt_cfgx_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_37_63:27;
-                uint64_t rawdrp:1;
-                uint64_t tag_inc:2;
-                uint64_t dyn_rs:1;
-                uint64_t inst_hdr:1;
-                uint64_t grp_wat:4;
-                uint64_t reserved_27_27:1;
-                uint64_t qos:3;
-                uint64_t qos_wat:4;
-                uint64_t reserved_18_19:2;
-                uint64_t qos_diff:1;
-                uint64_t qos_vlan:1;
-                uint64_t reserved_13_15:3;
-                uint64_t crc_en:1;
-                uint64_t reserved_10_11:2;
-                uint64_t mode:2;
-                uint64_t reserved_7_7:1;
-                uint64_t skip:7;
-#else
-                uint64_t skip:7;
-                uint64_t reserved_7_7:1;
-                uint64_t mode:2;
-                uint64_t reserved_10_11:2;
-                uint64_t crc_en:1;
-                uint64_t reserved_13_15:3;
-                uint64_t qos_vlan:1;
-                uint64_t qos_diff:1;
-                uint64_t reserved_18_19:2;
-                uint64_t qos_wat:4;
-                uint64_t qos:3;
-                uint64_t reserved_27_27:1;
-                uint64_t grp_wat:4;
-                uint64_t inst_hdr:1;
-                uint64_t dyn_rs:1;
-                uint64_t tag_inc:2;
-                uint64_t rawdrp:1;
-                uint64_t reserved_37_63:27;
-#endif
-        } cn38xx;
-        struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2;
-        struct cvmx_pip_prt_cfgx_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_53_63:11;
-                uint64_t pad_len:1;
-                uint64_t vlan_len:1;
-                uint64_t lenerr_en:1;
-                uint64_t maxerr_en:1;
-                uint64_t minerr_en:1;
-                uint64_t grp_wat_47:4;
-                uint64_t qos_wat_47:4;
-                uint64_t reserved_37_39:3;
-                uint64_t rawdrp:1;
-                uint64_t tag_inc:2;
-                uint64_t dyn_rs:1;
-                uint64_t inst_hdr:1;
-                uint64_t grp_wat:4;
-                uint64_t reserved_27_27:1;
-                uint64_t qos:3;
-                uint64_t qos_wat:4;
-                uint64_t reserved_19_19:1;
-                uint64_t qos_vod:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vlan:1;
-                uint64_t reserved_13_15:3;
-                uint64_t crc_en:1;
-                uint64_t reserved_10_11:2;
-                uint64_t mode:2;
-                uint64_t reserved_7_7:1;
-                uint64_t skip:7;
-#else
-                uint64_t skip:7;
-                uint64_t reserved_7_7:1;
-                uint64_t mode:2;
-                uint64_t reserved_10_11:2;
-                uint64_t crc_en:1;
-                uint64_t reserved_13_15:3;
-                uint64_t qos_vlan:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vod:1;
-                uint64_t reserved_19_19:1;
-                uint64_t qos_wat:4;
-                uint64_t qos:3;
-                uint64_t reserved_27_27:1;
-                uint64_t grp_wat:4;
-                uint64_t inst_hdr:1;
-                uint64_t dyn_rs:1;
-                uint64_t tag_inc:2;
-                uint64_t rawdrp:1;
-                uint64_t reserved_37_39:3;
-                uint64_t qos_wat_47:4;
-                uint64_t grp_wat_47:4;
-                uint64_t minerr_en:1;
-                uint64_t maxerr_en:1;
-                uint64_t lenerr_en:1;
-                uint64_t vlan_len:1;
-                uint64_t pad_len:1;
-                uint64_t reserved_53_63:11;
-#endif
-        } cn50xx;
-        struct cvmx_pip_prt_cfgx_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_53_63:11;
-                uint64_t pad_len:1;
-                uint64_t vlan_len:1;
-                uint64_t lenerr_en:1;
-                uint64_t maxerr_en:1;
-                uint64_t minerr_en:1;
-                uint64_t grp_wat_47:4;
-                uint64_t qos_wat_47:4;
-                uint64_t reserved_37_39:3;
-                uint64_t rawdrp:1;
-                uint64_t tag_inc:2;
-                uint64_t dyn_rs:1;
-                uint64_t inst_hdr:1;
-                uint64_t grp_wat:4;
-                uint64_t hg_qos:1;
-                uint64_t qos:3;
-                uint64_t qos_wat:4;
-                uint64_t qos_vsel:1;
-                uint64_t qos_vod:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vlan:1;
-                uint64_t reserved_13_15:3;
-                uint64_t crc_en:1;
-                uint64_t higig_en:1;
-                uint64_t dsa_en:1;
-                uint64_t mode:2;
-                uint64_t reserved_7_7:1;
-                uint64_t skip:7;
-#else
-                uint64_t skip:7;
-                uint64_t reserved_7_7:1;
-                uint64_t mode:2;
-                uint64_t dsa_en:1;
-                uint64_t higig_en:1;
-                uint64_t crc_en:1;
-                uint64_t reserved_13_15:3;
-                uint64_t qos_vlan:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vod:1;
-                uint64_t qos_vsel:1;
-                uint64_t qos_wat:4;
-                uint64_t qos:3;
-                uint64_t hg_qos:1;
-                uint64_t grp_wat:4;
-                uint64_t inst_hdr:1;
-                uint64_t dyn_rs:1;
-                uint64_t tag_inc:2;
-                uint64_t rawdrp:1;
-                uint64_t reserved_37_39:3;
-                uint64_t qos_wat_47:4;
-                uint64_t grp_wat_47:4;
-                uint64_t minerr_en:1;
-                uint64_t maxerr_en:1;
-                uint64_t lenerr_en:1;
-                uint64_t vlan_len:1;
-                uint64_t pad_len:1;
-                uint64_t reserved_53_63:11;
-#endif
-        } cn52xx;
-        struct cvmx_pip_prt_cfgx_cn52xx cn52xxp1;
-        struct cvmx_pip_prt_cfgx_cn52xx cn56xx;
-        struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1;
-        struct cvmx_pip_prt_cfgx_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_37_63:27;
-                uint64_t rawdrp:1;
-                uint64_t tag_inc:2;
-                uint64_t dyn_rs:1;
-                uint64_t inst_hdr:1;
-                uint64_t grp_wat:4;
-                uint64_t reserved_27_27:1;
-                uint64_t qos:3;
-                uint64_t qos_wat:4;
-                uint64_t reserved_19_19:1;
-                uint64_t qos_vod:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vlan:1;
-                uint64_t reserved_13_15:3;
-                uint64_t crc_en:1;
-                uint64_t reserved_10_11:2;
-                uint64_t mode:2;
-                uint64_t reserved_7_7:1;
-                uint64_t skip:7;
-#else
-                uint64_t skip:7;
-                uint64_t reserved_7_7:1;
-                uint64_t mode:2;
-                uint64_t reserved_10_11:2;
-                uint64_t crc_en:1;
-                uint64_t reserved_13_15:3;
-                uint64_t qos_vlan:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vod:1;
-                uint64_t reserved_19_19:1;
-                uint64_t qos_wat:4;
-                uint64_t qos:3;
-                uint64_t reserved_27_27:1;
-                uint64_t grp_wat:4;
-                uint64_t inst_hdr:1;
-                uint64_t dyn_rs:1;
-                uint64_t tag_inc:2;
-                uint64_t rawdrp:1;
-                uint64_t reserved_37_63:27;
-#endif
-        } cn58xx;
-        struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1;
-        struct cvmx_pip_prt_cfgx_cn52xx cn61xx;
-        struct cvmx_pip_prt_cfgx_cn52xx cn63xx;
-        struct cvmx_pip_prt_cfgx_cn52xx cn63xxp1;
-        struct cvmx_pip_prt_cfgx_cn52xx cn66xx;
-        struct cvmx_pip_prt_cfgx_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_55_63:9;
-                uint64_t ih_pri:1;
-                uint64_t len_chk_sel:1;
-                uint64_t pad_len:1;
-                uint64_t vlan_len:1;
-                uint64_t lenerr_en:1;
-                uint64_t maxerr_en:1;
-                uint64_t minerr_en:1;
-                uint64_t grp_wat_47:4;
-                uint64_t qos_wat_47:4;
-                uint64_t reserved_37_39:3;
-                uint64_t rawdrp:1;
-                uint64_t tag_inc:2;
-                uint64_t dyn_rs:1;
-                uint64_t inst_hdr:1;
-                uint64_t grp_wat:4;
-                uint64_t hg_qos:1;
-                uint64_t qos:3;
-                uint64_t qos_wat:4;
-                uint64_t reserved_19_19:1;
-                uint64_t qos_vod:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vlan:1;
-                uint64_t reserved_13_15:3;
-                uint64_t crc_en:1;
-                uint64_t higig_en:1;
-                uint64_t dsa_en:1;
-                uint64_t mode:2;
-                uint64_t reserved_7_7:1;
-                uint64_t skip:7;
-#else
-                uint64_t skip:7;
-                uint64_t reserved_7_7:1;
-                uint64_t mode:2;
-                uint64_t dsa_en:1;
-                uint64_t higig_en:1;
-                uint64_t crc_en:1;
-                uint64_t reserved_13_15:3;
-                uint64_t qos_vlan:1;
-                uint64_t qos_diff:1;
-                uint64_t qos_vod:1;
-                uint64_t reserved_19_19:1;
-                uint64_t qos_wat:4;
-                uint64_t qos:3;
-                uint64_t hg_qos:1;
-                uint64_t grp_wat:4;
-                uint64_t inst_hdr:1;
-                uint64_t dyn_rs:1;
-                uint64_t tag_inc:2;
-                uint64_t rawdrp:1;
-                uint64_t reserved_37_39:3;
-                uint64_t qos_wat_47:4;
-                uint64_t grp_wat_47:4;
-                uint64_t minerr_en:1;
-                uint64_t maxerr_en:1;
-                uint64_t lenerr_en:1;
-                uint64_t vlan_len:1;
-                uint64_t pad_len:1;
-                uint64_t len_chk_sel:1;
-                uint64_t ih_pri:1;
-                uint64_t reserved_55_63:9;
-#endif
-        } cn68xx;
-        struct cvmx_pip_prt_cfgx_cn68xx cn68xxp1;
-        struct cvmx_pip_prt_cfgx_cn52xx cnf71xx;
-};
-
-union cvmx_pip_prt_cfgbx {
-        uint64_t u64;
-        struct cvmx_pip_prt_cfgbx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_39_63:25;
-                uint64_t alt_skp_sel:2;
-                uint64_t alt_skp_en:1;
-                uint64_t reserved_35_35:1;
-                uint64_t bsel_num:2;
-                uint64_t bsel_en:1;
-                uint64_t reserved_24_31:8;
-                uint64_t base:8;
-                uint64_t reserved_6_15:10;
-                uint64_t bpid:6;
-#else
-                uint64_t bpid:6;
-                uint64_t reserved_6_15:10;
-                uint64_t base:8;
-                uint64_t reserved_24_31:8;
-                uint64_t bsel_en:1;
-                uint64_t bsel_num:2;
-                uint64_t reserved_35_35:1;
-                uint64_t alt_skp_en:1;
-                uint64_t alt_skp_sel:2;
-                uint64_t reserved_39_63:25;
-#endif
-        } s;
-        struct cvmx_pip_prt_cfgbx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_39_63:25;
-                uint64_t alt_skp_sel:2;
-                uint64_t alt_skp_en:1;
-                uint64_t reserved_35_35:1;
-                uint64_t bsel_num:2;
-                uint64_t bsel_en:1;
-                uint64_t reserved_0_31:32;
-#else
-                uint64_t reserved_0_31:32;
-                uint64_t bsel_en:1;
-                uint64_t bsel_num:2;
-                uint64_t reserved_35_35:1;
-                uint64_t alt_skp_en:1;
-                uint64_t alt_skp_sel:2;
-                uint64_t reserved_39_63:25;
-#endif
-        } cn61xx;
-        struct cvmx_pip_prt_cfgbx_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_39_63:25;
-                uint64_t alt_skp_sel:2;
-                uint64_t alt_skp_en:1;
-                uint64_t reserved_0_35:36;
-#else
-                uint64_t reserved_0_35:36;
-                uint64_t alt_skp_en:1;
-                uint64_t alt_skp_sel:2;
-                uint64_t reserved_39_63:25;
-#endif
-        } cn66xx;
-        struct cvmx_pip_prt_cfgbx_s cn68xx;
-        struct cvmx_pip_prt_cfgbx_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t base:8;
-                uint64_t reserved_6_15:10;
-                uint64_t bpid:6;
-#else
-                uint64_t bpid:6;
-                uint64_t reserved_6_15:10;
-                uint64_t base:8;
-                uint64_t reserved_24_63:40;
-#endif
-        } cn68xxp1;
-        struct cvmx_pip_prt_cfgbx_cn61xx cnf71xx;
-};
-
-union cvmx_pip_prt_tagx {
-        uint64_t u64;
-        struct cvmx_pip_prt_tagx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t portadd_en:1;
-                uint64_t inc_hwchk:1;
-                uint64_t reserved_50_51:2;
-                uint64_t grptagbase_msb:2;
-                uint64_t reserved_46_47:2;
-                uint64_t grptagmask_msb:2;
-                uint64_t reserved_42_43:2;
-                uint64_t grp_msb:2;
-                uint64_t grptagbase:4;
-                uint64_t grptagmask:4;
-                uint64_t grptag:1;
-                uint64_t grptag_mskip:1;
-                uint64_t tag_mode:2;
-                uint64_t inc_vs:2;
-                uint64_t inc_vlan:1;
-                uint64_t inc_prt_flag:1;
-                uint64_t ip6_dprt_flag:1;
-                uint64_t ip4_dprt_flag:1;
-                uint64_t ip6_sprt_flag:1;
-                uint64_t ip4_sprt_flag:1;
-                uint64_t ip6_nxth_flag:1;
-                uint64_t ip4_pctl_flag:1;
-                uint64_t ip6_dst_flag:1;
-                uint64_t ip4_dst_flag:1;
-                uint64_t ip6_src_flag:1;
-                uint64_t ip4_src_flag:1;
-                uint64_t tcp6_tag_type:2;
-                uint64_t tcp4_tag_type:2;
-                uint64_t ip6_tag_type:2;
-                uint64_t ip4_tag_type:2;
-                uint64_t non_tag_type:2;
-                uint64_t grp:4;
-#else
-                uint64_t grp:4;
-                uint64_t non_tag_type:2;
-                uint64_t ip4_tag_type:2;
-                uint64_t ip6_tag_type:2;
-                uint64_t tcp4_tag_type:2;
-                uint64_t tcp6_tag_type:2;
-                uint64_t ip4_src_flag:1;
-                uint64_t ip6_src_flag:1;
-                uint64_t ip4_dst_flag:1;
-                uint64_t ip6_dst_flag:1;
-                uint64_t ip4_pctl_flag:1;
-                uint64_t ip6_nxth_flag:1;
-                uint64_t ip4_sprt_flag:1;
-                uint64_t ip6_sprt_flag:1;
-                uint64_t ip4_dprt_flag:1;
-                uint64_t ip6_dprt_flag:1;
-                uint64_t inc_prt_flag:1;
-                uint64_t inc_vlan:1;
-                uint64_t inc_vs:2;
-                uint64_t tag_mode:2;
-                uint64_t grptag_mskip:1;
-                uint64_t grptag:1;
-                uint64_t grptagmask:4;
-                uint64_t grptagbase:4;
-                uint64_t grp_msb:2;
-                uint64_t reserved_42_43:2;
-                uint64_t grptagmask_msb:2;
-                uint64_t reserved_46_47:2;
-                uint64_t grptagbase_msb:2;
-                uint64_t reserved_50_51:2;
-                uint64_t inc_hwchk:1;
-                uint64_t portadd_en:1;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_pip_prt_tagx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_40_63:24;
-                uint64_t grptagbase:4;
-                uint64_t grptagmask:4;
-                uint64_t grptag:1;
-                uint64_t reserved_30_30:1;
-                uint64_t tag_mode:2;
-                uint64_t inc_vs:2;
-                uint64_t inc_vlan:1;
-                uint64_t inc_prt_flag:1;
-                uint64_t ip6_dprt_flag:1;
-                uint64_t ip4_dprt_flag:1;
-                uint64_t ip6_sprt_flag:1;
-                uint64_t ip4_sprt_flag:1;
-                uint64_t ip6_nxth_flag:1;
-                uint64_t ip4_pctl_flag:1;
-                uint64_t ip6_dst_flag:1;
-                uint64_t ip4_dst_flag:1;
-                uint64_t ip6_src_flag:1;
-                uint64_t ip4_src_flag:1;
-                uint64_t tcp6_tag_type:2;
-                uint64_t tcp4_tag_type:2;
-                uint64_t ip6_tag_type:2;
-                uint64_t ip4_tag_type:2;
-                uint64_t non_tag_type:2;
-                uint64_t grp:4;
-#else
-                uint64_t grp:4;
-                uint64_t non_tag_type:2;
-                uint64_t ip4_tag_type:2;
-                uint64_t ip6_tag_type:2;
-                uint64_t tcp4_tag_type:2;
-                uint64_t tcp6_tag_type:2;
-                uint64_t ip4_src_flag:1;
-                uint64_t ip6_src_flag:1;
-                uint64_t ip4_dst_flag:1;
-                uint64_t ip6_dst_flag:1;
-                uint64_t ip4_pctl_flag:1;
-                uint64_t ip6_nxth_flag:1;
-                uint64_t ip4_sprt_flag:1;
-                uint64_t ip6_sprt_flag:1;
-                uint64_t ip4_dprt_flag:1;
-                uint64_t ip6_dprt_flag:1;
-                uint64_t inc_prt_flag:1;
-                uint64_t inc_vlan:1;
-                uint64_t inc_vs:2;
-                uint64_t tag_mode:2;
-                uint64_t reserved_30_30:1;
-                uint64_t grptag:1;
-                uint64_t grptagmask:4;
-                uint64_t grptagbase:4;
-                uint64_t reserved_40_63:24;
-#endif
-        } cn30xx;
-        struct cvmx_pip_prt_tagx_cn30xx cn31xx;
-        struct cvmx_pip_prt_tagx_cn30xx cn38xx;
-        struct cvmx_pip_prt_tagx_cn30xx cn38xxp2;
-        struct cvmx_pip_prt_tagx_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_40_63:24;
-                uint64_t grptagbase:4;
-                uint64_t grptagmask:4;
-                uint64_t grptag:1;
-                uint64_t grptag_mskip:1;
-                uint64_t tag_mode:2;
-                uint64_t inc_vs:2;
-                uint64_t inc_vlan:1;
-                uint64_t inc_prt_flag:1;
-                uint64_t ip6_dprt_flag:1;
-                uint64_t ip4_dprt_flag:1;
-                uint64_t ip6_sprt_flag:1;
-                uint64_t ip4_sprt_flag:1;
-                uint64_t ip6_nxth_flag:1;
-                uint64_t ip4_pctl_flag:1;
-                uint64_t ip6_dst_flag:1;
-                uint64_t ip4_dst_flag:1;
-                uint64_t ip6_src_flag:1;
-                uint64_t ip4_src_flag:1;
-                uint64_t tcp6_tag_type:2;
-                uint64_t tcp4_tag_type:2;
-                uint64_t ip6_tag_type:2;
-                uint64_t ip4_tag_type:2;
-                uint64_t non_tag_type:2;
-                uint64_t grp:4;
-#else
-                uint64_t grp:4;
-                uint64_t non_tag_type:2;
-                uint64_t ip4_tag_type:2;
-                uint64_t ip6_tag_type:2;
-                uint64_t tcp4_tag_type:2;
-                uint64_t tcp6_tag_type:2;
-                uint64_t ip4_src_flag:1;
-                uint64_t ip6_src_flag:1;
-                uint64_t ip4_dst_flag:1;
-                uint64_t ip6_dst_flag:1;
-                uint64_t ip4_pctl_flag:1;
-                uint64_t ip6_nxth_flag:1;
-                uint64_t ip4_sprt_flag:1;
-                uint64_t ip6_sprt_flag:1;
-                uint64_t ip4_dprt_flag:1;
-                uint64_t ip6_dprt_flag:1;
-                uint64_t inc_prt_flag:1;
-                uint64_t inc_vlan:1;
-                uint64_t inc_vs:2;
-                uint64_t tag_mode:2;
-                uint64_t grptag_mskip:1;
-                uint64_t grptag:1;
-                uint64_t grptagmask:4;
-                uint64_t grptagbase:4;
-                uint64_t reserved_40_63:24;
-#endif
-        } cn50xx;
-        struct cvmx_pip_prt_tagx_cn50xx cn52xx;
-        struct cvmx_pip_prt_tagx_cn50xx cn52xxp1;
-        struct cvmx_pip_prt_tagx_cn50xx cn56xx;
-        struct cvmx_pip_prt_tagx_cn50xx cn56xxp1;
-        struct cvmx_pip_prt_tagx_cn30xx cn58xx;
-        struct cvmx_pip_prt_tagx_cn30xx cn58xxp1;
-        struct cvmx_pip_prt_tagx_cn50xx cn61xx;
-        struct cvmx_pip_prt_tagx_cn50xx cn63xx;
-        struct cvmx_pip_prt_tagx_cn50xx cn63xxp1;
-        struct cvmx_pip_prt_tagx_cn50xx cn66xx;
-        struct cvmx_pip_prt_tagx_s cn68xx;
-        struct cvmx_pip_prt_tagx_s cn68xxp1;
-        struct cvmx_pip_prt_tagx_cn50xx cnf71xx;
-};
-
-union cvmx_pip_qos_diffx {
-        uint64_t u64;
-        struct cvmx_pip_qos_diffx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_pip_qos_diffx_s cn30xx;
-        struct cvmx_pip_qos_diffx_s cn31xx;
-        struct cvmx_pip_qos_diffx_s cn38xx;
-        struct cvmx_pip_qos_diffx_s cn38xxp2;
-        struct cvmx_pip_qos_diffx_s cn50xx;
-        struct cvmx_pip_qos_diffx_s cn52xx;
-        struct cvmx_pip_qos_diffx_s cn52xxp1;
-        struct cvmx_pip_qos_diffx_s cn56xx;
-        struct cvmx_pip_qos_diffx_s cn56xxp1;
-        struct cvmx_pip_qos_diffx_s cn58xx;
-        struct cvmx_pip_qos_diffx_s cn58xxp1;
-        struct cvmx_pip_qos_diffx_s cn61xx;
-        struct cvmx_pip_qos_diffx_s cn63xx;
-        struct cvmx_pip_qos_diffx_s cn63xxp1;
-        struct cvmx_pip_qos_diffx_s cn66xx;
-        struct cvmx_pip_qos_diffx_s cnf71xx;
-};
-
-union cvmx_pip_qos_vlanx {
-        uint64_t u64;
-        struct cvmx_pip_qos_vlanx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t qos1:3;
-                uint64_t reserved_3_3:1;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t reserved_3_3:1;
-                uint64_t qos1:3;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_pip_qos_vlanx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn30xx;
-        struct cvmx_pip_qos_vlanx_cn30xx cn31xx;
-        struct cvmx_pip_qos_vlanx_cn30xx cn38xx;
-        struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2;
-        struct cvmx_pip_qos_vlanx_cn30xx cn50xx;
-        struct cvmx_pip_qos_vlanx_s cn52xx;
-        struct cvmx_pip_qos_vlanx_s cn52xxp1;
-        struct cvmx_pip_qos_vlanx_s cn56xx;
-        struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1;
-        struct cvmx_pip_qos_vlanx_cn30xx cn58xx;
-        struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1;
-        struct cvmx_pip_qos_vlanx_s cn61xx;
-        struct cvmx_pip_qos_vlanx_s cn63xx;
-        struct cvmx_pip_qos_vlanx_s cn63xxp1;
-        struct cvmx_pip_qos_vlanx_s cn66xx;
-        struct cvmx_pip_qos_vlanx_s cnf71xx;
-};
-
-union cvmx_pip_qos_watchx {
-        uint64_t u64;
-        struct cvmx_pip_qos_watchx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t mask:16;
-                uint64_t reserved_30_31:2;
-                uint64_t grp:6;
-                uint64_t reserved_23_23:1;
-                uint64_t qos:3;
-                uint64_t reserved_19_19:1;
-                uint64_t match_type:3;
-                uint64_t match_value:16;
-#else
-                uint64_t match_value:16;
-                uint64_t match_type:3;
-                uint64_t reserved_19_19:1;
-                uint64_t qos:3;
-                uint64_t reserved_23_23:1;
-                uint64_t grp:6;
-                uint64_t reserved_30_31:2;
-                uint64_t mask:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_pip_qos_watchx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t mask:16;
-                uint64_t reserved_28_31:4;
-                uint64_t grp:4;
-                uint64_t reserved_23_23:1;
-                uint64_t qos:3;
-                uint64_t reserved_18_19:2;
-                uint64_t match_type:2;
-                uint64_t match_value:16;
-#else
-                uint64_t match_value:16;
-                uint64_t match_type:2;
-                uint64_t reserved_18_19:2;
-                uint64_t qos:3;
-                uint64_t reserved_23_23:1;
-                uint64_t grp:4;
-                uint64_t reserved_28_31:4;
-                uint64_t mask:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } cn30xx;
-        struct cvmx_pip_qos_watchx_cn30xx cn31xx;
-        struct cvmx_pip_qos_watchx_cn30xx cn38xx;
-        struct cvmx_pip_qos_watchx_cn30xx cn38xxp2;
-        struct cvmx_pip_qos_watchx_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t mask:16;
-                uint64_t reserved_28_31:4;
-                uint64_t grp:4;
-                uint64_t reserved_23_23:1;
-                uint64_t qos:3;
-                uint64_t reserved_19_19:1;
-                uint64_t match_type:3;
-                uint64_t match_value:16;
-#else
-                uint64_t match_value:16;
-                uint64_t match_type:3;
-                uint64_t reserved_19_19:1;
-                uint64_t qos:3;
-                uint64_t reserved_23_23:1;
-                uint64_t grp:4;
-                uint64_t reserved_28_31:4;
-                uint64_t mask:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } cn50xx;
-        struct cvmx_pip_qos_watchx_cn50xx cn52xx;
-        struct cvmx_pip_qos_watchx_cn50xx cn52xxp1;
-        struct cvmx_pip_qos_watchx_cn50xx cn56xx;
-        struct cvmx_pip_qos_watchx_cn50xx cn56xxp1;
-        struct cvmx_pip_qos_watchx_cn30xx cn58xx;
-        struct cvmx_pip_qos_watchx_cn30xx cn58xxp1;
-        struct cvmx_pip_qos_watchx_cn50xx cn61xx;
-        struct cvmx_pip_qos_watchx_cn50xx cn63xx;
-        struct cvmx_pip_qos_watchx_cn50xx cn63xxp1;
-        struct cvmx_pip_qos_watchx_cn50xx cn66xx;
-        struct cvmx_pip_qos_watchx_s cn68xx;
-        struct cvmx_pip_qos_watchx_s cn68xxp1;
-        struct cvmx_pip_qos_watchx_cn50xx cnf71xx;
-};
-
-union cvmx_pip_raw_word {
-        uint64_t u64;
-        struct cvmx_pip_raw_word_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t word:56;
-#else
-                uint64_t word:56;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_pip_raw_word_s cn30xx;
-        struct cvmx_pip_raw_word_s cn31xx;
-        struct cvmx_pip_raw_word_s cn38xx;
-        struct cvmx_pip_raw_word_s cn38xxp2;
-        struct cvmx_pip_raw_word_s cn50xx;
-        struct cvmx_pip_raw_word_s cn52xx;
-        struct cvmx_pip_raw_word_s cn52xxp1;
-        struct cvmx_pip_raw_word_s cn56xx;
-        struct cvmx_pip_raw_word_s cn56xxp1;
-        struct cvmx_pip_raw_word_s cn58xx;
-        struct cvmx_pip_raw_word_s cn58xxp1;
-        struct cvmx_pip_raw_word_s cn61xx;
-        struct cvmx_pip_raw_word_s cn63xx;
-        struct cvmx_pip_raw_word_s cn63xxp1;
-        struct cvmx_pip_raw_word_s cn66xx;
-        struct cvmx_pip_raw_word_s cn68xx;
-        struct cvmx_pip_raw_word_s cn68xxp1;
-        struct cvmx_pip_raw_word_s cnf71xx;
-};
-
-union cvmx_pip_sft_rst {
-        uint64_t u64;
-        struct cvmx_pip_sft_rst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t rst:1;
-#else
-                uint64_t rst:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_pip_sft_rst_s cn30xx;
-        struct cvmx_pip_sft_rst_s cn31xx;
-        struct cvmx_pip_sft_rst_s cn38xx;
-        struct cvmx_pip_sft_rst_s cn50xx;
-        struct cvmx_pip_sft_rst_s cn52xx;
-        struct cvmx_pip_sft_rst_s cn52xxp1;
-        struct cvmx_pip_sft_rst_s cn56xx;
-        struct cvmx_pip_sft_rst_s cn56xxp1;
-        struct cvmx_pip_sft_rst_s cn58xx;
-        struct cvmx_pip_sft_rst_s cn58xxp1;
-        struct cvmx_pip_sft_rst_s cn61xx;
-        struct cvmx_pip_sft_rst_s cn63xx;
-        struct cvmx_pip_sft_rst_s cn63xxp1;
-        struct cvmx_pip_sft_rst_s cn66xx;
-        struct cvmx_pip_sft_rst_s cn68xx;
-        struct cvmx_pip_sft_rst_s cn68xxp1;
-        struct cvmx_pip_sft_rst_s cnf71xx;
-};
-
-union cvmx_pip_stat0_x {
-        uint64_t u64;
-        struct cvmx_pip_stat0_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t drp_pkts:32;
-                uint64_t drp_octs:32;
-#else
-                uint64_t drp_octs:32;
-                uint64_t drp_pkts:32;
-#endif
-        } s;
-        struct cvmx_pip_stat0_x_s cn68xx;
-        struct cvmx_pip_stat0_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat0_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat0_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t drp_pkts:32;
-                uint64_t drp_octs:32;
-#else
-                uint64_t drp_octs:32;
-                uint64_t drp_pkts:32;
-#endif
-        } s;
-        struct cvmx_pip_stat0_prtx_s cn30xx;
-        struct cvmx_pip_stat0_prtx_s cn31xx;
-        struct cvmx_pip_stat0_prtx_s cn38xx;
-        struct cvmx_pip_stat0_prtx_s cn38xxp2;
-        struct cvmx_pip_stat0_prtx_s cn50xx;
-        struct cvmx_pip_stat0_prtx_s cn52xx;
-        struct cvmx_pip_stat0_prtx_s cn52xxp1;
-        struct cvmx_pip_stat0_prtx_s cn56xx;
-        struct cvmx_pip_stat0_prtx_s cn56xxp1;
-        struct cvmx_pip_stat0_prtx_s cn58xx;
-        struct cvmx_pip_stat0_prtx_s cn58xxp1;
-        struct cvmx_pip_stat0_prtx_s cn61xx;
-        struct cvmx_pip_stat0_prtx_s cn63xx;
-        struct cvmx_pip_stat0_prtx_s cn63xxp1;
-        struct cvmx_pip_stat0_prtx_s cn66xx;
-        struct cvmx_pip_stat0_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat10_x {
-        uint64_t u64;
-        struct cvmx_pip_stat10_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bcast:32;
-                uint64_t mcast:32;
-#else
-                uint64_t mcast:32;
-                uint64_t bcast:32;
-#endif
-        } s;
-        struct cvmx_pip_stat10_x_s cn68xx;
-        struct cvmx_pip_stat10_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat10_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat10_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bcast:32;
-                uint64_t mcast:32;
-#else
-                uint64_t mcast:32;
-                uint64_t bcast:32;
-#endif
-        } s;
-        struct cvmx_pip_stat10_prtx_s cn52xx;
-        struct cvmx_pip_stat10_prtx_s cn52xxp1;
-        struct cvmx_pip_stat10_prtx_s cn56xx;
-        struct cvmx_pip_stat10_prtx_s cn56xxp1;
-        struct cvmx_pip_stat10_prtx_s cn61xx;
-        struct cvmx_pip_stat10_prtx_s cn63xx;
-        struct cvmx_pip_stat10_prtx_s cn63xxp1;
-        struct cvmx_pip_stat10_prtx_s cn66xx;
-        struct cvmx_pip_stat10_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat11_x {
-        uint64_t u64;
-        struct cvmx_pip_stat11_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bcast:32;
-                uint64_t mcast:32;
-#else
-                uint64_t mcast:32;
-                uint64_t bcast:32;
-#endif
-        } s;
-        struct cvmx_pip_stat11_x_s cn68xx;
-        struct cvmx_pip_stat11_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat11_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat11_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bcast:32;
-                uint64_t mcast:32;
-#else
-                uint64_t mcast:32;
-                uint64_t bcast:32;
-#endif
-        } s;
-        struct cvmx_pip_stat11_prtx_s cn52xx;
-        struct cvmx_pip_stat11_prtx_s cn52xxp1;
-        struct cvmx_pip_stat11_prtx_s cn56xx;
-        struct cvmx_pip_stat11_prtx_s cn56xxp1;
-        struct cvmx_pip_stat11_prtx_s cn61xx;
-        struct cvmx_pip_stat11_prtx_s cn63xx;
-        struct cvmx_pip_stat11_prtx_s cn63xxp1;
-        struct cvmx_pip_stat11_prtx_s cn66xx;
-        struct cvmx_pip_stat11_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat1_x {
-        uint64_t u64;
-        struct cvmx_pip_stat1_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t octs:48;
-#else
-                uint64_t octs:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_pip_stat1_x_s cn68xx;
-        struct cvmx_pip_stat1_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat1_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat1_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t octs:48;
-#else
-                uint64_t octs:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_pip_stat1_prtx_s cn30xx;
-        struct cvmx_pip_stat1_prtx_s cn31xx;
-        struct cvmx_pip_stat1_prtx_s cn38xx;
-        struct cvmx_pip_stat1_prtx_s cn38xxp2;
-        struct cvmx_pip_stat1_prtx_s cn50xx;
-        struct cvmx_pip_stat1_prtx_s cn52xx;
-        struct cvmx_pip_stat1_prtx_s cn52xxp1;
-        struct cvmx_pip_stat1_prtx_s cn56xx;
-        struct cvmx_pip_stat1_prtx_s cn56xxp1;
-        struct cvmx_pip_stat1_prtx_s cn58xx;
-        struct cvmx_pip_stat1_prtx_s cn58xxp1;
-        struct cvmx_pip_stat1_prtx_s cn61xx;
-        struct cvmx_pip_stat1_prtx_s cn63xx;
-        struct cvmx_pip_stat1_prtx_s cn63xxp1;
-        struct cvmx_pip_stat1_prtx_s cn66xx;
-        struct cvmx_pip_stat1_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat2_x {
-        uint64_t u64;
-        struct cvmx_pip_stat2_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t pkts:32;
-                uint64_t raw:32;
-#else
-                uint64_t raw:32;
-                uint64_t pkts:32;
-#endif
-        } s;
-        struct cvmx_pip_stat2_x_s cn68xx;
-        struct cvmx_pip_stat2_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat2_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat2_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t pkts:32;
-                uint64_t raw:32;
-#else
-                uint64_t raw:32;
-                uint64_t pkts:32;
-#endif
-        } s;
-        struct cvmx_pip_stat2_prtx_s cn30xx;
-        struct cvmx_pip_stat2_prtx_s cn31xx;
-        struct cvmx_pip_stat2_prtx_s cn38xx;
-        struct cvmx_pip_stat2_prtx_s cn38xxp2;
-        struct cvmx_pip_stat2_prtx_s cn50xx;
-        struct cvmx_pip_stat2_prtx_s cn52xx;
-        struct cvmx_pip_stat2_prtx_s cn52xxp1;
-        struct cvmx_pip_stat2_prtx_s cn56xx;
-        struct cvmx_pip_stat2_prtx_s cn56xxp1;
-        struct cvmx_pip_stat2_prtx_s cn58xx;
-        struct cvmx_pip_stat2_prtx_s cn58xxp1;
-        struct cvmx_pip_stat2_prtx_s cn61xx;
-        struct cvmx_pip_stat2_prtx_s cn63xx;
-        struct cvmx_pip_stat2_prtx_s cn63xxp1;
-        struct cvmx_pip_stat2_prtx_s cn66xx;
-        struct cvmx_pip_stat2_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat3_x {
-        uint64_t u64;
-        struct cvmx_pip_stat3_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bcst:32;
-                uint64_t mcst:32;
-#else
-                uint64_t mcst:32;
-                uint64_t bcst:32;
-#endif
-        } s;
-        struct cvmx_pip_stat3_x_s cn68xx;
-        struct cvmx_pip_stat3_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat3_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat3_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bcst:32;
-                uint64_t mcst:32;
-#else
-                uint64_t mcst:32;
-                uint64_t bcst:32;
-#endif
-        } s;
-        struct cvmx_pip_stat3_prtx_s cn30xx;
-        struct cvmx_pip_stat3_prtx_s cn31xx;
-        struct cvmx_pip_stat3_prtx_s cn38xx;
-        struct cvmx_pip_stat3_prtx_s cn38xxp2;
-        struct cvmx_pip_stat3_prtx_s cn50xx;
-        struct cvmx_pip_stat3_prtx_s cn52xx;
-        struct cvmx_pip_stat3_prtx_s cn52xxp1;
-        struct cvmx_pip_stat3_prtx_s cn56xx;
-        struct cvmx_pip_stat3_prtx_s cn56xxp1;
-        struct cvmx_pip_stat3_prtx_s cn58xx;
-        struct cvmx_pip_stat3_prtx_s cn58xxp1;
-        struct cvmx_pip_stat3_prtx_s cn61xx;
-        struct cvmx_pip_stat3_prtx_s cn63xx;
-        struct cvmx_pip_stat3_prtx_s cn63xxp1;
-        struct cvmx_pip_stat3_prtx_s cn66xx;
-        struct cvmx_pip_stat3_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat4_x {
-        uint64_t u64;
-        struct cvmx_pip_stat4_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t h65to127:32;
-                uint64_t h64:32;
-#else
-                uint64_t h64:32;
-                uint64_t h65to127:32;
-#endif
-        } s;
-        struct cvmx_pip_stat4_x_s cn68xx;
-        struct cvmx_pip_stat4_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat4_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat4_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t h65to127:32;
-                uint64_t h64:32;
-#else
-                uint64_t h64:32;
-                uint64_t h65to127:32;
-#endif
-        } s;
-        struct cvmx_pip_stat4_prtx_s cn30xx;
-        struct cvmx_pip_stat4_prtx_s cn31xx;
-        struct cvmx_pip_stat4_prtx_s cn38xx;
-        struct cvmx_pip_stat4_prtx_s cn38xxp2;
-        struct cvmx_pip_stat4_prtx_s cn50xx;
-        struct cvmx_pip_stat4_prtx_s cn52xx;
-        struct cvmx_pip_stat4_prtx_s cn52xxp1;
-        struct cvmx_pip_stat4_prtx_s cn56xx;
-        struct cvmx_pip_stat4_prtx_s cn56xxp1;
-        struct cvmx_pip_stat4_prtx_s cn58xx;
-        struct cvmx_pip_stat4_prtx_s cn58xxp1;
-        struct cvmx_pip_stat4_prtx_s cn61xx;
-        struct cvmx_pip_stat4_prtx_s cn63xx;
-        struct cvmx_pip_stat4_prtx_s cn63xxp1;
-        struct cvmx_pip_stat4_prtx_s cn66xx;
-        struct cvmx_pip_stat4_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat5_x {
-        uint64_t u64;
-        struct cvmx_pip_stat5_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t h256to511:32;
-                uint64_t h128to255:32;
-#else
-                uint64_t h128to255:32;
-                uint64_t h256to511:32;
-#endif
-        } s;
-        struct cvmx_pip_stat5_x_s cn68xx;
-        struct cvmx_pip_stat5_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat5_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat5_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t h256to511:32;
-                uint64_t h128to255:32;
-#else
-                uint64_t h128to255:32;
-                uint64_t h256to511:32;
-#endif
-        } s;
-        struct cvmx_pip_stat5_prtx_s cn30xx;
-        struct cvmx_pip_stat5_prtx_s cn31xx;
-        struct cvmx_pip_stat5_prtx_s cn38xx;
-        struct cvmx_pip_stat5_prtx_s cn38xxp2;
-        struct cvmx_pip_stat5_prtx_s cn50xx;
-        struct cvmx_pip_stat5_prtx_s cn52xx;
-        struct cvmx_pip_stat5_prtx_s cn52xxp1;
-        struct cvmx_pip_stat5_prtx_s cn56xx;
-        struct cvmx_pip_stat5_prtx_s cn56xxp1;
-        struct cvmx_pip_stat5_prtx_s cn58xx;
-        struct cvmx_pip_stat5_prtx_s cn58xxp1;
-        struct cvmx_pip_stat5_prtx_s cn61xx;
-        struct cvmx_pip_stat5_prtx_s cn63xx;
-        struct cvmx_pip_stat5_prtx_s cn63xxp1;
-        struct cvmx_pip_stat5_prtx_s cn66xx;
-        struct cvmx_pip_stat5_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat6_x {
-        uint64_t u64;
-        struct cvmx_pip_stat6_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t h1024to1518:32;
-                uint64_t h512to1023:32;
-#else
-                uint64_t h512to1023:32;
-                uint64_t h1024to1518:32;
-#endif
-        } s;
-        struct cvmx_pip_stat6_x_s cn68xx;
-        struct cvmx_pip_stat6_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat6_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat6_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t h1024to1518:32;
-                uint64_t h512to1023:32;
-#else
-                uint64_t h512to1023:32;
-                uint64_t h1024to1518:32;
-#endif
-        } s;
-        struct cvmx_pip_stat6_prtx_s cn30xx;
-        struct cvmx_pip_stat6_prtx_s cn31xx;
-        struct cvmx_pip_stat6_prtx_s cn38xx;
-        struct cvmx_pip_stat6_prtx_s cn38xxp2;
-        struct cvmx_pip_stat6_prtx_s cn50xx;
-        struct cvmx_pip_stat6_prtx_s cn52xx;
-        struct cvmx_pip_stat6_prtx_s cn52xxp1;
-        struct cvmx_pip_stat6_prtx_s cn56xx;
-        struct cvmx_pip_stat6_prtx_s cn56xxp1;
-        struct cvmx_pip_stat6_prtx_s cn58xx;
-        struct cvmx_pip_stat6_prtx_s cn58xxp1;
-        struct cvmx_pip_stat6_prtx_s cn61xx;
-        struct cvmx_pip_stat6_prtx_s cn63xx;
-        struct cvmx_pip_stat6_prtx_s cn63xxp1;
-        struct cvmx_pip_stat6_prtx_s cn66xx;
-        struct cvmx_pip_stat6_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat7_x {
-        uint64_t u64;
-        struct cvmx_pip_stat7_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t fcs:32;
-                uint64_t h1519:32;
-#else
-                uint64_t h1519:32;
-                uint64_t fcs:32;
-#endif
-        } s;
-        struct cvmx_pip_stat7_x_s cn68xx;
-        struct cvmx_pip_stat7_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat7_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat7_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t fcs:32;
-                uint64_t h1519:32;
-#else
-                uint64_t h1519:32;
-                uint64_t fcs:32;
-#endif
-        } s;
-        struct cvmx_pip_stat7_prtx_s cn30xx;
-        struct cvmx_pip_stat7_prtx_s cn31xx;
-        struct cvmx_pip_stat7_prtx_s cn38xx;
-        struct cvmx_pip_stat7_prtx_s cn38xxp2;
-        struct cvmx_pip_stat7_prtx_s cn50xx;
-        struct cvmx_pip_stat7_prtx_s cn52xx;
-        struct cvmx_pip_stat7_prtx_s cn52xxp1;
-        struct cvmx_pip_stat7_prtx_s cn56xx;
-        struct cvmx_pip_stat7_prtx_s cn56xxp1;
-        struct cvmx_pip_stat7_prtx_s cn58xx;
-        struct cvmx_pip_stat7_prtx_s cn58xxp1;
-        struct cvmx_pip_stat7_prtx_s cn61xx;
-        struct cvmx_pip_stat7_prtx_s cn63xx;
-        struct cvmx_pip_stat7_prtx_s cn63xxp1;
-        struct cvmx_pip_stat7_prtx_s cn66xx;
-        struct cvmx_pip_stat7_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat8_x {
-        uint64_t u64;
-        struct cvmx_pip_stat8_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t frag:32;
-                uint64_t undersz:32;
-#else
-                uint64_t undersz:32;
-                uint64_t frag:32;
-#endif
-        } s;
-        struct cvmx_pip_stat8_x_s cn68xx;
-        struct cvmx_pip_stat8_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat8_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat8_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t frag:32;
-                uint64_t undersz:32;
-#else
-                uint64_t undersz:32;
-                uint64_t frag:32;
-#endif
-        } s;
-        struct cvmx_pip_stat8_prtx_s cn30xx;
-        struct cvmx_pip_stat8_prtx_s cn31xx;
-        struct cvmx_pip_stat8_prtx_s cn38xx;
-        struct cvmx_pip_stat8_prtx_s cn38xxp2;
-        struct cvmx_pip_stat8_prtx_s cn50xx;
-        struct cvmx_pip_stat8_prtx_s cn52xx;
-        struct cvmx_pip_stat8_prtx_s cn52xxp1;
-        struct cvmx_pip_stat8_prtx_s cn56xx;
-        struct cvmx_pip_stat8_prtx_s cn56xxp1;
-        struct cvmx_pip_stat8_prtx_s cn58xx;
-        struct cvmx_pip_stat8_prtx_s cn58xxp1;
-        struct cvmx_pip_stat8_prtx_s cn61xx;
-        struct cvmx_pip_stat8_prtx_s cn63xx;
-        struct cvmx_pip_stat8_prtx_s cn63xxp1;
-        struct cvmx_pip_stat8_prtx_s cn66xx;
-        struct cvmx_pip_stat8_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat9_x {
-        uint64_t u64;
-        struct cvmx_pip_stat9_x_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t jabber:32;
-                uint64_t oversz:32;
-#else
-                uint64_t oversz:32;
-                uint64_t jabber:32;
-#endif
-        } s;
-        struct cvmx_pip_stat9_x_s cn68xx;
-        struct cvmx_pip_stat9_x_s cn68xxp1;
-};
-
-union cvmx_pip_stat9_prtx {
-        uint64_t u64;
-        struct cvmx_pip_stat9_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t jabber:32;
-                uint64_t oversz:32;
-#else
-                uint64_t oversz:32;
-                uint64_t jabber:32;
-#endif
-        } s;
-        struct cvmx_pip_stat9_prtx_s cn30xx;
-        struct cvmx_pip_stat9_prtx_s cn31xx;
-        struct cvmx_pip_stat9_prtx_s cn38xx;
-        struct cvmx_pip_stat9_prtx_s cn38xxp2;
-        struct cvmx_pip_stat9_prtx_s cn50xx;
-        struct cvmx_pip_stat9_prtx_s cn52xx;
-        struct cvmx_pip_stat9_prtx_s cn52xxp1;
-        struct cvmx_pip_stat9_prtx_s cn56xx;
-        struct cvmx_pip_stat9_prtx_s cn56xxp1;
-        struct cvmx_pip_stat9_prtx_s cn58xx;
-        struct cvmx_pip_stat9_prtx_s cn58xxp1;
-        struct cvmx_pip_stat9_prtx_s cn61xx;
-        struct cvmx_pip_stat9_prtx_s cn63xx;
-        struct cvmx_pip_stat9_prtx_s cn63xxp1;
-        struct cvmx_pip_stat9_prtx_s cn66xx;
-        struct cvmx_pip_stat9_prtx_s cnf71xx;
-};
-
-union cvmx_pip_stat_ctl {
-        uint64_t u64;
-        struct cvmx_pip_stat_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t mode:1;
-                uint64_t reserved_1_7:7;
-                uint64_t rdclr:1;
-#else
-                uint64_t rdclr:1;
-                uint64_t reserved_1_7:7;
-                uint64_t mode:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_pip_stat_ctl_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t rdclr:1;
-#else
-                uint64_t rdclr:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } cn30xx;
-        struct cvmx_pip_stat_ctl_cn30xx cn31xx;
-        struct cvmx_pip_stat_ctl_cn30xx cn38xx;
-        struct cvmx_pip_stat_ctl_cn30xx cn38xxp2;
-        struct cvmx_pip_stat_ctl_cn30xx cn50xx;
-        struct cvmx_pip_stat_ctl_cn30xx cn52xx;
-        struct cvmx_pip_stat_ctl_cn30xx cn52xxp1;
-        struct cvmx_pip_stat_ctl_cn30xx cn56xx;
-        struct cvmx_pip_stat_ctl_cn30xx cn56xxp1;
-        struct cvmx_pip_stat_ctl_cn30xx cn58xx;
-        struct cvmx_pip_stat_ctl_cn30xx cn58xxp1;
-        struct cvmx_pip_stat_ctl_cn30xx cn61xx;
-        struct cvmx_pip_stat_ctl_cn30xx cn63xx;
-        struct cvmx_pip_stat_ctl_cn30xx cn63xxp1;
-        struct cvmx_pip_stat_ctl_cn30xx cn66xx;
-        struct cvmx_pip_stat_ctl_s cn68xx;
-        struct cvmx_pip_stat_ctl_s cn68xxp1;
-        struct cvmx_pip_stat_ctl_cn30xx cnf71xx;
-};
-
-union cvmx_pip_stat_inb_errsx {
-        uint64_t u64;
-        struct cvmx_pip_stat_inb_errsx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t errs:16;
-#else
-                uint64_t errs:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pip_stat_inb_errsx_s cn30xx;
-        struct cvmx_pip_stat_inb_errsx_s cn31xx;
-        struct cvmx_pip_stat_inb_errsx_s cn38xx;
-        struct cvmx_pip_stat_inb_errsx_s cn38xxp2;
-        struct cvmx_pip_stat_inb_errsx_s cn50xx;
-        struct cvmx_pip_stat_inb_errsx_s cn52xx;
-        struct cvmx_pip_stat_inb_errsx_s cn52xxp1;
-        struct cvmx_pip_stat_inb_errsx_s cn56xx;
-        struct cvmx_pip_stat_inb_errsx_s cn56xxp1;
-        struct cvmx_pip_stat_inb_errsx_s cn58xx;
-        struct cvmx_pip_stat_inb_errsx_s cn58xxp1;
-        struct cvmx_pip_stat_inb_errsx_s cn61xx;
-        struct cvmx_pip_stat_inb_errsx_s cn63xx;
-        struct cvmx_pip_stat_inb_errsx_s cn63xxp1;
-        struct cvmx_pip_stat_inb_errsx_s cn66xx;
-        struct cvmx_pip_stat_inb_errsx_s cnf71xx;
-};
-
-union cvmx_pip_stat_inb_errs_pkndx {
-        uint64_t u64;
-        struct cvmx_pip_stat_inb_errs_pkndx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t errs:16;
-#else
-                uint64_t errs:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pip_stat_inb_errs_pkndx_s cn68xx;
-        struct cvmx_pip_stat_inb_errs_pkndx_s cn68xxp1;
-};
-
-union cvmx_pip_stat_inb_octsx {
-        uint64_t u64;
-        struct cvmx_pip_stat_inb_octsx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t octs:48;
-#else
-                uint64_t octs:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_pip_stat_inb_octsx_s cn30xx;
-        struct cvmx_pip_stat_inb_octsx_s cn31xx;
-        struct cvmx_pip_stat_inb_octsx_s cn38xx;
-        struct cvmx_pip_stat_inb_octsx_s cn38xxp2;
-        struct cvmx_pip_stat_inb_octsx_s cn50xx;
-        struct cvmx_pip_stat_inb_octsx_s cn52xx;
-        struct cvmx_pip_stat_inb_octsx_s cn52xxp1;
-        struct cvmx_pip_stat_inb_octsx_s cn56xx;
-        struct cvmx_pip_stat_inb_octsx_s cn56xxp1;
-        struct cvmx_pip_stat_inb_octsx_s cn58xx;
-        struct cvmx_pip_stat_inb_octsx_s cn58xxp1;
-        struct cvmx_pip_stat_inb_octsx_s cn61xx;
-        struct cvmx_pip_stat_inb_octsx_s cn63xx;
-        struct cvmx_pip_stat_inb_octsx_s cn63xxp1;
-        struct cvmx_pip_stat_inb_octsx_s cn66xx;
-        struct cvmx_pip_stat_inb_octsx_s cnf71xx;
-};
-
-union cvmx_pip_stat_inb_octs_pkndx {
-        uint64_t u64;
-        struct cvmx_pip_stat_inb_octs_pkndx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t octs:48;
-#else
-                uint64_t octs:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_pip_stat_inb_octs_pkndx_s cn68xx;
-        struct cvmx_pip_stat_inb_octs_pkndx_s cn68xxp1;
-};
-
-union cvmx_pip_stat_inb_pktsx {
-        uint64_t u64;
-        struct cvmx_pip_stat_inb_pktsx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t pkts:32;
-#else
-                uint64_t pkts:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pip_stat_inb_pktsx_s cn30xx;
-        struct cvmx_pip_stat_inb_pktsx_s cn31xx;
-        struct cvmx_pip_stat_inb_pktsx_s cn38xx;
-        struct cvmx_pip_stat_inb_pktsx_s cn38xxp2;
-        struct cvmx_pip_stat_inb_pktsx_s cn50xx;
-        struct cvmx_pip_stat_inb_pktsx_s cn52xx;
-        struct cvmx_pip_stat_inb_pktsx_s cn52xxp1;
-        struct cvmx_pip_stat_inb_pktsx_s cn56xx;
-        struct cvmx_pip_stat_inb_pktsx_s cn56xxp1;
-        struct cvmx_pip_stat_inb_pktsx_s cn58xx;
-        struct cvmx_pip_stat_inb_pktsx_s cn58xxp1;
-        struct cvmx_pip_stat_inb_pktsx_s cn61xx;
-        struct cvmx_pip_stat_inb_pktsx_s cn63xx;
-        struct cvmx_pip_stat_inb_pktsx_s cn63xxp1;
-        struct cvmx_pip_stat_inb_pktsx_s cn66xx;
-        struct cvmx_pip_stat_inb_pktsx_s cnf71xx;
-};
-
-union cvmx_pip_stat_inb_pkts_pkndx {
-        uint64_t u64;
-        struct cvmx_pip_stat_inb_pkts_pkndx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t pkts:32;
-#else
-                uint64_t pkts:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xx;
-        struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xxp1;
-};
-
-union cvmx_pip_sub_pkind_fcsx {
-        uint64_t u64;
-        struct cvmx_pip_sub_pkind_fcsx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t port_bit:64;
-#else
-                uint64_t port_bit:64;
-#endif
-        } s;
-        struct cvmx_pip_sub_pkind_fcsx_s cn68xx;
-        struct cvmx_pip_sub_pkind_fcsx_s cn68xxp1;
-};
-
-union cvmx_pip_tag_incx {
-        uint64_t u64;
-        struct cvmx_pip_tag_incx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t en:8;
-#else
-                uint64_t en:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_pip_tag_incx_s cn30xx;
-        struct cvmx_pip_tag_incx_s cn31xx;
-        struct cvmx_pip_tag_incx_s cn38xx;
-        struct cvmx_pip_tag_incx_s cn38xxp2;
-        struct cvmx_pip_tag_incx_s cn50xx;
-        struct cvmx_pip_tag_incx_s cn52xx;
-        struct cvmx_pip_tag_incx_s cn52xxp1;
-        struct cvmx_pip_tag_incx_s cn56xx;
-        struct cvmx_pip_tag_incx_s cn56xxp1;
-        struct cvmx_pip_tag_incx_s cn58xx;
-        struct cvmx_pip_tag_incx_s cn58xxp1;
-        struct cvmx_pip_tag_incx_s cn61xx;
-        struct cvmx_pip_tag_incx_s cn63xx;
-        struct cvmx_pip_tag_incx_s cn63xxp1;
-        struct cvmx_pip_tag_incx_s cn66xx;
-        struct cvmx_pip_tag_incx_s cn68xx;
-        struct cvmx_pip_tag_incx_s cn68xxp1;
-        struct cvmx_pip_tag_incx_s cnf71xx;
-};
-
-union cvmx_pip_tag_mask {
-        uint64_t u64;
-        struct cvmx_pip_tag_mask_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t mask:16;
-#else
-                uint64_t mask:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pip_tag_mask_s cn30xx;
-        struct cvmx_pip_tag_mask_s cn31xx;
-        struct cvmx_pip_tag_mask_s cn38xx;
-        struct cvmx_pip_tag_mask_s cn38xxp2;
-        struct cvmx_pip_tag_mask_s cn50xx;
-        struct cvmx_pip_tag_mask_s cn52xx;
-        struct cvmx_pip_tag_mask_s cn52xxp1;
-        struct cvmx_pip_tag_mask_s cn56xx;
-        struct cvmx_pip_tag_mask_s cn56xxp1;
-        struct cvmx_pip_tag_mask_s cn58xx;
-        struct cvmx_pip_tag_mask_s cn58xxp1;
-        struct cvmx_pip_tag_mask_s cn61xx;
-        struct cvmx_pip_tag_mask_s cn63xx;
-        struct cvmx_pip_tag_mask_s cn63xxp1;
-        struct cvmx_pip_tag_mask_s cn66xx;
-        struct cvmx_pip_tag_mask_s cn68xx;
-        struct cvmx_pip_tag_mask_s cn68xxp1;
-        struct cvmx_pip_tag_mask_s cnf71xx;
-};
-
-union cvmx_pip_tag_secret {
-        uint64_t u64;
-        struct cvmx_pip_tag_secret_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t dst:16;
-                uint64_t src:16;
-#else
-                uint64_t src:16;
-                uint64_t dst:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pip_tag_secret_s cn30xx;
-        struct cvmx_pip_tag_secret_s cn31xx;
-        struct cvmx_pip_tag_secret_s cn38xx;
-        struct cvmx_pip_tag_secret_s cn38xxp2;
-        struct cvmx_pip_tag_secret_s cn50xx;
-        struct cvmx_pip_tag_secret_s cn52xx;
-        struct cvmx_pip_tag_secret_s cn52xxp1;
-        struct cvmx_pip_tag_secret_s cn56xx;
-        struct cvmx_pip_tag_secret_s cn56xxp1;
-        struct cvmx_pip_tag_secret_s cn58xx;
-        struct cvmx_pip_tag_secret_s cn58xxp1;
-        struct cvmx_pip_tag_secret_s cn61xx;
-        struct cvmx_pip_tag_secret_s cn63xx;
-        struct cvmx_pip_tag_secret_s cn63xxp1;
-        struct cvmx_pip_tag_secret_s cn66xx;
-        struct cvmx_pip_tag_secret_s cn68xx;
-        struct cvmx_pip_tag_secret_s cn68xxp1;
-        struct cvmx_pip_tag_secret_s cnf71xx;
-};
-
-union cvmx_pip_todo_entry {
-        uint64_t u64;
-        struct cvmx_pip_todo_entry_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t val:1;
-                uint64_t reserved_62_62:1;
-                uint64_t entry:62;
-#else
-                uint64_t entry:62;
-                uint64_t reserved_62_62:1;
-                uint64_t val:1;
-#endif
-        } s;
-        struct cvmx_pip_todo_entry_s cn30xx;
-        struct cvmx_pip_todo_entry_s cn31xx;
-        struct cvmx_pip_todo_entry_s cn38xx;
-        struct cvmx_pip_todo_entry_s cn38xxp2;
-        struct cvmx_pip_todo_entry_s cn50xx;
-        struct cvmx_pip_todo_entry_s cn52xx;
-        struct cvmx_pip_todo_entry_s cn52xxp1;
-        struct cvmx_pip_todo_entry_s cn56xx;
-        struct cvmx_pip_todo_entry_s cn56xxp1;
-        struct cvmx_pip_todo_entry_s cn58xx;
-        struct cvmx_pip_todo_entry_s cn58xxp1;
-        struct cvmx_pip_todo_entry_s cn61xx;
-        struct cvmx_pip_todo_entry_s cn63xx;
-        struct cvmx_pip_todo_entry_s cn63xxp1;
-        struct cvmx_pip_todo_entry_s cn66xx;
-        struct cvmx_pip_todo_entry_s cn68xx;
-        struct cvmx_pip_todo_entry_s cn68xxp1;
-        struct cvmx_pip_todo_entry_s cnf71xx;
-};
-
-union cvmx_pip_vlan_etypesx {
-        uint64_t u64;
-        struct cvmx_pip_vlan_etypesx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t type3:16;
-                uint64_t type2:16;
-                uint64_t type1:16;
-                uint64_t type0:16;
-#else
-                uint64_t type0:16;
-                uint64_t type1:16;
-                uint64_t type2:16;
-                uint64_t type3:16;
-#endif
-        } s;
-        struct cvmx_pip_vlan_etypesx_s cn61xx;
-        struct cvmx_pip_vlan_etypesx_s cn66xx;
-        struct cvmx_pip_vlan_etypesx_s cn68xx;
-        struct cvmx_pip_vlan_etypesx_s cnf71xx;
-};
-
-union cvmx_pip_xstat0_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat0_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t drp_pkts:32;
-                uint64_t drp_octs:32;
-#else
-                uint64_t drp_octs:32;
-                uint64_t drp_pkts:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat0_prtx_s cn63xx;
-        struct cvmx_pip_xstat0_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat0_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat10_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat10_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bcast:32;
-                uint64_t mcast:32;
-#else
-                uint64_t mcast:32;
-                uint64_t bcast:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat10_prtx_s cn63xx;
-        struct cvmx_pip_xstat10_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat10_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat11_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat11_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bcast:32;
-                uint64_t mcast:32;
-#else
-                uint64_t mcast:32;
-                uint64_t bcast:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat11_prtx_s cn63xx;
-        struct cvmx_pip_xstat11_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat11_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat1_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat1_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t octs:48;
-#else
-                uint64_t octs:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_pip_xstat1_prtx_s cn63xx;
-        struct cvmx_pip_xstat1_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat1_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat2_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat2_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t pkts:32;
-                uint64_t raw:32;
-#else
-                uint64_t raw:32;
-                uint64_t pkts:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat2_prtx_s cn63xx;
-        struct cvmx_pip_xstat2_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat2_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat3_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat3_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t bcst:32;
-                uint64_t mcst:32;
-#else
-                uint64_t mcst:32;
-                uint64_t bcst:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat3_prtx_s cn63xx;
-        struct cvmx_pip_xstat3_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat3_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat4_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat4_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t h65to127:32;
-                uint64_t h64:32;
-#else
-                uint64_t h64:32;
-                uint64_t h65to127:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat4_prtx_s cn63xx;
-        struct cvmx_pip_xstat4_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat4_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat5_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat5_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t h256to511:32;
-                uint64_t h128to255:32;
-#else
-                uint64_t h128to255:32;
-                uint64_t h256to511:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat5_prtx_s cn63xx;
-        struct cvmx_pip_xstat5_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat5_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat6_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat6_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t h1024to1518:32;
-                uint64_t h512to1023:32;
-#else
-                uint64_t h512to1023:32;
-                uint64_t h1024to1518:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat6_prtx_s cn63xx;
-        struct cvmx_pip_xstat6_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat6_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat7_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat7_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t fcs:32;
-                uint64_t h1519:32;
-#else
-                uint64_t h1519:32;
-                uint64_t fcs:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat7_prtx_s cn63xx;
-        struct cvmx_pip_xstat7_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat7_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat8_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat8_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t frag:32;
-                uint64_t undersz:32;
-#else
-                uint64_t undersz:32;
-                uint64_t frag:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat8_prtx_s cn63xx;
-        struct cvmx_pip_xstat8_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat8_prtx_s cn66xx;
-};
-
-union cvmx_pip_xstat9_prtx {
-        uint64_t u64;
-        struct cvmx_pip_xstat9_prtx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t jabber:32;
-                uint64_t oversz:32;
-#else
-                uint64_t oversz:32;
-                uint64_t jabber:32;
-#endif
-        } s;
-        struct cvmx_pip_xstat9_prtx_s cn63xx;
-        struct cvmx_pip_xstat9_prtx_s cn63xxp1;
-        struct cvmx_pip_xstat9_prtx_s cn66xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h
deleted file mode 100644
index 9e739a64085..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-pip.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- * Interface to the hardware Packet Input Processing unit.
- *
- */
-
-#ifndef __CVMX_PIP_H__
-#define __CVMX_PIP_H__
-
-#include <asm/octeon/cvmx-wqe.h>
-#include <asm/octeon/cvmx-fpa.h>
-#include <asm/octeon/cvmx-pip-defs.h>
-
-#define CVMX_PIP_NUM_INPUT_PORTS                40
-#define CVMX_PIP_NUM_WATCHERS                   4
-
-/*
- * Encodes the different error and exception codes
- */
-typedef enum {
-        CVMX_PIP_L4_NO_ERR = 0ull,
-        /*
-         * 1 = TCP (UDP) packet not long enough to cover TCP (UDP)
-         * header
-         */
-        CVMX_PIP_L4_MAL_ERR = 1ull,
-        /* 2  = TCP/UDP checksum failure */
-        CVMX_PIP_CHK_ERR = 2ull,
-        /*
-         * 3 = TCP/UDP length check (TCP/UDP length does not match IP
-         * length).
-         */
-        CVMX_PIP_L4_LENGTH_ERR = 3ull,
-        /* 4  = illegal TCP/UDP port (either source or dest port is zero) */
-        CVMX_PIP_BAD_PRT_ERR = 4ull,
-        /* 8  = TCP flags = FIN only */
-        CVMX_PIP_TCP_FLG8_ERR = 8ull,
-        /* 9  = TCP flags = 0 */
-        CVMX_PIP_TCP_FLG9_ERR = 9ull,
-        /* 10 = TCP flags = FIN+RST+* */
-        CVMX_PIP_TCP_FLG10_ERR = 10ull,
-        /* 11 = TCP flags = SYN+URG+* */
-        CVMX_PIP_TCP_FLG11_ERR = 11ull,
-        /* 12 = TCP flags = SYN+RST+* */
-        CVMX_PIP_TCP_FLG12_ERR = 12ull,
-        /* 13 = TCP flags = SYN+FIN+* */
-        CVMX_PIP_TCP_FLG13_ERR = 13ull
-} cvmx_pip_l4_err_t;
-
-typedef enum {
-
-        CVMX_PIP_IP_NO_ERR = 0ull,
-        /* 1 = not IPv4 or IPv6 */
-        CVMX_PIP_NOT_IP = 1ull,
-        /* 2 = IPv4 header checksum violation */
-        CVMX_PIP_IPV4_HDR_CHK = 2ull,
-        /* 3 = malformed (packet not long enough to cover IP hdr) */
-        CVMX_PIP_IP_MAL_HDR = 3ull,
-        /* 4 = malformed (packet not long enough to cover len in IP hdr) */
-        CVMX_PIP_IP_MAL_PKT = 4ull,
-        /* 5 = TTL / hop count equal zero */
-        CVMX_PIP_TTL_HOP = 5ull,
-        /* 6 = IPv4 options / IPv6 early extension headers */
-        CVMX_PIP_OPTS = 6ull
-} cvmx_pip_ip_exc_t;
-
-/**
- * NOTES
- *       late collision (data received before collision)
- *            late collisions cannot be detected by the receiver
- *            they would appear as JAM bits which would appear as bad FCS
- *            or carrier extend error which is CVMX_PIP_EXTEND_ERR
- */
-typedef enum {
-        /* No error */
-        CVMX_PIP_RX_NO_ERR = 0ull,
-        /* RGM+SPI 1 = partially received packet (buffering/bandwidth
-         * not adequate) */
-        CVMX_PIP_PARTIAL_ERR = 1ull,
-        /* RGM+SPI 2 = receive packet too large and truncated */
-        CVMX_PIP_JABBER_ERR = 2ull,
-        /*
-         * RGM 3 = max frame error (pkt len > max frame len) (with FCS
-         * error)
-         */
-        CVMX_PIP_OVER_FCS_ERR = 3ull,
-        /* RGM+SPI 4 = max frame error (pkt len > max frame len) */
-        CVMX_PIP_OVER_ERR = 4ull,
-        /*
-         * RGM 5 = nibble error (data not byte multiple - 100M and 10M
-         * only)
-         */
-        CVMX_PIP_ALIGN_ERR = 5ull,
-        /*
-         * RGM 6 = min frame error (pkt len < min frame len) (with FCS
-         * error)
-         */
-        CVMX_PIP_UNDER_FCS_ERR = 6ull,
-        /* RGM     7 = FCS error */
-        CVMX_PIP_GMX_FCS_ERR = 7ull,
-        /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
-        CVMX_PIP_UNDER_ERR = 8ull,
-        /* RGM     9 = Frame carrier extend error */
-        CVMX_PIP_EXTEND_ERR = 9ull,
-        /*
-         * RGM 10 = length mismatch (len did not match len in L2
-         * length/type)
-         */
-        CVMX_PIP_LENGTH_ERR = 10ull,
-        /* RGM 11 = Frame error (some or all data bits marked err) */
-        CVMX_PIP_DAT_ERR = 11ull,
-        /*     SPI 11 = DIP4 error */
-        CVMX_PIP_DIP_ERR = 11ull,
-        /*
-         * RGM 12 = packet was not large enough to pass the skipper -
-         * no inspection could occur.
-         */
-        CVMX_PIP_SKIP_ERR = 12ull,
-        /*
-         * RGM 13 = studder error (data not repeated - 100M and 10M
-         * only)
-         */
-        CVMX_PIP_NIBBLE_ERR = 13ull,
-        /* RGM+SPI 16 = FCS error */
-        CVMX_PIP_PIP_FCS = 16L,
-        /*
-         * RGM+SPI+PCI 17 = packet was not large enough to pass the
-         * skipper - no inspection could occur.
-         */
-        CVMX_PIP_PIP_SKIP_ERR = 17L,
-        /*
-         * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to
-         * cover L2 hdr).
-         */
-        CVMX_PIP_PIP_L2_MAL_HDR = 18L
-        /*
-         * NOTES: xx = late collision (data received before collision)
-         *       late collisions cannot be detected by the receiver
-         *       they would appear as JAM bits which would appear as
-         *       bad FCS or carrier extend error which is
-         *       CVMX_PIP_EXTEND_ERR
-         */
-} cvmx_pip_rcv_err_t;
-
-/**
- * This defines the err_code field errors in the work Q entry
- */
-typedef union {
-        cvmx_pip_l4_err_t l4_err;
-        cvmx_pip_ip_exc_t ip_exc;
-        cvmx_pip_rcv_err_t rcv_err;
-} cvmx_pip_err_t;
-
-/**
- * Status statistics for a port
- */
-typedef struct {
-        /* Inbound octets marked to be dropped by the IPD */
-        uint32_t dropped_octets;
-        /* Inbound packets marked to be dropped by the IPD */
-        uint32_t dropped_packets;
-        /* RAW PCI Packets received by PIP per port */
-        uint32_t pci_raw_packets;
-        /* Number of octets processed by PIP */
-        uint32_t octets;
-        /* Number of packets processed by PIP */
-        uint32_t packets;
-        /*
-         * Number of indentified L2 multicast packets.  Does not
-         * include broadcast packets.  Only includes packets whose
-         * parse mode is SKIP_TO_L2
-         */
-        uint32_t multicast_packets;
-        /*
-         * Number of indentified L2 broadcast packets.  Does not
-         * include multicast packets.  Only includes packets whose
-         * parse mode is SKIP_TO_L2
-         */
-        uint32_t broadcast_packets;
-        /* Number of 64B packets */
-        uint32_t len_64_packets;
-        /* Number of 65-127B packets */
-        uint32_t len_65_127_packets;
-        /* Number of 128-255B packets */
-        uint32_t len_128_255_packets;
-        /* Number of 256-511B packets */
-        uint32_t len_256_511_packets;
-        /* Number of 512-1023B packets */
-        uint32_t len_512_1023_packets;
-        /* Number of 1024-1518B packets */
-        uint32_t len_1024_1518_packets;
-        /* Number of 1519-max packets */
-        uint32_t len_1519_max_packets;
-        /* Number of packets with FCS or Align opcode errors */
-        uint32_t fcs_align_err_packets;
-        /* Number of packets with length < min */
-        uint32_t runt_packets;
-        /* Number of packets with length < min and FCS error */
-        uint32_t runt_crc_packets;
-        /* Number of packets with length > max */
-        uint32_t oversize_packets;
-        /* Number of packets with length > max and FCS error */
-        uint32_t oversize_crc_packets;
-        /* Number of packets without GMX/SPX/PCI errors received by PIP */
-        uint32_t inb_packets;
-        /*
-         * Total number of octets from all packets received by PIP,
-         * including CRC
-         */
-        uint64_t inb_octets;
-        /* Number of packets with GMX/SPX/PCI errors received by PIP */
-        uint16_t inb_errors;
-} cvmx_pip_port_status_t;
-
-/**
- * Definition of the PIP custom header that can be prepended
- * to a packet by external hardware.
- */
-typedef union {
-        uint64_t u64;
-        struct {
-                /*
-                 * Documented as R - Set if the Packet is RAWFULL. If
-                 * set, this header must be the full 8 bytes.
-                 */
-                uint64_t rawfull:1;
-                /* Must be zero */
-                uint64_t reserved0:5;
-                /* PIP parse mode for this packet */
-                uint64_t parse_mode:2;
-                /* Must be zero */
-                uint64_t reserved1:1;
-                /*
-                 * Skip amount, including this header, to the
-                 * beginning of the packet
-                 */
-                uint64_t skip_len:7;
-                /* Must be zero */
-                uint64_t reserved2:6;
-                /* POW input queue for this packet */
-                uint64_t qos:3;
-                /* POW input group for this packet */
-                uint64_t grp:4;
-                /*
-                 * Flag to store this packet in the work queue entry,
-                 * if possible
-                 */
-                uint64_t rs:1;
-                /* POW input tag type */
-                uint64_t tag_type:2;
-                /* POW input tag */
-                uint64_t tag:32;
-        } s;
-} cvmx_pip_pkt_inst_hdr_t;
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-/**
- * Configure an ethernet input port
- *
- * @port_num: Port number to configure
- * @port_cfg: Port hardware configuration
- * @port_tag_cfg:
- *                 Port POW tagging configuration
- */
-static inline void cvmx_pip_config_port(uint64_t port_num,
-                                        union cvmx_pip_prt_cfgx port_cfg,
-                                        union cvmx_pip_prt_tagx port_tag_cfg)
-{
-        cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
-        cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
-}
-#if 0
-/**
- * @deprecated      This function is a thin wrapper around the Pass1 version
- *                  of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
- *                  setting the group that is incompatible with this function,
- *                  the preferred upgrade path is to use the CSR directly.
- *
- * Configure the global QoS packet watchers. Each watcher is
- * capable of matching a field in a packet to determine the
- * QoS queue for scheduling.
- *
- * @watcher:    Watcher number to configure (0 - 3).
- * @match_type: Watcher match type
- * @match_value:
- *                   Value the watcher will match against
- * @qos:        QoS queue for packets matching this watcher
- */
-static inline void cvmx_pip_config_watcher(uint64_t watcher,
-                                           cvmx_pip_qos_watch_types match_type,
-                                           uint64_t match_value, uint64_t qos)
-{
-        cvmx_pip_port_watcher_cfg_t watcher_config;
-
-        watcher_config.u64 = 0;
-        watcher_config.s.match_type = match_type;
-        watcher_config.s.match_value = match_value;
-        watcher_config.s.qos = qos;
-
-        cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
-}
-#endif
-/**
- * Configure the VLAN priority to QoS queue mapping.
- *
- * @vlan_priority:
- *               VLAN priority (0-7)
- * @qos:    QoS queue for packets matching this watcher
- */
-static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority,
-                                            uint64_t qos)
-{
-        union cvmx_pip_qos_vlanx pip_qos_vlanx;
-        pip_qos_vlanx.u64 = 0;
-        pip_qos_vlanx.s.qos = qos;
-        cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
-}
-
-/**
- * Configure the Diffserv to QoS queue mapping.
- *
- * @diffserv: Diffserv field value (0-63)
- * @qos:      QoS queue for packets matching this watcher
- */
-static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
-{
-        union cvmx_pip_qos_diffx pip_qos_diffx;
-        pip_qos_diffx.u64 = 0;
-        pip_qos_diffx.s.qos = qos;
-        cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
-}
-
-/**
- * Get the status counters for a port.
- *
- * @port_num: Port number to get statistics for.
- * @clear:    Set to 1 to clear the counters after they are read
- * @status:   Where to put the results.
- */
-static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
-                                            cvmx_pip_port_status_t *status)
-{
-        union cvmx_pip_stat_ctl pip_stat_ctl;
-        union cvmx_pip_stat0_prtx stat0;
-        union cvmx_pip_stat1_prtx stat1;
-        union cvmx_pip_stat2_prtx stat2;
-        union cvmx_pip_stat3_prtx stat3;
-        union cvmx_pip_stat4_prtx stat4;
-        union cvmx_pip_stat5_prtx stat5;
-        union cvmx_pip_stat6_prtx stat6;
-        union cvmx_pip_stat7_prtx stat7;
-        union cvmx_pip_stat8_prtx stat8;
-        union cvmx_pip_stat9_prtx stat9;
-        union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx;
-        union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx;
-        union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx;
-
-        pip_stat_ctl.u64 = 0;
-        pip_stat_ctl.s.rdclr = clear;
-        cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
-
-        stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
-        stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
-        stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
-        stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
-        stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
-        stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
-        stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
-        stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
-        stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
-        stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
-        pip_stat_inb_pktsx.u64 =
-            cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
-        pip_stat_inb_octsx.u64 =
-            cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
-        pip_stat_inb_errsx.u64 =
-            cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
-
-        status->dropped_octets = stat0.s.drp_octs;
-        status->dropped_packets = stat0.s.drp_pkts;
-        status->octets = stat1.s.octs;
-        status->pci_raw_packets = stat2.s.raw;
-        status->packets = stat2.s.pkts;
-        status->multicast_packets = stat3.s.mcst;
-        status->broadcast_packets = stat3.s.bcst;
-        status->len_64_packets = stat4.s.h64;
-        status->len_65_127_packets = stat4.s.h65to127;
-        status->len_128_255_packets = stat5.s.h128to255;
-        status->len_256_511_packets = stat5.s.h256to511;
-        status->len_512_1023_packets = stat6.s.h512to1023;
-        status->len_1024_1518_packets = stat6.s.h1024to1518;
-        status->len_1519_max_packets = stat7.s.h1519;
-        status->fcs_align_err_packets = stat7.s.fcs;
-        status->runt_packets = stat8.s.undersz;
-        status->runt_crc_packets = stat8.s.frag;
-        status->oversize_packets = stat9.s.oversz;
-        status->oversize_crc_packets = stat9.s.jabber;
-        status->inb_packets = pip_stat_inb_pktsx.s.pkts;
-        status->inb_octets = pip_stat_inb_octsx.s.octs;
-        status->inb_errors = pip_stat_inb_errsx.s.errs;
-
-        if (cvmx_octeon_is_pass1()) {
-                /*
-                 * Kludge to fix Octeon Pass 1 errata - Drop counts
-                 * don't work.
-                 */
-                if (status->inb_packets > status->packets)
-                        status->dropped_packets =
-                            status->inb_packets - status->packets;
-                else
-                        status->dropped_packets = 0;
-                if (status->inb_octets - status->inb_packets * 4 >
-                    status->octets)
-                        status->dropped_octets =
-                            status->inb_octets - status->inb_packets * 4 -
-                            status->octets;
-                else
-                        status->dropped_octets = 0;
-        }
-}
-
-/**
- * Configure the hardware CRC engine
- *
- * @interface: Interface to configure (0 or 1)
- * @invert_result:
- *                 Invert the result of the CRC
- * @reflect:  Reflect
- * @initialization_vector:
- *                 CRC initialization vector
- */
-static inline void cvmx_pip_config_crc(uint64_t interface,
-                                       uint64_t invert_result, uint64_t reflect,
-                                       uint32_t initialization_vector)
-{
-        if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
-                union cvmx_pip_crc_ctlx config;
-                union cvmx_pip_crc_ivx pip_crc_ivx;
-
-                config.u64 = 0;
-                config.s.invres = invert_result;
-                config.s.reflect = reflect;
-                cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
-
-                pip_crc_ivx.u64 = 0;
-                pip_crc_ivx.s.iv = initialization_vector;
-                cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
-        }
-}
-
-/**
- * Clear all bits in a tag mask. This should be called on
- * startup before any calls to cvmx_pip_tag_mask_set. Each bit
- * set in the final mask represent a byte used in the packet for
- * tag generation.
- *
- * @mask_index: Which tag mask to clear (0..3)
- */
-static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
-{
-        uint64_t index;
-        union cvmx_pip_tag_incx pip_tag_incx;
-        pip_tag_incx.u64 = 0;
-        pip_tag_incx.s.en = 0;
-        for (index = mask_index * 16; index < (mask_index + 1) * 16; index++)
-                cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
-}
-
-/**
- * Sets a range of bits in the tag mask. The tag mask is used
- * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
- * There are four separate masks that can be configured.
- *
- * @mask_index: Which tag mask to modify (0..3)
- * @offset: Offset into the bitmask to set bits at. Use the GCC macro
- *          offsetof() to determine the offsets into packet headers.
- *          For example, offsetof(ethhdr, protocol) returns the offset
- *          of the ethernet protocol field.  The bitmask selects which
- *          bytes to include the the tag, with bit offset X selecting
- *          byte at offset X from the beginning of the packet data.
- * @len:    Number of bytes to include. Usually this is the sizeof()
- *          the field.
- */
-static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset,
-                                         uint64_t len)
-{
-        while (len--) {
-                union cvmx_pip_tag_incx pip_tag_incx;
-                uint64_t index = mask_index * 16 + offset / 8;
-                pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
-                pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
-                cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
-                offset++;
-        }
-}
-
-#endif /*  __CVMX_PIP_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
deleted file mode 100644
index 87c3b970cad..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-pko-defs.h
+++ /dev/null
@@ -1,2824 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_PKO_DEFS_H__
-#define __CVMX_PKO_DEFS_H__
-
-#define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
-#define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
-#define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
-#define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
-#define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
-#define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
-#define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
-#define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
-#define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull))
-#define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull))
-#define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull))
-#define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull))
-#define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull))
-#define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull))
-#define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull))
-#define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
-#define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
-#define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull))
-#define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull))
-#define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull))
-#define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull))
-#define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull))
-#define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull))
-#define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull))
-#define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
-#define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
-#define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
-#define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull))
-#define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull))
-#define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
-#define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
-#define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8)
-#define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull))
-#define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8)
-#define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull))
-#define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull))
-#define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull))
-#define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
-#define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull))
-#define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
-#define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull))
-#define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8)
-#define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull))
-#define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
-#define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
-#define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
-#define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
-#define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull))
-#define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull))
-#define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull))
-#define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull))
-#define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
-#define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull))
-#define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull))
-#define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
-#define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull))
-#define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull))
-
-union cvmx_pko_mem_count0 {
-        uint64_t u64;
-        struct cvmx_pko_mem_count0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t count:32;
-#else
-                uint64_t count:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pko_mem_count0_s cn30xx;
-        struct cvmx_pko_mem_count0_s cn31xx;
-        struct cvmx_pko_mem_count0_s cn38xx;
-        struct cvmx_pko_mem_count0_s cn38xxp2;
-        struct cvmx_pko_mem_count0_s cn50xx;
-        struct cvmx_pko_mem_count0_s cn52xx;
-        struct cvmx_pko_mem_count0_s cn52xxp1;
-        struct cvmx_pko_mem_count0_s cn56xx;
-        struct cvmx_pko_mem_count0_s cn56xxp1;
-        struct cvmx_pko_mem_count0_s cn58xx;
-        struct cvmx_pko_mem_count0_s cn58xxp1;
-        struct cvmx_pko_mem_count0_s cn61xx;
-        struct cvmx_pko_mem_count0_s cn63xx;
-        struct cvmx_pko_mem_count0_s cn63xxp1;
-        struct cvmx_pko_mem_count0_s cn66xx;
-        struct cvmx_pko_mem_count0_s cn68xx;
-        struct cvmx_pko_mem_count0_s cn68xxp1;
-        struct cvmx_pko_mem_count0_s cnf71xx;
-};
-
-union cvmx_pko_mem_count1 {
-        uint64_t u64;
-        struct cvmx_pko_mem_count1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t count:48;
-#else
-                uint64_t count:48;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_pko_mem_count1_s cn30xx;
-        struct cvmx_pko_mem_count1_s cn31xx;
-        struct cvmx_pko_mem_count1_s cn38xx;
-        struct cvmx_pko_mem_count1_s cn38xxp2;
-        struct cvmx_pko_mem_count1_s cn50xx;
-        struct cvmx_pko_mem_count1_s cn52xx;
-        struct cvmx_pko_mem_count1_s cn52xxp1;
-        struct cvmx_pko_mem_count1_s cn56xx;
-        struct cvmx_pko_mem_count1_s cn56xxp1;
-        struct cvmx_pko_mem_count1_s cn58xx;
-        struct cvmx_pko_mem_count1_s cn58xxp1;
-        struct cvmx_pko_mem_count1_s cn61xx;
-        struct cvmx_pko_mem_count1_s cn63xx;
-        struct cvmx_pko_mem_count1_s cn63xxp1;
-        struct cvmx_pko_mem_count1_s cn66xx;
-        struct cvmx_pko_mem_count1_s cn68xx;
-        struct cvmx_pko_mem_count1_s cn68xxp1;
-        struct cvmx_pko_mem_count1_s cnf71xx;
-};
-
-union cvmx_pko_mem_debug0 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t fau:28;
-                uint64_t cmd:14;
-                uint64_t segs:6;
-                uint64_t size:16;
-#else
-                uint64_t size:16;
-                uint64_t segs:6;
-                uint64_t cmd:14;
-                uint64_t fau:28;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug0_s cn30xx;
-        struct cvmx_pko_mem_debug0_s cn31xx;
-        struct cvmx_pko_mem_debug0_s cn38xx;
-        struct cvmx_pko_mem_debug0_s cn38xxp2;
-        struct cvmx_pko_mem_debug0_s cn50xx;
-        struct cvmx_pko_mem_debug0_s cn52xx;
-        struct cvmx_pko_mem_debug0_s cn52xxp1;
-        struct cvmx_pko_mem_debug0_s cn56xx;
-        struct cvmx_pko_mem_debug0_s cn56xxp1;
-        struct cvmx_pko_mem_debug0_s cn58xx;
-        struct cvmx_pko_mem_debug0_s cn58xxp1;
-        struct cvmx_pko_mem_debug0_s cn61xx;
-        struct cvmx_pko_mem_debug0_s cn63xx;
-        struct cvmx_pko_mem_debug0_s cn63xxp1;
-        struct cvmx_pko_mem_debug0_s cn66xx;
-        struct cvmx_pko_mem_debug0_s cn68xx;
-        struct cvmx_pko_mem_debug0_s cn68xxp1;
-        struct cvmx_pko_mem_debug0_s cnf71xx;
-};
-
-union cvmx_pko_mem_debug1 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t i:1;
-                uint64_t back:4;
-                uint64_t pool:3;
-                uint64_t size:16;
-                uint64_t ptr:40;
-#else
-                uint64_t ptr:40;
-                uint64_t size:16;
-                uint64_t pool:3;
-                uint64_t back:4;
-                uint64_t i:1;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug1_s cn30xx;
-        struct cvmx_pko_mem_debug1_s cn31xx;
-        struct cvmx_pko_mem_debug1_s cn38xx;
-        struct cvmx_pko_mem_debug1_s cn38xxp2;
-        struct cvmx_pko_mem_debug1_s cn50xx;
-        struct cvmx_pko_mem_debug1_s cn52xx;
-        struct cvmx_pko_mem_debug1_s cn52xxp1;
-        struct cvmx_pko_mem_debug1_s cn56xx;
-        struct cvmx_pko_mem_debug1_s cn56xxp1;
-        struct cvmx_pko_mem_debug1_s cn58xx;
-        struct cvmx_pko_mem_debug1_s cn58xxp1;
-        struct cvmx_pko_mem_debug1_s cn61xx;
-        struct cvmx_pko_mem_debug1_s cn63xx;
-        struct cvmx_pko_mem_debug1_s cn63xxp1;
-        struct cvmx_pko_mem_debug1_s cn66xx;
-        struct cvmx_pko_mem_debug1_s cn68xx;
-        struct cvmx_pko_mem_debug1_s cn68xxp1;
-        struct cvmx_pko_mem_debug1_s cnf71xx;
-};
-
-union cvmx_pko_mem_debug10 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug10_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug10_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t fau:28;
-                uint64_t cmd:14;
-                uint64_t segs:6;
-                uint64_t size:16;
-#else
-                uint64_t size:16;
-                uint64_t segs:6;
-                uint64_t cmd:14;
-                uint64_t fau:28;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug10_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug10_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug10_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ptrs1:17;
-                uint64_t reserved_17_31:15;
-                uint64_t ptrs2:17;
-#else
-                uint64_t ptrs2:17;
-                uint64_t reserved_17_31:15;
-                uint64_t ptrs1:17;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug10_cn50xx cn52xx;
-        struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
-        struct cvmx_pko_mem_debug10_cn50xx cn56xx;
-        struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
-        struct cvmx_pko_mem_debug10_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug10_cn50xx cn61xx;
-        struct cvmx_pko_mem_debug10_cn50xx cn63xx;
-        struct cvmx_pko_mem_debug10_cn50xx cn63xxp1;
-        struct cvmx_pko_mem_debug10_cn50xx cn66xx;
-        struct cvmx_pko_mem_debug10_cn50xx cn68xx;
-        struct cvmx_pko_mem_debug10_cn50xx cn68xxp1;
-        struct cvmx_pko_mem_debug10_cn50xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug11 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug11_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t i:1;
-                uint64_t back:4;
-                uint64_t pool:3;
-                uint64_t size:16;
-                uint64_t reserved_0_39:40;
-#else
-                uint64_t reserved_0_39:40;
-                uint64_t size:16;
-                uint64_t pool:3;
-                uint64_t back:4;
-                uint64_t i:1;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug11_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t i:1;
-                uint64_t back:4;
-                uint64_t pool:3;
-                uint64_t size:16;
-                uint64_t ptr:40;
-#else
-                uint64_t ptr:40;
-                uint64_t size:16;
-                uint64_t pool:3;
-                uint64_t back:4;
-                uint64_t i:1;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug11_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug11_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug11_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t maj:1;
-                uint64_t uid:3;
-                uint64_t sop:1;
-                uint64_t len:1;
-                uint64_t chk:1;
-                uint64_t cnt:13;
-                uint64_t mod:3;
-#else
-                uint64_t mod:3;
-                uint64_t cnt:13;
-                uint64_t chk:1;
-                uint64_t len:1;
-                uint64_t sop:1;
-                uint64_t uid:3;
-                uint64_t maj:1;
-                uint64_t reserved_23_63:41;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug11_cn50xx cn52xx;
-        struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
-        struct cvmx_pko_mem_debug11_cn50xx cn56xx;
-        struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
-        struct cvmx_pko_mem_debug11_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug11_cn50xx cn61xx;
-        struct cvmx_pko_mem_debug11_cn50xx cn63xx;
-        struct cvmx_pko_mem_debug11_cn50xx cn63xxp1;
-        struct cvmx_pko_mem_debug11_cn50xx cn66xx;
-        struct cvmx_pko_mem_debug11_cn50xx cn68xx;
-        struct cvmx_pko_mem_debug11_cn50xx cn68xxp1;
-        struct cvmx_pko_mem_debug11_cn50xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug12 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug12_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug12_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug12_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug12_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug12_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t fau:28;
-                uint64_t cmd:14;
-                uint64_t segs:6;
-                uint64_t size:16;
-#else
-                uint64_t size:16;
-                uint64_t segs:6;
-                uint64_t cmd:14;
-                uint64_t fau:28;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug12_cn50xx cn52xx;
-        struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
-        struct cvmx_pko_mem_debug12_cn50xx cn56xx;
-        struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
-        struct cvmx_pko_mem_debug12_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug12_cn50xx cn61xx;
-        struct cvmx_pko_mem_debug12_cn50xx cn63xx;
-        struct cvmx_pko_mem_debug12_cn50xx cn63xxp1;
-        struct cvmx_pko_mem_debug12_cn50xx cn66xx;
-        struct cvmx_pko_mem_debug12_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t state:64;
-#else
-                uint64_t state:64;
-#endif
-        } cn68xx;
-        struct cvmx_pko_mem_debug12_cn68xx cn68xxp1;
-        struct cvmx_pko_mem_debug12_cn50xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug13 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug13_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug13_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_51_63:13;
-                uint64_t widx:17;
-                uint64_t ridx2:17;
-                uint64_t widx2:17;
-#else
-                uint64_t widx2:17;
-                uint64_t ridx2:17;
-                uint64_t widx:17;
-                uint64_t reserved_51_63:13;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug13_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug13_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug13_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t i:1;
-                uint64_t back:4;
-                uint64_t pool:3;
-                uint64_t size:16;
-                uint64_t ptr:40;
-#else
-                uint64_t ptr:40;
-                uint64_t size:16;
-                uint64_t pool:3;
-                uint64_t back:4;
-                uint64_t i:1;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug13_cn50xx cn52xx;
-        struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
-        struct cvmx_pko_mem_debug13_cn50xx cn56xx;
-        struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
-        struct cvmx_pko_mem_debug13_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug13_cn50xx cn61xx;
-        struct cvmx_pko_mem_debug13_cn50xx cn63xx;
-        struct cvmx_pko_mem_debug13_cn50xx cn63xxp1;
-        struct cvmx_pko_mem_debug13_cn50xx cn66xx;
-        struct cvmx_pko_mem_debug13_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t state:64;
-#else
-                uint64_t state:64;
-#endif
-        } cn68xx;
-        struct cvmx_pko_mem_debug13_cn68xx cn68xxp1;
-        struct cvmx_pko_mem_debug13_cn50xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug14 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug14_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug14_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t ridx:17;
-#else
-                uint64_t ridx:17;
-                uint64_t reserved_17_63:47;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug14_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug14_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug14_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } cn52xx;
-        struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
-        struct cvmx_pko_mem_debug14_cn52xx cn56xx;
-        struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
-        struct cvmx_pko_mem_debug14_cn52xx cn61xx;
-        struct cvmx_pko_mem_debug14_cn52xx cn63xx;
-        struct cvmx_pko_mem_debug14_cn52xx cn63xxp1;
-        struct cvmx_pko_mem_debug14_cn52xx cn66xx;
-        struct cvmx_pko_mem_debug14_cn52xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug2 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t i:1;
-                uint64_t back:4;
-                uint64_t pool:3;
-                uint64_t size:16;
-                uint64_t ptr:40;
-#else
-                uint64_t ptr:40;
-                uint64_t size:16;
-                uint64_t pool:3;
-                uint64_t back:4;
-                uint64_t i:1;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug2_s cn30xx;
-        struct cvmx_pko_mem_debug2_s cn31xx;
-        struct cvmx_pko_mem_debug2_s cn38xx;
-        struct cvmx_pko_mem_debug2_s cn38xxp2;
-        struct cvmx_pko_mem_debug2_s cn50xx;
-        struct cvmx_pko_mem_debug2_s cn52xx;
-        struct cvmx_pko_mem_debug2_s cn52xxp1;
-        struct cvmx_pko_mem_debug2_s cn56xx;
-        struct cvmx_pko_mem_debug2_s cn56xxp1;
-        struct cvmx_pko_mem_debug2_s cn58xx;
-        struct cvmx_pko_mem_debug2_s cn58xxp1;
-        struct cvmx_pko_mem_debug2_s cn61xx;
-        struct cvmx_pko_mem_debug2_s cn63xx;
-        struct cvmx_pko_mem_debug2_s cn63xxp1;
-        struct cvmx_pko_mem_debug2_s cn66xx;
-        struct cvmx_pko_mem_debug2_s cn68xx;
-        struct cvmx_pko_mem_debug2_s cn68xxp1;
-        struct cvmx_pko_mem_debug2_s cnf71xx;
-};
-
-union cvmx_pko_mem_debug3 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug3_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t i:1;
-                uint64_t back:4;
-                uint64_t pool:3;
-                uint64_t size:16;
-                uint64_t ptr:40;
-#else
-                uint64_t ptr:40;
-                uint64_t size:16;
-                uint64_t pool:3;
-                uint64_t back:4;
-                uint64_t i:1;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug3_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug3_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug3_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug3_cn50xx cn52xx;
-        struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
-        struct cvmx_pko_mem_debug3_cn50xx cn56xx;
-        struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
-        struct cvmx_pko_mem_debug3_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug3_cn50xx cn61xx;
-        struct cvmx_pko_mem_debug3_cn50xx cn63xx;
-        struct cvmx_pko_mem_debug3_cn50xx cn63xxp1;
-        struct cvmx_pko_mem_debug3_cn50xx cn66xx;
-        struct cvmx_pko_mem_debug3_cn50xx cn68xx;
-        struct cvmx_pko_mem_debug3_cn50xx cn68xxp1;
-        struct cvmx_pko_mem_debug3_cn50xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug4 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug4_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug4_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug4_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug4_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t cmnd_segs:3;
-                uint64_t cmnd_siz:16;
-                uint64_t cmnd_off:6;
-                uint64_t uid:3;
-                uint64_t dread_sop:1;
-                uint64_t init_dwrite:1;
-                uint64_t chk_once:1;
-                uint64_t chk_mode:1;
-                uint64_t active:1;
-                uint64_t static_p:1;
-                uint64_t qos:3;
-                uint64_t qcb_ridx:5;
-                uint64_t qid_off_max:4;
-                uint64_t qid_off:4;
-                uint64_t qid_base:8;
-                uint64_t wait:1;
-                uint64_t minor:2;
-                uint64_t major:3;
-#else
-                uint64_t major:3;
-                uint64_t minor:2;
-                uint64_t wait:1;
-                uint64_t qid_base:8;
-                uint64_t qid_off:4;
-                uint64_t qid_off_max:4;
-                uint64_t qcb_ridx:5;
-                uint64_t qos:3;
-                uint64_t static_p:1;
-                uint64_t active:1;
-                uint64_t chk_mode:1;
-                uint64_t chk_once:1;
-                uint64_t init_dwrite:1;
-                uint64_t dread_sop:1;
-                uint64_t uid:3;
-                uint64_t cmnd_off:6;
-                uint64_t cmnd_siz:16;
-                uint64_t cmnd_segs:3;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug4_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t curr_siz:8;
-                uint64_t curr_off:16;
-                uint64_t cmnd_segs:6;
-                uint64_t cmnd_siz:16;
-                uint64_t cmnd_off:6;
-                uint64_t uid:2;
-                uint64_t dread_sop:1;
-                uint64_t init_dwrite:1;
-                uint64_t chk_once:1;
-                uint64_t chk_mode:1;
-                uint64_t wait:1;
-                uint64_t minor:2;
-                uint64_t major:3;
-#else
-                uint64_t major:3;
-                uint64_t minor:2;
-                uint64_t wait:1;
-                uint64_t chk_mode:1;
-                uint64_t chk_once:1;
-                uint64_t init_dwrite:1;
-                uint64_t dread_sop:1;
-                uint64_t uid:2;
-                uint64_t cmnd_off:6;
-                uint64_t cmnd_siz:16;
-                uint64_t cmnd_segs:6;
-                uint64_t curr_off:16;
-                uint64_t curr_siz:8;
-#endif
-        } cn52xx;
-        struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
-        struct cvmx_pko_mem_debug4_cn52xx cn56xx;
-        struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
-        struct cvmx_pko_mem_debug4_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug4_cn52xx cn61xx;
-        struct cvmx_pko_mem_debug4_cn52xx cn63xx;
-        struct cvmx_pko_mem_debug4_cn52xx cn63xxp1;
-        struct cvmx_pko_mem_debug4_cn52xx cn66xx;
-        struct cvmx_pko_mem_debug4_cn52xx cn68xx;
-        struct cvmx_pko_mem_debug4_cn52xx cn68xxp1;
-        struct cvmx_pko_mem_debug4_cn52xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug5 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug5_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug5_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dwri_mod:1;
-                uint64_t dwri_sop:1;
-                uint64_t dwri_len:1;
-                uint64_t dwri_cnt:13;
-                uint64_t cmnd_siz:16;
-                uint64_t uid:1;
-                uint64_t xfer_wor:1;
-                uint64_t xfer_dwr:1;
-                uint64_t cbuf_fre:1;
-                uint64_t reserved_27_27:1;
-                uint64_t chk_mode:1;
-                uint64_t active:1;
-                uint64_t qos:3;
-                uint64_t qcb_ridx:5;
-                uint64_t qid_off:3;
-                uint64_t qid_base:7;
-                uint64_t wait:1;
-                uint64_t minor:2;
-                uint64_t major:4;
-#else
-                uint64_t major:4;
-                uint64_t minor:2;
-                uint64_t wait:1;
-                uint64_t qid_base:7;
-                uint64_t qid_off:3;
-                uint64_t qcb_ridx:5;
-                uint64_t qos:3;
-                uint64_t active:1;
-                uint64_t chk_mode:1;
-                uint64_t reserved_27_27:1;
-                uint64_t cbuf_fre:1;
-                uint64_t xfer_dwr:1;
-                uint64_t xfer_wor:1;
-                uint64_t uid:1;
-                uint64_t cmnd_siz:16;
-                uint64_t dwri_cnt:13;
-                uint64_t dwri_len:1;
-                uint64_t dwri_sop:1;
-                uint64_t dwri_mod:1;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug5_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug5_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug5_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t curr_ptr:29;
-                uint64_t curr_siz:16;
-                uint64_t curr_off:16;
-                uint64_t cmnd_segs:3;
-#else
-                uint64_t cmnd_segs:3;
-                uint64_t curr_off:16;
-                uint64_t curr_siz:16;
-                uint64_t curr_ptr:29;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug5_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t nxt_inflt:6;
-                uint64_t curr_ptr:40;
-                uint64_t curr_siz:8;
-#else
-                uint64_t curr_siz:8;
-                uint64_t curr_ptr:40;
-                uint64_t nxt_inflt:6;
-                uint64_t reserved_54_63:10;
-#endif
-        } cn52xx;
-        struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
-        struct cvmx_pko_mem_debug5_cn52xx cn56xx;
-        struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
-        struct cvmx_pko_mem_debug5_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug5_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t ptp:1;
-                uint64_t major_3:1;
-                uint64_t nxt_inflt:6;
-                uint64_t curr_ptr:40;
-                uint64_t curr_siz:8;
-#else
-                uint64_t curr_siz:8;
-                uint64_t curr_ptr:40;
-                uint64_t nxt_inflt:6;
-                uint64_t major_3:1;
-                uint64_t ptp:1;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn61xx;
-        struct cvmx_pko_mem_debug5_cn61xx cn63xx;
-        struct cvmx_pko_mem_debug5_cn61xx cn63xxp1;
-        struct cvmx_pko_mem_debug5_cn61xx cn66xx;
-        struct cvmx_pko_mem_debug5_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_57_63:7;
-                uint64_t uid_2:1;
-                uint64_t ptp:1;
-                uint64_t major_3:1;
-                uint64_t nxt_inflt:6;
-                uint64_t curr_ptr:40;
-                uint64_t curr_siz:8;
-#else
-                uint64_t curr_siz:8;
-                uint64_t curr_ptr:40;
-                uint64_t nxt_inflt:6;
-                uint64_t major_3:1;
-                uint64_t ptp:1;
-                uint64_t uid_2:1;
-                uint64_t reserved_57_63:7;
-#endif
-        } cn68xx;
-        struct cvmx_pko_mem_debug5_cn68xx cn68xxp1;
-        struct cvmx_pko_mem_debug5_cn61xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug6 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug6_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_37_63:27;
-                uint64_t qid_offres:4;
-                uint64_t qid_offths:4;
-                uint64_t preempter:1;
-                uint64_t preemptee:1;
-                uint64_t preempted:1;
-                uint64_t active:1;
-                uint64_t statc:1;
-                uint64_t qos:3;
-                uint64_t qcb_ridx:5;
-                uint64_t qid_offmax:4;
-                uint64_t reserved_0_11:12;
-#else
-                uint64_t reserved_0_11:12;
-                uint64_t qid_offmax:4;
-                uint64_t qcb_ridx:5;
-                uint64_t qos:3;
-                uint64_t statc:1;
-                uint64_t active:1;
-                uint64_t preempted:1;
-                uint64_t preemptee:1;
-                uint64_t preempter:1;
-                uint64_t qid_offths:4;
-                uint64_t qid_offres:4;
-                uint64_t reserved_37_63:27;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug6_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t qid_offm:3;
-                uint64_t static_p:1;
-                uint64_t work_min:3;
-                uint64_t dwri_chk:1;
-                uint64_t dwri_uid:1;
-                uint64_t dwri_mod:2;
-#else
-                uint64_t dwri_mod:2;
-                uint64_t dwri_uid:1;
-                uint64_t dwri_chk:1;
-                uint64_t work_min:3;
-                uint64_t static_p:1;
-                uint64_t qid_offm:3;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug6_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug6_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug6_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t curr_ptr:11;
-#else
-                uint64_t curr_ptr:11;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug6_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_37_63:27;
-                uint64_t qid_offres:4;
-                uint64_t qid_offths:4;
-                uint64_t preempter:1;
-                uint64_t preemptee:1;
-                uint64_t preempted:1;
-                uint64_t active:1;
-                uint64_t statc:1;
-                uint64_t qos:3;
-                uint64_t qcb_ridx:5;
-                uint64_t qid_offmax:4;
-                uint64_t qid_off:4;
-                uint64_t qid_base:8;
-#else
-                uint64_t qid_base:8;
-                uint64_t qid_off:4;
-                uint64_t qid_offmax:4;
-                uint64_t qcb_ridx:5;
-                uint64_t qos:3;
-                uint64_t statc:1;
-                uint64_t active:1;
-                uint64_t preempted:1;
-                uint64_t preemptee:1;
-                uint64_t preempter:1;
-                uint64_t qid_offths:4;
-                uint64_t qid_offres:4;
-                uint64_t reserved_37_63:27;
-#endif
-        } cn52xx;
-        struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
-        struct cvmx_pko_mem_debug6_cn52xx cn56xx;
-        struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
-        struct cvmx_pko_mem_debug6_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug6_cn52xx cn61xx;
-        struct cvmx_pko_mem_debug6_cn52xx cn63xx;
-        struct cvmx_pko_mem_debug6_cn52xx cn63xxp1;
-        struct cvmx_pko_mem_debug6_cn52xx cn66xx;
-        struct cvmx_pko_mem_debug6_cn52xx cn68xx;
-        struct cvmx_pko_mem_debug6_cn52xx cn68xxp1;
-        struct cvmx_pko_mem_debug6_cn52xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug7 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug7_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug7_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_58_63:6;
-                uint64_t dwb:9;
-                uint64_t start:33;
-                uint64_t size:16;
-#else
-                uint64_t size:16;
-                uint64_t start:33;
-                uint64_t dwb:9;
-                uint64_t reserved_58_63:6;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug7_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug7_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug7_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t qos:5;
-                uint64_t tail:1;
-                uint64_t buf_siz:13;
-                uint64_t buf_ptr:33;
-                uint64_t qcb_widx:6;
-                uint64_t qcb_ridx:6;
-#else
-                uint64_t qcb_ridx:6;
-                uint64_t qcb_widx:6;
-                uint64_t buf_ptr:33;
-                uint64_t buf_siz:13;
-                uint64_t tail:1;
-                uint64_t qos:5;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug7_cn50xx cn52xx;
-        struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
-        struct cvmx_pko_mem_debug7_cn50xx cn56xx;
-        struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
-        struct cvmx_pko_mem_debug7_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug7_cn50xx cn61xx;
-        struct cvmx_pko_mem_debug7_cn50xx cn63xx;
-        struct cvmx_pko_mem_debug7_cn50xx cn63xxp1;
-        struct cvmx_pko_mem_debug7_cn50xx cn66xx;
-        struct cvmx_pko_mem_debug7_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t qos:3;
-                uint64_t tail:1;
-                uint64_t buf_siz:13;
-                uint64_t buf_ptr:33;
-                uint64_t qcb_widx:7;
-                uint64_t qcb_ridx:7;
-#else
-                uint64_t qcb_ridx:7;
-                uint64_t qcb_widx:7;
-                uint64_t buf_ptr:33;
-                uint64_t buf_siz:13;
-                uint64_t tail:1;
-                uint64_t qos:3;
-#endif
-        } cn68xx;
-        struct cvmx_pko_mem_debug7_cn68xx cn68xxp1;
-        struct cvmx_pko_mem_debug7_cn50xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug8 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug8_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_59_63:5;
-                uint64_t tail:1;
-                uint64_t buf_siz:13;
-                uint64_t reserved_0_44:45;
-#else
-                uint64_t reserved_0_44:45;
-                uint64_t buf_siz:13;
-                uint64_t tail:1;
-                uint64_t reserved_59_63:5;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug8_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t qos:5;
-                uint64_t tail:1;
-                uint64_t buf_siz:13;
-                uint64_t buf_ptr:33;
-                uint64_t qcb_widx:6;
-                uint64_t qcb_ridx:6;
-#else
-                uint64_t qcb_ridx:6;
-                uint64_t qcb_widx:6;
-                uint64_t buf_ptr:33;
-                uint64_t buf_siz:13;
-                uint64_t tail:1;
-                uint64_t qos:5;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug8_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug8_cn30xx cn38xx;
-        struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;
-        struct cvmx_pko_mem_debug8_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t doorbell:20;
-                uint64_t reserved_6_7:2;
-                uint64_t static_p:1;
-                uint64_t s_tail:1;
-                uint64_t static_q:1;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t static_q:1;
-                uint64_t s_tail:1;
-                uint64_t static_p:1;
-                uint64_t reserved_6_7:2;
-                uint64_t doorbell:20;
-                uint64_t reserved_28_63:36;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug8_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_29_63:35;
-                uint64_t preempter:1;
-                uint64_t doorbell:20;
-                uint64_t reserved_7_7:1;
-                uint64_t preemptee:1;
-                uint64_t static_p:1;
-                uint64_t s_tail:1;
-                uint64_t static_q:1;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t static_q:1;
-                uint64_t s_tail:1;
-                uint64_t static_p:1;
-                uint64_t preemptee:1;
-                uint64_t reserved_7_7:1;
-                uint64_t doorbell:20;
-                uint64_t preempter:1;
-                uint64_t reserved_29_63:35;
-#endif
-        } cn52xx;
-        struct cvmx_pko_mem_debug8_cn52xx cn52xxp1;
-        struct cvmx_pko_mem_debug8_cn52xx cn56xx;
-        struct cvmx_pko_mem_debug8_cn52xx cn56xxp1;
-        struct cvmx_pko_mem_debug8_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug8_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug8_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_42_63:22;
-                uint64_t qid_qqos:8;
-                uint64_t reserved_33_33:1;
-                uint64_t qid_idx:4;
-                uint64_t preempter:1;
-                uint64_t doorbell:20;
-                uint64_t reserved_7_7:1;
-                uint64_t preemptee:1;
-                uint64_t static_p:1;
-                uint64_t s_tail:1;
-                uint64_t static_q:1;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t static_q:1;
-                uint64_t s_tail:1;
-                uint64_t static_p:1;
-                uint64_t preemptee:1;
-                uint64_t reserved_7_7:1;
-                uint64_t doorbell:20;
-                uint64_t preempter:1;
-                uint64_t qid_idx:4;
-                uint64_t reserved_33_33:1;
-                uint64_t qid_qqos:8;
-                uint64_t reserved_42_63:22;
-#endif
-        } cn61xx;
-        struct cvmx_pko_mem_debug8_cn52xx cn63xx;
-        struct cvmx_pko_mem_debug8_cn52xx cn63xxp1;
-        struct cvmx_pko_mem_debug8_cn61xx cn66xx;
-        struct cvmx_pko_mem_debug8_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_37_63:27;
-                uint64_t preempter:1;
-                uint64_t doorbell:20;
-                uint64_t reserved_9_15:7;
-                uint64_t preemptee:1;
-                uint64_t static_p:1;
-                uint64_t s_tail:1;
-                uint64_t static_q:1;
-                uint64_t qos:5;
-#else
-                uint64_t qos:5;
-                uint64_t static_q:1;
-                uint64_t s_tail:1;
-                uint64_t static_p:1;
-                uint64_t preemptee:1;
-                uint64_t reserved_9_15:7;
-                uint64_t doorbell:20;
-                uint64_t preempter:1;
-                uint64_t reserved_37_63:27;
-#endif
-        } cn68xx;
-        struct cvmx_pko_mem_debug8_cn68xx cn68xxp1;
-        struct cvmx_pko_mem_debug8_cn61xx cnf71xx;
-};
-
-union cvmx_pko_mem_debug9 {
-        uint64_t u64;
-        struct cvmx_pko_mem_debug9_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ptrs0:17;
-                uint64_t reserved_0_31:32;
-#else
-                uint64_t reserved_0_31:32;
-                uint64_t ptrs0:17;
-                uint64_t reserved_49_63:15;
-#endif
-        } s;
-        struct cvmx_pko_mem_debug9_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t doorbell:20;
-                uint64_t reserved_5_7:3;
-                uint64_t s_tail:1;
-                uint64_t static_q:1;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t static_q:1;
-                uint64_t s_tail:1;
-                uint64_t reserved_5_7:3;
-                uint64_t doorbell:20;
-                uint64_t reserved_28_63:36;
-#endif
-        } cn30xx;
-        struct cvmx_pko_mem_debug9_cn30xx cn31xx;
-        struct cvmx_pko_mem_debug9_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t doorbell:20;
-                uint64_t reserved_6_7:2;
-                uint64_t static_p:1;
-                uint64_t s_tail:1;
-                uint64_t static_q:1;
-                uint64_t qos:3;
-#else
-                uint64_t qos:3;
-                uint64_t static_q:1;
-                uint64_t s_tail:1;
-                uint64_t static_p:1;
-                uint64_t reserved_6_7:2;
-                uint64_t doorbell:20;
-                uint64_t reserved_28_63:36;
-#endif
-        } cn38xx;
-        struct cvmx_pko_mem_debug9_cn38xx cn38xxp2;
-        struct cvmx_pko_mem_debug9_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t ptrs0:17;
-                uint64_t reserved_17_31:15;
-                uint64_t ptrs3:17;
-#else
-                uint64_t ptrs3:17;
-                uint64_t reserved_17_31:15;
-                uint64_t ptrs0:17;
-                uint64_t reserved_49_63:15;
-#endif
-        } cn50xx;
-        struct cvmx_pko_mem_debug9_cn50xx cn52xx;
-        struct cvmx_pko_mem_debug9_cn50xx cn52xxp1;
-        struct cvmx_pko_mem_debug9_cn50xx cn56xx;
-        struct cvmx_pko_mem_debug9_cn50xx cn56xxp1;
-        struct cvmx_pko_mem_debug9_cn50xx cn58xx;
-        struct cvmx_pko_mem_debug9_cn50xx cn58xxp1;
-        struct cvmx_pko_mem_debug9_cn50xx cn61xx;
-        struct cvmx_pko_mem_debug9_cn50xx cn63xx;
-        struct cvmx_pko_mem_debug9_cn50xx cn63xxp1;
-        struct cvmx_pko_mem_debug9_cn50xx cn66xx;
-        struct cvmx_pko_mem_debug9_cn50xx cn68xx;
-        struct cvmx_pko_mem_debug9_cn50xx cn68xxp1;
-        struct cvmx_pko_mem_debug9_cn50xx cnf71xx;
-};
-
-union cvmx_pko_mem_iport_ptrs {
-        uint64_t u64;
-        struct cvmx_pko_mem_iport_ptrs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_63_63:1;
-                uint64_t crc:1;
-                uint64_t static_p:1;
-                uint64_t qos_mask:8;
-                uint64_t min_pkt:3;
-                uint64_t reserved_31_49:19;
-                uint64_t pipe:7;
-                uint64_t reserved_21_23:3;
-                uint64_t intr:5;
-                uint64_t reserved_13_15:3;
-                uint64_t eid:5;
-                uint64_t reserved_7_7:1;
-                uint64_t ipid:7;
-#else
-                uint64_t ipid:7;
-                uint64_t reserved_7_7:1;
-                uint64_t eid:5;
-                uint64_t reserved_13_15:3;
-                uint64_t intr:5;
-                uint64_t reserved_21_23:3;
-                uint64_t pipe:7;
-                uint64_t reserved_31_49:19;
-                uint64_t min_pkt:3;
-                uint64_t qos_mask:8;
-                uint64_t static_p:1;
-                uint64_t crc:1;
-                uint64_t reserved_63_63:1;
-#endif
-        } s;
-        struct cvmx_pko_mem_iport_ptrs_s cn68xx;
-        struct cvmx_pko_mem_iport_ptrs_s cn68xxp1;
-};
-
-union cvmx_pko_mem_iport_qos {
-        uint64_t u64;
-        struct cvmx_pko_mem_iport_qos_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t qos_mask:8;
-                uint64_t reserved_13_52:40;
-                uint64_t eid:5;
-                uint64_t reserved_7_7:1;
-                uint64_t ipid:7;
-#else
-                uint64_t ipid:7;
-                uint64_t reserved_7_7:1;
-                uint64_t eid:5;
-                uint64_t reserved_13_52:40;
-                uint64_t qos_mask:8;
-                uint64_t reserved_61_63:3;
-#endif
-        } s;
-        struct cvmx_pko_mem_iport_qos_s cn68xx;
-        struct cvmx_pko_mem_iport_qos_s cn68xxp1;
-};
-
-union cvmx_pko_mem_iqueue_ptrs {
-        uint64_t u64;
-        struct cvmx_pko_mem_iqueue_ptrs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t s_tail:1;
-                uint64_t static_p:1;
-                uint64_t static_q:1;
-                uint64_t qos_mask:8;
-                uint64_t buf_ptr:31;
-                uint64_t tail:1;
-                uint64_t index:5;
-                uint64_t reserved_15_15:1;
-                uint64_t ipid:7;
-                uint64_t qid:8;
-#else
-                uint64_t qid:8;
-                uint64_t ipid:7;
-                uint64_t reserved_15_15:1;
-                uint64_t index:5;
-                uint64_t tail:1;
-                uint64_t buf_ptr:31;
-                uint64_t qos_mask:8;
-                uint64_t static_q:1;
-                uint64_t static_p:1;
-                uint64_t s_tail:1;
-#endif
-        } s;
-        struct cvmx_pko_mem_iqueue_ptrs_s cn68xx;
-        struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1;
-};
-
-union cvmx_pko_mem_iqueue_qos {
-        uint64_t u64;
-        struct cvmx_pko_mem_iqueue_qos_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t qos_mask:8;
-                uint64_t reserved_15_52:38;
-                uint64_t ipid:7;
-                uint64_t qid:8;
-#else
-                uint64_t qid:8;
-                uint64_t ipid:7;
-                uint64_t reserved_15_52:38;
-                uint64_t qos_mask:8;
-                uint64_t reserved_61_63:3;
-#endif
-        } s;
-        struct cvmx_pko_mem_iqueue_qos_s cn68xx;
-        struct cvmx_pko_mem_iqueue_qos_s cn68xxp1;
-};
-
-union cvmx_pko_mem_port_ptrs {
-        uint64_t u64;
-        struct cvmx_pko_mem_port_ptrs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t static_p:1;
-                uint64_t qos_mask:8;
-                uint64_t reserved_16_52:37;
-                uint64_t bp_port:6;
-                uint64_t eid:4;
-                uint64_t pid:6;
-#else
-                uint64_t pid:6;
-                uint64_t eid:4;
-                uint64_t bp_port:6;
-                uint64_t reserved_16_52:37;
-                uint64_t qos_mask:8;
-                uint64_t static_p:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_pko_mem_port_ptrs_s cn52xx;
-        struct cvmx_pko_mem_port_ptrs_s cn52xxp1;
-        struct cvmx_pko_mem_port_ptrs_s cn56xx;
-        struct cvmx_pko_mem_port_ptrs_s cn56xxp1;
-        struct cvmx_pko_mem_port_ptrs_s cn61xx;
-        struct cvmx_pko_mem_port_ptrs_s cn63xx;
-        struct cvmx_pko_mem_port_ptrs_s cn63xxp1;
-        struct cvmx_pko_mem_port_ptrs_s cn66xx;
-        struct cvmx_pko_mem_port_ptrs_s cnf71xx;
-};
-
-union cvmx_pko_mem_port_qos {
-        uint64_t u64;
-        struct cvmx_pko_mem_port_qos_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t qos_mask:8;
-                uint64_t reserved_10_52:43;
-                uint64_t eid:4;
-                uint64_t pid:6;
-#else
-                uint64_t pid:6;
-                uint64_t eid:4;
-                uint64_t reserved_10_52:43;
-                uint64_t qos_mask:8;
-                uint64_t reserved_61_63:3;
-#endif
-        } s;
-        struct cvmx_pko_mem_port_qos_s cn52xx;
-        struct cvmx_pko_mem_port_qos_s cn52xxp1;
-        struct cvmx_pko_mem_port_qos_s cn56xx;
-        struct cvmx_pko_mem_port_qos_s cn56xxp1;
-        struct cvmx_pko_mem_port_qos_s cn61xx;
-        struct cvmx_pko_mem_port_qos_s cn63xx;
-        struct cvmx_pko_mem_port_qos_s cn63xxp1;
-        struct cvmx_pko_mem_port_qos_s cn66xx;
-        struct cvmx_pko_mem_port_qos_s cnf71xx;
-};
-
-union cvmx_pko_mem_port_rate0 {
-        uint64_t u64;
-        struct cvmx_pko_mem_port_rate0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_51_63:13;
-                uint64_t rate_word:19;
-                uint64_t rate_pkt:24;
-                uint64_t reserved_7_7:1;
-                uint64_t pid:7;
-#else
-                uint64_t pid:7;
-                uint64_t reserved_7_7:1;
-                uint64_t rate_pkt:24;
-                uint64_t rate_word:19;
-                uint64_t reserved_51_63:13;
-#endif
-        } s;
-        struct cvmx_pko_mem_port_rate0_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_51_63:13;
-                uint64_t rate_word:19;
-                uint64_t rate_pkt:24;
-                uint64_t reserved_6_7:2;
-                uint64_t pid:6;
-#else
-                uint64_t pid:6;
-                uint64_t reserved_6_7:2;
-                uint64_t rate_pkt:24;
-                uint64_t rate_word:19;
-                uint64_t reserved_51_63:13;
-#endif
-        } cn52xx;
-        struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1;
-        struct cvmx_pko_mem_port_rate0_cn52xx cn56xx;
-        struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1;
-        struct cvmx_pko_mem_port_rate0_cn52xx cn61xx;
-        struct cvmx_pko_mem_port_rate0_cn52xx cn63xx;
-        struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1;
-        struct cvmx_pko_mem_port_rate0_cn52xx cn66xx;
-        struct cvmx_pko_mem_port_rate0_s cn68xx;
-        struct cvmx_pko_mem_port_rate0_s cn68xxp1;
-        struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx;
-};
-
-union cvmx_pko_mem_port_rate1 {
-        uint64_t u64;
-        struct cvmx_pko_mem_port_rate1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t rate_lim:24;
-                uint64_t reserved_7_7:1;
-                uint64_t pid:7;
-#else
-                uint64_t pid:7;
-                uint64_t reserved_7_7:1;
-                uint64_t rate_lim:24;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pko_mem_port_rate1_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t rate_lim:24;
-                uint64_t reserved_6_7:2;
-                uint64_t pid:6;
-#else
-                uint64_t pid:6;
-                uint64_t reserved_6_7:2;
-                uint64_t rate_lim:24;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn52xx;
-        struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1;
-        struct cvmx_pko_mem_port_rate1_cn52xx cn56xx;
-        struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1;
-        struct cvmx_pko_mem_port_rate1_cn52xx cn61xx;
-        struct cvmx_pko_mem_port_rate1_cn52xx cn63xx;
-        struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1;
-        struct cvmx_pko_mem_port_rate1_cn52xx cn66xx;
-        struct cvmx_pko_mem_port_rate1_s cn68xx;
-        struct cvmx_pko_mem_port_rate1_s cn68xxp1;
-        struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx;
-};
-
-union cvmx_pko_mem_queue_ptrs {
-        uint64_t u64;
-        struct cvmx_pko_mem_queue_ptrs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t s_tail:1;
-                uint64_t static_p:1;
-                uint64_t static_q:1;
-                uint64_t qos_mask:8;
-                uint64_t buf_ptr:36;
-                uint64_t tail:1;
-                uint64_t index:3;
-                uint64_t port:6;
-                uint64_t queue:7;
-#else
-                uint64_t queue:7;
-                uint64_t port:6;
-                uint64_t index:3;
-                uint64_t tail:1;
-                uint64_t buf_ptr:36;
-                uint64_t qos_mask:8;
-                uint64_t static_q:1;
-                uint64_t static_p:1;
-                uint64_t s_tail:1;
-#endif
-        } s;
-        struct cvmx_pko_mem_queue_ptrs_s cn30xx;
-        struct cvmx_pko_mem_queue_ptrs_s cn31xx;
-        struct cvmx_pko_mem_queue_ptrs_s cn38xx;
-        struct cvmx_pko_mem_queue_ptrs_s cn38xxp2;
-        struct cvmx_pko_mem_queue_ptrs_s cn50xx;
-        struct cvmx_pko_mem_queue_ptrs_s cn52xx;
-        struct cvmx_pko_mem_queue_ptrs_s cn52xxp1;
-        struct cvmx_pko_mem_queue_ptrs_s cn56xx;
-        struct cvmx_pko_mem_queue_ptrs_s cn56xxp1;
-        struct cvmx_pko_mem_queue_ptrs_s cn58xx;
-        struct cvmx_pko_mem_queue_ptrs_s cn58xxp1;
-        struct cvmx_pko_mem_queue_ptrs_s cn61xx;
-        struct cvmx_pko_mem_queue_ptrs_s cn63xx;
-        struct cvmx_pko_mem_queue_ptrs_s cn63xxp1;
-        struct cvmx_pko_mem_queue_ptrs_s cn66xx;
-        struct cvmx_pko_mem_queue_ptrs_s cnf71xx;
-};
-
-union cvmx_pko_mem_queue_qos {
-        uint64_t u64;
-        struct cvmx_pko_mem_queue_qos_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t qos_mask:8;
-                uint64_t reserved_13_52:40;
-                uint64_t pid:6;
-                uint64_t qid:7;
-#else
-                uint64_t qid:7;
-                uint64_t pid:6;
-                uint64_t reserved_13_52:40;
-                uint64_t qos_mask:8;
-                uint64_t reserved_61_63:3;
-#endif
-        } s;
-        struct cvmx_pko_mem_queue_qos_s cn30xx;
-        struct cvmx_pko_mem_queue_qos_s cn31xx;
-        struct cvmx_pko_mem_queue_qos_s cn38xx;
-        struct cvmx_pko_mem_queue_qos_s cn38xxp2;
-        struct cvmx_pko_mem_queue_qos_s cn50xx;
-        struct cvmx_pko_mem_queue_qos_s cn52xx;
-        struct cvmx_pko_mem_queue_qos_s cn52xxp1;
-        struct cvmx_pko_mem_queue_qos_s cn56xx;
-        struct cvmx_pko_mem_queue_qos_s cn56xxp1;
-        struct cvmx_pko_mem_queue_qos_s cn58xx;
-        struct cvmx_pko_mem_queue_qos_s cn58xxp1;
-        struct cvmx_pko_mem_queue_qos_s cn61xx;
-        struct cvmx_pko_mem_queue_qos_s cn63xx;
-        struct cvmx_pko_mem_queue_qos_s cn63xxp1;
-        struct cvmx_pko_mem_queue_qos_s cn66xx;
-        struct cvmx_pko_mem_queue_qos_s cnf71xx;
-};
-
-union cvmx_pko_mem_throttle_int {
-        uint64_t u64;
-        struct cvmx_pko_mem_throttle_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_47_63:17;
-                uint64_t word:15;
-                uint64_t reserved_14_31:18;
-                uint64_t packet:6;
-                uint64_t reserved_5_7:3;
-                uint64_t intr:5;
-#else
-                uint64_t intr:5;
-                uint64_t reserved_5_7:3;
-                uint64_t packet:6;
-                uint64_t reserved_14_31:18;
-                uint64_t word:15;
-                uint64_t reserved_47_63:17;
-#endif
-        } s;
-        struct cvmx_pko_mem_throttle_int_s cn68xx;
-        struct cvmx_pko_mem_throttle_int_s cn68xxp1;
-};
-
-union cvmx_pko_mem_throttle_pipe {
-        uint64_t u64;
-        struct cvmx_pko_mem_throttle_pipe_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_47_63:17;
-                uint64_t word:15;
-                uint64_t reserved_14_31:18;
-                uint64_t packet:6;
-                uint64_t reserved_7_7:1;
-                uint64_t pipe:7;
-#else
-                uint64_t pipe:7;
-                uint64_t reserved_7_7:1;
-                uint64_t packet:6;
-                uint64_t reserved_14_31:18;
-                uint64_t word:15;
-                uint64_t reserved_47_63:17;
-#endif
-        } s;
-        struct cvmx_pko_mem_throttle_pipe_s cn68xx;
-        struct cvmx_pko_mem_throttle_pipe_s cn68xxp1;
-};
-
-union cvmx_pko_reg_bist_result {
-        uint64_t u64;
-        struct cvmx_pko_reg_bist_result_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_pko_reg_bist_result_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_27_63:37;
-                uint64_t psb2:5;
-                uint64_t count:1;
-                uint64_t rif:1;
-                uint64_t wif:1;
-                uint64_t ncb:1;
-                uint64_t out:1;
-                uint64_t crc:1;
-                uint64_t chk:1;
-                uint64_t qsb:2;
-                uint64_t qcb:2;
-                uint64_t pdb:4;
-                uint64_t psb:7;
-#else
-                uint64_t psb:7;
-                uint64_t pdb:4;
-                uint64_t qcb:2;
-                uint64_t qsb:2;
-                uint64_t chk:1;
-                uint64_t crc:1;
-                uint64_t out:1;
-                uint64_t ncb:1;
-                uint64_t wif:1;
-                uint64_t rif:1;
-                uint64_t count:1;
-                uint64_t psb2:5;
-                uint64_t reserved_27_63:37;
-#endif
-        } cn30xx;
-        struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
-        struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
-        struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
-        struct cvmx_pko_reg_bist_result_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t csr:1;
-                uint64_t iob:1;
-                uint64_t out_crc:1;
-                uint64_t out_ctl:3;
-                uint64_t out_sta:1;
-                uint64_t out_wif:1;
-                uint64_t prt_chk:3;
-                uint64_t prt_nxt:1;
-                uint64_t prt_psb:6;
-                uint64_t ncb_inb:2;
-                uint64_t prt_qcb:2;
-                uint64_t prt_qsb:3;
-                uint64_t dat_dat:4;
-                uint64_t dat_ptr:4;
-#else
-                uint64_t dat_ptr:4;
-                uint64_t dat_dat:4;
-                uint64_t prt_qsb:3;
-                uint64_t prt_qcb:2;
-                uint64_t ncb_inb:2;
-                uint64_t prt_psb:6;
-                uint64_t prt_nxt:1;
-                uint64_t prt_chk:3;
-                uint64_t out_wif:1;
-                uint64_t out_sta:1;
-                uint64_t out_ctl:3;
-                uint64_t out_crc:1;
-                uint64_t iob:1;
-                uint64_t csr:1;
-                uint64_t reserved_33_63:31;
-#endif
-        } cn50xx;
-        struct cvmx_pko_reg_bist_result_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_35_63:29;
-                uint64_t csr:1;
-                uint64_t iob:1;
-                uint64_t out_dat:1;
-                uint64_t out_ctl:3;
-                uint64_t out_sta:1;
-                uint64_t out_wif:1;
-                uint64_t prt_chk:3;
-                uint64_t prt_nxt:1;
-                uint64_t prt_psb:8;
-                uint64_t ncb_inb:2;
-                uint64_t prt_qcb:2;
-                uint64_t prt_qsb:3;
-                uint64_t prt_ctl:2;
-                uint64_t dat_dat:2;
-                uint64_t dat_ptr:4;
-#else
-                uint64_t dat_ptr:4;
-                uint64_t dat_dat:2;
-                uint64_t prt_ctl:2;
-                uint64_t prt_qsb:3;
-                uint64_t prt_qcb:2;
-                uint64_t ncb_inb:2;
-                uint64_t prt_psb:8;
-                uint64_t prt_nxt:1;
-                uint64_t prt_chk:3;
-                uint64_t out_wif:1;
-                uint64_t out_sta:1;
-                uint64_t out_ctl:3;
-                uint64_t out_dat:1;
-                uint64_t iob:1;
-                uint64_t csr:1;
-                uint64_t reserved_35_63:29;
-#endif
-        } cn52xx;
-        struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
-        struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
-        struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
-        struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
-        struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
-        struct cvmx_pko_reg_bist_result_cn52xx cn61xx;
-        struct cvmx_pko_reg_bist_result_cn52xx cn63xx;
-        struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1;
-        struct cvmx_pko_reg_bist_result_cn52xx cn66xx;
-        struct cvmx_pko_reg_bist_result_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_36_63:28;
-                uint64_t crc:1;
-                uint64_t csr:1;
-                uint64_t iob:1;
-                uint64_t out_dat:1;
-                uint64_t reserved_31_31:1;
-                uint64_t out_ctl:2;
-                uint64_t out_sta:1;
-                uint64_t out_wif:1;
-                uint64_t prt_chk:3;
-                uint64_t prt_nxt:1;
-                uint64_t prt_psb7:1;
-                uint64_t reserved_21_21:1;
-                uint64_t prt_psb:6;
-                uint64_t ncb_inb:2;
-                uint64_t prt_qcb:2;
-                uint64_t prt_qsb:3;
-                uint64_t prt_ctl:2;
-                uint64_t dat_dat:2;
-                uint64_t dat_ptr:4;
-#else
-                uint64_t dat_ptr:4;
-                uint64_t dat_dat:2;
-                uint64_t prt_ctl:2;
-                uint64_t prt_qsb:3;
-                uint64_t prt_qcb:2;
-                uint64_t ncb_inb:2;
-                uint64_t prt_psb:6;
-                uint64_t reserved_21_21:1;
-                uint64_t prt_psb7:1;
-                uint64_t prt_nxt:1;
-                uint64_t prt_chk:3;
-                uint64_t out_wif:1;
-                uint64_t out_sta:1;
-                uint64_t out_ctl:2;
-                uint64_t reserved_31_31:1;
-                uint64_t out_dat:1;
-                uint64_t iob:1;
-                uint64_t csr:1;
-                uint64_t crc:1;
-                uint64_t reserved_36_63:28;
-#endif
-        } cn68xx;
-        struct cvmx_pko_reg_bist_result_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_35_63:29;
-                uint64_t csr:1;
-                uint64_t iob:1;
-                uint64_t out_dat:1;
-                uint64_t reserved_31_31:1;
-                uint64_t out_ctl:2;
-                uint64_t out_sta:1;
-                uint64_t out_wif:1;
-                uint64_t prt_chk:3;
-                uint64_t prt_nxt:1;
-                uint64_t prt_psb7:1;
-                uint64_t reserved_21_21:1;
-                uint64_t prt_psb:6;
-                uint64_t ncb_inb:2;
-                uint64_t prt_qcb:2;
-                uint64_t prt_qsb:3;
-                uint64_t prt_ctl:2;
-                uint64_t dat_dat:2;
-                uint64_t dat_ptr:4;
-#else
-                uint64_t dat_ptr:4;
-                uint64_t dat_dat:2;
-                uint64_t prt_ctl:2;
-                uint64_t prt_qsb:3;
-                uint64_t prt_qcb:2;
-                uint64_t ncb_inb:2;
-                uint64_t prt_psb:6;
-                uint64_t reserved_21_21:1;
-                uint64_t prt_psb7:1;
-                uint64_t prt_nxt:1;
-                uint64_t prt_chk:3;
-                uint64_t out_wif:1;
-                uint64_t out_sta:1;
-                uint64_t out_ctl:2;
-                uint64_t reserved_31_31:1;
-                uint64_t out_dat:1;
-                uint64_t iob:1;
-                uint64_t csr:1;
-                uint64_t reserved_35_63:29;
-#endif
-        } cn68xxp1;
-        struct cvmx_pko_reg_bist_result_cn52xx cnf71xx;
-};
-
-union cvmx_pko_reg_cmd_buf {
-        uint64_t u64;
-        struct cvmx_pko_reg_cmd_buf_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t pool:3;
-                uint64_t reserved_13_19:7;
-                uint64_t size:13;
-#else
-                uint64_t size:13;
-                uint64_t reserved_13_19:7;
-                uint64_t pool:3;
-                uint64_t reserved_23_63:41;
-#endif
-        } s;
-        struct cvmx_pko_reg_cmd_buf_s cn30xx;
-        struct cvmx_pko_reg_cmd_buf_s cn31xx;
-        struct cvmx_pko_reg_cmd_buf_s cn38xx;
-        struct cvmx_pko_reg_cmd_buf_s cn38xxp2;
-        struct cvmx_pko_reg_cmd_buf_s cn50xx;
-        struct cvmx_pko_reg_cmd_buf_s cn52xx;
-        struct cvmx_pko_reg_cmd_buf_s cn52xxp1;
-        struct cvmx_pko_reg_cmd_buf_s cn56xx;
-        struct cvmx_pko_reg_cmd_buf_s cn56xxp1;
-        struct cvmx_pko_reg_cmd_buf_s cn58xx;
-        struct cvmx_pko_reg_cmd_buf_s cn58xxp1;
-        struct cvmx_pko_reg_cmd_buf_s cn61xx;
-        struct cvmx_pko_reg_cmd_buf_s cn63xx;
-        struct cvmx_pko_reg_cmd_buf_s cn63xxp1;
-        struct cvmx_pko_reg_cmd_buf_s cn66xx;
-        struct cvmx_pko_reg_cmd_buf_s cn68xx;
-        struct cvmx_pko_reg_cmd_buf_s cn68xxp1;
-        struct cvmx_pko_reg_cmd_buf_s cnf71xx;
-};
-
-union cvmx_pko_reg_crc_ctlx {
-        uint64_t u64;
-        struct cvmx_pko_reg_crc_ctlx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t invres:1;
-                uint64_t refin:1;
-#else
-                uint64_t refin:1;
-                uint64_t invres:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_pko_reg_crc_ctlx_s cn38xx;
-        struct cvmx_pko_reg_crc_ctlx_s cn38xxp2;
-        struct cvmx_pko_reg_crc_ctlx_s cn58xx;
-        struct cvmx_pko_reg_crc_ctlx_s cn58xxp1;
-};
-
-union cvmx_pko_reg_crc_enable {
-        uint64_t u64;
-        struct cvmx_pko_reg_crc_enable_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t enable:32;
-#else
-                uint64_t enable:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pko_reg_crc_enable_s cn38xx;
-        struct cvmx_pko_reg_crc_enable_s cn38xxp2;
-        struct cvmx_pko_reg_crc_enable_s cn58xx;
-        struct cvmx_pko_reg_crc_enable_s cn58xxp1;
-};
-
-union cvmx_pko_reg_crc_ivx {
-        uint64_t u64;
-        struct cvmx_pko_reg_crc_ivx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t iv:32;
-#else
-                uint64_t iv:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pko_reg_crc_ivx_s cn38xx;
-        struct cvmx_pko_reg_crc_ivx_s cn38xxp2;
-        struct cvmx_pko_reg_crc_ivx_s cn58xx;
-        struct cvmx_pko_reg_crc_ivx_s cn58xxp1;
-};
-
-union cvmx_pko_reg_debug0 {
-        uint64_t u64;
-        struct cvmx_pko_reg_debug0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t asserts:64;
-#else
-                uint64_t asserts:64;
-#endif
-        } s;
-        struct cvmx_pko_reg_debug0_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t asserts:17;
-#else
-                uint64_t asserts:17;
-                uint64_t reserved_17_63:47;
-#endif
-        } cn30xx;
-        struct cvmx_pko_reg_debug0_cn30xx cn31xx;
-        struct cvmx_pko_reg_debug0_cn30xx cn38xx;
-        struct cvmx_pko_reg_debug0_cn30xx cn38xxp2;
-        struct cvmx_pko_reg_debug0_s cn50xx;
-        struct cvmx_pko_reg_debug0_s cn52xx;
-        struct cvmx_pko_reg_debug0_s cn52xxp1;
-        struct cvmx_pko_reg_debug0_s cn56xx;
-        struct cvmx_pko_reg_debug0_s cn56xxp1;
-        struct cvmx_pko_reg_debug0_s cn58xx;
-        struct cvmx_pko_reg_debug0_s cn58xxp1;
-        struct cvmx_pko_reg_debug0_s cn61xx;
-        struct cvmx_pko_reg_debug0_s cn63xx;
-        struct cvmx_pko_reg_debug0_s cn63xxp1;
-        struct cvmx_pko_reg_debug0_s cn66xx;
-        struct cvmx_pko_reg_debug0_s cn68xx;
-        struct cvmx_pko_reg_debug0_s cn68xxp1;
-        struct cvmx_pko_reg_debug0_s cnf71xx;
-};
-
-union cvmx_pko_reg_debug1 {
-        uint64_t u64;
-        struct cvmx_pko_reg_debug1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t asserts:64;
-#else
-                uint64_t asserts:64;
-#endif
-        } s;
-        struct cvmx_pko_reg_debug1_s cn50xx;
-        struct cvmx_pko_reg_debug1_s cn52xx;
-        struct cvmx_pko_reg_debug1_s cn52xxp1;
-        struct cvmx_pko_reg_debug1_s cn56xx;
-        struct cvmx_pko_reg_debug1_s cn56xxp1;
-        struct cvmx_pko_reg_debug1_s cn58xx;
-        struct cvmx_pko_reg_debug1_s cn58xxp1;
-        struct cvmx_pko_reg_debug1_s cn61xx;
-        struct cvmx_pko_reg_debug1_s cn63xx;
-        struct cvmx_pko_reg_debug1_s cn63xxp1;
-        struct cvmx_pko_reg_debug1_s cn66xx;
-        struct cvmx_pko_reg_debug1_s cn68xx;
-        struct cvmx_pko_reg_debug1_s cn68xxp1;
-        struct cvmx_pko_reg_debug1_s cnf71xx;
-};
-
-union cvmx_pko_reg_debug2 {
-        uint64_t u64;
-        struct cvmx_pko_reg_debug2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t asserts:64;
-#else
-                uint64_t asserts:64;
-#endif
-        } s;
-        struct cvmx_pko_reg_debug2_s cn50xx;
-        struct cvmx_pko_reg_debug2_s cn52xx;
-        struct cvmx_pko_reg_debug2_s cn52xxp1;
-        struct cvmx_pko_reg_debug2_s cn56xx;
-        struct cvmx_pko_reg_debug2_s cn56xxp1;
-        struct cvmx_pko_reg_debug2_s cn58xx;
-        struct cvmx_pko_reg_debug2_s cn58xxp1;
-        struct cvmx_pko_reg_debug2_s cn61xx;
-        struct cvmx_pko_reg_debug2_s cn63xx;
-        struct cvmx_pko_reg_debug2_s cn63xxp1;
-        struct cvmx_pko_reg_debug2_s cn66xx;
-        struct cvmx_pko_reg_debug2_s cn68xx;
-        struct cvmx_pko_reg_debug2_s cn68xxp1;
-        struct cvmx_pko_reg_debug2_s cnf71xx;
-};
-
-union cvmx_pko_reg_debug3 {
-        uint64_t u64;
-        struct cvmx_pko_reg_debug3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t asserts:64;
-#else
-                uint64_t asserts:64;
-#endif
-        } s;
-        struct cvmx_pko_reg_debug3_s cn50xx;
-        struct cvmx_pko_reg_debug3_s cn52xx;
-        struct cvmx_pko_reg_debug3_s cn52xxp1;
-        struct cvmx_pko_reg_debug3_s cn56xx;
-        struct cvmx_pko_reg_debug3_s cn56xxp1;
-        struct cvmx_pko_reg_debug3_s cn58xx;
-        struct cvmx_pko_reg_debug3_s cn58xxp1;
-        struct cvmx_pko_reg_debug3_s cn61xx;
-        struct cvmx_pko_reg_debug3_s cn63xx;
-        struct cvmx_pko_reg_debug3_s cn63xxp1;
-        struct cvmx_pko_reg_debug3_s cn66xx;
-        struct cvmx_pko_reg_debug3_s cn68xx;
-        struct cvmx_pko_reg_debug3_s cn68xxp1;
-        struct cvmx_pko_reg_debug3_s cnf71xx;
-};
-
-union cvmx_pko_reg_debug4 {
-        uint64_t u64;
-        struct cvmx_pko_reg_debug4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t asserts:64;
-#else
-                uint64_t asserts:64;
-#endif
-        } s;
-        struct cvmx_pko_reg_debug4_s cn68xx;
-        struct cvmx_pko_reg_debug4_s cn68xxp1;
-};
-
-union cvmx_pko_reg_engine_inflight {
-        uint64_t u64;
-        struct cvmx_pko_reg_engine_inflight_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t engine15:4;
-                uint64_t engine14:4;
-                uint64_t engine13:4;
-                uint64_t engine12:4;
-                uint64_t engine11:4;
-                uint64_t engine10:4;
-                uint64_t engine9:4;
-                uint64_t engine8:4;
-                uint64_t engine7:4;
-                uint64_t engine6:4;
-                uint64_t engine5:4;
-                uint64_t engine4:4;
-                uint64_t engine3:4;
-                uint64_t engine2:4;
-                uint64_t engine1:4;
-                uint64_t engine0:4;
-#else
-                uint64_t engine0:4;
-                uint64_t engine1:4;
-                uint64_t engine2:4;
-                uint64_t engine3:4;
-                uint64_t engine4:4;
-                uint64_t engine5:4;
-                uint64_t engine6:4;
-                uint64_t engine7:4;
-                uint64_t engine8:4;
-                uint64_t engine9:4;
-                uint64_t engine10:4;
-                uint64_t engine11:4;
-                uint64_t engine12:4;
-                uint64_t engine13:4;
-                uint64_t engine14:4;
-                uint64_t engine15:4;
-#endif
-        } s;
-        struct cvmx_pko_reg_engine_inflight_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_40_63:24;
-                uint64_t engine9:4;
-                uint64_t engine8:4;
-                uint64_t engine7:4;
-                uint64_t engine6:4;
-                uint64_t engine5:4;
-                uint64_t engine4:4;
-                uint64_t engine3:4;
-                uint64_t engine2:4;
-                uint64_t engine1:4;
-                uint64_t engine0:4;
-#else
-                uint64_t engine0:4;
-                uint64_t engine1:4;
-                uint64_t engine2:4;
-                uint64_t engine3:4;
-                uint64_t engine4:4;
-                uint64_t engine5:4;
-                uint64_t engine6:4;
-                uint64_t engine7:4;
-                uint64_t engine8:4;
-                uint64_t engine9:4;
-                uint64_t reserved_40_63:24;
-#endif
-        } cn52xx;
-        struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1;
-        struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx;
-        struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1;
-        struct cvmx_pko_reg_engine_inflight_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t engine13:4;
-                uint64_t engine12:4;
-                uint64_t engine11:4;
-                uint64_t engine10:4;
-                uint64_t engine9:4;
-                uint64_t engine8:4;
-                uint64_t engine7:4;
-                uint64_t engine6:4;
-                uint64_t engine5:4;
-                uint64_t engine4:4;
-                uint64_t engine3:4;
-                uint64_t engine2:4;
-                uint64_t engine1:4;
-                uint64_t engine0:4;
-#else
-                uint64_t engine0:4;
-                uint64_t engine1:4;
-                uint64_t engine2:4;
-                uint64_t engine3:4;
-                uint64_t engine4:4;
-                uint64_t engine5:4;
-                uint64_t engine6:4;
-                uint64_t engine7:4;
-                uint64_t engine8:4;
-                uint64_t engine9:4;
-                uint64_t engine10:4;
-                uint64_t engine11:4;
-                uint64_t engine12:4;
-                uint64_t engine13:4;
-                uint64_t reserved_56_63:8;
-#endif
-        } cn61xx;
-        struct cvmx_pko_reg_engine_inflight_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t engine11:4;
-                uint64_t engine10:4;
-                uint64_t engine9:4;
-                uint64_t engine8:4;
-                uint64_t engine7:4;
-                uint64_t engine6:4;
-                uint64_t engine5:4;
-                uint64_t engine4:4;
-                uint64_t engine3:4;
-                uint64_t engine2:4;
-                uint64_t engine1:4;
-                uint64_t engine0:4;
-#else
-                uint64_t engine0:4;
-                uint64_t engine1:4;
-                uint64_t engine2:4;
-                uint64_t engine3:4;
-                uint64_t engine4:4;
-                uint64_t engine5:4;
-                uint64_t engine6:4;
-                uint64_t engine7:4;
-                uint64_t engine8:4;
-                uint64_t engine9:4;
-                uint64_t engine10:4;
-                uint64_t engine11:4;
-                uint64_t reserved_48_63:16;
-#endif
-        } cn63xx;
-        struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1;
-        struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx;
-        struct cvmx_pko_reg_engine_inflight_s cn68xx;
-        struct cvmx_pko_reg_engine_inflight_s cn68xxp1;
-        struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx;
-};
-
-union cvmx_pko_reg_engine_inflight1 {
-        uint64_t u64;
-        struct cvmx_pko_reg_engine_inflight1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t engine19:4;
-                uint64_t engine18:4;
-                uint64_t engine17:4;
-                uint64_t engine16:4;
-#else
-                uint64_t engine16:4;
-                uint64_t engine17:4;
-                uint64_t engine18:4;
-                uint64_t engine19:4;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pko_reg_engine_inflight1_s cn68xx;
-        struct cvmx_pko_reg_engine_inflight1_s cn68xxp1;
-};
-
-union cvmx_pko_reg_engine_storagex {
-        uint64_t u64;
-        struct cvmx_pko_reg_engine_storagex_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t engine15:4;
-                uint64_t engine14:4;
-                uint64_t engine13:4;
-                uint64_t engine12:4;
-                uint64_t engine11:4;
-                uint64_t engine10:4;
-                uint64_t engine9:4;
-                uint64_t engine8:4;
-                uint64_t engine7:4;
-                uint64_t engine6:4;
-                uint64_t engine5:4;
-                uint64_t engine4:4;
-                uint64_t engine3:4;
-                uint64_t engine2:4;
-                uint64_t engine1:4;
-                uint64_t engine0:4;
-#else
-                uint64_t engine0:4;
-                uint64_t engine1:4;
-                uint64_t engine2:4;
-                uint64_t engine3:4;
-                uint64_t engine4:4;
-                uint64_t engine5:4;
-                uint64_t engine6:4;
-                uint64_t engine7:4;
-                uint64_t engine8:4;
-                uint64_t engine9:4;
-                uint64_t engine10:4;
-                uint64_t engine11:4;
-                uint64_t engine12:4;
-                uint64_t engine13:4;
-                uint64_t engine14:4;
-                uint64_t engine15:4;
-#endif
-        } s;
-        struct cvmx_pko_reg_engine_storagex_s cn68xx;
-        struct cvmx_pko_reg_engine_storagex_s cn68xxp1;
-};
-
-union cvmx_pko_reg_engine_thresh {
-        uint64_t u64;
-        struct cvmx_pko_reg_engine_thresh_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t mask:20;
-#else
-                uint64_t mask:20;
-                uint64_t reserved_20_63:44;
-#endif
-        } s;
-        struct cvmx_pko_reg_engine_thresh_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t mask:10;
-#else
-                uint64_t mask:10;
-                uint64_t reserved_10_63:54;
-#endif
-        } cn52xx;
-        struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1;
-        struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx;
-        struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1;
-        struct cvmx_pko_reg_engine_thresh_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t mask:14;
-#else
-                uint64_t mask:14;
-                uint64_t reserved_14_63:50;
-#endif
-        } cn61xx;
-        struct cvmx_pko_reg_engine_thresh_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t mask:12;
-#else
-                uint64_t mask:12;
-                uint64_t reserved_12_63:52;
-#endif
-        } cn63xx;
-        struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1;
-        struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx;
-        struct cvmx_pko_reg_engine_thresh_s cn68xx;
-        struct cvmx_pko_reg_engine_thresh_s cn68xxp1;
-        struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx;
-};
-
-union cvmx_pko_reg_error {
-        uint64_t u64;
-        struct cvmx_pko_reg_error_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t loopback:1;
-                uint64_t currzero:1;
-                uint64_t doorbell:1;
-                uint64_t parity:1;
-#else
-                uint64_t parity:1;
-                uint64_t doorbell:1;
-                uint64_t currzero:1;
-                uint64_t loopback:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_pko_reg_error_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t doorbell:1;
-                uint64_t parity:1;
-#else
-                uint64_t parity:1;
-                uint64_t doorbell:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } cn30xx;
-        struct cvmx_pko_reg_error_cn30xx cn31xx;
-        struct cvmx_pko_reg_error_cn30xx cn38xx;
-        struct cvmx_pko_reg_error_cn30xx cn38xxp2;
-        struct cvmx_pko_reg_error_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t currzero:1;
-                uint64_t doorbell:1;
-                uint64_t parity:1;
-#else
-                uint64_t parity:1;
-                uint64_t doorbell:1;
-                uint64_t currzero:1;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn50xx;
-        struct cvmx_pko_reg_error_cn50xx cn52xx;
-        struct cvmx_pko_reg_error_cn50xx cn52xxp1;
-        struct cvmx_pko_reg_error_cn50xx cn56xx;
-        struct cvmx_pko_reg_error_cn50xx cn56xxp1;
-        struct cvmx_pko_reg_error_cn50xx cn58xx;
-        struct cvmx_pko_reg_error_cn50xx cn58xxp1;
-        struct cvmx_pko_reg_error_cn50xx cn61xx;
-        struct cvmx_pko_reg_error_cn50xx cn63xx;
-        struct cvmx_pko_reg_error_cn50xx cn63xxp1;
-        struct cvmx_pko_reg_error_cn50xx cn66xx;
-        struct cvmx_pko_reg_error_s cn68xx;
-        struct cvmx_pko_reg_error_s cn68xxp1;
-        struct cvmx_pko_reg_error_cn50xx cnf71xx;
-};
-
-union cvmx_pko_reg_flags {
-        uint64_t u64;
-        struct cvmx_pko_reg_flags_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t dis_perf3:1;
-                uint64_t dis_perf2:1;
-                uint64_t dis_perf1:1;
-                uint64_t dis_perf0:1;
-                uint64_t ena_throttle:1;
-                uint64_t reset:1;
-                uint64_t store_be:1;
-                uint64_t ena_dwb:1;
-                uint64_t ena_pko:1;
-#else
-                uint64_t ena_pko:1;
-                uint64_t ena_dwb:1;
-                uint64_t store_be:1;
-                uint64_t reset:1;
-                uint64_t ena_throttle:1;
-                uint64_t dis_perf0:1;
-                uint64_t dis_perf1:1;
-                uint64_t dis_perf2:1;
-                uint64_t dis_perf3:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_pko_reg_flags_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t reset:1;
-                uint64_t store_be:1;
-                uint64_t ena_dwb:1;
-                uint64_t ena_pko:1;
-#else
-                uint64_t ena_pko:1;
-                uint64_t ena_dwb:1;
-                uint64_t store_be:1;
-                uint64_t reset:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } cn30xx;
-        struct cvmx_pko_reg_flags_cn30xx cn31xx;
-        struct cvmx_pko_reg_flags_cn30xx cn38xx;
-        struct cvmx_pko_reg_flags_cn30xx cn38xxp2;
-        struct cvmx_pko_reg_flags_cn30xx cn50xx;
-        struct cvmx_pko_reg_flags_cn30xx cn52xx;
-        struct cvmx_pko_reg_flags_cn30xx cn52xxp1;
-        struct cvmx_pko_reg_flags_cn30xx cn56xx;
-        struct cvmx_pko_reg_flags_cn30xx cn56xxp1;
-        struct cvmx_pko_reg_flags_cn30xx cn58xx;
-        struct cvmx_pko_reg_flags_cn30xx cn58xxp1;
-        struct cvmx_pko_reg_flags_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t dis_perf3:1;
-                uint64_t dis_perf2:1;
-                uint64_t reserved_4_6:3;
-                uint64_t reset:1;
-                uint64_t store_be:1;
-                uint64_t ena_dwb:1;
-                uint64_t ena_pko:1;
-#else
-                uint64_t ena_pko:1;
-                uint64_t ena_dwb:1;
-                uint64_t store_be:1;
-                uint64_t reset:1;
-                uint64_t reserved_4_6:3;
-                uint64_t dis_perf2:1;
-                uint64_t dis_perf3:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } cn61xx;
-        struct cvmx_pko_reg_flags_cn30xx cn63xx;
-        struct cvmx_pko_reg_flags_cn30xx cn63xxp1;
-        struct cvmx_pko_reg_flags_cn61xx cn66xx;
-        struct cvmx_pko_reg_flags_s cn68xx;
-        struct cvmx_pko_reg_flags_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t dis_perf1:1;
-                uint64_t dis_perf0:1;
-                uint64_t ena_throttle:1;
-                uint64_t reset:1;
-                uint64_t store_be:1;
-                uint64_t ena_dwb:1;
-                uint64_t ena_pko:1;
-#else
-                uint64_t ena_pko:1;
-                uint64_t ena_dwb:1;
-                uint64_t store_be:1;
-                uint64_t reset:1;
-                uint64_t ena_throttle:1;
-                uint64_t dis_perf0:1;
-                uint64_t dis_perf1:1;
-                uint64_t reserved_7_63:57;
-#endif
-        } cn68xxp1;
-        struct cvmx_pko_reg_flags_cn61xx cnf71xx;
-};
-
-union cvmx_pko_reg_gmx_port_mode {
-        uint64_t u64;
-        struct cvmx_pko_reg_gmx_port_mode_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t mode1:3;
-                uint64_t mode0:3;
-#else
-                uint64_t mode0:3;
-                uint64_t mode1:3;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_pko_reg_gmx_port_mode_s cn30xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cn31xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cn38xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2;
-        struct cvmx_pko_reg_gmx_port_mode_s cn50xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cn52xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1;
-        struct cvmx_pko_reg_gmx_port_mode_s cn56xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1;
-        struct cvmx_pko_reg_gmx_port_mode_s cn58xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1;
-        struct cvmx_pko_reg_gmx_port_mode_s cn61xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cn63xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1;
-        struct cvmx_pko_reg_gmx_port_mode_s cn66xx;
-        struct cvmx_pko_reg_gmx_port_mode_s cnf71xx;
-};
-
-union cvmx_pko_reg_int_mask {
-        uint64_t u64;
-        struct cvmx_pko_reg_int_mask_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t loopback:1;
-                uint64_t currzero:1;
-                uint64_t doorbell:1;
-                uint64_t parity:1;
-#else
-                uint64_t parity:1;
-                uint64_t doorbell:1;
-                uint64_t currzero:1;
-                uint64_t loopback:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_pko_reg_int_mask_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t doorbell:1;
-                uint64_t parity:1;
-#else
-                uint64_t parity:1;
-                uint64_t doorbell:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } cn30xx;
-        struct cvmx_pko_reg_int_mask_cn30xx cn31xx;
-        struct cvmx_pko_reg_int_mask_cn30xx cn38xx;
-        struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2;
-        struct cvmx_pko_reg_int_mask_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t currzero:1;
-                uint64_t doorbell:1;
-                uint64_t parity:1;
-#else
-                uint64_t parity:1;
-                uint64_t doorbell:1;
-                uint64_t currzero:1;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn50xx;
-        struct cvmx_pko_reg_int_mask_cn50xx cn52xx;
-        struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1;
-        struct cvmx_pko_reg_int_mask_cn50xx cn56xx;
-        struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1;
-        struct cvmx_pko_reg_int_mask_cn50xx cn58xx;
-        struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1;
-        struct cvmx_pko_reg_int_mask_cn50xx cn61xx;
-        struct cvmx_pko_reg_int_mask_cn50xx cn63xx;
-        struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1;
-        struct cvmx_pko_reg_int_mask_cn50xx cn66xx;
-        struct cvmx_pko_reg_int_mask_s cn68xx;
-        struct cvmx_pko_reg_int_mask_s cn68xxp1;
-        struct cvmx_pko_reg_int_mask_cn50xx cnf71xx;
-};
-
-union cvmx_pko_reg_loopback_bpid {
-        uint64_t u64;
-        struct cvmx_pko_reg_loopback_bpid_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_59_63:5;
-                uint64_t bpid7:6;
-                uint64_t reserved_52_52:1;
-                uint64_t bpid6:6;
-                uint64_t reserved_45_45:1;
-                uint64_t bpid5:6;
-                uint64_t reserved_38_38:1;
-                uint64_t bpid4:6;
-                uint64_t reserved_31_31:1;
-                uint64_t bpid3:6;
-                uint64_t reserved_24_24:1;
-                uint64_t bpid2:6;
-                uint64_t reserved_17_17:1;
-                uint64_t bpid1:6;
-                uint64_t reserved_10_10:1;
-                uint64_t bpid0:6;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t bpid0:6;
-                uint64_t reserved_10_10:1;
-                uint64_t bpid1:6;
-                uint64_t reserved_17_17:1;
-                uint64_t bpid2:6;
-                uint64_t reserved_24_24:1;
-                uint64_t bpid3:6;
-                uint64_t reserved_31_31:1;
-                uint64_t bpid4:6;
-                uint64_t reserved_38_38:1;
-                uint64_t bpid5:6;
-                uint64_t reserved_45_45:1;
-                uint64_t bpid6:6;
-                uint64_t reserved_52_52:1;
-                uint64_t bpid7:6;
-                uint64_t reserved_59_63:5;
-#endif
-        } s;
-        struct cvmx_pko_reg_loopback_bpid_s cn68xx;
-        struct cvmx_pko_reg_loopback_bpid_s cn68xxp1;
-};
-
-union cvmx_pko_reg_loopback_pkind {
-        uint64_t u64;
-        struct cvmx_pko_reg_loopback_pkind_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_59_63:5;
-                uint64_t pkind7:6;
-                uint64_t reserved_52_52:1;
-                uint64_t pkind6:6;
-                uint64_t reserved_45_45:1;
-                uint64_t pkind5:6;
-                uint64_t reserved_38_38:1;
-                uint64_t pkind4:6;
-                uint64_t reserved_31_31:1;
-                uint64_t pkind3:6;
-                uint64_t reserved_24_24:1;
-                uint64_t pkind2:6;
-                uint64_t reserved_17_17:1;
-                uint64_t pkind1:6;
-                uint64_t reserved_10_10:1;
-                uint64_t pkind0:6;
-                uint64_t num_ports:4;
-#else
-                uint64_t num_ports:4;
-                uint64_t pkind0:6;
-                uint64_t reserved_10_10:1;
-                uint64_t pkind1:6;
-                uint64_t reserved_17_17:1;
-                uint64_t pkind2:6;
-                uint64_t reserved_24_24:1;
-                uint64_t pkind3:6;
-                uint64_t reserved_31_31:1;
-                uint64_t pkind4:6;
-                uint64_t reserved_38_38:1;
-                uint64_t pkind5:6;
-                uint64_t reserved_45_45:1;
-                uint64_t pkind6:6;
-                uint64_t reserved_52_52:1;
-                uint64_t pkind7:6;
-                uint64_t reserved_59_63:5;
-#endif
-        } s;
-        struct cvmx_pko_reg_loopback_pkind_s cn68xx;
-        struct cvmx_pko_reg_loopback_pkind_s cn68xxp1;
-};
-
-union cvmx_pko_reg_min_pkt {
-        uint64_t u64;
-        struct cvmx_pko_reg_min_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t size7:8;
-                uint64_t size6:8;
-                uint64_t size5:8;
-                uint64_t size4:8;
-                uint64_t size3:8;
-                uint64_t size2:8;
-                uint64_t size1:8;
-                uint64_t size0:8;
-#else
-                uint64_t size0:8;
-                uint64_t size1:8;
-                uint64_t size2:8;
-                uint64_t size3:8;
-                uint64_t size4:8;
-                uint64_t size5:8;
-                uint64_t size6:8;
-                uint64_t size7:8;
-#endif
-        } s;
-        struct cvmx_pko_reg_min_pkt_s cn68xx;
-        struct cvmx_pko_reg_min_pkt_s cn68xxp1;
-};
-
-union cvmx_pko_reg_preempt {
-        uint64_t u64;
-        struct cvmx_pko_reg_preempt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t min_size:16;
-#else
-                uint64_t min_size:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pko_reg_preempt_s cn52xx;
-        struct cvmx_pko_reg_preempt_s cn52xxp1;
-        struct cvmx_pko_reg_preempt_s cn56xx;
-        struct cvmx_pko_reg_preempt_s cn56xxp1;
-        struct cvmx_pko_reg_preempt_s cn61xx;
-        struct cvmx_pko_reg_preempt_s cn63xx;
-        struct cvmx_pko_reg_preempt_s cn63xxp1;
-        struct cvmx_pko_reg_preempt_s cn66xx;
-        struct cvmx_pko_reg_preempt_s cn68xx;
-        struct cvmx_pko_reg_preempt_s cn68xxp1;
-        struct cvmx_pko_reg_preempt_s cnf71xx;
-};
-
-union cvmx_pko_reg_queue_mode {
-        uint64_t u64;
-        struct cvmx_pko_reg_queue_mode_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t mode:2;
-#else
-                uint64_t mode:2;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_pko_reg_queue_mode_s cn30xx;
-        struct cvmx_pko_reg_queue_mode_s cn31xx;
-        struct cvmx_pko_reg_queue_mode_s cn38xx;
-        struct cvmx_pko_reg_queue_mode_s cn38xxp2;
-        struct cvmx_pko_reg_queue_mode_s cn50xx;
-        struct cvmx_pko_reg_queue_mode_s cn52xx;
-        struct cvmx_pko_reg_queue_mode_s cn52xxp1;
-        struct cvmx_pko_reg_queue_mode_s cn56xx;
-        struct cvmx_pko_reg_queue_mode_s cn56xxp1;
-        struct cvmx_pko_reg_queue_mode_s cn58xx;
-        struct cvmx_pko_reg_queue_mode_s cn58xxp1;
-        struct cvmx_pko_reg_queue_mode_s cn61xx;
-        struct cvmx_pko_reg_queue_mode_s cn63xx;
-        struct cvmx_pko_reg_queue_mode_s cn63xxp1;
-        struct cvmx_pko_reg_queue_mode_s cn66xx;
-        struct cvmx_pko_reg_queue_mode_s cn68xx;
-        struct cvmx_pko_reg_queue_mode_s cn68xxp1;
-        struct cvmx_pko_reg_queue_mode_s cnf71xx;
-};
-
-union cvmx_pko_reg_queue_preempt {
-        uint64_t u64;
-        struct cvmx_pko_reg_queue_preempt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t preemptee:1;
-                uint64_t preempter:1;
-#else
-                uint64_t preempter:1;
-                uint64_t preemptee:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_pko_reg_queue_preempt_s cn52xx;
-        struct cvmx_pko_reg_queue_preempt_s cn52xxp1;
-        struct cvmx_pko_reg_queue_preempt_s cn56xx;
-        struct cvmx_pko_reg_queue_preempt_s cn56xxp1;
-        struct cvmx_pko_reg_queue_preempt_s cn61xx;
-        struct cvmx_pko_reg_queue_preempt_s cn63xx;
-        struct cvmx_pko_reg_queue_preempt_s cn63xxp1;
-        struct cvmx_pko_reg_queue_preempt_s cn66xx;
-        struct cvmx_pko_reg_queue_preempt_s cn68xx;
-        struct cvmx_pko_reg_queue_preempt_s cn68xxp1;
-        struct cvmx_pko_reg_queue_preempt_s cnf71xx;
-};
-
-union cvmx_pko_reg_queue_ptrs1 {
-        uint64_t u64;
-        struct cvmx_pko_reg_queue_ptrs1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t idx3:1;
-                uint64_t qid7:1;
-#else
-                uint64_t qid7:1;
-                uint64_t idx3:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_pko_reg_queue_ptrs1_s cn50xx;
-        struct cvmx_pko_reg_queue_ptrs1_s cn52xx;
-        struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1;
-        struct cvmx_pko_reg_queue_ptrs1_s cn56xx;
-        struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1;
-        struct cvmx_pko_reg_queue_ptrs1_s cn58xx;
-        struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1;
-        struct cvmx_pko_reg_queue_ptrs1_s cn61xx;
-        struct cvmx_pko_reg_queue_ptrs1_s cn63xx;
-        struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1;
-        struct cvmx_pko_reg_queue_ptrs1_s cn66xx;
-        struct cvmx_pko_reg_queue_ptrs1_s cnf71xx;
-};
-
-union cvmx_pko_reg_read_idx {
-        uint64_t u64;
-        struct cvmx_pko_reg_read_idx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t inc:8;
-                uint64_t index:8;
-#else
-                uint64_t index:8;
-                uint64_t inc:8;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_pko_reg_read_idx_s cn30xx;
-        struct cvmx_pko_reg_read_idx_s cn31xx;
-        struct cvmx_pko_reg_read_idx_s cn38xx;
-        struct cvmx_pko_reg_read_idx_s cn38xxp2;
-        struct cvmx_pko_reg_read_idx_s cn50xx;
-        struct cvmx_pko_reg_read_idx_s cn52xx;
-        struct cvmx_pko_reg_read_idx_s cn52xxp1;
-        struct cvmx_pko_reg_read_idx_s cn56xx;
-        struct cvmx_pko_reg_read_idx_s cn56xxp1;
-        struct cvmx_pko_reg_read_idx_s cn58xx;
-        struct cvmx_pko_reg_read_idx_s cn58xxp1;
-        struct cvmx_pko_reg_read_idx_s cn61xx;
-        struct cvmx_pko_reg_read_idx_s cn63xx;
-        struct cvmx_pko_reg_read_idx_s cn63xxp1;
-        struct cvmx_pko_reg_read_idx_s cn66xx;
-        struct cvmx_pko_reg_read_idx_s cn68xx;
-        struct cvmx_pko_reg_read_idx_s cn68xxp1;
-        struct cvmx_pko_reg_read_idx_s cnf71xx;
-};
-
-union cvmx_pko_reg_throttle {
-        uint64_t u64;
-        struct cvmx_pko_reg_throttle_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t int_mask:32;
-#else
-                uint64_t int_mask:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_pko_reg_throttle_s cn68xx;
-        struct cvmx_pko_reg_throttle_s cn68xxp1;
-};
-
-union cvmx_pko_reg_timestamp {
-        uint64_t u64;
-        struct cvmx_pko_reg_timestamp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t wqe_word:4;
-#else
-                uint64_t wqe_word:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_pko_reg_timestamp_s cn61xx;
-        struct cvmx_pko_reg_timestamp_s cn63xx;
-        struct cvmx_pko_reg_timestamp_s cn63xxp1;
-        struct cvmx_pko_reg_timestamp_s cn66xx;
-        struct cvmx_pko_reg_timestamp_s cn68xx;
-        struct cvmx_pko_reg_timestamp_s cn68xxp1;
-        struct cvmx_pko_reg_timestamp_s cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
deleted file mode 100644
index c6daeedf1f8..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-pko.h
+++ /dev/null
@@ -1,610 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- *
- * Interface to the hardware Packet Output unit.
- *
- * Starting with SDK 1.7.0, the PKO output functions now support
- * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
- * function similarly to previous SDKs by using POW atomic tags
- * to preserve ordering and exclusivity. As a new option, you
- * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
- * memory based locking instead. This locking has the advantage
- * of not affecting the tag state but doesn't preserve packet
- * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
- * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
- * with hand tuned fast path code.
- *
- * Some of other SDK differences visible to the command command
- * queuing:
- * - PKO indexes are no longer stored in the FAU. A large
- *   percentage of the FAU register block used to be tied up
- *   maintaining PKO queue pointers. These are now stored in a
- *   global named block.
- * - The PKO <b>use_locking</b> parameter can now have a global
- *   effect. Since all application use the same named block,
- *   queue locking correctly applies across all operating
- *   systems when using CVMX_PKO_LOCK_CMD_QUEUE.
- * - PKO 3 word commands are now supported. Use
- *   cvmx_pko_send_packet_finish3().
- *
- */
-
-#ifndef __CVMX_PKO_H__
-#define __CVMX_PKO_H__
-
-#include <asm/octeon/cvmx-fpa.h>
-#include <asm/octeon/cvmx-pow.h>
-#include <asm/octeon/cvmx-cmd-queue.h>
-#include <asm/octeon/cvmx-pko-defs.h>
-
-/* Adjust the command buffer size by 1 word so that in the case of using only
- * two word PKO commands no command words stradle buffers.  The useful values
- * for this are 0 and 1. */
-#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
-
-#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
-#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
-        OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
-        OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
-                (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
-                OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
-#define CVMX_PKO_NUM_OUTPUT_PORTS       40
-/* use this for queues that are not used */
-#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
-#define CVMX_PKO_QUEUE_STATIC_PRIORITY  9
-#define CVMX_PKO_ILLEGAL_QUEUE  0xFFFF
-#define CVMX_PKO_MAX_QUEUE_DEPTH 0
-
-typedef enum {
-        CVMX_PKO_SUCCESS,
-        CVMX_PKO_INVALID_PORT,
-        CVMX_PKO_INVALID_QUEUE,
-        CVMX_PKO_INVALID_PRIORITY,
-        CVMX_PKO_NO_MEMORY,
-        CVMX_PKO_PORT_ALREADY_SETUP,
-        CVMX_PKO_CMD_QUEUE_INIT_ERROR
-} cvmx_pko_status_t;
-
-/**
- * This enumeration represents the differnet locking modes supported by PKO.
- */
-typedef enum {
-        /*
-         * PKO doesn't do any locking. It is the responsibility of the
-         * application to make sure that no other core is accessing
-         * the same queue at the same time
-         */
-        CVMX_PKO_LOCK_NONE = 0,
-        /*
-         * PKO performs an atomic tagswitch to insure exclusive access
-         * to the output queue. This will maintain packet ordering on
-         * output.
-         */
-        CVMX_PKO_LOCK_ATOMIC_TAG = 1,
-        /*
-         * PKO uses the common command queue locks to insure exclusive
-         * access to the output queue. This is a memory based
-         * ll/sc. This is the most portable locking mechanism.
-         */
-        CVMX_PKO_LOCK_CMD_QUEUE = 2,
-} cvmx_pko_lock_t;
-
-typedef struct {
-        uint32_t packets;
-        uint64_t octets;
-        uint64_t doorbell;
-} cvmx_pko_port_status_t;
-
-/**
- * This structure defines the address to use on a packet enqueue
- */
-typedef union {
-        uint64_t u64;
-        struct {
-                /* Must CVMX_IO_SEG */
-                uint64_t mem_space:2;
-                /* Must be zero */
-                uint64_t reserved:13;
-                /* Must be one */
-                uint64_t is_io:1;
-                /* The ID of the device on the non-coherent bus */
-                uint64_t did:8;
-                /* Must be zero */
-                uint64_t reserved2:4;
-                /* Must be zero */
-                uint64_t reserved3:18;
-                /*
-                 * The hardware likes to have the output port in
-                 * addition to the output queue,
-                 */
-                uint64_t port:6;
-                /*
-                 * The output queue to send the packet to (0-127 are
-                 * legal)
-                 */
-                uint64_t queue:9;
-                /* Must be zero */
-                uint64_t reserved4:3;
-        } s;
-} cvmx_pko_doorbell_address_t;
-
-/**
- * Structure of the first packet output command word.
- */
-typedef union {
-        uint64_t u64;
-        struct {
-                /*
-                 * The size of the reg1 operation - could be 8, 16,
-                 * 32, or 64 bits.
-                 */
-                uint64_t size1:2;
-                /*
-                 * The size of the reg0 operation - could be 8, 16,
-                 * 32, or 64 bits.
-                 */
-                uint64_t size0:2;
-                /*
-                 * If set, subtract 1, if clear, subtract packet
-                 * size.
-                 */
-                uint64_t subone1:1;
-                /*
-                 * The register, subtract will be done if reg1 is
-                 * non-zero.
-                 */
-                uint64_t reg1:11;
-                /* If set, subtract 1, if clear, subtract packet size */
-                uint64_t subone0:1;
-                /* The register, subtract will be done if reg0 is non-zero */
-                uint64_t reg0:11;
-                /*
-                 * When set, interpret segment pointer and segment
-                 * bytes in little endian order.
-                 */
-                uint64_t le:1;
-                /*
-                 * When set, packet data not allocated in L2 cache by
-                 * PKO.
-                 */
-                uint64_t n2:1;
-                /*
-                 * If set and rsp is set, word3 contains a pointer to
-                 * a work queue entry.
-                 */
-                uint64_t wqp:1;
-                /* If set, the hardware will send a response when done */
-                uint64_t rsp:1;
-                /*
-                 * If set, the supplied pkt_ptr is really a pointer to
-                 * a list of pkt_ptr's.
-                 */
-                uint64_t gather:1;
-                /*
-                 * If ipoffp1 is non zero, (ipoffp1-1) is the number
-                 * of bytes to IP header, and the hardware will
-                 * calculate and insert the UDP/TCP checksum.
-                 */
-                uint64_t ipoffp1:7;
-                /*
-                 * If set, ignore the I bit (force to zero) from all
-                 * pointer structures.
-                 */
-                uint64_t ignore_i:1;
-                /*
-                 * If clear, the hardware will attempt to free the
-                 * buffers containing the packet.
-                 */
-                uint64_t dontfree:1;
-                /*
-                 * The total number of segs in the packet, if gather
-                 * set, also gather list length.
-                 */
-                uint64_t segs:6;
-                /* Including L2, but no trailing CRC */
-                uint64_t total_bytes:16;
-        } s;
-} cvmx_pko_command_word0_t;
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-/**
- * Definition of internal state for Packet output processing
- */
-typedef struct {
-        /* ptr to start of buffer, offset kept in FAU reg */
-        uint64_t *start_ptr;
-} cvmx_pko_state_elem_t;
-
-/**
- * Call before any other calls to initialize the packet
- * output system.
- */
-extern void cvmx_pko_initialize_global(void);
-extern int cvmx_pko_initialize_local(void);
-
-/**
- * Enables the packet output hardware. It must already be
- * configured.
- */
-extern void cvmx_pko_enable(void);
-
-/**
- * Disables the packet output. Does not affect any configuration.
- */
-extern void cvmx_pko_disable(void);
-
-/**
- * Shutdown and free resources required by packet output.
- */
-
-extern void cvmx_pko_shutdown(void);
-
-/**
- * Configure a output port and the associated queues for use.
- *
- * @port:       Port to configure.
- * @base_queue: First queue number to associate with this port.
- * @num_queues: Number of queues t oassociate with this port
- * @priority:   Array of priority levels for each queue. Values are
- *                   allowed to be 1-8. A value of 8 get 8 times the traffic
- *                   of a value of 1. There must be num_queues elements in the
- *                   array.
- */
-extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
-                                              uint64_t base_queue,
-                                              uint64_t num_queues,
-                                              const uint64_t priority[]);
-
-/**
- * Ring the packet output doorbell. This tells the packet
- * output hardware that "len" command words have been added
- * to its pending list.  This command includes the required
- * CVMX_SYNCWS before the doorbell ring.
- *
- * @port:   Port the packet is for
- * @queue:  Queue the packet is for
- * @len:    Length of the command in 64 bit words
- */
-static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
-                                     uint64_t len)
-{
-        cvmx_pko_doorbell_address_t ptr;
-
-        ptr.u64 = 0;
-        ptr.s.mem_space = CVMX_IO_SEG;
-        ptr.s.did = CVMX_OCT_DID_PKT_SEND;
-        ptr.s.is_io = 1;
-        ptr.s.port = port;
-        ptr.s.queue = queue;
-        /*
-         * Need to make sure output queue data is in DRAM before
-         * doorbell write.
-         */
-        CVMX_SYNCWS;
-        cvmx_write_io(ptr.u64, len);
-}
-
-/**
- * Prepare to send a packet.  This may initiate a tag switch to
- * get exclusive access to the output queue structure, and
- * performs other prep work for the packet send operation.
- *
- * cvmx_pko_send_packet_finish() MUST be called after this function is called,
- * and must be called with the same port/queue/use_locking arguments.
- *
- * The use_locking parameter allows the caller to use three
- * possible locking modes.
- * - CVMX_PKO_LOCK_NONE
- *      - PKO doesn't do any locking. It is the responsibility
- *          of the application to make sure that no other core
- *          is accessing the same queue at the same time.
- * - CVMX_PKO_LOCK_ATOMIC_TAG
- *      - PKO performs an atomic tagswitch to insure exclusive
- *          access to the output queue. This will maintain
- *          packet ordering on output.
- * - CVMX_PKO_LOCK_CMD_QUEUE
- *      - PKO uses the common command queue locks to insure
- *          exclusive access to the output queue. This is a
- *          memory based ll/sc. This is the most portable
- *          locking mechanism.
- *
- * NOTE: If atomic locking is used, the POW entry CANNOT be
- * descheduled, as it does not contain a valid WQE pointer.
- *
- * @port:   Port to send it on
- * @queue:  Queue to use
- * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
- *               CVMX_PKO_LOCK_CMD_QUEUE
- */
-
-static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
-                                                cvmx_pko_lock_t use_locking)
-{
-        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) {
-                /*
-                 * Must do a full switch here to handle all cases.  We
-                 * use a fake WQE pointer, as the POW does not access
-                 * this memory.  The WQE pointer and group are only
-                 * used if this work is descheduled, which is not
-                 * supported by the
-                 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
-                 * combination.  Note that this is a special case in
-                 * which these fake values can be used - this is not a
-                 * general technique.
-                 */
-                uint32_t tag =
-                    CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT |
-                    CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT |
-                    (CVMX_TAG_SUBGROUP_MASK & queue);
-                cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag,
-                                     CVMX_POW_TAG_TYPE_ATOMIC, 0);
-        }
-}
-
-/**
- * Complete packet output. cvmx_pko_send_packet_prepare() must be
- * called exactly once before this, and the same parameters must be
- * passed to both cvmx_pko_send_packet_prepare() and
- * cvmx_pko_send_packet_finish().
- *
- * @port:   Port to send it on
- * @queue:  Queue to use
- * @pko_command:
- *               PKO HW command word
- * @packet: Packet to send
- * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
- *               CVMX_PKO_LOCK_CMD_QUEUE
- *
- * Returns returns CVMX_PKO_SUCCESS on success, or error code on
- * failure of output
- */
-static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
-        uint64_t port,
-        uint64_t queue,
-        cvmx_pko_command_word0_t pko_command,
-        union cvmx_buf_ptr packet,
-        cvmx_pko_lock_t use_locking)
-{
-        cvmx_cmd_queue_result_t result;
-        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
-                cvmx_pow_tag_sw_wait();
-        result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
-                                       (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
-                                       pko_command.u64, packet.u64);
-        if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
-                cvmx_pko_doorbell(port, queue, 2);
-                return CVMX_PKO_SUCCESS;
-        } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
-                   || (result == CVMX_CMD_QUEUE_FULL)) {
-                return CVMX_PKO_NO_MEMORY;
-        } else {
-                return CVMX_PKO_INVALID_QUEUE;
-        }
-}
-
-/**
- * Complete packet output. cvmx_pko_send_packet_prepare() must be
- * called exactly once before this, and the same parameters must be
- * passed to both cvmx_pko_send_packet_prepare() and
- * cvmx_pko_send_packet_finish().
- *
- * @port:   Port to send it on
- * @queue:  Queue to use
- * @pko_command:
- *               PKO HW command word
- * @packet: Packet to send
- * @addr: Plysical address of a work queue entry or physical address
- *        to zero on complete.
- * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
- *               CVMX_PKO_LOCK_CMD_QUEUE
- *
- * Returns returns CVMX_PKO_SUCCESS on success, or error code on
- * failure of output
- */
-static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
-        uint64_t port,
-        uint64_t queue,
-        cvmx_pko_command_word0_t pko_command,
-        union cvmx_buf_ptr packet,
-        uint64_t addr,
-        cvmx_pko_lock_t use_locking)
-{
-        cvmx_cmd_queue_result_t result;
-        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
-                cvmx_pow_tag_sw_wait();
-        result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
-                                       (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
-                                       pko_command.u64, packet.u64, addr);
-        if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
-                cvmx_pko_doorbell(port, queue, 3);
-                return CVMX_PKO_SUCCESS;
-        } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
-                   || (result == CVMX_CMD_QUEUE_FULL)) {
-                return CVMX_PKO_NO_MEMORY;
-        } else {
-                return CVMX_PKO_INVALID_QUEUE;
-        }
-}
-
-/**
- * Return the pko output queue associated with a port and a specific core.
- * In normal mode (PKO lockless operation is disabled), the value returned
- * is the base queue.
- *
- * @port:   Port number
- * @core:   Core to get queue for
- *
- * Returns Core-specific output queue
- */
-static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
-{
-#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
-#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
-#endif
-#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
-#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
-#endif
-
-        if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
-                return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
-        else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
-                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
-                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port -
-                                                           16) *
-                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
-        else if ((port >= 32) && (port < 36))
-                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
-                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
-                    CVMX_PKO_MAX_PORTS_INTERFACE1 *
-                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port -
-                                                           32) *
-                    CVMX_PKO_QUEUES_PER_PORT_PCI;
-        else if ((port >= 36) && (port < 40))
-                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
-                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
-                    CVMX_PKO_MAX_PORTS_INTERFACE1 *
-                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
-                    4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port -
-                                                        36) *
-                    CVMX_PKO_QUEUES_PER_PORT_LOOP;
-        else
-                /* Given the limit on the number of ports we can map to
-                 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
-                 * divided among all cores), the remaining unmapped ports
-                 * are assigned an illegal queue number */
-                return CVMX_PKO_ILLEGAL_QUEUE;
-}
-
-/**
- * For a given port number, return the base pko output queue
- * for the port.
- *
- * @port:   Port number
- * Returns Base output queue
- */
-static inline int cvmx_pko_get_base_queue(int port)
-{
-        return cvmx_pko_get_base_queue_per_core(port, 0);
-}
-
-/**
- * For a given port number, return the number of pko output queues.
- *
- * @port:   Port number
- * Returns Number of output queues
- */
-static inline int cvmx_pko_get_num_queues(int port)
-{
-        if (port < 16)
-                return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
-        else if (port < 32)
-                return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
-        else if (port < 36)
-                return CVMX_PKO_QUEUES_PER_PORT_PCI;
-        else if (port < 40)
-                return CVMX_PKO_QUEUES_PER_PORT_LOOP;
-        else
-                return 0;
-}
-
-/**
- * Get the status counters for a port.
- *
- * @port_num: Port number to get statistics for.
- * @clear:    Set to 1 to clear the counters after they are read
- * @status:   Where to put the results.
- */
-static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
-                                            cvmx_pko_port_status_t *status)
-{
-        union cvmx_pko_reg_read_idx pko_reg_read_idx;
-        union cvmx_pko_mem_count0 pko_mem_count0;
-        union cvmx_pko_mem_count1 pko_mem_count1;
-
-        pko_reg_read_idx.u64 = 0;
-        pko_reg_read_idx.s.index = port_num;
-        cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
-
-        pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
-        status->packets = pko_mem_count0.s.count;
-        if (clear) {
-                pko_mem_count0.s.count = port_num;
-                cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
-        }
-
-        pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
-        status->octets = pko_mem_count1.s.count;
-        if (clear) {
-                pko_mem_count1.s.count = port_num;
-                cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
-        }
-
-        if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
-                union cvmx_pko_mem_debug9 debug9;
-                pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
-                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
-                debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
-                status->doorbell = debug9.cn38xx.doorbell;
-        } else {
-                union cvmx_pko_mem_debug8 debug8;
-                pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
-                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
-                debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
-                status->doorbell = debug8.cn58xx.doorbell;
-        }
-}
-
-/**
- * Rate limit a PKO port to a max packets/sec. This function is only
- * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
- *
- * @port:      Port to rate limit
- * @packets_s: Maximum packet/sec
- * @burst:     Maximum number of packets to burst in a row before rate
- *                  limiting cuts in.
- *
- * Returns Zero on success, negative on failure
- */
-extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
-
-/**
- * Rate limit a PKO port to a max bits/sec. This function is only
- * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
- *
- * @port:   Port to rate limit
- * @bits_s: PKO rate limit in bits/sec
- * @burst:  Maximum number of bits to burst before rate
- *               limiting cuts in.
- *
- * Returns Zero on success, negative on failure
- */
-extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
-
-#endif /* __CVMX_PKO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
index 9020ef44373..39fd75b03f7 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -55,18 +55,11 @@
 union cvmx_pow_bist_stat {
         uint64_t u64;
         struct cvmx_pow_bist_stat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t pp:16;
                 uint64_t reserved_0_15:16;
-#else
-                uint64_t reserved_0_15:16;
-                uint64_t pp:16;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_bist_stat_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t pp:1;
                 uint64_t reserved_9_15:7;
@@ -79,23 +72,8 @@ union cvmx_pow_bist_stat {
                 uint64_t nbr0:1;
                 uint64_t pend:1;
                 uint64_t adr:1;
-#else
-                uint64_t adr:1;
-                uint64_t pend:1;
-                uint64_t nbr0:1;
-                uint64_t nbr1:1;
-                uint64_t fidx:1;
-                uint64_t index:1;
-                uint64_t nbt0:1;
-                uint64_t nbt1:1;
-                uint64_t cam:1;
-                uint64_t reserved_9_15:7;
-                uint64_t pp:1;
-                uint64_t reserved_17_63:47;
-#endif
         } cn30xx;
         struct cvmx_pow_bist_stat_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t pp:2;
                 uint64_t reserved_9_15:7;
@@ -108,23 +86,8 @@ union cvmx_pow_bist_stat {
                 uint64_t nbr0:1;
                 uint64_t pend:1;
                 uint64_t adr:1;
-#else
-                uint64_t adr:1;
-                uint64_t pend:1;
-                uint64_t nbr0:1;
-                uint64_t nbr1:1;
-                uint64_t fidx:1;
-                uint64_t index:1;
-                uint64_t nbt0:1;
-                uint64_t nbt1:1;
-                uint64_t cam:1;
-                uint64_t reserved_9_15:7;
-                uint64_t pp:2;
-                uint64_t reserved_18_63:46;
-#endif
         } cn31xx;
         struct cvmx_pow_bist_stat_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t pp:16;
                 uint64_t reserved_10_15:6;
@@ -138,26 +101,10 @@ union cvmx_pow_bist_stat {
                 uint64_t pend0:1;
                 uint64_t adr1:1;
                 uint64_t adr0:1;
-#else
-                uint64_t adr0:1;
-                uint64_t adr1:1;
-                uint64_t pend0:1;
-                uint64_t pend1:1;
-                uint64_t nbr0:1;
-                uint64_t nbr1:1;
-                uint64_t fidx:1;
-                uint64_t index:1;
-                uint64_t nbt:1;
-                uint64_t cam:1;
-                uint64_t reserved_10_15:6;
-                uint64_t pp:16;
-                uint64_t reserved_32_63:32;
-#endif
         } cn38xx;
         struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
         struct cvmx_pow_bist_stat_cn31xx cn50xx;
         struct cvmx_pow_bist_stat_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t pp:4;
                 uint64_t reserved_9_15:7;
@@ -170,24 +117,9 @@ union cvmx_pow_bist_stat {
                 uint64_t nbr0:1;
                 uint64_t pend:1;
                 uint64_t adr:1;
-#else
-                uint64_t adr:1;
-                uint64_t pend:1;
-                uint64_t nbr0:1;
-                uint64_t nbr1:1;
-                uint64_t fidx:1;
-                uint64_t index:1;
-                uint64_t nbt0:1;
-                uint64_t nbt1:1;
-                uint64_t cam:1;
-                uint64_t reserved_9_15:7;
-                uint64_t pp:4;
-                uint64_t reserved_20_63:44;
-#endif
         } cn52xx;
         struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
         struct cvmx_pow_bist_stat_cn56xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t pp:12;
                 uint64_t reserved_10_15:6;
@@ -201,52 +133,11 @@ union cvmx_pow_bist_stat {
                 uint64_t pend0:1;
                 uint64_t adr1:1;
                 uint64_t adr0:1;
-#else
-                uint64_t adr0:1;
-                uint64_t adr1:1;
-                uint64_t pend0:1;
-                uint64_t pend1:1;
-                uint64_t nbr0:1;
-                uint64_t nbr1:1;
-                uint64_t fidx:1;
-                uint64_t index:1;
-                uint64_t nbt:1;
-                uint64_t cam:1;
-                uint64_t reserved_10_15:6;
-                uint64_t pp:12;
-                uint64_t reserved_28_63:36;
-#endif
         } cn56xx;
         struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
         struct cvmx_pow_bist_stat_cn38xx cn58xx;
         struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
-        struct cvmx_pow_bist_stat_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t pp:4;
-                uint64_t reserved_12_15:4;
-                uint64_t cam:1;
-                uint64_t nbr:3;
-                uint64_t nbt:4;
-                uint64_t index:1;
-                uint64_t fidx:1;
-                uint64_t pend:1;
-                uint64_t adr:1;
-#else
-                uint64_t adr:1;
-                uint64_t pend:1;
-                uint64_t fidx:1;
-                uint64_t index:1;
-                uint64_t nbt:4;
-                uint64_t nbr:3;
-                uint64_t cam:1;
-                uint64_t reserved_12_15:4;
-                uint64_t pp:4;
-                uint64_t reserved_20_63:44;
-#endif
-        } cn61xx;
         struct cvmx_pow_bist_stat_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_22_63:42;
                 uint64_t pp:6;
                 uint64_t reserved_12_15:4;
@@ -257,58 +148,15 @@ union cvmx_pow_bist_stat {
                 uint64_t fidx:1;
                 uint64_t pend:1;
                 uint64_t adr:1;
-#else
-                uint64_t adr:1;
-                uint64_t pend:1;
-                uint64_t fidx:1;
-                uint64_t index:1;
-                uint64_t nbt:4;
-                uint64_t nbr:3;
-                uint64_t cam:1;
-                uint64_t reserved_12_15:4;
-                uint64_t pp:6;
-                uint64_t reserved_22_63:42;
-#endif
         } cn63xx;
         struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
-        struct cvmx_pow_bist_stat_cn66xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_26_63:38;
-                uint64_t pp:10;
-                uint64_t reserved_12_15:4;
-                uint64_t cam:1;
-                uint64_t nbr:3;
-                uint64_t nbt:4;
-                uint64_t index:1;
-                uint64_t fidx:1;
-                uint64_t pend:1;
-                uint64_t adr:1;
-#else
-                uint64_t adr:1;
-                uint64_t pend:1;
-                uint64_t fidx:1;
-                uint64_t index:1;
-                uint64_t nbt:4;
-                uint64_t nbr:3;
-                uint64_t cam:1;
-                uint64_t reserved_12_15:4;
-                uint64_t pp:10;
-                uint64_t reserved_26_63:38;
-#endif
-        } cn66xx;
-        struct cvmx_pow_bist_stat_cn61xx cnf71xx;
 };
 
 union cvmx_pow_ds_pc {
         uint64_t u64;
         struct cvmx_pow_ds_pc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t ds_pc:32;
-#else
-                uint64_t ds_pc:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_ds_pc_s cn30xx;
         struct cvmx_pow_ds_pc_s cn31xx;
@@ -321,17 +169,13 @@ union cvmx_pow_ds_pc {
         struct cvmx_pow_ds_pc_s cn56xxp1;
         struct cvmx_pow_ds_pc_s cn58xx;
         struct cvmx_pow_ds_pc_s cn58xxp1;
-        struct cvmx_pow_ds_pc_s cn61xx;
         struct cvmx_pow_ds_pc_s cn63xx;
         struct cvmx_pow_ds_pc_s cn63xxp1;
-        struct cvmx_pow_ds_pc_s cn66xx;
-        struct cvmx_pow_ds_pc_s cnf71xx;
 };
 
 union cvmx_pow_ecc_err {
         uint64_t u64;
         struct cvmx_pow_ecc_err_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_45_63:19;
                 uint64_t iop_ie:13;
                 uint64_t reserved_29_31:3;
@@ -345,25 +189,9 @@ union cvmx_pow_ecc_err {
                 uint64_t sbe_ie:1;
                 uint64_t dbe:1;
                 uint64_t sbe:1;
-#else
-                uint64_t sbe:1;
-                uint64_t dbe:1;
-                uint64_t sbe_ie:1;
-                uint64_t dbe_ie:1;
-                uint64_t syn:5;
-                uint64_t reserved_9_11:3;
-                uint64_t rpe:1;
-                uint64_t rpe_ie:1;
-                uint64_t reserved_14_15:2;
-                uint64_t iop:13;
-                uint64_t reserved_29_31:3;
-                uint64_t iop_ie:13;
-                uint64_t reserved_45_63:19;
-#endif
         } s;
         struct cvmx_pow_ecc_err_s cn30xx;
         struct cvmx_pow_ecc_err_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_14_63:50;
                 uint64_t rpe_ie:1;
                 uint64_t rpe:1;
@@ -373,17 +201,6 @@ union cvmx_pow_ecc_err {
                 uint64_t sbe_ie:1;
                 uint64_t dbe:1;
                 uint64_t sbe:1;
-#else
-                uint64_t sbe:1;
-                uint64_t dbe:1;
-                uint64_t sbe_ie:1;
-                uint64_t dbe_ie:1;
-                uint64_t syn:5;
-                uint64_t reserved_9_11:3;
-                uint64_t rpe:1;
-                uint64_t rpe_ie:1;
-                uint64_t reserved_14_63:50;
-#endif
         } cn31xx;
         struct cvmx_pow_ecc_err_s cn38xx;
         struct cvmx_pow_ecc_err_cn31xx cn38xxp2;
@@ -394,25 +211,16 @@ union cvmx_pow_ecc_err {
         struct cvmx_pow_ecc_err_s cn56xxp1;
         struct cvmx_pow_ecc_err_s cn58xx;
         struct cvmx_pow_ecc_err_s cn58xxp1;
-        struct cvmx_pow_ecc_err_s cn61xx;
         struct cvmx_pow_ecc_err_s cn63xx;
         struct cvmx_pow_ecc_err_s cn63xxp1;
-        struct cvmx_pow_ecc_err_s cn66xx;
-        struct cvmx_pow_ecc_err_s cnf71xx;
 };
 
 union cvmx_pow_int_ctl {
         uint64_t u64;
         struct cvmx_pow_int_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t pfr_dis:1;
                 uint64_t nbr_thr:5;
-#else
-                uint64_t nbr_thr:5;
-                uint64_t pfr_dis:1;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
         struct cvmx_pow_int_ctl_s cn30xx;
         struct cvmx_pow_int_ctl_s cn31xx;
@@ -425,23 +233,15 @@ union cvmx_pow_int_ctl {
         struct cvmx_pow_int_ctl_s cn56xxp1;
         struct cvmx_pow_int_ctl_s cn58xx;
         struct cvmx_pow_int_ctl_s cn58xxp1;
-        struct cvmx_pow_int_ctl_s cn61xx;
         struct cvmx_pow_int_ctl_s cn63xx;
         struct cvmx_pow_int_ctl_s cn63xxp1;
-        struct cvmx_pow_int_ctl_s cn66xx;
-        struct cvmx_pow_int_ctl_s cnf71xx;
 };
 
 union cvmx_pow_iq_cntx {
         uint64_t u64;
         struct cvmx_pow_iq_cntx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t iq_cnt:32;
-#else
-                uint64_t iq_cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_iq_cntx_s cn30xx;
         struct cvmx_pow_iq_cntx_s cn31xx;
@@ -454,23 +254,15 @@ union cvmx_pow_iq_cntx {
         struct cvmx_pow_iq_cntx_s cn56xxp1;
         struct cvmx_pow_iq_cntx_s cn58xx;
         struct cvmx_pow_iq_cntx_s cn58xxp1;
-        struct cvmx_pow_iq_cntx_s cn61xx;
         struct cvmx_pow_iq_cntx_s cn63xx;
         struct cvmx_pow_iq_cntx_s cn63xxp1;
-        struct cvmx_pow_iq_cntx_s cn66xx;
-        struct cvmx_pow_iq_cntx_s cnf71xx;
 };
 
 union cvmx_pow_iq_com_cnt {
         uint64_t u64;
         struct cvmx_pow_iq_com_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t iq_cnt:32;
-#else
-                uint64_t iq_cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_iq_com_cnt_s cn30xx;
         struct cvmx_pow_iq_com_cnt_s cn31xx;
@@ -483,150 +275,90 @@ union cvmx_pow_iq_com_cnt {
         struct cvmx_pow_iq_com_cnt_s cn56xxp1;
         struct cvmx_pow_iq_com_cnt_s cn58xx;
         struct cvmx_pow_iq_com_cnt_s cn58xxp1;
-        struct cvmx_pow_iq_com_cnt_s cn61xx;
         struct cvmx_pow_iq_com_cnt_s cn63xx;
         struct cvmx_pow_iq_com_cnt_s cn63xxp1;
-        struct cvmx_pow_iq_com_cnt_s cn66xx;
-        struct cvmx_pow_iq_com_cnt_s cnf71xx;
 };
 
 union cvmx_pow_iq_int {
         uint64_t u64;
         struct cvmx_pow_iq_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t iq_int:8;
-#else
-                uint64_t iq_int:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_pow_iq_int_s cn52xx;
         struct cvmx_pow_iq_int_s cn52xxp1;
         struct cvmx_pow_iq_int_s cn56xx;
         struct cvmx_pow_iq_int_s cn56xxp1;
-        struct cvmx_pow_iq_int_s cn61xx;
         struct cvmx_pow_iq_int_s cn63xx;
         struct cvmx_pow_iq_int_s cn63xxp1;
-        struct cvmx_pow_iq_int_s cn66xx;
-        struct cvmx_pow_iq_int_s cnf71xx;
 };
 
 union cvmx_pow_iq_int_en {
         uint64_t u64;
         struct cvmx_pow_iq_int_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t int_en:8;
-#else
-                uint64_t int_en:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_pow_iq_int_en_s cn52xx;
         struct cvmx_pow_iq_int_en_s cn52xxp1;
         struct cvmx_pow_iq_int_en_s cn56xx;
         struct cvmx_pow_iq_int_en_s cn56xxp1;
-        struct cvmx_pow_iq_int_en_s cn61xx;
         struct cvmx_pow_iq_int_en_s cn63xx;
         struct cvmx_pow_iq_int_en_s cn63xxp1;
-        struct cvmx_pow_iq_int_en_s cn66xx;
-        struct cvmx_pow_iq_int_en_s cnf71xx;
 };
 
 union cvmx_pow_iq_thrx {
         uint64_t u64;
         struct cvmx_pow_iq_thrx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t iq_thr:32;
-#else
-                uint64_t iq_thr:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_iq_thrx_s cn52xx;
         struct cvmx_pow_iq_thrx_s cn52xxp1;
         struct cvmx_pow_iq_thrx_s cn56xx;
         struct cvmx_pow_iq_thrx_s cn56xxp1;
-        struct cvmx_pow_iq_thrx_s cn61xx;
         struct cvmx_pow_iq_thrx_s cn63xx;
         struct cvmx_pow_iq_thrx_s cn63xxp1;
-        struct cvmx_pow_iq_thrx_s cn66xx;
-        struct cvmx_pow_iq_thrx_s cnf71xx;
 };
 
 union cvmx_pow_nos_cnt {
         uint64_t u64;
         struct cvmx_pow_nos_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_12_63:52;
                 uint64_t nos_cnt:12;
-#else
-                uint64_t nos_cnt:12;
-                uint64_t reserved_12_63:52;
-#endif
         } s;
         struct cvmx_pow_nos_cnt_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_7_63:57;
                 uint64_t nos_cnt:7;
-#else
-                uint64_t nos_cnt:7;
-                uint64_t reserved_7_63:57;
-#endif
         } cn30xx;
         struct cvmx_pow_nos_cnt_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t nos_cnt:9;
-#else
-                uint64_t nos_cnt:9;
-                uint64_t reserved_9_63:55;
-#endif
         } cn31xx;
         struct cvmx_pow_nos_cnt_s cn38xx;
         struct cvmx_pow_nos_cnt_s cn38xxp2;
         struct cvmx_pow_nos_cnt_cn31xx cn50xx;
         struct cvmx_pow_nos_cnt_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t nos_cnt:10;
-#else
-                uint64_t nos_cnt:10;
-                uint64_t reserved_10_63:54;
-#endif
         } cn52xx;
         struct cvmx_pow_nos_cnt_cn52xx cn52xxp1;
         struct cvmx_pow_nos_cnt_s cn56xx;
         struct cvmx_pow_nos_cnt_s cn56xxp1;
         struct cvmx_pow_nos_cnt_s cn58xx;
         struct cvmx_pow_nos_cnt_s cn58xxp1;
-        struct cvmx_pow_nos_cnt_cn52xx cn61xx;
         struct cvmx_pow_nos_cnt_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_11_63:53;
                 uint64_t nos_cnt:11;
-#else
-                uint64_t nos_cnt:11;
-                uint64_t reserved_11_63:53;
-#endif
         } cn63xx;
         struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
-        struct cvmx_pow_nos_cnt_cn63xx cn66xx;
-        struct cvmx_pow_nos_cnt_cn52xx cnf71xx;
 };
 
 union cvmx_pow_nw_tim {
         uint64_t u64;
         struct cvmx_pow_nw_tim_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t nw_tim:10;
-#else
-                uint64_t nw_tim:10;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
         struct cvmx_pow_nw_tim_s cn30xx;
         struct cvmx_pow_nw_tim_s cn31xx;
@@ -639,23 +371,15 @@ union cvmx_pow_nw_tim {
         struct cvmx_pow_nw_tim_s cn56xxp1;
         struct cvmx_pow_nw_tim_s cn58xx;
         struct cvmx_pow_nw_tim_s cn58xxp1;
-        struct cvmx_pow_nw_tim_s cn61xx;
         struct cvmx_pow_nw_tim_s cn63xx;
         struct cvmx_pow_nw_tim_s cn63xxp1;
-        struct cvmx_pow_nw_tim_s cn66xx;
-        struct cvmx_pow_nw_tim_s cnf71xx;
 };
 
 union cvmx_pow_pf_rst_msk {
         uint64_t u64;
         struct cvmx_pow_pf_rst_msk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t rst_msk:8;
-#else
-                uint64_t rst_msk:8;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
         struct cvmx_pow_pf_rst_msk_s cn50xx;
         struct cvmx_pow_pf_rst_msk_s cn52xx;
@@ -664,17 +388,13 @@ union cvmx_pow_pf_rst_msk {
         struct cvmx_pow_pf_rst_msk_s cn56xxp1;
         struct cvmx_pow_pf_rst_msk_s cn58xx;
         struct cvmx_pow_pf_rst_msk_s cn58xxp1;
-        struct cvmx_pow_pf_rst_msk_s cn61xx;
         struct cvmx_pow_pf_rst_msk_s cn63xx;
         struct cvmx_pow_pf_rst_msk_s cn63xxp1;
-        struct cvmx_pow_pf_rst_msk_s cn66xx;
-        struct cvmx_pow_pf_rst_msk_s cnf71xx;
 };
 
 union cvmx_pow_pp_grp_mskx {
         uint64_t u64;
         struct cvmx_pow_pp_grp_mskx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_48_63:16;
                 uint64_t qos7_pri:4;
                 uint64_t qos6_pri:4;
@@ -685,27 +405,10 @@ union cvmx_pow_pp_grp_mskx {
                 uint64_t qos1_pri:4;
                 uint64_t qos0_pri:4;
                 uint64_t grp_msk:16;
-#else
-                uint64_t grp_msk:16;
-                uint64_t qos0_pri:4;
-                uint64_t qos1_pri:4;
-                uint64_t qos2_pri:4;
-                uint64_t qos3_pri:4;
-                uint64_t qos4_pri:4;
-                uint64_t qos5_pri:4;
-                uint64_t qos6_pri:4;
-                uint64_t qos7_pri:4;
-                uint64_t reserved_48_63:16;
-#endif
         } s;
         struct cvmx_pow_pp_grp_mskx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_16_63:48;
                 uint64_t grp_msk:16;
-#else
-                uint64_t grp_msk:16;
-                uint64_t reserved_16_63:48;
-#endif
         } cn30xx;
         struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;
         struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;
@@ -717,29 +420,18 @@ union cvmx_pow_pp_grp_mskx {
         struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
         struct cvmx_pow_pp_grp_mskx_s cn58xx;
         struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
-        struct cvmx_pow_pp_grp_mskx_s cn61xx;
         struct cvmx_pow_pp_grp_mskx_s cn63xx;
         struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
-        struct cvmx_pow_pp_grp_mskx_s cn66xx;
-        struct cvmx_pow_pp_grp_mskx_s cnf71xx;
 };
 
 union cvmx_pow_qos_rndx {
         uint64_t u64;
         struct cvmx_pow_qos_rndx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t rnd_p3:8;
                 uint64_t rnd_p2:8;
                 uint64_t rnd_p1:8;
                 uint64_t rnd:8;
-#else
-                uint64_t rnd:8;
-                uint64_t rnd_p1:8;
-                uint64_t rnd_p2:8;
-                uint64_t rnd_p3:8;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_qos_rndx_s cn30xx;
         struct cvmx_pow_qos_rndx_s cn31xx;
@@ -752,17 +444,13 @@ union cvmx_pow_qos_rndx {
         struct cvmx_pow_qos_rndx_s cn56xxp1;
         struct cvmx_pow_qos_rndx_s cn58xx;
         struct cvmx_pow_qos_rndx_s cn58xxp1;
-        struct cvmx_pow_qos_rndx_s cn61xx;
         struct cvmx_pow_qos_rndx_s cn63xx;
         struct cvmx_pow_qos_rndx_s cn63xxp1;
-        struct cvmx_pow_qos_rndx_s cn66xx;
-        struct cvmx_pow_qos_rndx_s cnf71xx;
 };
 
 union cvmx_pow_qos_thrx {
         uint64_t u64;
         struct cvmx_pow_qos_thrx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_60_63:4;
                 uint64_t des_cnt:12;
                 uint64_t buf_cnt:12;
@@ -771,19 +459,8 @@ union cvmx_pow_qos_thrx {
                 uint64_t max_thr:11;
                 uint64_t reserved_11_11:1;
                 uint64_t min_thr:11;
-#else
-                uint64_t min_thr:11;
-                uint64_t reserved_11_11:1;
-                uint64_t max_thr:11;
-                uint64_t reserved_23_23:1;
-                uint64_t free_cnt:12;
-                uint64_t buf_cnt:12;
-                uint64_t des_cnt:12;
-                uint64_t reserved_60_63:4;
-#endif
         } s;
         struct cvmx_pow_qos_thrx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_55_63:9;
                 uint64_t des_cnt:7;
                 uint64_t reserved_43_47:5;
@@ -794,21 +471,8 @@ union cvmx_pow_qos_thrx {
                 uint64_t max_thr:6;
                 uint64_t reserved_6_11:6;
                 uint64_t min_thr:6;
-#else
-                uint64_t min_thr:6;
-                uint64_t reserved_6_11:6;
-                uint64_t max_thr:6;
-                uint64_t reserved_18_23:6;
-                uint64_t free_cnt:7;
-                uint64_t reserved_31_35:5;
-                uint64_t buf_cnt:7;
-                uint64_t reserved_43_47:5;
-                uint64_t des_cnt:7;
-                uint64_t reserved_55_63:9;
-#endif
         } cn30xx;
         struct cvmx_pow_qos_thrx_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_57_63:7;
                 uint64_t des_cnt:9;
                 uint64_t reserved_45_47:3;
@@ -819,24 +483,11 @@ union cvmx_pow_qos_thrx {
                 uint64_t max_thr:8;
                 uint64_t reserved_8_11:4;
                 uint64_t min_thr:8;
-#else
-                uint64_t min_thr:8;
-                uint64_t reserved_8_11:4;
-                uint64_t max_thr:8;
-                uint64_t reserved_20_23:4;
-                uint64_t free_cnt:9;
-                uint64_t reserved_33_35:3;
-                uint64_t buf_cnt:9;
-                uint64_t reserved_45_47:3;
-                uint64_t des_cnt:9;
-                uint64_t reserved_57_63:7;
-#endif
         } cn31xx;
         struct cvmx_pow_qos_thrx_s cn38xx;
         struct cvmx_pow_qos_thrx_s cn38xxp2;
         struct cvmx_pow_qos_thrx_cn31xx cn50xx;
         struct cvmx_pow_qos_thrx_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_58_63:6;
                 uint64_t des_cnt:10;
                 uint64_t reserved_46_47:2;
@@ -847,27 +498,13 @@ union cvmx_pow_qos_thrx {
                 uint64_t max_thr:9;
                 uint64_t reserved_9_11:3;
                 uint64_t min_thr:9;
-#else
-                uint64_t min_thr:9;
-                uint64_t reserved_9_11:3;
-                uint64_t max_thr:9;
-                uint64_t reserved_21_23:3;
-                uint64_t free_cnt:10;
-                uint64_t reserved_34_35:2;
-                uint64_t buf_cnt:10;
-                uint64_t reserved_46_47:2;
-                uint64_t des_cnt:10;
-                uint64_t reserved_58_63:6;
-#endif
         } cn52xx;
         struct cvmx_pow_qos_thrx_cn52xx cn52xxp1;
         struct cvmx_pow_qos_thrx_s cn56xx;
         struct cvmx_pow_qos_thrx_s cn56xxp1;
         struct cvmx_pow_qos_thrx_s cn58xx;
         struct cvmx_pow_qos_thrx_s cn58xxp1;
-        struct cvmx_pow_qos_thrx_cn52xx cn61xx;
         struct cvmx_pow_qos_thrx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_59_63:5;
                 uint64_t des_cnt:11;
                 uint64_t reserved_47_47:1;
@@ -878,34 +515,15 @@ union cvmx_pow_qos_thrx {
                 uint64_t max_thr:10;
                 uint64_t reserved_10_11:2;
                 uint64_t min_thr:10;
-#else
-                uint64_t min_thr:10;
-                uint64_t reserved_10_11:2;
-                uint64_t max_thr:10;
-                uint64_t reserved_22_23:2;
-                uint64_t free_cnt:11;
-                uint64_t reserved_35_35:1;
-                uint64_t buf_cnt:11;
-                uint64_t reserved_47_47:1;
-                uint64_t des_cnt:11;
-                uint64_t reserved_59_63:5;
-#endif
         } cn63xx;
         struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
-        struct cvmx_pow_qos_thrx_cn63xx cn66xx;
-        struct cvmx_pow_qos_thrx_cn52xx cnf71xx;
 };
 
 union cvmx_pow_ts_pc {
         uint64_t u64;
         struct cvmx_pow_ts_pc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t ts_pc:32;
-#else
-                uint64_t ts_pc:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_ts_pc_s cn30xx;
         struct cvmx_pow_ts_pc_s cn31xx;
@@ -918,23 +536,15 @@ union cvmx_pow_ts_pc {
         struct cvmx_pow_ts_pc_s cn56xxp1;
         struct cvmx_pow_ts_pc_s cn58xx;
         struct cvmx_pow_ts_pc_s cn58xxp1;
-        struct cvmx_pow_ts_pc_s cn61xx;
         struct cvmx_pow_ts_pc_s cn63xx;
         struct cvmx_pow_ts_pc_s cn63xxp1;
-        struct cvmx_pow_ts_pc_s cn66xx;
-        struct cvmx_pow_ts_pc_s cnf71xx;
 };
 
 union cvmx_pow_wa_com_pc {
         uint64_t u64;
         struct cvmx_pow_wa_com_pc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t wa_pc:32;
-#else
-                uint64_t wa_pc:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_wa_com_pc_s cn30xx;
         struct cvmx_pow_wa_com_pc_s cn31xx;
@@ -947,23 +557,15 @@ union cvmx_pow_wa_com_pc {
         struct cvmx_pow_wa_com_pc_s cn56xxp1;
         struct cvmx_pow_wa_com_pc_s cn58xx;
         struct cvmx_pow_wa_com_pc_s cn58xxp1;
-        struct cvmx_pow_wa_com_pc_s cn61xx;
         struct cvmx_pow_wa_com_pc_s cn63xx;
         struct cvmx_pow_wa_com_pc_s cn63xxp1;
-        struct cvmx_pow_wa_com_pc_s cn66xx;
-        struct cvmx_pow_wa_com_pc_s cnf71xx;
 };
 
 union cvmx_pow_wa_pcx {
         uint64_t u64;
         struct cvmx_pow_wa_pcx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t wa_pc:32;
-#else
-                uint64_t wa_pc:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_wa_pcx_s cn30xx;
         struct cvmx_pow_wa_pcx_s cn31xx;
@@ -976,25 +578,16 @@ union cvmx_pow_wa_pcx {
         struct cvmx_pow_wa_pcx_s cn56xxp1;
         struct cvmx_pow_wa_pcx_s cn58xx;
         struct cvmx_pow_wa_pcx_s cn58xxp1;
-        struct cvmx_pow_wa_pcx_s cn61xx;
         struct cvmx_pow_wa_pcx_s cn63xx;
         struct cvmx_pow_wa_pcx_s cn63xxp1;
-        struct cvmx_pow_wa_pcx_s cn66xx;
-        struct cvmx_pow_wa_pcx_s cnf71xx;
 };
 
 union cvmx_pow_wq_int {
         uint64_t u64;
         struct cvmx_pow_wq_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t iq_dis:16;
                 uint64_t wq_int:16;
-#else
-                uint64_t wq_int:16;
-                uint64_t iq_dis:16;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_wq_int_s cn30xx;
         struct cvmx_pow_wq_int_s cn31xx;
@@ -1007,126 +600,69 @@ union cvmx_pow_wq_int {
         struct cvmx_pow_wq_int_s cn56xxp1;
         struct cvmx_pow_wq_int_s cn58xx;
         struct cvmx_pow_wq_int_s cn58xxp1;
-        struct cvmx_pow_wq_int_s cn61xx;
         struct cvmx_pow_wq_int_s cn63xx;
         struct cvmx_pow_wq_int_s cn63xxp1;
-        struct cvmx_pow_wq_int_s cn66xx;
-        struct cvmx_pow_wq_int_s cnf71xx;
 };
 
 union cvmx_pow_wq_int_cntx {
         uint64_t u64;
         struct cvmx_pow_wq_int_cntx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t tc_cnt:4;
                 uint64_t ds_cnt:12;
                 uint64_t iq_cnt:12;
-#else
-                uint64_t iq_cnt:12;
-                uint64_t ds_cnt:12;
-                uint64_t tc_cnt:4;
-                uint64_t reserved_28_63:36;
-#endif
         } s;
         struct cvmx_pow_wq_int_cntx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t tc_cnt:4;
                 uint64_t reserved_19_23:5;
                 uint64_t ds_cnt:7;
                 uint64_t reserved_7_11:5;
                 uint64_t iq_cnt:7;
-#else
-                uint64_t iq_cnt:7;
-                uint64_t reserved_7_11:5;
-                uint64_t ds_cnt:7;
-                uint64_t reserved_19_23:5;
-                uint64_t tc_cnt:4;
-                uint64_t reserved_28_63:36;
-#endif
         } cn30xx;
         struct cvmx_pow_wq_int_cntx_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t tc_cnt:4;
                 uint64_t reserved_21_23:3;
                 uint64_t ds_cnt:9;
                 uint64_t reserved_9_11:3;
                 uint64_t iq_cnt:9;
-#else
-                uint64_t iq_cnt:9;
-                uint64_t reserved_9_11:3;
-                uint64_t ds_cnt:9;
-                uint64_t reserved_21_23:3;
-                uint64_t tc_cnt:4;
-                uint64_t reserved_28_63:36;
-#endif
         } cn31xx;
         struct cvmx_pow_wq_int_cntx_s cn38xx;
         struct cvmx_pow_wq_int_cntx_s cn38xxp2;
         struct cvmx_pow_wq_int_cntx_cn31xx cn50xx;
         struct cvmx_pow_wq_int_cntx_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t tc_cnt:4;
                 uint64_t reserved_22_23:2;
                 uint64_t ds_cnt:10;
                 uint64_t reserved_10_11:2;
                 uint64_t iq_cnt:10;
-#else
-                uint64_t iq_cnt:10;
-                uint64_t reserved_10_11:2;
-                uint64_t ds_cnt:10;
-                uint64_t reserved_22_23:2;
-                uint64_t tc_cnt:4;
-                uint64_t reserved_28_63:36;
-#endif
         } cn52xx;
         struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;
         struct cvmx_pow_wq_int_cntx_s cn56xx;
         struct cvmx_pow_wq_int_cntx_s cn56xxp1;
         struct cvmx_pow_wq_int_cntx_s cn58xx;
         struct cvmx_pow_wq_int_cntx_s cn58xxp1;
-        struct cvmx_pow_wq_int_cntx_cn52xx cn61xx;
         struct cvmx_pow_wq_int_cntx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_28_63:36;
                 uint64_t tc_cnt:4;
                 uint64_t reserved_23_23:1;
                 uint64_t ds_cnt:11;
                 uint64_t reserved_11_11:1;
                 uint64_t iq_cnt:11;
-#else
-                uint64_t iq_cnt:11;
-                uint64_t reserved_11_11:1;
-                uint64_t ds_cnt:11;
-                uint64_t reserved_23_23:1;
-                uint64_t tc_cnt:4;
-                uint64_t reserved_28_63:36;
-#endif
         } cn63xx;
         struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
-        struct cvmx_pow_wq_int_cntx_cn63xx cn66xx;
-        struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx;
 };
 
 union cvmx_pow_wq_int_pc {
         uint64_t u64;
         struct cvmx_pow_wq_int_pc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_60_63:4;
                 uint64_t pc:28;
                 uint64_t reserved_28_31:4;
                 uint64_t pc_thr:20;
                 uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t pc_thr:20;
-                uint64_t reserved_28_31:4;
-                uint64_t pc:28;
-                uint64_t reserved_60_63:4;
-#endif
         } s;
         struct cvmx_pow_wq_int_pc_s cn30xx;
         struct cvmx_pow_wq_int_pc_s cn31xx;
@@ -1139,17 +675,13 @@ union cvmx_pow_wq_int_pc {
         struct cvmx_pow_wq_int_pc_s cn56xxp1;
         struct cvmx_pow_wq_int_pc_s cn58xx;
         struct cvmx_pow_wq_int_pc_s cn58xxp1;
-        struct cvmx_pow_wq_int_pc_s cn61xx;
         struct cvmx_pow_wq_int_pc_s cn63xx;
         struct cvmx_pow_wq_int_pc_s cn63xxp1;
-        struct cvmx_pow_wq_int_pc_s cn66xx;
-        struct cvmx_pow_wq_int_pc_s cnf71xx;
 };
 
 union cvmx_pow_wq_int_thrx {
         uint64_t u64;
         struct cvmx_pow_wq_int_thrx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t tc_en:1;
                 uint64_t tc_thr:4;
@@ -1157,18 +689,8 @@ union cvmx_pow_wq_int_thrx {
                 uint64_t ds_thr:11;
                 uint64_t reserved_11_11:1;
                 uint64_t iq_thr:11;
-#else
-                uint64_t iq_thr:11;
-                uint64_t reserved_11_11:1;
-                uint64_t ds_thr:11;
-                uint64_t reserved_23_23:1;
-                uint64_t tc_thr:4;
-                uint64_t tc_en:1;
-                uint64_t reserved_29_63:35;
-#endif
         } s;
         struct cvmx_pow_wq_int_thrx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t tc_en:1;
                 uint64_t tc_thr:4;
@@ -1176,18 +698,8 @@ union cvmx_pow_wq_int_thrx {
                 uint64_t ds_thr:6;
                 uint64_t reserved_6_11:6;
                 uint64_t iq_thr:6;
-#else
-                uint64_t iq_thr:6;
-                uint64_t reserved_6_11:6;
-                uint64_t ds_thr:6;
-                uint64_t reserved_18_23:6;
-                uint64_t tc_thr:4;
-                uint64_t tc_en:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn30xx;
         struct cvmx_pow_wq_int_thrx_cn31xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t tc_en:1;
                 uint64_t tc_thr:4;
@@ -1195,21 +707,11 @@ union cvmx_pow_wq_int_thrx {
                 uint64_t ds_thr:8;
                 uint64_t reserved_8_11:4;
                 uint64_t iq_thr:8;
-#else
-                uint64_t iq_thr:8;
-                uint64_t reserved_8_11:4;
-                uint64_t ds_thr:8;
-                uint64_t reserved_20_23:4;
-                uint64_t tc_thr:4;
-                uint64_t tc_en:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn31xx;
         struct cvmx_pow_wq_int_thrx_s cn38xx;
         struct cvmx_pow_wq_int_thrx_s cn38xxp2;
         struct cvmx_pow_wq_int_thrx_cn31xx cn50xx;
         struct cvmx_pow_wq_int_thrx_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t tc_en:1;
                 uint64_t tc_thr:4;
@@ -1217,24 +719,13 @@ union cvmx_pow_wq_int_thrx {
                 uint64_t ds_thr:9;
                 uint64_t reserved_9_11:3;
                 uint64_t iq_thr:9;
-#else
-                uint64_t iq_thr:9;
-                uint64_t reserved_9_11:3;
-                uint64_t ds_thr:9;
-                uint64_t reserved_21_23:3;
-                uint64_t tc_thr:4;
-                uint64_t tc_en:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn52xx;
         struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;
         struct cvmx_pow_wq_int_thrx_s cn56xx;
         struct cvmx_pow_wq_int_thrx_s cn56xxp1;
         struct cvmx_pow_wq_int_thrx_s cn58xx;
         struct cvmx_pow_wq_int_thrx_s cn58xxp1;
-        struct cvmx_pow_wq_int_thrx_cn52xx cn61xx;
         struct cvmx_pow_wq_int_thrx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_29_63:35;
                 uint64_t tc_en:1;
                 uint64_t tc_thr:4;
@@ -1242,31 +733,15 @@ union cvmx_pow_wq_int_thrx {
                 uint64_t ds_thr:10;
                 uint64_t reserved_10_11:2;
                 uint64_t iq_thr:10;
-#else
-                uint64_t iq_thr:10;
-                uint64_t reserved_10_11:2;
-                uint64_t ds_thr:10;
-                uint64_t reserved_22_23:2;
-                uint64_t tc_thr:4;
-                uint64_t tc_en:1;
-                uint64_t reserved_29_63:35;
-#endif
         } cn63xx;
         struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
-        struct cvmx_pow_wq_int_thrx_cn63xx cn66xx;
-        struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx;
 };
 
 union cvmx_pow_ws_pcx {
         uint64_t u64;
         struct cvmx_pow_ws_pcx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t ws_pc:32;
-#else
-                uint64_t ws_pc:32;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
         struct cvmx_pow_ws_pcx_s cn30xx;
         struct cvmx_pow_ws_pcx_s cn31xx;
@@ -1279,11 +754,8 @@ union cvmx_pow_ws_pcx {
         struct cvmx_pow_ws_pcx_s cn56xxp1;
         struct cvmx_pow_ws_pcx_s cn58xx;
         struct cvmx_pow_ws_pcx_s cn58xxp1;
-        struct cvmx_pow_ws_pcx_s cn61xx;
         struct cvmx_pow_ws_pcx_s cn63xx;
         struct cvmx_pow_ws_pcx_s cn63xxp1;
-        struct cvmx_pow_ws_pcx_s cn66xx;
-        struct cvmx_pow_ws_pcx_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
deleted file mode 100644
index 92742b241a5..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-pow.h
+++ /dev/null
@@ -1,1982 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * Interface to the hardware Packet Order / Work unit.
- *
- * New, starting with SDK 1.7.0, cvmx-pow supports a number of
- * extended consistency checks. The define
- * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW
- * internal state checks to find common programming errors. If
- * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default
- * enabled. For example, cvmx-pow will check for the following
- * program errors or POW state inconsistency.
- * - Requesting a POW operation with an active tag switch in
- *   progress.
- * - Waiting for a tag switch to complete for an excessively
- *   long period. This is normally a sign of an error in locking
- *   causing deadlock.
- * - Illegal tag switches from NULL_NULL.
- * - Illegal tag switches from NULL.
- * - Illegal deschedule request.
- * - WQE pointer not matching the one attached to the core by
- *   the POW.
- *
- */
-
-#ifndef __CVMX_POW_H__
-#define __CVMX_POW_H__
-
-#include <asm/octeon/cvmx-pow-defs.h>
-
-#include <asm/octeon/cvmx-scratch.h>
-#include <asm/octeon/cvmx-wqe.h>
-
-/* Default to having all POW constancy checks turned on */
-#ifndef CVMX_ENABLE_POW_CHECKS
-#define CVMX_ENABLE_POW_CHECKS 1
-#endif
-
-enum cvmx_pow_tag_type {
-        /* Tag ordering is maintained */
-        CVMX_POW_TAG_TYPE_ORDERED   = 0L,
-        /* Tag ordering is maintained, and at most one PP has the tag */
-        CVMX_POW_TAG_TYPE_ATOMIC    = 1L,
-        /*
-         * The work queue entry from the order - NEVER tag switch from
-         * NULL to NULL
-         */
-        CVMX_POW_TAG_TYPE_NULL      = 2L,
-        /* A tag switch to NULL, and there is no space reserved in POW
-         * - NEVER tag switch to NULL_NULL
-         * - NEVER tag switch from NULL_NULL
-         * - NULL_NULL is entered at the beginning of time and on a deschedule.
-         * - NULL_NULL can be exited by a new work request. A NULL_SWITCH
-         * load can also switch the state to NULL
-         */
-        CVMX_POW_TAG_TYPE_NULL_NULL = 3L
-};
-
-/**
- * Wait flag values for pow functions.
- */
-typedef enum {
-        CVMX_POW_WAIT = 1,
-        CVMX_POW_NO_WAIT = 0,
-} cvmx_pow_wait_t;
-
-/**
- *  POW tag operations.  These are used in the data stored to the POW.
- */
-typedef enum {
-        /*
-         * switch the tag (only) for this PP
-         * - the previous tag should be non-NULL in this case
-         * - tag switch response required
-         * - fields used: op, type, tag
-         */
-        CVMX_POW_TAG_OP_SWTAG = 0L,
-        /*
-         * switch the tag for this PP, with full information
-         * - this should be used when the previous tag is NULL
-         * - tag switch response required
-         * - fields used: address, op, grp, type, tag
-         */
-        CVMX_POW_TAG_OP_SWTAG_FULL = 1L,
-        /*
-         * switch the tag (and/or group) for this PP and de-schedule
-         * - OK to keep the tag the same and only change the group
-         * - fields used: op, no_sched, grp, type, tag
-         */
-        CVMX_POW_TAG_OP_SWTAG_DESCH = 2L,
-        /*
-         * just de-schedule
-         * - fields used: op, no_sched
-         */
-        CVMX_POW_TAG_OP_DESCH = 3L,
-        /*
-         * create an entirely new work queue entry
-         * - fields used: address, op, qos, grp, type, tag
-         */
-        CVMX_POW_TAG_OP_ADDWQ = 4L,
-        /*
-         * just update the work queue pointer and grp for this PP
-         * - fields used: address, op, grp
-         */
-        CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L,
-        /*
-         * set the no_sched bit on the de-schedule list
-         *
-         * - does nothing if the selected entry is not on the
-         *   de-schedule list
-         *
-         * - does nothing if the stored work queue pointer does not
-         *   match the address field
-         *
-         * - fields used: address, index, op
-         *
-         *  Before issuing a *_NSCHED operation, SW must guarantee
-         *  that all prior deschedules and set/clr NSCHED operations
-         *  are complete and all prior switches are complete. The
-         *  hardware provides the opsdone bit and swdone bit for SW
-         *  polling. After issuing a *_NSCHED operation, SW must
-         *  guarantee that the set/clr NSCHED is complete before any
-         *  subsequent operations.
-         */
-        CVMX_POW_TAG_OP_SET_NSCHED = 6L,
-        /*
-         * clears the no_sched bit on the de-schedule list
-         *
-         * - does nothing if the selected entry is not on the
-         *   de-schedule list
-         *
-         * - does nothing if the stored work queue pointer does not
-         *   match the address field
-         *
-         * - fields used: address, index, op
-         *
-         * Before issuing a *_NSCHED operation, SW must guarantee that
-         * all prior deschedules and set/clr NSCHED operations are
-         * complete and all prior switches are complete. The hardware
-         * provides the opsdone bit and swdone bit for SW
-         * polling. After issuing a *_NSCHED operation, SW must
-         * guarantee that the set/clr NSCHED is complete before any
-         * subsequent operations.
-         */
-        CVMX_POW_TAG_OP_CLR_NSCHED = 7L,
-        /* do nothing */
-        CVMX_POW_TAG_OP_NOP = 15L
-} cvmx_pow_tag_op_t;
-
-/**
- * This structure defines the store data on a store to POW
- */
-typedef union {
-        uint64_t u64;
-        struct {
-                /*
-                 * Don't reschedule this entry. no_sched is used for
-                 * CVMX_POW_TAG_OP_SWTAG_DESCH and
-                 * CVMX_POW_TAG_OP_DESCH
-                 */
-                uint64_t no_sched:1;
-                uint64_t unused:2;
-                /* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
-                uint64_t index:13;
-                /* The operation to perform */
-                cvmx_pow_tag_op_t op:4;
-                uint64_t unused2:2;
-                /*
-                 * The QOS level for the packet. qos is only used for
-                 * CVMX_POW_TAG_OP_ADDWQ
-                 */
-                uint64_t qos:3;
-                /*
-                 * The group that the work queue entry will be
-                 * scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ,
-                 * CVMX_POW_TAG_OP_SWTAG_FULL,
-                 * CVMX_POW_TAG_OP_SWTAG_DESCH, and
-                 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP
-                 */
-                uint64_t grp:4;
-                /*
-                 * The type of the tag. type is used for everything
-                 * except CVMX_POW_TAG_OP_DESCH,
-                 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
-                 * CVMX_POW_TAG_OP_*_NSCHED
-                 */
-                uint64_t type:3;
-                /*
-                 * The actual tag. tag is used for everything except
-                 * CVMX_POW_TAG_OP_DESCH,
-                 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
-                 * CVMX_POW_TAG_OP_*_NSCHED
-                 */
-                uint64_t tag:32;
-        } s;
-} cvmx_pow_tag_req_t;
-
-/**
- * This structure describes the address to load stuff from POW
- */
-typedef union {
-        uint64_t u64;
-
-    /**
-     * Address for new work request loads (did<2:0> == 0)
-     */
-        struct {
-                /* Mips64 address region. Should be CVMX_IO_SEG */
-                uint64_t mem_region:2;
-                /* Must be zero */
-                uint64_t reserved_49_61:13;
-                /* Must be one */
-                uint64_t is_io:1;
-                /* the ID of POW -- did<2:0> == 0 in this case */
-                uint64_t did:8;
-                /* Must be zero */
-                uint64_t reserved_4_39:36;
-                /*
-                 * If set, don't return load response until work is
-                 * available.
-                 */
-                uint64_t wait:1;
-                /* Must be zero */
-                uint64_t reserved_0_2:3;
-        } swork;
-
-    /**
-     * Address for loads to get POW internal status
-     */
-        struct {
-                /* Mips64 address region. Should be CVMX_IO_SEG */
-                uint64_t mem_region:2;
-                /* Must be zero */
-                uint64_t reserved_49_61:13;
-                /* Must be one */
-                uint64_t is_io:1;
-                /* the ID of POW -- did<2:0> == 1 in this case */
-                uint64_t did:8;
-                /* Must be zero */
-                uint64_t reserved_10_39:30;
-                /* The core id to get status for */
-                uint64_t coreid:4;
-                /*
-                 * If set and get_cur is set, return reverse tag-list
-                 * pointer rather than forward tag-list pointer.
-                 */
-                uint64_t get_rev:1;
-                /*
-                 * If set, return current status rather than pending
-                 * status.
-                 */
-                uint64_t get_cur:1;
-                /*
-                 * If set, get the work-queue pointer rather than
-                 * tag/type.
-                 */
-                uint64_t get_wqp:1;
-                /* Must be zero */
-                uint64_t reserved_0_2:3;
-        } sstatus;
-
-    /**
-     * Address for memory loads to get POW internal state
-     */
-        struct {
-                /* Mips64 address region. Should be CVMX_IO_SEG */
-                uint64_t mem_region:2;
-                /* Must be zero */
-                uint64_t reserved_49_61:13;
-                /* Must be one */
-                uint64_t is_io:1;
-                /* the ID of POW -- did<2:0> == 2 in this case */
-                uint64_t did:8;
-                /* Must be zero */
-                uint64_t reserved_16_39:24;
-                /* POW memory index */
-                uint64_t index:11;
-                /*
-                 * If set, return deschedule information rather than
-                 * the standard response for work-queue index (invalid
-                 * if the work-queue entry is not on the deschedule
-                 * list).
-                 */
-                uint64_t get_des:1;
-                /*
-                 * If set, get the work-queue pointer rather than
-                 * tag/type (no effect when get_des set).
-                 */
-                uint64_t get_wqp:1;
-                /* Must be zero */
-                uint64_t reserved_0_2:3;
-        } smemload;
-
-    /**
-     * Address for index/pointer loads
-     */
-        struct {
-                /* Mips64 address region. Should be CVMX_IO_SEG */
-                uint64_t mem_region:2;
-                /* Must be zero */
-                uint64_t reserved_49_61:13;
-                /* Must be one */
-                uint64_t is_io:1;
-                /* the ID of POW -- did<2:0> == 3 in this case */
-                uint64_t did:8;
-                /* Must be zero */
-                uint64_t reserved_9_39:31;
-                /*
-                 * when {get_rmt ==0 AND get_des_get_tail == 0}, this
-                 * field selects one of eight POW internal-input
-                 * queues (0-7), one per QOS level; values 8-15 are
-                 * illegal in this case; when {get_rmt ==0 AND
-                 * get_des_get_tail == 1}, this field selects one of
-                 * 16 deschedule lists (per group); when get_rmt ==1,
-                 * this field selects one of 16 memory-input queue
-                 * lists.  The two memory-input queue lists associated
-                 * with each QOS level are:
-                 *
-                 * - qosgrp = 0, qosgrp = 8:      QOS0
-                 * - qosgrp = 1, qosgrp = 9:      QOS1
-                 * - qosgrp = 2, qosgrp = 10:     QOS2
-                 * - qosgrp = 3, qosgrp = 11:     QOS3
-                 * - qosgrp = 4, qosgrp = 12:     QOS4
-                 * - qosgrp = 5, qosgrp = 13:     QOS5
-                 * - qosgrp = 6, qosgrp = 14:     QOS6
-                 * - qosgrp = 7, qosgrp = 15:     QOS7
-                 */
-                uint64_t qosgrp:4;
-                /*
-                 * If set and get_rmt is clear, return deschedule list
-                 * indexes rather than indexes for the specified qos
-                 * level; if set and get_rmt is set, return the tail
-                 * pointer rather than the head pointer for the
-                 * specified qos level.
-                 */
-                uint64_t get_des_get_tail:1;
-                /*
-                 * If set, return remote pointers rather than the
-                 * local indexes for the specified qos level.
-                 */
-                uint64_t get_rmt:1;
-                /* Must be zero */
-                uint64_t reserved_0_2:3;
-        } sindexload;
-
-    /**
-     * address for NULL_RD request (did<2:0> == 4) when this is read,
-     * HW attempts to change the state to NULL if it is NULL_NULL (the
-     * hardware cannot switch from NULL_NULL to NULL if a POW entry is
-     * not available - software may need to recover by finishing
-     * another piece of work before a POW entry can ever become
-     * available.)
-     */
-        struct {
-                /* Mips64 address region. Should be CVMX_IO_SEG */
-                uint64_t mem_region:2;
-                /* Must be zero */
-                uint64_t reserved_49_61:13;
-                /* Must be one */
-                uint64_t is_io:1;
-                /* the ID of POW -- did<2:0> == 4 in this case */
-                uint64_t did:8;
-                /* Must be zero */
-                uint64_t reserved_0_39:40;
-        } snull_rd;
-} cvmx_pow_load_addr_t;
-
-/**
- * This structure defines the response to a load/SENDSINGLE to POW
- * (except CSR reads)
- */
-typedef union {
-        uint64_t u64;
-
-    /**
-     * Response to new work request loads
-     */
-        struct {
-                /*
-                 * Set when no new work queue entry was returned.  *
-                 * If there was de-scheduled work, the HW will
-                 * definitely return it. When this bit is set, it
-                 * could mean either mean:
-                 *
-                 * - There was no work, or
-                 *
-                 * - There was no work that the HW could find. This
-                 *   case can happen, regardless of the wait bit value
-                 *   in the original request, when there is work in
-                 *   the IQ's that is too deep down the list.
-                 */
-                uint64_t no_work:1;
-                /* Must be zero */
-                uint64_t reserved_40_62:23;
-                /* 36 in O1 -- the work queue pointer */
-                uint64_t addr:40;
-        } s_work;
-
-    /**
-     * Result for a POW Status Load (when get_cur==0 and get_wqp==0)
-     */
-        struct {
-                uint64_t reserved_62_63:2;
-                /* Set when there is a pending non-NULL SWTAG or
-                 * SWTAG_FULL, and the POW entry has not left the list
-                 * for the original tag. */
-                uint64_t pend_switch:1;
-                /* Set when SWTAG_FULL and pend_switch is set. */
-                uint64_t pend_switch_full:1;
-                /*
-                 * Set when there is a pending NULL SWTAG, or an
-                 * implicit switch to NULL.
-                 */
-                uint64_t pend_switch_null:1;
-                /* Set when there is a pending DESCHED or SWTAG_DESCHED. */
-                uint64_t pend_desched:1;
-                /*
-                 * Set when there is a pending SWTAG_DESCHED and
-                 * pend_desched is set.
-                 */
-                uint64_t pend_desched_switch:1;
-                /* Set when nosched is desired and pend_desched is set. */
-                uint64_t pend_nosched:1;
-                /* Set when there is a pending GET_WORK. */
-                uint64_t pend_new_work:1;
-                /*
-                 * When pend_new_work is set, this bit indicates that
-                 * the wait bit was set.
-                 */
-                uint64_t pend_new_work_wait:1;
-                /* Set when there is a pending NULL_RD. */
-                uint64_t pend_null_rd:1;
-                /* Set when there is a pending CLR_NSCHED. */
-                uint64_t pend_nosched_clr:1;
-                uint64_t reserved_51:1;
-                /* This is the index when pend_nosched_clr is set. */
-                uint64_t pend_index:11;
-                /*
-                 * This is the new_grp when (pend_desched AND
-                 * pend_desched_switch) is set.
-                 */
-                uint64_t pend_grp:4;
-                uint64_t reserved_34_35:2;
-                /*
-                 * This is the tag type when pend_switch or
-                 * (pend_desched AND pend_desched_switch) are set.
-                 */
-                uint64_t pend_type:2;
-                /*
-                 * - this is the tag when pend_switch or (pend_desched
-                 *    AND pend_desched_switch) are set.
-                 */
-                uint64_t pend_tag:32;
-        } s_sstatus0;
-
-    /**
-     * Result for a POW Status Load (when get_cur==0 and get_wqp==1)
-     */
-        struct {
-                uint64_t reserved_62_63:2;
-                /*
-                 * Set when there is a pending non-NULL SWTAG or
-                 * SWTAG_FULL, and the POW entry has not left the list
-                 * for the original tag.
-                 */
-                uint64_t pend_switch:1;
-                /* Set when SWTAG_FULL and pend_switch is set. */
-                uint64_t pend_switch_full:1;
-                /*
-                 * Set when there is a pending NULL SWTAG, or an
-                 * implicit switch to NULL.
-                 */
-                uint64_t pend_switch_null:1;
-                /*
-                 * Set when there is a pending DESCHED or
-                 * SWTAG_DESCHED.
-                 */
-                uint64_t pend_desched:1;
-                /*
-                 * Set when there is a pending SWTAG_DESCHED and
-                 * pend_desched is set.
-                 */
-                uint64_t pend_desched_switch:1;
-                /* Set when nosched is desired and pend_desched is set. */
-                uint64_t pend_nosched:1;
-                /* Set when there is a pending GET_WORK. */
-                uint64_t pend_new_work:1;
-                /*
-                 * When pend_new_work is set, this bit indicates that
-                 * the wait bit was set.
-                 */
-                uint64_t pend_new_work_wait:1;
-                /* Set when there is a pending NULL_RD. */
-                uint64_t pend_null_rd:1;
-                /* Set when there is a pending CLR_NSCHED. */
-                uint64_t pend_nosched_clr:1;
-                uint64_t reserved_51:1;
-                /* This is the index when pend_nosched_clr is set. */
-                uint64_t pend_index:11;
-                /*
-                 * This is the new_grp when (pend_desched AND
-                 * pend_desched_switch) is set.
-                 */
-                uint64_t pend_grp:4;
-                /* This is the wqp when pend_nosched_clr is set. */
-                uint64_t pend_wqp:36;
-        } s_sstatus1;
-
-    /**
-     * Result for a POW Status Load (when get_cur==1, get_wqp==0, and
-     * get_rev==0)
-     */
-        struct {
-                uint64_t reserved_62_63:2;
-                /*
-                 * Points to the next POW entry in the tag list when
-                 * tail == 0 (and tag_type is not NULL or NULL_NULL).
-                 */
-                uint64_t link_index:11;
-                /* The POW entry attached to the core. */
-                uint64_t index:11;
-                /*
-                 * The group attached to the core (updated when new
-                 * tag list entered on SWTAG_FULL).
-                 */
-                uint64_t grp:4;
-                /*
-                 * Set when this POW entry is at the head of its tag
-                 * list (also set when in the NULL or NULL_NULL
-                 * state).
-                 */
-                uint64_t head:1;
-                /*
-                 * Set when this POW entry is at the tail of its tag
-                 * list (also set when in the NULL or NULL_NULL
-                 * state).
-                 */
-                uint64_t tail:1;
-                /*
-                 * The tag type attached to the core (updated when new
-                 * tag list entered on SWTAG, SWTAG_FULL, or
-                 * SWTAG_DESCHED).
-                 */
-                uint64_t tag_type:2;
-                /*
-                 * The tag attached to the core (updated when new tag
-                 * list entered on SWTAG, SWTAG_FULL, or
-                 * SWTAG_DESCHED).
-                 */
-                uint64_t tag:32;
-        } s_sstatus2;
-
-    /**
-     * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
-     */
-        struct {
-                uint64_t reserved_62_63:2;
-                /*
-                 * Points to the prior POW entry in the tag list when
-                 * head == 0 (and tag_type is not NULL or
-                 * NULL_NULL). This field is unpredictable when the
-                 * core's state is NULL or NULL_NULL.
-                 */
-                uint64_t revlink_index:11;
-                /* The POW entry attached to the core. */
-                uint64_t index:11;
-                /*
-                 * The group attached to the core (updated when new
-                 * tag list entered on SWTAG_FULL).
-                 */
-                uint64_t grp:4;
-                /* Set when this POW entry is at the head of its tag
-                 * list (also set when in the NULL or NULL_NULL
-                 * state).
-                 */
-                uint64_t head:1;
-                /*
-                 * Set when this POW entry is at the tail of its tag
-                 * list (also set when in the NULL or NULL_NULL
-                 * state).
-                 */
-                uint64_t tail:1;
-                /*
-                 * The tag type attached to the core (updated when new
-                 * tag list entered on SWTAG, SWTAG_FULL, or
-                 * SWTAG_DESCHED).
-                 */
-                uint64_t tag_type:2;
-                /*
-                 * The tag attached to the core (updated when new tag
-                 * list entered on SWTAG, SWTAG_FULL, or
-                 * SWTAG_DESCHED).
-                 */
-                uint64_t tag:32;
-        } s_sstatus3;
-
-    /**
-     * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
-     * get_rev==0)
-     */
-        struct {
-                uint64_t reserved_62_63:2;
-                /*
-                 * Points to the next POW entry in the tag list when
-                 * tail == 0 (and tag_type is not NULL or NULL_NULL).
-                 */
-                uint64_t link_index:11;
-                /* The POW entry attached to the core. */
-                uint64_t index:11;
-                /*
-                 * The group attached to the core (updated when new
-                 * tag list entered on SWTAG_FULL).
-                 */
-                uint64_t grp:4;
-                /*
-                 * The wqp attached to the core (updated when new tag
-                 * list entered on SWTAG_FULL).
-                 */
-                uint64_t wqp:36;
-        } s_sstatus4;
-
-    /**
-     * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
-     * get_rev==1)
-     */
-        struct {
-                uint64_t reserved_62_63:2;
-                /*
-                 * Points to the prior POW entry in the tag list when
-                 * head == 0 (and tag_type is not NULL or
-                 * NULL_NULL). This field is unpredictable when the
-                 * core's state is NULL or NULL_NULL.
-                 */
-                uint64_t revlink_index:11;
-                /* The POW entry attached to the core. */
-                uint64_t index:11;
-                /*
-                 * The group attached to the core (updated when new
-                 * tag list entered on SWTAG_FULL).
-                 */
-                uint64_t grp:4;
-                /*
-                 * The wqp attached to the core (updated when new tag
-                 * list entered on SWTAG_FULL).
-                 */
-                uint64_t wqp:36;
-        } s_sstatus5;
-
-    /**
-     * Result For POW Memory Load (get_des == 0 and get_wqp == 0)
-     */
-        struct {
-                uint64_t reserved_51_63:13;
-                /*
-                 * The next entry in the input, free, descheduled_head
-                 * list (unpredictable if entry is the tail of the
-                 * list).
-                 */
-                uint64_t next_index:11;
-                /* The group of the POW entry. */
-                uint64_t grp:4;
-                uint64_t reserved_35:1;
-                /*
-                 * Set when this POW entry is at the tail of its tag
-                 * list (also set when in the NULL or NULL_NULL
-                 * state).
-                 */
-                uint64_t tail:1;
-                /* The tag type of the POW entry. */
-                uint64_t tag_type:2;
-                /* The tag of the POW entry. */
-                uint64_t tag:32;
-        } s_smemload0;
-
-    /**
-     * Result For POW Memory Load (get_des == 0 and get_wqp == 1)
-     */
-        struct {
-                uint64_t reserved_51_63:13;
-                /*
-                 * The next entry in the input, free, descheduled_head
-                 * list (unpredictable if entry is the tail of the
-                 * list).
-                 */
-                uint64_t next_index:11;
-                /* The group of the POW entry. */
-                uint64_t grp:4;
-                /* The WQP held in the POW entry. */
-                uint64_t wqp:36;
-        } s_smemload1;
-
-    /**
-     * Result For POW Memory Load (get_des == 1)
-     */
-        struct {
-                uint64_t reserved_51_63:13;
-                /*
-                 * The next entry in the tag list connected to the
-                 * descheduled head.
-                 */
-                uint64_t fwd_index:11;
-                /* The group of the POW entry. */
-                uint64_t grp:4;
-                /* The nosched bit for the POW entry. */
-                uint64_t nosched:1;
-                /* There is a pending tag switch */
-                uint64_t pend_switch:1;
-                /*
-                 * The next tag type for the new tag list when
-                 * pend_switch is set.
-                 */
-                uint64_t pend_type:2;
-                /*
-                 * The next tag for the new tag list when pend_switch
-                 * is set.
-                 */
-                uint64_t pend_tag:32;
-        } s_smemload2;
-
-    /**
-     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
-     */
-        struct {
-                uint64_t reserved_52_63:12;
-                /*
-                 * set when there is one or more POW entries on the
-                 * free list.
-                 */
-                uint64_t free_val:1;
-                /*
-                 * set when there is exactly one POW entry on the free
-                 * list.
-                 */
-                uint64_t free_one:1;
-                uint64_t reserved_49:1;
-                /*
-                 * when free_val is set, indicates the first entry on
-                 * the free list.
-                 */
-                uint64_t free_head:11;
-                uint64_t reserved_37:1;
-                /*
-                 * when free_val is set, indicates the last entry on
-                 * the free list.
-                 */
-                uint64_t free_tail:11;
-                /*
-                 * set when there is one or more POW entries on the
-                 * input Q list selected by qosgrp.
-                 */
-                uint64_t loc_val:1;
-                /*
-                 * set when there is exactly one POW entry on the
-                 * input Q list selected by qosgrp.
-                 */
-                uint64_t loc_one:1;
-                uint64_t reserved_23:1;
-                /*
-                 * when loc_val is set, indicates the first entry on
-                 * the input Q list selected by qosgrp.
-                 */
-                uint64_t loc_head:11;
-                uint64_t reserved_11:1;
-                /*
-                 * when loc_val is set, indicates the last entry on
-                 * the input Q list selected by qosgrp.
-                 */
-                uint64_t loc_tail:11;
-        } sindexload0;
-
-    /**
-     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
-     */
-        struct {
-                uint64_t reserved_52_63:12;
-                /*
-                 * set when there is one or more POW entries on the
-                 * nosched list.
-                 */
-                uint64_t nosched_val:1;
-                /*
-                 * set when there is exactly one POW entry on the
-                 * nosched list.
-                 */
-                uint64_t nosched_one:1;
-                uint64_t reserved_49:1;
-                /*
-                 * when nosched_val is set, indicates the first entry
-                 * on the nosched list.
-                 */
-                uint64_t nosched_head:11;
-                uint64_t reserved_37:1;
-                /*
-                 * when nosched_val is set, indicates the last entry
-                 * on the nosched list.
-                 */
-                uint64_t nosched_tail:11;
-                /*
-                 * set when there is one or more descheduled heads on
-                 * the descheduled list selected by qosgrp.
-                 */
-                uint64_t des_val:1;
-                /*
-                 * set when there is exactly one descheduled head on
-                 * the descheduled list selected by qosgrp.
-                 */
-                uint64_t des_one:1;
-                uint64_t reserved_23:1;
-                /*
-                 * when des_val is set, indicates the first
-                 * descheduled head on the descheduled list selected
-                 * by qosgrp.
-                 */
-                uint64_t des_head:11;
-                uint64_t reserved_11:1;
-                /*
-                 * when des_val is set, indicates the last descheduled
-                 * head on the descheduled list selected by qosgrp.
-                 */
-                uint64_t des_tail:11;
-        } sindexload1;
-
-    /**
-     * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
-     */
-        struct {
-                uint64_t reserved_39_63:25;
-                /*
-                 * Set when this DRAM list is the current head
-                 * (i.e. is the next to be reloaded when the POW
-                 * hardware reloads a POW entry from DRAM). The POW
-                 * hardware alternates between the two DRAM lists
-                 * associated with a QOS level when it reloads work
-                 * from DRAM into the POW unit.
-                 */
-                uint64_t rmt_is_head:1;
-                /*
-                 * Set when the DRAM portion of the input Q list
-                 * selected by qosgrp contains one or more pieces of
-                 * work.
-                 */
-                uint64_t rmt_val:1;
-                /*
-                 * Set when the DRAM portion of the input Q list
-                 * selected by qosgrp contains exactly one piece of
-                 * work.
-                 */
-                uint64_t rmt_one:1;
-                /*
-                 * When rmt_val is set, indicates the first piece of
-                 * work on the DRAM input Q list selected by
-                 * qosgrp.
-                 */
-                uint64_t rmt_head:36;
-        } sindexload2;
-
-    /**
-     * Result For POW Index/Pointer Load (get_rmt ==
-     * 1/get_des_get_tail == 1)
-     */
-        struct {
-                uint64_t reserved_39_63:25;
-                /*
-                 * set when this DRAM list is the current head
-                 * (i.e. is the next to be reloaded when the POW
-                 * hardware reloads a POW entry from DRAM). The POW
-                 * hardware alternates between the two DRAM lists
-                 * associated with a QOS level when it reloads work
-                 * from DRAM into the POW unit.
-                 */
-                uint64_t rmt_is_head:1;
-                /*
-                 * set when the DRAM portion of the input Q list
-                 * selected by qosgrp contains one or more pieces of
-                 * work.
-                 */
-                uint64_t rmt_val:1;
-                /*
-                 * set when the DRAM portion of the input Q list
-                 * selected by qosgrp contains exactly one piece of
-                 * work.
-                 */
-                uint64_t rmt_one:1;
-                /*
-                 * when rmt_val is set, indicates the last piece of
-                 * work on the DRAM input Q list selected by
-                 * qosgrp.
-                 */
-                uint64_t rmt_tail:36;
-        } sindexload3;
-
-    /**
-     * Response to NULL_RD request loads
-     */
-        struct {
-                uint64_t unused:62;
-                /* of type cvmx_pow_tag_type_t. state is one of the
-                 * following:
-                 *
-                 * - CVMX_POW_TAG_TYPE_ORDERED
-                 * - CVMX_POW_TAG_TYPE_ATOMIC
-                 * - CVMX_POW_TAG_TYPE_NULL
-                 * - CVMX_POW_TAG_TYPE_NULL_NULL
-                 */
-                uint64_t state:2;
-        } s_null_rd;
-
-} cvmx_pow_tag_load_resp_t;
-
-/**
- * This structure describes the address used for stores to the POW.
- *  The store address is meaningful on stores to the POW.  The
- *  hardware assumes that an aligned 64-bit store was used for all
- *  these stores.  Note the assumption that the work queue entry is
- *  aligned on an 8-byte boundary (since the low-order 3 address bits
- *  must be zero).  Note that not all fields are used by all
- *  operations.
- *
- *  NOTE: The following is the behavior of the pending switch bit at the PP
- *       for POW stores (i.e. when did<7:3> == 0xc)
- *     - did<2:0> == 0      => pending switch bit is set
- *     - did<2:0> == 1      => no affect on the pending switch bit
- *     - did<2:0> == 3      => pending switch bit is cleared
- *     - did<2:0> == 7      => no affect on the pending switch bit
- *     - did<2:0> == others => must not be used
- *     - No other loads/stores have an affect on the pending switch bit
- *     - The switch bus from POW can clear the pending switch bit
- *
- *  NOTE: did<2:0> == 2 is used by the HW for a special single-cycle
- *  ADDWQ command that only contains the pointer). SW must never use
- *  did<2:0> == 2.
- */
-typedef union {
-    /**
-     * Unsigned 64 bit integer representation of store address
-     */
-        uint64_t u64;
-
-        struct {
-                /* Memory region.  Should be CVMX_IO_SEG in most cases */
-                uint64_t mem_reg:2;
-                uint64_t reserved_49_61:13;     /* Must be zero */
-                uint64_t is_io:1;       /* Must be one */
-                /* Device ID of POW.  Note that different sub-dids are used. */
-                uint64_t did:8;
-                uint64_t reserved_36_39:4;      /* Must be zero */
-                /* Address field. addr<2:0> must be zero */
-                uint64_t addr:36;
-        } stag;
-} cvmx_pow_tag_store_addr_t;
-
-/**
- * decode of the store data when an IOBDMA SENDSINGLE is sent to POW
- */
-typedef union {
-        uint64_t u64;
-
-        struct {
-                /*
-                 * the (64-bit word) location in scratchpad to write
-                 * to (if len != 0)
-                 */
-                uint64_t scraddr:8;
-                /* the number of words in the response (0 => no response) */
-                uint64_t len:8;
-                /* the ID of the device on the non-coherent bus */
-                uint64_t did:8;
-                uint64_t unused:36;
-                /* if set, don't return load response until work is available */
-                uint64_t wait:1;
-                uint64_t unused2:3;
-        } s;
-
-} cvmx_pow_iobdma_store_t;
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-/**
- * Get the POW tag for this core. This returns the current
- * tag type, tag, group, and POW entry index associated with
- * this core. Index is only valid if the tag type isn't NULL_NULL.
- * If a tag switch is pending this routine returns the tag before
- * the tag switch, not after.
- *
- * Returns Current tag
- */
-static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void)
-{
-        cvmx_pow_load_addr_t load_addr;
-        cvmx_pow_tag_load_resp_t load_resp;
-        cvmx_pow_tag_req_t result;
-
-        load_addr.u64 = 0;
-        load_addr.sstatus.mem_region = CVMX_IO_SEG;
-        load_addr.sstatus.is_io = 1;
-        load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
-        load_addr.sstatus.coreid = cvmx_get_core_num();
-        load_addr.sstatus.get_cur = 1;
-        load_resp.u64 = cvmx_read_csr(load_addr.u64);
-        result.u64 = 0;
-        result.s.grp = load_resp.s_sstatus2.grp;
-        result.s.index = load_resp.s_sstatus2.index;
-        result.s.type = load_resp.s_sstatus2.tag_type;
-        result.s.tag = load_resp.s_sstatus2.tag;
-        return result;
-}
-
-/**
- * Get the POW WQE for this core. This returns the work queue
- * entry currently associated with this core.
- *
- * Returns WQE pointer
- */
-static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void)
-{
-        cvmx_pow_load_addr_t load_addr;
-        cvmx_pow_tag_load_resp_t load_resp;
-
-        load_addr.u64 = 0;
-        load_addr.sstatus.mem_region = CVMX_IO_SEG;
-        load_addr.sstatus.is_io = 1;
-        load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
-        load_addr.sstatus.coreid = cvmx_get_core_num();
-        load_addr.sstatus.get_cur = 1;
-        load_addr.sstatus.get_wqp = 1;
-        load_resp.u64 = cvmx_read_csr(load_addr.u64);
-        return (cvmx_wqe_t *) cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp);
-}
-
-#ifndef CVMX_MF_CHORD
-#define CVMX_MF_CHORD(dest)         CVMX_RDHWR(dest, 30)
-#endif
-
-/**
- * Print a warning if a tag switch is pending for this core
- *
- * @function: Function name checking for a pending tag switch
- */
-static inline void __cvmx_pow_warn_if_pending_switch(const char *function)
-{
-        uint64_t switch_complete;
-        CVMX_MF_CHORD(switch_complete);
-        if (!switch_complete)
-                pr_warning("%s called with tag switch in progress\n", function);
-}
-
-/**
- * Waits for a tag switch to complete by polling the completion bit.
- * Note that switches to NULL complete immediately and do not need
- * to be waited for.
- */
-static inline void cvmx_pow_tag_sw_wait(void)
-{
-        const uint64_t MAX_CYCLES = 1ull << 31;
-        uint64_t switch_complete;
-        uint64_t start_cycle = cvmx_get_cycle();
-        while (1) {
-                CVMX_MF_CHORD(switch_complete);
-                if (unlikely(switch_complete))
-                        break;
-                if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) {
-                        pr_warning("Tag switch is taking a long time, "
-                                   "possible deadlock\n");
-                        start_cycle = -MAX_CYCLES - 1;
-                }
-        }
-}
-
-/**
- * Synchronous work request.  Requests work from the POW.
- * This function does NOT wait for previous tag switches to complete,
- * so the caller must ensure that there is not a pending tag switch.
- *
- * @wait:   When set, call stalls until work becomes avaiable, or times out.
- *               If not set, returns immediately.
- *
- * Returns Returns the WQE pointer from POW. Returns NULL if no work
- * was available.
- */
-static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t
-                                                             wait)
-{
-        cvmx_pow_load_addr_t ptr;
-        cvmx_pow_tag_load_resp_t result;
-
-        if (CVMX_ENABLE_POW_CHECKS)
-                __cvmx_pow_warn_if_pending_switch(__func__);
-
-        ptr.u64 = 0;
-        ptr.swork.mem_region = CVMX_IO_SEG;
-        ptr.swork.is_io = 1;
-        ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG;
-        ptr.swork.wait = wait;
-
-        result.u64 = cvmx_read_csr(ptr.u64);
-
-        if (result.s_work.no_work)
-                return NULL;
-        else
-                return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr);
-}
-
-/**
- * Synchronous work request.  Requests work from the POW.
- * This function waits for any previous tag switch to complete before
- * requesting the new work.
- *
- * @wait:   When set, call stalls until work becomes avaiable, or times out.
- *               If not set, returns immediately.
- *
- * Returns Returns the WQE pointer from POW. Returns NULL if no work
- * was available.
- */
-static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
-{
-        if (CVMX_ENABLE_POW_CHECKS)
-                __cvmx_pow_warn_if_pending_switch(__func__);
-
-        /* Must not have a switch pending when requesting work */
-        cvmx_pow_tag_sw_wait();
-        return cvmx_pow_work_request_sync_nocheck(wait);
-
-}
-
-/**
- * Synchronous null_rd request.  Requests a switch out of NULL_NULL POW state.
- * This function waits for any previous tag switch to complete before
- * requesting the null_rd.
- *
- * Returns Returns the POW state of type cvmx_pow_tag_type_t.
- */
-static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void)
-{
-        cvmx_pow_load_addr_t ptr;
-        cvmx_pow_tag_load_resp_t result;
-
-        if (CVMX_ENABLE_POW_CHECKS)
-                __cvmx_pow_warn_if_pending_switch(__func__);
-
-        /* Must not have a switch pending when requesting work */
-        cvmx_pow_tag_sw_wait();
-
-        ptr.u64 = 0;
-        ptr.snull_rd.mem_region = CVMX_IO_SEG;
-        ptr.snull_rd.is_io = 1;
-        ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD;
-
-        result.u64 = cvmx_read_csr(ptr.u64);
-
-        return (enum cvmx_pow_tag_type) result.s_null_rd.state;
-}
-
-/**
- * Asynchronous work request.  Work is requested from the POW unit,
- * and should later be checked with function
- * cvmx_pow_work_response_async.  This function does NOT wait for
- * previous tag switches to complete, so the caller must ensure that
- * there is not a pending tag switch.
- *
- * @scr_addr: Scratch memory address that response will be returned
- *            to, which is either a valid WQE, or a response with the
- *            invalid bit set.  Byte address, must be 8 byte aligned.
- *
- * @wait: 1 to cause response to wait for work to become available (or
- *        timeout), 0 to cause response to return immediately
- */
-static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
-                                                       cvmx_pow_wait_t wait)
-{
-        cvmx_pow_iobdma_store_t data;
-
-        if (CVMX_ENABLE_POW_CHECKS)
-                __cvmx_pow_warn_if_pending_switch(__func__);
-
-        /* scr_addr must be 8 byte aligned */
-        data.s.scraddr = scr_addr >> 3;
-        data.s.len = 1;
-        data.s.did = CVMX_OCT_DID_TAG_SWTAG;
-        data.s.wait = wait;
-        cvmx_send_single(data.u64);
-}
-
-/**
- * Asynchronous work request.  Work is requested from the POW unit,
- * and should later be checked with function
- * cvmx_pow_work_response_async.  This function waits for any previous
- * tag switch to complete before requesting the new work.
- *
- * @scr_addr: Scratch memory address that response will be returned
- *            to, which is either a valid WQE, or a response with the
- *            invalid bit set.  Byte address, must be 8 byte aligned.
- *
- * @wait: 1 to cause response to wait for work to become available (or
- *                  timeout), 0 to cause response to return immediately
- */
-static inline void cvmx_pow_work_request_async(int scr_addr,
-                                               cvmx_pow_wait_t wait)
-{
-        if (CVMX_ENABLE_POW_CHECKS)
-                __cvmx_pow_warn_if_pending_switch(__func__);
-
-        /* Must not have a switch pending when requesting work */
-        cvmx_pow_tag_sw_wait();
-        cvmx_pow_work_request_async_nocheck(scr_addr, wait);
-}
-
-/**
- * Gets result of asynchronous work request.  Performs a IOBDMA sync
- * to wait for the response.
- *
- * @scr_addr: Scratch memory address to get result from Byte address,
- *            must be 8 byte aligned.
- *
- * Returns Returns the WQE from the scratch register, or NULL if no
- * work was available.
- */
-static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr)
-{
-        cvmx_pow_tag_load_resp_t result;
-
-        CVMX_SYNCIOBDMA;
-        result.u64 = cvmx_scratch_read64(scr_addr);
-
-        if (result.s_work.no_work)
-                return NULL;
-        else
-                return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr);
-}
-
-/**
- * Checks if a work queue entry pointer returned by a work
- * request is valid.  It may be invalid due to no work
- * being available or due to a timeout.
- *
- * @wqe_ptr: pointer to a work queue entry returned by the POW
- *
- * Returns 0 if pointer is valid
- *         1 if invalid (no work was returned)
- */
-static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr)
-{
-        return wqe_ptr == NULL;
-}
-
-/**
- * Starts a tag switch to the provided tag value and tag type.
- * Completion for the tag switch must be checked for separately.  This
- * function does NOT update the work queue entry in dram to match tag
- * value and type, so the application must keep track of these if they
- * are important to the application.  This tag switch command must not
- * be used for switches to NULL, as the tag switch pending bit will be
- * set by the switch request, but never cleared by the hardware.
- *
- * NOTE: This should not be used when switching from a NULL tag.  Use
- * cvmx_pow_tag_sw_full() instead.
- *
- * This function does no checks, so the caller must ensure that any
- * previous tag switch has completed.
- *
- * @tag:      new tag value
- * @tag_type: new tag type (ordered or atomic)
- */
-static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag,
-                                           enum cvmx_pow_tag_type tag_type)
-{
-        cvmx_addr_t ptr;
-        cvmx_pow_tag_req_t tag_req;
-
-        if (CVMX_ENABLE_POW_CHECKS) {
-                cvmx_pow_tag_req_t current_tag;
-                __cvmx_pow_warn_if_pending_switch(__func__);
-                current_tag = cvmx_pow_get_current_tag();
-                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
-                        pr_warning("%s called with NULL_NULL tag\n",
-                                   __func__);
-                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
-                        pr_warning("%s called with NULL tag\n", __func__);
-                if ((current_tag.s.type == tag_type)
-                   && (current_tag.s.tag == tag))
-                        pr_warning("%s called to perform a tag switch to the "
-                                   "same tag\n",
-                             __func__);
-                if (tag_type == CVMX_POW_TAG_TYPE_NULL)
-                        pr_warning("%s called to perform a tag switch to "
-                                   "NULL. Use cvmx_pow_tag_sw_null() instead\n",
-                             __func__);
-        }
-
-        /*
-         * Note that WQE in DRAM is not updated here, as the POW does
-         * not read from DRAM once the WQE is in flight.  See hardware
-         * manual for complete details.  It is the application's
-         * responsibility to keep track of the current tag value if
-         * that is important.
-         */
-
-        tag_req.u64 = 0;
-        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
-        tag_req.s.tag = tag;
-        tag_req.s.type = tag_type;
-
-        ptr.u64 = 0;
-        ptr.sio.mem_region = CVMX_IO_SEG;
-        ptr.sio.is_io = 1;
-        ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
-
-        /* once this store arrives at POW, it will attempt the switch
-           software must wait for the switch to complete separately */
-        cvmx_write_io(ptr.u64, tag_req.u64);
-}
-
-/**
- * Starts a tag switch to the provided tag value and tag type.
- * Completion for the tag switch must be checked for separately.  This
- * function does NOT update the work queue entry in dram to match tag
- * value and type, so the application must keep track of these if they
- * are important to the application.  This tag switch command must not
- * be used for switches to NULL, as the tag switch pending bit will be
- * set by the switch request, but never cleared by the hardware.
- *
- * NOTE: This should not be used when switching from a NULL tag.  Use
- * cvmx_pow_tag_sw_full() instead.
- *
- * This function waits for any previous tag switch to complete, and also
- * displays an error on tag switches to NULL.
- *
- * @tag:      new tag value
- * @tag_type: new tag type (ordered or atomic)
- */
-static inline void cvmx_pow_tag_sw(uint32_t tag,
-                                   enum cvmx_pow_tag_type tag_type)
-{
-        if (CVMX_ENABLE_POW_CHECKS)
-                __cvmx_pow_warn_if_pending_switch(__func__);
-
-        /*
-         * Note that WQE in DRAM is not updated here, as the POW does
-         * not read from DRAM once the WQE is in flight.  See hardware
-         * manual for complete details.  It is the application's
-         * responsibility to keep track of the current tag value if
-         * that is important.
-         */
-
-        /*
-         * Ensure that there is not a pending tag switch, as a tag
-         * switch cannot be started if a previous switch is still
-         * pending.
-         */
-        cvmx_pow_tag_sw_wait();
-        cvmx_pow_tag_sw_nocheck(tag, tag_type);
-}
-
-/**
- * Starts a tag switch to the provided tag value and tag type.
- * Completion for the tag switch must be checked for separately.  This
- * function does NOT update the work queue entry in dram to match tag
- * value and type, so the application must keep track of these if they
- * are important to the application.  This tag switch command must not
- * be used for switches to NULL, as the tag switch pending bit will be
- * set by the switch request, but never cleared by the hardware.
- *
- * This function must be used for tag switches from NULL.
- *
- * This function does no checks, so the caller must ensure that any
- * previous tag switch has completed.
- *
- * @wqp:      pointer to work queue entry to submit.  This entry is
- *            updated to match the other parameters
- * @tag:      tag value to be assigned to work queue entry
- * @tag_type: type of tag
- * @group:    group value for the work queue entry.
- */
-static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag,
-                                                enum cvmx_pow_tag_type tag_type,
-                                                uint64_t group)
-{
-        cvmx_addr_t ptr;
-        cvmx_pow_tag_req_t tag_req;
-
-        if (CVMX_ENABLE_POW_CHECKS) {
-                cvmx_pow_tag_req_t current_tag;
-                __cvmx_pow_warn_if_pending_switch(__func__);
-                current_tag = cvmx_pow_get_current_tag();
-                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
-                        pr_warning("%s called with NULL_NULL tag\n",
-                                   __func__);
-                if ((current_tag.s.type == tag_type)
-                   && (current_tag.s.tag == tag))
-                        pr_warning("%s called to perform a tag switch to "
-                                   "the same tag\n",
-                             __func__);
-                if (tag_type == CVMX_POW_TAG_TYPE_NULL)
-                        pr_warning("%s called to perform a tag switch to "
-                                   "NULL. Use cvmx_pow_tag_sw_null() instead\n",
-                             __func__);
-                if (wqp != cvmx_phys_to_ptr(0x80))
-                        if (wqp != cvmx_pow_get_current_wqp())
-                                pr_warning("%s passed WQE(%p) doesn't match "
-                                           "the address in the POW(%p)\n",
-                                     __func__, wqp,
-                                     cvmx_pow_get_current_wqp());
-        }
-
-        /*
-         * Note that WQE in DRAM is not updated here, as the POW does
-         * not read from DRAM once the WQE is in flight.  See hardware
-         * manual for complete details.  It is the application's
-         * responsibility to keep track of the current tag value if
-         * that is important.
-         */
-
-        tag_req.u64 = 0;
-        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL;
-        tag_req.s.tag = tag;
-        tag_req.s.type = tag_type;
-        tag_req.s.grp = group;
-
-        ptr.u64 = 0;
-        ptr.sio.mem_region = CVMX_IO_SEG;
-        ptr.sio.is_io = 1;
-        ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
-        ptr.sio.offset = CAST64(wqp);
-
-        /*
-         * once this store arrives at POW, it will attempt the switch
-         * software must wait for the switch to complete separately.
-         */
-        cvmx_write_io(ptr.u64, tag_req.u64);
-}
-
-/**
- * Starts a tag switch to the provided tag value and tag type.
- * Completion for the tag switch must be checked for separately.  This
- * function does NOT update the work queue entry in dram to match tag
- * value and type, so the application must keep track of these if they
- * are important to the application.  This tag switch command must not
- * be used for switches to NULL, as the tag switch pending bit will be
- * set by the switch request, but never cleared by the hardware.
- *
- * This function must be used for tag switches from NULL.
- *
- * This function waits for any pending tag switches to complete
- * before requesting the tag switch.
- *
- * @wqp:      pointer to work queue entry to submit.  This entry is updated
- *            to match the other parameters
- * @tag:      tag value to be assigned to work queue entry
- * @tag_type: type of tag
- * @group:      group value for the work queue entry.
- */
-static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag,
-                                        enum cvmx_pow_tag_type tag_type,
-                                        uint64_t group)
-{
-        if (CVMX_ENABLE_POW_CHECKS)
-                __cvmx_pow_warn_if_pending_switch(__func__);
-
-        /*
-         * Ensure that there is not a pending tag switch, as a tag
-         * switch cannot be started if a previous switch is still
-         * pending.
-         */
-        cvmx_pow_tag_sw_wait();
-        cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group);
-}
-
-/**
- * Switch to a NULL tag, which ends any ordering or
- * synchronization provided by the POW for the current
- * work queue entry.  This operation completes immediately,
- * so completion should not be waited for.
- * This function does NOT wait for previous tag switches to complete,
- * so the caller must ensure that any previous tag switches have completed.
- */
-static inline void cvmx_pow_tag_sw_null_nocheck(void)
-{
-        cvmx_addr_t ptr;
-        cvmx_pow_tag_req_t tag_req;
-
-        if (CVMX_ENABLE_POW_CHECKS) {
-                cvmx_pow_tag_req_t current_tag;
-                __cvmx_pow_warn_if_pending_switch(__func__);
-                current_tag = cvmx_pow_get_current_tag();
-                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
-                        pr_warning("%s called with NULL_NULL tag\n",
-                                   __func__);
-                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
-                        pr_warning("%s called when we already have a "
-                                   "NULL tag\n",
-                             __func__);
-        }
-
-        tag_req.u64 = 0;
-        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
-        tag_req.s.type = CVMX_POW_TAG_TYPE_NULL;
-
-        ptr.u64 = 0;
-        ptr.sio.mem_region = CVMX_IO_SEG;
-        ptr.sio.is_io = 1;
-        ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
-
-        cvmx_write_io(ptr.u64, tag_req.u64);
-
-        /* switch to NULL completes immediately */
-}
-
-/**
- * Switch to a NULL tag, which ends any ordering or
- * synchronization provided by the POW for the current
- * work queue entry.  This operation completes immediately,
- * so completion should not be waited for.
- * This function waits for any pending tag switches to complete
- * before requesting the switch to NULL.
- */
-static inline void cvmx_pow_tag_sw_null(void)
-{
-        if (CVMX_ENABLE_POW_CHECKS)
-                __cvmx_pow_warn_if_pending_switch(__func__);
-
-        /*
-         * Ensure that there is not a pending tag switch, as a tag
-         * switch cannot be started if a previous switch is still
-         * pending.
-         */
-        cvmx_pow_tag_sw_wait();
-        cvmx_pow_tag_sw_null_nocheck();
-
-        /* switch to NULL completes immediately */
-}
-
-/**
- * Submits work to an input queue.  This function updates the work
- * queue entry in DRAM to match the arguments given.  Note that the
- * tag provided is for the work queue entry submitted, and is
- * unrelated to the tag that the core currently holds.
- *
- * @wqp:      pointer to work queue entry to submit.  This entry is
- *            updated to match the other parameters
- * @tag:      tag value to be assigned to work queue entry
- * @tag_type: type of tag
- * @qos:      Input queue to add to.
- * @grp:      group value for the work queue entry.
- */
-static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag,
-                                        enum cvmx_pow_tag_type tag_type,
-                                        uint64_t qos, uint64_t grp)
-{
-        cvmx_addr_t ptr;
-        cvmx_pow_tag_req_t tag_req;
-
-        wqp->qos = qos;
-        wqp->tag = tag;
-        wqp->tag_type = tag_type;
-        wqp->grp = grp;
-
-        tag_req.u64 = 0;
-        tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ;
-        tag_req.s.type = tag_type;
-        tag_req.s.tag = tag;
-        tag_req.s.qos = qos;
-        tag_req.s.grp = grp;
-
-        ptr.u64 = 0;
-        ptr.sio.mem_region = CVMX_IO_SEG;
-        ptr.sio.is_io = 1;
-        ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
-        ptr.sio.offset = cvmx_ptr_to_phys(wqp);
-
-        /*
-         * SYNC write to memory before the work submit.  This is
-         * necessary as POW may read values from DRAM at this time.
-         */
-        CVMX_SYNCWS;
-        cvmx_write_io(ptr.u64, tag_req.u64);
-}
-
-/**
- * This function sets the group mask for a core.  The group mask
- * indicates which groups each core will accept work from. There are
- * 16 groups.
- *
- * @core_num:   core to apply mask to
- * @mask:   Group mask. There are 16 groups, so only bits 0-15 are valid,
- *               representing groups 0-15.
- *               Each 1 bit in the mask enables the core to accept work from
- *               the corresponding group.
- */
-static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
-{
-        union cvmx_pow_pp_grp_mskx grp_msk;
-
-        grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
-        grp_msk.s.grp_msk = mask;
-        cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
-}
-
-/**
- * This function sets POW static priorities for a core. Each input queue has
- * an associated priority value.
- *
- * @core_num:   core to apply priorities to
- * @priority:   Vector of 8 priorities, one per POW Input Queue (0-7).
- *                   Highest priority is 0 and lowest is 7. A priority value
- *                   of 0xF instructs POW to skip the Input Queue when
- *                   scheduling to this specific core.
- *                   NOTE: priorities should not have gaps in values, meaning
- *                         {0,1,1,1,1,1,1,1} is a valid configuration while
- *                         {0,2,2,2,2,2,2,2} is not.
- */
-static inline void cvmx_pow_set_priority(uint64_t core_num,
-                                         const uint8_t priority[])
-{
-        /* POW priorities are supported on CN5xxx and later */
-        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
-                union cvmx_pow_pp_grp_mskx grp_msk;
-
-                grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
-                grp_msk.s.qos0_pri = priority[0];
-                grp_msk.s.qos1_pri = priority[1];
-                grp_msk.s.qos2_pri = priority[2];
-                grp_msk.s.qos3_pri = priority[3];
-                grp_msk.s.qos4_pri = priority[4];
-                grp_msk.s.qos5_pri = priority[5];
-                grp_msk.s.qos6_pri = priority[6];
-                grp_msk.s.qos7_pri = priority[7];
-
-                /* Detect gaps between priorities and flag error */
-                {
-                        int i;
-                        uint32_t prio_mask = 0;
-
-                        for (i = 0; i < 8; i++)
-                                if (priority[i] != 0xF)
-                                        prio_mask |= 1 << priority[i];
-
-                        if (prio_mask ^ ((1 << cvmx_pop(prio_mask)) - 1)) {
-                                pr_err("POW static priorities should be "
-                                       "contiguous (0x%llx)\n",
-                                     (unsigned long long)prio_mask);
-                                return;
-                        }
-                }
-
-                cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
-        }
-}
-
-/**
- * Performs a tag switch and then an immediate deschedule. This completes
- * immediately, so completion must not be waited for.  This function does NOT
- * update the wqe in DRAM to match arguments.
- *
- * This function does NOT wait for any prior tag switches to complete, so the
- * calling code must do this.
- *
- * Note the following CAVEAT of the Octeon HW behavior when
- * re-scheduling DE-SCHEDULEd items whose (next) state is
- * ORDERED:
- *   - If there are no switches pending at the time that the
- *     HW executes the de-schedule, the HW will only re-schedule
- *     the head of the FIFO associated with the given tag. This
- *     means that in many respects, the HW treats this ORDERED
- *     tag as an ATOMIC tag. Note that in the SWTAG_DESCH
- *     case (to an ORDERED tag), the HW will do the switch
- *     before the deschedule whenever it is possible to do
- *     the switch immediately, so it may often look like
- *     this case.
- *   - If there is a pending switch to ORDERED at the time
- *     the HW executes the de-schedule, the HW will perform
- *     the switch at the time it re-schedules, and will be
- *     able to reschedule any/all of the entries with the
- *     same tag.
- * Due to this behavior, the RECOMMENDATION to software is
- * that they have a (next) state of ATOMIC when they
- * DE-SCHEDULE. If an ORDERED tag is what was really desired,
- * SW can choose to immediately switch to an ORDERED tag
- * after the work (that has an ATOMIC tag) is re-scheduled.
- * Note that since there are never any tag switches pending
- * when the HW re-schedules, this switch can be IMMEDIATE upon
- * the reception of the pointer during the re-schedule.
- *
- * @tag:      New tag value
- * @tag_type: New tag type
- * @group:    New group value
- * @no_sched: Control whether this work queue entry will be rescheduled.
- *                 - 1 : don't schedule this work
- *                 - 0 : allow this work to be scheduled.
- */
-static inline void cvmx_pow_tag_sw_desched_nocheck(
-        uint32_t tag,
-        enum cvmx_pow_tag_type tag_type,
-        uint64_t group,
-        uint64_t no_sched)
-{
-        cvmx_addr_t ptr;
-        cvmx_pow_tag_req_t tag_req;
-
-        if (CVMX_ENABLE_POW_CHECKS) {
-                cvmx_pow_tag_req_t current_tag;
-                __cvmx_pow_warn_if_pending_switch(__func__);
-                current_tag = cvmx_pow_get_current_tag();
-                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
-                        pr_warning("%s called with NULL_NULL tag\n",
-                                   __func__);
-                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
-                        pr_warning("%s called with NULL tag. Deschedule not "
-                                   "allowed from NULL state\n",
-                             __func__);
-                if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC)
-                        && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC))
-                        pr_warning("%s called where neither the before or "
-                                   "after tag is ATOMIC\n",
-                             __func__);
-        }
-
-        tag_req.u64 = 0;
-        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH;
-        tag_req.s.tag = tag;
-        tag_req.s.type = tag_type;
-        tag_req.s.grp = group;
-        tag_req.s.no_sched = no_sched;
-
-        ptr.u64 = 0;
-        ptr.sio.mem_region = CVMX_IO_SEG;
-        ptr.sio.is_io = 1;
-        ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
-        /*
-         * since TAG3 is used, this store will clear the local pending
-         * switch bit.
-         */
-        cvmx_write_io(ptr.u64, tag_req.u64);
-}
-
-/**
- * Performs a tag switch and then an immediate deschedule. This completes
- * immediately, so completion must not be waited for.  This function does NOT
- * update the wqe in DRAM to match arguments.
- *
- * This function waits for any prior tag switches to complete, so the
- * calling code may call this function with a pending tag switch.
- *
- * Note the following CAVEAT of the Octeon HW behavior when
- * re-scheduling DE-SCHEDULEd items whose (next) state is
- * ORDERED:
- *   - If there are no switches pending at the time that the
- *     HW executes the de-schedule, the HW will only re-schedule
- *     the head of the FIFO associated with the given tag. This
- *     means that in many respects, the HW treats this ORDERED
- *     tag as an ATOMIC tag. Note that in the SWTAG_DESCH
- *     case (to an ORDERED tag), the HW will do the switch
- *     before the deschedule whenever it is possible to do
- *     the switch immediately, so it may often look like
- *     this case.
- *   - If there is a pending switch to ORDERED at the time
- *     the HW executes the de-schedule, the HW will perform
- *     the switch at the time it re-schedules, and will be
- *     able to reschedule any/all of the entries with the
- *     same tag.
- * Due to this behavior, the RECOMMENDATION to software is
- * that they have a (next) state of ATOMIC when they
- * DE-SCHEDULE. If an ORDERED tag is what was really desired,
- * SW can choose to immediately switch to an ORDERED tag
- * after the work (that has an ATOMIC tag) is re-scheduled.
- * Note that since there are never any tag switches pending
- * when the HW re-schedules, this switch can be IMMEDIATE upon
- * the reception of the pointer during the re-schedule.
- *
- * @tag:      New tag value
- * @tag_type: New tag type
- * @group:    New group value
- * @no_sched: Control whether this work queue entry will be rescheduled.
- *                 - 1 : don't schedule this work
- *                 - 0 : allow this work to be scheduled.
- */
-static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
-                                           enum cvmx_pow_tag_type tag_type,
-                                           uint64_t group, uint64_t no_sched)
-{
-        if (CVMX_ENABLE_POW_CHECKS)
-                __cvmx_pow_warn_if_pending_switch(__func__);
-
-        /* Need to make sure any writes to the work queue entry are complete */
-        CVMX_SYNCWS;
-        /*
-         * Ensure that there is not a pending tag switch, as a tag
-         * switch cannot be started if a previous switch is still
-         * pending.
-         */
-        cvmx_pow_tag_sw_wait();
-        cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched);
-}
-
-/**
- * Descchedules the current work queue entry.
- *
- * @no_sched: no schedule flag value to be set on the work queue
- *            entry.  If this is set the entry will not be
- *            rescheduled.
- */
-static inline void cvmx_pow_desched(uint64_t no_sched)
-{
-        cvmx_addr_t ptr;
-        cvmx_pow_tag_req_t tag_req;
-
-        if (CVMX_ENABLE_POW_CHECKS) {
-                cvmx_pow_tag_req_t current_tag;
-                __cvmx_pow_warn_if_pending_switch(__func__);
-                current_tag = cvmx_pow_get_current_tag();
-                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
-                        pr_warning("%s called with NULL_NULL tag\n",
-                                   __func__);
-                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
-                        pr_warning("%s called with NULL tag. Deschedule not "
-                                   "expected from NULL state\n",
-                             __func__);
-        }
-
-        /* Need to make sure any writes to the work queue entry are complete */
-        CVMX_SYNCWS;
-
-        tag_req.u64 = 0;
-        tag_req.s.op = CVMX_POW_TAG_OP_DESCH;
-        tag_req.s.no_sched = no_sched;
-
-        ptr.u64 = 0;
-        ptr.sio.mem_region = CVMX_IO_SEG;
-        ptr.sio.is_io = 1;
-        ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
-        /*
-         * since TAG3 is used, this store will clear the local pending
-         * switch bit.
-         */
-        cvmx_write_io(ptr.u64, tag_req.u64);
-}
-
-/****************************************************
-* Define usage of bits within the 32 bit tag values.
-*****************************************************/
-
-/*
- * Number of bits of the tag used by software.  The SW bits are always
- * a contiguous block of the high starting at bit 31.  The hardware
- * bits are always the low bits.  By default, the top 8 bits of the
- * tag are reserved for software, and the low 24 are set by the IPD
- * unit.
- */
-#define CVMX_TAG_SW_BITS    (8)
-#define CVMX_TAG_SW_SHIFT   (32 - CVMX_TAG_SW_BITS)
-
-/* Below is the list of values for the top 8 bits of the tag. */
-/*
- * Tag values with top byte of this value are reserved for internal
- * executive uses.
- */
-#define CVMX_TAG_SW_BITS_INTERNAL  0x1
-/* The executive divides the remaining 24 bits as follows:
- *  - the upper 8 bits (bits 23 - 16 of the tag) define a subgroup
- *
- *  - the lower 16 bits (bits 15 - 0 of the tag) define are the value
- *    with the subgroup
- *
- * Note that this section describes the format of tags generated by
- * software - refer to the hardware documentation for a description of
- * the tags values generated by the packet input hardware.  Subgroups
- * are defined here.
- */
-/* Mask for the value portion of the tag */
-#define CVMX_TAG_SUBGROUP_MASK  0xFFFF
-#define CVMX_TAG_SUBGROUP_SHIFT 16
-#define CVMX_TAG_SUBGROUP_PKO  0x1
-
-/* End of executive tag subgroup definitions */
-
-/*
- * The remaining values software bit values 0x2 - 0xff are available
- * for application use.
- */
-
-/**
- * This function creates a 32 bit tag value from the two values provided.
- *
- * @sw_bits: The upper bits (number depends on configuration) are set
- *           to this value.  The remainder of bits are set by the
- *           hw_bits parameter.
- *
- * @hw_bits: The lower bits (number depends on configuration) are set
- *           to this value.  The remainder of bits are set by the
- *           sw_bits parameter.
- *
- * Returns 32 bit value of the combined hw and sw bits.
- */
-static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits)
-{
-        return ((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) <<
-                        CVMX_TAG_SW_SHIFT) |
-                (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS));
-}
-
-/**
- * Extracts the bits allocated for software use from the tag
- *
- * @tag:    32 bit tag value
- *
- * Returns N bit software tag value, where N is configurable with the
- * CVMX_TAG_SW_BITS define
- */
-static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag)
-{
-        return (tag >> (32 - CVMX_TAG_SW_BITS)) &
-                cvmx_build_mask(CVMX_TAG_SW_BITS);
-}
-
-/**
- *
- * Extracts the bits allocated for hardware use from the tag
- *
- * @tag:    32 bit tag value
- *
- * Returns (32 - N) bit software tag value, where N is configurable
- * with the CVMX_TAG_SW_BITS define
- */
-static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag)
-{
-        return tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS);
-}
-
-/**
- * Store the current POW internal state into the supplied
- * buffer. It is recommended that you pass a buffer of at least
- * 128KB. The format of the capture may change based on SDK
- * version and Octeon chip.
- *
- * @buffer: Buffer to store capture into
- * @buffer_size:
- *               The size of the supplied buffer
- *
- * Returns Zero on success, negative on failure
- */
-extern int cvmx_pow_capture(void *buffer, int buffer_size);
-
-/**
- * Dump a POW capture to the console in a human readable format.
- *
- * @buffer: POW capture from cvmx_pow_capture()
- * @buffer_size:
- *               Size of the buffer
- */
-extern void cvmx_pow_display(void *buffer, int buffer_size);
-
-/**
- * Return the number of POW entries supported by this chip
- *
- * Returns Number of POW entries
- */
-extern int cvmx_pow_get_num_entries(void);
-
-#endif /* __CVMX_POW_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
index 87d6f92a548..c45da1f35ea 100644
--- a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,6 +28,8 @@
 #ifndef __CVMX_RNM_DEFS_H__
 #define __CVMX_RNM_DEFS_H__
 
+#include <linux/types.h>
+
 #define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
 #define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
 #define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
@@ -37,15 +39,9 @@
 union cvmx_rnm_bist_status {
         uint64_t u64;
         struct cvmx_rnm_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_2_63:62;
                 uint64_t rrc:1;
                 uint64_t mem:1;
-#else
-                uint64_t mem:1;
-                uint64_t rrc:1;
-                uint64_t reserved_2_63:62;
-#endif
         } s;
         struct cvmx_rnm_bist_status_s cn30xx;
         struct cvmx_rnm_bist_status_s cn31xx;
@@ -58,21 +54,14 @@ union cvmx_rnm_bist_status {
         struct cvmx_rnm_bist_status_s cn56xxp1;
         struct cvmx_rnm_bist_status_s cn58xx;
         struct cvmx_rnm_bist_status_s cn58xxp1;
-        struct cvmx_rnm_bist_status_s cn61xx;
         struct cvmx_rnm_bist_status_s cn63xx;
         struct cvmx_rnm_bist_status_s cn63xxp1;
-        struct cvmx_rnm_bist_status_s cn66xx;
-        struct cvmx_rnm_bist_status_s cn68xx;
-        struct cvmx_rnm_bist_status_s cn68xxp1;
-        struct cvmx_rnm_bist_status_s cnf71xx;
 };
 
 union cvmx_rnm_ctl_status {
         uint64_t u64;
         struct cvmx_rnm_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t dis_mak:1;
+                uint64_t reserved_11_63:53;
                 uint64_t eer_lck:1;
                 uint64_t eer_val:1;
                 uint64_t ent_sel:4;
@@ -81,39 +70,18 @@ union cvmx_rnm_ctl_status {
                 uint64_t rnm_rst:1;
                 uint64_t rng_en:1;
                 uint64_t ent_en:1;
-#else
-                uint64_t ent_en:1;
-                uint64_t rng_en:1;
-                uint64_t rnm_rst:1;
-                uint64_t rng_rst:1;
-                uint64_t exp_ent:1;
-                uint64_t ent_sel:4;
-                uint64_t eer_val:1;
-                uint64_t eer_lck:1;
-                uint64_t dis_mak:1;
-                uint64_t reserved_12_63:52;
-#endif
         } s;
         struct cvmx_rnm_ctl_status_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_4_63:60;
                 uint64_t rng_rst:1;
                 uint64_t rnm_rst:1;
                 uint64_t rng_en:1;
                 uint64_t ent_en:1;
-#else
-                uint64_t ent_en:1;
-                uint64_t rng_en:1;
-                uint64_t rnm_rst:1;
-                uint64_t rng_rst:1;
-                uint64_t reserved_4_63:60;
-#endif
         } cn30xx;
         struct cvmx_rnm_ctl_status_cn30xx cn31xx;
         struct cvmx_rnm_ctl_status_cn30xx cn38xx;
         struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
         struct cvmx_rnm_ctl_status_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_9_63:55;
                 uint64_t ent_sel:4;
                 uint64_t exp_ent:1;
@@ -121,15 +89,6 @@ union cvmx_rnm_ctl_status {
                 uint64_t rnm_rst:1;
                 uint64_t rng_en:1;
                 uint64_t ent_en:1;
-#else
-                uint64_t ent_en:1;
-                uint64_t rng_en:1;
-                uint64_t rnm_rst:1;
-                uint64_t rng_rst:1;
-                uint64_t exp_ent:1;
-                uint64_t ent_sel:4;
-                uint64_t reserved_9_63:55;
-#endif
         } cn50xx;
         struct cvmx_rnm_ctl_status_cn50xx cn52xx;
         struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
@@ -137,88 +96,34 @@ union cvmx_rnm_ctl_status {
         struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
         struct cvmx_rnm_ctl_status_cn50xx cn58xx;
         struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
-        struct cvmx_rnm_ctl_status_s cn61xx;
-        struct cvmx_rnm_ctl_status_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t eer_lck:1;
-                uint64_t eer_val:1;
-                uint64_t ent_sel:4;
-                uint64_t exp_ent:1;
-                uint64_t rng_rst:1;
-                uint64_t rnm_rst:1;
-                uint64_t rng_en:1;
-                uint64_t ent_en:1;
-#else
-                uint64_t ent_en:1;
-                uint64_t rng_en:1;
-                uint64_t rnm_rst:1;
-                uint64_t rng_rst:1;
-                uint64_t exp_ent:1;
-                uint64_t ent_sel:4;
-                uint64_t eer_val:1;
-                uint64_t eer_lck:1;
-                uint64_t reserved_11_63:53;
-#endif
-        } cn63xx;
-        struct cvmx_rnm_ctl_status_cn63xx cn63xxp1;
-        struct cvmx_rnm_ctl_status_s cn66xx;
-        struct cvmx_rnm_ctl_status_cn63xx cn68xx;
-        struct cvmx_rnm_ctl_status_cn63xx cn68xxp1;
-        struct cvmx_rnm_ctl_status_s cnf71xx;
+        struct cvmx_rnm_ctl_status_s cn63xx;
+        struct cvmx_rnm_ctl_status_s cn63xxp1;
 };
 
 union cvmx_rnm_eer_dbg {
         uint64_t u64;
         struct cvmx_rnm_eer_dbg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t dat:64;
-#else
-                uint64_t dat:64;
-#endif
         } s;
-        struct cvmx_rnm_eer_dbg_s cn61xx;
         struct cvmx_rnm_eer_dbg_s cn63xx;
         struct cvmx_rnm_eer_dbg_s cn63xxp1;
-        struct cvmx_rnm_eer_dbg_s cn66xx;
-        struct cvmx_rnm_eer_dbg_s cn68xx;
-        struct cvmx_rnm_eer_dbg_s cn68xxp1;
-        struct cvmx_rnm_eer_dbg_s cnf71xx;
 };
 
 union cvmx_rnm_eer_key {
         uint64_t u64;
         struct cvmx_rnm_eer_key_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t key:64;
-#else
                 uint64_t key:64;
-#endif
         } s;
-        struct cvmx_rnm_eer_key_s cn61xx;
         struct cvmx_rnm_eer_key_s cn63xx;
         struct cvmx_rnm_eer_key_s cn63xxp1;
-        struct cvmx_rnm_eer_key_s cn66xx;
-        struct cvmx_rnm_eer_key_s cn68xx;
-        struct cvmx_rnm_eer_key_s cn68xxp1;
-        struct cvmx_rnm_eer_key_s cnf71xx;
 };
 
 union cvmx_rnm_serial_num {
         uint64_t u64;
         struct cvmx_rnm_serial_num_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dat:64;
-#else
                 uint64_t dat:64;
-#endif
         } s;
-        struct cvmx_rnm_serial_num_s cn61xx;
         struct cvmx_rnm_serial_num_s cn63xx;
-        struct cvmx_rnm_serial_num_s cn66xx;
-        struct cvmx_rnm_serial_num_s cn68xx;
-        struct cvmx_rnm_serial_num_s cn68xxp1;
-        struct cvmx_rnm_serial_num_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h
deleted file mode 100644
index 96b70cfd624..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-scratch.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- *
- * This file provides support for the processor local scratch memory.
- * Scratch memory is byte addressable - all addresses are byte addresses.
- *
- */
-
-#ifndef __CVMX_SCRATCH_H__
-#define __CVMX_SCRATCH_H__
-
-/*
- * Note: This define must be a long, not a long long in order to
- * compile without warnings for both 32bit and 64bit.
- */
-#define CVMX_SCRATCH_BASE       (-32768l)       /* 0xffffffffffff8000 */
-
-/**
- * Reads an 8 bit value from the processor local scratchpad memory.
- *
- * @address: byte address to read from
- *
- * Returns value read
- */
-static inline uint8_t cvmx_scratch_read8(uint64_t address)
-{
-        return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address);
-}
-
-/**
- * Reads a 16 bit value from the processor local scratchpad memory.
- *
- * @address: byte address to read from
- *
- * Returns value read
- */
-static inline uint16_t cvmx_scratch_read16(uint64_t address)
-{
-        return *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address);
-}
-
-/**
- * Reads a 32 bit value from the processor local scratchpad memory.
- *
- * @address: byte address to read from
- *
- * Returns value read
- */
-static inline uint32_t cvmx_scratch_read32(uint64_t address)
-{
-        return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address);
-}
-
-/**
- * Reads a 64 bit value from the processor local scratchpad memory.
- *
- * @address: byte address to read from
- *
- * Returns value read
- */
-static inline uint64_t cvmx_scratch_read64(uint64_t address)
-{
-        return *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address);
-}
-
-/**
- * Writes an 8 bit value to the processor local scratchpad memory.
- *
- * @address: byte address to write to
- * @value:   value to write
- */
-static inline void cvmx_scratch_write8(uint64_t address, uint64_t value)
-{
-        *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) =
-            (uint8_t) value;
-}
-
-/**
- * Writes a 32 bit value to the processor local scratchpad memory.
- *
- * @address: byte address to write to
- * @value:   value to write
- */
-static inline void cvmx_scratch_write16(uint64_t address, uint64_t value)
-{
-        *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address) =
-            (uint16_t) value;
-}
-
-/**
- * Writes a 16 bit value to the processor local scratchpad memory.
- *
- * @address: byte address to write to
- * @value:   value to write
- */
-static inline void cvmx_scratch_write32(uint64_t address, uint64_t value)
-{
-        *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) =
-            (uint32_t) value;
-}
-
-/**
- * Writes a 64 bit value to the processor local scratchpad memory.
- *
- * @address: byte address to write to
- * @value:   value to write
- */
-static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
-{
-        *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address) = value;
-}
-
-#endif /* __CVMX_SCRATCH_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
deleted file mode 100644
index e697c2f52a6..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-sli-defs.h
+++ /dev/null
@@ -1,3521 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_SLI_DEFS_H__
-#define __CVMX_SLI_DEFS_H__
-
-#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
-#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
-#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
-#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
-#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
-#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
-#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
-#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
-#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
-#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
-#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
-#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
-#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
-#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
-#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
-#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
-#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
-#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
-#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
-#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
-#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
-#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
-#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
-#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
-#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
-#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
-#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
-#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
-#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
-#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
-#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
-#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
-#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
-#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
-#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
-#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
-#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
-#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
-#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
-#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
-#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
-#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
-#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
-#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
-#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
-#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
-#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
-#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
-#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
-#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
-#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
-#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
-#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
-#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
-#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
-#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
-#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
-#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
-#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
-#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
-#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
-#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
-#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
-#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
-#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
-#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
-#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
-#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
-#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
-#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
-#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
-#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
-#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
-#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
-#define CVMX_SLI_STATE1 (0x0000000000000620ull)
-#define CVMX_SLI_STATE2 (0x0000000000000630ull)
-#define CVMX_SLI_STATE3 (0x0000000000000640ull)
-#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
-#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
-#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
-#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
-#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
-#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
-#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
-
-union cvmx_sli_bist_status {
-        uint64_t u64;
-        struct cvmx_sli_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ncb_req:1;
-                uint64_t n2p0_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p1_o:1;
-                uint64_t cpl_p0:1;
-                uint64_t cpl_p1:1;
-                uint64_t reserved_19_24:6;
-                uint64_t p2n0_c0:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_p1:1;
-                uint64_t reserved_6_8:3;
-                uint64_t dsi1_1:1;
-                uint64_t dsi1_0:1;
-                uint64_t dsi0_1:1;
-                uint64_t dsi0_0:1;
-                uint64_t msi:1;
-                uint64_t ncb_cmd:1;
-#else
-                uint64_t ncb_cmd:1;
-                uint64_t msi:1;
-                uint64_t dsi0_0:1;
-                uint64_t dsi0_1:1;
-                uint64_t dsi1_0:1;
-                uint64_t dsi1_1:1;
-                uint64_t reserved_6_8:3;
-                uint64_t p2n1_p1:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_c0:1;
-                uint64_t reserved_19_24:6;
-                uint64_t cpl_p1:1;
-                uint64_t cpl_p0:1;
-                uint64_t n2p1_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p0_c:1;
-                uint64_t ncb_req:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_bist_status_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_31_63:33;
-                uint64_t n2p0_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t reserved_27_28:2;
-                uint64_t cpl_p0:1;
-                uint64_t cpl_p1:1;
-                uint64_t reserved_19_24:6;
-                uint64_t p2n0_c0:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_p1:1;
-                uint64_t reserved_6_8:3;
-                uint64_t dsi1_1:1;
-                uint64_t dsi1_0:1;
-                uint64_t dsi0_1:1;
-                uint64_t dsi0_0:1;
-                uint64_t msi:1;
-                uint64_t ncb_cmd:1;
-#else
-                uint64_t ncb_cmd:1;
-                uint64_t msi:1;
-                uint64_t dsi0_0:1;
-                uint64_t dsi0_1:1;
-                uint64_t dsi1_0:1;
-                uint64_t dsi1_1:1;
-                uint64_t reserved_6_8:3;
-                uint64_t p2n1_p1:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_c0:1;
-                uint64_t reserved_19_24:6;
-                uint64_t cpl_p1:1;
-                uint64_t cpl_p0:1;
-                uint64_t reserved_27_28:2;
-                uint64_t n2p0_o:1;
-                uint64_t n2p0_c:1;
-                uint64_t reserved_31_63:33;
-#endif
-        } cn61xx;
-        struct cvmx_sli_bist_status_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_31_63:33;
-                uint64_t n2p0_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p1_o:1;
-                uint64_t cpl_p0:1;
-                uint64_t cpl_p1:1;
-                uint64_t reserved_19_24:6;
-                uint64_t p2n0_c0:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_p1:1;
-                uint64_t reserved_6_8:3;
-                uint64_t dsi1_1:1;
-                uint64_t dsi1_0:1;
-                uint64_t dsi0_1:1;
-                uint64_t dsi0_0:1;
-                uint64_t msi:1;
-                uint64_t ncb_cmd:1;
-#else
-                uint64_t ncb_cmd:1;
-                uint64_t msi:1;
-                uint64_t dsi0_0:1;
-                uint64_t dsi0_1:1;
-                uint64_t dsi1_0:1;
-                uint64_t dsi1_1:1;
-                uint64_t reserved_6_8:3;
-                uint64_t p2n1_p1:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_c0:1;
-                uint64_t reserved_19_24:6;
-                uint64_t cpl_p1:1;
-                uint64_t cpl_p0:1;
-                uint64_t n2p1_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p0_c:1;
-                uint64_t reserved_31_63:33;
-#endif
-        } cn63xx;
-        struct cvmx_sli_bist_status_cn63xx cn63xxp1;
-        struct cvmx_sli_bist_status_cn61xx cn66xx;
-        struct cvmx_sli_bist_status_s cn68xx;
-        struct cvmx_sli_bist_status_s cn68xxp1;
-        struct cvmx_sli_bist_status_cn61xx cnf71xx;
-};
-
-union cvmx_sli_ctl_portx {
-        uint64_t u64;
-        struct cvmx_sli_ctl_portx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t intd:1;
-                uint64_t intc:1;
-                uint64_t intb:1;
-                uint64_t inta:1;
-                uint64_t dis_port:1;
-                uint64_t waitl_com:1;
-                uint64_t intd_map:2;
-                uint64_t intc_map:2;
-                uint64_t intb_map:2;
-                uint64_t inta_map:2;
-                uint64_t ctlp_ro:1;
-                uint64_t reserved_6_6:1;
-                uint64_t ptlp_ro:1;
-                uint64_t reserved_1_4:4;
-                uint64_t wait_com:1;
-#else
-                uint64_t wait_com:1;
-                uint64_t reserved_1_4:4;
-                uint64_t ptlp_ro:1;
-                uint64_t reserved_6_6:1;
-                uint64_t ctlp_ro:1;
-                uint64_t inta_map:2;
-                uint64_t intb_map:2;
-                uint64_t intc_map:2;
-                uint64_t intd_map:2;
-                uint64_t waitl_com:1;
-                uint64_t dis_port:1;
-                uint64_t inta:1;
-                uint64_t intb:1;
-                uint64_t intc:1;
-                uint64_t intd:1;
-                uint64_t reserved_22_63:42;
-#endif
-        } s;
-        struct cvmx_sli_ctl_portx_s cn61xx;
-        struct cvmx_sli_ctl_portx_s cn63xx;
-        struct cvmx_sli_ctl_portx_s cn63xxp1;
-        struct cvmx_sli_ctl_portx_s cn66xx;
-        struct cvmx_sli_ctl_portx_s cn68xx;
-        struct cvmx_sli_ctl_portx_s cn68xxp1;
-        struct cvmx_sli_ctl_portx_s cnf71xx;
-};
-
-union cvmx_sli_ctl_status {
-        uint64_t u64;
-        struct cvmx_sli_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_20_63:44;
-                uint64_t p1_ntags:6;
-                uint64_t p0_ntags:6;
-                uint64_t chip_rev:8;
-#else
-                uint64_t chip_rev:8;
-                uint64_t p0_ntags:6;
-                uint64_t p1_ntags:6;
-                uint64_t reserved_20_63:44;
-#endif
-        } s;
-        struct cvmx_sli_ctl_status_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t p0_ntags:6;
-                uint64_t chip_rev:8;
-#else
-                uint64_t chip_rev:8;
-                uint64_t p0_ntags:6;
-                uint64_t reserved_14_63:50;
-#endif
-        } cn61xx;
-        struct cvmx_sli_ctl_status_s cn63xx;
-        struct cvmx_sli_ctl_status_s cn63xxp1;
-        struct cvmx_sli_ctl_status_cn61xx cn66xx;
-        struct cvmx_sli_ctl_status_s cn68xx;
-        struct cvmx_sli_ctl_status_s cn68xxp1;
-        struct cvmx_sli_ctl_status_cn61xx cnf71xx;
-};
-
-union cvmx_sli_data_out_cnt {
-        uint64_t u64;
-        struct cvmx_sli_data_out_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t p1_ucnt:16;
-                uint64_t p1_fcnt:6;
-                uint64_t p0_ucnt:16;
-                uint64_t p0_fcnt:6;
-#else
-                uint64_t p0_fcnt:6;
-                uint64_t p0_ucnt:16;
-                uint64_t p1_fcnt:6;
-                uint64_t p1_ucnt:16;
-                uint64_t reserved_44_63:20;
-#endif
-        } s;
-        struct cvmx_sli_data_out_cnt_s cn61xx;
-        struct cvmx_sli_data_out_cnt_s cn63xx;
-        struct cvmx_sli_data_out_cnt_s cn63xxp1;
-        struct cvmx_sli_data_out_cnt_s cn66xx;
-        struct cvmx_sli_data_out_cnt_s cn68xx;
-        struct cvmx_sli_data_out_cnt_s cn68xxp1;
-        struct cvmx_sli_data_out_cnt_s cnf71xx;
-};
-
-union cvmx_sli_dbg_data {
-        uint64_t u64;
-        struct cvmx_sli_dbg_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_18_63:46;
-                uint64_t dsel_ext:1;
-                uint64_t data:17;
-#else
-                uint64_t data:17;
-                uint64_t dsel_ext:1;
-                uint64_t reserved_18_63:46;
-#endif
-        } s;
-        struct cvmx_sli_dbg_data_s cn61xx;
-        struct cvmx_sli_dbg_data_s cn63xx;
-        struct cvmx_sli_dbg_data_s cn63xxp1;
-        struct cvmx_sli_dbg_data_s cn66xx;
-        struct cvmx_sli_dbg_data_s cn68xx;
-        struct cvmx_sli_dbg_data_s cn68xxp1;
-        struct cvmx_sli_dbg_data_s cnf71xx;
-};
-
-union cvmx_sli_dbg_select {
-        uint64_t u64;
-        struct cvmx_sli_dbg_select_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t adbg_sel:1;
-                uint64_t dbg_sel:32;
-#else
-                uint64_t dbg_sel:32;
-                uint64_t adbg_sel:1;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_sli_dbg_select_s cn61xx;
-        struct cvmx_sli_dbg_select_s cn63xx;
-        struct cvmx_sli_dbg_select_s cn63xxp1;
-        struct cvmx_sli_dbg_select_s cn66xx;
-        struct cvmx_sli_dbg_select_s cn68xx;
-        struct cvmx_sli_dbg_select_s cn68xxp1;
-        struct cvmx_sli_dbg_select_s cnf71xx;
-};
-
-union cvmx_sli_dmax_cnt {
-        uint64_t u64;
-        struct cvmx_sli_dmax_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_dmax_cnt_s cn61xx;
-        struct cvmx_sli_dmax_cnt_s cn63xx;
-        struct cvmx_sli_dmax_cnt_s cn63xxp1;
-        struct cvmx_sli_dmax_cnt_s cn66xx;
-        struct cvmx_sli_dmax_cnt_s cn68xx;
-        struct cvmx_sli_dmax_cnt_s cn68xxp1;
-        struct cvmx_sli_dmax_cnt_s cnf71xx;
-};
-
-union cvmx_sli_dmax_int_level {
-        uint64_t u64;
-        struct cvmx_sli_dmax_int_level_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t time:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t time:32;
-#endif
-        } s;
-        struct cvmx_sli_dmax_int_level_s cn61xx;
-        struct cvmx_sli_dmax_int_level_s cn63xx;
-        struct cvmx_sli_dmax_int_level_s cn63xxp1;
-        struct cvmx_sli_dmax_int_level_s cn66xx;
-        struct cvmx_sli_dmax_int_level_s cn68xx;
-        struct cvmx_sli_dmax_int_level_s cn68xxp1;
-        struct cvmx_sli_dmax_int_level_s cnf71xx;
-};
-
-union cvmx_sli_dmax_tim {
-        uint64_t u64;
-        struct cvmx_sli_dmax_tim_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t tim:32;
-#else
-                uint64_t tim:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_dmax_tim_s cn61xx;
-        struct cvmx_sli_dmax_tim_s cn63xx;
-        struct cvmx_sli_dmax_tim_s cn63xxp1;
-        struct cvmx_sli_dmax_tim_s cn66xx;
-        struct cvmx_sli_dmax_tim_s cn68xx;
-        struct cvmx_sli_dmax_tim_s cn68xxp1;
-        struct cvmx_sli_dmax_tim_s cnf71xx;
-};
-
-union cvmx_sli_int_enb_ciu {
-        uint64_t u64;
-        struct cvmx_sli_int_enb_ciu_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t pipe_err:1;
-                uint64_t ill_pad:1;
-                uint64_t sprt3_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_28_31:4;
-                uint64_t m3_un_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_up_b0:1;
-                uint64_t reserved_18_19:2;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t reserved_18_19:2;
-                uint64_t m2_up_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_un_wi:1;
-                uint64_t reserved_28_31:4;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt3_err:1;
-                uint64_t ill_pad:1;
-                uint64_t pipe_err:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_sli_int_enb_ciu_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t ill_pad:1;
-                uint64_t sprt3_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_28_31:4;
-                uint64_t m3_un_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_up_b0:1;
-                uint64_t reserved_18_19:2;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t reserved_18_19:2;
-                uint64_t m2_up_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_un_wi:1;
-                uint64_t reserved_28_31:4;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt3_err:1;
-                uint64_t ill_pad:1;
-                uint64_t reserved_61_63:3;
-#endif
-        } cn61xx;
-        struct cvmx_sli_int_enb_ciu_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t ill_pad:1;
-                uint64_t reserved_58_59:2;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_18_31:14;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t reserved_18_31:14;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t reserved_58_59:2;
-                uint64_t ill_pad:1;
-                uint64_t reserved_61_63:3;
-#endif
-        } cn63xx;
-        struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
-        struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
-        struct cvmx_sli_int_enb_ciu_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t pipe_err:1;
-                uint64_t ill_pad:1;
-                uint64_t reserved_58_59:2;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t reserved_51_51:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_18_31:14;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t reserved_18_31:14;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t reserved_51_51:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t reserved_58_59:2;
-                uint64_t ill_pad:1;
-                uint64_t pipe_err:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } cn68xx;
-        struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
-        struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx;
-};
-
-union cvmx_sli_int_enb_portx {
-        uint64_t u64;
-        struct cvmx_sli_int_enb_portx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t pipe_err:1;
-                uint64_t ill_pad:1;
-                uint64_t sprt3_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_28_31:4;
-                uint64_t m3_un_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_up_b0:1;
-                uint64_t mac1_int:1;
-                uint64_t mac0_int:1;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t mac0_int:1;
-                uint64_t mac1_int:1;
-                uint64_t m2_up_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_un_wi:1;
-                uint64_t reserved_28_31:4;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt3_err:1;
-                uint64_t ill_pad:1;
-                uint64_t pipe_err:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_sli_int_enb_portx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t ill_pad:1;
-                uint64_t sprt3_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_28_31:4;
-                uint64_t m3_un_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_up_b0:1;
-                uint64_t mac1_int:1;
-                uint64_t mac0_int:1;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t mac0_int:1;
-                uint64_t mac1_int:1;
-                uint64_t m2_up_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_un_wi:1;
-                uint64_t reserved_28_31:4;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt3_err:1;
-                uint64_t ill_pad:1;
-                uint64_t reserved_61_63:3;
-#endif
-        } cn61xx;
-        struct cvmx_sli_int_enb_portx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t ill_pad:1;
-                uint64_t reserved_58_59:2;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_20_31:12;
-                uint64_t mac1_int:1;
-                uint64_t mac0_int:1;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t mac0_int:1;
-                uint64_t mac1_int:1;
-                uint64_t reserved_20_31:12;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t reserved_58_59:2;
-                uint64_t ill_pad:1;
-                uint64_t reserved_61_63:3;
-#endif
-        } cn63xx;
-        struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
-        struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
-        struct cvmx_sli_int_enb_portx_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t pipe_err:1;
-                uint64_t ill_pad:1;
-                uint64_t reserved_58_59:2;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t reserved_51_51:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_20_31:12;
-                uint64_t mac1_int:1;
-                uint64_t mac0_int:1;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t mac0_int:1;
-                uint64_t mac1_int:1;
-                uint64_t reserved_20_31:12;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t reserved_51_51:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t reserved_58_59:2;
-                uint64_t ill_pad:1;
-                uint64_t pipe_err:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } cn68xx;
-        struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
-        struct cvmx_sli_int_enb_portx_cn61xx cnf71xx;
-};
-
-union cvmx_sli_int_sum {
-        uint64_t u64;
-        struct cvmx_sli_int_sum_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t pipe_err:1;
-                uint64_t ill_pad:1;
-                uint64_t sprt3_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_28_31:4;
-                uint64_t m3_un_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_up_b0:1;
-                uint64_t mac1_int:1;
-                uint64_t mac0_int:1;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t mac0_int:1;
-                uint64_t mac1_int:1;
-                uint64_t m2_up_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_un_wi:1;
-                uint64_t reserved_28_31:4;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt3_err:1;
-                uint64_t ill_pad:1;
-                uint64_t pipe_err:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } s;
-        struct cvmx_sli_int_sum_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t ill_pad:1;
-                uint64_t sprt3_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_28_31:4;
-                uint64_t m3_un_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_up_b0:1;
-                uint64_t mac1_int:1;
-                uint64_t mac0_int:1;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t mac0_int:1;
-                uint64_t mac1_int:1;
-                uint64_t m2_up_b0:1;
-                uint64_t m2_up_wi:1;
-                uint64_t m2_un_b0:1;
-                uint64_t m2_un_wi:1;
-                uint64_t m3_up_b0:1;
-                uint64_t m3_up_wi:1;
-                uint64_t m3_un_b0:1;
-                uint64_t m3_un_wi:1;
-                uint64_t reserved_28_31:4;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t sprt2_err:1;
-                uint64_t sprt3_err:1;
-                uint64_t ill_pad:1;
-                uint64_t reserved_61_63:3;
-#endif
-        } cn61xx;
-        struct cvmx_sli_int_sum_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_61_63:3;
-                uint64_t ill_pad:1;
-                uint64_t reserved_58_59:2;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_20_31:12;
-                uint64_t mac1_int:1;
-                uint64_t mac0_int:1;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t mac0_int:1;
-                uint64_t mac1_int:1;
-                uint64_t reserved_20_31:12;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t pin_bp:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t reserved_58_59:2;
-                uint64_t ill_pad:1;
-                uint64_t reserved_61_63:3;
-#endif
-        } cn63xx;
-        struct cvmx_sli_int_sum_cn63xx cn63xxp1;
-        struct cvmx_sli_int_sum_cn61xx cn66xx;
-        struct cvmx_sli_int_sum_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_62_63:2;
-                uint64_t pipe_err:1;
-                uint64_t ill_pad:1;
-                uint64_t reserved_58_59:2;
-                uint64_t sprt1_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t pins_err:1;
-                uint64_t pop_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pgl_err:1;
-                uint64_t reserved_51_51:1;
-                uint64_t pout_err:1;
-                uint64_t psldbof:1;
-                uint64_t pidbof:1;
-                uint64_t reserved_38_47:10;
-                uint64_t dtime:2;
-                uint64_t dcnt:2;
-                uint64_t dmafi:2;
-                uint64_t reserved_20_31:12;
-                uint64_t mac1_int:1;
-                uint64_t mac0_int:1;
-                uint64_t mio_int1:1;
-                uint64_t mio_int0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_up_b0:1;
-                uint64_t reserved_6_7:2;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t iob2big:1;
-                uint64_t bar0_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t rml_to:1;
-#else
-                uint64_t rml_to:1;
-                uint64_t reserved_1_1:1;
-                uint64_t bar0_to:1;
-                uint64_t iob2big:1;
-                uint64_t pcnt:1;
-                uint64_t ptime:1;
-                uint64_t reserved_6_7:2;
-                uint64_t m0_up_b0:1;
-                uint64_t m0_up_wi:1;
-                uint64_t m0_un_b0:1;
-                uint64_t m0_un_wi:1;
-                uint64_t m1_up_b0:1;
-                uint64_t m1_up_wi:1;
-                uint64_t m1_un_b0:1;
-                uint64_t m1_un_wi:1;
-                uint64_t mio_int0:1;
-                uint64_t mio_int1:1;
-                uint64_t mac0_int:1;
-                uint64_t mac1_int:1;
-                uint64_t reserved_20_31:12;
-                uint64_t dmafi:2;
-                uint64_t dcnt:2;
-                uint64_t dtime:2;
-                uint64_t reserved_38_47:10;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
-                uint64_t pout_err:1;
-                uint64_t reserved_51_51:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t sprt0_err:1;
-                uint64_t sprt1_err:1;
-                uint64_t reserved_58_59:2;
-                uint64_t ill_pad:1;
-                uint64_t pipe_err:1;
-                uint64_t reserved_62_63:2;
-#endif
-        } cn68xx;
-        struct cvmx_sli_int_sum_cn68xx cn68xxp1;
-        struct cvmx_sli_int_sum_cn61xx cnf71xx;
-};
-
-union cvmx_sli_last_win_rdata0 {
-        uint64_t u64;
-        struct cvmx_sli_last_win_rdata0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } s;
-        struct cvmx_sli_last_win_rdata0_s cn61xx;
-        struct cvmx_sli_last_win_rdata0_s cn63xx;
-        struct cvmx_sli_last_win_rdata0_s cn63xxp1;
-        struct cvmx_sli_last_win_rdata0_s cn66xx;
-        struct cvmx_sli_last_win_rdata0_s cn68xx;
-        struct cvmx_sli_last_win_rdata0_s cn68xxp1;
-        struct cvmx_sli_last_win_rdata0_s cnf71xx;
-};
-
-union cvmx_sli_last_win_rdata1 {
-        uint64_t u64;
-        struct cvmx_sli_last_win_rdata1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } s;
-        struct cvmx_sli_last_win_rdata1_s cn61xx;
-        struct cvmx_sli_last_win_rdata1_s cn63xx;
-        struct cvmx_sli_last_win_rdata1_s cn63xxp1;
-        struct cvmx_sli_last_win_rdata1_s cn66xx;
-        struct cvmx_sli_last_win_rdata1_s cn68xx;
-        struct cvmx_sli_last_win_rdata1_s cn68xxp1;
-        struct cvmx_sli_last_win_rdata1_s cnf71xx;
-};
-
-union cvmx_sli_last_win_rdata2 {
-        uint64_t u64;
-        struct cvmx_sli_last_win_rdata2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } s;
-        struct cvmx_sli_last_win_rdata2_s cn61xx;
-        struct cvmx_sli_last_win_rdata2_s cn66xx;
-        struct cvmx_sli_last_win_rdata2_s cnf71xx;
-};
-
-union cvmx_sli_last_win_rdata3 {
-        uint64_t u64;
-        struct cvmx_sli_last_win_rdata3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } s;
-        struct cvmx_sli_last_win_rdata3_s cn61xx;
-        struct cvmx_sli_last_win_rdata3_s cn66xx;
-        struct cvmx_sli_last_win_rdata3_s cnf71xx;
-};
-
-union cvmx_sli_mac_credit_cnt {
-        uint64_t u64;
-        struct cvmx_sli_mac_credit_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t p1_c_d:1;
-                uint64_t p1_n_d:1;
-                uint64_t p1_p_d:1;
-                uint64_t p0_c_d:1;
-                uint64_t p0_n_d:1;
-                uint64_t p0_p_d:1;
-                uint64_t p1_ccnt:8;
-                uint64_t p1_ncnt:8;
-                uint64_t p1_pcnt:8;
-                uint64_t p0_ccnt:8;
-                uint64_t p0_ncnt:8;
-                uint64_t p0_pcnt:8;
-#else
-                uint64_t p0_pcnt:8;
-                uint64_t p0_ncnt:8;
-                uint64_t p0_ccnt:8;
-                uint64_t p1_pcnt:8;
-                uint64_t p1_ncnt:8;
-                uint64_t p1_ccnt:8;
-                uint64_t p0_p_d:1;
-                uint64_t p0_n_d:1;
-                uint64_t p0_c_d:1;
-                uint64_t p1_p_d:1;
-                uint64_t p1_n_d:1;
-                uint64_t p1_c_d:1;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_sli_mac_credit_cnt_s cn61xx;
-        struct cvmx_sli_mac_credit_cnt_s cn63xx;
-        struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t p1_ccnt:8;
-                uint64_t p1_ncnt:8;
-                uint64_t p1_pcnt:8;
-                uint64_t p0_ccnt:8;
-                uint64_t p0_ncnt:8;
-                uint64_t p0_pcnt:8;
-#else
-                uint64_t p0_pcnt:8;
-                uint64_t p0_ncnt:8;
-                uint64_t p0_ccnt:8;
-                uint64_t p1_pcnt:8;
-                uint64_t p1_ncnt:8;
-                uint64_t p1_ccnt:8;
-                uint64_t reserved_48_63:16;
-#endif
-        } cn63xxp1;
-        struct cvmx_sli_mac_credit_cnt_s cn66xx;
-        struct cvmx_sli_mac_credit_cnt_s cn68xx;
-        struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
-        struct cvmx_sli_mac_credit_cnt_s cnf71xx;
-};
-
-union cvmx_sli_mac_credit_cnt2 {
-        uint64_t u64;
-        struct cvmx_sli_mac_credit_cnt2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t p3_c_d:1;
-                uint64_t p3_n_d:1;
-                uint64_t p3_p_d:1;
-                uint64_t p2_c_d:1;
-                uint64_t p2_n_d:1;
-                uint64_t p2_p_d:1;
-                uint64_t p3_ccnt:8;
-                uint64_t p3_ncnt:8;
-                uint64_t p3_pcnt:8;
-                uint64_t p2_ccnt:8;
-                uint64_t p2_ncnt:8;
-                uint64_t p2_pcnt:8;
-#else
-                uint64_t p2_pcnt:8;
-                uint64_t p2_ncnt:8;
-                uint64_t p2_ccnt:8;
-                uint64_t p3_pcnt:8;
-                uint64_t p3_ncnt:8;
-                uint64_t p3_ccnt:8;
-                uint64_t p2_p_d:1;
-                uint64_t p2_n_d:1;
-                uint64_t p2_c_d:1;
-                uint64_t p3_p_d:1;
-                uint64_t p3_n_d:1;
-                uint64_t p3_c_d:1;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_sli_mac_credit_cnt2_s cn61xx;
-        struct cvmx_sli_mac_credit_cnt2_s cn66xx;
-        struct cvmx_sli_mac_credit_cnt2_s cnf71xx;
-};
-
-union cvmx_sli_mac_number {
-        uint64_t u64;
-        struct cvmx_sli_mac_number_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t a_mode:1;
-                uint64_t num:8;
-#else
-                uint64_t num:8;
-                uint64_t a_mode:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_sli_mac_number_s cn61xx;
-        struct cvmx_sli_mac_number_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t num:8;
-#else
-                uint64_t num:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } cn63xx;
-        struct cvmx_sli_mac_number_s cn66xx;
-        struct cvmx_sli_mac_number_cn63xx cn68xx;
-        struct cvmx_sli_mac_number_cn63xx cn68xxp1;
-        struct cvmx_sli_mac_number_s cnf71xx;
-};
-
-union cvmx_sli_mem_access_ctl {
-        uint64_t u64;
-        struct cvmx_sli_mem_access_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t max_word:4;
-                uint64_t timer:10;
-#else
-                uint64_t timer:10;
-                uint64_t max_word:4;
-                uint64_t reserved_14_63:50;
-#endif
-        } s;
-        struct cvmx_sli_mem_access_ctl_s cn61xx;
-        struct cvmx_sli_mem_access_ctl_s cn63xx;
-        struct cvmx_sli_mem_access_ctl_s cn63xxp1;
-        struct cvmx_sli_mem_access_ctl_s cn66xx;
-        struct cvmx_sli_mem_access_ctl_s cn68xx;
-        struct cvmx_sli_mem_access_ctl_s cn68xxp1;
-        struct cvmx_sli_mem_access_ctl_s cnf71xx;
-};
-
-union cvmx_sli_mem_access_subidx {
-        uint64_t u64;
-        struct cvmx_sli_mem_access_subidx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_43_63:21;
-                uint64_t zero:1;
-                uint64_t port:3;
-                uint64_t nmerge:1;
-                uint64_t esr:2;
-                uint64_t esw:2;
-                uint64_t wtype:2;
-                uint64_t rtype:2;
-                uint64_t reserved_0_29:30;
-#else
-                uint64_t reserved_0_29:30;
-                uint64_t rtype:2;
-                uint64_t wtype:2;
-                uint64_t esw:2;
-                uint64_t esr:2;
-                uint64_t nmerge:1;
-                uint64_t port:3;
-                uint64_t zero:1;
-                uint64_t reserved_43_63:21;
-#endif
-        } s;
-        struct cvmx_sli_mem_access_subidx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_43_63:21;
-                uint64_t zero:1;
-                uint64_t port:3;
-                uint64_t nmerge:1;
-                uint64_t esr:2;
-                uint64_t esw:2;
-                uint64_t wtype:2;
-                uint64_t rtype:2;
-                uint64_t ba:30;
-#else
-                uint64_t ba:30;
-                uint64_t rtype:2;
-                uint64_t wtype:2;
-                uint64_t esw:2;
-                uint64_t esr:2;
-                uint64_t nmerge:1;
-                uint64_t port:3;
-                uint64_t zero:1;
-                uint64_t reserved_43_63:21;
-#endif
-        } cn61xx;
-        struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
-        struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
-        struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
-        struct cvmx_sli_mem_access_subidx_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_43_63:21;
-                uint64_t zero:1;
-                uint64_t port:3;
-                uint64_t nmerge:1;
-                uint64_t esr:2;
-                uint64_t esw:2;
-                uint64_t wtype:2;
-                uint64_t rtype:2;
-                uint64_t ba:28;
-                uint64_t reserved_0_1:2;
-#else
-                uint64_t reserved_0_1:2;
-                uint64_t ba:28;
-                uint64_t rtype:2;
-                uint64_t wtype:2;
-                uint64_t esw:2;
-                uint64_t esr:2;
-                uint64_t nmerge:1;
-                uint64_t port:3;
-                uint64_t zero:1;
-                uint64_t reserved_43_63:21;
-#endif
-        } cn68xx;
-        struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
-        struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx;
-};
-
-union cvmx_sli_msi_enb0 {
-        uint64_t u64;
-        struct cvmx_sli_msi_enb0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t enb:64;
-#else
-                uint64_t enb:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_enb0_s cn61xx;
-        struct cvmx_sli_msi_enb0_s cn63xx;
-        struct cvmx_sli_msi_enb0_s cn63xxp1;
-        struct cvmx_sli_msi_enb0_s cn66xx;
-        struct cvmx_sli_msi_enb0_s cn68xx;
-        struct cvmx_sli_msi_enb0_s cn68xxp1;
-        struct cvmx_sli_msi_enb0_s cnf71xx;
-};
-
-union cvmx_sli_msi_enb1 {
-        uint64_t u64;
-        struct cvmx_sli_msi_enb1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t enb:64;
-#else
-                uint64_t enb:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_enb1_s cn61xx;
-        struct cvmx_sli_msi_enb1_s cn63xx;
-        struct cvmx_sli_msi_enb1_s cn63xxp1;
-        struct cvmx_sli_msi_enb1_s cn66xx;
-        struct cvmx_sli_msi_enb1_s cn68xx;
-        struct cvmx_sli_msi_enb1_s cn68xxp1;
-        struct cvmx_sli_msi_enb1_s cnf71xx;
-};
-
-union cvmx_sli_msi_enb2 {
-        uint64_t u64;
-        struct cvmx_sli_msi_enb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t enb:64;
-#else
-                uint64_t enb:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_enb2_s cn61xx;
-        struct cvmx_sli_msi_enb2_s cn63xx;
-        struct cvmx_sli_msi_enb2_s cn63xxp1;
-        struct cvmx_sli_msi_enb2_s cn66xx;
-        struct cvmx_sli_msi_enb2_s cn68xx;
-        struct cvmx_sli_msi_enb2_s cn68xxp1;
-        struct cvmx_sli_msi_enb2_s cnf71xx;
-};
-
-union cvmx_sli_msi_enb3 {
-        uint64_t u64;
-        struct cvmx_sli_msi_enb3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t enb:64;
-#else
-                uint64_t enb:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_enb3_s cn61xx;
-        struct cvmx_sli_msi_enb3_s cn63xx;
-        struct cvmx_sli_msi_enb3_s cn63xxp1;
-        struct cvmx_sli_msi_enb3_s cn66xx;
-        struct cvmx_sli_msi_enb3_s cn68xx;
-        struct cvmx_sli_msi_enb3_s cn68xxp1;
-        struct cvmx_sli_msi_enb3_s cnf71xx;
-};
-
-union cvmx_sli_msi_rcv0 {
-        uint64_t u64;
-        struct cvmx_sli_msi_rcv0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t intr:64;
-#else
-                uint64_t intr:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_rcv0_s cn61xx;
-        struct cvmx_sli_msi_rcv0_s cn63xx;
-        struct cvmx_sli_msi_rcv0_s cn63xxp1;
-        struct cvmx_sli_msi_rcv0_s cn66xx;
-        struct cvmx_sli_msi_rcv0_s cn68xx;
-        struct cvmx_sli_msi_rcv0_s cn68xxp1;
-        struct cvmx_sli_msi_rcv0_s cnf71xx;
-};
-
-union cvmx_sli_msi_rcv1 {
-        uint64_t u64;
-        struct cvmx_sli_msi_rcv1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t intr:64;
-#else
-                uint64_t intr:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_rcv1_s cn61xx;
-        struct cvmx_sli_msi_rcv1_s cn63xx;
-        struct cvmx_sli_msi_rcv1_s cn63xxp1;
-        struct cvmx_sli_msi_rcv1_s cn66xx;
-        struct cvmx_sli_msi_rcv1_s cn68xx;
-        struct cvmx_sli_msi_rcv1_s cn68xxp1;
-        struct cvmx_sli_msi_rcv1_s cnf71xx;
-};
-
-union cvmx_sli_msi_rcv2 {
-        uint64_t u64;
-        struct cvmx_sli_msi_rcv2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t intr:64;
-#else
-                uint64_t intr:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_rcv2_s cn61xx;
-        struct cvmx_sli_msi_rcv2_s cn63xx;
-        struct cvmx_sli_msi_rcv2_s cn63xxp1;
-        struct cvmx_sli_msi_rcv2_s cn66xx;
-        struct cvmx_sli_msi_rcv2_s cn68xx;
-        struct cvmx_sli_msi_rcv2_s cn68xxp1;
-        struct cvmx_sli_msi_rcv2_s cnf71xx;
-};
-
-union cvmx_sli_msi_rcv3 {
-        uint64_t u64;
-        struct cvmx_sli_msi_rcv3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t intr:64;
-#else
-                uint64_t intr:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_rcv3_s cn61xx;
-        struct cvmx_sli_msi_rcv3_s cn63xx;
-        struct cvmx_sli_msi_rcv3_s cn63xxp1;
-        struct cvmx_sli_msi_rcv3_s cn66xx;
-        struct cvmx_sli_msi_rcv3_s cn68xx;
-        struct cvmx_sli_msi_rcv3_s cn68xxp1;
-        struct cvmx_sli_msi_rcv3_s cnf71xx;
-};
-
-union cvmx_sli_msi_rd_map {
-        uint64_t u64;
-        struct cvmx_sli_msi_rd_map_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t rd_int:8;
-                uint64_t msi_int:8;
-#else
-                uint64_t msi_int:8;
-                uint64_t rd_int:8;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_sli_msi_rd_map_s cn61xx;
-        struct cvmx_sli_msi_rd_map_s cn63xx;
-        struct cvmx_sli_msi_rd_map_s cn63xxp1;
-        struct cvmx_sli_msi_rd_map_s cn66xx;
-        struct cvmx_sli_msi_rd_map_s cn68xx;
-        struct cvmx_sli_msi_rd_map_s cn68xxp1;
-        struct cvmx_sli_msi_rd_map_s cnf71xx;
-};
-
-union cvmx_sli_msi_w1c_enb0 {
-        uint64_t u64;
-        struct cvmx_sli_msi_w1c_enb0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t clr:64;
-#else
-                uint64_t clr:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_w1c_enb0_s cn61xx;
-        struct cvmx_sli_msi_w1c_enb0_s cn63xx;
-        struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
-        struct cvmx_sli_msi_w1c_enb0_s cn66xx;
-        struct cvmx_sli_msi_w1c_enb0_s cn68xx;
-        struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
-        struct cvmx_sli_msi_w1c_enb0_s cnf71xx;
-};
-
-union cvmx_sli_msi_w1c_enb1 {
-        uint64_t u64;
-        struct cvmx_sli_msi_w1c_enb1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t clr:64;
-#else
-                uint64_t clr:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_w1c_enb1_s cn61xx;
-        struct cvmx_sli_msi_w1c_enb1_s cn63xx;
-        struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
-        struct cvmx_sli_msi_w1c_enb1_s cn66xx;
-        struct cvmx_sli_msi_w1c_enb1_s cn68xx;
-        struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
-        struct cvmx_sli_msi_w1c_enb1_s cnf71xx;
-};
-
-union cvmx_sli_msi_w1c_enb2 {
-        uint64_t u64;
-        struct cvmx_sli_msi_w1c_enb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t clr:64;
-#else
-                uint64_t clr:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_w1c_enb2_s cn61xx;
-        struct cvmx_sli_msi_w1c_enb2_s cn63xx;
-        struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
-        struct cvmx_sli_msi_w1c_enb2_s cn66xx;
-        struct cvmx_sli_msi_w1c_enb2_s cn68xx;
-        struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
-        struct cvmx_sli_msi_w1c_enb2_s cnf71xx;
-};
-
-union cvmx_sli_msi_w1c_enb3 {
-        uint64_t u64;
-        struct cvmx_sli_msi_w1c_enb3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t clr:64;
-#else
-                uint64_t clr:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_w1c_enb3_s cn61xx;
-        struct cvmx_sli_msi_w1c_enb3_s cn63xx;
-        struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
-        struct cvmx_sli_msi_w1c_enb3_s cn66xx;
-        struct cvmx_sli_msi_w1c_enb3_s cn68xx;
-        struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
-        struct cvmx_sli_msi_w1c_enb3_s cnf71xx;
-};
-
-union cvmx_sli_msi_w1s_enb0 {
-        uint64_t u64;
-        struct cvmx_sli_msi_w1s_enb0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t set:64;
-#else
-                uint64_t set:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_w1s_enb0_s cn61xx;
-        struct cvmx_sli_msi_w1s_enb0_s cn63xx;
-        struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
-        struct cvmx_sli_msi_w1s_enb0_s cn66xx;
-        struct cvmx_sli_msi_w1s_enb0_s cn68xx;
-        struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
-        struct cvmx_sli_msi_w1s_enb0_s cnf71xx;
-};
-
-union cvmx_sli_msi_w1s_enb1 {
-        uint64_t u64;
-        struct cvmx_sli_msi_w1s_enb1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t set:64;
-#else
-                uint64_t set:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_w1s_enb1_s cn61xx;
-        struct cvmx_sli_msi_w1s_enb1_s cn63xx;
-        struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
-        struct cvmx_sli_msi_w1s_enb1_s cn66xx;
-        struct cvmx_sli_msi_w1s_enb1_s cn68xx;
-        struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
-        struct cvmx_sli_msi_w1s_enb1_s cnf71xx;
-};
-
-union cvmx_sli_msi_w1s_enb2 {
-        uint64_t u64;
-        struct cvmx_sli_msi_w1s_enb2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t set:64;
-#else
-                uint64_t set:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_w1s_enb2_s cn61xx;
-        struct cvmx_sli_msi_w1s_enb2_s cn63xx;
-        struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
-        struct cvmx_sli_msi_w1s_enb2_s cn66xx;
-        struct cvmx_sli_msi_w1s_enb2_s cn68xx;
-        struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
-        struct cvmx_sli_msi_w1s_enb2_s cnf71xx;
-};
-
-union cvmx_sli_msi_w1s_enb3 {
-        uint64_t u64;
-        struct cvmx_sli_msi_w1s_enb3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t set:64;
-#else
-                uint64_t set:64;
-#endif
-        } s;
-        struct cvmx_sli_msi_w1s_enb3_s cn61xx;
-        struct cvmx_sli_msi_w1s_enb3_s cn63xx;
-        struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
-        struct cvmx_sli_msi_w1s_enb3_s cn66xx;
-        struct cvmx_sli_msi_w1s_enb3_s cn68xx;
-        struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
-        struct cvmx_sli_msi_w1s_enb3_s cnf71xx;
-};
-
-union cvmx_sli_msi_wr_map {
-        uint64_t u64;
-        struct cvmx_sli_msi_wr_map_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t ciu_int:8;
-                uint64_t msi_int:8;
-#else
-                uint64_t msi_int:8;
-                uint64_t ciu_int:8;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_sli_msi_wr_map_s cn61xx;
-        struct cvmx_sli_msi_wr_map_s cn63xx;
-        struct cvmx_sli_msi_wr_map_s cn63xxp1;
-        struct cvmx_sli_msi_wr_map_s cn66xx;
-        struct cvmx_sli_msi_wr_map_s cn68xx;
-        struct cvmx_sli_msi_wr_map_s cn68xxp1;
-        struct cvmx_sli_msi_wr_map_s cnf71xx;
-};
-
-union cvmx_sli_pcie_msi_rcv {
-        uint64_t u64;
-        struct cvmx_sli_pcie_msi_rcv_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t intr:8;
-#else
-                uint64_t intr:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_sli_pcie_msi_rcv_s cn61xx;
-        struct cvmx_sli_pcie_msi_rcv_s cn63xx;
-        struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
-        struct cvmx_sli_pcie_msi_rcv_s cn66xx;
-        struct cvmx_sli_pcie_msi_rcv_s cn68xx;
-        struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
-        struct cvmx_sli_pcie_msi_rcv_s cnf71xx;
-};
-
-union cvmx_sli_pcie_msi_rcv_b1 {
-        uint64_t u64;
-        struct cvmx_sli_pcie_msi_rcv_b1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t intr:8;
-                uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t intr:8;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
-        struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
-        struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
-        struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
-        struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
-        struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
-        struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx;
-};
-
-union cvmx_sli_pcie_msi_rcv_b2 {
-        uint64_t u64;
-        struct cvmx_sli_pcie_msi_rcv_b2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t intr:8;
-                uint64_t reserved_0_15:16;
-#else
-                uint64_t reserved_0_15:16;
-                uint64_t intr:8;
-                uint64_t reserved_24_63:40;
-#endif
-        } s;
-        struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
-        struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
-        struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
-        struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
-        struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
-        struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
-        struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx;
-};
-
-union cvmx_sli_pcie_msi_rcv_b3 {
-        uint64_t u64;
-        struct cvmx_sli_pcie_msi_rcv_b3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t intr:8;
-                uint64_t reserved_0_23:24;
-#else
-                uint64_t reserved_0_23:24;
-                uint64_t intr:8;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
-        struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
-        struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
-        struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
-        struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
-        struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
-        struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx;
-};
-
-union cvmx_sli_pktx_cnts {
-        uint64_t u64;
-        struct cvmx_sli_pktx_cnts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t timer:22;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t timer:22;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_sli_pktx_cnts_s cn61xx;
-        struct cvmx_sli_pktx_cnts_s cn63xx;
-        struct cvmx_sli_pktx_cnts_s cn63xxp1;
-        struct cvmx_sli_pktx_cnts_s cn66xx;
-        struct cvmx_sli_pktx_cnts_s cn68xx;
-        struct cvmx_sli_pktx_cnts_s cn68xxp1;
-        struct cvmx_sli_pktx_cnts_s cnf71xx;
-};
-
-union cvmx_sli_pktx_in_bp {
-        uint64_t u64;
-        struct cvmx_sli_pktx_in_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t wmark:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t wmark:32;
-#endif
-        } s;
-        struct cvmx_sli_pktx_in_bp_s cn61xx;
-        struct cvmx_sli_pktx_in_bp_s cn63xx;
-        struct cvmx_sli_pktx_in_bp_s cn63xxp1;
-        struct cvmx_sli_pktx_in_bp_s cn66xx;
-        struct cvmx_sli_pktx_in_bp_s cnf71xx;
-};
-
-union cvmx_sli_pktx_instr_baddr {
-        uint64_t u64;
-        struct cvmx_sli_pktx_instr_baddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t addr:61;
-                uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t addr:61;
-#endif
-        } s;
-        struct cvmx_sli_pktx_instr_baddr_s cn61xx;
-        struct cvmx_sli_pktx_instr_baddr_s cn63xx;
-        struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
-        struct cvmx_sli_pktx_instr_baddr_s cn66xx;
-        struct cvmx_sli_pktx_instr_baddr_s cn68xx;
-        struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
-        struct cvmx_sli_pktx_instr_baddr_s cnf71xx;
-};
-
-union cvmx_sli_pktx_instr_baoff_dbell {
-        uint64_t u64;
-        struct cvmx_sli_pktx_instr_baoff_dbell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t aoff:32;
-                uint64_t dbell:32;
-#else
-                uint64_t dbell:32;
-                uint64_t aoff:32;
-#endif
-        } s;
-        struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
-        struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
-        struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
-        struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
-        struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
-        struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
-        struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx;
-};
-
-union cvmx_sli_pktx_instr_fifo_rsize {
-        uint64_t u64;
-        struct cvmx_sli_pktx_instr_fifo_rsize_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t max:9;
-                uint64_t rrp:9;
-                uint64_t wrp:9;
-                uint64_t fcnt:5;
-                uint64_t rsize:32;
-#else
-                uint64_t rsize:32;
-                uint64_t fcnt:5;
-                uint64_t wrp:9;
-                uint64_t rrp:9;
-                uint64_t max:9;
-#endif
-        } s;
-        struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
-        struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
-        struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
-        struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
-        struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
-        struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
-        struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx;
-};
-
-union cvmx_sli_pktx_instr_header {
-        uint64_t u64;
-        struct cvmx_sli_pktx_instr_header_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t pbp:1;
-                uint64_t reserved_38_42:5;
-                uint64_t rparmode:2;
-                uint64_t reserved_35_35:1;
-                uint64_t rskp_len:7;
-                uint64_t rngrpext:2;
-                uint64_t rnqos:1;
-                uint64_t rngrp:1;
-                uint64_t rntt:1;
-                uint64_t rntag:1;
-                uint64_t use_ihdr:1;
-                uint64_t reserved_16_20:5;
-                uint64_t par_mode:2;
-                uint64_t reserved_13_13:1;
-                uint64_t skp_len:7;
-                uint64_t ngrpext:2;
-                uint64_t nqos:1;
-                uint64_t ngrp:1;
-                uint64_t ntt:1;
-                uint64_t ntag:1;
-#else
-                uint64_t ntag:1;
-                uint64_t ntt:1;
-                uint64_t ngrp:1;
-                uint64_t nqos:1;
-                uint64_t ngrpext:2;
-                uint64_t skp_len:7;
-                uint64_t reserved_13_13:1;
-                uint64_t par_mode:2;
-                uint64_t reserved_16_20:5;
-                uint64_t use_ihdr:1;
-                uint64_t rntag:1;
-                uint64_t rntt:1;
-                uint64_t rngrp:1;
-                uint64_t rnqos:1;
-                uint64_t rngrpext:2;
-                uint64_t rskp_len:7;
-                uint64_t reserved_35_35:1;
-                uint64_t rparmode:2;
-                uint64_t reserved_38_42:5;
-                uint64_t pbp:1;
-                uint64_t reserved_44_63:20;
-#endif
-        } s;
-        struct cvmx_sli_pktx_instr_header_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t pbp:1;
-                uint64_t reserved_38_42:5;
-                uint64_t rparmode:2;
-                uint64_t reserved_35_35:1;
-                uint64_t rskp_len:7;
-                uint64_t reserved_26_27:2;
-                uint64_t rnqos:1;
-                uint64_t rngrp:1;
-                uint64_t rntt:1;
-                uint64_t rntag:1;
-                uint64_t use_ihdr:1;
-                uint64_t reserved_16_20:5;
-                uint64_t par_mode:2;
-                uint64_t reserved_13_13:1;
-                uint64_t skp_len:7;
-                uint64_t reserved_4_5:2;
-                uint64_t nqos:1;
-                uint64_t ngrp:1;
-                uint64_t ntt:1;
-                uint64_t ntag:1;
-#else
-                uint64_t ntag:1;
-                uint64_t ntt:1;
-                uint64_t ngrp:1;
-                uint64_t nqos:1;
-                uint64_t reserved_4_5:2;
-                uint64_t skp_len:7;
-                uint64_t reserved_13_13:1;
-                uint64_t par_mode:2;
-                uint64_t reserved_16_20:5;
-                uint64_t use_ihdr:1;
-                uint64_t rntag:1;
-                uint64_t rntt:1;
-                uint64_t rngrp:1;
-                uint64_t rnqos:1;
-                uint64_t reserved_26_27:2;
-                uint64_t rskp_len:7;
-                uint64_t reserved_35_35:1;
-                uint64_t rparmode:2;
-                uint64_t reserved_38_42:5;
-                uint64_t pbp:1;
-                uint64_t reserved_44_63:20;
-#endif
-        } cn61xx;
-        struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
-        struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
-        struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
-        struct cvmx_sli_pktx_instr_header_s cn68xx;
-        struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
-        struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx;
-};
-
-union cvmx_sli_pktx_out_size {
-        uint64_t u64;
-        struct cvmx_sli_pktx_out_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t isize:7;
-                uint64_t bsize:16;
-#else
-                uint64_t bsize:16;
-                uint64_t isize:7;
-                uint64_t reserved_23_63:41;
-#endif
-        } s;
-        struct cvmx_sli_pktx_out_size_s cn61xx;
-        struct cvmx_sli_pktx_out_size_s cn63xx;
-        struct cvmx_sli_pktx_out_size_s cn63xxp1;
-        struct cvmx_sli_pktx_out_size_s cn66xx;
-        struct cvmx_sli_pktx_out_size_s cn68xx;
-        struct cvmx_sli_pktx_out_size_s cn68xxp1;
-        struct cvmx_sli_pktx_out_size_s cnf71xx;
-};
-
-union cvmx_sli_pktx_slist_baddr {
-        uint64_t u64;
-        struct cvmx_sli_pktx_slist_baddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t addr:60;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t addr:60;
-#endif
-        } s;
-        struct cvmx_sli_pktx_slist_baddr_s cn61xx;
-        struct cvmx_sli_pktx_slist_baddr_s cn63xx;
-        struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
-        struct cvmx_sli_pktx_slist_baddr_s cn66xx;
-        struct cvmx_sli_pktx_slist_baddr_s cn68xx;
-        struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
-        struct cvmx_sli_pktx_slist_baddr_s cnf71xx;
-};
-
-union cvmx_sli_pktx_slist_baoff_dbell {
-        uint64_t u64;
-        struct cvmx_sli_pktx_slist_baoff_dbell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t aoff:32;
-                uint64_t dbell:32;
-#else
-                uint64_t dbell:32;
-                uint64_t aoff:32;
-#endif
-        } s;
-        struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
-        struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
-        struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
-        struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
-        struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
-        struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
-        struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx;
-};
-
-union cvmx_sli_pktx_slist_fifo_rsize {
-        uint64_t u64;
-        struct cvmx_sli_pktx_slist_fifo_rsize_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t rsize:32;
-#else
-                uint64_t rsize:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
-        struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
-        struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
-        struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
-        struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
-        struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
-        struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx;
-};
-
-union cvmx_sli_pkt_cnt_int {
-        uint64_t u64;
-        struct cvmx_sli_pkt_cnt_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t port:32;
-#else
-                uint64_t port:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_cnt_int_s cn61xx;
-        struct cvmx_sli_pkt_cnt_int_s cn63xx;
-        struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
-        struct cvmx_sli_pkt_cnt_int_s cn66xx;
-        struct cvmx_sli_pkt_cnt_int_s cn68xx;
-        struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
-        struct cvmx_sli_pkt_cnt_int_s cnf71xx;
-};
-
-union cvmx_sli_pkt_cnt_int_enb {
-        uint64_t u64;
-        struct cvmx_sli_pkt_cnt_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t port:32;
-#else
-                uint64_t port:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
-        struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
-        struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
-        struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
-        struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
-        struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
-        struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx;
-};
-
-union cvmx_sli_pkt_ctl {
-        uint64_t u64;
-        struct cvmx_sli_pkt_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t ring_en:1;
-                uint64_t pkt_bp:4;
-#else
-                uint64_t pkt_bp:4;
-                uint64_t ring_en:1;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_sli_pkt_ctl_s cn61xx;
-        struct cvmx_sli_pkt_ctl_s cn63xx;
-        struct cvmx_sli_pkt_ctl_s cn63xxp1;
-        struct cvmx_sli_pkt_ctl_s cn66xx;
-        struct cvmx_sli_pkt_ctl_s cn68xx;
-        struct cvmx_sli_pkt_ctl_s cn68xxp1;
-        struct cvmx_sli_pkt_ctl_s cnf71xx;
-};
-
-union cvmx_sli_pkt_data_out_es {
-        uint64_t u64;
-        struct cvmx_sli_pkt_data_out_es_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t es:64;
-#else
-                uint64_t es:64;
-#endif
-        } s;
-        struct cvmx_sli_pkt_data_out_es_s cn61xx;
-        struct cvmx_sli_pkt_data_out_es_s cn63xx;
-        struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
-        struct cvmx_sli_pkt_data_out_es_s cn66xx;
-        struct cvmx_sli_pkt_data_out_es_s cn68xx;
-        struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
-        struct cvmx_sli_pkt_data_out_es_s cnf71xx;
-};
-
-union cvmx_sli_pkt_data_out_ns {
-        uint64_t u64;
-        struct cvmx_sli_pkt_data_out_ns_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t nsr:32;
-#else
-                uint64_t nsr:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_data_out_ns_s cn61xx;
-        struct cvmx_sli_pkt_data_out_ns_s cn63xx;
-        struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
-        struct cvmx_sli_pkt_data_out_ns_s cn66xx;
-        struct cvmx_sli_pkt_data_out_ns_s cn68xx;
-        struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
-        struct cvmx_sli_pkt_data_out_ns_s cnf71xx;
-};
-
-union cvmx_sli_pkt_data_out_ror {
-        uint64_t u64;
-        struct cvmx_sli_pkt_data_out_ror_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ror:32;
-#else
-                uint64_t ror:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_data_out_ror_s cn61xx;
-        struct cvmx_sli_pkt_data_out_ror_s cn63xx;
-        struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
-        struct cvmx_sli_pkt_data_out_ror_s cn66xx;
-        struct cvmx_sli_pkt_data_out_ror_s cn68xx;
-        struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
-        struct cvmx_sli_pkt_data_out_ror_s cnf71xx;
-};
-
-union cvmx_sli_pkt_dpaddr {
-        uint64_t u64;
-        struct cvmx_sli_pkt_dpaddr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t dptr:32;
-#else
-                uint64_t dptr:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_dpaddr_s cn61xx;
-        struct cvmx_sli_pkt_dpaddr_s cn63xx;
-        struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
-        struct cvmx_sli_pkt_dpaddr_s cn66xx;
-        struct cvmx_sli_pkt_dpaddr_s cn68xx;
-        struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
-        struct cvmx_sli_pkt_dpaddr_s cnf71xx;
-};
-
-union cvmx_sli_pkt_in_bp {
-        uint64_t u64;
-        struct cvmx_sli_pkt_in_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t bp:32;
-#else
-                uint64_t bp:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_in_bp_s cn61xx;
-        struct cvmx_sli_pkt_in_bp_s cn63xx;
-        struct cvmx_sli_pkt_in_bp_s cn63xxp1;
-        struct cvmx_sli_pkt_in_bp_s cn66xx;
-        struct cvmx_sli_pkt_in_bp_s cnf71xx;
-};
-
-union cvmx_sli_pkt_in_donex_cnts {
-        uint64_t u64;
-        struct cvmx_sli_pkt_in_donex_cnts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
-        struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
-        struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
-        struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
-        struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
-        struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
-        struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx;
-};
-
-union cvmx_sli_pkt_in_instr_counts {
-        uint64_t u64;
-        struct cvmx_sli_pkt_in_instr_counts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t wr_cnt:32;
-                uint64_t rd_cnt:32;
-#else
-                uint64_t rd_cnt:32;
-                uint64_t wr_cnt:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
-        struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
-        struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
-        struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
-        struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
-        struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
-        struct cvmx_sli_pkt_in_instr_counts_s cnf71xx;
-};
-
-union cvmx_sli_pkt_in_pcie_port {
-        uint64_t u64;
-        struct cvmx_sli_pkt_in_pcie_port_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t pp:64;
-#else
-                uint64_t pp:64;
-#endif
-        } s;
-        struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
-        struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
-        struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
-        struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
-        struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
-        struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
-        struct cvmx_sli_pkt_in_pcie_port_s cnf71xx;
-};
-
-union cvmx_sli_pkt_input_control {
-        uint64_t u64;
-        struct cvmx_sli_pkt_input_control_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t prd_erst:1;
-                uint64_t prd_rds:7;
-                uint64_t gii_erst:1;
-                uint64_t gii_rds:7;
-                uint64_t reserved_41_47:7;
-                uint64_t prc_idle:1;
-                uint64_t reserved_24_39:16;
-                uint64_t pin_rst:1;
-                uint64_t pkt_rr:1;
-                uint64_t pbp_dhi:13;
-                uint64_t d_nsr:1;
-                uint64_t d_esr:2;
-                uint64_t d_ror:1;
-                uint64_t use_csr:1;
-                uint64_t nsr:1;
-                uint64_t esr:2;
-                uint64_t ror:1;
-#else
-                uint64_t ror:1;
-                uint64_t esr:2;
-                uint64_t nsr:1;
-                uint64_t use_csr:1;
-                uint64_t d_ror:1;
-                uint64_t d_esr:2;
-                uint64_t d_nsr:1;
-                uint64_t pbp_dhi:13;
-                uint64_t pkt_rr:1;
-                uint64_t pin_rst:1;
-                uint64_t reserved_24_39:16;
-                uint64_t prc_idle:1;
-                uint64_t reserved_41_47:7;
-                uint64_t gii_rds:7;
-                uint64_t gii_erst:1;
-                uint64_t prd_rds:7;
-                uint64_t prd_erst:1;
-#endif
-        } s;
-        struct cvmx_sli_pkt_input_control_s cn61xx;
-        struct cvmx_sli_pkt_input_control_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_23_63:41;
-                uint64_t pkt_rr:1;
-                uint64_t pbp_dhi:13;
-                uint64_t d_nsr:1;
-                uint64_t d_esr:2;
-                uint64_t d_ror:1;
-                uint64_t use_csr:1;
-                uint64_t nsr:1;
-                uint64_t esr:2;
-                uint64_t ror:1;
-#else
-                uint64_t ror:1;
-                uint64_t esr:2;
-                uint64_t nsr:1;
-                uint64_t use_csr:1;
-                uint64_t d_ror:1;
-                uint64_t d_esr:2;
-                uint64_t d_nsr:1;
-                uint64_t pbp_dhi:13;
-                uint64_t pkt_rr:1;
-                uint64_t reserved_23_63:41;
-#endif
-        } cn63xx;
-        struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
-        struct cvmx_sli_pkt_input_control_s cn66xx;
-        struct cvmx_sli_pkt_input_control_s cn68xx;
-        struct cvmx_sli_pkt_input_control_s cn68xxp1;
-        struct cvmx_sli_pkt_input_control_s cnf71xx;
-};
-
-union cvmx_sli_pkt_instr_enb {
-        uint64_t u64;
-        struct cvmx_sli_pkt_instr_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t enb:32;
-#else
-                uint64_t enb:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_instr_enb_s cn61xx;
-        struct cvmx_sli_pkt_instr_enb_s cn63xx;
-        struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
-        struct cvmx_sli_pkt_instr_enb_s cn66xx;
-        struct cvmx_sli_pkt_instr_enb_s cn68xx;
-        struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
-        struct cvmx_sli_pkt_instr_enb_s cnf71xx;
-};
-
-union cvmx_sli_pkt_instr_rd_size {
-        uint64_t u64;
-        struct cvmx_sli_pkt_instr_rd_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rdsize:64;
-#else
-                uint64_t rdsize:64;
-#endif
-        } s;
-        struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
-        struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
-        struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
-        struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
-        struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
-        struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
-        struct cvmx_sli_pkt_instr_rd_size_s cnf71xx;
-};
-
-union cvmx_sli_pkt_instr_size {
-        uint64_t u64;
-        struct cvmx_sli_pkt_instr_size_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t is_64b:32;
-#else
-                uint64_t is_64b:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_instr_size_s cn61xx;
-        struct cvmx_sli_pkt_instr_size_s cn63xx;
-        struct cvmx_sli_pkt_instr_size_s cn63xxp1;
-        struct cvmx_sli_pkt_instr_size_s cn66xx;
-        struct cvmx_sli_pkt_instr_size_s cn68xx;
-        struct cvmx_sli_pkt_instr_size_s cn68xxp1;
-        struct cvmx_sli_pkt_instr_size_s cnf71xx;
-};
-
-union cvmx_sli_pkt_int_levels {
-        uint64_t u64;
-        struct cvmx_sli_pkt_int_levels_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t time:22;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t time:22;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_sli_pkt_int_levels_s cn61xx;
-        struct cvmx_sli_pkt_int_levels_s cn63xx;
-        struct cvmx_sli_pkt_int_levels_s cn63xxp1;
-        struct cvmx_sli_pkt_int_levels_s cn66xx;
-        struct cvmx_sli_pkt_int_levels_s cn68xx;
-        struct cvmx_sli_pkt_int_levels_s cn68xxp1;
-        struct cvmx_sli_pkt_int_levels_s cnf71xx;
-};
-
-union cvmx_sli_pkt_iptr {
-        uint64_t u64;
-        struct cvmx_sli_pkt_iptr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t iptr:32;
-#else
-                uint64_t iptr:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_iptr_s cn61xx;
-        struct cvmx_sli_pkt_iptr_s cn63xx;
-        struct cvmx_sli_pkt_iptr_s cn63xxp1;
-        struct cvmx_sli_pkt_iptr_s cn66xx;
-        struct cvmx_sli_pkt_iptr_s cn68xx;
-        struct cvmx_sli_pkt_iptr_s cn68xxp1;
-        struct cvmx_sli_pkt_iptr_s cnf71xx;
-};
-
-union cvmx_sli_pkt_out_bmode {
-        uint64_t u64;
-        struct cvmx_sli_pkt_out_bmode_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t bmode:32;
-#else
-                uint64_t bmode:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_out_bmode_s cn61xx;
-        struct cvmx_sli_pkt_out_bmode_s cn63xx;
-        struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
-        struct cvmx_sli_pkt_out_bmode_s cn66xx;
-        struct cvmx_sli_pkt_out_bmode_s cn68xx;
-        struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
-        struct cvmx_sli_pkt_out_bmode_s cnf71xx;
-};
-
-union cvmx_sli_pkt_out_bp_en {
-        uint64_t u64;
-        struct cvmx_sli_pkt_out_bp_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t bp_en:32;
-#else
-                uint64_t bp_en:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_out_bp_en_s cn68xx;
-        struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
-};
-
-union cvmx_sli_pkt_out_enb {
-        uint64_t u64;
-        struct cvmx_sli_pkt_out_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t enb:32;
-#else
-                uint64_t enb:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_out_enb_s cn61xx;
-        struct cvmx_sli_pkt_out_enb_s cn63xx;
-        struct cvmx_sli_pkt_out_enb_s cn63xxp1;
-        struct cvmx_sli_pkt_out_enb_s cn66xx;
-        struct cvmx_sli_pkt_out_enb_s cn68xx;
-        struct cvmx_sli_pkt_out_enb_s cn68xxp1;
-        struct cvmx_sli_pkt_out_enb_s cnf71xx;
-};
-
-union cvmx_sli_pkt_output_wmark {
-        uint64_t u64;
-        struct cvmx_sli_pkt_output_wmark_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t wmark:32;
-#else
-                uint64_t wmark:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_output_wmark_s cn61xx;
-        struct cvmx_sli_pkt_output_wmark_s cn63xx;
-        struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
-        struct cvmx_sli_pkt_output_wmark_s cn66xx;
-        struct cvmx_sli_pkt_output_wmark_s cn68xx;
-        struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
-        struct cvmx_sli_pkt_output_wmark_s cnf71xx;
-};
-
-union cvmx_sli_pkt_pcie_port {
-        uint64_t u64;
-        struct cvmx_sli_pkt_pcie_port_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t pp:64;
-#else
-                uint64_t pp:64;
-#endif
-        } s;
-        struct cvmx_sli_pkt_pcie_port_s cn61xx;
-        struct cvmx_sli_pkt_pcie_port_s cn63xx;
-        struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
-        struct cvmx_sli_pkt_pcie_port_s cn66xx;
-        struct cvmx_sli_pkt_pcie_port_s cn68xx;
-        struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
-        struct cvmx_sli_pkt_pcie_port_s cnf71xx;
-};
-
-union cvmx_sli_pkt_port_in_rst {
-        uint64_t u64;
-        struct cvmx_sli_pkt_port_in_rst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t in_rst:32;
-                uint64_t out_rst:32;
-#else
-                uint64_t out_rst:32;
-                uint64_t in_rst:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_port_in_rst_s cn61xx;
-        struct cvmx_sli_pkt_port_in_rst_s cn63xx;
-        struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
-        struct cvmx_sli_pkt_port_in_rst_s cn66xx;
-        struct cvmx_sli_pkt_port_in_rst_s cn68xx;
-        struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
-        struct cvmx_sli_pkt_port_in_rst_s cnf71xx;
-};
-
-union cvmx_sli_pkt_slist_es {
-        uint64_t u64;
-        struct cvmx_sli_pkt_slist_es_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t es:64;
-#else
-                uint64_t es:64;
-#endif
-        } s;
-        struct cvmx_sli_pkt_slist_es_s cn61xx;
-        struct cvmx_sli_pkt_slist_es_s cn63xx;
-        struct cvmx_sli_pkt_slist_es_s cn63xxp1;
-        struct cvmx_sli_pkt_slist_es_s cn66xx;
-        struct cvmx_sli_pkt_slist_es_s cn68xx;
-        struct cvmx_sli_pkt_slist_es_s cn68xxp1;
-        struct cvmx_sli_pkt_slist_es_s cnf71xx;
-};
-
-union cvmx_sli_pkt_slist_ns {
-        uint64_t u64;
-        struct cvmx_sli_pkt_slist_ns_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t nsr:32;
-#else
-                uint64_t nsr:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_slist_ns_s cn61xx;
-        struct cvmx_sli_pkt_slist_ns_s cn63xx;
-        struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
-        struct cvmx_sli_pkt_slist_ns_s cn66xx;
-        struct cvmx_sli_pkt_slist_ns_s cn68xx;
-        struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
-        struct cvmx_sli_pkt_slist_ns_s cnf71xx;
-};
-
-union cvmx_sli_pkt_slist_ror {
-        uint64_t u64;
-        struct cvmx_sli_pkt_slist_ror_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t ror:32;
-#else
-                uint64_t ror:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_slist_ror_s cn61xx;
-        struct cvmx_sli_pkt_slist_ror_s cn63xx;
-        struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
-        struct cvmx_sli_pkt_slist_ror_s cn66xx;
-        struct cvmx_sli_pkt_slist_ror_s cn68xx;
-        struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
-        struct cvmx_sli_pkt_slist_ror_s cnf71xx;
-};
-
-union cvmx_sli_pkt_time_int {
-        uint64_t u64;
-        struct cvmx_sli_pkt_time_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t port:32;
-#else
-                uint64_t port:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_time_int_s cn61xx;
-        struct cvmx_sli_pkt_time_int_s cn63xx;
-        struct cvmx_sli_pkt_time_int_s cn63xxp1;
-        struct cvmx_sli_pkt_time_int_s cn66xx;
-        struct cvmx_sli_pkt_time_int_s cn68xx;
-        struct cvmx_sli_pkt_time_int_s cn68xxp1;
-        struct cvmx_sli_pkt_time_int_s cnf71xx;
-};
-
-union cvmx_sli_pkt_time_int_enb {
-        uint64_t u64;
-        struct cvmx_sli_pkt_time_int_enb_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t port:32;
-#else
-                uint64_t port:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_pkt_time_int_enb_s cn61xx;
-        struct cvmx_sli_pkt_time_int_enb_s cn63xx;
-        struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
-        struct cvmx_sli_pkt_time_int_enb_s cn66xx;
-        struct cvmx_sli_pkt_time_int_enb_s cn68xx;
-        struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
-        struct cvmx_sli_pkt_time_int_enb_s cnf71xx;
-};
-
-union cvmx_sli_portx_pkind {
-        uint64_t u64;
-        struct cvmx_sli_portx_pkind_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_25_63:39;
-                uint64_t rpk_enb:1;
-                uint64_t reserved_22_23:2;
-                uint64_t pkindr:6;
-                uint64_t reserved_14_15:2;
-                uint64_t bpkind:6;
-                uint64_t reserved_6_7:2;
-                uint64_t pkind:6;
-#else
-                uint64_t pkind:6;
-                uint64_t reserved_6_7:2;
-                uint64_t bpkind:6;
-                uint64_t reserved_14_15:2;
-                uint64_t pkindr:6;
-                uint64_t reserved_22_23:2;
-                uint64_t rpk_enb:1;
-                uint64_t reserved_25_63:39;
-#endif
-        } s;
-        struct cvmx_sli_portx_pkind_s cn68xx;
-        struct cvmx_sli_portx_pkind_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t bpkind:6;
-                uint64_t reserved_6_7:2;
-                uint64_t pkind:6;
-#else
-                uint64_t pkind:6;
-                uint64_t reserved_6_7:2;
-                uint64_t bpkind:6;
-                uint64_t reserved_14_63:50;
-#endif
-        } cn68xxp1;
-};
-
-union cvmx_sli_s2m_portx_ctl {
-        uint64_t u64;
-        struct cvmx_sli_s2m_portx_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t wind_d:1;
-                uint64_t bar0_d:1;
-                uint64_t mrrs:3;
-#else
-                uint64_t mrrs:3;
-                uint64_t bar0_d:1;
-                uint64_t wind_d:1;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_sli_s2m_portx_ctl_s cn61xx;
-        struct cvmx_sli_s2m_portx_ctl_s cn63xx;
-        struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
-        struct cvmx_sli_s2m_portx_ctl_s cn66xx;
-        struct cvmx_sli_s2m_portx_ctl_s cn68xx;
-        struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
-        struct cvmx_sli_s2m_portx_ctl_s cnf71xx;
-};
-
-union cvmx_sli_scratch_1 {
-        uint64_t u64;
-        struct cvmx_sli_scratch_1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } s;
-        struct cvmx_sli_scratch_1_s cn61xx;
-        struct cvmx_sli_scratch_1_s cn63xx;
-        struct cvmx_sli_scratch_1_s cn63xxp1;
-        struct cvmx_sli_scratch_1_s cn66xx;
-        struct cvmx_sli_scratch_1_s cn68xx;
-        struct cvmx_sli_scratch_1_s cn68xxp1;
-        struct cvmx_sli_scratch_1_s cnf71xx;
-};
-
-union cvmx_sli_scratch_2 {
-        uint64_t u64;
-        struct cvmx_sli_scratch_2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t data:64;
-#else
-                uint64_t data:64;
-#endif
-        } s;
-        struct cvmx_sli_scratch_2_s cn61xx;
-        struct cvmx_sli_scratch_2_s cn63xx;
-        struct cvmx_sli_scratch_2_s cn63xxp1;
-        struct cvmx_sli_scratch_2_s cn66xx;
-        struct cvmx_sli_scratch_2_s cn68xx;
-        struct cvmx_sli_scratch_2_s cn68xxp1;
-        struct cvmx_sli_scratch_2_s cnf71xx;
-};
-
-union cvmx_sli_state1 {
-        uint64_t u64;
-        struct cvmx_sli_state1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t cpl1:12;
-                uint64_t cpl0:12;
-                uint64_t arb:1;
-                uint64_t csr:39;
-#else
-                uint64_t csr:39;
-                uint64_t arb:1;
-                uint64_t cpl0:12;
-                uint64_t cpl1:12;
-#endif
-        } s;
-        struct cvmx_sli_state1_s cn61xx;
-        struct cvmx_sli_state1_s cn63xx;
-        struct cvmx_sli_state1_s cn63xxp1;
-        struct cvmx_sli_state1_s cn66xx;
-        struct cvmx_sli_state1_s cn68xx;
-        struct cvmx_sli_state1_s cn68xxp1;
-        struct cvmx_sli_state1_s cnf71xx;
-};
-
-union cvmx_sli_state2 {
-        uint64_t u64;
-        struct cvmx_sli_state2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t nnp1:8;
-                uint64_t reserved_47_47:1;
-                uint64_t rac:1;
-                uint64_t csm1:15;
-                uint64_t csm0:15;
-                uint64_t nnp0:8;
-                uint64_t nnd:8;
-#else
-                uint64_t nnd:8;
-                uint64_t nnp0:8;
-                uint64_t csm0:15;
-                uint64_t csm1:15;
-                uint64_t rac:1;
-                uint64_t reserved_47_47:1;
-                uint64_t nnp1:8;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_sli_state2_s cn61xx;
-        struct cvmx_sli_state2_s cn63xx;
-        struct cvmx_sli_state2_s cn63xxp1;
-        struct cvmx_sli_state2_s cn66xx;
-        struct cvmx_sli_state2_s cn68xx;
-        struct cvmx_sli_state2_s cn68xxp1;
-        struct cvmx_sli_state2_s cnf71xx;
-};
-
-union cvmx_sli_state3 {
-        uint64_t u64;
-        struct cvmx_sli_state3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t psm1:15;
-                uint64_t psm0:15;
-                uint64_t nsm1:13;
-                uint64_t nsm0:13;
-#else
-                uint64_t nsm0:13;
-                uint64_t nsm1:13;
-                uint64_t psm0:15;
-                uint64_t psm1:15;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_sli_state3_s cn61xx;
-        struct cvmx_sli_state3_s cn63xx;
-        struct cvmx_sli_state3_s cn63xxp1;
-        struct cvmx_sli_state3_s cn66xx;
-        struct cvmx_sli_state3_s cn68xx;
-        struct cvmx_sli_state3_s cn68xxp1;
-        struct cvmx_sli_state3_s cnf71xx;
-};
-
-union cvmx_sli_tx_pipe {
-        uint64_t u64;
-        struct cvmx_sli_tx_pipe_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t nump:8;
-                uint64_t reserved_7_15:9;
-                uint64_t base:7;
-#else
-                uint64_t base:7;
-                uint64_t reserved_7_15:9;
-                uint64_t nump:8;
-                uint64_t reserved_24_63:40;
-#endif
-        } s;
-        struct cvmx_sli_tx_pipe_s cn68xx;
-        struct cvmx_sli_tx_pipe_s cn68xxp1;
-};
-
-union cvmx_sli_win_rd_addr {
-        uint64_t u64;
-        struct cvmx_sli_win_rd_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_51_63:13;
-                uint64_t ld_cmd:2;
-                uint64_t iobit:1;
-                uint64_t rd_addr:48;
-#else
-                uint64_t rd_addr:48;
-                uint64_t iobit:1;
-                uint64_t ld_cmd:2;
-                uint64_t reserved_51_63:13;
-#endif
-        } s;
-        struct cvmx_sli_win_rd_addr_s cn61xx;
-        struct cvmx_sli_win_rd_addr_s cn63xx;
-        struct cvmx_sli_win_rd_addr_s cn63xxp1;
-        struct cvmx_sli_win_rd_addr_s cn66xx;
-        struct cvmx_sli_win_rd_addr_s cn68xx;
-        struct cvmx_sli_win_rd_addr_s cn68xxp1;
-        struct cvmx_sli_win_rd_addr_s cnf71xx;
-};
-
-union cvmx_sli_win_rd_data {
-        uint64_t u64;
-        struct cvmx_sli_win_rd_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rd_data:64;
-#else
-                uint64_t rd_data:64;
-#endif
-        } s;
-        struct cvmx_sli_win_rd_data_s cn61xx;
-        struct cvmx_sli_win_rd_data_s cn63xx;
-        struct cvmx_sli_win_rd_data_s cn63xxp1;
-        struct cvmx_sli_win_rd_data_s cn66xx;
-        struct cvmx_sli_win_rd_data_s cn68xx;
-        struct cvmx_sli_win_rd_data_s cn68xxp1;
-        struct cvmx_sli_win_rd_data_s cnf71xx;
-};
-
-union cvmx_sli_win_wr_addr {
-        uint64_t u64;
-        struct cvmx_sli_win_wr_addr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_49_63:15;
-                uint64_t iobit:1;
-                uint64_t wr_addr:45;
-                uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t wr_addr:45;
-                uint64_t iobit:1;
-                uint64_t reserved_49_63:15;
-#endif
-        } s;
-        struct cvmx_sli_win_wr_addr_s cn61xx;
-        struct cvmx_sli_win_wr_addr_s cn63xx;
-        struct cvmx_sli_win_wr_addr_s cn63xxp1;
-        struct cvmx_sli_win_wr_addr_s cn66xx;
-        struct cvmx_sli_win_wr_addr_s cn68xx;
-        struct cvmx_sli_win_wr_addr_s cn68xxp1;
-        struct cvmx_sli_win_wr_addr_s cnf71xx;
-};
-
-union cvmx_sli_win_wr_data {
-        uint64_t u64;
-        struct cvmx_sli_win_wr_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t wr_data:64;
-#else
-                uint64_t wr_data:64;
-#endif
-        } s;
-        struct cvmx_sli_win_wr_data_s cn61xx;
-        struct cvmx_sli_win_wr_data_s cn63xx;
-        struct cvmx_sli_win_wr_data_s cn63xxp1;
-        struct cvmx_sli_win_wr_data_s cn66xx;
-        struct cvmx_sli_win_wr_data_s cn68xx;
-        struct cvmx_sli_win_wr_data_s cn68xxp1;
-        struct cvmx_sli_win_wr_data_s cnf71xx;
-};
-
-union cvmx_sli_win_wr_mask {
-        uint64_t u64;
-        struct cvmx_sli_win_wr_mask_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t wr_mask:8;
-#else
-                uint64_t wr_mask:8;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_sli_win_wr_mask_s cn61xx;
-        struct cvmx_sli_win_wr_mask_s cn63xx;
-        struct cvmx_sli_win_wr_mask_s cn63xxp1;
-        struct cvmx_sli_win_wr_mask_s cn66xx;
-        struct cvmx_sli_win_wr_mask_s cn68xx;
-        struct cvmx_sli_win_wr_mask_s cn68xxp1;
-        struct cvmx_sli_win_wr_mask_s cnf71xx;
-};
-
-union cvmx_sli_window_ctl {
-        uint64_t u64;
-        struct cvmx_sli_window_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t time:32;
-#else
-                uint64_t time:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sli_window_ctl_s cn61xx;
-        struct cvmx_sli_window_ctl_s cn63xx;
-        struct cvmx_sli_window_ctl_s cn63xxp1;
-        struct cvmx_sli_window_ctl_s cn66xx;
-        struct cvmx_sli_window_ctl_s cn68xx;
-        struct cvmx_sli_window_ctl_s cn68xxp1;
-        struct cvmx_sli_window_ctl_s cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
index 8a278e6ddba..4f3c0666e94 100644
--- a/arch/mips/include/asm/octeon/cvmx-smix-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,120 +28,15 @@
 #ifndef __CVMX_SMIX_DEFS_H__
 #define __CVMX_SMIX_DEFS_H__
 
-static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
-}
-
-static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
-}
-
-static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
-}
-
-static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
-}
-
-static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
-{
-        switch (cvmx_get_octeon_family()) {
-        case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
-        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
-        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
-        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
-                return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128;
-        }
-        return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
-}
+#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256)
 
 union cvmx_smix_clk {
         uint64_t u64;
         struct cvmx_smix_clk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_25_63:39;
                 uint64_t mode:1;
                 uint64_t reserved_21_23:3;
@@ -152,21 +47,8 @@ union cvmx_smix_clk {
                 uint64_t preamble:1;
                 uint64_t sample:4;
                 uint64_t phase:8;
-#else
-                uint64_t phase:8;
-                uint64_t sample:4;
-                uint64_t preamble:1;
-                uint64_t clk_idle:1;
-                uint64_t reserved_14_14:1;
-                uint64_t sample_mode:1;
-                uint64_t sample_hi:5;
-                uint64_t reserved_21_23:3;
-                uint64_t mode:1;
-                uint64_t reserved_25_63:39;
-#endif
         } s;
         struct cvmx_smix_clk_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_21_63:43;
                 uint64_t sample_hi:5;
                 uint64_t sample_mode:1;
@@ -175,16 +57,6 @@ union cvmx_smix_clk {
                 uint64_t preamble:1;
                 uint64_t sample:4;
                 uint64_t phase:8;
-#else
-                uint64_t phase:8;
-                uint64_t sample:4;
-                uint64_t preamble:1;
-                uint64_t clk_idle:1;
-                uint64_t reserved_14_14:1;
-                uint64_t sample_mode:1;
-                uint64_t sample_hi:5;
-                uint64_t reserved_21_63:43;
-#endif
         } cn30xx;
         struct cvmx_smix_clk_cn30xx cn31xx;
         struct cvmx_smix_clk_cn30xx cn38xx;
@@ -196,50 +68,27 @@ union cvmx_smix_clk {
         struct cvmx_smix_clk_s cn56xxp1;
         struct cvmx_smix_clk_cn30xx cn58xx;
         struct cvmx_smix_clk_cn30xx cn58xxp1;
-        struct cvmx_smix_clk_s cn61xx;
         struct cvmx_smix_clk_s cn63xx;
         struct cvmx_smix_clk_s cn63xxp1;
-        struct cvmx_smix_clk_s cn66xx;
-        struct cvmx_smix_clk_s cn68xx;
-        struct cvmx_smix_clk_s cn68xxp1;
-        struct cvmx_smix_clk_s cnf71xx;
 };
 
 union cvmx_smix_cmd {
         uint64_t u64;
         struct cvmx_smix_cmd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t phy_op:2;
                 uint64_t reserved_13_15:3;
                 uint64_t phy_adr:5;
                 uint64_t reserved_5_7:3;
                 uint64_t reg_adr:5;
-#else
-                uint64_t reg_adr:5;
-                uint64_t reserved_5_7:3;
-                uint64_t phy_adr:5;
-                uint64_t reserved_13_15:3;
-                uint64_t phy_op:2;
-                uint64_t reserved_18_63:46;
-#endif
         } s;
         struct cvmx_smix_cmd_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_17_63:47;
                 uint64_t phy_op:1;
                 uint64_t reserved_13_15:3;
                 uint64_t phy_adr:5;
                 uint64_t reserved_5_7:3;
                 uint64_t reg_adr:5;
-#else
-                uint64_t reg_adr:5;
-                uint64_t reserved_5_7:3;
-                uint64_t phy_adr:5;
-                uint64_t reserved_13_15:3;
-                uint64_t phy_op:1;
-                uint64_t reserved_17_63:47;
-#endif
         } cn30xx;
         struct cvmx_smix_cmd_cn30xx cn31xx;
         struct cvmx_smix_cmd_cn30xx cn38xx;
@@ -251,25 +100,15 @@ union cvmx_smix_cmd {
         struct cvmx_smix_cmd_s cn56xxp1;
         struct cvmx_smix_cmd_cn30xx cn58xx;
         struct cvmx_smix_cmd_cn30xx cn58xxp1;
-        struct cvmx_smix_cmd_s cn61xx;
         struct cvmx_smix_cmd_s cn63xx;
         struct cvmx_smix_cmd_s cn63xxp1;
-        struct cvmx_smix_cmd_s cn66xx;
-        struct cvmx_smix_cmd_s cn68xx;
-        struct cvmx_smix_cmd_s cn68xxp1;
-        struct cvmx_smix_cmd_s cnf71xx;
 };
 
 union cvmx_smix_en {
         uint64_t u64;
         struct cvmx_smix_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
         struct cvmx_smix_en_s cn30xx;
         struct cvmx_smix_en_s cn31xx;
@@ -282,29 +121,17 @@ union cvmx_smix_en {
         struct cvmx_smix_en_s cn56xxp1;
         struct cvmx_smix_en_s cn58xx;
         struct cvmx_smix_en_s cn58xxp1;
-        struct cvmx_smix_en_s cn61xx;
         struct cvmx_smix_en_s cn63xx;
         struct cvmx_smix_en_s cn63xxp1;
-        struct cvmx_smix_en_s cn66xx;
-        struct cvmx_smix_en_s cn68xx;
-        struct cvmx_smix_en_s cn68xxp1;
-        struct cvmx_smix_en_s cnf71xx;
 };
 
 union cvmx_smix_rd_dat {
         uint64_t u64;
         struct cvmx_smix_rd_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t pending:1;
                 uint64_t val:1;
                 uint64_t dat:16;
-#else
-                uint64_t dat:16;
-                uint64_t val:1;
-                uint64_t pending:1;
-                uint64_t reserved_18_63:46;
-#endif
         } s;
         struct cvmx_smix_rd_dat_s cn30xx;
         struct cvmx_smix_rd_dat_s cn31xx;
@@ -317,29 +144,17 @@ union cvmx_smix_rd_dat {
         struct cvmx_smix_rd_dat_s cn56xxp1;
         struct cvmx_smix_rd_dat_s cn58xx;
         struct cvmx_smix_rd_dat_s cn58xxp1;
-        struct cvmx_smix_rd_dat_s cn61xx;
         struct cvmx_smix_rd_dat_s cn63xx;
         struct cvmx_smix_rd_dat_s cn63xxp1;
-        struct cvmx_smix_rd_dat_s cn66xx;
-        struct cvmx_smix_rd_dat_s cn68xx;
-        struct cvmx_smix_rd_dat_s cn68xxp1;
-        struct cvmx_smix_rd_dat_s cnf71xx;
 };
 
 union cvmx_smix_wr_dat {
         uint64_t u64;
         struct cvmx_smix_wr_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_18_63:46;
                 uint64_t pending:1;
                 uint64_t val:1;
                 uint64_t dat:16;
-#else
-                uint64_t dat:16;
-                uint64_t val:1;
-                uint64_t pending:1;
-                uint64_t reserved_18_63:46;
-#endif
         } s;
         struct cvmx_smix_wr_dat_s cn30xx;
         struct cvmx_smix_wr_dat_s cn31xx;
@@ -352,13 +167,8 @@ union cvmx_smix_wr_dat {
         struct cvmx_smix_wr_dat_s cn56xxp1;
         struct cvmx_smix_wr_dat_s cn58xx;
         struct cvmx_smix_wr_dat_s cn58xxp1;
-        struct cvmx_smix_wr_dat_s cn61xx;
         struct cvmx_smix_wr_dat_s cn63xx;
         struct cvmx_smix_wr_dat_s cn63xxp1;
-        struct cvmx_smix_wr_dat_s cn66xx;
-        struct cvmx_smix_wr_dat_s cn68xx;
-        struct cvmx_smix_wr_dat_s cn68xxp1;
-        struct cvmx_smix_wr_dat_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h
deleted file mode 100644
index 3bf53b537bc..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-spi.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/*
- *
- * This file contains defines for the SPI interface
- */
-#ifndef __CVMX_SPI_H__
-#define __CVMX_SPI_H__
-
-#include <asm/octeon/cvmx-gmxx-defs.h>
-
-/* CSR typedefs have been moved to cvmx-csr-*.h */
-
-typedef enum {
-        CVMX_SPI_MODE_UNKNOWN = 0,
-        CVMX_SPI_MODE_TX_HALFPLEX = 1,
-        CVMX_SPI_MODE_RX_HALFPLEX = 2,
-        CVMX_SPI_MODE_DUPLEX = 3
-} cvmx_spi_mode_t;
-
-/** Callbacks structure to customize SPI4 initialization sequence */
-typedef struct {
-    /** Called to reset SPI4 DLL */
-        int (*reset_cb) (int interface, cvmx_spi_mode_t mode);
-
-    /** Called to setup calendar */
-        int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode,
-                                  int num_ports);
-
-    /** Called for Tx and Rx clock detection */
-        int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode,
-                                int timeout);
-
-    /** Called to perform link training */
-        int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout);
-
-    /** Called for calendar data synchronization */
-        int (*calendar_sync_cb) (int interface, cvmx_spi_mode_t mode,
-                                 int timeout);
-
-    /** Called when interface is up */
-        int (*interface_up_cb) (int interface, cvmx_spi_mode_t mode);
-
-} cvmx_spi_callbacks_t;
-
-/**
- * Return true if the supplied interface is configured for SPI
- *
- * @interface: Interface to check
- * Returns True if interface is SPI
- */
-static inline int cvmx_spi_is_spi_interface(int interface)
-{
-        uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
-        return (gmxState & 0x2) && (gmxState & 0x1);
-}
-
-/**
- * Initialize and start the SPI interface.
- *
- * @interface: The identifier of the packet interface to configure and
- *                  use as a SPI interface.
- * @mode:      The operating mode for the SPI interface. The interface
- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
- * @timeout:   Timeout to wait for clock synchronization in seconds
- * @num_ports: Number of SPI ports to configure
- *
- * Returns Zero on success, negative of failure.
- */
-extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode,
-                                    int timeout, int num_ports);
-
-/**
- * This routine restarts the SPI interface after it has lost synchronization
- * with its corespondant system.
- *
- * @interface: The identifier of the packet interface to configure and
- *                  use as a SPI interface.
- * @mode:      The operating mode for the SPI interface. The interface
- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
- * @timeout:   Timeout to wait for clock synchronization in seconds
- * Returns Zero on success, negative of failure.
- */
-extern int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode,
-                                      int timeout);
-
-/**
- * Return non-zero if the SPI interface has a SPI4000 attached
- *
- * @interface: SPI interface the SPI4000 is connected to
- *
- * Returns
- */
-static inline int cvmx_spi4000_is_present(int interface)
-{
-        return 0;
-}
-
-/**
- * Initialize the SPI4000 for use
- *
- * @interface: SPI interface the SPI4000 is connected to
- */
-static inline int cvmx_spi4000_initialize(int interface)
-{
-        return 0;
-}
-
-/**
- * Poll all the SPI4000 port and check its speed
- *
- * @interface: Interface the SPI4000 is on
- * @port:      Port to poll (0-9)
- * Returns Status of the port. 0=down. All other values the port is up.
- */
-static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
-        int interface,
-        int port)
-{
-        union cvmx_gmxx_rxx_rx_inbnd r;
-        r.u64 = 0;
-        return r;
-}
-
-/**
- * Get current SPI4 initialization callbacks
- *
- * @callbacks:  Pointer to the callbacks structure.to fill
- *
- * Returns Pointer to cvmx_spi_callbacks_t structure.
- */
-extern void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks);
-
-/**
- * Set new SPI4 initialization callbacks
- *
- * @new_callbacks:  Pointer to an updated callbacks structure.
- */
-extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks);
-
-/**
- * Callback to perform SPI4 reset
- *
- * @interface: The identifier of the packet interface to configure and
- *                  use as a SPI interface.
- * @mode:      The operating mode for the SPI interface. The interface
- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
- *
- * Returns Zero on success, non-zero error code on failure (will cause
- * SPI initialization to abort)
- */
-extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode);
-
-/**
- * Callback to setup calendar and miscellaneous settings before clock
- * detection
- *
- * @interface: The identifier of the packet interface to configure and
- *                  use as a SPI interface.
- * @mode:      The operating mode for the SPI interface. The interface
- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
- * @num_ports: Number of ports to configure on SPI
- *
- * Returns Zero on success, non-zero error code on failure (will cause
- * SPI initialization to abort)
- */
-extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
-                                      int num_ports);
-
-/**
- * Callback to perform clock detection
- *
- * @interface: The identifier of the packet interface to configure and
- *                  use as a SPI interface.
- * @mode:      The operating mode for the SPI interface. The interface
- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
- * @timeout:   Timeout to wait for clock synchronization in seconds
- *
- * Returns Zero on success, non-zero error code on failure (will cause
- * SPI initialization to abort)
- */
-extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode,
-                                    int timeout);
-
-/**
- * Callback to perform link training
- *
- * @interface: The identifier of the packet interface to configure and
- *                  use as a SPI interface.
- * @mode:      The operating mode for the SPI interface. The interface
- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
- * @timeout:   Timeout to wait for link to be trained (in seconds)
- *
- * Returns Zero on success, non-zero error code on failure (will cause
- * SPI initialization to abort)
- */
-extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode,
-                                int timeout);
-
-/**
- * Callback to perform calendar data synchronization
- *
- * @interface: The identifier of the packet interface to configure and
- *                  use as a SPI interface.
- * @mode:      The operating mode for the SPI interface. The interface
- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
- * @timeout:   Timeout to wait for calendar data in seconds
- *
- * Returns Zero on success, non-zero error code on failure (will cause
- * SPI initialization to abort)
- */
-extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode,
-                                     int timeout);
-
-/**
- * Callback to handle interface up
- *
- * @interface: The identifier of the packet interface to configure and
- *                  use as a SPI interface.
- * @mode:      The operating mode for the SPI interface. The interface
- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
- *
- * Returns Zero on success, non-zero error code on failure (will cause
- * SPI initialization to abort)
- */
-extern int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode);
-
-#endif /* __CVMX_SPI_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h
index a672abb1bc4..2fbf0871df1 100644
--- a/arch/mips/include/asm/octeon/cvmx-spinlock.h
+++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h
@@ -35,7 +35,7 @@
 #ifndef __CVMX_SPINLOCK_H__
 #define __CVMX_SPINLOCK_H__
 
-#include <asm/octeon/cvmx-asm.h>
+#include "cvmx-asm.h"
 
 /* Spinlocks for Octeon */
 
diff --git a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
deleted file mode 100644
index c7d601d9446..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_SPXX_DEFS_H__
-#define __CVMX_SPXX_DEFS_H__
-
-#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
-
-union cvmx_spxx_bckprs_cnt {
-        uint64_t u64;
-        struct cvmx_spxx_bckprs_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_spxx_bckprs_cnt_s cn38xx;
-        struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
-        struct cvmx_spxx_bckprs_cnt_s cn58xx;
-        struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
-};
-
-union cvmx_spxx_bist_stat {
-        uint64_t u64;
-        struct cvmx_spxx_bist_stat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t stat2:1;
-                uint64_t stat1:1;
-                uint64_t stat0:1;
-#else
-                uint64_t stat0:1;
-                uint64_t stat1:1;
-                uint64_t stat2:1;
-                uint64_t reserved_3_63:61;
-#endif
-        } s;
-        struct cvmx_spxx_bist_stat_s cn38xx;
-        struct cvmx_spxx_bist_stat_s cn38xxp2;
-        struct cvmx_spxx_bist_stat_s cn58xx;
-        struct cvmx_spxx_bist_stat_s cn58xxp1;
-};
-
-union cvmx_spxx_clk_ctl {
-        uint64_t u64;
-        struct cvmx_spxx_clk_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t seetrn:1;
-                uint64_t reserved_12_15:4;
-                uint64_t clkdly:5;
-                uint64_t runbist:1;
-                uint64_t statdrv:1;
-                uint64_t statrcv:1;
-                uint64_t sndtrn:1;
-                uint64_t drptrn:1;
-                uint64_t rcvtrn:1;
-                uint64_t srxdlck:1;
-#else
-                uint64_t srxdlck:1;
-                uint64_t rcvtrn:1;
-                uint64_t drptrn:1;
-                uint64_t sndtrn:1;
-                uint64_t statrcv:1;
-                uint64_t statdrv:1;
-                uint64_t runbist:1;
-                uint64_t clkdly:5;
-                uint64_t reserved_12_15:4;
-                uint64_t seetrn:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_spxx_clk_ctl_s cn38xx;
-        struct cvmx_spxx_clk_ctl_s cn38xxp2;
-        struct cvmx_spxx_clk_ctl_s cn58xx;
-        struct cvmx_spxx_clk_ctl_s cn58xxp1;
-};
-
-union cvmx_spxx_clk_stat {
-        uint64_t u64;
-        struct cvmx_spxx_clk_stat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_11_63:53;
-                uint64_t stxcal:1;
-                uint64_t reserved_9_9:1;
-                uint64_t srxtrn:1;
-                uint64_t s4clk1:1;
-                uint64_t s4clk0:1;
-                uint64_t d4clk1:1;
-                uint64_t d4clk0:1;
-                uint64_t reserved_0_3:4;
-#else
-                uint64_t reserved_0_3:4;
-                uint64_t d4clk0:1;
-                uint64_t d4clk1:1;
-                uint64_t s4clk0:1;
-                uint64_t s4clk1:1;
-                uint64_t srxtrn:1;
-                uint64_t reserved_9_9:1;
-                uint64_t stxcal:1;
-                uint64_t reserved_11_63:53;
-#endif
-        } s;
-        struct cvmx_spxx_clk_stat_s cn38xx;
-        struct cvmx_spxx_clk_stat_s cn38xxp2;
-        struct cvmx_spxx_clk_stat_s cn58xx;
-        struct cvmx_spxx_clk_stat_s cn58xxp1;
-};
-
-union cvmx_spxx_dbg_deskew_ctl {
-        uint64_t u64;
-        struct cvmx_spxx_dbg_deskew_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_30_63:34;
-                uint64_t fallnop:1;
-                uint64_t fall8:1;
-                uint64_t reserved_26_27:2;
-                uint64_t sstep_go:1;
-                uint64_t sstep:1;
-                uint64_t reserved_22_23:2;
-                uint64_t clrdly:1;
-                uint64_t dec:1;
-                uint64_t inc:1;
-                uint64_t mux:1;
-                uint64_t offset:5;
-                uint64_t bitsel:5;
-                uint64_t offdly:6;
-                uint64_t dllfrc:1;
-                uint64_t dlldis:1;
-#else
-                uint64_t dlldis:1;
-                uint64_t dllfrc:1;
-                uint64_t offdly:6;
-                uint64_t bitsel:5;
-                uint64_t offset:5;
-                uint64_t mux:1;
-                uint64_t inc:1;
-                uint64_t dec:1;
-                uint64_t clrdly:1;
-                uint64_t reserved_22_23:2;
-                uint64_t sstep:1;
-                uint64_t sstep_go:1;
-                uint64_t reserved_26_27:2;
-                uint64_t fall8:1;
-                uint64_t fallnop:1;
-                uint64_t reserved_30_63:34;
-#endif
-        } s;
-        struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
-        struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
-        struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
-        struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
-};
-
-union cvmx_spxx_dbg_deskew_state {
-        uint64_t u64;
-        struct cvmx_spxx_dbg_deskew_state_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t testres:1;
-                uint64_t unxterm:1;
-                uint64_t muxsel:2;
-                uint64_t offset:5;
-#else
-                uint64_t offset:5;
-                uint64_t muxsel:2;
-                uint64_t unxterm:1;
-                uint64_t testres:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_spxx_dbg_deskew_state_s cn38xx;
-        struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
-        struct cvmx_spxx_dbg_deskew_state_s cn58xx;
-        struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
-};
-
-union cvmx_spxx_drv_ctl {
-        uint64_t u64;
-        struct cvmx_spxx_drv_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_0_63:64;
-#else
-                uint64_t reserved_0_63:64;
-#endif
-        } s;
-        struct cvmx_spxx_drv_ctl_cn38xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t stx4ncmp:4;
-                uint64_t stx4pcmp:4;
-                uint64_t srx4cmp:8;
-#else
-                uint64_t srx4cmp:8;
-                uint64_t stx4pcmp:4;
-                uint64_t stx4ncmp:4;
-                uint64_t reserved_16_63:48;
-#endif
-        } cn38xx;
-        struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
-        struct cvmx_spxx_drv_ctl_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_24_63:40;
-                uint64_t stx4ncmp:4;
-                uint64_t stx4pcmp:4;
-                uint64_t reserved_10_15:6;
-                uint64_t srx4cmp:10;
-#else
-                uint64_t srx4cmp:10;
-                uint64_t reserved_10_15:6;
-                uint64_t stx4pcmp:4;
-                uint64_t stx4ncmp:4;
-                uint64_t reserved_24_63:40;
-#endif
-        } cn58xx;
-        struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
-};
-
-union cvmx_spxx_err_ctl {
-        uint64_t u64;
-        struct cvmx_spxx_err_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t prtnxa:1;
-                uint64_t dipcls:1;
-                uint64_t dippay:1;
-                uint64_t reserved_4_5:2;
-                uint64_t errcnt:4;
-#else
-                uint64_t errcnt:4;
-                uint64_t reserved_4_5:2;
-                uint64_t dippay:1;
-                uint64_t dipcls:1;
-                uint64_t prtnxa:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_spxx_err_ctl_s cn38xx;
-        struct cvmx_spxx_err_ctl_s cn38xxp2;
-        struct cvmx_spxx_err_ctl_s cn58xx;
-        struct cvmx_spxx_err_ctl_s cn58xxp1;
-};
-
-union cvmx_spxx_int_dat {
-        uint64_t u64;
-        struct cvmx_spxx_int_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t mul:1;
-                uint64_t reserved_14_30:17;
-                uint64_t calbnk:2;
-                uint64_t rsvop:4;
-                uint64_t prt:8;
-#else
-                uint64_t prt:8;
-                uint64_t rsvop:4;
-                uint64_t calbnk:2;
-                uint64_t reserved_14_30:17;
-                uint64_t mul:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_spxx_int_dat_s cn38xx;
-        struct cvmx_spxx_int_dat_s cn38xxp2;
-        struct cvmx_spxx_int_dat_s cn58xx;
-        struct cvmx_spxx_int_dat_s cn58xxp1;
-};
-
-union cvmx_spxx_int_msk {
-        uint64_t u64;
-        struct cvmx_spxx_int_msk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t calerr:1;
-                uint64_t syncerr:1;
-                uint64_t diperr:1;
-                uint64_t tpaovr:1;
-                uint64_t rsverr:1;
-                uint64_t drwnng:1;
-                uint64_t clserr:1;
-                uint64_t spiovr:1;
-                uint64_t reserved_2_3:2;
-                uint64_t abnorm:1;
-                uint64_t prtnxa:1;
-#else
-                uint64_t prtnxa:1;
-                uint64_t abnorm:1;
-                uint64_t reserved_2_3:2;
-                uint64_t spiovr:1;
-                uint64_t clserr:1;
-                uint64_t drwnng:1;
-                uint64_t rsverr:1;
-                uint64_t tpaovr:1;
-                uint64_t diperr:1;
-                uint64_t syncerr:1;
-                uint64_t calerr:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } s;
-        struct cvmx_spxx_int_msk_s cn38xx;
-        struct cvmx_spxx_int_msk_s cn38xxp2;
-        struct cvmx_spxx_int_msk_s cn58xx;
-        struct cvmx_spxx_int_msk_s cn58xxp1;
-};
-
-union cvmx_spxx_int_reg {
-        uint64_t u64;
-        struct cvmx_spxx_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t spf:1;
-                uint64_t reserved_12_30:19;
-                uint64_t calerr:1;
-                uint64_t syncerr:1;
-                uint64_t diperr:1;
-                uint64_t tpaovr:1;
-                uint64_t rsverr:1;
-                uint64_t drwnng:1;
-                uint64_t clserr:1;
-                uint64_t spiovr:1;
-                uint64_t reserved_2_3:2;
-                uint64_t abnorm:1;
-                uint64_t prtnxa:1;
-#else
-                uint64_t prtnxa:1;
-                uint64_t abnorm:1;
-                uint64_t reserved_2_3:2;
-                uint64_t spiovr:1;
-                uint64_t clserr:1;
-                uint64_t drwnng:1;
-                uint64_t rsverr:1;
-                uint64_t tpaovr:1;
-                uint64_t diperr:1;
-                uint64_t syncerr:1;
-                uint64_t calerr:1;
-                uint64_t reserved_12_30:19;
-                uint64_t spf:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_spxx_int_reg_s cn38xx;
-        struct cvmx_spxx_int_reg_s cn38xxp2;
-        struct cvmx_spxx_int_reg_s cn58xx;
-        struct cvmx_spxx_int_reg_s cn58xxp1;
-};
-
-union cvmx_spxx_int_sync {
-        uint64_t u64;
-        struct cvmx_spxx_int_sync_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_12_63:52;
-                uint64_t calerr:1;
-                uint64_t syncerr:1;
-                uint64_t diperr:1;
-                uint64_t tpaovr:1;
-                uint64_t rsverr:1;
-                uint64_t drwnng:1;
-                uint64_t clserr:1;
-                uint64_t spiovr:1;
-                uint64_t reserved_2_3:2;
-                uint64_t abnorm:1;
-                uint64_t prtnxa:1;
-#else
-                uint64_t prtnxa:1;
-                uint64_t abnorm:1;
-                uint64_t reserved_2_3:2;
-                uint64_t spiovr:1;
-                uint64_t clserr:1;
-                uint64_t drwnng:1;
-                uint64_t rsverr:1;
-                uint64_t tpaovr:1;
-                uint64_t diperr:1;
-                uint64_t syncerr:1;
-                uint64_t calerr:1;
-                uint64_t reserved_12_63:52;
-#endif
-        } s;
-        struct cvmx_spxx_int_sync_s cn38xx;
-        struct cvmx_spxx_int_sync_s cn38xxp2;
-        struct cvmx_spxx_int_sync_s cn58xx;
-        struct cvmx_spxx_int_sync_s cn58xxp1;
-};
-
-union cvmx_spxx_tpa_acc {
-        uint64_t u64;
-        struct cvmx_spxx_tpa_acc_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_spxx_tpa_acc_s cn38xx;
-        struct cvmx_spxx_tpa_acc_s cn38xxp2;
-        struct cvmx_spxx_tpa_acc_s cn58xx;
-        struct cvmx_spxx_tpa_acc_s cn58xxp1;
-};
-
-union cvmx_spxx_tpa_max {
-        uint64_t u64;
-        struct cvmx_spxx_tpa_max_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t max:32;
-#else
-                uint64_t max:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_spxx_tpa_max_s cn38xx;
-        struct cvmx_spxx_tpa_max_s cn38xxp2;
-        struct cvmx_spxx_tpa_max_s cn58xx;
-        struct cvmx_spxx_tpa_max_s cn58xxp1;
-};
-
-union cvmx_spxx_tpa_sel {
-        uint64_t u64;
-        struct cvmx_spxx_tpa_sel_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t prtsel:4;
-#else
-                uint64_t prtsel:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_spxx_tpa_sel_s cn38xx;
-        struct cvmx_spxx_tpa_sel_s cn38xxp2;
-        struct cvmx_spxx_tpa_sel_s cn58xx;
-        struct cvmx_spxx_tpa_sel_s cn58xxp1;
-};
-
-union cvmx_spxx_trn4_ctl {
-        uint64_t u64;
-        struct cvmx_spxx_trn4_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_13_63:51;
-                uint64_t trntest:1;
-                uint64_t jitter:3;
-                uint64_t clr_boot:1;
-                uint64_t set_boot:1;
-                uint64_t maxdist:5;
-                uint64_t macro_en:1;
-                uint64_t mux_en:1;
-#else
-                uint64_t mux_en:1;
-                uint64_t macro_en:1;
-                uint64_t maxdist:5;
-                uint64_t set_boot:1;
-                uint64_t clr_boot:1;
-                uint64_t jitter:3;
-                uint64_t trntest:1;
-                uint64_t reserved_13_63:51;
-#endif
-        } s;
-        struct cvmx_spxx_trn4_ctl_s cn38xx;
-        struct cvmx_spxx_trn4_ctl_s cn38xxp2;
-        struct cvmx_spxx_trn4_ctl_s cn58xx;
-        struct cvmx_spxx_trn4_ctl_s cn58xxp1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
deleted file mode 100644
index 5140f2d2ad1..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
+++ /dev/null
@@ -1,1737 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_SRIOX_DEFS_H__
-#define __CVMX_SRIOX_DEFS_H__
-
-#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
-#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
-#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
-#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
-#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
-#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
-#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
-#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
-#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
-#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
-#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
-#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
-#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
-
-union cvmx_sriox_acc_ctrl {
-        uint64_t u64;
-        struct cvmx_sriox_acc_ctrl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_7_63:57;
-                uint64_t deny_adr2:1;
-                uint64_t deny_adr1:1;
-                uint64_t deny_adr0:1;
-                uint64_t reserved_3_3:1;
-                uint64_t deny_bar2:1;
-                uint64_t deny_bar1:1;
-                uint64_t deny_bar0:1;
-#else
-                uint64_t deny_bar0:1;
-                uint64_t deny_bar1:1;
-                uint64_t deny_bar2:1;
-                uint64_t reserved_3_3:1;
-                uint64_t deny_adr0:1;
-                uint64_t deny_adr1:1;
-                uint64_t deny_adr2:1;
-                uint64_t reserved_7_63:57;
-#endif
-        } s;
-        struct cvmx_sriox_acc_ctrl_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_3_63:61;
-                uint64_t deny_bar2:1;
-                uint64_t deny_bar1:1;
-                uint64_t deny_bar0:1;
-#else
-                uint64_t deny_bar0:1;
-                uint64_t deny_bar1:1;
-                uint64_t deny_bar2:1;
-                uint64_t reserved_3_63:61;
-#endif
-        } cn63xx;
-        struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
-        struct cvmx_sriox_acc_ctrl_s cn66xx;
-};
-
-union cvmx_sriox_asmbly_id {
-        uint64_t u64;
-        struct cvmx_sriox_asmbly_id_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t assy_id:16;
-                uint64_t assy_ven:16;
-#else
-                uint64_t assy_ven:16;
-                uint64_t assy_id:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_asmbly_id_s cn63xx;
-        struct cvmx_sriox_asmbly_id_s cn63xxp1;
-        struct cvmx_sriox_asmbly_id_s cn66xx;
-};
-
-union cvmx_sriox_asmbly_info {
-        uint64_t u64;
-        struct cvmx_sriox_asmbly_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t assy_rev:16;
-                uint64_t reserved_0_15:16;
-#else
-                uint64_t reserved_0_15:16;
-                uint64_t assy_rev:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_asmbly_info_s cn63xx;
-        struct cvmx_sriox_asmbly_info_s cn63xxp1;
-        struct cvmx_sriox_asmbly_info_s cn66xx;
-};
-
-union cvmx_sriox_bell_resp_ctrl {
-        uint64_t u64;
-        struct cvmx_sriox_bell_resp_ctrl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t rp1_sid:1;
-                uint64_t rp0_sid:2;
-                uint64_t rp1_pid:1;
-                uint64_t rp0_pid:2;
-#else
-                uint64_t rp0_pid:2;
-                uint64_t rp1_pid:1;
-                uint64_t rp0_sid:2;
-                uint64_t rp1_sid:1;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
-        struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
-        struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
-};
-
-union cvmx_sriox_bist_status {
-        uint64_t u64;
-        struct cvmx_sriox_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_45_63:19;
-                uint64_t lram:1;
-                uint64_t mram:2;
-                uint64_t cram:2;
-                uint64_t bell:2;
-                uint64_t otag:2;
-                uint64_t itag:1;
-                uint64_t ofree:1;
-                uint64_t rtn:2;
-                uint64_t obulk:4;
-                uint64_t optrs:4;
-                uint64_t oarb2:2;
-                uint64_t rxbuf2:2;
-                uint64_t oarb:2;
-                uint64_t ispf:1;
-                uint64_t ospf:1;
-                uint64_t txbuf:2;
-                uint64_t rxbuf:2;
-                uint64_t imsg:5;
-                uint64_t omsg:7;
-#else
-                uint64_t omsg:7;
-                uint64_t imsg:5;
-                uint64_t rxbuf:2;
-                uint64_t txbuf:2;
-                uint64_t ospf:1;
-                uint64_t ispf:1;
-                uint64_t oarb:2;
-                uint64_t rxbuf2:2;
-                uint64_t oarb2:2;
-                uint64_t optrs:4;
-                uint64_t obulk:4;
-                uint64_t rtn:2;
-                uint64_t ofree:1;
-                uint64_t itag:1;
-                uint64_t otag:2;
-                uint64_t bell:2;
-                uint64_t cram:2;
-                uint64_t mram:2;
-                uint64_t lram:1;
-                uint64_t reserved_45_63:19;
-#endif
-        } s;
-        struct cvmx_sriox_bist_status_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t mram:2;
-                uint64_t cram:2;
-                uint64_t bell:2;
-                uint64_t otag:2;
-                uint64_t itag:1;
-                uint64_t ofree:1;
-                uint64_t rtn:2;
-                uint64_t obulk:4;
-                uint64_t optrs:4;
-                uint64_t oarb2:2;
-                uint64_t rxbuf2:2;
-                uint64_t oarb:2;
-                uint64_t ispf:1;
-                uint64_t ospf:1;
-                uint64_t txbuf:2;
-                uint64_t rxbuf:2;
-                uint64_t imsg:5;
-                uint64_t omsg:7;
-#else
-                uint64_t omsg:7;
-                uint64_t imsg:5;
-                uint64_t rxbuf:2;
-                uint64_t txbuf:2;
-                uint64_t ospf:1;
-                uint64_t ispf:1;
-                uint64_t oarb:2;
-                uint64_t rxbuf2:2;
-                uint64_t oarb2:2;
-                uint64_t optrs:4;
-                uint64_t obulk:4;
-                uint64_t rtn:2;
-                uint64_t ofree:1;
-                uint64_t itag:1;
-                uint64_t otag:2;
-                uint64_t bell:2;
-                uint64_t cram:2;
-                uint64_t mram:2;
-                uint64_t reserved_44_63:20;
-#endif
-        } cn63xx;
-        struct cvmx_sriox_bist_status_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_44_63:20;
-                uint64_t mram:2;
-                uint64_t cram:2;
-                uint64_t bell:2;
-                uint64_t otag:2;
-                uint64_t itag:1;
-                uint64_t ofree:1;
-                uint64_t rtn:2;
-                uint64_t obulk:4;
-                uint64_t optrs:4;
-                uint64_t reserved_20_23:4;
-                uint64_t oarb:2;
-                uint64_t ispf:1;
-                uint64_t ospf:1;
-                uint64_t txbuf:2;
-                uint64_t rxbuf:2;
-                uint64_t imsg:5;
-                uint64_t omsg:7;
-#else
-                uint64_t omsg:7;
-                uint64_t imsg:5;
-                uint64_t rxbuf:2;
-                uint64_t txbuf:2;
-                uint64_t ospf:1;
-                uint64_t ispf:1;
-                uint64_t oarb:2;
-                uint64_t reserved_20_23:4;
-                uint64_t optrs:4;
-                uint64_t obulk:4;
-                uint64_t rtn:2;
-                uint64_t ofree:1;
-                uint64_t itag:1;
-                uint64_t otag:2;
-                uint64_t bell:2;
-                uint64_t cram:2;
-                uint64_t mram:2;
-                uint64_t reserved_44_63:20;
-#endif
-        } cn63xxp1;
-        struct cvmx_sriox_bist_status_s cn66xx;
-};
-
-union cvmx_sriox_imsg_ctrl {
-        uint64_t u64;
-        struct cvmx_sriox_imsg_ctrl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t to_mode:1;
-                uint64_t reserved_30_30:1;
-                uint64_t rsp_thr:6;
-                uint64_t reserved_22_23:2;
-                uint64_t rp1_sid:1;
-                uint64_t rp0_sid:2;
-                uint64_t rp1_pid:1;
-                uint64_t rp0_pid:2;
-                uint64_t reserved_15_15:1;
-                uint64_t prt_sel:3;
-                uint64_t lttr:4;
-                uint64_t prio:4;
-                uint64_t mbox:4;
-#else
-                uint64_t mbox:4;
-                uint64_t prio:4;
-                uint64_t lttr:4;
-                uint64_t prt_sel:3;
-                uint64_t reserved_15_15:1;
-                uint64_t rp0_pid:2;
-                uint64_t rp1_pid:1;
-                uint64_t rp0_sid:2;
-                uint64_t rp1_sid:1;
-                uint64_t reserved_22_23:2;
-                uint64_t rsp_thr:6;
-                uint64_t reserved_30_30:1;
-                uint64_t to_mode:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_imsg_ctrl_s cn63xx;
-        struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
-        struct cvmx_sriox_imsg_ctrl_s cn66xx;
-};
-
-union cvmx_sriox_imsg_inst_hdrx {
-        uint64_t u64;
-        struct cvmx_sriox_imsg_inst_hdrx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t r:1;
-                uint64_t reserved_58_62:5;
-                uint64_t pm:2;
-                uint64_t reserved_55_55:1;
-                uint64_t sl:7;
-                uint64_t reserved_46_47:2;
-                uint64_t nqos:1;
-                uint64_t ngrp:1;
-                uint64_t ntt:1;
-                uint64_t ntag:1;
-                uint64_t reserved_35_41:7;
-                uint64_t rs:1;
-                uint64_t tt:2;
-                uint64_t tag:32;
-#else
-                uint64_t tag:32;
-                uint64_t tt:2;
-                uint64_t rs:1;
-                uint64_t reserved_35_41:7;
-                uint64_t ntag:1;
-                uint64_t ntt:1;
-                uint64_t ngrp:1;
-                uint64_t nqos:1;
-                uint64_t reserved_46_47:2;
-                uint64_t sl:7;
-                uint64_t reserved_55_55:1;
-                uint64_t pm:2;
-                uint64_t reserved_58_62:5;
-                uint64_t r:1;
-#endif
-        } s;
-        struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
-        struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
-        struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
-};
-
-union cvmx_sriox_imsg_qos_grpx {
-        uint64_t u64;
-        struct cvmx_sriox_imsg_qos_grpx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_63_63:1;
-                uint64_t qos7:3;
-                uint64_t grp7:4;
-                uint64_t reserved_55_55:1;
-                uint64_t qos6:3;
-                uint64_t grp6:4;
-                uint64_t reserved_47_47:1;
-                uint64_t qos5:3;
-                uint64_t grp5:4;
-                uint64_t reserved_39_39:1;
-                uint64_t qos4:3;
-                uint64_t grp4:4;
-                uint64_t reserved_31_31:1;
-                uint64_t qos3:3;
-                uint64_t grp3:4;
-                uint64_t reserved_23_23:1;
-                uint64_t qos2:3;
-                uint64_t grp2:4;
-                uint64_t reserved_15_15:1;
-                uint64_t qos1:3;
-                uint64_t grp1:4;
-                uint64_t reserved_7_7:1;
-                uint64_t qos0:3;
-                uint64_t grp0:4;
-#else
-                uint64_t grp0:4;
-                uint64_t qos0:3;
-                uint64_t reserved_7_7:1;
-                uint64_t grp1:4;
-                uint64_t qos1:3;
-                uint64_t reserved_15_15:1;
-                uint64_t grp2:4;
-                uint64_t qos2:3;
-                uint64_t reserved_23_23:1;
-                uint64_t grp3:4;
-                uint64_t qos3:3;
-                uint64_t reserved_31_31:1;
-                uint64_t grp4:4;
-                uint64_t qos4:3;
-                uint64_t reserved_39_39:1;
-                uint64_t grp5:4;
-                uint64_t qos5:3;
-                uint64_t reserved_47_47:1;
-                uint64_t grp6:4;
-                uint64_t qos6:3;
-                uint64_t reserved_55_55:1;
-                uint64_t grp7:4;
-                uint64_t qos7:3;
-                uint64_t reserved_63_63:1;
-#endif
-        } s;
-        struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
-        struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
-        struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
-};
-
-union cvmx_sriox_imsg_statusx {
-        uint64_t u64;
-        struct cvmx_sriox_imsg_statusx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t val1:1;
-                uint64_t err1:1;
-                uint64_t toe1:1;
-                uint64_t toc1:1;
-                uint64_t prt1:1;
-                uint64_t reserved_58_58:1;
-                uint64_t tt1:1;
-                uint64_t dis1:1;
-                uint64_t seg1:4;
-                uint64_t mbox1:2;
-                uint64_t lttr1:2;
-                uint64_t sid1:16;
-                uint64_t val0:1;
-                uint64_t err0:1;
-                uint64_t toe0:1;
-                uint64_t toc0:1;
-                uint64_t prt0:1;
-                uint64_t reserved_26_26:1;
-                uint64_t tt0:1;
-                uint64_t dis0:1;
-                uint64_t seg0:4;
-                uint64_t mbox0:2;
-                uint64_t lttr0:2;
-                uint64_t sid0:16;
-#else
-                uint64_t sid0:16;
-                uint64_t lttr0:2;
-                uint64_t mbox0:2;
-                uint64_t seg0:4;
-                uint64_t dis0:1;
-                uint64_t tt0:1;
-                uint64_t reserved_26_26:1;
-                uint64_t prt0:1;
-                uint64_t toc0:1;
-                uint64_t toe0:1;
-                uint64_t err0:1;
-                uint64_t val0:1;
-                uint64_t sid1:16;
-                uint64_t lttr1:2;
-                uint64_t mbox1:2;
-                uint64_t seg1:4;
-                uint64_t dis1:1;
-                uint64_t tt1:1;
-                uint64_t reserved_58_58:1;
-                uint64_t prt1:1;
-                uint64_t toc1:1;
-                uint64_t toe1:1;
-                uint64_t err1:1;
-                uint64_t val1:1;
-#endif
-        } s;
-        struct cvmx_sriox_imsg_statusx_s cn63xx;
-        struct cvmx_sriox_imsg_statusx_s cn63xxp1;
-        struct cvmx_sriox_imsg_statusx_s cn66xx;
-};
-
-union cvmx_sriox_imsg_vport_thr {
-        uint64_t u64;
-        struct cvmx_sriox_imsg_vport_thr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_54_63:10;
-                uint64_t max_tot:6;
-                uint64_t reserved_46_47:2;
-                uint64_t max_s1:6;
-                uint64_t reserved_38_39:2;
-                uint64_t max_s0:6;
-                uint64_t sp_vport:1;
-                uint64_t reserved_20_30:11;
-                uint64_t buf_thr:4;
-                uint64_t reserved_14_15:2;
-                uint64_t max_p1:6;
-                uint64_t reserved_6_7:2;
-                uint64_t max_p0:6;
-#else
-                uint64_t max_p0:6;
-                uint64_t reserved_6_7:2;
-                uint64_t max_p1:6;
-                uint64_t reserved_14_15:2;
-                uint64_t buf_thr:4;
-                uint64_t reserved_20_30:11;
-                uint64_t sp_vport:1;
-                uint64_t max_s0:6;
-                uint64_t reserved_38_39:2;
-                uint64_t max_s1:6;
-                uint64_t reserved_46_47:2;
-                uint64_t max_tot:6;
-                uint64_t reserved_54_63:10;
-#endif
-        } s;
-        struct cvmx_sriox_imsg_vport_thr_s cn63xx;
-        struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
-        struct cvmx_sriox_imsg_vport_thr_s cn66xx;
-};
-
-union cvmx_sriox_imsg_vport_thr2 {
-        uint64_t u64;
-        struct cvmx_sriox_imsg_vport_thr2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_46_63:18;
-                uint64_t max_s3:6;
-                uint64_t reserved_38_39:2;
-                uint64_t max_s2:6;
-                uint64_t reserved_0_31:32;
-#else
-                uint64_t reserved_0_31:32;
-                uint64_t max_s2:6;
-                uint64_t reserved_38_39:2;
-                uint64_t max_s3:6;
-                uint64_t reserved_46_63:18;
-#endif
-        } s;
-        struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
-};
-
-union cvmx_sriox_int2_enable {
-        uint64_t u64;
-        struct cvmx_sriox_int2_enable_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t pko_rst:1;
-#else
-                uint64_t pko_rst:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_sriox_int2_enable_s cn63xx;
-        struct cvmx_sriox_int2_enable_s cn66xx;
-};
-
-union cvmx_sriox_int2_reg {
-        uint64_t u64;
-        struct cvmx_sriox_int2_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t int_sum:1;
-                uint64_t reserved_1_30:30;
-                uint64_t pko_rst:1;
-#else
-                uint64_t pko_rst:1;
-                uint64_t reserved_1_30:30;
-                uint64_t int_sum:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_int2_reg_s cn63xx;
-        struct cvmx_sriox_int2_reg_s cn66xx;
-};
-
-union cvmx_sriox_int_enable {
-        uint64_t u64;
-        struct cvmx_sriox_int_enable_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_27_63:37;
-                uint64_t zero_pkt:1;
-                uint64_t ttl_tout:1;
-                uint64_t fail:1;
-                uint64_t degrade:1;
-                uint64_t mac_buf:1;
-                uint64_t f_error:1;
-                uint64_t rtry_err:1;
-                uint64_t pko_err:1;
-                uint64_t omsg_err:1;
-                uint64_t omsg1:1;
-                uint64_t omsg0:1;
-                uint64_t link_up:1;
-                uint64_t link_dwn:1;
-                uint64_t phy_erb:1;
-                uint64_t log_erb:1;
-                uint64_t soft_rx:1;
-                uint64_t soft_tx:1;
-                uint64_t mce_rx:1;
-                uint64_t mce_tx:1;
-                uint64_t wr_done:1;
-                uint64_t sli_err:1;
-                uint64_t deny_wr:1;
-                uint64_t bar_err:1;
-                uint64_t maint_op:1;
-                uint64_t rxbell:1;
-                uint64_t bell_err:1;
-                uint64_t txbell:1;
-#else
-                uint64_t txbell:1;
-                uint64_t bell_err:1;
-                uint64_t rxbell:1;
-                uint64_t maint_op:1;
-                uint64_t bar_err:1;
-                uint64_t deny_wr:1;
-                uint64_t sli_err:1;
-                uint64_t wr_done:1;
-                uint64_t mce_tx:1;
-                uint64_t mce_rx:1;
-                uint64_t soft_tx:1;
-                uint64_t soft_rx:1;
-                uint64_t log_erb:1;
-                uint64_t phy_erb:1;
-                uint64_t link_dwn:1;
-                uint64_t link_up:1;
-                uint64_t omsg0:1;
-                uint64_t omsg1:1;
-                uint64_t omsg_err:1;
-                uint64_t pko_err:1;
-                uint64_t rtry_err:1;
-                uint64_t f_error:1;
-                uint64_t mac_buf:1;
-                uint64_t degrade:1;
-                uint64_t fail:1;
-                uint64_t ttl_tout:1;
-                uint64_t zero_pkt:1;
-                uint64_t reserved_27_63:37;
-#endif
-        } s;
-        struct cvmx_sriox_int_enable_s cn63xx;
-        struct cvmx_sriox_int_enable_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t f_error:1;
-                uint64_t rtry_err:1;
-                uint64_t pko_err:1;
-                uint64_t omsg_err:1;
-                uint64_t omsg1:1;
-                uint64_t omsg0:1;
-                uint64_t link_up:1;
-                uint64_t link_dwn:1;
-                uint64_t phy_erb:1;
-                uint64_t log_erb:1;
-                uint64_t soft_rx:1;
-                uint64_t soft_tx:1;
-                uint64_t mce_rx:1;
-                uint64_t mce_tx:1;
-                uint64_t wr_done:1;
-                uint64_t sli_err:1;
-                uint64_t deny_wr:1;
-                uint64_t bar_err:1;
-                uint64_t maint_op:1;
-                uint64_t rxbell:1;
-                uint64_t bell_err:1;
-                uint64_t txbell:1;
-#else
-                uint64_t txbell:1;
-                uint64_t bell_err:1;
-                uint64_t rxbell:1;
-                uint64_t maint_op:1;
-                uint64_t bar_err:1;
-                uint64_t deny_wr:1;
-                uint64_t sli_err:1;
-                uint64_t wr_done:1;
-                uint64_t mce_tx:1;
-                uint64_t mce_rx:1;
-                uint64_t soft_tx:1;
-                uint64_t soft_rx:1;
-                uint64_t log_erb:1;
-                uint64_t phy_erb:1;
-                uint64_t link_dwn:1;
-                uint64_t link_up:1;
-                uint64_t omsg0:1;
-                uint64_t omsg1:1;
-                uint64_t omsg_err:1;
-                uint64_t pko_err:1;
-                uint64_t rtry_err:1;
-                uint64_t f_error:1;
-                uint64_t reserved_22_63:42;
-#endif
-        } cn63xxp1;
-        struct cvmx_sriox_int_enable_s cn66xx;
-};
-
-union cvmx_sriox_int_info0 {
-        uint64_t u64;
-        struct cvmx_sriox_int_info0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t cmd:4;
-                uint64_t type:4;
-                uint64_t tag:8;
-                uint64_t reserved_42_47:6;
-                uint64_t length:10;
-                uint64_t status:3;
-                uint64_t reserved_16_28:13;
-                uint64_t be0:8;
-                uint64_t be1:8;
-#else
-                uint64_t be1:8;
-                uint64_t be0:8;
-                uint64_t reserved_16_28:13;
-                uint64_t status:3;
-                uint64_t length:10;
-                uint64_t reserved_42_47:6;
-                uint64_t tag:8;
-                uint64_t type:4;
-                uint64_t cmd:4;
-#endif
-        } s;
-        struct cvmx_sriox_int_info0_s cn63xx;
-        struct cvmx_sriox_int_info0_s cn63xxp1;
-        struct cvmx_sriox_int_info0_s cn66xx;
-};
-
-union cvmx_sriox_int_info1 {
-        uint64_t u64;
-        struct cvmx_sriox_int_info1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t info1:64;
-#else
-                uint64_t info1:64;
-#endif
-        } s;
-        struct cvmx_sriox_int_info1_s cn63xx;
-        struct cvmx_sriox_int_info1_s cn63xxp1;
-        struct cvmx_sriox_int_info1_s cn66xx;
-};
-
-union cvmx_sriox_int_info2 {
-        uint64_t u64;
-        struct cvmx_sriox_int_info2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t prio:2;
-                uint64_t tt:1;
-                uint64_t sis:1;
-                uint64_t ssize:4;
-                uint64_t did:16;
-                uint64_t xmbox:4;
-                uint64_t mbox:2;
-                uint64_t letter:2;
-                uint64_t rsrvd:30;
-                uint64_t lns:1;
-                uint64_t intr:1;
-#else
-                uint64_t intr:1;
-                uint64_t lns:1;
-                uint64_t rsrvd:30;
-                uint64_t letter:2;
-                uint64_t mbox:2;
-                uint64_t xmbox:4;
-                uint64_t did:16;
-                uint64_t ssize:4;
-                uint64_t sis:1;
-                uint64_t tt:1;
-                uint64_t prio:2;
-#endif
-        } s;
-        struct cvmx_sriox_int_info2_s cn63xx;
-        struct cvmx_sriox_int_info2_s cn63xxp1;
-        struct cvmx_sriox_int_info2_s cn66xx;
-};
-
-union cvmx_sriox_int_info3 {
-        uint64_t u64;
-        struct cvmx_sriox_int_info3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t prio:2;
-                uint64_t tt:2;
-                uint64_t type:4;
-                uint64_t other:48;
-                uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t other:48;
-                uint64_t type:4;
-                uint64_t tt:2;
-                uint64_t prio:2;
-#endif
-        } s;
-        struct cvmx_sriox_int_info3_s cn63xx;
-        struct cvmx_sriox_int_info3_s cn63xxp1;
-        struct cvmx_sriox_int_info3_s cn66xx;
-};
-
-union cvmx_sriox_int_reg {
-        uint64_t u64;
-        struct cvmx_sriox_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t int2_sum:1;
-                uint64_t reserved_27_30:4;
-                uint64_t zero_pkt:1;
-                uint64_t ttl_tout:1;
-                uint64_t fail:1;
-                uint64_t degrad:1;
-                uint64_t mac_buf:1;
-                uint64_t f_error:1;
-                uint64_t rtry_err:1;
-                uint64_t pko_err:1;
-                uint64_t omsg_err:1;
-                uint64_t omsg1:1;
-                uint64_t omsg0:1;
-                uint64_t link_up:1;
-                uint64_t link_dwn:1;
-                uint64_t phy_erb:1;
-                uint64_t log_erb:1;
-                uint64_t soft_rx:1;
-                uint64_t soft_tx:1;
-                uint64_t mce_rx:1;
-                uint64_t mce_tx:1;
-                uint64_t wr_done:1;
-                uint64_t sli_err:1;
-                uint64_t deny_wr:1;
-                uint64_t bar_err:1;
-                uint64_t maint_op:1;
-                uint64_t rxbell:1;
-                uint64_t bell_err:1;
-                uint64_t txbell:1;
-#else
-                uint64_t txbell:1;
-                uint64_t bell_err:1;
-                uint64_t rxbell:1;
-                uint64_t maint_op:1;
-                uint64_t bar_err:1;
-                uint64_t deny_wr:1;
-                uint64_t sli_err:1;
-                uint64_t wr_done:1;
-                uint64_t mce_tx:1;
-                uint64_t mce_rx:1;
-                uint64_t soft_tx:1;
-                uint64_t soft_rx:1;
-                uint64_t log_erb:1;
-                uint64_t phy_erb:1;
-                uint64_t link_dwn:1;
-                uint64_t link_up:1;
-                uint64_t omsg0:1;
-                uint64_t omsg1:1;
-                uint64_t omsg_err:1;
-                uint64_t pko_err:1;
-                uint64_t rtry_err:1;
-                uint64_t f_error:1;
-                uint64_t mac_buf:1;
-                uint64_t degrad:1;
-                uint64_t fail:1;
-                uint64_t ttl_tout:1;
-                uint64_t zero_pkt:1;
-                uint64_t reserved_27_30:4;
-                uint64_t int2_sum:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_int_reg_s cn63xx;
-        struct cvmx_sriox_int_reg_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_22_63:42;
-                uint64_t f_error:1;
-                uint64_t rtry_err:1;
-                uint64_t pko_err:1;
-                uint64_t omsg_err:1;
-                uint64_t omsg1:1;
-                uint64_t omsg0:1;
-                uint64_t link_up:1;
-                uint64_t link_dwn:1;
-                uint64_t phy_erb:1;
-                uint64_t log_erb:1;
-                uint64_t soft_rx:1;
-                uint64_t soft_tx:1;
-                uint64_t mce_rx:1;
-                uint64_t mce_tx:1;
-                uint64_t wr_done:1;
-                uint64_t sli_err:1;
-                uint64_t deny_wr:1;
-                uint64_t bar_err:1;
-                uint64_t maint_op:1;
-                uint64_t rxbell:1;
-                uint64_t bell_err:1;
-                uint64_t txbell:1;
-#else
-                uint64_t txbell:1;
-                uint64_t bell_err:1;
-                uint64_t rxbell:1;
-                uint64_t maint_op:1;
-                uint64_t bar_err:1;
-                uint64_t deny_wr:1;
-                uint64_t sli_err:1;
-                uint64_t wr_done:1;
-                uint64_t mce_tx:1;
-                uint64_t mce_rx:1;
-                uint64_t soft_tx:1;
-                uint64_t soft_rx:1;
-                uint64_t log_erb:1;
-                uint64_t phy_erb:1;
-                uint64_t link_dwn:1;
-                uint64_t link_up:1;
-                uint64_t omsg0:1;
-                uint64_t omsg1:1;
-                uint64_t omsg_err:1;
-                uint64_t pko_err:1;
-                uint64_t rtry_err:1;
-                uint64_t f_error:1;
-                uint64_t reserved_22_63:42;
-#endif
-        } cn63xxp1;
-        struct cvmx_sriox_int_reg_s cn66xx;
-};
-
-union cvmx_sriox_ip_feature {
-        uint64_t u64;
-        struct cvmx_sriox_ip_feature_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t ops:32;
-                uint64_t reserved_15_31:17;
-                uint64_t no_vmin:1;
-                uint64_t a66:1;
-                uint64_t a50:1;
-                uint64_t reserved_11_11:1;
-                uint64_t tx_flow:1;
-                uint64_t pt_width:2;
-                uint64_t tx_pol:4;
-                uint64_t rx_pol:4;
-#else
-                uint64_t rx_pol:4;
-                uint64_t tx_pol:4;
-                uint64_t pt_width:2;
-                uint64_t tx_flow:1;
-                uint64_t reserved_11_11:1;
-                uint64_t a50:1;
-                uint64_t a66:1;
-                uint64_t no_vmin:1;
-                uint64_t reserved_15_31:17;
-                uint64_t ops:32;
-#endif
-        } s;
-        struct cvmx_sriox_ip_feature_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t ops:32;
-                uint64_t reserved_14_31:18;
-                uint64_t a66:1;
-                uint64_t a50:1;
-                uint64_t reserved_11_11:1;
-                uint64_t tx_flow:1;
-                uint64_t pt_width:2;
-                uint64_t tx_pol:4;
-                uint64_t rx_pol:4;
-#else
-                uint64_t rx_pol:4;
-                uint64_t tx_pol:4;
-                uint64_t pt_width:2;
-                uint64_t tx_flow:1;
-                uint64_t reserved_11_11:1;
-                uint64_t a50:1;
-                uint64_t a66:1;
-                uint64_t reserved_14_31:18;
-                uint64_t ops:32;
-#endif
-        } cn63xx;
-        struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
-        struct cvmx_sriox_ip_feature_s cn66xx;
-};
-
-union cvmx_sriox_mac_buffers {
-        uint64_t u64;
-        struct cvmx_sriox_mac_buffers_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_56_63:8;
-                uint64_t tx_enb:8;
-                uint64_t reserved_44_47:4;
-                uint64_t tx_inuse:4;
-                uint64_t tx_stat:8;
-                uint64_t reserved_24_31:8;
-                uint64_t rx_enb:8;
-                uint64_t reserved_12_15:4;
-                uint64_t rx_inuse:4;
-                uint64_t rx_stat:8;
-#else
-                uint64_t rx_stat:8;
-                uint64_t rx_inuse:4;
-                uint64_t reserved_12_15:4;
-                uint64_t rx_enb:8;
-                uint64_t reserved_24_31:8;
-                uint64_t tx_stat:8;
-                uint64_t tx_inuse:4;
-                uint64_t reserved_44_47:4;
-                uint64_t tx_enb:8;
-                uint64_t reserved_56_63:8;
-#endif
-        } s;
-        struct cvmx_sriox_mac_buffers_s cn63xx;
-        struct cvmx_sriox_mac_buffers_s cn66xx;
-};
-
-union cvmx_sriox_maint_op {
-        uint64_t u64;
-        struct cvmx_sriox_maint_op_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t wr_data:32;
-                uint64_t reserved_27_31:5;
-                uint64_t fail:1;
-                uint64_t pending:1;
-                uint64_t op:1;
-                uint64_t addr:24;
-#else
-                uint64_t addr:24;
-                uint64_t op:1;
-                uint64_t pending:1;
-                uint64_t fail:1;
-                uint64_t reserved_27_31:5;
-                uint64_t wr_data:32;
-#endif
-        } s;
-        struct cvmx_sriox_maint_op_s cn63xx;
-        struct cvmx_sriox_maint_op_s cn63xxp1;
-        struct cvmx_sriox_maint_op_s cn66xx;
-};
-
-union cvmx_sriox_maint_rd_data {
-        uint64_t u64;
-        struct cvmx_sriox_maint_rd_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_33_63:31;
-                uint64_t valid:1;
-                uint64_t rd_data:32;
-#else
-                uint64_t rd_data:32;
-                uint64_t valid:1;
-                uint64_t reserved_33_63:31;
-#endif
-        } s;
-        struct cvmx_sriox_maint_rd_data_s cn63xx;
-        struct cvmx_sriox_maint_rd_data_s cn63xxp1;
-        struct cvmx_sriox_maint_rd_data_s cn66xx;
-};
-
-union cvmx_sriox_mce_tx_ctl {
-        uint64_t u64;
-        struct cvmx_sriox_mce_tx_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_1_63:63;
-                uint64_t mce:1;
-#else
-                uint64_t mce:1;
-                uint64_t reserved_1_63:63;
-#endif
-        } s;
-        struct cvmx_sriox_mce_tx_ctl_s cn63xx;
-        struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
-        struct cvmx_sriox_mce_tx_ctl_s cn66xx;
-};
-
-union cvmx_sriox_mem_op_ctrl {
-        uint64_t u64;
-        struct cvmx_sriox_mem_op_ctrl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_10_63:54;
-                uint64_t rr_ro:1;
-                uint64_t w_ro:1;
-                uint64_t reserved_6_7:2;
-                uint64_t rp1_sid:1;
-                uint64_t rp0_sid:2;
-                uint64_t rp1_pid:1;
-                uint64_t rp0_pid:2;
-#else
-                uint64_t rp0_pid:2;
-                uint64_t rp1_pid:1;
-                uint64_t rp0_sid:2;
-                uint64_t rp1_sid:1;
-                uint64_t reserved_6_7:2;
-                uint64_t w_ro:1;
-                uint64_t rr_ro:1;
-                uint64_t reserved_10_63:54;
-#endif
-        } s;
-        struct cvmx_sriox_mem_op_ctrl_s cn63xx;
-        struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
-        struct cvmx_sriox_mem_op_ctrl_s cn66xx;
-};
-
-union cvmx_sriox_omsg_ctrlx {
-        uint64_t u64;
-        struct cvmx_sriox_omsg_ctrlx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t testmode:1;
-                uint64_t reserved_37_62:26;
-                uint64_t silo_max:5;
-                uint64_t rtry_thr:16;
-                uint64_t rtry_en:1;
-                uint64_t reserved_11_14:4;
-                uint64_t idm_tt:1;
-                uint64_t idm_sis:1;
-                uint64_t idm_did:1;
-                uint64_t lttr_sp:4;
-                uint64_t lttr_mp:4;
-#else
-                uint64_t lttr_mp:4;
-                uint64_t lttr_sp:4;
-                uint64_t idm_did:1;
-                uint64_t idm_sis:1;
-                uint64_t idm_tt:1;
-                uint64_t reserved_11_14:4;
-                uint64_t rtry_en:1;
-                uint64_t rtry_thr:16;
-                uint64_t silo_max:5;
-                uint64_t reserved_37_62:26;
-                uint64_t testmode:1;
-#endif
-        } s;
-        struct cvmx_sriox_omsg_ctrlx_s cn63xx;
-        struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t testmode:1;
-                uint64_t reserved_32_62:31;
-                uint64_t rtry_thr:16;
-                uint64_t rtry_en:1;
-                uint64_t reserved_11_14:4;
-                uint64_t idm_tt:1;
-                uint64_t idm_sis:1;
-                uint64_t idm_did:1;
-                uint64_t lttr_sp:4;
-                uint64_t lttr_mp:4;
-#else
-                uint64_t lttr_mp:4;
-                uint64_t lttr_sp:4;
-                uint64_t idm_did:1;
-                uint64_t idm_sis:1;
-                uint64_t idm_tt:1;
-                uint64_t reserved_11_14:4;
-                uint64_t rtry_en:1;
-                uint64_t rtry_thr:16;
-                uint64_t reserved_32_62:31;
-                uint64_t testmode:1;
-#endif
-        } cn63xxp1;
-        struct cvmx_sriox_omsg_ctrlx_s cn66xx;
-};
-
-union cvmx_sriox_omsg_done_countsx {
-        uint64_t u64;
-        struct cvmx_sriox_omsg_done_countsx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t bad:16;
-                uint64_t good:16;
-#else
-                uint64_t good:16;
-                uint64_t bad:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_omsg_done_countsx_s cn63xx;
-        struct cvmx_sriox_omsg_done_countsx_s cn66xx;
-};
-
-union cvmx_sriox_omsg_fmp_mrx {
-        uint64_t u64;
-        struct cvmx_sriox_omsg_fmp_mrx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t ctlr_sp:1;
-                uint64_t ctlr_fmp:1;
-                uint64_t ctlr_nmp:1;
-                uint64_t id_sp:1;
-                uint64_t id_fmp:1;
-                uint64_t id_nmp:1;
-                uint64_t id_psd:1;
-                uint64_t mbox_sp:1;
-                uint64_t mbox_fmp:1;
-                uint64_t mbox_nmp:1;
-                uint64_t mbox_psd:1;
-                uint64_t all_sp:1;
-                uint64_t all_fmp:1;
-                uint64_t all_nmp:1;
-                uint64_t all_psd:1;
-#else
-                uint64_t all_psd:1;
-                uint64_t all_nmp:1;
-                uint64_t all_fmp:1;
-                uint64_t all_sp:1;
-                uint64_t mbox_psd:1;
-                uint64_t mbox_nmp:1;
-                uint64_t mbox_fmp:1;
-                uint64_t mbox_sp:1;
-                uint64_t id_psd:1;
-                uint64_t id_nmp:1;
-                uint64_t id_fmp:1;
-                uint64_t id_sp:1;
-                uint64_t ctlr_nmp:1;
-                uint64_t ctlr_fmp:1;
-                uint64_t ctlr_sp:1;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
-        struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
-        struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
-};
-
-union cvmx_sriox_omsg_nmp_mrx {
-        uint64_t u64;
-        struct cvmx_sriox_omsg_nmp_mrx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_15_63:49;
-                uint64_t ctlr_sp:1;
-                uint64_t ctlr_fmp:1;
-                uint64_t ctlr_nmp:1;
-                uint64_t id_sp:1;
-                uint64_t id_fmp:1;
-                uint64_t id_nmp:1;
-                uint64_t reserved_8_8:1;
-                uint64_t mbox_sp:1;
-                uint64_t mbox_fmp:1;
-                uint64_t mbox_nmp:1;
-                uint64_t reserved_4_4:1;
-                uint64_t all_sp:1;
-                uint64_t all_fmp:1;
-                uint64_t all_nmp:1;
-                uint64_t reserved_0_0:1;
-#else
-                uint64_t reserved_0_0:1;
-                uint64_t all_nmp:1;
-                uint64_t all_fmp:1;
-                uint64_t all_sp:1;
-                uint64_t reserved_4_4:1;
-                uint64_t mbox_nmp:1;
-                uint64_t mbox_fmp:1;
-                uint64_t mbox_sp:1;
-                uint64_t reserved_8_8:1;
-                uint64_t id_nmp:1;
-                uint64_t id_fmp:1;
-                uint64_t id_sp:1;
-                uint64_t ctlr_nmp:1;
-                uint64_t ctlr_fmp:1;
-                uint64_t ctlr_sp:1;
-                uint64_t reserved_15_63:49;
-#endif
-        } s;
-        struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
-        struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
-        struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
-};
-
-union cvmx_sriox_omsg_portx {
-        uint64_t u64;
-        struct cvmx_sriox_omsg_portx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t enable:1;
-                uint64_t reserved_3_30:28;
-                uint64_t port:3;
-#else
-                uint64_t port:3;
-                uint64_t reserved_3_30:28;
-                uint64_t enable:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_omsg_portx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t enable:1;
-                uint64_t reserved_2_30:29;
-                uint64_t port:2;
-#else
-                uint64_t port:2;
-                uint64_t reserved_2_30:29;
-                uint64_t enable:1;
-                uint64_t reserved_32_63:32;
-#endif
-        } cn63xx;
-        struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
-        struct cvmx_sriox_omsg_portx_s cn66xx;
-};
-
-union cvmx_sriox_omsg_silo_thr {
-        uint64_t u64;
-        struct cvmx_sriox_omsg_silo_thr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t tot_silo:5;
-#else
-                uint64_t tot_silo:5;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_sriox_omsg_silo_thr_s cn63xx;
-        struct cvmx_sriox_omsg_silo_thr_s cn66xx;
-};
-
-union cvmx_sriox_omsg_sp_mrx {
-        uint64_t u64;
-        struct cvmx_sriox_omsg_sp_mrx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t xmbox_sp:1;
-                uint64_t ctlr_sp:1;
-                uint64_t ctlr_fmp:1;
-                uint64_t ctlr_nmp:1;
-                uint64_t id_sp:1;
-                uint64_t id_fmp:1;
-                uint64_t id_nmp:1;
-                uint64_t id_psd:1;
-                uint64_t mbox_sp:1;
-                uint64_t mbox_fmp:1;
-                uint64_t mbox_nmp:1;
-                uint64_t mbox_psd:1;
-                uint64_t all_sp:1;
-                uint64_t all_fmp:1;
-                uint64_t all_nmp:1;
-                uint64_t all_psd:1;
-#else
-                uint64_t all_psd:1;
-                uint64_t all_nmp:1;
-                uint64_t all_fmp:1;
-                uint64_t all_sp:1;
-                uint64_t mbox_psd:1;
-                uint64_t mbox_nmp:1;
-                uint64_t mbox_fmp:1;
-                uint64_t mbox_sp:1;
-                uint64_t id_psd:1;
-                uint64_t id_nmp:1;
-                uint64_t id_fmp:1;
-                uint64_t id_sp:1;
-                uint64_t ctlr_nmp:1;
-                uint64_t ctlr_fmp:1;
-                uint64_t ctlr_sp:1;
-                uint64_t xmbox_sp:1;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
-        struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
-        struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
-};
-
-union cvmx_sriox_priox_in_use {
-        uint64_t u64;
-        struct cvmx_sriox_priox_in_use_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t end_cnt:16;
-                uint64_t start_cnt:16;
-#else
-                uint64_t start_cnt:16;
-                uint64_t end_cnt:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_priox_in_use_s cn63xx;
-        struct cvmx_sriox_priox_in_use_s cn66xx;
-};
-
-union cvmx_sriox_rx_bell {
-        uint64_t u64;
-        struct cvmx_sriox_rx_bell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t data:16;
-                uint64_t src_id:16;
-                uint64_t count:8;
-                uint64_t reserved_5_7:3;
-                uint64_t dest_id:1;
-                uint64_t id16:1;
-                uint64_t reserved_2_2:1;
-                uint64_t priority:2;
-#else
-                uint64_t priority:2;
-                uint64_t reserved_2_2:1;
-                uint64_t id16:1;
-                uint64_t dest_id:1;
-                uint64_t reserved_5_7:3;
-                uint64_t count:8;
-                uint64_t src_id:16;
-                uint64_t data:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_sriox_rx_bell_s cn63xx;
-        struct cvmx_sriox_rx_bell_s cn63xxp1;
-        struct cvmx_sriox_rx_bell_s cn66xx;
-};
-
-union cvmx_sriox_rx_bell_seq {
-        uint64_t u64;
-        struct cvmx_sriox_rx_bell_seq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_40_63:24;
-                uint64_t count:8;
-                uint64_t seq:32;
-#else
-                uint64_t seq:32;
-                uint64_t count:8;
-                uint64_t reserved_40_63:24;
-#endif
-        } s;
-        struct cvmx_sriox_rx_bell_seq_s cn63xx;
-        struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
-        struct cvmx_sriox_rx_bell_seq_s cn66xx;
-};
-
-union cvmx_sriox_rx_status {
-        uint64_t u64;
-        struct cvmx_sriox_rx_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t rtn_pr3:8;
-                uint64_t rtn_pr2:8;
-                uint64_t rtn_pr1:8;
-                uint64_t reserved_28_39:12;
-                uint64_t mbox:4;
-                uint64_t comp:8;
-                uint64_t reserved_13_15:3;
-                uint64_t n_post:5;
-                uint64_t post:8;
-#else
-                uint64_t post:8;
-                uint64_t n_post:5;
-                uint64_t reserved_13_15:3;
-                uint64_t comp:8;
-                uint64_t mbox:4;
-                uint64_t reserved_28_39:12;
-                uint64_t rtn_pr1:8;
-                uint64_t rtn_pr2:8;
-                uint64_t rtn_pr3:8;
-#endif
-        } s;
-        struct cvmx_sriox_rx_status_s cn63xx;
-        struct cvmx_sriox_rx_status_s cn63xxp1;
-        struct cvmx_sriox_rx_status_s cn66xx;
-};
-
-union cvmx_sriox_s2m_typex {
-        uint64_t u64;
-        struct cvmx_sriox_s2m_typex_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_19_63:45;
-                uint64_t wr_op:3;
-                uint64_t reserved_15_15:1;
-                uint64_t rd_op:3;
-                uint64_t wr_prior:2;
-                uint64_t rd_prior:2;
-                uint64_t reserved_6_7:2;
-                uint64_t src_id:1;
-                uint64_t id16:1;
-                uint64_t reserved_2_3:2;
-                uint64_t iaow_sel:2;
-#else
-                uint64_t iaow_sel:2;
-                uint64_t reserved_2_3:2;
-                uint64_t id16:1;
-                uint64_t src_id:1;
-                uint64_t reserved_6_7:2;
-                uint64_t rd_prior:2;
-                uint64_t wr_prior:2;
-                uint64_t rd_op:3;
-                uint64_t reserved_15_15:1;
-                uint64_t wr_op:3;
-                uint64_t reserved_19_63:45;
-#endif
-        } s;
-        struct cvmx_sriox_s2m_typex_s cn63xx;
-        struct cvmx_sriox_s2m_typex_s cn63xxp1;
-        struct cvmx_sriox_s2m_typex_s cn66xx;
-};
-
-union cvmx_sriox_seq {
-        uint64_t u64;
-        struct cvmx_sriox_seq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t seq:32;
-#else
-                uint64_t seq:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_seq_s cn63xx;
-        struct cvmx_sriox_seq_s cn63xxp1;
-        struct cvmx_sriox_seq_s cn66xx;
-};
-
-union cvmx_sriox_status_reg {
-        uint64_t u64;
-        struct cvmx_sriox_status_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_2_63:62;
-                uint64_t access:1;
-                uint64_t srio:1;
-#else
-                uint64_t srio:1;
-                uint64_t access:1;
-                uint64_t reserved_2_63:62;
-#endif
-        } s;
-        struct cvmx_sriox_status_reg_s cn63xx;
-        struct cvmx_sriox_status_reg_s cn63xxp1;
-        struct cvmx_sriox_status_reg_s cn66xx;
-};
-
-union cvmx_sriox_tag_ctrl {
-        uint64_t u64;
-        struct cvmx_sriox_tag_ctrl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t o_clr:1;
-                uint64_t reserved_13_15:3;
-                uint64_t otag:5;
-                uint64_t reserved_5_7:3;
-                uint64_t itag:5;
-#else
-                uint64_t itag:5;
-                uint64_t reserved_5_7:3;
-                uint64_t otag:5;
-                uint64_t reserved_13_15:3;
-                uint64_t o_clr:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_sriox_tag_ctrl_s cn63xx;
-        struct cvmx_sriox_tag_ctrl_s cn63xxp1;
-        struct cvmx_sriox_tag_ctrl_s cn66xx;
-};
-
-union cvmx_sriox_tlp_credits {
-        uint64_t u64;
-        struct cvmx_sriox_tlp_credits_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_28_63:36;
-                uint64_t mbox:4;
-                uint64_t comp:8;
-                uint64_t reserved_13_15:3;
-                uint64_t n_post:5;
-                uint64_t post:8;
-#else
-                uint64_t post:8;
-                uint64_t n_post:5;
-                uint64_t reserved_13_15:3;
-                uint64_t comp:8;
-                uint64_t mbox:4;
-                uint64_t reserved_28_63:36;
-#endif
-        } s;
-        struct cvmx_sriox_tlp_credits_s cn63xx;
-        struct cvmx_sriox_tlp_credits_s cn63xxp1;
-        struct cvmx_sriox_tlp_credits_s cn66xx;
-};
-
-union cvmx_sriox_tx_bell {
-        uint64_t u64;
-        struct cvmx_sriox_tx_bell_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t data:16;
-                uint64_t dest_id:16;
-                uint64_t reserved_9_15:7;
-                uint64_t pending:1;
-                uint64_t reserved_5_7:3;
-                uint64_t src_id:1;
-                uint64_t id16:1;
-                uint64_t reserved_2_2:1;
-                uint64_t priority:2;
-#else
-                uint64_t priority:2;
-                uint64_t reserved_2_2:1;
-                uint64_t id16:1;
-                uint64_t src_id:1;
-                uint64_t reserved_5_7:3;
-                uint64_t pending:1;
-                uint64_t reserved_9_15:7;
-                uint64_t dest_id:16;
-                uint64_t data:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_sriox_tx_bell_s cn63xx;
-        struct cvmx_sriox_tx_bell_s cn63xxp1;
-        struct cvmx_sriox_tx_bell_s cn66xx;
-};
-
-union cvmx_sriox_tx_bell_info {
-        uint64_t u64;
-        struct cvmx_sriox_tx_bell_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_48_63:16;
-                uint64_t data:16;
-                uint64_t dest_id:16;
-                uint64_t reserved_8_15:8;
-                uint64_t timeout:1;
-                uint64_t error:1;
-                uint64_t retry:1;
-                uint64_t src_id:1;
-                uint64_t id16:1;
-                uint64_t reserved_2_2:1;
-                uint64_t priority:2;
-#else
-                uint64_t priority:2;
-                uint64_t reserved_2_2:1;
-                uint64_t id16:1;
-                uint64_t src_id:1;
-                uint64_t retry:1;
-                uint64_t error:1;
-                uint64_t timeout:1;
-                uint64_t reserved_8_15:8;
-                uint64_t dest_id:16;
-                uint64_t data:16;
-                uint64_t reserved_48_63:16;
-#endif
-        } s;
-        struct cvmx_sriox_tx_bell_info_s cn63xx;
-        struct cvmx_sriox_tx_bell_info_s cn63xxp1;
-        struct cvmx_sriox_tx_bell_info_s cn66xx;
-};
-
-union cvmx_sriox_tx_ctrl {
-        uint64_t u64;
-        struct cvmx_sriox_tx_ctrl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_53_63:11;
-                uint64_t tag_th2:5;
-                uint64_t reserved_45_47:3;
-                uint64_t tag_th1:5;
-                uint64_t reserved_37_39:3;
-                uint64_t tag_th0:5;
-                uint64_t reserved_20_31:12;
-                uint64_t tx_th2:4;
-                uint64_t reserved_12_15:4;
-                uint64_t tx_th1:4;
-                uint64_t reserved_4_7:4;
-                uint64_t tx_th0:4;
-#else
-                uint64_t tx_th0:4;
-                uint64_t reserved_4_7:4;
-                uint64_t tx_th1:4;
-                uint64_t reserved_12_15:4;
-                uint64_t tx_th2:4;
-                uint64_t reserved_20_31:12;
-                uint64_t tag_th0:5;
-                uint64_t reserved_37_39:3;
-                uint64_t tag_th1:5;
-                uint64_t reserved_45_47:3;
-                uint64_t tag_th2:5;
-                uint64_t reserved_53_63:11;
-#endif
-        } s;
-        struct cvmx_sriox_tx_ctrl_s cn63xx;
-        struct cvmx_sriox_tx_ctrl_s cn63xxp1;
-        struct cvmx_sriox_tx_ctrl_s cn66xx;
-};
-
-union cvmx_sriox_tx_emphasis {
-        uint64_t u64;
-        struct cvmx_sriox_tx_emphasis_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t emph:4;
-#else
-                uint64_t emph:4;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_sriox_tx_emphasis_s cn63xx;
-        struct cvmx_sriox_tx_emphasis_s cn66xx;
-};
-
-union cvmx_sriox_tx_status {
-        uint64_t u64;
-        struct cvmx_sriox_tx_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t s2m_pr3:8;
-                uint64_t s2m_pr2:8;
-                uint64_t s2m_pr1:8;
-                uint64_t s2m_pr0:8;
-#else
-                uint64_t s2m_pr0:8;
-                uint64_t s2m_pr1:8;
-                uint64_t s2m_pr2:8;
-                uint64_t s2m_pr3:8;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_tx_status_s cn63xx;
-        struct cvmx_sriox_tx_status_s cn63xxp1;
-        struct cvmx_sriox_tx_status_s cn66xx;
-};
-
-union cvmx_sriox_wr_done_counts {
-        uint64_t u64;
-        struct cvmx_sriox_wr_done_counts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t bad:16;
-                uint64_t good:16;
-#else
-                uint64_t good:16;
-                uint64_t bad:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_sriox_wr_done_counts_s cn63xx;
-        struct cvmx_sriox_wr_done_counts_s cn66xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
deleted file mode 100644
index c98e625cd4e..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_SRXX_DEFS_H__
-#define __CVMX_SRXX_DEFS_H__
-
-#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
-#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
-
-union cvmx_srxx_com_ctl {
-        uint64_t u64;
-        struct cvmx_srxx_com_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t prts:4;
-                uint64_t st_en:1;
-                uint64_t reserved_1_2:2;
-                uint64_t inf_en:1;
-#else
-                uint64_t inf_en:1;
-                uint64_t reserved_1_2:2;
-                uint64_t st_en:1;
-                uint64_t prts:4;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_srxx_com_ctl_s cn38xx;
-        struct cvmx_srxx_com_ctl_s cn38xxp2;
-        struct cvmx_srxx_com_ctl_s cn58xx;
-        struct cvmx_srxx_com_ctl_s cn58xxp1;
-};
-
-union cvmx_srxx_ign_rx_full {
-        uint64_t u64;
-        struct cvmx_srxx_ign_rx_full_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t ignore:16;
-#else
-                uint64_t ignore:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_srxx_ign_rx_full_s cn38xx;
-        struct cvmx_srxx_ign_rx_full_s cn38xxp2;
-        struct cvmx_srxx_ign_rx_full_s cn58xx;
-        struct cvmx_srxx_ign_rx_full_s cn58xxp1;
-};
-
-union cvmx_srxx_spi4_calx {
-        uint64_t u64;
-        struct cvmx_srxx_spi4_calx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t oddpar:1;
-                uint64_t prt3:4;
-                uint64_t prt2:4;
-                uint64_t prt1:4;
-                uint64_t prt0:4;
-#else
-                uint64_t prt0:4;
-                uint64_t prt1:4;
-                uint64_t prt2:4;
-                uint64_t prt3:4;
-                uint64_t oddpar:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_srxx_spi4_calx_s cn38xx;
-        struct cvmx_srxx_spi4_calx_s cn38xxp2;
-        struct cvmx_srxx_spi4_calx_s cn58xx;
-        struct cvmx_srxx_spi4_calx_s cn58xxp1;
-};
-
-union cvmx_srxx_spi4_stat {
-        uint64_t u64;
-        struct cvmx_srxx_spi4_stat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t m:8;
-                uint64_t reserved_7_7:1;
-                uint64_t len:7;
-#else
-                uint64_t len:7;
-                uint64_t reserved_7_7:1;
-                uint64_t m:8;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_srxx_spi4_stat_s cn38xx;
-        struct cvmx_srxx_spi4_stat_s cn38xxp2;
-        struct cvmx_srxx_spi4_stat_s cn58xx;
-        struct cvmx_srxx_spi4_stat_s cn58xxp1;
-};
-
-union cvmx_srxx_sw_tick_ctl {
-        uint64_t u64;
-        struct cvmx_srxx_sw_tick_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_14_63:50;
-                uint64_t eop:1;
-                uint64_t sop:1;
-                uint64_t mod:4;
-                uint64_t opc:4;
-                uint64_t adr:4;
-#else
-                uint64_t adr:4;
-                uint64_t opc:4;
-                uint64_t mod:4;
-                uint64_t sop:1;
-                uint64_t eop:1;
-                uint64_t reserved_14_63:50;
-#endif
-        } s;
-        struct cvmx_srxx_sw_tick_ctl_s cn38xx;
-        struct cvmx_srxx_sw_tick_ctl_s cn58xx;
-        struct cvmx_srxx_sw_tick_ctl_s cn58xxp1;
-};
-
-union cvmx_srxx_sw_tick_dat {
-        uint64_t u64;
-        struct cvmx_srxx_sw_tick_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t dat:64;
-#else
-                uint64_t dat:64;
-#endif
-        } s;
-        struct cvmx_srxx_sw_tick_dat_s cn38xx;
-        struct cvmx_srxx_sw_tick_dat_s cn58xx;
-        struct cvmx_srxx_sw_tick_dat_s cn58xxp1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
deleted file mode 100644
index 146354005d3..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_STXX_DEFS_H__
-#define __CVMX_STXX_DEFS_H__
-
-#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
-#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
-
-union cvmx_stxx_arb_ctl {
-        uint64_t u64;
-        struct cvmx_stxx_arb_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_6_63:58;
-                uint64_t mintrn:1;
-                uint64_t reserved_4_4:1;
-                uint64_t igntpa:1;
-                uint64_t reserved_0_2:3;
-#else
-                uint64_t reserved_0_2:3;
-                uint64_t igntpa:1;
-                uint64_t reserved_4_4:1;
-                uint64_t mintrn:1;
-                uint64_t reserved_6_63:58;
-#endif
-        } s;
-        struct cvmx_stxx_arb_ctl_s cn38xx;
-        struct cvmx_stxx_arb_ctl_s cn38xxp2;
-        struct cvmx_stxx_arb_ctl_s cn58xx;
-        struct cvmx_stxx_arb_ctl_s cn58xxp1;
-};
-
-union cvmx_stxx_bckprs_cnt {
-        uint64_t u64;
-        struct cvmx_stxx_bckprs_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_stxx_bckprs_cnt_s cn38xx;
-        struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
-        struct cvmx_stxx_bckprs_cnt_s cn58xx;
-        struct cvmx_stxx_bckprs_cnt_s cn58xxp1;
-};
-
-union cvmx_stxx_com_ctl {
-        uint64_t u64;
-        struct cvmx_stxx_com_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_4_63:60;
-                uint64_t st_en:1;
-                uint64_t reserved_1_2:2;
-                uint64_t inf_en:1;
-#else
-                uint64_t inf_en:1;
-                uint64_t reserved_1_2:2;
-                uint64_t st_en:1;
-                uint64_t reserved_4_63:60;
-#endif
-        } s;
-        struct cvmx_stxx_com_ctl_s cn38xx;
-        struct cvmx_stxx_com_ctl_s cn38xxp2;
-        struct cvmx_stxx_com_ctl_s cn58xx;
-        struct cvmx_stxx_com_ctl_s cn58xxp1;
-};
-
-union cvmx_stxx_dip_cnt {
-        uint64_t u64;
-        struct cvmx_stxx_dip_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t frmmax:4;
-                uint64_t dipmax:4;
-#else
-                uint64_t dipmax:4;
-                uint64_t frmmax:4;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_stxx_dip_cnt_s cn38xx;
-        struct cvmx_stxx_dip_cnt_s cn38xxp2;
-        struct cvmx_stxx_dip_cnt_s cn58xx;
-        struct cvmx_stxx_dip_cnt_s cn58xxp1;
-};
-
-union cvmx_stxx_ign_cal {
-        uint64_t u64;
-        struct cvmx_stxx_ign_cal_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t igntpa:16;
-#else
-                uint64_t igntpa:16;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_stxx_ign_cal_s cn38xx;
-        struct cvmx_stxx_ign_cal_s cn38xxp2;
-        struct cvmx_stxx_ign_cal_s cn58xx;
-        struct cvmx_stxx_ign_cal_s cn58xxp1;
-};
-
-union cvmx_stxx_int_msk {
-        uint64_t u64;
-        struct cvmx_stxx_int_msk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t frmerr:1;
-                uint64_t unxfrm:1;
-                uint64_t nosync:1;
-                uint64_t diperr:1;
-                uint64_t datovr:1;
-                uint64_t ovrbst:1;
-                uint64_t calpar1:1;
-                uint64_t calpar0:1;
-#else
-                uint64_t calpar0:1;
-                uint64_t calpar1:1;
-                uint64_t ovrbst:1;
-                uint64_t datovr:1;
-                uint64_t diperr:1;
-                uint64_t nosync:1;
-                uint64_t unxfrm:1;
-                uint64_t frmerr:1;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_stxx_int_msk_s cn38xx;
-        struct cvmx_stxx_int_msk_s cn38xxp2;
-        struct cvmx_stxx_int_msk_s cn58xx;
-        struct cvmx_stxx_int_msk_s cn58xxp1;
-};
-
-union cvmx_stxx_int_reg {
-        uint64_t u64;
-        struct cvmx_stxx_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t syncerr:1;
-                uint64_t frmerr:1;
-                uint64_t unxfrm:1;
-                uint64_t nosync:1;
-                uint64_t diperr:1;
-                uint64_t datovr:1;
-                uint64_t ovrbst:1;
-                uint64_t calpar1:1;
-                uint64_t calpar0:1;
-#else
-                uint64_t calpar0:1;
-                uint64_t calpar1:1;
-                uint64_t ovrbst:1;
-                uint64_t datovr:1;
-                uint64_t diperr:1;
-                uint64_t nosync:1;
-                uint64_t unxfrm:1;
-                uint64_t frmerr:1;
-                uint64_t syncerr:1;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_stxx_int_reg_s cn38xx;
-        struct cvmx_stxx_int_reg_s cn38xxp2;
-        struct cvmx_stxx_int_reg_s cn58xx;
-        struct cvmx_stxx_int_reg_s cn58xxp1;
-};
-
-union cvmx_stxx_int_sync {
-        uint64_t u64;
-        struct cvmx_stxx_int_sync_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_8_63:56;
-                uint64_t frmerr:1;
-                uint64_t unxfrm:1;
-                uint64_t nosync:1;
-                uint64_t diperr:1;
-                uint64_t datovr:1;
-                uint64_t ovrbst:1;
-                uint64_t calpar1:1;
-                uint64_t calpar0:1;
-#else
-                uint64_t calpar0:1;
-                uint64_t calpar1:1;
-                uint64_t ovrbst:1;
-                uint64_t datovr:1;
-                uint64_t diperr:1;
-                uint64_t nosync:1;
-                uint64_t unxfrm:1;
-                uint64_t frmerr:1;
-                uint64_t reserved_8_63:56;
-#endif
-        } s;
-        struct cvmx_stxx_int_sync_s cn38xx;
-        struct cvmx_stxx_int_sync_s cn38xxp2;
-        struct cvmx_stxx_int_sync_s cn58xx;
-        struct cvmx_stxx_int_sync_s cn58xxp1;
-};
-
-union cvmx_stxx_min_bst {
-        uint64_t u64;
-        struct cvmx_stxx_min_bst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_9_63:55;
-                uint64_t minb:9;
-#else
-                uint64_t minb:9;
-                uint64_t reserved_9_63:55;
-#endif
-        } s;
-        struct cvmx_stxx_min_bst_s cn38xx;
-        struct cvmx_stxx_min_bst_s cn38xxp2;
-        struct cvmx_stxx_min_bst_s cn58xx;
-        struct cvmx_stxx_min_bst_s cn58xxp1;
-};
-
-union cvmx_stxx_spi4_calx {
-        uint64_t u64;
-        struct cvmx_stxx_spi4_calx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_17_63:47;
-                uint64_t oddpar:1;
-                uint64_t prt3:4;
-                uint64_t prt2:4;
-                uint64_t prt1:4;
-                uint64_t prt0:4;
-#else
-                uint64_t prt0:4;
-                uint64_t prt1:4;
-                uint64_t prt2:4;
-                uint64_t prt3:4;
-                uint64_t oddpar:1;
-                uint64_t reserved_17_63:47;
-#endif
-        } s;
-        struct cvmx_stxx_spi4_calx_s cn38xx;
-        struct cvmx_stxx_spi4_calx_s cn38xxp2;
-        struct cvmx_stxx_spi4_calx_s cn58xx;
-        struct cvmx_stxx_spi4_calx_s cn58xxp1;
-};
-
-union cvmx_stxx_spi4_dat {
-        uint64_t u64;
-        struct cvmx_stxx_spi4_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t alpha:16;
-                uint64_t max_t:16;
-#else
-                uint64_t max_t:16;
-                uint64_t alpha:16;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_stxx_spi4_dat_s cn38xx;
-        struct cvmx_stxx_spi4_dat_s cn38xxp2;
-        struct cvmx_stxx_spi4_dat_s cn58xx;
-        struct cvmx_stxx_spi4_dat_s cn58xxp1;
-};
-
-union cvmx_stxx_spi4_stat {
-        uint64_t u64;
-        struct cvmx_stxx_spi4_stat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_16_63:48;
-                uint64_t m:8;
-                uint64_t reserved_7_7:1;
-                uint64_t len:7;
-#else
-                uint64_t len:7;
-                uint64_t reserved_7_7:1;
-                uint64_t m:8;
-                uint64_t reserved_16_63:48;
-#endif
-        } s;
-        struct cvmx_stxx_spi4_stat_s cn38xx;
-        struct cvmx_stxx_spi4_stat_s cn38xxp2;
-        struct cvmx_stxx_spi4_stat_s cn58xx;
-        struct cvmx_stxx_spi4_stat_s cn58xxp1;
-};
-
-union cvmx_stxx_stat_bytes_hi {
-        uint64_t u64;
-        struct cvmx_stxx_stat_bytes_hi_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_stxx_stat_bytes_hi_s cn38xx;
-        struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
-        struct cvmx_stxx_stat_bytes_hi_s cn58xx;
-        struct cvmx_stxx_stat_bytes_hi_s cn58xxp1;
-};
-
-union cvmx_stxx_stat_bytes_lo {
-        uint64_t u64;
-        struct cvmx_stxx_stat_bytes_lo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_stxx_stat_bytes_lo_s cn38xx;
-        struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
-        struct cvmx_stxx_stat_bytes_lo_s cn58xx;
-        struct cvmx_stxx_stat_bytes_lo_s cn58xxp1;
-};
-
-union cvmx_stxx_stat_ctl {
-        uint64_t u64;
-        struct cvmx_stxx_stat_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_5_63:59;
-                uint64_t clr:1;
-                uint64_t bckprs:4;
-#else
-                uint64_t bckprs:4;
-                uint64_t clr:1;
-                uint64_t reserved_5_63:59;
-#endif
-        } s;
-        struct cvmx_stxx_stat_ctl_s cn38xx;
-        struct cvmx_stxx_stat_ctl_s cn38xxp2;
-        struct cvmx_stxx_stat_ctl_s cn58xx;
-        struct cvmx_stxx_stat_ctl_s cn58xxp1;
-};
-
-union cvmx_stxx_stat_pkt_xmt {
-        uint64_t u64;
-        struct cvmx_stxx_stat_pkt_xmt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-                uint64_t reserved_32_63:32;
-                uint64_t cnt:32;
-#else
-                uint64_t cnt:32;
-                uint64_t reserved_32_63:32;
-#endif
-        } s;
-        struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
-        struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;
-        struct cvmx_stxx_stat_pkt_xmt_s cn58xx;
-        struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
index bc5b80c6bbe..594f1b68cd6 100644
--- a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -25,8 +25,8 @@
  * Contact Cavium Networks for more information
  ***********************license end**************************************/
 
-#ifndef __CVMX_UCTLX_DEFS_H__
-#define __CVMX_UCTLX_DEFS_H__
+#ifndef __CVMX_UCTLX_TYPEDEFS_H__
+#define __CVMX_UCTLX_TYPEDEFS_H__
 
 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
@@ -45,7 +45,6 @@
 union cvmx_uctlx_bist_status {
         uint64_t u64;
         struct cvmx_uctlx_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t data_bis:1;
                 uint64_t desc_bis:1;
@@ -53,29 +52,14 @@ union cvmx_uctlx_bist_status {
                 uint64_t orbm_bis:1;
                 uint64_t wrbm_bis:1;
                 uint64_t ppaf_bis:1;
-#else
-                uint64_t ppaf_bis:1;
-                uint64_t wrbm_bis:1;
-                uint64_t orbm_bis:1;
-                uint64_t erbm_bis:1;
-                uint64_t desc_bis:1;
-                uint64_t data_bis:1;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
-        struct cvmx_uctlx_bist_status_s cn61xx;
-        struct cvmx_uctlx_bist_status_s cn63xx;
-        struct cvmx_uctlx_bist_status_s cn63xxp1;
-        struct cvmx_uctlx_bist_status_s cn66xx;
-        struct cvmx_uctlx_bist_status_s cn68xx;
-        struct cvmx_uctlx_bist_status_s cn68xxp1;
-        struct cvmx_uctlx_bist_status_s cnf71xx;
+        struct cvmx_uctlx_bist_status_s       cn63xx;
+        struct cvmx_uctlx_bist_status_s       cn63xxp1;
 };
 
 union cvmx_uctlx_clk_rst_ctl {
         uint64_t u64;
         struct cvmx_uctlx_clk_rst_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_25_63:39;
                 uint64_t clear_bist:1;
                 uint64_t start_bist:1;
@@ -97,43 +81,14 @@ union cvmx_uctlx_clk_rst_ctl {
                 uint64_t p_por:1;
                 uint64_t p_prst:1;
                 uint64_t hrst:1;
-#else
-                uint64_t hrst:1;
-                uint64_t p_prst:1;
-                uint64_t p_por:1;
-                uint64_t p_com_on:1;
-                uint64_t reserved_4_4:1;
-                uint64_t p_refclk_div:2;
-                uint64_t p_refclk_sel:2;
-                uint64_t h_div:4;
-                uint64_t o_clkdiv_en:1;
-                uint64_t h_clkdiv_en:1;
-                uint64_t h_clkdiv_rst:1;
-                uint64_t h_clkdiv_byp:1;
-                uint64_t o_clkdiv_rst:1;
-                uint64_t app_start_clk:1;
-                uint64_t ohci_susp_lgcy:1;
-                uint64_t ohci_sm:1;
-                uint64_t ohci_clkcktrst:1;
-                uint64_t ehci_sm:1;
-                uint64_t start_bist:1;
-                uint64_t clear_bist:1;
-                uint64_t reserved_25_63:39;
-#endif
         } s;
-        struct cvmx_uctlx_clk_rst_ctl_s cn61xx;
-        struct cvmx_uctlx_clk_rst_ctl_s cn63xx;
-        struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1;
-        struct cvmx_uctlx_clk_rst_ctl_s cn66xx;
-        struct cvmx_uctlx_clk_rst_ctl_s cn68xx;
-        struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1;
-        struct cvmx_uctlx_clk_rst_ctl_s cnf71xx;
+        struct cvmx_uctlx_clk_rst_ctl_s       cn63xx;
+        struct cvmx_uctlx_clk_rst_ctl_s       cn63xxp1;
 };
 
 union cvmx_uctlx_ehci_ctl {
         uint64_t u64;
         struct cvmx_uctlx_ehci_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_20_63:44;
                 uint64_t desc_rbm:1;
                 uint64_t reg_nb:1;
@@ -146,96 +101,45 @@ union cvmx_uctlx_ehci_ctl {
                 uint64_t inv_reg_a2:1;
                 uint64_t ehci_64b_addr_en:1;
                 uint64_t l2c_addr_msb:8;
-#else
-                uint64_t l2c_addr_msb:8;
-                uint64_t ehci_64b_addr_en:1;
-                uint64_t inv_reg_a2:1;
-                uint64_t l2c_desc_emod:2;
-                uint64_t l2c_buff_emod:2;
-                uint64_t l2c_stt:1;
-                uint64_t l2c_0pag:1;
-                uint64_t l2c_bc:1;
-                uint64_t l2c_dc:1;
-                uint64_t reg_nb:1;
-                uint64_t desc_rbm:1;
-                uint64_t reserved_20_63:44;
-#endif
         } s;
-        struct cvmx_uctlx_ehci_ctl_s cn61xx;
-        struct cvmx_uctlx_ehci_ctl_s cn63xx;
-        struct cvmx_uctlx_ehci_ctl_s cn63xxp1;
-        struct cvmx_uctlx_ehci_ctl_s cn66xx;
-        struct cvmx_uctlx_ehci_ctl_s cn68xx;
-        struct cvmx_uctlx_ehci_ctl_s cn68xxp1;
-        struct cvmx_uctlx_ehci_ctl_s cnf71xx;
+        struct cvmx_uctlx_ehci_ctl_s          cn63xx;
+        struct cvmx_uctlx_ehci_ctl_s          cn63xxp1;
 };
 
 union cvmx_uctlx_ehci_fla {
         uint64_t u64;
         struct cvmx_uctlx_ehci_fla_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_6_63:58;
                 uint64_t fla:6;
-#else
-                uint64_t fla:6;
-                uint64_t reserved_6_63:58;
-#endif
         } s;
-        struct cvmx_uctlx_ehci_fla_s cn61xx;
-        struct cvmx_uctlx_ehci_fla_s cn63xx;
-        struct cvmx_uctlx_ehci_fla_s cn63xxp1;
-        struct cvmx_uctlx_ehci_fla_s cn66xx;
-        struct cvmx_uctlx_ehci_fla_s cn68xx;
-        struct cvmx_uctlx_ehci_fla_s cn68xxp1;
-        struct cvmx_uctlx_ehci_fla_s cnf71xx;
+        struct cvmx_uctlx_ehci_fla_s          cn63xx;
+        struct cvmx_uctlx_ehci_fla_s          cn63xxp1;
 };
 
 union cvmx_uctlx_erto_ctl {
         uint64_t u64;
         struct cvmx_uctlx_erto_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t to_val:27;
                 uint64_t reserved_0_4:5;
-#else
-                uint64_t reserved_0_4:5;
-                uint64_t to_val:27;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
-        struct cvmx_uctlx_erto_ctl_s cn61xx;
-        struct cvmx_uctlx_erto_ctl_s cn63xx;
-        struct cvmx_uctlx_erto_ctl_s cn63xxp1;
-        struct cvmx_uctlx_erto_ctl_s cn66xx;
-        struct cvmx_uctlx_erto_ctl_s cn68xx;
-        struct cvmx_uctlx_erto_ctl_s cn68xxp1;
-        struct cvmx_uctlx_erto_ctl_s cnf71xx;
+        struct cvmx_uctlx_erto_ctl_s          cn63xx;
+        struct cvmx_uctlx_erto_ctl_s          cn63xxp1;
 };
 
 union cvmx_uctlx_if_ena {
         uint64_t u64;
         struct cvmx_uctlx_if_ena_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_1_63:63;
                 uint64_t en:1;
-#else
-                uint64_t en:1;
-                uint64_t reserved_1_63:63;
-#endif
         } s;
-        struct cvmx_uctlx_if_ena_s cn61xx;
-        struct cvmx_uctlx_if_ena_s cn63xx;
-        struct cvmx_uctlx_if_ena_s cn63xxp1;
-        struct cvmx_uctlx_if_ena_s cn66xx;
-        struct cvmx_uctlx_if_ena_s cn68xx;
-        struct cvmx_uctlx_if_ena_s cn68xxp1;
-        struct cvmx_uctlx_if_ena_s cnf71xx;
+        struct cvmx_uctlx_if_ena_s            cn63xx;
+        struct cvmx_uctlx_if_ena_s            cn63xxp1;
 };
 
 union cvmx_uctlx_int_ena {
         uint64_t u64;
         struct cvmx_uctlx_int_ena_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t ec_ovf_e:1;
                 uint64_t oc_ovf_e:1;
@@ -245,31 +149,14 @@ union cvmx_uctlx_int_ena {
                 uint64_t or_psh_f:1;
                 uint64_t er_psh_f:1;
                 uint64_t pp_psh_f:1;
-#else
-                uint64_t pp_psh_f:1;
-                uint64_t er_psh_f:1;
-                uint64_t or_psh_f:1;
-                uint64_t cf_psh_f:1;
-                uint64_t wb_psh_f:1;
-                uint64_t wb_pop_e:1;
-                uint64_t oc_ovf_e:1;
-                uint64_t ec_ovf_e:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
-        struct cvmx_uctlx_int_ena_s cn61xx;
-        struct cvmx_uctlx_int_ena_s cn63xx;
-        struct cvmx_uctlx_int_ena_s cn63xxp1;
-        struct cvmx_uctlx_int_ena_s cn66xx;
-        struct cvmx_uctlx_int_ena_s cn68xx;
-        struct cvmx_uctlx_int_ena_s cn68xxp1;
-        struct cvmx_uctlx_int_ena_s cnf71xx;
+        struct cvmx_uctlx_int_ena_s           cn63xx;
+        struct cvmx_uctlx_int_ena_s           cn63xxp1;
 };
 
 union cvmx_uctlx_int_reg {
         uint64_t u64;
         struct cvmx_uctlx_int_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_8_63:56;
                 uint64_t ec_ovf_e:1;
                 uint64_t oc_ovf_e:1;
@@ -279,31 +166,14 @@ union cvmx_uctlx_int_reg {
                 uint64_t or_psh_f:1;
                 uint64_t er_psh_f:1;
                 uint64_t pp_psh_f:1;
-#else
-                uint64_t pp_psh_f:1;
-                uint64_t er_psh_f:1;
-                uint64_t or_psh_f:1;
-                uint64_t cf_psh_f:1;
-                uint64_t wb_psh_f:1;
-                uint64_t wb_pop_e:1;
-                uint64_t oc_ovf_e:1;
-                uint64_t ec_ovf_e:1;
-                uint64_t reserved_8_63:56;
-#endif
         } s;
-        struct cvmx_uctlx_int_reg_s cn61xx;
-        struct cvmx_uctlx_int_reg_s cn63xx;
-        struct cvmx_uctlx_int_reg_s cn63xxp1;
-        struct cvmx_uctlx_int_reg_s cn66xx;
-        struct cvmx_uctlx_int_reg_s cn68xx;
-        struct cvmx_uctlx_int_reg_s cn68xxp1;
-        struct cvmx_uctlx_int_reg_s cnf71xx;
+        struct cvmx_uctlx_int_reg_s           cn63xx;
+        struct cvmx_uctlx_int_reg_s           cn63xxp1;
 };
 
 union cvmx_uctlx_ohci_ctl {
         uint64_t u64;
         struct cvmx_uctlx_ohci_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_19_63:45;
                 uint64_t reg_nb:1;
                 uint64_t l2c_dc:1;
@@ -315,73 +185,35 @@ union cvmx_uctlx_ohci_ctl {
                 uint64_t inv_reg_a2:1;
                 uint64_t reserved_8_8:1;
                 uint64_t l2c_addr_msb:8;
-#else
-                uint64_t l2c_addr_msb:8;
-                uint64_t reserved_8_8:1;
-                uint64_t inv_reg_a2:1;
-                uint64_t l2c_desc_emod:2;
-                uint64_t l2c_buff_emod:2;
-                uint64_t l2c_stt:1;
-                uint64_t l2c_0pag:1;
-                uint64_t l2c_bc:1;
-                uint64_t l2c_dc:1;
-                uint64_t reg_nb:1;
-                uint64_t reserved_19_63:45;
-#endif
         } s;
-        struct cvmx_uctlx_ohci_ctl_s cn61xx;
-        struct cvmx_uctlx_ohci_ctl_s cn63xx;
-        struct cvmx_uctlx_ohci_ctl_s cn63xxp1;
-        struct cvmx_uctlx_ohci_ctl_s cn66xx;
-        struct cvmx_uctlx_ohci_ctl_s cn68xx;
-        struct cvmx_uctlx_ohci_ctl_s cn68xxp1;
-        struct cvmx_uctlx_ohci_ctl_s cnf71xx;
+        struct cvmx_uctlx_ohci_ctl_s          cn63xx;
+        struct cvmx_uctlx_ohci_ctl_s          cn63xxp1;
 };
 
 union cvmx_uctlx_orto_ctl {
         uint64_t u64;
         struct cvmx_uctlx_orto_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_32_63:32;
                 uint64_t to_val:24;
                 uint64_t reserved_0_7:8;
-#else
-                uint64_t reserved_0_7:8;
-                uint64_t to_val:24;
-                uint64_t reserved_32_63:32;
-#endif
         } s;
-        struct cvmx_uctlx_orto_ctl_s cn61xx;
-        struct cvmx_uctlx_orto_ctl_s cn63xx;
-        struct cvmx_uctlx_orto_ctl_s cn63xxp1;
-        struct cvmx_uctlx_orto_ctl_s cn66xx;
-        struct cvmx_uctlx_orto_ctl_s cn68xx;
-        struct cvmx_uctlx_orto_ctl_s cn68xxp1;
-        struct cvmx_uctlx_orto_ctl_s cnf71xx;
+        struct cvmx_uctlx_orto_ctl_s          cn63xx;
+        struct cvmx_uctlx_orto_ctl_s          cn63xxp1;
 };
 
 union cvmx_uctlx_ppaf_wm {
         uint64_t u64;
         struct cvmx_uctlx_ppaf_wm_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_5_63:59;
                 uint64_t wm:5;
-#else
-                uint64_t wm:5;
-                uint64_t reserved_5_63:59;
-#endif
         } s;
-        struct cvmx_uctlx_ppaf_wm_s cn61xx;
-        struct cvmx_uctlx_ppaf_wm_s cn63xx;
-        struct cvmx_uctlx_ppaf_wm_s cn63xxp1;
-        struct cvmx_uctlx_ppaf_wm_s cn66xx;
-        struct cvmx_uctlx_ppaf_wm_s cnf71xx;
+        struct cvmx_uctlx_ppaf_wm_s           cn63xx;
+        struct cvmx_uctlx_ppaf_wm_s           cn63xxp1;
 };
 
 union cvmx_uctlx_uphy_ctl_status {
         uint64_t u64;
         struct cvmx_uctlx_uphy_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_10_63:54;
                 uint64_t bist_done:1;
                 uint64_t bist_err:1;
@@ -393,33 +225,14 @@ union cvmx_uctlx_uphy_ctl_status {
                 uint64_t uphy_bist:1;
                 uint64_t bist_en:1;
                 uint64_t ate_reset:1;
-#else
-                uint64_t ate_reset:1;
-                uint64_t bist_en:1;
-                uint64_t uphy_bist:1;
-                uint64_t vtest_en:1;
-                uint64_t siddq:1;
-                uint64_t lsbist:1;
-                uint64_t fsbist:1;
-                uint64_t hsbist:1;
-                uint64_t bist_err:1;
-                uint64_t bist_done:1;
-                uint64_t reserved_10_63:54;
-#endif
         } s;
-        struct cvmx_uctlx_uphy_ctl_status_s cn61xx;
-        struct cvmx_uctlx_uphy_ctl_status_s cn63xx;
-        struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1;
-        struct cvmx_uctlx_uphy_ctl_status_s cn66xx;
-        struct cvmx_uctlx_uphy_ctl_status_s cn68xx;
-        struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1;
-        struct cvmx_uctlx_uphy_ctl_status_s cnf71xx;
+        struct cvmx_uctlx_uphy_ctl_status_s   cn63xx;
+        struct cvmx_uctlx_uphy_ctl_status_s   cn63xxp1;
 };
 
 union cvmx_uctlx_uphy_portx_ctl_status {
         uint64_t u64;
         struct cvmx_uctlx_uphy_portx_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
                 uint64_t reserved_43_63:21;
                 uint64_t tdata_out:4;
                 uint64_t txbiststuffenh:1;
@@ -440,36 +253,9 @@ union cvmx_uctlx_uphy_portx_ctl_status {
                 uint64_t tdata_sel:1;
                 uint64_t taddr_in:4;
                 uint64_t tdata_in:8;
-#else
-                uint64_t tdata_in:8;
-                uint64_t taddr_in:4;
-                uint64_t tdata_sel:1;
-                uint64_t tclk:1;
-                uint64_t loop_en:1;
-                uint64_t compdistune:3;
-                uint64_t sqrxtune:3;
-                uint64_t txfslstune:4;
-                uint64_t txpreemphasistune:1;
-                uint64_t txrisetune:1;
-                uint64_t txvreftune:4;
-                uint64_t txhsvxtune:2;
-                uint64_t portreset:1;
-                uint64_t vbusvldext:1;
-                uint64_t dppulldown:1;
-                uint64_t dmpulldown:1;
-                uint64_t txbiststuffen:1;
-                uint64_t txbiststuffenh:1;
-                uint64_t tdata_out:4;
-                uint64_t reserved_43_63:21;
-#endif
         } s;
-        struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx;
         struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
         struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
-        struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx;
-        struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx;
-        struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1;
-        struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
deleted file mode 100644
index df762389e27..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-wqe.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- *
- * This header file defines the work queue entry (wqe) data structure.
- * Since this is a commonly used structure that depends on structures
- * from several hardware blocks, those definitions have been placed
- * in this file to create a single point of definition of the wqe
- * format.
- * Data structures are still named according to the block that they
- * relate to.
- *
- */
-
-#ifndef __CVMX_WQE_H__
-#define __CVMX_WQE_H__
-
-#include <asm/octeon/cvmx-packet.h>
-
-
-#define OCT_TAG_TYPE_STRING(x)                                          \
-        (((x) == CVMX_POW_TAG_TYPE_ORDERED) ?  "ORDERED" :              \
-                (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ?  "ATOMIC" :        \
-                        (((x) == CVMX_POW_TAG_TYPE_NULL) ?  "NULL" :    \
-                                "NULL_NULL")))
-
-/**
- * HW decode / err_code in work queue entry
- */
-typedef union {
-        uint64_t u64;
-
-        /* Use this struct if the hardware determines that the packet is IP */
-        struct {
-                /* HW sets this to the number of buffers used by this packet */
-                uint64_t bufs:8;
-                /* HW sets to the number of L2 bytes prior to the IP */
-                uint64_t ip_offset:8;
-                /* set to 1 if we found DSA/VLAN in the L2 */
-                uint64_t vlan_valid:1;
-                /* Set to 1 if the DSA/VLAN tag is stacked */
-                uint64_t vlan_stacked:1;
-                uint64_t unassigned:1;
-                /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
-                uint64_t vlan_cfi:1;
-                /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
-                uint64_t vlan_id:12;
-                /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
-                uint64_t pr:4;
-                uint64_t unassigned2:8;
-                /* the packet needs to be decompressed */
-                uint64_t dec_ipcomp:1;
-                /* the packet is either TCP or UDP */
-                uint64_t tcp_or_udp:1;
-                /* the packet needs to be decrypted (ESP or AH) */
-                uint64_t dec_ipsec:1;
-                /* the packet is IPv6 */
-                uint64_t is_v6:1;
-
-                /*
-                 * (rcv_error, not_IP, IP_exc, is_frag, L4_error,
-                 * software, etc.).
-                 */
-
-                /*
-                 * reserved for software use, hardware will clear on
-                 * packet creation.
-                 */
-                uint64_t software:1;
-                /* exceptional conditions below */
-                /* the receive interface hardware detected an L4 error
-                 * (only applies if !is_frag) (only applies if
-                 * !rcv_error && !not_IP && !IP_exc && !is_frag)
-                 * failure indicated in err_code below, decode:
-                 *
-                 * - 1 = Malformed L4
-                 * - 2 = L4 Checksum Error: the L4 checksum value is
-                 * - 3 = UDP Length Error: The UDP length field would
-                 *       make the UDP data longer than what remains in
-                 *       the IP packet (as defined by the IP header
-                 *       length field).
-                 * - 4 = Bad L4 Port: either the source or destination
-                 *       TCP/UDP port is 0.
-                 * - 8 = TCP FIN Only: the packet is TCP and only the
-                 *       FIN flag set.
-                 * - 9 = TCP No Flags: the packet is TCP and no flags
-                 *       are set.
-                 * - 10 = TCP FIN RST: the packet is TCP and both FIN
-                 *        and RST are set.
-                 * - 11 = TCP SYN URG: the packet is TCP and both SYN
-                 *        and URG are set.
-                 * - 12 = TCP SYN RST: the packet is TCP and both SYN
-                 *        and RST are set.
-                 * - 13 = TCP SYN FIN: the packet is TCP and both SYN
-                 *        and FIN are set.
-                 */
-                uint64_t L4_error:1;
-                /* set if the packet is a fragment */
-                uint64_t is_frag:1;
-                /* the receive interface hardware detected an IP error
-                 * / exception (only applies if !rcv_error && !not_IP)
-                 * failure indicated in err_code below, decode:
-                 *
-                 * - 1 = Not IP: the IP version field is neither 4 nor
-                 *       6.
-                 * - 2 = IPv4 Header Checksum Error: the IPv4 header
-                 *       has a checksum violation.
-                 * - 3 = IP Malformed Header: the packet is not long
-                 *       enough to contain the IP header.
-                 * - 4 = IP Malformed: the packet is not long enough
-                 *       to contain the bytes indicated by the IP
-                 *       header. Pad is allowed.
-                 * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
-                 *       Hop Count field are zero.
-                 * - 6 = IP Options
-                 */
-                uint64_t IP_exc:1;
-                /*
-                 * Set if the hardware determined that the packet is a
-                 * broadcast.
-                 */
-                uint64_t is_bcast:1;
-                /*
-                 * St if the hardware determined that the packet is a
-                 * multi-cast.
-                 */
-                uint64_t is_mcast:1;
-                /*
-                 * Set if the packet may not be IP (must be zero in
-                 * this case).
-                 */
-                uint64_t not_IP:1;
-                /*
-                 * The receive interface hardware detected a receive
-                 * error (must be zero in this case).
-                 */
-                uint64_t rcv_error:1;
-                /* lower err_code = first-level descriptor of the
-                 * work */
-                /* zero for packet submitted by hardware that isn't on
-                 * the slow path */
-                /* type is cvmx_pip_err_t */
-                uint64_t err_code:8;
-        } s;
-
-        /* use this to get at the 16 vlan bits */
-        struct {
-                uint64_t unused1:16;
-                uint64_t vlan:16;
-                uint64_t unused2:32;
-        } svlan;
-
-        /*
-         * use this struct if the hardware could not determine that
-         * the packet is ip.
-         */
-        struct {
-                /*
-                 * HW sets this to the number of buffers used by this
-                 * packet.
-                 */
-                uint64_t bufs:8;
-                uint64_t unused:8;
-                /* set to 1 if we found DSA/VLAN in the L2 */
-                uint64_t vlan_valid:1;
-                /* Set to 1 if the DSA/VLAN tag is stacked */
-                uint64_t vlan_stacked:1;
-                uint64_t unassigned:1;
-                /*
-                 * HW sets to the DSA/VLAN CFI flag (valid when
-                 * vlan_valid)
-                 */
-                uint64_t vlan_cfi:1;
-                /*
-                 * HW sets to the DSA/VLAN_ID field (valid when
-                 * vlan_valid).
-                 */
-                uint64_t vlan_id:12;
-                /*
-                 * Ring Identifier (if PCIe). Requires
-                 * PIP_GBL_CTL[RING_EN]=1
-                 */
-                uint64_t pr:4;
-                uint64_t unassigned2:12;
-                /*
-                 * reserved for software use, hardware will clear on
-                 * packet creation.
-                 */
-                uint64_t software:1;
-                uint64_t unassigned3:1;
-                /*
-                 * set if the hardware determined that the packet is
-                 * rarp.
-                 */
-                uint64_t is_rarp:1;
-                /*
-                 * set if the hardware determined that the packet is
-                 * arp
-                 */
-                uint64_t is_arp:1;
-                /*
-                 * set if the hardware determined that the packet is a
-                 * broadcast.
-                 */
-                uint64_t is_bcast:1;
-                /*
-                 * set if the hardware determined that the packet is a
-                 * multi-cast
-                 */
-                uint64_t is_mcast:1;
-                /*
-                 * set if the packet may not be IP (must be one in
-                 * this case)
-                 */
-                uint64_t not_IP:1;
-                /* The receive interface hardware detected a receive
-                 * error.  Failure indicated in err_code below,
-                 * decode:
-                 *
-                 * - 1 = partial error: a packet was partially
-                 *       received, but internal buffering / bandwidth
-                 *       was not adequate to receive the entire
-                 *       packet.
-                 * - 2 = jabber error: the RGMII packet was too large
-                 *       and is truncated.
-                 * - 3 = overrun error: the RGMII packet is longer
-                 *       than allowed and had an FCS error.
-                 * - 4 = oversize error: the RGMII packet is longer
-                 *       than allowed.
-                 * - 5 = alignment error: the RGMII packet is not an
-                 *       integer number of bytes
-                 *       and had an FCS error (100M and 10M only).
-                 * - 6 = fragment error: the RGMII packet is shorter
-                 *       than allowed and had an FCS error.
-                 * - 7 = GMX FCS error: the RGMII packet had an FCS
-                 *       error.
-                 * - 8 = undersize error: the RGMII packet is shorter
-                 *       than allowed.
-                 * - 9 = extend error: the RGMII packet had an extend
-                 *       error.
-                 * - 10 = length mismatch error: the RGMII packet had
-                 *        a length that did not match the length field
-                 *        in the L2 HDR.
-                 * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
-                 *        packet had one or more data reception errors
-                 *        (RXERR) or the SPI4 packet had one or more
-                 *        DIP4 errors.
-                 * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
-                 *        packet was not large enough to cover the
-                 *        skipped bytes or the SPI4 packet was
-                 *        terminated with an About EOPS.
-                 * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
-                 *        RGMII packet had a studder error (data not
-                 *        repeated - 10/100M only) or the SPI4 packet
-                 *        was sent to an NXA.
-                 * - 16 = FCS error: a SPI4.2 packet had an FCS error.
-                 * - 17 = Skip error: a packet was not large enough to
-                 *        cover the skipped bytes.
-                 * - 18 = L2 header malformed: the packet is not long
-                 *        enough to contain the L2.
-                 */
-
-                uint64_t rcv_error:1;
-                /*
-                 * lower err_code = first-level descriptor of the
-                 * work
-                 */
-                /*
-                 * zero for packet submitted by hardware that isn't on
-                 * the slow path
-                 */
-                /* type is cvmx_pip_err_t (union, so can't use directly */
-                uint64_t err_code:8;
-        } snoip;
-
-} cvmx_pip_wqe_word2;
-
-/**
- * Work queue entry format
- *
- * must be 8-byte aligned
- */
-typedef struct {
-
-    /*****************************************************************
-     * WORD 0
-     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
-     */
-
-    /**
-     * raw chksum result generated by the HW
-     */
-        uint16_t hw_chksum;
-    /**
-     * Field unused by hardware - available for software
-     */
-        uint8_t unused;
-    /**
-     * Next pointer used by hardware for list maintenance.
-     * May be written/read by HW before the work queue
-     *           entry is scheduled to a PP
-     * (Only 36 bits used in Octeon 1)
-     */
-        uint64_t next_ptr:40;
-
-    /*****************************************************************
-     * WORD 1
-     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
-     */
-
-    /**
-     * HW sets to the total number of bytes in the packet
-     */
-        uint64_t len:16;
-    /**
-     * HW sets this to input physical port
-     */
-        uint64_t ipprt:6;
-
-    /**
-     * HW sets this to what it thought the priority of the input packet was
-     */
-        uint64_t qos:3;
-
-    /**
-     * the group that the work queue entry will be scheduled to
-     */
-        uint64_t grp:4;
-    /**
-     * the type of the tag (ORDERED, ATOMIC, NULL)
-     */
-        uint64_t tag_type:3;
-    /**
-     * the synchronization/ordering tag
-     */
-        uint64_t tag:32;
-
-    /**
-     * WORD 2 HW WRITE: the following 64-bits are filled in by
-     *   hardware when a packet arrives This indicates a variety of
-     *   status and error conditions.
-     */
-        cvmx_pip_wqe_word2 word2;
-
-    /**
-     * Pointer to the first segment of the packet.
-     */
-        union cvmx_buf_ptr packet_ptr;
-
-    /**
-     *   HW WRITE: octeon will fill in a programmable amount from the
-     *             packet, up to (at most, but perhaps less) the amount
-     *             needed to fill the work queue entry to 128 bytes
-     *
-     *   If the packet is recognized to be IP, the hardware starts
-     *   (except that the IPv4 header is padded for appropriate
-     *   alignment) writing here where the IP header starts.  If the
-     *   packet is not recognized to be IP, the hardware starts
-     *   writing the beginning of the packet here.
-     */
-        uint8_t packet_data[96];
-
-    /**
-     * If desired, SW can make the work Q entry any length. For the
-     * purposes of discussion here, Assume 128B always, as this is all that
-     * the hardware deals with.
-     *
-     */
-
-} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
-
-#endif /* __CVMX_WQE_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index db58beab6cb..7e1286706d4 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -31,45 +31,24 @@
 #include <linux/kernel.h>
 #include <linux/string.h>
 
-enum cvmx_mips_space {
-        CVMX_MIPS_SPACE_XKSEG = 3LL,
-        CVMX_MIPS_SPACE_XKPHYS = 2LL,
-        CVMX_MIPS_SPACE_XSSEG = 1LL,
-        CVMX_MIPS_SPACE_XUSEG = 0LL
-};
-
-/* These macros for use when using 32 bit pointers. */
-#define CVMX_MIPS32_SPACE_KSEG0 1l
-#define CVMX_ADD_SEG32(segment, add) \
-        (((int32_t)segment << 31) | (int32_t)(add))
-
-#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
-
-/* These macros simplify the process of creating common IO addresses */
-#define CVMX_ADD_SEG(segment, add) \
-        ((((uint64_t)segment) << 62) | (add))
-#ifndef CVMX_ADD_IO_SEG
-#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
-#endif
-
-#include <asm/octeon/cvmx-asm.h>
-#include <asm/octeon/cvmx-packet.h>
-#include <asm/octeon/cvmx-sysinfo.h>
-
-#include <asm/octeon/cvmx-ciu-defs.h>
-#include <asm/octeon/cvmx-gpio-defs.h>
-#include <asm/octeon/cvmx-iob-defs.h>
-#include <asm/octeon/cvmx-ipd-defs.h>
-#include <asm/octeon/cvmx-l2c-defs.h>
-#include <asm/octeon/cvmx-l2d-defs.h>
-#include <asm/octeon/cvmx-l2t-defs.h>
-#include <asm/octeon/cvmx-led-defs.h>
-#include <asm/octeon/cvmx-mio-defs.h>
-#include <asm/octeon/cvmx-pow-defs.h>
-
-#include <asm/octeon/cvmx-bootinfo.h>
-#include <asm/octeon/cvmx-bootmem.h>
-#include <asm/octeon/cvmx-l2c.h>
+#include "cvmx-asm.h"
+#include "cvmx-packet.h"
+#include "cvmx-sysinfo.h"
+
+#include "cvmx-ciu-defs.h"
+#include "cvmx-gpio-defs.h"
+#include "cvmx-iob-defs.h"
+#include "cvmx-ipd-defs.h"
+#include "cvmx-l2c-defs.h"
+#include "cvmx-l2d-defs.h"
+#include "cvmx-l2t-defs.h"
+#include "cvmx-led-defs.h"
+#include "cvmx-mio-defs.h"
+#include "cvmx-pow-defs.h"
+
+#include "cvmx-bootinfo.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-l2c.h"
 
 #ifndef CVMX_ENABLE_DEBUG_PRINTS
 #define CVMX_ENABLE_DEBUG_PRINTS 1
@@ -150,6 +129,27 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit,
         return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
 }
 
+enum cvmx_mips_space {
+        CVMX_MIPS_SPACE_XKSEG = 3LL,
+        CVMX_MIPS_SPACE_XKPHYS = 2LL,
+        CVMX_MIPS_SPACE_XSSEG = 1LL,
+        CVMX_MIPS_SPACE_XUSEG = 0LL
+};
+
+/* These macros for use when using 32 bit pointers. */
+#define CVMX_MIPS32_SPACE_KSEG0 1l
+#define CVMX_ADD_SEG32(segment, add) \
+        (((int32_t)segment << 31) | (int32_t)(add))
+
+#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
+
+/* These macros simplify the process of creating common IO addresses */
+#define CVMX_ADD_SEG(segment, add) \
+        ((((uint64_t)segment) << 62) | (add))
+#ifndef CVMX_ADD_IO_SEG
+#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
+#endif
+
 /**
  * Convert a memory pointer (void*) into a hardware compatible
  * memory address (uint64_t). Octeon hardware widgets don't
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index 8008da2f877..cba6fbed9f4 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -31,14 +31,8 @@
 
 #ifndef __OCTEON_FEATURE_H__
 #define __OCTEON_FEATURE_H__
-#include <asm/octeon/cvmx-mio-defs.h>
-#include <asm/octeon/cvmx-rnm-defs.h>
 
 enum octeon_feature {
-        /* CN68XX uses port kinds for packet interface */
-        OCTEON_FEATURE_PKND,
-        /* CN68XX has different fields in word0 - word2 */
-        OCTEON_FEATURE_CN68XX_WQE,
         /*
          * Octeon models in the CN5XXX family and higher support
          * atomic add instructions to memory (saa/saad).
@@ -48,13 +42,8 @@ enum octeon_feature {
         OCTEON_FEATURE_ZIP,
         /* Does this Octeon support crypto acceleration using COP2? */
         OCTEON_FEATURE_CRYPTO,
-        OCTEON_FEATURE_DORM_CRYPTO,
         /* Does this Octeon support PCI express? */
         OCTEON_FEATURE_PCIE,
-        /* Does this Octeon support SRIOs */
-        OCTEON_FEATURE_SRIO,
-        /*  Does this Octeon support Interlaken */
-        OCTEON_FEATURE_ILK,
         /* Some Octeon models support internal memory for storing
          * cryptographic keys */
         OCTEON_FEATURE_KEY_MEMORY,
@@ -75,15 +64,6 @@ enum octeon_feature {
         /* Octeon MDIO block supports clause 45 transactions for 10
          * Gig support */
         OCTEON_FEATURE_MDIO_CLAUSE_45,
-        /*
-         *  CN52XX and CN56XX used a block named NPEI for PCIe
-         *  access. Newer chips replaced this with SLI+DPI.
-         */
-        OCTEON_FEATURE_NPEI,
-        OCTEON_FEATURE_HFA,
-        OCTEON_FEATURE_DFM,
-        OCTEON_FEATURE_CIU2,
-        OCTEON_MAX_FEATURE
 };
 
 static inline int cvmx_fuse_read(int fuse);
@@ -116,78 +96,30 @@ static inline int octeon_has_feature(enum octeon_feature feature)
                         return !cvmx_fuse_read(121);
 
         case OCTEON_FEATURE_CRYPTO:
-                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
-                        union cvmx_mio_fus_dat2 fus_2;
-                        fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
-                        if (fus_2.s.nocrypto || fus_2.s.nomul) {
-                                return 0;
-                        } else if (!fus_2.s.dorm_crypto) {
-                                return 1;
-                        } else {
-                                union cvmx_rnm_ctl_status st;
-                                st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
-                                return st.s.eer_val;
-                        }
-                } else {
-                        return !cvmx_fuse_read(90);
-                }
-
-        case OCTEON_FEATURE_DORM_CRYPTO:
-                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
-                        union cvmx_mio_fus_dat2 fus_2;
-                        fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
-                        return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
-                } else {
-                        return 0;
-                }
+                return !cvmx_fuse_read(90);
 
         case OCTEON_FEATURE_PCIE:
+        case OCTEON_FEATURE_MGMT_PORT:
+        case OCTEON_FEATURE_RAID:
                 return OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
-
-        case OCTEON_FEATURE_SRIO:
-                return OCTEON_IS_MODEL(OCTEON_CN63XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN66XX);
-
-        case OCTEON_FEATURE_ILK:
-                return (OCTEON_IS_MODEL(OCTEON_CN68XX));
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX);
 
         case OCTEON_FEATURE_KEY_MEMORY:
-                return OCTEON_IS_MODEL(OCTEON_CN38XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN58XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
-
         case OCTEON_FEATURE_LED_CONTROLLER:
                 return OCTEON_IS_MODEL(OCTEON_CN38XX)
                         || OCTEON_IS_MODEL(OCTEON_CN58XX)
                         || OCTEON_IS_MODEL(OCTEON_CN56XX);
-
         case OCTEON_FEATURE_TRA:
                 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
                          || OCTEON_IS_MODEL(OCTEON_CN50XX));
-        case OCTEON_FEATURE_MGMT_PORT:
-                return OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
-
-        case OCTEON_FEATURE_RAID:
-                return OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
-
         case OCTEON_FEATURE_USB:
                 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
                          || OCTEON_IS_MODEL(OCTEON_CN58XX));
-
         case OCTEON_FEATURE_NO_WPTR:
                 return (OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN6XXX))
-                          && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
-                          && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
-
+                         || OCTEON_IS_MODEL(OCTEON_CN52XX))
+                        && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
+                        && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
         case OCTEON_FEATURE_DFA:
                 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
                     && !OCTEON_IS_MODEL(OCTEON_CN31XX)
@@ -195,42 +127,14 @@ static inline int octeon_has_feature(enum octeon_feature feature)
                         return 0;
                 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
                         return 0;
+                else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
+                        return 1;
                 else
                         return !cvmx_fuse_read(120);
-
-        case OCTEON_FEATURE_HFA:
-                if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
-                        return 0;
-                else
-                        return !cvmx_fuse_read(90);
-
-        case OCTEON_FEATURE_DFM:
-                if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
-                      || OCTEON_IS_MODEL(OCTEON_CN66XX)))
-                        return 0;
-                else
-                        return !cvmx_fuse_read(90);
-
         case OCTEON_FEATURE_MDIO_CLAUSE_45:
                 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
                          || OCTEON_IS_MODEL(OCTEON_CN58XX)
                          || OCTEON_IS_MODEL(OCTEON_CN50XX));
-
-        case OCTEON_FEATURE_NPEI:
-                return OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN52XX);
-
-        case OCTEON_FEATURE_PKND:
-                return OCTEON_IS_MODEL(OCTEON_CN68XX);
-
-        case OCTEON_FEATURE_CN68XX_WQE:
-                return OCTEON_IS_MODEL(OCTEON_CN68XX);
-
-        case OCTEON_FEATURE_CIU2:
-                return OCTEON_IS_MODEL(OCTEON_CN68XX);
-
-        default:
-                break;
         }
         return 0;
 }
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 349bb2ba840..700f88e31ca 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2008 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -24,6 +24,14 @@
  * This file may also be available under a different license from Cavium.
  * Contact Cavium Networks for more information
  ***********************license end**************************************/
+
+/*
+ *
+ * File defining different Octeon model IDs and macros to
+ * compare them.
+ *
+ */
+
 #ifndef __OCTEON_MODEL_H__
 #define __OCTEON_MODEL_H__
 
@@ -44,8 +52,6 @@
  * for internal use only, and may change without notice.
  */
 
-#define OCTEON_FAMILY_MASK      0x00ffff00
-
 /* Flag bits in top byte */
 /* Ignores revision in model checks */
 #define OM_IGNORE_REVISION        0x01000000
@@ -57,58 +63,21 @@
 #define OM_IGNORE_MINOR_REVISION  0x08000000
 #define OM_FLAG_MASK              0xff000000
 
-/* Match all cn5XXX Octeon models. */
-#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000
-/* Match all cn6XXX Octeon models. */
-#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000
-/* Match all cnf7XXX Octeon models. */
-#define OM_MATCH_F7XXX_FAMILY_MODELS    0x80000000
-
-/*
- * CNF7XXX models with new revision encoding
- */
-#define OCTEON_CNF71XX_PASS1_0  0x000d9400
-
-#define OCTEON_CNF71XX          (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CNF71XX_PASS1_X  (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000 /* Match all cn5XXX Octeon models. */
+#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000 /* Match all cn6XXX Octeon models. */
 
 /*
  * CN6XXX models with new revision encoding
  */
-#define OCTEON_CN68XX_PASS1_0   0x000d9100
-#define OCTEON_CN68XX_PASS1_1   0x000d9101
-#define OCTEON_CN68XX_PASS1_2   0x000d9102
-#define OCTEON_CN68XX_PASS2_0   0x000d9108
-
-#define OCTEON_CN68XX           (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN68XX_PASS1_X   (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN68XX_PASS2_X   (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
-
-#define OCTEON_CN68XX_PASS1     OCTEON_CN68XX_PASS1_X
-#define OCTEON_CN68XX_PASS2     OCTEON_CN68XX_PASS2_X
-
-#define OCTEON_CN66XX_PASS1_0   0x000d9200
-#define OCTEON_CN66XX_PASS1_2   0x000d9202
-
-#define OCTEON_CN66XX           (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN66XX_PASS1_X   (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-
 #define OCTEON_CN63XX_PASS1_0   0x000d9000
 #define OCTEON_CN63XX_PASS1_1   0x000d9001
 #define OCTEON_CN63XX_PASS1_2   0x000d9002
 #define OCTEON_CN63XX_PASS2_0   0x000d9008
-#define OCTEON_CN63XX_PASS2_1   0x000d9009
-#define OCTEON_CN63XX_PASS2_2   0x000d900a
 
 #define OCTEON_CN63XX           (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
 #define OCTEON_CN63XX_PASS1_X   (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN63XX_PASS2_X   (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 
-#define OCTEON_CN61XX_PASS1_0   0x000d9300
-
-#define OCTEON_CN61XX           (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN61XX_PASS1_X   (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-
 /*
  * CN5XXX models with new revision encoding
  */
@@ -121,8 +90,10 @@
 #define OCTEON_CN58XX_PASS2_3   0x000d030b
 
 #define OCTEON_CN58XX           (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN58XX_PASS1_X   (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN58XX_PASS2_X   (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS1_X   (OCTEON_CN58XX_PASS1_0 \
+                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS2_X   (OCTEON_CN58XX_PASS2_0 \
+                                 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN58XX_PASS1     OCTEON_CN58XX_PASS1_X
 #define OCTEON_CN58XX_PASS2     OCTEON_CN58XX_PASS2_X
 
@@ -132,8 +103,10 @@
 #define OCTEON_CN56XX_PASS2_1   0x000d0409
 
 #define OCTEON_CN56XX           (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN56XX_PASS1_X   (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN56XX_PASS2_X   (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS1_X   (OCTEON_CN56XX_PASS1_0 \
+                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS2_X   (OCTEON_CN56XX_PASS2_0 \
+                                 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN56XX_PASS1     OCTEON_CN56XX_PASS1_X
 #define OCTEON_CN56XX_PASS2     OCTEON_CN56XX_PASS2_X
 
@@ -152,7 +125,8 @@
 #define OCTEON_CN50XX_PASS1_0   0x000d0600
 
 #define OCTEON_CN50XX           (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN50XX_PASS1_X   (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN50XX_PASS1_X   (OCTEON_CN50XX_PASS1_0 \
+                                 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN50XX_PASS1     OCTEON_CN50XX_PASS1_X
 
 /*
@@ -164,8 +138,10 @@
 #define OCTEON_CN52XX_PASS2_0   0x000d0708
 
 #define OCTEON_CN52XX           (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN52XX_PASS1_X   (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN52XX_PASS2_X   (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS1_X   (OCTEON_CN52XX_PASS1_0 \
+                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS2_X   (OCTEON_CN52XX_PASS2_0 \
+                                 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN52XX_PASS1     OCTEON_CN52XX_PASS1_X
 #define OCTEON_CN52XX_PASS2     OCTEON_CN52XX_PASS2_X
 
@@ -198,32 +174,31 @@
 #define OCTEON_CN3005_PASS1     (0x000d0210 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3005_PASS1_0   (0x000d0210 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3005_PASS1_1   (0x000d0212 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3005           (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005           (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \
+                                 | OM_CHECK_SUBMODEL)
 
 #define OCTEON_CN3010_PASS1     (0x000d0200 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3010_PASS1_0   (0x000d0200 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3010_PASS1_1   (0x000d0202 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3010           (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010           (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \
+                                 | OM_CHECK_SUBMODEL)
 
 #define OCTEON_CN3020_PASS1     (0x000d0110 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3020_PASS1_0   (0x000d0110 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3020_PASS1_1   (0x000d0112 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3020           (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020           (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \
+                                 | OM_CHECK_SUBMODEL)
+
+
+
+/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
+#define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 \
+                                 | OM_MATCH_PREVIOUS_MODELS \
+                                 | OM_IGNORE_REVISION)
 
-/*
- * This matches the complete family of CN3xxx CPUs, and not subsequent
- * models
- */
-#define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
 #define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
 #define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
 
-/* These are used to cover entire families of OCTEON processors */
-#define OCTEON_FAM_1            (OCTEON_CN3XXX)
-#define OCTEON_FAM_PLUS         (OCTEON_CN5XXX)
-#define OCTEON_FAM_1_PLUS       (OCTEON_FAM_PLUS | OM_MATCH_PREVIOUS_MODELS)
-#define OCTEON_FAM_2            (OCTEON_CN6XXX)
-
 /* The revision byte (low byte) has two different encodings.
  * CN3XXX:
  *
@@ -246,55 +221,90 @@
 #define OCTEON_38XX_FAMILY_MASK      0x00ffff00
 #define OCTEON_38XX_FAMILY_REV_MASK  0x00ffff0f
 #define OCTEON_38XX_MODEL_MASK       0x00ffff10
-#define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
+#define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK \
+                                      | OCTEON_38XX_MODEL_MASK)
 
 /* CN5XXX and later use different layout of bits in the revision ID field */
 #define OCTEON_58XX_FAMILY_MASK      OCTEON_38XX_FAMILY_MASK
 #define OCTEON_58XX_FAMILY_REV_MASK  0x00ffff3f
 #define OCTEON_58XX_MODEL_MASK       0x00ffffc0
-#define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
-#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
+#define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK \
+                                      | OCTEON_58XX_MODEL_MASK)
+#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
+                                          & 0x00fffff8)
 #define OCTEON_5XXX_MODEL_MASK       0x00ff0fc0
 
+#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
+
+/* NOTE: This is for internal (to this file) use only. */
+static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
+                                              uint32_t chip_model)
+{
+        uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
+
+        if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
+                if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
+                    __OCTEON_MATCH_MASK__(chip_model, arg_model,
+                                          OCTEON_38XX_MODEL_MASK))
+                        return 1;
+                if (((arg_model & OM_FLAG_MASK) == 0) &&
+                    __OCTEON_MATCH_MASK__(chip_model, arg_model,
+                                          OCTEON_38XX_FAMILY_REV_MASK))
+                        return 1;
+                if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
+                    __OCTEON_MATCH_MASK__(chip_model, arg_model,
+                                          OCTEON_38XX_FAMILY_MASK))
+                        return 1;
+                if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
+                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
+                                          OCTEON_38XX_MODEL_REV_MASK))
+                        return 1;
+                if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
+                    ((chip_model & OCTEON_38XX_MODEL_MASK) <
+                            (arg_model & OCTEON_38XX_MODEL_MASK)))
+                        return 1;
+        } else {
+                if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
+                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
+                                          OCTEON_58XX_MODEL_MASK))
+                        return 1;
+                if (((arg_model & OM_FLAG_MASK) == 0) &&
+                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
+                                          OCTEON_58XX_FAMILY_REV_MASK))
+                        return 1;
+                if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
+                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
+                                          OCTEON_58XX_MODEL_MINOR_REV_MASK))
+                        return 1;
+                if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
+                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
+                                          OCTEON_58XX_FAMILY_MASK))
+                        return 1;
+                if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
+                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
+                                          OCTEON_58XX_MODEL_REV_MASK))
+                        return 1;
+
+                if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
+                    ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
+                        return 1;
+
+                if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
+                    ((chip_model) >= OCTEON_CN63XX_PASS1_0))
+                        return 1;
+
+                if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
+                    ((chip_model & OCTEON_58XX_MODEL_MASK) <
+                            (arg_model & OCTEON_58XX_MODEL_MASK)))
+                        return 1;
+        }
+        return 0;
+}
+
 /* forward declarations */
 static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
 static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
 
-#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
-
-/* NOTE: This for internal use only! */
-#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model)              \
-((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0)  && ( \
-                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
-                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
-                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
-                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \
-                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
-                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \
-                ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL)  \
-                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \
-                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
-                        && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
-                )) ||                                                   \
-        (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0)  && ( \
-                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
-                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
-                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
-                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \
-                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \
-                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \
-                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
-                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
-                ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL)  \
-                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
-                ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
-                        && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
-                ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
-                        && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) ||  \
-                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
-                        && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
-                )))
-
 /* NOTE: This for internal use only!!!!! */
 static inline int __octeon_is_model_runtime__(uint32_t model)
 {
@@ -302,25 +312,22 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
 
         /*
          * Check for special case of mismarked 3005 samples. We only
-         * need to check if the sub model isn't being ignored
+         * need to check if the sub model isn't being ignored.
          */
         if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
-                if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
+                if (cpuid == OCTEON_CN3010_PASS1 \
+                    && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
                         cpuid |= 0x10;
         }
         return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
 }
 
 /*
- * The OCTEON_IS_MODEL macro should be used for all Octeon model checking done
- * in a program.
- * This should be kept runtime if at all possible  and must be conditionalized
- * with OCTEON_IS_COMMON_BINARY() if runtime checking support is required.
- *
- * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
- * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
- * I.e.:
- *  #if OCTEON_IS_MODEL(OCTEON_CN56XX)  ->  #if CVMX_COMPILED_FOR(OCTEON_CN56XX)
+ * The OCTEON_IS_MODEL macro should be used for all Octeon model
+ * checking done in a program.  This should be kept runtime if at all
+ * possible.  Any compile time (#if OCTEON_IS_MODEL) usage must be
+ * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking
+ * support is required.
  */
 #define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
 #define OCTEON_IS_COMMON_BINARY() 1
@@ -329,14 +336,6 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
 const char *octeon_model_get_string(uint32_t chip_id);
 const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
 
-/*
- * Return the octeon family, i.e., ProcessorID of the PrID register.
- */
-static inline uint32_t cvmx_get_octeon_family(void)
-{
-        return cvmx_get_proc_id() & OCTEON_FAMILY_MASK;
-}
-
-#include <asm/octeon/octeon-feature.h>
+#include "octeon-feature.h"
 
 #endif /* __OCTEON_MODEL_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 254e9954ed7..f72f768cd3a 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -8,7 +8,7 @@
 #ifndef __ASM_OCTEON_OCTEON_H
 #define __ASM_OCTEON_OCTEON_H
 
-#include <asm/octeon/cvmx.h>
+#include "cvmx.h"
 
 extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
                                                 uint64_t alignment,
@@ -52,7 +52,6 @@ extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
 
 extern void octeon_init_cvmcount(void);
 extern void octeon_setup_delays(void);
-extern void octeon_io_clk_delay(unsigned long);
 
 #define OCTEON_ARGV_MAX_ARGS    64
 #define OCTOEN_SERIAL_LEN       20
@@ -209,6 +208,18 @@ union octeon_cvmemctl {
         } s;
 };
 
+struct octeon_cf_data {
+        unsigned long   base_region_bias;
+        unsigned int    base_region;    /* The chip select region used by CF */
+        int             is16bit;        /* 0 - 8bit, !0 - 16bit */
+        int             dma_engine;     /* -1 for no DMA */
+};
+
+struct octeon_i2c_data {
+        unsigned int    sys_freq;
+        unsigned int    i2c_freq;
+};
+
 extern void octeon_write_lcd(const char *s);
 extern void octeon_check_cpu_bist(void);
 extern int octeon_get_boot_debug_flag(void);
@@ -248,7 +259,4 @@ extern uint64_t octeon_bootloader_entry_addr;
 
 extern void (*octeon_irq_setup_secondary)(void);
 
-typedef void (*octeon_irq_ip4_handler_t)(void);
-void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
-
 #endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index c66734bd338..fba2ba200f5 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -56,8 +56,7 @@ enum octeon_dma_bar_type {
         OCTEON_DMA_BAR_TYPE_INVALID,
         OCTEON_DMA_BAR_TYPE_SMALL,
         OCTEON_DMA_BAR_TYPE_BIG,
-        OCTEON_DMA_BAR_TYPE_PCIE,
-        OCTEON_DMA_BAR_TYPE_PCIE2
+        OCTEON_DMA_BAR_TYPE_PCIE
 };
 
 /*
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index dbaec94046d..e59cd1ac09c 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -31,19 +31,16 @@
 #define PAGE_SHIFT      16
 #endif
 #define PAGE_SIZE       (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK       (~(PAGE_SIZE - 1))
+#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
 
-#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+#ifdef CONFIG_HUGETLB_PAGE
 #define HPAGE_SHIFT     (PAGE_SHIFT + PAGE_SHIFT - 3)
 #define HPAGE_SIZE      (_AC(1,UL) << HPAGE_SHIFT)
 #define HPAGE_MASK      (~(HPAGE_SIZE - 1))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
-#else /* !CONFIG_MIPS_HUGE_TLB_SUPPORT */
-#define HPAGE_SHIFT     ({BUILD_BUG(); 0; })
-#define HPAGE_SIZE      ({BUILD_BUG(); 0; })
-#define HPAGE_MASK      ({BUILD_BUG(); 0; })
-#define HUGETLB_PAGE_ORDER      ({BUILD_BUG(); 0; })
-#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
+#endif /* CONFIG_HUGETLB_PAGE */
+
+#ifndef __ASSEMBLY__
 
 #include <linux/pfn.h>
 #include <asm/io.h>
@@ -137,6 +134,8 @@ typedef struct { unsigned long pgprot; } pgprot_t;
  */
 #define ptep_buddy(x)   ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
 
+#endif /* !__ASSEMBLY__ */
+
 /*
  * __pa()/__va() should be used only during mem init.
  */
@@ -198,10 +197,7 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #endif
 
 #define virt_to_page(kaddr)     pfn_to_page(PFN_DOWN(virt_to_phys(kaddr)))
-
-extern int __virt_addr_valid(const volatile void *kaddr);
-#define virt_addr_valid(kaddr)                                          \
-        __virt_addr_valid((const volatile void *) (kaddr))
+#define virt_addr_valid(kaddr)  pfn_valid(PFN_DOWN(virt_to_phys(kaddr)))
 
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
                                  VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index d69ea743272..576397c6992 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -17,7 +17,6 @@
  */
 
 #include <linux/ioport.h>
-#include <linux/of.h>
 
 /*
  * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
@@ -27,7 +26,6 @@
 struct pci_controller {
         struct pci_controller *next;
         struct pci_bus *bus;
-        struct device_node *of_node;
 
         struct pci_ops *pci_ops;
         struct resource *mem_resource;
@@ -94,7 +92,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 #include <asm/scatterlist.h>
 #include <linux/string.h>
 #include <asm/io.h>
-#include <asm-generic/pci-bridge.h>
 
 struct pci_dev;
 
@@ -115,6 +112,12 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
+extern void pcibios_resource_to_bus(struct pci_dev *dev,
+        struct pci_bus_region *region, struct resource *res);
+
+extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                                    struct pci_bus_region *region);
+
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
@@ -142,10 +145,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 #define arch_setup_msi_irqs arch_setup_msi_irqs
 #endif
 
-extern char * (*pcibios_plat_setup)(char *str);
+extern int pci_probe_only;
 
-/* this function parses memory ranges from a device node */
-extern void pci_load_of_ranges(struct pci_controller *hose,
-                               struct device_node *node);
+extern char * (*pcibios_plat_setup)(char *str);
 
 #endif /* _ASM_PCI_H */
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 5d56bb23034..8a153d2fa62 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -19,7 +19,23 @@
 #include <asm-generic/pgtable-nopmd.h>
 
 /*
- * Basically we have the same two-level (which is the logical three level
+ * - add_wired_entry() add a fixed TLB entry, and move wired register
+ */
+extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
+                               unsigned long entryhi, unsigned long pagemask);
+
+/*
+ * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
+ *      starting at the top and working down. This is for populating the
+ *      TLB before trap_init() puts the TLB miss handler in place. It
+ *      should be used only for entries matching the actual page tables,
+ *      to prevent inconsistencies.
+ */
+extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
+                               unsigned long entryhi, unsigned long pagemask);
+
+
+/* Basically we have the same two-level (which is the logical three level
  * Linux page table layout folded) page tables as the i386.  Some day
  * when we have proper page coloring support we can have a 1% quicker
  * tlb refill handling mechanism, but for now it is a bit slower but
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index c63191055e6..55908fd56b1 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -9,7 +9,6 @@
 #ifndef _ASM_PGTABLE_64_H
 #define _ASM_PGTABLE_64_H
 
-#include <linux/compiler.h>
 #include <linux/linkage.h>
 
 #include <asm/addrspace.h>
@@ -163,6 +162,7 @@ typedef struct { unsigned long pmd; } pmd_t;
 
 
 extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
+extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
 #endif
 
 /*
@@ -173,19 +173,7 @@ static inline int pmd_none(pmd_t pmd)
         return pmd_val(pmd) == (unsigned long) invalid_pte_table;
 }
 
-static inline int pmd_bad(pmd_t pmd)
-{
-#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
-        /* pmd_huge(pmd) but inline */
-        if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
-                return 0;
-#endif
-
-        if (unlikely(pmd_val(pmd) & ~PAGE_MASK))
-                return 1;
-
-        return 0;
-}
+#define pmd_bad(pmd)            (pmd_val(pmd) & ~PAGE_MASK)
 
 static inline int pmd_present(pmd_t pmd)
 {
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index f6a0439a408..e9fe7e97ce4 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -34,72 +34,38 @@
  */
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 
-/*
- * The following bits are directly used by the TLB hardware
- */
-#define _PAGE_R4KBUG            (1 << 0)  /* workaround for r4k bug  */
-#define _PAGE_GLOBAL            (1 << 0)
-#define _PAGE_VALID_SHIFT       1
-#define _PAGE_VALID             (1 << _PAGE_VALID_SHIFT)
-#define _PAGE_SILENT_READ       (1 << 1)  /* synonym                 */
-#define _PAGE_DIRTY_SHIFT       2
-#define _PAGE_DIRTY             (1 << _PAGE_DIRTY_SHIFT)  /* The MIPS dirty bit      */
-#define _PAGE_SILENT_WRITE      (1 << 2)
-#define _CACHE_SHIFT            3
-#define _CACHE_MASK             (7 << 3)
-
-/*
- * The following bits are implemented in software
- *
- * _PAGE_FILE semantics: set:pagecache unset:swap
- */ 
-#define _PAGE_PRESENT_SHIFT     6
-#define _PAGE_PRESENT           (1 << _PAGE_PRESENT_SHIFT)
-#define _PAGE_READ_SHIFT        7
-#define _PAGE_READ              (1 << _PAGE_READ_SHIFT)
-#define _PAGE_WRITE_SHIFT       8
-#define _PAGE_WRITE             (1 << _PAGE_WRITE_SHIFT)
-#define _PAGE_ACCESSED_SHIFT    9
-#define _PAGE_ACCESSED          (1 << _PAGE_ACCESSED_SHIFT)
-#define _PAGE_MODIFIED_SHIFT    10
-#define _PAGE_MODIFIED          (1 << _PAGE_MODIFIED_SHIFT)
-
-#define _PAGE_FILE              (1 << 10)
+#define _PAGE_PRESENT               (1<<6)  /* implemented in software */
+#define _PAGE_READ                  (1<<7)  /* implemented in software */
+#define _PAGE_WRITE                 (1<<8)  /* implemented in software */
+#define _PAGE_ACCESSED              (1<<9)  /* implemented in software */
+#define _PAGE_MODIFIED              (1<<10) /* implemented in software */
+#define _PAGE_FILE                  (1<<10) /* set:pagecache unset:swap */
+
+#define _PAGE_R4KBUG                (1<<0)  /* workaround for r4k bug  */
+#define _PAGE_GLOBAL                (1<<0)
+#define _PAGE_VALID                 (1<<1)
+#define _PAGE_SILENT_READ           (1<<1)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<2)  /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<2)
+#define _CACHE_SHIFT                3
+#define _CACHE_MASK                 (7<<3)
 
 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
-/*
- * The following are implemented by software
- *
- * _PAGE_FILE semantics: set:pagecache unset:swap
- */
-#define _PAGE_PRESENT_SHIFT     0
-#define _PAGE_PRESENT           (1 <<  _PAGE_PRESENT_SHIFT)
-#define _PAGE_READ_SHIFT        1
-#define _PAGE_READ              (1 <<  _PAGE_READ_SHIFT)
-#define _PAGE_WRITE_SHIFT       2
-#define _PAGE_WRITE             (1 <<  _PAGE_WRITE_SHIFT)
-#define _PAGE_ACCESSED_SHIFT    3
-#define _PAGE_ACCESSED          (1 <<  _PAGE_ACCESSED_SHIFT)
-#define _PAGE_MODIFIED_SHIFT    4
-#define _PAGE_MODIFIED          (1 <<  _PAGE_MODIFIED_SHIFT)
-#define _PAGE_FILE_SHIFT        4
-#define _PAGE_FILE              (1 <<  _PAGE_FILE_SHIFT)
-
-/*
- * And these are the hardware TLB bits
- */
-#define _PAGE_GLOBAL_SHIFT      8
-#define _PAGE_GLOBAL            (1 <<  _PAGE_GLOBAL_SHIFT)
-#define _PAGE_VALID_SHIFT       9
-#define _PAGE_VALID             (1 <<  _PAGE_VALID_SHIFT)
-#define _PAGE_SILENT_READ       (1 <<  _PAGE_VALID_SHIFT)       /* synonym  */
-#define _PAGE_DIRTY_SHIFT       10
-#define _PAGE_DIRTY             (1 << _PAGE_DIRTY_SHIFT)
-#define _PAGE_SILENT_WRITE      (1 << _PAGE_DIRTY_SHIFT)
-#define _CACHE_UNCACHED_SHIFT   11
-#define _CACHE_UNCACHED         (1 << _CACHE_UNCACHED_SHIFT)
-#define _CACHE_MASK             (1 << _CACHE_UNCACHED_SHIFT)
+#define _PAGE_PRESENT               (1<<0)  /* implemented in software */
+#define _PAGE_READ                  (1<<1)  /* implemented in software */
+#define _PAGE_WRITE                 (1<<2)  /* implemented in software */
+#define _PAGE_ACCESSED              (1<<3)  /* implemented in software */
+#define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
+#define _PAGE_FILE                  (1<<4)  /* set:pagecache unset:swap */
+
+#define _PAGE_GLOBAL                (1<<8)
+#define _PAGE_VALID                 (1<<9)
+#define _PAGE_SILENT_READ           (1<<9)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<10) /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<10)
+#define _CACHE_UNCACHED             (1<<11)
+#define _CACHE_MASK                 (1<<11)
 
 #else /* 'Normal' r4K case */
 /*
@@ -110,25 +76,25 @@
  * which is more than we need right now.
  */
 
-/*
- * The following bits are implemented in software
- *
- * _PAGE_READ / _PAGE_READ_SHIFT should be unused if cpu_has_rixi.
- * _PAGE_FILE semantics: set:pagecache unset:swap
- */
+/* implemented in software */
 #define _PAGE_PRESENT_SHIFT     (0)
 #define _PAGE_PRESENT           (1 << _PAGE_PRESENT_SHIFT)
-#define _PAGE_READ_SHIFT        (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
-#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; })
+/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */
+#define _PAGE_READ_SHIFT        (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; })
+/* implemented in software */
 #define _PAGE_WRITE_SHIFT       (_PAGE_READ_SHIFT + 1)
 #define _PAGE_WRITE             (1 << _PAGE_WRITE_SHIFT)
+/* implemented in software */
 #define _PAGE_ACCESSED_SHIFT    (_PAGE_WRITE_SHIFT + 1)
 #define _PAGE_ACCESSED          (1 << _PAGE_ACCESSED_SHIFT)
+/* implemented in software */
 #define _PAGE_MODIFIED_SHIFT    (_PAGE_ACCESSED_SHIFT + 1)
 #define _PAGE_MODIFIED          (1 << _PAGE_MODIFIED_SHIFT)
+/* set:pagecache unset:swap */
 #define _PAGE_FILE              (_PAGE_MODIFIED)
 
-#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+#ifdef CONFIG_HUGETLB_PAGE
 /* huge tlb page */
 #define _PAGE_HUGE_SHIFT        (_PAGE_MODIFIED_SHIFT + 1)
 #define _PAGE_HUGE              (1 << _PAGE_HUGE_SHIFT)
@@ -137,22 +103,13 @@
 #define _PAGE_HUGE              ({BUG(); 1; })  /* Dummy value */
 #endif
 
-#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
-/* huge tlb page */
-#define _PAGE_SPLITTING_SHIFT   (_PAGE_HUGE_SHIFT + 1)
-#define _PAGE_SPLITTING         (1 << _PAGE_SPLITTING_SHIFT)
-#else
-#define _PAGE_SPLITTING_SHIFT   (_PAGE_HUGE_SHIFT)
-#define _PAGE_SPLITTING         ({BUG(); 1; })  /* Dummy value */
-#endif
-
 /* Page cannot be executed */
-#define _PAGE_NO_EXEC_SHIFT     (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT)
-#define _PAGE_NO_EXEC           ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; })
+#define _PAGE_NO_EXEC_SHIFT     (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
+#define _PAGE_NO_EXEC           ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
 
 /* Page cannot be read */
-#define _PAGE_NO_READ_SHIFT     (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
-#define _PAGE_NO_READ           ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; })
+#define _PAGE_NO_READ_SHIFT     (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
+#define _PAGE_NO_READ           ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
 
 #define _PAGE_GLOBAL_SHIFT      (_PAGE_NO_READ_SHIFT + 1)
 #define _PAGE_GLOBAL            (1 << _PAGE_GLOBAL_SHIFT)
@@ -198,7 +155,7 @@
  */
 static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 {
-        if (cpu_has_rixi) {
+        if (kernel_uses_smartmips_rixi) {
                 int sa;
 #ifdef CONFIG_32BIT
                 sa = 31 - _PAGE_NO_READ_SHIFT;
@@ -235,6 +192,20 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
+#elif defined(CONFIG_CPU_RM9000)
+
+#define _CACHE_WT                   (0<<_CACHE_SHIFT)
+#define _CACHE_WTWA                 (1<<_CACHE_SHIFT)
+#define _CACHE_UC_B                 (2<<_CACHE_SHIFT)
+#define _CACHE_WB                   (3<<_CACHE_SHIFT)
+#define _CACHE_CWBEA                (4<<_CACHE_SHIFT)
+#define _CACHE_CWB                  (5<<_CACHE_SHIFT)
+#define _CACHE_UCNB                 (6<<_CACHE_SHIFT)
+#define _CACHE_FPC                  (7<<_CACHE_SHIFT)
+
+#define _CACHE_UNCACHED             _CACHE_UC_B
+#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
+
 #else
 
 #define _CACHE_CACHABLE_NO_WA       (0<<_CACHE_SHIFT)  /* R4600 only      */
@@ -249,7 +220,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 
 #endif
 
-#define __READABLE      (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
+#define __READABLE      (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ))
 #define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
 
 #define _PAGE_CHG_MASK  (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index ec50d52cfb7..b2202a68cf0 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -8,7 +8,6 @@
 #ifndef _ASM_PGTABLE_H
 #define _ASM_PGTABLE_H
 
-#include <linux/mmzone.h>
 #ifdef CONFIG_32BIT
 #include <asm/pgtable-32.h>
 #endif
@@ -23,15 +22,15 @@ struct mm_struct;
 struct vm_area_struct;
 
 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
-#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_rixi ? 0 : _PAGE_READ) | \
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
                                  _page_cachable_default)
-#define PAGE_COPY       __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \
-                                 (cpu_has_rixi ?  _PAGE_NO_EXEC : 0) | _page_cachable_default)
-#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
+                                 (kernel_uses_smartmips_rixi ?  _PAGE_NO_EXEC : 0) | _page_cachable_default)
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
                                  _page_cachable_default)
 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
                                  _PAGE_GLOBAL | _page_cachable_default)
-#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
+#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
                                  _page_cachable_default)
 #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
                         __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
@@ -77,7 +76,16 @@ extern unsigned long zero_page_mask;
 
 #define ZERO_PAGE(vaddr) \
         (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
-#define __HAVE_COLOR_ZERO_PAGE
+
+#define is_zero_pfn is_zero_pfn
+static inline int is_zero_pfn(unsigned long pfn)
+{
+        extern unsigned long zero_pfn;
+        unsigned long offset_from_zero_pfn = pfn - zero_pfn;
+        return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
+}
+
+#define my_zero_pfn(addr)       page_to_pfn(ZERO_PAGE(addr))
 
 extern void paging_init(void);
 
@@ -86,12 +94,7 @@ extern void paging_init(void);
  * and a page entry and page directory to the page they refer to.
  */
 #define pmd_phys(pmd)           virt_to_phys((void *)pmd_val(pmd))
-
-#define __pmd_page(pmd)         (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
-#ifndef CONFIG_TRANSPARENT_HUGEPAGE
-#define pmd_page(pmd)           __pmd_page(pmd)
-#endif /* CONFIG_TRANSPARENT_HUGEPAGE  */
-
+#define pmd_page(pmd)           (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
 #define pmd_page_vaddr(pmd)     pmd_val(pmd)
 
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
@@ -104,6 +107,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
         ptep->pte_high = pte.pte_high;
         smp_wmb();
         ptep->pte_low = pte.pte_low;
+        //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
 
         if (pte.pte_low & _PAGE_GLOBAL) {
                 pte_t *buddy = ptep_buddy(ptep);
@@ -295,7 +299,7 @@ static inline pte_t pte_mkdirty(pte_t pte)
 static inline pte_t pte_mkyoung(pte_t pte)
 {
         pte_val(pte) |= _PAGE_ACCESSED;
-        if (cpu_has_rixi) {
+        if (kernel_uses_smartmips_rixi) {
                 if (!(pte_val(pte) & _PAGE_NO_READ))
                         pte_val(pte) |= _PAGE_SILENT_READ;
         } else {
@@ -371,14 +375,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
         __update_cache(vma, address, pte);
 }
 
-static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
-        unsigned long address, pmd_t *pmdp)
-{
-        pte_t pte = *(pte_t *)pmdp;
-
-        __update_tlb(vma, address, pte);
-}
-
 #define kern_addr_valid(addr)   (1)
 
 #ifdef CONFIG_64BIT_PHYS_ADDR
@@ -398,157 +394,6 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 #endif
 
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-
-extern int has_transparent_hugepage(void);
-
-static inline int pmd_trans_huge(pmd_t pmd)
-{
-        return !!(pmd_val(pmd) & _PAGE_HUGE);
-}
-
-static inline pmd_t pmd_mkhuge(pmd_t pmd)
-{
-        pmd_val(pmd) |= _PAGE_HUGE;
-
-        return pmd;
-}
-
-static inline int pmd_trans_splitting(pmd_t pmd)
-{
-        return !!(pmd_val(pmd) & _PAGE_SPLITTING);
-}
-
-static inline pmd_t pmd_mksplitting(pmd_t pmd)
-{
-        pmd_val(pmd) |= _PAGE_SPLITTING;
-
-        return pmd;
-}
-
-extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
-                       pmd_t *pmdp, pmd_t pmd);
-
-#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
-/* Extern to avoid header file madness */
-extern void pmdp_splitting_flush(struct vm_area_struct *vma,
-                                        unsigned long address,
-                                        pmd_t *pmdp);
-
-#define __HAVE_ARCH_PMD_WRITE
-static inline int pmd_write(pmd_t pmd)
-{
-        return !!(pmd_val(pmd) & _PAGE_WRITE);
-}
-
-static inline pmd_t pmd_wrprotect(pmd_t pmd)
-{
-        pmd_val(pmd) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
-        return pmd;
-}
-
-static inline pmd_t pmd_mkwrite(pmd_t pmd)
-{
-        pmd_val(pmd) |= _PAGE_WRITE;
-        if (pmd_val(pmd) & _PAGE_MODIFIED)
-                pmd_val(pmd) |= _PAGE_SILENT_WRITE;
-
-        return pmd;
-}
-
-static inline int pmd_dirty(pmd_t pmd)
-{
-        return !!(pmd_val(pmd) & _PAGE_MODIFIED);
-}
-
-static inline pmd_t pmd_mkclean(pmd_t pmd)
-{
-        pmd_val(pmd) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
-        return pmd;
-}
-
-static inline pmd_t pmd_mkdirty(pmd_t pmd)
-{
-        pmd_val(pmd) |= _PAGE_MODIFIED;
-        if (pmd_val(pmd) & _PAGE_WRITE)
-                pmd_val(pmd) |= _PAGE_SILENT_WRITE;
-
-        return pmd;
-}
-
-static inline int pmd_young(pmd_t pmd)
-{
-        return !!(pmd_val(pmd) & _PAGE_ACCESSED);
-}
-
-static inline pmd_t pmd_mkold(pmd_t pmd)
-{
-        pmd_val(pmd) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
-
-        return pmd;
-}
-
-static inline pmd_t pmd_mkyoung(pmd_t pmd)
-{
-        pmd_val(pmd) |= _PAGE_ACCESSED;
-
-        if (cpu_has_rixi) {
-                if (!(pmd_val(pmd) & _PAGE_NO_READ))
-                        pmd_val(pmd) |= _PAGE_SILENT_READ;
-        } else {
-                if (pmd_val(pmd) & _PAGE_READ)
-                        pmd_val(pmd) |= _PAGE_SILENT_READ;
-        }
-
-        return pmd;
-}
-
-/* Extern to avoid header file madness */
-extern pmd_t mk_pmd(struct page *page, pgprot_t prot);
-
-static inline unsigned long pmd_pfn(pmd_t pmd)
-{
-        return pmd_val(pmd) >> _PFN_SHIFT;
-}
-
-static inline struct page *pmd_page(pmd_t pmd)
-{
-        if (pmd_trans_huge(pmd))
-                return pfn_to_page(pmd_pfn(pmd));
-
-        return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT);
-}
-
-static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
-{
-        pmd_val(pmd) = (pmd_val(pmd) & _PAGE_CHG_MASK) | pgprot_val(newprot);
-        return pmd;
-}
-
-static inline pmd_t pmd_mknotpresent(pmd_t pmd)
-{
-        pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY);
-
-        return pmd;
-}
-
-/*
- * The generic version pmdp_get_and_clear uses a version of pmd_clear() with a
- * different prototype.
- */
-#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
-static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
-                                       unsigned long address, pmd_t *pmdp)
-{
-        pmd_t old = *pmdp;
-
-        pmd_clear(pmdp);
-
-        return old;
-}
-
-#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
-
 #include <asm-generic/pgtable.h>
 
 /*
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h b/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h
index 016fa9446ba..a80801b094b 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h
@@ -10,7 +10,6 @@
 
 #define cpu_has_mips16          1
 #define cpu_has_dsp             1
-/* #define cpu_has_dsp2         ??? - do runtime detection */
 #define cpu_has_mipsmt          1
 #define cpu_has_fpu             0
 
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
index c74eb1657f5..9e2ee429c52 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
@@ -17,6 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR        0
 #define MIPS_CACHE_SYNC_WAR             0
 #define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
 #define ICACHE_REFILLS_WORKAROUND_WAR   0
 #define R10000_LLSC_WAR                 0
 #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index bd98b503f04..c104f1039a6 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -19,6 +19,7 @@
 #include <asm/cpu-info.h>
 #include <asm/mipsregs.h>
 #include <asm/prefetch.h>
+#include <asm/system.h>
 
 /*
  * Return current * instruction pointer ("program counter").
@@ -226,6 +227,8 @@ struct thread_struct {
         unsigned long cp0_badvaddr;     /* Last user fault */
         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
         unsigned long error_code;
+        unsigned long irix_trampoline;  /* Wheee... */
+        unsigned long irix_oldctx;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
     struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
     struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
@@ -295,6 +298,8 @@ struct thread_struct {
         .cp0_badvaddr           = 0,                            \
         .cp0_baduaddr           = 0,                            \
         .error_code             = 0,                            \
+        .irix_trampoline        = 0,                            \
+        .irix_oldctx            = 0,                            \
         /*                                                      \
          * Cavium Octeon specifics (null if not Octeon)         \
          */                                                     \
@@ -306,6 +311,11 @@ struct task_struct;
 /* Free all resources held by a thread. */
 #define release_thread(thread) do { } while(0)
 
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 
 /*
@@ -346,12 +356,6 @@ unsigned long get_wchan(struct task_struct *p);
 #define ARCH_HAS_PREFETCHW
 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
 
-/*
- * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
- * systems.
- */
-#define __ARCH_WANT_UNLOCKED_CTXSW
-
 #endif
 
 #endif /* _ASM_PROCESSOR_H */
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 8808bf548b9..857d9b7858a 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -8,44 +8,21 @@
  * published by the Free Software Foundation.
  *
  */
-#ifndef __ASM_PROM_H
-#define __ASM_PROM_H
+#ifndef __ASM_MIPS_PROM_H
+#define __ASM_MIPS_PROM_H
 
 #ifdef CONFIG_OF
-#include <linux/bug.h>
-#include <linux/io.h>
-#include <linux/types.h>
 #include <asm/bootinfo.h>
 
 extern int early_init_dt_scan_memory_arch(unsigned long node,
         const char *uname, int depth, void *data);
 
-extern void device_tree_init(void);
-
-static inline unsigned long pci_address_to_pio(phys_addr_t address)
-{
-        /*
-         * The ioport address can be directly used by inX() / outX()
-         */
-        BUG_ON(address > IO_SPACE_LIMIT);
-
-        return (unsigned long) address;
-}
-#define pci_address_to_pio pci_address_to_pio
-
-struct boot_param_header;
-
-extern void __dt_setup_arch(struct boot_param_header *bph);
-
-#define dt_setup_arch(sym)                                              \
-({                                                                      \
-        extern struct boot_param_header __dtb_##sym##_begin;            \
-                                                                        \
-        __dt_setup_arch(&__dtb_##sym##_begin);                          \
-})
+extern int reserve_mem_mach(unsigned long addr, unsigned long size);
+extern void free_mem_mach(unsigned long addr, unsigned long size);
 
+extern void device_tree_init(void);
 #else /* CONFIG_OF */
 static inline void device_tree_init(void) { }
 #endif /* CONFIG_OF */
 
-#endif /* __ASM_PROM_H */
+#endif /* _ASM_MIPS_PROM_H */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index a3186f2bb8a..de39b1f343e 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -9,12 +9,115 @@
 #ifndef _ASM_PTRACE_H
 #define _ASM_PTRACE_H
 
+/* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
+#define FPR_BASE        32
+#define PC              64
+#define CAUSE           65
+#define BADVADDR        66
+#define MMHI            67
+#define MMLO            68
+#define FPC_CSR         69
+#define FPC_EIR         70
+#define DSP_BASE        71              /* 3 more hi / lo register pairs */
+#define DSP_CONTROL     77
+#define ACX             78
+
+/*
+ * This struct defines the way the registers are stored on the stack during a
+ * system call/exception. As usual the registers k0/k1 aren't being saved.
+ */
+struct pt_regs {
+#ifdef CONFIG_32BIT
+        /* Pad bytes for argument save space on the stack. */
+        unsigned long pad0[6];
+#endif
+
+        /* Saved main processor registers. */
+        unsigned long regs[32];
+
+        /* Saved special registers. */
+        unsigned long cp0_status;
+        unsigned long hi;
+        unsigned long lo;
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+        unsigned long acx;
+#endif
+        unsigned long cp0_badvaddr;
+        unsigned long cp0_cause;
+        unsigned long cp0_epc;
+#ifdef CONFIG_MIPS_MT_SMTC
+        unsigned long cp0_tcstatus;
+#endif /* CONFIG_MIPS_MT_SMTC */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+        unsigned long long mpl[3];        /* MTM{0,1,2} */
+        unsigned long long mtp[3];        /* MTP{0,1,2} */
+#endif
+} __attribute__ ((aligned (8)));
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS          12
+#define PTRACE_SETREGS          13
+#define PTRACE_GETFPREGS                14
+#define PTRACE_SETFPREGS                15
+/* #define PTRACE_GETFPXREGS            18 */
+/* #define PTRACE_SETFPXREGS            19 */
+
+#define PTRACE_OLDSETOPTIONS    21
+
+#define PTRACE_GET_THREAD_AREA  25
+#define PTRACE_SET_THREAD_AREA  26
+
+/* Calls to trace a 64bit program from a 32bit program.  */
+#define PTRACE_PEEKTEXT_3264    0xc0
+#define PTRACE_PEEKDATA_3264    0xc1
+#define PTRACE_POKETEXT_3264    0xc2
+#define PTRACE_POKEDATA_3264    0xc3
+#define PTRACE_GET_THREAD_AREA_3264     0xc4
+
+/* Read and write watchpoint registers.  */
+enum pt_watch_style {
+        pt_watch_style_mips32,
+        pt_watch_style_mips64
+};
+struct mips32_watch_regs {
+        unsigned int watchlo[8];
+        /* Lower 16 bits of watchhi. */
+        unsigned short watchhi[8];
+        /* Valid mask and I R W bits.
+         * bit 0 -- 1 if W bit is usable.
+         * bit 1 -- 1 if R bit is usable.
+         * bit 2 -- 1 if I bit is usable.
+         * bits 3 - 11 -- Valid watchhi mask bits.
+         */
+        unsigned short watch_masks[8];
+        /* The number of valid watch register pairs.  */
+        unsigned int num_valid;
+} __attribute__((aligned(8)));
+
+struct mips64_watch_regs {
+        unsigned long long watchlo[8];
+        unsigned short watchhi[8];
+        unsigned short watch_masks[8];
+        unsigned int num_valid;
+} __attribute__((aligned(8)));
+
+struct pt_watch_regs {
+        enum pt_watch_style style;
+        union {
+                struct mips32_watch_regs mips32;
+                struct mips64_watch_regs mips64;
+        };
+};
+
+#define PTRACE_GET_WATCH_REGS   0xd0
+#define PTRACE_SET_WATCH_REGS   0xd1
+
+#ifdef __KERNEL__
 
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <linux/types.h>
 #include <asm/isadep.h>
-#include <uapi/asm/ptrace.h>
 
 struct task_struct;
 
@@ -34,27 +137,14 @@ extern int ptrace_set_watch_regs(struct task_struct *child,
  */
 #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
 
-static inline int is_syscall_success(struct pt_regs *regs)
-{
-        return !regs->regs[7];
-}
-
-static inline long regs_return_value(struct pt_regs *regs)
-{
-        if (is_syscall_success(regs))
-                return regs->regs[2];
-        else
-                return -regs->regs[2];
-}
-
+#define regs_return_value(_regs) ((_regs)->regs[2])
 #define instruction_pointer(regs) ((regs)->cp0_epc)
 #define profile_pc(regs) instruction_pointer(regs)
-#define user_stack_pointer(r) ((r)->regs[29])
 
 extern asmlinkage void syscall_trace_enter(struct pt_regs *regs);
 extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
 
-extern void die(const char *, struct pt_regs *) __noreturn;
+extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET;
 
 static inline void die_if_kernel(const char *str, struct pt_regs *regs)
 {
@@ -62,10 +152,6 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs)
                 die(str, regs);
 }
 
-#define current_pt_regs()                                               \
-({                                                                      \
-        unsigned long sp = (unsigned long)__builtin_frame_address(0);   \
-        (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1;      \
-})
+#endif
 
 #endif /* _ASM_PTRACE_H */
diff --git a/arch/mips/include/asm/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h
index afe9e0e03fe..a37d12b3b61 100644
--- a/arch/mips/include/asm/r4k-timer.h
+++ b/arch/mips/include/asm/r4k-timer.h
@@ -12,16 +12,16 @@
 
 #ifdef CONFIG_SYNC_R4K
 
-extern void synchronise_count_master(int cpu);
-extern void synchronise_count_slave(int cpu);
+extern void synchronise_count_master(void);
+extern void synchronise_count_slave(void);
 
 #else
 
-static inline void synchronise_count_master(int cpu)
+static inline void synchronise_count_master(void)
 {
 }
 
-static inline void synchronise_count_slave(int cpu)
+static inline void synchronise_count_slave(void)
 {
 }
 
diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
index 785a5189b37..7c8ecb6b9c4 100644
--- a/arch/mips/include/asm/regdef.h
+++ b/arch/mips/include/asm/regdef.h
@@ -6,8 +6,6 @@
  * Copyright (C) 1985 MIPS Computer Systems, Inc.
  * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
  * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
- * Copyright (C) 2011 Wind River Systems,
- *   written by Ralf Baechle <ralf@linux-mips.org>
  */
 #ifndef _ASM_REGDEF_H
 #define _ASM_REGDEF_H
@@ -32,13 +30,9 @@
 #define t2      $10
 #define t3      $11
 #define t4      $12
-#define ta0     $12
 #define t5      $13
-#define ta1     $13
 #define t6      $14
-#define ta2     $14
 #define t7      $15
-#define ta3     $15
 #define s0      $16     /* callee saved */
 #define s1      $17
 #define s2      $18
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h
index e26589ef36e..50511aac04e 100644
--- a/arch/mips/include/asm/setup.h
+++ b/arch/mips/include/asm/setup.h
@@ -1,19 +1,10 @@
 #ifndef _MIPS_SETUP_H
 #define _MIPS_SETUP_H
 
-#include <uapi/asm/setup.h>
+#define COMMAND_LINE_SIZE       4096
 
+#ifdef  __KERNEL__
 extern void setup_early_printk(void);
-
-extern void set_handler(unsigned long offset, void *addr, unsigned long len);
-extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
-
-typedef void (*vi_handler_t)(void);
-extern void *set_vi_handler(int n, vi_handler_t addr);
-
-extern void *set_except_vector(int n, void *addr);
-extern unsigned long ebase;
-extern void per_cpu_trap_init(bool);
-extern void cpu_cache_init(void);
+#endif /* __KERNEL__ */
 
 #endif /* __SETUP_H */
diff --git a/arch/mips/include/asm/sgiarcs.h b/arch/mips/include/asm/sgiarcs.h
index 3dce7c788b3..14934295143 100644
--- a/arch/mips/include/asm/sgiarcs.h
+++ b/arch/mips/include/asm/sgiarcs.h
@@ -366,7 +366,7 @@ struct linux_smonblock {
  * Macros for calling a 32-bit ARC implementation from 64-bit code
  */
 
-#if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)
+#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32)
 
 #define __arc_clobbers                                                  \
         "$2", "$3" /* ... */, "$8", "$9", "$10", "$11",                         \
@@ -475,10 +475,10 @@ struct linux_smonblock {
         __res;                                                          \
 })
 
-#endif /* defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32) */
+#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */
 
-#if (defined(CONFIG_32BIT) && defined(CONFIG_FW_ARC32)) ||              \
-    (defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC64))
+#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) ||         \
+    (defined(CONFIG_64BIT) && defined(CONFIG_ARC64))
 
 #define ARC_CALL0(dest)                                                 \
 ({      long __res;                                                     \
diff --git a/arch/mips/include/asm/sibyte/bcm1480_int.h b/arch/mips/include/asm/sibyte/bcm1480_int.h
index fffb224d229..6109557c14e 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_int.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_int.h
@@ -34,7 +34,7 @@
 #ifndef _BCM1480_INT_H
 #define _BCM1480_INT_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*  *********************************************************************
     *  Interrupt Mapper Constants
diff --git a/arch/mips/include/asm/sibyte/bcm1480_l2c.h b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
index 725d38cb9d1..fd75817f7ac 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_l2c.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
@@ -33,7 +33,7 @@
 #ifndef _BCM1480_L2C_H
 #define _BCM1480_L2C_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*
  * Format of level 2 cache management address (Table 55)
diff --git a/arch/mips/include/asm/sibyte/bcm1480_mc.h b/arch/mips/include/asm/sibyte/bcm1480_mc.h
index 4307a758e3b..f26a41a82b5 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_mc.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_mc.h
@@ -33,7 +33,7 @@
 #ifndef _BCM1480_MC_H
 #define _BCM1480_MC_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*
  * Memory Channel Configuration Register (Table 81)
diff --git a/arch/mips/include/asm/sibyte/bcm1480_regs.h b/arch/mips/include/asm/sibyte/bcm1480_regs.h
index 84d168ddfeb..b4077bb7261 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_regs.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_regs.h
@@ -32,14 +32,14 @@
 #ifndef _BCM1480_REGS_H
 #define _BCM1480_REGS_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*  *********************************************************************
     *  Pull in the BCM1250's registers since a great deal of the 1480's
     *  functions are the same as the BCM1250.
     ********************************************************************* */
 
-#include <asm/sibyte/sb1250_regs.h>
+#include "sb1250_regs.h"
 
 
 /*  *********************************************************************
diff --git a/arch/mips/include/asm/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h
index 2af3706b964..25ef24cbb92 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_scd.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h
@@ -32,13 +32,13 @@
 #ifndef _BCM1480_SCD_H
 #define _BCM1480_SCD_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*  *********************************************************************
     *  Pull in the BCM1250's SCD since lots of stuff is the same.
     ********************************************************************* */
 
-#include <asm/sibyte/sb1250_scd.h>
+#include "sb1250_scd.h"
 
 /*  *********************************************************************
     *  Some general notes:
diff --git a/arch/mips/include/asm/sibyte/sb1250_dma.h b/arch/mips/include/asm/sibyte/sb1250_dma.h
index 6c44dfb5287..bad56171d74 100644
--- a/arch/mips/include/asm/sibyte/sb1250_dma.h
+++ b/arch/mips/include/asm/sibyte/sb1250_dma.h
@@ -36,7 +36,7 @@
 #define _SB1250_DMA_H
 
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*  *********************************************************************
     *  DMA Registers
diff --git a/arch/mips/include/asm/sibyte/sb1250_genbus.h b/arch/mips/include/asm/sibyte/sb1250_genbus.h
index a96ded17bdc..94e9c7c8e78 100644
--- a/arch/mips/include/asm/sibyte/sb1250_genbus.h
+++ b/arch/mips/include/asm/sibyte/sb1250_genbus.h
@@ -34,7 +34,7 @@
 #ifndef _SB1250_GENBUS_H
 #define _SB1250_GENBUS_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*
  * Generic Bus Region Configuration Registers (Table 11-4)
diff --git a/arch/mips/include/asm/sibyte/sb1250_int.h b/arch/mips/include/asm/sibyte/sb1250_int.h
index dbea73ddd2f..f2850b4bcfd 100644
--- a/arch/mips/include/asm/sibyte/sb1250_int.h
+++ b/arch/mips/include/asm/sibyte/sb1250_int.h
@@ -33,7 +33,7 @@
 #ifndef _SB1250_INT_H
 #define _SB1250_INT_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*  *********************************************************************
     *  Interrupt Mapper Constants
diff --git a/arch/mips/include/asm/sibyte/sb1250_l2c.h b/arch/mips/include/asm/sibyte/sb1250_l2c.h
index b61a7491607..6554dcf05cf 100644
--- a/arch/mips/include/asm/sibyte/sb1250_l2c.h
+++ b/arch/mips/include/asm/sibyte/sb1250_l2c.h
@@ -33,7 +33,7 @@
 #ifndef _SB1250_L2C_H
 #define _SB1250_L2C_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*
  * Level 2 Cache Tag register (Table 5-3)
diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h
index bf7f320d1a8..1e76cf13799 100644
--- a/arch/mips/include/asm/sibyte/sb1250_ldt.h
+++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h
@@ -33,7 +33,7 @@
 #ifndef _SB1250_LDT_H
 #define _SB1250_LDT_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 #define K_LDT_VENDOR_SIBYTE     0x166D
 #define K_LDT_DEVICE_SB1250     0x0002
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
index cfc4d787088..77f78728423 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mac.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -33,7 +33,7 @@
 #ifndef _SB1250_MAC_H
 #define _SB1250_MAC_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*  *********************************************************************
     *  Ethernet MAC Registers
diff --git a/arch/mips/include/asm/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h
index 15048dcaf22..1eb1b5a8873 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mc.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mc.h
@@ -33,7 +33,7 @@
 #ifndef _SB1250_MC_H
 #define _SB1250_MC_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*
  * Memory Channel Config Register (table 6-14)
diff --git a/arch/mips/include/asm/sibyte/sb1250_regs.h b/arch/mips/include/asm/sibyte/sb1250_regs.h
index 29b9f0b26b3..8f53ec817a5 100644
--- a/arch/mips/include/asm/sibyte/sb1250_regs.h
+++ b/arch/mips/include/asm/sibyte/sb1250_regs.h
@@ -33,7 +33,7 @@
 #ifndef _SB1250_REGS_H
 #define _SB1250_REGS_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 
 /*  *********************************************************************
diff --git a/arch/mips/include/asm/sibyte/sb1250_scd.h b/arch/mips/include/asm/sibyte/sb1250_scd.h
index 615e165dbd2..e49c3e89b5e 100644
--- a/arch/mips/include/asm/sibyte/sb1250_scd.h
+++ b/arch/mips/include/asm/sibyte/sb1250_scd.h
@@ -32,7 +32,7 @@
 #ifndef _SB1250_SCD_H
 #define _SB1250_SCD_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*  *********************************************************************
     *  System control/debug registers
diff --git a/arch/mips/include/asm/sibyte/sb1250_smbus.h b/arch/mips/include/asm/sibyte/sb1250_smbus.h
index 128d6b75b81..04769923cf1 100644
--- a/arch/mips/include/asm/sibyte/sb1250_smbus.h
+++ b/arch/mips/include/asm/sibyte/sb1250_smbus.h
@@ -34,7 +34,7 @@
 #ifndef _SB1250_SMBUS_H
 #define _SB1250_SMBUS_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*
  * SMBus Clock Frequency Register (Table 14-2)
diff --git a/arch/mips/include/asm/sibyte/sb1250_syncser.h b/arch/mips/include/asm/sibyte/sb1250_syncser.h
index 274e9179d32..d4b8558e0bf 100644
--- a/arch/mips/include/asm/sibyte/sb1250_syncser.h
+++ b/arch/mips/include/asm/sibyte/sb1250_syncser.h
@@ -33,7 +33,7 @@
 #ifndef _SB1250_SYNCSER_H
 #define _SB1250_SYNCSER_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /*
  * Serial Mode Configuration Register
diff --git a/arch/mips/include/asm/sibyte/sb1250_uart.h b/arch/mips/include/asm/sibyte/sb1250_uart.h
index bb99ecac581..d835bf28014 100644
--- a/arch/mips/include/asm/sibyte/sb1250_uart.h
+++ b/arch/mips/include/asm/sibyte/sb1250_uart.h
@@ -33,7 +33,7 @@
 #ifndef _SB1250_UART_H
 #define _SB1250_UART_H
 
-#include <asm/sibyte/sb1250_defs.h>
+#include "sb1250_defs.h"
 
 /* **********************************************************************
    * DUART Registers
diff --git a/arch/mips/include/asm/sigcontext.h b/arch/mips/include/asm/sigcontext.h
index eeeb0f48c76..9e89cf99d4e 100644
--- a/arch/mips/include/asm/sigcontext.h
+++ b/arch/mips/include/asm/sigcontext.h
@@ -9,10 +9,71 @@
 #ifndef _ASM_SIGCONTEXT_H
 #define _ASM_SIGCONTEXT_H
 
-#include <uapi/asm/sigcontext.h>
+#include <linux/types.h>
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Keep this struct definition in sync with the sigcontext fragment
+ * in arch/mips/tools/offset.c
+ */
+struct sigcontext {
+        unsigned int            sc_regmask;     /* Unused */
+        unsigned int            sc_status;      /* Unused */
+        unsigned long long      sc_pc;
+        unsigned long long      sc_regs[32];
+        unsigned long long      sc_fpregs[32];
+        unsigned int            sc_acx;         /* Was sc_ownedfp */
+        unsigned int            sc_fpc_csr;
+        unsigned int            sc_fpc_eir;     /* Unused */
+        unsigned int            sc_used_math;
+        unsigned int            sc_dsp;         /* dsp status, was sc_ssflags */
+        unsigned long long      sc_mdhi;
+        unsigned long long      sc_mdlo;
+        unsigned long           sc_hi1;         /* Was sc_cause */
+        unsigned long           sc_lo1;         /* Was sc_badvaddr */
+        unsigned long           sc_hi2;         /* Was sc_sigset[4] */
+        unsigned long           sc_lo2;
+        unsigned long           sc_hi3;
+        unsigned long           sc_lo3;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
 
+#include <linux/posix_types.h>
+/*
+ * Keep this struct definition in sync with the sigcontext fragment
+ * in arch/mips/tools/offset.c
+ *
+ * Warning: this structure illdefined with sc_badvaddr being just an unsigned
+ * int so it was changed to unsigned long in 2.6.0-test1.  This may break
+ * binary compatibility - no prisoners.
+ * DSP ASE in 2.6.12-rc4.  Turn sc_mdhi and sc_mdlo into an array of four
+ * entries, add sc_dsp and sc_reserved for padding.  No prisoners.
+ */
+struct sigcontext {
+        __u64   sc_regs[32];
+        __u64   sc_fpregs[32];
+        __u64   sc_mdhi;
+        __u64   sc_hi1;
+        __u64   sc_hi2;
+        __u64   sc_hi3;
+        __u64   sc_mdlo;
+        __u64   sc_lo1;
+        __u64   sc_lo2;
+        __u64   sc_lo3;
+        __u64   sc_pc;
+        __u32   sc_fpc_csr;
+        __u32   sc_used_math;
+        __u32   sc_dsp;
+        __u32   sc_reserved;
+};
+
+#ifdef __KERNEL__
+
 struct sigcontext32 {
         __u32           sc_regmask;     /* Unused */
         __u32           sc_status;      /* Unused */
@@ -33,5 +94,8 @@ struct sigcontext32 {
         __u32           sc_hi3;
         __u32           sc_lo3;
 };
+#endif /* __KERNEL__ */
+
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
 #endif /* _ASM_SIGCONTEXT_H */
diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h
index dd9a762646f..20ebeb875ee 100644
--- a/arch/mips/include/asm/siginfo.h
+++ b/arch/mips/include/asm/siginfo.h
@@ -9,8 +9,108 @@
 #ifndef _ASM_SIGINFO_H
 #define _ASM_SIGINFO_H
 
-#include <uapi/asm/siginfo.h>
 
+#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
+#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ...  */
+
+#define HAVE_ARCH_SIGINFO_T
+
+/*
+ * We duplicate the generic versions - <asm-generic/siginfo.h> is just borked
+ * by design ...
+ */
+#define HAVE_ARCH_COPY_SIGINFO
+struct siginfo;
+
+/*
+ * Careful to keep union _sifields from shifting ...
+ */
+#ifdef CONFIG_32BIT
+#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
+#endif
+#ifdef CONFIG_64BIT
+#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
+#endif
+
+#include <asm-generic/siginfo.h>
+
+typedef struct siginfo {
+        int si_signo;
+        int si_code;
+        int si_errno;
+        int __pad0[SI_MAX_SIZE / sizeof(int) - SI_PAD_SIZE - 3];
+
+        union {
+                int _pad[SI_PAD_SIZE];
+
+                /* kill() */
+                struct {
+                        pid_t _pid;             /* sender's pid */
+                        __ARCH_SI_UID_T _uid;   /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        timer_t _tid;           /* timer id */
+                        int _overrun;           /* overrun count */
+                        char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
+                        sigval_t _sigval;       /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        pid_t _pid;             /* sender's pid */
+                        __ARCH_SI_UID_T _uid;   /* sender's uid */
+                        sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        pid_t _pid;             /* which child */
+                        __ARCH_SI_UID_T _uid;   /* sender's uid */
+                        int _status;            /* exit code */
+                        clock_t _utime;
+                        clock_t _stime;
+                } _sigchld;
+
+                /* IRIX SIGCHLD */
+                struct {
+                        pid_t _pid;             /* which child */
+                        clock_t _utime;
+                        int _status;            /* exit code */
+                        clock_t _stime;
+                } _irix_sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        void __user *_addr; /* faulting insn/memory ref. */
+#ifdef __ARCH_SI_TRAPNO
+                        int _trapno;    /* TRAP # which caused the signal */
+#endif
+                        short _addr_lsb;
+                } _sigfault;
+
+                /* SIGPOLL, SIGXFSZ (To do ...)  */
+                struct {
+                        __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} siginfo_t;
+
+/*
+ * si_code values
+ * Again these have been chosen to be IRIX compatible.
+ */
+#undef SI_ASYNCIO
+#undef SI_TIMER
+#undef SI_MESGQ
+#define SI_ASYNCIO      -2      /* sent by AIO completion */
+#define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */
+#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */
+
+#ifdef __KERNEL__
 
 /*
  * Duplicated here because of <asm-generic/siginfo.h> braindamage ...
@@ -26,4 +126,6 @@ static inline void copy_siginfo(struct siginfo *to, struct siginfo *from)
                 memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld));
 }
 
+#endif
+
 #endif /* _ASM_SIGINFO_H */
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
index cf4a08062d1..c783f364938 100644
--- a/arch/mips/include/asm/signal.h
+++ b/arch/mips/include/asm/signal.h
@@ -9,8 +9,93 @@
 #ifndef _ASM_SIGNAL_H
 #define _ASM_SIGNAL_H
 
-#include <uapi/asm/signal.h>
+#include <linux/types.h>
 
+#define _NSIG           128
+#define _NSIG_BPW       (sizeof(unsigned long) * 8)
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+#define SIGHUP           1      /* Hangup (POSIX).  */
+#define SIGINT           2      /* Interrupt (ANSI).  */
+#define SIGQUIT          3      /* Quit (POSIX).  */
+#define SIGILL           4      /* Illegal instruction (ANSI).  */
+#define SIGTRAP          5      /* Trace trap (POSIX).  */
+#define SIGIOT           6      /* IOT trap (4.2 BSD).  */
+#define SIGABRT          SIGIOT /* Abort (ANSI).  */
+#define SIGEMT           7
+#define SIGFPE           8      /* Floating-point exception (ANSI).  */
+#define SIGKILL          9      /* Kill, unblockable (POSIX).  */
+#define SIGBUS          10      /* BUS error (4.2 BSD).  */
+#define SIGSEGV         11      /* Segmentation violation (ANSI).  */
+#define SIGSYS          12
+#define SIGPIPE         13      /* Broken pipe (POSIX).  */
+#define SIGALRM         14      /* Alarm clock (POSIX).  */
+#define SIGTERM         15      /* Termination (ANSI).  */
+#define SIGUSR1         16      /* User-defined signal 1 (POSIX).  */
+#define SIGUSR2         17      /* User-defined signal 2 (POSIX).  */
+#define SIGCHLD         18      /* Child status has changed (POSIX).  */
+#define SIGCLD          SIGCHLD /* Same as SIGCHLD (System V).  */
+#define SIGPWR          19      /* Power failure restart (System V).  */
+#define SIGWINCH        20      /* Window size change (4.3 BSD, Sun).  */
+#define SIGURG          21      /* Urgent condition on socket (4.2 BSD).  */
+#define SIGIO           22      /* I/O now possible (4.2 BSD).  */
+#define SIGPOLL         SIGIO   /* Pollable event occurred (System V).  */
+#define SIGSTOP         23      /* Stop, unblockable (POSIX).  */
+#define SIGTSTP         24      /* Keyboard stop (POSIX).  */
+#define SIGCONT         25      /* Continue (POSIX).  */
+#define SIGTTIN         26      /* Background read from tty (POSIX).  */
+#define SIGTTOU         27      /* Background write to tty (POSIX).  */
+#define SIGVTALRM       28      /* Virtual alarm clock (4.2 BSD).  */
+#define SIGPROF         29      /* Profiling alarm clock (4.2 BSD).  */
+#define SIGXCPU         30      /* CPU limit exceeded (4.2 BSD).  */
+#define SIGXFSZ         31      /* File size limit exceeded (4.2 BSD).  */
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_ONSTACK      0x08000000
+#define SA_RESETHAND    0x80000000
+#define SA_RESTART      0x10000000
+#define SA_SIGINFO      0x00000008
+#define SA_NODEFER      0x40000000
+#define SA_NOCLDWAIT    0x00010000
+#define SA_NOCLDSTOP    0x00000001
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+#define SA_RESTORER     0x04000000      /* Only for o32 */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK     1
+#define SS_DISABLE     2
+
+#define MINSIGSTKSZ    2048
+#define SIGSTKSZ       8192
+
+#ifdef __KERNEL__
 
 #ifdef CONFIG_TRAD_SIGNALS
 #define sig_uses_siginfo(ka)    ((ka)->sa.sa_flags & SA_SIGINFO)
@@ -18,7 +103,37 @@
 #define sig_uses_siginfo(ka)    (1)
 #endif
 
+#endif /* __KERNEL__ */
+
+#define SIG_BLOCK       1       /* for blocking signals */
+#define SIG_UNBLOCK     2       /* for unblocking signals */
+#define SIG_SETMASK     3       /* for setting the signal mask */
+
+#include <asm-generic/signal-defs.h>
+
+struct sigaction {
+        unsigned int    sa_flags;
+        __sighandler_t  sa_handler;
+        sigset_t        sa_mask;
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+
+/* IRIX compatible stack_t  */
+typedef struct sigaltstack {
+        void __user *ss_sp;
+        size_t ss_size;
+        int ss_flags;
+} stack_t;
+
+#ifdef __KERNEL__
 #include <asm/sigcontext.h>
 #include <asm/siginfo.h>
 
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_SIGNAL_H */
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index f33b5fd6972..d4fb4d852a6 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -40,8 +40,6 @@ extern int __cpu_logical_map[NR_CPUS];
 #define SMP_CALL_FUNCTION       0x2
 /* Octeon - Tell another core to flush its icache */
 #define SMP_ICACHE_FLUSH        0x4
-/* Used by kexec crashdump to save all cpu's state */
-#define SMP_DUMP                0x8
 
 extern volatile cpumask_t cpu_callin_map;
 
@@ -93,8 +91,4 @@ static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
         mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
 }
 
-#if defined(CONFIG_KEXEC)
-extern void (*dump_ipi_function_ptr)(void *);
-void dump_send_ipi(void (*dump_ipi_callback)(void *));
-#endif
 #endif /* __ASM_SMP_H */
diff --git a/arch/mips/include/asm/smtc.h b/arch/mips/include/asm/smtc.h
index 8935426a56a..c9736fc0632 100644
--- a/arch/mips/include/asm/smtc.h
+++ b/arch/mips/include/asm/smtc.h
@@ -33,12 +33,6 @@ typedef long asiduse;
 #endif
 #endif
 
-/*
- * VPE Management information
- */
-
-#define MAX_SMTC_VPES   MAX_SMTC_TLBS   /* FIXME: May not always be true. */
-
 extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
 
 struct mm_struct;
diff --git a/arch/mips/include/asm/socket.h b/arch/mips/include/asm/socket.h
index 4724a563c5b..9de5190f248 100644
--- a/arch/mips/include/asm/socket.h
+++ b/arch/mips/include/asm/socket.h
@@ -9,8 +9,80 @@
 #ifndef _ASM_SOCKET_H
 #define _ASM_SOCKET_H
 
-#include <uapi/asm/socket.h>
+#include <asm/sockios.h>
 
+/*
+ * For setsockopt(2)
+ *
+ * This defines are ABI conformant as far as Linux supports these ...
+ */
+#define SOL_SOCKET      0xffff
+
+#define SO_DEBUG        0x0001  /* Record debugging information.  */
+#define SO_REUSEADDR    0x0004  /* Allow reuse of local addresses.  */
+#define SO_KEEPALIVE    0x0008  /* Keep connections alive and send
+                                   SIGPIPE when they die.  */
+#define SO_DONTROUTE    0x0010  /* Don't do local routing.  */
+#define SO_BROADCAST    0x0020  /* Allow transmission of
+                                   broadcast messages.  */
+#define SO_LINGER       0x0080  /* Block on close of a reliable
+                                   socket to transmit pending data.  */
+#define SO_OOBINLINE 0x0100     /* Receive out-of-band data in-band.  */
+#if 0
+To add: #define SO_REUSEPORT 0x0200     /* Allow local address and port reuse.  */
+#endif
+
+#define SO_TYPE         0x1008  /* Compatible name for SO_STYLE.  */
+#define SO_STYLE        SO_TYPE /* Synonym */
+#define SO_ERROR        0x1007  /* get error status and clear */
+#define SO_SNDBUF       0x1001  /* Send buffer size. */
+#define SO_RCVBUF       0x1002  /* Receive buffer. */
+#define SO_SNDLOWAT     0x1003  /* send low-water mark */
+#define SO_RCVLOWAT     0x1004  /* receive low-water mark */
+#define SO_SNDTIMEO     0x1005  /* send timeout */
+#define SO_RCVTIMEO     0x1006  /* receive timeout */
+#define SO_ACCEPTCONN   0x1009
+#define SO_PROTOCOL     0x1028  /* protocol type */
+#define SO_DOMAIN       0x1029  /* domain/socket family */
+
+/* linux-specific, might as well be the same as on i386 */
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_BSDCOMPAT    14
+
+#define SO_PASSCRED     17
+#define SO_PEERCRED     18
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE         25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_PEERSEC              30
+#define SO_SNDBUFFORCE          31
+#define SO_RCVBUFFORCE          33
+#define SO_PASSSEC              34
+#define SO_TIMESTAMPNS          35
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 36
+
+#define SO_TIMESTAMPING         37
+#define SCM_TIMESTAMPING        SO_TIMESTAMPING
+
+#define SO_RXQ_OVFL             40
+
+#ifdef __KERNEL__
 
 /** sock_type - Socket types
  *
@@ -47,4 +119,6 @@ enum sock_type {
 
 #define ARCH_HAS_SOCKET_TYPES 1
 
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index 65900dab3ad..7165333ad04 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -6,11 +6,7 @@
  * SECTION_SIZE_BITS            2^N: how big each section will be
  * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
  */
-#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && defined(CONFIG_PAGE_SIZE_64KB)
-# define SECTION_SIZE_BITS      29
-#else
-# define SECTION_SIZE_BITS      28
-#endif
+#define SECTION_SIZE_BITS       28
 #define MAX_PHYSMEM_BITS        35
 
 #endif /* CONFIG_SPARSEMEM */
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
deleted file mode 100644
index 4f8ddba8c36..00000000000
--- a/arch/mips/include/asm/switch_to.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
- * Copyright (C) 1996 by Paul M. Antoine
- * Copyright (C) 1999 Silicon Graphics
- * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.
- */
-#ifndef _ASM_SWITCH_TO_H
-#define _ASM_SWITCH_TO_H
-
-#include <asm/cpu-features.h>
-#include <asm/watch.h>
-#include <asm/dsp.h>
-
-struct task_struct;
-
-/*
- * switch_to(n) should switch tasks to task nr n, first
- * checking that n isn't the current task, in which case it does nothing.
- */
-extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu);
-
-extern unsigned int ll_bit;
-extern struct task_struct *ll_task;
-
-#ifdef CONFIG_MIPS_MT_FPAFF
-
-/*
- * Handle the scheduler resume end of FPU affinity management.  We do this
- * inline to try to keep the overhead down. If we have been forced to run on
- * a "CPU" with an FPU because of a previous high level of FP computation,
- * but did not actually use the FPU during the most recent time-slice (CU1
- * isn't set), we undo the restriction on cpus_allowed.
- *
- * We're not calling set_cpus_allowed() here, because we have no need to
- * force prompt migration - we're already switching the current CPU to a
- * different thread.
- */
-
-#define __mips_mt_fpaff_switch_to(prev)                                 \
-do {                                                                    \
-        struct thread_info *__prev_ti = task_thread_info(prev);         \
-                                                                        \
-        if (cpu_has_fpu &&                                              \
-            test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&             \
-            (!(KSTK_STATUS(prev) & ST0_CU1))) {                         \
-                clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);          \
-                prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
-        }                                                               \
-        next->thread.emulated_fp = 0;                                   \
-} while(0)
-
-#else
-#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
-#endif
-
-#define __clear_software_ll_bit()                                       \
-do {                                                                    \
-        if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc)       \
-                ll_bit = 0;                                             \
-} while (0)
-
-#define switch_to(prev, next, last)                                     \
-do {                                                                    \
-        u32 __usedfpu;                                                  \
-        __mips_mt_fpaff_switch_to(prev);                                \
-        if (cpu_has_dsp)                                                \
-                __save_dsp(prev);                                       \
-        __clear_software_ll_bit();                                      \
-        __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU);  \
-        (last) = resume(prev, next, task_thread_info(next), __usedfpu); \
-} while (0)
-
-#define finish_arch_switch(prev)                                        \
-do {                                                                    \
-        if (cpu_has_dsp)                                                \
-                __restore_dsp(current);                                 \
-        if (cpu_has_userlocal)                                          \
-                write_c0_userlocal(current_thread_info()->tp_value);    \
-        __restore_watch();                                              \
-} while (0)
-
-#endif /* _ASM_SWITCH_TO_H */
diff --git a/arch/mips/include/asm/termios.h b/arch/mips/include/asm/termios.h
index 6245b68a69a..8f77f774a2a 100644
--- a/arch/mips/include/asm/termios.h
+++ b/arch/mips/include/asm/termios.h
@@ -9,8 +9,58 @@
 #ifndef _ASM_TERMIOS_H
 #define _ASM_TERMIOS_H
 
-#include <asm/uaccess.h>
-#include <uapi/asm/termios.h>
+#include <linux/errno.h>
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct sgttyb {
+        char    sg_ispeed;
+        char    sg_ospeed;
+        char    sg_erase;
+        char    sg_kill;
+        int     sg_flags;       /* SGI special - int, not short */
+};
+
+struct tchars {
+        char    t_intrc;
+        char    t_quitc;
+        char    t_startc;
+        char    t_stopc;
+        char    t_eofc;
+        char    t_brkc;
+};
+
+struct ltchars {
+        char    t_suspc;        /* stop process signal */
+        char    t_dsuspc;       /* delayed stop process signal */
+        char    t_rprntc;       /* reprint line */
+        char    t_flushc;       /* flush output (toggles) */
+        char    t_werasc;       /* word erase */
+        char    t_lnextc;       /* literal next character */
+};
+
+/* TIOCGSIZE, TIOCSSIZE not defined yet.  Only needed for SunOS source
+   compatibility anyway ... */
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC     8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        char c_line;                    /* line discipline */
+        unsigned char c_cc[NCCS];       /* control characters */
+};
+
+#ifdef __KERNEL__
+#include <linux/module.h>
 
 /*
  *      intr=^C         quit=^\         erase=del       kill=^U
@@ -20,6 +70,25 @@
  *      eof=^D          eol=\0
  */
 #define INIT_C_CC "\003\034\177\025\1\0\0\0\021\023\032\0\022\017\027\026\004\0"
+#endif
+
+/* modem lines */
+#define TIOCM_LE        0x001           /* line enable */
+#define TIOCM_DTR       0x002           /* data terminal ready */
+#define TIOCM_RTS       0x004           /* request to send */
+#define TIOCM_ST        0x010           /* secondary transmit */
+#define TIOCM_SR        0x020           /* secondary receive */
+#define TIOCM_CTS       0x040           /* clear to send */
+#define TIOCM_CAR       0x100           /* carrier detect */
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RNG       0x200           /* ring */
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_DSR       0x400           /* data set ready */
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+#ifdef __KERNEL__
 
 #include <linux/string.h>
 
@@ -102,4 +171,6 @@ static inline int kernel_termios_to_user_termios_1(struct termios __user *u,
         return copy_to_user(u, k, sizeof(struct termios)) ? -EFAULT : 0;
 }
 
+#endif /* defined(__KERNEL__) */
+
 #endif /* _ASM_TERMIOS_H */
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index b2050b9e64b..97f8bf6639e 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -29,11 +29,10 @@ struct thread_info {
         __u32                   cpu;            /* current CPU */
         int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
 
-        mm_segment_t            addr_limit;     /*
-                                                 * thread address space limit:
-                                                 * 0x7fffffff for user-thead
-                                                 * 0xffffffff for kernel-thread
-                                                 */
+        mm_segment_t            addr_limit;     /* thread address space:
+                                                   0-0xBFFFFFFF for user-thead
+                                                   0-0xFFFFFFFF for kernel-thread
+                                                */
         struct restart_block    restart_block;
         struct pt_regs          *regs;
 };
@@ -61,8 +60,6 @@ struct thread_info {
 register struct thread_info *__current_thread_info __asm__("$28");
 #define current_thread_info()  __current_thread_info
 
-#endif /* !__ASSEMBLY__ */
-
 /* thread information allocation */
 #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
 #define THREAD_SIZE_ORDER (1)
@@ -88,6 +85,20 @@ register struct thread_info *__current_thread_info __asm__("$28");
 
 #define STACK_WARN      (THREAD_SIZE / 8)
 
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info_node(tsk, node) \
+                kzalloc_node(THREAD_SIZE, GFP_KERNEL, node)
+#else
+#define alloc_thread_info_node(tsk, node) \
+                kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
+#endif
+
+#define free_thread_info(info) kfree(info)
+
+#endif /* !__ASSEMBLY__ */
+
 #define PREEMPT_ACTIVE          0x10000000
 
 /*
@@ -104,7 +115,9 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define TIF_NOTIFY_RESUME       5       /* callback before returning to user */
 #define TIF_RESTORE_SIGMASK     9       /* restore signal mask in do_signal() */
 #define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
+#define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
+#define TIF_FREEZE              19
 #define TIF_FIXADE              20      /* Fix address errors in software */
 #define TIF_LOGADE              21      /* Log address errors to syslog */
 #define TIF_32BIT_REGS          22      /* also implies 16/32 fprs */
@@ -113,13 +126,22 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define TIF_LOAD_WATCH          25      /* If set, load watch registers */
 #define TIF_SYSCALL_TRACE       31      /* syscall trace active */
 
+#ifdef CONFIG_MIPS32_O32
+#define TIF_32BIT TIF_32BIT_REGS
+#elif defined(CONFIG_MIPS32_N32)
+#define TIF_32BIT _TIF_32BIT_ADDR
+#endif /* CONFIG_MIPS32_O32 */
+
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
 #define _TIF_USEDFPU            (1<<TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_FREEZE             (1<<TIF_FREEZE)
 #define _TIF_FIXADE             (1<<TIF_FIXADE)
 #define _TIF_LOGADE             (1<<TIF_LOGADE)
 #define _TIF_32BIT_REGS         (1<<TIF_32BIT_REGS)
@@ -131,10 +153,10 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define _TIF_WORK_SYSCALL_EXIT  (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
 
 /* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK          \
-        (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
+#define _TIF_WORK_MASK          (0x0000ffef &                           \
+                                        ~(_TIF_SECCOMP | _TIF_SYSCALL_AUDIT))
 /* work to do on any return to u-space */
-#define _TIF_ALLWORK_MASK       (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT)
+#define _TIF_ALLWORK_MASK       (0x8000ffff & ~_TIF_SECCOMP)
 
 #endif /* __KERNEL__ */
 
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 761f2e92119..bc14447e69b 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -50,8 +50,10 @@ extern int (*perf_irq)(void);
 /*
  * Initialize the calling CPU's compare interrupt as clockevent device
  */
+#ifdef CONFIG_CEVT_R4K_LIB
 extern unsigned int __weak get_c0_compare_int(void);
 extern int r4k_clockevent_init(void);
+#endif
 
 static inline int mips_clockevent_init(void)
 {
@@ -69,7 +71,7 @@ static inline int mips_clockevent_init(void)
 /*
  * Initialize the count register as a clocksource
  */
-#ifdef CONFIG_CSRC_R4K
+#ifdef CONFIG_CSRC_R4K_LIB
 extern int init_r4k_clocksource(void);
 #endif
 
diff --git a/arch/mips/include/asm/tlbmisc.h b/arch/mips/include/asm/tlbmisc.h
deleted file mode 100644
index 3a452282cba..00000000000
--- a/arch/mips/include/asm/tlbmisc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __ASM_TLBMISC_H
-#define __ASM_TLBMISC_H
-
-/*
- * - add_wired_entry() add a fixed TLB entry, and move wired register
- */
-extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
-        unsigned long entryhi, unsigned long pagemask);
-
-#endif /* __ASM_TLBMISC_H */
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 420ca06b2f4..90ff2f497c5 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -24,19 +24,5 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 extern void (*board_nmi_handler_setup)(void);
 extern void (*board_ejtag_handler_setup)(void);
 extern void (*board_bind_eic_interrupt)(int irq, int regset);
-extern void (*board_ebase_setup)(void);
-extern void (*board_cache_error_setup)(void);
-
-extern int register_nmi_notifier(struct notifier_block *nb);
-
-#define nmi_notifier(fn, pri)                                           \
-({                                                                      \
-        static struct notifier_block fn##_nb = {                        \
-                .notifier_call = fn,                                    \
-                .priority = pri                                         \
-        };                                                              \
-                                                                        \
-        register_nmi_notifier(&fn##_nb);                                \
-})
 
 #endif /* _ASM_TRAPS_H */
diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h
index 8808d7f82da..a409c446bf1 100644
--- a/arch/mips/include/asm/txx9/jmr3927.h
+++ b/arch/mips/include/asm/txx9/jmr3927.h
@@ -12,6 +12,7 @@
 
 #include <asm/txx9/tx3927.h>
 #include <asm/addrspace.h>
+#include <asm/system.h>
 #include <asm/txx9irq.h>
 
 /* CS */
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index a845aafedee..533812b6188 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -11,12 +11,26 @@
 #ifndef _ASM_TYPES_H
 #define _ASM_TYPES_H
 
+/*
+ * We don't use int-l64.h for the kernel anymore but still use it for
+ * userspace to avoid code changes.
+ */
+#if (_MIPS_SZLONG == 64) && !defined(__KERNEL__)
+# include <asm-generic/int-l64.h>
+#else
 # include <asm-generic/int-ll64.h>
-#include <uapi/asm/types.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
 
 /*
  * These aren't exported outside the kernel to avoid name space clashes
  */
+#ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 
 /*
@@ -30,4 +44,6 @@ typedef unsigned long phys_t;
 
 #endif /* __ASSEMBLY__ */
 
+#endif /* __KERNEL__ */
+
 #endif /* _ASM_TYPES_H */
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 3b92efef56d..653a412c036 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -687,7 +687,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
         __MODULE_JAL(__copy_user)                                       \
         : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
         :                                                               \
-        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
+        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
           DADDI_SCRATCH, "memory");                                     \
         __cu_len_r;                                                     \
 })
@@ -797,7 +797,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
         ".set\treorder"                                                 \
         : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
         :                                                               \
-        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
+        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
           DADDI_SCRATCH, "memory");                                     \
         __cu_len_r;                                                     \
 })
@@ -820,7 +820,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
         ".set\treorder"                                                 \
         : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
         :                                                               \
-        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
+        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
           DADDI_SCRATCH, "memory");                                     \
         __cu_len_r;                                                     \
 })
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 7e0bf17c932..504d40aedfa 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -6,13 +6,12 @@
  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  * Copyright (C) 2005  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2012  MIPS Technologies, Inc.
  */
 
 #include <linux/types.h>
 
 #ifdef CONFIG_EXPORT_UASM
-#include <linux/export.h>
+#include <linux/module.h>
 #define __uasminit
 #define __uasminitdata
 #define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
@@ -63,10 +62,8 @@ void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
 
 Ip_u2u1s3(_addiu);
 Ip_u3u1u2(_addu);
-Ip_u3u1u2(_and);
 Ip_u2u1u3(_andi);
-Ip_u1u2s3(_bbit0);
-Ip_u1u2s3(_bbit1);
+Ip_u3u1u2(_and);
 Ip_u1u2s3(_beq);
 Ip_u1u2s3(_beql);
 Ip_u1s2(_bgez);
@@ -75,56 +72,55 @@ Ip_u1s2(_bltz);
 Ip_u1s2(_bltzl);
 Ip_u1u2s3(_bne);
 Ip_u2s3u1(_cache);
-Ip_u2u1s3(_daddiu);
-Ip_u3u1u2(_daddu);
-Ip_u2u1msbu3(_dins);
-Ip_u2u1msbu3(_dinsm);
 Ip_u1u2u3(_dmfc0);
 Ip_u1u2u3(_dmtc0);
-Ip_u2u1u3(_drotr);
-Ip_u2u1u3(_drotr32);
+Ip_u2u1s3(_daddiu);
+Ip_u3u1u2(_daddu);
 Ip_u2u1u3(_dsll);
 Ip_u2u1u3(_dsll32);
 Ip_u2u1u3(_dsra);
 Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
+Ip_u2u1u3(_drotr);
+Ip_u2u1u3(_drotr32);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
-Ip_u2u1msbu3(_ext);
-Ip_u2u1msbu3(_ins);
 Ip_u1(_j);
 Ip_u1(_jal);
 Ip_u1(_jr);
 Ip_u2s3u1(_ld);
-Ip_u3u1u2(_ldx);
 Ip_u2s3u1(_ll);
 Ip_u2s3u1(_lld);
 Ip_u1s2(_lui);
 Ip_u2s3u1(_lw);
-Ip_u3u1u2(_lwx);
 Ip_u1u2u3(_mfc0);
 Ip_u1u2u3(_mtc0);
-Ip_u3u1u2(_or);
 Ip_u2u1u3(_ori);
+Ip_u3u1u2(_or);
 Ip_u2s3u1(_pref);
 Ip_0(_rfe);
-Ip_u2u1u3(_rotr);
 Ip_u2s3u1(_sc);
 Ip_u2s3u1(_scd);
 Ip_u2s3u1(_sd);
 Ip_u2u1u3(_sll);
 Ip_u2u1u3(_sra);
 Ip_u2u1u3(_srl);
+Ip_u2u1u3(_rotr);
 Ip_u3u1u2(_subu);
 Ip_u2s3u1(_sw);
-Ip_u1(_syscall);
 Ip_0(_tlbp);
 Ip_0(_tlbr);
 Ip_0(_tlbwi);
 Ip_0(_tlbwr);
 Ip_u3u1u2(_xor);
 Ip_u2u1u3(_xori);
-
+Ip_u2u1msbu3(_dins);
+Ip_u2u1msbu3(_dinsm);
+Ip_u1(_syscall);
+Ip_u1u2s3(_bbit0);
+Ip_u1u2s3(_bbit1);
+Ip_u3u1u2(_lwx);
+Ip_u3u1u2(_ldx);
 
 /* Handle labels. */
 struct uasm_label {
@@ -149,37 +145,37 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
 
 /* convenience macros for instructions */
 #ifdef CONFIG_64BIT
-# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
-# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
-# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
 # define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off)
-# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
-# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
-# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
-# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
-# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
+# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
 # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)
 # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)
 # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)
 # define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_dsrl_safe(buf, rs, rt, sh)
+# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
+# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
+# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
+# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
+# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
 # define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)
-# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
+# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
+# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
+# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
 #else
-# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
-# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
-# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
 # define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)
-# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
-# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
-# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
-# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
-# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
+# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
 # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)
 # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)
 # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
 # define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
+# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
+# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
+# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
+# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
+# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
 # define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)
-# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
+# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
+# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
+# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
 #endif
 
 #define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)
@@ -187,10 +183,19 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
 #define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off)
 #define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off)
 #define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)
-#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
 #define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)
 #define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)
 #define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)
+#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
+
+static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
+                                    unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_dsrl(p, a1, a2, a3);
+        else
+                uasm_i_dsrl32(p, a1, a2, a3 - 32);
+}
 
 static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
                                      unsigned int a2, unsigned int a3)
@@ -210,15 +215,6 @@ static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
                 uasm_i_dsll32(p, a1, a2, a3 - 32);
 }
 
-static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
-                                    unsigned int a2, unsigned int a3)
-{
-        if (a3 < 32)
-                uasm_i_dsrl(p, a1, a2, a3);
-        else
-                uasm_i_dsrl32(p, a1, a2, a3 - 32);
-}
-
 /* Handle relocations. */
 struct uasm_reloc {
         u32 *addr;
@@ -238,16 +234,16 @@ void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
 int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
 
 /* Convenience functions for labeled branches. */
+void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
-void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
-                   unsigned int bit, int lid);
-void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
-                   unsigned int bit, int lid);
 void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
                  unsigned int reg2, int lid);
 void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
+void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 9e47cc11aa2..ecea7871dec 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -12,12 +12,1023 @@
 #ifndef _ASM_UNISTD_H
 #define _ASM_UNISTD_H
 
-#include <uapi/asm/unistd.h>
+#include <asm/sgidefs.h>
 
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Linux o32 style syscalls are in the range from 4000 to 4999.
+ */
+#define __NR_Linux                      4000
+#define __NR_syscall                    (__NR_Linux +   0)
+#define __NR_exit                       (__NR_Linux +   1)
+#define __NR_fork                       (__NR_Linux +   2)
+#define __NR_read                       (__NR_Linux +   3)
+#define __NR_write                      (__NR_Linux +   4)
+#define __NR_open                       (__NR_Linux +   5)
+#define __NR_close                      (__NR_Linux +   6)
+#define __NR_waitpid                    (__NR_Linux +   7)
+#define __NR_creat                      (__NR_Linux +   8)
+#define __NR_link                       (__NR_Linux +   9)
+#define __NR_unlink                     (__NR_Linux +  10)
+#define __NR_execve                     (__NR_Linux +  11)
+#define __NR_chdir                      (__NR_Linux +  12)
+#define __NR_time                       (__NR_Linux +  13)
+#define __NR_mknod                      (__NR_Linux +  14)
+#define __NR_chmod                      (__NR_Linux +  15)
+#define __NR_lchown                     (__NR_Linux +  16)
+#define __NR_break                      (__NR_Linux +  17)
+#define __NR_unused18                   (__NR_Linux +  18)
+#define __NR_lseek                      (__NR_Linux +  19)
+#define __NR_getpid                     (__NR_Linux +  20)
+#define __NR_mount                      (__NR_Linux +  21)
+#define __NR_umount                     (__NR_Linux +  22)
+#define __NR_setuid                     (__NR_Linux +  23)
+#define __NR_getuid                     (__NR_Linux +  24)
+#define __NR_stime                      (__NR_Linux +  25)
+#define __NR_ptrace                     (__NR_Linux +  26)
+#define __NR_alarm                      (__NR_Linux +  27)
+#define __NR_unused28                   (__NR_Linux +  28)
+#define __NR_pause                      (__NR_Linux +  29)
+#define __NR_utime                      (__NR_Linux +  30)
+#define __NR_stty                       (__NR_Linux +  31)
+#define __NR_gtty                       (__NR_Linux +  32)
+#define __NR_access                     (__NR_Linux +  33)
+#define __NR_nice                       (__NR_Linux +  34)
+#define __NR_ftime                      (__NR_Linux +  35)
+#define __NR_sync                       (__NR_Linux +  36)
+#define __NR_kill                       (__NR_Linux +  37)
+#define __NR_rename                     (__NR_Linux +  38)
+#define __NR_mkdir                      (__NR_Linux +  39)
+#define __NR_rmdir                      (__NR_Linux +  40)
+#define __NR_dup                        (__NR_Linux +  41)
+#define __NR_pipe                       (__NR_Linux +  42)
+#define __NR_times                      (__NR_Linux +  43)
+#define __NR_prof                       (__NR_Linux +  44)
+#define __NR_brk                        (__NR_Linux +  45)
+#define __NR_setgid                     (__NR_Linux +  46)
+#define __NR_getgid                     (__NR_Linux +  47)
+#define __NR_signal                     (__NR_Linux +  48)
+#define __NR_geteuid                    (__NR_Linux +  49)
+#define __NR_getegid                    (__NR_Linux +  50)
+#define __NR_acct                       (__NR_Linux +  51)
+#define __NR_umount2                    (__NR_Linux +  52)
+#define __NR_lock                       (__NR_Linux +  53)
+#define __NR_ioctl                      (__NR_Linux +  54)
+#define __NR_fcntl                      (__NR_Linux +  55)
+#define __NR_mpx                        (__NR_Linux +  56)
+#define __NR_setpgid                    (__NR_Linux +  57)
+#define __NR_ulimit                     (__NR_Linux +  58)
+#define __NR_unused59                   (__NR_Linux +  59)
+#define __NR_umask                      (__NR_Linux +  60)
+#define __NR_chroot                     (__NR_Linux +  61)
+#define __NR_ustat                      (__NR_Linux +  62)
+#define __NR_dup2                       (__NR_Linux +  63)
+#define __NR_getppid                    (__NR_Linux +  64)
+#define __NR_getpgrp                    (__NR_Linux +  65)
+#define __NR_setsid                     (__NR_Linux +  66)
+#define __NR_sigaction                  (__NR_Linux +  67)
+#define __NR_sgetmask                   (__NR_Linux +  68)
+#define __NR_ssetmask                   (__NR_Linux +  69)
+#define __NR_setreuid                   (__NR_Linux +  70)
+#define __NR_setregid                   (__NR_Linux +  71)
+#define __NR_sigsuspend                 (__NR_Linux +  72)
+#define __NR_sigpending                 (__NR_Linux +  73)
+#define __NR_sethostname                (__NR_Linux +  74)
+#define __NR_setrlimit                  (__NR_Linux +  75)
+#define __NR_getrlimit                  (__NR_Linux +  76)
+#define __NR_getrusage                  (__NR_Linux +  77)
+#define __NR_gettimeofday               (__NR_Linux +  78)
+#define __NR_settimeofday               (__NR_Linux +  79)
+#define __NR_getgroups                  (__NR_Linux +  80)
+#define __NR_setgroups                  (__NR_Linux +  81)
+#define __NR_reserved82                 (__NR_Linux +  82)
+#define __NR_symlink                    (__NR_Linux +  83)
+#define __NR_unused84                   (__NR_Linux +  84)
+#define __NR_readlink                   (__NR_Linux +  85)
+#define __NR_uselib                     (__NR_Linux +  86)
+#define __NR_swapon                     (__NR_Linux +  87)
+#define __NR_reboot                     (__NR_Linux +  88)
+#define __NR_readdir                    (__NR_Linux +  89)
+#define __NR_mmap                       (__NR_Linux +  90)
+#define __NR_munmap                     (__NR_Linux +  91)
+#define __NR_truncate                   (__NR_Linux +  92)
+#define __NR_ftruncate                  (__NR_Linux +  93)
+#define __NR_fchmod                     (__NR_Linux +  94)
+#define __NR_fchown                     (__NR_Linux +  95)
+#define __NR_getpriority                (__NR_Linux +  96)
+#define __NR_setpriority                (__NR_Linux +  97)
+#define __NR_profil                     (__NR_Linux +  98)
+#define __NR_statfs                     (__NR_Linux +  99)
+#define __NR_fstatfs                    (__NR_Linux + 100)
+#define __NR_ioperm                     (__NR_Linux + 101)
+#define __NR_socketcall                 (__NR_Linux + 102)
+#define __NR_syslog                     (__NR_Linux + 103)
+#define __NR_setitimer                  (__NR_Linux + 104)
+#define __NR_getitimer                  (__NR_Linux + 105)
+#define __NR_stat                       (__NR_Linux + 106)
+#define __NR_lstat                      (__NR_Linux + 107)
+#define __NR_fstat                      (__NR_Linux + 108)
+#define __NR_unused109                  (__NR_Linux + 109)
+#define __NR_iopl                       (__NR_Linux + 110)
+#define __NR_vhangup                    (__NR_Linux + 111)
+#define __NR_idle                       (__NR_Linux + 112)
+#define __NR_vm86                       (__NR_Linux + 113)
+#define __NR_wait4                      (__NR_Linux + 114)
+#define __NR_swapoff                    (__NR_Linux + 115)
+#define __NR_sysinfo                    (__NR_Linux + 116)
+#define __NR_ipc                        (__NR_Linux + 117)
+#define __NR_fsync                      (__NR_Linux + 118)
+#define __NR_sigreturn                  (__NR_Linux + 119)
+#define __NR_clone                      (__NR_Linux + 120)
+#define __NR_setdomainname              (__NR_Linux + 121)
+#define __NR_uname                      (__NR_Linux + 122)
+#define __NR_modify_ldt                 (__NR_Linux + 123)
+#define __NR_adjtimex                   (__NR_Linux + 124)
+#define __NR_mprotect                   (__NR_Linux + 125)
+#define __NR_sigprocmask                (__NR_Linux + 126)
+#define __NR_create_module              (__NR_Linux + 127)
+#define __NR_init_module                (__NR_Linux + 128)
+#define __NR_delete_module              (__NR_Linux + 129)
+#define __NR_get_kernel_syms            (__NR_Linux + 130)
+#define __NR_quotactl                   (__NR_Linux + 131)
+#define __NR_getpgid                    (__NR_Linux + 132)
+#define __NR_fchdir                     (__NR_Linux + 133)
+#define __NR_bdflush                    (__NR_Linux + 134)
+#define __NR_sysfs                      (__NR_Linux + 135)
+#define __NR_personality                (__NR_Linux + 136)
+#define __NR_afs_syscall                (__NR_Linux + 137) /* Syscall for Andrew File System */
+#define __NR_setfsuid                   (__NR_Linux + 138)
+#define __NR_setfsgid                   (__NR_Linux + 139)
+#define __NR__llseek                    (__NR_Linux + 140)
+#define __NR_getdents                   (__NR_Linux + 141)
+#define __NR__newselect                 (__NR_Linux + 142)
+#define __NR_flock                      (__NR_Linux + 143)
+#define __NR_msync                      (__NR_Linux + 144)
+#define __NR_readv                      (__NR_Linux + 145)
+#define __NR_writev                     (__NR_Linux + 146)
+#define __NR_cacheflush                 (__NR_Linux + 147)
+#define __NR_cachectl                   (__NR_Linux + 148)
+#define __NR_sysmips                    (__NR_Linux + 149)
+#define __NR_unused150                  (__NR_Linux + 150)
+#define __NR_getsid                     (__NR_Linux + 151)
+#define __NR_fdatasync                  (__NR_Linux + 152)
+#define __NR__sysctl                    (__NR_Linux + 153)
+#define __NR_mlock                      (__NR_Linux + 154)
+#define __NR_munlock                    (__NR_Linux + 155)
+#define __NR_mlockall                   (__NR_Linux + 156)
+#define __NR_munlockall                 (__NR_Linux + 157)
+#define __NR_sched_setparam             (__NR_Linux + 158)
+#define __NR_sched_getparam             (__NR_Linux + 159)
+#define __NR_sched_setscheduler         (__NR_Linux + 160)
+#define __NR_sched_getscheduler         (__NR_Linux + 161)
+#define __NR_sched_yield                (__NR_Linux + 162)
+#define __NR_sched_get_priority_max     (__NR_Linux + 163)
+#define __NR_sched_get_priority_min     (__NR_Linux + 164)
+#define __NR_sched_rr_get_interval      (__NR_Linux + 165)
+#define __NR_nanosleep                  (__NR_Linux + 166)
+#define __NR_mremap                     (__NR_Linux + 167)
+#define __NR_accept                     (__NR_Linux + 168)
+#define __NR_bind                       (__NR_Linux + 169)
+#define __NR_connect                    (__NR_Linux + 170)
+#define __NR_getpeername                (__NR_Linux + 171)
+#define __NR_getsockname                (__NR_Linux + 172)
+#define __NR_getsockopt                 (__NR_Linux + 173)
+#define __NR_listen                     (__NR_Linux + 174)
+#define __NR_recv                       (__NR_Linux + 175)
+#define __NR_recvfrom                   (__NR_Linux + 176)
+#define __NR_recvmsg                    (__NR_Linux + 177)
+#define __NR_send                       (__NR_Linux + 178)
+#define __NR_sendmsg                    (__NR_Linux + 179)
+#define __NR_sendto                     (__NR_Linux + 180)
+#define __NR_setsockopt                 (__NR_Linux + 181)
+#define __NR_shutdown                   (__NR_Linux + 182)
+#define __NR_socket                     (__NR_Linux + 183)
+#define __NR_socketpair                 (__NR_Linux + 184)
+#define __NR_setresuid                  (__NR_Linux + 185)
+#define __NR_getresuid                  (__NR_Linux + 186)
+#define __NR_query_module               (__NR_Linux + 187)
+#define __NR_poll                       (__NR_Linux + 188)
+#define __NR_nfsservctl                 (__NR_Linux + 189)
+#define __NR_setresgid                  (__NR_Linux + 190)
+#define __NR_getresgid                  (__NR_Linux + 191)
+#define __NR_prctl                      (__NR_Linux + 192)
+#define __NR_rt_sigreturn               (__NR_Linux + 193)
+#define __NR_rt_sigaction               (__NR_Linux + 194)
+#define __NR_rt_sigprocmask             (__NR_Linux + 195)
+#define __NR_rt_sigpending              (__NR_Linux + 196)
+#define __NR_rt_sigtimedwait            (__NR_Linux + 197)
+#define __NR_rt_sigqueueinfo            (__NR_Linux + 198)
+#define __NR_rt_sigsuspend              (__NR_Linux + 199)
+#define __NR_pread64                    (__NR_Linux + 200)
+#define __NR_pwrite64                   (__NR_Linux + 201)
+#define __NR_chown                      (__NR_Linux + 202)
+#define __NR_getcwd                     (__NR_Linux + 203)
+#define __NR_capget                     (__NR_Linux + 204)
+#define __NR_capset                     (__NR_Linux + 205)
+#define __NR_sigaltstack                (__NR_Linux + 206)
+#define __NR_sendfile                   (__NR_Linux + 207)
+#define __NR_getpmsg                    (__NR_Linux + 208)
+#define __NR_putpmsg                    (__NR_Linux + 209)
+#define __NR_mmap2                      (__NR_Linux + 210)
+#define __NR_truncate64                 (__NR_Linux + 211)
+#define __NR_ftruncate64                (__NR_Linux + 212)
+#define __NR_stat64                     (__NR_Linux + 213)
+#define __NR_lstat64                    (__NR_Linux + 214)
+#define __NR_fstat64                    (__NR_Linux + 215)
+#define __NR_pivot_root                 (__NR_Linux + 216)
+#define __NR_mincore                    (__NR_Linux + 217)
+#define __NR_madvise                    (__NR_Linux + 218)
+#define __NR_getdents64                 (__NR_Linux + 219)
+#define __NR_fcntl64                    (__NR_Linux + 220)
+#define __NR_reserved221                (__NR_Linux + 221)
+#define __NR_gettid                     (__NR_Linux + 222)
+#define __NR_readahead                  (__NR_Linux + 223)
+#define __NR_setxattr                   (__NR_Linux + 224)
+#define __NR_lsetxattr                  (__NR_Linux + 225)
+#define __NR_fsetxattr                  (__NR_Linux + 226)
+#define __NR_getxattr                   (__NR_Linux + 227)
+#define __NR_lgetxattr                  (__NR_Linux + 228)
+#define __NR_fgetxattr                  (__NR_Linux + 229)
+#define __NR_listxattr                  (__NR_Linux + 230)
+#define __NR_llistxattr                 (__NR_Linux + 231)
+#define __NR_flistxattr                 (__NR_Linux + 232)
+#define __NR_removexattr                (__NR_Linux + 233)
+#define __NR_lremovexattr               (__NR_Linux + 234)
+#define __NR_fremovexattr               (__NR_Linux + 235)
+#define __NR_tkill                      (__NR_Linux + 236)
+#define __NR_sendfile64                 (__NR_Linux + 237)
+#define __NR_futex                      (__NR_Linux + 238)
+#define __NR_sched_setaffinity          (__NR_Linux + 239)
+#define __NR_sched_getaffinity          (__NR_Linux + 240)
+#define __NR_io_setup                   (__NR_Linux + 241)
+#define __NR_io_destroy                 (__NR_Linux + 242)
+#define __NR_io_getevents               (__NR_Linux + 243)
+#define __NR_io_submit                  (__NR_Linux + 244)
+#define __NR_io_cancel                  (__NR_Linux + 245)
+#define __NR_exit_group                 (__NR_Linux + 246)
+#define __NR_lookup_dcookie             (__NR_Linux + 247)
+#define __NR_epoll_create               (__NR_Linux + 248)
+#define __NR_epoll_ctl                  (__NR_Linux + 249)
+#define __NR_epoll_wait                 (__NR_Linux + 250)
+#define __NR_remap_file_pages           (__NR_Linux + 251)
+#define __NR_set_tid_address            (__NR_Linux + 252)
+#define __NR_restart_syscall            (__NR_Linux + 253)
+#define __NR_fadvise64                  (__NR_Linux + 254)
+#define __NR_statfs64                   (__NR_Linux + 255)
+#define __NR_fstatfs64                  (__NR_Linux + 256)
+#define __NR_timer_create               (__NR_Linux + 257)
+#define __NR_timer_settime              (__NR_Linux + 258)
+#define __NR_timer_gettime              (__NR_Linux + 259)
+#define __NR_timer_getoverrun           (__NR_Linux + 260)
+#define __NR_timer_delete               (__NR_Linux + 261)
+#define __NR_clock_settime              (__NR_Linux + 262)
+#define __NR_clock_gettime              (__NR_Linux + 263)
+#define __NR_clock_getres               (__NR_Linux + 264)
+#define __NR_clock_nanosleep            (__NR_Linux + 265)
+#define __NR_tgkill                     (__NR_Linux + 266)
+#define __NR_utimes                     (__NR_Linux + 267)
+#define __NR_mbind                      (__NR_Linux + 268)
+#define __NR_get_mempolicy              (__NR_Linux + 269)
+#define __NR_set_mempolicy              (__NR_Linux + 270)
+#define __NR_mq_open                    (__NR_Linux + 271)
+#define __NR_mq_unlink                  (__NR_Linux + 272)
+#define __NR_mq_timedsend               (__NR_Linux + 273)
+#define __NR_mq_timedreceive            (__NR_Linux + 274)
+#define __NR_mq_notify                  (__NR_Linux + 275)
+#define __NR_mq_getsetattr              (__NR_Linux + 276)
+#define __NR_vserver                    (__NR_Linux + 277)
+#define __NR_waitid                     (__NR_Linux + 278)
+/* #define __NR_sys_setaltroot          (__NR_Linux + 279) */
+#define __NR_add_key                    (__NR_Linux + 280)
+#define __NR_request_key                (__NR_Linux + 281)
+#define __NR_keyctl                     (__NR_Linux + 282)
+#define __NR_set_thread_area            (__NR_Linux + 283)
+#define __NR_inotify_init               (__NR_Linux + 284)
+#define __NR_inotify_add_watch          (__NR_Linux + 285)
+#define __NR_inotify_rm_watch           (__NR_Linux + 286)
+#define __NR_migrate_pages              (__NR_Linux + 287)
+#define __NR_openat                     (__NR_Linux + 288)
+#define __NR_mkdirat                    (__NR_Linux + 289)
+#define __NR_mknodat                    (__NR_Linux + 290)
+#define __NR_fchownat                   (__NR_Linux + 291)
+#define __NR_futimesat                  (__NR_Linux + 292)
+#define __NR_fstatat64                  (__NR_Linux + 293)
+#define __NR_unlinkat                   (__NR_Linux + 294)
+#define __NR_renameat                   (__NR_Linux + 295)
+#define __NR_linkat                     (__NR_Linux + 296)
+#define __NR_symlinkat                  (__NR_Linux + 297)
+#define __NR_readlinkat                 (__NR_Linux + 298)
+#define __NR_fchmodat                   (__NR_Linux + 299)
+#define __NR_faccessat                  (__NR_Linux + 300)
+#define __NR_pselect6                   (__NR_Linux + 301)
+#define __NR_ppoll                      (__NR_Linux + 302)
+#define __NR_unshare                    (__NR_Linux + 303)
+#define __NR_splice                     (__NR_Linux + 304)
+#define __NR_sync_file_range            (__NR_Linux + 305)
+#define __NR_tee                        (__NR_Linux + 306)
+#define __NR_vmsplice                   (__NR_Linux + 307)
+#define __NR_move_pages                 (__NR_Linux + 308)
+#define __NR_set_robust_list            (__NR_Linux + 309)
+#define __NR_get_robust_list            (__NR_Linux + 310)
+#define __NR_kexec_load                 (__NR_Linux + 311)
+#define __NR_getcpu                     (__NR_Linux + 312)
+#define __NR_epoll_pwait                (__NR_Linux + 313)
+#define __NR_ioprio_set                 (__NR_Linux + 314)
+#define __NR_ioprio_get                 (__NR_Linux + 315)
+#define __NR_utimensat                  (__NR_Linux + 316)
+#define __NR_signalfd                   (__NR_Linux + 317)
+#define __NR_timerfd                    (__NR_Linux + 318)
+#define __NR_eventfd                    (__NR_Linux + 319)
+#define __NR_fallocate                  (__NR_Linux + 320)
+#define __NR_timerfd_create             (__NR_Linux + 321)
+#define __NR_timerfd_gettime            (__NR_Linux + 322)
+#define __NR_timerfd_settime            (__NR_Linux + 323)
+#define __NR_signalfd4                  (__NR_Linux + 324)
+#define __NR_eventfd2                   (__NR_Linux + 325)
+#define __NR_epoll_create1              (__NR_Linux + 326)
+#define __NR_dup3                       (__NR_Linux + 327)
+#define __NR_pipe2                      (__NR_Linux + 328)
+#define __NR_inotify_init1              (__NR_Linux + 329)
+#define __NR_preadv                     (__NR_Linux + 330)
+#define __NR_pwritev                    (__NR_Linux + 331)
+#define __NR_rt_tgsigqueueinfo          (__NR_Linux + 332)
+#define __NR_perf_event_open            (__NR_Linux + 333)
+#define __NR_accept4                    (__NR_Linux + 334)
+#define __NR_recvmmsg                   (__NR_Linux + 335)
+#define __NR_fanotify_init              (__NR_Linux + 336)
+#define __NR_fanotify_mark              (__NR_Linux + 337)
+#define __NR_prlimit64                  (__NR_Linux + 338)
+#define __NR_name_to_handle_at          (__NR_Linux + 339)
+#define __NR_open_by_handle_at          (__NR_Linux + 340)
+#define __NR_clock_adjtime              (__NR_Linux + 341)
+#define __NR_syncfs                     (__NR_Linux + 342)
+#define __NR_sendmmsg                   (__NR_Linux + 343)
+#define __NR_setns                      (__NR_Linux + 344)
+
+/*
+ * Offset of the last Linux o32 flavoured syscall
+ */
+#define __NR_Linux_syscalls             344
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#define __NR_O32_Linux                  4000
+#define __NR_O32_Linux_syscalls         344
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+/*
+ * Linux 64-bit syscalls are in the range from 5000 to 5999.
+ */
+#define __NR_Linux                      5000
+#define __NR_read                       (__NR_Linux +   0)
+#define __NR_write                      (__NR_Linux +   1)
+#define __NR_open                       (__NR_Linux +   2)
+#define __NR_close                      (__NR_Linux +   3)
+#define __NR_stat                       (__NR_Linux +   4)
+#define __NR_fstat                      (__NR_Linux +   5)
+#define __NR_lstat                      (__NR_Linux +   6)
+#define __NR_poll                       (__NR_Linux +   7)
+#define __NR_lseek                      (__NR_Linux +   8)
+#define __NR_mmap                       (__NR_Linux +   9)
+#define __NR_mprotect                   (__NR_Linux +  10)
+#define __NR_munmap                     (__NR_Linux +  11)
+#define __NR_brk                        (__NR_Linux +  12)
+#define __NR_rt_sigaction               (__NR_Linux +  13)
+#define __NR_rt_sigprocmask             (__NR_Linux +  14)
+#define __NR_ioctl                      (__NR_Linux +  15)
+#define __NR_pread64                    (__NR_Linux +  16)
+#define __NR_pwrite64                   (__NR_Linux +  17)
+#define __NR_readv                      (__NR_Linux +  18)
+#define __NR_writev                     (__NR_Linux +  19)
+#define __NR_access                     (__NR_Linux +  20)
+#define __NR_pipe                       (__NR_Linux +  21)
+#define __NR__newselect                 (__NR_Linux +  22)
+#define __NR_sched_yield                (__NR_Linux +  23)
+#define __NR_mremap                     (__NR_Linux +  24)
+#define __NR_msync                      (__NR_Linux +  25)
+#define __NR_mincore                    (__NR_Linux +  26)
+#define __NR_madvise                    (__NR_Linux +  27)
+#define __NR_shmget                     (__NR_Linux +  28)
+#define __NR_shmat                      (__NR_Linux +  29)
+#define __NR_shmctl                     (__NR_Linux +  30)
+#define __NR_dup                        (__NR_Linux +  31)
+#define __NR_dup2                       (__NR_Linux +  32)
+#define __NR_pause                      (__NR_Linux +  33)
+#define __NR_nanosleep                  (__NR_Linux +  34)
+#define __NR_getitimer                  (__NR_Linux +  35)
+#define __NR_setitimer                  (__NR_Linux +  36)
+#define __NR_alarm                      (__NR_Linux +  37)
+#define __NR_getpid                     (__NR_Linux +  38)
+#define __NR_sendfile                   (__NR_Linux +  39)
+#define __NR_socket                     (__NR_Linux +  40)
+#define __NR_connect                    (__NR_Linux +  41)
+#define __NR_accept                     (__NR_Linux +  42)
+#define __NR_sendto                     (__NR_Linux +  43)
+#define __NR_recvfrom                   (__NR_Linux +  44)
+#define __NR_sendmsg                    (__NR_Linux +  45)
+#define __NR_recvmsg                    (__NR_Linux +  46)
+#define __NR_shutdown                   (__NR_Linux +  47)
+#define __NR_bind                       (__NR_Linux +  48)
+#define __NR_listen                     (__NR_Linux +  49)
+#define __NR_getsockname                (__NR_Linux +  50)
+#define __NR_getpeername                (__NR_Linux +  51)
+#define __NR_socketpair                 (__NR_Linux +  52)
+#define __NR_setsockopt                 (__NR_Linux +  53)
+#define __NR_getsockopt                 (__NR_Linux +  54)
+#define __NR_clone                      (__NR_Linux +  55)
+#define __NR_fork                       (__NR_Linux +  56)
+#define __NR_execve                     (__NR_Linux +  57)
+#define __NR_exit                       (__NR_Linux +  58)
+#define __NR_wait4                      (__NR_Linux +  59)
+#define __NR_kill                       (__NR_Linux +  60)
+#define __NR_uname                      (__NR_Linux +  61)
+#define __NR_semget                     (__NR_Linux +  62)
+#define __NR_semop                      (__NR_Linux +  63)
+#define __NR_semctl                     (__NR_Linux +  64)
+#define __NR_shmdt                      (__NR_Linux +  65)
+#define __NR_msgget                     (__NR_Linux +  66)
+#define __NR_msgsnd                     (__NR_Linux +  67)
+#define __NR_msgrcv                     (__NR_Linux +  68)
+#define __NR_msgctl                     (__NR_Linux +  69)
+#define __NR_fcntl                      (__NR_Linux +  70)
+#define __NR_flock                      (__NR_Linux +  71)
+#define __NR_fsync                      (__NR_Linux +  72)
+#define __NR_fdatasync                  (__NR_Linux +  73)
+#define __NR_truncate                   (__NR_Linux +  74)
+#define __NR_ftruncate                  (__NR_Linux +  75)
+#define __NR_getdents                   (__NR_Linux +  76)
+#define __NR_getcwd                     (__NR_Linux +  77)
+#define __NR_chdir                      (__NR_Linux +  78)
+#define __NR_fchdir                     (__NR_Linux +  79)
+#define __NR_rename                     (__NR_Linux +  80)
+#define __NR_mkdir                      (__NR_Linux +  81)
+#define __NR_rmdir                      (__NR_Linux +  82)
+#define __NR_creat                      (__NR_Linux +  83)
+#define __NR_link                       (__NR_Linux +  84)
+#define __NR_unlink                     (__NR_Linux +  85)
+#define __NR_symlink                    (__NR_Linux +  86)
+#define __NR_readlink                   (__NR_Linux +  87)
+#define __NR_chmod                      (__NR_Linux +  88)
+#define __NR_fchmod                     (__NR_Linux +  89)
+#define __NR_chown                      (__NR_Linux +  90)
+#define __NR_fchown                     (__NR_Linux +  91)
+#define __NR_lchown                     (__NR_Linux +  92)
+#define __NR_umask                      (__NR_Linux +  93)
+#define __NR_gettimeofday               (__NR_Linux +  94)
+#define __NR_getrlimit                  (__NR_Linux +  95)
+#define __NR_getrusage                  (__NR_Linux +  96)
+#define __NR_sysinfo                    (__NR_Linux +  97)
+#define __NR_times                      (__NR_Linux +  98)
+#define __NR_ptrace                     (__NR_Linux +  99)
+#define __NR_getuid                     (__NR_Linux + 100)
+#define __NR_syslog                     (__NR_Linux + 101)
+#define __NR_getgid                     (__NR_Linux + 102)
+#define __NR_setuid                     (__NR_Linux + 103)
+#define __NR_setgid                     (__NR_Linux + 104)
+#define __NR_geteuid                    (__NR_Linux + 105)
+#define __NR_getegid                    (__NR_Linux + 106)
+#define __NR_setpgid                    (__NR_Linux + 107)
+#define __NR_getppid                    (__NR_Linux + 108)
+#define __NR_getpgrp                    (__NR_Linux + 109)
+#define __NR_setsid                     (__NR_Linux + 110)
+#define __NR_setreuid                   (__NR_Linux + 111)
+#define __NR_setregid                   (__NR_Linux + 112)
+#define __NR_getgroups                  (__NR_Linux + 113)
+#define __NR_setgroups                  (__NR_Linux + 114)
+#define __NR_setresuid                  (__NR_Linux + 115)
+#define __NR_getresuid                  (__NR_Linux + 116)
+#define __NR_setresgid                  (__NR_Linux + 117)
+#define __NR_getresgid                  (__NR_Linux + 118)
+#define __NR_getpgid                    (__NR_Linux + 119)
+#define __NR_setfsuid                   (__NR_Linux + 120)
+#define __NR_setfsgid                   (__NR_Linux + 121)
+#define __NR_getsid                     (__NR_Linux + 122)
+#define __NR_capget                     (__NR_Linux + 123)
+#define __NR_capset                     (__NR_Linux + 124)
+#define __NR_rt_sigpending              (__NR_Linux + 125)
+#define __NR_rt_sigtimedwait            (__NR_Linux + 126)
+#define __NR_rt_sigqueueinfo            (__NR_Linux + 127)
+#define __NR_rt_sigsuspend              (__NR_Linux + 128)
+#define __NR_sigaltstack                (__NR_Linux + 129)
+#define __NR_utime                      (__NR_Linux + 130)
+#define __NR_mknod                      (__NR_Linux + 131)
+#define __NR_personality                (__NR_Linux + 132)
+#define __NR_ustat                      (__NR_Linux + 133)
+#define __NR_statfs                     (__NR_Linux + 134)
+#define __NR_fstatfs                    (__NR_Linux + 135)
+#define __NR_sysfs                      (__NR_Linux + 136)
+#define __NR_getpriority                (__NR_Linux + 137)
+#define __NR_setpriority                (__NR_Linux + 138)
+#define __NR_sched_setparam             (__NR_Linux + 139)
+#define __NR_sched_getparam             (__NR_Linux + 140)
+#define __NR_sched_setscheduler         (__NR_Linux + 141)
+#define __NR_sched_getscheduler         (__NR_Linux + 142)
+#define __NR_sched_get_priority_max     (__NR_Linux + 143)
+#define __NR_sched_get_priority_min     (__NR_Linux + 144)
+#define __NR_sched_rr_get_interval      (__NR_Linux + 145)
+#define __NR_mlock                      (__NR_Linux + 146)
+#define __NR_munlock                    (__NR_Linux + 147)
+#define __NR_mlockall                   (__NR_Linux + 148)
+#define __NR_munlockall                 (__NR_Linux + 149)
+#define __NR_vhangup                    (__NR_Linux + 150)
+#define __NR_pivot_root                 (__NR_Linux + 151)
+#define __NR__sysctl                    (__NR_Linux + 152)
+#define __NR_prctl                      (__NR_Linux + 153)
+#define __NR_adjtimex                   (__NR_Linux + 154)
+#define __NR_setrlimit                  (__NR_Linux + 155)
+#define __NR_chroot                     (__NR_Linux + 156)
+#define __NR_sync                       (__NR_Linux + 157)
+#define __NR_acct                       (__NR_Linux + 158)
+#define __NR_settimeofday               (__NR_Linux + 159)
+#define __NR_mount                      (__NR_Linux + 160)
+#define __NR_umount2                    (__NR_Linux + 161)
+#define __NR_swapon                     (__NR_Linux + 162)
+#define __NR_swapoff                    (__NR_Linux + 163)
+#define __NR_reboot                     (__NR_Linux + 164)
+#define __NR_sethostname                (__NR_Linux + 165)
+#define __NR_setdomainname              (__NR_Linux + 166)
+#define __NR_create_module              (__NR_Linux + 167)
+#define __NR_init_module                (__NR_Linux + 168)
+#define __NR_delete_module              (__NR_Linux + 169)
+#define __NR_get_kernel_syms            (__NR_Linux + 170)
+#define __NR_query_module               (__NR_Linux + 171)
+#define __NR_quotactl                   (__NR_Linux + 172)
+#define __NR_nfsservctl                 (__NR_Linux + 173)
+#define __NR_getpmsg                    (__NR_Linux + 174)
+#define __NR_putpmsg                    (__NR_Linux + 175)
+#define __NR_afs_syscall                (__NR_Linux + 176)
+#define __NR_reserved177                (__NR_Linux + 177)
+#define __NR_gettid                     (__NR_Linux + 178)
+#define __NR_readahead                  (__NR_Linux + 179)
+#define __NR_setxattr                   (__NR_Linux + 180)
+#define __NR_lsetxattr                  (__NR_Linux + 181)
+#define __NR_fsetxattr                  (__NR_Linux + 182)
+#define __NR_getxattr                   (__NR_Linux + 183)
+#define __NR_lgetxattr                  (__NR_Linux + 184)
+#define __NR_fgetxattr                  (__NR_Linux + 185)
+#define __NR_listxattr                  (__NR_Linux + 186)
+#define __NR_llistxattr                 (__NR_Linux + 187)
+#define __NR_flistxattr                 (__NR_Linux + 188)
+#define __NR_removexattr                (__NR_Linux + 189)
+#define __NR_lremovexattr               (__NR_Linux + 190)
+#define __NR_fremovexattr               (__NR_Linux + 191)
+#define __NR_tkill                      (__NR_Linux + 192)
+#define __NR_reserved193                (__NR_Linux + 193)
+#define __NR_futex                      (__NR_Linux + 194)
+#define __NR_sched_setaffinity          (__NR_Linux + 195)
+#define __NR_sched_getaffinity          (__NR_Linux + 196)
+#define __NR_cacheflush                 (__NR_Linux + 197)
+#define __NR_cachectl                   (__NR_Linux + 198)
+#define __NR_sysmips                    (__NR_Linux + 199)
+#define __NR_io_setup                   (__NR_Linux + 200)
+#define __NR_io_destroy                 (__NR_Linux + 201)
+#define __NR_io_getevents               (__NR_Linux + 202)
+#define __NR_io_submit                  (__NR_Linux + 203)
+#define __NR_io_cancel                  (__NR_Linux + 204)
+#define __NR_exit_group                 (__NR_Linux + 205)
+#define __NR_lookup_dcookie             (__NR_Linux + 206)
+#define __NR_epoll_create               (__NR_Linux + 207)
+#define __NR_epoll_ctl                  (__NR_Linux + 208)
+#define __NR_epoll_wait                 (__NR_Linux + 209)
+#define __NR_remap_file_pages           (__NR_Linux + 210)
+#define __NR_rt_sigreturn               (__NR_Linux + 211)
+#define __NR_set_tid_address            (__NR_Linux + 212)
+#define __NR_restart_syscall            (__NR_Linux + 213)
+#define __NR_semtimedop                 (__NR_Linux + 214)
+#define __NR_fadvise64                  (__NR_Linux + 215)
+#define __NR_timer_create               (__NR_Linux + 216)
+#define __NR_timer_settime              (__NR_Linux + 217)
+#define __NR_timer_gettime              (__NR_Linux + 218)
+#define __NR_timer_getoverrun           (__NR_Linux + 219)
+#define __NR_timer_delete               (__NR_Linux + 220)
+#define __NR_clock_settime              (__NR_Linux + 221)
+#define __NR_clock_gettime              (__NR_Linux + 222)
+#define __NR_clock_getres               (__NR_Linux + 223)
+#define __NR_clock_nanosleep            (__NR_Linux + 224)
+#define __NR_tgkill                     (__NR_Linux + 225)
+#define __NR_utimes                     (__NR_Linux + 226)
+#define __NR_mbind                      (__NR_Linux + 227)
+#define __NR_get_mempolicy              (__NR_Linux + 228)
+#define __NR_set_mempolicy              (__NR_Linux + 229)
+#define __NR_mq_open                    (__NR_Linux + 230)
+#define __NR_mq_unlink                  (__NR_Linux + 231)
+#define __NR_mq_timedsend               (__NR_Linux + 232)
+#define __NR_mq_timedreceive            (__NR_Linux + 233)
+#define __NR_mq_notify                  (__NR_Linux + 234)
+#define __NR_mq_getsetattr              (__NR_Linux + 235)
+#define __NR_vserver                    (__NR_Linux + 236)
+#define __NR_waitid                     (__NR_Linux + 237)
+/* #define __NR_sys_setaltroot          (__NR_Linux + 238) */
+#define __NR_add_key                    (__NR_Linux + 239)
+#define __NR_request_key                (__NR_Linux + 240)
+#define __NR_keyctl                     (__NR_Linux + 241)
+#define __NR_set_thread_area            (__NR_Linux + 242)
+#define __NR_inotify_init               (__NR_Linux + 243)
+#define __NR_inotify_add_watch          (__NR_Linux + 244)
+#define __NR_inotify_rm_watch           (__NR_Linux + 245)
+#define __NR_migrate_pages              (__NR_Linux + 246)
+#define __NR_openat                     (__NR_Linux + 247)
+#define __NR_mkdirat                    (__NR_Linux + 248)
+#define __NR_mknodat                    (__NR_Linux + 249)
+#define __NR_fchownat                   (__NR_Linux + 250)
+#define __NR_futimesat                  (__NR_Linux + 251)
+#define __NR_newfstatat                 (__NR_Linux + 252)
+#define __NR_unlinkat                   (__NR_Linux + 253)
+#define __NR_renameat                   (__NR_Linux + 254)
+#define __NR_linkat                     (__NR_Linux + 255)
+#define __NR_symlinkat                  (__NR_Linux + 256)
+#define __NR_readlinkat                 (__NR_Linux + 257)
+#define __NR_fchmodat                   (__NR_Linux + 258)
+#define __NR_faccessat                  (__NR_Linux + 259)
+#define __NR_pselect6                   (__NR_Linux + 260)
+#define __NR_ppoll                      (__NR_Linux + 261)
+#define __NR_unshare                    (__NR_Linux + 262)
+#define __NR_splice                     (__NR_Linux + 263)
+#define __NR_sync_file_range            (__NR_Linux + 264)
+#define __NR_tee                        (__NR_Linux + 265)
+#define __NR_vmsplice                   (__NR_Linux + 266)
+#define __NR_move_pages                 (__NR_Linux + 267)
+#define __NR_set_robust_list            (__NR_Linux + 268)
+#define __NR_get_robust_list            (__NR_Linux + 269)
+#define __NR_kexec_load                 (__NR_Linux + 270)
+#define __NR_getcpu                     (__NR_Linux + 271)
+#define __NR_epoll_pwait                (__NR_Linux + 272)
+#define __NR_ioprio_set                 (__NR_Linux + 273)
+#define __NR_ioprio_get                 (__NR_Linux + 274)
+#define __NR_utimensat                  (__NR_Linux + 275)
+#define __NR_signalfd                   (__NR_Linux + 276)
+#define __NR_timerfd                    (__NR_Linux + 277)
+#define __NR_eventfd                    (__NR_Linux + 278)
+#define __NR_fallocate                  (__NR_Linux + 279)
+#define __NR_timerfd_create             (__NR_Linux + 280)
+#define __NR_timerfd_gettime            (__NR_Linux + 281)
+#define __NR_timerfd_settime            (__NR_Linux + 282)
+#define __NR_signalfd4                  (__NR_Linux + 283)
+#define __NR_eventfd2                   (__NR_Linux + 284)
+#define __NR_epoll_create1              (__NR_Linux + 285)
+#define __NR_dup3                       (__NR_Linux + 286)
+#define __NR_pipe2                      (__NR_Linux + 287)
+#define __NR_inotify_init1              (__NR_Linux + 288)
+#define __NR_preadv                     (__NR_Linux + 289)
+#define __NR_pwritev                    (__NR_Linux + 290)
+#define __NR_rt_tgsigqueueinfo          (__NR_Linux + 291)
+#define __NR_perf_event_open            (__NR_Linux + 292)
+#define __NR_accept4                    (__NR_Linux + 293)
+#define __NR_recvmmsg                   (__NR_Linux + 294)
+#define __NR_fanotify_init              (__NR_Linux + 295)
+#define __NR_fanotify_mark              (__NR_Linux + 296)
+#define __NR_prlimit64                  (__NR_Linux + 297)
+#define __NR_name_to_handle_at          (__NR_Linux + 298)
+#define __NR_open_by_handle_at          (__NR_Linux + 299)
+#define __NR_clock_adjtime              (__NR_Linux + 300)
+#define __NR_syncfs                     (__NR_Linux + 301)
+#define __NR_sendmmsg                   (__NR_Linux + 302)
+#define __NR_setns                      (__NR_Linux + 303)
+
+/*
+ * Offset of the last Linux 64-bit flavoured syscall
+ */
+#define __NR_Linux_syscalls             303
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#define __NR_64_Linux                   5000
+#define __NR_64_Linux_syscalls          303
+
+#if _MIPS_SIM == _MIPS_SIM_NABI32
+
+/*
+ * Linux N32 syscalls are in the range from 6000 to 6999.
+ */
+#define __NR_Linux                      6000
+#define __NR_read                       (__NR_Linux +   0)
+#define __NR_write                      (__NR_Linux +   1)
+#define __NR_open                       (__NR_Linux +   2)
+#define __NR_close                      (__NR_Linux +   3)
+#define __NR_stat                       (__NR_Linux +   4)
+#define __NR_fstat                      (__NR_Linux +   5)
+#define __NR_lstat                      (__NR_Linux +   6)
+#define __NR_poll                       (__NR_Linux +   7)
+#define __NR_lseek                      (__NR_Linux +   8)
+#define __NR_mmap                       (__NR_Linux +   9)
+#define __NR_mprotect                   (__NR_Linux +  10)
+#define __NR_munmap                     (__NR_Linux +  11)
+#define __NR_brk                        (__NR_Linux +  12)
+#define __NR_rt_sigaction               (__NR_Linux +  13)
+#define __NR_rt_sigprocmask             (__NR_Linux +  14)
+#define __NR_ioctl                      (__NR_Linux +  15)
+#define __NR_pread64                    (__NR_Linux +  16)
+#define __NR_pwrite64                   (__NR_Linux +  17)
+#define __NR_readv                      (__NR_Linux +  18)
+#define __NR_writev                     (__NR_Linux +  19)
+#define __NR_access                     (__NR_Linux +  20)
+#define __NR_pipe                       (__NR_Linux +  21)
+#define __NR__newselect                 (__NR_Linux +  22)
+#define __NR_sched_yield                (__NR_Linux +  23)
+#define __NR_mremap                     (__NR_Linux +  24)
+#define __NR_msync                      (__NR_Linux +  25)
+#define __NR_mincore                    (__NR_Linux +  26)
+#define __NR_madvise                    (__NR_Linux +  27)
+#define __NR_shmget                     (__NR_Linux +  28)
+#define __NR_shmat                      (__NR_Linux +  29)
+#define __NR_shmctl                     (__NR_Linux +  30)
+#define __NR_dup                        (__NR_Linux +  31)
+#define __NR_dup2                       (__NR_Linux +  32)
+#define __NR_pause                      (__NR_Linux +  33)
+#define __NR_nanosleep                  (__NR_Linux +  34)
+#define __NR_getitimer                  (__NR_Linux +  35)
+#define __NR_setitimer                  (__NR_Linux +  36)
+#define __NR_alarm                      (__NR_Linux +  37)
+#define __NR_getpid                     (__NR_Linux +  38)
+#define __NR_sendfile                   (__NR_Linux +  39)
+#define __NR_socket                     (__NR_Linux +  40)
+#define __NR_connect                    (__NR_Linux +  41)
+#define __NR_accept                     (__NR_Linux +  42)
+#define __NR_sendto                     (__NR_Linux +  43)
+#define __NR_recvfrom                   (__NR_Linux +  44)
+#define __NR_sendmsg                    (__NR_Linux +  45)
+#define __NR_recvmsg                    (__NR_Linux +  46)
+#define __NR_shutdown                   (__NR_Linux +  47)
+#define __NR_bind                       (__NR_Linux +  48)
+#define __NR_listen                     (__NR_Linux +  49)
+#define __NR_getsockname                (__NR_Linux +  50)
+#define __NR_getpeername                (__NR_Linux +  51)
+#define __NR_socketpair                 (__NR_Linux +  52)
+#define __NR_setsockopt                 (__NR_Linux +  53)
+#define __NR_getsockopt                 (__NR_Linux +  54)
+#define __NR_clone                      (__NR_Linux +  55)
+#define __NR_fork                       (__NR_Linux +  56)
+#define __NR_execve                     (__NR_Linux +  57)
+#define __NR_exit                       (__NR_Linux +  58)
+#define __NR_wait4                      (__NR_Linux +  59)
+#define __NR_kill                       (__NR_Linux +  60)
+#define __NR_uname                      (__NR_Linux +  61)
+#define __NR_semget                     (__NR_Linux +  62)
+#define __NR_semop                      (__NR_Linux +  63)
+#define __NR_semctl                     (__NR_Linux +  64)
+#define __NR_shmdt                      (__NR_Linux +  65)
+#define __NR_msgget                     (__NR_Linux +  66)
+#define __NR_msgsnd                     (__NR_Linux +  67)
+#define __NR_msgrcv                     (__NR_Linux +  68)
+#define __NR_msgctl                     (__NR_Linux +  69)
+#define __NR_fcntl                      (__NR_Linux +  70)
+#define __NR_flock                      (__NR_Linux +  71)
+#define __NR_fsync                      (__NR_Linux +  72)
+#define __NR_fdatasync                  (__NR_Linux +  73)
+#define __NR_truncate                   (__NR_Linux +  74)
+#define __NR_ftruncate                  (__NR_Linux +  75)
+#define __NR_getdents                   (__NR_Linux +  76)
+#define __NR_getcwd                     (__NR_Linux +  77)
+#define __NR_chdir                      (__NR_Linux +  78)
+#define __NR_fchdir                     (__NR_Linux +  79)
+#define __NR_rename                     (__NR_Linux +  80)
+#define __NR_mkdir                      (__NR_Linux +  81)
+#define __NR_rmdir                      (__NR_Linux +  82)
+#define __NR_creat                      (__NR_Linux +  83)
+#define __NR_link                       (__NR_Linux +  84)
+#define __NR_unlink                     (__NR_Linux +  85)
+#define __NR_symlink                    (__NR_Linux +  86)
+#define __NR_readlink                   (__NR_Linux +  87)
+#define __NR_chmod                      (__NR_Linux +  88)
+#define __NR_fchmod                     (__NR_Linux +  89)
+#define __NR_chown                      (__NR_Linux +  90)
+#define __NR_fchown                     (__NR_Linux +  91)
+#define __NR_lchown                     (__NR_Linux +  92)
+#define __NR_umask                      (__NR_Linux +  93)
+#define __NR_gettimeofday               (__NR_Linux +  94)
+#define __NR_getrlimit                  (__NR_Linux +  95)
+#define __NR_getrusage                  (__NR_Linux +  96)
+#define __NR_sysinfo                    (__NR_Linux +  97)
+#define __NR_times                      (__NR_Linux +  98)
+#define __NR_ptrace                     (__NR_Linux +  99)
+#define __NR_getuid                     (__NR_Linux + 100)
+#define __NR_syslog                     (__NR_Linux + 101)
+#define __NR_getgid                     (__NR_Linux + 102)
+#define __NR_setuid                     (__NR_Linux + 103)
+#define __NR_setgid                     (__NR_Linux + 104)
+#define __NR_geteuid                    (__NR_Linux + 105)
+#define __NR_getegid                    (__NR_Linux + 106)
+#define __NR_setpgid                    (__NR_Linux + 107)
+#define __NR_getppid                    (__NR_Linux + 108)
+#define __NR_getpgrp                    (__NR_Linux + 109)
+#define __NR_setsid                     (__NR_Linux + 110)
+#define __NR_setreuid                   (__NR_Linux + 111)
+#define __NR_setregid                   (__NR_Linux + 112)
+#define __NR_getgroups                  (__NR_Linux + 113)
+#define __NR_setgroups                  (__NR_Linux + 114)
+#define __NR_setresuid                  (__NR_Linux + 115)
+#define __NR_getresuid                  (__NR_Linux + 116)
+#define __NR_setresgid                  (__NR_Linux + 117)
+#define __NR_getresgid                  (__NR_Linux + 118)
+#define __NR_getpgid                    (__NR_Linux + 119)
+#define __NR_setfsuid                   (__NR_Linux + 120)
+#define __NR_setfsgid                   (__NR_Linux + 121)
+#define __NR_getsid                     (__NR_Linux + 122)
+#define __NR_capget                     (__NR_Linux + 123)
+#define __NR_capset                     (__NR_Linux + 124)
+#define __NR_rt_sigpending              (__NR_Linux + 125)
+#define __NR_rt_sigtimedwait            (__NR_Linux + 126)
+#define __NR_rt_sigqueueinfo            (__NR_Linux + 127)
+#define __NR_rt_sigsuspend              (__NR_Linux + 128)
+#define __NR_sigaltstack                (__NR_Linux + 129)
+#define __NR_utime                      (__NR_Linux + 130)
+#define __NR_mknod                      (__NR_Linux + 131)
+#define __NR_personality                (__NR_Linux + 132)
+#define __NR_ustat                      (__NR_Linux + 133)
+#define __NR_statfs                     (__NR_Linux + 134)
+#define __NR_fstatfs                    (__NR_Linux + 135)
+#define __NR_sysfs                      (__NR_Linux + 136)
+#define __NR_getpriority                (__NR_Linux + 137)
+#define __NR_setpriority                (__NR_Linux + 138)
+#define __NR_sched_setparam             (__NR_Linux + 139)
+#define __NR_sched_getparam             (__NR_Linux + 140)
+#define __NR_sched_setscheduler         (__NR_Linux + 141)
+#define __NR_sched_getscheduler         (__NR_Linux + 142)
+#define __NR_sched_get_priority_max     (__NR_Linux + 143)
+#define __NR_sched_get_priority_min     (__NR_Linux + 144)
+#define __NR_sched_rr_get_interval      (__NR_Linux + 145)
+#define __NR_mlock                      (__NR_Linux + 146)
+#define __NR_munlock                    (__NR_Linux + 147)
+#define __NR_mlockall                   (__NR_Linux + 148)
+#define __NR_munlockall                 (__NR_Linux + 149)
+#define __NR_vhangup                    (__NR_Linux + 150)
+#define __NR_pivot_root                 (__NR_Linux + 151)
+#define __NR__sysctl                    (__NR_Linux + 152)
+#define __NR_prctl                      (__NR_Linux + 153)
+#define __NR_adjtimex                   (__NR_Linux + 154)
+#define __NR_setrlimit                  (__NR_Linux + 155)
+#define __NR_chroot                     (__NR_Linux + 156)
+#define __NR_sync                       (__NR_Linux + 157)
+#define __NR_acct                       (__NR_Linux + 158)
+#define __NR_settimeofday               (__NR_Linux + 159)
+#define __NR_mount                      (__NR_Linux + 160)
+#define __NR_umount2                    (__NR_Linux + 161)
+#define __NR_swapon                     (__NR_Linux + 162)
+#define __NR_swapoff                    (__NR_Linux + 163)
+#define __NR_reboot                     (__NR_Linux + 164)
+#define __NR_sethostname                (__NR_Linux + 165)
+#define __NR_setdomainname              (__NR_Linux + 166)
+#define __NR_create_module              (__NR_Linux + 167)
+#define __NR_init_module                (__NR_Linux + 168)
+#define __NR_delete_module              (__NR_Linux + 169)
+#define __NR_get_kernel_syms            (__NR_Linux + 170)
+#define __NR_query_module               (__NR_Linux + 171)
+#define __NR_quotactl                   (__NR_Linux + 172)
+#define __NR_nfsservctl                 (__NR_Linux + 173)
+#define __NR_getpmsg                    (__NR_Linux + 174)
+#define __NR_putpmsg                    (__NR_Linux + 175)
+#define __NR_afs_syscall                (__NR_Linux + 176)
+#define __NR_reserved177                (__NR_Linux + 177)
+#define __NR_gettid                     (__NR_Linux + 178)
+#define __NR_readahead                  (__NR_Linux + 179)
+#define __NR_setxattr                   (__NR_Linux + 180)
+#define __NR_lsetxattr                  (__NR_Linux + 181)
+#define __NR_fsetxattr                  (__NR_Linux + 182)
+#define __NR_getxattr                   (__NR_Linux + 183)
+#define __NR_lgetxattr                  (__NR_Linux + 184)
+#define __NR_fgetxattr                  (__NR_Linux + 185)
+#define __NR_listxattr                  (__NR_Linux + 186)
+#define __NR_llistxattr                 (__NR_Linux + 187)
+#define __NR_flistxattr                 (__NR_Linux + 188)
+#define __NR_removexattr                (__NR_Linux + 189)
+#define __NR_lremovexattr               (__NR_Linux + 190)
+#define __NR_fremovexattr               (__NR_Linux + 191)
+#define __NR_tkill                      (__NR_Linux + 192)
+#define __NR_reserved193                (__NR_Linux + 193)
+#define __NR_futex                      (__NR_Linux + 194)
+#define __NR_sched_setaffinity          (__NR_Linux + 195)
+#define __NR_sched_getaffinity          (__NR_Linux + 196)
+#define __NR_cacheflush                 (__NR_Linux + 197)
+#define __NR_cachectl                   (__NR_Linux + 198)
+#define __NR_sysmips                    (__NR_Linux + 199)
+#define __NR_io_setup                   (__NR_Linux + 200)
+#define __NR_io_destroy                 (__NR_Linux + 201)
+#define __NR_io_getevents               (__NR_Linux + 202)
+#define __NR_io_submit                  (__NR_Linux + 203)
+#define __NR_io_cancel                  (__NR_Linux + 204)
+#define __NR_exit_group                 (__NR_Linux + 205)
+#define __NR_lookup_dcookie             (__NR_Linux + 206)
+#define __NR_epoll_create               (__NR_Linux + 207)
+#define __NR_epoll_ctl                  (__NR_Linux + 208)
+#define __NR_epoll_wait                 (__NR_Linux + 209)
+#define __NR_remap_file_pages           (__NR_Linux + 210)
+#define __NR_rt_sigreturn               (__NR_Linux + 211)
+#define __NR_fcntl64                    (__NR_Linux + 212)
+#define __NR_set_tid_address            (__NR_Linux + 213)
+#define __NR_restart_syscall            (__NR_Linux + 214)
+#define __NR_semtimedop                 (__NR_Linux + 215)
+#define __NR_fadvise64                  (__NR_Linux + 216)
+#define __NR_statfs64                   (__NR_Linux + 217)
+#define __NR_fstatfs64                  (__NR_Linux + 218)
+#define __NR_sendfile64                 (__NR_Linux + 219)
+#define __NR_timer_create               (__NR_Linux + 220)
+#define __NR_timer_settime              (__NR_Linux + 221)
+#define __NR_timer_gettime              (__NR_Linux + 222)
+#define __NR_timer_getoverrun           (__NR_Linux + 223)
+#define __NR_timer_delete               (__NR_Linux + 224)
+#define __NR_clock_settime              (__NR_Linux + 225)
+#define __NR_clock_gettime              (__NR_Linux + 226)
+#define __NR_clock_getres               (__NR_Linux + 227)
+#define __NR_clock_nanosleep            (__NR_Linux + 228)
+#define __NR_tgkill                     (__NR_Linux + 229)
+#define __NR_utimes                     (__NR_Linux + 230)
+#define __NR_mbind                      (__NR_Linux + 231)
+#define __NR_get_mempolicy              (__NR_Linux + 232)
+#define __NR_set_mempolicy              (__NR_Linux + 233)
+#define __NR_mq_open                    (__NR_Linux + 234)
+#define __NR_mq_unlink                  (__NR_Linux + 235)
+#define __NR_mq_timedsend               (__NR_Linux + 236)
+#define __NR_mq_timedreceive            (__NR_Linux + 237)
+#define __NR_mq_notify                  (__NR_Linux + 238)
+#define __NR_mq_getsetattr              (__NR_Linux + 239)
+#define __NR_vserver                    (__NR_Linux + 240)
+#define __NR_waitid                     (__NR_Linux + 241)
+/* #define __NR_sys_setaltroot          (__NR_Linux + 242) */
+#define __NR_add_key                    (__NR_Linux + 243)
+#define __NR_request_key                (__NR_Linux + 244)
+#define __NR_keyctl                     (__NR_Linux + 245)
+#define __NR_set_thread_area            (__NR_Linux + 246)
+#define __NR_inotify_init               (__NR_Linux + 247)
+#define __NR_inotify_add_watch          (__NR_Linux + 248)
+#define __NR_inotify_rm_watch           (__NR_Linux + 249)
+#define __NR_migrate_pages              (__NR_Linux + 250)
+#define __NR_openat                     (__NR_Linux + 251)
+#define __NR_mkdirat                    (__NR_Linux + 252)
+#define __NR_mknodat                    (__NR_Linux + 253)
+#define __NR_fchownat                   (__NR_Linux + 254)
+#define __NR_futimesat                  (__NR_Linux + 255)
+#define __NR_newfstatat                 (__NR_Linux + 256)
+#define __NR_unlinkat                   (__NR_Linux + 257)
+#define __NR_renameat                   (__NR_Linux + 258)
+#define __NR_linkat                     (__NR_Linux + 259)
+#define __NR_symlinkat                  (__NR_Linux + 260)
+#define __NR_readlinkat                 (__NR_Linux + 261)
+#define __NR_fchmodat                   (__NR_Linux + 262)
+#define __NR_faccessat                  (__NR_Linux + 263)
+#define __NR_pselect6                   (__NR_Linux + 264)
+#define __NR_ppoll                      (__NR_Linux + 265)
+#define __NR_unshare                    (__NR_Linux + 266)
+#define __NR_splice                     (__NR_Linux + 267)
+#define __NR_sync_file_range            (__NR_Linux + 268)
+#define __NR_tee                        (__NR_Linux + 269)
+#define __NR_vmsplice                   (__NR_Linux + 270)
+#define __NR_move_pages                 (__NR_Linux + 271)
+#define __NR_set_robust_list            (__NR_Linux + 272)
+#define __NR_get_robust_list            (__NR_Linux + 273)
+#define __NR_kexec_load                 (__NR_Linux + 274)
+#define __NR_getcpu                     (__NR_Linux + 275)
+#define __NR_epoll_pwait                (__NR_Linux + 276)
+#define __NR_ioprio_set                 (__NR_Linux + 277)
+#define __NR_ioprio_get                 (__NR_Linux + 278)
+#define __NR_utimensat                  (__NR_Linux + 279)
+#define __NR_signalfd                   (__NR_Linux + 280)
+#define __NR_timerfd                    (__NR_Linux + 281)
+#define __NR_eventfd                    (__NR_Linux + 282)
+#define __NR_fallocate                  (__NR_Linux + 283)
+#define __NR_timerfd_create             (__NR_Linux + 284)
+#define __NR_timerfd_gettime            (__NR_Linux + 285)
+#define __NR_timerfd_settime            (__NR_Linux + 286)
+#define __NR_signalfd4                  (__NR_Linux + 287)
+#define __NR_eventfd2                   (__NR_Linux + 288)
+#define __NR_epoll_create1              (__NR_Linux + 289)
+#define __NR_dup3                       (__NR_Linux + 290)
+#define __NR_pipe2                      (__NR_Linux + 291)
+#define __NR_inotify_init1              (__NR_Linux + 292)
+#define __NR_preadv                     (__NR_Linux + 293)
+#define __NR_pwritev                    (__NR_Linux + 294)
+#define __NR_rt_tgsigqueueinfo          (__NR_Linux + 295)
+#define __NR_perf_event_open            (__NR_Linux + 296)
+#define __NR_accept4                    (__NR_Linux + 297)
+#define __NR_recvmmsg                   (__NR_Linux + 298)
+#define __NR_getdents64                 (__NR_Linux + 299)
+#define __NR_fanotify_init              (__NR_Linux + 300)
+#define __NR_fanotify_mark              (__NR_Linux + 301)
+#define __NR_prlimit64                  (__NR_Linux + 302)
+#define __NR_name_to_handle_at          (__NR_Linux + 303)
+#define __NR_open_by_handle_at          (__NR_Linux + 304)
+#define __NR_clock_adjtime              (__NR_Linux + 305)
+#define __NR_syncfs                     (__NR_Linux + 306)
+#define __NR_sendmmsg                   (__NR_Linux + 307)
+#define __NR_setns                      (__NR_Linux + 308)
+
+/*
+ * Offset of the last N32 flavoured syscall
+ */
+#define __NR_Linux_syscalls             308
+
+#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#define __NR_N32_Linux                  6000
+#define __NR_N32_Linux_syscalls         308
+
+#ifdef __KERNEL__
 
 #ifndef __ASSEMBLY__
 
 #define __ARCH_OMIT_COMPAT_SYS_GETDENTS64
+#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_SYS_ALARM
 #define __ARCH_WANT_SYS_GETHOSTNAME
@@ -70,4 +1081,5 @@
  */
 #define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall")
 
+#endif /* __KERNEL__ */
 #endif /* _ASM_UNISTD_H */
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 65e344532de..fa133c1bc1f 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -209,6 +209,14 @@
 #endif
 
 /*
+ * On the RM9000 there is a problem which makes the CreateDirtyExclusive
+ * eache operation unusable on SMP systems.
+ */
+#ifndef RM9000_CDEX_SMP_WAR
+#error Check setting of RM9000_CDEX_SMP_WAR for your platform
+#endif
+
+/*
  * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
  * opposes it being called that) where invalid instructions in the same
  * I-cache line worth of instructions being fetched may case spurious