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Diffstat (limited to 'arch/mips/include/asm/netlogic/xlr/gpio.h')
-rw-r--r--arch/mips/include/asm/netlogic/xlr/gpio.h59
1 files changed, 29 insertions, 30 deletions
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
index 8492e835b11..51f6ad4aeb1 100644
--- a/arch/mips/include/asm/netlogic/xlr/gpio.h
+++ b/arch/mips/include/asm/netlogic/xlr/gpio.h
@@ -35,40 +35,39 @@
35#ifndef _ASM_NLM_GPIO_H 35#ifndef _ASM_NLM_GPIO_H
36#define _ASM_NLM_GPIO_H 36#define _ASM_NLM_GPIO_H
37 37
38#define GPIO_INT_EN_REG 0 38#define NETLOGIC_GPIO_INT_EN_REG 0
39#define GPIO_INPUT_INVERSION_REG 1 39#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1
40#define GPIO_IO_DIR_REG 2 40#define NETLOGIC_GPIO_IO_DIR_REG 2
41#define GPIO_IO_DATA_WR_REG 3 41#define NETLOGIC_GPIO_IO_DATA_WR_REG 3
42#define GPIO_IO_DATA_RD_REG 4 42#define NETLOGIC_GPIO_IO_DATA_RD_REG 4
43 43
44#define GPIO_SWRESET_REG 8 44#define NETLOGIC_GPIO_SWRESET_REG 8
45#define GPIO_DRAM1_CNTRL_REG 9 45#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9
46#define GPIO_DRAM1_RATIO_REG 10 46#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10
47#define GPIO_DRAM1_RESET_REG 11 47#define NETLOGIC_GPIO_DRAM1_RESET_REG 11
48#define GPIO_DRAM1_STATUS_REG 12 48#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12
49#define GPIO_DRAM2_CNTRL_REG 13 49#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13
50#define GPIO_DRAM2_RATIO_REG 14 50#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14
51#define GPIO_DRAM2_RESET_REG 15 51#define NETLOGIC_GPIO_DRAM2_RESET_REG 15
52#define GPIO_DRAM2_STATUS_REG 16 52#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16
53 53
54#define GPIO_PWRON_RESET_CFG_REG 21 54#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21
55#define GPIO_BIST_ALL_GO_STATUS_REG 24 55#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24
56#define GPIO_BIST_CPU_GO_STATUS_REG 25 56#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25
57#define GPIO_BIST_DEV_GO_STATUS_REG 26 57#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26
58 58
59#define GPIO_FUSE_BANK_REG 35 59#define NETLOGIC_GPIO_FUSE_BANK_REG 35
60#define GPIO_CPU_RESET_REG 40 60#define NETLOGIC_GPIO_CPU_RESET_REG 40
61#define GPIO_RNG_REG 43 61#define NETLOGIC_GPIO_RNG_REG 43
62 62
63#define PWRON_RESET_PCMCIA_BOOT 17 63#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17
64#define NETLOGIC_GPIO_LED_BITMAP 0x1700000
65#define NETLOGIC_GPIO_LED_0_SHIFT 20
66#define NETLOGIC_GPIO_LED_1_SHIFT 24
64 67
65#define GPIO_LED_BITMAP 0x1700000 68#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01
66#define GPIO_LED_0_SHIFT 20 69#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
67#define GPIO_LED_1_SHIFT 24 70#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
68 71#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04
69#define GPIO_LED_OUTPUT_CODE_RESET 0x01
70#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
71#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
72#define GPIO_LED_OUTPUT_CODE_MAIN 0x04
73 72
74#endif 73#endif