diff options
Diffstat (limited to 'arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h')
| -rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 681 |
1 files changed, 20 insertions, 661 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index c3eeb90b480..0ed5230243c 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | |||
| @@ -15,30 +15,6 @@ | |||
| 15 | /* Clock Control register */ | 15 | /* Clock Control register */ |
| 16 | #define PERF_CKCTL_REG 0x4 | 16 | #define PERF_CKCTL_REG 0x4 |
| 17 | 17 | ||
| 18 | #define CKCTL_6328_PHYMIPS_EN (1 << 0) | ||
| 19 | #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) | ||
| 20 | #define CKCTL_6328_ADSL_AFE_EN (1 << 2) | ||
| 21 | #define CKCTL_6328_ADSL_EN (1 << 3) | ||
| 22 | #define CKCTL_6328_MIPS_EN (1 << 4) | ||
| 23 | #define CKCTL_6328_SAR_EN (1 << 5) | ||
| 24 | #define CKCTL_6328_PCM_EN (1 << 6) | ||
| 25 | #define CKCTL_6328_USBD_EN (1 << 7) | ||
| 26 | #define CKCTL_6328_USBH_EN (1 << 8) | ||
| 27 | #define CKCTL_6328_HSSPI_EN (1 << 9) | ||
| 28 | #define CKCTL_6328_PCIE_EN (1 << 10) | ||
| 29 | #define CKCTL_6328_ROBOSW_EN (1 << 11) | ||
| 30 | |||
| 31 | #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \ | ||
| 32 | CKCTL_6328_ADSL_QPROC_EN | \ | ||
| 33 | CKCTL_6328_ADSL_AFE_EN | \ | ||
| 34 | CKCTL_6328_ADSL_EN | \ | ||
| 35 | CKCTL_6328_SAR_EN | \ | ||
| 36 | CKCTL_6328_PCM_EN | \ | ||
| 37 | CKCTL_6328_USBD_EN | \ | ||
| 38 | CKCTL_6328_USBH_EN | \ | ||
| 39 | CKCTL_6328_ROBOSW_EN | \ | ||
| 40 | CKCTL_6328_PCIE_EN) | ||
| 41 | |||
| 42 | #define CKCTL_6338_ADSLPHY_EN (1 << 0) | 18 | #define CKCTL_6338_ADSLPHY_EN (1 << 0) |
| 43 | #define CKCTL_6338_MPI_EN (1 << 1) | 19 | #define CKCTL_6338_MPI_EN (1 << 1) |
| 44 | #define CKCTL_6338_DRAM_EN (1 << 2) | 20 | #define CKCTL_6338_DRAM_EN (1 << 2) |
| @@ -53,18 +29,13 @@ | |||
| 53 | CKCTL_6338_SAR_EN | \ | 29 | CKCTL_6338_SAR_EN | \ |
| 54 | CKCTL_6338_SPI_EN) | 30 | CKCTL_6338_SPI_EN) |
| 55 | 31 | ||
| 56 | /* BCM6345 clock bits are shifted by 16 on the left, because of the test | 32 | #define CKCTL_6345_CPU_EN (1 << 0) |
| 57 | * control register which is 16-bits wide. That way we do not have any | 33 | #define CKCTL_6345_BUS_EN (1 << 1) |
| 58 | * specific BCM6345 code for handling clocks, and writing 0 to the test | 34 | #define CKCTL_6345_EBI_EN (1 << 2) |
| 59 | * control register is fine. | 35 | #define CKCTL_6345_UART_EN (1 << 3) |
| 60 | */ | 36 | #define CKCTL_6345_ADSLPHY_EN (1 << 4) |
| 61 | #define CKCTL_6345_CPU_EN (1 << 16) | 37 | #define CKCTL_6345_ENET_EN (1 << 7) |
| 62 | #define CKCTL_6345_BUS_EN (1 << 17) | 38 | #define CKCTL_6345_USBH_EN (1 << 8) |
| 63 | #define CKCTL_6345_EBI_EN (1 << 18) | ||
| 64 | #define CKCTL_6345_UART_EN (1 << 19) | ||
| 65 | #define CKCTL_6345_ADSLPHY_EN (1 << 20) | ||
| 66 | #define CKCTL_6345_ENET_EN (1 << 23) | ||
| 67 | #define CKCTL_6345_USBH_EN (1 << 24) | ||
| 68 | 39 | ||
| 69 | #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ | 40 | #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ |
| 70 | CKCTL_6345_USBH_EN | \ | 41 | CKCTL_6345_USBH_EN | \ |
| @@ -112,104 +83,30 @@ | |||
| 112 | CKCTL_6358_USBSU_EN | \ | 83 | CKCTL_6358_USBSU_EN | \ |
| 113 | CKCTL_6358_EPHY_EN) | 84 | CKCTL_6358_EPHY_EN) |
| 114 | 85 | ||
| 115 | #define CKCTL_6368_VDSL_QPROC_EN (1 << 2) | ||
| 116 | #define CKCTL_6368_VDSL_AFE_EN (1 << 3) | ||
| 117 | #define CKCTL_6368_VDSL_BONDING_EN (1 << 4) | ||
| 118 | #define CKCTL_6368_VDSL_EN (1 << 5) | ||
| 119 | #define CKCTL_6368_PHYMIPS_EN (1 << 6) | ||
| 120 | #define CKCTL_6368_SWPKT_USB_EN (1 << 7) | ||
| 121 | #define CKCTL_6368_SWPKT_SAR_EN (1 << 8) | ||
| 122 | #define CKCTL_6368_SPI_EN (1 << 9) | ||
| 123 | #define CKCTL_6368_USBD_EN (1 << 10) | ||
| 124 | #define CKCTL_6368_SAR_EN (1 << 11) | ||
| 125 | #define CKCTL_6368_ROBOSW_EN (1 << 12) | ||
| 126 | #define CKCTL_6368_UTOPIA_EN (1 << 13) | ||
| 127 | #define CKCTL_6368_PCM_EN (1 << 14) | ||
| 128 | #define CKCTL_6368_USBH_EN (1 << 15) | ||
| 129 | #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) | ||
| 130 | #define CKCTL_6368_NAND_EN (1 << 17) | ||
| 131 | #define CKCTL_6368_IPSEC_EN (1 << 18) | ||
| 132 | |||
| 133 | #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ | ||
| 134 | CKCTL_6368_SWPKT_SAR_EN | \ | ||
| 135 | CKCTL_6368_SPI_EN | \ | ||
| 136 | CKCTL_6368_USBD_EN | \ | ||
| 137 | CKCTL_6368_SAR_EN | \ | ||
| 138 | CKCTL_6368_ROBOSW_EN | \ | ||
| 139 | CKCTL_6368_UTOPIA_EN | \ | ||
| 140 | CKCTL_6368_PCM_EN | \ | ||
| 141 | CKCTL_6368_USBH_EN | \ | ||
| 142 | CKCTL_6368_DISABLE_GLESS_EN | \ | ||
| 143 | CKCTL_6368_NAND_EN | \ | ||
| 144 | CKCTL_6368_IPSEC_EN) | ||
| 145 | |||
| 146 | /* System PLL Control register */ | 86 | /* System PLL Control register */ |
| 147 | #define PERF_SYS_PLL_CTL_REG 0x8 | 87 | #define PERF_SYS_PLL_CTL_REG 0x8 |
| 148 | #define SYS_PLL_SOFT_RESET 0x1 | 88 | #define SYS_PLL_SOFT_RESET 0x1 |
| 149 | 89 | ||
| 150 | /* Interrupt Mask register */ | 90 | /* Interrupt Mask register */ |
| 151 | #define PERF_IRQMASK_6328_REG 0x20 | 91 | #define PERF_IRQMASK_REG 0xc |
| 152 | #define PERF_IRQMASK_6338_REG 0xc | ||
| 153 | #define PERF_IRQMASK_6345_REG 0xc | ||
| 154 | #define PERF_IRQMASK_6348_REG 0xc | ||
| 155 | #define PERF_IRQMASK_6358_REG 0xc | ||
| 156 | #define PERF_IRQMASK_6368_REG 0x20 | ||
| 157 | 92 | ||
| 158 | /* Interrupt Status register */ | 93 | /* Interrupt Status register */ |
| 159 | #define PERF_IRQSTAT_6328_REG 0x28 | 94 | #define PERF_IRQSTAT_REG 0x10 |
| 160 | #define PERF_IRQSTAT_6338_REG 0x10 | ||
| 161 | #define PERF_IRQSTAT_6345_REG 0x10 | ||
| 162 | #define PERF_IRQSTAT_6348_REG 0x10 | ||
| 163 | #define PERF_IRQSTAT_6358_REG 0x10 | ||
| 164 | #define PERF_IRQSTAT_6368_REG 0x28 | ||
| 165 | 95 | ||
| 166 | /* External Interrupt Configuration register */ | 96 | /* External Interrupt Configuration register */ |
| 167 | #define PERF_EXTIRQ_CFG_REG_6328 0x18 | 97 | #define PERF_EXTIRQ_CFG_REG 0x14 |
| 168 | #define PERF_EXTIRQ_CFG_REG_6338 0x14 | ||
| 169 | #define PERF_EXTIRQ_CFG_REG_6345 0x14 | ||
| 170 | #define PERF_EXTIRQ_CFG_REG_6348 0x14 | ||
| 171 | #define PERF_EXTIRQ_CFG_REG_6358 0x14 | ||
| 172 | #define PERF_EXTIRQ_CFG_REG_6368 0x18 | ||
| 173 | |||
| 174 | #define PERF_EXTIRQ_CFG_REG2_6368 0x1c | ||
| 175 | |||
| 176 | /* for 6348 only */ | ||
| 177 | #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x)) | ||
| 178 | #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5)) | ||
| 179 | #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10)) | ||
| 180 | #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15)) | ||
| 181 | #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20)) | ||
| 182 | #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25)) | ||
| 183 | #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10) | ||
| 184 | #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15) | ||
| 185 | |||
| 186 | /* for all others */ | ||
| 187 | #define EXTIRQ_CFG_SENSE(x) (1 << (x)) | 98 | #define EXTIRQ_CFG_SENSE(x) (1 << (x)) |
| 188 | #define EXTIRQ_CFG_STAT(x) (1 << (x + 4)) | 99 | #define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) |
| 189 | #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8)) | 100 | #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) |
| 190 | #define EXTIRQ_CFG_MASK(x) (1 << (x + 12)) | 101 | #define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) |
| 191 | #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16)) | 102 | #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) |
| 192 | #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20)) | 103 | #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) |
| 193 | #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8) | 104 | |
| 194 | #define EXTIRQ_CFG_MASK_ALL (0xf << 12) | 105 | #define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) |
| 106 | #define EXTIRQ_CFG_MASK_ALL (0xf << 15) | ||
| 195 | 107 | ||
| 196 | /* Soft Reset register */ | 108 | /* Soft Reset register */ |
| 197 | #define PERF_SOFTRESET_REG 0x28 | 109 | #define PERF_SOFTRESET_REG 0x28 |
| 198 | #define PERF_SOFTRESET_6328_REG 0x10 | ||
| 199 | #define PERF_SOFTRESET_6358_REG 0x34 | ||
| 200 | #define PERF_SOFTRESET_6368_REG 0x10 | ||
| 201 | |||
| 202 | #define SOFTRESET_6328_SPI_MASK (1 << 0) | ||
| 203 | #define SOFTRESET_6328_EPHY_MASK (1 << 1) | ||
| 204 | #define SOFTRESET_6328_SAR_MASK (1 << 2) | ||
| 205 | #define SOFTRESET_6328_ENETSW_MASK (1 << 3) | ||
| 206 | #define SOFTRESET_6328_USBS_MASK (1 << 4) | ||
| 207 | #define SOFTRESET_6328_USBH_MASK (1 << 5) | ||
| 208 | #define SOFTRESET_6328_PCM_MASK (1 << 6) | ||
| 209 | #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7) | ||
| 210 | #define SOFTRESET_6328_PCIE_MASK (1 << 8) | ||
| 211 | #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9) | ||
| 212 | #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10) | ||
| 213 | 110 | ||
| 214 | #define SOFTRESET_6338_SPI_MASK (1 << 0) | 111 | #define SOFTRESET_6338_SPI_MASK (1 << 0) |
| 215 | #define SOFTRESET_6338_ENET_MASK (1 << 2) | 112 | #define SOFTRESET_6338_ENET_MASK (1 << 2) |
| @@ -250,24 +147,6 @@ | |||
| 250 | SOFTRESET_6348_ACLC_MASK | \ | 147 | SOFTRESET_6348_ACLC_MASK | \ |
| 251 | SOFTRESET_6348_ADSLMIPSPLL_MASK) | 148 | SOFTRESET_6348_ADSLMIPSPLL_MASK) |
| 252 | 149 | ||
| 253 | #define SOFTRESET_6358_SPI_MASK (1 << 0) | ||
| 254 | #define SOFTRESET_6358_ENET_MASK (1 << 2) | ||
| 255 | #define SOFTRESET_6358_MPI_MASK (1 << 3) | ||
| 256 | #define SOFTRESET_6358_EPHY_MASK (1 << 6) | ||
| 257 | #define SOFTRESET_6358_SAR_MASK (1 << 7) | ||
| 258 | #define SOFTRESET_6358_USBH_MASK (1 << 12) | ||
| 259 | #define SOFTRESET_6358_PCM_MASK (1 << 13) | ||
| 260 | #define SOFTRESET_6358_ADSL_MASK (1 << 14) | ||
| 261 | |||
| 262 | #define SOFTRESET_6368_SPI_MASK (1 << 0) | ||
| 263 | #define SOFTRESET_6368_MPI_MASK (1 << 3) | ||
| 264 | #define SOFTRESET_6368_EPHY_MASK (1 << 6) | ||
| 265 | #define SOFTRESET_6368_SAR_MASK (1 << 7) | ||
| 266 | #define SOFTRESET_6368_ENETSW_MASK (1 << 10) | ||
| 267 | #define SOFTRESET_6368_USBS_MASK (1 << 11) | ||
| 268 | #define SOFTRESET_6368_USBH_MASK (1 << 12) | ||
| 269 | #define SOFTRESET_6368_PCM_MASK (1 << 13) | ||
| 270 | |||
| 271 | /* MIPS PLL control register */ | 150 | /* MIPS PLL control register */ |
| 272 | #define PERF_MIPSPLLCTL_REG 0x34 | 151 | #define PERF_MIPSPLLCTL_REG 0x34 |
| 273 | #define MIPSPLLCTL_N1_SHIFT 20 | 152 | #define MIPSPLLCTL_N1_SHIFT 20 |
| @@ -363,8 +242,6 @@ | |||
| 363 | /* Watchdog reset length register */ | 242 | /* Watchdog reset length register */ |
| 364 | #define WDT_RSTLEN_REG 0x8 | 243 | #define WDT_RSTLEN_REG 0x8 |
| 365 | 244 | ||
| 366 | /* Watchdog soft reset register (BCM6328 only) */ | ||
| 367 | #define WDT_SOFTRESET_REG 0xc | ||
| 368 | 245 | ||
| 369 | /************************************************************************* | 246 | /************************************************************************* |
| 370 | * _REG relative to RSET_UARTx | 247 | * _REG relative to RSET_UARTx |
| @@ -495,7 +372,6 @@ | |||
| 495 | #define GPIO_CTL_LO_REG 0x4 | 372 | #define GPIO_CTL_LO_REG 0x4 |
| 496 | #define GPIO_DATA_HI_REG 0x8 | 373 | #define GPIO_DATA_HI_REG 0x8 |
| 497 | #define GPIO_DATA_LO_REG 0xC | 374 | #define GPIO_DATA_LO_REG 0xC |
| 498 | #define GPIO_DATA_LO_REG_6345 0x8 | ||
| 499 | 375 | ||
| 500 | /* GPIO mux registers and constants */ | 376 | /* GPIO mux registers and constants */ |
| 501 | #define GPIO_MODE_REG 0x18 | 377 | #define GPIO_MODE_REG 0x18 |
| @@ -526,59 +402,6 @@ | |||
| 526 | #define GPIO_MODE_6358_SERIAL_LED (1 << 10) | 402 | #define GPIO_MODE_6358_SERIAL_LED (1 << 10) |
| 527 | #define GPIO_MODE_6358_UTOPIA (1 << 12) | 403 | #define GPIO_MODE_6358_UTOPIA (1 << 12) |
| 528 | 404 | ||
| 529 | #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0) | ||
| 530 | #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1) | ||
| 531 | #define GPIO_MODE_6368_SYS_IRQ (1 << 2) | ||
| 532 | #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3) | ||
| 533 | #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4) | ||
| 534 | #define GPIO_MODE_6368_INET_LED (1 << 5) | ||
| 535 | #define GPIO_MODE_6368_EPHY0_LED (1 << 6) | ||
| 536 | #define GPIO_MODE_6368_EPHY1_LED (1 << 7) | ||
| 537 | #define GPIO_MODE_6368_EPHY2_LED (1 << 8) | ||
| 538 | #define GPIO_MODE_6368_EPHY3_LED (1 << 9) | ||
| 539 | #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10) | ||
| 540 | #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11) | ||
| 541 | #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12) | ||
| 542 | #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13) | ||
| 543 | #define GPIO_MODE_6368_USBD_LED (1 << 14) | ||
| 544 | #define GPIO_MODE_6368_NTR_PULSE (1 << 15) | ||
| 545 | #define GPIO_MODE_6368_PCI_REQ1 (1 << 16) | ||
| 546 | #define GPIO_MODE_6368_PCI_GNT1 (1 << 17) | ||
| 547 | #define GPIO_MODE_6368_PCI_INTB (1 << 18) | ||
| 548 | #define GPIO_MODE_6368_PCI_REQ0 (1 << 19) | ||
| 549 | #define GPIO_MODE_6368_PCI_GNT0 (1 << 20) | ||
| 550 | #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22) | ||
| 551 | #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23) | ||
| 552 | #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24) | ||
| 553 | #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25) | ||
| 554 | #define GPIO_MODE_6368_EBI_CS2 (1 << 26) | ||
| 555 | #define GPIO_MODE_6368_EBI_CS3 (1 << 27) | ||
| 556 | #define GPIO_MODE_6368_SPI_SSN2 (1 << 28) | ||
| 557 | #define GPIO_MODE_6368_SPI_SSN3 (1 << 29) | ||
| 558 | #define GPIO_MODE_6368_SPI_SSN4 (1 << 30) | ||
| 559 | #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) | ||
| 560 | |||
| 561 | |||
| 562 | #define GPIO_PINMUX_OTHR_REG 0x24 | ||
| 563 | #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 | ||
| 564 | #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) | ||
| 565 | #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) | ||
| 566 | #define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) | ||
| 567 | |||
| 568 | #define GPIO_BASEMODE_6368_REG 0x38 | ||
| 569 | #define GPIO_BASEMODE_6368_UART2 0x1 | ||
| 570 | #define GPIO_BASEMODE_6368_GPIO 0x0 | ||
| 571 | #define GPIO_BASEMODE_6368_MASK 0x7 | ||
| 572 | /* those bits must be kept as read in gpio basemode register*/ | ||
| 573 | |||
| 574 | #define GPIO_STRAPBUS_REG 0x40 | ||
| 575 | #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) | ||
| 576 | #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) | ||
| 577 | #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 | ||
| 578 | #define STRAPBUS_6368_BOOT_SEL_NAND 0 | ||
| 579 | #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 | ||
| 580 | #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 | ||
| 581 | |||
| 582 | 405 | ||
| 583 | /************************************************************************* | 406 | /************************************************************************* |
| 584 | * _REG relative to RSET_ENET | 407 | * _REG relative to RSET_ENET |
| @@ -692,12 +515,6 @@ | |||
| 692 | #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 | 515 | #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 |
| 693 | #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) | 516 | #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) |
| 694 | 517 | ||
| 695 | /* Global interrupt status */ | ||
| 696 | #define ENETDMA_GLB_IRQSTAT_REG (0x40) | ||
| 697 | |||
| 698 | /* Global interrupt mask */ | ||
| 699 | #define ENETDMA_GLB_IRQMASK_REG (0x44) | ||
| 700 | |||
| 701 | /* Channel Configuration register */ | 518 | /* Channel Configuration register */ |
| 702 | #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) | 519 | #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) |
| 703 | #define ENETDMA_CHANCFG_EN_SHIFT 0 | 520 | #define ENETDMA_CHANCFG_EN_SHIFT 0 |
| @@ -731,58 +548,6 @@ | |||
| 731 | 548 | ||
| 732 | 549 | ||
| 733 | /************************************************************************* | 550 | /************************************************************************* |
| 734 | * _REG relative to RSET_ENETDMAC | ||
| 735 | *************************************************************************/ | ||
| 736 | |||
| 737 | /* Channel Configuration register */ | ||
| 738 | #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) | ||
| 739 | #define ENETDMAC_CHANCFG_EN_SHIFT 0 | ||
| 740 | #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) | ||
| 741 | #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 | ||
| 742 | #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) | ||
| 743 | #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 | ||
| 744 | #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) | ||
| 745 | |||
| 746 | /* Interrupt Control/Status register */ | ||
| 747 | #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) | ||
| 748 | #define ENETDMAC_IR_BUFDONE_MASK (1 << 0) | ||
| 749 | #define ENETDMAC_IR_PKTDONE_MASK (1 << 1) | ||
| 750 | #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2) | ||
| 751 | |||
| 752 | /* Interrupt Mask register */ | ||
| 753 | #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10) | ||
| 754 | |||
| 755 | /* Maximum Burst Length */ | ||
| 756 | #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10) | ||
| 757 | |||
| 758 | |||
| 759 | /************************************************************************* | ||
| 760 | * _REG relative to RSET_ENETDMAS | ||
| 761 | *************************************************************************/ | ||
| 762 | |||
| 763 | /* Ring Start Address register */ | ||
| 764 | #define ENETDMAS_RSTART_REG(x) ((x) * 0x10) | ||
| 765 | |||
| 766 | /* State Ram Word 2 */ | ||
| 767 | #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10) | ||
| 768 | |||
| 769 | /* State Ram Word 3 */ | ||
| 770 | #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10) | ||
| 771 | |||
| 772 | /* State Ram Word 4 */ | ||
| 773 | #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10) | ||
| 774 | |||
| 775 | |||
| 776 | /************************************************************************* | ||
| 777 | * _REG relative to RSET_ENETSW | ||
| 778 | *************************************************************************/ | ||
| 779 | |||
| 780 | /* MIB register */ | ||
| 781 | #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4) | ||
| 782 | #define ENETSW_MIB_REG_COUNT 47 | ||
| 783 | |||
| 784 | |||
| 785 | /************************************************************************* | ||
| 786 | * _REG relative to RSET_OHCI_PRIV | 551 | * _REG relative to RSET_OHCI_PRIV |
| 787 | *************************************************************************/ | 552 | *************************************************************************/ |
| 788 | 553 | ||
| @@ -797,11 +562,7 @@ | |||
| 797 | * _REG relative to RSET_USBH_PRIV | 562 | * _REG relative to RSET_USBH_PRIV |
| 798 | *************************************************************************/ | 563 | *************************************************************************/ |
| 799 | 564 | ||
| 800 | #define USBH_PRIV_SWAP_6358_REG 0x0 | 565 | #define USBH_PRIV_SWAP_REG 0x0 |
| 801 | #define USBH_PRIV_SWAP_6368_REG 0x1c | ||
| 802 | |||
| 803 | #define USBH_PRIV_SWAP_USBD_SHIFT 6 | ||
| 804 | #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) | ||
| 805 | #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 | 566 | #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 |
| 806 | #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) | 567 | #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) |
| 807 | #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 | 568 | #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 |
| @@ -811,160 +572,7 @@ | |||
| 811 | #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 | 572 | #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 |
| 812 | #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) | 573 | #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) |
| 813 | 574 | ||
| 814 | #define USBH_PRIV_UTMI_CTL_6368_REG 0x10 | 575 | #define USBH_PRIV_TEST_REG 0x24 |
| 815 | #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 | ||
| 816 | #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT) | ||
| 817 | #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0 | ||
| 818 | #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT) | ||
| 819 | |||
| 820 | #define USBH_PRIV_TEST_6358_REG 0x24 | ||
| 821 | #define USBH_PRIV_TEST_6368_REG 0x14 | ||
| 822 | |||
| 823 | #define USBH_PRIV_SETUP_6368_REG 0x28 | ||
| 824 | #define USBH_PRIV_SETUP_IOC_SHIFT 4 | ||
| 825 | #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) | ||
| 826 | |||
| 827 | |||
| 828 | /************************************************************************* | ||
| 829 | * _REG relative to RSET_USBD | ||
| 830 | *************************************************************************/ | ||
| 831 | |||
| 832 | /* General control */ | ||
| 833 | #define USBD_CONTROL_REG 0x00 | ||
| 834 | #define USBD_CONTROL_TXZLENINS_SHIFT 14 | ||
| 835 | #define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT) | ||
| 836 | #define USBD_CONTROL_AUTO_CSRS_SHIFT 13 | ||
| 837 | #define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT) | ||
| 838 | #define USBD_CONTROL_RXZSCFG_SHIFT 12 | ||
| 839 | #define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT) | ||
| 840 | #define USBD_CONTROL_INIT_SEL_SHIFT 8 | ||
| 841 | #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT) | ||
| 842 | #define USBD_CONTROL_FIFO_RESET_SHIFT 6 | ||
| 843 | #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT) | ||
| 844 | #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 | ||
| 845 | #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT) | ||
| 846 | #define USBD_CONTROL_DONE_CSRS_SHIFT 0 | ||
| 847 | #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT) | ||
| 848 | |||
| 849 | /* Strap options */ | ||
| 850 | #define USBD_STRAPS_REG 0x04 | ||
| 851 | #define USBD_STRAPS_APP_SELF_PWR_SHIFT 10 | ||
| 852 | #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT) | ||
| 853 | #define USBD_STRAPS_APP_DISCON_SHIFT 9 | ||
| 854 | #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT) | ||
| 855 | #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 | ||
| 856 | #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT) | ||
| 857 | #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6 | ||
| 858 | #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT) | ||
| 859 | #define USBD_STRAPS_APP_RAM_IF_SHIFT 7 | ||
| 860 | #define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT) | ||
| 861 | #define USBD_STRAPS_APP_8BITPHY_SHIFT 2 | ||
| 862 | #define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT) | ||
| 863 | #define USBD_STRAPS_SPEED_SHIFT 0 | ||
| 864 | #define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT) | ||
| 865 | |||
| 866 | /* Stall control */ | ||
| 867 | #define USBD_STALL_REG 0x08 | ||
| 868 | #define USBD_STALL_UPDATE_SHIFT 7 | ||
| 869 | #define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT) | ||
| 870 | #define USBD_STALL_ENABLE_SHIFT 6 | ||
| 871 | #define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT) | ||
| 872 | #define USBD_STALL_EPNUM_SHIFT 0 | ||
| 873 | #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT) | ||
| 874 | |||
| 875 | /* General status */ | ||
| 876 | #define USBD_STATUS_REG 0x0c | ||
| 877 | #define USBD_STATUS_SOF_SHIFT 16 | ||
| 878 | #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT) | ||
| 879 | #define USBD_STATUS_SPD_SHIFT 12 | ||
| 880 | #define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT) | ||
| 881 | #define USBD_STATUS_ALTINTF_SHIFT 8 | ||
| 882 | #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT) | ||
| 883 | #define USBD_STATUS_INTF_SHIFT 4 | ||
| 884 | #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT) | ||
| 885 | #define USBD_STATUS_CFG_SHIFT 0 | ||
| 886 | #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT) | ||
| 887 | |||
| 888 | /* Other events */ | ||
| 889 | #define USBD_EVENTS_REG 0x10 | ||
| 890 | #define USBD_EVENTS_USB_LINK_SHIFT 10 | ||
| 891 | #define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT) | ||
| 892 | |||
| 893 | /* IRQ status */ | ||
| 894 | #define USBD_EVENT_IRQ_STATUS_REG 0x14 | ||
| 895 | |||
| 896 | /* IRQ level (2 bits per IRQ event) */ | ||
| 897 | #define USBD_EVENT_IRQ_CFG_HI_REG 0x18 | ||
| 898 | |||
| 899 | #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c | ||
| 900 | |||
| 901 | #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1) | ||
| 902 | #define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x)) | ||
| 903 | #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x)) | ||
| 904 | #define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x)) | ||
| 905 | |||
| 906 | /* IRQ mask (1=unmasked) */ | ||
| 907 | #define USBD_EVENT_IRQ_MASK_REG 0x20 | ||
| 908 | |||
| 909 | /* IRQ bits */ | ||
| 910 | #define USBD_EVENT_IRQ_USB_LINK 10 | ||
| 911 | #define USBD_EVENT_IRQ_SETCFG 9 | ||
| 912 | #define USBD_EVENT_IRQ_SETINTF 8 | ||
| 913 | #define USBD_EVENT_IRQ_ERRATIC_ERR 7 | ||
| 914 | #define USBD_EVENT_IRQ_SET_CSRS 6 | ||
| 915 | #define USBD_EVENT_IRQ_SUSPEND 5 | ||
| 916 | #define USBD_EVENT_IRQ_EARLY_SUSPEND 4 | ||
| 917 | #define USBD_EVENT_IRQ_SOF 3 | ||
| 918 | #define USBD_EVENT_IRQ_ENUM_ON 2 | ||
| 919 | #define USBD_EVENT_IRQ_SETUP 1 | ||
| 920 | #define USBD_EVENT_IRQ_USB_RESET 0 | ||
| 921 | |||
| 922 | /* TX FIFO partitioning */ | ||
| 923 | #define USBD_TXFIFO_CONFIG_REG 0x40 | ||
| 924 | #define USBD_TXFIFO_CONFIG_END_SHIFT 16 | ||
| 925 | #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) | ||
| 926 | #define USBD_TXFIFO_CONFIG_START_SHIFT 0 | ||
| 927 | #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) | ||
| 928 | |||
| 929 | /* RX FIFO partitioning */ | ||
| 930 | #define USBD_RXFIFO_CONFIG_REG 0x44 | ||
| 931 | #define USBD_RXFIFO_CONFIG_END_SHIFT 16 | ||
| 932 | #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) | ||
| 933 | #define USBD_RXFIFO_CONFIG_START_SHIFT 0 | ||
| 934 | #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) | ||
| 935 | |||
| 936 | /* TX FIFO/endpoint configuration */ | ||
| 937 | #define USBD_TXFIFO_EPSIZE_REG 0x48 | ||
| 938 | |||
| 939 | /* RX FIFO/endpoint configuration */ | ||
| 940 | #define USBD_RXFIFO_EPSIZE_REG 0x4c | ||
| 941 | |||
| 942 | /* Endpoint<->DMA mappings */ | ||
| 943 | #define USBD_EPNUM_TYPEMAP_REG 0x50 | ||
| 944 | #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8 | ||
| 945 | #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) | ||
| 946 | #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 | ||
| 947 | #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT) | ||
| 948 | |||
| 949 | /* Misc per-endpoint settings */ | ||
| 950 | #define USBD_CSR_SETUPADDR_REG 0x80 | ||
| 951 | #define USBD_CSR_SETUPADDR_DEF 0xb550 | ||
| 952 | |||
| 953 | #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4) | ||
| 954 | #define USBD_CSR_EP_MAXPKT_SHIFT 19 | ||
| 955 | #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT) | ||
| 956 | #define USBD_CSR_EP_ALTIFACE_SHIFT 15 | ||
| 957 | #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT) | ||
| 958 | #define USBD_CSR_EP_IFACE_SHIFT 11 | ||
| 959 | #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT) | ||
| 960 | #define USBD_CSR_EP_CFG_SHIFT 7 | ||
| 961 | #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT) | ||
| 962 | #define USBD_CSR_EP_TYPE_SHIFT 5 | ||
| 963 | #define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT) | ||
| 964 | #define USBD_CSR_EP_DIR_SHIFT 4 | ||
| 965 | #define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT) | ||
| 966 | #define USBD_CSR_EP_LOG_SHIFT 0 | ||
| 967 | #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT) | ||
| 968 | 576 | ||
| 969 | 577 | ||
| 970 | /************************************************************************* | 578 | /************************************************************************* |
| @@ -1126,8 +734,6 @@ | |||
| 1126 | #define SDRAM_CFG_BANK_SHIFT 13 | 734 | #define SDRAM_CFG_BANK_SHIFT 13 |
| 1127 | #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) | 735 | #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) |
| 1128 | 736 | ||
| 1129 | #define SDRAM_MBASE_REG 0xc | ||
| 1130 | |||
| 1131 | #define SDRAM_PRIO_REG 0x2C | 737 | #define SDRAM_PRIO_REG 0x2C |
| 1132 | #define SDRAM_PRIO_MIPS_SHIFT 29 | 738 | #define SDRAM_PRIO_MIPS_SHIFT 29 |
| 1133 | #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) | 739 | #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) |
| @@ -1154,8 +760,6 @@ | |||
| 1154 | * _REG relative to RSET_DDR | 760 | * _REG relative to RSET_DDR |
| 1155 | *************************************************************************/ | 761 | *************************************************************************/ |
| 1156 | 762 | ||
| 1157 | #define DDR_CSEND_REG 0x8 | ||
| 1158 | |||
| 1159 | #define DDR_DMIPSPLLCFG_REG 0x18 | 763 | #define DDR_DMIPSPLLCFG_REG 0x18 |
| 1160 | #define DMIPSPLLCFG_M1_SHIFT 0 | 764 | #define DMIPSPLLCFG_M1_SHIFT 0 |
| 1161 | #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) | 765 | #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) |
| @@ -1164,249 +768,4 @@ | |||
| 1164 | #define DMIPSPLLCFG_N2_SHIFT 29 | 768 | #define DMIPSPLLCFG_N2_SHIFT 29 |
| 1165 | #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) | 769 | #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) |
| 1166 | 770 | ||
| 1167 | #define DDR_DMIPSPLLCFG_6368_REG 0x20 | ||
| 1168 | #define DMIPSPLLCFG_6368_P1_SHIFT 0 | ||
| 1169 | #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) | ||
| 1170 | #define DMIPSPLLCFG_6368_P2_SHIFT 4 | ||
| 1171 | #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT) | ||
| 1172 | #define DMIPSPLLCFG_6368_NDIV_SHIFT 16 | ||
| 1173 | #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT) | ||
| 1174 | |||
| 1175 | #define DDR_DMIPSPLLDIV_6368_REG 0x24 | ||
| 1176 | #define DMIPSPLLDIV_6368_MDIV_SHIFT 0 | ||
| 1177 | #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT) | ||
| 1178 | |||
| 1179 | |||
| 1180 | /************************************************************************* | ||
| 1181 | * _REG relative to RSET_M2M | ||
| 1182 | *************************************************************************/ | ||
| 1183 | |||
| 1184 | #define M2M_RX 0 | ||
| 1185 | #define M2M_TX 1 | ||
| 1186 | |||
| 1187 | #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00) | ||
| 1188 | #define M2M_DST_REG(x) ((x) * 0x40 + 0x04) | ||
| 1189 | #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08) | ||
| 1190 | |||
| 1191 | #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c) | ||
| 1192 | #define M2M_CTRL_ENABLE_MASK (1 << 0) | ||
| 1193 | #define M2M_CTRL_IRQEN_MASK (1 << 1) | ||
| 1194 | #define M2M_CTRL_ERROR_CLR_MASK (1 << 6) | ||
| 1195 | #define M2M_CTRL_DONE_CLR_MASK (1 << 7) | ||
| 1196 | #define M2M_CTRL_NOINC_MASK (1 << 8) | ||
| 1197 | #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9) | ||
| 1198 | #define M2M_CTRL_SWAPBYTE_MASK (1 << 10) | ||
| 1199 | #define M2M_CTRL_ENDIAN_MASK (1 << 11) | ||
| 1200 | |||
| 1201 | #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10) | ||
| 1202 | #define M2M_STAT_DONE (1 << 0) | ||
| 1203 | #define M2M_STAT_ERROR (1 << 1) | ||
| 1204 | |||
| 1205 | #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) | ||
| 1206 | #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) | ||
| 1207 | |||
| 1208 | /************************************************************************* | ||
| 1209 | * _REG relative to RSET_RNG | ||
| 1210 | *************************************************************************/ | ||
| 1211 | |||
| 1212 | #define RNG_CTRL 0x00 | ||
| 1213 | #define RNG_EN (1 << 0) | ||
| 1214 | |||
| 1215 | #define RNG_STAT 0x04 | ||
| 1216 | #define RNG_AVAIL_MASK (0xff000000) | ||
| 1217 | |||
| 1218 | #define RNG_DATA 0x08 | ||
| 1219 | #define RNG_THRES 0x0c | ||
| 1220 | #define RNG_MASK 0x10 | ||
| 1221 | |||
| 1222 | /************************************************************************* | ||
| 1223 | * _REG relative to RSET_SPI | ||
| 1224 | *************************************************************************/ | ||
| 1225 | |||
| 1226 | /* BCM 6338 SPI core */ | ||
| 1227 | #define SPI_6338_CMD 0x00 /* 16-bits register */ | ||
| 1228 | #define SPI_6338_INT_STATUS 0x02 | ||
| 1229 | #define SPI_6338_INT_MASK_ST 0x03 | ||
| 1230 | #define SPI_6338_INT_MASK 0x04 | ||
| 1231 | #define SPI_6338_ST 0x05 | ||
| 1232 | #define SPI_6338_CLK_CFG 0x06 | ||
| 1233 | #define SPI_6338_FILL_BYTE 0x07 | ||
| 1234 | #define SPI_6338_MSG_TAIL 0x09 | ||
| 1235 | #define SPI_6338_RX_TAIL 0x0b | ||
| 1236 | #define SPI_6338_MSG_CTL 0x40 /* 8-bits register */ | ||
| 1237 | #define SPI_6338_MSG_CTL_WIDTH 8 | ||
| 1238 | #define SPI_6338_MSG_DATA 0x41 | ||
| 1239 | #define SPI_6338_MSG_DATA_SIZE 0x3f | ||
| 1240 | #define SPI_6338_RX_DATA 0x80 | ||
| 1241 | #define SPI_6338_RX_DATA_SIZE 0x3f | ||
| 1242 | |||
| 1243 | /* BCM 6348 SPI core */ | ||
| 1244 | #define SPI_6348_CMD 0x00 /* 16-bits register */ | ||
| 1245 | #define SPI_6348_INT_STATUS 0x02 | ||
| 1246 | #define SPI_6348_INT_MASK_ST 0x03 | ||
| 1247 | #define SPI_6348_INT_MASK 0x04 | ||
| 1248 | #define SPI_6348_ST 0x05 | ||
| 1249 | #define SPI_6348_CLK_CFG 0x06 | ||
| 1250 | #define SPI_6348_FILL_BYTE 0x07 | ||
| 1251 | #define SPI_6348_MSG_TAIL 0x09 | ||
| 1252 | #define SPI_6348_RX_TAIL 0x0b | ||
| 1253 | #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */ | ||
| 1254 | #define SPI_6348_MSG_CTL_WIDTH 8 | ||
| 1255 | #define SPI_6348_MSG_DATA 0x41 | ||
| 1256 | #define SPI_6348_MSG_DATA_SIZE 0x3f | ||
| 1257 | #define SPI_6348_RX_DATA 0x80 | ||
| 1258 | #define SPI_6348_RX_DATA_SIZE 0x3f | ||
| 1259 | |||
| 1260 | /* BCM 6358 SPI core */ | ||
| 1261 | #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ | ||
| 1262 | #define SPI_6358_MSG_CTL_WIDTH 16 | ||
| 1263 | #define SPI_6358_MSG_DATA 0x02 | ||
| 1264 | #define SPI_6358_MSG_DATA_SIZE 0x21e | ||
| 1265 | #define SPI_6358_RX_DATA 0x400 | ||
| 1266 | #define SPI_6358_RX_DATA_SIZE 0x220 | ||
| 1267 | #define SPI_6358_CMD 0x700 /* 16-bits register */ | ||
| 1268 | #define SPI_6358_INT_STATUS 0x702 | ||
| 1269 | #define SPI_6358_INT_MASK_ST 0x703 | ||
| 1270 | #define SPI_6358_INT_MASK 0x704 | ||
| 1271 | #define SPI_6358_ST 0x705 | ||
| 1272 | #define SPI_6358_CLK_CFG 0x706 | ||
| 1273 | #define SPI_6358_FILL_BYTE 0x707 | ||
| 1274 | #define SPI_6358_MSG_TAIL 0x709 | ||
| 1275 | #define SPI_6358_RX_TAIL 0x70B | ||
| 1276 | |||
| 1277 | /* BCM 6358 SPI core */ | ||
| 1278 | #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */ | ||
| 1279 | #define SPI_6368_MSG_CTL_WIDTH 16 | ||
| 1280 | #define SPI_6368_MSG_DATA 0x02 | ||
| 1281 | #define SPI_6368_MSG_DATA_SIZE 0x21e | ||
| 1282 | #define SPI_6368_RX_DATA 0x400 | ||
| 1283 | #define SPI_6368_RX_DATA_SIZE 0x220 | ||
| 1284 | #define SPI_6368_CMD 0x700 /* 16-bits register */ | ||
| 1285 | #define SPI_6368_INT_STATUS 0x702 | ||
| 1286 | #define SPI_6368_INT_MASK_ST 0x703 | ||
| 1287 | #define SPI_6368_INT_MASK 0x704 | ||
| 1288 | #define SPI_6368_ST 0x705 | ||
| 1289 | #define SPI_6368_CLK_CFG 0x706 | ||
| 1290 | #define SPI_6368_FILL_BYTE 0x707 | ||
| 1291 | #define SPI_6368_MSG_TAIL 0x709 | ||
| 1292 | #define SPI_6368_RX_TAIL 0x70B | ||
| 1293 | |||
| 1294 | /* Shared SPI definitions */ | ||
| 1295 | |||
| 1296 | /* Message configuration */ | ||
| 1297 | #define SPI_FD_RW 0x00 | ||
| 1298 | #define SPI_HD_W 0x01 | ||
| 1299 | #define SPI_HD_R 0x02 | ||
| 1300 | #define SPI_BYTE_CNT_SHIFT 0 | ||
| 1301 | #define SPI_6338_MSG_TYPE_SHIFT 6 | ||
| 1302 | #define SPI_6348_MSG_TYPE_SHIFT 6 | ||
| 1303 | #define SPI_6358_MSG_TYPE_SHIFT 14 | ||
| 1304 | #define SPI_6368_MSG_TYPE_SHIFT 14 | ||
| 1305 | |||
| 1306 | /* Command */ | ||
| 1307 | #define SPI_CMD_NOOP 0x00 | ||
| 1308 | #define SPI_CMD_SOFT_RESET 0x01 | ||
| 1309 | #define SPI_CMD_HARD_RESET 0x02 | ||
| 1310 | #define SPI_CMD_START_IMMEDIATE 0x03 | ||
| 1311 | #define SPI_CMD_COMMAND_SHIFT 0 | ||
| 1312 | #define SPI_CMD_COMMAND_MASK 0x000f | ||
| 1313 | #define SPI_CMD_DEVICE_ID_SHIFT 4 | ||
| 1314 | #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 | ||
| 1315 | #define SPI_CMD_ONE_BYTE_SHIFT 11 | ||
| 1316 | #define SPI_CMD_ONE_WIRE_SHIFT 12 | ||
| 1317 | #define SPI_DEV_ID_0 0 | ||
| 1318 | #define SPI_DEV_ID_1 1 | ||
| 1319 | #define SPI_DEV_ID_2 2 | ||
| 1320 | #define SPI_DEV_ID_3 3 | ||
| 1321 | |||
| 1322 | /* Interrupt mask */ | ||
| 1323 | #define SPI_INTR_CMD_DONE 0x01 | ||
| 1324 | #define SPI_INTR_RX_OVERFLOW 0x02 | ||
| 1325 | #define SPI_INTR_TX_UNDERFLOW 0x04 | ||
| 1326 | #define SPI_INTR_TX_OVERFLOW 0x08 | ||
| 1327 | #define SPI_INTR_RX_UNDERFLOW 0x10 | ||
| 1328 | #define SPI_INTR_CLEAR_ALL 0x1f | ||
| 1329 | |||
| 1330 | /* Status */ | ||
| 1331 | #define SPI_RX_EMPTY 0x02 | ||
| 1332 | #define SPI_CMD_BUSY 0x04 | ||
| 1333 | #define SPI_SERIAL_BUSY 0x08 | ||
| 1334 | |||
| 1335 | /* Clock configuration */ | ||
| 1336 | #define SPI_CLK_20MHZ 0x00 | ||
| 1337 | #define SPI_CLK_0_391MHZ 0x01 | ||
| 1338 | #define SPI_CLK_0_781MHZ 0x02 /* default */ | ||
| 1339 | #define SPI_CLK_1_563MHZ 0x03 | ||
| 1340 | #define SPI_CLK_3_125MHZ 0x04 | ||
| 1341 | #define SPI_CLK_6_250MHZ 0x05 | ||
| 1342 | #define SPI_CLK_12_50MHZ 0x06 | ||
| 1343 | #define SPI_CLK_MASK 0x07 | ||
| 1344 | #define SPI_SSOFFTIME_MASK 0x38 | ||
| 1345 | #define SPI_SSOFFTIME_SHIFT 3 | ||
| 1346 | #define SPI_BYTE_SWAP 0x80 | ||
| 1347 | |||
| 1348 | /************************************************************************* | ||
| 1349 | * _REG relative to RSET_MISC | ||
| 1350 | *************************************************************************/ | ||
| 1351 | #define MISC_SERDES_CTRL_REG 0x0 | ||
| 1352 | #define SERDES_PCIE_EN (1 << 0) | ||
| 1353 | #define SERDES_PCIE_EXD_EN (1 << 15) | ||
| 1354 | |||
| 1355 | #define MISC_STRAPBUS_6328_REG 0x240 | ||
| 1356 | #define STRAPBUS_6328_FCVO_SHIFT 7 | ||
| 1357 | #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) | ||
| 1358 | #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) | ||
| 1359 | #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28) | ||
| 1360 | |||
| 1361 | /************************************************************************* | ||
| 1362 | * _REG relative to RSET_PCIE | ||
| 1363 | *************************************************************************/ | ||
| 1364 | |||
| 1365 | #define PCIE_CONFIG2_REG 0x408 | ||
| 1366 | #define CONFIG2_BAR1_SIZE_EN 1 | ||
| 1367 | #define CONFIG2_BAR1_SIZE_MASK 0xf | ||
| 1368 | |||
| 1369 | #define PCIE_IDVAL3_REG 0x43c | ||
| 1370 | #define IDVAL3_CLASS_CODE_MASK 0xffffff | ||
| 1371 | #define IDVAL3_SUBCLASS_SHIFT 8 | ||
| 1372 | #define IDVAL3_CLASS_SHIFT 16 | ||
| 1373 | |||
| 1374 | #define PCIE_DLSTATUS_REG 0x1048 | ||
| 1375 | #define DLSTATUS_PHYLINKUP (1 << 13) | ||
| 1376 | |||
| 1377 | #define PCIE_BRIDGE_OPT1_REG 0x2820 | ||
| 1378 | #define OPT1_RD_BE_OPT_EN (1 << 7) | ||
| 1379 | #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9) | ||
| 1380 | #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11) | ||
| 1381 | #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12) | ||
| 1382 | |||
| 1383 | #define PCIE_BRIDGE_OPT2_REG 0x2824 | ||
| 1384 | #define OPT2_UBUS_UR_DECODE_DIS (1 << 2) | ||
| 1385 | #define OPT2_TX_CREDIT_CHK_EN (1 << 4) | ||
| 1386 | #define OPT2_CFG_TYPE1_BD_SEL (1 << 7) | ||
| 1387 | #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16 | ||
| 1388 | #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT) | ||
| 1389 | |||
| 1390 | #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828 | ||
| 1391 | #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830 | ||
| 1392 | #define BASEMASK_REMAP_EN (1 << 0) | ||
| 1393 | #define BASEMASK_SWAP_EN (1 << 1) | ||
| 1394 | #define BASEMASK_MASK_SHIFT 4 | ||
| 1395 | #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT) | ||
| 1396 | #define BASEMASK_BASE_SHIFT 20 | ||
| 1397 | #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT) | ||
| 1398 | |||
| 1399 | #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c | ||
| 1400 | #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834 | ||
| 1401 | #define REBASE_ADDR_BASE_SHIFT 20 | ||
| 1402 | #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT) | ||
| 1403 | |||
| 1404 | #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854 | ||
| 1405 | #define PCIE_RC_INT_A (1 << 0) | ||
| 1406 | #define PCIE_RC_INT_B (1 << 1) | ||
| 1407 | #define PCIE_RC_INT_C (1 << 2) | ||
| 1408 | #define PCIE_RC_INT_D (1 << 3) | ||
| 1409 | |||
| 1410 | #define PCIE_DEVICE_OFFSET 0x8000 | ||
| 1411 | |||
| 1412 | #endif /* BCM63XX_REGS_H_ */ | 771 | #endif /* BCM63XX_REGS_H_ */ |