1 files changed, 10 insertions, 23 deletions

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 7e4e6f8fab3..6a6f8a8f542 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -240,7 +240,7 @@
 #define PM_HUGE_MASK    PM_64M
 #elif defined(CONFIG_PAGE_SIZE_64KB)
 #define PM_HUGE_MASK    PM_256M
-#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+#elif defined(CONFIG_HUGETLB_PAGE)
 #error Bad page size configuration for hugetlbfs!
 #endif
 
@@ -458,8 +458,6 @@
 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 #define  CAUSEB_IV              23
 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
-#define  CAUSEB_PCI             26
-#define  CAUSEF_PCI             (_ULCAST_(1)   << 26)
 #define  CAUSEB_CE              28
 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 #define  CAUSEB_TI              30
@@ -592,16 +590,12 @@
 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
-#define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
-#define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 
 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 
-#define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
-
 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 
 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
@@ -977,6 +971,10 @@ do {									\
 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
 
+/* RM9000 PerfControl performance counter control register */
+#define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
+#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
+
 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
 
@@ -1008,26 +1006,22 @@ do {									\
 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
-#define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
-#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
-#define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
-#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
-#define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
-#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
-#define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
-#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
+
+/* RM9000 PerfCount performance counter register */
+#define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
+#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
 
 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
@@ -1104,7 +1098,7 @@ do {									\
 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
 
-/* BMIPS43xx */
+/* BMIPS4380 */
 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
 
@@ -1665,13 +1659,6 @@ __BUILD_SET_C0(config)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
-__BUILD_SET_C0(brcm_config_0)
-__BUILD_SET_C0(brcm_bus_pll)
-__BUILD_SET_C0(brcm_reset)
-__BUILD_SET_C0(brcm_cmt_intr)
-__BUILD_SET_C0(brcm_cmt_ctrl)
-__BUILD_SET_C0(brcm_config)
-__BUILD_SET_C0(brcm_mode)
 
 #endif /* !__ASSEMBLY__ */