1533 files changed, 96291 insertions, 13327 deletions

diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c
index 83df541650fc..06b6fdab639f 100644
--- a/arch/alpha/kernel/smp.c
+++ b/arch/alpha/kernel/smp.c
@@ -149,6 +149,9 @@ smp_callin(void)
         atomic_inc(&init_mm.mm_count);
         current->active_mm = &init_mm;
 
+        /* inform the notifiers about the new cpu */
+        notify_cpu_starting(cpuid);
+
         /* Must have completely accurate bogos.  */
         local_irq_enable();
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 70dba1668907..efeed65b4a66 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -148,7 +148,6 @@ config ARCH_MAY_HAVE_PC_FDC
 
 config ZONE_DMA
         bool
-        default y
 
 config GENERIC_ISA_DMA
         bool
@@ -178,6 +177,11 @@ config OPROFILE_MPCORE
 config OPROFILE_ARM11_CORE
         bool
 
+config OPROFILE_ARMV7
+        def_bool y
+        depends on CPU_V7 && !SMP
+        bool
+
 endif
 
 config VECTORS_BASE
@@ -245,6 +249,7 @@ config ARCH_CLPS7500
         select TIMER_ACORN
         select ISA
         select NO_IOPORT
+        select ARCH_SPARSEMEM_ENABLE
         help
           Support for the Cirrus Logic PS7500FE system-on-a-chip.
 
@@ -306,6 +311,7 @@ config ARCH_IOP13XX
         select PLAT_IOP
         select PCI
         select ARCH_SUPPORTS_MSI
+        select VMSPLIT_1G
         help
           Support for Intel's IOP13XX (XScale) family of processors.
 
@@ -350,6 +356,7 @@ config ARCH_IXP4XX
         select GENERIC_GPIO
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
+        select ZONE_DMA if PCI
         help
           Support for Intel's IXP4XX (XScale) family of processors.
 
@@ -434,7 +441,7 @@ config ARCH_ORION5X
         help
           Support for the following Marvell Orion 5x series SoCs:
           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
-          Orion-2 (5281).
+          Orion-2 (5281), Orion-1-90 (6183).
 
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
@@ -464,6 +471,7 @@ config ARCH_RPC
         select HAVE_PATA_PLATFORM
         select ISA_DMA_API
         select NO_IOPORT
+        select ARCH_SPARSEMEM_ENABLE
         help
           On the Acorn Risc-PC, Linux can support the internal IDE disk and
           CD-ROM interface, serial and parallel port, and the floppy drive.
@@ -471,9 +479,7 @@ config ARCH_RPC
 config ARCH_SA1100
         bool "SA1100-based"
         select ISA
-        select ARCH_DISCONTIGMEM_ENABLE
         select ARCH_SPARSEMEM_ENABLE
-        select ARCH_SELECT_MEMORY_MODEL
         select ARCH_MTD_XIP
         select GENERIC_GPIO
         select GENERIC_TIME
@@ -497,6 +503,7 @@ config ARCH_SHARK
         bool "Shark"
         select ISA
         select ISA_DMA
+        select ZONE_DMA
         select PCI
         help
           Support for the StrongARM based Digital DNARD machine, also known
@@ -504,6 +511,8 @@ config ARCH_SHARK
 
 config ARCH_LH7A40X
         bool "Sharp LH7A40X"
+        select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
+        select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
         help
           Say Y here for systems based on one of the Sharp LH7A40X
           System on a Chip processors.  These CPUs include an ARM922T
@@ -515,7 +524,9 @@ config ARCH_DAVINCI
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
+        select ZONE_DMA
         help
           Support for TI's DaVinci platform.
 
@@ -734,6 +745,29 @@ config SMP
 
           If you don't know what to do here, say N.
 
+choice
+        prompt "Memory split"
+        default VMSPLIT_3G
+        help
+          Select the desired split between kernel and user memory.
+
+          If you are not absolutely sure what you are doing, leave this
+          option alone!
+
+        config VMSPLIT_3G
+                bool "3G/1G user/kernel split"
+        config VMSPLIT_2G
+                bool "2G/2G user/kernel split"
+        config VMSPLIT_1G
+                bool "1G/3G user/kernel split"
+endchoice
+
+config PAGE_OFFSET
+        hex
+        default 0x40000000 if VMSPLIT_1G
+        default 0x80000000 if VMSPLIT_2G
+        default 0xC0000000
+
 config NR_CPUS
         int "Maximum number of CPUs (2-32)"
         range 2 32
@@ -815,20 +849,18 @@ config ARCH_FLATMEM_HAS_HOLES
         default y
         depends on FLATMEM
 
+# Discontigmem is deprecated
 config ARCH_DISCONTIGMEM_ENABLE
         bool
-        default (ARCH_LH7A40X && !LH7A40X_CONTIGMEM)
-        help
-          Say Y to support efficient handling of discontiguous physical memory,
-          for architectures which are either NUMA (Non-Uniform Memory Access)
-          or have huge holes in the physical address space for other reasons.
-          See <file:Documentation/vm/numa> for more.
 
 config ARCH_SPARSEMEM_ENABLE
         bool
 
+config ARCH_SPARSEMEM_DEFAULT
+        def_bool ARCH_SPARSEMEM_ENABLE
+
 config ARCH_SELECT_MEMORY_MODEL
-        bool
+        def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE
 
 config NODES_SHIFT
         int
@@ -845,7 +877,7 @@ config LEDS
                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
-                   ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \
+                   ARCH_AT91 || ARCH_DAVINCI || \
                    ARCH_KS8695 || MACH_RD88F5182
         help
           If you say Y here, the LEDs on your machine will be used
@@ -1005,9 +1037,9 @@ config ATAGS_PROC
 
 endmenu
 
-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
+menu "CPU Power Management"
 
-menu "CPU Frequency scaling"
+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
 
 source "drivers/cpufreq/Kconfig"
 
@@ -1047,10 +1079,12 @@ config CPU_FREQ_PXA
         default y
         select CPU_FREQ_DEFAULT_GOV_USERSPACE
 
-endmenu
-
 endif
 
+source "drivers/cpuidle/Kconfig"
+
+endmenu
+
 menu "Floating point emulation"
 
 comment "At least one emulation must be selected"
@@ -1202,6 +1236,8 @@ source "drivers/power/Kconfig"
 
 source "drivers/hwmon/Kconfig"
 
+source "drivers/thermal/Kconfig"
+
 source "drivers/watchdog/Kconfig"
 
 source "drivers/ssb/Kconfig"
@@ -1222,6 +1258,10 @@ source "drivers/usb/Kconfig"
 
 source "drivers/mmc/Kconfig"
 
+source "drivers/memstick/Kconfig"
+
+source "drivers/accessibility/Kconfig"
+
 source "drivers/leds/Kconfig"
 
 source "drivers/rtc/Kconfig"
@@ -1230,6 +1270,8 @@ source "drivers/dma/Kconfig"
 
 source "drivers/dca/Kconfig"
 
+source "drivers/auxdisplay/Kconfig"
+
 source "drivers/regulator/Kconfig"
 
 source "drivers/uio/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 703a44fa0f9b..e2274bc0b544 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -47,7 +47,7 @@ comma = ,
 # Note that GCC does not numerically define an architecture version
 # macro, but instead defines a whole series of macros which makes
 # testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_CPU_32v7)         :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
+arch-$(CONFIG_CPU_32v7)         :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
 arch-$(CONFIG_CPU_32v6)         :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
 # Only override the compiler option if ARMv6. The ARMv6K extensions are
 # always available in ARMv7
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 94462a097f86..7a03f2007882 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -76,7 +76,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
 EXTRA_CFLAGS  := -fpic -fno-builtin
-EXTRA_AFLAGS  :=
+EXTRA_AFLAGS  := -Wa,-march=all
 
 # Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
 # linker symbols.  We only define initrd_phys and params_phys if the
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index d42f89b7760b..84a1e0496a3c 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -421,6 +421,7 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
                 add     r1, r1, #1048576
                 str     r1, [r0]
                 mov     pc, lr
+ENDPROC(__setup_mmu)
 
 __armv4_mmu_cache_on:
                 mov     r12, lr
@@ -801,7 +802,7 @@ loop1:
                 add     r2, r2, #4              @ add 4 (line length offset)
                 ldr     r4, =0x3ff
                 ands    r4, r4, r1, lsr #3      @ find maximum number on the way size
-                .word   0xe16f5f14              @ clz r5, r4 - find bit position of way size increment
+                clz     r5, r4                  @ find bit position of way size increment
                 ldr     r7, =0x7fff
                 ands    r7, r7, r1, lsr #13     @ extract max number of the index size
 loop2:
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 3e073467caca..2e32acca02fb 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -12,7 +12,8 @@ config ICST307
 
 config SA1111
         bool
-        select DMABOUNCE
+        select DMABOUNCE if !ARCH_PXA
+        select ZONE_DMA if !ARCH_PXA
 
 config DMABOUNCE
         bool
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index aecc6c3f908f..f030f0775be7 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -154,9 +154,7 @@ alloc_safe_buffer(struct dmabounce_device_info *device_info, void *ptr,
 #endif
 
         write_lock_irqsave(&device_info->lock, flags);
-
         list_add(&buf->node, &device_info->safe_buffers);
-
         write_unlock_irqrestore(&device_info->lock, flags);
 
         return buf;
@@ -205,8 +203,22 @@ free_safe_buffer(struct dmabounce_device_info *device_info, struct safe_buffer *
 
 /* ************************************************** */
 
-static inline dma_addr_t
-map_single(struct device *dev, void *ptr, size_t size,
+static struct safe_buffer *find_safe_buffer_dev(struct device *dev,
+                dma_addr_t dma_addr, const char *where)
+{
+        if (!dev || !dev->archdata.dmabounce)
+                return NULL;
+        if (dma_mapping_error(dev, dma_addr)) {
+                if (dev)
+                        dev_err(dev, "Trying to %s invalid mapping\n", where);
+                else
+                        pr_err("unknown device: Trying to %s invalid mapping\n", where);
+                return NULL;
+        }
+        return find_safe_buffer(dev->archdata.dmabounce, dma_addr);
+}
+
+static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
                 enum dma_data_direction dir)
 {
         struct dmabounce_device_info *device_info = dev->archdata.dmabounce;
@@ -270,33 +282,21 @@ map_single(struct device *dev, void *ptr, size_t size,
         return dma_addr;
 }
 
-static inline void
-unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                enum dma_data_direction dir)
+static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
+                size_t size, enum dma_data_direction dir)
 {
-        struct dmabounce_device_info *device_info = dev->archdata.dmabounce;
-        struct safe_buffer *buf = NULL;
-
-        /*
-         * Trying to unmap an invalid mapping
-         */
-        if (dma_mapping_error(dev, dma_addr)) {
-                dev_err(dev, "Trying to unmap invalid mapping\n");
-                return;
-        }
-
-        if (device_info)
-                buf = find_safe_buffer(device_info, dma_addr);
+        struct safe_buffer *buf = find_safe_buffer_dev(dev, dma_addr, "unmap");
 
         if (buf) {
                 BUG_ON(buf->size != size);
+                BUG_ON(buf->direction != dir);
 
                 dev_dbg(dev,
                         "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
                         __func__, buf->ptr, virt_to_dma(dev, buf->ptr),
                         buf->safe, buf->safe_dma_addr);
 
-                DO_STATS ( device_info->bounce_count++ );
+                DO_STATS(dev->archdata.dmabounce->bounce_count++);
 
                 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) {
                         void *ptr = buf->ptr;
@@ -317,74 +317,7 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
                         dmac_clean_range(ptr, ptr + size);
                         outer_clean_range(__pa(ptr), __pa(ptr) + size);
                 }
-                free_safe_buffer(device_info, buf);
-        }
-}
-
-static int sync_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                        enum dma_data_direction dir)
-{
-        struct dmabounce_device_info *device_info = dev->archdata.dmabounce;
-        struct safe_buffer *buf = NULL;
-
-        if (device_info)
-                buf = find_safe_buffer(device_info, dma_addr);
-
-        if (buf) {
-                /*
-                 * Both of these checks from original code need to be
-                 * commented out b/c some drivers rely on the following:
-                 *
-                 * 1) Drivers may map a large chunk of memory into DMA space
-                 *    but only sync a small portion of it. Good example is
-                 *    allocating a large buffer, mapping it, and then
-                 *    breaking it up into small descriptors. No point
-                 *    in syncing the whole buffer if you only have to
-                 *    touch one descriptor.
-                 *
-                 * 2) Buffers that are mapped as DMA_BIDIRECTIONAL are
-                 *    usually only synced in one dir at a time.
-                 *
-                 * See drivers/net/eepro100.c for examples of both cases.
-                 *
-                 * -ds
-                 *
-                 * BUG_ON(buf->size != size);
-                 * BUG_ON(buf->direction != dir);
-                 */
-
-                dev_dbg(dev,
-                        "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
-                        __func__, buf->ptr, virt_to_dma(dev, buf->ptr),
-                        buf->safe, buf->safe_dma_addr);
-
-                DO_STATS ( device_info->bounce_count++ );
-
-                switch (dir) {
-                case DMA_FROM_DEVICE:
-                        dev_dbg(dev,
-                                "%s: copy back safe %p to unsafe %p size %d\n",
-                                __func__, buf->safe, buf->ptr, size);
-                        memcpy(buf->ptr, buf->safe, size);
-                        break;
-                case DMA_TO_DEVICE:
-                        dev_dbg(dev,
-                                "%s: copy out unsafe %p to safe %p, size %d\n",
-                                __func__,buf->ptr, buf->safe, size);
-                        memcpy(buf->safe, buf->ptr, size);
-                        break;
-                case DMA_BIDIRECTIONAL:
-                        BUG();  /* is this allowed?  what does it mean? */
-                default:
-                        BUG();
-                }
-                /*
-                 * No need to sync the safe buffer - it was allocated
-                 * via the coherent allocators.
-                 */
-                return 0;
-        } else {
-                return 1;
+                free_safe_buffer(dev->archdata.dmabounce, buf);
         }
 }
 
@@ -396,21 +329,29 @@ static int sync_single(struct device *dev, dma_addr_t dma_addr, size_t size,
  * substitute the safe buffer for the unsafe one.
  * (basically move the buffer from an unsafe area to a safe one)
  */
-dma_addr_t
-dma_map_single(struct device *dev, void *ptr, size_t size,
+dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
                 enum dma_data_direction dir)
 {
-        dma_addr_t dma_addr;
-
         dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
                 __func__, ptr, size, dir);
 
-        BUG_ON(dir == DMA_NONE);
+        BUG_ON(!valid_dma_direction(dir));
 
-        dma_addr = map_single(dev, ptr, size, dir);
+        return map_single(dev, ptr, size, dir);
+}
+EXPORT_SYMBOL(dma_map_single);
 
-        return dma_addr;
+dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                unsigned long offset, size_t size, enum dma_data_direction dir)
+{
+        dev_dbg(dev, "%s(page=%p,off=%#lx,size=%zx,dir=%x)\n",
+                __func__, page, offset, size, dir);
+
+        BUG_ON(!valid_dma_direction(dir));
+
+        return map_single(dev, page_address(page) + offset, size, dir);
 }
+EXPORT_SYMBOL(dma_map_page);
 
 /*
  * see if a mapped address was really a "safe" buffer and if so, copy
@@ -419,126 +360,76 @@ dma_map_single(struct device *dev, void *ptr, size_t size,
  * should be)
  */
 
-void
-dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                        enum dma_data_direction dir)
+void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+                enum dma_data_direction dir)
 {
         dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
                 __func__, (void *) dma_addr, size, dir);
 
-        BUG_ON(dir == DMA_NONE);
-
         unmap_single(dev, dma_addr, size, dir);
 }
+EXPORT_SYMBOL(dma_unmap_single);
 
-int
-dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-                enum dma_data_direction dir)
+int dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr,
+                unsigned long off, size_t sz, enum dma_data_direction dir)
 {
-        int i;
-
-        dev_dbg(dev, "%s(sg=%p,nents=%d,dir=%x)\n",
-                __func__, sg, nents, dir);
-
-        BUG_ON(dir == DMA_NONE);
-
-        for (i = 0; i < nents; i++, sg++) {
-                struct page *page = sg_page(sg);
-                unsigned int offset = sg->offset;
-                unsigned int length = sg->length;
-                void *ptr = page_address(page) + offset;
+        struct safe_buffer *buf;
 
-                sg->dma_address =
-                        map_single(dev, ptr, length, dir);
-        }
+        dev_dbg(dev, "%s(dma=%#x,off=%#lx,sz=%zx,dir=%x)\n",
+                __func__, addr, off, sz, dir);
 
-        return nents;
-}
-
-void
-dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
-                enum dma_data_direction dir)
-{
-        int i;
+        buf = find_safe_buffer_dev(dev, addr, __func__);
+        if (!buf)
+                return 1;
 
-        dev_dbg(dev, "%s(sg=%p,nents=%d,dir=%x)\n",
-                __func__, sg, nents, dir);
+        BUG_ON(buf->direction != dir);
 
-        BUG_ON(dir == DMA_NONE);
+        dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
+                __func__, buf->ptr, virt_to_dma(dev, buf->ptr),
+                buf->safe, buf->safe_dma_addr);
 
-        for (i = 0; i < nents; i++, sg++) {
-                dma_addr_t dma_addr = sg->dma_address;
-                unsigned int length = sg->length;
+        DO_STATS(dev->archdata.dmabounce->bounce_count++);
 
-                unmap_single(dev, dma_addr, length, dir);
+        if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) {
+                dev_dbg(dev, "%s: copy back safe %p to unsafe %p size %d\n",
+                        __func__, buf->safe + off, buf->ptr + off, sz);
+                memcpy(buf->ptr + off, buf->safe + off, sz);
         }
+        return 0;
 }
+EXPORT_SYMBOL(dmabounce_sync_for_cpu);
 
-void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_addr,
-                                   unsigned long offset, size_t size,
-                                   enum dma_data_direction dir)
-{
-        dev_dbg(dev, "%s(dma=%#x,off=%#lx,size=%zx,dir=%x)\n",
-                __func__, dma_addr, offset, size, dir);
-
-        if (sync_single(dev, dma_addr, offset + size, dir))
-                dma_cache_maint(dma_to_virt(dev, dma_addr) + offset, size, dir);
-}
-EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
-
-void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_addr,
-                                      unsigned long offset, size_t size,
-                                      enum dma_data_direction dir)
-{
-        dev_dbg(dev, "%s(dma=%#x,off=%#lx,size=%zx,dir=%x)\n",
-                __func__, dma_addr, offset, size, dir);
-
-        if (sync_single(dev, dma_addr, offset + size, dir))
-                dma_cache_maint(dma_to_virt(dev, dma_addr) + offset, size, dir);
-}
-EXPORT_SYMBOL(dma_sync_single_range_for_device);
-
-void
-dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
-                        enum dma_data_direction dir)
+int dmabounce_sync_for_device(struct device *dev, dma_addr_t addr,
+                unsigned long off, size_t sz, enum dma_data_direction dir)
 {
-        int i;
-
-        dev_dbg(dev, "%s(sg=%p,nents=%d,dir=%x)\n",
-                __func__, sg, nents, dir);
-
-        BUG_ON(dir == DMA_NONE);
+        struct safe_buffer *buf;
 
-        for (i = 0; i < nents; i++, sg++) {
-                dma_addr_t dma_addr = sg->dma_address;
-                unsigned int length = sg->length;
+        dev_dbg(dev, "%s(dma=%#x,off=%#lx,sz=%zx,dir=%x)\n",
+                __func__, addr, off, sz, dir);
 
-                sync_single(dev, dma_addr, length, dir);
-        }
-}
-
-void
-dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
-                        enum dma_data_direction dir)
-{
-        int i;
+        buf = find_safe_buffer_dev(dev, addr, __func__);
+        if (!buf)
+                return 1;
 
-        dev_dbg(dev, "%s(sg=%p,nents=%d,dir=%x)\n",
-                __func__, sg, nents, dir);
+        BUG_ON(buf->direction != dir);
 
-        BUG_ON(dir == DMA_NONE);
+        dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
+                __func__, buf->ptr, virt_to_dma(dev, buf->ptr),
+                buf->safe, buf->safe_dma_addr);
 
-        for (i = 0; i < nents; i++, sg++) {
-                dma_addr_t dma_addr = sg->dma_address;
-                unsigned int length = sg->length;
+        DO_STATS(dev->archdata.dmabounce->bounce_count++);
 
-                sync_single(dev, dma_addr, length, dir);
+        if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) {
+                dev_dbg(dev, "%s: copy out unsafe %p to safe %p, size %d\n",
+                        __func__,buf->ptr + off, buf->safe + off, sz);
+                memcpy(buf->safe + off, buf->ptr + off, sz);
         }
+        return 0;
 }
+EXPORT_SYMBOL(dmabounce_sync_for_device);
 
-static int
-dmabounce_init_pool(struct dmabounce_pool *pool, struct device *dev, const char *name,
-                    unsigned long size)
+static int dmabounce_init_pool(struct dmabounce_pool *pool, struct device *dev,
+                const char *name, unsigned long size)
 {
         pool->size = size;
         DO_STATS(pool->allocs = 0);
@@ -549,9 +440,8 @@ dmabounce_init_pool(struct dmabounce_pool *pool, struct device *dev, const char
         return pool->pool ? 0 : -ENOMEM;
 }
 
-int
-dmabounce_register_dev(struct device *dev, unsigned long small_buffer_size,
-                        unsigned long large_buffer_size)
+int dmabounce_register_dev(struct device *dev, unsigned long small_buffer_size,
+                unsigned long large_buffer_size)
 {
         struct dmabounce_device_info *device_info;
         int ret;
@@ -607,9 +497,9 @@ dmabounce_register_dev(struct device *dev, unsigned long small_buffer_size,
         kfree(device_info);
         return ret;
 }
+EXPORT_SYMBOL(dmabounce_register_dev);
 
-void
-dmabounce_unregister_dev(struct device *dev)
+void dmabounce_unregister_dev(struct device *dev)
 {
         struct dmabounce_device_info *device_info = dev->archdata.dmabounce;
 
@@ -642,15 +532,6 @@ dmabounce_unregister_dev(struct device *dev)
 
         dev_info(dev, "dmabounce: device unregistered\n");
 }
-
-
-EXPORT_SYMBOL(dma_map_single);
-EXPORT_SYMBOL(dma_unmap_single);
-EXPORT_SYMBOL(dma_map_sg);
-EXPORT_SYMBOL(dma_unmap_sg);
-EXPORT_SYMBOL(dma_sync_sg_for_cpu);
-EXPORT_SYMBOL(dma_sync_sg_for_device);
-EXPORT_SYMBOL(dmabounce_register_dev);
 EXPORT_SYMBOL(dmabounce_unregister_dev);
 
 MODULE_AUTHOR("Christopher Hoover <ch@hpl.hp.com>, Deepak Saxena <dsaxena@plexity.net>");
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 0c89bd35e06f..7fc9860a97d7 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -27,9 +27,9 @@
 #include <linux/list.h>
 #include <linux/smp.h>
 #include <linux/cpumask.h>
+#include <linux/io.h>
 
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
 
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 5fe9588db077..2793447621c3 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -66,14 +66,6 @@ static void it8152_unmask_irq(unsigned int irq)
        }
 }
 
-static inline void it8152_irq(int irq)
-{
-        struct irq_desc *desc;
-
-        desc = irq_desc + irq;
-        desc_handle_irq(irq, desc);
-}
-
 static struct irq_chip it8152_irq_chip = {
         .name           = "it8152",
         .ack            = it8152_mask_irq,
@@ -128,21 +120,21 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
                bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
                while (bits_pd) {
                        i = __ffs(bits_pd);
-                       it8152_irq(IT8152_PD_IRQ(i));
+                       generic_handle_irq(IT8152_PD_IRQ(i));
                        bits_pd &= ~(1 << i);
                }
 
                bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
                while (bits_lp) {
                        i = __ffs(bits_lp);
-                       it8152_irq(IT8152_LP_IRQ(i));
+                       generic_handle_irq(IT8152_LP_IRQ(i));
                        bits_lp &= ~(1 << i);
                }
 
                bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
                while (bits_ld) {
                        i = __ffs(bits_ld);
-                       it8152_irq(IT8152_LD_IRQ(i));
+                       generic_handle_irq(IT8152_LD_IRQ(i));
                        bits_ld &= ~(1 << i);
                }
        }
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 283051eaf931..7c6b4b99a2df 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -24,9 +24,9 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
@@ -169,7 +169,6 @@ static struct locomo_dev_info locomo_devices[] = {
 static void locomo_handler(unsigned int irq, struct irq_desc *desc)
 {
         int req, i;
-        struct irq_desc *d;
         void __iomem *mapbase = get_irq_chip_data(irq);
 
         /* Acknowledge the parent IRQ */
@@ -181,10 +180,9 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc)
         if (req) {
                 /* generate the next interrupt(s) */
                 irq = LOCOMO_IRQ_START;
-                d = irq_desc + irq;
-                for (i = 0; i <= 3; i++, d++, irq++) {
+                for (i = 0; i <= 3; i++, irq++) {
                         if (req & (0x0100 << i)) {
-                                desc_handle_irq(irq, d);
+                                generic_handle_irq(irq);
                         }
 
                 }
@@ -222,12 +220,10 @@ static struct irq_chip locomo_chip = {
 
 static void locomo_key_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_desc *d;
         void __iomem *mapbase = get_irq_chip_data(irq);
 
         if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) {
-                d = irq_desc + LOCOMO_IRQ_KEY_START;
-                desc_handle_irq(LOCOMO_IRQ_KEY_START, d);
+                generic_handle_irq(LOCOMO_IRQ_KEY_START);
         }
 }
 
@@ -268,7 +264,6 @@ static struct irq_chip locomo_key_chip = {
 static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc)
 {
         int req, i;
-        struct irq_desc *d;
         void __iomem *mapbase = get_irq_chip_data(irq);
 
         req =   locomo_readl(mapbase + LOCOMO_GIR) &
@@ -277,10 +272,9 @@ static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc)
 
         if (req) {
                 irq = LOCOMO_IRQ_GPIO_START;
-                d = irq_desc + LOCOMO_IRQ_GPIO_START;
-                for (i = 0; i <= 15; i++, irq++, d++) {
+                for (i = 0; i <= 15; i++, irq++) {
                         if (req & (0x0001 << i)) {
-                                desc_handle_irq(irq, d);
+                                generic_handle_irq(irq);
                         }
                 }
         }
@@ -361,12 +355,10 @@ static struct irq_chip locomo_gpio_chip = {
 
 static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_desc *d;
         void __iomem *mapbase = get_irq_chip_data(irq);
 
         if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) {
-                d = irq_desc + LOCOMO_IRQ_LT_START;
-                desc_handle_irq(LOCOMO_IRQ_LT_START, d);
+                generic_handle_irq(LOCOMO_IRQ_LT_START);
         }
 }
 
@@ -407,17 +399,15 @@ static struct irq_chip locomo_lt_chip = {
 static void locomo_spi_handler(unsigned int irq, struct irq_desc *desc)
 {
         int req, i;
-        struct irq_desc *d;
         void __iomem *mapbase = get_irq_chip_data(irq);
 
         req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F;
         if (req) {
                 irq = LOCOMO_IRQ_SPI_START;
-                d = irq_desc + irq;
 
-                for (i = 0; i <= 3; i++, irq++, d++) {
+                for (i = 0; i <= 3; i++, irq++) {
                         if (req & (0x0001 << i)) {
-                                desc_handle_irq(irq, d);
+                                generic_handle_irq(irq);
                         }
                 }
         }
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index ec8a5471bf06..fb86f248aab8 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -25,10 +25,10 @@
 #include <linux/spinlock.h>
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/sizes.h>
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index ae39553589dd..697c64913990 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -15,7 +15,7 @@
 #include <linux/string.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/gpio.h>
 #include <asm/hardware/scoop.h>
 
diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c
index aad4d94ba8f5..d56c932580eb 100644
--- a/arch/arm/common/sharpsl_param.c
+++ b/arch/arm/common/sharpsl_param.c
@@ -12,6 +12,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/string.h>
 #include <asm/mach/sharpsl_param.h>
 
@@ -36,6 +37,7 @@
 #define PHAD_MAGIC      MAGIC_CHG('P','H','A','D')
 
 struct sharpsl_param_info sharpsl_param;
+EXPORT_SYMBOL(sharpsl_param);
 
 void sharpsl_save_param(void)
 {
diff --git a/arch/arm/common/time-acorn.c b/arch/arm/common/time-acorn.c
index df0983aafe69..deeed561b168 100644
--- a/arch/arm/common/time-acorn.c
+++ b/arch/arm/common/time-acorn.c
@@ -17,9 +17,9 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/hardware/ioc.h>
 
 #include <asm/mach/time.h>
diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c
index 7ecd3c0ab011..b520e56216a9 100644
--- a/arch/arm/common/uengine.c
+++ b/arch/arm/common/uengine.c
@@ -16,9 +16,9 @@
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/string.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/hardware/uengine.h>
-#include <asm/io.h>
 
 #if defined(CONFIG_ARCH_IXP2000)
 #define IXP_UENGINE_CSR_VIRT_BASE       IXP2000_UENGINE_CSR_VIRT_BASE
diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c
index 79a8206e62ac..8421d39109b3 100644
--- a/arch/arm/common/via82c505.c
+++ b/arch/arm/common/via82c505.c
@@ -4,8 +4,8 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/system.h>
 
 #include <asm/mach/pci.h>
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index c026fa2214a3..f1e4b8f60cab 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -20,8 +20,8 @@
  */
 #include <linux/init.h>
 #include <linux/list.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
 
diff --git a/arch/arm/configs/afeb9260_defconfig b/arch/arm/configs/afeb9260_defconfig
new file mode 100644
index 000000000000..ce909586a34f
--- /dev/null
+++ b/arch/arm/configs/afeb9260_defconfig
@@ -0,0 +1,1259 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27-rc2
+# Tue Aug 12 22:30:16 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
+CONFIG_MACH_AFEB9260=y
+# CONFIG_MACH_USB_A9260 is not set
+# CONFIG_MACH_QIL_A9260 is not set
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_ATMEL_TCLIB is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+CONFIG_AT24=y
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_DEBUG=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+CONFIG_RTC_DRV_FM3130=y
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig
index 1c76642272a1..811bebbdc784 100644
--- a/arch/arm/configs/at91sam9rlek_defconfig
+++ b/arch/arm/configs/at91sam9rlek_defconfig
@@ -496,6 +496,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
 # CONFIG_TOUCHSCREEN_UCB1400 is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_INPUT_MISC is not set
diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig
new file mode 100644
index 000000000000..46f1c9dc350c
--- /dev/null
+++ b/arch/arm/configs/cm_x300_defconfig
@@ -0,0 +1,1466 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27-rc3
+# Tue Aug 19 11:26:54 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-cm-x300"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+
+#
+# Supported PXA3xx Processor Variants
+#
+CONFIG_CPU_PXA300=y
+# CONFIG_CPU_PXA310 is not set
+# CONFIG_CPU_PXA320 is not set
+# CONFIG_CPU_PXA930 is not set
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+# CONFIG_MACH_ARMCORE is not set
+CONFIG_MACH_CM_X300=y
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
+CONFIG_PXA3xx=y
+# CONFIG_PXA_PWM is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSC3=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_IO_36=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_XSC3L2=y
+CONFIG_IWMMXT=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=jffs2 console=ttyS2,38400"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=m
+CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_H1900 is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_SHARPSL is not set
+CONFIG_MTD_NAND_PXA3xx=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=0
+CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_USB is not set
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_HOSTAP is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_PXA27x=m
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+CONFIG_GPIO_PCA953X=y
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_SMARTPANEL is not set
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_W100 is not set
+# CONFIG_FB_AM200EPD is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+CONFIG_FONT_6x11=y
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_PXA2XX_AC97 is not set
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_PXA2XX_SOC=m
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_MON=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_SIERRA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=m
+# CONFIG_MMC_SDHCI is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+# CONFIG_DMADEVICES is not set
+
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index 0c556289a3f4..81fadafae02d 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -1,84 +1,174 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc1-bk2
-# Sun Mar 27 23:10:35 2005
+# Linux kernel version: 2.6.27-rc6
+# Tue Sep 16 18:56:58 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-CONFIG_UID16=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_IOMAP=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
-
-#
-# General setup
-#
+CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 # CONFIG_MODULE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System Type
 #
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
 # CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
 CONFIG_ARCH_SA1100=y
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_MSM7X00A is not set
+CONFIG_DMABOUNCE=y
 
 #
 # SA11x0 Implementations
@@ -91,12 +181,21 @@ CONFIG_ARCH_SA1100=y
 # CONFIG_SA1100_H3800 is not set
 # CONFIG_SA1100_BADGE4 is not set
 CONFIG_SA1100_JORNADA720=y
+CONFIG_SA1100_JORNADA720_SSP=y
 # CONFIG_SA1100_HACKKIT is not set
 # CONFIG_SA1100_LART is not set
 # CONFIG_SA1100_PLEB is not set
 # CONFIG_SA1100_SHANNON is not set
 # CONFIG_SA1100_SIMPAD is not set
-# CONFIG_SA1100_SSP is not set
+CONFIG_SA1100_SSP=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
 
 #
 # Processor Type
@@ -105,44 +204,71 @@ CONFIG_CPU_32=y
 CONFIG_CPU_SA1100=y
 CONFIG_CPU_32v4=y
 CONFIG_CPU_ABRT_EV4=y
+CONFIG_CPU_PABRT_NOIFAR=y
 CONFIG_CPU_CACHE_V4WB=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WB=y
-CONFIG_CPU_MINICACHE=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
 
 #
 # Processor Features
 #
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
 CONFIG_SA1111=y
-CONFIG_DMABOUNCE=y
 CONFIG_FORCE_MAX_ZONEORDER=9
 
 #
 # Bus support
 #
 CONFIG_ISA=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_PCCARD=y
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
 
 #
 # PC-card bridges
 #
-CONFIG_I82365=y
+# CONFIG_I82365 is not set
 # CONFIG_TCIC is not set
 CONFIG_PCMCIA_SA1100=y
 # CONFIG_PCMCIA_SA1111 is not set
-CONFIG_PCCARD_NONSTATIC=y
 
 #
 # Kernel Features
 #
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_NODES_SHIFT=2
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -151,8 +277,9 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="keepinitrd mem=32M"
+CONFIG_CMDLINE=""
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # CPU Frequency scaling
@@ -174,7 +301,7 @@ CONFIG_FPE_FASTFPE=y
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_AOUT=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_ARTHUR is not set
 
@@ -182,188 +309,12 @@ CONFIG_BINFMT_AOUT=m
 # Power management options
 #
 CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
-# CONFIG_APM is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=1
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-CONFIG_MTD_SA1100=y
-# CONFIG_MTD_EDB7312 is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-# CONFIG_MTD_NAND is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNP is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_XD is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_RAM is not set
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=m
-CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=m
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_BLK_DEV_IDECS is not set
-CONFIG_BLK_DEV_IDECD=m
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-CONFIG_IDE_GENERIC=m
-# CONFIG_IDE_ARM is not set
-# CONFIG_IDE_CHIPSETS is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
 
 #
@@ -371,12 +322,17 @@ CONFIG_NET=y
 #
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
-# CONFIG_NETLINK_DEV is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 # CONFIG_IP_PNP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
@@ -386,31 +342,42 @@ CONFIG_IP_MULTICAST=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-# CONFIG_IP_TCPDIAG is not set
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# IP: Virtual Server Configuration
-#
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IP_VS is not set
 # CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
 
 #
 # IP: Netfilter Configuration
 #
-# CONFIG_IP_NF_CONNTRACK is not set
-# CONFIG_IP_NF_CONNTRACK_MARK is not set
 # CONFIG_IP_NF_QUEUE is not set
 # CONFIG_IP_NF_IPTABLES is not set
 # CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
+# CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
@@ -420,30 +387,22 @@ CONFIG_NETFILTER=y
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 CONFIG_IRDA=m
 
 #
 # IrDA protocols
 #
 CONFIG_IRLAN=m
-# CONFIG_IRNET is not set
 CONFIG_IRCOMM=m
 # CONFIG_IRDA_ULTRA is not set
 
@@ -468,89 +427,105 @@ CONFIG_IRCOMM=m
 #
 
 #
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
 # FIR device drivers
 #
-# CONFIG_NSC_FIR is not set
-# CONFIG_WINBOND_FIR is not set
-# CONFIG_SMC_IRCC_FIR is not set
-# CONFIG_ALI_FIR is not set
 CONFIG_SA1100_FIR=m
 # CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-# CONFIG_NET_ETHERNET is not set
-CONFIG_MII=m
+# CONFIG_AF_RXRPC is not set
 
 #
-# Ethernet (1000 Mbit)
+# Wireless
 #
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
+# Device Drivers
 #
-CONFIG_NET_RADIO=y
 
 #
-# Obsolete Wireless cards support (pre-802.11)
+# Generic Driver Options
 #
-# CONFIG_STRIP is not set
-CONFIG_ARLAN=m
-CONFIG_WAVELAN=m
-CONFIG_PCMCIA_WAVELAN=m
-# CONFIG_PCMCIA_NETWAVE is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
 
 #
-# Wireless 802.11 Frequency Hopping cards support
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
-# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=y
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
-# Wireless 802.11b ISA/PCI cards support
+# IDE chipset support/bugfixes
 #
-CONFIG_HERMES=m
-# CONFIG_ATMEL is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
 
 #
-# Wireless 802.11b Pcmcia/Cardbus cards support
+# SCSI device support
 #
-CONFIG_PCMCIA_HERMES=m
-CONFIG_AIRO_CS=m
-# CONFIG_PCMCIA_WL3501 is not set
-CONFIG_NET_WIRELESS=y
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_MII=m
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
 
 #
-# PCMCIA network device support
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
 CONFIG_NET_PCMCIA=y
 CONFIG_PCMCIA_3C589=m
 CONFIG_PCMCIA_3C574=m
@@ -560,32 +535,20 @@ CONFIG_PCMCIA_NMCLAN=m
 CONFIG_PCMCIA_SMC91C92=m
 CONFIG_PCMCIA_XIRC2PS=m
 CONFIG_PCMCIA_AXNET=m
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
-CONFIG_PPP=m
-# CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPPOE is not set
+# CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
-
-#
-# ISDN subsystem
-#
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_ISDN is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -595,7 +558,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -603,20 +565,31 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_KEYBOARD_SUNKBD is not set
 # CONFIG_KEYBOARD_LKKBD is not set
 # CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_KEYBOARD_NEWTON is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_INPORT is not set
-# CONFIG_MOUSE_LOGIBM is not set
-# CONFIG_MOUSE_PC110PAD is not set
-# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_HP7XX=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+CONFIG_TOUCHSCREEN_HP7XX=y
+# CONFIG_TOUCHSCREEN_HTCPEN is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -625,17 +598,18 @@ CONFIG_MOUSE_PS2=y
 CONFIG_SERIO=y
 CONFIG_SERIO_SERPORT=y
 # CONFIG_SERIO_SA1111 is not set
-CONFIG_SERIO_LIBPS2=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -652,69 +626,120 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
 
 #
-# IPMI
+# PCMCIA character devices
 #
-# CONFIG_IPMI_HANDLER is not set
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
 
 #
-# Watchdog Cards
+# I2C GPIO expanders:
 #
-# CONFIG_WATCHDOG is not set
-# CONFIG_NVRAM is not set
-# CONFIG_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
 
 #
-# Ftape, the floppy tape device driver
+# PCI GPIO expanders:
 #
-# CONFIG_DRM is not set
 
 #
-# PCMCIA character devices
+# SPI GPIO expanders:
 #
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_RAW_DRIVER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
 
 #
-# TPM devices
+# Sonics Silicon Backplane
 #
-# CONFIG_TCG_TPM is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# I2C support
+# Multifunction device drivers
 #
-# CONFIG_I2C is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
 
 #
-# Misc devices
+# Multimedia Capabilities Port drivers
 #
+# CONFIG_MCP_SA11X0 is not set
 
 #
 # Multimedia devices
 #
+
+#
+# Multimedia core support
+#
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multimedia drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
-# CONFIG_FB_SOFT_CURSOR is not set
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
 # CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
 # CONFIG_FB_SA1100 is not set
+CONFIG_FB_S1D13XXX=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -722,94 +747,110 @@ CONFIG_FB=y
 # CONFIG_VGA_CONSOLE is not set
 # CONFIG_MDA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
-
-#
-# Logo configuration
-#
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
 # CONFIG_LOGO is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-CONFIG_SOUND=m
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# Advanced Linux Sound Architecture
+# RTC interfaces
 #
-# CONFIG_SND is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# Open Sound System
+# SPI RTC drivers
 #
-# CONFIG_SOUND_PRIME is not set
 
 #
-# USB support
+# Platform RTC drivers
 #
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB is not set
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# USB Gadget Support
+# on-CPU RTC drivers
 #
-# CONFIG_USB_GADGET is not set
+CONFIG_RTC_DRV_SA1100=y
+# CONFIG_DMADEVICES is not set
 
 #
-# MMC/SD Card support
+# Voltage and Current regulators
 #
-# CONFIG_MMC is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4DEV_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-
-#
-# XFS support
-#
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
+# CONFIG_OCFS2_FS is not set
 CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
 
 #
 # CD-ROM/DVD Filesystems
 #
-CONFIG_ISO9660_FS=m
-# CONFIG_JOLIET is not set
-# CONFIG_ZISOFS is not set
+# CONFIG_ISO9660_FS is not set
 # CONFIG_UDF_FS is not set
 
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
-CONFIG_DEVFS_FS=y
-CONFIG_DEVFS_MOUNT=y
-CONFIG_DEVFS_DEBUG=y
-# CONFIG_DEVPTS_FS_XATTR is not set
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
 
 #
 # Miscellaneous filesystems
@@ -821,75 +862,122 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=2
-# CONFIG_JFFS2_FS_NAND is not set
-# CONFIG_JFFS2_FS_NOR_ECC is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_SUNRPC=m
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
-CONFIG_DEBUG_SLAB=y
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
 # CONFIG_DEBUG_USER is not set
 CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
 
@@ -898,21 +986,100 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
 
 #
-# Cryptographic options
+# Ciphers
 #
-# CONFIG_CRYPTO is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Hardware crypto devices
+# Compression
 #
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 4017d83c9d2d..b2456ca544c9 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -176,14 +176,17 @@ CONFIG_MACH_KUROBOX_PRO=y
 CONFIG_MACH_DNS323=y
 CONFIG_MACH_TS209=y
 CONFIG_MACH_LINKSTATION_PRO=y
+CONFIG_MACH_LINKSTATION_MINI=y
 CONFIG_MACH_TS409=y
 CONFIG_MACH_WRT350N_V2=y
 CONFIG_MACH_TS78XX=y
 CONFIG_MACH_MV2120=y
+CONFIG_MACH_EDMINI_V2=y
 CONFIG_MACH_MSS2=y
 CONFIG_MACH_WNR854T=y
 CONFIG_MACH_RD88F5181L_GE=y
 CONFIG_MACH_RD88F5181L_FXO=y
+CONFIG_MACH_RD88F6183AP_GE=y
 
 #
 # Boot options
diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig
new file mode 100644
index 000000000000..3245f8f33e0a
--- /dev/null
+++ b/arch/arm/configs/palmz72_defconfig
@@ -0,0 +1,951 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27-rc4
+# Sun Aug 24 02:29:27 2008
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
+CONFIG_ARCH_PXA_PALM=y
+# CONFIG_MACH_PALMTX is not set
+CONFIG_MACH_PALMZ72=y
+# CONFIG_PXA_EZX is not set
+CONFIG_PXA27x=y
+CONFIG_PXA_PWM=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=32M console=tty root=/dev/mmcblk0"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_PXA27x=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_PXA is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_PXA2XX is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+# CONFIG_APM_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_SMARTPANEL is not set
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_W100 is not set
+# CONFIG_FB_AM200EPD is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_CORGI is not set
+CONFIG_BACKLIGHT_PWM=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+# CONFIG_DMADEVICES is not set
+
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=866
+CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+CONFIG_NLS_CODEPAGE_866=y
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_DEBUG_USER=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
new file mode 100644
index 000000000000..d01fecb8673e
--- /dev/null
+++ b/arch/arm/configs/viper_defconfig
@@ -0,0 +1,1678 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27-rc4
+# Thu Aug 21 17:12:07 2008
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=13
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+CONFIG_ARCH_VIPER=y
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
+CONFIG_PXA25x=y
+CONFIG_PXA_PWM=m
+CONFIG_PXA_HAVE_ISA_IRQS=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+CONFIG_ISA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_PXA2XX=m
+CONFIG_PCMCIA_PROBE=y
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_FREQ_PXA=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+CONFIG_FPE_FASTFPE=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+# CONFIG_BT_SCO is not set
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+# CONFIG_BT_HIDP is not set
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=m
+# CONFIG_BT_HCIUSB_SCO is not set
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+# CONFIG_BT_HCIUART_LL is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBTUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=m
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=0
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+CONFIG_MTD_SPARSE_RAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_SATA_PMP is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_MV is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_PATA_PCMCIA=m
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_PEGASUS=m
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=m
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_PCMCIA_PCNET is not set
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_FUJITSU=m
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+CONFIG_TOUCHSCREEN_ELO=m
+CONFIG_TOUCHSCREEN_MTOUCH=m
+CONFIG_TOUCHSCREEN_INEXIO=m
+# CONFIG_TOUCHSCREEN_MK712 is not set
+CONFIG_TOUCHSCREEN_HTCPEN=m
+CONFIG_TOUCHSCREEN_PENMOUNT=m
+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
+CONFIG_TOUCHSCREEN_TOUCHWIN=m
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+CONFIG_TOUCHSCREEN_TOUCHIT213=m
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=m
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=5
+CONFIG_SERIAL_8250_RUNTIME_UARTS=5
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_NVRAM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_ELEKTOR is not set
+# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SA1100_WATCHDOG is not set
+
+#
+# ISA-based Watchdog Cards
+#
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=m
+CONFIG_FB_CFB_COPYAREA=m
+CONFIG_FB_CFB_IMAGEBLIT=m
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=m
+# CONFIG_FB_PXA_SMARTPANEL is not set
+CONFIG_FB_PXA_PARAMETERS=y
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_W100 is not set
+# CONFIG_FB_AM200EPD is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+# CONFIG_BACKLIGHT_CORGI is not set
+CONFIG_BACKLIGHT_PWM=m
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_AC97_POWER_SAVE is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_PXA2XX_PCM=m
+CONFIG_SND_PXA2XX_AC97=m
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_PCMCIA=y
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_ISP116X_HCD=m
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_SL811_HCD=m
+# CONFIG_USB_SL811_CS is not set
+CONFIG_USB_R8A66597_HCD=m
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_SIERRA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+CONFIG_USB_GADGET_PXA25X=y
+CONFIG_USB_PXA25X=m
+# CONFIG_USB_PXA25X_SMALL is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=m
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=m
+# CONFIG_DMADEVICES is not set
+
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=m
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=m
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=m
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=m
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/xm_x270_defconfig b/arch/arm/configs/xm_x2xx_defconfig
index aa40d91ce599..f891364deceb 100644
--- a/arch/arm/configs/xm_x270_defconfig
+++ b/arch/arm/configs/xm_x2xx_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25
-# Sun May 11 15:12:52 2008
+# Linux kernel version: 2.6.27-rc8
+# Sun Oct  5 11:05:36 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -12,6 +12,7 @@ CONFIG_MMU=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
@@ -24,6 +25,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
@@ -62,7 +64,6 @@ CONFIG_SYSCTL=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -88,14 +89,21 @@ CONFIG_SLUB=y
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
 # CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
@@ -106,6 +114,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -131,7 +140,6 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
@@ -145,8 +153,11 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
 # CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_PNX4008 is not set
@@ -164,26 +175,32 @@ CONFIG_DMABOUNCE=y
 #
 # Intel PXA2xx/PXA3xx Implementations
 #
-
-#
-# Select target boards
-#
 # CONFIG_ARCH_GUMSTIX is not set
 # CONFIG_ARCH_LUBBOCK is not set
 # CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_MP900C is not set
 # CONFIG_ARCH_PXA_IDP is not set
 # CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_VIPER is not set
 # CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_TRIZEPS_PXA is not set
 CONFIG_MACH_EM_X270=y
 # CONFIG_MACH_COLIBRI is not set
 # CONFIG_MACH_ZYLONITE is not set
 # CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
 CONFIG_MACH_ARMCORE=y
+# CONFIG_MACH_CM_X300 is not set
 # CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_MIOA701 is not set
 # CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
+CONFIG_PXA25x=y
 CONFIG_PXA27x=y
+CONFIG_PXA_SSP=y
 # CONFIG_PXA_PWM is not set
 
 #
@@ -253,11 +270,17 @@ CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PREEMPT is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -284,9 +307,10 @@ CONFIG_CMDLINE="root=1f03 mem=32M"
 # CONFIG_KEXEC is not set
 
 #
-# CPU Frequency scaling
+# CPU Power Management
 #
 # CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
 
 #
 # Floating point emulation
@@ -316,10 +340,6 @@ CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
 CONFIG_APM_EMULATION=m
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -402,6 +422,7 @@ CONFIG_BT_HIDP=m
 #
 CONFIG_BT_HCIUSB=m
 CONFIG_BT_HCIUSB_SCO=y
+# CONFIG_BT_HCIBTUSB is not set
 # CONFIG_BT_HCIBTSDIO is not set
 # CONFIG_BT_HCIUART is not set
 # CONFIG_BT_HCIBCM203X is not set
@@ -419,6 +440,7 @@ CONFIG_BT_HCIUSB_SCO=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
 # CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
@@ -435,6 +457,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
@@ -527,6 +551,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
 # CONFIG_MTD_NAND_H1900 is not set
+CONFIG_MTD_NAND_GPIO=m
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_SHARPSL is not set
@@ -636,6 +661,7 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
 # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_ATA=m
 # CONFIG_ATA_NONSTANDARD is not set
 # CONFIG_SATA_PMP is not set
@@ -696,17 +722,21 @@ CONFIG_PATA_PCMCIA=m
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
 # CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -725,6 +755,7 @@ CONFIG_MII=y
 # CONFIG_SMC91X is not set
 CONFIG_DM9000=y
 CONFIG_DM9000_DEBUGLEVEL=1
+# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
 # CONFIG_SMC911X is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
@@ -780,7 +811,6 @@ CONFIG_LIBERTAS_SDIO=m
 # CONFIG_PRISM54 is not set
 # CONFIG_USB_ZD1201 is not set
 # CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_IWLWIFI is not set
 # CONFIG_IWLWIFI_LEDS is not set
 # CONFIG_HOSTAP is not set
 
@@ -853,17 +883,18 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-CONFIG_TOUCHSCREEN_UCB1400=m
 CONFIG_TOUCHSCREEN_WM97XX=m
 # CONFIG_TOUCHSCREEN_WM9705 is not set
 CONFIG_TOUCHSCREEN_WM9712=y
 # CONFIG_TOUCHSCREEN_WM9713 is not set
 # CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -880,6 +911,7 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
@@ -922,45 +954,66 @@ CONFIG_DEVPORT=y
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
 
 #
 # I2C Hardware Bus support
 #
+
+#
+# PC SMBus host controller drivers
+#
 # CONFIG_I2C_ALI1535 is not set
 # CONFIG_I2C_ALI1563 is not set
 # CONFIG_I2C_ALI15X3 is not set
 # CONFIG_I2C_AMD756 is not set
 # CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_I801 is not set
-# CONFIG_I2C_I810 is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_ISCH is not set
 # CONFIG_I2C_PIIX4 is not set
 # CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PROSAVAGE is not set
-# CONFIG_I2C_SAVAGE4 is not set
-# CONFIG_I2C_SIMTEC is not set
 # CONFIG_I2C_SIS5595 is not set
 # CONFIG_I2C_SIS630 is not set
 # CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_TINY_USB is not set
 # CONFIG_I2C_VIA is not set
 # CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
 # CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
 # CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
@@ -970,25 +1023,31 @@ CONFIG_I2C_PXA=y
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
-CONFIG_HAVE_GPIO_LIB=y
-
-#
-# GPIO Support
-#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
 
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
 
 #
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+
+#
 # SPI GPIO expanders:
 #
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -1000,10 +1059,16 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
 
 #
 # Multimedia devices
@@ -1014,6 +1079,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # CONFIG_VIDEO_DEV is not set
 # CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
 
 #
 # Multimedia drivers
@@ -1038,7 +1104,6 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SYS_IMAGEBLIT is not set
 # CONFIG_FB_FOREIGN_ENDIAN is not set
 # CONFIG_FB_SYS_FOPS is not set
-CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -1071,12 +1136,14 @@ CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_TRIDENT is not set
 # CONFIG_FB_ARK is not set
 # CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
 CONFIG_FB_PXA=y
 # CONFIG_FB_PXA_SMARTPANEL is not set
 CONFIG_FB_PXA_PARAMETERS=y
 CONFIG_FB_MBX=m
-# CONFIG_FB_AM200EPD is not set
+# CONFIG_FB_W100 is not set
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
@@ -1099,15 +1166,7 @@ CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
@@ -1121,19 +1180,15 @@ CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
+CONFIG_SND_VMASTER=y
 CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_DRIVERS=y
 # CONFIG_SND_DUMMY is not set
 # CONFIG_SND_MTPAV is not set
 # CONFIG_SND_SERIAL_U16550 is not set
 # CONFIG_SND_MPU401 is not set
-
-#
-# PCI devices
-#
+# CONFIG_SND_AC97_POWER_SAVE is not set
+CONFIG_SND_PCI=y
 # CONFIG_SND_AD1889 is not set
 # CONFIG_SND_ALS300 is not set
 # CONFIG_SND_ALI5451 is not set
@@ -1193,42 +1248,16 @@ CONFIG_SND_AC97_CODEC=m
 # CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 # CONFIG_SND_YMFPCI is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
-
-#
-# ALSA ARM devices
-#
+CONFIG_SND_ARM=y
 CONFIG_SND_PXA2XX_PCM=m
 CONFIG_SND_PXA2XX_AC97=m
-
-#
-# USB devices
-#
+CONFIG_SND_USB=y
 # CONFIG_SND_USB_AUDIO is not set
 # CONFIG_SND_USB_CAIAQ is not set
-
-#
-# PCMCIA devices
-#
+CONFIG_SND_PCMCIA=y
 # CONFIG_SND_VXPOCKET is not set
 # CONFIG_SND_PDAUDIOCF is not set
-
-#
-# System on Chip audio support
-#
 # CONFIG_SND_SOC is not set
-
-#
-# ALSA SoC audio for Freescale SOCs
-#
-
-#
-# SoC Audio for the Texas Instruments OMAP
-#
-
-#
-# Open Sound System
-#
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
 CONFIG_HID_SUPPORT=y
@@ -1261,12 +1290,15 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
 # CONFIG_USB_EHCI_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1274,12 +1306,14 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_UHCI_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
 
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1309,7 +1343,6 @@ CONFIG_USB_STORAGE=y
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-CONFIG_USB_MON=y
 
 #
 # USB port drivers
@@ -1322,7 +1355,6 @@ CONFIG_USB_MON=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1338,6 +1370,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_GADGET is not set
 CONFIG_MMC=m
 # CONFIG_MMC_DEBUG is not set
@@ -1349,6 +1382,7 @@ CONFIG_MMC=m
 CONFIG_MMC_BLOCK=m
 CONFIG_MMC_BLOCK_BOUNCE=y
 # CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
 
 #
 # MMC/SD Host Controller Drivers
@@ -1356,14 +1390,19 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 CONFIG_MMC_PXA=m
 # CONFIG_MMC_SDHCI is not set
 # CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_SDRICOH_CS is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 
 #
 # LED drivers
 #
+# CONFIG_LEDS_PCA9532 is not set
 # CONFIG_LEDS_GPIO is not set
 CONFIG_LEDS_CM_X270=y
+# CONFIG_LEDS_PCA955X is not set
 
 #
 # LED Triggers
@@ -1401,6 +1440,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_PCF8583 is not set
 # CONFIG_RTC_DRV_M41T80 is not set
 # CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
 
 #
 # SPI RTC drivers
@@ -1422,6 +1462,15 @@ CONFIG_RTC_DRV_V3020=y
 # on-CPU RTC drivers
 #
 CONFIG_RTC_DRV_SA1100=y
+# CONFIG_DMADEVICES is not set
+
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
 # CONFIG_UIO is not set
 
 #
@@ -1501,6 +1550,7 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -1511,13 +1561,12 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1626,6 +1675,7 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
@@ -1633,7 +1683,17 @@ CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
 # CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_STACK_USAGE is not set
@@ -1689,6 +1749,10 @@ CONFIG_CRYPTO=y
 # CONFIG_CRYPTO_MD4 is not set
 # CONFIG_CRYPTO_MD5 is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
 # CONFIG_CRYPTO_SHA1 is not set
 # CONFIG_CRYPTO_SHA256 is not set
 # CONFIG_CRYPTO_SHA512 is not set
@@ -1729,6 +1793,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index 7b62351f097d..4d88425a4169 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -12,7 +12,7 @@ extern void __bug(const char *file, int line) __attribute__((noreturn));
 #else
 
 /* this just causes an oops */
-#define BUG()           (*(int *)0 = 0)
+#define BUG()           do { *(int *)0 = 0; } while (1)
 
 #endif
 
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 9073d9c6567e..de6c59f814a1 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -444,94 +444,4 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt,
         dmac_inv_range(start, start + size);
 }
 
-#define __cacheid_present(val)                  (val != read_cpuid(CPUID_ID))
-#define __cacheid_type_v7(val)                  ((val & (7 << 29)) == (4 << 29))
-
-#define __cacheid_vivt_prev7(val)               ((val & (15 << 25)) != (14 << 25))
-#define __cacheid_vipt_prev7(val)               ((val & (15 << 25)) == (14 << 25))
-#define __cacheid_vipt_nonaliasing_prev7(val)   ((val & (15 << 25 | 1 << 23)) == (14 << 25))
-#define __cacheid_vipt_aliasing_prev7(val)      ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
-
-#define __cacheid_vivt(val)                     (__cacheid_type_v7(val) ? 0 : __cacheid_vivt_prev7(val))
-#define __cacheid_vipt(val)                     (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_prev7(val))
-#define __cacheid_vipt_nonaliasing(val)         (__cacheid_type_v7(val) ? 1 : __cacheid_vipt_nonaliasing_prev7(val))
-#define __cacheid_vipt_aliasing(val)            (__cacheid_type_v7(val) ? 0 : __cacheid_vipt_aliasing_prev7(val))
-#define __cacheid_vivt_asid_tagged_instr(val)   (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0)
-
-#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
-/*
- * VIVT caches only
- */
-#define cache_is_vivt()                 1
-#define cache_is_vipt()                 0
-#define cache_is_vipt_nonaliasing()     0
-#define cache_is_vipt_aliasing()        0
-#define icache_is_vivt_asid_tagged()    0
-
-#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
-/*
- * VIPT caches only
- */
-#define cache_is_vivt()                 0
-#define cache_is_vipt()                 1
-#define cache_is_vipt_nonaliasing()                                     \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_vipt_nonaliasing(__val);                      \
-        })
-
-#define cache_is_vipt_aliasing()                                        \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_vipt_aliasing(__val);                         \
-        })
-
-#define icache_is_vivt_asid_tagged()                                    \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_vivt_asid_tagged_instr(__val);                \
-        })
-
-#else
-/*
- * VIVT or VIPT caches.  Note that this is unreliable since ARM926
- * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test.
- * There's no way to tell from the CacheType register what type (!)
- * the cache is.
- */
-#define cache_is_vivt()                                                 \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
-        })
-                
-#define cache_is_vipt()                                                 \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) && __cacheid_vipt(__val);      \
-        })
-
-#define cache_is_vipt_nonaliasing()                                     \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) &&                             \
-                 __cacheid_vipt_nonaliasing(__val);                     \
-        })
-
-#define cache_is_vipt_aliasing()                                        \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) &&                             \
-                 __cacheid_vipt_aliasing(__val);                        \
-        })
-
-#define icache_is_vivt_asid_tagged()                                    \
-        ({                                                              \
-                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
-                __cacheid_present(__val) &&                             \
-                 __cacheid_vivt_asid_tagged_instr(__val);               \
-        })
-
-#endif
-
 #endif
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h
new file mode 100644
index 000000000000..d3a4c2cb9f2f
--- /dev/null
+++ b/arch/arm/include/asm/cachetype.h
@@ -0,0 +1,52 @@
+#ifndef __ASM_ARM_CACHETYPE_H
+#define __ASM_ARM_CACHETYPE_H
+
+#define CACHEID_VIVT                    (1 << 0)
+#define CACHEID_VIPT_NONALIASING        (1 << 1)
+#define CACHEID_VIPT_ALIASING           (1 << 2)
+#define CACHEID_VIPT                    (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING)
+#define CACHEID_ASID_TAGGED             (1 << 3)
+
+extern unsigned int cacheid;
+
+#define cache_is_vivt()                 cacheid_is(CACHEID_VIVT)
+#define cache_is_vipt()                 cacheid_is(CACHEID_VIPT)
+#define cache_is_vipt_nonaliasing()     cacheid_is(CACHEID_VIPT_NONALIASING)
+#define cache_is_vipt_aliasing()        cacheid_is(CACHEID_VIPT_ALIASING)
+#define icache_is_vivt_asid_tagged()    cacheid_is(CACHEID_ASID_TAGGED)
+
+/*
+ * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
+ * Mask out support which will never be present on newer CPUs.
+ * - v6+ is never VIVT
+ * - v7+ VIPT never aliases
+ */
+#if __LINUX_ARM_ARCH__ >= 7
+#define __CACHEID_ARCH_MIN      (CACHEID_VIPT_NONALIASING | CACHEID_ASID_TAGGED)
+#elif __LINUX_ARM_ARCH__ >= 6
+#define __CACHEID_ARCH_MIN      (~CACHEID_VIVT)
+#else
+#define __CACHEID_ARCH_MIN      (~0)
+#endif
+
+/*
+ * Mask out support which isn't configured
+ */
+#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
+#define __CACHEID_ALWAYS        (CACHEID_VIVT)
+#define __CACHEID_NEVER         (~CACHEID_VIVT)
+#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
+#define __CACHEID_ALWAYS        (0)
+#define __CACHEID_NEVER         (CACHEID_VIVT)
+#else
+#define __CACHEID_ALWAYS        (0)
+#define __CACHEID_NEVER         (0)
+#endif
+
+static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
+{
+        return (__CACHEID_ALWAYS & mask) |
+               (~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
+}
+
+#endif
diff --git a/arch/arm/include/asm/cnt32_to_63.h b/arch/arm/include/asm/cnt32_to_63.h
deleted file mode 100644
index 480c873fa746..000000000000
--- a/arch/arm/include/asm/cnt32_to_63.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  include/asm/cnt32_to_63.h -- extend a 32-bit counter to 63 bits
- *
- *  Author:     Nicolas Pitre
- *  Created:    December 3, 2006
- *  Copyright:  MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- */
-
-#ifndef __INCLUDE_CNT32_TO_63_H__
-#define __INCLUDE_CNT32_TO_63_H__
-
-#include <linux/compiler.h>
-#include <asm/types.h>
-#include <asm/byteorder.h>
-
-/*
- * Prototype: u64 cnt32_to_63(u32 cnt)
- * Many hardware clock counters are only 32 bits wide and therefore have
- * a relatively short period making wrap-arounds rather frequent.  This
- * is a problem when implementing sched_clock() for example, where a 64-bit
- * non-wrapping monotonic value is expected to be returned.
- *
- * To overcome that limitation, let's extend a 32-bit counter to 63 bits
- * in a completely lock free fashion. Bits 0 to 31 of the clock are provided
- * by the hardware while bits 32 to 62 are stored in memory.  The top bit in
- * memory is used to synchronize with the hardware clock half-period.  When
- * the top bit of both counters (hardware and in memory) differ then the
- * memory is updated with a new value, incrementing it when the hardware
- * counter wraps around.
- *
- * Because a word store in memory is atomic then the incremented value will
- * always be in synch with the top bit indicating to any potential concurrent
- * reader if the value in memory is up to date or not with regards to the
- * needed increment.  And any race in updating the value in memory is harmless
- * as the same value would simply be stored more than once.
- *
- * The only restriction for the algorithm to work properly is that this
- * code must be executed at least once per each half period of the 32-bit
- * counter to properly update the state bit in memory. This is usually not a
- * problem in practice, but if it is then a kernel timer could be scheduled
- * to manage for this code to be executed often enough.
- *
- * Note that the top bit (bit 63) in the returned value should be considered
- * as garbage.  It is not cleared here because callers are likely to use a
- * multiplier on the returned value which can get rid of the top bit
- * implicitly by making the multiplier even, therefore saving on a runtime
- * clear-bit instruction. Otherwise caller must remember to clear the top
- * bit explicitly.
- */
-
-/* this is used only to give gcc a clue about good code generation */
-typedef union {
-        struct {
-#if defined(__LITTLE_ENDIAN)
-                u32 lo, hi;
-#elif defined(__BIG_ENDIAN)
-                u32 hi, lo;
-#endif
-        };
-        u64 val;
-} cnt32_to_63_t;
-
-#define cnt32_to_63(cnt_lo) \
-({ \
-        static volatile u32 __m_cnt_hi = 0; \
-        cnt32_to_63_t __x; \
-        __x.hi = __m_cnt_hi; \
-        __x.lo = (cnt_lo); \
-        if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \
-                __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \
-        __x.val; \
-})
-
-#endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
new file mode 100644
index 000000000000..7b9d27e749b8
--- /dev/null
+++ b/arch/arm/include/asm/cputype.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_ARM_CPUTYPE_H
+#define __ASM_ARM_CPUTYPE_H
+
+#include <linux/stringify.h>
+
+#define CPUID_ID        0
+#define CPUID_CACHETYPE 1
+#define CPUID_TCM       2
+#define CPUID_TLBTYPE   3
+
+#ifdef CONFIG_CPU_CP15
+#define read_cpuid(reg)                                                 \
+        ({                                                              \
+                unsigned int __val;                                     \
+                asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
+                    : "=r" (__val)                                      \
+                    :                                                   \
+                    : "cc");                                            \
+                __val;                                                  \
+        })
+#else
+extern unsigned int processor_id;
+#define read_cpuid(reg) (processor_id)
+#endif
+
+/*
+ * The CPU ID never changes at run time, so we might as well tell the
+ * compiler that it's constant.  Use this function to read the CPU ID
+ * rather than directly reading processor_id or read_cpuid() directly.
+ */
+static inline unsigned int __attribute_const__ read_cpuid_id(void)
+{
+        return read_cpuid(CPUID_ID);
+}
+
+static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
+{
+        return read_cpuid(CPUID_CACHETYPE);
+}
+
+/*
+ * Intel's XScale3 core supports some v6 features (supersections, L2)
+ * but advertises itself as v5 as it does not support the v6 ISA.  For
+ * this reason, we need a way to explicitly test for this type of CPU.
+ */
+#ifndef CONFIG_CPU_XSC3
+#define cpu_is_xsc3()   0
+#else
+static inline int cpu_is_xsc3(void)
+{
+        if ((read_cpuid_id() & 0xffffe000) == 0x69056000)
+                return 1;
+
+        return 0;
+}
+#endif
+
+#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
+#define cpu_is_xscale() 0
+#else
+#define cpu_is_xscale() 1
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 7b95d2058395..1cb8602dd9d5 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -104,15 +104,14 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
  * Dummy noncoherent implementation.  We don't provide a dma_cache_sync
  * function so drivers using this API are highlighted with build warnings.
  */
-static inline void *
-dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
+static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
+                dma_addr_t *handle, gfp_t gfp)
 {
         return NULL;
 }
 
-static inline void
-dma_free_noncoherent(struct device *dev, size_t size, void *cpu_addr,
-                     dma_addr_t handle)
+static inline void dma_free_noncoherent(struct device *dev, size_t size,
+                void *cpu_addr, dma_addr_t handle)
 {
 }
 
@@ -127,8 +126,7 @@ dma_free_noncoherent(struct device *dev, size_t size, void *cpu_addr,
  * return the CPU-viewed address, and sets @handle to be the
  * device-viewed address.
  */
-extern void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
+extern void *dma_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
 
 /**
  * dma_free_coherent - free memory allocated by dma_alloc_coherent
@@ -143,9 +141,7 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gf
  * References to memory and mappings associated with cpu_addr/handle
  * during and after this call executing are illegal.
  */
-extern void
-dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
-                  dma_addr_t handle);
+extern void dma_free_coherent(struct device *, size_t, void *, dma_addr_t);
 
 /**
  * dma_mmap_coherent - map a coherent DMA allocation into user space
@@ -159,8 +155,8 @@ dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
  * into user space.  The coherent DMA buffer must not be freed by the
  * driver until the user space mapping has been released.
  */
-int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
-                      void *cpu_addr, dma_addr_t handle, size_t size);
+int dma_mmap_coherent(struct device *, struct vm_area_struct *,
+                void *, dma_addr_t, size_t);
 
 
 /**
@@ -174,14 +170,94 @@ int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
  * return the CPU-viewed address, and sets @handle to be the
  * device-viewed address.
  */
-extern void *
-dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
+extern void *dma_alloc_writecombine(struct device *, size_t, dma_addr_t *,
+                gfp_t);
 
 #define dma_free_writecombine(dev,size,cpu_addr,handle) \
         dma_free_coherent(dev,size,cpu_addr,handle)
 
-int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
-                          void *cpu_addr, dma_addr_t handle, size_t size);
+int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
+                void *, dma_addr_t, size_t);
+
+
+#ifdef CONFIG_DMABOUNCE
+/*
+ * For SA-1111, IXP425, and ADI systems  the dma-mapping functions are "magic"
+ * and utilize bounce buffers as needed to work around limited DMA windows.
+ *
+ * On the SA-1111, a bug limits DMA to only certain regions of RAM.
+ * On the IXP425, the PCI inbound window is 64MB (256MB total RAM)
+ * On some ADI engineering systems, PCI inbound window is 32MB (12MB total RAM)
+ *
+ * The following are helper functions used by the dmabounce subystem
+ *
+ */
+
+/**
+ * dmabounce_register_dev
+ *
+ * @dev: valid struct device pointer
+ * @small_buf_size: size of buffers to use with small buffer pool
+ * @large_buf_size: size of buffers to use with large buffer pool (can be 0)
+ *
+ * This function should be called by low-level platform code to register
+ * a device as requireing DMA buffer bouncing. The function will allocate
+ * appropriate DMA pools for the device.
+ *
+ */
+extern int dmabounce_register_dev(struct device *, unsigned long,
+                unsigned long);
+
+/**
+ * dmabounce_unregister_dev
+ *
+ * @dev: valid struct device pointer
+ *
+ * This function should be called by low-level platform code when device
+ * that was previously registered with dmabounce_register_dev is removed
+ * from the system.
+ *
+ */
+extern void dmabounce_unregister_dev(struct device *);
+
+/**
+ * dma_needs_bounce
+ *
+ * @dev: valid struct device pointer
+ * @dma_handle: dma_handle of unbounced buffer
+ * @size: size of region being mapped
+ *
+ * Platforms that utilize the dmabounce mechanism must implement
+ * this function.
+ *
+ * The dmabounce routines call this function whenever a dma-mapping
+ * is requested to determine whether a given buffer needs to be bounced
+ * or not. The function must return 0 if the buffer is OK for
+ * DMA access and 1 if the buffer needs to be bounced.
+ *
+ */
+extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
+
+/*
+ * The DMA API, implemented by dmabounce.c.  See below for descriptions.
+ */
+extern dma_addr_t dma_map_single(struct device *, void *, size_t,
+                enum dma_data_direction);
+extern dma_addr_t dma_map_page(struct device *, struct page *,
+                unsigned long, size_t, enum dma_data_direction);
+extern void dma_unmap_single(struct device *, dma_addr_t, size_t,
+                enum dma_data_direction);
+
+/*
+ * Private functions
+ */
+int dmabounce_sync_for_cpu(struct device *, dma_addr_t, unsigned long,
+                size_t, enum dma_data_direction);
+int dmabounce_sync_for_device(struct device *, dma_addr_t, unsigned long,
+                size_t, enum dma_data_direction);
+#else
+#define dmabounce_sync_for_cpu(dev,dma,off,sz,dir)      (1)
+#define dmabounce_sync_for_device(dev,dma,off,sz,dir)   (1)
 
 
 /**
@@ -198,19 +274,16 @@ int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
  * can regain ownership by calling dma_unmap_single() or
  * dma_sync_single_for_cpu().
  */
-#ifndef CONFIG_DMABOUNCE
-static inline dma_addr_t
-dma_map_single(struct device *dev, void *cpu_addr, size_t size,
-               enum dma_data_direction dir)
+static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+                size_t size, enum dma_data_direction dir)
 {
+        BUG_ON(!valid_dma_direction(dir));
+
         if (!arch_is_coherent())
                 dma_cache_maint(cpu_addr, size, dir);
 
         return virt_to_dma(dev, cpu_addr);
 }
-#else
-extern dma_addr_t dma_map_single(struct device *,void *, size_t, enum dma_data_direction);
-#endif
 
 /**
  * dma_map_page - map a portion of a page for streaming DMA
@@ -224,23 +297,25 @@ extern dma_addr_t dma_map_single(struct device *,void *, size_t, enum dma_data_d
  * or written back.
  *
  * The device owns this memory once this call has completed.  The CPU
- * can regain ownership by calling dma_unmap_page() or
- * dma_sync_single_for_cpu().
+ * can regain ownership by calling dma_unmap_page().
  */
-static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page,
-             unsigned long offset, size_t size,
-             enum dma_data_direction dir)
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+             unsigned long offset, size_t size, enum dma_data_direction dir)
 {
-        return dma_map_single(dev, page_address(page) + offset, size, dir);
+        BUG_ON(!valid_dma_direction(dir));
+
+        if (!arch_is_coherent())
+                dma_cache_maint(page_address(page) + offset, size, dir);
+
+        return page_to_dma(dev, page) + offset;
 }
 
 /**
  * dma_unmap_single - unmap a single buffer previously mapped
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  * @handle: DMA address of buffer
- * @size: size of buffer to map
- * @dir: DMA transfer direction
+ * @size: size of buffer (same as passed to dma_map_single)
+ * @dir: DMA transfer direction (same as passed to dma_map_single)
  *
  * Unmap a single streaming mode DMA translation.  The handle and size
  * must match what was provided in the previous dma_map_single() call.
@@ -249,108 +324,34 @@ dma_map_page(struct device *dev, struct page *page,
  * After this call, reads by the CPU to the buffer are guaranteed to see
  * whatever the device wrote there.
  */
-#ifndef CONFIG_DMABOUNCE
-static inline void
-dma_unmap_single(struct device *dev, dma_addr_t handle, size_t size,
-                 enum dma_data_direction dir)
+static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir)
 {
         /* nothing to do */
 }
-#else
-extern void dma_unmap_single(struct device *, dma_addr_t, size_t, enum dma_data_direction);
-#endif
+#endif /* CONFIG_DMABOUNCE */
 
 /**
  * dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  * @handle: DMA address of buffer
- * @size: size of buffer to map
- * @dir: DMA transfer direction
+ * @size: size of buffer (same as passed to dma_map_page)
+ * @dir: DMA transfer direction (same as passed to dma_map_page)
  *
- * Unmap a single streaming mode DMA translation.  The handle and size
- * must match what was provided in the previous dma_map_single() call.
+ * Unmap a page streaming mode DMA translation.  The handle and size
+ * must match what was provided in the previous dma_map_page() call.
  * All other usages are undefined.
  *
  * After this call, reads by the CPU to the buffer are guaranteed to see
  * whatever the device wrote there.
  */
-static inline void
-dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size,
-               enum dma_data_direction dir)
+static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir)
 {
         dma_unmap_single(dev, handle, size, dir);
 }
 
 /**
- * dma_map_sg - map a set of SG buffers for streaming mode DMA
- * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
- * @sg: list of buffers
- * @nents: number of buffers to map
- * @dir: DMA transfer direction
- *
- * Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scatter-gather version of the
- * above dma_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for dma_map_single are
- * the same here.
- */
-#ifndef CONFIG_DMABOUNCE
-static inline int
-dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-           enum dma_data_direction dir)
-{
-        int i;
-
-        for (i = 0; i < nents; i++, sg++) {
-                char *virt;
-
-                sg->dma_address = page_to_dma(dev, sg_page(sg)) + sg->offset;
-                virt = sg_virt(sg);
-
-                if (!arch_is_coherent())
-                        dma_cache_maint(virt, sg->length, dir);
-        }
-
-        return nents;
-}
-#else
-extern int dma_map_sg(struct device *, struct scatterlist *, int, enum dma_data_direction);
-#endif
-
-/**
- * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
- * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
- * @sg: list of buffers
- * @nents: number of buffers to map
- * @dir: DMA transfer direction
- *
- * Unmap a set of streaming mode DMA translations.
- * Again, CPU read rules concerning calls here are the same as for
- * dma_unmap_single() above.
- */
-#ifndef CONFIG_DMABOUNCE
-static inline void
-dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
-             enum dma_data_direction dir)
-{
-
-        /* nothing to do */
-}
-#else
-extern void dma_unmap_sg(struct device *, struct scatterlist *, int, enum dma_data_direction);
-#endif
-
-
-/**
  * dma_sync_single_range_for_cpu
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  * @handle: DMA address of buffer
@@ -368,145 +369,52 @@ extern void dma_unmap_sg(struct device *, struct scatterlist *, int, enum dma_da
  * must first the perform a dma_sync_for_device, and then the
  * device again owns the buffer.
  */
-#ifndef CONFIG_DMABOUNCE
-static inline void
-dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t handle,
-                              unsigned long offset, size_t size,
-                              enum dma_data_direction dir)
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+                dma_addr_t handle, unsigned long offset, size_t size,
+                enum dma_data_direction dir)
 {
-        if (!arch_is_coherent())
-                dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
+        BUG_ON(!valid_dma_direction(dir));
+
+        dmabounce_sync_for_cpu(dev, handle, offset, size, dir);
 }
 
-static inline void
-dma_sync_single_range_for_device(struct device *dev, dma_addr_t handle,
-                                 unsigned long offset, size_t size,
-                                 enum dma_data_direction dir)
+static inline void dma_sync_single_range_for_device(struct device *dev,
+                dma_addr_t handle, unsigned long offset, size_t size,
+                enum dma_data_direction dir)
 {
+        BUG_ON(!valid_dma_direction(dir));
+
+        if (!dmabounce_sync_for_device(dev, handle, offset, size, dir))
+                return;
+
         if (!arch_is_coherent())
                 dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
 }
-#else
-extern void dma_sync_single_range_for_cpu(struct device *, dma_addr_t, unsigned long, size_t, enum dma_data_direction);
-extern void dma_sync_single_range_for_device(struct device *, dma_addr_t, unsigned long, size_t, enum dma_data_direction);
-#endif
 
-static inline void
-dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
-                        enum dma_data_direction dir)
+static inline void dma_sync_single_for_cpu(struct device *dev,
+                dma_addr_t handle, size_t size, enum dma_data_direction dir)
 {
         dma_sync_single_range_for_cpu(dev, handle, 0, size, dir);
 }
 
-static inline void
-dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
-                           enum dma_data_direction dir)
+static inline void dma_sync_single_for_device(struct device *dev,
+                dma_addr_t handle, size_t size, enum dma_data_direction dir)
 {
         dma_sync_single_range_for_device(dev, handle, 0, size, dir);
 }
 
-
-/**
- * dma_sync_sg_for_cpu
- * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
- * @sg: list of buffers
- * @nents: number of buffers to map
- * @dir: DMA transfer direction
- *
- * Make physical memory consistent for a set of streaming
- * mode DMA translations after a transfer.
- *
- * The same as dma_sync_single_for_* but for a scatter-gather list,
- * same rules and usage.
- */
-#ifndef CONFIG_DMABOUNCE
-static inline void
-dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
-                    enum dma_data_direction dir)
-{
-        int i;
-
-        for (i = 0; i < nents; i++, sg++) {
-                char *virt = sg_virt(sg);
-                if (!arch_is_coherent())
-                        dma_cache_maint(virt, sg->length, dir);
-        }
-}
-
-static inline void
-dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
-                       enum dma_data_direction dir)
-{
-        int i;
-
-        for (i = 0; i < nents; i++, sg++) {
-                char *virt = sg_virt(sg);
-                if (!arch_is_coherent())
-                        dma_cache_maint(virt, sg->length, dir);
-        }
-}
-#else
-extern void dma_sync_sg_for_cpu(struct device*, struct scatterlist*, int, enum dma_data_direction);
-extern void dma_sync_sg_for_device(struct device*, struct scatterlist*, int, enum dma_data_direction);
-#endif
-
-#ifdef CONFIG_DMABOUNCE
 /*
- * For SA-1111, IXP425, and ADI systems  the dma-mapping functions are "magic"
- * and utilize bounce buffers as needed to work around limited DMA windows.
- *
- * On the SA-1111, a bug limits DMA to only certain regions of RAM.
- * On the IXP425, the PCI inbound window is 64MB (256MB total RAM)
- * On some ADI engineering systems, PCI inbound window is 32MB (12MB total RAM)
- *
- * The following are helper functions used by the dmabounce subystem
- *
- */
-
-/**
- * dmabounce_register_dev
- *
- * @dev: valid struct device pointer
- * @small_buf_size: size of buffers to use with small buffer pool
- * @large_buf_size: size of buffers to use with large buffer pool (can be 0)
- *
- * This function should be called by low-level platform code to register
- * a device as requireing DMA buffer bouncing. The function will allocate
- * appropriate DMA pools for the device.
- *
- */
-extern int dmabounce_register_dev(struct device *, unsigned long, unsigned long);
-
-/**
- * dmabounce_unregister_dev
- *
- * @dev: valid struct device pointer
- *
- * This function should be called by low-level platform code when device
- * that was previously registered with dmabounce_register_dev is removed
- * from the system.
- *
+ * The scatter list versions of the above methods.
  */
-extern void dmabounce_unregister_dev(struct device *);
+extern int dma_map_sg(struct device *, struct scatterlist *, int,
+                enum dma_data_direction);
+extern void dma_unmap_sg(struct device *, struct scatterlist *, int,
+                enum dma_data_direction);
+extern void dma_sync_sg_for_cpu(struct device *, struct scatterlist *, int,
+                enum dma_data_direction);
+extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
+                enum dma_data_direction);
 
-/**
- * dma_needs_bounce
- *
- * @dev: valid struct device pointer
- * @dma_handle: dma_handle of unbounced buffer
- * @size: size of region being mapped
- *
- * Platforms that utilize the dmabounce mechanism must implement
- * this function.
- *
- * The dmabounce routines call this function whenever a dma-mapping
- * is requested to determine whether a given buffer needs to be bounced
- * or not. The function must return 0 if the buffer is OK for
- * DMA access and 1 if the buffer needs to be bounced.
- *
- */
-extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
-#endif /* CONFIG_DMABOUNCE */
 
 #endif /* __KERNEL__ */
 #endif
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 4ca751627489..5be016980c19 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -3,7 +3,6 @@
 
 #include <asm/hwcap.h>
 
-#ifndef __ASSEMBLY__
 /*
  * ELF register definitions..
  */
@@ -17,12 +16,34 @@ typedef unsigned long elf_freg_t[3];
 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 
 typedef struct user_fp elf_fpregset_t;
-#endif
 
 #define EM_ARM  40
-#define EF_ARM_APCS26 0x08
-#define EF_ARM_SOFT_FLOAT 0x200
-#define EF_ARM_EABI_MASK 0xFF000000
+
+#define EF_ARM_EABI_MASK        0xff000000
+#define EF_ARM_EABI_UNKNOWN     0x00000000
+#define EF_ARM_EABI_VER1        0x01000000
+#define EF_ARM_EABI_VER2        0x02000000
+#define EF_ARM_EABI_VER3        0x03000000
+#define EF_ARM_EABI_VER4        0x04000000
+#define EF_ARM_EABI_VER5        0x05000000
+
+#define EF_ARM_BE8              0x00800000      /* ABI 4,5 */
+#define EF_ARM_LE8              0x00400000      /* ABI 4,5 */
+#define EF_ARM_MAVERICK_FLOAT   0x00000800      /* ABI 0 */
+#define EF_ARM_VFP_FLOAT        0x00000400      /* ABI 0 */
+#define EF_ARM_SOFT_FLOAT       0x00000200      /* ABI 0 */
+#define EF_ARM_OLD_ABI          0x00000100      /* ABI 0 */
+#define EF_ARM_NEW_ABI          0x00000080      /* ABI 0 */
+#define EF_ARM_ALIGN8           0x00000040      /* ABI 0 */
+#define EF_ARM_PIC              0x00000020      /* ABI 0 */
+#define EF_ARM_MAPSYMSFIRST     0x00000010      /* ABI 2 */
+#define EF_ARM_APCS_FLOAT       0x00000010      /* ABI 0, floats in fp regs */
+#define EF_ARM_DYNSYMSUSESEGIDX 0x00000008      /* ABI 2 */
+#define EF_ARM_APCS_26          0x00000008      /* ABI 0 */
+#define EF_ARM_SYMSARESORTED    0x00000004      /* ABI 1,2 */
+#define EF_ARM_INTERWORK        0x00000004      /* ABI 0 */
+#define EF_ARM_HASENTRY         0x00000002      /* All */
+#define EF_ARM_RELEXEC          0x00000001      /* All */
 
 #define R_ARM_NONE      0
 #define R_ARM_PC24      1
@@ -41,7 +62,6 @@ typedef struct user_fp elf_fpregset_t;
 #endif
 #define ELF_ARCH        EM_ARM
 
-#ifndef __ASSEMBLY__
 /*
  * This yields a string that ld.so will use to load implementation
  * specific libraries for optimization.  This is more specific in
@@ -59,25 +79,17 @@ typedef struct user_fp elf_fpregset_t;
 #define ELF_PLATFORM    (elf_platform)
 
 extern char elf_platform[];
-#endif
 
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x))
+struct elf32_hdr;
 
 /*
- * 32-bit code is always OK.  Some cpus can do 26-bit, some can't.
+ * This is used to ensure we don't load something for the wrong architecture.
  */
-#define ELF_PROC_OK(x)  (ELF_THUMB_OK(x) && ELF_26BIT_OK(x))
-
-#define ELF_THUMB_OK(x) \
-        ((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \
-         ((x)->e_entry & 3) == 0)
+extern int elf_check_arch(const struct elf32_hdr *);
+#define elf_check_arch elf_check_arch
 
-#define ELF_26BIT_OK(x) \
-        ((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \
-          ((x)->e_flags & EF_ARM_APCS26) == 0)
+extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int);
+#define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk)
 
 #define USE_ELF_CORE_DUMP
 #define ELF_EXEC_PAGESIZE       4096
@@ -94,23 +106,7 @@ extern char elf_platform[];
    have no such handler.  */
 #define ELF_PLAT_INIT(_r, load_addr)    (_r)->ARM_r0 = 0
 
-/*
- * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0
- * and CP1, we only enable access to the iWMMXt coprocessor if the
- * binary is EABI or softfloat (and thus, guaranteed not to use
- * FPA instructions.)
- */
-#define SET_PERSONALITY(ex, ibcs2)                                      \
-        do {                                                            \
-                if ((ex).e_flags & EF_ARM_APCS26) {                     \
-                        set_personality(PER_LINUX);                     \
-                } else {                                                \
-                        set_personality(PER_LINUX_32BIT);               \
-                        if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \
-                                set_thread_flag(TIF_USING_IWMMXT);      \
-                        else                                            \
-                                clear_thread_flag(TIF_USING_IWMMXT);    \
-                }                                                       \
-        } while (0)
+extern void elf_set_personality(const struct elf32_hdr *);
+#define SET_PERSONALITY(ex, ibcs2)      elf_set_personality(&(ex))
 
 #endif
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 6a332a9f099c..9ee743b95de8 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -1,6 +1,124 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
+#ifndef _ASM_ARM_FUTEX_H
+#define _ASM_ARM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_SMP
 
 #include <asm-generic/futex.h>
 
-#endif
+#else /* !SMP, we can work around lack of atomic ops by disabling preemption */
+
+#include <linux/futex.h>
+#include <linux/preempt.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)      \
+        __asm__ __volatile__(                                   \
+        "1:     ldrt    %1, [%2]\n"                             \
+        "       " insn "\n"                                     \
+        "2:     strt    %0, [%2]\n"                             \
+        "       mov     %0, #0\n"                               \
+        "3:\n"                                                  \
+        "       .section __ex_table,\"a\"\n"                    \
+        "       .align  3\n"                                    \
+        "       .long   1b, 4f, 2b, 4f\n"                       \
+        "       .previous\n"                                    \
+        "       .section .fixup,\"ax\"\n"                       \
+        "4:     mov     %0, %4\n"                               \
+        "       b       3b\n"                                   \
+        "       .previous"                                      \
+        : "=&r" (ret), "=&r" (oldval)                           \
+        : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT)              \
+        : "cc", "memory")
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        pagefault_disable();    /* implies preempt_disable() */
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op("mov  %0, %3", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ADD:
+                __futex_atomic_op("add  %0, %1, %3", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op("orr  %0, %1, %3", ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op("and  %0, %1, %3", ret, oldval, uaddr, ~oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op("eor  %0, %1, %3", ret, oldval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        pagefault_enable();     /* subsumes preempt_enable() */
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+        int val;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        pagefault_disable();    /* implies preempt_disable() */
+
+        __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
+        "1:     ldrt    %0, [%3]\n"
+        "       teq     %0, %1\n"
+        "2:     streqt  %2, [%3]\n"
+        "3:\n"
+        "       .section __ex_table,\"a\"\n"
+        "       .align  3\n"
+        "       .long   1b, 4f, 2b, 4f\n"
+        "       .previous\n"
+        "       .section .fixup,\"ax\"\n"
+        "4:     mov     %0, %4\n"
+        "       b       3b\n"
+        "       .previous"
+        : "=&r" (val)
+        : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
+        : "cc", "memory");
+
+        pagefault_enable();     /* subsumes preempt_enable() */
+
+        return val;
+}
+
+#endif /* !SMP */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_ARM_FUTEX_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 71934856fc22..a8094451be57 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -60,10 +60,9 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 #define MT_DEVICE               0
 #define MT_DEVICE_NONSHARED     1
 #define MT_DEVICE_CACHED        2
-#define MT_DEVICE_IXP2000       3
-#define MT_DEVICE_WC            4
+#define MT_DEVICE_WC            3
 /*
- * types 5 onwards can be found in asm/mach/map.h and are undefined
+ * types 4 onwards can be found in asm/mach/map.h and are undefined
  * for ioremap
  */
 
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index d6786090d02c..a0009aa5d157 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -22,6 +22,10 @@
 #ifndef __ASSEMBLY__
 struct irqaction;
 extern void migrate_irqs(void);
+
+extern void asm_do_IRQ(unsigned int, struct pt_regs *);
+void init_IRQ(void);
+
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h
index a5d0d99ad387..bb8a19bd5822 100644
--- a/arch/arm/include/asm/kprobes.h
+++ b/arch/arm/include/asm/kprobes.h
@@ -61,7 +61,6 @@ struct kprobe_ctlblk {
 void arch_remove_kprobe(struct kprobe *);
 void kretprobe_trampoline(void);
 
-int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr);
 int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr);
 int kprobe_exceptions_notify(struct notifier_block *self,
                              unsigned long val, void *data);
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index 9eb936e49cc3..cb1139ac1943 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -18,16 +18,13 @@ struct map_desc {
         unsigned int type;
 };
 
-/* types 0-4 are defined in asm/io.h */
-#define MT_CACHECLEAN           5
-#define MT_MINICLEAN            6
-#define MT_LOW_VECTORS          7
-#define MT_HIGH_VECTORS         8
-#define MT_MEMORY               9
-#define MT_ROM                  10
-
-#define MT_NONSHARED_DEVICE     MT_DEVICE_NONSHARED
-#define MT_IXP2000_DEVICE       MT_DEVICE_IXP2000
+/* types 0-3 are defined in asm/io.h */
+#define MT_CACHECLEAN           4
+#define MT_MINICLEAN            5
+#define MT_LOW_VECTORS          6
+#define MT_HIGH_VECTORS         7
+#define MT_MEMORY               8
+#define MT_ROM                  9
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/mach/udc_pxa2xx.h b/arch/arm/include/asm/mach/udc_pxa2xx.h
index 270902c353fd..f3eabf1ecec3 100644
--- a/arch/arm/include/asm/mach/udc_pxa2xx.h
+++ b/arch/arm/include/asm/mach/udc_pxa2xx.h
@@ -18,8 +18,7 @@ struct pxa2xx_udc_mach_info {
         /* Boards following the design guidelines in the developer's manual,
          * with on-chip GPIOs not Lubbock's weird hardware, can have a sane
          * VBUS IRQ and omit the methods above.  Store the GPIO number
-         * here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits.
-         * Note that sometimes the signals go through inverters...
+         * here.  Note that sometimes the signals go through inverters...
          */
         bool    gpio_vbus_inverted;
         u16     gpio_vbus;                      /* high == vbus present */
diff --git a/arch/arm/include/asm/mc146818rtc.h b/arch/arm/include/asm/mc146818rtc.h
index e1ca48a9e973..6b884d2b0b69 100644
--- a/arch/arm/include/asm/mc146818rtc.h
+++ b/arch/arm/include/asm/mc146818rtc.h
@@ -4,8 +4,8 @@
 #ifndef _ASM_MC146818RTC_H
 #define _ASM_MC146818RTC_H
 
+#include <linux/io.h>
 #include <mach/irqs.h>
-#include <asm/io.h>
 
 #ifndef RTC_PORT
 #define RTC_PORT(x)     (0x70 + (x))
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index bf7c737c9226..809ff9ab853a 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -13,30 +13,27 @@
 #ifndef __ASM_ARM_MEMORY_H
 #define __ASM_ARM_MEMORY_H
 
+#include <linux/compiler.h>
+#include <linux/const.h>
+#include <mach/memory.h>
+#include <asm/sizes.h>
+
 /*
  * Allow for constants defined here to be used from assembly code
  * by prepending the UL suffix only with actual C code compilation.
  */
-#ifndef __ASSEMBLY__
-#define UL(x) (x##UL)
-#else
-#define UL(x) (x)
-#endif
-
-#include <linux/compiler.h>
-#include <mach/memory.h>
-#include <asm/sizes.h>
+#define UL(x) _AC(x, UL)
 
 #ifdef CONFIG_MMU
 
-#ifndef TASK_SIZE
 /*
+ * PAGE_OFFSET - the virtual address of the start of the kernel image
  * TASK_SIZE - the maximum size of a user space task.
  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
  */
-#define TASK_SIZE               UL(0xbf000000)
-#define TASK_UNMAPPED_BASE      UL(0x40000000)
-#endif
+#define PAGE_OFFSET             UL(CONFIG_PAGE_OFFSET)
+#define TASK_SIZE               (UL(CONFIG_PAGE_OFFSET) - UL(0x01000000))
+#define TASK_UNMAPPED_BASE      (UL(CONFIG_PAGE_OFFSET) / 3)
 
 /*
  * The maximum size of a 26-bit user space task.
@@ -44,13 +41,6 @@
 #define TASK_SIZE_26            UL(0x04000000)
 
 /*
- * Page offset: 3GB
- */
-#ifndef PAGE_OFFSET
-#define PAGE_OFFSET             UL(0xc0000000)
-#endif
-
-/*
  * The module space lives between the addresses given by TASK_SIZE
  * and PAGE_OFFSET - it must be within 32MB of the kernel text.
  */
@@ -147,17 +137,11 @@
 
 #ifndef arch_adjust_zones
 #define arch_adjust_zones(node,size,holes) do { } while (0)
+#elif !defined(CONFIG_ZONE_DMA)
+#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
 #endif
 
 /*
- * Amount of memory reserved for the vmalloc() area, and minimum
- * address for vmalloc mappings.
- */
-extern unsigned long vmalloc_reserve;
-
-#define VMALLOC_MIN             (void *)(VMALLOC_END - vmalloc_reserve)
-
-/*
  * PFNs are used to describe any physical page; this means
  * PFN 0 == physical address 0.
  *
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a301e446007f..0559f37c2a27 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -15,6 +15,7 @@
 
 #include <linux/compiler.h>
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 #include <asm/proc-fns.h>
 #include <asm-generic/mm_hooks.h>
 
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index cf2e2680daaa..bed1c0a00368 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -184,8 +184,9 @@ typedef struct page *pgtable_t;
 
 #endif /* !__ASSEMBLY__ */
 
-#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
-                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+#define VM_DATA_DEFAULT_FLAGS \
+        (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
+         VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
 /*
  * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 721c03d53f4b..918d0cbbf064 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -30,7 +30,7 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
  * The networking and block device layers use this boolean for bounce
  * buffer decisions.
  */
-#define PCI_DMA_BUS_IS_PHYS     (0)
+#define PCI_DMA_BUS_IS_PHYS     (1)
 
 /*
  * Whether pci_unmap_{single,page} is a nop depends upon the
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 8e21ef15bd74..110295c5461d 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -164,14 +164,30 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 #define L_PTE_PRESENT           (1 << 0)
 #define L_PTE_FILE              (1 << 1)        /* only when !PRESENT */
 #define L_PTE_YOUNG             (1 << 1)
-#define L_PTE_BUFFERABLE        (1 << 2)        /* matches PTE */
-#define L_PTE_CACHEABLE         (1 << 3)        /* matches PTE */
-#define L_PTE_USER              (1 << 4)
-#define L_PTE_WRITE             (1 << 5)
-#define L_PTE_EXEC              (1 << 6)
-#define L_PTE_DIRTY             (1 << 7)
+#define L_PTE_BUFFERABLE        (1 << 2)        /* obsolete, matches PTE */
+#define L_PTE_CACHEABLE         (1 << 3)        /* obsolete, matches PTE */
+#define L_PTE_DIRTY             (1 << 6)
+#define L_PTE_WRITE             (1 << 7)
+#define L_PTE_USER              (1 << 8)
+#define L_PTE_EXEC              (1 << 9)
 #define L_PTE_SHARED            (1 << 10)       /* shared(v6), coherent(xsc3) */
 
+/*
+ * These are the memory types, defined to be compatible with
+ * pre-ARMv6 CPUs cacheable and bufferable bits:   XXCB
+ */
+#define L_PTE_MT_UNCACHED       (0x00 << 2)     /* 0000 */
+#define L_PTE_MT_BUFFERABLE     (0x01 << 2)     /* 0001 */
+#define L_PTE_MT_WRITETHROUGH   (0x02 << 2)     /* 0010 */
+#define L_PTE_MT_WRITEBACK      (0x03 << 2)     /* 0011 */
+#define L_PTE_MT_MINICACHE      (0x06 << 2)     /* 0110 (sa1100, xscale) */
+#define L_PTE_MT_WRITEALLOC     (0x07 << 2)     /* 0111 */
+#define L_PTE_MT_DEV_SHARED     (0x04 << 2)     /* 0100 */
+#define L_PTE_MT_DEV_NONSHARED  (0x0c << 2)     /* 1100 */
+#define L_PTE_MT_DEV_WC         (0x09 << 2)     /* 1001 */
+#define L_PTE_MT_DEV_CACHED     (0x0b << 2)     /* 1011 */
+#define L_PTE_MT_MASK           (0x0f << 2)
+
 #ifndef __ASSEMBLY__
 
 /*
@@ -180,23 +196,30 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
  * as well as any architecture dependent bits like global/ASID and SMP
  * shared mapping bits.
  */
-#define _L_PTE_DEFAULT  L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_CACHEABLE | L_PTE_BUFFERABLE
-#define _L_PTE_READ     L_PTE_USER | L_PTE_EXEC
+#define _L_PTE_DEFAULT  L_PTE_PRESENT | L_PTE_YOUNG
 
 extern pgprot_t         pgprot_user;
 extern pgprot_t         pgprot_kernel;
 
-#define PAGE_NONE       pgprot_user
-#define PAGE_COPY       __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ)
-#define PAGE_SHARED     __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ | \
-                                 L_PTE_WRITE)
-#define PAGE_READONLY   __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ)
-#define PAGE_KERNEL     pgprot_kernel
-
-#define __PAGE_NONE     __pgprot(_L_PTE_DEFAULT)
-#define __PAGE_COPY     __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
-#define __PAGE_SHARED   __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE)
-#define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
+#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
+
+#define PAGE_NONE               pgprot_user
+#define PAGE_SHARED             _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE)
+#define PAGE_SHARED_EXEC        _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
+#define PAGE_COPY               _MOD_PROT(pgprot_user, L_PTE_USER)
+#define PAGE_COPY_EXEC          _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
+#define PAGE_READONLY           _MOD_PROT(pgprot_user, L_PTE_USER)
+#define PAGE_READONLY_EXEC      _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
+#define PAGE_KERNEL             pgprot_kernel
+#define PAGE_KERNEL_EXEC        _MOD_PROT(pgprot_kernel, L_PTE_EXEC)
+
+#define __PAGE_NONE             __pgprot(_L_PTE_DEFAULT)
+#define __PAGE_SHARED           __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE)
+#define __PAGE_SHARED_EXEC      __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
+#define __PAGE_COPY             __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
+#define __PAGE_COPY_EXEC        __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)
+#define __PAGE_READONLY         __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
+#define __PAGE_READONLY_EXEC    __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)
 
 #endif /* __ASSEMBLY__ */
 
@@ -212,19 +235,19 @@ extern pgprot_t		pgprot_kernel;
 #define __P001  __PAGE_READONLY
 #define __P010  __PAGE_COPY
 #define __P011  __PAGE_COPY
-#define __P100  __PAGE_READONLY
-#define __P101  __PAGE_READONLY
-#define __P110  __PAGE_COPY
-#define __P111  __PAGE_COPY
+#define __P100  __PAGE_READONLY_EXEC
+#define __P101  __PAGE_READONLY_EXEC
+#define __P110  __PAGE_COPY_EXEC
+#define __P111  __PAGE_COPY_EXEC
 
 #define __S000  __PAGE_NONE
 #define __S001  __PAGE_READONLY
 #define __S010  __PAGE_SHARED
 #define __S011  __PAGE_SHARED
-#define __S100  __PAGE_READONLY
-#define __S101  __PAGE_READONLY
-#define __S110  __PAGE_SHARED
-#define __S111  __PAGE_SHARED
+#define __S100  __PAGE_READONLY_EXEC
+#define __S101  __PAGE_READONLY_EXEC
+#define __S110  __PAGE_SHARED_EXEC
+#define __S111  __PAGE_SHARED_EXEC
 
 #ifndef __ASSEMBLY__
 /*
@@ -286,8 +309,10 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 /*
  * Mark the prot value as uncacheable and unbufferable.
  */
-#define pgprot_noncached(prot)  __pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE))
-#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~L_PTE_CACHEABLE)
+#define pgprot_noncached(prot) \
+        __pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_UNCACHED)
+#define pgprot_writecombine(prot) \
+        __pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_BUFFERABLE)
 
 #define pmd_none(pmd)           (!pmd_val(pmd))
 #define pmd_present(pmd)        (pmd_val(pmd))
@@ -320,11 +345,6 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 #define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
 
 /*
- * Permanent address of a page. We never have highmem, so this is trivial.
- */
-#define pages_to_mb(x)          ((x) >> (20 - PAGE_SHIFT))
-
-/*
  * Conversion functions: convert a page and protection to a page entry,
  * and a page entry and page directory to the page they refer to.
  */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index b415c0e85458..73192618f1c2 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -54,7 +54,6 @@
 #define PSR_C_BIT       0x20000000
 #define PSR_Z_BIT       0x40000000
 #define PSR_N_BIT       0x80000000
-#define PCMASK          0
 
 /*
  * Groups of PSR bits
@@ -139,11 +138,7 @@ static inline int valid_user_regs(struct pt_regs *regs)
         return 0;
 }
 
-#define pc_pointer(v) \
-        ((v) & ~PCMASK)
-
-#define instruction_pointer(regs) \
-        (pc_pointer((regs)->ARM_pc))
+#define instruction_pointer(regs)       (regs)->ARM_pc
 
 #ifdef CONFIG_SMP
 extern unsigned long profile_pc(struct pt_regs *regs);
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 7bbf105463f1..a65413ba121d 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -209,6 +209,17 @@ struct meminfo {
         struct membank bank[NR_BANKS];
 };
 
+#define for_each_nodebank(iter,mi,no)                   \
+        for (iter = 0; iter < mi->nr_banks; iter++)     \
+                if (mi->bank[iter].node == no)
+
+#define bank_pfn_start(bank)    __phys_to_pfn((bank)->start)
+#define bank_pfn_end(bank)      __phys_to_pfn((bank)->start + (bank)->size)
+#define bank_pfn_size(bank)     ((bank)->size >> PAGE_SHIFT)
+#define bank_phys_start(bank)   (bank)->start
+#define bank_phys_end(bank)     ((bank)->start + (bank)->size)
+#define bank_phys_size(bank)    (bank)->size
+
 /*
  * Early command line parameters.
  */
diff --git a/arch/arm/include/asm/sparsemem.h b/arch/arm/include/asm/sparsemem.h
index 277158191a0d..00098615c6f0 100644
--- a/arch/arm/include/asm/sparsemem.h
+++ b/arch/arm/include/asm/sparsemem.h
@@ -3,8 +3,22 @@
 
 #include <asm/memory.h>
 
-#define MAX_PHYSADDR_BITS       32
-#define MAX_PHYSMEM_BITS        32
-#define SECTION_SIZE_BITS       NODE_MEM_SIZE_BITS
+/*
+ * Two definitions are required for sparsemem:
+ *
+ * MAX_PHYSMEM_BITS: The number of physical address bits required
+ *   to address the last byte of memory.
+ *
+ * SECTION_SIZE_BITS: The number of physical address bits to cover
+ *   the maximum amount of memory in a section.
+ *
+ * Eg, if you have 2 banks of up to 64MB at 0x80000000, 0x84000000,
+ * then MAX_PHYSMEM_BITS is 32, SECTION_SIZE_BITS is 26.
+ *
+ * Define these in your mach/memory.h.
+ */
+#if !defined(SECTION_SIZE_BITS) || !defined(MAX_PHYSMEM_BITS)
+#error Sparsemem is not supported on this platform
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 514af792a598..7aad78420f18 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -43,11 +43,6 @@
 #define CR_XP   (1 << 23)       /* Extended page tables                 */
 #define CR_VE   (1 << 24)       /* Vectored interrupts                  */
 
-#define CPUID_ID        0
-#define CPUID_CACHETYPE 1
-#define CPUID_TCM       2
-#define CPUID_TLBTYPE   3
-
 /*
  * This is used to ensure the compiler did actually allocate the register we
  * asked it for some inline assembly sequences.  Apparently we can't trust
@@ -61,36 +56,8 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/linkage.h>
-#include <linux/stringify.h>
 #include <linux/irqflags.h>
 
-#ifdef CONFIG_CPU_CP15
-#define read_cpuid(reg)                                                 \
-        ({                                                              \
-                unsigned int __val;                                     \
-                asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
-                    : "=r" (__val)                                      \
-                    :                                                   \
-                    : "cc");                                            \
-                __val;                                                  \
-        })
-#else
-extern unsigned int processor_id;
-#define read_cpuid(reg) (processor_id)
-#endif
-
-/*
- * The CPU ID never changes at run time, so we might as well tell the
- * compiler that it's constant.  Use this function to read the CPU ID
- * rather than directly reading processor_id or read_cpuid() directly.
- */
-static inline unsigned int read_cpuid_id(void) __attribute_const__;
-
-static inline unsigned int read_cpuid_id(void)
-{
-        return read_cpuid(CPUID_ID);
-}
-
 #define __exception     __attribute__((section(".exception.text")))
 
 struct thread_info;
@@ -131,31 +98,6 @@ extern void cpu_init(void);
 void arm_machine_restart(char mode);
 extern void (*arm_pm_restart)(char str);
 
-/*
- * Intel's XScale3 core supports some v6 features (supersections, L2)
- * but advertises itself as v5 as it does not support the v6 ISA.  For
- * this reason, we need a way to explicitly test for this type of CPU.
- */
-#ifndef CONFIG_CPU_XSC3
-#define cpu_is_xsc3()   0
-#else
-static inline int cpu_is_xsc3(void)
-{
-        extern unsigned int processor_id;
-
-        if ((processor_id & 0xffffe000) == 0x69056000)
-                return 1;
-
-        return 0;
-}
-#endif
-
-#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
-#define cpu_is_xscale() 0
-#else
-#define cpu_is_xscale() 1
-#endif
-
 #define UDBG_UNDEFINED  (1 << 0)
 #define UDBG_SYSCALL    (1 << 1)
 #define UDBG_BADABORT   (1 << 2)
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index e56fa48e4ae7..68b9ec82a37f 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -98,7 +98,7 @@ static inline struct thread_info *current_thread_info(void)
 }
 
 #define thread_saved_pc(tsk)    \
-        ((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc)))
+        ((unsigned long)(task_thread_info(tsk)->cpu_context.pc))
 #define thread_saved_fp(tsk)    \
         ((unsigned long)(task_thread_info(tsk)->cpu_context.fp))
 
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index d0f51ff900b5..e98ec60b3400 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -225,7 +225,7 @@ do {									\
 
 #define __get_user_asm_byte(x,addr,err)                         \
         __asm__ __volatile__(                                   \
-        "1:     ldrbt   %1,[%2],#0\n"                           \
+        "1:     ldrbt   %1,[%2]\n"                              \
         "2:\n"                                                  \
         "       .section .fixup,\"ax\"\n"                       \
         "       .align  2\n"                                    \
@@ -261,7 +261,7 @@ do {									\
 
 #define __get_user_asm_word(x,addr,err)                         \
         __asm__ __volatile__(                                   \
-        "1:     ldrt    %1,[%2],#0\n"                           \
+        "1:     ldrt    %1,[%2]\n"                              \
         "2:\n"                                                  \
         "       .section .fixup,\"ax\"\n"                       \
         "       .align  2\n"                                    \
@@ -306,7 +306,7 @@ do {									\
 
 #define __put_user_asm_byte(x,__pu_addr,err)                    \
         __asm__ __volatile__(                                   \
-        "1:     strbt   %1,[%2],#0\n"                           \
+        "1:     strbt   %1,[%2]\n"                              \
         "2:\n"                                                  \
         "       .section .fixup,\"ax\"\n"                       \
         "       .align  2\n"                                    \
@@ -339,7 +339,7 @@ do {									\
 
 #define __put_user_asm_word(x,__pu_addr,err)                    \
         __asm__ __volatile__(                                   \
-        "1:     strt    %1,[%2],#0\n"                           \
+        "1:     strt    %1,[%2]\n"                              \
         "2:\n"                                                  \
         "       .section .fixup,\"ax\"\n"                       \
         "       .align  2\n"                                    \
@@ -365,7 +365,7 @@ do {									\
 #define __put_user_asm_dword(x,__pu_addr,err)                   \
         __asm__ __volatile__(                                   \
         "1:     strt    " __reg_oper1 ", [%1], #4\n"            \
-        "2:     strt    " __reg_oper0 ", [%1], #0\n"            \
+        "2:     strt    " __reg_oper0 ", [%1]\n"                \
         "3:\n"                                                  \
         "       .section .fixup,\"ax\"\n"                       \
         "       .align  2\n"                                    \
diff --git a/arch/arm/include/asm/vga.h b/arch/arm/include/asm/vga.h
index 6a3cd2a2f670..250a4dd00630 100644
--- a/arch/arm/include/asm/vga.h
+++ b/arch/arm/include/asm/vga.h
@@ -1,8 +1,8 @@
 #ifndef ASMARM_VGA_H
 #define ASMARM_VGA_H
 
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #define VGA_MAP_MEM(x,s)        (PCIMEM_BASE + (x))
 
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 1d296fc8494e..4305345987d3 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -10,7 +10,7 @@ endif
 
 # Object file lists.
 
-obj-y           := compat.o entry-armv.o entry-common.o irq.o \
+obj-y           := compat.o elf.o entry-armv.o entry-common.o irq.o \
                    process.o ptrace.o setup.o signal.o \
                    sys_arm.o stacktrace.o time.o traps.o
 
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index cc7b246e9652..2357b1cf1cf9 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -13,11 +13,11 @@
 #include <linux/delay.h>
 #include <linux/in6.h>
 #include <linux/syscalls.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
 
 #include <asm/checksum.h>
-#include <asm/io.h>
 #include <asm/system.h>
-#include <asm/uaccess.h>
 #include <asm/ftrace.h>
 
 /*
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index e5747547b44c..17a59b6e521f 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -10,8 +10,8 @@
 #include <linux/pci.h>
 #include <linux/slab.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/pci.h>
 
diff --git a/arch/arm/kernel/crunch.c b/arch/arm/kernel/crunch.c
index 3b6a1c293ee4..99995c2b2312 100644
--- a/arch/arm/kernel/crunch.c
+++ b/arch/arm/kernel/crunch.c
@@ -15,9 +15,9 @@
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <mach/ep93xx-regs.h>
 #include <asm/thread_notify.h>
-#include <asm/io.h>
 
 struct crunch_state *crunch_owner;
 
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index 9550ff0ddde4..f53c58290543 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -89,10 +89,12 @@
 ENTRY(printhex8)
                 mov     r1, #8
                 b       printhex
+ENDPROC(printhex8)
 
 ENTRY(printhex4)
                 mov     r1, #4
                 b       printhex
+ENDPROC(printhex4)
 
 ENTRY(printhex2)
                 mov     r1, #2
@@ -110,6 +112,7 @@ printhex:	adr	r2, hexbuf
                 bne     1b
                 mov     r0, r2
                 b       printascii
+ENDPROC(printhex2)
 
                 .ltorg
 
@@ -127,11 +130,13 @@ ENTRY(printascii)
                 teqne   r1, #0
                 bne     1b
                 mov     pc, lr
+ENDPROC(printascii)
 
 ENTRY(printch)
                 addruart r3
                 mov     r1, r0
                 mov     r0, #0
                 b       1b
+ENDPROC(printch)
 
 hexbuf:         .space 16
diff --git a/arch/arm/kernel/dma-isa.c b/arch/arm/kernel/dma-isa.c
index 2f080a35a2d9..4a3a50495c60 100644
--- a/arch/arm/kernel/dma-isa.c
+++ b/arch/arm/kernel/dma-isa.c
@@ -19,10 +19,9 @@
 #include <linux/ioport.h>
 #include <linux/init.h>
 #include <linux/dma-mapping.h>
+#include <linux/io.h>
 
 #include <asm/dma.h>
-#include <asm/io.h>
-
 #include <asm/mach/dma.h>
 
 #define ISA_DMA_MODE_READ       0x44
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index 7a50575a8d4d..60c079d85355 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -587,8 +587,7 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
                         pending = ecard_default_ops.irqpending(ec);
 
                 if (pending) {
-                        struct irq_desc *d = irq_desc + ec->irq;
-                        desc_handle_irq(ec->irq, d);
+                        generic_handle_irq(ec->irq);
                         called ++;
                 }
         }
@@ -622,7 +621,6 @@ ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
                 ecard_t *ec = slot_to_ecard(slot);
 
                 if (ec->claimed) {
-                        struct irq_desc *d = irq_desc + ec->irq;
                         /*
                          * this ugly code is so that we can operate a
                          * prioritorising system:
@@ -635,7 +633,7 @@ ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
                          * Serial cards should go in 0/1, ethernet/scsi in 2/3
                          * otherwise you will lose serial data at high speeds!
                          */
-                        desc_handle_irq(ec->irq, d);
+                        generic_handle_irq(ec->irq);
                 } else {
                         printk(KERN_WARNING "card%d: interrupt from unclaimed "
                                "card???\n", slot);
diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c
new file mode 100644
index 000000000000..513f332f040d
--- /dev/null
+++ b/arch/arm/kernel/elf.c
@@ -0,0 +1,79 @@
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/personality.h>
+#include <linux/binfmts.h>
+#include <linux/elf.h>
+
+int elf_check_arch(const struct elf32_hdr *x)
+{
+        unsigned int eflags;
+
+        /* Make sure it's an ARM executable */
+        if (x->e_machine != EM_ARM)
+                return 0;
+
+        /* Make sure the entry address is reasonable */
+        if (x->e_entry & 1) {
+                if (!(elf_hwcap & HWCAP_THUMB))
+                        return 0;
+        } else if (x->e_entry & 3)
+                return 0;
+
+        eflags = x->e_flags;
+        if ((eflags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN) {
+                /* APCS26 is only allowed if the CPU supports it */
+                if ((eflags & EF_ARM_APCS_26) && !(elf_hwcap & HWCAP_26BIT))
+                        return 0;
+
+                /* VFP requires the supporting code */
+                if ((eflags & EF_ARM_VFP_FLOAT) && !(elf_hwcap & HWCAP_VFP))
+                        return 0;
+        }
+        return 1;
+}
+EXPORT_SYMBOL(elf_check_arch);
+
+void elf_set_personality(const struct elf32_hdr *x)
+{
+        unsigned int eflags = x->e_flags;
+        unsigned int personality = PER_LINUX_32BIT;
+
+        /*
+         * APCS-26 is only valid for OABI executables
+         */
+        if ((eflags & EF_ARM_EABI_MASK) == EF_ARM_EABI_UNKNOWN) {
+                if (eflags & EF_ARM_APCS_26)
+                        personality = PER_LINUX;
+        }
+
+        set_personality(personality);
+
+        /*
+         * Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0
+         * and CP1, we only enable access to the iWMMXt coprocessor if the
+         * binary is EABI or softfloat (and thus, guaranteed not to use
+         * FPA instructions.)
+         */
+        if (elf_hwcap & HWCAP_IWMMXT &&
+            eflags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) {
+                set_thread_flag(TIF_USING_IWMMXT);
+        } else {
+                clear_thread_flag(TIF_USING_IWMMXT);
+        }
+}
+EXPORT_SYMBOL(elf_set_personality);
+
+/*
+ * Set READ_IMPLIES_EXEC if:
+ *  - the binary requires an executable stack
+ *  - we're running on a CPU which doesn't support NX.
+ */
+int arm_elf_read_implies_exec(const struct elf32_hdr *x, int executable_stack)
+{
+        if (executable_stack != EXSTACK_ENABLE_X)
+                return 1;
+        if (cpu_architecture() <= CPU_ARCH_ARMv6)
+                return 1;
+        return 0;
+}
+EXPORT_SYMBOL(arm_elf_read_implies_exec);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 617e509d60df..77b047475539 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -76,14 +76,17 @@
 __pabt_invalid:
         inv_entry BAD_PREFETCH
         b       common_invalid
+ENDPROC(__pabt_invalid)
 
 __dabt_invalid:
         inv_entry BAD_DATA
         b       common_invalid
+ENDPROC(__dabt_invalid)
 
 __irq_invalid:
         inv_entry BAD_IRQ
         b       common_invalid
+ENDPROC(__irq_invalid)
 
 __und_invalid:
         inv_entry BAD_UNDEFINSTR
@@ -107,6 +110,7 @@ common_invalid:
 
         mov     r0, sp
         b       bad_mode
+ENDPROC(__und_invalid)
 
 /*
  * SVC mode handlers
@@ -192,6 +196,7 @@ __dabt_svc:
         ldr     r0, [sp, #S_PSR]
         msr     spsr_cxsf, r0
         ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+ENDPROC(__dabt_svc)
 
         .align  5
 __irq_svc:
@@ -223,6 +228,7 @@ __irq_svc:
         bleq    trace_hardirqs_on
 #endif
         ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+ENDPROC(__irq_svc)
 
         .ltorg
 
@@ -272,6 +278,7 @@ __und_svc:
         ldr     lr, [sp, #S_PSR]                @ Get SVC cpsr
         msr     spsr_cxsf, lr
         ldmia   sp, {r0 - pc}^                  @ Restore SVC registers
+ENDPROC(__und_svc)
 
         .align  5
 __pabt_svc:
@@ -313,6 +320,7 @@ __pabt_svc:
         ldr     r0, [sp, #S_PSR]
         msr     spsr_cxsf, r0
         ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+ENDPROC(__pabt_svc)
 
         .align  5
 .LCcralign:
@@ -412,6 +420,7 @@ __dabt_usr:
         mov     r2, sp
         adr     lr, ret_from_exception
         b       do_DataAbort
+ENDPROC(__dabt_usr)
 
         .align  5
 __irq_usr:
@@ -441,6 +450,7 @@ __irq_usr:
 
         mov     why, #0
         b       ret_to_user
+ENDPROC(__irq_usr)
 
         .ltorg
 
@@ -474,6 +484,7 @@ __und_usr:
 #else
         b       __und_usr_unknown
 #endif
+ENDPROC(__und_usr)
 
         @
         @ fallthrough to call_fpe
@@ -642,6 +653,7 @@ __und_usr_unknown:
         mov     r0, sp
         adr     lr, ret_from_exception
         b       do_undefinstr
+ENDPROC(__und_usr_unknown)
 
         .align  5
 __pabt_usr:
@@ -666,6 +678,8 @@ ENTRY(ret_from_exception)
         get_thread_info tsk
         mov     why, #0
         b       ret_to_user
+ENDPROC(__pabt_usr)
+ENDPROC(ret_from_exception)
 
 /*
  * Register switch for ARMv3 and ARMv4 processors
@@ -702,6 +716,7 @@ ENTRY(__switch_to)
         bl      atomic_notifier_call_chain
         mov     r0, r5
         ldmia   r4, {r4 - sl, fp, sp, pc}       @ Load all regs saved previously
+ENDPROC(__switch_to)
 
         __INIT
 
@@ -1029,6 +1044,7 @@ vector_\name:
         mov     r0, sp
         ldr     lr, [pc, lr, lsl #2]
         movs    pc, lr                  @ branch to handler in SVC mode
+ENDPROC(vector_\name)
         .endm
 
         .globl  __stubs_start
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 060d7e2e9f64..3aa14dcc5bab 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -77,6 +77,7 @@ no_work_pending:
         mov     r0, r0
         add     sp, sp, #S_FRAME_SIZE - S_PC
         movs    pc, lr                          @ return & move spsr_svc into cpsr
+ENDPROC(ret_to_user)
 
 /*
  * This is how we return from a fork.
@@ -92,7 +93,7 @@ ENTRY(ret_from_fork)
         mov     r0, #1                          @ trace exit [IP = 1]
         bl      syscall_trace
         b       ret_slow_syscall
-        
+ENDPROC(ret_from_fork)
 
         .equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
@@ -269,6 +270,7 @@ ENTRY(vector_swi)
         eor     r0, scno, #__NR_SYSCALL_BASE    @ put OS number back
         bcs     arm_syscall     
         b       sys_ni_syscall                  @ not private func
+ENDPROC(vector_swi)
 
         /*
          * This is the really slow path.  We're going to be doing
@@ -326,7 +328,6 @@ ENTRY(sys_call_table)
  */
 @ r0 = syscall number
 @ r8 = syscall table
-                .type   sys_syscall, #function
 sys_syscall:
                 bic     scno, r0, #__NR_OABI_SYSCALL_BASE
                 cmp     scno, #__NR_syscall - __NR_SYSCALL_BASE
@@ -338,53 +339,65 @@ sys_syscall:
                 movlo   r3, r4
                 ldrlo   pc, [tbl, scno, lsl #2]
                 b       sys_ni_syscall
+ENDPROC(sys_syscall)
 
 sys_fork_wrapper:
                 add     r0, sp, #S_OFF
                 b       sys_fork
+ENDPROC(sys_fork_wrapper)
 
 sys_vfork_wrapper:
                 add     r0, sp, #S_OFF
                 b       sys_vfork
+ENDPROC(sys_vfork_wrapper)
 
 sys_execve_wrapper:
                 add     r3, sp, #S_OFF
                 b       sys_execve
+ENDPROC(sys_execve_wrapper)
 
 sys_clone_wrapper:
                 add     ip, sp, #S_OFF
                 str     ip, [sp, #4]
                 b       sys_clone
+ENDPROC(sys_clone_wrapper)
 
 sys_sigsuspend_wrapper:
                 add     r3, sp, #S_OFF
                 b       sys_sigsuspend
+ENDPROC(sys_sigsuspend_wrapper)
 
 sys_rt_sigsuspend_wrapper:
                 add     r2, sp, #S_OFF
                 b       sys_rt_sigsuspend
+ENDPROC(sys_rt_sigsuspend_wrapper)
 
 sys_sigreturn_wrapper:
                 add     r0, sp, #S_OFF
                 b       sys_sigreturn
+ENDPROC(sys_sigreturn_wrapper)
 
 sys_rt_sigreturn_wrapper:
                 add     r0, sp, #S_OFF
                 b       sys_rt_sigreturn
+ENDPROC(sys_rt_sigreturn_wrapper)
 
 sys_sigaltstack_wrapper:
                 ldr     r2, [sp, #S_OFF + S_SP]
                 b       do_sigaltstack
+ENDPROC(sys_sigaltstack_wrapper)
 
 sys_statfs64_wrapper:
                 teq     r1, #88
                 moveq   r1, #84
                 b       sys_statfs64
+ENDPROC(sys_statfs64_wrapper)
 
 sys_fstatfs64_wrapper:
                 teq     r1, #88
                 moveq   r1, #84
                 b       sys_fstatfs64
+ENDPROC(sys_fstatfs64_wrapper)
 
 /*
  * Note: off_4k (r5) is always units of 4K.  If we can't do the requested
@@ -402,11 +415,14 @@ sys_mmap2:
                 str     r5, [sp, #4]
                 b       do_mmap2
 #endif
+ENDPROC(sys_mmap2)
 
 ENTRY(pabort_ifar)
                 mrc     p15, 0, r0, cr6, cr0, 2
 ENTRY(pabort_noifar)
                 mov     pc, lr
+ENDPROC(pabort_ifar)
+ENDPROC(pabort_noifar)
 
 #ifdef CONFIG_OABI_COMPAT
 
@@ -417,26 +433,31 @@ ENTRY(pabort_noifar)
 sys_oabi_pread64:
                 stmia   sp, {r3, r4}
                 b       sys_pread64
+ENDPROC(sys_oabi_pread64)
 
 sys_oabi_pwrite64:
                 stmia   sp, {r3, r4}
                 b       sys_pwrite64
+ENDPROC(sys_oabi_pwrite64)
 
 sys_oabi_truncate64:
                 mov     r3, r2
                 mov     r2, r1
                 b       sys_truncate64
+ENDPROC(sys_oabi_truncate64)
 
 sys_oabi_ftruncate64:
                 mov     r3, r2
                 mov     r2, r1
                 b       sys_ftruncate64
+ENDPROC(sys_oabi_ftruncate64)
 
 sys_oabi_readahead:
                 str     r3, [sp]
                 mov     r3, r2
                 mov     r2, r1
                 b       sys_readahead
+ENDPROC(sys_oabi_readahead)
 
 /*
  * Let's declare a second syscall table for old ABI binaries
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index e8e90346f11c..36f81d967979 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -45,7 +45,6 @@
 #include <asm/fiq.h>
 #include <asm/irq.h>
 #include <asm/system.h>
-#include <asm/uaccess.h>
 
 static unsigned long no_fiq_insn;
 
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 1c3c6ea5f9e7..bde52df1c668 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -36,7 +36,6 @@ __switch_data:
  *  r2  = atags pointer
  *  r9  = processor ID
  */
-        .type   __mmap_switched, %function
 __mmap_switched:
         adr     r3, __switch_data + 4
 
@@ -59,6 +58,7 @@ __mmap_switched:
         bic     r4, r0, #CR_A                   @ Clear 'A' bit
         stmia   r7, {r0, r4}                    @ Save control register values
         b       start_kernel
+ENDPROC(__mmap_switched)
 
 /*
  * Exception handling.  Something went wrong and we can't proceed.  We
@@ -69,8 +69,6 @@ __mmap_switched:
  * and hope for the best (useful if bootloader fails to pass a proper
  * machine ID for example).
  */
-
-        .type   __error_p, %function
 __error_p:
 #ifdef CONFIG_DEBUG_LL
         adr     r0, str_p1
@@ -84,8 +82,8 @@ str_p1:	.asciz	"\nError: unrecognized/unsupported processor variant (0x"
 str_p2: .asciz  ").\n"
         .align
 #endif
+ENDPROC(__error_p)
 
-        .type   __error_a, %function
 __error_a:
 #ifdef CONFIG_DEBUG_LL
         mov     r4, r1                          @ preserve machine ID
@@ -115,13 +113,14 @@ __error_a:
         adr     r0, str_a3
         bl      printascii
         b       __error
+ENDPROC(__error_a)
+
 str_a1: .asciz  "\nError: unrecognized/unsupported machine ID (r1 = 0x"
 str_a2: .asciz  ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n"
 str_a3: .asciz  "\nPlease check your kernel config and/or bootloader.\n"
         .align
 #endif
 
-        .type   __error, %function
 __error:
 #ifdef CONFIG_ARCH_RPC
 /*
@@ -138,6 +137,7 @@ __error:
 #endif
 1:      mov     r0, r0
         b       1b
+ENDPROC(__error)
 
 
 /*
@@ -153,7 +153,6 @@ __error:
  *      r5 = proc_info pointer in physical address space
  *      r9 = cpuid (preserved)
  */
-        .type   __lookup_processor_type, %function
 __lookup_processor_type:
         adr     r3, 3f
         ldmda   r3, {r5 - r7}
@@ -169,6 +168,7 @@ __lookup_processor_type:
         blo     1b
         mov     r5, #0                          @ unknown processor
 2:      mov     pc, lr
+ENDPROC(__lookup_processor_type)
 
 /*
  * This provides a C-API version of the above function.
@@ -179,6 +179,7 @@ ENTRY(lookup_processor_type)
         bl      __lookup_processor_type
         mov     r0, r5
         ldmfd   sp!, {r4 - r7, r9, pc}
+ENDPROC(lookup_processor_type)
 
 /*
  * Look in <asm/procinfo.h> and arch/arm/kernel/arch.[ch] for
@@ -201,7 +202,6 @@ ENTRY(lookup_processor_type)
  *  r3, r4, r6 corrupted
  *  r5 = mach_info pointer in physical address space
  */
-        .type   __lookup_machine_type, %function
 __lookup_machine_type:
         adr     r3, 3b
         ldmia   r3, {r4, r5, r6}
@@ -216,6 +216,7 @@ __lookup_machine_type:
         blo     1b
         mov     r5, #0                          @ unknown machine
 2:      mov     pc, lr
+ENDPROC(__lookup_machine_type)
 
 /*
  * This provides a C-API version of the above function.
@@ -226,6 +227,7 @@ ENTRY(lookup_machine_type)
         bl      __lookup_machine_type
         mov     r0, r5
         ldmfd   sp!, {r4 - r6, pc}
+ENDPROC(lookup_machine_type)
 
 /* Determine validity of the r2 atags pointer.  The heuristic requires
  * that the pointer be aligned, in the first 16k of physical RAM and
@@ -239,8 +241,6 @@ ENTRY(lookup_machine_type)
  *  r2 either valid atags pointer, or zero
  *  r5, r6 corrupted
  */
-
-        .type   __vet_atags, %function
 __vet_atags:
         tst     r2, #0x3                        @ aligned?
         bne     1f
@@ -257,3 +257,4 @@ __vet_atags:
 
 1:      mov     r2, #0
         mov     pc, lr
+ENDPROC(__vet_atags)
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 27329bd32037..cc87e1765ed2 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -33,7 +33,6 @@
  *
  */
         .section ".text.head", "ax"
-        .type   stext, %function
 ENTRY(stext)
         msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
                                                 @ and irqs disabled
@@ -53,11 +52,11 @@ ENTRY(stext)
                                                 @ the initialization is done
         adr     lr, __after_proc_init           @ return (PIC) address
         add     pc, r10, #PROCINFO_INITFUNC
+ENDPROC(stext)
 
 /*
  * Set the Control Register and Read the process ID.
  */
-        .type   __after_proc_init, %function
 __after_proc_init:
 #ifdef CONFIG_CPU_CP15
         mrc     p15, 0, r0, c1, c0, 0           @ read control reg
@@ -85,6 +84,7 @@ __after_proc_init:
 
         mov     pc, r13                         @ clear the BSS and jump
                                                 @ to start_kernel
+ENDPROC(__after_proc_init)
         .ltorg
 
 #include "head-common.S"
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index bff4c6e90dd5..21e17dc94cb5 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -75,7 +75,6 @@
  * circumstances, zImage) is for.
  */
         .section ".text.head", "ax"
-        .type   stext, %function
 ENTRY(stext)
         msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
                                                 @ and irqs disabled
@@ -100,9 +99,9 @@ ENTRY(stext)
                                                 @ mmu has been enabled
         adr     lr, __enable_mmu                @ return (PIC) address
         add     pc, r10, #PROCINFO_INITFUNC
+ENDPROC(stext)
 
 #if defined(CONFIG_SMP)
-        .type   secondary_startup, #function
 ENTRY(secondary_startup)
         /*
          * Common entry point for secondary CPUs.
@@ -128,6 +127,7 @@ ENTRY(secondary_startup)
         adr     lr, __enable_mmu                @ return address
         add     pc, r10, #PROCINFO_INITFUNC     @ initialise processor
                                                 @ (return control reg)
+ENDPROC(secondary_startup)
 
         /*
          * r6  = &secondary_data
@@ -136,6 +136,7 @@ ENTRY(__secondary_switched)
         ldr     sp, [r7, #4]                    @ get secondary_data.stack
         mov     fp, #0
         b       secondary_start_kernel
+ENDPROC(__secondary_switched)
 
         .type   __secondary_data, %object
 __secondary_data:
@@ -151,7 +152,6 @@ __secondary_data:
  * this is just loading the page table pointer and domain access
  * registers.
  */
-        .type   __enable_mmu, %function
 __enable_mmu:
 #ifdef CONFIG_ALIGNMENT_TRAP
         orr     r0, r0, #CR_A
@@ -174,6 +174,7 @@ __enable_mmu:
         mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
         mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
         b       __turn_mmu_on
+ENDPROC(__enable_mmu)
 
 /*
  * Enable the MMU.  This completely changes the structure of the visible
@@ -187,7 +188,6 @@ __enable_mmu:
  * other registers depend on the function called upon completion
  */
         .align  5
-        .type   __turn_mmu_on, %function
 __turn_mmu_on:
         mov     r0, r0
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
@@ -195,7 +195,7 @@ __turn_mmu_on:
         mov     r3, r3
         mov     r3, r3
         mov     pc, r13
-
+ENDPROC(__turn_mmu_on)
 
 
 /*
@@ -211,7 +211,6 @@ __turn_mmu_on:
  *  r0, r3, r6, r7 corrupted
  *  r4 = physical page table address
  */
-        .type   __create_page_tables, %function
 __create_page_tables:
         pgtbl   r4                              @ page table address
 
@@ -325,6 +324,7 @@ __create_page_tables:
 #endif
 #endif
         mov     pc, lr
+ENDPROC(__create_page_tables)
         .ltorg
 
 #include "head-common.S"
diff --git a/arch/arm/kernel/init_task.c b/arch/arm/kernel/init_task.c
index 8b8c9d38a761..0bbf80625395 100644
--- a/arch/arm/kernel/init_task.c
+++ b/arch/arm/kernel/init_task.c
@@ -8,8 +8,8 @@
 #include <linux/init.h>
 #include <linux/init_task.h>
 #include <linux/mqueue.h>
+#include <linux/uaccess.h>
 
-#include <asm/uaccess.h>
 #include <asm/pgtable.h>
 
 static struct fs_struct init_fs = INIT_FS;
diff --git a/arch/arm/kernel/io.c b/arch/arm/kernel/io.c
index 1f6822dfae74..f4470307edb8 100644
--- a/arch/arm/kernel/io.c
+++ b/arch/arm/kernel/io.c
@@ -1,7 +1,6 @@
 #include <linux/module.h>
 #include <linux/types.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 /*
  * Copy data from IO memory space to "real" memory space.
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index f88efb135b70..2f3eb795fa6e 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -112,18 +112,17 @@ static struct irq_desc bad_irq_desc = {
 asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
 {
         struct pt_regs *old_regs = set_irq_regs(regs);
-        struct irq_desc *desc = irq_desc + irq;
+
+        irq_enter();
 
         /*
          * Some hardware gives randomly wrong interrupts.  Rather
          * than crashing, do something sensible.
          */
         if (irq >= NR_IRQS)
-                desc = &bad_irq_desc;
-
-        irq_enter();
-
-        desc_handle_irq(irq, desc);
+                handle_bad_irq(irq, &bad_irq_desc);
+        else
+                generic_handle_irq(irq);
 
         /* AT91 specific workaround */
         irq_finish(irq);
diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c
index aaffaecffcd1..ba8ccfede964 100644
--- a/arch/arm/kernel/kgdb.c
+++ b/arch/arm/kernel/kgdb.c
@@ -111,8 +111,6 @@ int kgdb_arch_handle_exception(int exception_vector, int signo,
         case 'D':
         case 'k':
         case 'c':
-                kgdb_contthread = NULL;
-
                 /*
                  * Try to read optional parameter, pc unchanged if no parm.
                  * If this was a compiled breakpoint, we need to move
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index b4565bb133c1..da1f94906a4e 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -488,7 +488,7 @@ static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
 
         if (!ubit)
                 addr -= reg_count;
-        addr += (!pbit ^ !ubit);
+        addr += (!pbit == !ubit);
 
         reg_bit_vector = insn & 0xffff;
         while (reg_bit_vector) {
@@ -503,7 +503,7 @@ static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
         if (wbit) {
                 if (!ubit)
                         addr -= reg_count;
-                addr -= (!pbit ^ !ubit);
+                addr -= (!pbit == !ubit);
                 regs->uregs[rn] = (long)addr;
         }
 }
diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
index d28513f14d05..3f9abe0e9aff 100644
--- a/arch/arm/kernel/kprobes.c
+++ b/arch/arm/kernel/kprobes.c
@@ -200,9 +200,12 @@ void __kprobes kprobe_handler(struct pt_regs *regs)
         }
 }
 
-int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr)
+static int __kprobes kprobe_trap_handler(struct pt_regs *regs, unsigned int instr)
 {
+        unsigned long flags;
+        local_irq_save(flags);
         kprobe_handler(regs);
+        local_irq_restore(flags);
         return 0;
 }
 
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index fae5beb3c3d6..440dc62cdc3a 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -6,10 +6,10 @@
 #include <linux/kexec.h>
 #include <linux/delay.h>
 #include <linux/reboot.h>
+#include <linux/io.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/mmu_context.h>
-#include <asm/io.h>
 #include <asm/cacheflush.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index a68259a0cccd..9203ba7d58ee 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -47,7 +47,7 @@ void *module_alloc(unsigned long size)
         if (!area)
                 return NULL;
 
-        return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL);
+        return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL_EXEC);
 }
 #else /* CONFIG_MMU */
 void *module_alloc(unsigned long size)
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 3fd882337064..d3ea6fa89521 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -28,12 +28,12 @@
 #include <linux/pm.h>
 #include <linux/tick.h>
 #include <linux/utsname.h>
+#include <linux/uaccess.h>
 
 #include <asm/leds.h>
 #include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/thread_notify.h>
-#include <asm/uaccess.h>
 #include <asm/mach/time.h>
 
 static const char *processor_modes[] = {
@@ -267,35 +267,6 @@ void show_regs(struct pt_regs * regs)
         __backtrace();
 }
 
-void show_fpregs(struct user_fp *regs)
-{
-        int i;
-
-        for (i = 0; i < 8; i++) {
-                unsigned long *p;
-                char type;
-
-                p = (unsigned long *)(regs->fpregs + i);
-
-                switch (regs->ftype[i]) {
-                        case 1: type = 'f'; break;
-                        case 2: type = 'd'; break;
-                        case 3: type = 'e'; break;
-                        default: type = '?'; break;
-                }
-                if (regs->init_flag)
-                        type = '?';
-
-                printk("  f%d(%c): %08lx %08lx %08lx%c",
-                        i, type, p[0], p[1], p[2], i & 1 ? '\n' : ' ');
-        }
-                        
-
-        printk("FPSR: %08lx FPCR: %08lx\n",
-                (unsigned long)regs->fpsr,
-                (unsigned long)regs->fpcr);
-}
-
 /*
  * Free current thread data structures etc..
  */
@@ -414,7 +385,7 @@ unsigned long get_wchan(struct task_struct *p)
         do {
                 if (fp < stack_start || fp > stack_end)
                         return 0;
-                lr = pc_pointer (((unsigned long *)fp)[-1]);
+                lr = ((unsigned long *)fp)[-1];
                 if (!in_sched_functions(lr))
                         return lr;
                 fp = *(unsigned long *) (fp - 12);
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 4b05dc5c1023..df653ea59250 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -18,8 +18,8 @@
 #include <linux/security.h>
 #include <linux/init.h>
 #include <linux/signal.h>
+#include <linux/uaccess.h>
 
-#include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/traps.h>
@@ -126,7 +126,7 @@ ptrace_getrn(struct task_struct *child, unsigned long insn)
 
         val = get_user_reg(child, reg);
         if (reg == 15)
-                val = pc_pointer(val + 8);
+                val += 8;
 
         return val;
 }
@@ -278,8 +278,7 @@ get_branch_address(struct task_struct *child, unsigned long pc, unsigned long in
                                 else
                                         base -= aluop2;
                         }
-                        if (read_u32(child, base, &alt) == 0)
-                                alt = pc_pointer(alt);
+                        read_u32(child, base, &alt);
                 }
                 break;
 
@@ -305,8 +304,7 @@ get_branch_address(struct task_struct *child, unsigned long pc, unsigned long in
 
                         base = ptrace_getrn(child, insn);
 
-                        if (read_u32(child, base + nr_regs, &alt) == 0)
-                                alt = pc_pointer(alt);
+                        read_u32(child, base + nr_regs, &alt);
                         break;
                 }
                 break;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 2ca7038b67a7..1f1eecca7f55 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -26,11 +26,13 @@
 #include <linux/fs.h>
 
 #include <asm/cpu.h>
+#include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/procinfo.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 #include <asm/tlbflush.h>
 
 #include <asm/mach/arch.h>
@@ -59,13 +61,14 @@ __setup("fpe=", fpe_setup);
 
 extern void paging_init(struct meminfo *, struct machine_desc *desc);
 extern void reboot_setup(char *str);
-extern int root_mountflags;
-extern void _stext, _text, _etext, __data_start, _edata, _end;
+extern void _text, _etext, __data_start, _edata, _end;
 
 unsigned int processor_id;
 EXPORT_SYMBOL(processor_id);
 unsigned int __machine_arch_type;
 EXPORT_SYMBOL(__machine_arch_type);
+unsigned int cacheid;
+EXPORT_SYMBOL(cacheid);
 
 unsigned int __atags_pointer __initdata;
 
@@ -81,8 +84,6 @@ EXPORT_SYMBOL(system_serial_high);
 unsigned int elf_hwcap;
 EXPORT_SYMBOL(elf_hwcap);
 
-unsigned long __initdata vmalloc_reserve = 128 << 20;
-
 
 #ifdef MULTI_CPU
 struct processor processor;
@@ -111,9 +112,6 @@ static struct stack stacks[NR_CPUS];
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);
 
-unsigned long phys_initrd_start __initdata = 0;
-unsigned long phys_initrd_size __initdata = 0;
-
 static struct meminfo meminfo __initdata = { 0, };
 static const char *cpu_name;
 static const char *machine_name;
@@ -178,63 +176,6 @@ static struct resource io_res[] = {
 #define lp1 io_res[1]
 #define lp2 io_res[2]
 
-static const char *cache_types[16] = {
-        "write-through",
-        "write-back",
-        "write-back",
-        "undefined 3",
-        "undefined 4",
-        "undefined 5",
-        "write-back",
-        "write-back",
-        "undefined 8",
-        "undefined 9",
-        "undefined 10",
-        "undefined 11",
-        "undefined 12",
-        "undefined 13",
-        "write-back",
-        "undefined 15",
-};
-
-static const char *cache_clean[16] = {
-        "not required",
-        "read-block",
-        "cp15 c7 ops",
-        "undefined 3",
-        "undefined 4",
-        "undefined 5",
-        "cp15 c7 ops",
-        "cp15 c7 ops",
-        "undefined 8",
-        "undefined 9",
-        "undefined 10",
-        "undefined 11",
-        "undefined 12",
-        "undefined 13",
-        "cp15 c7 ops",
-        "undefined 15",
-};
-
-static const char *cache_lockdown[16] = {
-        "not supported",
-        "not supported",
-        "not supported",
-        "undefined 3",
-        "undefined 4",
-        "undefined 5",
-        "format A",
-        "format B",
-        "undefined 8",
-        "undefined 9",
-        "undefined 10",
-        "undefined 11",
-        "undefined 12",
-        "undefined 13",
-        "format C",
-        "undefined 15",
-};
-
 static const char *proc_arch[] = {
         "undefined/unknown",
         "3",
@@ -255,61 +196,19 @@ static const char *proc_arch[] = {
         "?(17)",
 };
 
-#define CACHE_TYPE(x)   (((x) >> 25) & 15)
-#define CACHE_S(x)      ((x) & (1 << 24))
-#define CACHE_DSIZE(x)  (((x) >> 12) & 4095)    /* only if S=1 */
-#define CACHE_ISIZE(x)  ((x) & 4095)
-
-#define CACHE_SIZE(y)   (((y) >> 6) & 7)
-#define CACHE_ASSOC(y)  (((y) >> 3) & 7)
-#define CACHE_M(y)      ((y) & (1 << 2))
-#define CACHE_LINE(y)   ((y) & 3)
-
-static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
-{
-        unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
-
-        printk("CPU%u: %s: %d bytes, associativity %d, %d byte lines, %d sets\n",
-                cpu, prefix,
-                mult << (8 + CACHE_SIZE(cache)),
-                (mult << CACHE_ASSOC(cache)) >> 1,
-                8 << CACHE_LINE(cache),
-                1 << (6 + CACHE_SIZE(cache) - CACHE_ASSOC(cache) -
-                        CACHE_LINE(cache)));
-}
-
-static void __init dump_cpu_info(int cpu)
-{
-        unsigned int info = read_cpuid(CPUID_CACHETYPE);
-
-        if (info != processor_id) {
-                printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
-                       cache_types[CACHE_TYPE(info)]);
-                if (CACHE_S(info)) {
-                        dump_cache("I cache", cpu, CACHE_ISIZE(info));
-                        dump_cache("D cache", cpu, CACHE_DSIZE(info));
-                } else {
-                        dump_cache("cache", cpu, CACHE_ISIZE(info));
-                }
-        }
-
-        if (arch_is_coherent())
-                printk("Cache coherency enabled\n");
-}
-
 int cpu_architecture(void)
 {
         int cpu_arch;
 
-        if ((processor_id & 0x0008f000) == 0) {
+        if ((read_cpuid_id() & 0x0008f000) == 0) {
                 cpu_arch = CPU_ARCH_UNKNOWN;
-        } else if ((processor_id & 0x0008f000) == 0x00007000) {
-                cpu_arch = (processor_id & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
-        } else if ((processor_id & 0x00080000) == 0x00000000) {
-                cpu_arch = (processor_id >> 16) & 7;
+        } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
+                cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
+        } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
+                cpu_arch = (read_cpuid_id() >> 16) & 7;
                 if (cpu_arch)
                         cpu_arch += CPU_ARCH_ARMv3;
-        } else if ((processor_id & 0x000f0000) == 0x000f0000) {
+        } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
                 unsigned int mmfr0;
 
                 /* Revised CPUID format. Read the Memory Model Feature
@@ -330,6 +229,34 @@ int cpu_architecture(void)
         return cpu_arch;
 }
 
+static void __init cacheid_init(void)
+{
+        unsigned int cachetype = read_cpuid_cachetype();
+        unsigned int arch = cpu_architecture();
+
+        if (arch >= CPU_ARCH_ARMv7) {
+                cacheid = CACHEID_VIPT_NONALIASING;
+                if ((cachetype & (3 << 14)) == 1 << 14)
+                        cacheid |= CACHEID_ASID_TAGGED;
+        } else if (arch >= CPU_ARCH_ARMv6) {
+                if (cachetype & (1 << 23))
+                        cacheid = CACHEID_VIPT_ALIASING;
+                else
+                        cacheid = CACHEID_VIPT_NONALIASING;
+        } else {
+                cacheid = CACHEID_VIVT;
+        }
+
+        printk("CPU: %s data cache, %s instruction cache\n",
+                cache_is_vivt() ? "VIVT" :
+                cache_is_vipt_aliasing() ? "VIPT aliasing" :
+                cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown",
+                cache_is_vivt() ? "VIVT" :
+                icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
+                cache_is_vipt_aliasing() ? "VIPT aliasing" :
+                cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
+}
+
 /*
  * These functions re-use the assembly code in head.S, which
  * already provide the required functionality.
@@ -346,10 +273,10 @@ static void __init setup_processor(void)
          * types.  The linker builds this table for us from the
          * entries in arch/arm/mm/proc-*.S
          */
-        list = lookup_processor_type(processor_id);
+        list = lookup_processor_type(read_cpuid_id());
         if (!list) {
                 printk("CPU configuration botched (ID %08x), unable "
-                       "to continue.\n", processor_id);
+                       "to continue.\n", read_cpuid_id());
                 while (1);
         }
 
@@ -369,7 +296,7 @@ static void __init setup_processor(void)
 #endif
 
         printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
-               cpu_name, processor_id, (int)processor_id & 15,
+               cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
                proc_arch[cpu_architecture()], cr_alignment);
 
         sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
@@ -379,14 +306,14 @@ static void __init setup_processor(void)
         elf_hwcap &= ~HWCAP_THUMB;
 #endif
 
+        cacheid_init();
         cpu_proc_init();
 }
 
 /*
  * cpu_init - initialise one CPU.
  *
- * cpu_init dumps the cache information, initialises SMP specific
- * information, and sets up the per-CPU stacks.
+ * cpu_init sets up the per-CPU stacks.
  */
 void cpu_init(void)
 {
@@ -398,9 +325,6 @@ void cpu_init(void)
                 BUG();
         }
 
-        if (system_state == SYSTEM_BOOTING)
-                dump_cpu_info(cpu);
-
         /*
          * setup stacks for re-entrant exception handlers
          */
@@ -443,20 +367,6 @@ static struct machine_desc * __init setup_machine(unsigned int nr)
         return list;
 }
 
-static void __init early_initrd(char **p)
-{
-        unsigned long start, size;
-
-        start = memparse(*p, p);
-        if (**p == ',') {
-                size = memparse((*p) + 1, p);
-
-                phys_initrd_start = start;
-                phys_initrd_size = size;
-        }
-}
-__early_param("initrd=", early_initrd);
-
 static void __init arm_add_memory(unsigned long start, unsigned long size)
 {
         struct membank *bank;
@@ -503,17 +413,6 @@ static void __init early_mem(char **p)
 __early_param("mem=", early_mem);
 
 /*
- * vmalloc=size forces the vmalloc area to be exactly 'size'
- * bytes. This can be used to increase (or decrease) the vmalloc
- * area - the default is 128m.
- */
-static void __init early_vmalloc(char **arg)
-{
-        vmalloc_reserve = memparse(*arg, arg);
-}
-__early_param("vmalloc=", early_vmalloc);
-
-/*
  * Initial parsing of the command line.
  */
 static void __init parse_cmdline(char **cmdline_p, char *from)
@@ -527,12 +426,12 @@ static void __init parse_cmdline(char **cmdline_p, char *from)
                         struct early_params *p;
 
                         for (p = &__early_begin; p < &__early_end; p++) {
-                                int len = strlen(p->arg);
+                                int arglen = strlen(p->arg);
 
-                                if (memcmp(from, p->arg, len) == 0) {
+                                if (memcmp(from, p->arg, arglen) == 0) {
                                         if (to != command_line)
                                                 to -= 1;
-                                        from += len;
+                                        from += arglen;
                                         p->fn(&from);
 
                                         while (*from != ' ' && *from != '\0')
@@ -579,18 +478,13 @@ request_standard_resources(struct meminfo *mi, struct machine_desc *mdesc)
         kernel_data.end     = virt_to_phys(&_end - 1);
 
         for (i = 0; i < mi->nr_banks; i++) {
-                unsigned long virt_start, virt_end;
-
                 if (mi->bank[i].size == 0)
                         continue;
 
-                virt_start = __phys_to_virt(mi->bank[i].start);
-                virt_end   = virt_start + mi->bank[i].size - 1;
-
                 res = alloc_bootmem_low(sizeof(*res));
                 res->name  = "System RAM";
-                res->start = __virt_to_phys(virt_start);
-                res->end   = __virt_to_phys(virt_end);
+                res->start = mi->bank[i].start;
+                res->end   = mi->bank[i].start + mi->bank[i].size - 1;
                 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 
                 request_resource(&iomem_resource, res);
@@ -694,26 +588,6 @@ static int __init parse_tag_ramdisk(const struct tag *tag)
 
 __tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
 
-static int __init parse_tag_initrd(const struct tag *tag)
-{
-        printk(KERN_WARNING "ATAG_INITRD is deprecated; "
-                "please update your bootloader.\n");
-        phys_initrd_start = __virt_to_phys(tag->u.initrd.start);
-        phys_initrd_size = tag->u.initrd.size;
-        return 0;
-}
-
-__tagtable(ATAG_INITRD, parse_tag_initrd);
-
-static int __init parse_tag_initrd2(const struct tag *tag)
-{
-        phys_initrd_start = tag->u.initrd.start;
-        phys_initrd_size = tag->u.initrd.size;
-        return 0;
-}
-
-__tagtable(ATAG_INITRD2, parse_tag_initrd2);
-
 static int __init parse_tag_serialnr(const struct tag *tag)
 {
         system_serial_low = tag->u.serialnr.low;
@@ -901,28 +775,12 @@ static const char *hwcap_str[] = {
         NULL
 };
 
-static void
-c_show_cache(struct seq_file *m, const char *type, unsigned int cache)
-{
-        unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
-
-        seq_printf(m, "%s size\t\t: %d\n"
-                      "%s assoc\t\t: %d\n"
-                      "%s line length\t: %d\n"
-                      "%s sets\t\t: %d\n",
-                type, mult << (8 + CACHE_SIZE(cache)),
-                type, (mult << CACHE_ASSOC(cache)) >> 1,
-                type, 8 << CACHE_LINE(cache),
-                type, 1 << (6 + CACHE_SIZE(cache) - CACHE_ASSOC(cache) -
-                            CACHE_LINE(cache)));
-}
-
 static int c_show(struct seq_file *m, void *v)
 {
         int i;
 
         seq_printf(m, "Processor\t: %s rev %d (%s)\n",
-                   cpu_name, (int)processor_id & 15, elf_platform);
+                   cpu_name, read_cpuid_id() & 15, elf_platform);
 
 #if defined(CONFIG_SMP)
         for_each_online_cpu(i) {
@@ -949,47 +807,26 @@ static int c_show(struct seq_file *m, void *v)
                 if (elf_hwcap & (1 << i))
                         seq_printf(m, "%s ", hwcap_str[i]);
 
-        seq_printf(m, "\nCPU implementer\t: 0x%02x\n", processor_id >> 24);
+        seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
         seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
 
-        if ((processor_id & 0x0008f000) == 0x00000000) {
+        if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
                 /* pre-ARM7 */
-                seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4);
+                seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
         } else {
-                if ((processor_id & 0x0008f000) == 0x00007000) {
+                if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
                         /* ARM7 */
                         seq_printf(m, "CPU variant\t: 0x%02x\n",
-                                   (processor_id >> 16) & 127);
+                                   (read_cpuid_id() >> 16) & 127);
                 } else {
                         /* post-ARM7 */
                         seq_printf(m, "CPU variant\t: 0x%x\n",
-                                   (processor_id >> 20) & 15);
+                                   (read_cpuid_id() >> 20) & 15);
                 }
                 seq_printf(m, "CPU part\t: 0x%03x\n",
-                           (processor_id >> 4) & 0xfff);
-        }
-        seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);
-
-        {
-                unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
-                if (cache_info != processor_id) {
-                        seq_printf(m, "Cache type\t: %s\n"
-                                      "Cache clean\t: %s\n"
-                                      "Cache lockdown\t: %s\n"
-                                      "Cache format\t: %s\n",
-                                   cache_types[CACHE_TYPE(cache_info)],
-                                   cache_clean[CACHE_TYPE(cache_info)],
-                                   cache_lockdown[CACHE_TYPE(cache_info)],
-                                   CACHE_S(cache_info) ? "Harvard" : "Unified");
-
-                        if (CACHE_S(cache_info)) {
-                                c_show_cache(m, "I", CACHE_ISIZE(cache_info));
-                                c_show_cache(m, "D", CACHE_DSIZE(cache_info));
-                        } else {
-                                c_show_cache(m, "Cache", CACHE_ISIZE(cache_info));
-                        }
-                }
+                           (read_cpuid_id() >> 4) & 0xfff);
         }
+        seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
 
         seq_puts(m, "\n");
 
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index ef2f86a5e78a..80b8b5c7e07a 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -11,11 +11,11 @@
 #include <linux/signal.h>
 #include <linux/personality.h>
 #include <linux/freezer.h>
+#include <linux/uaccess.h>
 
 #include <asm/elf.h>
 #include <asm/cacheflush.h>
 #include <asm/ucontext.h>
-#include <asm/uaccess.h>
 #include <asm/unistd.h>
 
 #include "ptrace.h"
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index e9842f6767f9..e42a749a56dd 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -277,6 +277,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         /*
          * Enable local interrupts.
          */
+        notify_cpu_starting(cpu);
         local_irq_enable();
         local_fiq_enable();
 
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 0128687ba0f7..b3ec641b5cf8 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -27,8 +27,7 @@
 #include <linux/file.h>
 #include <linux/utsname.h>
 #include <linux/ipc.h>
-
-#include <asm/uaccess.h>
+#include <linux/uaccess.h>
 
 extern unsigned long do_mremap(unsigned long addr, unsigned long old_len,
                                unsigned long new_len, unsigned long flags,
diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c
index 96ab5f52949c..42623db7f870 100644
--- a/arch/arm/kernel/sys_oabi-compat.c
+++ b/arch/arm/kernel/sys_oabi-compat.c
@@ -82,7 +82,7 @@
 #include <linux/socket.h>
 #include <linux/net.h>
 #include <linux/ipc.h>
-#include <asm/uaccess.h>
+#include <linux/uaccess.h>
 
 struct oldabi_stat64 {
         unsigned long long st_dev;
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 368d171754cf..c68b44aa88d2 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -59,7 +59,7 @@ unsigned long profile_pc(struct pt_regs *regs)
 
         if (in_lock_functions(pc)) {
                 fp = regs->ARM_fp;
-                pc = pc_pointer(((unsigned long *)fp)[-1]);
+                pc = ((unsigned long *)fp)[-1];
         }
 
         return pc;
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 872f1f8fbb57..57e6874d0b80 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -19,15 +19,13 @@
 #include <linux/kallsyms.h>
 #include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/kprobes.h>
+#include <linux/uaccess.h>
 
 #include <asm/atomic.h>
 #include <asm/cacheflush.h>
 #include <asm/system.h>
-#include <asm/uaccess.h>
 #include <asm/unistd.h>
 #include <asm/traps.h>
-#include <asm/io.h>
 
 #include "ptrace.h"
 #include "signal.h"
@@ -69,7 +67,8 @@ void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long
  */
 static int verify_stack(unsigned long sp)
 {
-        if (sp < PAGE_OFFSET || (sp > (unsigned long)high_memory && high_memory != 0))
+        if (sp < PAGE_OFFSET ||
+            (sp > (unsigned long)high_memory && high_memory != NULL))
                 return -EFAULT;
 
         return 0;
@@ -328,17 +327,6 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
                 get_user(instr, (u32 __user *)pc);
         }
 
-#ifdef CONFIG_KPROBES
-        /*
-         * It is possible to have recursive kprobes, so we can't call
-         * the kprobe trap handler with the undef_lock held.
-         */
-        if (instr == KPROBE_BREAKPOINT_INSTRUCTION && !user_mode(regs)) {
-                kprobe_trap_handler(regs, instr);
-                return;
-        }
-#endif
-
         if (call_undef_hook(regs, instr) == 0)
                 return;
 
diff --git a/arch/arm/kernel/xscale-cp0.c b/arch/arm/kernel/xscale-cp0.c
index 180000bfdc8f..17127db906fa 100644
--- a/arch/arm/kernel/xscale-cp0.c
+++ b/arch/arm/kernel/xscale-cp0.c
@@ -14,8 +14,8 @@
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <asm/thread_notify.h>
-#include <asm/io.h>
 
 static inline void dsp_save_state(u32 *state)
 {
diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index 55e57a1c2e6d..1154d924080b 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -47,3 +47,5 @@ ENTRY(__aeabi_llsl)
         mov     al, al, lsl r2
         mov     pc, lr
 
+ENDPROC(__ashldi3)
+ENDPROC(__aeabi_llsl)
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index 0b31398f89b2..9f8b35572f8c 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -47,3 +47,5 @@ ENTRY(__aeabi_lasr)
         mov     ah, ah, asr r2
         mov     pc, lr
 
+ENDPROC(__ashrdi3)
+ENDPROC(__aeabi_lasr)
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index 84dc890d2bf3..b0951d0e8b2c 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -30,6 +30,8 @@ ENTRY(c_backtrace)
 
 #if !defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_PRINTK)
                 mov     pc, lr
+ENDPROC(__backtrace)
+ENDPROC(c_backtrace)
 #else
                 stmfd   sp!, {r4 - r8, lr}      @ Save an extra register so we have a location...
                 movs    frame, r0               @ if frame pointer is zero
@@ -103,6 +105,8 @@ for_each_frame:	tst	frame, mask		@ Check for address exceptions
                 mov     r1, frame
                 bl      printk
 no_frame:       ldmfd   sp!, {r4 - r8, pc}
+ENDPROC(__backtrace)
+ENDPROC(c_backtrace)
                 
                 .section __ex_table,"a"
                 .align  3
diff --git a/arch/arm/lib/changebit.S b/arch/arm/lib/changebit.S
index 389567c24090..80f3115cbee2 100644
--- a/arch/arm/lib/changebit.S
+++ b/arch/arm/lib/changebit.S
@@ -19,3 +19,5 @@ ENTRY(_change_bit_be)
                 eor     r0, r0, #0x18           @ big endian byte ordering
 ENTRY(_change_bit_le)
         bitop   eor
+ENDPROC(_change_bit_be)
+ENDPROC(_change_bit_le)
diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
index ecb28dcdaf7b..4d6bc71231f3 100644
--- a/arch/arm/lib/clear_user.S
+++ b/arch/arm/lib/clear_user.S
@@ -41,9 +41,10 @@ USER(		strplt	r2, [r0], #4)
 USER(           strnebt r2, [r0], #1)
 USER(           strnebt r2, [r0], #1)
                 tst     r1, #1                  @ x1 x0 x1 x0 x1 x0 x1
-USER(           strnebt r2, [r0], #1)
+USER(           strnebt r2, [r0])
                 mov     r0, #0
                 ldmfd   sp!, {r1, pc}
+ENDPROC(__clear_user)
 
                 .section .fixup,"ax"
                 .align  0
diff --git a/arch/arm/lib/clearbit.S b/arch/arm/lib/clearbit.S
index 347516533025..1a63e43a1df0 100644
--- a/arch/arm/lib/clearbit.S
+++ b/arch/arm/lib/clearbit.S
@@ -20,3 +20,5 @@ ENTRY(_clear_bit_be)
                 eor     r0, r0, #0x18           @ big endian byte ordering
 ENTRY(_clear_bit_le)
         bitop   bic
+ENDPROC(_clear_bit_be)
+ENDPROC(_clear_bit_le)
diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index 6b7363ce749c..56799a165cc4 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -87,6 +87,8 @@ ENTRY(__copy_from_user)
 
 #include "copy_template.S"
 
+ENDPROC(__copy_from_user)
+
         .section .fixup,"ax"
         .align 0
         copy_abort_preamble
diff --git a/arch/arm/lib/copy_page.S b/arch/arm/lib/copy_page.S
index 666c99cc0744..6ae04db1ca4f 100644
--- a/arch/arm/lib/copy_page.S
+++ b/arch/arm/lib/copy_page.S
@@ -44,3 +44,4 @@ ENTRY(copy_page)
         PLD(    ldmeqia r1!, {r3, r4, ip, lr}   )
         PLD(    beq     2b                      )
                 ldmfd   sp!, {r4, pc}                   @       3
+ENDPROC(copy_page)
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index 5224d94688d9..22f968bbdffd 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -90,6 +90,8 @@ ENTRY(__copy_to_user)
 
 #include "copy_template.S"
 
+ENDPROC(__copy_to_user)
+
         .section .fixup,"ax"
         .align 0
         copy_abort_preamble
diff --git a/arch/arm/lib/csumipv6.S b/arch/arm/lib/csumipv6.S
index 9621469beec1..3ac6ef01bc43 100644
--- a/arch/arm/lib/csumipv6.S
+++ b/arch/arm/lib/csumipv6.S
@@ -29,4 +29,5 @@ ENTRY(__csum_ipv6_magic)
                 adcs    r0, r0, r2
                 adcs    r0, r0, #0
                 ldmfd   sp!, {pc}
+ENDPROC(__csum_ipv6_magic)
 
diff --git a/arch/arm/lib/csumpartial.S b/arch/arm/lib/csumpartial.S
index a78dae5a7b28..31d3cb34740d 100644
--- a/arch/arm/lib/csumpartial.S
+++ b/arch/arm/lib/csumpartial.S
@@ -139,3 +139,4 @@ ENTRY(csum_partial)
                 tst     len, #0x1c
                 bne     4b
                 b       .Lless4
+ENDPROC(csum_partial)
diff --git a/arch/arm/lib/csumpartialcopy.S b/arch/arm/lib/csumpartialcopy.S
index 21effe0dbf97..d03fc71fc88c 100644
--- a/arch/arm/lib/csumpartialcopy.S
+++ b/arch/arm/lib/csumpartialcopy.S
@@ -18,13 +18,11 @@
  */
 
                 .macro  save_regs
-                mov     ip, sp
-                stmfd   sp!, {r1, r4 - r8, fp, ip, lr, pc}
-                sub     fp, ip, #4
+                stmfd   sp!, {r1, r4 - r8, lr}
                 .endm
 
                 .macro  load_regs
-                ldmfd   sp, {r1, r4 - r8, fp, sp, pc}
+                ldmfd   sp!, {r1, r4 - r8, pc}
                 .endm
 
                 .macro  load1b, reg1
@@ -50,5 +48,6 @@
                 .endm
 
 #define FN_ENTRY        ENTRY(csum_partial_copy_nocheck)
+#define FN_EXIT         ENDPROC(csum_partial_copy_nocheck)
 
 #include "csumpartialcopygeneric.S"
diff --git a/arch/arm/lib/csumpartialcopygeneric.S b/arch/arm/lib/csumpartialcopygeneric.S
index c50e8f5285d1..d620a5f22a09 100644
--- a/arch/arm/lib/csumpartialcopygeneric.S
+++ b/arch/arm/lib/csumpartialcopygeneric.S
@@ -329,3 +329,4 @@ FN_ENTRY
                 adcs    sum, sum, r4, push #24
                 mov     r5, r4, get_byte_1
                 b       .Lexit
+FN_EXIT
diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S
index c3b93e22ea25..14677fb4b0c4 100644
--- a/arch/arm/lib/csumpartialcopyuser.S
+++ b/arch/arm/lib/csumpartialcopyuser.S
@@ -18,13 +18,11 @@
                 .text
 
                 .macro  save_regs
-                mov     ip, sp
-                stmfd   sp!, {r1 - r2, r4 - r8, fp, ip, lr, pc}
-                sub     fp, ip, #4
+                stmfd   sp!, {r1, r2, r4 - r8, lr}
                 .endm
 
                 .macro  load_regs
-                ldmfd   sp, {r1, r2, r4-r8, fp, sp, pc}
+                ldmfd   sp!, {r1, r2, r4 - r8, pc}
                 .endm
 
                 .macro  load1b, reg1
@@ -82,6 +80,7 @@
  */
 
 #define FN_ENTRY        ENTRY(csum_partial_copy_from_user)
+#define FN_EXIT         ENDPROC(csum_partial_copy_from_user)
 
 #include "csumpartialcopygeneric.S"
 
diff --git a/arch/arm/lib/delay.S b/arch/arm/lib/delay.S
index 930a70259220..8d6a8762ab88 100644
--- a/arch/arm/lib/delay.S
+++ b/arch/arm/lib/delay.S
@@ -60,3 +60,6 @@ ENTRY(__delay)
 #endif
                 bhi     __delay
                 mov     pc, lr
+ENDPROC(__udelay)
+ENDPROC(__const_udelay)
+ENDPROC(__delay)
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index 58eef6607629..1425e789ba86 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -198,3 +198,4 @@ ENTRY(__do_div64)
         mov     xh, #0
         ldr     pc, [sp], #8
 
+ENDPROC(__do_div64)
diff --git a/arch/arm/lib/findbit.S b/arch/arm/lib/findbit.S
index a5ca0248aa4e..8c4defc4f3c4 100644
--- a/arch/arm/lib/findbit.S
+++ b/arch/arm/lib/findbit.S
@@ -33,6 +33,7 @@ ENTRY(_find_first_zero_bit_le)
                 blo     1b
 3:              mov     r0, r1                  @ no free bits
                 mov     pc, lr
+ENDPROC(_find_first_zero_bit_le)
 
 /*
  * Purpose  : Find next 'zero' bit
@@ -50,6 +51,7 @@ ENTRY(_find_next_zero_bit_le)
                 orr     r2, r2, #7              @ if zero, then no bits here
                 add     r2, r2, #1              @ align bit pointer
                 b       2b                      @ loop for next bit
+ENDPROC(_find_next_zero_bit_le)
 
 /*
  * Purpose  : Find a 'one' bit
@@ -67,6 +69,7 @@ ENTRY(_find_first_bit_le)
                 blo     1b
 3:              mov     r0, r1                  @ no free bits
                 mov     pc, lr
+ENDPROC(_find_first_bit_le)
 
 /*
  * Purpose  : Find next 'one' bit
@@ -83,6 +86,7 @@ ENTRY(_find_next_bit_le)
                 orr     r2, r2, #7              @ if zero, then no bits here
                 add     r2, r2, #1              @ align bit pointer
                 b       2b                      @ loop for next bit
+ENDPROC(_find_next_bit_le)
 
 #ifdef __ARMEB__
 
@@ -99,6 +103,7 @@ ENTRY(_find_first_zero_bit_be)
                 blo     1b
 3:              mov     r0, r1                  @ no free bits
                 mov     pc, lr
+ENDPROC(_find_first_zero_bit_be)
 
 ENTRY(_find_next_zero_bit_be)
                 teq     r1, #0
@@ -113,6 +118,7 @@ ENTRY(_find_next_zero_bit_be)
                 orr     r2, r2, #7              @ if zero, then no bits here
                 add     r2, r2, #1              @ align bit pointer
                 b       2b                      @ loop for next bit
+ENDPROC(_find_next_zero_bit_be)
 
 ENTRY(_find_first_bit_be)
                 teq     r1, #0
@@ -127,6 +133,7 @@ ENTRY(_find_first_bit_be)
                 blo     1b
 3:              mov     r0, r1                  @ no free bits
                 mov     pc, lr
+ENDPROC(_find_first_bit_be)
 
 ENTRY(_find_next_bit_be)
                 teq     r1, #0
@@ -140,6 +147,7 @@ ENTRY(_find_next_bit_be)
                 orr     r2, r2, #7              @ if zero, then no bits here
                 add     r2, r2, #1              @ align bit pointer
                 b       2b                      @ loop for next bit
+ENDPROC(_find_next_bit_be)
 
 #endif
 
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 2034d4dbe6ad..6763088b7607 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -26,16 +26,16 @@
  * Note that ADDR_LIMIT is either 0 or 0xc0000000.
  * Note also that it is intended that __get_user_bad is not global.
  */
+#include <linux/linkage.h>
 #include <asm/errno.h>
 
-        .global __get_user_1
-__get_user_1:
+ENTRY(__get_user_1)
 1:      ldrbt   r2, [r0]
         mov     r0, #0
         mov     pc, lr
+ENDPROC(__get_user_1)
 
-        .global __get_user_2
-__get_user_2:
+ENTRY(__get_user_2)
 2:      ldrbt   r2, [r0], #1
 3:      ldrbt   r3, [r0]
 #ifndef __ARMEB__
@@ -45,17 +45,19 @@ __get_user_2:
 #endif
         mov     r0, #0
         mov     pc, lr
+ENDPROC(__get_user_2)
 
-        .global __get_user_4
-__get_user_4:
+ENTRY(__get_user_4)
 4:      ldrt    r2, [r0]
         mov     r0, #0
         mov     pc, lr
+ENDPROC(__get_user_4)
 
 __get_user_bad:
         mov     r2, #0
         mov     r0, #-EFAULT
         mov     pc, lr
+ENDPROC(__get_user_bad)
 
 .section __ex_table, "a"
         .long   1b, __get_user_bad
diff --git a/arch/arm/lib/io-readsb.S b/arch/arm/lib/io-readsb.S
index fb966ad0276f..9f4238987fe9 100644
--- a/arch/arm/lib/io-readsb.S
+++ b/arch/arm/lib/io-readsb.S
@@ -120,3 +120,4 @@ ENTRY(__raw_readsb)
                 strgtb  r3, [r1]
 
                 ldmfd   sp!, {r4 - r6, pc}
+ENDPROC(__raw_readsb)
diff --git a/arch/arm/lib/io-readsl.S b/arch/arm/lib/io-readsl.S
index 75a9121cb23f..5fb97e7f9f4b 100644
--- a/arch/arm/lib/io-readsl.S
+++ b/arch/arm/lib/io-readsl.S
@@ -76,3 +76,4 @@ ENTRY(__raw_readsl)
 8:              mov     r3, ip, get_byte_0
                 strb    r3, [r1, #0]
                 mov     pc, lr
+ENDPROC(__raw_readsl)
diff --git a/arch/arm/lib/io-readsw-armv4.S b/arch/arm/lib/io-readsw-armv4.S
index 4db1c5f0b219..1f393d42593d 100644
--- a/arch/arm/lib/io-readsw-armv4.S
+++ b/arch/arm/lib/io-readsw-armv4.S
@@ -128,3 +128,4 @@ ENTRY(__raw_readsw)
    _BE_ONLY_(   movne   ip, ip, lsr #24         )
                 strneb  ip, [r1]
                 ldmfd   sp!, {r4, pc}
+ENDPROC(__raw_readsw)
diff --git a/arch/arm/lib/io-writesb.S b/arch/arm/lib/io-writesb.S
index 7eba2b6cc69f..68b92f4acaeb 100644
--- a/arch/arm/lib/io-writesb.S
+++ b/arch/arm/lib/io-writesb.S
@@ -91,3 +91,4 @@ ENTRY(__raw_writesb)
                 strgtb  r3, [r0]
 
                 ldmfd   sp!, {r4, r5, pc}
+ENDPROC(__raw_writesb)
diff --git a/arch/arm/lib/io-writesl.S b/arch/arm/lib/io-writesl.S
index f8f14dd227ca..8d3b7813725c 100644
--- a/arch/arm/lib/io-writesl.S
+++ b/arch/arm/lib/io-writesl.S
@@ -64,3 +64,4 @@ ENTRY(__raw_writesl)
                 str     ip, [r0]
                 bne     6b
                 mov     pc, lr
+ENDPROC(__raw_writesl)
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index c8e85bd653b7..d6585612c86b 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -94,3 +94,4 @@ ENTRY(__raw_writesw)
 3:              movne   ip, r3, lsr #8
                 strneh  ip, [r0]
                 mov     pc, lr
+ENDPROC(__raw_writesw)
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 4e492f4b3f0e..67964bcfc854 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -230,6 +230,8 @@ ENTRY(__aeabi_uidiv)
         mov     r0, r0, lsr r2
         mov     pc, lr
 
+ENDPROC(__udivsi3)
+ENDPROC(__aeabi_uidiv)
 
 ENTRY(__umodsi3)
 
@@ -245,6 +247,7 @@ ENTRY(__umodsi3)
 
         mov     pc, lr
 
+ENDPROC(__umodsi3)
 
 ENTRY(__divsi3)
 ENTRY(__aeabi_idiv)
@@ -284,6 +287,8 @@ ENTRY(__aeabi_idiv)
         rsbmi   r0, r0, #0
         mov     pc, lr
 
+ENDPROC(__divsi3)
+ENDPROC(__aeabi_idiv)
 
 ENTRY(__modsi3)
 
@@ -305,6 +310,8 @@ ENTRY(__modsi3)
         rsbmi   r0, r0, #0
         mov     pc, lr
 
+ENDPROC(__modsi3)
+
 #ifdef CONFIG_AEABI
 
 ENTRY(__aeabi_uidivmod)
@@ -316,6 +323,8 @@ ENTRY(__aeabi_uidivmod)
         sub     r1, r1, r3
         mov     pc, lr
 
+ENDPROC(__aeabi_uidivmod)
+
 ENTRY(__aeabi_idivmod)
 
         stmfd   sp!, {r0, r1, ip, lr}
@@ -325,6 +334,8 @@ ENTRY(__aeabi_idivmod)
         sub     r1, r1, r3
         mov     pc, lr
 
+ENDPROC(__aeabi_idivmod)
+
 #endif
 
 Ldiv0:
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
index a86dbdd59cc4..99ea338bf87c 100644
--- a/arch/arm/lib/lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -47,3 +47,5 @@ ENTRY(__aeabi_llsr)
         mov     ah, ah, lsr r2
         mov     pc, lr
 
+ENDPROC(__lshrdi3)
+ENDPROC(__aeabi_llsr)
diff --git a/arch/arm/lib/memchr.S b/arch/arm/lib/memchr.S
index e7ab1ea8ebaa..1da86991d700 100644
--- a/arch/arm/lib/memchr.S
+++ b/arch/arm/lib/memchr.S
@@ -23,3 +23,4 @@ ENTRY(memchr)
         sub     r0, r0, #1
 2:      movne   r0, #0
         mov     pc, lr
+ENDPROC(memchr)
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index 7e71d6708a8d..e0d002641d3f 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -57,3 +57,4 @@ ENTRY(memcpy)
 
 #include "copy_template.S"
 
+ENDPROC(memcpy)
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index 2e301b7bd8f1..12549187088c 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -196,3 +196,4 @@ ENTRY(memmove)
 
 18:             backward_copy_shift     push=24 pull=8
 
+ENDPROC(memmove)
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index b477d4ac88ef..761eefa76243 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -124,3 +124,4 @@ ENTRY(memset)
         tst     r2, #1
         strneb  r1, [r0], #1
         mov     pc, lr
+ENDPROC(memset)
diff --git a/arch/arm/lib/memzero.S b/arch/arm/lib/memzero.S
index b8f79d80ee9b..3fbdef5f802a 100644
--- a/arch/arm/lib/memzero.S
+++ b/arch/arm/lib/memzero.S
@@ -122,3 +122,4 @@ ENTRY(__memzero)
         tst     r1, #1                  @ 1 a byte left over
         strneb  r2, [r0], #1            @ 1
         mov     pc, lr                  @ 1
+ENDPROC(__memzero)
diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S
index d89c60615794..36c91b4957e2 100644
--- a/arch/arm/lib/muldi3.S
+++ b/arch/arm/lib/muldi3.S
@@ -43,3 +43,5 @@ ENTRY(__aeabi_lmul)
         adc     xh, xh, ip, lsr #16
         mov     pc, lr
 
+ENDPROC(__muldi3)
+ENDPROC(__aeabi_lmul)
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 08ec7dffa52e..864f3c1c4f18 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -26,16 +26,16 @@
  * Note that ADDR_LIMIT is either 0 or 0xc0000000
  * Note also that it is intended that __put_user_bad is not global.
  */
+#include <linux/linkage.h>
 #include <asm/errno.h>
 
-        .global __put_user_1
-__put_user_1:
+ENTRY(__put_user_1)
 1:      strbt   r2, [r0]
         mov     r0, #0
         mov     pc, lr
+ENDPROC(__put_user_1)
 
-        .global __put_user_2
-__put_user_2:
+ENTRY(__put_user_2)
         mov     ip, r2, lsr #8
 #ifndef __ARMEB__
 2:      strbt   r2, [r0], #1
@@ -46,23 +46,25 @@ __put_user_2:
 #endif
         mov     r0, #0
         mov     pc, lr
+ENDPROC(__put_user_2)
 
-        .global __put_user_4
-__put_user_4:
+ENTRY(__put_user_4)
 4:      strt    r2, [r0]
         mov     r0, #0
         mov     pc, lr
+ENDPROC(__put_user_4)
 
-        .global __put_user_8
-__put_user_8:
+ENTRY(__put_user_8)
 5:      strt    r2, [r0], #4
 6:      strt    r3, [r0]
         mov     r0, #0
         mov     pc, lr
+ENDPROC(__put_user_8)
 
 __put_user_bad:
         mov     r0, #-EFAULT
         mov     pc, lr
+ENDPROC(__put_user_bad)
 
 .section __ex_table, "a"
         .long   1b, __put_user_bad
diff --git a/arch/arm/lib/setbit.S b/arch/arm/lib/setbit.S
index 83bc23d5b037..1dd7176c4b2b 100644
--- a/arch/arm/lib/setbit.S
+++ b/arch/arm/lib/setbit.S
@@ -20,3 +20,5 @@ ENTRY(_set_bit_be)
                 eor     r0, r0, #0x18           @ big endian byte ordering
 ENTRY(_set_bit_le)
         bitop   orr
+ENDPROC(_set_bit_be)
+ENDPROC(_set_bit_le)
diff --git a/arch/arm/lib/sha1.S b/arch/arm/lib/sha1.S
index 67c2bf4774b7..a16fb208c841 100644
--- a/arch/arm/lib/sha1.S
+++ b/arch/arm/lib/sha1.S
@@ -185,6 +185,8 @@ ENTRY(sha_transform)
 
         ldmfd   sp!, {r4 - r8, pc}
 
+ENDPROC(sha_transform)
+
 .L_sha_K:
         .word   0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6
 
@@ -204,3 +206,4 @@ ENTRY(sha_init)
         stmia   r0, {r1, r2, r3, ip, lr}
         ldr     pc, [sp], #4
 
+ENDPROC(sha_init)
diff --git a/arch/arm/lib/strchr.S b/arch/arm/lib/strchr.S
index 9f18d6fdee6a..d8f2a1c1aea4 100644
--- a/arch/arm/lib/strchr.S
+++ b/arch/arm/lib/strchr.S
@@ -24,3 +24,4 @@ ENTRY(strchr)
                 movne   r0, #0
                 subeq   r0, r0, #1
                 mov     pc, lr
+ENDPROC(strchr)
diff --git a/arch/arm/lib/strncpy_from_user.S b/arch/arm/lib/strncpy_from_user.S
index 36e3741a3772..330373c26dd9 100644
--- a/arch/arm/lib/strncpy_from_user.S
+++ b/arch/arm/lib/strncpy_from_user.S
@@ -31,6 +31,7 @@ USER(	ldrplbt	r3, [r1], #1)
         sub     r1, r1, #1      @ take NUL character out of count
 2:      sub     r0, r1, ip
         mov     pc, lr
+ENDPROC(__strncpy_from_user)
 
         .section .fixup,"ax"
         .align  0
diff --git a/arch/arm/lib/strnlen_user.S b/arch/arm/lib/strnlen_user.S
index 18d8fa4f925a..90bb9d020836 100644
--- a/arch/arm/lib/strnlen_user.S
+++ b/arch/arm/lib/strnlen_user.S
@@ -31,6 +31,7 @@ USER(	ldrbt	r3, [r0], #1)
         add     r0, r0, #1
 2:      sub     r0, r0, r2
         mov     pc, lr
+ENDPROC(__strnlen_user)
 
         .section .fixup,"ax"
         .align  0
diff --git a/arch/arm/lib/strrchr.S b/arch/arm/lib/strrchr.S
index 538df220aa48..302f20cd2423 100644
--- a/arch/arm/lib/strrchr.S
+++ b/arch/arm/lib/strrchr.S
@@ -23,3 +23,4 @@ ENTRY(strrchr)
                 bne     1b
                 mov     r0, r3
                 mov     pc, lr
+ENDPROC(strrchr)
diff --git a/arch/arm/lib/testchangebit.S b/arch/arm/lib/testchangebit.S
index b25dcd2be53e..5c98dc567f0f 100644
--- a/arch/arm/lib/testchangebit.S
+++ b/arch/arm/lib/testchangebit.S
@@ -16,3 +16,5 @@ ENTRY(_test_and_change_bit_be)
                 eor     r0, r0, #0x18           @ big endian byte ordering
 ENTRY(_test_and_change_bit_le)
         testop  eor, strb
+ENDPROC(_test_and_change_bit_be)
+ENDPROC(_test_and_change_bit_le)
diff --git a/arch/arm/lib/testclearbit.S b/arch/arm/lib/testclearbit.S
index 2dcc4b16b68e..543d7094d18e 100644
--- a/arch/arm/lib/testclearbit.S
+++ b/arch/arm/lib/testclearbit.S
@@ -16,3 +16,5 @@ ENTRY(_test_and_clear_bit_be)
                 eor     r0, r0, #0x18           @ big endian byte ordering
 ENTRY(_test_and_clear_bit_le)
         testop  bicne, strneb
+ENDPROC(_test_and_clear_bit_be)
+ENDPROC(_test_and_clear_bit_le)
diff --git a/arch/arm/lib/testsetbit.S b/arch/arm/lib/testsetbit.S
index 9011c969761a..0b3f390401ce 100644
--- a/arch/arm/lib/testsetbit.S
+++ b/arch/arm/lib/testsetbit.S
@@ -16,3 +16,5 @@ ENTRY(_test_and_set_bit_be)
                 eor     r0, r0, #0x18           @ big endian byte ordering
 ENTRY(_test_and_set_bit_le)
         testop  orreq, streqb
+ENDPROC(_test_and_set_bit_be)
+ENDPROC(_test_and_set_bit_le)
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index b48bd6d5fd83..ffdd27498cee 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -277,6 +277,7 @@ USER(		strgebt	r3, [r0], #1)			@ May fault
                 ldrgtb  r3, [r1], #0
 USER(           strgtbt r3, [r0], #1)                   @ May fault
                 b       .Lc2u_finished
+ENDPROC(__copy_to_user)
 
                 .section .fixup,"ax"
                 .align  0
@@ -542,6 +543,7 @@ USER(		ldrgebt	r3, [r1], #1)			@ May fault
 USER(           ldrgtbt r3, [r1], #1)                   @ May fault
                 strgtb  r3, [r0], #1
                 b       .Lcfu_finished
+ENDPROC(__copy_from_user)
 
                 .section .fixup,"ax"
                 .align  0
diff --git a/arch/arm/lib/ucmpdi2.S b/arch/arm/lib/ucmpdi2.S
index f76de07ac182..f0df6a91db04 100644
--- a/arch/arm/lib/ucmpdi2.S
+++ b/arch/arm/lib/ucmpdi2.S
@@ -33,6 +33,8 @@ ENTRY(__ucmpdi2)
         movhi   r0, #2
         mov     pc, lr
 
+ENDPROC(__ucmpdi2)
+
 #ifdef CONFIG_AEABI
 
 ENTRY(__aeabi_ulcmp)
@@ -44,5 +46,7 @@ ENTRY(__aeabi_ulcmp)
         movhi   r0, #1
         mov     pc, lr
 
+ENDPROC(__aeabi_ulcmp)
+
 #endif
 
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index a048b92cb407..5aafb2e2ca7a 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -175,6 +175,15 @@ config MACH_SAM9_L9260
           Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
           <http://www.olimex.com/dev/sam9-L9260.html>
 
+config MACH_AFEB9260
+        bool "Custom afeb9260 board v1"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using custom afeb9260 board based on
+          open hardware design. Select this for revision 1 of the board.
+          <svn://194.85.238.22/home/users/george/svn/arm9eb>
+          <http://groups.google.com/group/arm9fpga-evolution-board>
+
 config MACH_USB_A9260
         bool "CALAO USB-A9260"
         depends on ARCH_AT91SAM9260
@@ -314,6 +323,19 @@ config AT91_PROGRAMMABLE_CLOCKS
           Select this if you need to program one or more of the PCK0..PCK3
           programmable clock outputs.
 
+config AT91_SLOW_CLOCK
+        bool "Suspend-to-RAM disables main oscillator"
+        depends on SUSPEND
+        help
+          Select this if you want Suspend-to-RAM to save the most power
+          possible (without powering off the CPU) by disabling the PLLs
+          and main oscillator so that only the 32 KiHz clock is available.
+
+          When only that slow-clock is available, some peripherals lose
+          functionality.  Many can't issue wakeup events unless faster
+          clocks are available.  Some lose their operating state and
+          need to be completely re-initialized.
+
 config AT91_TIMER_HZ
        int "Kernel HZ (jiffies per second)"
        range 32 1024
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 7d641f97516b..cca612d97ca2 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_MACH_CAM60)	+= board-cam60.o
 obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
 obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a9260.o
 obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
+obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
 
 # AT91SAM9261 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
@@ -64,6 +65,7 @@ obj-y				+= leds.o
 
 # Power Management
 obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_AT91_SLOW_CLOCK)   += pm_slowclock.o
 
 ifeq ($(CONFIG_PM_DEBUG),y)
 CFLAGS_pm.o += -DDEBUG
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index 638948c16770..0fc0adaebd58 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -141,8 +141,8 @@ static struct clk tcb_clk = {
         .pmc_mask       = 1 << AT91CAP9_ID_TCB,
         .type           = CLK_TYPE_PERIPHERAL,
 };
-static struct clk pwmc_clk = {
-        .name           = "pwmc_clk",
+static struct clk pwm_clk = {
+        .name           = "pwm_clk",
         .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
         .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -207,7 +207,7 @@ static struct clk *periph_clocks[] __initdata = {
         &ssc1_clk,
         &ac97_clk,
         &tcb_clk,
-        &pwmc_clk,
+        &pwm_clk,
         &macb_clk,
         &aestdes_clk,
         &adc_clk,
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index abb4aac8fa98..5ebd4273d353 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -719,6 +719,60 @@ static void __init at91_add_device_watchdog(void) {}
 
 
 /* --------------------------------------------------------------------
+ *  PWM
+ * --------------------------------------------------------------------*/
+
+#if defined(CONFIG_ATMEL_PWM)
+static u32 pwm_mask;
+
+static struct resource pwm_resources[] = {
+        [0] = {
+                .start  = AT91CAP9_BASE_PWMC,
+                .end    = AT91CAP9_BASE_PWMC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91CAP9_ID_PWMC,
+                .end    = AT91CAP9_ID_PWMC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91cap9_pwm0_device = {
+        .name   = "atmel_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data          = &pwm_mask,
+        },
+        .resource       = pwm_resources,
+        .num_resources  = ARRAY_SIZE(pwm_resources),
+};
+
+void __init at91_add_device_pwm(u32 mask)
+{
+        if (mask & (1 << AT91_PWM0))
+                at91_set_A_periph(AT91_PIN_PB19, 1);    /* enable PWM0 */
+
+        if (mask & (1 << AT91_PWM1))
+                at91_set_B_periph(AT91_PIN_PB8, 1);     /* enable PWM1 */
+
+        if (mask & (1 << AT91_PWM2))
+                at91_set_B_periph(AT91_PIN_PC29, 1);    /* enable PWM2 */
+
+        if (mask & (1 << AT91_PWM3))
+                at91_set_B_periph(AT91_PIN_PA11, 1);    /* enable PWM3 */
+
+        pwm_mask = mask;
+
+        platform_device_register(&at91cap9_pwm0_device);
+}
+#else
+void __init at91_add_device_pwm(u32 mask) {}
+#endif
+
+
+
+/* --------------------------------------------------------------------
  *  AC97
  * -------------------------------------------------------------------- */
 
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 80bfab5680e2..ada4b6769107 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -129,8 +129,8 @@ static struct clk tcb_clk = {
         .pmc_mask       = 1 << AT91SAM9263_ID_TCB,
         .type           = CLK_TYPE_PERIPHERAL,
 };
-static struct clk pwmc_clk = {
-        .name           = "pwmc_clk",
+static struct clk pwm_clk = {
+        .name           = "pwm_clk",
         .pmc_mask       = 1 << AT91SAM9263_ID_PWMC,
         .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -187,7 +187,7 @@ static struct clk *periph_clocks[] __initdata = {
         &ssc1_clk,
         &ac97_clk,
         &tcb_clk,
-        &pwmc_clk,
+        &pwm_clk,
         &macb_clk,
         &twodge_clk,
         &udc_clk,
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index c93992f55dc9..8b884083f76d 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -886,6 +886,59 @@ static void __init at91_add_device_watchdog(void) {}
 
 
 /* --------------------------------------------------------------------
+ *  PWM
+ * --------------------------------------------------------------------*/
+
+#if defined(CONFIG_ATMEL_PWM)
+static u32 pwm_mask;
+
+static struct resource pwm_resources[] = {
+        [0] = {
+                .start  = AT91SAM9263_BASE_PWMC,
+                .end    = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9263_ID_PWMC,
+                .end    = AT91SAM9263_ID_PWMC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9263_pwm0_device = {
+        .name   = "atmel_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data          = &pwm_mask,
+        },
+        .resource       = pwm_resources,
+        .num_resources  = ARRAY_SIZE(pwm_resources),
+};
+
+void __init at91_add_device_pwm(u32 mask)
+{
+        if (mask & (1 << AT91_PWM0))
+                at91_set_B_periph(AT91_PIN_PB7, 1);     /* enable PWM0 */
+
+        if (mask & (1 << AT91_PWM1))
+                at91_set_B_periph(AT91_PIN_PB8, 1);     /* enable PWM1 */
+
+        if (mask & (1 << AT91_PWM2))
+                at91_set_B_periph(AT91_PIN_PC29, 1);    /* enable PWM2 */
+
+        if (mask & (1 << AT91_PWM3))
+                at91_set_B_periph(AT91_PIN_PB29, 1);    /* enable PWM3 */
+
+        pwm_mask = mask;
+
+        platform_device_register(&at91sam9263_pwm0_device);
+}
+#else
+void __init at91_add_device_pwm(u32 mask) {}
+#endif
+
+
+/* --------------------------------------------------------------------
  *  SSC -- Synchronous Serial Controller
  * -------------------------------------------------------------------- */
 
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 556bddf35b45..252e954b49fd 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -131,8 +131,8 @@ static struct clk tc2_clk = {
         .pmc_mask       = 1 << AT91SAM9RL_ID_TC2,
         .type           = CLK_TYPE_PERIPHERAL,
 };
-static struct clk pwmc_clk = {
-        .name           = "pwmc_clk",
+static struct clk pwm_clk = {
+        .name           = "pwm_clk",
         .pmc_mask       = 1 << AT91SAM9RL_ID_PWMC,
         .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -180,7 +180,7 @@ static struct clk *periph_clocks[] __initdata = {
         &tc0_clk,
         &tc1_clk,
         &tc2_clk,
-        &pwmc_clk,
+        &pwm_clk,
         &tsc_clk,
         &dma_clk,
         &udphs_clk,
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 620886341fb5..87deb1e1b529 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -527,6 +527,51 @@ static void __init at91_add_device_tc(void) { }
 
 
 /* --------------------------------------------------------------------
+ *  Touchscreen
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
+static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
+
+static struct resource tsadcc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9RL_BASE_TSC,
+                .end    = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9RL_ID_TSC,
+                .end    = AT91SAM9RL_ID_TSC,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device at91sam9rl_tsadcc_device = {
+        .name           = "atmel_tsadcc",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &tsadcc_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = tsadcc_resources,
+        .num_resources  = ARRAY_SIZE(tsadcc_resources),
+};
+
+void __init at91_add_device_tsadcc(void)
+{
+        at91_set_A_periph(AT91_PIN_PA17, 0);    /* AD0_XR */
+        at91_set_A_periph(AT91_PIN_PA18, 0);    /* AD1_XL */
+        at91_set_A_periph(AT91_PIN_PA19, 0);    /* AD2_YT */
+        at91_set_A_periph(AT91_PIN_PA20, 0);    /* AD3_TB */
+
+        platform_device_register(&at91sam9rl_tsadcc_device);
+}
+#else
+void __init at91_add_device_tsadcc(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTC
  * -------------------------------------------------------------------- */
 
@@ -592,6 +637,59 @@ static void __init at91_add_device_watchdog(void) {}
 
 
 /* --------------------------------------------------------------------
+ *  PWM
+ * --------------------------------------------------------------------*/
+
+#if defined(CONFIG_ATMEL_PWM)
+static u32 pwm_mask;
+
+static struct resource pwm_resources[] = {
+        [0] = {
+                .start  = AT91SAM9RL_BASE_PWMC,
+                .end    = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9RL_ID_PWMC,
+                .end    = AT91SAM9RL_ID_PWMC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9rl_pwm0_device = {
+        .name   = "atmel_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data          = &pwm_mask,
+        },
+        .resource       = pwm_resources,
+        .num_resources  = ARRAY_SIZE(pwm_resources),
+};
+
+void __init at91_add_device_pwm(u32 mask)
+{
+        if (mask & (1 << AT91_PWM0))
+                at91_set_B_periph(AT91_PIN_PB8, 1);     /* enable PWM0 */
+
+        if (mask & (1 << AT91_PWM1))
+                at91_set_B_periph(AT91_PIN_PB9, 1);     /* enable PWM1 */
+
+        if (mask & (1 << AT91_PWM2))
+                at91_set_B_periph(AT91_PIN_PD5, 1);     /* enable PWM2 */
+
+        if (mask & (1 << AT91_PWM3))
+                at91_set_B_periph(AT91_PIN_PD8, 1);     /* enable PWM3 */
+
+        pwm_mask = mask;
+
+        platform_device_register(&at91sam9rl_pwm0_device);
+}
+#else
+void __init at91_add_device_pwm(u32 mask) {}
+#endif
+
+
+/* --------------------------------------------------------------------
  *  SSC -- Synchronous Serial Controller
  * -------------------------------------------------------------------- */
 
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 869b5e28d195..dfff2895f4b2 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -23,8 +23,8 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/time.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach/time.h>
 #include <mach/at91_tc.h>
 
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
new file mode 100644
index 000000000000..9c040c78889a
--- /dev/null
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -0,0 +1,210 @@
+/*
+ * linux/arch/arm/mach-at91/board-afeb-9260v1.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *  Copyright (C) 2008 Sergey Lapin
+ *
+ * A custom board designed as open hardware; PCBs and various information
+ * is available at http://groups.google.com/group/arm9fpga-evolution-board/
+ * Subversion repository: svn://194.85.238.22/home/users/george/svn/arm9eb
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+
+#include "generic.h"
+
+
+static void __init afeb9260_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1,
+                             ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR
+                           | ATMEL_UART_DCD | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2,
+                        ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init afeb9260_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata afeb9260_usbh_data = {
+        .ports          = 1,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata afeb9260_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info afeb9260_spi_devices[] = {
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 1,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata afeb9260_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA9,
+        .is_rmii        = 0,
+};
+
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata afeb9260_nand_partition[] = {
+        {
+                .name   = "bootloader",
+                .offset = 0,
+                .size   = (640 * SZ_1K),
+        },
+        {
+                .name   = "kernel",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = SZ_2M,
+        },
+        {
+                .name   = "rootfs",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(afeb9260_nand_partition);
+        return afeb9260_nand_partition;
+}
+
+static struct atmel_nand_data __initdata afeb9260_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+        .bus_width_16   = 0,
+};
+
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata afeb9260_mmc_data = {
+        .slot_b         = 1,
+        .wire4          = 1,
+};
+
+
+
+static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("fm3130", 0x68),
+                I2C_BOARD_INFO("24c64", 0x50),
+        },
+};
+
+static void __init afeb9260_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&afeb9260_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&afeb9260_udc_data);
+        /* SPI */
+        at91_add_device_spi(afeb9260_spi_devices,
+                        ARRAY_SIZE(afeb9260_spi_devices));
+        /* NAND */
+        at91_add_device_nand(&afeb9260_nand_data);
+        /* Ethernet */
+        at91_add_device_eth(&afeb9260_macb_data);
+
+        /* Standard function's pin assignments are not
+         * appropriate for us and generic code provide
+         * no API to configure these pins any other way */
+        at91_set_B_periph(AT91_PIN_PA10, 0);    /* ETX2 */
+        at91_set_B_periph(AT91_PIN_PA11, 0);    /* ETX3 */
+        /* MMC */
+        at91_add_device_mmc(0, &afeb9260_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(afeb9260_i2c_devices,
+                        ARRAY_SIZE(afeb9260_i2c_devices));
+}
+
+MACHINE_START(AFEB9260, "Custom afeb9260 board")
+        /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = afeb9260_map_io,
+        .init_irq       = afeb9260_init_irq,
+        .init_machine   = afeb9260_board_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index 196199552eb6..201b89392dcc 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -214,7 +214,7 @@ static struct physmap_flash_data cap9adk_nor_data = {
 };
 
 #define NOR_BASE        AT91_CHIPSELECT_0
-#define NOR_SIZE        0x800000
+#define NOR_SIZE        SZ_8M
 
 static struct resource nor_flash_resources[] = {
         {
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index afa1ff0e9577..db1f9544d2e0 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -25,7 +25,6 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,6 +33,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 
@@ -114,6 +114,30 @@ static struct spi_board_info carmeva_spi_devices[] = {
         },
 };
 
+static struct gpio_led carmeva_leds[] = {
+        { /* "user led 1", LED9 */
+                .name                   = "led9",
+                .gpio                   = AT91_PIN_PA21,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        { /* "user led 2", LED10 */
+                .name                   = "led10",
+                .gpio                   = AT91_PIN_PA25,
+                .active_low             = 1,
+        },
+        { /* "user led 3", LED11 */
+                .name                   = "led11",
+                .gpio                   = AT91_PIN_PA26,
+                .active_low             = 1,
+        },
+        { /* "user led 4", LED12 */
+                .name                   = "led12",
+                .gpio                   = AT91_PIN_PA18,
+                .active_low             = 1,
+        }
+};
+
 static void __init carmeva_board_init(void)
 {
         /* Serial */
@@ -132,6 +156,8 @@ static void __init carmeva_board_init(void)
 //      at91_add_device_cf(&carmeva_cf_data);
         /* MMC */
         at91_add_device_mmc(0, &carmeva_mmc_data);
+        /* LEDs */
+        at91_gpio_leds(carmeva_leds, ARRAY_SIZE(carmeva_leds));
 }
 
 MACHINE_START(CARMEVA, "Carmeva")
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index cb7c9a8fa487..fea2529ebcf9 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -28,7 +28,6 @@
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,6 +36,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 
@@ -114,7 +114,7 @@ static struct spi_board_info csb337_spi_devices[] = {
 };
 
 #define CSB_FLASH_BASE  AT91_CHIPSELECT_0
-#define CSB_FLASH_SIZE  0x800000
+#define CSB_FLASH_SIZE  SZ_8M
 
 static struct mtd_partition csb_flash_partitions[] = {
         {
@@ -193,11 +193,11 @@ static struct platform_device csb300_button_device = {
 
 static void __init csb300_add_device_buttons(void)
 {
-        at91_set_gpio_input(AT91_PIN_PB29, 0);  /* sw0 */
+        at91_set_gpio_input(AT91_PIN_PB29, 1);  /* sw0 */
         at91_set_deglitch(AT91_PIN_PB29, 1);
-        at91_set_gpio_input(AT91_PIN_PB28, 0);  /* sw1 */
+        at91_set_gpio_input(AT91_PIN_PB28, 1);  /* sw1 */
         at91_set_deglitch(AT91_PIN_PB28, 1);
-        at91_set_gpio_input(AT91_PIN_PA21, 0);  /* sw2 */
+        at91_set_gpio_input(AT91_PIN_PA21, 1);  /* sw2 */
         at91_set_deglitch(AT91_PIN_PA21, 1);
 
         platform_device_register(&csb300_button_device);
@@ -224,7 +224,7 @@ static struct gpio_led csb_leds[] = {
                 .gpio                   = AT91_PIN_PB0,
                 .active_low             = 1,
                 .default_trigger        = "ide-disk",
-        },
+        }
 };
 
 
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 8db8bd8babd9..cfa3f04b2205 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -25,7 +25,6 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -34,6 +33,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 
@@ -72,7 +72,7 @@ static struct at91_udc_data __initdata csb637_udc_data = {
 };
 
 #define CSB_FLASH_BASE  AT91_CHIPSELECT_0
-#define CSB_FLASH_SIZE  0x1000000
+#define CSB_FLASH_SIZE  SZ_16M
 
 static struct mtd_partition csb_flash_partitions[] = {
         {
diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-dk.c
index 43e1aa7ecef7..0fd0f5bc77ea 100644
--- a/arch/arm/mach-at91/board-dk.c
+++ b/arch/arm/mach-at91/board-dk.c
@@ -29,7 +29,6 @@
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -38,6 +37,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91rm9200_mc.h>
@@ -157,7 +157,7 @@ static struct atmel_nand_data __initdata dk_nand_data = {
 };
 
 #define DK_FLASH_BASE   AT91_CHIPSELECT_0
-#define DK_FLASH_SIZE   0x200000
+#define DK_FLASH_SIZE   SZ_2M
 
 static struct physmap_flash_data dk_flash_data = {
         .width          = 2,
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index bfeee8a2af28..1d69908617f0 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -86,7 +86,7 @@ static struct mtd_partition __initdata my_flash0_partitions[] =
         {       /* 0x8400 */
                 .name   = "Darrell-loader",
                 .offset = 0,
-                .size   = 12* 1056,
+                .size   = 12 * 1056,
         },
         {
                 .name   = "U-boot",
diff --git a/arch/arm/mach-at91/board-ek.c b/arch/arm/mach-at91/board-ek.c
index 60626e7a3490..4cdfaac8e590 100644
--- a/arch/arm/mach-at91/board-ek.c
+++ b/arch/arm/mach-at91/board-ek.c
@@ -29,7 +29,6 @@
 #include <linux/spi/spi.h>
 #include <linux/mtd/physmap.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -38,6 +37,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91rm9200_mc.h>
@@ -116,7 +116,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
 };
 
 #define EK_FLASH_BASE   AT91_CHIPSELECT_0
-#define EK_FLASH_SIZE   0x200000
+#define EK_FLASH_SIZE   SZ_2M
 
 static struct physmap_flash_data ek_flash_data = {
         .width          = 2,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index dbc912d633c7..859727e7ea30 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -105,7 +105,7 @@ static struct at91_mmc_data __initdata picotux200_mmc_data = {
 // };
 
 #define PICOTUX200_FLASH_BASE   AT91_CHIPSELECT_0
-#define PICOTUX200_FLASH_SIZE   0x400000
+#define PICOTUX200_FLASH_SIZE   SZ_4M
 
 static struct physmap_flash_data picotux200_flash_data = {
         .width  = 2,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 4c28413426c2..cfb4571a2e27 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -30,7 +30,6 @@
 #include <linux/input.h>
 #include <linux/clk.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -39,6 +38,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91_shdwc.h>
@@ -119,18 +119,18 @@ static struct at91_eth_data __initdata ek_macb_data = {
 static struct mtd_partition __initdata ek_nand_partition[] = {
         {
                 .name   = "Uboot & Kernel",
-                .offset = 0x00000000,
-                .size   = 16 * 1024 * 1024,
+                .offset = 0,
+                .size   = SZ_16M,
         },
         {
                 .name   = "Root FS",
-                .offset = 0x01000000,
-                .size   = 120 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 120 * SZ_1M,
         },
         {
                 .name   = "FS",
-                .offset = 0x08800000,
-                .size   = 120 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 120 * SZ_1M,
         },
 };
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index e4910cb26c16..99bb4cc23a09 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -126,11 +126,11 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
         {
                 .name   = "Bootloader Area",
                 .offset = 0,
-                .size   = 10 * 1024 * 1024,
+                .size   = 10 * SZ_1M,
         },
         {
                 .name   = "User Area",
-                .offset = 10 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
                 .size   = MTDPART_SIZ_FULL,
         },
 };
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index cb20e70b3b06..b49eb6e4918a 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -27,8 +27,10 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/at73c213.h>
 #include <linux/clk.h>
+#include <linux/i2c/at24.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -37,6 +39,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 
@@ -163,11 +166,11 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
         {
                 .name   = "Partition 1",
                 .offset = 0,
-                .size   = 256 * 1024,
+                .size   = SZ_256K,
         },
         {
                 .name   = "Partition 2",
-                .offset = 256 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
                 .size   = MTDPART_SIZ_FULL,
         },
 };
@@ -222,6 +225,73 @@ static struct gpio_led ek_leds[] = {
         }
 };
 
+/*
+ * I2C devices
+ */
+static struct at24_platform_data at24c512 = {
+        .byte_len       = SZ_512K / 8,
+        .page_size      = 128,
+        .flags          = AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info __initdata ek_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("24c512", 0x50),
+                .platform_data = &at24c512,
+        },
+        /* more devices can be added using expansion connectors */
+};
+
+
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {
+                .gpio           = AT91_PIN_PA30,
+                .code           = BTN_3,
+                .desc           = "Button 3",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PA31,
+                .code           = BTN_4,
+                .desc           = "Button 4",
+                .active_low     = 1,
+                .wakeup         = 1,
+        }
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_gpio_input(AT91_PIN_PA30, 1);  /* btn3 */
+        at91_set_deglitch(AT91_PIN_PA30, 1);
+        at91_set_gpio_input(AT91_PIN_PA31, 1);  /* btn4 */
+        at91_set_deglitch(AT91_PIN_PA31, 1);
+
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+
 static void __init ek_board_init(void)
 {
         /* Serial */
@@ -239,12 +309,14 @@ static void __init ek_board_init(void)
         /* MMC */
         at91_add_device_mmc(0, &ek_mmc_data);
         /* I2C */
-        at91_add_device_i2c(NULL, 0);
+        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
         /* SSC (to AT73C213) */
         at73c213_set_clk(&at73c213_data);
         at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
         /* LEDs */
         at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* Push Buttons */
+        ek_add_device_buttons();
 }
 
 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 1a9963b811c7..4977409d4fc6 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -35,7 +35,6 @@
 
 #include <video/atmel_lcdc.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -44,6 +43,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91sam9_smc.h>
@@ -168,11 +168,11 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
         {
                 .name   = "Partition 1",
                 .offset = 0,
-                .size   = 256 * 1024,
+                .size   = SZ_256K,
         },
         {
                 .name   = "Partition 2",
-                .offset = 256 * 1024 ,
+                .offset = MTDPART_OFS_NXTBLK,
                 .size   = MTDPART_SIZ_FULL,
         },
 };
@@ -435,24 +435,28 @@ static struct gpio_keys_button ek_buttons[] = {
                 .code           = BTN_0,
                 .desc           = "Button 0",
                 .active_low     = 1,
+                .wakeup         = 1,
         },
         {
                 .gpio           = AT91_PIN_PA26,
                 .code           = BTN_1,
                 .desc           = "Button 1",
                 .active_low     = 1,
+                .wakeup         = 1,
         },
         {
                 .gpio           = AT91_PIN_PA25,
                 .code           = BTN_2,
                 .desc           = "Button 2",
                 .active_low     = 1,
+                .wakeup         = 1,
         },
         {
                 .gpio           = AT91_PIN_PA24,
                 .code           = BTN_3,
                 .desc           = "Button 3",
                 .active_low     = 1,
+                .wakeup         = 1,
         }
 };
 
@@ -472,13 +476,13 @@ static struct platform_device ek_button_device = {
 
 static void __init ek_add_device_buttons(void)
 {
-        at91_set_gpio_input(AT91_PIN_PA27, 0);  /* btn0 */
+        at91_set_gpio_input(AT91_PIN_PA27, 1);  /* btn0 */
         at91_set_deglitch(AT91_PIN_PA27, 1);
-        at91_set_gpio_input(AT91_PIN_PA26, 0);  /* btn1 */
+        at91_set_gpio_input(AT91_PIN_PA26, 1);  /* btn1 */
         at91_set_deglitch(AT91_PIN_PA26, 1);
-        at91_set_gpio_input(AT91_PIN_PA25, 0);  /* btn2 */
+        at91_set_gpio_input(AT91_PIN_PA25, 1);  /* btn2 */
         at91_set_deglitch(AT91_PIN_PA25, 1);
-        at91_set_gpio_input(AT91_PIN_PA24, 0);  /* btn3 */
+        at91_set_gpio_input(AT91_PIN_PA24, 1);  /* btn3 */
         at91_set_deglitch(AT91_PIN_PA24, 1);
 
         platform_device_register(&ek_button_device);
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index b1d11960a735..8354015c6a23 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -26,13 +26,14 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/i2c/at24.h>
 #include <linux/fb.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/leds.h>
 
 #include <video/atmel_lcdc.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -41,6 +42,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91sam9_smc.h>
@@ -172,11 +174,11 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
         {
                 .name   = "Partition 1",
                 .offset = 0,
-                .size   = 64 * 1024 * 1024,
+                .size   = SZ_64M,
         },
         {
                 .name   = "Partition 2",
-                .offset = 64 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
                 .size   = MTDPART_SIZ_FULL,
         },
 };
@@ -203,12 +205,30 @@ static struct atmel_nand_data __initdata ek_nand_data = {
 
 
 /*
+ * I2C devices
+ */
+static struct at24_platform_data at24c512 = {
+        .byte_len       = SZ_512K / 8,
+        .page_size      = 128,
+        .flags          = AT24_FLAG_ADDR16,
+};
+
+
+static struct i2c_board_info __initdata ek_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("24c512", 0x50),
+                .platform_data = &at24c512,
+        },
+        /* more devices can be added using expansion connectors */
+};
+
+/*
  * LCD Controller
  */
 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 static struct fb_videomode at91_tft_vga_modes[] = {
         {
-                .name           = "TX09D50VM1CCA @ 60",
+                .name           = "TX09D50VM1CCA @ 60",
                 .refresh        = 60,
                 .xres           = 240,          .yres           = 320,
                 .pixclock       = KHZ2PICOS(4965),
@@ -224,7 +244,7 @@ static struct fb_videomode at91_tft_vga_modes[] = {
 
 static struct fb_monspecs at91fb_default_monspecs = {
         .manufacturer   = "HIT",
-        .monitor        = "TX09D70VM1CCA",
+        .monitor        = "TX09D70VM1CCA",
 
         .modedb         = at91_tft_vga_modes,
         .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
@@ -235,7 +255,7 @@ static struct fb_monspecs at91fb_default_monspecs = {
 };
 
 #define AT91SAM9263_DEFAULT_LCDCON2     (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_TFT    \
+                                        | ATMEL_LCDC_DISTYPE_TFT \
                                         | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
 
 static void at91_lcdc_power_control(int on)
@@ -277,7 +297,7 @@ static struct gpio_keys_button ek_buttons[] = {
                 .active_low     = 1,
                 .desc           = "right_click",
                 .wakeup         = 1,
-        },
+        }
 };
 
 static struct gpio_keys_platform_data ek_button_data = {
@@ -296,9 +316,9 @@ static struct platform_device ek_button_device = {
 
 static void __init ek_add_device_buttons(void)
 {
-        at91_set_GPIO_periph(AT91_PIN_PC5, 0);  /* left button */
+        at91_set_GPIO_periph(AT91_PIN_PC5, 1);  /* left button */
         at91_set_deglitch(AT91_PIN_PC5, 1);
-        at91_set_GPIO_periph(AT91_PIN_PC4, 0);  /* right button */
+        at91_set_GPIO_periph(AT91_PIN_PC4, 1);  /* right button */
         at91_set_deglitch(AT91_PIN_PC4, 1);
 
         platform_device_register(&ek_button_device);
@@ -320,25 +340,32 @@ static struct atmel_ac97_data ek_ac97_data = {
  * LEDs ... these could all be PWM-driven, for variable brightness
  */
 static struct gpio_led ek_leds[] = {
-        {       /* "left" led, green, userled1, pwm1 */
-                .name                   = "ds1",
-                .gpio                   = AT91_PIN_PB8,
-                .active_low             = 1,
-                .default_trigger        = "mmc0",
-        },
-        {       /* "right" led, green, userled2, pwm2 */
+        {       /* "right" led, green, userled2 (could be driven by pwm2) */
                 .name                   = "ds2",
                 .gpio                   = AT91_PIN_PC29,
                 .active_low             = 1,
                 .default_trigger        = "nand-disk",
         },
-        {       /* "power" led, yellow, pwm0 */
+        {       /* "power" led, yellow (could be driven by pwm0) */
                 .name                   = "ds3",
                 .gpio                   = AT91_PIN_PB7,
                 .default_trigger        = "heartbeat",
         }
 };
 
+/*
+ * PWM Leds
+ */
+static struct gpio_led ek_pwm_led[] = {
+        /* For now only DS1 is PWM-driven (by pwm1) */
+        {
+                .name                   = "ds1",
+                .gpio                   = 1,    /* is PWM channel number */
+                .active_low             = 1,
+                .default_trigger        = "none",
+        }
+};
+
 
 static void __init ek_board_init(void)
 {
@@ -360,7 +387,7 @@ static void __init ek_board_init(void)
         /* NAND */
         at91_add_device_nand(&ek_nand_data);
         /* I2C */
-        at91_add_device_i2c(NULL, 0);
+        at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
         /* LCD Controller */
         at91_add_device_lcdc(&ek_lcdc_data);
         /* Push Buttons */
@@ -369,6 +396,7 @@ static void __init ek_board_init(void)
         at91_add_device_ac97(&ek_ac97_data);
         /* LEDs */
         at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
 }
 
 MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index d4eba5c0ce02..b588ead14d68 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -122,16 +122,16 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
         {
                 .name   = "Bootstrap",
                 .offset = 0,
-                .size   = 4 * 1024 * 1024,
+                .size   = 4 * SZ_1M,
         },
         {
                 .name   = "Partition 1",
-                .offset = 4 * 1024 * 1024,
-                .size   = 60 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 60 * SZ_1M,
         },
         {
                 .name   = "Partition 2",
-                .offset = 64 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
                 .size   = MTDPART_SIZ_FULL,
         },
 };
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index c6dce49c388c..270851864308 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -18,7 +18,6 @@
 
 #include <video/atmel_lcdc.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -27,6 +26,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91sam9_smc.h>
@@ -81,11 +81,11 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
         {
                 .name   = "Partition 1",
                 .offset = 0,
-                .size   = 256 * 1024,
+                .size   = SZ_256K,
         },
         {
                 .name   = "Partition 2",
-                .offset = 256 * 1024 ,
+                .offset = MTDPART_OFS_NXTBLK,
                 .size   = MTDPART_SIZ_FULL,
         },
 };
@@ -195,6 +195,8 @@ static void __init ek_board_init(void)
         at91_add_device_mmc(0, &ek_mmc_data);
         /* LCD Controller */
         at91_add_device_lcdc(&ek_lcdc_data);
+        /* Touch Screen Controller */
+        at91_add_device_tsadcc();
 }
 
 MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
index f9d0b65da40b..7c350357333a 100644
--- a/arch/arm/mach-at91/board-usb-a9260.c
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -30,7 +30,6 @@
 #include <linux/input.h>
 #include <linux/clk.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -39,6 +38,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91_shdwc.h>
@@ -93,18 +93,18 @@ static struct at91_eth_data __initdata ek_macb_data = {
 static struct mtd_partition __initdata ek_nand_partition[] = {
         {
                 .name   = "Uboot & Kernel",
-                .offset = 0x00000000,
-                .size   = 16 * 1024 * 1024,
+                .offset = 0,
+                .size   = SZ_16M,
         },
         {
                 .name   = "Root FS",
-                .offset = 0x01000000,
-                .size   = 120 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 120 * SZ_1M,
         },
         {
                 .name   = "FS",
-                .offset = 0x08800000,
-                .size   = 120 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 120 * SZ_1M,
         }
 };
 
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
index 673e5c27214d..391b566c4571 100644
--- a/arch/arm/mach-at91/board-usb-a9263.c
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -29,7 +29,6 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -38,6 +37,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91_shdwc.h>
@@ -106,18 +106,18 @@ static struct at91_eth_data __initdata ek_macb_data = {
 static struct mtd_partition __initdata ek_nand_partition[] = {
         {
                 .name   = "Linux Kernel",
-                .offset = 0x00000000,
-                .size   = 16 * 1024 * 1024,
+                .offset = 0,
+                .size   = SZ_16M,
         },
         {
                 .name   = "Root FS",
-                .offset = 0x01000000,
-                .size   = 120 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 120 * SZ_1M,
         },
         {
                 .name   = "FS",
-                .offset = 0x08800000,
-                .size   = 120 * 1024 * 1024,
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 120 * SZ_1M,
         }
 };
 
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 36b380aad006..e22bf051f835 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -33,7 +33,6 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 
-#include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
@@ -42,6 +41,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91rm9200_mc.h>
@@ -150,27 +150,27 @@ static struct mtd_partition __initdata yl9200_nand_partition[] = {
         {
                 .name   = "AT91 NAND partition 1, boot",
                 .offset = 0,
-                .size   = 1 * SZ_256K
+                .size   = SZ_256K
         },
         {
                 .name   = "AT91 NAND partition 2, kernel",
-                .offset = 1 * SZ_256K,
-                .size   = 2 * SZ_1M - 1 * SZ_256K
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = (2 * SZ_1M) - SZ_256K
         },
         {
                 .name   = "AT91 NAND partition 3, filesystem",
-                .offset = 2 * SZ_1M,
+                .offset = MTDPART_OFS_NXTBLK,
                 .size   = 14 * SZ_1M
         },
         {
                 .name   = "AT91 NAND partition 4, storage",
-                .offset = 16 * SZ_1M,
-                .size   = 16 * SZ_1M
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = SZ_16M
         },
         {
                 .name   = "AT91 NAND partition 5, ext-fs",
-                .offset = 32 * SZ_1M,
-                .size   = 32 * SZ_1M
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = SZ_32M
         }
 };
 
@@ -193,24 +193,24 @@ static struct atmel_nand_data __initdata yl9200_nand_data = {
  * NOR Flash
  */
 #define YL9200_FLASH_BASE       AT91_CHIPSELECT_0
-#define YL9200_FLASH_SIZE       0x1000000
+#define YL9200_FLASH_SIZE       SZ_16M
 
 static struct mtd_partition yl9200_flash_partitions[] = {
         {
                 .name           = "Bootloader",
-                .size           = 0x00040000,
                 .offset         = 0,
+                .size           = SZ_256K,
                 .mask_flags     = MTD_WRITEABLE,        /* force read-only */
         },
         {
                 .name           = "Kernel",
-                .size           = 0x001C0000,
-                .offset         = 0x00040000,
+                .offset         = MTDPART_OFS_NXTBLK,
+                .size           = (2 * SZ_1M) - SZ_256K
         },
         {
                 .name           = "Filesystem",
-                .size           = MTDPART_SIZ_FULL,
-                .offset         = 0x00200000
+                .offset         = MTDPART_OFS_NXTBLK,
+                .size           = MTDPART_SIZ_FULL
         }
 };
 
@@ -390,10 +390,6 @@ static struct spi_board_info yl9200_spi_devices[] = {
 #if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
 #include <video/s1d13xxxfb.h>
 
-#define AT91_FB_REG_BASE        0x80000000L
-#define AT91_FB_REG_SIZE        0x200
-#define AT91_FB_VMEM_BASE       0x80200000L
-#define AT91_FB_VMEM_SIZE       0x200000L
 
 static void __init yl9200_init_video(void)
 {
@@ -516,29 +512,33 @@ static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
         {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
 };
 
-static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
-
 static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
         .initregs               = yl9200_s1dfb_initregs,
         .initregssize           = ARRAY_SIZE(yl9200_s1dfb_initregs),
         .platform_init_video    = yl9200_init_video,
 };
 
+#define YL9200_FB_REG_BASE      AT91_CHIPSELECT_7
+#define YL9200_FB_VMEM_BASE     YL9200_FB_REG_BASE + SZ_2M
+#define YL9200_FB_VMEM_SIZE     SZ_2M
+
 static struct resource yl9200_s1dfb_resource[] = {
         [0] = { /* video mem */
                 .name   = "s1d13xxxfb memory",
-                .start  = AT91_FB_VMEM_BASE,
-                .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
+                .start  = YL9200_FB_VMEM_BASE,
+                .end    = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = { /* video registers */
                 .name   = "s1d13xxxfb registers",
-                .start  = AT91_FB_REG_BASE,
-                .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
+                .start  = YL9200_FB_REG_BASE,
+                .end    = YL9200_FB_REG_BASE + SZ_512 -1,
                 .flags  = IORESOURCE_MEM,
         },
 };
 
+static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
+
 static struct platform_device yl9200_s1dfb_device = {
         .name           = "s1d13806fb",
         .id             = -1,
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index f5c2847161f5..e4345106ee57 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -22,8 +22,7 @@
 #include <linux/spinlock.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 8392d5b517f1..7e5ebb5bdd17 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -18,8 +18,8 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/module.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
 #include <mach/gpio.h>
@@ -404,7 +404,6 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                 }
 
                 pin = bank->chipbase;
-                gpio = &irq_desc[pin];
 
                 while (isr) {
                         if (isr & 1) {
@@ -417,7 +416,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                                         gpio_irq_mask(pin);
                                 }
                                 else
-                                        desc_handle_irq(pin, gpio);
+                                        generic_handle_irq(pin);
                         }
                         pin++;
                         gpio++;
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
index 0448ac36eadb..974d0bd05b5b 100644
--- a/arch/arm/mach-at91/include/mach/at91_pit.h
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
@@ -1,6 +1,9 @@
 /*
  * arch/arm/mach-at91/include/mach/at91_pit.h
  *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
  * Periodic Interval Timer (PIT) - System peripherals regsters.
  * Based on AT91SAM9261 datasheet revision D.
  *
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
index 7cd1b39aaa43..cbd2bf052c1f 100644
--- a/arch/arm/mach-at91/include/mach/at91_rstc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -1,6 +1,9 @@
 /*
  * arch/arm/mach-at91/include/mach/at91_rstc.h
  *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
  * Reset Controller (RSTC) - System peripherals regsters.
  * Based on AT91SAM9261 datasheet revision D.
  *
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h
index 71782e5d2159..7ec75de8bbb6 100644
--- a/arch/arm/mach-at91/include/mach/at91_rtt.h
+++ b/arch/arm/mach-at91/include/mach/at91_rtt.h
@@ -1,6 +1,9 @@
 /*
  * arch/arm/mach-at91/include/mach/at91_rtt.h
  *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
  * Real-time Timer (RTT) - System peripherals regsters.
  * Based on AT91SAM9261 datasheet revision D.
  *
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
index 60be5ae624f1..c4ce07e8a8fa 100644
--- a/arch/arm/mach-at91/include/mach/at91_shdwc.h
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -1,6 +1,9 @@
 /*
  * arch/arm/mach-at91/include/mach/at91_shdwc.h
  *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
  * Shutdown Controller (SHDWC) - System peripherals regsters.
  * Based on AT91SAM9261 datasheet revision D.
  *
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
index 973b4526a98e..fecc2e9f0ca8 100644
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -1,6 +1,9 @@
 /*
  * arch/arm/mach-at91/include/mach/at91_wdt.h
  *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
  * Watchdog Timer (WDT) - System peripherals regsters.
  * Based on AT91SAM9261 datasheet revision D.
  *
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
index bca878f3bd87..1499b1cbffdd 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
@@ -1,6 +1,8 @@
 /*
  * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
  *
+ *  (C) 2008 Andrew Victor
+ *
  * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
  * Based on AT91CAP9 datasheet revision B.
  *
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index f027de5df956..020f02ed921a 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -1,6 +1,8 @@
 /*
  * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
  *
+ *  Copyright (C) 2007 Atmel Corporation.
+ *
  * Memory Controllers (MATRIX, EBI) - System peripherals registers.
  * Based on AT91SAM9260 datasheet revision B.
  *
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index db62b1f18300..69c6501915d9 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -1,6 +1,8 @@
 /*
  * arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
  *
+ *  Copyright (C) 2007 Atmel Corporation.
+ *
  * Memory Controllers (MATRIX, EBI) - System peripherals registers.
  * Based on AT91SAM9261 datasheet revision D.
  *
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 1921181c63ca..b7260389f7ca 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -1,6 +1,9 @@
 /*
  * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
  *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
  * SDRAM Controllers (SDRAMC) - System peripherals registers.
  * Based on AT91SAM9261 datasheet revision D.
  *
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index ec6ad1338b5a..57de6207e57e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -1,6 +1,9 @@
 /*
  * arch/arm/mach-at91/include/mach/at91sam9_smc.h
  *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
  * Static Memory Controllers (SMC) - System peripherals registers.
  * Based on AT91SAM9261 datasheet revision D.
  *
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index acd60f2a0724..fb51f0e0a83f 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -133,6 +133,16 @@ struct atmel_uart_data {
 extern void __init at91_add_device_serial(void);
 
 /*
+ * PWM
+ */
+#define AT91_PWM0       0
+#define AT91_PWM1       1
+#define AT91_PWM2       2
+#define AT91_PWM3       3
+
+extern void __init at91_add_device_pwm(u32 mask);
+
+/*
  * SSC -- accessed through ssc_request(id).  Drivers don't bind to SSC
  * platform devices.  Their SSC ID is part of their configuration data,
  * along with information about which SSC signals they should use.
@@ -162,9 +172,13 @@ extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
  /* ISI */
 extern void __init at91_add_device_isi(void);
 
+ /* Touchscreen Controller */
+extern void __init at91_add_device_tsadcc(void);
+
  /* LEDs */
 extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
+extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
 
 /* FIXME: this needs a better location, but gets stuff building again */
 extern int at91_suspend_entering_slow_clock(void);
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
index bda29ccbcd94..36bd55f3fc6e 100644
--- a/arch/arm/mach-at91/include/mach/irqs.h
+++ b/arch/arm/mach-at91/include/mach/irqs.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
 
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/at91_aic.h>
 
 #define NR_AIC_IRQS 32
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 0410d548e9b1..18bdcdeb474f 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -21,7 +21,7 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
 
-#include <asm/io.h>
+#include <linux/io.h>
 #include <linux/atmel_serial.h>
 
 #if defined(CONFIG_AT91_EARLY_DBGU)
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index fec03c59ff94..0415a839e1ad 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/platform_device.h>
 
 #include <mach/board.h>
 #include <mach/gpio.h>
@@ -21,15 +22,13 @@
 
 #if defined(CONFIG_NEW_LEDS)
 
-#include <linux/platform_device.h>
-
 /*
  * New cross-platform LED support.
  */
 
 static struct gpio_led_platform_data led_data;
 
-static struct platform_device at91_leds = {
+static struct platform_device at91_gpio_leds_device = {
         .name                   = "leds-gpio",
         .id                     = -1,
         .dev.platform_data      = &led_data,
@@ -47,7 +46,7 @@ void __init at91_gpio_leds(struct gpio_led *leds, int nr)
 
         led_data.leds = leds;
         led_data.num_leds = nr;
-        platform_device_register(&at91_leds);
+        platform_device_register(&at91_gpio_leds_device);
 }
 
 #else
@@ -57,6 +56,44 @@ void __init at91_gpio_leds(struct gpio_led *leds, int nr) {}
 
 /* ------------------------------------------------------------------------- */
 
+#if defined (CONFIG_LEDS_ATMEL_PWM)
+
+/*
+ * PWM Leds
+ */
+
+static struct gpio_led_platform_data pwm_led_data;
+
+static struct platform_device at91_pwm_leds_device = {
+        .name                   = "leds-atmel-pwm",
+        .id                     = -1,
+        .dev.platform_data      = &pwm_led_data,
+};
+
+void __init at91_pwm_leds(struct gpio_led *leds, int nr)
+{
+        int i;
+        u32 pwm_mask = 0;
+
+        if (!nr)
+                return;
+
+        for (i = 0; i < nr; i++)
+                pwm_mask |= (1 << leds[i].gpio);
+
+        pwm_led_data.leds = leds;
+        pwm_led_data.num_leds = nr;
+
+        at91_add_device_pwm(pwm_mask);
+        platform_device_register(&at91_pwm_leds_device);
+}
+#else
+void __init at91_pwm_leds(struct gpio_led *leds, int nr){}
+#endif
+
+
+/* ------------------------------------------------------------------------- */
+
 #if defined(CONFIG_LEDS)
 
 #include <asm/leds.h>
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index ec2fe4ca1e27..9bb4f043aa22 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -17,8 +17,8 @@
 #include <linux/sysfs.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/atomic.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
new file mode 100644
index 000000000000..987fab3d846a
--- /dev/null
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -0,0 +1,283 @@
+/*
+ * arch/arm/mach-at91/pm_slow_clock.S
+ *
+ *  Copyright (C) 2006 Savin Zlobec
+ *
+ * AT91SAM9 support:
+ *  Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/linkage.h>
+#include <mach/hardware.h>
+#include <mach/at91_pmc.h>
+
+#ifdef CONFIG_ARCH_AT91RM9200
+#include <mach/at91rm9200_mc.h>
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#include <mach/at91cap9_ddrsdr.h>
+#else
+#include <mach/at91sam9_sdramc.h>
+#endif
+
+
+#ifdef CONFIG_ARCH_AT91SAM9263
+/*
+ * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
+ * handle those cases both here and in the Suspend-To-RAM support.
+ */
+#define AT91_SDRAMC     AT91_SDRAMC0
+#warning Assuming EB1 SDRAM controller is *NOT* used
+#endif
+
+/*
+ * When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
+ * clock during suspend by adjusting its prescalar and divisor.
+ * NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
+ *       are errata regarding adjusting the prescalar and divisor.
+ */
+#undef SLOWDOWN_MASTER_CLOCK
+
+#define MCKRDY_TIMEOUT          1000
+#define MOSCRDY_TIMEOUT         1000
+#define PLLALOCK_TIMEOUT        1000
+#define PLLBLOCK_TIMEOUT        1000
+
+
+/*
+ * Wait until master clock is ready (after switching master clock source)
+ */
+        .macro wait_mckrdy
+        mov     r4, #MCKRDY_TIMEOUT
+1:      sub     r4, r4, #1
+        cmp     r4, #0
+        beq     2f
+        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
+        tst     r3, #AT91_PMC_MCKRDY
+        beq     1b
+2:
+        .endm
+
+/*
+ * Wait until master oscillator has stabilized.
+ */
+        .macro wait_moscrdy
+        mov     r4, #MOSCRDY_TIMEOUT
+1:      sub     r4, r4, #1
+        cmp     r4, #0
+        beq     2f
+        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
+        tst     r3, #AT91_PMC_MOSCS
+        beq     1b
+2:
+        .endm
+
+/*
+ * Wait until PLLA has locked.
+ */
+        .macro wait_pllalock
+        mov     r4, #PLLALOCK_TIMEOUT
+1:      sub     r4, r4, #1
+        cmp     r4, #0
+        beq     2f
+        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
+        tst     r3, #AT91_PMC_LOCKA
+        beq     1b
+2:
+        .endm
+
+/*
+ * Wait until PLLB has locked.
+ */
+        .macro wait_pllblock
+        mov     r4, #PLLBLOCK_TIMEOUT
+1:      sub     r4, r4, #1
+        cmp     r4, #0
+        beq     2f
+        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
+        tst     r3, #AT91_PMC_LOCKB
+        beq     1b
+2:
+        .endm
+
+        .text
+
+ENTRY(at91_slow_clock)
+        /* Save registers on stack */
+        stmfd   sp!, {r0 - r12, lr}
+
+        /*
+         * Register usage:
+         *  R1 = Base address of AT91_PMC
+         *  R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200)
+         *  R3 = temporary register
+         *  R4 = temporary register
+         */
+        ldr     r1, .at91_va_base_pmc
+        ldr     r2, .at91_va_base_sdramc
+
+        /* Drain write buffer */
+        mcr     p15, 0, r0, c7, c10, 4
+
+#ifdef CONFIG_ARCH_AT91RM9200
+        /* Put SDRAM in self-refresh mode */
+        mov     r3, #1
+        str     r3, [r2, #AT91_SDRAMC_SRR]
+#elif defined(CONFIG_ARCH_AT91CAP9)
+        /* Enable SDRAM self-refresh mode */
+        ldr     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+        str     r3, .saved_sam9_lpr
+
+        mov     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+        str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+#else
+        /* Enable SDRAM self-refresh mode */
+        ldr     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+        str     r3, .saved_sam9_lpr
+
+        mov     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
+        str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+#endif
+
+        /* Save Master clock setting */
+        ldr     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        str     r3, .saved_mckr
+
+        /*
+         * Set the Master clock source to slow clock
+         */
+        bic     r3, r3, #AT91_PMC_CSS
+        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+
+        wait_mckrdy
+
+#ifdef SLOWDOWN_MASTER_CLOCK
+        /*
+         * Set the Master Clock PRES and MDIV fields.
+         *
+         * See AT91RM9200 errata #27 and #28 for details.
+         */
+        mov     r3, #0
+        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+
+        wait_mckrdy
+#endif
+
+        /* Save PLLA setting and disable it */
+        ldr     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+        str     r3, .saved_pllar
+
+        mov     r3, #AT91_PMC_PLLCOUNT
+        orr     r3, r3, #(1 << 29)              /* bit 29 always set */
+        str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+
+        wait_pllalock
+
+        /* Save PLLB setting and disable it */
+        ldr     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+        str     r3, .saved_pllbr
+
+        mov     r3, #AT91_PMC_PLLCOUNT
+        str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+
+        wait_pllblock
+
+        /* Turn off the main oscillator */
+        ldr     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        bic     r3, r3, #AT91_PMC_MOSCEN
+        str     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+
+        /* Wait for interrupt */
+        mcr     p15, 0, r0, c7, c0, 4
+
+        /* Turn on the main oscillator */
+        ldr     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        orr     r3, r3, #AT91_PMC_MOSCEN
+        str     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+
+        wait_moscrdy
+
+        /* Restore PLLB setting */
+        ldr     r3, .saved_pllbr
+        str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+
+        wait_pllblock
+
+        /* Restore PLLA setting */
+        ldr     r3, .saved_pllar
+        str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+
+        wait_pllalock
+
+#ifdef SLOWDOWN_MASTER_CLOCK
+        /*
+         * First set PRES if it was not 0,
+         * than set CSS and MDIV fields.
+         *
+         * See AT91RM9200 errata #27 and #28 for details.
+         */
+        ldr     r3, .saved_mckr
+        tst     r3, #AT91_PMC_PRES
+        beq     2f
+        and     r3, r3, #AT91_PMC_PRES
+        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+
+        wait_mckrdy
+#endif
+
+        /*
+         * Restore master clock setting
+         */
+2:      ldr     r3, .saved_mckr
+        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+
+        wait_mckrdy
+
+#ifdef CONFIG_ARCH_AT91RM9200
+        /* Do nothing - self-refresh is automatically disabled. */
+#elif defined(CONFIG_ARCH_AT91CAP9)
+        /* Restore LPR on AT91CAP9 */
+        ldr     r3, .saved_sam9_lpr
+        str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+#else
+        /* Restore LPR on AT91SAM9 */
+        ldr     r3, .saved_sam9_lpr
+        str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+#endif
+
+        /* Restore registers, and return */
+        ldmfd   sp!, {r0 - r12, pc}
+
+
+.saved_mckr:
+        .word 0
+
+.saved_pllar:
+        .word 0
+
+.saved_pllbr:
+        .word 0
+
+.saved_sam9_lpr:
+        .word 0
+
+.at91_va_base_pmc:
+        .word AT91_VA_BASE_SYS + AT91_PMC
+
+#ifdef CONFIG_ARCH_AT91RM9200
+.at91_va_base_sdramc:
+        .word AT91_VA_BASE_SYS
+#elif defined(CONFIG_ARCH_AT91CAP9)
+.at91_va_base_sdramc:
+        .word AT91_VA_BASE_SYS + AT91_DDRSDRC
+#else
+.at91_va_base_sdramc:
+        .word AT91_VA_BASE_SYS + AT91_SDRAMC
+#endif
+
+ENTRY(at91_slow_clock_sz)
+        .word .-at91_slow_clock
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 474616dcd7a6..5f18eccdc725 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -22,10 +22,10 @@
 #include <linux/types.h>
 #include <linux/string.h>
 #include <linux/mm.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/sizes.h>
-#include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index aa02aa5a01f4..71a80b5b8ad6 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -22,9 +22,9 @@
 #include <linux/types.h>
 #include <linux/string.h>
 #include <linux/mm.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h
index a8eade40317f..24e96159e3e7 100644
--- a/arch/arm/mach-clps711x/include/mach/system.h
+++ b/arch/arm/mach-clps711x/include/mach/system.h
@@ -20,9 +20,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/hardware/clps7111.h>
-#include <asm/io.h>
 
 static inline void arch_idle(void)
 {
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 38623cfcac5a..9a12d8562284 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -19,10 +19,10 @@
  */
 #include <linux/init.h>
 #include <linux/list.h>
+#include <linux/io.h>
 
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <asm/hardware/clps7111.h>
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
index 262c3c361453..15121446efc8 100644
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ b/arch/arm/mach-clps711x/p720t-leds.c
@@ -21,9 +21,9 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index f51f97d4f212..0d94a30fd6fc 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -22,9 +22,9 @@
 #include <linux/types.h>
 #include <linux/string.h>
 #include <linux/mm.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-clps711x/time.c b/arch/arm/mach-clps711x/time.c
index ef1fcd17189e..d581ef0bcd24 100644
--- a/arch/arm/mach-clps711x/time.c
+++ b/arch/arm/mach-clps711x/time.c
@@ -21,11 +21,11 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
-#include <asm/io.h>
 #include <asm/hardware/clps7111.h>
 
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c
index cc1b82179e83..c3a33b8a5aac 100644
--- a/arch/arm/mach-clps7500/core.c
+++ b/arch/arm/mach-clps7500/core.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/serial_8250.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -23,7 +24,6 @@
 
 #include <mach/hardware.h>
 #include <asm/hardware/iomd.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-clps7500/include/mach/irq.h b/arch/arm/mach-clps7500/include/mach/irq.h
index e8da3c58df76..d02fcf28ee05 100644
--- a/arch/arm/mach-clps7500/include/mach/irq.h
+++ b/arch/arm/mach-clps7500/include/mach/irq.h
@@ -10,8 +10,8 @@
  *   11-08-1999 PJB     Created ARM7500 version, derived from RiscPC code
  */
 
+#include <linux/io.h>
 #include <asm/hardware/iomd.h>
-#include <asm/io.h>
 
 static inline int fixup_irq(unsigned int irq)
 {
diff --git a/arch/arm/mach-clps7500/include/mach/memory.h b/arch/arm/mach-clps7500/include/mach/memory.h
index 3326aa99d3ec..87b32db470c8 100644
--- a/arch/arm/mach-clps7500/include/mach/memory.h
+++ b/arch/arm/mach-clps7500/include/mach/memory.h
@@ -32,4 +32,12 @@
 #define FLUSH_BASE_PHYS         0x00000000
 #define FLUSH_BASE              0xdf000000
 
+/*
+ * Sparsemem support.  Each section is a maximum of 64MB.  The sections
+ * are offset by 128MB and can cover 128MB, so that gives us a maximum
+ * of 29 physmem bits.
+ */
+#define MAX_PHYSMEM_BITS        29
+#define SECTION_SIZE_BITS       26
+
 #endif
diff --git a/arch/arm/mach-clps7500/include/mach/system.h b/arch/arm/mach-clps7500/include/mach/system.h
index 624fc2830ae0..6d325fbe8b08 100644
--- a/arch/arm/mach-clps7500/include/mach/system.h
+++ b/arch/arm/mach-clps7500/include/mach/system.h
@@ -6,8 +6,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
+#include <linux/io.h>
 #include <asm/hardware/iomd.h>
-#include <asm/io.h>
 
 static inline void arch_idle(void)
 {
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 99ac2e55774d..4dc458597f40 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,7 @@
 
 # Common objects
 obj-y                   := time.o irq.o clock.o serial.o io.o id.o psc.o \
-                           gpio.o mux.o
+                           gpio.o mux.o devices.o usb.o
 
 # Board specific
 obj-$(CONFIG_MACH_DAVINCI_EVM)  += board-evm.o
diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-evm.c
index 134355787814..a957d239a683 100644
--- a/arch/arm/mach-davinci/board-evm.c
+++ b/arch/arm/mach-davinci/board-evm.c
@@ -13,20 +13,28 @@
 #include <linux/init.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c/pcf857x.h>
+#include <linux/i2c/at24.h>
+
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/io.h>
 
 #include <asm/setup.h>
-#include <asm/io.h>
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
+#include <mach/hardware.h>
 #include <mach/common.h>
+#include <mach/i2c.h>
 
 /* other misc. init functions */
 void __init davinci_psc_init(void);
@@ -34,10 +42,10 @@ void __init davinci_irq_init(void);
 void __init davinci_map_common_io(void);
 void __init davinci_init_common_hw(void);
 
-/* NOR Flash base address set to CS0 by default */
-#define NOR_FLASH_PHYS 0x02000000
+#if defined(CONFIG_MTD_PHYSMAP) || \
+    defined(CONFIG_MTD_PHYSMAP_MODULE)
 
-static struct mtd_partition davinci_evm_partitions[] = {
+static struct mtd_partition davinci_evm_norflash_partitions[] = {
         /* bootloader (U-Boot, etc) in first 4 sectors */
         {
                 .name           = "bootloader",
@@ -68,32 +76,323 @@ static struct mtd_partition davinci_evm_partitions[] = {
         }
 };
 
-static struct physmap_flash_data davinci_evm_flash_data = {
+static struct physmap_flash_data davinci_evm_norflash_data = {
         .width          = 2,
-        .parts          = davinci_evm_partitions,
-        .nr_parts       = ARRAY_SIZE(davinci_evm_partitions),
+        .parts          = davinci_evm_norflash_partitions,
+        .nr_parts       = ARRAY_SIZE(davinci_evm_norflash_partitions),
 };
 
 /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
  * limits addresses to 16M, so using addresses past 16M will wrap */
-static struct resource davinci_evm_flash_resource = {
-        .start          = NOR_FLASH_PHYS,
-        .end            = NOR_FLASH_PHYS + SZ_16M - 1,
+static struct resource davinci_evm_norflash_resource = {
+        .start          = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
+        .end            = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
         .flags          = IORESOURCE_MEM,
 };
 
-static struct platform_device davinci_evm_flash_device = {
+static struct platform_device davinci_evm_norflash_device = {
         .name           = "physmap-flash",
         .id             = 0,
         .dev            = {
-                .platform_data  = &davinci_evm_flash_data,
+                .platform_data  = &davinci_evm_norflash_data,
         },
         .num_resources  = 1,
-        .resource       = &davinci_evm_flash_resource,
+        .resource       = &davinci_evm_norflash_resource,
+};
+
+#endif
+
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+
+static struct resource ide_resources[] = {
+        {
+                .start          = DAVINCI_CFC_ATA_BASE,
+                .end            = DAVINCI_CFC_ATA_BASE + 0x7ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = IRQ_IDE,
+                .end            = IRQ_IDE,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ide_dma_mask = DMA_32BIT_MASK;
+
+static struct platform_device ide_dev = {
+        .name           = "palm_bk3710",
+        .id             = -1,
+        .resource       = ide_resources,
+        .num_resources  = ARRAY_SIZE(ide_resources),
+        .dev = {
+                .dma_mask               = &ide_dma_mask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+        },
+};
+
+#endif
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * I2C GPIO expanders
+ */
+
+#define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
+
+
+/* U2 -- LEDs */
+
+static struct gpio_led evm_leds[] = {
+        { .name = "DS8", .active_low = 1,
+                .default_trigger = "heartbeat", },
+        { .name = "DS7", .active_low = 1, },
+        { .name = "DS6", .active_low = 1, },
+        { .name = "DS5", .active_low = 1, },
+        { .name = "DS4", .active_low = 1, },
+        { .name = "DS3", .active_low = 1, },
+        { .name = "DS2", .active_low = 1,
+                .default_trigger = "mmc0", },
+        { .name = "DS1", .active_low = 1,
+                .default_trigger = "ide-disk", },
+};
+
+static const struct gpio_led_platform_data evm_led_data = {
+        .num_leds       = ARRAY_SIZE(evm_leds),
+        .leds           = evm_leds,
+};
+
+static struct platform_device *evm_led_dev;
+
+static int
+evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
+{
+        struct gpio_led *leds = evm_leds;
+        int status;
+
+        while (ngpio--) {
+                leds->gpio = gpio++;
+                leds++;
+        }
+
+        /* what an extremely annoying way to be forced to handle
+         * device unregistration ...
+         */
+        evm_led_dev = platform_device_alloc("leds-gpio", 0);
+        platform_device_add_data(evm_led_dev,
+                        &evm_led_data, sizeof evm_led_data);
+
+        evm_led_dev->dev.parent = &client->dev;
+        status = platform_device_add(evm_led_dev);
+        if (status < 0) {
+                platform_device_put(evm_led_dev);
+                evm_led_dev = NULL;
+        }
+        return status;
+}
+
+static int
+evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
+{
+        if (evm_led_dev) {
+                platform_device_unregister(evm_led_dev);
+                evm_led_dev = NULL;
+        }
+        return 0;
+}
+
+static struct pcf857x_platform_data pcf_data_u2 = {
+        .gpio_base      = PCF_Uxx_BASE(0),
+        .setup          = evm_led_setup,
+        .teardown       = evm_led_teardown,
+};
+
+
+/* U18 - A/V clock generator and user switch */
+
+static int sw_gpio;
+
+static ssize_t
+sw_show(struct device *d, struct device_attribute *a, char *buf)
+{
+        char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
+
+        strcpy(buf, s);
+        return strlen(s);
+}
+
+static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
+
+static int
+evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
+{
+        int     status;
+
+        /* export dip switch option */
+        sw_gpio = gpio + 7;
+        status = gpio_request(sw_gpio, "user_sw");
+        if (status == 0)
+                status = gpio_direction_input(sw_gpio);
+        if (status == 0)
+                status = device_create_file(&client->dev, &dev_attr_user_sw);
+        else
+                gpio_free(sw_gpio);
+        if (status != 0)
+                sw_gpio = -EINVAL;
+
+        /* audio PLL:  48 kHz (vs 44.1 or 32), single rate (vs double) */
+        gpio_request(gpio + 3, "pll_fs2");
+        gpio_direction_output(gpio + 3, 0);
+
+        gpio_request(gpio + 2, "pll_fs1");
+        gpio_direction_output(gpio + 2, 0);
+
+        gpio_request(gpio + 1, "pll_sr");
+        gpio_direction_output(gpio + 1, 0);
+
+        return 0;
+}
+
+static int
+evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
+{
+        gpio_free(gpio + 1);
+        gpio_free(gpio + 2);
+        gpio_free(gpio + 3);
+
+        if (sw_gpio > 0) {
+                device_remove_file(&client->dev, &dev_attr_user_sw);
+                gpio_free(sw_gpio);
+        }
+        return 0;
+}
+
+static struct pcf857x_platform_data pcf_data_u18 = {
+        .gpio_base      = PCF_Uxx_BASE(1),
+        .n_latch        = (1 << 3) | (1 << 2) | (1 << 1),
+        .setup          = evm_u18_setup,
+        .teardown       = evm_u18_teardown,
 };
 
+
+/* U35 - various I/O signals used to manage USB, CF, ATA, etc */
+
+static int
+evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
+{
+        /* p0 = nDRV_VBUS (initial:  don't supply it) */
+        gpio_request(gpio + 0, "nDRV_VBUS");
+        gpio_direction_output(gpio + 0, 1);
+
+        /* p1 = VDDIMX_EN */
+        gpio_request(gpio + 1, "VDDIMX_EN");
+        gpio_direction_output(gpio + 1, 1);
+
+        /* p2 = VLYNQ_EN */
+        gpio_request(gpio + 2, "VLYNQ_EN");
+        gpio_direction_output(gpio + 2, 1);
+
+        /* p3 = n3V3_CF_RESET (initial: stay in reset) */
+        gpio_request(gpio + 3, "nCF_RESET");
+        gpio_direction_output(gpio + 3, 0);
+
+        /* (p4 unused) */
+
+        /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
+        gpio_request(gpio + 5, "WLAN_RESET");
+        gpio_direction_output(gpio + 5, 1);
+
+        /* p6 = nATA_SEL (initial: select) */
+        gpio_request(gpio + 6, "nATA_SEL");
+        gpio_direction_output(gpio + 6, 0);
+
+        /* p7 = nCF_SEL (initial: deselect) */
+        gpio_request(gpio + 7, "nCF_SEL");
+        gpio_direction_output(gpio + 7, 1);
+
+        return 0;
+}
+
+static int
+evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
+{
+        gpio_free(gpio + 7);
+        gpio_free(gpio + 6);
+        gpio_free(gpio + 5);
+        gpio_free(gpio + 3);
+        gpio_free(gpio + 2);
+        gpio_free(gpio + 1);
+        gpio_free(gpio + 0);
+        return 0;
+}
+
+static struct pcf857x_platform_data pcf_data_u35 = {
+        .gpio_base      = PCF_Uxx_BASE(2),
+        .setup          = evm_u35_setup,
+        .teardown       = evm_u35_teardown,
+};
+
+/*----------------------------------------------------------------------*/
+
+/* Most of this EEPROM is unused, but U-Boot uses some data:
+ *  - 0x7f00, 6 bytes Ethernet Address
+ *  - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
+ *  - ... newer boards may have more
+ */
+static struct at24_platform_data eeprom_info = {
+        .byte_len       = (256*1024) / 8,
+        .page_size      = 64,
+        .flags          = AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info __initdata i2c_info[] =  {
+        {
+                I2C_BOARD_INFO("pcf8574", 0x38),
+                .platform_data  = &pcf_data_u2,
+        },
+        {
+                I2C_BOARD_INFO("pcf8574", 0x39),
+                .platform_data  = &pcf_data_u18,
+        },
+        {
+                I2C_BOARD_INFO("pcf8574", 0x3a),
+                .platform_data  = &pcf_data_u35,
+        },
+        {
+                I2C_BOARD_INFO("24c256", 0x50),
+                .platform_data  = &eeprom_info,
+        },
+        /* ALSO:
+         * - tvl320aic33 audio codec (0x1b)
+         * - msp430 microcontroller (0x23)
+         * - tvp5146 video decoder (0x5d)
+         */
+};
+
+/* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
+ * which requires 100 usec of idle bus after i2c writes sent to it.
+ */
+static struct davinci_i2c_platform_data i2c_pdata = {
+        .bus_freq       = 20 /* kHz */,
+        .bus_delay      = 100 /* usec */,
+};
+
+static void __init evm_init_i2c(void)
+{
+        davinci_init_i2c(&i2c_pdata);
+        i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
+}
+
 static struct platform_device *davinci_evm_devices[] __initdata = {
-        &davinci_evm_flash_device,
+#if defined(CONFIG_MTD_PHYSMAP) || \
+    defined(CONFIG_MTD_PHYSMAP_MODULE)
+        &davinci_evm_norflash_device,
+#endif
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+        &ide_dev,
+#endif
 };
 
 static void __init
@@ -106,13 +405,21 @@ static __init void davinci_evm_init(void)
 {
         davinci_psc_init();
 
-#if defined(CONFIG_BLK_DEV_DAVINCI) || defined(CONFIG_BLK_DEV_DAVINCI_MODULE)
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+#if defined(CONFIG_MTD_PHYSMAP) || \
+    defined(CONFIG_MTD_PHYSMAP_MODULE)
         printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, "
                "but share pins.\n\t Disable IDE for NOR support.\n");
 #endif
+#endif
 
         platform_add_devices(davinci_evm_devices,
                              ARRAY_SIZE(davinci_evm_devices));
+        evm_init_i2c();
+
+        /* irlml6401 sustains over 3A, switches 5V in under 8 msec */
+        setup_usb(500, 8);
 }
 
 static __init void davinci_evm_irq_init(void)
@@ -124,7 +431,7 @@ static __init void davinci_evm_irq_init(void)
 MACHINE_START(DAVINCI_EVM, "DaVinci EVM")
         /* Maintainer: MontaVista Software <source@mvista.com> */
         .phys_io      = IO_PHYS,
-        .io_pg_offst  = (io_p2v(IO_PHYS) >> 18) & 0xfffc,
+        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
         .boot_params  = (DAVINCI_DDR_BASE + 0x100),
         .map_io       = davinci_evm_map_io,
         .init_irq     = davinci_evm_irq_init,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index d46c69b55aaa..28f6dbc95bd7 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -16,9 +16,9 @@
 #include <linux/err.h>
 #include <linux/mutex.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <mach/psc.h>
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
new file mode 100644
index 000000000000..3d4b1de8f898
--- /dev/null
+++ b/arch/arm/mach-davinci/devices.c
@@ -0,0 +1,48 @@
+/*
+ * mach-davinci/devices.c
+ *
+ * DaVinci platform device setup/initialization
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/i2c.h>
+
+static struct resource i2c_resources[] = {
+        {
+                .start          = DAVINCI_I2C_BASE,
+                .end            = DAVINCI_I2C_BASE + 0x40,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = IRQ_I2C,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device davinci_i2c_device = {
+        .name           = "i2c_davinci",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(i2c_resources),
+        .resource       = i2c_resources,
+};
+
+void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
+{
+        davinci_i2c_device.dev.platform_data = pdata;
+        (void) platform_device_register(&davinci_i2c_device);
+}
+
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index c9cb4f09b18f..b49e9d092aab 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -1,7 +1,7 @@
 /*
  * TI DaVinci GPIO Support
  *
- * Copyright (c) 2006 David Brownell
+ * Copyright (c) 2006-2007 David Brownell
  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -26,47 +26,45 @@
 
 #include <asm/mach/irq.h>
 
-static DEFINE_SPINLOCK(gpio_lock);
-static DECLARE_BITMAP(gpio_in_use, DAVINCI_N_GPIO);
 
-int gpio_request(unsigned gpio, const char *tag)
-{
-        if (gpio >= DAVINCI_N_GPIO)
-                return -EINVAL;
+static DEFINE_SPINLOCK(gpio_lock);
 
-        if (test_and_set_bit(gpio, gpio_in_use))
-                return -EBUSY;
+struct davinci_gpio {
+        struct gpio_chip        chip;
+        struct gpio_controller  *__iomem regs;
+};
 
-        return 0;
-}
-EXPORT_SYMBOL(gpio_request);
+static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
-void gpio_free(unsigned gpio)
-{
-        if (gpio >= DAVINCI_N_GPIO)
-                return;
-
-        clear_bit(gpio, gpio_in_use);
-}
-EXPORT_SYMBOL(gpio_free);
 
 /* create a non-inlined version */
-static struct gpio_controller *__iomem gpio2controller(unsigned gpio)
+static struct gpio_controller *__iomem __init gpio2controller(unsigned gpio)
 {
         return __gpio_to_controller(gpio);
 }
 
+
+/*--------------------------------------------------------------------------*/
+
 /*
- * Assuming the pin is muxed as a gpio output, set its output value.
+ * board setup code *MUST* set PINMUX0 and PINMUX1 as
+ * needed, and enable the GPIO clock.
  */
-void __gpio_set(unsigned gpio, int value)
+
+static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 {
-        struct gpio_controller *__iomem g = gpio2controller(gpio);
+        struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+        struct gpio_controller *__iomem g = d->regs;
+        u32 temp;
 
-        __raw_writel(__gpio_mask(gpio), value ? &g->set_data : &g->clr_data);
-}
-EXPORT_SYMBOL(__gpio_set);
+        spin_lock(&gpio_lock);
+        temp = __raw_readl(&g->dir);
+        temp |= (1 << offset);
+        __raw_writel(temp, &g->dir);
+        spin_unlock(&gpio_lock);
 
+        return 0;
+}
 
 /*
  * Read the pin's value (works even if it's set up as output);
@@ -75,61 +73,72 @@ EXPORT_SYMBOL(__gpio_set);
  * Note that changes are synched to the GPIO clock, so reading values back
  * right after you've set them may give old values.
  */
-int __gpio_get(unsigned gpio)
+static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        struct gpio_controller *__iomem g = gpio2controller(gpio);
+        struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+        struct gpio_controller *__iomem g = d->regs;
 
-        return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
+        return (1 << offset) & __raw_readl(&g->in_data);
 }
-EXPORT_SYMBOL(__gpio_get);
 
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * board setup code *MUST* set PINMUX0 and PINMUX1 as
- * needed, and enable the GPIO clock.
- */
-
-int gpio_direction_input(unsigned gpio)
+static int
+davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
 {
-        struct gpio_controller *__iomem g = gpio2controller(gpio);
+        struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+        struct gpio_controller *__iomem g = d->regs;
         u32 temp;
-        u32 mask;
-
-        if (!g)
-                return -EINVAL;
+        u32 mask = 1 << offset;
 
         spin_lock(&gpio_lock);
-        mask = __gpio_mask(gpio);
         temp = __raw_readl(&g->dir);
-        temp |= mask;
+        temp &= ~mask;
+        __raw_writel(mask, value ? &g->set_data : &g->clr_data);
         __raw_writel(temp, &g->dir);
         spin_unlock(&gpio_lock);
         return 0;
 }
-EXPORT_SYMBOL(gpio_direction_input);
 
-int gpio_direction_output(unsigned gpio, int value)
+/*
+ * Assuming the pin is muxed as a gpio output, set its output value.
+ */
+static void
+davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-        struct gpio_controller *__iomem g = gpio2controller(gpio);
-        u32 temp;
-        u32 mask;
+        struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+        struct gpio_controller *__iomem g = d->regs;
 
-        if (!g)
-                return -EINVAL;
+        __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
+}
+
+static int __init davinci_gpio_setup(void)
+{
+        int i, base;
+
+        for (i = 0, base = 0;
+                        i < ARRAY_SIZE(chips);
+                        i++, base += 32) {
+                chips[i].chip.label = "DaVinci";
+
+                chips[i].chip.direction_input = davinci_direction_in;
+                chips[i].chip.get = davinci_gpio_get;
+                chips[i].chip.direction_output = davinci_direction_out;
+                chips[i].chip.set = davinci_gpio_set;
+
+                chips[i].chip.base = base;
+                chips[i].chip.ngpio = DAVINCI_N_GPIO - base;
+                if (chips[i].chip.ngpio > 32)
+                        chips[i].chip.ngpio = 32;
+
+                chips[i].regs = gpio2controller(base);
+
+                gpiochip_add(&chips[i].chip);
+        }
 
-        spin_lock(&gpio_lock);
-        mask = __gpio_mask(gpio);
-        temp = __raw_readl(&g->dir);
-        temp &= ~mask;
-        __raw_writel(mask, value ? &g->set_data : &g->clr_data);
-        __raw_writel(temp, &g->dir);
-        spin_unlock(&gpio_lock);
         return 0;
 }
-EXPORT_SYMBOL(gpio_direction_output);
+pure_initcall(davinci_gpio_setup);
 
+/*--------------------------------------------------------------------------*/
 /*
  * We expect irqs will normally be set up as input pins, but they can also be
  * used as output pins ... which is convenient for testing.
@@ -201,7 +210,6 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
         desc->chip->ack(irq);
         while (1) {
                 u32             status;
-                struct irq_desc *gpio;
                 int             n;
                 int             res;
 
@@ -215,12 +223,10 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 
                 /* now demux them to the right lowlevel handler */
                 n = (int)get_irq_data(irq);
-                gpio = &irq_desc[n];
                 while (status) {
                         res = ffs(status);
                         n += res;
-                        gpio += res;
-                        desc_handle_irq(n - 1, gpio - 1);
+                        generic_handle_irq(n - 1);
                         status >>= res;
                 }
         }
diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c
index 70608f76aed8..bf067d604918 100644
--- a/arch/arm/mach-davinci/id.c
+++ b/arch/arm/mach-davinci/id.c
@@ -13,8 +13,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 #define JTAG_ID_BASE            0x01c40028
 
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index a97dfbb15e57..4b522e5c70ec 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -16,4 +16,7 @@ struct sys_timer;
 
 extern struct sys_timer davinci_timer;
 
+/* parameters describe VBUS sourcing for host mode */
+extern void setup_usb(unsigned mA, unsigned potpgt_msec);
+
 #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index ec151ccf1e8f..b3a2961f0f46 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -14,6 +14,7 @@
 #define __DAVINCI_GPIO_H
 
 #include <linux/io.h>
+#include <asm-generic/gpio.h>
 #include <mach/hardware.h>
 
 /*
@@ -27,13 +28,16 @@
  * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
  * used as gpios, not with other peripherals.
  *
- * GPIOs are numbered 0..(DAVINCI_N_GPIO-1).  For documentation, and maybe
- * for later updates, code should write GPIO(N) or:
+ * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1).  For documentation,
+ * and maybe for later updates, code should write GPIO(N) or:
  *  - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
  *  - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
  *
  * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
  * for now, that's != GPIO(N)
+ *
+ * GPIOs can also be on external chips, numbered after the ones built-in
+ * to the DaVinci chip.  For now, they won't be usable as IRQ sources.
  */
 #define GPIO(X)         (X)             /* 0 <= X <= 70 */
 #define GPIOV18(X)      (X)             /* 1.8V i/o; 0 <= X <= 53 */
@@ -67,11 +71,11 @@ __gpio_to_controller(unsigned gpio)
         void *__iomem ptr;
 
         if (gpio < 32)
-                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
+                ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
         else if (gpio < 64)
-                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
+                ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
         else if (gpio < DAVINCI_N_GPIO)
-                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
+                ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
         else
                 ptr = NULL;
         return ptr;
@@ -83,25 +87,17 @@ static inline u32 __gpio_mask(unsigned gpio)
 }
 
 /* The get/set/clear functions will inline when called with constant
- * parameters, for low-overhead bitbanging.  Illegal constant parameters
- * cause link-time errors.
+ * parameters referencing built-in GPIOs, for low-overhead bitbanging.
  *
- * Otherwise, calls with variable parameters use outlined functions.
+ * Otherwise, calls with variable parameters or referencing external
+ * GPIOs (e.g. on GPIO expander chips) use outlined functions.
  */
-extern int __error_inval_gpio(void);
-
-extern void __gpio_set(unsigned gpio, int value);
-extern int __gpio_get(unsigned gpio);
-
 static inline void gpio_set_value(unsigned gpio, int value)
 {
-        if (__builtin_constant_p(value)) {
+        if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
                 struct gpio_controller  *__iomem g;
                 u32                     mask;
 
-                if (gpio >= DAVINCI_N_GPIO)
-                        __error_inval_gpio();
-
                 g = __gpio_to_controller(gpio);
                 mask = __gpio_mask(gpio);
                 if (value)
@@ -111,48 +107,47 @@ static inline void gpio_set_value(unsigned gpio, int value)
                 return;
         }
 
-        __gpio_set(gpio, value);
+        __gpio_set_value(gpio, value);
 }
 
 /* Returns zero or nonzero; works for gpios configured as inputs OR
- * as outputs.
+ * as outputs, at least for built-in GPIOs.
  *
- * NOTE: changes in reported values are synchronized to the GPIO clock.
- * This is most easily seen after calling gpio_set_value() and then immediatly
- * gpio_get_value(), where the gpio_get_value() would return the old value
- * until the GPIO clock ticks and the new value gets latched.
+ * NOTE: for built-in GPIOs, changes in reported values are synchronized
+ * to the GPIO clock.  This is easily seen after calling gpio_set_value()
+ * and then immediately gpio_get_value(), where the gpio_get_value() will
+ * return the old value until the GPIO clock ticks and the new value gets
+ * latched.
  */
-
 static inline int gpio_get_value(unsigned gpio)
 {
-        struct gpio_controller *__iomem g;
-
-        if (!__builtin_constant_p(gpio))
-                return __gpio_get(gpio);
+        struct gpio_controller  *__iomem g;
 
-        if (gpio >= DAVINCI_N_GPIO)
-                return __error_inval_gpio();
+        if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
+                return __gpio_get_value(gpio);
 
         g = __gpio_to_controller(gpio);
-        return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
+        return __gpio_mask(gpio) & __raw_readl(&g->in_data);
 }
 
-/* powerup default direction is IN */
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
-
-#include <asm-generic/gpio.h>   /* cansleep wrappers */
-
-extern int gpio_request(unsigned gpio, const char *tag);
-extern void gpio_free(unsigned gpio);
+static inline int gpio_cansleep(unsigned gpio)
+{
+        if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
+                return 0;
+        else
+                return __gpio_cansleep(gpio);
+}
 
 static inline int gpio_to_irq(unsigned gpio)
 {
+        if (gpio >= DAVINCI_N_GPIO)
+                return -EINVAL;
         return DAVINCI_N_AINTC_IRQ + gpio;
 }
 
 static inline int irq_to_gpio(unsigned irq)
 {
+        /* caller guarantees gpio_to_irq() succeeded */
         return irq - DAVINCI_N_AINTC_IRQ;
 }
 
diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h
index e2f54168abd1..c248e9b7e825 100644
--- a/arch/arm/mach-davinci/include/mach/i2c.h
+++ b/arch/arm/mach-davinci/include/mach/i2c.h
@@ -14,8 +14,11 @@
 
 /* All frequencies are expressed in kHz */
 struct davinci_i2c_platform_data {
-        unsigned int    bus_freq;       /* standard bus frequency */
-        unsigned int    bus_delay;      /* transaction delay */
+        unsigned int    bus_freq;       /* standard bus frequency (kHz) */
+        unsigned int    bus_delay;      /* post-transaction delay (usec) */
 };
 
+/* for board setup code */
+void davinci_init_i2c(struct davinci_i2c_platform_data *);
+
 #endif /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index e7accb910864..b78ee9140496 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -22,9 +22,8 @@
 #define IO_OFFSET       0xfd000000 /* Virtual IO = 0xfec00000 */
 #define IO_SIZE         0x00400000
 #define IO_VIRT         (IO_PHYS + IO_OFFSET)
-#define io_p2v(pa)      ((pa) + IO_OFFSET)
 #define io_v2p(va)      ((va) - IO_OFFSET)
-#define IO_ADDRESS(x)   io_p2v(x)
+#define __IO_ADDRESS(x) ((x) + IO_OFFSET)
 
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
@@ -35,7 +34,12 @@
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            (a)
 
-#ifndef __ASSEMBLER__
+#define IO_ADDRESS(pa)          IOMEM(__IO_ADDRESS(pa))
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x)                x
+#else
+#define IOMEM(x)                ((void __force __iomem *)(x))
 
 /*
  * Functions to access the DaVinci IO region
@@ -46,34 +50,13 @@
  *       - DO NOT use hardcoded virtual addresses to allow changing the
  *         IO address space again if needed
  */
-#define davinci_readb(a)        (*(volatile unsigned char  *)IO_ADDRESS(a))
-#define davinci_readw(a)        (*(volatile unsigned short *)IO_ADDRESS(a))
-#define davinci_readl(a)        (*(volatile unsigned int   *)IO_ADDRESS(a))
-
-#define davinci_writeb(v,a)     (*(volatile unsigned char  *)IO_ADDRESS(a) = (v))
-#define davinci_writew(v,a)     (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
-#define davinci_writel(v,a)     (*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
-
-/* 16 bit uses LDRH/STRH, base +/- offset_8 */
-typedef struct { volatile u16 offset[256]; } __regbase16;
-#define __REGV16(vaddr)         ((__regbase16 *)((vaddr)&~0xff)) \
-                                        ->offset[((vaddr)&0xff)>>1]
-#define __REG16(paddr)          __REGV16(io_p2v(paddr))
-
-/* 8/32 bit uses LDR/STR, base +/- offset_12 */
-typedef struct { volatile u8 offset[4096]; } __regbase8;
-#define __REGV8(vaddr)          ((__regbase8  *)((vaddr)&~4095)) \
-                                        ->offset[((vaddr)&4095)>>0]
-#define __REG8(paddr)           __REGV8(io_p2v(paddr))
-
-typedef struct { volatile u32 offset[4096]; } __regbase32;
-#define __REGV32(vaddr)         ((__regbase32 *)((vaddr)&~4095)) \
-                                        ->offset[((vaddr)&4095)>>2]
-
-#define __REG(paddr)            __REGV32(io_p2v(paddr))
-#else
+#define davinci_readb(a)        __raw_readb(IO_ADDRESS(a))
+#define davinci_readw(a)        __raw_readw(IO_ADDRESS(a))
+#define davinci_readl(a)        __raw_readl(IO_ADDRESS(a))
 
-#define __REG(x)        (*((volatile unsigned long *)io_p2v(x)))
+#define davinci_writeb(v, a)    __raw_writeb(v, IO_ADDRESS(a))
+#define davinci_writew(v, a)    __raw_writew(v, IO_ADDRESS(a))
+#define davinci_writel(v, a)    __raw_writel(v, IO_ADDRESS(a))
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index 84ff77aeb738..17ca41dc2c53 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -11,7 +11,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 
 extern void davinci_watchdog_reset(void);
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index 5bb66b61c1a3..299515f70b8b 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -11,9 +11,9 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <asm/tlb.h>
-#include <asm/io.h>
 #include <asm/memory.h>
 
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 12ca9f29f847..38021af8359a 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -22,9 +22,9 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach/irq.h>
 
 #define IRQ_BIT(irq)            ((irq) & 0x1f)
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 720c48b9ee04..58754f066d5b 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -21,8 +21,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
@@ -70,9 +70,6 @@ void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
 {
         u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
 
-        if (id < 0)
-                return;
-
         mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
         if (enable)
                 mdctl |= 0x00000003;    /* Enable Module */
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index caf101e2cc62..3010f9971255 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -26,8 +26,8 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/serial.h>
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 206e80d41717..3b9a296b5c4b 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -15,8 +15,8 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/spinlock.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
new file mode 100644
index 000000000000..fe182a85159c
--- /dev/null
+++ b/arch/arm/mach-davinci/usb.c
@@ -0,0 +1,116 @@
+/*
+ * USB
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <linux/usb/musb.h>
+#include <linux/usb/otg.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+static struct musb_hdrc_eps_bits musb_eps[] = {
+        { "ep1_tx", 8, },
+        { "ep1_rx", 8, },
+        { "ep2_tx", 8, },
+        { "ep2_rx", 8, },
+        { "ep3_tx", 5, },
+        { "ep3_rx", 5, },
+        { "ep4_tx", 5, },
+        { "ep4_rx", 5, },
+};
+
+static struct musb_hdrc_config musb_config = {
+        .multipoint     = true,
+        .dyn_fifo       = true,
+        .soft_con       = true,
+        .dma            = true,
+
+        .num_eps        = 5,
+        .dma_channels   = 8,
+        .ram_bits       = 10,
+        .eps_bits       = musb_eps,
+};
+
+static struct musb_hdrc_platform_data usb_data = {
+#if defined(CONFIG_USB_MUSB_OTG)
+        /* OTG requires a Mini-AB connector */
+        .mode           = MUSB_OTG,
+#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
+        .mode           = MUSB_PERIPHERAL,
+#elif defined(CONFIG_USB_MUSB_HOST)
+        .mode           = MUSB_HOST,
+#endif
+        .config         = &musb_config,
+};
+
+static struct resource usb_resources[] = {
+        {
+                /* physical address */
+                .start          = DAVINCI_USB_OTG_BASE,
+                .end            = DAVINCI_USB_OTG_BASE + 0x5ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = IRQ_USBINT,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static u64 usb_dmamask = DMA_32BIT_MASK;
+
+static struct platform_device usb_dev = {
+        .name           = "musb_hdrc",
+        .id             = -1,
+        .dev = {
+                .platform_data          = &usb_data,
+                .dma_mask               = &usb_dmamask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+        },
+        .resource       = usb_resources,
+        .num_resources  = ARRAY_SIZE(usb_resources),
+};
+
+#ifdef CONFIG_USB_MUSB_OTG
+
+static struct otg_transceiver *xceiv;
+
+struct otg_transceiver *otg_get_transceiver(void)
+{
+        if (xceiv)
+                get_device(xceiv->dev);
+        return xceiv;
+}
+EXPORT_SYMBOL(otg_get_transceiver);
+
+int otg_set_transceiver(struct otg_transceiver *x)
+{
+        if (xceiv && x)
+                return -EBUSY;
+        xceiv = x;
+        return 0;
+}
+EXPORT_SYMBOL(otg_set_transceiver);
+
+#endif
+
+void __init setup_usb(unsigned mA, unsigned potpgt_msec)
+{
+        usb_data.power = mA / 2;
+        usb_data.potpgt = potpgt_msec / 2;
+        platform_device_register(&usb_dev);
+}
+
+#else
+
+void __init setup_usb(unsigned mA, unsigned potpgt_msec)
+{
+}
+
+#endif  /* CONFIG_USB_MUSB_HDRC */
+
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 65cc7c271917..c7bc7fbb11a6 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -14,10 +14,10 @@
 #include <linux/interrupt.h>
 #include <linux/serial_8250.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mach-ebsa110/io.c b/arch/arm/mach-ebsa110/io.c
index 53748f5462e9..c52e3047a7eb 100644
--- a/arch/arm/mach-ebsa110/io.c
+++ b/arch/arm/mach-ebsa110/io.c
@@ -23,9 +23,9 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/page.h>
 
 static void __iomem *__isamem_convert_addr(const volatile void __iomem *addr)
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index ea8549bfbef2..5a1b8c05c958 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -88,6 +88,20 @@ config MACH_TS72XX
           Say 'Y' here if you want your kernel to support the
           Technologic Systems TS-72xx board.
 
+choice
+        prompt "Select a UART for early kernel messages"
+
+config EP93XX_EARLY_UART1
+        bool "UART1"
+
+config EP93XX_EARLY_UART2
+        bool "UART2"
+
+config EP93XX_EARLY_UART3
+        bool "UART3"
+
+endchoice
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index aa1fb352fb8f..561db73ec1ae 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -18,7 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,36 +47,12 @@ static struct ep93xx_eth_data adssphere_eth_data = {
         .phy_id         = 1,
 };
 
-static struct resource adssphere_eth_resource[] = {
-        {
-                .start  = EP93XX_ETHERNET_PHYS_BASE,
-                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_EP93XX_ETHERNET,
-                .end    = IRQ_EP93XX_ETHERNET,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device adssphere_eth_device = {
-        .name           = "ep93xx-eth",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &adssphere_eth_data,
-        },
-        .num_resources  = 2,
-        .resource       = adssphere_eth_resource,
-};
-
 static void __init adssphere_init_machine(void)
 {
         ep93xx_init_devices();
         platform_device_register(&adssphere_flash);
 
-        memcpy(adssphere_eth_data.dev_addr,
-                (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
-        platform_device_register(&adssphere_eth_device);
+        ep93xx_register_eth(&adssphere_eth_data, 1);
 }
 
 MACHINE_START(ADSSPHERE, "ADS Sphere board")
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 6062e47f2043..8c9f2491dccc 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -15,9 +15,9 @@
 #include <linux/err.h>
 #include <linux/module.h>
 #include <linux/string.h>
+#include <linux/io.h>
 #include <asm/div64.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 struct clk {
         char            *name;
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index f99f43669392..de53f0be71b9 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -32,6 +32,7 @@
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
+#include <linux/io.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -41,7 +42,6 @@
 #include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
-#include <asm/io.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -157,7 +157,7 @@ static unsigned char gpio_int_type2[3];
 static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
 static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
 static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
-static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x5c };
+static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
 
 void ep93xx_gpio_update_int_params(unsigned port)
 {
@@ -192,8 +192,7 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
         for (i = 0; i < 8; i++) {
                 if (status & (1 << i)) {
                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
-                        desc = irq_desc + gpio_irq;
-                        desc_handle_irq(gpio_irq, desc);
+                        generic_handle_irq(gpio_irq);
                 }
         }
 
@@ -202,7 +201,7 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
                 if (status & (1 << i)) {
                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
                         desc = irq_desc + gpio_irq;
-                        desc_handle_irq(gpio_irq, desc);
+                        generic_handle_irq(gpio_irq);
                 }
         }
 }
@@ -217,7 +216,7 @@ static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
         int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
 
-        desc_handle_irq(gpio_irq, irq_desc + gpio_irq);
+        generic_handle_irq(gpio_irq);
 }
 
 static void ep93xx_gpio_irq_ack(unsigned int irq)
@@ -461,6 +460,41 @@ static struct platform_device ep93xx_ohci_device = {
         .resource       = ep93xx_ohci_resources,
 };
 
+static struct ep93xx_eth_data ep93xx_eth_data;
+
+static struct resource ep93xx_eth_resource[] = {
+        {
+                .start  = EP93XX_ETHERNET_PHYS_BASE,
+                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_EP93XX_ETHERNET,
+                .end    = IRQ_EP93XX_ETHERNET,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device ep93xx_eth_device = {
+        .name           = "ep93xx-eth",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ep93xx_eth_data,
+        },
+        .num_resources  = ARRAY_SIZE(ep93xx_eth_resource),
+        .resource       = ep93xx_eth_resource,
+};
+
+void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
+{
+        if (copy_addr) {
+                memcpy(data->dev_addr,
+                        (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
+        }
+
+        ep93xx_eth_data = *data;
+        platform_device_register(&ep93xx_eth_device);
+}
+
 extern void ep93xx_gpio_init(void);
 
 void __init ep93xx_init_devices(void)
diff --git a/arch/arm/mach-ep93xx/edb9302.c b/arch/arm/mach-ep93xx/edb9302.c
index 97550c0ad7b0..e4add5bdccfd 100644
--- a/arch/arm/mach-ep93xx/edb9302.c
+++ b/arch/arm/mach-ep93xx/edb9302.c
@@ -18,7 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -43,10 +43,16 @@ static struct platform_device edb9302_flash = {
         .resource       = &edb9302_flash_resource,
 };
 
+static struct ep93xx_eth_data edb9302_eth_data = {
+        .phy_id         = 1,
+};
+
 static void __init edb9302_init_machine(void)
 {
         ep93xx_init_devices();
         platform_device_register(&edb9302_flash);
+
+        ep93xx_register_eth(&edb9302_eth_data, 1);
 }
 
 MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
diff --git a/arch/arm/mach-ep93xx/edb9302a.c b/arch/arm/mach-ep93xx/edb9302a.c
index 99b01d44bf1c..02c4405afed7 100644
--- a/arch/arm/mach-ep93xx/edb9302a.c
+++ b/arch/arm/mach-ep93xx/edb9302a.c
@@ -18,7 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,36 +47,12 @@ static struct ep93xx_eth_data edb9302a_eth_data = {
         .phy_id                 = 1,
 };
 
-static struct resource edb9302a_eth_resource[] = {
-        {
-                .start  = EP93XX_ETHERNET_PHYS_BASE,
-                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_EP93XX_ETHERNET,
-                .end    = IRQ_EP93XX_ETHERNET,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device edb9302a_eth_device = {
-        .name           = "ep93xx-eth",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &edb9302a_eth_data,
-        },
-        .num_resources  = 2,
-        .resource       = edb9302a_eth_resource,
-};
-
 static void __init edb9302a_init_machine(void)
 {
         ep93xx_init_devices();
         platform_device_register(&edb9302a_flash);
 
-        memcpy(edb9302a_eth_data.dev_addr,
-                (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
-        platform_device_register(&edb9302a_eth_device);
+        ep93xx_register_eth(&edb9302a_eth_data, 1);
 }
 
 MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
diff --git a/arch/arm/mach-ep93xx/edb9307.c b/arch/arm/mach-ep93xx/edb9307.c
index 9fb72d01a36c..040edbd2ea05 100644
--- a/arch/arm/mach-ep93xx/edb9307.c
+++ b/arch/arm/mach-ep93xx/edb9307.c
@@ -18,7 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,36 +47,12 @@ static struct ep93xx_eth_data edb9307_eth_data = {
         .phy_id                 = 1,
 };
 
-static struct resource edb9307_eth_resource[] = {
-        {
-                .start  = EP93XX_ETHERNET_PHYS_BASE,
-                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_EP93XX_ETHERNET,
-                .end    = IRQ_EP93XX_ETHERNET,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device edb9307_eth_device = {
-        .name           = "ep93xx-eth",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &edb9307_eth_data,
-        },
-        .num_resources  = 2,
-        .resource       = edb9307_eth_resource,
-};
-
 static void __init edb9307_init_machine(void)
 {
         ep93xx_init_devices();
         platform_device_register(&edb9307_flash);
 
-        memcpy(edb9307_eth_data.dev_addr,
-                (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
-        platform_device_register(&edb9307_eth_device);
+        ep93xx_register_eth(&edb9307_eth_data, 1);
 }
 
 MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
diff --git a/arch/arm/mach-ep93xx/edb9312.c b/arch/arm/mach-ep93xx/edb9312.c
index 87267a574f5e..6853e302bc3a 100644
--- a/arch/arm/mach-ep93xx/edb9312.c
+++ b/arch/arm/mach-ep93xx/edb9312.c
@@ -19,7 +19,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -44,10 +44,16 @@ static struct platform_device edb9312_flash = {
         .resource       = &edb9312_flash_resource,
 };
 
+static struct ep93xx_eth_data edb9312_eth_data = {
+        .phy_id                 = 1,
+};
+
 static void __init edb9312_init_machine(void)
 {
         ep93xx_init_devices();
         platform_device_register(&edb9312_flash);
+
+        ep93xx_register_eth(&edb9312_eth_data, 1);
 }
 
 MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
diff --git a/arch/arm/mach-ep93xx/edb9315.c b/arch/arm/mach-ep93xx/edb9315.c
index 7e373950be4d..9469b350d253 100644
--- a/arch/arm/mach-ep93xx/edb9315.c
+++ b/arch/arm/mach-ep93xx/edb9315.c
@@ -18,7 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -43,10 +43,16 @@ static struct platform_device edb9315_flash = {
         .resource       = &edb9315_flash_resource,
 };
 
+static struct ep93xx_eth_data edb9315_eth_data = {
+        .phy_id                 = 1,
+};
+
 static void __init edb9315_init_machine(void)
 {
         ep93xx_init_devices();
         platform_device_register(&edb9315_flash);
+
+        ep93xx_register_eth(&edb9315_eth_data, 1);
 }
 
 MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
diff --git a/arch/arm/mach-ep93xx/edb9315a.c b/arch/arm/mach-ep93xx/edb9315a.c
index 08a7c9bfb689..584457ce7c80 100644
--- a/arch/arm/mach-ep93xx/edb9315a.c
+++ b/arch/arm/mach-ep93xx/edb9315a.c
@@ -18,7 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,36 +47,12 @@ static struct ep93xx_eth_data edb9315a_eth_data = {
         .phy_id                 = 1,
 };
 
-static struct resource edb9315a_eth_resource[] = {
-        {
-                .start  = EP93XX_ETHERNET_PHYS_BASE,
-                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_EP93XX_ETHERNET,
-                .end    = IRQ_EP93XX_ETHERNET,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device edb9315a_eth_device = {
-        .name           = "ep93xx-eth",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &edb9315a_eth_data,
-        },
-        .num_resources  = 2,
-        .resource       = edb9315a_eth_resource,
-};
-
 static void __init edb9315a_init_machine(void)
 {
         ep93xx_init_devices();
         platform_device_register(&edb9315a_flash);
 
-        memcpy(edb9315a_eth_data.dev_addr,
-                (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
-        platform_device_register(&edb9315a_eth_device);
+        ep93xx_register_eth(&edb9315a_eth_data, 1);
 }
 
 MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 9b41ec1f089e..035b24e31b64 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -18,7 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -44,36 +44,15 @@ static struct platform_device gesbc9312_flash = {
 };
 
 static struct ep93xx_eth_data gesbc9312_eth_data = {
-        .phy_id                 = 1,
-};
-
-static struct resource gesbc9312_eth_resource[] = {
-        {
-                .start  = EP93XX_ETHERNET_PHYS_BASE,
-                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_EP93XX_ETHERNET,
-                .end    = IRQ_EP93XX_ETHERNET,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device gesbc9312_eth_device = {
-        .name           = "ep93xx-eth",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &gesbc9312_eth_data,
-        },
-        .num_resources  = 2,
-        .resource       = gesbc9312_eth_resource,
+        .phy_id         = 1,
 };
 
 static void __init gesbc9312_init_machine(void)
 {
         ep93xx_init_devices();
         platform_device_register(&gesbc9312_flash);
-        platform_device_register(&gesbc9312_eth_device);
+
+        ep93xx_register_eth(&gesbc9312_eth_data, 0);
 }
 
 MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 0f3fb87ca4be..482cf3d2fbcd 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -16,9 +16,9 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/seq_file.h>
+#include <linux/io.h>
 
 #include <mach/ep93xx-regs.h>
-#include <asm/io.h>
 #include <asm/gpio.h>
 
 struct ep93xx_gpio_chip {
@@ -141,10 +141,10 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
         EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
         EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
-        EP93XX_GPIO_BANK("C", 0x30, 0x34, 40),
+        EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
         EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
         EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
-        EP93XX_GPIO_BANK("F", 0x08, 0x18, 16),
+        EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
         EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
         EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
 };
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 9f4458c8e070..22d6c9a6e4ca 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -6,6 +6,40 @@
 #define __ASM_ARCH_EP93XX_REGS_H
 
 /*
+ * EP93xx Physical Memory Map:
+ *
+ * The ASDO pin is sampled at system reset to select a synchronous or
+ * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
+ * the synchronous boot mode is selected.  When ASDO is "0" (i.e
+ * pulled-down) the asynchronous boot mode is selected.
+ *
+ * In synchronous boot mode nSDCE3 is decoded starting at physical address
+ * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
+ * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
+ * decoded at 0xf0000000.
+ *
+ * There is known errata for the EP93xx dealing with External Memory
+ * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
+ * Guidelines" for more information.  This document can be found at:
+ *
+ *      http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
+ */
+
+#define EP93XX_CS0_PHYS_BASE_ASYNC      0x00000000      /* ASDO Pin = 0 */
+#define EP93XX_SDCE3_PHYS_BASE_SYNC     0x00000000      /* ASDO Pin = 1 */
+#define EP93XX_CS1_PHYS_BASE            0x10000000
+#define EP93XX_CS2_PHYS_BASE            0x20000000
+#define EP93XX_CS3_PHYS_BASE            0x30000000
+#define EP93XX_PCMCIA_PHYS_BASE         0x40000000
+#define EP93XX_CS6_PHYS_BASE            0x60000000
+#define EP93XX_CS7_PHYS_BASE            0x70000000
+#define EP93XX_SDCE0_PHYS_BASE          0xc0000000
+#define EP93XX_SDCE1_PHYS_BASE          0xd0000000
+#define EP93XX_SDCE2_PHYS_BASE          0xe0000000
+#define EP93XX_SDCE3_PHYS_BASE_ASYNC    0xf0000000      /* ASDO Pin = 0 */
+#define EP93XX_CS0_PHYS_BASE_SYNC       0xf0000000      /* ASDO Pin = 1 */
+
+/*
  * EP93xx linux memory map:
  *
  * virt         phys            size
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index b5c182473f5d..db2489d3bda7 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -4,17 +4,17 @@
 
 #ifndef __ASSEMBLY__
 
-void ep93xx_map_io(void);
-void ep93xx_init_irq(void);
-void ep93xx_init_time(unsigned long);
-void ep93xx_init_devices(void);
-extern struct sys_timer ep93xx_timer;
-
 struct ep93xx_eth_data
 {
         unsigned char   dev_addr[6];
         unsigned char   phy_id;
 };
 
+void ep93xx_map_io(void);
+void ep93xx_init_irq(void);
+void ep93xx_init_time(unsigned long);
+void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
+void ep93xx_init_devices(void);
+extern struct sys_timer ep93xx_timer;
 
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
index 30b318aa1a1f..34ddec081c40 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
@@ -70,7 +70,7 @@
 
 
 #ifndef __ASSEMBLY__
-#include <asm/io.h>
+#include <linux/io.h>
 
 static inline int board_is_ts7200(void)
 {
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
index 1fd2f17de325..16026c2b1c8c 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -31,10 +31,19 @@ static void __raw_writel(unsigned int value, unsigned int ptr)
         *((volatile unsigned int *)ptr) = value;
 }
 
-
-#define PHYS_UART1_DATA         0x808c0000
-#define PHYS_UART1_FLAG         0x808c0018
-#define UART1_FLAG_TXFF         0x20
+#if defined(CONFIG_EP93XX_EARLY_UART1)
+#define UART_BASE               EP93XX_UART1_PHYS_BASE
+#elif defined(CONFIG_EP93XX_EARLY_UART2)
+#define UART_BASE               EP93XX_UART2_PHYS_BASE
+#elif defined(CONFIG_EP93XX_EARLY_UART3)
+#define UART_BASE               EP93XX_UART3_PHYS_BASE
+#else
+#define UART_BASE               EP93XX_UART1_PHYS_BASE
+#endif
+
+#define PHYS_UART_DATA          (UART_BASE + 0x00)
+#define PHYS_UART_FLAG          (UART_BASE + 0x18)
+#define UART_FLAG_TXFF          0x20
 
 static inline void putc(int c)
 {
@@ -42,11 +51,11 @@ static inline void putc(int c)
 
         for (i = 0; i < 1000; i++) {
                 /* Transmit fifo not full?  */
-                if (!(__raw_readb(PHYS_UART1_FLAG) & UART1_FLAG_TXFF))
+                if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
                         break;
         }
 
-        __raw_writeb(c, PHYS_UART1_DATA);
+        __raw_writeb(c, PHYS_UART_DATA);
 }
 
 static inline void flush(void)
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index de047a5c8112..c2197236b632 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -16,10 +16,9 @@
 #include <linux/mm.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
-
+#include <linux/io.h>
 #include <linux/mtd/physmap.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 
 #include <asm/mach/arch.h>
@@ -29,38 +28,9 @@ static struct ep93xx_eth_data micro9_eth_data = {
        .phy_id                 = 0x1f,
 };
 
-static struct resource micro9_eth_resource[] = {
-       {
-               .start  = EP93XX_ETHERNET_PHYS_BASE,
-               .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
-               .flags  = IORESOURCE_MEM,
-       }, {
-               .start  = IRQ_EP93XX_ETHERNET,
-               .end    = IRQ_EP93XX_ETHERNET,
-               .flags  = IORESOURCE_IRQ,
-       }
-};
-
-static struct platform_device micro9_eth_device = {
-       .name           = "ep93xx-eth",
-       .id             = -1,
-       .dev            = {
-               .platform_data  = &micro9_eth_data,
-       },
-       .num_resources = ARRAY_SIZE(micro9_eth_resource),
-       .resource       = micro9_eth_resource,
-};
-
-static void __init micro9_eth_init(void)
-{
-       memcpy(micro9_eth_data.dev_addr,
-               (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
-       platform_device_register(&micro9_eth_device);
-}
-
 static void __init micro9_init(void)
 {
-       micro9_eth_init();
+        ep93xx_register_eth(&micro9_eth_data, 1);
 }
 
 /*
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index c3cbff126d0c..b4aa4c054276 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -19,7 +19,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <linux/m48t86.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -161,28 +161,6 @@ static struct ep93xx_eth_data ts72xx_eth_data = {
         .phy_id                 = 1,
 };
 
-static struct resource ts72xx_eth_resource[] = {
-        {
-                .start  = EP93XX_ETHERNET_PHYS_BASE,
-                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_EP93XX_ETHERNET,
-                .end    = IRQ_EP93XX_ETHERNET,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static struct platform_device ts72xx_eth_device = {
-        .name           = "ep93xx-eth",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &ts72xx_eth_data,
-        },
-        .num_resources  = 2,
-        .resource       = ts72xx_eth_resource,
-};
-
 static void __init ts72xx_init_machine(void)
 {
         ep93xx_init_devices();
@@ -190,9 +168,7 @@ static void __init ts72xx_init_machine(void)
                 platform_device_register(&ts72xx_flash);
         platform_device_register(&ts72xx_rtc_device);
 
-        memcpy(ts72xx_eth_data.dev_addr,
-                (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
-        platform_device_register(&ts72xx_eth_device);
+        ep93xx_register_eth(&ts72xx_eth_data, 1);
 }
 
 MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index c261472208cb..6a5b437ab86f 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -9,9 +9,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/screen_info.h>
+#include <linux/io.h>
 
 #include <asm/hardware/dec21285.h>
-#include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index b08ab507c052..818014e09f4a 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -13,11 +13,11 @@
 #include <linux/ioport.h>
 #include <linux/list.h>
 #include <linux/init.h>
+#include <linux/io.h>
  
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/hardware/dec21285.h>
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index d0dc51e81338..d4c1e526f59c 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -16,8 +16,8 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-footbridge/dma.c b/arch/arm/mach-footbridge/dma.c
index 1f9b09b8ed88..b653e9cfa3f7 100644
--- a/arch/arm/mach-footbridge/dma.c
+++ b/arch/arm/mach-footbridge/dma.c
@@ -11,9 +11,9 @@
  *                      ISA DMA controllers.
  */
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <asm/dma.h>
-#include <asm/io.h>
 #include <asm/scatterlist.h>
 
 #include <asm/mach/dma.h>
diff --git a/arch/arm/mach-footbridge/include/mach/memory.h b/arch/arm/mach-footbridge/include/mach/memory.h
index e9cae99dd1f9..6ae2f1a07ab9 100644
--- a/arch/arm/mach-footbridge/include/mach/memory.h
+++ b/arch/arm/mach-footbridge/include/mach/memory.h
@@ -42,10 +42,6 @@ extern unsigned long __bus_to_virt(unsigned long);
 
 #endif
 
-/* Task size and page offset at 3GB */
-#define TASK_SIZE               UL(0xbf000000)
-#define PAGE_OFFSET             UL(0xc0000000)
-
 /*
  * Cache flushing area.
  */
@@ -56,12 +52,6 @@ extern unsigned long __bus_to_virt(unsigned long);
  */
 #define PHYS_OFFSET             UL(0x00000000)
 
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
-
 #define FLUSH_BASE_PHYS         0x50000000
 
 #endif
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h
index 01c9f407f498..2db7f36bd6ca 100644
--- a/arch/arm/mach-footbridge/include/mach/system.h
+++ b/arch/arm/mach-footbridge/include/mach/system.h
@@ -7,8 +7,8 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/io.h>
 #include <asm/hardware/dec21285.h>
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 7132e522c366..54fec9ae28b9 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -18,13 +18,13 @@
 #include <linux/interrupt.h>
 #include <linux/list.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
 #include <asm/hardware/dec21285.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/mach-types.h>
 
 static void isa_mask_pic_lo_irq(unsigned int irq)
@@ -94,8 +94,7 @@ isa_irq_handler(unsigned int irq, struct irq_desc *desc)
                 return;
         }
 
-        desc = irq_desc + isa_irq;
-        desc_handle_irq(isa_irq, desc);
+        generic_handle_irq(isa_irq);
 }
 
 static struct irqaction irq_cascade = {
diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c
index a764e01d3573..0c8390082fa8 100644
--- a/arch/arm/mach-footbridge/isa-timer.c
+++ b/arch/arm/mach-footbridge/isa-timer.c
@@ -7,8 +7,8 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index a1f381c64a30..00b0ddcac283 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -10,9 +10,9 @@
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <asm/hardware/dec21285.h>
-#include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-footbridge/time.c b/arch/arm/mach-footbridge/time.c
index 004819ea85c8..cd1b54ff9fe2 100644
--- a/arch/arm/mach-footbridge/time.c
+++ b/arch/arm/mach-footbridge/time.c
@@ -22,9 +22,9 @@
 #include <linux/sched.h>
 #include <linux/mc146818rtc.h>
 #include <linux/bcd.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <asm/mach/time.h>
 #include "common.h"
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index b5f9741ae13c..7a2614828217 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -18,11 +18,11 @@
 #include <linux/mman.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
 
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/dma.h>
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
@@ -104,14 +104,12 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq,
                  struct irq_desc *desc)
 {
         IRQDBG("%s irq: %d\n", __func__, irq);
-        desc = irq_desc + irq;
         while (mask) {
                 if (mask & 1) {
                         IRQDBG("handling irq %d\n", irq);
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
                 }
                 irq++;
-                desc++;
                 mask >>= 1;
         }
 }
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index 53e1f62f2e79..fd33a19c813a 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -120,12 +120,10 @@ h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
 
         mask >>= 1;
         irq = IRQ_TIMER1;
-        desc = irq_desc + irq;
         while (mask) {
                 if (mask & 1)
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
                 irq++;
-                desc++;
                 mask >>= 1;
         }
 }
diff --git a/arch/arm/mach-imx/clock.c b/arch/arm/mach-imx/clock.c
index 4b4230db3765..7ec60fc91565 100644
--- a/arch/arm/mach-imx/clock.c
+++ b/arch/arm/mach-imx/clock.c
@@ -21,8 +21,8 @@
 #include <linux/list.h>
 #include <linux/math64.h>
 #include <linux/err.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/imx-regs.h>
 
 /*
diff --git a/arch/arm/mach-imx/include/mach/irqs.h b/arch/arm/mach-imx/include/mach/irqs.h
index eb8d5bd05d56..67812c5ac1f9 100644
--- a/arch/arm/mach-imx/include/mach/irqs.h
+++ b/arch/arm/mach-imx/include/mach/irqs.h
@@ -111,6 +111,11 @@
 /* decode irq number to use with IMR(x), ISR(x) and friends */
 #define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5)
 
+/* all normal IRQs can be FIQs */
+#define FIQ_START       0
+/* switch betwean IRQ and FIQ */
+extern int imx_set_irq_fiq(unsigned int irq, unsigned int type);
+
 #define NR_IRQS (IRQ_GPIOD(32) + 1)
 #define IRQ_GPIO(x)
 #endif
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index 798f221eb3b7..531b95deadc0 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -26,20 +26,17 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/timer.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
 /*
  *
  * We simply use the ENABLE DISABLE registers inside of the IMX
- * to turn on/off specific interrupts.  FIXME- We should
- * also add support for the accelerated interrupt controller
- * by putting offets to irq jump code in the appropriate
- * places.
+ * to turn on/off specific interrupts.
  *
  */
 
@@ -102,6 +99,28 @@ imx_unmask_irq(unsigned int irq)
         __raw_writel(irq, IMX_AITC_INTENNUM);
 }
 
+#ifdef CONFIG_FIQ
+int imx_set_irq_fiq(unsigned int irq, unsigned int type)
+{
+        unsigned int irqt;
+
+        if (irq >= IMX_IRQS)
+                return -EINVAL;
+
+        if (irq < IMX_IRQS / 2) {
+                irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq);
+                __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL);
+        } else {
+                irq -= IMX_IRQS / 2;
+                irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq);
+                __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH);
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_set_irq_fiq);
+#endif /* CONFIG_FIQ */
+
 static int
 imx_gpio_irq_type(unsigned int _irq, unsigned int type)
 {
@@ -182,14 +201,12 @@ static void
 imx_gpio_handler(unsigned int mask, unsigned int irq,
                  struct irq_desc *desc)
 {
-        desc = irq_desc + irq;
         while (mask) {
                 if (mask & 1) {
                         DEBUG_IRQ("handling irq %d\n", irq);
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
                 }
                 irq++;
-                desc++;
                 mask >>= 1;
         }
 }
@@ -286,4 +303,9 @@ imx_init_irq(void)
 
         /* Release masking of interrupts according to priority */
         __raw_writel(-1, IMX_AITC_NIMASK);
+
+#ifdef CONFIG_FIQ
+        /* Initialize FIQ */
+        init_FIQ();
+#endif
 }
diff --git a/arch/arm/mach-imx/leds-mx1ads.c b/arch/arm/mach-imx/leds-mx1ads.c
index af81621f689b..1d48f2762cbc 100644
--- a/arch/arm/mach-imx/leds-mx1ads.c
+++ b/arch/arm/mach-imx/leds-mx1ads.c
@@ -13,9 +13,9 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/system.h>
-#include <asm/io.h>
 #include <asm/leds.h>
 #include "leds.h"
 
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 08be3875c59e..a11765f5f23b 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -18,9 +18,9 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 8bacf6d4d097..595b7392ee4e 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -19,10 +19,10 @@
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/hardware/arm_timer.h>
 #include <mach/cm.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c
index 7c49d55e6b27..e4f72d202cc0 100644
--- a/arch/arm/mach-integrator/cpu.c
+++ b/arch/arm/mach-integrator/cpu.c
@@ -17,9 +17,9 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/icst525.h>
 
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 3c8383dbe9e6..172299a78302 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -20,8 +20,8 @@
 #include <linux/mm.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/hardware/icst525.h>
 #include <mach/lm.h>
 #include <mach/impd1.h>
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 6e472b5f8f26..8138a7e24562 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -27,9 +27,9 @@
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/kmi.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/param.h>          /* HZ */
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 6b99e9c258bd..88026ccd5ac9 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -19,9 +19,9 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/kmi.h>
 #include <linux/amba/clcd.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -217,8 +217,7 @@ sic_handle_irq(unsigned int irq, struct irq_desc *desc)
 
                 irq += IRQ_SIC_START;
 
-                desc = irq_desc + irq;
-                desc_handle_irq(irq, desc);
+                generic_handle_irq(irq);
         } while (status);
 }
 
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 7bc6881434ec..8dcc823f4135 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -24,9 +24,9 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/spinlock.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/system.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 9f2b1ea8fb20..f1d72b225450 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,9 +27,9 @@
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index e8b59d8f1bb9..b82602d529bf 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -7,9 +7,6 @@
  * Physical DRAM offset.
  */
 #define PHYS_OFFSET     UL(0x00000000)
-#define TASK_SIZE       UL(0x3f000000)
-#define PAGE_OFFSET     UL(0x40000000)
-#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
 
 #ifndef __ASSEMBLY__
 
@@ -29,32 +26,52 @@
 
 /* RAM has 1:1 mapping on the PCIe/x Busses */
 #define __virt_to_bus(x)        (__virt_to_phys(x))
-#define __bus_to_virt(x)    (__phys_to_virt(x))
+#define __bus_to_virt(x)        (__phys_to_virt(x))
 
-#define virt_to_lbus(x)                                            \
-(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) &&                  \
-((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ?                       \
-((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
-((x) - PAGE_OFFSET + PHYS_OFFSET))
+static inline dma_addr_t __virt_to_lbus(unsigned long x)
+{
+        return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
+}
 
-#define lbus_to_virt(x)                                            \
-(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
-((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
-((x) - PHYS_OFFSET + PAGE_OFFSET))
+static inline unsigned long __lbus_to_virt(dma_addr_t x)
+{
+        return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
+}
+
+#define __is_lbus_dma(a)                                \
+        ((a) >= IOP13XX_PMMR_P_START && (a) < IOP13XX_PMMR_P_END)
+
+#define __is_lbus_virt(a)                               \
+        ((a) >= IOP13XX_PMMR_V_START && (a) < IOP13XX_PMMR_V_END)
 
 /* Device is an lbus device if it is on the platform bus of the IOP13XX */
-#define is_lbus_device(dev) (dev &&\
-                             (strncmp(dev->bus->name, "platform", 8) == 0))
+#define is_lbus_device(dev)                             \
+        (dev && strncmp(dev->bus->name, "platform", 8) == 0)
 
-#define __arch_page_to_dma(dev, page)                                   \
-({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
-(dma_addr_t)__virt_to_bus(page_address(page));})
+#define __arch_dma_to_virt(dev, addr)                                   \
+        ({                                                              \
+                unsigned long __virt;                                   \
+                dma_addr_t __dma = addr;                                \
+                if (is_lbus_device(dev) && __is_lbus_dma(__dma))        \
+                        __virt = __lbus_to_virt(__dma);                 \
+                else                                                    \
+                        __virt = __bus_to_virt(__dma);                  \
+                (void *)__virt;                                         \
+        })
 
-#define __arch_dma_to_virt(dev, addr) \
-({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
+#define __arch_virt_to_dma(dev, addr)                                   \
+        ({                                                              \
+                unsigned long __virt = (unsigned long)addr;             \
+                dma_addr_t __dma;                                       \
+                if (is_lbus_device(dev) && __is_lbus_virt(__virt))      \
+                        __dma = __virt_to_lbus(__virt);                 \
+                else                                                    \
+                        __dma = __virt_to_bus(__virt);                  \
+                __dma;                                                  \
+        })
 
-#define __arch_virt_to_dma(dev, addr) \
-({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
+#define __arch_page_to_dma(dev, page)                                   \
+        __arch_virt_to_dma(dev, page_address(page))
 
 #endif /* CONFIG_ARCH_IOP13XX */
 #endif /* !ASSEMBLY */
diff --git a/arch/arm/mach-iop13xx/include/mach/pci.h b/arch/arm/mach-iop13xx/include/mach/pci.h
index 17b5515af8b1..59f42b535572 100644
--- a/arch/arm/mach-iop13xx/include/mach/pci.h
+++ b/arch/arm/mach-iop13xx/include/mach/pci.h
@@ -1,7 +1,7 @@
 #ifndef _IOP13XX_PCI_H_
 #define _IOP13XX_PCI_H_
+#include <linux/io.h>
 #include <mach/irqs.h>
-#include <asm/io.h>
 
 struct pci_sys_data;
 struct hw_pci;
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 26cfa318142c..529580997814 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -18,8 +18,8 @@
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 void * __iomem __iop13xx_io(unsigned long io_addr)
 {
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index 63ef1124ca5c..f34b0ed80630 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -110,8 +110,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
                 do {
                         j = find_first_bit(&status, 32);
                         (write_imipr[i])(1 << j); /* write back to clear bit */
-                        desc = irq_desc + IRQ_IOP13XX_MSI_0 + j + (32*i);
-                        desc_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i), desc);
+                        generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i));
                         status = (read_imipr[i])();
                 } while (status);
         }
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index b17ccc8cb471..cfd4d2e6dacd 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -18,13 +18,13 @@
  */
 
 #include <linux/serial_8250.h>
+#include <linux/io.h>
 #ifdef CONFIG_MTD_PHYSMAP
 #include <linux/mtd/physmap.h>
 #endif
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/hardware/iop_adma.h>
 
 #define IOP13XX_UART_XTAL 33334000
diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c
index 2476347ea62f..c6af1e1bee32 100644
--- a/arch/arm/mach-iop13xx/tpmi.c
+++ b/arch/arm/mach-iop13xx/tpmi.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 45d61276d233..a9c2dfdb2507 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -25,8 +25,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 082818aaa205..dd1cd9904518 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -26,8 +26,9 @@
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
+#include <asm/cputype.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -49,8 +50,7 @@ static int force_ep80219;
 
 static int is_80219(void)
 {
-        extern int processor_id;
-        return !!((processor_id & 0xffffffe0) == 0x69052e20);
+        return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
 }
 
 static int is_ep80219(void)
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index d735539808b4..fbe27798759d 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -23,8 +23,8 @@
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 3173f9c5835d..d2e427899729 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -30,8 +30,8 @@
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
 #include <linux/reboot.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index c7d99f9fafed..d51e10cddf20 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -22,8 +22,8 @@
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index af616c5f4fb2..92fb44cdbcad 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -22,8 +22,8 @@
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
index 8c21870fa808..cdae24e46eea 100644
--- a/arch/arm/mach-iop33x/uart.c
+++ b/arch/arm/mach-iop33x/uart.c
@@ -17,7 +17,7 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index a6a4f93085fd..babb22597163 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -84,64 +84,57 @@ static struct map_desc ixp2000_io_desc[] __initdata = {
                 .virtual        = IXP2000_CAP_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
                 .length         = IXP2000_CAP_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = IXP2000_INTCTL_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
                 .length         = IXP2000_INTCTL_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
                 .length         = IXP2000_PCI_CREG_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
                 .length         = IXP2000_PCI_CSR_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = IXP2000_MSF_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
                 .length         = IXP2000_MSF_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = IXP2000_SCRATCH_RING_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
                 .length         = IXP2000_SCRATCH_RING_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = IXP2000_SRAM0_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
                 .length         = IXP2000_SRAM0_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_IO_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
                 .length         = IXP2000_PCI_IO_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
                 .length         = IXP2000_PCI_CFG0_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
                 .length         = IXP2000_PCI_CFG1_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }
 };
 
 void __init ixp2000_map_io(void)
 {
-        /*
-         * On IXP2400 CPUs we need to use MT_DEVICE_IXP2000 so that
-         * XCB=101 (to avoid triggering erratum #66), and given that
-         * this mode speeds up I/O accesses and we have write buffer
-         * flushes in the right places anyway, it doesn't hurt to use
-         * XCB=101 for all IXP2000s.
-         */
         iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
 
         /* Set slowport to 8-bit mode.  */
@@ -311,8 +304,7 @@ static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
                    
         for (i = 0; i <= 7; i++) {
                 if (status & (1<<i)) {
-                        desc = irq_desc + i + IRQ_IXP2000_GPIO0;
-                        desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc);
+                        generic_handle_irq(i + IRQ_IXP2000_GPIO0);
                 }
         }
 }
@@ -404,8 +396,7 @@ static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         for(i = 31; i >= 0; i--) {
                 if(status & (1 << i)) {
-                        desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
-                        desc_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc);
+                        generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
                 }
         }
 }
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index c62ed655c1a7..c84dfac13882 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -32,8 +32,8 @@
 #include <linux/tty.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -70,17 +70,17 @@ static struct map_desc enp2611_io_desc[] __initdata = {
                 .virtual        = ENP2611_CALEB_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
                 .length         = ENP2611_CALEB_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = ENP2611_PM3386_0_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
                 .length         = ENP2611_PM3386_0_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }, {
                 .virtual        = ENP2611_PM3386_1_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
                 .length         = ENP2611_PM3386_1_SIZE,
-                .type           = MT_DEVICE_IXP2000,
+                .type           = MT_DEVICE,
         }
 };
 
diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
index 19d80379a3e3..822f63f2f4a2 100644
--- a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
+++ b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
@@ -41,13 +41,7 @@
  * Most of the registers are clumped in 4K regions spread throughout
  * the 0xc0000000 -> 0xc0100000 address range, but we just map in
  * the whole range using a single 1 MB section instead of small
- * 4K pages.  This has two advantages for us:
- *
- * 1) We use only one TLB entry for large number of on-chip I/O devices.
- *
- * 2) We can easily set the Section attributes to XCB=101 on the IXP2400
- *    as required per erratum #66.  We accomplish this by using a
- *    new MT_IXP2000_DEVICE memory type with the bits set as required.
+ * 4K pages.
  *
  * CAP stands for CSR Access Proxy.
  *
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index c673b9ef9f69..4467c4224d73 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -25,8 +25,8 @@
 #include <linux/ioport.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index 6715b50829a6..94f68ba9ea50 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -25,8 +25,8 @@
 #include <linux/ioport.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 5a781fd9757a..b0653a87159a 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -25,8 +25,8 @@
 #include <linux/ioport.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -129,10 +129,8 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         for(i = 0; i < board_irq_count; i++) {
                 if(ex_interrupt & (1 << i))  {
-                        struct irq_desc *cpld_desc;
                         int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
-                        cpld_desc = irq_desc + cpld_irq;
-                        desc_handle_irq(cpld_irq, cpld_desc);
+                        generic_handle_irq(cpld_irq);
                 }
         }
 
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 78a2341dee2c..4a12327a09a3 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -30,8 +30,8 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -79,10 +79,8 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
                 if (ex_interrupt & (1 << i)) {
-                        struct irq_desc *cpld_desc;
                         int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
-                        cpld_desc = irq_desc + cpld_irq;
-                        desc_handle_irq(cpld_irq, cpld_desc);
+                        generic_handle_irq(cpld_irq);
                 }
         }
 
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 03d916fbe531..60e9fd08ab80 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -24,8 +24,8 @@
 #include <linux/ioport.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 68b4ac5b2481..aa4c4420ff3d 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -253,7 +253,6 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc)
 {
         u32 pci_interrupt;
         unsigned int irqno;
-        struct irq_desc *int_desc;
 
         pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
 
@@ -268,8 +267,7 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc)
                 BUG();
         }
 
-        int_desc = irq_desc + irqno;
-        desc_handle_irq(irqno, int_desc);
+        generic_handle_irq(irqno);
 
         desc->chip->unmask(irq);
 }
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index b6e0bfa44df9..f1b124a709ab 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -68,11 +68,9 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
 
         for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
                 if (ex_interrupt & (1 << i)) {
-                        struct irq_desc *cpld_desc;
                         int cpld_irq =
                                 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
-                        cpld_desc = irq_desc + cpld_irq;
-                        desc_handle_irq(cpld_irq, cpld_desc);
+                        generic_handle_irq(cpld_irq);
                 }
         }
 
@@ -105,11 +103,9 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
 
         for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
                 if (ex_interrupt & (1 << i)) {
-                        struct irq_desc *cpld_desc;
                         int cpld_irq =
                                 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
-                        cpld_desc = irq_desc + cpld_irq;
-                        desc_handle_irq(cpld_irq, cpld_desc);
+                        generic_handle_irq(cpld_irq);
                 }
         }
 
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 701d60aa0efd..59022becb134 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -25,8 +25,8 @@
 #include <linux/ioport.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 192538a04575..d816c51320c7 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -25,9 +25,10 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/device.h>
+#include <linux/io.h>
 #include <asm/dma-mapping.h>
 
-#include <asm/io.h>
+#include <asm/cputype.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 #include <asm/system.h>
@@ -366,15 +367,13 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
 
 void __init ixp4xx_pci_preinit(void)
 {  
-        unsigned long processor_id;
-
-        asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
+        unsigned long cpuid = read_cpuid_id();
 
         /*
          * Determine which PCI read method to use.
          * Rev 0 IXP425 requires workaround.
          */
-        if (!(processor_id & 0xf) && cpu_is_ixp42x()) {
+        if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
                 printk("PCI: IXP42x A0 silicon detected - "
                         "PCI Non-Prefetch Workaround Enabled\n");
                 ixp4xx_pci_read = ixp4xx_pci_read_errata;
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 58bd2842a6f1..7766f469456b 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -28,11 +28,11 @@
 #include <linux/timex.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/io.h>
 
 #include <mach/udc.h>
 #include <mach/hardware.h>
 #include <asm/uaccess.h>
-#include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 501dfdcc39fe..e7c6386782ed 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -23,11 +23,11 @@
 #include <linux/reboot.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
+#include <linux/io.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
-#include <asm/io.h>
 #include <asm/gpio.h>
 
 static struct flash_platform_data fsg_flash_data = {
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
index ff8aa2393bf9..51bd69c46d94 100644
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -14,18 +14,19 @@
 #ifndef __ASM_ARCH_CPU_H__
 #define __ASM_ARCH_CPU_H__
 
-extern unsigned int processor_id;
+#include <asm/cputype.h>
+
 /* Processor id value in CP15 Register 0 */
 #define IXP425_PROCESSOR_ID_VALUE       0x690541c0
 #define IXP435_PROCESSOR_ID_VALUE       0x69054040
 #define IXP465_PROCESSOR_ID_VALUE       0x69054200
 #define IXP4XX_PROCESSOR_ID_MASK        0xfffffff0
 
-#define cpu_is_ixp42x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+#define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
                           IXP425_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp43x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+#define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
                           IXP435_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+#define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
                           IXP465_PROCESSOR_ID_VALUE)
 
 static inline u32 ixp4xx_read_feature_bits(void)
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 9b2d2ec14c80..f4a0c1bc1331 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -20,6 +20,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/delay.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -29,7 +30,6 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
-#include <asm/delay.h>
 
 static struct flash_platform_data ixdp425_flash_data = {
         .map_name       = "cfi_probe",
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 84b5e62a9c0a..0acd95ecf27e 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -28,11 +28,11 @@
 #include <linux/reboot.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
+#include <linux/io.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
-#include <asm/io.h>
 #include <asm/gpio.h>
 
 static struct flash_platform_data nas100d_flash_data = {
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index a48a6655b887..bc9d920ae54f 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -25,12 +25,12 @@
 #include <linux/reboot.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
+#include <linux/io.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/time.h>
-#include <asm/io.h>
 #include <asm/gpio.h>
 
 static struct flash_platform_data nslu2_flash_data = {
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index c79f492072f9..5db4f0bbe5ee 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -48,6 +48,7 @@
 
 
 struct mbus_dram_target_info kirkwood_mbus_dram_info;
+static int __initdata win_alloc_count;
 
 static int __init cpu_win_can_remap(int win)
 {
@@ -111,6 +112,8 @@ void __init kirkwood_setup_cpu_mbus(void)
         setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
                       TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
+        win_alloc_count = 3;
+
         /*
          * Setup MBUS dram target info.
          */
@@ -137,3 +140,8 @@ void __init kirkwood_setup_cpu_mbus(void)
         }
         kirkwood_mbus_dram_info.num_cs = cs;
 }
+
+void __init kirkwood_setup_sram_win(u32 base, u32 size)
+{
+        setup_cpu_win(win_alloc_count++, base, size, 0x03, 0x00, -1);
+}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 189f16f3619d..85cad05d8c5b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -98,7 +98,6 @@ void __init kirkwood_ehci_init(void)
  * GE00
  ****************************************************************************/
 struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
-        .t_clk          = KIRKWOOD_TCLK,
         .dram           = &kirkwood_mbus_dram_info,
 };
 
@@ -108,6 +107,11 @@ static struct resource kirkwood_ge00_shared_resources[] = {
                 .start  = GE00_PHYS_BASE + 0x2000,
                 .end    = GE00_PHYS_BASE + 0x3fff,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "ge00 err irq",
+                .start  = IRQ_KIRKWOOD_GE00_ERR,
+                .end    = IRQ_KIRKWOOD_GE00_ERR,
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -117,7 +121,7 @@ static struct platform_device kirkwood_ge00_shared = {
         .dev            = {
                 .platform_data  = &kirkwood_ge00_shared_data,
         },
-        .num_resources  = 1,
+        .num_resources  = ARRAY_SIZE(kirkwood_ge00_shared_resources),
         .resource       = kirkwood_ge00_shared_resources,
 };
 
@@ -201,7 +205,6 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
  * SPI
  ****************************************************************************/
 static struct orion_spi_info kirkwood_spi_plat_data = {
-        .tclk           = KIRKWOOD_TCLK,
 };
 
 static struct resource kirkwood_spi_resources[] = {
@@ -239,7 +242,7 @@ static struct plat_serial8250_port kirkwood_uart0_data[] = {
                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = KIRKWOOD_TCLK,
+                .uartclk        = 0,
         }, {
         },
 };
@@ -283,7 +286,7 @@ static struct plat_serial8250_port kirkwood_uart1_data[] = {
                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = KIRKWOOD_TCLK,
+                .uartclk        = 0,
         }, {
         },
 };
@@ -525,9 +528,23 @@ void __init kirkwood_xor1_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+int kirkwood_tclk;
+
+int __init kirkwood_find_tclk(void)
+{
+        u32 dev, rev;
+
+        kirkwood_pcie_id(&dev, &rev);
+        if (dev == MV88F6281_DEV_ID && rev == MV88F6281_REV_A0)
+                return 200000000;
+
+        return 166666667;
+}
+
 static void kirkwood_timer_init(void)
 {
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, KIRKWOOD_TCLK);
+        kirkwood_tclk = kirkwood_find_tclk();
+        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 }
 
 struct sys_timer kirkwood_timer = {
@@ -538,33 +555,62 @@ struct sys_timer kirkwood_timer = {
 /*****************************************************************************
  * General
  ****************************************************************************/
+/*
+ * Identify device ID and revision.
+ */
 static char * __init kirkwood_id(void)
 {
-        switch (readl(DEVICE_ID) & 0x3) {
-        case 0:
-                return "88F6180";
-        case 1:
-                return "88F6192";
-        case 2:
-                return "88F6281";
+        u32 dev, rev;
+
+        kirkwood_pcie_id(&dev, &rev);
+
+        if (dev == MV88F6281_DEV_ID) {
+                if (rev == MV88F6281_REV_Z0)
+                        return "MV88F6281-Z0";
+                else if (rev == MV88F6281_REV_A0)
+                        return "MV88F6281-A0";
+                else
+                        return "MV88F6281-Rev-Unsupported";
+        } else if (dev == MV88F6192_DEV_ID) {
+                if (rev == MV88F6192_REV_Z0)
+                        return "MV88F6192-Z0";
+                else if (rev == MV88F6192_REV_A0)
+                        return "MV88F6192-A0";
+                else
+                        return "MV88F6192-Rev-Unsupported";
+        } else if (dev == MV88F6180_DEV_ID) {
+                if (rev == MV88F6180_REV_A0)
+                        return "MV88F6180-Rev-A0";
+                else
+                        return "MV88F6180-Rev-Unsupported";
+        } else {
+                return "Device-Unknown";
         }
-
-        return "unknown 88F6000 variant";
 }
 
-static int __init is_l2_writethrough(void)
+static void __init kirkwood_l2_init(void)
 {
-        return !!(readl(L2_CONFIG_REG) & L2_WRITETHROUGH);
+#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
+        writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
+        feroceon_l2_init(1);
+#else
+        writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
+        feroceon_l2_init(0);
+#endif
 }
 
 void __init kirkwood_init(void)
 {
         printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
-                kirkwood_id(), KIRKWOOD_TCLK);
+                kirkwood_id(), kirkwood_tclk);
+        kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
+        kirkwood_spi_plat_data.tclk = kirkwood_tclk;
+        kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
+        kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
 
         kirkwood_setup_cpu_mbus();
 
 #ifdef CONFIG_CACHE_FEROCEON_L2
-        feroceon_l2_init(is_l2_writethrough());
+        kirkwood_l2_init();
 #endif
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 69cd113af03a..8fa0f6a27635 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -23,10 +23,9 @@ void kirkwood_init_irq(void);
 
 extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
 void kirkwood_setup_cpu_mbus(void);
-void kirkwood_setup_pcie_io_win(int window, u32 base, u32 size,
-                                int maj, int min);
-void kirkwood_setup_pcie_mem_win(int window, u32 base, u32 size,
-                                 int maj, int min);
+void kirkwood_setup_sram_win(u32 base, u32 size);
+
+void kirkwood_pcie_id(u32 *dev, u32 *rev);
 
 void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 610fb24d8ae2..a14c2948c62a 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -25,7 +25,7 @@
 #include "common.h"
 
 static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
-        .phy_addr       = 8,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
 static struct mv_sata_platform_data db88f6281_sata_data = {
@@ -44,7 +44,6 @@ static void __init db88f6281_init(void)
         kirkwood_rtc_init();
         kirkwood_sata_init(&db88f6281_sata_data);
         kirkwood_uart0_init();
-        kirkwood_uart1_init();
 }
 
 static int __init db88f6281_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 6fd05838c72d..ffab89f21c11 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -50,6 +50,7 @@
 #define IRQ_KIRKWOOD_GPIO_HIGH_0_7      39
 #define IRQ_KIRKWOOD_GPIO_HIGH_8_15     40
 #define IRQ_KIRKWOOD_GPIO_HIGH_16_23    41
+#define IRQ_KIRKWOOD_GE00_ERR   46
 
 /*
  * KIRKWOOD General Purpose Pins
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 5c69992295e8..eae42406fd86 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -68,6 +68,20 @@
 #define   L2_WRITETHROUGH       0x00000010
 
 /*
+ * Supported devices and revisions.
+ */
+#define MV88F6281_DEV_ID        0x6281
+#define MV88F6281_REV_Z0        0
+#define MV88F6281_REV_A0        2
+
+#define MV88F6192_DEV_ID        0x6192
+#define MV88F6192_REV_Z0        0
+#define MV88F6192_REV_A0        2
+
+#define MV88F6180_DEV_ID        0x6180
+#define MV88F6180_REV_A0        2
+
+/*
  * Register Map
  */
 #define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
diff --git a/arch/arm/mach-kirkwood/include/mach/timex.h b/arch/arm/mach-kirkwood/include/mach/timex.h
index f77ef4a32c5f..c923cd169b9c 100644
--- a/arch/arm/mach-kirkwood/include/mach/timex.h
+++ b/arch/arm/mach-kirkwood/include/mach/timex.h
@@ -8,4 +8,3 @@
 
 #define CLOCK_TICK_RATE         (100 * HZ)
 
-#define KIRKWOOD_TCLK           166666667
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 2195fa31f6b7..f6b08f207c89 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,6 +18,12 @@
 
 #define PCIE_BASE       ((void __iomem *)PCIE_VIRT_BASE)
 
+void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+{
+        *dev = orion_pcie_dev_id(PCIE_BASE);
+        *rev = orion_pcie_rev(PCIE_BASE);
+}
+
 static int pcie_valid_config(int bus, int dev)
 {
         /*
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index a3012d445971..b1d1a87a6821 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -30,7 +30,7 @@
 #define RD88F6192_GPIO_USB_VBUS         10
 
 static struct mv643xx_eth_platform_data rd88f6192_ge00_data = {
-        .phy_addr       = 8,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
 static struct mv_sata_platform_data rd88f6192_sata_data = {
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index d96487a0f18b..f785093e433f 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -69,7 +69,7 @@ static struct platform_device rd88f6281_nand_flash = {
 };
 
 static struct mv643xx_eth_platform_data rd88f6281_ge00_data = {
-        .phy_addr       = -1,
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
         .speed          = SPEED_1000,
         .duplex         = DUPLEX_FULL,
 };
@@ -90,7 +90,6 @@ static void __init rd88f6281_init(void)
         kirkwood_rtc_init();
         kirkwood_sata_init(&rd88f6281_sata_data);
         kirkwood_uart0_init();
-        kirkwood_uart1_init();
 
         platform_device_register(&rd88f6281_nand_flash);
 }
diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c
index c6c08e800233..7f3f24053a00 100644
--- a/arch/arm/mach-ks8695/cpu.c
+++ b/arch/arm/mach-ks8695/cpu.c
@@ -24,9 +24,9 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c
index 3624e65cd89b..9aecf0c4b8b1 100644
--- a/arch/arm/mach-ks8695/gpio.c
+++ b/arch/arm/mach-ks8695/gpio.c
@@ -23,8 +23,8 @@
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/module.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <asm/mach/irq.h>
 
@@ -72,7 +72,7 @@ int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type)
 
         /* set pin as input */
         x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
-        x &= ~IOPM_(pin);
+        x &= ~IOPM(pin);
         __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
 
         local_irq_restore(flags);
@@ -108,7 +108,7 @@ int __init_or_module gpio_direction_input(unsigned int pin)
 
         /* set pin as input */
         x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
-        x &= ~IOPM_(pin);
+        x &= ~IOPM(pin);
         __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
 
         local_irq_restore(flags);
@@ -136,14 +136,14 @@ int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state)
         /* set line state */
         x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
         if (state)
-                x |= (1 << pin);
+                x |= IOPD(pin);
         else
-                x &= ~(1 << pin);
+                x &= ~IOPD(pin);
         __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
 
         /* set pin as output */
         x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPM);
-        x |= IOPM_(pin);
+        x |= IOPM(pin);
         __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM);
 
         local_irq_restore(flags);
@@ -168,9 +168,9 @@ void gpio_set_value(unsigned int pin, unsigned int state)
         /* set output line state */
         x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
         if (state)
-                x |= (1 << pin);
+                x |= IOPD(pin);
         else
-                x &= ~(1 << pin);
+                x &= ~IOPD(pin);
         __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD);
 
         local_irq_restore(flags);
@@ -189,7 +189,7 @@ int gpio_get_value(unsigned int pin)
                 return -EINVAL;
 
         x = __raw_readl(KS8695_GPIO_VA + KS8695_IOPD);
-        return (x & (1 << pin)) != 0;
+        return (x & IOPD(pin)) != 0;
 }
 EXPORT_SYMBOL(gpio_get_value);
 
@@ -240,7 +240,7 @@ static int ks8695_gpio_show(struct seq_file *s, void *unused)
         for (i = KS8695_GPIO_0; i <= KS8695_GPIO_15 ; i++) {
                 seq_printf(s, "%i:\t", i);
 
-                seq_printf(s, "%s\t", (mode & IOPM_(i)) ? "Output" : "Input");
+                seq_printf(s, "%s\t", (mode & IOPM(i)) ? "Output" : "Input");
 
                 if (i <= KS8695_GPIO_3) {
                         if (ctrl & enable[i]) {
@@ -273,7 +273,7 @@ static int ks8695_gpio_show(struct seq_file *s, void *unused)
 
                 seq_printf(s, "\t");
 
-                seq_printf(s, "%i\n", (data & IOPD_(i)) ? 1 : 0);
+                seq_printf(s, "%i\n", (data & IOPD(i)) ? 1 : 0);
         }
         return 0;
 }
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
index dadbe66cb75c..8fbc4c76c38b 100644
--- a/arch/arm/mach-ks8695/include/mach/memory.h
+++ b/arch/arm/mach-ks8695/include/mach/memory.h
@@ -31,8 +31,8 @@
 /* Platform-bus mapping */
 extern struct bus_type platform_bus_type;
 #define is_lbus_device(dev)             (dev && dev->bus == &platform_bus_type)
-#define __arch_dma_to_virt(dev, x)      ({ is_lbus_device(dev) ? \
-                                        __phys_to_virt(x) : __bus_to_virt(x); })
+#define __arch_dma_to_virt(dev, x)      ({ (void *) (is_lbus_device(dev) ? \
+                                        __phys_to_virt(x) : __bus_to_virt(x)); })
 #define __arch_virt_to_dma(dev, x)      ({ is_lbus_device(dev) ? \
                                         (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
 #define __arch_page_to_dma(dev, x)      __arch_virt_to_dma(dev, page_address(x))
diff --git a/arch/arm/mach-ks8695/include/mach/regs-gpio.h b/arch/arm/mach-ks8695/include/mach/regs-gpio.h
index 0df6fe61d1ce..90614a7d0548 100644
--- a/arch/arm/mach-ks8695/include/mach/regs-gpio.h
+++ b/arch/arm/mach-ks8695/include/mach/regs-gpio.h
@@ -24,7 +24,7 @@
 
 
 /* Port Mode Register */
-#define IOPM_(x)                (1 << (x))      /* Mode for GPIO Pin x */
+#define IOPM(x)                 (1 << (x))      /* Mode for GPIO Pin x */
 
 /* Port Control Register */
 #define IOPC_IOTIM1EN           (1 << 17)       /* GPIO Pin for Timer1 Enable */
@@ -50,6 +50,6 @@
 #define IOPC_TM_EDGE            (6)             /* Both Edge Detection */
 
 /* Port Data Register */
-#define IOPD_(x)                (1 << (x))      /* Signal Level of GPIO Pin x */
+#define IOPD(x)                 (1 << (x))      /* Signal Level of GPIO Pin x */
 
 #endif
diff --git a/arch/arm/mach-ks8695/include/mach/regs-lan.h b/arch/arm/mach-ks8695/include/mach/regs-lan.h
index 9ef409901e76..82c5f3791afb 100644
--- a/arch/arm/mach-ks8695/include/mach/regs-lan.h
+++ b/arch/arm/mach-ks8695/include/mach/regs-lan.h
@@ -29,8 +29,8 @@
 #define KS8695_LRDLB            (0x14)          /* Receive Descriptor List Base Address */
 #define KS8695_LMAL             (0x18)          /* MAC Station Address Low */
 #define KS8695_LMAH             (0x1c)          /* MAC Station Address High */
-#define KS8695_LMAAL_(n)        (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
-#define KS8695_LMAAH_(n)        (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
+#define KS8695_LMAAL(n)         (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
+#define KS8695_LMAAH(n)         (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
 
 
 /* DMA Transmit Control Register */
diff --git a/arch/arm/mach-ks8695/include/mach/regs-wan.h b/arch/arm/mach-ks8695/include/mach/regs-wan.h
index eb494ec6e956..c475bed22b8e 100644
--- a/arch/arm/mach-ks8695/include/mach/regs-wan.h
+++ b/arch/arm/mach-ks8695/include/mach/regs-wan.h
@@ -29,8 +29,8 @@
 #define KS8695_WRDLB            (0x14)          /* Receive Descriptor List Base Address */
 #define KS8695_WMAL             (0x18)          /* MAC Station Address Low */
 #define KS8695_WMAH             (0x1c)          /* MAC Station Address High */
-#define KS8695_WMAAL_(n)        (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
-#define KS8695_WMAAH_(n)        (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
+#define KS8695_WMAAL(n)         (0x80 + ((n)*8))        /* MAC Additional Station Address (0..15) Low */
+#define KS8695_WMAAH(n)         (0x84 + ((n)*8))        /* MAC Additional Station Address (0..15) High */
 
 
 /* DMA Transmit Control Register */
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h
index 2a6f91869056..5a9b032bdbeb 100644
--- a/arch/arm/mach-ks8695/include/mach/system.h
+++ b/arch/arm/mach-ks8695/include/mach/system.h
@@ -14,7 +14,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/regs-timer.h>
 
 static void arch_idle(void)
diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h
index 0eee37a69075..9495cb4d701a 100644
--- a/arch/arm/mach-ks8695/include/mach/uncompress.h
+++ b/arch/arm/mach-ks8695/include/mach/uncompress.h
@@ -14,7 +14,7 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
 
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/regs-uart.h>
 
 static void putc(char c)
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
index e5e71f4dbb84..e375c1d53f81 100644
--- a/arch/arm/mach-ks8695/irq.c
+++ b/arch/arm/mach-ks8695/irq.c
@@ -24,10 +24,10 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index 1746c67af176..f5ebcc0fcab9 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -27,8 +27,8 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/signal.h>
 #include <asm/mach/pci.h>
 #include <mach/hardware.h>
@@ -141,7 +141,7 @@ static struct pci_ops ks8695_pci_ops = {
         .write  = ks8695_pci_writeconfig,
 };
 
-static struct pci_bus *ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
+static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
 {
         return pci_scan_bus(sys->busnr, &ks8695_pci_ops, sys);
 }
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 940888dffc16..69c072c2c0f9 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -24,8 +24,8 @@
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/mach/time.h>
 
 #include <mach/regs-timer.h>
diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig
index 6f4c6a1798c1..9be7466e346c 100644
--- a/arch/arm/mach-lh7a40x/Kconfig
+++ b/arch/arm/mach-lh7a40x/Kconfig
@@ -40,23 +40,22 @@ config LPD7A40X_CPLD_SSP
         bool
 
 config LH7A40X_CONTIGMEM
-        bool "Disable NUMA Support"
-        depends on ARCH_LH7A40X
+        bool "Disable NUMA/SparseMEM Support"
         help
           Say Y here if your bootloader sets the SROMLL bit(s) in
           the SDRAM controller, organizing memory as a contiguous
-          array.  This option will disable CONFIG_DISCONTIGMEM and
-          force the kernel to manage all memory in one node.
+          array.  This option will disable sparse memory support
+          and force the kernel to manage all memory in one node.
 
-          Setting this option incorrectly may prevent the kernel from
-          booting.  It is OK to leave it N.
+          Setting this option incorrectly may prevent the kernel
+          from booting.  It is OK to leave it N.
 
           For more information, consult
             <file:Documentation/arm/Sharp-LH/SDRAM>.
 
 config LH7A40X_ONE_BANK_PER_NODE
         bool "Optimize NUMA Node Tables for Size"
-        depends on ARCH_LH7A40X && !LH7A40X_CONTIGMEM
+        depends on !LH7A40X_CONTIGMEM
         help
           Say Y here to produce compact memory node tables.  By
           default pairs of adjacent physical RAM banks are managed
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index 551b97261826..3d7bd50b9095 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -77,7 +77,7 @@ static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
         irq = IRQ_KEV7A400_CPLD;
         for (; mask; mask >>= 1, ++irq)
                 if (mask & 1)
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
 }
 
 void __init lh7a40x_init_board_irq (void)
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index e373fb8e2699..cb15e5d32120 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -214,11 +214,11 @@ static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
         desc->chip->ack (irq);
 
         if ((mask & (1<<0)) == 0)       /* WLAN */
-                IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT);
+                generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
 
 #if defined (IRQ_TOUCH)
         if ((mask & (1<<1)) == 0)       /* Touch */
-                IRQ_DISPATCH (IRQ_TOUCH);
+                generic_handle_irq(IRQ_TOUCH);
 #endif
 
         desc->chip->unmask (irq); /* Level-triggered need this */
diff --git a/arch/arm/mach-lh7a40x/common.h b/arch/arm/mach-lh7a40x/common.h
index 0ca20c6c83b7..6ed3f6b6db76 100644
--- a/arch/arm/mach-lh7a40x/common.h
+++ b/arch/arm/mach-lh7a40x/common.h
@@ -15,4 +15,3 @@ extern void lh7a404_init_irq (void);
 extern void lh7a40x_clcd_init (void);
 extern void lh7a40x_init_board_irq (void);
 
-#define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq))
diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
index f7107b4c197a..1da14ff66c93 100644
--- a/arch/arm/mach-lh7a40x/include/mach/memory.h
+++ b/arch/arm/mach-lh7a40x/include/mach/memory.h
@@ -73,4 +73,10 @@
 
 #endif
 
+/*
+ * Sparsemem version of the above
+ */
+#define MAX_PHYSMEM_BITS        32
+#define SECTION_SIZE_BITS       24
+
 #endif
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
index 0d5063ebda10..fd033bb4342f 100644
--- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
@@ -63,10 +63,10 @@ static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
         desc->chip->ack (irq);
 
         if ((mask & 0x1) == 0)  /* WLAN */
-                IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT);
+                generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
 
         if ((mask & 0x2) == 0)  /* Touch */
-                IRQ_DISPATCH (IRQ_LPD7A400_TS);
+                generic_handle_irq(IRQ_LPD7A400_TS);
 
         desc->chip->unmask (irq); /* Level-triggered need this */
 }
diff --git a/arch/arm/mach-lh7a40x/ssp-cpld.c b/arch/arm/mach-lh7a40x/ssp-cpld.c
index 51fbef9601b9..2901d49d1484 100644
--- a/arch/arm/mach-lh7a40x/ssp-cpld.c
+++ b/arch/arm/mach-lh7a40x/ssp-cpld.c
@@ -43,8 +43,8 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/spinlock.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-lh7a40x/time.c b/arch/arm/mach-lh7a40x/time.c
index 7fe9e06cf662..4601e425bae3 100644
--- a/arch/arm/mach-lh7a40x/time.c
+++ b/arch/arm/mach-lh7a40x/time.c
@@ -13,9 +13,9 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/time.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 
diff --git a/arch/arm/mach-loki/addr-map.c b/arch/arm/mach-loki/addr-map.c
index 70ca56bb6f33..0332d8f5c18c 100644
--- a/arch/arm/mach-loki/addr-map.c
+++ b/arch/arm/mach-loki/addr-map.c
@@ -11,8 +11,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mbus.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include "common.h"
 
 /*
diff --git a/arch/arm/mach-loki/irq.c b/arch/arm/mach-loki/irq.c
index 5a487930cb2f..e1f97338d5b7 100644
--- a/arch/arm/mach-loki/irq.c
+++ b/arch/arm/mach-loki/irq.c
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <plat/irq.h>
 #include "common.h"
 
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
index 2cc9ac9b488f..85f9c1296aa0 100644
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -67,7 +67,7 @@ static struct platform_device lb88rc8480_boot_flash = {
 };
 
 static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
-        .phy_addr       = 1,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
         .mac_addr       = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
 };
 
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 995afc4ade4b..a24259133e07 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -18,6 +18,8 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
+#include <linux/io.h>
+#include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -28,9 +30,6 @@
 #include <mach/board.h>
 #include <mach/msm_iomap.h>
 
-#include <asm/io.h>
-#include <asm/delay.h>
-
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
diff --git a/arch/arm/mach-msm/common.c b/arch/arm/mach-msm/common.c
index 3a511368a5d8..604f8ade9587 100644
--- a/arch/arm/mach-msm/common.c
+++ b/arch/arm/mach-msm/common.c
@@ -19,9 +19,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/flash.h>
-#include <asm/io.h>
 
 #include <asm/setup.h>
 
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 9de08265d974..0c8f252637e1 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -13,7 +13,7 @@
  *
  */
 
-#include <asm/io.h>
+#include <linux/io.h>
 #include <linux/interrupt.h>
 #include <mach/dma.h>
 
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 5976200de99b..7999e4ba8e20 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -18,9 +18,9 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/page.h>
 #include <mach/msm_iomap.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
index 66901baf8c8e..04b8d182ff8a 100644
--- a/arch/arm/mach-msm/irq.c
+++ b/arch/arm/mach-msm/irq.c
@@ -19,11 +19,10 @@
 #include <linux/interrupt.h>
 #include <linux/ptrace.h>
 #include <linux/timer.h>
-
 #include <linux/irq.h>
-#include <mach/hardware.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
+#include <mach/hardware.h>
 
 #include <mach/msm_iomap.h>
 
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 9f02d7dca985..2bffe9b7e9fe 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -20,12 +20,11 @@
 #include <linux/clk.h>
 #include <linux/clockchips.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
 #include <asm/mach/time.h>
 #include <mach/msm_iomap.h>
 
-#include <asm/io.h>
-
 #define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
 #define MSM_DGT_SHIFT (5)
 
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 4004b672a2eb..311d5b0e9bc7 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mbus.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include "common.h"
 
 /*
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 953a26c469cb..238a2f8c2d52 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -285,6 +285,11 @@ static struct resource mv78xx0_ge00_shared_resources[] = {
                 .start  = GE00_PHYS_BASE + 0x2000,
                 .end    = GE00_PHYS_BASE + 0x3fff,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "ge err irq",
+                .start  = IRQ_MV78XX0_GE_ERR,
+                .end    = IRQ_MV78XX0_GE_ERR,
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -294,7 +299,7 @@ static struct platform_device mv78xx0_ge00_shared = {
         .dev            = {
                 .platform_data  = &mv78xx0_ge00_shared_data,
         },
-        .num_resources  = 1,
+        .num_resources  = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
         .resource       = mv78xx0_ge00_shared_resources,
 };
 
@@ -330,6 +335,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
         .t_clk          = 0,
         .dram           = &mv78xx0_mbus_dram_info,
+        .shared_smi     = &mv78xx0_ge00_shared,
 };
 
 static struct resource mv78xx0_ge01_shared_resources[] = {
@@ -370,7 +376,6 @@ static struct platform_device mv78xx0_ge01 = {
 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
         eth_data->shared = &mv78xx0_ge01_shared;
-        eth_data->shared_smi = &mv78xx0_ge00_shared;
         mv78xx0_ge01.dev.platform_data = eth_data;
 
         platform_device_register(&mv78xx0_ge01_shared);
@@ -384,6 +389,7 @@ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
         .t_clk          = 0,
         .dram           = &mv78xx0_mbus_dram_info,
+        .shared_smi     = &mv78xx0_ge00_shared,
 };
 
 static struct resource mv78xx0_ge10_shared_resources[] = {
@@ -424,7 +430,6 @@ static struct platform_device mv78xx0_ge10 = {
 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
 {
         eth_data->shared = &mv78xx0_ge10_shared;
-        eth_data->shared_smi = &mv78xx0_ge00_shared;
         mv78xx0_ge10.dev.platform_data = eth_data;
 
         platform_device_register(&mv78xx0_ge10_shared);
@@ -438,6 +443,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
 struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
         .t_clk          = 0,
         .dram           = &mv78xx0_mbus_dram_info,
+        .shared_smi     = &mv78xx0_ge00_shared,
 };
 
 static struct resource mv78xx0_ge11_shared_resources[] = {
@@ -478,7 +484,6 @@ static struct platform_device mv78xx0_ge11 = {
 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
 {
         eth_data->shared = &mv78xx0_ge11_shared;
-        eth_data->shared_smi = &mv78xx0_ge00_shared;
         mv78xx0_ge11.dev.platform_data = eth_data;
 
         platform_device_register(&mv78xx0_ge11_shared);
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index a2d0c9783604..49f434c39eb7 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -19,19 +19,19 @@
 #include "common.h"
 
 static struct mv643xx_eth_platform_data db78x00_ge00_data = {
-        .phy_addr       = 8,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
 static struct mv643xx_eth_platform_data db78x00_ge01_data = {
-        .phy_addr       = 9,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(9),
 };
 
 static struct mv643xx_eth_platform_data db78x00_ge10_data = {
-        .phy_addr       = -1,
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
 };
 
 static struct mv643xx_eth_platform_data db78x00_ge11_data = {
-        .phy_addr       = -1,
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
 };
 
 static struct mv_sata_platform_data db78x00_sata_data = {
diff --git a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
index ed4a46bcd3b0..fbfb2693ce6c 100644
--- a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
+++ b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
@@ -26,14 +26,22 @@
         ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
         mov     \irqnr, #31
         ands    \irqstat, \irqstat, \tmp
+        bne     1001f
 
         @ if no low interrupts set, check high interrupts
-        ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
-        ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
-        moveq   \irqnr, #63
-        andeqs  \irqstat, \irqstat, \tmp
+        ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        mov     \irqnr, #63
+        ands    \irqstat, \irqstat, \tmp
+        bne     1001f
+
+        @ if no high interrupts set, check error interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_ERR_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_ERR_OFF]
+        mov     \irqnr, #95
+        ands    \irqstat, \irqstat, \tmp
 
         @ find first active interrupt source
-        clzne   \irqstat, \irqstat
+1001:   clzne   \irqstat, \irqstat
         subne   \irqnr, \irqnr, \irqstat
         .endm
diff --git a/arch/arm/mach-mv78xx0/include/mach/irqs.h b/arch/arm/mach-mv78xx0/include/mach/irqs.h
index 995d7fb8d06f..bebc330281ec 100644
--- a/arch/arm/mach-mv78xx0/include/mach/irqs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/irqs.h
@@ -80,9 +80,14 @@
 #define IRQ_MV78XX0_DB_OUT      61
 
 /*
+ * MV78xx0 Error Interrupt Controller
+ */
+#define IRQ_MV78XX0_GE_ERR      70
+
+/*
  * MV78XX0 General Purpose Pins
  */
-#define IRQ_MV78XX0_GPIO_START  64
+#define IRQ_MV78XX0_GPIO_START  96
 #define NR_GPIO_IRQS            GPIO_MAX
 
 #define NR_IRQS                 (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index ad664178d6e1..ee9c5593ee92 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -71,8 +71,10 @@
 #define   BRIDGE_INT_TIMER1     0x0004
 #define   BRIDGE_INT_TIMER1_CLR (~0x0004)
 #define  IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define   IRQ_CAUSE_ERR_OFF     0x0000
 #define   IRQ_CAUSE_LOW_OFF     0x0004
 #define   IRQ_CAUSE_HIGH_OFF    0x0008
+#define   IRQ_MASK_ERR_OFF      0x000c
 #define   IRQ_MASK_LOW_OFF      0x0010
 #define   IRQ_MASK_HIGH_OFF     0x0014
 #define  TIMER_VIRT_BASE        (BRIDGE_VIRT_BASE | 0x0300)
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 28248d37b999..503e5d195ae5 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -19,4 +19,5 @@ void __init mv78xx0_init_irq(void)
 {
         orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
         orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
 }
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
new file mode 100644
index 000000000000..c77a4b8f73b4
--- /dev/null
+++ b/arch/arm/mach-mx2/devices.h
@@ -0,0 +1,15 @@
+
+extern struct platform_device mxc_gpt1;
+extern struct platform_device mxc_gpt2;
+extern struct platform_device mxc_gpt3;
+extern struct platform_device mxc_gpt4;
+extern struct platform_device mxc_gpt5;
+extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_irda_device;
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+extern struct platform_device mxc_uart_device3;
+extern struct platform_device mxc_uart_device4;
+extern struct platform_device mxc_uart_device5;
+
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 4ce56ef4d8d3..56e22d3ca075 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -34,6 +34,8 @@
 #include <mach/iomux-mx1-mx2.h>
 #include <mach/board-mx27ads.h>
 
+#include "devices.h"
+
 /* ADS's NOR flash */
 static struct physmap_flash_data mx27ads_flash_data = {
         .width = 2,
@@ -251,12 +253,14 @@ static struct imxuart_platform_data uart_pdata[] = {
 
 static void __init mx27ads_board_init(void)
 {
-        int i;
-
         gpio_fec_active();
 
-        for (i = 0; i < 6; i++)
-                imx_init_uart(i, &uart_pdata[i]);
+        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+        mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
+        mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
+        mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index 1028f453cfc8..7f55746e2591 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -28,6 +28,8 @@
 #include <mach/imx-uart.h>
 #include <mach/board-pcm038.h>
 
+#include "devices.h"
+
 /*
  * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
  * 16 bit width
@@ -170,11 +172,11 @@ static struct platform_device *platform_devices[] __initdata = {
 
 static void __init pcm038_init(void)
 {
-        int i;
         gpio_fec_active();
 
-        for (i = 0; i < 3; i++)
-                imx_init_uart(i, &uart_pdata[i]);
+        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
index e31fd44f7941..16debc296dad 100644
--- a/arch/arm/mach-mx2/serial.c
+++ b/arch/arm/mach-mx2/serial.c
@@ -35,7 +35,7 @@ static struct resource uart0[] = {
         },
 };
 
-static struct platform_device mxc_uart_device0 = {
+struct platform_device mxc_uart_device0 = {
         .name = "imx-uart",
         .id = 0,
         .resource = uart0,
@@ -54,7 +54,7 @@ static struct resource uart1[] = {
         },
 };
 
-static struct platform_device mxc_uart_device1 = {
+struct platform_device mxc_uart_device1 = {
         .name = "imx-uart",
         .id = 1,
         .resource = uart1,
@@ -73,7 +73,7 @@ static struct resource uart2[] = {
         },
 };
 
-static struct platform_device mxc_uart_device2 = {
+struct platform_device mxc_uart_device2 = {
         .name = "imx-uart",
         .id = 2,
         .resource = uart2,
@@ -92,7 +92,7 @@ static struct resource uart3[] = {
         },
 };
 
-static struct platform_device mxc_uart_device3 = {
+struct platform_device mxc_uart_device3 = {
         .name = "imx-uart",
         .id = 3,
         .resource = uart3,
@@ -111,7 +111,7 @@ static struct resource uart4[] = {
         },
 };
 
-static struct platform_device mxc_uart_device4 = {
+struct platform_device mxc_uart_device4 = {
         .name = "imx-uart",
         .id = 4,
         .resource = uart4,
@@ -130,48 +130,9 @@ static struct resource uart5[] = {
         },
 };
 
-static struct platform_device mxc_uart_device5 = {
+struct platform_device mxc_uart_device5 = {
         .name = "imx-uart",
         .id = 5,
         .resource = uart5,
         .num_resources = ARRAY_SIZE(uart5),
 };
-
-/*
- * Register only those UARTs that physically exists
- */
-int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
-{
-        switch (uart_no) {
-        case 0:
-                mxc_uart_device0.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device0);
-                break;
-        case 1:
-                mxc_uart_device1.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device1);
-                break;
-#ifndef CONFIG_MXC_IRDA
-        case 2:
-                mxc_uart_device2.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device2);
-                break;
-#endif
-        case 3:
-                mxc_uart_device3.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device3);
-                break;
-        case 4:
-                mxc_uart_device4.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device4);
-                break;
-        case 5:
-                mxc_uart_device5.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device5);
-                break;
-        default:
-                return -ENODEV;
-        }
-
-        return 0;
-}
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index e08c6a8ac56b..a6bdcc07f3c9 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -36,7 +36,7 @@ static struct resource uart0[] = {
         },
 };
 
-static struct platform_device mxc_uart_device0 = {
+struct platform_device mxc_uart_device0 = {
         .name = "imx-uart",
         .id = 0,
         .resource = uart0,
@@ -55,7 +55,7 @@ static struct resource uart1[] = {
         },
 };
 
-static struct platform_device mxc_uart_device1 = {
+struct platform_device mxc_uart_device1 = {
         .name = "imx-uart",
         .id = 1,
         .resource = uart1,
@@ -74,7 +74,7 @@ static struct resource uart2[] = {
         },
 };
 
-static struct platform_device mxc_uart_device2 = {
+struct platform_device mxc_uart_device2 = {
         .name = "imx-uart",
         .id = 2,
         .resource = uart2,
@@ -93,7 +93,7 @@ static struct resource uart3[] = {
         },
 };
 
-static struct platform_device mxc_uart_device3 = {
+struct platform_device mxc_uart_device3 = {
         .name = "imx-uart",
         .id = 3,
         .resource = uart3,
@@ -112,46 +112,13 @@ static struct resource uart4[] = {
         },
 };
 
-static struct platform_device mxc_uart_device4 = {
+struct platform_device mxc_uart_device4 = {
         .name = "imx-uart",
         .id = 4,
         .resource = uart4,
         .num_resources = ARRAY_SIZE(uart4),
 };
 
-/*
- * Register only those UARTs that physically exist
- */
-int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
-{
-        switch (uart_no) {
-        case 0:
-                mxc_uart_device0.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device0);
-                break;
-        case 1:
-                mxc_uart_device1.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device1);
-                break;
-        case 2:
-                mxc_uart_device2.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device2);
-                break;
-        case 3:
-                mxc_uart_device3.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device3);
-                break;
-        case 4:
-                mxc_uart_device4.dev.platform_data = pdata;
-                platform_device_register(&mxc_uart_device4);
-                break;
-        default:
-                return -ENODEV;
-        }
-
-        return 0;
-}
-
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
         [0] = {
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
new file mode 100644
index 000000000000..4dc03f9e6001
--- /dev/null
+++ b/arch/arm/mach-mx3/devices.h
@@ -0,0 +1,6 @@
+
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+extern struct platform_device mxc_uart_device3;
+extern struct platform_device mxc_uart_device4;
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
index 3dda1fe23cbf..6e664be8cc13 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux.c
@@ -43,7 +43,8 @@ static DEFINE_SPINLOCK(gpio_mux_lock);
  */
 int mxc_iomux_mode(unsigned int pin_mode)
 {
-        u32 reg, field, l, mode, ret = 0;
+        u32 field, l, mode, ret = 0;
+        void __iomem *reg;
 
         reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
         field = pin_mode & 0x3;
@@ -70,7 +71,8 @@ EXPORT_SYMBOL(mxc_iomux_mode);
  */
 void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
 {
-        u32 reg, field, l;
+        u32 field, l;
+        void __iomem *reg;
 
         reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
         field = (pin + 2) % 3;
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 30d842bd4d64..0589b5cd33c7 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -49,7 +49,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
                 .virtual        = AVIC_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(AVIC_BASE_ADDR),
                 .length         = AVIC_SIZE,
-                .type           = MT_NONSHARED_DEVICE
+                .type           = MT_DEVICE_NONSHARED
         },
 };
 
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 60fb4e0d5acd..1be4a390c63f 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
+#include <linux/irq.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -31,6 +32,8 @@
 #include <asm/mach/map.h>
 #include <mach/common.h>
 #include <mach/board-mx31ads.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
 
 /*!
  * @file mx31ads.c
@@ -84,6 +87,108 @@ static inline int mxc_init_extuart(void)
 }
 #endif
 
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+        mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
+        mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
+        mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
+        mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
+
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* !SERIAL_IMX */
+
+static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 imr_val;
+        u32 int_valid;
+        u32 expio_irq;
+
+        imr_val = __raw_readw(PBC_INTMASK_SET_REG);
+        int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
+
+        expio_irq = MXC_EXP_IO_BASE;
+        for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+                if ((int_valid & 1) == 0)
+                        continue;
+
+                generic_handle_irq(expio_irq);
+        }
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * @param irq           an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+        /* mask the interrupt */
+        __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
+        __raw_readw(PBC_INTMASK_CLEAR_REG);
+}
+
+/*
+ * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
+ * @param irq           an expanded io virtual irq number
+ */
+static void expio_ack_irq(u32 irq)
+{
+        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+        /* clear the interrupt status */
+        __raw_writew(1 << expio, PBC_INTSTATUS_REG);
+}
+
+/*
+ * Enable a expio pin's interrupt by clearing the bit in the imr.
+ * @param irq           a expio virtual irq number
+ */
+static void expio_unmask_irq(u32 irq)
+{
+        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+        /* unmask the interrupt */
+        __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+        .ack = expio_ack_irq,
+        .mask = expio_mask_irq,
+        .unmask = expio_unmask_irq,
+};
+
+static void __init mx31ads_init_expio(void)
+{
+        int i;
+
+        printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
+
+        /*
+         * Configure INT line as GPIO input
+         */
+        mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO));
+
+        /* disable the interrupt and clear the status */
+        __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
+        __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
+        for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
+             i++) {
+                set_irq_chip(i, &expio_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+        set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
+        set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
+}
+
 /*!
  * This structure defines static mappings for the i.MX31ADS board.
  */
@@ -92,17 +197,17 @@ static struct map_desc mx31ads_io_desc[] __initdata = {
                 .virtual        = AIPS1_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
                 .length         = AIPS1_SIZE,
-                .type           = MT_NONSHARED_DEVICE
+                .type           = MT_DEVICE_NONSHARED
         }, {
                 .virtual        = SPBA0_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(SPBA0_BASE_ADDR),
                 .length         = SPBA0_SIZE,
-                .type           = MT_NONSHARED_DEVICE
+                .type           = MT_DEVICE_NONSHARED
         }, {
                 .virtual        = AIPS2_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
                 .length         = AIPS2_SIZE,
-                .type           = MT_NONSHARED_DEVICE
+                .type           = MT_DEVICE_NONSHARED
         }, {
                 .virtual        = CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(CS4_BASE_ADDR),
@@ -120,12 +225,19 @@ void __init mx31ads_map_io(void)
         iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
 }
 
+void __init mx31ads_init_irq(void)
+{
+        mxc_init_irq();
+        mx31ads_init_expio();
+}
+
 /*!
  * Board specific initialization.
  */
 static void __init mxc_board_init(void)
 {
         mxc_init_extuart();
+        mxc_init_imx_uart();
 }
 
 static void __init mx31ads_timer_init(void)
@@ -148,7 +260,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31ads_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31ads_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx31ads_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index d363a6e79f80..c43440070143 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -45,17 +45,17 @@ static struct map_desc mx31lite_io_desc[] __initdata = {
                 .virtual = AIPS1_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
                 .length = AIPS1_SIZE,
-                .type = MT_NONSHARED_DEVICE
+                .type = MT_DEVICE_NONSHARED
         }, {
                 .virtual = SPBA0_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
                 .length = SPBA0_SIZE,
-                .type = MT_NONSHARED_DEVICE
+                .type = MT_DEVICE_NONSHARED
         }, {
                 .virtual = AIPS2_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
                 .length = AIPS2_SIZE,
-                .type = MT_NONSHARED_DEVICE
+                .type = MT_DEVICE_NONSHARED
         }, {
                 .virtual = CS4_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 0a152ed15a85..11fda95c86a5 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -33,6 +33,8 @@
 #include <mach/iomux-mx3.h>
 #include <mach/board-pcm037.h>
 
+#include "devices.h"
+
 static struct physmap_flash_data pcm037_flash_data = {
         .width  = 2,
 };
@@ -54,7 +56,7 @@ static struct platform_device pcm037_flash = {
 };
 
 static struct imxuart_platform_data uart_pdata = {
-        .flags = 0,
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -73,12 +75,12 @@ static void __init mxc_board_init(void)
         mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
         mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
 
-        imx_init_uart(0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
 
         mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3);
         mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3);
 
-        imx_init_uart(2, &uart_pdata);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata);
 }
 
 /*
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 1b40483ea753..79df60c20e70 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -22,10 +22,10 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/vic.h>
-#include <asm/io.h>
 #include <mach/netx-regs.h>
 #include <asm/mach/irq.h>
 
@@ -77,15 +77,12 @@ netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
         stat = ((readl(NETX_DPMAS_INT_EN) &
                 readl(NETX_DPMAS_INT_STAT)) >> 24) & 0x1f;
 
-        desc = irq_desc + NETX_IRQ_HIF_CHAINED(0);
-
         while (stat) {
                 if (stat & 1) {
                         DEBUG_IRQ("handling irq %d\n", irq);
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
                 }
                 irq++;
-                desc++;
                 stat >>= 1;
         }
 }
diff --git a/arch/arm/mach-netx/include/mach/system.h b/arch/arm/mach-netx/include/mach/system.h
index 27d8ef8e8e29..6c1023b8a9ab 100644
--- a/arch/arm/mach-netx/include/mach/system.h
+++ b/arch/arm/mach-netx/include/mach/system.h
@@ -19,7 +19,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include "netx-regs.h"
 
diff --git a/arch/arm/mach-netx/pfifo.c b/arch/arm/mach-netx/pfifo.c
index 19ae0a72bea3..03984943e16d 100644
--- a/arch/arm/mach-netx/pfifo.c
+++ b/arch/arm/mach-netx/pfifo.c
@@ -20,8 +20,8 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <mach/netx-regs.h>
 #include <mach/pfifo.h>
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index ac8e5bfed691..7c540c1f01fa 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -21,9 +21,9 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clocksource.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach/time.h>
 #include <mach/netx-regs.h>
 
diff --git a/arch/arm/mach-netx/xc.c b/arch/arm/mach-netx/xc.c
index 04c34e82fe6d..32eabf5dfa4f 100644
--- a/arch/arm/mach-netx/xc.c
+++ b/arch/arm/mach-netx/xc.c
@@ -21,8 +21,8 @@
 #include <linux/device.h>
 #include <linux/firmware.h>
 #include <linux/mutex.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <mach/netx-regs.h>
 
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index a22a608a7aba..b45bb3b802f1 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -86,13 +86,10 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
 
         while (stat != 0) {
                 int irqno = fls(stat) - 1;
-                struct irq_desc *fpgadesc;
 
                 stat &= ~(1 << irqno);
 
-                fpgadesc = irq_desc + FPGA_IRQ(irqno);
-
-                desc_handle_irq(FPGA_IRQ(irqno), fpgadesc);
+                generic_handle_irq(FPGA_IRQ(irqno));
         }
 
         desc->chip->unmask(irq);
diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c
index 804c30075960..5241e6a286cc 100644
--- a/arch/arm/mach-ns9xxx/gpio.c
+++ b/arch/arm/mach-ns9xxx/gpio.c
@@ -12,13 +12,13 @@
 #include <linux/init.h>
 #include <linux/spinlock.h>
 #include <linux/module.h>
+#include <linux/bitops.h>
 
 #include <mach/gpio.h>
 #include <mach/processor.h>
 #include <mach/processor-ns9360.h>
 #include <asm/bug.h>
 #include <asm/types.h>
-#include <asm/bitops.h>
 
 #include "gpio-ns9360.h"
 
diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
index 5dbc3c5167c8..1b12d324b087 100644
--- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h
+++ b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
@@ -11,7 +11,7 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
 
-#include <asm/io.h>
+#include <linux/io.h>
 
 #define __REG(x)        ((void __iomem __force *)(x))
 
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 38260d5f849b..22e0eb6e9ec4 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -10,7 +10,7 @@
  */
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/mach/irq.h>
 #include <mach/regs-sys-common.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 213b48787102..45a01311669a 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -21,6 +21,7 @@
 #include <linux/reboot.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
+#include <linux/irq.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 5965cf09f8c4..478c2c9a22cb 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -17,8 +17,8 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/mach-types.h>
 
 #include <mach/cpu.h>
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index ab708d4c597e..99982d3380c9 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -13,9 +13,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach/map.h>
 
 #include <mach/tc.h>
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 4449d86095f6..04995381aa5c 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -21,9 +21,9 @@
 #include <linux/kernel.h>
 #include <linux/device.h>
 #include <linux/errno.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
@@ -86,7 +86,6 @@ static void fpga_mask_ack_irq(unsigned int irq)
 
 void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_desc *d;
         u32 stat;
         int fpga_irq;
 
@@ -99,8 +98,7 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
              (fpga_irq < OMAP_FPGA_IRQ_END) && stat;
              fpga_irq++, stat >>= 1) {
                 if (stat & 1) {
-                        d = irq_desc + fpga_irq;
-                        desc_handle_irq(fpga_irq, d);
+                        generic_handle_irq(fpga_irq);
                 }
         }
 }
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index da13c3e82850..13083d7e692d 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -14,8 +14,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 #define OMAP_DIE_ID_0           0xfffe1800
 #define OMAP_DIE_ID_1           0xfffe1804
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 2b9750b200ce..b3bd8ca85118 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -11,10 +11,10 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
-#include <asm/io.h>
 #include <mach/mux.h>
 #include <mach/tc.h>
 
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 0ec6c1ec4250..9ad5197075ff 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -40,6 +40,7 @@
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -47,8 +48,6 @@
 #include <mach/gpio.h>
 #include <mach/cpu.h>
 
-#include <asm/io.h>
-
 #define IRQ_BANK(irq) ((irq) >> 5)
 #define IRQ_BIT(irq)  ((irq) & 0x1f)
 
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index 610f51f18741..71fe2cc7f7cf 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -12,8 +12,8 @@
 #include <linux/init.h>
 #include <linux/kernel_stat.h>
 #include <linux/sched.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index af44eab1ed24..59abbf331a96 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -13,9 +13,9 @@
 #include <linux/resource.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <mach/mailbox.h>
 #include <mach/irqs.h>
-#include <asm/io.h>
 
 #define MAILBOX_ARM2DSP1                0x00
 #define MAILBOX_ARM2DSP1b               0x04
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 898516e362e7..062c905c2ba6 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -24,10 +24,11 @@
  */
 #include <linux/module.h>
 #include <linux/init.h>
-#include <asm/system.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <linux/spinlock.h>
 
+#include <asm/system.h>
+
 #include <mach/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 63c4ea18b1ca..770d256c790b 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -41,8 +41,8 @@
 #include <linux/interrupt.h>
 #include <linux/sysfs.h>
 #include <linux/module.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/atomic.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index 0e25a996bb4c..aefc967fc003 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -18,8 +18,8 @@
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/mach-types.h>
 
 #include <mach/board.h>
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index e54708595ecf..2cf7e32bd293 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -43,10 +43,10 @@
 #include <linux/err.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index e67760189d14..705367ece174 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -44,10 +44,10 @@
 #include <linux/clk.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index b72ca13b3acb..24688efaa445 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -21,6 +21,7 @@
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -34,8 +35,6 @@
 #include <mach/common.h>
 #include <mach/gpmc.h>
 
-#include <asm/io.h>
-
 
 #define SDP2430_FLASH_CS        0
 #define SDP2430_SMC91X_CS       5
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 9e2624ca70a2..d4e3b6fc4705 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -21,6 +21,7 @@
 #include <linux/input.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -41,8 +42,6 @@
 #include <mach/dma.h>
 #include <mach/gpmc.h>
 
-#include <asm/io.h>
-
 #define H4_FLASH_CS     0
 #define H4_SMC91X_CS    1
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1d891e4a6933..97cde3d3611d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -21,9 +21,8 @@
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
-#include <asm/bitops.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
 
 #include <mach/clock.h>
 #include <mach/sram.h>
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 295e671e9cfd..d382eb0184ac 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -24,14 +24,13 @@
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
-
 #include <linux/io.h>
 #include <linux/cpufreq.h>
+#include <linux/bitops.h>
 
 #include <mach/clock.h>
 #include <mach/sram.h>
 #include <asm/div64.h>
-#include <asm/bitops.h>
 
 #include "memory.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 3ff74952f835..e5b475f21081 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -25,11 +25,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/limits.h>
+#include <linux/bitops.h>
 
 #include <mach/clock.h>
 #include <mach/sram.h>
 #include <asm/div64.h>
-#include <asm/bitops.h>
 
 #include "memory.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7a7f02559075..2ee954a0bc7c 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -13,9 +13,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f51d69bc457d..af1081a0b27c 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -15,8 +15,8 @@
 #include <linux/clk.h>
 #include <linux/ioport.h>
 #include <linux/spinlock.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/mach-types.h>
 #include <mach/gpmc.h>
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a5d4526ac4d6..209177c7f22f 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -14,8 +14,9 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
+#include <asm/cputype.h>
 
 #include <mach/control.h>
 #include <mach/cpu.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 987351f07d7b..7c3d6289c05f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -15,9 +15,9 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <asm/tlb.h>
-#include <asm/io.h>
 
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 9ef15b31d8fc..196a9565a8dc 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -13,10 +13,10 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #define INTC_REVISION   0x0000
 #define INTC_SYSCONFIG  0x0010
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index a480b96948e4..32b7af3c610b 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,9 +14,9 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <mach/mailbox.h>
 #include <mach/irqs.h>
-#include <asm/io.h>
 
 #define MAILBOX_REVISION                0x00
 #define MAILBOX_SYSCONFIG               0x10
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 6b49cc9cbdcb..ab1462b02e6e 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -21,8 +21,7 @@
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 #include <mach/common.h>
 #include <mach/clock.h>
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 443d07fef7f3..6b7d672058b9 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -25,10 +25,11 @@
  */
 #include <linux/module.h>
 #include <linux/init.h>
-#include <asm/system.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <linux/spinlock.h>
 
+#include <asm/system.h>
+
 #include <mach/control.h>
 #include <mach/mux.h>
 
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 8671e1079ab5..55361c16c9d9 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -24,8 +24,8 @@
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/atomic.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index adc8a26a8fb0..7d9444adc5df 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -17,8 +17,7 @@
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 #include <mach/common.h>
 #include <mach/board.h>
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index ddcd41b15d17..f59a8d0e0824 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -36,6 +36,12 @@ config MACH_TS209
           Say 'Y' here if you want your kernel to support the
           QNAP TS-109/TS-209 platform.
 
+config MACH_TERASTATION_PRO2
+        bool "Buffalo Terastation Pro II/Live"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Buffalo Terastation Pro II/Live platform.
+
 config MACH_LINKSTATION_PRO
         bool "Buffalo Linkstation Pro/Live"
         select I2C_BOARDINFO
@@ -44,6 +50,13 @@ config MACH_LINKSTATION_PRO
           Buffalo Linkstation Pro/Live platform. Both v1 and
           v2 devices are supported.
 
+config MACH_LINKSTATION_MINI
+        bool "Buffalo Linkstation Mini"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          Buffalo Linkstation Mini platform.
+
 config MACH_TS409
         bool "QNAP TS-409"
         help
@@ -68,6 +81,13 @@ config MACH_MV2120
           Say 'Y' here if you want your kernel to support the
           HP Media Vault mv2120 or mv5100.
 
+config MACH_EDMINI_V2
+        bool "LaCie Ethernet Disk mini V2"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Ethernet Disk mini V2.
+
 config MACH_MSS2
         bool "Maxtor Shared Storage II"
         help
@@ -92,6 +112,12 @@ config MACH_RD88F5181L_FXO
           Say 'Y' here if you want your kernel to support the
           Marvell Orion-VoIP FXO (88F5181L) RD.
 
+config MACH_RD88F6183AP_GE
+        bool "Marvell Orion-1-90 AP GE Reference Design"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Orion-1-90 (88F6183) AP GE RD.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index fcc48a8864f3..3d4a1bc12355 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -2,14 +2,18 @@ obj-y				+= common.o addr-map.o pci.o gpio.o irq.o mpp.o
 obj-$(CONFIG_MACH_DB88F5281)    += db88f5281-setup.o
 obj-$(CONFIG_MACH_RD88F5182)    += rd88f5182-setup.o
 obj-$(CONFIG_MACH_KUROBOX_PRO)  += kurobox_pro-setup.o
+obj-$(CONFIG_MACH_TERASTATION_PRO2)     += terastation_pro2-setup.o
 obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
+obj-$(CONFIG_MACH_LINKSTATION_MINI) += lsmini-setup.o
 obj-$(CONFIG_MACH_DNS323)       += dns323-setup.o
 obj-$(CONFIG_MACH_TS209)        += ts209-setup.o tsx09-common.o
 obj-$(CONFIG_MACH_TS409)        += ts409-setup.o tsx09-common.o
 obj-$(CONFIG_MACH_WRT350N_V2)   += wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)       += ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)       += mv2120-setup.o
+obj-$(CONFIG_MACH_EDMINI_V2)    += edmini_v2-setup.o
 obj-$(CONFIG_MACH_MSS2)         += mss2-setup.o
 obj-$(CONFIG_MACH_WNR854T)      += wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)        += rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)       += rd88f5181l-fxo-setup.o
+obj-$(CONFIG_MACH_RD88F6183AP_GE)       += rd88f6183ap-ge-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index bea37972120a..719957e05d9e 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -13,8 +13,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mbus.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include "common.h"
 
 /*
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 7b11e552bc5a..9625ef5975d0 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -18,6 +18,7 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
+#include <linux/spi/orion_spi.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -146,7 +147,6 @@ void __init orion5x_ehci1_init(void)
  ****************************************************************************/
 struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
         .dram           = &orion5x_mbus_dram_info,
-        .t_clk          = ORION5X_TCLK,
 };
 
 static struct resource orion5x_eth_shared_resources[] = {
@@ -154,6 +154,10 @@ static struct resource orion5x_eth_shared_resources[] = {
                 .start  = ORION5X_ETH_PHYS_BASE + 0x2000,
                 .end    = ORION5X_ETH_PHYS_BASE + 0x3fff,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_ORION5X_ETH_ERR,
+                .end    = IRQ_ORION5X_ETH_ERR,
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -163,7 +167,7 @@ static struct platform_device orion5x_eth_shared = {
         .dev            = {
                 .platform_data  = &orion5x_eth_shared_data,
         },
-        .num_resources  = 1,
+        .num_resources  = ARRAY_SIZE(orion5x_eth_shared_resources),
         .resource       = orion5x_eth_shared_resources,
 };
 
@@ -268,6 +272,38 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 
 
 /*****************************************************************************
+ * SPI
+ ****************************************************************************/
+static struct orion_spi_info orion5x_spi_plat_data = {
+        .tclk           = 0,
+};
+
+static struct resource orion5x_spi_resources[] = {
+        {
+                .name   = "spi base",
+                .start  = SPI_PHYS_BASE,
+                .end    = SPI_PHYS_BASE + 0x1f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device orion5x_spi = {
+        .name           = "orion_spi",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &orion5x_spi_plat_data,
+        },
+        .num_resources  = ARRAY_SIZE(orion5x_spi_resources),
+        .resource       = orion5x_spi_resources,
+};
+
+void __init orion5x_spi_init()
+{
+        platform_device_register(&orion5x_spi);
+}
+
+
+/*****************************************************************************
  * UART0
  ****************************************************************************/
 static struct plat_serial8250_port orion5x_uart0_data[] = {
@@ -278,7 +314,7 @@ static struct plat_serial8250_port orion5x_uart0_data[] = {
                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = ORION5X_TCLK,
+                .uartclk        = 0,
         }, {
         },
 };
@@ -322,7 +358,7 @@ static struct plat_serial8250_port orion5x_uart1_data[] = {
                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = ORION5X_TCLK,
+                .uartclk        = 0,
         }, {
         },
 };
@@ -455,9 +491,24 @@ void __init orion5x_xor_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+int orion5x_tclk;
+
+int __init orion5x_find_tclk(void)
+{
+        u32 dev, rev;
+
+        orion5x_pcie_id(&dev, &rev);
+        if (dev == MV88F6183_DEV_ID &&
+            (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
+                return 133333333;
+
+        return 166666667;
+}
+
 static void orion5x_timer_init(void)
 {
-        orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
+        orion5x_tclk = orion5x_find_tclk();
+        orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
 }
 
 struct sys_timer orion5x_timer = {
@@ -499,6 +550,12 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
                 } else {
                         *dev_name = "MV88F5181(L)-Rev-Unsupported";
                 }
+        } else if (*dev == MV88F6183_DEV_ID) {
+                if (*rev == MV88F6183_REV_B0) {
+                        *dev_name = "MV88F6183-Rev-B0";
+                } else {
+                        *dev_name = "MV88F6183-Rev-Unsupported";
+                }
         } else {
                 *dev_name = "Device-Unknown";
         }
@@ -510,7 +567,12 @@ void __init orion5x_init(void)
         u32 dev, rev;
 
         orion5x_id(&dev, &rev, &dev_name);
-        printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK);
+        printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
+
+        orion5x_eth_shared_data.t_clk = orion5x_tclk;
+        orion5x_spi_plat_data.tclk = orion5x_tclk;
+        orion5x_uart0_data[0].uartclk = orion5x_tclk;
+        orion5x_uart1_data[0].uartclk = orion5x_tclk;
 
         /*
          * Setup Orion address map
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 0bd195551a27..1f8b2da676a5 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -10,6 +10,7 @@ struct mv_sata_platform_data;
 void orion5x_map_io(void);
 void orion5x_init_irq(void);
 void orion5x_init(void);
+extern int orion5x_tclk;
 extern struct sys_timer orion5x_timer;
 
 /*
@@ -30,6 +31,7 @@ void orion5x_ehci1_init(void);
 void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
 void orion5x_i2c_init(void);
 void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
+void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index ff13e9060b18..d318bea2af91 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -285,7 +285,7 @@ subsys_initcall(db88f5281_pci_init);
  * Ethernet
  ****************************************************************************/
 static struct mv643xx_eth_platform_data db88f5281_eth_data = {
-        .phy_addr       = 8,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index b38c65ccfb15..3e66098340a5 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -79,7 +79,7 @@ subsys_initcall(dns323_pci_init);
  */
 
 static struct mv643xx_eth_platform_data dns323_eth_data = {
-        .phy_addr = 8,
+        .phy_addr = MV643XX_ETH_PHY_ADDR(8),
 };
 
 /****************************************************************************
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
new file mode 100644
index 000000000000..b24ee0c2cd61
--- /dev/null
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -0,0 +1,262 @@
+/*
+ * arch/arm/mach-orion5x/edmini_v2-setup.c
+ *
+ * LaCie Ethernet Disk mini V2 Setup
+ *
+ * Copyright (C) 2008 Christopher Moore <moore@free.fr>
+ * Copyright (C) 2008 Albert Aribaud <albert.aribaud@free.fr>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * TODO: add Orion USB device port init when kernel.org support is added.
+ * TODO: add flash write support: see below.
+ * TODO: add power-off support.
+ * TODO: add I2C EEPROM support.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * EDMINI_V2 Info
+ ****************************************************************************/
+
+/*
+ * 512KB NOR flash Device bus boot chip select
+ */
+
+#define EDMINI_V2_NOR_BOOT_BASE         0xfff80000
+#define EDMINI_V2_NOR_BOOT_SIZE         SZ_512K
+
+/*****************************************************************************
+ * 512KB NOR Flash on BOOT Device
+ ****************************************************************************/
+
+/*
+ * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom
+ * -type device. This could cause risks of accidentally erasing critical
+ * flash sectors. We thus define a single, write-protected partition covering
+ * the whole flash.
+ * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD
+ * code, break this into at least three partitions: 'u-boot code', 'u-boot
+ * environment' and 'whatever is left'.
+ */
+
+static struct mtd_partition edmini_v2_partitions[] = {
+        {
+                .name           = "Full512kb",
+                .size           = 0x00080000,
+                .offset         = 0x00000000,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+
+static struct physmap_flash_data edmini_v2_nor_flash_data = {
+        .width          = 1,
+        .parts          = edmini_v2_partitions,
+        .nr_parts       = ARRAY_SIZE(edmini_v2_partitions),
+};
+
+static struct resource edmini_v2_nor_flash_resource = {
+        .flags                  = IORESOURCE_MEM,
+        .start                  = EDMINI_V2_NOR_BOOT_BASE,
+        .end                    = EDMINI_V2_NOR_BOOT_BASE
+                + EDMINI_V2_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device edmini_v2_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &edmini_v2_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &edmini_v2_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data edmini_v2_eth_data = {
+        .phy_addr       = 8,
+};
+
+/*****************************************************************************
+ * RTC 5C372a on I2C bus
+ ****************************************************************************/
+
+#define EDMINIV2_RTC_GPIO       3
+
+static struct i2c_board_info __initdata edmini_v2_i2c_rtc = {
+        I2C_BOARD_INFO("rs5c372a", 0x32),
+        .irq = 0,
+};
+
+/*****************************************************************************
+ * Sata
+ ****************************************************************************/
+
+static struct mv_sata_platform_data edmini_v2_sata_data = {
+        .n_ports        = 2,
+};
+
+/*****************************************************************************
+ * GPIO LED (simple - doesn't use hardware blinking support)
+ ****************************************************************************/
+
+#define EDMINI_V2_GPIO_LED_POWER        16
+
+static struct gpio_led edmini_v2_leds[] = {
+        {
+                .name = "power:blue",
+                .gpio = EDMINI_V2_GPIO_LED_POWER,
+                .active_low = 1,
+        },
+};
+
+static struct gpio_led_platform_data edmini_v2_led_data = {
+        .num_leds = ARRAY_SIZE(edmini_v2_leds),
+        .leds = edmini_v2_leds,
+};
+
+static struct platform_device edmini_v2_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &edmini_v2_led_data,
+        },
+};
+
+/****************************************************************************
+ * GPIO key
+ ****************************************************************************/
+
+#define EDMINI_V2_GPIO_KEY_POWER        18
+
+static struct gpio_keys_button edmini_v2_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = EDMINI_V2_GPIO_KEY_POWER,
+                .desc           = "Power Button",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data edmini_v2_button_data = {
+        .buttons        = edmini_v2_buttons,
+        .nbuttons       = ARRAY_SIZE(edmini_v2_buttons),
+};
+
+static struct platform_device edmini_v2_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &edmini_v2_button_data,
+        },
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED },
+        {  1, MPP_UNUSED },
+        {  2, MPP_UNUSED },
+        {  3, MPP_GPIO },       /* RTC interrupt */
+        {  4, MPP_UNUSED },
+        {  5, MPP_UNUSED },
+        {  6, MPP_UNUSED },
+        {  7, MPP_UNUSED },
+        {  8, MPP_UNUSED },
+        {  9, MPP_UNUSED },
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },   /* SATA 0 presence */
+        { 13, MPP_SATA_LED },   /* SATA 1 presence */
+        { 14, MPP_SATA_LED },   /* SATA 0 active */
+        { 15, MPP_SATA_LED },   /* SATA 1 active */
+        /* 16: Power LED control (0 = On, 1 = Off) */
+        { 16, MPP_GPIO },
+        /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
+        { 17, MPP_GPIO },
+        /* 18: Power button status (0 = Released, 1 = Pressed) */
+        { 18, MPP_GPIO },
+        { 19, MPP_UNUSED },
+        { -1 }
+};
+
+static void __init edmini_v2_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(edminiv2_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&edmini_v2_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&edmini_v2_sata_data);
+        orion5x_uart0_init();
+
+        orion5x_setup_dev_boot_win(EDMINI_V2_NOR_BOOT_BASE,
+                                EDMINI_V2_NOR_BOOT_SIZE);
+        platform_device_register(&edmini_v2_nor_flash);
+        platform_device_register(&edmini_v2_gpio_leds);
+        platform_device_register(&edmini_v2_gpio_buttons);
+
+        pr_notice("edmini_v2: USB device port, flash write and power-off "
+                  "are not yet supported.\n");
+
+        /* Get RTC IRQ and register the chip */
+        if (gpio_request(EDMINIV2_RTC_GPIO, "rtc") == 0) {
+                if (gpio_direction_input(EDMINIV2_RTC_GPIO) == 0)
+                        edmini_v2_i2c_rtc.irq = gpio_to_irq(EDMINIV2_RTC_GPIO);
+                else
+                        gpio_free(EDMINIV2_RTC_GPIO);
+        }
+
+        if (edmini_v2_i2c_rtc.irq == 0)
+                pr_warning("edmini_v2: failed to get RTC IRQ\n");
+
+        i2c_register_board_info(0, &edmini_v2_i2c_rtc, 1);
+}
+
+/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
+MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
+        /* Maintainer: Christopher Moore <moore@free.fr> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = edmini_v2_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c
index cd8a16f67d2b..fc419868e39f 100644
--- a/arch/arm/mach-orion5x/gpio.c
+++ b/arch/arm/mach-orion5x/gpio.c
@@ -15,8 +15,8 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/bitops.h>
+#include <linux/io.h>
 #include <asm/gpio.h>
-#include <asm/io.h>
 #include <mach/orion5x.h>
 #include "common.h"
 
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 61eb74a88862..e67c843baa02 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -2,7 +2,7 @@
  * arch/arm/mach-orion5x/include/mach/orion5x.h
  *
  * Generic definitions of Orion SoC flavors:
- *  Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
+ *  Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90.
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
@@ -76,6 +76,9 @@
 #define MV88F5281_REV_D0        4
 #define MV88F5281_REV_D1        5
 #define MV88F5281_REV_D2        6
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID        0x6183
+#define MV88F6183_REV_B0        3
 
 /*******************************************************************************
  * Orion Registers Map
@@ -86,6 +89,7 @@
 #define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
 #define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
 #define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
 #define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
 #define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
diff --git a/arch/arm/mach-orion5x/include/mach/timex.h b/arch/arm/mach-orion5x/include/mach/timex.h
index e82e44db7629..4c69820e0810 100644
--- a/arch/arm/mach-orion5x/include/mach/timex.h
+++ b/arch/arm/mach-orion5x/include/mach/timex.h
@@ -9,5 +9,3 @@
  */
 
 #define CLOCK_TICK_RATE         (100 * HZ)
-
-#define ORION5X_TCLK            166666667
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 2545ff9e5830..632a36f5cf14 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -13,8 +13,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <asm/gpio.h>
-#include <asm/io.h>
 #include <mach/orion5x.h>
 #include <plat/irq.h>
 #include "common.h"
@@ -162,7 +162,7 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                                 polarity ^= 1 << pin;
                                 writel(polarity, GPIO_IN_POL);
                         }
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
                 }
         }
 }
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index e321ec331839..dfbb68df7b09 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -161,7 +161,7 @@ subsys_initcall(kurobox_pro_pci_init);
  ****************************************************************************/
 
 static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
-        .phy_addr       = 8,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
 /*****************************************************************************
@@ -293,7 +293,7 @@ static void kurobox_pro_power_off(void)
         const unsigned char shutdownwait[]      = {0x00, 0x0c};
         const unsigned char poweroff[]          = {0x00, 0x06};
         /* 38400 baud divisor */
-        const unsigned divisor = ((ORION5X_TCLK + (8 * 38400)) / (16 * 38400));
+        const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400));
 
         pr_info("%s: triggering power-off...\n", __func__);
 
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
new file mode 100644
index 000000000000..e0c43b8beb72
--- /dev/null
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -0,0 +1,279 @@
+/*
+ * arch/arm/mach-orion5x/lsmini-setup.c
+ *
+ * Maintainer: Alexey Kopytko <alexey@kopytko.ru>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <asm/mach-types.h>
+#include <linux/gpio.h>
+#include <asm/mach/arch.h>
+#include "common.h"
+#include "mpp.h"
+#include "include/mach/system.h"
+
+/*****************************************************************************
+ * Linkstation Mini Info
+ ****************************************************************************/
+
+/*
+ * 256K NOR flash Device bus boot chip select
+ */
+
+#define LSMINI_NOR_BOOT_BASE    0xf4000000
+#define LSMINI_NOR_BOOT_SIZE    SZ_256K
+
+/*****************************************************************************
+ * 256KB NOR Flash on BOOT Device
+ ****************************************************************************/
+
+static struct physmap_flash_data lsmini_nor_flash_data = {
+        .width          = 1,
+};
+
+static struct resource lsmini_nor_flash_resource = {
+        .flags  = IORESOURCE_MEM,
+        .start  = LSMINI_NOR_BOOT_BASE,
+        .end    = LSMINI_NOR_BOOT_BASE + LSMINI_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device lsmini_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &lsmini_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &lsmini_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data lsmini_eth_data = {
+        .phy_addr       = 8,
+};
+
+/*****************************************************************************
+ * RTC 5C372a on I2C bus
+ ****************************************************************************/
+
+static struct i2c_board_info __initdata lsmini_i2c_rtc = {
+        I2C_BOARD_INFO("rs5c372a", 0x32),
+};
+
+/*****************************************************************************
+ * LEDs attached to GPIO
+ ****************************************************************************/
+
+#define LSMINI_GPIO_LED_ALARM   2
+#define LSMINI_GPIO_LED_INFO    3
+#define LSMINI_GPIO_LED_FUNC    9
+#define LSMINI_GPIO_LED_PWR     14
+
+static struct gpio_led lsmini_led_pins[] = {
+        {
+                .name      = "alarm:red",
+                .gpio      = LSMINI_GPIO_LED_ALARM,
+                .active_low     = 1,
+        }, {
+                .name      = "info:amber",
+                .gpio      = LSMINI_GPIO_LED_INFO,
+                .active_low     = 1,
+        }, {
+                .name      = "func:blue:top",
+                .gpio      = LSMINI_GPIO_LED_FUNC,
+                .active_low     = 1,
+        }, {
+                .name      = "power:blue:bottom",
+                .gpio      = LSMINI_GPIO_LED_PWR,
+        },
+};
+
+static struct gpio_led_platform_data lsmini_led_data = {
+        .leds      = lsmini_led_pins,
+        .num_leds       = ARRAY_SIZE(lsmini_led_pins),
+};
+
+static struct platform_device lsmini_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &lsmini_led_data,
+        },
+};
+
+/****************************************************************************
+ * GPIO Attached Keys
+ ****************************************************************************/
+
+#define LSMINI_GPIO_KEY_FUNC       15
+#define LSMINI_GPIO_KEY_POWER      18
+#define LSMINI_GPIO_KEY_AUTOPOWER 17
+
+#define LSMINI_SW_POWER         0x00
+#define LSMINI_SW_AUTOPOWER     0x01
+
+static struct gpio_keys_button lsmini_buttons[] = {
+        {
+                .code      = KEY_OPTION,
+                .gpio      = LSMINI_GPIO_KEY_FUNC,
+                .desc      = "Function Button",
+                .active_low     = 1,
+        }, {
+                .type           = EV_SW,
+                .code      = LSMINI_SW_POWER,
+                .gpio      = LSMINI_GPIO_KEY_POWER,
+                .desc      = "Power-on Switch",
+                .active_low     = 1,
+        }, {
+                .type           = EV_SW,
+                .code      = LSMINI_SW_AUTOPOWER,
+                .gpio      = LSMINI_GPIO_KEY_AUTOPOWER,
+                .desc      = "Power-auto Switch",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data lsmini_button_data = {
+        .buttons        = lsmini_buttons,
+        .nbuttons       = ARRAY_SIZE(lsmini_buttons),
+};
+
+static struct platform_device lsmini_button_device = {
+        .name      = "gpio-keys",
+        .id          = -1,
+        .num_resources  = 0,
+        .dev        = {
+                .platform_data  = &lsmini_button_data,
+        },
+};
+
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct mv_sata_platform_data lsmini_sata_data = {
+        .n_ports        = 2,
+};
+
+
+/*****************************************************************************
+ * Linkstation Mini specific power off method: reboot
+ ****************************************************************************/
+/*
+ * On the Linkstation Mini, the shutdown process is following:
+ * - Userland monitors key events until the power switch goes to off position
+ * - The board reboots
+ * - U-boot starts and goes into an idle mode waiting for the user
+ *   to move the switch to ON position
+ */
+
+static void lsmini_power_off(void)
+{
+        arch_reset(0);
+}
+
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+#define LSMINI_GPIO_USB_POWER   16
+#define LSMINI_GPIO_AUTO_POWER  17
+#define LSMINI_GPIO_POWER       18
+
+#define LSMINI_GPIO_HDD_POWER0  1
+#define LSMINI_GPIO_HDD_POWER1  19
+
+static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = {
+        {  0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */
+        {  1, MPP_GPIO }, /* HDD_PWR */
+        {  2, MPP_GPIO }, /* LED_ALARM */
+        {  3, MPP_GPIO }, /* LED_INFO */
+        {  4, MPP_UNUSED },
+        {  5, MPP_UNUSED },
+        {  6, MPP_UNUSED },
+        {  7, MPP_UNUSED },
+        {  8, MPP_UNUSED },
+        {  9, MPP_GPIO }, /* LED_FUNC */
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED }, /* LED_ETH (dummy) */
+        { 12, MPP_UNUSED },
+        { 13, MPP_UNUSED },
+        { 14, MPP_GPIO }, /* LED_PWR */
+        { 15, MPP_GPIO }, /* FUNC */
+        { 16, MPP_GPIO }, /* USB_PWR */
+        { 17, MPP_GPIO }, /* AUTO_POWER */
+        { 18, MPP_GPIO }, /* POWER */
+        { 19, MPP_GPIO }, /* HDD_PWR1 */
+        { -1 },
+};
+
+static void __init lsmini_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(lsmini_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&lsmini_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&lsmini_sata_data);
+        orion5x_uart0_init();
+        orion5x_xor_init();
+
+        orion5x_setup_dev_boot_win(LSMINI_NOR_BOOT_BASE,
+                                   LSMINI_NOR_BOOT_SIZE);
+        platform_device_register(&lsmini_nor_flash);
+
+        platform_device_register(&lsmini_button_device);
+
+        platform_device_register(&lsmini_leds);
+
+        i2c_register_board_info(0, &lsmini_i2c_rtc, 1);
+
+        /* enable USB power */
+        gpio_set_value(LSMINI_GPIO_USB_POWER, 1);
+
+        /* register power-off method */
+        pm_power_off = lsmini_power_off;
+
+        pr_info("%s: finished\n", __func__);
+}
+
+#ifdef CONFIG_MACH_LINKSTATION_MINI
+MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
+        /* Maintainer: Alexey Kopytko <alexey@kopytko.ru> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = lsmini_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index c04ab0e16ea1..640ea2a3fc6c 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -11,8 +11,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mbus.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include "common.h"
 #include "mpp.h"
 
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 53ff1893b883..68acca98e638 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -109,7 +109,7 @@ subsys_initcall(mss2_pci_init);
  ****************************************************************************/
 
 static struct mv643xx_eth_platform_data mss2_eth_data = {
-        .phy_addr       = 8,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 978d4d599396..97c9ccb2ac60 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -39,7 +39,7 @@
  * Ethernet
  ****************************************************************************/
 static struct mv643xx_eth_platform_data mv2120_eth_data = {
-        .phy_addr       = 8,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
 static struct mv_sata_platform_data mv2120_sata_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index e72fe1e065e8..500cdadaf09c 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -88,7 +88,7 @@ static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
 };
 
 static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
-        .phy_addr       = -1,
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
         .speed          = SPEED_1000,
         .duplex         = DUPLEX_FULL,
 };
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index a1fe3257320d..ebde81416499 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -89,7 +89,7 @@ static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
 };
 
 static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
-        .phy_addr       = -1,
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
         .speed          = SPEED_1000,
         .duplex         = DUPLEX_FULL,
 };
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 4c3bcd76ac85..a04f9e4b633a 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -221,7 +221,7 @@ subsys_initcall(rd88f5182_pci_init);
  ****************************************************************************/
 
 static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
-        .phy_addr       = 8,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
new file mode 100644
index 000000000000..40e049539091
--- /dev/null
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -0,0 +1,117 @@
+/*
+ * arch/arm/mach-orion5x/rd88f6183-ap-ge-setup.c
+ *
+ * Marvell Orion-1-90 AP GE Reference Design Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/spi/flash.h>
+#include <linux/ethtool.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/leds.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = {
+        .phy_addr       = -1,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
+};
+
+static struct mtd_partition rd88f6183ap_ge_partitions[] = {
+        {
+                .name   = "kernel",
+                .offset = 0x00000000,
+                .size   = 0x00200000,
+        }, {
+                .name   = "rootfs",
+                .offset = 0x00200000,
+                .size   = 0x00500000,
+        }, {
+                .name   = "nvram",
+                .offset = 0x00700000,
+                .size   = 0x00080000,
+        },
+};
+
+static struct flash_platform_data rd88f6183ap_ge_spi_slave_data = {
+        .type           = "m25p64",
+        .nr_parts       = ARRAY_SIZE(rd88f6183ap_ge_partitions),
+        .parts          = rd88f6183ap_ge_partitions,
+};
+
+static struct spi_board_info __initdata rd88f6183ap_ge_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &rd88f6183ap_ge_spi_slave_data,
+                .irq            = NO_IRQ,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+static void __init rd88f6183ap_ge_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&rd88f6183ap_ge_eth_data);
+        spi_register_board_info(rd88f6183ap_ge_spi_slave_info,
+                                ARRAY_SIZE(rd88f6183ap_ge_spi_slave_info));
+        orion5x_spi_init();
+        orion5x_uart0_init();
+}
+
+static struct hw_pci rd88f6183ap_ge_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = orion5x_pci_map_irq,
+};
+
+static int __init rd88f6183ap_ge_pci_init(void)
+{
+        if (machine_is_rd88f6183ap_ge()) {
+                orion5x_pci_disable();
+                pci_common_init(&rd88f6183ap_ge_pci);
+        }
+
+        return 0;
+}
+subsys_initcall(rd88f6183ap_ge_pci_init);
+
+MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
+        /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = rd88f6183ap_ge_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
new file mode 100644
index 000000000000..0b101d7d41c2
--- /dev/null
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -0,0 +1,369 @@
+/*
+ * Buffalo Terastation Pro II/Live Board Setup
+ *
+ * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/i2c.h>
+#include <linux/serial_reg.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * Terastation Pro 2/Live Info
+ ****************************************************************************/
+
+/*
+ * Terastation Pro 2 hardware :
+ * - Marvell 88F5281-D0
+ * - Marvell 88SX6042 SATA controller (PCI)
+ * - Marvell 88E1118 Gigabit Ethernet PHY
+ * - 256KB NOR flash
+ * - 128MB of DDR RAM
+ * - PCIe port (not equipped)
+ */
+
+/*
+ * 256K NOR flash Device bus boot chip select
+ */
+
+#define TSP2_NOR_BOOT_BASE      0xf4000000
+#define TSP2_NOR_BOOT_SIZE      SZ_256K
+
+/*****************************************************************************
+ * 256KB NOR Flash on BOOT Device
+ ****************************************************************************/
+
+static struct physmap_flash_data tsp2_nor_flash_data = {
+        .width    = 1,
+};
+
+static struct resource tsp2_nor_flash_resource = {
+        .flags = IORESOURCE_MEM,
+        .start = TSP2_NOR_BOOT_BASE,
+        .end   = TSP2_NOR_BOOT_BASE + TSP2_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device tsp2_nor_flash = {
+        .name          = "physmap-flash",
+        .id            = 0,
+        .dev           = {
+                .platform_data  = &tsp2_nor_flash_data,
+        },
+        .num_resources = 1,
+        .resource      = &tsp2_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * PCI
+ ****************************************************************************/
+#define TSP2_PCI_SLOT0_OFFS             7
+#define TSP2_PCI_SLOT0_IRQ_PIN          11
+
+void __init tsp2_pci_preinit(void)
+{
+        int pin;
+
+        /*
+         * Configure PCI GPIO IRQ pins
+         */
+        pin = TSP2_PCI_SLOT0_IRQ_PIN;
+        if (gpio_request(pin, "PCI Int1") == 0) {
+                if (gpio_direction_input(pin) == 0) {
+                        set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                } else {
+                        printk(KERN_ERR "tsp2_pci_preinit failed "
+                                        "to set_irq_type pin %d\n", pin);
+                        gpio_free(pin);
+                }
+        } else {
+                printk(KERN_ERR "tsp2_pci_preinit failed to "
+                                "gpio_request %d\n", pin);
+        }
+}
+
+static int __init tsp2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+
+        /*
+         * PCI IRQs are connected via GPIOs.
+         */
+        if (slot == TSP2_PCI_SLOT0_OFFS)
+                return gpio_to_irq(TSP2_PCI_SLOT0_IRQ_PIN);
+
+        return -1;
+}
+
+static struct hw_pci tsp2_pci __initdata = {
+        .nr_controllers = 2,
+        .preinit        = tsp2_pci_preinit,
+        .swizzle        = pci_std_swizzle,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = tsp2_pci_map_irq,
+};
+
+static int __init tsp2_pci_init(void)
+{
+        if (machine_is_terastation_pro2())
+                pci_common_init(&tsp2_pci);
+
+        return 0;
+}
+
+subsys_initcall(tsp2_pci_init);
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data tsp2_eth_data = {
+        .phy_addr       = 0,
+};
+
+/*****************************************************************************
+ * RTC 5C372a on I2C bus
+ ****************************************************************************/
+
+#define TSP2_RTC_GPIO   9
+
+static struct i2c_board_info __initdata tsp2_i2c_rtc = {
+        I2C_BOARD_INFO("rs5c372a", 0x32),
+};
+
+/*****************************************************************************
+ * Terastation Pro II specific power off method via UART1-attached
+ * microcontroller
+ ****************************************************************************/
+
+#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
+
+static int tsp2_miconread(unsigned char *buf, int count)
+{
+        int i;
+        int timeout;
+
+        for (i = 0; i < count; i++) {
+                timeout = 10;
+
+                while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
+                        if (--timeout == 0)
+                                break;
+                        udelay(1000);
+                }
+
+                if (timeout == 0)
+                        break;
+                buf[i] = readl(UART1_REG(RX));
+        }
+
+        /* return read bytes */
+        return i;
+}
+
+static int tsp2_miconwrite(const unsigned char *buf, int count)
+{
+        int i = 0;
+
+        while (count--) {
+                while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
+                        barrier();
+                writel(buf[i++], UART1_REG(TX));
+        }
+
+        return 0;
+}
+
+static int tsp2_miconsend(const unsigned char *data, int count)
+{
+        int i;
+        unsigned char checksum = 0;
+        unsigned char recv_buf[40];
+        unsigned char send_buf[40];
+        unsigned char correct_ack[3];
+        int retry = 2;
+
+        /* Generate checksum */
+        for (i = 0; i < count; i++)
+                checksum -=  data[i];
+
+        do {
+                /* Send data */
+                tsp2_miconwrite(data, count);
+
+                /* send checksum */
+                tsp2_miconwrite(&checksum, 1);
+
+                if (tsp2_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
+                        printk(KERN_ERR ">%s: receive failed.\n", __func__);
+
+                        /* send preamble to clear the receive buffer */
+                        memset(&send_buf, 0xff, sizeof(send_buf));
+                        tsp2_miconwrite(send_buf, sizeof(send_buf));
+
+                        /* make dummy reads */
+                        mdelay(100);
+                        tsp2_miconread(recv_buf, sizeof(recv_buf));
+                } else {
+                        /* Generate expected ack */
+                        correct_ack[0] = 0x01;
+                        correct_ack[1] = data[1];
+                        correct_ack[2] = 0x00;
+
+                        /* checksum Check */
+                        if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
+                             recv_buf[3]) & 0xFF) {
+                                printk(KERN_ERR ">%s: Checksum Error : "
+                                        "Received data[%02x, %02x, %02x, %02x]"
+                                        "\n", __func__, recv_buf[0],
+                                        recv_buf[1], recv_buf[2], recv_buf[3]);
+                        } else {
+                                /* Check Received Data */
+                                if (correct_ack[0] == recv_buf[0] &&
+                                    correct_ack[1] == recv_buf[1] &&
+                                    correct_ack[2] == recv_buf[2]) {
+                                        /* Interval for next command */
+                                        mdelay(10);
+
+                                        /* Receive ACK */
+                                        return 0;
+                                }
+                        }
+                        /* Received NAK or illegal Data */
+                        printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
+                                        "Received\n", __func__);
+                }
+        } while (retry--);
+
+        /* Interval for next command */
+        mdelay(10);
+
+        return -1;
+}
+
+static void tsp2_power_off(void)
+{
+        const unsigned char watchdogkill[]      = {0x01, 0x35, 0x00};
+        const unsigned char shutdownwait[]      = {0x00, 0x0c};
+        const unsigned char poweroff[]          = {0x00, 0x06};
+        /* 38400 baud divisor */
+        const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400));
+
+        pr_info("%s: triggering power-off...\n", __func__);
+
+        /* hijack uart1 and reset into sane state (38400,8n1,even parity) */
+        writel(0x83, UART1_REG(LCR));
+        writel(divisor & 0xff, UART1_REG(DLL));
+        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
+        writel(0x1b, UART1_REG(LCR));
+        writel(0x00, UART1_REG(IER));
+        writel(0x07, UART1_REG(FCR));
+        writel(0x00, UART1_REG(MCR));
+
+        /* Send the commands to shutdown the Terastation Pro II */
+        tsp2_miconsend(watchdogkill, sizeof(watchdogkill)) ;
+        tsp2_miconsend(shutdownwait, sizeof(shutdownwait)) ;
+        tsp2_miconsend(poweroff, sizeof(poweroff));
+}
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = {
+        {  0, MPP_PCIE_RST_OUTn },
+        {  1, MPP_UNUSED },
+        {  2, MPP_UNUSED },
+        {  3, MPP_UNUSED },
+        {  4, MPP_NAND },               /* BOOT NAND Flash REn */
+        {  5, MPP_NAND },               /* BOOT NAND Flash WEn */
+        {  6, MPP_NAND },               /* BOOT NAND Flash HREn[0] */
+        {  7, MPP_NAND },               /* BOOT NAND Flash WEn[0] */
+        {  8, MPP_GPIO },               /* MICON int */
+        {  9, MPP_GPIO },               /* RTC int */
+        { 10, MPP_UNUSED },
+        { 11, MPP_GPIO },               /* PCI Int A */
+        { 12, MPP_UNUSED },
+        { 13, MPP_GPIO },               /* UPS on UART0 enable */
+        { 14, MPP_GPIO },               /* UPS low battery detection */
+        { 15, MPP_UNUSED },
+        { 16, MPP_UART },               /* UART1 RXD */
+        { 17, MPP_UART },               /* UART1 TXD */
+        { 18, MPP_UART },               /* UART1 CTSn */
+        { 19, MPP_UART },               /* UART1 RTSn */
+        { -1 },
+};
+
+static void __init tsp2_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(tsp2_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_setup_dev_boot_win(TSP2_NOR_BOOT_BASE,
+                                   TSP2_NOR_BOOT_SIZE);
+        platform_device_register(&tsp2_nor_flash);
+
+        orion5x_ehci0_init();
+        orion5x_eth_init(&tsp2_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+        orion5x_uart1_init();
+
+        /* Get RTC IRQ and register the chip */
+        if (gpio_request(TSP2_RTC_GPIO, "rtc") == 0) {
+                if (gpio_direction_input(TSP2_RTC_GPIO) == 0)
+                        tsp2_i2c_rtc.irq = gpio_to_irq(TSP2_RTC_GPIO);
+                else
+                        gpio_free(TSP2_RTC_GPIO);
+        }
+        if (tsp2_i2c_rtc.irq == 0)
+                pr_warning("tsp2_init: failed to get RTC IRQ\n");
+        i2c_register_board_info(0, &tsp2_i2c_rtc, 1);
+
+        /* register Terastation Pro II specific power-off method */
+        pm_power_off = tsp2_power_off;
+}
+
+MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
+        /* Maintainer:  Sylver Bruneau <sylver.bruneau@googlemail.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = tsp2_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index ae0a5dccd2a1..1368e9fd1a06 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -103,8 +103,7 @@ static struct platform_device ts78xx_nor_boot_flash = {
  * Ethernet
  ****************************************************************************/
 static struct mv643xx_eth_platform_data ts78xx_eth_data = {
-        .phy_addr       = 0,
-        .force_phy_addr = 1,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
 };
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
index 83feac3147a6..c9abb8fbfa70 100644
--- a/arch/arm/mach-orion5x/tsx09-common.c
+++ b/arch/arm/mach-orion5x/tsx09-common.c
@@ -16,6 +16,7 @@
 #include <linux/timex.h>
 #include <linux/serial_reg.h>
 #include "tsx09-common.h"
+#include "common.h"
 
 /*****************************************************************************
  * QNAP TS-x09 specific power off method via UART1-attached PIC
@@ -26,7 +27,7 @@
 void qnap_tsx09_power_off(void)
 {
         /* 19200 baud divisor */
-        const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
+        const unsigned divisor = ((orion5x_tclk + (8 * 19200)) / (16 * 19200));
 
         pr_info("%s: triggering power-off...\n", __func__);
 
@@ -48,7 +49,7 @@ void qnap_tsx09_power_off(void)
  ****************************************************************************/
 
 struct mv643xx_eth_platform_data qnap_tsx09_eth_data = {
-        .phy_addr       = 8,
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
 static int __init qnap_tsx09_parse_hex_nibble(char n)
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index b6bc43e07eed..7ddc22c2bb54 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -92,7 +92,7 @@ static struct platform_device wnr854t_nor_flash = {
 };
 
 static struct mv643xx_eth_platform_data wnr854t_eth_data = {
-        .phy_addr       = -1,
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
         .speed          = SPEED_1000,
         .duplex         = DUPLEX_FULL,
 };
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index b10da17b3fbd..9a4fd5256462 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -100,7 +100,7 @@ static struct platform_device wrt350n_v2_nor_flash = {
 };
 
 static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
-        .phy_addr       = -1,
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
         .speed          = SPEED_1000,
         .duplex         = DUPLEX_FULL,
 };
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
index 24d036a24a72..898c0e88acbc 100644
--- a/arch/arm/mach-pnx4008/clock.c
+++ b/arch/arm/mach-pnx4008/clock.c
@@ -20,9 +20,9 @@
 #include <linux/device.h>
 #include <linux/err.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <mach/clock.h>
 #include "clock.h"
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 3ba46ede9bbd..45734bb880a8 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -25,9 +25,9 @@
 #include <linux/serial_8250.h>
 #include <linux/device.h>
 #include <linux/spi/spi.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
index 833c56be7344..ac2f70eddb9e 100644
--- a/arch/arm/mach-pnx4008/dma.c
+++ b/arch/arm/mach-pnx4008/dma.c
@@ -21,12 +21,12 @@
 #include <linux/err.h>
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/dma.h>
 #include <asm/dma-mapping.h>
-#include <asm/io.h>
 #include <asm/mach/dma.h>
 #include <mach/clock.h>
 
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
index fb51f7279e95..015cc21d5f55 100644
--- a/arch/arm/mach-pnx4008/gpio.c
+++ b/arch/arm/mach-pnx4008/gpio.c
@@ -17,7 +17,7 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/platform.h>
 #include <mach/gpio.h>
 
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h
index 8985a4622b8c..e12e7abfcbcf 100644
--- a/arch/arm/mach-pnx4008/include/mach/system.h
+++ b/arch/arm/mach-pnx4008/include/mach/system.h
@@ -21,8 +21,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <mach/platform.h>
 
 static void arch_idle(void)
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
index 956fbd8e977c..5ff0196c0f16 100644
--- a/arch/arm/mach-pnx4008/include/mach/timex.h
+++ b/arch/arm/mach-pnx4008/include/mach/timex.h
@@ -14,8 +14,8 @@
 #ifndef __PNX4008_TIMEX_H
 #define __PNX4008_TIMEX_H
 
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #define CLOCK_TICK_RATE         1000000
 
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 5c4f55af5d4b..a9ce02b4bf17 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -23,8 +23,8 @@
 #include <linux/ioport.h>
 #include <linux/device.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
index f970906d8848..b3d8d53e32ef 100644
--- a/arch/arm/mach-pnx4008/pm.c
+++ b/arch/arm/mach-pnx4008/pm.c
@@ -18,8 +18,8 @@
 #include <linux/suspend.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/cacheflush.h>
 #include <mach/pm.h>
 #include <mach/clock.h>
diff --git a/arch/arm/mach-pnx4008/serial.c b/arch/arm/mach-pnx4008/serial.c
index 9be84bbb30e8..f40961e51914 100644
--- a/arch/arm/mach-pnx4008/serial.c
+++ b/arch/arm/mach-pnx4008/serial.c
@@ -12,8 +12,7 @@
 
 #include <linux/kernel.h>
 #include <linux/types.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 #include <mach/platform.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index 180975244f96..fc0ba183fe12 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -22,10 +22,10 @@
 #include <linux/time.h>
 #include <linux/timex.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/mach/time.h>
 #include <asm/errno.h>
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index e8ee7ec9ff6d..f27f6b3d6e6f 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -38,16 +38,23 @@ config ARCH_LUBBOCK
         bool "Intel DBPXA250 Development Platform"
         select PXA25x
         select SA1111
+        select PXA_HAVE_BOARD_IRQS
 
 config MACH_LOGICPD_PXA270
         bool "LogicPD PXA270 Card Engine Development Platform"
         select PXA27x
         select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
 
 config MACH_MAINSTONE
         bool "Intel HCDDBBVA0 Development Platform"
         select PXA27x
         select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
+
+config MACH_MP900C
+        bool "Nec Mobilepro 900/c"
+        select PXA25x
 
 config ARCH_PXA_IDP
         bool "Accelent Xscale IDP"
@@ -114,10 +121,21 @@ config MACH_TOSA
         bool "Enable Sharp SL-6000x (Tosa) Support"
         depends on PXA_SHARPSL
         select PXA25x
+        select PXA_HAVE_BOARD_IRQS
+
+config ARCH_VIPER
+        bool "Arcom/Eurotech VIPER SBC"
+        select PXA25x
+        select ISA
+        select I2C_GPIO
+        select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
+        select PXA_HAVE_ISA_IRQS
 
 config ARCH_PXA_ESERIES
         bool "PXA based Toshiba e-series PDAs"
         select PXA25x
+        select PXA_HAVE_BOARD_IRQS
 
 config MACH_E330
         bool "Toshiba e330"
@@ -170,13 +188,41 @@ config MACH_E800
           Say Y here if you intend to run this kernel on a Toshiba
           e800 family PDA.
 
+config TRIZEPS_PXA
+        bool "PXA based Keith und Koep Trizeps DIMM-Modules"
+
 config MACH_TRIZEPS4
         bool "Keith und Koep Trizeps4 DIMM-Module"
+        depends on TRIZEPS_PXA
+        select TRIZEPS_PCMCIA
         select PXA27x
 
-config MACH_TRIZEPS4_CONXS
+config MACH_TRIZEPS4WL
+        bool "Keith und Koep Trizeps4-WL DIMM-Module"
+        depends on TRIZEPS_PXA
+        select TRIZEPS_PCMCIA
+        select PXA27x
+        select PXA_SSP
+
+choice
+        prompt "Select base board for Trizeps module"
+        depends on TRIZEPS_PXA
+
+config MACH_TRIZEPS_CONXS
         bool "ConXS Eval Board"
-        depends on MACH_TRIZEPS4
+
+config MACH_TRIZEPS_UCONXS
+        bool "uConXS Eval Board"
+
+config MACH_TRIZEPS_ANY
+        bool "another Board"
+
+endchoice
+
+config TRIZEPS_PCMCIA
+        bool
+        help
+          Enable PCMCIA support for Trizeps modules
 
 config MACH_EM_X270
         bool "CompuLab EM-x270 platform"
@@ -189,6 +235,7 @@ config MACH_COLIBRI
 config MACH_ZYLONITE
         bool "PXA3xx Development Platform (aka Zylonite)"
         select PXA3xx
+        select PXA_SSP
         select HAVE_PWM
 
 config MACH_LITTLETON
@@ -207,20 +254,42 @@ config MACH_SAAR
         select PXA930
 
 config MACH_ARMCORE
-        bool "CompuLab CM-X270 modules"
+        bool "CompuLab CM-X255/CM-X270 modules"
         select PXA27x
         select IWMMXT
+        select ZONE_DMA if PCI
+        select PXA25x
+        select PXA_SSP
+
+config MACH_CM_X300
+        bool "CompuLab CM-X300 modules"
+        select PXA3xx
+        select CPU_PXA300
 
 config MACH_MAGICIAN
         bool "Enable HTC Magician Support"
         select PXA27x
         select IWMMXT
+        select PXA_HAVE_BOARD_IRQS
+
+config MACH_MIOA701
+        bool "Mitac Mio A701 Support"
+        select PXA27x
+        select IWMMXT
+        select LEDS_GPIO
+        select HAVE_PWM
+        select GPIO_SYSFS
+        help
+          Say Y here if you intend to run this kernel on a
+          MIO A701. Currently there is only basic support
+          for this PDA.
 
 config MACH_PCM027
         bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
         select PXA27x
         select IWMMXT
         select PXA_SSP
+        select PXA_HAVE_BOARD_IRQS
 
 config ARCH_PXA_PALM
         bool "PXA based Palm PDAs"
@@ -236,6 +305,16 @@ config MACH_PALMTX
           Say Y here if you intend to run this kernel on a Palm T|X
           handheld computer.
 
+config MACH_PALMZ72
+        bool "Palm Zire 72"
+        default y
+        depends on ARCH_PXA_PALM
+        select PXA27x
+        select IWMMXT
+        help
+          Say Y here if you intend to run this kernel on Palm Zire 72
+          handheld computer.
+
 config MACH_PCM990_BASEBOARD
         bool "PHYTEC PCM-990 development board"
         select HAVE_PWM
@@ -256,6 +335,9 @@ config PCM990_DISPLAY_NONE
 
 endchoice
 
+config MACH_AM200EPD
+        depends on MACH_GUMSTIX_F
+        bool "Enable AM200EPD board support"
 
 config PXA_EZX
         bool "Motorola EZX Platform"
@@ -343,4 +425,10 @@ config TOSA_BT
           This is a simple driver that is able to control
           the state of built in bluetooth chip on tosa.
 
+config PXA_HAVE_BOARD_IRQS
+        bool
+
+config PXA_HAVE_ISA_IRQS
+        bool
+
 endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 99ecbe7f8506..d31c9979cfa3 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -6,7 +6,12 @@
 obj-y                           += clock.o devices.o generic.o irq.o dma.o \
                                    time.o gpio.o reset.o
 obj-$(CONFIG_PM)                += pm.o sleep.o standby.o
-obj-$(CONFIG_CPU_FREQ)          += cpu-pxa.o
+
+ifeq ($(CONFIG_CPU_FREQ),y)
+obj-$(CONFIG_PXA25x)            += cpufreq-pxa2xx.o
+obj-$(CONFIG_PXA27x)            += cpufreq-pxa2xx.o
+obj-$(CONFIG_PXA3xx)            += cpufreq-pxa3xx.o
+endif
 
 # Generic drivers that other drivers may depend upon
 obj-$(CONFIG_PXA_SSP)           += ssp.o
@@ -22,27 +27,33 @@ obj-$(CONFIG_CPU_PXA930)	+= pxa930.o
 
 # Specific board support
 obj-$(CONFIG_ARCH_GUMSTIX)      += gumstix.o
+obj-$(CONFIG_MACH_AM200EPD)     += am200epd.o
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
+obj-$(CONFIG_MACH_MP900C)       += mp900.o
 obj-$(CONFIG_ARCH_PXA_IDP)      += idp.o
 obj-$(CONFIG_MACH_TRIZEPS4)     += trizeps4.o
 obj-$(CONFIG_MACH_COLIBRI)      += colibri.o
-obj-$(CONFIG_PXA_SHARP_C7xx)    += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
-obj-$(CONFIG_PXA_SHARP_Cxx00)   += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
-obj-$(CONFIG_MACH_AKITA)        += akita-ioexp.o
-obj-$(CONFIG_MACH_POODLE)       += poodle.o corgi_ssp.o
+obj-$(CONFIG_PXA_SHARP_C7xx)    += corgi.o sharpsl_pm.o corgi_pm.o
+obj-$(CONFIG_PXA_SHARP_Cxx00)   += spitz.o sharpsl_pm.o spitz_pm.o
+obj-$(CONFIG_MACH_POODLE)       += poodle.o
 obj-$(CONFIG_MACH_PCM027)       += pcm027.o
 obj-$(CONFIG_MACH_PCM990_BASEBOARD)     += pcm990-baseboard.o
 obj-$(CONFIG_MACH_TOSA)         += tosa.o
 obj-$(CONFIG_MACH_EM_X270)      += em-x270.o
 obj-$(CONFIG_MACH_MAGICIAN)     += magician.o
-obj-$(CONFIG_ARCH_PXA_ESERIES)  += eseries.o eseries_udc.o
-obj-$(CONFIG_MACH_E740)         += e740_lcd.o
-obj-$(CONFIG_MACH_E750)         += e750_lcd.o
-obj-$(CONFIG_MACH_E400)         += e400_lcd.o
-obj-$(CONFIG_MACH_E800)         += e800_lcd.o
+obj-$(CONFIG_MACH_MIOA701)      += mioa701.o mioa701_bootresume.o
+obj-$(CONFIG_ARCH_PXA_ESERIES)  += eseries.o
+obj-$(CONFIG_MACH_E330)         += e330.o
+obj-$(CONFIG_MACH_E350)         += e350.o
+obj-$(CONFIG_MACH_E740)         += e740.o
+obj-$(CONFIG_MACH_E750)         += e750.o
+obj-$(CONFIG_MACH_E400)         += e400.o
+obj-$(CONFIG_MACH_E800)         += e800.o
 obj-$(CONFIG_MACH_PALMTX)       += palmtx.o
+obj-$(CONFIG_MACH_PALMZ72)      += palmz72.o
+obj-$(CONFIG_ARCH_VIPER)        += viper.o
 
 ifeq ($(CONFIG_MACH_ZYLONITE),y)
   obj-y                         += zylonite.o
@@ -53,7 +64,8 @@ obj-$(CONFIG_MACH_LITTLETON)	+= littleton.o
 obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
 obj-$(CONFIG_MACH_SAAR)         += saar.o
 
-obj-$(CONFIG_MACH_ARMCORE)      += cm-x270.o
+obj-$(CONFIG_MACH_ARMCORE)      += cm-x2xx.o cm-x255.o cm-x270.o
+obj-$(CONFIG_MACH_CM_X300)      += cm-x300.o
 obj-$(CONFIG_PXA_EZX)           += ezx.o
 
 # Support for blinky lights
@@ -61,12 +73,11 @@ led-y := leds.o
 led-$(CONFIG_ARCH_LUBBOCK)      += leds-lubbock.o
 led-$(CONFIG_MACH_MAINSTONE)    += leds-mainstone.o
 led-$(CONFIG_ARCH_PXA_IDP)      += leds-idp.o
-led-$(CONFIG_MACH_TRIZEPS4)     += leds-trizeps4.o
 
 obj-$(CONFIG_LEDS)              += $(led-y)
 
 ifeq ($(CONFIG_PCI),y)
-obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
+obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o
 endif
 
 obj-$(CONFIG_TOSA_BT)           += tosa-bt.o
diff --git a/arch/arm/mach-pxa/akita-ioexp.c b/arch/arm/mach-pxa/akita-ioexp.c
deleted file mode 100644
index 5c67b188a3ba..000000000000
--- a/arch/arm/mach-pxa/akita-ioexp.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * Support for the Extra GPIOs on the Sharp SL-C1000 (Akita)
- * (uses a Maxim MAX7310 8 Port IO Expander)
- *
- * Copyright 2005 Openedhand Ltd.
- *
- * Author: Richard Purdie <richard@openedhand.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/i2c.h>
-#include <linux/slab.h>
-#include <linux/workqueue.h>
-#include <mach/akita.h>
-
-/* MAX7310 Regiser Map */
-#define MAX7310_INPUT    0x00
-#define MAX7310_OUTPUT   0x01
-#define MAX7310_POLINV   0x02
-#define MAX7310_IODIR    0x03 /* 1 = Input, 0 = Output */
-#define MAX7310_TIMEOUT  0x04
-
-/* Addresses to scan */
-static const unsigned short normal_i2c[] = { 0x18, I2C_CLIENT_END };
-
-/* I2C Magic */
-I2C_CLIENT_INSMOD;
-
-static int max7310_write(struct i2c_client *client, int address, int data);
-static struct i2c_client max7310_template;
-static void akita_ioexp_work(struct work_struct *private_);
-
-static struct device *akita_ioexp_device;
-static unsigned char ioexp_output_value = AKITA_IOEXP_IO_OUT;
-DECLARE_WORK(akita_ioexp, akita_ioexp_work);
-
-
-/*
- * MAX7310 Access
- */
-static int max7310_config(struct device *dev, int iomode, int polarity)
-{
-        int ret;
-        struct i2c_client *client = to_i2c_client(dev);
-
-        ret = max7310_write(client, MAX7310_POLINV, polarity);
-        if (ret < 0)
-                return ret;
-        ret = max7310_write(client, MAX7310_IODIR, iomode);
-        return ret;
-}
-
-static int max7310_set_ouputs(struct device *dev, int outputs)
-{
-        struct i2c_client *client = to_i2c_client(dev);
-
-        return max7310_write(client, MAX7310_OUTPUT, outputs);
-}
-
-/*
- * I2C Functions
- */
-static int max7310_write(struct i2c_client *client, int address, int value)
-{
-        u8 data[2];
-
-        data[0] = address & 0xff;
-        data[1] = value & 0xff;
-
-        if (i2c_master_send(client, data, 2) == 2)
-                return 0;
-        return -1;
-}
-
-static int max7310_detect(struct i2c_adapter *adapter, int address, int kind)
-{
-        struct i2c_client *new_client;
-        int err;
-
-        if (!(new_client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL)))
-                return -ENOMEM;
-
-        max7310_template.adapter = adapter;
-        max7310_template.addr = address;
-
-        memcpy(new_client, &max7310_template, sizeof(struct i2c_client));
-
-        if ((err = i2c_attach_client(new_client))) {
-                kfree(new_client);
-                return err;
-        }
-
-        max7310_config(&new_client->dev, AKITA_IOEXP_IO_DIR, 0);
-        akita_ioexp_device = &new_client->dev;
-        schedule_work(&akita_ioexp);
-
-        return 0;
-}
-
-static int max7310_attach_adapter(struct i2c_adapter *adapter)
-{
-        return i2c_probe(adapter, &addr_data, max7310_detect);
-}
-
-static int max7310_detach_client(struct i2c_client *client)
-{
-        int err;
-
-        akita_ioexp_device = NULL;
-
-        if ((err = i2c_detach_client(client)))
-                return err;
-
-        kfree(client);
-        return 0;
-}
-
-static struct i2c_driver max7310_i2c_driver = {
-        .driver = {
-                .name   = "akita-max7310",
-        },
-        .id             = I2C_DRIVERID_AKITAIOEXP,
-        .attach_adapter = max7310_attach_adapter,
-        .detach_client  = max7310_detach_client,
-};
-
-static struct i2c_client max7310_template = {
-        name:   "akita-max7310",
-        driver: &max7310_i2c_driver,
-};
-
-void akita_set_ioexp(struct device *dev, unsigned char bit)
-{
-        ioexp_output_value |= bit;
-
-        if (akita_ioexp_device)
-                schedule_work(&akita_ioexp);
-        return;
-}
-
-void akita_reset_ioexp(struct device *dev, unsigned char bit)
-{
-        ioexp_output_value &= ~bit;
-
-        if (akita_ioexp_device)
-                schedule_work(&akita_ioexp);
-        return;
-}
-
-EXPORT_SYMBOL(akita_set_ioexp);
-EXPORT_SYMBOL(akita_reset_ioexp);
-
-static void akita_ioexp_work(struct work_struct *private_)
-{
-        if (akita_ioexp_device)
-                max7310_set_ouputs(akita_ioexp_device, ioexp_output_value);
-}
-
-
-#ifdef CONFIG_PM
-static int akita_ioexp_suspend(struct platform_device *pdev, pm_message_t state)
-{
-        flush_scheduled_work();
-        return 0;
-}
-
-static int akita_ioexp_resume(struct platform_device *pdev)
-{
-        schedule_work(&akita_ioexp);
-        return 0;
-}
-#else
-#define akita_ioexp_suspend NULL
-#define akita_ioexp_resume NULL
-#endif
-
-static int __init akita_ioexp_probe(struct platform_device *pdev)
-{
-        return i2c_add_driver(&max7310_i2c_driver);
-}
-
-static int akita_ioexp_remove(struct platform_device *pdev)
-{
-        i2c_del_driver(&max7310_i2c_driver);
-        return 0;
-}
-
-static struct platform_driver akita_ioexp_driver = {
-        .probe          = akita_ioexp_probe,
-        .remove         = akita_ioexp_remove,
-        .suspend        = akita_ioexp_suspend,
-        .resume         = akita_ioexp_resume,
-        .driver         = {
-                .name   = "akita-ioexp",
-        },
-};
-
-static int __init akita_ioexp_init(void)
-{
-        return platform_driver_register(&akita_ioexp_driver);
-}
-
-static void __exit akita_ioexp_exit(void)
-{
-        platform_driver_unregister(&akita_ioexp_driver);
-}
-
-MODULE_AUTHOR("Richard Purdie <rpurdie@openedhand.com>");
-MODULE_DESCRIPTION("Akita IO-Expander driver");
-MODULE_LICENSE("GPL");
-
-fs_initcall(akita_ioexp_init);
-module_exit(akita_ioexp_exit);
-
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
new file mode 100644
index 000000000000..b965085a37b9
--- /dev/null
+++ b/arch/arm/mach-pxa/am200epd.c
@@ -0,0 +1,374 @@
+/*
+ * am200epd.c -- Platform device for AM200 EPD kit
+ *
+ * Copyright (C) 2008, Jaya Kumar
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ *
+ * Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
+ *
+ * This work was made possible by help and equipment support from E-Ink
+ * Corporation. http://support.eink.com/community
+ *
+ * This driver is written to be used with the Metronome display controller.
+ * on the AM200 EPD prototype kit/development kit with an E-Ink 800x600
+ * Vizplex EPD on a Gumstix board using the Lyre interface board.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include <mach/pxafb.h>
+
+#include <video/metronomefb.h>
+
+static unsigned int panel_type = 6;
+static struct platform_device *am200_device;
+static struct metronome_board am200_board;
+
+static struct pxafb_mode_info am200_fb_mode_9inch7 = {
+        .pixclock       = 40000,
+        .xres           = 1200,
+        .yres           = 842,
+        .bpp            = 16,
+        .hsync_len      = 2,
+        .left_margin    = 2,
+        .right_margin   = 2,
+        .vsync_len      = 1,
+        .upper_margin   = 2,
+        .lower_margin   = 25,
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+};
+
+static struct pxafb_mode_info am200_fb_mode_8inch = {
+        .pixclock       = 40000,
+        .xres           = 1088,
+        .yres           = 791,
+        .bpp            = 16,
+        .hsync_len      = 28,
+        .left_margin    = 8,
+        .right_margin   = 30,
+        .vsync_len      = 8,
+        .upper_margin   = 10,
+        .lower_margin   = 8,
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+};
+
+static struct pxafb_mode_info am200_fb_mode_6inch = {
+        .pixclock       = 40189,
+        .xres           = 832,
+        .yres           = 622,
+        .bpp            = 16,
+        .hsync_len      = 28,
+        .left_margin    = 34,
+        .right_margin   = 34,
+        .vsync_len      = 25,
+        .upper_margin   = 0,
+        .lower_margin   = 2,
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+};
+
+static struct pxafb_mach_info am200_fb_info = {
+        .modes          = &am200_fb_mode_6inch,
+        .num_modes      = 1,
+        .lcd_conn       = LCD_TYPE_COLOR_TFT | LCD_PCLK_EDGE_FALL |
+                          LCD_AC_BIAS_FREQ(24),
+};
+
+/* register offsets for gpio control */
+#define LED_GPIO_PIN 51
+#define STDBY_GPIO_PIN 48
+#define RST_GPIO_PIN 49
+#define RDY_GPIO_PIN 32
+#define ERR_GPIO_PIN 17
+#define PCBPWR_GPIO_PIN 16
+static int gpios[] = { LED_GPIO_PIN , STDBY_GPIO_PIN , RST_GPIO_PIN,
+                        RDY_GPIO_PIN, ERR_GPIO_PIN, PCBPWR_GPIO_PIN };
+static char *gpio_names[] = { "LED" , "STDBY" , "RST", "RDY", "ERR", "PCBPWR" };
+
+static int am200_init_gpio_regs(struct metronomefb_par *par)
+{
+        int i;
+        int err;
+
+        for (i = 0; i < ARRAY_SIZE(gpios); i++) {
+                err = gpio_request(gpios[i], gpio_names[i]);
+                if (err) {
+                        dev_err(&am200_device->dev, "failed requesting "
+                                "gpio %s, err=%d\n", gpio_names[i], err);
+                        goto err_req_gpio;
+                }
+        }
+
+        gpio_direction_output(LED_GPIO_PIN, 0);
+        gpio_direction_output(STDBY_GPIO_PIN, 0);
+        gpio_direction_output(RST_GPIO_PIN, 0);
+
+        gpio_direction_input(RDY_GPIO_PIN);
+        gpio_direction_input(ERR_GPIO_PIN);
+
+        gpio_direction_output(PCBPWR_GPIO_PIN, 0);
+
+        return 0;
+
+err_req_gpio:
+        while (i > 0)
+                gpio_free(gpios[i--]);
+
+        return err;
+}
+
+static void am200_cleanup(struct metronomefb_par *par)
+{
+        int i;
+
+        free_irq(IRQ_GPIO(RDY_GPIO_PIN), par);
+
+        for (i = 0; i < ARRAY_SIZE(gpios); i++)
+                gpio_free(gpios[i]);
+}
+
+static int am200_share_video_mem(struct fb_info *info)
+{
+        /* rough check if this is our desired fb and not something else */
+        if ((info->var.xres != am200_fb_info.modes->xres)
+                || (info->var.yres != am200_fb_info.modes->yres))
+                return 0;
+
+        /* we've now been notified that we have our new fb */
+        am200_board.metromem = info->screen_base;
+        am200_board.host_fbinfo = info;
+
+        /* try to refcount host drv since we are the consumer after this */
+        if (!try_module_get(info->fbops->owner))
+                return -ENODEV;
+
+        return 0;
+}
+
+static int am200_unshare_video_mem(struct fb_info *info)
+{
+        dev_dbg(&am200_device->dev, "ENTER %s\n", __func__);
+
+        if (info != am200_board.host_fbinfo)
+                return 0;
+
+        module_put(am200_board.host_fbinfo->fbops->owner);
+        return 0;
+}
+
+static int am200_fb_notifier_callback(struct notifier_block *self,
+                                 unsigned long event, void *data)
+{
+        struct fb_event *evdata = data;
+        struct fb_info *info = evdata->info;
+
+        dev_dbg(&am200_device->dev, "ENTER %s\n", __func__);
+
+        if (event == FB_EVENT_FB_REGISTERED)
+                return am200_share_video_mem(info);
+        else if (event == FB_EVENT_FB_UNREGISTERED)
+                return am200_unshare_video_mem(info);
+
+        return 0;
+}
+
+static struct notifier_block am200_fb_notif = {
+        .notifier_call = am200_fb_notifier_callback,
+};
+
+/* this gets called as part of our init. these steps must be done now so
+ * that we can use set_pxa_fb_info */
+static void __init am200_presetup_fb(void)
+{
+        int fw;
+        int fh;
+        int padding_size;
+        int totalsize;
+
+        switch (panel_type) {
+        case 6:
+                am200_fb_info.modes = &am200_fb_mode_6inch;
+                break;
+        case 8:
+                am200_fb_info.modes = &am200_fb_mode_8inch;
+                break;
+        case 97:
+                am200_fb_info.modes = &am200_fb_mode_9inch7;
+                break;
+        default:
+                dev_err(&am200_device->dev, "invalid panel_type selection,"
+                                                " setting to 6\n");
+                am200_fb_info.modes = &am200_fb_mode_6inch;
+                break;
+        }
+
+        /* the frame buffer is divided as follows:
+        command | CRC | padding
+        16kb waveform data | CRC | padding
+        image data | CRC
+        */
+
+        fw = am200_fb_info.modes->xres;
+        fh = am200_fb_info.modes->yres;
+
+        /* waveform must be 16k + 2 for checksum */
+        am200_board.wfm_size = roundup(16*1024 + 2, fw);
+
+        padding_size = PAGE_SIZE + (4 * fw);
+
+        /* total is 1 cmd , 1 wfm, padding and image */
+        totalsize = fw + am200_board.wfm_size + padding_size + (fw*fh);
+
+        /* save this off because we're manipulating fw after this and
+         * we'll need it when we're ready to setup the framebuffer */
+        am200_board.fw = fw;
+        am200_board.fh = fh;
+
+        /* the reason we do this adjustment is because we want to acquire
+         * more framebuffer memory without imposing custom awareness on the
+         * underlying pxafb driver */
+        am200_fb_info.modes->yres = DIV_ROUND_UP(totalsize, fw);
+
+        /* we divide since we told the LCD controller we're 16bpp */
+        am200_fb_info.modes->xres /= 2;
+
+        set_pxa_fb_info(&am200_fb_info);
+
+}
+
+/* this gets called by metronomefb as part of its init, in our case, we
+ * have already completed initial framebuffer init in presetup_fb so we
+ * can just setup the fb access pointers */
+static int am200_setup_fb(struct metronomefb_par *par)
+{
+        int fw;
+        int fh;
+
+        fw = am200_board.fw;
+        fh = am200_board.fh;
+
+        /* metromem was set up by the notifier in share_video_mem so now
+         * we can use its value to calculate the other entries */
+        par->metromem_cmd = (struct metromem_cmd *) am200_board.metromem;
+        par->metromem_wfm = am200_board.metromem + fw;
+        par->metromem_img = par->metromem_wfm + am200_board.wfm_size;
+        par->metromem_img_csum = (u16 *) (par->metromem_img + (fw * fh));
+        par->metromem_dma = am200_board.host_fbinfo->fix.smem_start;
+
+        return 0;
+}
+
+static int am200_get_panel_type(void)
+{
+        return panel_type;
+}
+
+static irqreturn_t am200_handle_irq(int irq, void *dev_id)
+{
+        struct metronomefb_par *par = dev_id;
+
+        wake_up_interruptible(&par->waitq);
+        return IRQ_HANDLED;
+}
+
+static int am200_setup_irq(struct fb_info *info)
+{
+        int ret;
+
+        ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am200_handle_irq,
+                                IRQF_DISABLED|IRQF_TRIGGER_FALLING,
+                                "AM200", info->par);
+        if (ret)
+                dev_err(&am200_device->dev, "request_irq failed: %d\n", ret);
+
+        return ret;
+}
+
+static void am200_set_rst(struct metronomefb_par *par, int state)
+{
+        gpio_set_value(RST_GPIO_PIN, state);
+}
+
+static void am200_set_stdby(struct metronomefb_par *par, int state)
+{
+        gpio_set_value(STDBY_GPIO_PIN, state);
+}
+
+static int am200_wait_event(struct metronomefb_par *par)
+{
+        return wait_event_timeout(par->waitq, gpio_get_value(RDY_GPIO_PIN), HZ);
+}
+
+static int am200_wait_event_intr(struct metronomefb_par *par)
+{
+        return wait_event_interruptible_timeout(par->waitq,
+                                        gpio_get_value(RDY_GPIO_PIN), HZ);
+}
+
+static struct metronome_board am200_board = {
+        .owner                  = THIS_MODULE,
+        .setup_irq              = am200_setup_irq,
+        .setup_io               = am200_init_gpio_regs,
+        .setup_fb               = am200_setup_fb,
+        .set_rst                = am200_set_rst,
+        .set_stdby              = am200_set_stdby,
+        .met_wait_event         = am200_wait_event,
+        .met_wait_event_intr    = am200_wait_event_intr,
+        .get_panel_type         = am200_get_panel_type,
+        .cleanup                = am200_cleanup,
+};
+
+static int __init am200_init(void)
+{
+        int ret;
+
+        /* before anything else, we request notification for any fb
+         * creation events */
+        fb_register_client(&am200_fb_notif);
+
+        /* request our platform independent driver */
+        request_module("metronomefb");
+
+        am200_device = platform_device_alloc("metronomefb", -1);
+        if (!am200_device)
+                return -ENOMEM;
+
+        /* the am200_board that will be seen by metronomefb is a copy */
+        platform_device_add_data(am200_device, &am200_board,
+                                        sizeof(am200_board));
+
+        /* this _add binds metronomefb to am200. metronomefb refcounts am200 */
+        ret = platform_device_add(am200_device);
+
+        if (ret) {
+                platform_device_put(am200_device);
+                fb_unregister_client(&am200_fb_notif);
+                return ret;
+        }
+
+        am200_presetup_fb();
+
+        return 0;
+}
+
+module_param(panel_type, uint, 0);
+MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97");
+
+module_init(am200_init);
+
+MODULE_DESCRIPTION("board driver for am200 metronome epd kit");
+MODULE_AUTHOR("Jaya Kumar");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c
new file mode 100644
index 000000000000..83a4cdf08176
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x255.c
@@ -0,0 +1,258 @@
+/*
+ * linux/arch/arm/mach-pxa/cm-x255.c
+ *
+ * Copyright (C) 2007, 2008 CompuLab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand-gpio.h>
+
+#include <linux/spi/spi.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/pxa2xx_spi.h>
+#include <mach/bitfield.h>
+
+#include "generic.h"
+
+#define GPIO_NAND_CS    (5)
+#define GPIO_NAND_ALE   (4)
+#define GPIO_NAND_CLE   (3)
+#define GPIO_NAND_RB    (10)
+
+static unsigned long cmx255_pin_config[] = {
+        /* AC'97 */
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+
+        /* STUART */
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+
+        /* SSP1 */
+        GPIO23_SSP1_SCLK,
+        GPIO24_SSP1_SFRM,
+        GPIO25_SSP1_TXD,
+        GPIO26_SSP1_RXD,
+
+        /* SSP2 */
+        GPIO81_SSP2_CLK_OUT,
+        GPIO82_SSP2_FRM_OUT,
+        GPIO83_SSP2_TXD,
+        GPIO84_SSP2_RXD,
+
+        /* PC Card */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO52_nPCE_1,
+        GPIO53_nPCE_2,
+        GPIO54_nPSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* SDRAM and local bus */
+        GPIO15_nCS_1,
+        GPIO78_nCS_2,
+        GPIO79_nCS_3,
+        GPIO80_nCS_4,
+        GPIO33_nCS_5,
+        GPIO18_RDY,
+
+        /* GPIO */
+        GPIO0_GPIO      | WAKEUP_ON_EDGE_BOTH,
+        GPIO9_GPIO,                             /* PC card reset */
+
+        /* NAND controls */
+        GPIO5_GPIO      | MFP_LPM_DRIVE_HIGH,   /* NAND CE# */
+        GPIO4_GPIO      | MFP_LPM_DRIVE_LOW,    /* NAND ALE */
+        GPIO3_GPIO      | MFP_LPM_DRIVE_LOW,    /* NAND CLE */
+        GPIO10_GPIO,                            /* NAND Ready/Busy */
+
+        /* interrupts */
+        GPIO22_GPIO,    /* DM9000 interrupt */
+};
+
+#if defined(CONFIG_SPI_PXA2XX)
+static struct pxa2xx_spi_master pxa_ssp_master_info = {
+        .num_chipselect = 1,
+};
+
+static struct spi_board_info spi_board_info[] __initdata = {
+        [0] = {
+                .modalias       = "rtc-max6902",
+                .max_speed_hz   = 1000000,
+                .bus_num        = 1,
+                .chip_select    = 0,
+        },
+};
+
+static void __init cmx255_init_rtc(void)
+{
+        pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
+        spi_register_board_info(ARRAY_AND_SIZE(spi_board_info));
+}
+#else
+static inline void cmx255_init_rtc(void) {}
+#endif
+
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition cmx255_nor_partitions[] = {
+        {
+                .name           = "ARMmon",
+                .size           = 0x00030000,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE  /* force read-only */
+        } , {
+                .name           = "ARMmon setup block",
+                .size           = 0x00010000,
+                .offset         = MTDPART_OFS_APPEND,
+                .mask_flags     = MTD_WRITEABLE  /* force read-only */
+        } , {
+                .name           = "kernel",
+                .size           = 0x00160000,
+                .offset         = MTDPART_OFS_APPEND,
+        } , {
+                .name           = "ramdisk",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = MTDPART_OFS_APPEND
+        }
+};
+
+static struct physmap_flash_data cmx255_nor_flash_data[] = {
+        {
+                .width          = 2,    /* bankwidth in bytes */
+                .parts          = cmx255_nor_partitions,
+                .nr_parts       = ARRAY_SIZE(cmx255_nor_partitions)
+        }
+};
+
+static struct resource cmx255_nor_resource = {
+        .start  = PXA_CS0_PHYS,
+        .end    = PXA_CS0_PHYS + SZ_8M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device cmx255_nor = {
+        .name   = "physmap-flash",
+        .id     = -1,
+        .dev    = {
+                .platform_data = cmx255_nor_flash_data,
+        },
+        .resource = &cmx255_nor_resource,
+        .num_resources = 1,
+};
+
+static void __init cmx255_init_nor(void)
+{
+        platform_device_register(&cmx255_nor);
+}
+#else
+static inline void cmx255_init_nor(void) {}
+#endif
+
+#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
+static struct resource cmx255_nand_resource[] = {
+        [0] = {
+                .start = PXA_CS1_PHYS,
+                .end   = PXA_CS1_PHYS + 11,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = PXA_CS5_PHYS,
+                .end   = PXA_CS5_PHYS + 3,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static struct mtd_partition cmx255_nand_parts[] = {
+        [0] = {
+                .name   = "cmx255-nand",
+                .size   = MTDPART_SIZ_FULL,
+                .offset = 0,
+        },
+};
+
+static struct gpio_nand_platdata cmx255_nand_platdata = {
+        .gpio_nce = GPIO_NAND_CS,
+        .gpio_cle = GPIO_NAND_CLE,
+        .gpio_ale = GPIO_NAND_ALE,
+        .gpio_rdy = GPIO_NAND_RB,
+        .gpio_nwp = -1,
+        .parts = cmx255_nand_parts,
+        .num_parts = ARRAY_SIZE(cmx255_nand_parts),
+        .chip_delay = 25,
+};
+
+static struct platform_device cmx255_nand = {
+        .name           = "gpio-nand",
+        .num_resources  = ARRAY_SIZE(cmx255_nand_resource),
+        .resource       = cmx255_nand_resource,
+        .id             = -1,
+        .dev            = {
+                .platform_data = &cmx255_nand_platdata,
+        }
+};
+
+static void __init cmx255_init_nand(void)
+{
+        platform_device_register(&cmx255_nand);
+}
+#else
+static inline void cmx255_init_nand(void) {}
+#endif
+
+void __init cmx255_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config));
+
+        cmx255_init_rtc();
+        cmx255_init_nor();
+        cmx255_init_nand();
+}
diff --git a/arch/arm/mach-pxa/cm-x270-pci.h b/arch/arm/mach-pxa/cm-x270-pci.h
deleted file mode 100644
index 48f532f4cb51..000000000000
--- a/arch/arm/mach-pxa/cm-x270-pci.h
+++ /dev/null
@@ -1,13 +0,0 @@
-extern void __cmx270_pci_init_irq(int irq_gpio);
-extern void __cmx270_pci_suspend(void);
-extern void __cmx270_pci_resume(void);
-
-#ifdef CONFIG_PCI
-#define cmx270_pci_init_irq(x) __cmx270_pci_init_irq(x)
-#define cmx270_pci_suspend(x) __cmx270_pci_suspend(x)
-#define cmx270_pci_resume(x) __cmx270_pci_resume(x)
-#else
-#define cmx270_pci_init_irq(x) do {} while (0)
-#define cmx270_pci_suspend(x) do {} while (0)
-#define cmx270_pci_resume(x) do {} while (0)
-#endif
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index af003a269534..a82dad1a8cc8 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -14,46 +14,22 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 
-#include <linux/dm9000.h>
 #include <linux/rtc-v3020.h>
 #include <video/mbxfb.h>
-#include <linux/leds.h>
 
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-
-#include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa27x.h>
-#include <mach/pxa-regs.h>
-#include <mach/audio.h>
-#include <mach/pxafb.h>
 #include <mach/ohci.h>
 #include <mach/mmc.h>
-#include <mach/bitfield.h>
-
-#include <asm/hardware/it8152.h>
 
 #include "generic.h"
-#include "cm-x270-pci.h"
-
-/* virtual addresses for statically mapped regions */
-#define CMX270_VIRT_BASE        (0xe8000000)
-#define CMX270_IT8152_VIRT      (CMX270_VIRT_BASE)
 
+/* physical address if local-bus attached devices */
 #define RTC_PHYS_BASE           (PXA_CS1_PHYS + (5 << 22))
-#define DM9000_PHYS_BASE        (PXA_CS1_PHYS + (6 << 22))
 
 /* GPIO IRQ usage */
-#define GPIO10_ETHIRQ           (10)
-#define GPIO22_IT8152_IRQ       (22)
 #define GPIO83_MMC_IRQ          (83)
-#define GPIO95_GFXIRQ           (95)
 
-#define CMX270_ETHIRQ           IRQ_GPIO(GPIO10_ETHIRQ)
-#define CMX270_IT8152_IRQ       IRQ_GPIO(GPIO22_IT8152_IRQ)
 #define CMX270_MMC_IRQ          IRQ_GPIO(GPIO83_MMC_IRQ)
-#define CMX270_GFXIRQ           IRQ_GPIO(GPIO95_GFXIRQ)
 
 /* MMC power enable */
 #define GPIO105_MMC_POWER       (105)
@@ -157,62 +133,6 @@ static unsigned long cmx270_pin_config[] = {
         GPIO83_GPIO,    /* MMC card detect */
 };
 
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
-static struct resource cmx270_dm9000_resource[] = {
-        [0] = {
-                .start = DM9000_PHYS_BASE,
-                .end   = DM9000_PHYS_BASE + 4,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DM9000_PHYS_BASE + 8,
-                .end   = DM9000_PHYS_BASE + 8 + 500,
-                .flags = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start = CMX270_ETHIRQ,
-                .end   = CMX270_ETHIRQ,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
-        }
-};
-
-static struct dm9000_plat_data cmx270_dm9000_platdata = {
-        .flags          = DM9000_PLATF_32BITONLY,
-};
-
-static struct platform_device cmx270_dm9000_device = {
-        .name           = "dm9000",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(cmx270_dm9000_resource),
-        .resource       = cmx270_dm9000_resource,
-        .dev            = {
-                .platform_data = &cmx270_dm9000_platdata,
-        }
-};
-
-static void __init cmx270_init_dm9000(void)
-{
-        platform_device_register(&cmx270_dm9000_device);
-}
-#else
-static inline void cmx270_init_dm9000(void) {}
-#endif
-
-/* UCB1400 touchscreen controller */
-#if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
-static struct platform_device cmx270_ts_device = {
-        .name           = "ucb1400_ts",
-        .id             = -1,
-};
-
-static void __init cmx270_init_touchscreen(void)
-{
-        platform_device_register(&cmx270_ts_device);
-}
-#else
-static inline void cmx270_init_touchscreen(void) {}
-#endif
-
 /* V3020 RTC */
 #if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
 static struct resource cmx270_v3020_resource[] = {
@@ -242,45 +162,7 @@ static void __init cmx270_init_rtc(void)
         platform_device_register(&cmx270_rtc_device);
 }
 #else
-static inline void cmx270_init_rtc(void) {}
-#endif
-
-/* CM-X270 LEDs */
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-static struct gpio_led cmx270_leds[] = {
-        [0] = {
-                .name = "cm-x270:red",
-                .default_trigger = "nand-disk",
-                .gpio = 93,
-                .active_low = 1,
-        },
-        [1] = {
-                .name = "cm-x270:green",
-                .default_trigger = "heartbeat",
-                .gpio = 94,
-                .active_low = 1,
-        },
-};
-
-static struct gpio_led_platform_data cmx270_gpio_led_pdata = {
-        .num_leds = ARRAY_SIZE(cmx270_leds),
-        .leds = cmx270_leds,
-};
-
-static struct platform_device cmx270_led_device = {
-        .name           = "leds-gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &cmx270_gpio_led_pdata,
-        },
-};
-
-static void __init cmx270_init_leds(void)
-{
-        platform_device_register(&cmx270_led_device);
-}
-#else
-static inline void cmx270_init_leds(void) {}
+static inline void cmx2xx_init_rtc(void) {}
 #endif
 
 /* 2700G graphics */
@@ -373,238 +255,11 @@ static void __init cmx270_init_2700G(void)
 static inline void cmx270_init_2700G(void) {}
 #endif
 
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-/*
-  Display definitions
-  keep these for backwards compatibility, although symbolic names (as
-  e.g. in lpd270.c) looks better
-*/
-#define MTYPE_STN320x240        0
-#define MTYPE_TFT640x480        1
-#define MTYPE_CRT640x480        2
-#define MTYPE_CRT800x600        3
-#define MTYPE_TFT320x240        6
-#define MTYPE_STN640x480        7
-
-static struct pxafb_mode_info generic_stn_320x240_mode = {
-        .pixclock       = 76923,
-        .bpp            = 8,
-        .xres           = 320,
-        .yres           = 240,
-        .hsync_len      = 3,
-        .vsync_len      = 2,
-        .left_margin    = 3,
-        .upper_margin   = 0,
-        .right_margin   = 3,
-        .lower_margin   = 0,
-        .sync           = (FB_SYNC_HOR_HIGH_ACT |
-                           FB_SYNC_VERT_HIGH_ACT),
-        .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_stn_320x240 = {
-        .modes          = &generic_stn_320x240_mode,
-        .num_modes      = 1,
-        .lccr0          = 0,
-        .lccr3          = (LCCR3_PixClkDiv(0x03) |
-                           LCCR3_Acb(0xff) |
-                           LCCR3_PCP),
-        .cmap_inverse   = 0,
-        .cmap_static    = 0,
-};
-
-static struct pxafb_mode_info generic_tft_640x480_mode = {
-        .pixclock       = 38461,
-        .bpp            = 8,
-        .xres           = 640,
-        .yres           = 480,
-        .hsync_len      = 60,
-        .vsync_len      = 2,
-        .left_margin    = 70,
-        .upper_margin   = 10,
-        .right_margin   = 70,
-        .lower_margin   = 5,
-        .sync           = 0,
-        .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_tft_640x480 = {
-        .modes          = &generic_tft_640x480_mode,
-        .num_modes      = 1,
-        .lccr0          = (LCCR0_PAS),
-        .lccr3          = (LCCR3_PixClkDiv(0x01) |
-                           LCCR3_Acb(0xff) |
-                           LCCR3_PCP),
-        .cmap_inverse   = 0,
-        .cmap_static    = 0,
-};
-
-static struct pxafb_mode_info generic_crt_640x480_mode = {
-        .pixclock       = 38461,
-        .bpp            = 8,
-        .xres           = 640,
-        .yres           = 480,
-        .hsync_len      = 63,
-        .vsync_len      = 2,
-        .left_margin    = 81,
-        .upper_margin   = 33,
-        .right_margin   = 16,
-        .lower_margin   = 10,
-        .sync           = (FB_SYNC_HOR_HIGH_ACT |
-                           FB_SYNC_VERT_HIGH_ACT),
-        .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_crt_640x480 = {
-        .modes          = &generic_crt_640x480_mode,
-        .num_modes      = 1,
-        .lccr0          = (LCCR0_PAS),
-        .lccr3          = (LCCR3_PixClkDiv(0x01) |
-                           LCCR3_Acb(0xff)),
-        .cmap_inverse   = 0,
-        .cmap_static    = 0,
-};
-
-static struct pxafb_mode_info generic_crt_800x600_mode = {
-        .pixclock       = 28846,
-        .bpp            = 8,
-        .xres           = 800,
-        .yres           = 600,
-        .hsync_len      = 63,
-        .vsync_len      = 2,
-        .left_margin    = 26,
-        .upper_margin   = 21,
-        .right_margin   = 26,
-        .lower_margin   = 11,
-        .sync           = (FB_SYNC_HOR_HIGH_ACT |
-                           FB_SYNC_VERT_HIGH_ACT),
-        .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_crt_800x600 = {
-        .modes          = &generic_crt_800x600_mode,
-        .num_modes      = 1,
-        .lccr0          = (LCCR0_PAS),
-        .lccr3          = (LCCR3_PixClkDiv(0x02) |
-                           LCCR3_Acb(0xff)),
-        .cmap_inverse   = 0,
-        .cmap_static    = 0,
-};
-
-static struct pxafb_mode_info generic_tft_320x240_mode = {
-        .pixclock       = 134615,
-        .bpp            = 16,
-        .xres           = 320,
-        .yres           = 240,
-        .hsync_len      = 63,
-        .vsync_len      = 7,
-        .left_margin    = 75,
-        .upper_margin   = 0,
-        .right_margin   = 15,
-        .lower_margin   = 15,
-        .sync           = 0,
-        .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_tft_320x240 = {
-        .modes          = &generic_tft_320x240_mode,
-        .num_modes      = 1,
-        .lccr0          = (LCCR0_PAS),
-        .lccr3          = (LCCR3_PixClkDiv(0x06) |
-                           LCCR3_Acb(0xff) |
-                           LCCR3_PCP),
-        .cmap_inverse   = 0,
-        .cmap_static    = 0,
-};
-
-static struct pxafb_mode_info generic_stn_640x480_mode = {
-        .pixclock       = 57692,
-        .bpp            = 8,
-        .xres           = 640,
-        .yres           = 480,
-        .hsync_len      = 4,
-        .vsync_len      = 2,
-        .left_margin    = 10,
-        .upper_margin   = 5,
-        .right_margin   = 10,
-        .lower_margin   = 5,
-        .sync           = (FB_SYNC_HOR_HIGH_ACT |
-                           FB_SYNC_VERT_HIGH_ACT),
-        .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_stn_640x480 = {
-        .modes          = &generic_stn_640x480_mode,
-        .num_modes      = 1,
-        .lccr0          = 0,
-        .lccr3          = (LCCR3_PixClkDiv(0x02) |
-                           LCCR3_Acb(0xff)),
-        .cmap_inverse   = 0,
-        .cmap_static    = 0,
-};
-
-static struct pxafb_mach_info *cmx270_display = &generic_crt_640x480;
-
-static int __init cmx270_set_display(char *str)
-{
-        int disp_type = simple_strtol(str, NULL, 0);
-        switch (disp_type) {
-        case MTYPE_STN320x240:
-                cmx270_display = &generic_stn_320x240;
-                break;
-        case MTYPE_TFT640x480:
-                cmx270_display = &generic_tft_640x480;
-                break;
-        case MTYPE_CRT640x480:
-                cmx270_display = &generic_crt_640x480;
-                break;
-        case MTYPE_CRT800x600:
-                cmx270_display = &generic_crt_800x600;
-                break;
-        case MTYPE_TFT320x240:
-                cmx270_display = &generic_tft_320x240;
-                break;
-        case MTYPE_STN640x480:
-                cmx270_display = &generic_stn_640x480;
-                break;
-        default: /* fallback to CRT 640x480 */
-                cmx270_display = &generic_crt_640x480;
-                break;
-        }
-        return 1;
-}
-
-/*
-   This should be done really early to get proper configuration for
-   frame buffer.
-   Indeed, pxafb parameters can be used istead, but CM-X270 bootloader
-   has limitied line length for kernel command line, and also it will
-   break compatibitlty with proprietary releases already in field.
-*/
-__setup("monitor=", cmx270_set_display);
-
-static void __init cmx270_init_display(void)
-{
-        set_pxa_fb_info(cmx270_display);
-}
-#else
-static inline void cmx270_init_display(void) {}
-#endif
-
 /* PXA27x OHCI controller setup */
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static int cmx270_ohci_init(struct device *dev)
-{
-        /* Set the Power Control Polarity Low */
-        UHCHR = (UHCHR | UHCHR_PCPL) &
-                ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
-
-        return 0;
-}
-
 static struct pxaohci_platform_data cmx270_ohci_platform_data = {
         .port_mode      = PMM_PERPORT_MODE,
-        .init           = cmx270_ohci_init,
+        .flags          = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
 };
 
 static void __init cmx270_init_ohci(void)
@@ -676,131 +331,12 @@ static void __init cmx270_init_mmc(void)
 static inline void cmx270_init_mmc(void) {}
 #endif
 
-#ifdef CONFIG_PM
-static unsigned long sleep_save_msc[10];
-
-static int cmx270_suspend(struct sys_device *dev, pm_message_t state)
-{
-        cmx270_pci_suspend();
-
-        /* save MSC registers */
-        sleep_save_msc[0] = MSC0;
-        sleep_save_msc[1] = MSC1;
-        sleep_save_msc[2] = MSC2;
-
-        /* setup power saving mode registers */
-        PCFR = 0x0;
-        PSLR = 0xff400000;
-        PMCR  = 0x00000005;
-        PWER  = 0x80000000;
-        PFER  = 0x00000000;
-        PRER  = 0x00000000;
-        PGSR0 = 0xC0018800;
-        PGSR1 = 0x004F0002;
-        PGSR2 = 0x6021C000;
-        PGSR3 = 0x00020000;
-
-        return 0;
-}
-
-static int cmx270_resume(struct sys_device *dev)
-{
-        cmx270_pci_resume();
-
-        /* restore MSC registers */
-        MSC0 = sleep_save_msc[0];
-        MSC1 = sleep_save_msc[1];
-        MSC2 = sleep_save_msc[2];
-
-        return 0;
-}
-
-static struct sysdev_class cmx270_pm_sysclass = {
-        .name = "pm",
-        .resume = cmx270_resume,
-        .suspend = cmx270_suspend,
-};
-
-static struct sys_device cmx270_pm_device = {
-        .cls = &cmx270_pm_sysclass,
-};
-
-static int __init cmx270_pm_init(void)
-{
-        int error;
-        error = sysdev_class_register(&cmx270_pm_sysclass);
-        if (error == 0)
-                error = sysdev_register(&cmx270_pm_device);
-        return error;
-}
-#else
-static int __init cmx270_pm_init(void) { return 0; }
-#endif
-
-#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
-static void __init cmx270_init_ac97(void)
-{
-        pxa_set_ac97_info(NULL);
-}
-#else
-static inline void cmx270_init_ac97(void) {}
-#endif
-
-static void __init cmx270_init(void)
+void __init cmx270_init(void)
 {
-        cmx270_pm_init();
-
         pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_pin_config));
 
-        cmx270_init_dm9000();
         cmx270_init_rtc();
-        cmx270_init_display();
         cmx270_init_mmc();
         cmx270_init_ohci();
-        cmx270_init_ac97();
-        cmx270_init_touchscreen();
-        cmx270_init_leds();
         cmx270_init_2700G();
 }
-
-static void __init cmx270_init_irq(void)
-{
-        pxa27x_init_irq();
-
-        cmx270_pci_init_irq(GPIO22_IT8152_IRQ);
-}
-
-#ifdef CONFIG_PCI
-/* Map PCI companion statically */
-static struct map_desc cmx270_io_desc[] __initdata = {
-        [0] = { /* PCI bridge */
-                .virtual        = CMX270_IT8152_VIRT,
-                .pfn            = __phys_to_pfn(PXA_CS4_PHYS),
-                .length         = SZ_64M,
-                .type           = MT_DEVICE
-        },
-};
-
-static void __init cmx270_map_io(void)
-{
-        pxa_map_io();
-        iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
-
-        it8152_base_address = CMX270_IT8152_VIRT;
-}
-#else
-static void __init cmx270_map_io(void)
-{
-        pxa_map_io();
-}
-#endif
-
-MACHINE_START(ARMCORE, "Compulab CM-x270")
-        .boot_params    = 0xa0000100,
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .map_io         = cmx270_map_io,
-        .init_irq       = cmx270_init_irq,
-        .timer          = &pxa_timer,
-        .init_machine   = cmx270_init,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 2d5bcea1e520..3156b25f6e9d 100644
--- a/arch/arm/mach-pxa/cm-x270-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-pxa/cm-x270-pci.c
+ * linux/arch/arm/mach-pxa/cm-x2xx-pci.c
  *
  * PCI bios-type initialisation for PCI machines
  *
@@ -28,7 +28,7 @@
 #include <asm/hardware/it8152.h>
 
 unsigned long it8152_base_address;
-static int cmx270_it8152_irq_gpio;
+static int cmx2xx_it8152_irq_gpio;
 
 /*
  * Only first 64MB of memory can be accessed via PCI.
@@ -36,13 +36,13 @@ static int cmx270_it8152_irq_gpio;
  * This is really ugly and we need a better way of specifying
  * DMA-capable regions of memory.
  */
-void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
+void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size,
         unsigned long *zhole_size)
 {
         unsigned int sz = SZ_64M >> PAGE_SHIFT;
 
         if (machine_is_armcore()) {
-                pr_info("Adjusting zones for CM-X270\n");
+                pr_info("Adjusting zones for CM-X2XX\n");
 
                 /*
                  * Only adjust if > 64M on current system
@@ -57,29 +57,29 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
         }
 }
 
-static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
+static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
         /* clear our parent irq */
-        GEDR(cmx270_it8152_irq_gpio) = GPIO_bit(cmx270_it8152_irq_gpio);
+        GEDR(cmx2xx_it8152_irq_gpio) = GPIO_bit(cmx2xx_it8152_irq_gpio);
 
         it8152_irq_demux(irq, desc);
 }
 
-void __cmx270_pci_init_irq(int irq_gpio)
+void __cmx2xx_pci_init_irq(int irq_gpio)
 {
         it8152_init_irq();
 
-        cmx270_it8152_irq_gpio = irq_gpio;
+        cmx2xx_it8152_irq_gpio = irq_gpio;
 
         set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
 
-        set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux);
+        set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux);
 }
 
 #ifdef CONFIG_PM
 static unsigned long sleep_save_ite[10];
 
-void __cmx270_pci_suspend(void)
+void __cmx2xx_pci_suspend(void)
 {
         /* save ITE state */
         sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
@@ -91,7 +91,7 @@ void __cmx270_pci_suspend(void)
         __raw_writel((0), IT8152_INTC_LPCNIRR);
 }
 
-void __cmx270_pci_resume(void)
+void __cmx2xx_pci_resume(void)
 {
         /* restore IT8152 state */
         __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
@@ -99,12 +99,12 @@ void __cmx270_pci_resume(void)
         __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
 }
 #else
-void cmx270_pci_suspend(void) {}
-void cmx270_pci_resume(void) {}
+void cmx2xx_pci_suspend(void) {}
+void cmx2xx_pci_resume(void) {}
 #endif
 
 /* PCI IRQ mapping*/
-static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+static int __init cmx2xx_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
         int irq;
 
@@ -116,14 +116,14 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
         /*
           Here comes the ugly part. The routing is baseboard specific,
-          but defining a platform for each possible base of CM-X270 is
-          unrealistic. Here we keep mapping for ATXBase and SB-X270.
+          but defining a platform for each possible base of CM-X2XX is
+          unrealistic. Here we keep mapping for ATXBase and SB-X2XX.
         */
         /* ATXBASE PCI slot */
         if (slot == 7)
                 return IT8152_PCI_INTA;
 
-        /* ATXBase/SB-x270 CardBus */
+        /* ATXBase/SB-X2XX CardBus */
         if (slot == 8 || slot == 0)
                 return IT8152_PCI_INTB;
 
@@ -131,7 +131,11 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         if (slot == 9)
                 return IT8152_PCI_INTA;
 
-        /* SB-x270 Ethernet */
+        /* CM-x255 Onboard Ethernet */
+        if (slot == 15)
+                return IT8152_PCI_INTC;
+
+        /* SB-x2xx Ethernet */
         if (slot == 16)
                 return IT8152_PCI_INTA;
 
@@ -144,9 +148,9 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         return(0);
 }
 
-static void cmx270_pci_preinit(void)
+static void cmx2xx_pci_preinit(void)
 {
-        pr_info("Initializing CM-X270 PCI subsystem\n");
+        pr_info("Initializing CM-X2XX PCI subsystem\n");
 
         __raw_writel(0x800, IT8152_PCI_CFG_ADDR);
         if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
@@ -200,21 +204,21 @@ static void cmx270_pci_preinit(void)
         }
 }
 
-static struct hw_pci cmx270_pci __initdata = {
+static struct hw_pci cmx2xx_pci __initdata = {
         .swizzle        = pci_std_swizzle,
-        .map_irq        = cmx270_pci_map_irq,
+        .map_irq        = cmx2xx_pci_map_irq,
         .nr_controllers = 1,
         .setup          = it8152_pci_setup,
         .scan           = it8152_pci_scan_bus,
-        .preinit        = cmx270_pci_preinit,
+        .preinit        = cmx2xx_pci_preinit,
 };
 
-static int __init cmx270_init_pci(void)
+static int __init cmx2xx_init_pci(void)
 {
         if (machine_is_armcore())
-                pci_common_init(&cmx270_pci);
+                pci_common_init(&cmx2xx_pci);
 
         return 0;
 }
 
-subsys_initcall(cmx270_init_pci);
+subsys_initcall(cmx2xx_init_pci);
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.h b/arch/arm/mach-pxa/cm-x2xx-pci.h
new file mode 100644
index 000000000000..e24aad2e3ad7
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.h
@@ -0,0 +1,13 @@
+extern void __cmx2xx_pci_init_irq(int irq_gpio);
+extern void __cmx2xx_pci_suspend(void);
+extern void __cmx2xx_pci_resume(void);
+
+#ifdef CONFIG_PCI
+#define cmx2xx_pci_init_irq(x) __cmx2xx_pci_init_irq(x)
+#define cmx2xx_pci_suspend(x) __cmx2xx_pci_suspend(x)
+#define cmx2xx_pci_resume(x) __cmx2xx_pci_resume(x)
+#else
+#define cmx2xx_pci_init_irq(x) do {} while (0)
+#define cmx2xx_pci_suspend(x) do {} while (0)
+#define cmx2xx_pci_resume(x) do {} while (0)
+#endif
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
new file mode 100644
index 000000000000..0b3ce3b6d896
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -0,0 +1,531 @@
+/*
+ * linux/arch/arm/mach-pxa/cm-x2xx.c
+ *
+ * Copyright (C) 2008 CompuLab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include <linux/dm9000.h>
+#include <linux/leds.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pxa-regs.h>
+#include <mach/audio.h>
+#include <mach/pxafb.h>
+
+#include <asm/hardware/it8152.h>
+
+#include "generic.h"
+#include "cm-x2xx-pci.h"
+
+extern void cmx255_init(void);
+extern void cmx270_init(void);
+
+/* virtual addresses for statically mapped regions */
+#define CMX2XX_VIRT_BASE        (0xe8000000)
+#define CMX2XX_IT8152_VIRT      (CMX2XX_VIRT_BASE)
+
+/* physical address if local-bus attached devices */
+#define CMX255_DM9000_PHYS_BASE (PXA_CS1_PHYS + (8 << 22))
+#define CMX270_DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
+
+/* leds */
+#define CMX255_GPIO_RED         (27)
+#define CMX255_GPIO_GREEN       (32)
+#define CMX270_GPIO_RED         (93)
+#define CMX270_GPIO_GREEN       (94)
+
+/* GPIO IRQ usage */
+#define GPIO22_ETHIRQ           (22)
+#define GPIO10_ETHIRQ           (10)
+#define CMX255_GPIO_IT8152_IRQ  (0)
+#define CMX270_GPIO_IT8152_IRQ  (22)
+
+#define CMX255_ETHIRQ           IRQ_GPIO(GPIO22_ETHIRQ)
+#define CMX270_ETHIRQ           IRQ_GPIO(GPIO10_ETHIRQ)
+
+#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+static struct resource cmx255_dm9000_resource[] = {
+        [0] = {
+                .start = CMX255_DM9000_PHYS_BASE,
+                .end   = CMX255_DM9000_PHYS_BASE + 3,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CMX255_DM9000_PHYS_BASE + 4,
+                .end   = CMX255_DM9000_PHYS_BASE + 4 + 500,
+                .flags = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start = CMX255_ETHIRQ,
+                .end   = CMX255_ETHIRQ,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct resource cmx270_dm9000_resource[] = {
+        [0] = {
+                .start = CMX270_DM9000_PHYS_BASE,
+                .end   = CMX270_DM9000_PHYS_BASE + 3,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CMX270_DM9000_PHYS_BASE + 8,
+                .end   = CMX270_DM9000_PHYS_BASE + 8 + 500,
+                .flags = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start = CMX270_ETHIRQ,
+                .end   = CMX270_ETHIRQ,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct dm9000_plat_data cmx270_dm9000_platdata = {
+        .flags          = DM9000_PLATF_32BITONLY,
+};
+
+static struct platform_device cmx2xx_dm9000_device = {
+        .name           = "dm9000",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(cmx270_dm9000_resource),
+        .dev            = {
+                .platform_data = &cmx270_dm9000_platdata,
+        }
+};
+
+static void __init cmx2xx_init_dm9000(void)
+{
+        if (cpu_is_pxa25x())
+                cmx2xx_dm9000_device.resource = cmx255_dm9000_resource;
+        else
+                cmx2xx_dm9000_device.resource = cmx270_dm9000_resource;
+        platform_device_register(&cmx2xx_dm9000_device);
+}
+#else
+static inline void cmx2xx_init_dm9000(void) {}
+#endif
+
+/* UCB1400 touchscreen controller */
+#if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
+static struct platform_device cmx2xx_ts_device = {
+        .name           = "ucb1400_ts",
+        .id             = -1,
+};
+
+static void __init cmx2xx_init_touchscreen(void)
+{
+        platform_device_register(&cmx2xx_ts_device);
+}
+#else
+static inline void cmx2xx_init_touchscreen(void) {}
+#endif
+
+/* CM-X270 LEDs */
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led cmx2xx_leds[] = {
+        [0] = {
+                .name = "cm-x2xx:red",
+                .default_trigger = "nand-disk",
+                .active_low = 1,
+        },
+        [1] = {
+                .name = "cm-x2xx:green",
+                .default_trigger = "heartbeat",
+                .active_low = 1,
+        },
+};
+
+static struct gpio_led_platform_data cmx2xx_gpio_led_pdata = {
+        .num_leds = ARRAY_SIZE(cmx2xx_leds),
+        .leds = cmx2xx_leds,
+};
+
+static struct platform_device cmx2xx_led_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &cmx2xx_gpio_led_pdata,
+        },
+};
+
+static void __init cmx2xx_init_leds(void)
+{
+        if (cpu_is_pxa25x()) {
+                cmx2xx_leds[0].gpio = CMX255_GPIO_RED;
+                cmx2xx_leds[1].gpio = CMX255_GPIO_GREEN;
+        } else {
+                cmx2xx_leds[0].gpio = CMX270_GPIO_RED;
+                cmx2xx_leds[1].gpio = CMX270_GPIO_GREEN;
+        }
+        platform_device_register(&cmx2xx_led_device);
+}
+#else
+static inline void cmx2xx_init_leds(void) {}
+#endif
+
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+/*
+  Display definitions
+  keep these for backwards compatibility, although symbolic names (as
+  e.g. in lpd270.c) looks better
+*/
+#define MTYPE_STN320x240        0
+#define MTYPE_TFT640x480        1
+#define MTYPE_CRT640x480        2
+#define MTYPE_CRT800x600        3
+#define MTYPE_TFT320x240        6
+#define MTYPE_STN640x480        7
+
+static struct pxafb_mode_info generic_stn_320x240_mode = {
+        .pixclock       = 76923,
+        .bpp            = 8,
+        .xres           = 320,
+        .yres           = 240,
+        .hsync_len      = 3,
+        .vsync_len      = 2,
+        .left_margin    = 3,
+        .upper_margin   = 0,
+        .right_margin   = 3,
+        .lower_margin   = 0,
+        .sync           = (FB_SYNC_HOR_HIGH_ACT |
+                           FB_SYNC_VERT_HIGH_ACT),
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_stn_320x240 = {
+        .modes          = &generic_stn_320x240_mode,
+        .num_modes      = 1,
+        .lccr0          = 0,
+        .lccr3          = (LCCR3_PixClkDiv(0x03) |
+                           LCCR3_Acb(0xff) |
+                           LCCR3_PCP),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_tft_640x480_mode = {
+        .pixclock       = 38461,
+        .bpp            = 8,
+        .xres           = 640,
+        .yres           = 480,
+        .hsync_len      = 60,
+        .vsync_len      = 2,
+        .left_margin    = 70,
+        .upper_margin   = 10,
+        .right_margin   = 70,
+        .lower_margin   = 5,
+        .sync           = 0,
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_tft_640x480 = {
+        .modes          = &generic_tft_640x480_mode,
+        .num_modes      = 1,
+        .lccr0          = (LCCR0_PAS),
+        .lccr3          = (LCCR3_PixClkDiv(0x01) |
+                           LCCR3_Acb(0xff) |
+                           LCCR3_PCP),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_crt_640x480_mode = {
+        .pixclock       = 38461,
+        .bpp            = 8,
+        .xres           = 640,
+        .yres           = 480,
+        .hsync_len      = 63,
+        .vsync_len      = 2,
+        .left_margin    = 81,
+        .upper_margin   = 33,
+        .right_margin   = 16,
+        .lower_margin   = 10,
+        .sync           = (FB_SYNC_HOR_HIGH_ACT |
+                           FB_SYNC_VERT_HIGH_ACT),
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_crt_640x480 = {
+        .modes          = &generic_crt_640x480_mode,
+        .num_modes      = 1,
+        .lccr0          = (LCCR0_PAS),
+        .lccr3          = (LCCR3_PixClkDiv(0x01) |
+                           LCCR3_Acb(0xff)),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_crt_800x600_mode = {
+        .pixclock       = 28846,
+        .bpp            = 8,
+        .xres           = 800,
+        .yres           = 600,
+        .hsync_len      = 63,
+        .vsync_len      = 2,
+        .left_margin    = 26,
+        .upper_margin   = 21,
+        .right_margin   = 26,
+        .lower_margin   = 11,
+        .sync           = (FB_SYNC_HOR_HIGH_ACT |
+                           FB_SYNC_VERT_HIGH_ACT),
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_crt_800x600 = {
+        .modes          = &generic_crt_800x600_mode,
+        .num_modes      = 1,
+        .lccr0          = (LCCR0_PAS),
+        .lccr3          = (LCCR3_PixClkDiv(0x02) |
+                           LCCR3_Acb(0xff)),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_tft_320x240_mode = {
+        .pixclock       = 134615,
+        .bpp            = 16,
+        .xres           = 320,
+        .yres           = 240,
+        .hsync_len      = 63,
+        .vsync_len      = 7,
+        .left_margin    = 75,
+        .upper_margin   = 0,
+        .right_margin   = 15,
+        .lower_margin   = 15,
+        .sync           = 0,
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_tft_320x240 = {
+        .modes          = &generic_tft_320x240_mode,
+        .num_modes      = 1,
+        .lccr0          = (LCCR0_PAS),
+        .lccr3          = (LCCR3_PixClkDiv(0x06) |
+                           LCCR3_Acb(0xff) |
+                           LCCR3_PCP),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mode_info generic_stn_640x480_mode = {
+        .pixclock       = 57692,
+        .bpp            = 8,
+        .xres           = 640,
+        .yres           = 480,
+        .hsync_len      = 4,
+        .vsync_len      = 2,
+        .left_margin    = 10,
+        .upper_margin   = 5,
+        .right_margin   = 10,
+        .lower_margin   = 5,
+        .sync           = (FB_SYNC_HOR_HIGH_ACT |
+                           FB_SYNC_VERT_HIGH_ACT),
+        .cmap_greyscale = 0,
+};
+
+static struct pxafb_mach_info generic_stn_640x480 = {
+        .modes          = &generic_stn_640x480_mode,
+        .num_modes      = 1,
+        .lccr0          = 0,
+        .lccr3          = (LCCR3_PixClkDiv(0x02) |
+                           LCCR3_Acb(0xff)),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+};
+
+static struct pxafb_mach_info *cmx2xx_display = &generic_crt_640x480;
+
+static int __init cmx2xx_set_display(char *str)
+{
+        int disp_type = simple_strtol(str, NULL, 0);
+        switch (disp_type) {
+        case MTYPE_STN320x240:
+                cmx2xx_display = &generic_stn_320x240;
+                break;
+        case MTYPE_TFT640x480:
+                cmx2xx_display = &generic_tft_640x480;
+                break;
+        case MTYPE_CRT640x480:
+                cmx2xx_display = &generic_crt_640x480;
+                break;
+        case MTYPE_CRT800x600:
+                cmx2xx_display = &generic_crt_800x600;
+                break;
+        case MTYPE_TFT320x240:
+                cmx2xx_display = &generic_tft_320x240;
+                break;
+        case MTYPE_STN640x480:
+                cmx2xx_display = &generic_stn_640x480;
+                break;
+        default: /* fallback to CRT 640x480 */
+                cmx2xx_display = &generic_crt_640x480;
+                break;
+        }
+        return 1;
+}
+
+/*
+   This should be done really early to get proper configuration for
+   frame buffer.
+   Indeed, pxafb parameters can be used istead, but CM-X2XX bootloader
+   has limitied line length for kernel command line, and also it will
+   break compatibitlty with proprietary releases already in field.
+*/
+__setup("monitor=", cmx2xx_set_display);
+
+static void __init cmx2xx_init_display(void)
+{
+        set_pxa_fb_info(cmx2xx_display);
+}
+#else
+static inline void cmx2xx_init_display(void) {}
+#endif
+
+#ifdef CONFIG_PM
+static unsigned long sleep_save_msc[10];
+
+static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state)
+{
+        cmx2xx_pci_suspend();
+
+        /* save MSC registers */
+        sleep_save_msc[0] = MSC0;
+        sleep_save_msc[1] = MSC1;
+        sleep_save_msc[2] = MSC2;
+
+        /* setup power saving mode registers */
+        PCFR = 0x0;
+        PSLR = 0xff400000;
+        PMCR  = 0x00000005;
+        PWER  = 0x80000000;
+        PFER  = 0x00000000;
+        PRER  = 0x00000000;
+        PGSR0 = 0xC0018800;
+        PGSR1 = 0x004F0002;
+        PGSR2 = 0x6021C000;
+        PGSR3 = 0x00020000;
+
+        return 0;
+}
+
+static int cmx2xx_resume(struct sys_device *dev)
+{
+        cmx2xx_pci_resume();
+
+        /* restore MSC registers */
+        MSC0 = sleep_save_msc[0];
+        MSC1 = sleep_save_msc[1];
+        MSC2 = sleep_save_msc[2];
+
+        return 0;
+}
+
+static struct sysdev_class cmx2xx_pm_sysclass = {
+        .name = "pm",
+        .resume = cmx2xx_resume,
+        .suspend = cmx2xx_suspend,
+};
+
+static struct sys_device cmx2xx_pm_device = {
+        .cls = &cmx2xx_pm_sysclass,
+};
+
+static int __init cmx2xx_pm_init(void)
+{
+        int error;
+        error = sysdev_class_register(&cmx2xx_pm_sysclass);
+        if (error == 0)
+                error = sysdev_register(&cmx2xx_pm_device);
+        return error;
+}
+#else
+static int __init cmx2xx_pm_init(void) { return 0; }
+#endif
+
+#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
+static void __init cmx2xx_init_ac97(void)
+{
+        pxa_set_ac97_info(NULL);
+}
+#else
+static inline void cmx2xx_init_ac97(void) {}
+#endif
+
+static void __init cmx2xx_init(void)
+{
+        cmx2xx_pm_init();
+
+        if (cpu_is_pxa25x())
+                cmx255_init();
+        else
+                cmx270_init();
+
+        cmx2xx_init_dm9000();
+        cmx2xx_init_display();
+        cmx2xx_init_ac97();
+        cmx2xx_init_touchscreen();
+        cmx2xx_init_leds();
+}
+
+static void __init cmx2xx_init_irq(void)
+{
+        pxa27x_init_irq();
+
+        if (cpu_is_pxa25x()) {
+                pxa25x_init_irq();
+                cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ);
+        } else {
+                pxa27x_init_irq();
+                cmx2xx_pci_init_irq(CMX270_GPIO_IT8152_IRQ);
+        }
+}
+
+#ifdef CONFIG_PCI
+/* Map PCI companion statically */
+static struct map_desc cmx2xx_io_desc[] __initdata = {
+        [0] = { /* PCI bridge */
+                .virtual        = CMX2XX_IT8152_VIRT,
+                .pfn            = __phys_to_pfn(PXA_CS4_PHYS),
+                .length         = SZ_64M,
+                .type           = MT_DEVICE
+        },
+};
+
+static void __init cmx2xx_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));
+
+        it8152_base_address = CMX2XX_IT8152_VIRT;
+}
+#else
+static void __init cmx2xx_map_io(void)
+{
+        pxa_map_io();
+}
+#endif
+
+MACHINE_START(ARMCORE, "Compulab CM-X2XX")
+        .boot_params    = 0xa0000100,
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = cmx2xx_map_io,
+        .init_irq       = cmx2xx_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = cmx2xx_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
new file mode 100644
index 000000000000..deb46cd144bf
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -0,0 +1,465 @@
+/*
+ * linux/arch/arm/mach-pxa/cm-x300.c
+ *
+ * Support for the CompuLab CM-X300 modules
+ *
+ * Copyright (C) 2008 CompuLab Ltd.
+ *
+ * Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <linux/gpio.h>
+#include <linux/dm9000.h>
+#include <linux/leds.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/mfp-pxa300.h>
+
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/pxafb.h>
+#include <mach/mmc.h>
+#include <mach/ohci.h>
+#include <mach/i2c.h>
+#include <mach/pxa3xx_nand.h>
+
+#include <asm/mach/map.h>
+
+#include "generic.h"
+
+#define CM_X300_ETH_PHYS        0x08000010
+
+#define GPIO82_MMC2_IRQ         (82)
+#define GPIO85_MMC2_WP          (85)
+
+#define CM_X300_MMC2_IRQ        IRQ_GPIO(GPIO82_MMC2_IRQ)
+
+static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = {
+        /* LCD */
+        GPIO54_LCD_LDD_0,
+        GPIO55_LCD_LDD_1,
+        GPIO56_LCD_LDD_2,
+        GPIO57_LCD_LDD_3,
+        GPIO58_LCD_LDD_4,
+        GPIO59_LCD_LDD_5,
+        GPIO60_LCD_LDD_6,
+        GPIO61_LCD_LDD_7,
+        GPIO62_LCD_LDD_8,
+        GPIO63_LCD_LDD_9,
+        GPIO64_LCD_LDD_10,
+        GPIO65_LCD_LDD_11,
+        GPIO66_LCD_LDD_12,
+        GPIO67_LCD_LDD_13,
+        GPIO68_LCD_LDD_14,
+        GPIO69_LCD_LDD_15,
+        GPIO72_LCD_FCLK,
+        GPIO73_LCD_LCLK,
+        GPIO74_LCD_PCLK,
+        GPIO75_LCD_BIAS,
+
+        /* BTUART */
+        GPIO111_UART2_RTS,
+        GPIO112_UART2_RXD | MFP_LPM_EDGE_FALL,
+        GPIO113_UART2_TXD,
+        GPIO114_UART2_CTS | MFP_LPM_EDGE_BOTH,
+
+        /* STUART */
+        GPIO109_UART3_TXD,
+        GPIO110_UART3_RXD | MFP_LPM_EDGE_FALL,
+
+        /* AC97 */
+        GPIO23_AC97_nACRESET,
+        GPIO24_AC97_SYSCLK,
+        GPIO29_AC97_BITCLK,
+        GPIO25_AC97_SDATA_IN_0,
+        GPIO27_AC97_SDATA_OUT,
+        GPIO28_AC97_SYNC,
+
+        /* Keypad */
+        GPIO115_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
+        GPIO116_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
+        GPIO117_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
+        GPIO118_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
+        GPIO119_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
+        GPIO120_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
+        GPIO2_2_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
+        GPIO3_2_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
+        GPIO121_KP_MKOUT_0,
+        GPIO122_KP_MKOUT_1,
+        GPIO123_KP_MKOUT_2,
+        GPIO124_KP_MKOUT_3,
+        GPIO125_KP_MKOUT_4,
+        GPIO4_2_KP_MKOUT_5,
+
+        /* MMC1 */
+        GPIO3_MMC1_DAT0,
+        GPIO4_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
+        GPIO5_MMC1_DAT2,
+        GPIO6_MMC1_DAT3,
+        GPIO7_MMC1_CLK,
+        GPIO8_MMC1_CMD, /* CMD0 for slot 0 */
+
+        /* MMC2 */
+        GPIO9_MMC2_DAT0,
+        GPIO10_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
+        GPIO11_MMC2_DAT2,
+        GPIO12_MMC2_DAT3,
+        GPIO13_MMC2_CLK,
+        GPIO14_MMC2_CMD,
+
+        /* FFUART */
+        GPIO30_UART1_RXD | MFP_LPM_EDGE_FALL,
+        GPIO31_UART1_TXD,
+        GPIO32_UART1_CTS,
+        GPIO37_UART1_RTS,
+        GPIO33_UART1_DCD,
+        GPIO34_UART1_DSR | MFP_LPM_EDGE_FALL,
+        GPIO35_UART1_RI,
+        GPIO36_UART1_DTR,
+
+        /* GPIOs */
+        GPIO79_GPIO,                    /* LED */
+        GPIO82_GPIO | MFP_PULL_HIGH,    /* MMC CD */
+        GPIO85_GPIO,                    /* MMC WP */
+        GPIO99_GPIO,                    /* Ethernet IRQ */
+};
+
+#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+static struct resource dm9000_resources[] = {
+        [0] = {
+                .start  = CM_X300_ETH_PHYS,
+                .end    = CM_X300_ETH_PHYS + 0x3,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = CM_X300_ETH_PHYS + 0x4,
+                .end    = CM_X300_ETH_PHYS + 0x4 + 500,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)),
+                .end    = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct dm9000_plat_data cm_x300_dm9000_platdata = {
+        .flags          = DM9000_PLATF_16BITONLY,
+};
+
+static struct platform_device dm9000_device = {
+        .name           = "dm9000",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm9000_resources),
+        .resource       = dm9000_resources,
+        .dev            = {
+                .platform_data = &cm_x300_dm9000_platdata,
+        }
+
+};
+
+static void __init cm_x300_init_dm9000(void)
+{
+        platform_device_register(&dm9000_device);
+}
+#else
+static inline void cm_x300_init_dm9000(void) {}
+#endif
+
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct pxafb_mode_info cm_x300_lcd_modes[] = {
+        [0] = {
+                .pixclock       = 38000,
+                .bpp            = 16,
+                .xres           = 480,
+                .yres           = 640,
+                .hsync_len      = 8,
+                .vsync_len      = 2,
+                .left_margin    = 8,
+                .upper_margin   = 0,
+                .right_margin   = 24,
+                .lower_margin   = 4,
+                .cmap_greyscale = 0,
+        },
+        [1] = {
+                .pixclock       = 153800,
+                .bpp            = 16,
+                .xres           = 240,
+                .yres           = 320,
+                .hsync_len      = 8,
+                .vsync_len      = 2,
+                .left_margin    = 8,
+                .upper_margin   = 2,
+                .right_margin   = 88,
+                .lower_margin   = 2,
+                .cmap_greyscale = 0,
+        },
+};
+
+static struct pxafb_mach_info cm_x300_lcd = {
+        .modes                  = cm_x300_lcd_modes,
+        .num_modes              = 2,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+};
+
+static void __init cm_x300_init_lcd(void)
+{
+        set_pxa_fb_info(&cm_x300_lcd);
+}
+#else
+static inline void cm_x300_init_lcd(void) {}
+#endif
+
+#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
+static struct mtd_partition cm_x300_nand_partitions[] = {
+        [0] = {
+                .name        = "OBM",
+                .offset      = 0,
+                .size        = SZ_256K,
+                .mask_flags  = MTD_WRITEABLE, /* force read-only */
+        },
+        [1] = {
+                .name        = "U-Boot",
+                .offset      = MTDPART_OFS_APPEND,
+                .size        = SZ_256K,
+                .mask_flags  = MTD_WRITEABLE, /* force read-only */
+        },
+        [2] = {
+                .name        = "Environment",
+                .offset      = MTDPART_OFS_APPEND,
+                .size        = SZ_256K,
+        },
+        [3] = {
+                .name        = "reserved",
+                .offset      = MTDPART_OFS_APPEND,
+                .size        = SZ_256K + SZ_1M,
+                .mask_flags  = MTD_WRITEABLE, /* force read-only */
+        },
+        [4] = {
+                .name        = "kernel",
+                .offset      = MTDPART_OFS_APPEND,
+                .size        = SZ_4M,
+        },
+        [5] = {
+                .name        = "fs",
+                .offset      = MTDPART_OFS_APPEND,
+                .size        = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
+        .enable_arbiter = 1,
+        .parts          = cm_x300_nand_partitions,
+        .nr_parts       = ARRAY_SIZE(cm_x300_nand_partitions),
+};
+
+static void __init cm_x300_init_nand(void)
+{
+        pxa3xx_set_nand_info(&cm_x300_nand_info);
+}
+#else
+static inline void cm_x300_init_nand(void) {}
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
+/* The first MMC slot of CM-X300 is hardwired to Libertas card and has
+   no detection/ro pins */
+static int cm_x300_mci_init(struct device *dev,
+                            irq_handler_t cm_x300_detect_int,
+                            void *data)
+{
+        return 0;
+}
+
+static void cm_x300_mci_exit(struct device *dev, void *data)
+{
+}
+
+static struct pxamci_platform_data cm_x300_mci_platform_data = {
+        .detect_delay   = 20,
+        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .init           = cm_x300_mci_init,
+        .exit           = cm_x300_mci_exit,
+};
+
+static int cm_x300_mci2_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO85_MMC2_WP);
+}
+
+static int cm_x300_mci2_init(struct device *dev,
+                             irq_handler_t cm_x300_detect_int,
+                             void *data)
+{
+        int err;
+
+        /*
+         * setup GPIO for CM-X300 MMC controller
+         */
+        err = gpio_request(GPIO82_MMC2_IRQ, "mmc card detect");
+        if (err)
+                goto err_request_cd;
+        gpio_direction_input(GPIO82_MMC2_IRQ);
+
+        err = gpio_request(GPIO85_MMC2_WP, "mmc write protect");
+        if (err)
+                goto err_request_wp;
+        gpio_direction_input(GPIO85_MMC2_WP);
+
+        err = request_irq(CM_X300_MMC2_IRQ, cm_x300_detect_int,
+                          IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                          "MMC card detect", data);
+        if (err) {
+                printk(KERN_ERR "%s: MMC/SD/SDIO: "
+                                "can't request card detect IRQ\n", __func__);
+                goto err_request_irq;
+        }
+
+        return 0;
+
+err_request_irq:
+        gpio_free(GPIO85_MMC2_WP);
+err_request_wp:
+        gpio_free(GPIO82_MMC2_IRQ);
+err_request_cd:
+        return err;
+}
+
+static void cm_x300_mci2_exit(struct device *dev, void *data)
+{
+        free_irq(CM_X300_MMC2_IRQ, data);
+        gpio_free(GPIO82_MMC2_IRQ);
+        gpio_free(GPIO85_MMC2_WP);
+}
+
+static struct pxamci_platform_data cm_x300_mci2_platform_data = {
+        .detect_delay   = 20,
+        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .init           = cm_x300_mci2_init,
+        .exit           = cm_x300_mci2_exit,
+        .get_ro         = cm_x300_mci2_ro,
+};
+
+static void __init cm_x300_init_mmc(void)
+{
+        pxa_set_mci_info(&cm_x300_mci_platform_data);
+        pxa3xx_set_mci2_info(&cm_x300_mci2_platform_data);
+}
+#else
+static inline void cm_x300_init_mmc(void) {}
+#endif
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static struct pxaohci_platform_data cm_x300_ohci_platform_data = {
+        .port_mode      = PMM_PERPORT_MODE,
+        .flags          = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
+};
+
+static void __init cm_x300_init_ohci(void)
+{
+        pxa_set_ohci_info(&cm_x300_ohci_platform_data);
+}
+#else
+static inline void cm_x300_init_ohci(void) {}
+#endif
+
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led cm_x300_leds[] = {
+        [0] = {
+                .name = "cm-x300:green",
+                .default_trigger = "heartbeat",
+                .gpio = 79,
+                .active_low = 1,
+        },
+};
+
+static struct gpio_led_platform_data cm_x300_gpio_led_pdata = {
+        .num_leds = ARRAY_SIZE(cm_x300_leds),
+        .leds = cm_x300_leds,
+};
+
+static struct platform_device cm_x300_led_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &cm_x300_gpio_led_pdata,
+        },
+};
+
+static void __init cm_x300_init_leds(void)
+{
+        platform_device_register(&cm_x300_led_device);
+}
+#else
+static inline void cm_x300_init_leds(void) {}
+#endif
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+/* PCA9555 */
+static struct pca953x_platform_data cm_x300_gpio_ext_pdata_0 = {
+        .gpio_base = 128,
+};
+
+static struct pca953x_platform_data cm_x300_gpio_ext_pdata_1 = {
+        .gpio_base = 144,
+};
+
+static struct i2c_board_info cm_x300_gpio_ext_info[] = {
+        [0] = {
+                I2C_BOARD_INFO("pca9555", 0x24),
+                .platform_data = &cm_x300_gpio_ext_pdata_0,
+        },
+        [1] = {
+                I2C_BOARD_INFO("pca9555", 0x25),
+                .platform_data = &cm_x300_gpio_ext_pdata_1,
+        },
+};
+
+static void __init cm_x300_init_i2c(void)
+{
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, cm_x300_gpio_ext_info,
+                                ARRAY_SIZE(cm_x300_gpio_ext_info));
+}
+#else
+static inline void cm_x300_init_i2c(void) {}
+#endif
+
+static void __init cm_x300_init(void)
+{
+        /* board-processor specific GPIO initialization */
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_mfp_cfg));
+
+        cm_x300_init_dm9000();
+        cm_x300_init_lcd();
+        cm_x300_init_ohci();
+        cm_x300_init_mmc();
+        cm_x300_init_nand();
+        cm_x300_init_leds();
+        cm_x300_init_i2c();
+}
+
+MACHINE_START(CM_X300, "CM-X300 module")
+        .phys_io        = 0x40000000,
+        .boot_params    = 0xa0000100,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa3xx_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = cm_x300_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri.c
index abce13c846c5..e8473624427e 100644
--- a/arch/arm/mach-pxa/colibri.c
+++ b/arch/arm/mach-pxa/colibri.c
@@ -29,12 +29,17 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 #include <mach/pxa-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa27x.h>
 #include <mach/colibri.h>
 
 #include "generic.h"
 #include "devices.h"
 
+static unsigned long colibri_pin_config[] __initdata = {
+        GPIO78_nCS_2,   /* Ethernet CS */
+        GPIO114_GPIO,   /* Ethernet IRQ */
+};
+
 /*
  * Flash
  */
@@ -116,9 +121,7 @@ static struct platform_device *colibri_devices[] __initdata = {
 
 static void __init colibri_init(void)
 {
-        /* DM9000 LAN */
-        pxa_gpio_mode(GPIO78_nCS_2_MD);
-        pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pin_config));
 
         platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices));
 }
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index e703a8d209e2..65558d6aa220 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -20,7 +20,12 @@
 #include <linux/interrupt.h>
 #include <linux/mmc/host.h>
 #include <linux/pm.h>
+#include <linux/gpio.h>
 #include <linux/backlight.h>
+#include <linux/io.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+#include <linux/spi/corgi_lcd.h>
 #include <video/w100fb.h>
 
 #include <asm/setup.h>
@@ -28,7 +33,6 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/system.h>
 
 #include <asm/mach/arch.h>
@@ -37,11 +41,12 @@
 
 #include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa25x.h>
 #include <mach/i2c.h>
 #include <mach/irda.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
+#include <mach/pxa2xx_spi.h>
 #include <mach/corgi.h>
 #include <mach/sharpsl.h>
 
@@ -52,6 +57,61 @@
 #include "devices.h"
 #include "sharpsl.h"
 
+static unsigned long corgi_pin_config[] __initdata = {
+        /* Static Memory I/O */
+        GPIO78_nCS_2,   /* w100fb */
+        GPIO80_nCS_4,   /* scoop */
+
+        /* SSP1 */
+        GPIO23_SSP1_SCLK,
+        GPIO25_SSP1_TXD,
+        GPIO26_SSP1_RXD,
+        GPIO24_GPIO,    /* CORGI_GPIO_ADS7846_CS - SFRM as chip select */
+
+        /* I2S */
+        GPIO28_I2S_BITCLK_OUT,
+        GPIO29_I2S_SDATA_IN,
+        GPIO30_I2S_SDATA_OUT,
+        GPIO31_I2S_SYNC,
+        GPIO32_I2S_SYSCLK,
+
+        /* Infra-Red */
+        GPIO47_FICP_TXD,
+        GPIO46_FICP_RXD,
+
+        /* FFUART */
+        GPIO40_FFUART_DTR,
+        GPIO41_FFUART_RTS,
+        GPIO39_FFUART_TXD,
+        GPIO37_FFUART_DSR,
+        GPIO34_FFUART_RXD,
+        GPIO35_FFUART_CTS,
+
+        /* PC Card */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO52_nPCE_1,
+        GPIO53_nPCE_2,
+        GPIO54_nPSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* MMC */
+        GPIO6_MMC_CLK,
+        GPIO8_MMC_CS0,
+
+        /* GPIO */
+        GPIO9_GPIO,     /* CORGI_GPIO_nSD_DETECT */
+        GPIO7_GPIO,     /* CORGI_GPIO_nSD_WP */
+        GPIO33_GPIO,    /* CORGI_GPIO_SD_PWR */
+        GPIO22_GPIO,    /* CORGI_GPIO_IR_ON */
+        GPIO44_GPIO,    /* CORGI_GPIO_HSYNC */
+
+        GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
+};
 
 /*
  * Corgi SCOOP Device
@@ -67,6 +127,7 @@ static struct resource corgi_scoop_resources[] = {
 static struct scoop_config corgi_scoop_setup = {
         .io_dir         = CORGI_SCOOP_IO_DIR,
         .io_out         = CORGI_SCOOP_IO_OUT,
+        .gpio_base      = CORGI_SCOOP_GPIO_BASE,
 };
 
 struct platform_device corgiscoop_device = {
@@ -79,27 +140,6 @@ struct platform_device corgiscoop_device = {
         .resource       = corgi_scoop_resources,
 };
 
-static void corgi_pcmcia_init(void)
-{
-        /* Setup default state of GPIO outputs
-           before we enable them as outputs. */
-        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) |
-                GPIO_bit(GPIO53_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-        pxa_gpio_mode(GPIO52_nPCE_1_MD);
-        pxa_gpio_mode(GPIO53_nPCE_2_MD);
-        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
-}
-
 static struct scoop_pcmcia_dev corgi_pcmcia_scoop[] = {
 {
         .dev        = &corgiscoop_device.dev,
@@ -112,58 +152,10 @@ static struct scoop_pcmcia_dev corgi_pcmcia_scoop[] = {
 static struct scoop_pcmcia_config corgi_pcmcia_config = {
         .devs         = &corgi_pcmcia_scoop[0],
         .num_devs     = 1,
-        .pcmcia_init  = corgi_pcmcia_init,
 };
 
 EXPORT_SYMBOL(corgiscoop_device);
 
-
-/*
- * Corgi SSP Device
- *
- * Set the parent as the scoop device because a lot of SSP devices
- * also use scoop functions and this makes the power up/down order
- * work correctly.
- */
-struct platform_device corgissp_device = {
-        .name           = "corgi-ssp",
-        .dev            = {
-                .parent = &corgiscoop_device.dev,
-        },
-        .id             = -1,
-};
-
-struct corgissp_machinfo corgi_ssp_machinfo = {
-        .port           = 1,
-        .cs_lcdcon      = CORGI_GPIO_LCDCON_CS,
-        .cs_ads7846     = CORGI_GPIO_ADS7846_CS,
-        .cs_max1111     = CORGI_GPIO_MAX1111_CS,
-        .clk_lcdcon     = 76,
-        .clk_ads7846    = 2,
-        .clk_max1111    = 8,
-};
-
-
-/*
- * LCD/Framebuffer
- */
-static void w100_lcdtg_suspend(struct w100fb_par *par)
-{
-        corgi_lcdtg_suspend();
-}
-
-static void w100_lcdtg_init(struct w100fb_par *par)
-{
-        corgi_lcdtg_hw_init(par->xres);
-}
-
-
-static struct w100_tg_info corgi_lcdtg_info = {
-        .change  = w100_lcdtg_init,
-        .suspend = w100_lcdtg_suspend,
-        .resume  = w100_lcdtg_init,
-};
-
 static struct w100_mem_info corgi_fb_mem = {
         .ext_cntl          = 0x00040003,
         .sdram_mode_reg    = 0x00650021,
@@ -242,7 +234,6 @@ static struct w100_mode corgi_fb_modes[] = {
 };
 
 static struct w100fb_mach_info corgi_fb_info = {
-        .tg         = &corgi_lcdtg_info,
         .init_mode  = INIT_MODE_ROTATED,
         .mem        = &corgi_fb_mem,
         .regs       = &corgi_fb_regs,
@@ -268,60 +259,10 @@ static struct platform_device corgifb_device = {
         .resource       = corgi_fb_resources,
         .dev            = {
                 .platform_data = &corgi_fb_info,
-                .parent = &corgissp_device.dev,
         },
 
 };
 
-
-/*
- * Corgi Backlight Device
- */
-static void corgi_bl_kick_battery(void)
-{
-        void (*kick_batt)(void);
-
-        kick_batt = symbol_get(sharpsl_battery_kick);
-        if (kick_batt) {
-                kick_batt();
-                symbol_put(sharpsl_battery_kick);
-        }
-}
-
-static void corgi_bl_set_intensity(int intensity)
-{
-        if (intensity > 0x10)
-                intensity += 0x10;
-
-        /* Bits 0-4 are accessed via the SSP interface */
-        corgi_ssp_blduty_set(intensity & 0x1f);
-
-        /* Bit 5 is via SCOOP */
-        if (intensity & 0x0020)
-                set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
-        else
-                reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
-}
-
-static struct generic_bl_info corgi_bl_machinfo = {
-        .name = "corgi-bl",
-        .max_intensity = 0x2f,
-        .default_intensity = 0x1f,
-        .limit_mask = 0x0b,
-        .set_bl_intensity = corgi_bl_set_intensity,
-        .kick_battery = corgi_bl_kick_battery,
-};
-
-static struct platform_device corgibl_device = {
-        .name           = "generic-bl",
-        .dev            = {
-                .parent = &corgifb_device.dev,
-                .platform_data  = &corgi_bl_machinfo,
-        },
-        .id             = -1,
-};
-
-
 /*
  * Corgi Keyboard Device
  */
@@ -330,75 +271,35 @@ static struct platform_device corgikbd_device = {
         .id             = -1,
 };
 
-
 /*
  * Corgi LEDs
  */
-static struct platform_device corgiled_device = {
-        .name           = "corgi-led",
-        .id             = -1,
-};
-
-
-/*
- * Corgi Touch Screen Device
- */
-static unsigned long (*get_hsync_invperiod)(struct device *dev);
-
-static void inline sharpsl_wait_sync(int gpio)
-{
-        while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
-        while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
-}
-
-static unsigned long corgi_get_hsync_invperiod(void)
-{
-        if (!get_hsync_invperiod)
-                get_hsync_invperiod = symbol_get(w100fb_get_hsynclen);
-        if (!get_hsync_invperiod)
-                return 0;
-
-        return get_hsync_invperiod(&corgifb_device.dev);
-}
-
-static void corgi_put_hsync(void)
-{
-        if (get_hsync_invperiod)
-                symbol_put(w100fb_get_hsynclen);
-        get_hsync_invperiod = NULL;
-}
-
-static void corgi_wait_hsync(void)
-{
-        sharpsl_wait_sync(CORGI_GPIO_HSYNC);
-}
-
-static struct resource corgits_resources[] = {
-        [0] = {
-                .start          = CORGI_IRQ_GPIO_TP_INT,
-                .end            = CORGI_IRQ_GPIO_TP_INT,
-                .flags          = IORESOURCE_IRQ,
+static struct gpio_led corgi_gpio_leds[] = {
+        {
+                .name                   = "corgi:amber:charge",
+                .default_trigger        = "sharpsl-charge",
+                .gpio                   = CORGI_GPIO_LED_ORANGE,
+        },
+        {
+                .name                   = "corgi:green:mail",
+                .default_trigger        = "nand-disk",
+                .gpio                   = CORGI_GPIO_LED_GREEN,
         },
 };
 
-static struct corgits_machinfo  corgi_ts_machinfo = {
-        .get_hsync_invperiod = corgi_get_hsync_invperiod,
-        .put_hsync           = corgi_put_hsync,
-        .wait_hsync          = corgi_wait_hsync,
+static struct gpio_led_platform_data corgi_gpio_leds_info = {
+        .leds           = corgi_gpio_leds,
+        .num_leds       = ARRAY_SIZE(corgi_gpio_leds),
 };
 
-static struct platform_device corgits_device = {
-        .name           = "corgi-ts",
+static struct platform_device corgiled_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
         .dev            = {
-                .parent = &corgissp_device.dev,
-                .platform_data  = &corgi_ts_machinfo,
+                .platform_data = &corgi_gpio_leds_info,
         },
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(corgits_resources),
-        .resource       = corgits_resources,
 };
 
-
 /*
  * MMC/SD Device
  *
@@ -411,20 +312,42 @@ static int corgi_mci_init(struct device *dev, irq_handler_t corgi_detect_int, vo
 {
         int err;
 
-        /* setup GPIO for PXA25x MMC controller */
-        pxa_gpio_mode(GPIO6_MMCCLK_MD);
-        pxa_gpio_mode(GPIO8_MMCCS0_MD);
-        pxa_gpio_mode(CORGI_GPIO_nSD_DETECT | GPIO_IN);
-        pxa_gpio_mode(CORGI_GPIO_SD_PWR | GPIO_OUT);
+        err = gpio_request(CORGI_GPIO_nSD_DETECT, "nSD_DETECT");
+        if (err)
+                goto err_out;
 
-        corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250);
+        err = gpio_request(CORGI_GPIO_nSD_WP, "nSD_WP");
+        if (err)
+                goto err_free_1;
 
-        err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_detect_int,
-                          IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
-                          "MMC card detect", data);
+        err = gpio_request(CORGI_GPIO_SD_PWR, "SD_PWR");
         if (err)
-                printk(KERN_ERR "corgi_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
+                goto err_free_2;
 
+        gpio_direction_input(CORGI_GPIO_nSD_DETECT);
+        gpio_direction_input(CORGI_GPIO_nSD_WP);
+        gpio_direction_output(CORGI_GPIO_SD_PWR, 0);
+
+        corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250);
+
+        err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_detect_int,
+                                IRQF_DISABLED | IRQF_TRIGGER_RISING |
+                                IRQF_TRIGGER_FALLING,
+                                "MMC card detect", data);
+        if (err) {
+                pr_err("%s: MMC/SD: can't request MMC card detect IRQ\n",
+                                __func__);
+                goto err_free_3;
+        }
+        return 0;
+
+err_free_3:
+        gpio_free(CORGI_GPIO_SD_PWR);
+err_free_2:
+        gpio_free(CORGI_GPIO_nSD_WP);
+err_free_1:
+        gpio_free(CORGI_GPIO_nSD_DETECT);
+err_out:
         return err;
 }
 
@@ -432,20 +355,20 @@ static void corgi_mci_setpower(struct device *dev, unsigned int vdd)
 {
         struct pxamci_platform_data* p_d = dev->platform_data;
 
-        if (( 1 << vdd) & p_d->ocr_mask)
-                GPSR1 = GPIO_bit(CORGI_GPIO_SD_PWR);
-        else
-                GPCR1 = GPIO_bit(CORGI_GPIO_SD_PWR);
+        gpio_set_value(CORGI_GPIO_SD_PWR, ((1 << vdd) & p_d->ocr_mask));
 }
 
 static int corgi_mci_get_ro(struct device *dev)
 {
-        return GPLR(CORGI_GPIO_nSD_WP) & GPIO_bit(CORGI_GPIO_nSD_WP);
+        return gpio_get_value(CORGI_GPIO_nSD_WP);
 }
 
 static void corgi_mci_exit(struct device *dev, void *data)
 {
         free_irq(CORGI_IRQ_GPIO_nSD_DETECT, data);
+        gpio_free(CORGI_GPIO_SD_PWR);
+        gpio_free(CORGI_GPIO_nSD_WP);
+        gpio_free(CORGI_GPIO_nSD_DETECT);
 }
 
 static struct pxamci_platform_data corgi_mci_platform_data = {
@@ -462,16 +385,32 @@ static struct pxamci_platform_data corgi_mci_platform_data = {
  */
 static void corgi_irda_transceiver_mode(struct device *dev, int mode)
 {
-        if (mode & IR_OFF)
-                GPSR(CORGI_GPIO_IR_ON) = GPIO_bit(CORGI_GPIO_IR_ON);
-        else
-                GPCR(CORGI_GPIO_IR_ON) = GPIO_bit(CORGI_GPIO_IR_ON);
+        gpio_set_value(CORGI_GPIO_IR_ON, mode & IR_OFF);
         pxa2xx_transceiver_mode(dev, mode);
 }
 
+static int corgi_irda_startup(struct device *dev)
+{
+        int err;
+
+        err = gpio_request(CORGI_GPIO_IR_ON, "IR_ON");
+        if (err)
+                return err;
+
+        gpio_direction_output(CORGI_GPIO_IR_ON, 1);
+        return 0;
+}
+
+static void corgi_irda_shutdown(struct device *dev)
+{
+        gpio_free(CORGI_GPIO_IR_ON);
+}
+
 static struct pxaficp_platform_data corgi_ficp_platform_data = {
-        .transceiver_cap  = IR_SIRMODE | IR_OFF,
-        .transceiver_mode = corgi_irda_transceiver_mode,
+        .transceiver_cap        = IR_SIRMODE | IR_OFF,
+        .transceiver_mode       = corgi_irda_transceiver_mode,
+        .startup                = corgi_irda_startup,
+        .shutdown               = corgi_irda_shutdown,
 };
 
 
@@ -483,14 +422,129 @@ static struct pxa2xx_udc_mach_info udc_info __initdata = {
         .gpio_pullup            = CORGI_GPIO_USB_PULLUP,
 };
 
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MASTER)
+static struct pxa2xx_spi_master corgi_spi_info = {
+        .num_chipselect = 3,
+};
+
+static struct ads7846_platform_data corgi_ads7846_info = {
+        .model                  = 7846,
+        .vref_delay_usecs       = 100,
+        .x_plate_ohms           = 419,
+        .y_plate_ohms           = 486,
+        .gpio_pendown           = CORGI_GPIO_TP_INT,
+};
+
+static void corgi_ads7846_cs(u32 command)
+{
+        gpio_set_value(CORGI_GPIO_ADS7846_CS, !(command == PXA2XX_CS_ASSERT));
+}
+
+static struct pxa2xx_spi_chip corgi_ads7846_chip = {
+        .cs_control     = corgi_ads7846_cs,
+};
+
+static void corgi_bl_kick_battery(void)
+{
+        void (*kick_batt)(void);
+
+        kick_batt = symbol_get(sharpsl_battery_kick);
+        if (kick_batt) {
+                kick_batt();
+                symbol_put(sharpsl_battery_kick);
+        }
+}
+
+static struct corgi_lcd_platform_data corgi_lcdcon_info = {
+        .init_mode              = CORGI_LCD_MODE_VGA,
+        .max_intensity          = 0x2f,
+        .default_intensity      = 0x1f,
+        .limit_mask             = 0x0b,
+        .gpio_backlight_cont    = CORGI_GPIO_BACKLIGHT_CONT,
+        .gpio_backlight_on      = -1,
+        .kick_battery           = corgi_bl_kick_battery,
+};
+
+static void corgi_lcdcon_cs(u32 command)
+{
+        gpio_set_value(CORGI_GPIO_LCDCON_CS, !(command == PXA2XX_CS_ASSERT));
+}
+
+static struct pxa2xx_spi_chip corgi_lcdcon_chip = {
+        .cs_control     = corgi_lcdcon_cs,
+};
+
+static void corgi_max1111_cs(u32 command)
+{
+        gpio_set_value(CORGI_GPIO_MAX1111_CS, !(command == PXA2XX_CS_ASSERT));
+}
+
+static struct pxa2xx_spi_chip corgi_max1111_chip = {
+        .cs_control     = corgi_max1111_cs,
+};
+
+static struct spi_board_info corgi_spi_devices[] = {
+        {
+                .modalias       = "ads7846",
+                .max_speed_hz   = 1200000,
+                .bus_num        = 1,
+                .chip_select    = 0,
+                .platform_data  = &corgi_ads7846_info,
+                .controller_data= &corgi_ads7846_chip,
+                .irq            = gpio_to_irq(CORGI_GPIO_TP_INT),
+        }, {
+                .modalias       = "corgi-lcd",
+                .max_speed_hz   = 50000,
+                .bus_num        = 1,
+                .chip_select    = 1,
+                .platform_data  = &corgi_lcdcon_info,
+                .controller_data= &corgi_lcdcon_chip,
+        }, {
+                .modalias       = "max1111",
+                .max_speed_hz   = 450000,
+                .bus_num        = 1,
+                .chip_select    = 2,
+                .controller_data= &corgi_max1111_chip,
+        },
+};
+
+static void __init corgi_init_spi(void)
+{
+        int err;
+
+        err = gpio_request(CORGI_GPIO_ADS7846_CS, "ADS7846_CS");
+        if (err)
+                return;
+
+        err = gpio_request(CORGI_GPIO_LCDCON_CS, "LCDCON_CS");
+        if (err)
+                goto err_free_1;
+
+        err = gpio_request(CORGI_GPIO_MAX1111_CS, "MAX1111_CS");
+        if (err)
+                goto err_free_2;
+
+        gpio_direction_output(CORGI_GPIO_ADS7846_CS, 1);
+        gpio_direction_output(CORGI_GPIO_LCDCON_CS, 1);
+        gpio_direction_output(CORGI_GPIO_MAX1111_CS, 1);
+
+        pxa2xx_set_spi_info(1, &corgi_spi_info);
+        spi_register_board_info(ARRAY_AND_SIZE(corgi_spi_devices));
+        return;
+
+err_free_2:
+        gpio_free(CORGI_GPIO_LCDCON_CS);
+err_free_1:
+        gpio_free(CORGI_GPIO_ADS7846_CS);
+}
+#else
+static inline void corgi_init_spi(void) {}
+#endif
 
 static struct platform_device *devices[] __initdata = {
         &corgiscoop_device,
-        &corgissp_device,
         &corgifb_device,
         &corgikbd_device,
-        &corgibl_device,
-        &corgits_device,
         &corgiled_device,
 };
 
@@ -498,7 +552,8 @@ static void corgi_poweroff(void)
 {
         if (!machine_is_corgi())
                 /* Green LED off tells the bootloader to halt */
-                reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
+                gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
+
         arm_machine_restart('h');
 }
 
@@ -506,7 +561,8 @@ static void corgi_restart(char mode)
 {
         if (!machine_is_corgi())
                 /* Green LED on tells the bootloader to reboot */
-                set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
+                gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
+
         arm_machine_restart('h');
 }
 
@@ -515,20 +571,12 @@ static void __init corgi_init(void)
         pm_power_off = corgi_poweroff;
         arm_pm_restart = corgi_restart;
 
-        /* setup sleep mode values */
-        PWER  = 0x00000002;
-        PFER  = 0x00000000;
-        PRER  = 0x00000002;
-        PGSR0 = 0x0158C000;
-        PGSR1 = 0x00FF0080;
-        PGSR2 = 0x0001C004;
         /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
         PCFR |= PCFR_OPDE;
 
-        corgi_ssp_set_machinfo(&corgi_ssp_machinfo);
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config));
 
-        pxa_gpio_mode(CORGI_GPIO_IR_ON | GPIO_OUT);
-        pxa_gpio_mode(CORGI_GPIO_HSYNC | GPIO_IN);
+        corgi_init_spi();
 
         pxa_set_udc_info(&udc_info);
         pxa_set_mci_info(&corgi_mci_platform_data);
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
deleted file mode 100644
index 311baf149b07..000000000000
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/corgi_lcd.c
- *
- * Corgi/Spitz LCD Specific Code
- *
- * Copyright (C) 2005 Richard Purdie
- *
- * Connectivity:
- *   Corgi - LCD to ATI Imageon w100 (Wallaby)
- *   Spitz - LCD to PXA Framebuffer
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <mach/akita.h>
-#include <mach/corgi.h>
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
-#include <mach/sharpsl.h>
-#include <mach/spitz.h>
-#include <asm/hardware/scoop.h>
-#include <asm/mach/sharpsl_param.h>
-#include "generic.h"
-
-/* Register Addresses */
-#define RESCTL_ADRS     0x00
-#define PHACTRL_ADRS    0x01
-#define DUTYCTRL_ADRS   0x02
-#define POWERREG0_ADRS  0x03
-#define POWERREG1_ADRS  0x04
-#define GPOR3_ADRS      0x05
-#define PICTRL_ADRS     0x06
-#define POLCTRL_ADRS    0x07
-
-/* Register Bit Definitions */
-#define RESCTL_QVGA     0x01
-#define RESCTL_VGA      0x00
-
-#define POWER1_VW_ON    0x01  /* VW Supply FET ON */
-#define POWER1_GVSS_ON  0x02  /* GVSS(-8V) Power Supply ON */
-#define POWER1_VDD_ON   0x04  /* VDD(8V),SVSS(-4V) Power Supply ON */
-
-#define POWER1_VW_OFF   0x00  /* VW Supply FET OFF */
-#define POWER1_GVSS_OFF 0x00  /* GVSS(-8V) Power Supply OFF */
-#define POWER1_VDD_OFF  0x00  /* VDD(8V),SVSS(-4V) Power Supply OFF */
-
-#define POWER0_COM_DCLK 0x01  /* COM Voltage DC Bias DAC Serial Data Clock */
-#define POWER0_COM_DOUT 0x02  /* COM Voltage DC Bias DAC Serial Data Out */
-#define POWER0_DAC_ON   0x04  /* DAC Power Supply ON */
-#define POWER0_COM_ON   0x08  /* COM Power Supply ON */
-#define POWER0_VCC5_ON  0x10  /* VCC5 Power Supply ON */
-
-#define POWER0_DAC_OFF  0x00  /* DAC Power Supply OFF */
-#define POWER0_COM_OFF  0x00  /* COM Power Supply OFF */
-#define POWER0_VCC5_OFF 0x00  /* VCC5 Power Supply OFF */
-
-#define PICTRL_INIT_STATE      0x01
-#define PICTRL_INIOFF          0x02
-#define PICTRL_POWER_DOWN      0x04
-#define PICTRL_COM_SIGNAL_OFF  0x08
-#define PICTRL_DAC_SIGNAL_OFF  0x10
-
-#define POLCTRL_SYNC_POL_FALL  0x01
-#define POLCTRL_EN_POL_FALL    0x02
-#define POLCTRL_DATA_POL_FALL  0x04
-#define POLCTRL_SYNC_ACT_H     0x08
-#define POLCTRL_EN_ACT_L       0x10
-
-#define POLCTRL_SYNC_POL_RISE  0x00
-#define POLCTRL_EN_POL_RISE    0x00
-#define POLCTRL_DATA_POL_RISE  0x00
-#define POLCTRL_SYNC_ACT_L     0x00
-#define POLCTRL_EN_ACT_H       0x00
-
-#define PHACTRL_PHASE_MANUAL   0x01
-#define DEFAULT_PHAD_QVGA     (9)
-#define DEFAULT_COMADJ        (125)
-
-/*
- * This is only a psuedo I2C interface. We can't use the standard kernel
- * routines as the interface is write only. We just assume the data is acked...
- */
-static void lcdtg_ssp_i2c_send(u8 data)
-{
-        corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
-        udelay(10);
-}
-
-static void lcdtg_i2c_send_bit(u8 data)
-{
-        lcdtg_ssp_i2c_send(data);
-        lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
-        lcdtg_ssp_i2c_send(data);
-}
-
-static void lcdtg_i2c_send_start(u8 base)
-{
-        lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
-        lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
-        lcdtg_ssp_i2c_send(base);
-}
-
-static void lcdtg_i2c_send_stop(u8 base)
-{
-        lcdtg_ssp_i2c_send(base);
-        lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
-        lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
-}
-
-static void lcdtg_i2c_send_byte(u8 base, u8 data)
-{
-        int i;
-        for (i = 0; i < 8; i++) {
-                if (data & 0x80)
-                        lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
-                else
-                        lcdtg_i2c_send_bit(base);
-                data <<= 1;
-        }
-}
-
-static void lcdtg_i2c_wait_ack(u8 base)
-{
-        lcdtg_i2c_send_bit(base);
-}
-
-static void lcdtg_set_common_voltage(u8 base_data, u8 data)
-{
-        /* Set Common Voltage to M62332FP via I2C */
-        lcdtg_i2c_send_start(base_data);
-        lcdtg_i2c_send_byte(base_data, 0x9c);
-        lcdtg_i2c_wait_ack(base_data);
-        lcdtg_i2c_send_byte(base_data, 0x00);
-        lcdtg_i2c_wait_ack(base_data);
-        lcdtg_i2c_send_byte(base_data, data);
-        lcdtg_i2c_wait_ack(base_data);
-        lcdtg_i2c_send_stop(base_data);
-}
-
-/* Set Phase Adjust */
-static void lcdtg_set_phadadj(int mode)
-{
-        int adj;
-        switch(mode) {
-                case 480:
-                case 640:
-                        /* Setting for VGA */
-                        adj = sharpsl_param.phadadj;
-                        if (adj < 0) {
-                                adj = PHACTRL_PHASE_MANUAL;
-                        } else {
-                                adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
-                        }
-                        break;
-                case 240:
-                case 320:
-                default:
-                        /* Setting for QVGA */
-                        adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
-                        break;
-        }
-
-        corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
-}
-
-static int lcd_inited;
-
-void corgi_lcdtg_hw_init(int mode)
-{
-        if (!lcd_inited) {
-                int comadj;
-
-                /* Initialize Internal Logic & Port */
-                corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
-                                | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
-
-                corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
-                                | POWER0_COM_OFF | POWER0_VCC5_OFF);
-
-                corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
-
-                /* VDD(+8V), SVSS(-4V) ON */
-                corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
-                mdelay(3);
-
-                /* DAC ON */
-                corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
-                                | POWER0_COM_OFF | POWER0_VCC5_OFF);
-
-                /* INIB = H, INI = L  */
-                /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
-                corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
-
-                /* Set Common Voltage */
-                comadj = sharpsl_param.comadj;
-                if (comadj < 0)
-                        comadj = DEFAULT_COMADJ;
-                lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
-
-                /* VCC5 ON, DAC ON */
-                corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
-                                POWER0_COM_OFF | POWER0_VCC5_ON);
-
-                /* GVSS(-8V) ON, VDD ON */
-                corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
-                mdelay(2);
-
-                /* COM SIGNAL ON (PICTL[3] = L) */
-                corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
-
-                /* COM ON, DAC ON, VCC5_ON */
-                corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
-                                | POWER0_COM_ON | POWER0_VCC5_ON);
-
-                /* VW ON, GVSS ON, VDD ON */
-                corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
-
-                /* Signals output enable */
-                corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
-
-                /* Set Phase Adjust */
-                lcdtg_set_phadadj(mode);
-
-                /* Initialize for Input Signals from ATI */
-                corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
-                                | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
-                udelay(1000);
-
-                lcd_inited=1;
-        } else {
-                lcdtg_set_phadadj(mode);
-        }
-
-        switch(mode) {
-                case 480:
-                case 640:
-                        /* Set Lcd Resolution (VGA) */
-                        corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
-                        break;
-                case 240:
-                case 320:
-                default:
-                        /* Set Lcd Resolution (QVGA) */
-                        corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
-                        break;
-        }
-}
-
-void corgi_lcdtg_suspend(void)
-{
-        /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
-        mdelay(34);
-
-        /* (1)VW OFF */
-        corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
-
-        /* (2)COM OFF */
-        corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
-        corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
-
-        /* (3)Set Common Voltage Bias 0V */
-        lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
-
-        /* (4)GVSS OFF */
-        corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
-
-        /* (5)VCC5 OFF */
-        corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
-
-        /* (6)Set PDWN, INIOFF, DACOFF */
-        corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
-                        PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
-
-        /* (7)DAC OFF */
-        corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
-
-        /* (8)VDD OFF */
-        corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
-
-        lcd_inited = 0;
-}
-
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 35bbfccd2df3..eb7d6c94aa42 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -21,7 +21,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
-#include <asm/hardware/scoop.h>
 
 #include <mach/sharpsl.h>
 #include <mach/corgi.h>
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
deleted file mode 100644
index 8e2f2215c4ba..000000000000
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- *  SSP control code for Sharp Corgi devices
- *
- *  Copyright (c) 2004-2005 Richard Purdie
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-
-#include <mach/ssp.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-gpio.h>
-#include <mach/regs-ssp.h>
-#include "sharpsl.h"
-
-static DEFINE_SPINLOCK(corgi_ssp_lock);
-static struct ssp_dev corgi_ssp_dev;
-static struct ssp_state corgi_ssp_state;
-static struct corgissp_machinfo *ssp_machinfo;
-
-/*
- * There are three devices connected to the SSP interface:
- *   1. A touchscreen controller (TI ADS7846 compatible)
- *   2. An LCD controller (with some Backlight functionality)
- *   3. A battery monitoring IC (Maxim MAX1111)
- *
- * Each device uses a different speed/mode of communication.
- *
- * The touchscreen is very sensitive and the most frequently used
- * so the port is left configured for this.
- *
- * Devices are selected using Chip Selects on GPIOs.
- */
-
-/*
- *  ADS7846 Routines
- */
-unsigned long corgi_ssp_ads7846_putget(ulong data)
-{
-        unsigned long flag;
-        u32 ret = 0;
-
-        spin_lock_irqsave(&corgi_ssp_lock, flag);
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
-
-        ssp_write_word(&corgi_ssp_dev,data);
-        ssp_read_word(&corgi_ssp_dev, &ret);
-
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
-        spin_unlock_irqrestore(&corgi_ssp_lock, flag);
-
-        return ret;
-}
-
-/*
- * NOTE: These functions should always be called in interrupt context
- * and use the _lock and _unlock functions. They are very time sensitive.
- */
-void corgi_ssp_ads7846_lock(void)
-{
-        spin_lock(&corgi_ssp_lock);
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
-}
-
-void corgi_ssp_ads7846_unlock(void)
-{
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
-        spin_unlock(&corgi_ssp_lock);
-}
-
-void corgi_ssp_ads7846_put(ulong data)
-{
-        ssp_write_word(&corgi_ssp_dev,data);
-}
-
-unsigned long corgi_ssp_ads7846_get(void)
-{
-        u32 ret = 0;
-        ssp_read_word(&corgi_ssp_dev, &ret);
-        return ret;
-}
-
-EXPORT_SYMBOL(corgi_ssp_ads7846_putget);
-EXPORT_SYMBOL(corgi_ssp_ads7846_lock);
-EXPORT_SYMBOL(corgi_ssp_ads7846_unlock);
-EXPORT_SYMBOL(corgi_ssp_ads7846_put);
-EXPORT_SYMBOL(corgi_ssp_ads7846_get);
-
-
-/*
- *  LCD/Backlight Routines
- */
-unsigned long corgi_ssp_dac_put(ulong data)
-{
-        unsigned long flag, sscr1 = SSCR1_SPH;
-        u32 tmp;
-
-        spin_lock_irqsave(&corgi_ssp_lock, flag);
-
-        if (machine_is_spitz() || machine_is_akita() || machine_is_borzoi())
-                sscr1 = 0;
-
-        ssp_disable(&corgi_ssp_dev);
-        ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), sscr1, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_lcdcon));
-        ssp_enable(&corgi_ssp_dev);
-
-        if (ssp_machinfo->cs_lcdcon >= 0)
-                GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
-        ssp_write_word(&corgi_ssp_dev,data);
-        /* Read null data back from device to prevent SSP overflow */
-        ssp_read_word(&corgi_ssp_dev, &tmp);
-        if (ssp_machinfo->cs_lcdcon >= 0)
-                GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
-
-        ssp_disable(&corgi_ssp_dev);
-        ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
-        ssp_enable(&corgi_ssp_dev);
-
-        spin_unlock_irqrestore(&corgi_ssp_lock, flag);
-
-        return 0;
-}
-
-void corgi_ssp_lcdtg_send(u8 adrs, u8 data)
-{
-        corgi_ssp_dac_put(((adrs & 0x07) << 5) | (data & 0x1f));
-}
-
-void corgi_ssp_blduty_set(int duty)
-{
-        corgi_ssp_lcdtg_send(0x02,duty);
-}
-
-EXPORT_SYMBOL(corgi_ssp_lcdtg_send);
-EXPORT_SYMBOL(corgi_ssp_blduty_set);
-
-/*
- *  Max1111 Routines
- */
-int corgi_ssp_max1111_get(ulong data)
-{
-        unsigned long flag;
-        long voltage = 0, voltage1 = 0, voltage2 = 0;
-
-        spin_lock_irqsave(&corgi_ssp_lock, flag);
-        if (ssp_machinfo->cs_max1111 >= 0)
-                GPCR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
-        ssp_disable(&corgi_ssp_dev);
-        ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_max1111));
-        ssp_enable(&corgi_ssp_dev);
-
-        udelay(1);
-
-        /* TB1/RB1 */
-        ssp_write_word(&corgi_ssp_dev,data);
-        ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */
-
-        /* TB12/RB2 */
-        ssp_write_word(&corgi_ssp_dev,0);
-        ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1);
-
-        /* TB13/RB3*/
-        ssp_write_word(&corgi_ssp_dev,0);
-        ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2);
-
-        ssp_disable(&corgi_ssp_dev);
-        ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
-        ssp_enable(&corgi_ssp_dev);
-        if (ssp_machinfo->cs_max1111 >= 0)
-                GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
-        spin_unlock_irqrestore(&corgi_ssp_lock, flag);
-
-        if (voltage1 & 0xc0 || voltage2 & 0x3f)
-                voltage = -1;
-        else
-                voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03);
-
-        return voltage;
-}
-
-EXPORT_SYMBOL(corgi_ssp_max1111_get);
-
-/*
- *  Support Routines
- */
-
-void __init corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo)
-{
-        ssp_machinfo = machinfo;
-}
-
-static int __init corgi_ssp_probe(struct platform_device *dev)
-{
-        int ret;
-
-        /* Chip Select - Disable All */
-        if (ssp_machinfo->cs_lcdcon >= 0)
-                pxa_gpio_mode(ssp_machinfo->cs_lcdcon  | GPIO_OUT | GPIO_DFLT_HIGH);
-        if (ssp_machinfo->cs_max1111 >= 0)
-                pxa_gpio_mode(ssp_machinfo->cs_max1111 | GPIO_OUT | GPIO_DFLT_HIGH);
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                pxa_gpio_mode(ssp_machinfo->cs_ads7846 | GPIO_OUT | GPIO_DFLT_HIGH);
-
-        ret = ssp_init(&corgi_ssp_dev, ssp_machinfo->port, 0);
-
-        if (ret)
-                printk(KERN_ERR "Unable to register SSP handler!\n");
-        else {
-                ssp_disable(&corgi_ssp_dev);
-                ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
-                ssp_enable(&corgi_ssp_dev);
-        }
-
-        return ret;
-}
-
-static int corgi_ssp_remove(struct platform_device *dev)
-{
-        ssp_exit(&corgi_ssp_dev);
-        return 0;
-}
-
-static int corgi_ssp_suspend(struct platform_device *dev, pm_message_t state)
-{
-        ssp_flush(&corgi_ssp_dev);
-        ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state);
-
-        return 0;
-}
-
-static int corgi_ssp_resume(struct platform_device *dev)
-{
-        if (ssp_machinfo->cs_lcdcon >= 0)
-                GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);  /* High - Disable LCD Control/Timing Gen */
-        if (ssp_machinfo->cs_max1111 >= 0)
-                GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); /* High - Disable MAX1111*/
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); /* High - Disable ADS7846*/
-        ssp_restore_state(&corgi_ssp_dev,&corgi_ssp_state);
-        ssp_enable(&corgi_ssp_dev);
-
-        return 0;
-}
-
-static struct platform_driver corgissp_driver = {
-        .probe          = corgi_ssp_probe,
-        .remove         = corgi_ssp_remove,
-        .suspend        = corgi_ssp_suspend,
-        .resume         = corgi_ssp_resume,
-        .driver         = {
-                .name   = "corgi-ssp",
-        },
-};
-
-int __init corgi_ssp_init(void)
-{
-        return platform_driver_register(&corgissp_driver);
-}
-
-arch_initcall(corgi_ssp_init);
diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 6f5569bac131..d82528e74bd0 100644
--- a/arch/arm/mach-pxa/cpu-pxa.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/mach-pxa/cpu-pxa.c
+ *  linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c
  *
  *  Copyright (C) 2002,2003 Intrinsyc Software
  *
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
new file mode 100644
index 000000000000..1ea0c9c0adaf
--- /dev/null
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -0,0 +1,258 @@
+/*
+ * linux/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+ *
+ * Copyright (C) 2008 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/cpufreq.h>
+
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa3xx-regs.h>
+
+#include "generic.h"
+
+#define HSS_104M        (0)
+#define HSS_156M        (1)
+#define HSS_208M        (2)
+#define HSS_312M        (3)
+
+#define SMCFS_78M       (0)
+#define SMCFS_104M      (2)
+#define SMCFS_208M      (5)
+
+#define SFLFS_104M      (0)
+#define SFLFS_156M      (1)
+#define SFLFS_208M      (2)
+#define SFLFS_312M      (3)
+
+#define XSPCLK_156M     (0)
+#define XSPCLK_NONE     (3)
+
+#define DMCFS_26M       (0)
+#define DMCFS_260M      (3)
+
+struct pxa3xx_freq_info {
+        unsigned int cpufreq_mhz;
+        unsigned int core_xl : 5;
+        unsigned int core_xn : 3;
+        unsigned int hss : 2;
+        unsigned int dmcfs : 2;
+        unsigned int smcfs : 3;
+        unsigned int sflfs : 2;
+        unsigned int df_clkdiv : 3;
+
+        int     vcc_core;       /* in mV */
+        int     vcc_sram;       /* in mV */
+};
+
+#define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
+{                                                                       \
+        .cpufreq_mhz    = cpufreq,                                      \
+        .core_xl        = _xl,                                          \
+        .core_xn        = _xn,                                          \
+        .hss            = HSS_##_hss##M,                                \
+        .dmcfs          = DMCFS_##_dmc##M,                              \
+        .smcfs          = SMCFS_##_smc##M,                              \
+        .sflfs          = SFLFS_##_sfl##M,                              \
+        .df_clkdiv      = _dfi,                                         \
+        .vcc_core       = vcore,                                        \
+        .vcc_sram       = vsram,                                        \
+}
+
+static struct pxa3xx_freq_info pxa300_freqs[] = {
+        /*  CPU XL XN  HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
+        OP(104,  8, 1, 104, 260,  78, 104, 3, 1000, 1100), /* 104MHz */
+        OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
+        OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
+        OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
+};
+
+static struct pxa3xx_freq_info pxa320_freqs[] = {
+        /*  CPU XL XN  HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
+        OP(104,  8, 1, 104, 260,  78, 104, 3, 1000, 1100), /* 104MHz */
+        OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
+        OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
+        OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
+        OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
+};
+
+static unsigned int pxa3xx_freqs_num;
+static struct pxa3xx_freq_info *pxa3xx_freqs;
+static struct cpufreq_frequency_table *pxa3xx_freqs_table;
+
+static int setup_freqs_table(struct cpufreq_policy *policy,
+                             struct pxa3xx_freq_info *freqs, int num)
+{
+        struct cpufreq_frequency_table *table;
+        int i;
+
+        table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
+        if (table == NULL)
+                return -ENOMEM;
+
+        for (i = 0; i < num; i++) {
+                table[i].index = i;
+                table[i].frequency = freqs[i].cpufreq_mhz * 1000;
+        }
+        table[num].frequency = i;
+        table[num].frequency = CPUFREQ_TABLE_END;
+
+        pxa3xx_freqs = freqs;
+        pxa3xx_freqs_num = num;
+        pxa3xx_freqs_table = table;
+
+        return cpufreq_frequency_table_cpuinfo(policy, table);
+}
+
+static void __update_core_freq(struct pxa3xx_freq_info *info)
+{
+        uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
+        uint32_t accr = ACCR;
+        uint32_t xclkcfg;
+
+        accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
+        accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);
+
+        /* No clock until core PLL is re-locked */
+        accr |= ACCR_XSPCLK(XSPCLK_NONE);
+
+        xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2;     /* turbo bit */
+
+        ACCR = accr;
+        __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
+
+        while ((ACSR & mask) != (accr & mask))
+                cpu_relax();
+}
+
+static void __update_bus_freq(struct pxa3xx_freq_info *info)
+{
+        uint32_t mask;
+        uint32_t accr = ACCR;
+
+        mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
+                ACCR_DMCFS_MASK;
+
+        accr &= ~mask;
+        accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
+                ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);
+
+        ACCR = accr;
+
+        while ((ACSR & mask) != (accr & mask))
+                cpu_relax();
+}
+
+static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
+{
+        return cpufreq_frequency_table_verify(policy, pxa3xx_freqs_table);
+}
+
+static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
+{
+        return get_clk_frequency_khz(0);
+}
+
+static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
+                              unsigned int target_freq,
+                              unsigned int relation)
+{
+        struct pxa3xx_freq_info *next;
+        struct cpufreq_freqs freqs;
+        unsigned long flags;
+        int idx;
+
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        /* Lookup the next frequency */
+        if (cpufreq_frequency_table_target(policy, pxa3xx_freqs_table,
+                                target_freq, relation, &idx))
+                return -EINVAL;
+
+        next = &pxa3xx_freqs[idx];
+
+        freqs.old = policy->cur;
+        freqs.new = next->cpufreq_mhz * 1000;
+        freqs.cpu = policy->cpu;
+
+        pr_debug("CPU frequency from %d MHz to %d MHz%s\n",
+                        freqs.old / 1000, freqs.new / 1000,
+                        (freqs.old == freqs.new) ? " (skipped)" : "");
+
+        if (freqs.old == target_freq)
+                return 0;
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+        local_irq_save(flags);
+        __update_core_freq(next);
+        __update_bus_freq(next);
+        local_irq_restore(flags);
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        return 0;
+}
+
+static __init int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
+{
+        int ret = -EINVAL;
+
+        /* set default policy and cpuinfo */
+        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+        policy->cpuinfo.min_freq = 104000;
+        policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
+        policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
+        policy->cur = policy->min = policy->max = get_clk_frequency_khz(0);
+
+        if (cpu_is_pxa300() || cpu_is_pxa310())
+                ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
+
+        if (cpu_is_pxa320())
+                ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa320_freqs));
+
+        if (ret) {
+                pr_err("failed to setup frequency table\n");
+                return ret;
+        }
+
+        pr_info("CPUFREQ support for PXA3xx initialized\n");
+        return 0;
+}
+
+static struct cpufreq_driver pxa3xx_cpufreq_driver = {
+        .verify         = pxa3xx_cpufreq_verify,
+        .target         = pxa3xx_cpufreq_set,
+        .init           = pxa3xx_cpufreq_init,
+        .get            = pxa3xx_cpufreq_get,
+        .name           = "pxa3xx-cpufreq",
+};
+
+static int __init cpufreq_init(void)
+{
+        if (cpu_is_pxa3xx())
+                return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
+
+        return 0;
+}
+module_init(cpufreq_init);
+
+static void __exit cpufreq_exit(void)
+{
+        cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
+}
+module_exit(cpufreq_exit);
+
+MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 887c738f5911..bb04af4b0aa3 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -32,5 +32,6 @@ extern struct platform_device pxa27x_device_pwm0;
 extern struct platform_device pxa27x_device_pwm1;
 
 extern struct platform_device pxa3xx_device_nand;
+extern struct platform_device pxa3xx_device_i2c_power;
 
 void __init pxa_register_device(struct platform_device *dev, void *data);
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c
new file mode 100644
index 000000000000..d488eded2058
--- /dev/null
+++ b/arch/arm/mach-pxa/e330.c
@@ -0,0 +1,43 @@
+/*
+ * Hardware definitions for the Toshiba eseries PDAs
+ *
+ * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
+ *
+ * This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/mfp-pxa25x.h>
+#include <mach/hardware.h>
+#include <mach/udc.h>
+
+#include "generic.h"
+#include "eseries.h"
+
+static void __init e330_init(void)
+{
+        pxa_set_udc_info(&e7xx_udc_mach_info);
+}
+
+MACHINE_START(E330, "Toshiba e330")
+        /* Maintainer: Ian Molton (spyro@f2s.com) */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa25x_init_irq,
+        .fixup          = eseries_fixup,
+        .init_machine   = e330_init,
+        .timer          = &pxa_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c
new file mode 100644
index 000000000000..8ecbc5479828
--- /dev/null
+++ b/arch/arm/mach-pxa/e350.c
@@ -0,0 +1,43 @@
+/*
+ * Hardware definitions for the Toshiba eseries PDAs
+ *
+ * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
+ *
+ * This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/mfp-pxa25x.h>
+#include <mach/hardware.h>
+#include <mach/udc.h>
+
+#include "generic.h"
+#include "eseries.h"
+
+static void __init e350_init(void)
+{
+        pxa_set_udc_info(&e7xx_udc_mach_info);
+}
+
+MACHINE_START(E350, "Toshiba e350")
+        /* Maintainer: Ian Molton (spyro@f2s.com) */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa25x_init_irq,
+        .fixup          = eseries_fixup,
+        .init_machine   = e350_init,
+        .timer          = &pxa_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c
new file mode 100644
index 000000000000..544bbaa20621
--- /dev/null
+++ b/arch/arm/mach-pxa/e400.c
@@ -0,0 +1,94 @@
+/*
+ * Hardware definitions for the Toshiba eseries PDAs
+ *
+ * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
+ *
+ * This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/pxa-regs.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/hardware.h>
+
+#include <mach/pxafb.h>
+#include <mach/udc.h>
+
+#include "generic.h"
+#include "eseries.h"
+
+/* ------------------------ E400 LCD definitions ------------------------ */
+
+static struct pxafb_mode_info e400_pxafb_mode_info = {
+        .pixclock       = 140703,
+        .xres           = 240,
+        .yres           = 320,
+        .bpp            = 16,
+        .hsync_len      = 4,
+        .left_margin    = 28,
+        .right_margin   = 8,
+        .vsync_len      = 3,
+        .upper_margin   = 5,
+        .lower_margin   = 6,
+        .sync           = 0,
+};
+
+static struct pxafb_mach_info e400_pxafb_mach_info = {
+        .modes          = &e400_pxafb_mode_info,
+        .num_modes      = 1,
+        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3          = 0,
+        .pxafb_backlight_power  = NULL,
+};
+
+/* ------------------------ E400 MFP config ----------------------------- */
+
+static unsigned long e400_pin_config[] __initdata = {
+        /* Chip selects */
+        GPIO15_nCS_1,   /* CS1 - Flash */
+        GPIO80_nCS_4,   /* CS4 - TMIO */
+
+        /* Clocks */
+        GPIO12_32KHz,
+
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
+
+        /* wakeup */
+        GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
+};
+
+/* ---------------------------------------------------------------------- */
+
+static void __init e400_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config));
+        set_pxa_fb_info(&e400_pxafb_mach_info);
+        pxa_set_udc_info(&e7xx_udc_mach_info);
+}
+
+MACHINE_START(E400, "Toshiba e400")
+        /* Maintainer: Ian Molton (spyro@f2s.com) */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa25x_init_irq,
+        .fixup          = eseries_fixup,
+        .init_machine   = e400_init,
+        .timer          = &pxa_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/e400_lcd.c b/arch/arm/mach-pxa/e400_lcd.c
deleted file mode 100644
index 263884165f57..000000000000
--- a/arch/arm/mach-pxa/e400_lcd.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * e400_lcd.c
- *
- * (c) 2005 Ian Molton <spyro@f2s.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-
-#include <asm/mach-types.h>
-#include <mach/pxa-regs.h>
-#include <mach/pxafb.h>
-
-static struct pxafb_mode_info e400_pxafb_mode_info = {
-        .pixclock       = 140703,
-        .xres           = 240,
-        .yres           = 320,
-        .bpp            = 16,
-        .hsync_len      = 4,
-        .left_margin    = 28,
-        .right_margin   = 8,
-        .vsync_len      = 3,
-        .upper_margin   = 5,
-        .lower_margin   = 6,
-        .sync           = 0,
-};
-
-static struct pxafb_mach_info e400_pxafb_mach_info = {
-        .modes          = &e400_pxafb_mode_info,
-        .num_modes      = 1,
-        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
-        .lccr3          = 0,
-        .pxafb_backlight_power  = NULL,
-};
-
-static int __init e400_lcd_init(void)
-{
-        if (!machine_is_e400())
-                return -ENODEV;
-
-        set_pxa_fb_info(&e400_pxafb_mach_info);
-        return 0;
-}
-
-module_init(e400_lcd_init);
-
-MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
-MODULE_DESCRIPTION("e400 lcd driver");
-MODULE_LICENSE("GPLv2");
-
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c
new file mode 100644
index 000000000000..c57a15b37f0d
--- /dev/null
+++ b/arch/arm/mach-pxa/e740.c
@@ -0,0 +1,169 @@
+/*
+ * Hardware definitions for the Toshiba eseries PDAs
+ *
+ * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
+ *
+ * This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+
+#include <video/w100fb.h>
+
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/mfp-pxa25x.h>
+#include <mach/hardware.h>
+#include <mach/udc.h>
+
+#include "generic.h"
+#include "eseries.h"
+
+
+/* ------------------------ e740 video support --------------------------- */
+
+static struct w100_gen_regs e740_lcd_regs = {
+        .lcd_format =            0x00008023,
+        .lcdd_cntl1 =            0x0f000000,
+        .lcdd_cntl2 =            0x0003ffff,
+        .genlcd_cntl1 =          0x00ffff03,
+        .genlcd_cntl2 =          0x003c0f03,
+        .genlcd_cntl3 =          0x000143aa,
+};
+
+static struct w100_mode e740_lcd_mode = {
+        .xres            = 240,
+        .yres            = 320,
+        .left_margin     = 20,
+        .right_margin    = 28,
+        .upper_margin    = 9,
+        .lower_margin    = 8,
+        .crtc_ss         = 0x80140013,
+        .crtc_ls         = 0x81150110,
+        .crtc_gs         = 0x80050005,
+        .crtc_vpos_gs    = 0x000a0009,
+        .crtc_rev        = 0x0040010a,
+        .crtc_dclk       = 0xa906000a,
+        .crtc_gclk       = 0x80050108,
+        .crtc_goe        = 0x80050108,
+        .pll_freq        = 57,
+        .pixclk_divider         = 4,
+        .pixclk_divider_rotated = 4,
+        .pixclk_src     = CLK_SRC_XTAL,
+        .sysclk_divider  = 1,
+        .sysclk_src     = CLK_SRC_PLL,
+        .crtc_ps1_active =       0x41060010,
+};
+
+static struct w100_gpio_regs e740_w100_gpio_info = {
+        .init_data1 = 0x21002103,
+        .gpio_dir1  = 0xffffdeff,
+        .gpio_oe1   = 0x03c00643,
+        .init_data2 = 0x003f003f,
+        .gpio_dir2  = 0xffffffff,
+        .gpio_oe2   = 0x000000ff,
+};
+
+static struct w100fb_mach_info e740_fb_info = {
+        .modelist   = &e740_lcd_mode,
+        .num_modes  = 1,
+        .regs       = &e740_lcd_regs,
+        .gpio       = &e740_w100_gpio_info,
+        .xtal_freq = 14318000,
+        .xtal_dbl   = 1,
+};
+
+static struct resource e740_fb_resources[] = {
+        [0] = {
+                .start          = 0x0c000000,
+                .end            = 0x0cffffff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device e740_fb_device = {
+        .name           = "w100fb",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &e740_fb_info,
+        },
+        .num_resources  = ARRAY_SIZE(e740_fb_resources),
+        .resource       = e740_fb_resources,
+};
+
+/* --------------------------- MFP Pin config -------------------------- */
+
+static unsigned long e740_pin_config[] __initdata = {
+        /* Chip selects */
+        GPIO15_nCS_1,   /* CS1 - Flash */
+        GPIO79_nCS_3,   /* CS3 - IMAGEON */
+        GPIO80_nCS_4,   /* CS4 - TMIO */
+
+        /* Clocks */
+        GPIO12_32KHz,
+
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
+
+        /* PC Card */
+        GPIO8_GPIO,   /* CD0 */
+        GPIO44_GPIO,  /* CD1 */
+        GPIO11_GPIO,  /* IRQ0 */
+        GPIO6_GPIO,   /* IRQ1 */
+        GPIO27_GPIO,  /* RST0 */
+        GPIO24_GPIO,  /* RST1 */
+        GPIO20_GPIO,  /* PWR0 */
+        GPIO23_GPIO,  /* PWR1 */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO52_nPCE_1,
+        GPIO53_nPCE_2,
+        GPIO54_nPSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* wakeup */
+        GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
+};
+
+/* ----------------------------------------------------------------------- */
+
+static struct platform_device *devices[] __initdata = {
+        &e740_fb_device,
+};
+
+static void __init e740_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        pxa_set_udc_info(&e7xx_udc_mach_info);
+}
+
+MACHINE_START(E740, "Toshiba e740")
+        /* Maintainer: Ian Molton (spyro@f2s.com) */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa25x_init_irq,
+        .fixup          = eseries_fixup,
+        .init_machine   = e740_init,
+        .timer          = &pxa_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/e740_lcd.c b/arch/arm/mach-pxa/e740_lcd.c
deleted file mode 100644
index 26bd599af178..000000000000
--- a/arch/arm/mach-pxa/e740_lcd.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* e740_lcd.c
- *
- * This file contains the definitions for the LCD timings and functions
- * to control the LCD power / frontlighting via the w100fb driver.
- *
- * (c) 2005 Ian Molton <spyro@f2s.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/fb.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-types.h>
-
-#include <video/w100fb.h>
-
-/*
-**potential** shutdown routine - to be investigated
-devmem2 0x0c010528 w 0xff3fff00
-devmem2 0x0c010190 w 0x7FFF8000
-devmem2 0x0c0101b0 w 0x00FF0000
-devmem2 0x0c01008c w 0x00000000
-devmem2 0x0c010080 w 0x000000bf
-devmem2 0x0c010098 w 0x00000015
-devmem2 0x0c010088 w 0x4b000204
-devmem2 0x0c010098 w 0x0000001d
-*/
-
-static struct w100_gen_regs e740_lcd_regs = {
-        .lcd_format =            0x00008023,
-        .lcdd_cntl1 =            0x0f000000,
-        .lcdd_cntl2 =            0x0003ffff,
-        .genlcd_cntl1 =          0x00ffff03,
-        .genlcd_cntl2 =          0x003c0f03,
-        .genlcd_cntl3 =          0x000143aa,
-};
-
-static struct w100_mode e740_lcd_mode = {
-        .xres            = 240,
-        .yres            = 320,
-        .left_margin     = 20,
-        .right_margin    = 28,
-        .upper_margin    = 9,
-        .lower_margin    = 8,
-        .crtc_ss         = 0x80140013,
-        .crtc_ls         = 0x81150110,
-        .crtc_gs         = 0x80050005,
-        .crtc_vpos_gs    = 0x000a0009,
-        .crtc_rev        = 0x0040010a,
-        .crtc_dclk       = 0xa906000a,
-        .crtc_gclk       = 0x80050108,
-        .crtc_goe        = 0x80050108,
-        .pll_freq        = 57,
-        .pixclk_divider         = 4,
-        .pixclk_divider_rotated = 4,
-        .pixclk_src     = CLK_SRC_XTAL,
-        .sysclk_divider  = 1,
-        .sysclk_src     = CLK_SRC_PLL,
-        .crtc_ps1_active =       0x41060010,
-};
-
-
-static struct w100_gpio_regs e740_w100_gpio_info = {
-        .init_data1 = 0x21002103,
-        .gpio_dir1  = 0xffffdeff,
-        .gpio_oe1   = 0x03c00643,
-        .init_data2 = 0x003f003f,
-        .gpio_dir2  = 0xffffffff,
-        .gpio_oe2   = 0x000000ff,
-};
-
-static struct w100fb_mach_info e740_fb_info = {
-        .modelist   = &e740_lcd_mode,
-        .num_modes  = 1,
-        .regs       = &e740_lcd_regs,
-        .gpio       = &e740_w100_gpio_info,
-        .xtal_freq = 14318000,
-        .xtal_dbl   = 1,
-};
-
-static struct resource e740_fb_resources[] = {
-        [0] = {
-                .start          = 0x0c000000,
-                .end            = 0x0cffffff,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-/* ----------------------- device declarations -------------------------- */
-
-
-static struct platform_device e740_fb_device = {
-        .name           = "w100fb",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &e740_fb_info,
-        },
-        .num_resources  = ARRAY_SIZE(e740_fb_resources),
-        .resource       = e740_fb_resources,
-};
-
-static int e740_lcd_init(void)
-{
-        int ret;
-
-        if (!machine_is_e740())
-                return -ENODEV;
-
-        return platform_device_register(&e740_fb_device);
-}
-
-module_init(e740_lcd_init);
-
-MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
-MODULE_DESCRIPTION("e740 lcd driver");
-MODULE_LICENSE("GPLv2");
diff --git a/arch/arm/mach-pxa/e750_lcd.c b/arch/arm/mach-pxa/e750.c
index 75edc3b5390f..640e738b85df 100644
--- a/arch/arm/mach-pxa/e750_lcd.c
+++ b/arch/arm/mach-pxa/e750.c
@@ -1,25 +1,35 @@
-/* e750_lcd.c
+/*
+ * Hardware definitions for the Toshiba eseries PDAs
  *
- * This file contains the definitions for the LCD timings and functions
- * to control the LCD power / frontlighting via the w100fb driver.
+ * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
  *
- * (c) 2005 Ian Molton <spyro@f2s.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
  *
  */
 
-#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
 #include <linux/device.h>
-#include <linux/fb.h>
-#include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/fb.h>
+
+#include <video/w100fb.h>
 
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <video/w100fb.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/hardware.h>
+#include <mach/udc.h>
+
+#include "generic.h"
+#include "eseries.h"
+
+/* ---------------------- E750 LCD definitions -------------------- */
 
 static struct w100_gen_regs e750_lcd_regs = {
         .lcd_format =            0x00008003,
@@ -54,7 +64,6 @@ static struct w100_mode e750_lcd_mode = {
         .sysclk_src     = CLK_SRC_PLL,
 };
 
-
 static struct w100_gpio_regs e750_w100_gpio_info = {
         .init_data1 = 0x01192f1b,
         .gpio_dir1  = 0xd5ffdeff,
@@ -81,9 +90,6 @@ static struct resource e750_fb_resources[] = {
         },
 };
 
-/* ----------------------- device declarations -------------------------- */
-
-
 static struct platform_device e750_fb_device = {
         .name           = "w100fb",
         .id             = -1,
@@ -94,16 +100,27 @@ static struct platform_device e750_fb_device = {
         .resource       = e750_fb_resources,
 };
 
-static int e750_lcd_init(void)
-{
-        if (!machine_is_e750())
-                return -ENODEV;
+/* ----------------------------------------------------------------------- */
 
-        return platform_device_register(&e750_fb_device);
+static struct platform_device *devices[] __initdata = {
+        &e750_fb_device,
+};
+
+static void __init e750_init(void)
+{
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        pxa_set_udc_info(&e7xx_udc_mach_info);
 }
 
-module_init(e750_lcd_init);
+MACHINE_START(E750, "Toshiba e750")
+        /* Maintainer: Ian Molton (spyro@f2s.com) */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa25x_init_irq,
+        .fixup          = eseries_fixup,
+        .init_machine   = e750_init,
+        .timer          = &pxa_timer,
+MACHINE_END
 
-MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
-MODULE_DESCRIPTION("e750 lcd driver");
-MODULE_LICENSE("GPLv2");
diff --git a/arch/arm/mach-pxa/e800_lcd.c b/arch/arm/mach-pxa/e800.c
index e6aeab0ebc22..a293e09bfe25 100644
--- a/arch/arm/mach-pxa/e800_lcd.c
+++ b/arch/arm/mach-pxa/e800.c
@@ -1,25 +1,36 @@
-/* e800_lcd.c
+/*
+ * Hardware definitions for the Toshiba eseries PDAs
  *
- * This file contains the definitions for the LCD timings and functions
- * to control the LCD power / frontlighting via the w100fb driver.
+ * Copyright (c) 2003 Ian Molton <spyro@f2s.com>
  *
- * (c) 2005 Ian Molton <spyro@f2s.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
  *
  */
 
-#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
 #include <linux/device.h>
-#include <linux/fb.h>
-#include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/fb.h>
+
+#include <video/w100fb.h>
 
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
-#include <video/w100fb.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/hardware.h>
+#include <mach/eseries-gpio.h>
+#include <mach/udc.h>
+
+#include "generic.h"
+#include "eseries.h"
+
+/* ------------------------ e800 LCD definitions ------------------------- */
 
 static struct w100_gen_regs e800_lcd_regs = {
         .lcd_format =            0x00008003,
@@ -71,8 +82,8 @@ static struct w100_mode e800_lcd_mode[2] = {
                 .crtc_goe        = 0x80cc0015,
                 .crtc_ps1_active = 0x00000000,
                 .pll_freq        = 100,
-                .pixclk_divider         = 6, /* Wince uses 14 which gives a 7MHz pclk. */
-                .pixclk_divider_rotated = 6, /* we want a 14MHz one (much nicer to look at) */
+                .pixclk_divider         = 6, /* Wince uses 14 which gives a */
+                .pixclk_divider_rotated = 6, /* 7MHz Pclk. We use a 14MHz one */
                 .pixclk_src     = CLK_SRC_PLL,
                 .sysclk_divider  = 0,
                 .sysclk_src     = CLK_SRC_PLL,
@@ -131,9 +142,6 @@ static struct resource e800_fb_resources[] = {
         },
 };
 
-/* ----------------------- device declarations -------------------------- */
-
-
 static struct platform_device e800_fb_device = {
         .name           = "w100fb",
         .id             = -1,
@@ -144,16 +152,35 @@ static struct platform_device e800_fb_device = {
         .resource       = e800_fb_resources,
 };
 
-static int e800_lcd_init(void)
-{
-        if (!machine_is_e800())
-                return -ENODEV;
+/* --------------------------- UDC definitions --------------------------- */
+
+static struct pxa2xx_udc_mach_info e800_udc_mach_info = {
+        .gpio_vbus   = GPIO_E800_USB_DISC,
+        .gpio_pullup = GPIO_E800_USB_PULLUP,
+        .gpio_pullup_inverted = 1
+};
 
-        return platform_device_register(&e800_fb_device);
+/* ----------------------------------------------------------------------- */
+
+static struct platform_device *devices[] __initdata = {
+        &e800_fb_device,
+};
+
+static void __init e800_init(void)
+{
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        pxa_set_udc_info(&e800_udc_mach_info);
 }
 
-module_init(e800_lcd_init);
+MACHINE_START(E800, "Toshiba e800")
+        /* Maintainer: Ian Molton (spyro@f2s.com) */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa25x_init_irq,
+        .fixup          = eseries_fixup,
+        .init_machine   = e800_init,
+        .timer          = &pxa_timer,
+MACHINE_END
 
-MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
-MODULE_DESCRIPTION("e800 lcd driver");
-MODULE_LICENSE("GPLv2");
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 7a0a681a5847..f5ed8038ede5 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -373,10 +373,6 @@ static inline void em_x270_init_nand(void) {}
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 static int em_x270_ohci_init(struct device *dev)
 {
-        /* Set the Power Control Polarity Low */
-        UHCHR = (UHCHR | UHCHR_PCPL) &
-                ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
-
         /* enable port 2 transiever */
         UP2OCR = UP2OCR_HXS | UP2OCR_HXOE;
 
@@ -385,6 +381,7 @@ static int em_x270_ohci_init(struct device *dev)
 
 static struct pxaohci_platform_data em_x270_ohci_platform_data = {
         .port_mode      = PMM_PERPORT_MODE,
+        .flags          = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
         .init           = em_x270_ohci_init,
 };
 
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 001a252bd514..d28849b50a14 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -19,68 +19,13 @@
 
 #include <mach/mfp-pxa25x.h>
 #include <mach/hardware.h>
+#include <mach/eseries-gpio.h>
+#include <mach/udc.h>
 
 #include "generic.h"
 
-static unsigned long e740_pin_config[] __initdata = {
-        /* Chip selects */
-        GPIO15_nCS_1,   /* CS1 - Flash */
-        GPIO79_nCS_3,   /* CS3 - IMAGEON */
-        GPIO80_nCS_4,   /* CS4 - TMIO */
-
-        /* Clocks */
-        GPIO12_32KHz,
-
-        /* BTUART */
-        GPIO42_BTUART_RXD,
-        GPIO43_BTUART_TXD,
-        GPIO44_BTUART_CTS,
-        GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
-
-        /* PC Card */
-        GPIO8_GPIO,   /* CD0 */
-        GPIO44_GPIO,  /* CD1 */
-        GPIO11_GPIO,  /* IRQ0 */
-        GPIO6_GPIO,   /* IRQ1 */
-        GPIO27_GPIO,  /* RST0 */
-        GPIO24_GPIO,  /* RST1 */
-        GPIO20_GPIO,  /* PWR0 */
-        GPIO23_GPIO,  /* PWR1 */
-        GPIO48_nPOE,
-        GPIO49_nPWE,
-        GPIO50_nPIOR,
-        GPIO51_nPIOW,
-        GPIO52_nPCE_1,
-        GPIO53_nPCE_2,
-        GPIO54_nPSKTSEL,
-        GPIO55_nPREG,
-        GPIO56_nPWAIT,
-        GPIO57_nIOIS16,
-
-        /* wakeup */
-        GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
-};
-
-static unsigned long e400_pin_config[] __initdata = {
-        /* Chip selects */
-        GPIO15_nCS_1,   /* CS1 - Flash */
-        GPIO80_nCS_4,   /* CS4 - TMIO */
-
-        /* Clocks */
-        GPIO12_32KHz,
-
-        /* BTUART */
-        GPIO42_BTUART_RXD,
-        GPIO43_BTUART_TXD,
-        GPIO44_BTUART_CTS,
-        GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
-
-        /* wakeup */
-        GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
-};
-
 /* Only e800 has 128MB RAM */
-static void __init eseries_fixup(struct machine_desc *desc,
+void __init eseries_fixup(struct machine_desc *desc,
         struct tag *tags, char **cmdline, struct meminfo *mi)
 {
         mi->nr_banks=1;
@@ -92,95 +37,9 @@ static void __init eseries_fixup(struct machine_desc *desc,
                 mi->bank[0].size = (64*1024*1024);
 }
 
-static void __init e740_init(void)
-{
-        pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
-}
-
-static void __init e400_init(void)
-{
-        pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config));
-}
-
-/* e-series machine definitions */
-
-#ifdef CONFIG_MACH_E330
-MACHINE_START(E330, "Toshiba e330")
-        /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
-        .init_irq       = pxa25x_init_irq,
-        .fixup          = eseries_fixup,
-        .timer          = &pxa_timer,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E350
-MACHINE_START(E350, "Toshiba e350")
-        /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
-        .init_irq       = pxa25x_init_irq,
-        .fixup          = eseries_fixup,
-        .timer          = &pxa_timer,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E740
-MACHINE_START(E740, "Toshiba e740")
-        /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
-        .init_irq       = pxa25x_init_irq,
-        .fixup          = eseries_fixup,
-        .init_machine   = e740_init,
-        .timer          = &pxa_timer,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E750
-MACHINE_START(E750, "Toshiba e750")
-        /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
-        .init_irq       = pxa25x_init_irq,
-        .fixup          = eseries_fixup,
-        .timer          = &pxa_timer,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E400
-MACHINE_START(E400, "Toshiba e400")
-        /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
-        .init_irq       = pxa25x_init_irq,
-        .fixup          = eseries_fixup,
-        .init_machine   = e400_init,
-        .timer          = &pxa_timer,
-MACHINE_END
-#endif
-
-#ifdef CONFIG_MACH_E800
-MACHINE_START(E800, "Toshiba e800")
-        /* Maintainer: Ian Molton (spyro@f2s.com) */
-        .phys_io        = 0x40000000,
-        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-        .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
-        .init_irq       = pxa25x_init_irq,
-        .fixup          = eseries_fixup,
-        .timer          = &pxa_timer,
-MACHINE_END
-#endif
+struct pxa2xx_udc_mach_info e7xx_udc_mach_info = {
+        .gpio_vbus   = GPIO_E7XX_USB_DISC,
+        .gpio_pullup = GPIO_E7XX_USB_PULLUP,
+        .gpio_pullup_inverted = 1
+};
 
diff --git a/arch/arm/mach-pxa/eseries.h b/arch/arm/mach-pxa/eseries.h
new file mode 100644
index 000000000000..a83f88d4b6ad
--- /dev/null
+++ b/arch/arm/mach-pxa/eseries.h
@@ -0,0 +1,4 @@
+void __init eseries_fixup(struct machine_desc *desc,
+        struct tag *tags, char **cmdline, struct meminfo *mi);
+
+extern struct pxa2xx_udc_mach_info e7xx_udc_mach_info;
diff --git a/arch/arm/mach-pxa/eseries_udc.c b/arch/arm/mach-pxa/eseries_udc.c
deleted file mode 100644
index d622c04c0d44..000000000000
--- a/arch/arm/mach-pxa/eseries_udc.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * UDC functions for the Toshiba e-series PDAs
- *
- * Copyright (c) Ian Molton 2003
- *
- * This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <mach/udc.h>
-#include <mach/eseries-gpio.h>
-#include <mach/hardware.h>
-#include <mach/pxa-regs.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/domain.h>
-
-/* local PXA generic code */
-#include "generic.h"
-
-static struct pxa2xx_udc_mach_info e7xx_udc_mach_info = {
-        .gpio_vbus   = GPIO_E7XX_USB_DISC,
-        .gpio_pullup = GPIO_E7XX_USB_PULLUP,
-        .gpio_pullup_inverted = 1
-};
-
-static struct pxa2xx_udc_mach_info e800_udc_mach_info = {
-        .gpio_vbus   = GPIO_E800_USB_DISC,
-        .gpio_pullup = GPIO_E800_USB_PULLUP,
-        .gpio_pullup_inverted = 1
-};
-
-static int __init eseries_udc_init(void)
-{
-        if (machine_is_e330() || machine_is_e350() ||
-            machine_is_e740() || machine_is_e750() ||
-            machine_is_e400())
-                pxa_set_udc_info(&e7xx_udc_mach_info);
-        else if (machine_is_e800())
-                pxa_set_udc_info(&e800_udc_mach_info);
-
-        return 0;
-}
-
-module_init(eseries_udc_init);
-
-MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
-MODULE_DESCRIPTION("eseries UDC support");
-MODULE_LICENSE("GPLv2");
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index ceaed0076366..85ed0b33331f 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -46,7 +46,7 @@ void clear_reset_status(unsigned int mask)
  */
 unsigned int get_clk_frequency_khz(int info)
 {
-        if (cpu_is_pxa21x() || cpu_is_pxa25x())
+        if (cpu_is_pxa25x())
                 return pxa25x_get_clk_frequency_khz(info);
         else if (cpu_is_pxa27x())
                 return pxa27x_get_clk_frequency_khz(info);
@@ -60,7 +60,7 @@ EXPORT_SYMBOL(get_clk_frequency_khz);
  */
 unsigned int get_memclk_frequency_10khz(void)
 {
-        if (cpu_is_pxa21x() || cpu_is_pxa25x())
+        if (cpu_is_pxa25x())
                 return pxa25x_get_memclk_frequency_10khz();
         else if (cpu_is_pxa27x())
                 return pxa27x_get_memclk_frequency_10khz();
@@ -88,11 +88,6 @@ static struct map_desc standard_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(0x48000000),
                 .length         = 0x00200000,
                 .type           = MT_DEVICE
-        }, {    /* USB host */
-                .virtual        =  0xf8000000,
-                .pfn            = __phys_to_pfn(0x4c000000),
-                .length         = 0x00100000,
-                .type           = MT_DEVICE
         }, {    /* Camera */
                 .virtual        =  0xfa000000,
                 .pfn            = __phys_to_pfn(0x50000000),
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 041c048320e4..dc876a8e6668 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -65,4 +65,5 @@ static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
 
 extern struct sysdev_class pxa_irq_sysclass;
 extern struct sysdev_class pxa_gpio_sysclass;
+extern struct sysdev_class pxa2xx_mfp_sysclass;
 extern struct sysdev_class pxa3xx_mfp_sysclass;
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c
index 07acc1b23857..14930cf8be7b 100644
--- a/arch/arm/mach-pxa/gpio.c
+++ b/arch/arm/mach-pxa/gpio.c
@@ -16,10 +16,10 @@
 #include <linux/module.h>
 #include <linux/irq.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
 #include <asm/gpio.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <mach/pxa-regs.h>
 #include <mach/pxa2xx-gpio.h>
 
@@ -275,7 +275,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
                         loop = 1;
 
                         n = PXA_GPIO_IRQ_BASE + bit;
-                        desc_handle_irq(n, irq_desc + n);
+                        generic_handle_irq(n);
 
                         bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
                 }
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index c0092472fa58..d8962a0fb98d 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -20,8 +20,12 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
+#include <linux/delay.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/setup.h>
 #include <asm/memory.h>
@@ -40,7 +44,7 @@
 
 #include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa25x.h>
 
 #include "generic.h"
 
@@ -85,21 +89,8 @@ static struct platform_device *devices[] __initdata = {
 };
 
 #ifdef CONFIG_MMC_PXA
-static struct pxamci_platform_data gumstix_mci_platform_data;
-
-static int gumstix_mci_init(struct device *dev, irq_handler_t detect_int,
-                                void *data)
-{
-        pxa_gpio_mode(GPIO6_MMCCLK_MD);
-        pxa_gpio_mode(GPIO53_MMCCLK_MD);
-        pxa_gpio_mode(GPIO8_MMCCS0_MD);
-
-        return 0;
-}
-
 static struct pxamci_platform_data gumstix_mci_platform_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
-        .init           = gumstix_mci_init,
 };
 
 static void __init gumstix_mmc_init(void)
@@ -109,11 +100,11 @@ static void __init gumstix_mmc_init(void)
 #else
 static void __init gumstix_mmc_init(void)
 {
-        printk(KERN_INFO "Gumstix mmc disabled\n");
+        pr_debug("Gumstix mmc disabled\n");
 }
 #endif
 
-#ifdef CONFIG_USB_GADGET_PXA2XX
+#ifdef CONFIG_USB_GADGET_PXA25X
 static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = {
         .gpio_vbus              = GPIO_GUMSTIX_USB_GPIOn,
         .gpio_pullup            = GPIO_GUMSTIX_USB_GPIOx,
@@ -126,12 +117,87 @@ static void __init gumstix_udc_init(void)
 #else
 static void gumstix_udc_init(void)
 {
-        printk(KERN_INFO "Gumstix udc is disabled\n");
+        pr_debug("Gumstix udc is disabled\n");
 }
 #endif
 
+#ifdef CONFIG_BT
+/* Normally, the bootloader would have enabled this 32kHz clock but many
+** boards still have u-boot 1.1.4 so we check if it has been turned on and
+** if not, we turn it on with a warning message. */
+static void gumstix_setup_bt_clock(void)
+{
+        int timeout = 500;
+
+        if (!(OSCC & OSCC_OOK))
+                pr_warning("32kHz clock was not on. Bootloader may need to "
+                                "be updated\n");
+        else
+                return;
+
+        OSCC |= OSCC_OON;
+        do {
+                if (OSCC & OSCC_OOK)
+                        break;
+                udelay(1);
+        } while (--timeout);
+        if (!timeout)
+                pr_err("Failed to start 32kHz clock\n");
+}
+
+static void __init gumstix_bluetooth_init(void)
+{
+        int err;
+
+        gumstix_setup_bt_clock();
+
+        err = gpio_request(GPIO_GUMSTIX_BTRESET, "BTRST");
+        if (err) {
+                pr_err("gumstix: failed request gpio for bluetooth reset\n");
+                return;
+        }
+
+        err = gpio_direction_output(GPIO_GUMSTIX_BTRESET, 1);
+        if (err) {
+                pr_err("gumstix: can't reset bluetooth\n");
+                return;
+        }
+        gpio_set_value(GPIO_GUMSTIX_BTRESET, 0);
+        udelay(100);
+        gpio_set_value(GPIO_GUMSTIX_BTRESET, 1);
+}
+#else
+static void gumstix_bluetooth_init(void)
+{
+        pr_debug("Gumstix Bluetooth is disabled\n");
+}
+#endif
+
+static unsigned long gumstix_pin_config[] __initdata = {
+        GPIO12_32KHz,
+        /* BTUART */
+        GPIO42_HWUART_RXD,
+        GPIO43_HWUART_TXD,
+        GPIO44_HWUART_CTS,
+        GPIO45_HWUART_RTS,
+        /* MMC */
+        GPIO6_MMC_CLK,
+        GPIO53_MMC_CLK,
+        GPIO8_MMC_CS0,
+        /* these are used by AM200EPD */
+        GPIO51_GPIO,
+        GPIO49_GPIO,
+        GPIO48_GPIO,
+        GPIO32_GPIO,
+        GPIO17_GPIO,
+        GPIO16_GPIO,
+};
+
 static void __init gumstix_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config));
+
+        gumstix_bluetooth_init();
         gumstix_udc_init();
         gumstix_mmc_init();
         (void) platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 5aa0270d5605..013b15baa034 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -32,7 +32,7 @@
 #include <asm/mach/map.h>
 
 #include <mach/pxa-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa25x.h>
 #include <mach/idp.h>
 #include <mach/pxafb.h>
 #include <mach/bitfield.h>
@@ -46,6 +46,47 @@
  * - Ethernet interrupt
  */
 
+static unsigned long idp_pin_config[] __initdata = {
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+
+        /* STUART */
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+
+        /* MMC */
+        GPIO6_MMC_CLK,
+        GPIO8_MMC_CS0,
+
+        /* Ethernet */
+        GPIO33_nCS_5,   /* Ethernet CS */
+        GPIO4_GPIO,     /* Ethernet IRQ */
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .start  = (IDP_ETH_PHYS + 0x300),
@@ -121,44 +162,28 @@ static struct pxafb_mach_info sharp_lm8v31 = {
         .num_modes      = 1,
         .cmap_inverse   = 0,
         .cmap_static    = 0,
-        .lccr0          = LCCR0_SDS,
-        .lccr3          = LCCR3_PCP | LCCR3_Acb(255),
+        .lcd_conn       = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL |
+                          LCD_AC_BIAS_FREQ(255),
         .pxafb_backlight_power = &idp_backlight_power,
         .pxafb_lcd_power = &idp_lcd_power
 };
 
-static int idp_mci_init(struct device *dev, irq_handler_t idp_detect_int, void *data)
-{
-        /* setup GPIO for PXA25x MMC controller */
-        pxa_gpio_mode(GPIO6_MMCCLK_MD);
-        pxa_gpio_mode(GPIO8_MMCCS0_MD);
-
-        return 0;
-}
-
 static struct pxamci_platform_data idp_mci_platform_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
-        .init           = idp_mci_init,
 };
 
 static void __init idp_init(void)
 {
         printk("idp_init()\n");
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(idp_pin_config));
+
         platform_device_register(&smc91x_device);
         //platform_device_register(&mst_audio_device);
         set_pxa_fb_info(&sharp_lm8v31);
         pxa_set_mci_info(&idp_mci_platform_data);
 }
 
-static void __init idp_init_irq(void)
-{
-
-        pxa25x_init_irq();
-
-        set_irq_type(TOUCH_PANEL_IRQ, TOUCH_PANEL_IRQ_EDGE);
-}
-
 static struct map_desc idp_io_desc[] __initdata = {
         {
                 .virtual        =  IDP_COREVOLT_VIRT,
@@ -177,15 +202,6 @@ static void __init idp_map_io(void)
 {
         pxa_map_io();
         iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
-
-        // serial ports 2 & 3
-        pxa_gpio_mode(GPIO42_BTRXD_MD);
-        pxa_gpio_mode(GPIO43_BTTXD_MD);
-        pxa_gpio_mode(GPIO44_BTCTS_MD);
-        pxa_gpio_mode(GPIO45_BTRTS_MD);
-        pxa_gpio_mode(GPIO46_STRXD_MD);
-        pxa_gpio_mode(GPIO47_STTXD_MD);
-
 }
 
 
@@ -194,7 +210,7 @@ MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
         .phys_io        = 0x40000000,
         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
         .map_io         = idp_map_io,
-        .init_irq       = idp_init_irq,
+        .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = idp_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/include/mach/akita.h b/arch/arm/mach-pxa/include/mach/akita.h
deleted file mode 100644
index 5d8cc1d9cb10..000000000000
--- a/arch/arm/mach-pxa/include/mach/akita.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Hardware specific definitions for SL-C1000 (Akita)
- *
- * Copyright (c) 2005 Richard Purdie
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-/* Akita IO Expander GPIOs */
-
-#define AKITA_IOEXP_RESERVED_7      (1 << 7)
-#define AKITA_IOEXP_IR_ON           (1 << 6)
-#define AKITA_IOEXP_AKIN_PULLUP     (1 << 5)
-#define AKITA_IOEXP_BACKLIGHT_CONT  (1 << 4)
-#define AKITA_IOEXP_BACKLIGHT_ON    (1 << 3)
-#define AKITA_IOEXP_MIC_BIAS        (1 << 2)
-#define AKITA_IOEXP_RESERVED_1      (1 << 1)
-#define AKITA_IOEXP_RESERVED_0      (1 << 0)
-
-/* Direction Bitfield  0=output  1=input */
-#define AKITA_IOEXP_IO_DIR      0
-/* Default Values */
-#define AKITA_IOEXP_IO_OUT      (AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP)
-
-extern struct platform_device akitaioexp_device;
-
-void akita_set_ioexp(struct device *dev, unsigned char bitmask);
-void akita_reset_ioexp(struct device *dev, unsigned char bitmask);
-
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index bf856503baf6..585970ef08ce 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -98,12 +98,21 @@
                         CORGI_SCP_MIC_BIAS )
 #define CORGI_SCOOP_IO_OUT      ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
 
+#define CORGI_SCOOP_GPIO_BASE           (NR_BUILTIN_GPIO)
+#define CORGI_GPIO_LED_GREEN            (CORGI_SCOOP_GPIO_BASE + 0)
+#define CORGI_GPIO_SWA                  (CORGI_SCOOP_GPIO_BASE + 1)  /* Hinge Switch A */
+#define CORGI_GPIO_SWB                  (CORGI_SCOOP_GPIO_BASE + 2)  /* Hinge Switch B */
+#define CORGI_GPIO_MUTE_L               (CORGI_SCOOP_GPIO_BASE + 3)
+#define CORGI_GPIO_MUTE_R               (CORGI_SCOOP_GPIO_BASE + 4)
+#define CORGI_GPIO_AKIN_PULLUP          (CORGI_SCOOP_GPIO_BASE + 5)
+#define CORGI_GPIO_APM_ON               (CORGI_SCOOP_GPIO_BASE + 6)
+#define CORGI_GPIO_BACKLIGHT_CONT       (CORGI_SCOOP_GPIO_BASE + 7)
+#define CORGI_GPIO_MIC_BIAS             (CORGI_SCOOP_GPIO_BASE + 8)
 
 /*
  * Shared data structures
  */
 extern struct platform_device corgiscoop_device;
-extern struct platform_device corgissp_device;
 
 #endif /* __ASM_ARCH_CORGI_H  */
 
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
index de16c12d5232..f6b4bf3e73d2 100644
--- a/arch/arm/mach-pxa/include/mach/entry-macro.S
+++ b/arch/arm/mach-pxa/include/mach/entry-macro.S
@@ -41,7 +41,7 @@
                 and     \irqstat, \irqstat, \irqnr
                 clz     \irqnr, \irqstat
                 rsb     \irqnr, \irqnr, #31
-                add     \irqnr, \irqnr, #32
+                add     \irqnr, \irqnr, #(32 + PXA_IRQ(0))
                 b       1001f
 1003:
                 mrc     p6, 0, \irqstat, c0, c0, 0      @ ICIP
@@ -52,6 +52,6 @@
                 rsb     \irqstat, \irqnr, #0
                 and     \irqstat, \irqstat, \irqnr
                 clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #31
+                rsb     \irqnr, \irqnr, #(31 + PXA_IRQ(0))
 1001:
                 .endm
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index e89df4d0d239..a582a6d9b92b 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -62,26 +62,74 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/cputype.h>
+
+/*
+ *   CPU     Stepping     CPU_ID         JTAG_ID
+ *
+ *  PXA210      B0      0x69052922      0x2926C013
+ *  PXA210      B1      0x69052923      0x3926C013
+ *  PXA210      B2      0x69052924      0x4926C013
+ *  PXA210      C0      0x69052D25      0x5926C013
+ *
+ *  PXA250      A0      0x69052100      0x09264013
+ *  PXA250      A1      0x69052101      0x19264013
+ *  PXA250      B0      0x69052902      0x29264013
+ *  PXA250      B1      0x69052903      0x39264013
+ *  PXA250      B2      0x69052904      0x49264013
+ *  PXA250      C0      0x69052D05      0x59264013
+ *
+ *  PXA255      A0      0x69052D06      0x69264013
+ *
+ *  PXA26x      A0      0x69052903      0x39264013
+ *  PXA26x      B0      0x69052D05      0x59264013
+ *
+ *  PXA27x      A0      0x69054110      0x09265013
+ *  PXA27x      A1      0x69054111      0x19265013
+ *  PXA27x      B0      0x69054112      0x29265013
+ *  PXA27x      B1      0x69054113      0x39265013
+ *  PXA27x      C0      0x69054114      0x49265013
+ *  PXA27x      C5      0x69054117      0x79265013
+ *
+ *  PXA30x      A0      0x69056880      0x0E648013
+ *  PXA30x      A1      0x69056881      0x1E648013
+ *  PXA31x      A0      0x69056890      0x0E649013
+ *  PXA31x      A1      0x69056891      0x1E649013
+ *  PXA31x      A2      0x69056892      0x2E649013
+ *  PXA32x      B1      0x69056825      0x5E642013
+ *  PXA32x      B2      0x69056826      0x6E642013
+ *
+ *  PXA930      B0      0x69056835      0x5E643013
+ *  PXA930      B1      0x69056837      0x7E643013
+ *  PXA930      B2      0x69056838      0x8E643013
+ */
 #ifdef CONFIG_PXA25x
-#define __cpu_is_pxa21x(id)                             \
+#define __cpu_is_pxa210(id)                             \
         ({                                              \
-                unsigned int _id = (id) >> 4 & 0xf3f;   \
-                _id == 0x212;                           \
+                unsigned int _id = (id) & 0xf3f0;       \
+                _id == 0x2120;                          \
         })
 
-#define __cpu_is_pxa255(id)                             \
-        ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x2d0;                           \
-         })
+#define __cpu_is_pxa250(id)                             \
+        ({                                              \
+                unsigned int _id = (id) & 0xf3ff;       \
+                _id <= 0x2105;                          \
+        })
+
+#define __cpu_is_pxa255(id)                             \
+        ({                                              \
+                unsigned int _id = (id) & 0xffff;       \
+                _id == 0x2d06;                          \
+        })
 
 #define __cpu_is_pxa25x(id)                             \
         ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x2d0 || _id == 0x290;           \
+                unsigned int _id = (id) & 0xf300;       \
+                _id == 0x2100;                          \
         })
 #else
-#define __cpu_is_pxa21x(id)     (0)
+#define __cpu_is_pxa210(id)     (0)
+#define __cpu_is_pxa250(id)     (0)
 #define __cpu_is_pxa255(id)     (0)
 #define __cpu_is_pxa25x(id)     (0)
 #endif
@@ -136,9 +184,14 @@
 #define __cpu_is_pxa930(id)     (0)
 #endif
 
-#define cpu_is_pxa21x()                                 \
+#define cpu_is_pxa210()                                 \
         ({                                              \
-                __cpu_is_pxa21x(read_cpuid_id());       \
+                __cpu_is_pxa210(read_cpuid_id());       \
+        })
+
+#define cpu_is_pxa250()                                 \
+        ({                                              \
+                __cpu_is_pxa250(read_cpuid_id());       \
         })
 
 #define cpu_is_pxa255()                                 \
@@ -151,6 +204,8 @@
                 __cpu_is_pxa25x(read_cpuid_id());       \
         })
 
+extern int cpu_is_pxa26x(void);
+
 #define cpu_is_pxa27x()                                 \
         ({                                              \
                 __cpu_is_pxa27x(read_cpuid_id());       \
diff --git a/arch/arm/mach-pxa/include/mach/i2c.h b/arch/arm/mach-pxa/include/mach/i2c.h
index 80596b013443..1a9f65e6ec0f 100644
--- a/arch/arm/mach-pxa/include/mach/i2c.h
+++ b/arch/arm/mach-pxa/include/mach/i2c.h
@@ -65,13 +65,18 @@ struct i2c_pxa_platform_data {
         unsigned int            slave_addr;
         struct i2c_slave_client *slave;
         unsigned int            class;
-        int                     use_pio;
+        unsigned int            use_pio :1;
+        unsigned int            fast_mode :1;
 };
 
 extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
 
 #ifdef CONFIG_PXA27x
-extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info);
+extern void pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info);
+#endif
+
+#ifdef CONFIG_PXA3xx
+extern void pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info);
 #endif
 
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 108b5db9b2af..9c163e19ada9 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -11,7 +11,14 @@
  */
 
 
-#define PXA_IRQ(x)      (x)
+#ifdef CONFIG_PXA_HAVE_ISA_IRQS
+#define PXA_ISA_IRQ(x)  (x)
+#define PXA_ISA_IRQ_NUM (16)
+#else
+#define PXA_ISA_IRQ_NUM (0)
+#endif
+
+#define PXA_IRQ(x)      (PXA_ISA_IRQ_NUM + (x))
 
 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define IRQ_SSP3        PXA_IRQ(0)      /* SSP3 service request */
@@ -73,7 +80,7 @@
 #define IRQ_MMC3        PXA_IRQ(55)     /* MMC3 Controller (PXA310) */
 #endif
 
-#define PXA_GPIO_IRQ_BASE       (64)
+#define PXA_GPIO_IRQ_BASE       PXA_IRQ(64)
 #define PXA_GPIO_IRQ_NUM        (128)
 
 #define GPIO_2_x_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
@@ -178,13 +185,7 @@
 #define NR_IRQS                 (IRQ_S1_BVD1_STSCHG + 1)
 #elif defined(CONFIG_SHARP_LOCOMO)
 #define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
-#elif defined(CONFIG_ARCH_LUBBOCK) || \
-      defined(CONFIG_MACH_LOGICPD_PXA270) || \
-      defined(CONFIG_MACH_TOSA) || \
-      defined(CONFIG_MACH_MAINSTONE) || \
-      defined(CONFIG_MACH_PCM027) || \
-      defined(CONFIG_ARCH_PXA_ESERIES) || \
-      defined(CONFIG_MACH_MAGICIAN)
+#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
 #define NR_IRQS                 (IRQ_BOARD_END)
 #elif defined(CONFIG_MACH_ZYLONITE)
 #define NR_IRQS                 (IRQ_BOARD_START + 32)
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 79d209b826f4..5c4e320c1437 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -3,4 +3,6 @@
 
 #define LITTLETON_ETH_PHYS      0x30000000
 
+#define LITTLETON_GPIO_LCD_CS   (17)
+
 #endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 552eb7fa6579..59aef89808d6 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -40,11 +40,11 @@
 #define NODE_MEM_SIZE_BITS      26
 
 #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-void cmx270_pci_adjust_zones(int node, unsigned long *size,
+void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
                              unsigned long *holes);
 
 #define arch_adjust_zones(node, size, holes) \
-        cmx270_pci_adjust_zones(node, size, holes)
+        cmx2xx_pci_adjust_zones(node, size, holes)
 
 #define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_64M - 1)
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index 6c8e72238bfd..617cab2cc8d0 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -17,7 +17,7 @@
 
 /* Crystal and Clock Signals */
 #define GPIO10_RTCCLK           MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
-#define GPIO70_RTC_CLK          MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
+#define GPIO70_RTCCLK           MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
 #define GPIO7_48MHz             MFP_CFG_OUT(GPIO7,  AF1, DRIVE_LOW)
 #define GPIO11_3_6MHz           MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
 #define GPIO71_3_6MHz           MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
@@ -156,6 +156,6 @@
 #define GPIO74_LCD_FCLK         MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
 #define GPIO75_LCD_LCLK         MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
 #define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
-#define GPIO77_LCD_ACBIAS       MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+#define GPIO77_LCD_BIAS         MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
 
 #endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
index 74990510cf34..67f8385ea548 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
@@ -257,10 +257,10 @@
 #define GPIO38_SSP2_RXD         MFP_CFG(GPIO38, AF2)
 #define GPIO38_SSP2_TXD         MFP_CFG(GPIO38, AF5)
 
-#define GPIO69_SSP3_SCLK        MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
-#define GPIO70_SSP3_FRM         MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
-#define GPIO89_SSP3_SCLK        MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
-#define GPIO90_SSP3_FRM         MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
+#define GPIO69_SSP3_SCLK        MFP_CFG_X(GPIO69, AF2, DS08X, FLOAT)
+#define GPIO70_SSP3_FRM         MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
+#define GPIO89_SSP3_SCLK        MFP_CFG_X(GPIO89, AF1, DS08X, FLOAT)
+#define GPIO90_SSP3_FRM         MFP_CFG_X(GPIO90, AF1, DS08X, DRIVE_LOW)
 #define GPIO71_SSP3_RXD         MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
 #define GPIO71_SSP3_TXD         MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
 #define GPIO72_SSP3_RXD         MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h
index 8769567b389b..482185053a92 100644
--- a/arch/arm/mach-pxa/include/mach/mfp.h
+++ b/arch/arm/mach-pxa/include/mach/mfp.h
@@ -274,12 +274,13 @@ typedef unsigned long mfp_cfg_t;
 #define MFP_DS_MASK             (0x7 << 13)
 #define MFP_DS(x)               (((x) >> 13) & 0x7)
 
-#define MFP_LPM_INPUT           (0x0 << 16)
+#define MFP_LPM_DEFAULT         (0x0 << 16)
 #define MFP_LPM_DRIVE_LOW       (0x1 << 16)
 #define MFP_LPM_DRIVE_HIGH      (0x2 << 16)
 #define MFP_LPM_PULL_LOW        (0x3 << 16)
 #define MFP_LPM_PULL_HIGH       (0x4 << 16)
 #define MFP_LPM_FLOAT           (0x5 << 16)
+#define MFP_LPM_INPUT           (0x6 << 16)
 #define MFP_LPM_STATE_MASK      (0x7 << 16)
 #define MFP_LPM_STATE(x)        (((x) >> 16) & 0x7)
 
@@ -297,7 +298,7 @@ typedef unsigned long mfp_cfg_t;
 #define MFP_PULL_MASK           (0x3 << 21)
 #define MFP_PULL(x)             (((x) >> 21) & 0x3)
 
-#define MFP_CFG_DEFAULT         (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
+#define MFP_CFG_DEFAULT         (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
                                  MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
 
 #define MFP_CFG(pin, af)                \
diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h
new file mode 100644
index 000000000000..8483cb511831
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mioa701.h
@@ -0,0 +1,67 @@
+#ifndef _MIOA701_H_
+#define _MIOA701_H_
+
+#define MIO_CFG_IN(pin, af)             \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
+         (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN))
+
+#define MIO_CFG_OUT(pin, af, state)     \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
+
+/* Global GPIOs */
+#define GPIO9_CHARGE_nEN                        9
+#define GPIO18_POWEROFF                         18
+#define GPIO87_LCD_POWER                        87
+
+/* USB */
+#define GPIO13_USB_DETECT                       13
+#define GPIO22_USB_ENABLE                       22
+
+/* SDIO bits */
+#define GPIO78_SDIO_RO                          78
+#define GPIO15_SDIO_INSERT                      15
+#define GPIO91_SDIO_EN                          91
+
+/* Bluetooth */
+#define GPIO83_BT_ON                            83
+
+/* GPS */
+#define GPIO23_GPS_UNKNOWN1                     23
+#define GPIO26_GPS_ON                           26
+#define GPIO27_GPS_RESET                        27
+#define GPIO106_GPS_UNKNOWN2                    106
+#define GPIO107_GPS_UNKNOWN3                    107
+
+/* GSM */
+#define GPIO24_GSM_MOD_RESET_CMD                24
+#define GPIO88_GSM_nMOD_ON_CMD                  88
+#define GPIO90_GSM_nMOD_OFF_CMD                 90
+#define GPIO114_GSM_nMOD_DTE_UART_STATE         114
+#define GPIO25_GSM_MOD_ON_STATE                 25
+#define GPIO113_GSM_EVENT                       113
+
+/* SOUND */
+#define GPIO12_HPJACK_INSERT                    12
+
+/* LEDS */
+#define GPIO10_LED_nCharging                    10
+#define GPIO97_LED_nBlue                        97
+#define GPIO98_LED_nOrange                      98
+#define GPIO82_LED_nVibra                       82
+#define GPIO115_LED_nKeyboard                   115
+
+/* Keyboard */
+#define GPIO0_KEY_POWER                         0
+#define GPIO93_KEY_VOLUME_UP                    93
+#define GPIO94_KEY_VOLUME_DOWN                  94
+
+extern struct input_dev *mioa701_evdev;
+extern void mioa701_gpio_lpm_set(unsigned long mfp_pin);
+
+/* Assembler externals mioa701_bootresume.S */
+extern u32 mioa701_bootstrap;
+extern u32 mioa701_jumpaddr;
+extern u32 mioa701_bootstrap_lg;
+
+#endif /* _MIOA701_H */
diff --git a/arch/arm/mach-pxa/include/mach/ohci.h b/arch/arm/mach-pxa/include/mach/ohci.h
index e848a47128cd..95b6e2a6e514 100644
--- a/arch/arm/mach-pxa/include/mach/ohci.h
+++ b/arch/arm/mach-pxa/include/mach/ohci.h
@@ -7,6 +7,22 @@ struct pxaohci_platform_data {
         int (*init)(struct device *);
         void (*exit)(struct device *);
 
+        unsigned long flags;
+#define ENABLE_PORT1            (1 << 0)
+#define ENABLE_PORT2            (1 << 1)
+#define ENABLE_PORT3            (1 << 2)
+#define ENABLE_PORT_ALL         (ENABLE_PORT1 | ENABLE_PORT2 | ENABLE_PORT3)
+
+#define POWER_SENSE_LOW         (1 << 3)
+#define POWER_CONTROL_LOW       (1 << 4)
+#define NO_OC_PROTECTION        (1 << 5)
+#define OC_MODE_GLOBAL          (0 << 6)
+#define OC_MODE_PERPORT         (1 << 6)
+
+        int power_on_delay;     /* Power On to Power Good time - in ms
+                                 * HCD must wait for this duration before
+                                 * accessing a powered on port
+                                 */
         int port_mode;
 #define PMM_NPS_MODE           1
 #define PMM_GLOBAL_MODE        2
diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h
new file mode 100644
index 000000000000..5032307ebf7d
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmz72.h
@@ -0,0 +1,80 @@
+/*
+ * GPIOs and interrupts for Palm Zire72 Handheld Computer
+ *
+ * Authors:     Alex Osborne <bobofdoom@gmail.com>
+ *              Jan Herman <2hp@seznam.cz>
+ *              Sergey Lapin <slapin@ossfans.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _INCLUDE_PALMZ72_H_
+#define _INCLUDE_PALMZ72_H_
+
+/* Power and control */
+#define GPIO_NR_PALMZ72_GPIO_RESET              1
+#define GPIO_NR_PALMZ72_POWER_DETECT            0
+
+/* SD/MMC */
+#define GPIO_NR_PALMZ72_SD_DETECT_N             14
+#define GPIO_NR_PALMZ72_SD_POWER_N              98
+#define GPIO_NR_PALMZ72_SD_RO 115
+
+/* Touchscreen */
+#define GPIO_NR_PALMZ72_WM9712_IRQ              27
+
+/* IRDA -  disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
+#define GPIO_NR_PALMZ72_IR_DISABLE              49
+
+/* USB */
+#define GPIO_NR_PALMZ72_USB_DETECT_N            15
+#define GPIO_NR_PALMZ72_USB_POWER               95
+#define GPIO_NR_PALMZ72_USB_PULLUP              12
+
+/* LCD/Backlight */
+#define GPIO_NR_PALMZ72_BL_POWER                20
+#define GPIO_NR_PALMZ72_LCD_POWER               96
+
+/* LED */
+#define GPIO_NR_PALMZ72_LED_GREEN               88
+
+/* Bluetooth */
+#define GPIO_NR_PALMZ72_BT_POWER                17
+#define GPIO_NR_PALMZ72_BT_RESET                83
+
+/** Initial values **/
+
+/* Battery */
+#define PALMZ72_BAT_MAX_VOLTAGE         4000    /* 4.00v current voltage */
+#define PALMZ72_BAT_MIN_VOLTAGE         3550    /* 3.55v critical voltage */
+#define PALMZ72_BAT_MAX_CURRENT         0       /* unknokn */
+#define PALMZ72_BAT_MIN_CURRENT         0       /* unknown */
+#define PALMZ72_BAT_MAX_CHARGE          1       /* unknown */
+#define PALMZ72_BAT_MIN_CHARGE          1       /* unknown */
+#define PALMZ72_MAX_LIFE_MINS           360     /* on-life in minutes */
+
+/* Backlight */
+#define PALMZ72_MAX_INTENSITY           0xFE
+#define PALMZ72_DEFAULT_INTENSITY       0x7E
+#define PALMZ72_LIMIT_MASK              0x7F
+#define PALMZ72_PRESCALER               0x3F
+#define PALMZ72_PERIOD_NS               3500
+
+#ifdef CONFIG_PM
+struct palmz72_resume_info {
+        u32 magic0;             /* 0x0 */
+        u32 magic1;             /* 0x4 */
+        u32 resume_addr;        /* 0x8 */
+        u32 pad[11];            /* 0xc..0x37 */
+        u32 arm_control;        /* 0x38 */
+        u32 aux_control;        /* 0x3c */
+        u32 ttb;                /* 0x40 */
+        u32 domain_access;      /* 0x44 */
+        u32 process_id;         /* 0x48 */
+};
+#endif
+#endif
+
diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h
index 261e5bc958db..83342469acac 100644
--- a/arch/arm/mach-pxa/include/mach/pm.h
+++ b/arch/arm/mach-pxa/include/mach/pm.h
@@ -15,6 +15,8 @@ struct pxa_cpu_pm_fns {
         void    (*restore)(unsigned long *);
         int     (*valid)(suspend_state_t state);
         void    (*enter)(suspend_state_t state);
+        int     (*prepare)(void);
+        void    (*finish)(void);
 };
 
 extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index 67debc47e8c6..0b3e6d051c64 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -23,6 +23,7 @@
 #define POODLE_GPIO_AC_IN               (1)
 #define POODLE_GPIO_CO                  16
 #define POODLE_GPIO_TP_INT              (5)
+#define POODLE_GPIO_TP_CS               (24)
 #define POODLE_GPIO_WAKEUP              (11)    /* change battery */
 #define POODLE_GPIO_GA_INT              (10)
 #define POODLE_GPIO_IR_ON               (22)
@@ -70,6 +71,14 @@
 #define POODLE_SCOOP_IO_DIR     ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
 #define POODLE_SCOOP_IO_OUT     ( 0 )
 
+#define POODLE_SCOOP_GPIO_BASE  (NR_BUILTIN_GPIO)
+#define POODLE_GPIO_CHARGE_ON   (POODLE_SCOOP_GPIO_BASE + 0)
+#define POODLE_GPIO_CP401       (POODLE_SCOOP_GPIO_BASE + 2)
+#define POODLE_GPIO_VPEN        (POODLE_SCOOP_GPIO_BASE + 7)
+#define POODLE_GPIO_L_PCLK      (POODLE_SCOOP_GPIO_BASE + 9)
+#define POODLE_GPIO_L_LCLK      (POODLE_SCOOP_GPIO_BASE + 10)
+#define POODLE_GPIO_HS_OUT      (POODLE_SCOOP_GPIO_BASE + 11)
+
 #define POODLE_LOCOMO_GPIO_AMP_ON      LOCOMO_GPIO(8)
 #define POODLE_LOCOMO_GPIO_MUTE_L      LOCOMO_GPIO(10)
 #define POODLE_LOCOMO_GPIO_MUTE_R      LOCOMO_GPIO(11)
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index 12288ca3cbb2..15295d960000 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -69,30 +69,18 @@
 /*
  * DMA Controller
  */
-
-#define DCSR0           __REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
-#define DCSR1           __REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
-#define DCSR2           __REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
-#define DCSR3           __REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
-#define DCSR4           __REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */
-#define DCSR5           __REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */
-#define DCSR6           __REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */
-#define DCSR7           __REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
-#define DCSR8           __REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */
-#define DCSR9           __REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */
-#define DCSR10          __REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */
-#define DCSR11          __REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
-#define DCSR12          __REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */
-#define DCSR13          __REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
-#define DCSR14          __REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
-#define DCSR15          __REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
-
 #define DCSR(x)         __REG2(0x40000000, (x) << 2)
 
 #define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
 #define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
 #define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
-#ifdef CONFIG_PXA27x
+#define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
+#define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
+#define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
+#define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
+#define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
 #define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
 #define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
@@ -101,11 +89,6 @@
 #define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
 #define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
 #endif
-#define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
-#define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
-#define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
-#define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
-#define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
 
 #define DALGN           __REG(0x400000a0)  /* DMA Alignment Register */
 #define DINT            __REG(0x400000f0)  /* DMA Interrupt Register */
@@ -114,145 +97,9 @@
                         &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
                         &__REG2(0x40001100, ((n) & 0x3f) << 2)))
 
-#define DRCMR0          __REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
-#define DRCMR1          __REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
-#define DRCMR2          __REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
-#define DRCMR3          __REG(0x4000010c)  /* Request to Channel Map Register for I2S transmit Request */
-#define DRCMR4          __REG(0x40000110)  /* Request to Channel Map Register for BTUART receive Request */
-#define DRCMR5          __REG(0x40000114)  /* Request to Channel Map Register for BTUART transmit Request. */
-#define DRCMR6          __REG(0x40000118)  /* Request to Channel Map Register for FFUART receive Request */
-#define DRCMR7          __REG(0x4000011c)  /* Request to Channel Map Register for FFUART transmit Request */
-#define DRCMR8          __REG(0x40000120)  /* Request to Channel Map Register for AC97 microphone Request */
-#define DRCMR9          __REG(0x40000124)  /* Request to Channel Map Register for AC97 modem receive Request */
-#define DRCMR10         __REG(0x40000128)  /* Request to Channel Map Register for AC97 modem transmit Request */
-#define DRCMR11         __REG(0x4000012c)  /* Request to Channel Map Register for AC97 audio receive Request */
-#define DRCMR12         __REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */
-#define DRCMR13         __REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */
-#define DRCMR14         __REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */
-#define DRCMR15         __REG(0x4000013c)  /* Request to Channel Map Register for SSP2 receive Request */
-#define DRCMR16         __REG(0x40000140)  /* Request to Channel Map Register for SSP2 transmit Request */
-#define DRCMR17         __REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */
-#define DRCMR18         __REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */
-#define DRCMR19         __REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */
-#define DRCMR20         __REG(0x40000150)  /* Request to Channel Map Register for STUART transmit Request */
-#define DRCMR21         __REG(0x40000154)  /* Request to Channel Map Register for MMC receive Request */
-#define DRCMR22         __REG(0x40000158)  /* Request to Channel Map Register for MMC transmit Request */
-#define DRCMR23         __REG(0x4000015c)  /* Reserved */
-#define DRCMR24         __REG(0x40000160)  /* Reserved */
-#define DRCMR25         __REG(0x40000164)  /* Request to Channel Map Register for USB endpoint 1 Request */
-#define DRCMR26         __REG(0x40000168)  /* Request to Channel Map Register for USB endpoint 2 Request */
-#define DRCMR27         __REG(0x4000016C)  /* Request to Channel Map Register for USB endpoint 3 Request */
-#define DRCMR28         __REG(0x40000170)  /* Request to Channel Map Register for USB endpoint 4 Request */
-#define DRCMR29         __REG(0x40000174)  /* Reserved */
-#define DRCMR30         __REG(0x40000178)  /* Request to Channel Map Register for USB endpoint 6 Request */
-#define DRCMR31         __REG(0x4000017C)  /* Request to Channel Map Register for USB endpoint 7 Request */
-#define DRCMR32         __REG(0x40000180)  /* Request to Channel Map Register for USB endpoint 8 Request */
-#define DRCMR33         __REG(0x40000184)  /* Request to Channel Map Register for USB endpoint 9 Request */
-#define DRCMR34         __REG(0x40000188)  /* Reserved */
-#define DRCMR35         __REG(0x4000018C)  /* Request to Channel Map Register for USB endpoint 11 Request */
-#define DRCMR36         __REG(0x40000190)  /* Request to Channel Map Register for USB endpoint 12 Request */
-#define DRCMR37         __REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */
-#define DRCMR38         __REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
-#define DRCMR39         __REG(0x4000019C)  /* Reserved */
-#define DRCMR66         __REG(0x40001108)  /* Request to Channel Map Register for SSP3 receive Request */
-#define DRCMR67         __REG(0x4000110C)  /* Request to Channel Map Register for SSP3 transmit Request */
-#define DRCMR68         __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
-#define DRCMR69         __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
-#define DRCMR70         __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
-
-#define DRCMRRXSADR     DRCMR2
-#define DRCMRTXSADR     DRCMR3
-#define DRCMRRXBTRBR    DRCMR4
-#define DRCMRTXBTTHR    DRCMR5
-#define DRCMRRXFFRBR    DRCMR6
-#define DRCMRTXFFTHR    DRCMR7
-#define DRCMRRXMCDR     DRCMR8
-#define DRCMRRXMODR     DRCMR9
-#define DRCMRTXMODR     DRCMR10
-#define DRCMRRXPCDR     DRCMR11
-#define DRCMRTXPCDR     DRCMR12
-#define DRCMRRXSSDR     DRCMR13
-#define DRCMRTXSSDR     DRCMR14
-#define DRCMRRXSS2DR   DRCMR15
-#define DRCMRTXSS2DR   DRCMR16
-#define DRCMRRXICDR     DRCMR17
-#define DRCMRTXICDR     DRCMR18
-#define DRCMRRXSTRBR    DRCMR19
-#define DRCMRTXSTTHR    DRCMR20
-#define DRCMRRXMMC      DRCMR21
-#define DRCMRTXMMC      DRCMR22
-#define DRCMRRXSS3DR   DRCMR66
-#define DRCMRTXSS3DR   DRCMR67
-#define DRCMRUDC(x)     DRCMR((x) + 24)
-
 #define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
 #define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
 
-#define DDADR0          __REG(0x40000200)  /* DMA Descriptor Address Register Channel 0 */
-#define DSADR0          __REG(0x40000204)  /* DMA Source Address Register Channel 0 */
-#define DTADR0          __REG(0x40000208)  /* DMA Target Address Register Channel 0 */
-#define DCMD0           __REG(0x4000020c)  /* DMA Command Address Register Channel 0 */
-#define DDADR1          __REG(0x40000210)  /* DMA Descriptor Address Register Channel 1 */
-#define DSADR1          __REG(0x40000214)  /* DMA Source Address Register Channel 1 */
-#define DTADR1          __REG(0x40000218)  /* DMA Target Address Register Channel 1 */
-#define DCMD1           __REG(0x4000021c)  /* DMA Command Address Register Channel 1 */
-#define DDADR2          __REG(0x40000220)  /* DMA Descriptor Address Register Channel 2 */
-#define DSADR2          __REG(0x40000224)  /* DMA Source Address Register Channel 2 */
-#define DTADR2          __REG(0x40000228)  /* DMA Target Address Register Channel 2 */
-#define DCMD2           __REG(0x4000022c)  /* DMA Command Address Register Channel 2 */
-#define DDADR3          __REG(0x40000230)  /* DMA Descriptor Address Register Channel 3 */
-#define DSADR3          __REG(0x40000234)  /* DMA Source Address Register Channel 3 */
-#define DTADR3          __REG(0x40000238)  /* DMA Target Address Register Channel 3 */
-#define DCMD3           __REG(0x4000023c)  /* DMA Command Address Register Channel 3 */
-#define DDADR4          __REG(0x40000240)  /* DMA Descriptor Address Register Channel 4 */
-#define DSADR4          __REG(0x40000244)  /* DMA Source Address Register Channel 4 */
-#define DTADR4          __REG(0x40000248)  /* DMA Target Address Register Channel 4 */
-#define DCMD4           __REG(0x4000024c)  /* DMA Command Address Register Channel 4 */
-#define DDADR5          __REG(0x40000250)  /* DMA Descriptor Address Register Channel 5 */
-#define DSADR5          __REG(0x40000254)  /* DMA Source Address Register Channel 5 */
-#define DTADR5          __REG(0x40000258)  /* DMA Target Address Register Channel 5 */
-#define DCMD5           __REG(0x4000025c)  /* DMA Command Address Register Channel 5 */
-#define DDADR6          __REG(0x40000260)  /* DMA Descriptor Address Register Channel 6 */
-#define DSADR6          __REG(0x40000264)  /* DMA Source Address Register Channel 6 */
-#define DTADR6          __REG(0x40000268)  /* DMA Target Address Register Channel 6 */
-#define DCMD6           __REG(0x4000026c)  /* DMA Command Address Register Channel 6 */
-#define DDADR7          __REG(0x40000270)  /* DMA Descriptor Address Register Channel 7 */
-#define DSADR7          __REG(0x40000274)  /* DMA Source Address Register Channel 7 */
-#define DTADR7          __REG(0x40000278)  /* DMA Target Address Register Channel 7 */
-#define DCMD7           __REG(0x4000027c)  /* DMA Command Address Register Channel 7 */
-#define DDADR8          __REG(0x40000280)  /* DMA Descriptor Address Register Channel 8 */
-#define DSADR8          __REG(0x40000284)  /* DMA Source Address Register Channel 8 */
-#define DTADR8          __REG(0x40000288)  /* DMA Target Address Register Channel 8 */
-#define DCMD8           __REG(0x4000028c)  /* DMA Command Address Register Channel 8 */
-#define DDADR9          __REG(0x40000290)  /* DMA Descriptor Address Register Channel 9 */
-#define DSADR9          __REG(0x40000294)  /* DMA Source Address Register Channel 9 */
-#define DTADR9          __REG(0x40000298)  /* DMA Target Address Register Channel 9 */
-#define DCMD9           __REG(0x4000029c)  /* DMA Command Address Register Channel 9 */
-#define DDADR10         __REG(0x400002a0)  /* DMA Descriptor Address Register Channel 10 */
-#define DSADR10         __REG(0x400002a4)  /* DMA Source Address Register Channel 10 */
-#define DTADR10         __REG(0x400002a8)  /* DMA Target Address Register Channel 10 */
-#define DCMD10          __REG(0x400002ac)  /* DMA Command Address Register Channel 10 */
-#define DDADR11         __REG(0x400002b0)  /* DMA Descriptor Address Register Channel 11 */
-#define DSADR11         __REG(0x400002b4)  /* DMA Source Address Register Channel 11 */
-#define DTADR11         __REG(0x400002b8)  /* DMA Target Address Register Channel 11 */
-#define DCMD11          __REG(0x400002bc)  /* DMA Command Address Register Channel 11 */
-#define DDADR12         __REG(0x400002c0)  /* DMA Descriptor Address Register Channel 12 */
-#define DSADR12         __REG(0x400002c4)  /* DMA Source Address Register Channel 12 */
-#define DTADR12         __REG(0x400002c8)  /* DMA Target Address Register Channel 12 */
-#define DCMD12          __REG(0x400002cc)  /* DMA Command Address Register Channel 12 */
-#define DDADR13         __REG(0x400002d0)  /* DMA Descriptor Address Register Channel 13 */
-#define DSADR13         __REG(0x400002d4)  /* DMA Source Address Register Channel 13 */
-#define DTADR13         __REG(0x400002d8)  /* DMA Target Address Register Channel 13 */
-#define DCMD13          __REG(0x400002dc)  /* DMA Command Address Register Channel 13 */
-#define DDADR14         __REG(0x400002e0)  /* DMA Descriptor Address Register Channel 14 */
-#define DSADR14         __REG(0x400002e4)  /* DMA Source Address Register Channel 14 */
-#define DTADR14         __REG(0x400002e8)  /* DMA Target Address Register Channel 14 */
-#define DCMD14          __REG(0x400002ec)  /* DMA Command Address Register Channel 14 */
-#define DDADR15         __REG(0x400002f0)  /* DMA Descriptor Address Register Channel 15 */
-#define DSADR15         __REG(0x400002f4)  /* DMA Source Address Register Channel 15 */
-#define DTADR15         __REG(0x400002f8)  /* DMA Target Address Register Channel 15 */
-#define DCMD15          __REG(0x400002fc)  /* DMA Command Address Register Channel 15 */
-
 #define DDADR(x)        __REG2(0x40000200, (x) << 4)
 #define DSADR(x)        __REG2(0x40000204, (x) << 4)
 #define DTADR(x)        __REG2(0x40000208, (x) << 4)
@@ -418,91 +265,13 @@
 
 
 /*
- * I2C registers
+ * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
  */
 
-#define IBMR            __REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */
-#define IDBR            __REG(0x40301688)  /* I2C Data Buffer Register - IDBR */
-#define ICR             __REG(0x40301690)  /* I2C Control Register - ICR */
-#define ISR             __REG(0x40301698)  /* I2C Status Register - ISR */
-#define ISAR            __REG(0x403016A0)  /* I2C Slave Address Register - ISAR */
-
-#define PWRIBMR    __REG(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */
-#define PWRIDBR    __REG(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */
-#define PWRICR __REG(0x40f00190)  /* Power I2C Control Register - ICR */
-#define PWRISR __REG(0x40f00198)  /* Power I2C Status Register - ISR */
-#define PWRISAR    __REG(0x40f001A0)  /*Power I2C Slave Address Register-ISAR */
-
-#define ICR_START       (1 << 0)           /* start bit */
-#define ICR_STOP        (1 << 1)           /* stop bit */
-#define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
-#define ICR_TB          (1 << 3)           /* transfer byte bit */
-#define ICR_MA          (1 << 4)           /* master abort */
-#define ICR_SCLE        (1 << 5)           /* master clock enable */
-#define ICR_IUE         (1 << 6)           /* unit enable */
-#define ICR_GCD         (1 << 7)           /* general call disable */
-#define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
-#define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
-#define ICR_BEIE        (1 << 10)          /* enable bus error ints */
-#define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
-#define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
-#define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
-#define ICR_UR          (1 << 14)          /* unit reset */
-
-#define ISR_RWM         (1 << 0)           /* read/write mode */
-#define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
-#define ISR_UB          (1 << 2)           /* unit busy */
-#define ISR_IBB         (1 << 3)           /* bus busy */
-#define ISR_SSD         (1 << 4)           /* slave stop detected */
-#define ISR_ALD         (1 << 5)           /* arbitration loss detected */
-#define ISR_ITE         (1 << 6)           /* tx buffer empty */
-#define ISR_IRF         (1 << 7)           /* rx buffer full */
-#define ISR_GCAD        (1 << 8)           /* general call address detected */
-#define ISR_SAD         (1 << 9)           /* slave address detected */
-#define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
-
-
 /*
- * Serial Audio Controller
+ * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
  */
 
-#define SACR0           __REG(0x40400000)  /* Global Control Register */
-#define SACR1           __REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
-#define SASR0           __REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
-#define SAIMR           __REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
-#define SAICR           __REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
-#define SADIV           __REG(0x40400060)  /* Audio Clock Divider Register. */
-#define SADR            __REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
-
-#define SACR0_RFTH(x)   ((x) << 12)     /* Rx FIFO Interrupt or DMA Trigger Threshold */
-#define SACR0_TFTH(x)   ((x) << 8)      /* Tx FIFO Interrupt or DMA Trigger Threshold */
-#define SACR0_STRF      (1 << 5)        /* FIFO Select for EFWR Special Function */
-#define SACR0_EFWR      (1 << 4)        /* Enable EFWR Function  */
-#define SACR0_RST       (1 << 3)        /* FIFO, i2s Register Reset */
-#define SACR0_BCKD      (1 << 2)        /* Bit Clock Direction */
-#define SACR0_ENB       (1 << 0)        /* Enable I2S Link */
-#define SACR1_ENLBF     (1 << 5)        /* Enable Loopback */
-#define SACR1_DRPL      (1 << 4)        /* Disable Replaying Function */
-#define SACR1_DREC      (1 << 3)        /* Disable Recording Function */
-#define SACR1_AMSL      (1 << 0)        /* Specify Alternate Mode */
-
-#define SASR0_I2SOFF    (1 << 7)        /* Controller Status */
-#define SASR0_ROR       (1 << 6)        /* Rx FIFO Overrun */
-#define SASR0_TUR       (1 << 5)        /* Tx FIFO Underrun */
-#define SASR0_RFS       (1 << 4)        /* Rx FIFO Service Request */
-#define SASR0_TFS       (1 << 3)        /* Tx FIFO Service Request */
-#define SASR0_BSY       (1 << 2)        /* I2S Busy */
-#define SASR0_RNE       (1 << 1)        /* Rx FIFO Not Empty */
-#define SASR0_TNF       (1 << 0)        /* Tx FIFO Not Empty */
-
-#define SAICR_ROR       (1 << 6)        /* Clear Rx FIFO Overrun Interrupt */
-#define SAICR_TUR       (1 << 5)        /* Clear Tx FIFO Underrun Interrupt */
-
-#define SAIMR_ROR       (1 << 6)        /* Enable Rx FIFO Overrun Condition Interrupt */
-#define SAIMR_TUR       (1 << 5)        /* Enable Tx FIFO Underrun Condition Interrupt */
-#define SAIMR_RFS       (1 << 4)        /* Enable Rx FIFO Service Interrupt */
-#define SAIMR_TFS       (1 << 3)        /* Enable Tx FIFO Service Interrupt */
-
 /*
  * AC97 Controller registers
  */
@@ -989,77 +758,6 @@
 
 #endif
 
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-/*
- * UHC: USB Host Controller (OHCI-like) register definitions
- */
-#define UHC_BASE_PHYS   (0x4C000000)
-#define UHCREV          __REG(0x4C000000) /* UHC HCI Spec Revision */
-#define UHCHCON         __REG(0x4C000004) /* UHC Host Control Register */
-#define UHCCOMS         __REG(0x4C000008) /* UHC Command Status Register */
-#define UHCINTS         __REG(0x4C00000C) /* UHC Interrupt Status Register */
-#define UHCINTE         __REG(0x4C000010) /* UHC Interrupt Enable */
-#define UHCINTD         __REG(0x4C000014) /* UHC Interrupt Disable */
-#define UHCHCCA         __REG(0x4C000018) /* UHC Host Controller Comm. Area */
-#define UHCPCED         __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
-#define UHCCHED         __REG(0x4C000020) /* UHC Control Head Endpt Descr */
-#define UHCCCED         __REG(0x4C000024) /* UHC Control Current Endpt Descr */
-#define UHCBHED         __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
-#define UHCBCED         __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
-#define UHCDHEAD        __REG(0x4C000030) /* UHC Done Head */
-#define UHCFMI          __REG(0x4C000034) /* UHC Frame Interval */
-#define UHCFMR          __REG(0x4C000038) /* UHC Frame Remaining */
-#define UHCFMN          __REG(0x4C00003C) /* UHC Frame Number */
-#define UHCPERS         __REG(0x4C000040) /* UHC Periodic Start */
-#define UHCLS           __REG(0x4C000044) /* UHC Low Speed Threshold */
-
-#define UHCRHDA         __REG(0x4C000048) /* UHC Root Hub Descriptor A */
-#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
-
-#define UHCRHDB         __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
-#define UHCRHS          __REG(0x4C000050) /* UHC Root Hub Status */
-#define UHCRHPS1        __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
-#define UHCRHPS2        __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
-#define UHCRHPS3        __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
-
-#define UHCSTAT         __REG(0x4C000060) /* UHC Status Register */
-#define UHCSTAT_UPS3    (1 << 16)       /* USB Power Sense Port3 */
-#define UHCSTAT_SBMAI   (1 << 15)       /* System Bus Master Abort Interrupt*/
-#define UHCSTAT_SBTAI   (1 << 14)       /* System Bus Target Abort Interrupt*/
-#define UHCSTAT_UPRI    (1 << 13)       /* USB Port Resume Interrupt */
-#define UHCSTAT_UPS2    (1 << 12)       /* USB Power Sense Port 2 */
-#define UHCSTAT_UPS1    (1 << 11)       /* USB Power Sense Port 1 */
-#define UHCSTAT_HTA     (1 << 10)       /* HCI Target Abort */
-#define UHCSTAT_HBA     (1 << 8)        /* HCI Buffer Active */
-#define UHCSTAT_RWUE    (1 << 7)        /* HCI Remote Wake Up Event */
-
-#define UHCHR           __REG(0x4C000064) /* UHC Reset Register */
-#define UHCHR_SSEP3     (1 << 11)       /* Sleep Standby Enable for Port3 */
-#define UHCHR_SSEP2     (1 << 10)       /* Sleep Standby Enable for Port2 */
-#define UHCHR_SSEP1     (1 << 9)        /* Sleep Standby Enable for Port1 */
-#define UHCHR_PCPL      (1 << 7)        /* Power control polarity low */
-#define UHCHR_PSPL      (1 << 6)        /* Power sense polarity low */
-#define UHCHR_SSE       (1 << 5)        /* Sleep Standby Enable */
-#define UHCHR_UIT       (1 << 4)        /* USB Interrupt Test */
-#define UHCHR_SSDC      (1 << 3)        /* Simulation Scale Down Clock */
-#define UHCHR_CGR       (1 << 2)        /* Clock Generation Reset */
-#define UHCHR_FHR       (1 << 1)        /* Force Host Controller Reset */
-#define UHCHR_FSBIR     (1 << 0)        /* Force System Bus Iface Reset */
-
-#define UHCHIE          __REG(0x4C000068) /* UHC Interrupt Enable Register*/
-#define UHCHIE_UPS3IE   (1 << 14)       /* Power Sense Port3 IntEn */
-#define UHCHIE_UPRIE    (1 << 13)       /* Port Resume IntEn */
-#define UHCHIE_UPS2IE   (1 << 12)       /* Power Sense Port2 IntEn */
-#define UHCHIE_UPS1IE   (1 << 11)       /* Power Sense Port1 IntEn */
-#define UHCHIE_TAIE     (1 << 10)       /* HCI Interface Transfer Abort
-                                           Interrupt Enable*/
-#define UHCHIE_HBAIE    (1 << 8)        /* HCI Buffer Active IntEn */
-#define UHCHIE_RWIE     (1 << 7)        /* Remote Wake-up IntEn */
-
-#define UHCHIT          __REG(0x4C00006C) /* UHC Interrupt Test register */
-
-#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
-
 /* PWRMODE register M field values */
 
 #define PWRMODE_IDLE            0x1
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index 39eb68319e28..b1fcd10ab6c6 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -131,6 +131,28 @@
 #define CKENB           __REG(0x41340010)       /* B Clock Enable Register */
 #define AC97_DIV        __REG(0x41340014)       /* AC97 clock divisor value register */
 
+#define ACCR_XPDIS              (1 << 31)       /* Core PLL Output Disable */
+#define ACCR_SPDIS              (1 << 30)       /* System PLL Output Disable */
+#define ACCR_D0CS               (1 << 26)       /* D0 Mode Clock Select */
+#define ACCR_PCCE               (1 << 11)       /* Power Mode Change Clock Enable */
+#define ACCR_DDR_D0CS           (1 << 7)        /* DDR SDRAM clock frequency in D0CS (PXA31x only) */
+
+#define ACCR_SMCFS_MASK         (0x7 << 23)     /* Static Memory Controller Frequency Select */
+#define ACCR_SFLFS_MASK         (0x3 << 18)     /* Frequency Select for Internal Memory Controller */
+#define ACCR_XSPCLK_MASK        (0x3 << 16)     /* Core Frequency during Frequency Change */
+#define ACCR_HSS_MASK           (0x3 << 14)     /* System Bus-Clock Frequency Select */
+#define ACCR_DMCFS_MASK         (0x3 << 12)     /* Dynamic Memory Controller Clock Frequency Select */
+#define ACCR_XN_MASK            (0x7 << 8)      /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
+#define ACCR_XL_MASK            (0x1f)          /* Core PLL Run-Mode-to-Oscillator Ratio */
+
+#define ACCR_SMCFS(x)           (((x) & 0x7) << 23)
+#define ACCR_SFLFS(x)           (((x) & 0x3) << 18)
+#define ACCR_XSPCLK(x)          (((x) & 0x3) << 16)
+#define ACCR_HSS(x)             (((x) & 0x3) << 14)
+#define ACCR_DMCFS(x)           (((x) & 0x3) << 12)
+#define ACCR_XN(x)              (((x) & 0x7) << 8)
+#define ACCR_XL(x)              ((x) & 0x1f)
+
 /*
  * Clock Enable Bit
  */
diff --git a/arch/arm/mach-pxa/include/mach/reset.h b/arch/arm/mach-pxa/include/mach/reset.h
index 9489a48871a8..7b8842cfa5fc 100644
--- a/arch/arm/mach-pxa/include/mach/reset.h
+++ b/arch/arm/mach-pxa/include/mach/reset.h
@@ -10,9 +10,12 @@
 extern unsigned int reset_status;
 extern void clear_reset_status(unsigned int mask);
 
-/*
- * register GPIO as reset generator
+/**
+ * init_gpio_reset() - register GPIO as reset generator
+ *
+ * @gpio - gpio nr
+ * @output - set gpio as out/low instead of input during normal work
  */
-extern int init_gpio_reset(int gpio);
+extern int init_gpio_reset(int gpio, int output);
 
 #endif /* __ASM_ARCH_RESET_H */
diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index bd14365f7ed5..31ac26b55bc1 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -16,6 +16,7 @@
 #endif
 
 #include <linux/fb.h>
+#include <linux/gpio.h>
 
 /* Spitz/Akita GPIOs */
 
@@ -100,13 +101,24 @@
 #define SPITZ_SCP_JK_A          SCOOP_GPCR_PA18  /* Low */
 #define SPITZ_SCP_ADC_TEMP_ON   SCOOP_GPCR_PA19  /* Low */
 
-#define SPITZ_SCP_IO_DIR      (SPITZ_SCP_LED_GREEN | SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
-                               SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_LED_ORANGE | \
+#define SPITZ_SCP_IO_DIR      (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
+                               SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \
                                SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
 #define SPITZ_SCP_IO_OUT      (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
 #define SPITZ_SCP_SUS_CLR     (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
 #define SPITZ_SCP_SUS_SET     0
 
+#define SPITZ_SCP_GPIO_BASE     (NR_BUILTIN_GPIO)
+#define SPITZ_GPIO_LED_GREEN    (SPITZ_SCP_GPIO_BASE + 0)
+#define SPITZ_GPIO_JK_B         (SPITZ_SCP_GPIO_BASE + 1)
+#define SPITZ_GPIO_CHRG_ON      (SPITZ_SCP_GPIO_BASE + 2)
+#define SPITZ_GPIO_MUTE_L       (SPITZ_SCP_GPIO_BASE + 3)
+#define SPITZ_GPIO_MUTE_R       (SPITZ_SCP_GPIO_BASE + 4)
+#define SPITZ_GPIO_CF_POWER     (SPITZ_SCP_GPIO_BASE + 5)
+#define SPITZ_GPIO_LED_ORANGE   (SPITZ_SCP_GPIO_BASE + 6)
+#define SPITZ_GPIO_JK_A         (SPITZ_SCP_GPIO_BASE + 7)
+#define SPITZ_GPIO_ADC_TEMP_ON  (SPITZ_SCP_GPIO_BASE + 8)
+
 /* Spitz Scoop Device (No. 2) GPIOs */
 /* Suspend States in comments */
 #define SPITZ_SCP2_IR_ON           SCOOP_GPCR_PA11  /* High */
@@ -119,15 +131,36 @@
 #define SPITZ_SCP2_BACKLIGHT_ON    SCOOP_GPCR_PA18  /* Low */
 #define SPITZ_SCP2_MIC_BIAS        SCOOP_GPCR_PA19  /* Low */
 
-#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
+#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
                            SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
                            SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
 
-#define SPITZ_SCP2_IO_OUT   (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
+#define SPITZ_SCP2_IO_OUT   (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
 #define SPITZ_SCP2_SUS_CLR  (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
                              SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
 #define SPITZ_SCP2_SUS_SET  (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
 
+#define SPITZ_SCP2_GPIO_BASE            (NR_BUILTIN_GPIO + 12)
+#define SPITZ_GPIO_IR_ON                (SPITZ_SCP2_GPIO_BASE + 0)
+#define SPITZ_GPIO_AKIN_PULLUP          (SPITZ_SCP2_GPIO_BASE + 1
+#define SPITZ_GPIO_RESERVED_1           (SPITZ_SCP2_GPIO_BASE + 2)
+#define SPITZ_GPIO_RESERVED_2           (SPITZ_SCP2_GPIO_BASE + 3)
+#define SPITZ_GPIO_RESERVED_3           (SPITZ_SCP2_GPIO_BASE + 4)
+#define SPITZ_GPIO_RESERVED_4           (SPITZ_SCP2_GPIO_BASE + 5)
+#define SPITZ_GPIO_BACKLIGHT_CONT       (SPITZ_SCP2_GPIO_BASE + 6)
+#define SPITZ_GPIO_BACKLIGHT_ON         (SPITZ_SCP2_GPIO_BASE + 7)
+#define SPITZ_GPIO_MIC_BIAS             (SPITZ_SCP2_GPIO_BASE + 8)
+
+/* Akita IO Expander GPIOs */
+#define AKITA_IOEXP_GPIO_BASE           (NR_BUILTIN_GPIO + 12)
+#define AKITA_GPIO_RESERVED_0           (AKITA_IOEXP_GPIO_BASE + 0)
+#define AKITA_GPIO_RESERVED_1           (AKITA_IOEXP_GPIO_BASE + 1)
+#define AKITA_GPIO_MIC_BIAS             (AKITA_IOEXP_GPIO_BASE + 2)
+#define AKITA_GPIO_BACKLIGHT_ON         (AKITA_IOEXP_GPIO_BASE + 3)
+#define AKITA_GPIO_BACKLIGHT_CONT       (AKITA_IOEXP_GPIO_BASE + 4)
+#define AKITA_GPIO_AKIN_PULLUP          (AKITA_IOEXP_GPIO_BASE + 5)
+#define AKITA_GPIO_IR_ON                (AKITA_IOEXP_GPIO_BASE + 6)
+#define AKITA_GPIO_RESERVED_7           (AKITA_IOEXP_GPIO_BASE + 7)
 
 /* Spitz IRQ Definitions */
 
@@ -154,5 +187,4 @@
  */
 extern struct platform_device spitzscoop_device;
 extern struct platform_device spitzscoop2_device;
-extern struct platform_device spitzssp_device;
 extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/include/mach/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h
index a012882c9ee6..cb5cb766f0f1 100644
--- a/arch/arm/mach-pxa/include/mach/ssp.h
+++ b/arch/arm/mach-pxa/include/mach/ssp.h
@@ -20,6 +20,7 @@
 #define __ASM_ARCH_SSP_H
 
 #include <linux/list.h>
+#include <linux/io.h>
 
 enum pxa_ssp_type {
         SSP_UNDEFINED = 0,
@@ -78,6 +79,29 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
 int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
 void ssp_exit(struct ssp_dev *dev);
 
+/**
+ * ssp_write_reg - Write to a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to write to
+ * @val: Value to be written.
+ */
+static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
+{
+        __raw_writel(val, dev->mmio_base + reg);
+}
+
+/**
+ * ssp_read_reg - Read from a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to read from
+ */
+static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg)
+{
+        return __raw_readl(dev->mmio_base + reg);
+}
+
 struct ssp_device *ssp_request(int port, const char *label);
 void ssp_free(struct ssp_device *);
 #endif /* __ASM_ARCH_SSP_H */
diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h
index 641d0ec110bb..903e1a2e6641 100644
--- a/arch/arm/mach-pxa/include/mach/trizeps4.h
+++ b/arch/arm/mach-pxa/include/mach/trizeps4.h
@@ -17,11 +17,16 @@
 #define TRIZEPS4_PIC_PHYS       (PXA_CS3_PHYS)  /* Logic chip on ConXS-Board */
 #define TRIZEPS4_SDRAM_BASE     0xa0000000      /* SDRAM region */
 
-#define TRIZEPS4_CFSR_PHYS      (PXA_CS3_PHYS)                  /* Logic chip on ConXS-Board CSFR register */
-#define TRIZEPS4_BOCR_PHYS      (PXA_CS3_PHYS+0x02000000)       /* Logic chip on ConXS-Board BOCR register */
-#define TRIZEPS4_IRCR_PHYS      (PXA_CS3_PHYS+0x02400000)       /* Logic chip on ConXS-Board IRCR register*/
-#define TRIZEPS4_UPSR_PHYS      (PXA_CS3_PHYS+0x02800000)       /* Logic chip on ConXS-Board UPSR register*/
-#define TRIZEPS4_DICR_PHYS      (PXA_CS3_PHYS+0x03800000)       /* Logic chip on ConXS-Board DICR register*/
+                                /* Logic on ConXS-board CSFR register*/
+#define TRIZEPS4_CFSR_PHYS      (PXA_CS3_PHYS)
+                                /* Logic on ConXS-board BOCR register*/
+#define TRIZEPS4_BOCR_PHYS      (PXA_CS3_PHYS+0x02000000)
+                                /* Logic on ConXS-board IRCR register*/
+#define TRIZEPS4_IRCR_PHYS      (PXA_CS3_PHYS+0x02400000)
+                                /* Logic on ConXS-board UPSR register*/
+#define TRIZEPS4_UPSR_PHYS      (PXA_CS3_PHYS+0x02800000)
+                                /* Logic on ConXS-board DICR register*/
+#define TRIZEPS4_DICR_PHYS      (PXA_CS3_PHYS+0x03800000)
 
 /* virtual memory regions */
 #define TRIZEPS4_DISK_VIRT      0xF0000000      /* Disk On Chip region */
@@ -54,6 +59,15 @@
 #define GPIO_MMC_DET            12
 #define TRIZEPS4_MMC_IRQ        IRQ_GPIO(GPIO_MMC_DET)
 
+/* DOC NAND chip */
+#define GPIO_DOC_LOCK           94
+#define GPIO_DOC_IRQ            93
+#define TRIZEPS4_DOC_IRQ        IRQ_GPIO(GPIO_DOC_IRQ)
+
+/* SPI interface */
+#define GPIO_SPI                53
+#define TRIZEPS4_SPI_IRQ        IRQ_GPIO(GPIO_SPI)
+
 /* LEDS using tx2 / rx2 */
 #define GPIO_SYS_BUSY_LED       46
 #define GPIO_HEARTBEAT_LED      47
@@ -62,24 +76,66 @@
 #define GPIO_PIC                0
 #define TRIZEPS4_PIC_IRQ        IRQ_GPIO(GPIO_PIC)
 
-#define CFSR_P2V(x)             ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
-#define CFSR_V2P(x)             ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
+#ifdef CONFIG_MACH_TRIZEPS_CONXS
+/* for CONXS base board define these registers */
+#define CFSR_P2V(x)     ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
+#define CFSR_V2P(x)     ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
 
-#define BCR_P2V(x)              ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
-#define BCR_V2P(x)              ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
+#define BCR_P2V(x)      ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
+#define BCR_V2P(x)      ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
 
-#define DCR_P2V(x)              ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
-#define DCR_V2P(x)              ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
+#define DCR_P2V(x)      ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
+#define DCR_V2P(x)      ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
+
+#define IRCR_P2V(x)     ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT)
+#define IRCR_V2P(x)     ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS)
 
 #ifndef __ASSEMBLY__
-#define ConXS_CFSR              (*((volatile unsigned short *)CFSR_P2V(0x0C000000)))
-#define ConXS_BCR               (*((volatile unsigned short *)BCR_P2V(0x0E000000)))
-#define ConXS_DCR               (*((volatile unsigned short *)DCR_P2V(0x0F800000)))
+static inline unsigned short CFSR_readw(void)
+{
+        /* [Compact Flash Status Register] is read only */
+        return *((unsigned short *)CFSR_P2V(0x0C000000));
+}
+static inline void BCR_writew(unsigned short value)
+{
+        /* [Board Control Regsiter] is write only */
+        *((unsigned short *)BCR_P2V(0x0E000000)) = value;
+}
+static inline void DCR_writew(unsigned short value)
+{
+        /* [Display Control Register] is write only */
+        *((unsigned short *)DCR_P2V(0x0E000000)) = value;
+}
+static inline void IRCR_writew(unsigned short value)
+{
+        /* [InfraRed data Control Register] is write only */
+        *((unsigned short *)IRCR_P2V(0x0E000000)) = value;
+}
 #else
 #define ConXS_CFSR              CFSR_P2V(0x0C000000)
 #define ConXS_BCR               BCR_P2V(0x0E000000)
 #define ConXS_DCR               DCR_P2V(0x0F800000)
+#define ConXS_IRCR              IRCR_P2V(0x0F800000)
 #endif
+#else
+/* for whatever baseboard define function registers */
+static inline unsigned short CFSR_readw(void)
+{
+        return 0;
+}
+static inline void BCR_writew(unsigned short value)
+{
+        ;
+}
+static inline void DCR_writew(unsigned short value)
+{
+        ;
+}
+static inline void IRCR_writew(unsigned short value)
+{
+        ;
+}
+#endif  /* CONFIG_MACH_TRIZEPS_CONXS */
 
 #define ConXS_CFSR_BVD_MASK     0x0003
 #define ConXS_CFSR_BVD1         (1 << 0)
diff --git a/arch/arm/mach-pxa/include/mach/viper.h b/arch/arm/mach-pxa/include/mach/viper.h
new file mode 100644
index 000000000000..10988c270ca3
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/viper.h
@@ -0,0 +1,96 @@
+/*
+ * arch/arm/mach-pxa/include/mach/viper.h
+ *
+ * Author:      Ian Campbell
+ * Created:     Feb 03, 2003
+ * Copyright:   Arcom Control Systems.
+ *
+ * Maintained by Marc Zyngier <maz@misterjones.org>
+ *                            <marc.zyngier@altran.com>
+ *
+ * Created based on lubbock.h:
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ARCH_VIPER_H
+#define ARCH_VIPER_H
+
+#define VIPER_BOOT_PHYS         PXA_CS0_PHYS
+#define VIPER_FLASH_PHYS        PXA_CS1_PHYS
+#define VIPER_ETH_PHYS          PXA_CS2_PHYS
+#define VIPER_USB_PHYS          PXA_CS3_PHYS
+#define VIPER_ETH_DATA_PHYS     PXA_CS4_PHYS
+#define VIPER_CPLD_PHYS         PXA_CS5_PHYS
+
+#define VIPER_CPLD_BASE         (0xf0000000)
+#define VIPER_PC104IO_BASE      (0xf1000000)
+#define VIPER_USB_BASE          (0xf1800000)
+
+#define VIPER_ETH_GPIO          (0)
+#define VIPER_CPLD_GPIO         (1)
+#define VIPER_USB_GPIO          (2)
+#define VIPER_UARTA_GPIO        (4)
+#define VIPER_UARTB_GPIO        (3)
+#define VIPER_CF_CD_GPIO        (32)
+#define VIPER_CF_RDY_GPIO       (8)
+#define VIPER_BCKLIGHT_EN_GPIO  (9)
+#define VIPER_LCD_EN_GPIO       (10)
+#define VIPER_PSU_DATA_GPIO     (6)
+#define VIPER_PSU_CLK_GPIO      (11)
+#define VIPER_UART_SHDN_GPIO    (12)
+#define VIPER_BRIGHTNESS_GPIO   (16)
+#define VIPER_PSU_nCS_LD_GPIO   (19)
+#define VIPER_UPS_GPIO          (20)
+#define VIPER_CF_POWER_GPIO     (82)
+#define VIPER_TPM_I2C_SDA_GPIO  (26)
+#define VIPER_TPM_I2C_SCL_GPIO  (27)
+#define VIPER_RTC_I2C_SDA_GPIO  (83)
+#define VIPER_RTC_I2C_SCL_GPIO  (84)
+
+#define VIPER_CPLD_P2V(x)       ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE)
+#define VIPER_CPLD_V2P(x)       ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS)
+
+#ifndef __ASSEMBLY__
+#  define __VIPER_CPLD_REG(x)   (*((volatile u16 *)VIPER_CPLD_P2V(x)))
+#endif
+
+/* board level registers in the CPLD: (offsets from CPLD_BASE) ... */
+
+/* ... Physical addresses */
+#define _VIPER_LO_IRQ_STATUS    (VIPER_CPLD_PHYS + 0x100000)
+#define _VIPER_ICR_PHYS         (VIPER_CPLD_PHYS + 0x100002)
+#define _VIPER_HI_IRQ_STATUS    (VIPER_CPLD_PHYS + 0x100004)
+#define _VIPER_VERSION_PHYS     (VIPER_CPLD_PHYS + 0x100006)
+#define VIPER_UARTA_PHYS        (VIPER_CPLD_PHYS + 0x300010)
+#define VIPER_UARTB_PHYS        (VIPER_CPLD_PHYS + 0x300000)
+#define _VIPER_SRAM_BASE        (VIPER_CPLD_PHYS + 0x800000)
+
+/* ... Virtual addresses */
+#define VIPER_LO_IRQ_STATUS     __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS)
+#define VIPER_HI_IRQ_STATUS     __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS)
+#define VIPER_VERSION           __VIPER_CPLD_REG(_VIPER_VERSION_PHYS)
+#define VIPER_ICR               __VIPER_CPLD_REG(_VIPER_ICR_PHYS)
+
+/* Decode VIPER_VERSION register */
+#define VIPER_CPLD_REVISION(x)  (((x) >> 5) & 0x7)
+#define VIPER_BOARD_VERSION(x)  (((x) >> 3) & 0x3)
+#define VIPER_BOARD_ISSUE(x)    (((x) >> 0) & 0x7)
+
+/* Interrupt and Configuration Register (VIPER_ICR) */
+/* This is a write only register. Only CF_RST is used under Linux */
+
+extern void viper_cf_rst(int state);
+
+#define VIPER_ICR_RETRIG        (1 << 0)
+#define VIPER_ICR_AUTO_CLR      (1 << 1)
+#define VIPER_ICR_R_DIS         (1 << 2)
+#define VIPER_ICR_CF_RST        (1 << 3)
+
+#endif
+
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 5e95c5372fec..fa69c3a6a38e 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -57,7 +57,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
 
         pxa_internal_irq_nr = irq_nr;
 
-        for (irq = 0; irq < irq_nr; irq += 32) {
+        for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
                 _ICMR(irq) = 0; /* disable all IRQs */
                 _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
         }
diff --git a/arch/arm/mach-pxa/leds-trizeps4.c b/arch/arm/mach-pxa/leds-trizeps4.c
deleted file mode 100644
index 3bc29007df3a..000000000000
--- a/arch/arm/mach-pxa/leds-trizeps4.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-trizeps4.c
- *
- *  Author:     Jürgen Schindele
- *  Created:    20 02, 2006
- *  Copyright:  Jürgen Schindele
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/system.h>
-#include <asm/types.h>
-#include <asm/leds.h>
-
-#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-gpio.h>
-#include <mach/trizeps4.h>
-
-#include "leds.h"
-
-#define LED_STATE_ENABLED       1
-#define LED_STATE_CLAIMED       2
-
-#define SYS_BUSY                0x01
-#define HEARTBEAT               0x02
-#define BLINK                   0x04
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void trizeps4_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = 0;
-                pxa_gpio_mode( GPIO_SYS_BUSY_LED  | GPIO_OUT);          /* LED1 */
-                pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT);          /* LED2 */
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = 0;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                hw_led_state ^= HEARTBEAT;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                hw_led_state &= ~SYS_BUSY;
-                break;
-
-        case led_idle_end:
-                hw_led_state |= SYS_BUSY;
-                break;
-#endif
-
-        case led_halted:
-                break;
-
-        case led_green_on:
-                hw_led_state |= BLINK;
-                break;
-
-        case led_green_off:
-                hw_led_state &= ~BLINK;
-                break;
-
-        case led_amber_on:
-                break;
-
-        case led_amber_off:
-                break;
-
-        case led_red_on:
-                break;
-
-        case led_red_off:
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED) {
-                switch (hw_led_state) {
-                        case 0:
-                                GPSR(GPIO_SYS_BUSY_LED)  |= GPIO_bit(GPIO_SYS_BUSY_LED);
-                                GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
-                                break;
-                        case 1:
-                                GPCR(GPIO_SYS_BUSY_LED)  |= GPIO_bit(GPIO_SYS_BUSY_LED);
-                                GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
-                                break;
-                        case 2:
-                                GPSR(GPIO_SYS_BUSY_LED)  |= GPIO_bit(GPIO_SYS_BUSY_LED);
-                                GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
-                                break;
-                        case 3:
-                                GPCR(GPIO_SYS_BUSY_LED)  |= GPIO_bit(GPIO_SYS_BUSY_LED);
-                                GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
-                                break;
-                }
-        }
-        else {
-                /* turn all off */
-                GPSR(GPIO_SYS_BUSY_LED)  |= GPIO_bit(GPIO_SYS_BUSY_LED);
-                GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
-        }
-
-        local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds.c b/arch/arm/mach-pxa/leds.c
index e13eb841e48d..bbe4d5f6afaa 100644
--- a/arch/arm/mach-pxa/leds.c
+++ b/arch/arm/mach-pxa/leds.c
@@ -24,8 +24,6 @@ pxa_leds_init(void)
                 leds_event = mainstone_leds_event;
         if (machine_is_pxa_idp())
                 leds_event = idp_leds_event;
-        if (machine_is_trizeps4())
-                leds_event = trizeps4_leds_event;
 
         leds_event(led_start);
         return 0;
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 58f3402a0375..b4d00aba0e31 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -20,6 +20,7 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/spi/spi.h>
 #include <linux/smc91x.h>
 
 #include <asm/types.h>
@@ -38,6 +39,7 @@
 #include <mach/gpio.h>
 #include <mach/pxafb.h>
 #include <mach/ssp.h>
+#include <mach/pxa2xx_spi.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/pxa3xx_nand.h>
 #include <mach/littleton.h>
@@ -72,8 +74,8 @@ static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
 
         /* SSP2 */
         GPIO25_SSP2_SCLK,
-        GPIO17_SSP2_FRM,
         GPIO27_SSP2_TXD,
+        GPIO17_GPIO,    /* SFRM as chip-select */
 
         /* Debug Ethernet */
         GPIO90_GPIO,
@@ -123,160 +125,6 @@ static struct platform_device smc91x_device = {
 };
 
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-/* use bit 30, 31 as the indicator of command parameter number */
-#define CMD0(x)         ((0x00000000) | ((x) << 9))
-#define CMD1(x, x1)     ((0x40000000) | ((x) << 9) | 0x100 | (x1))
-#define CMD2(x, x1, x2) ((0x80000000) | ((x) << 18) | 0x20000 |\
-                         ((x1) << 9) | 0x100 | (x2))
-
-static uint32_t lcd_panel_reset[] = {
-        CMD0(0x1), /* reset */
-        CMD0(0x0), /* nop */
-        CMD0(0x0), /* nop */
-        CMD0(0x0), /* nop */
-};
-
-static uint32_t lcd_panel_on[] = {
-        CMD0(0x29),             /* Display ON */
-        CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
-        CMD0(0x11),             /* Sleep out */
-        CMD1(0xB0, 0x16),       /* Wake */
-};
-
-static uint32_t lcd_panel_off[] = {
-        CMD0(0x28),             /* Display OFF */
-        CMD2(0xB8, 0x80, 0x02), /* Output Control */
-        CMD0(0x10),             /* Sleep in */
-        CMD1(0xB0, 0x00),       /* Deep stand by in */
-};
-
-static uint32_t lcd_vga_pass_through[] = {
-        CMD1(0xB0, 0x16),
-        CMD1(0xBC, 0x80),
-        CMD1(0xE1, 0x00),
-        CMD1(0x36, 0x50),
-        CMD1(0x3B, 0x00),
-};
-
-static uint32_t lcd_qvga_pass_through[] = {
-        CMD1(0xB0, 0x16),
-        CMD1(0xBC, 0x81),
-        CMD1(0xE1, 0x00),
-        CMD1(0x36, 0x50),
-        CMD1(0x3B, 0x22),
-};
-
-static uint32_t lcd_vga_transfer[] = {
-        CMD1(0xcf, 0x02),       /* Blanking period control (1) */
-        CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
-        CMD1(0xd1, 0x01),       /* CKV timing control on/off */
-        CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
-        CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
-        CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
-        CMD1(0xd5, 0x14),       /* ASW timing control (2) */
-        CMD0(0x21),             /* Invert for normally black display */
-        CMD0(0x29),             /* Display on */
-};
-
-static uint32_t lcd_qvga_transfer[] = {
-        CMD1(0xd6, 0x02),       /* Blanking period control (1) */
-        CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
-        CMD1(0xd8, 0x01),       /* CKV timing control on/off */
-        CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
-        CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
-        CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
-        CMD1(0xe0, 0x0a),       /* ASW timing control (2) */
-        CMD0(0x21),             /* Invert for normally black display */
-        CMD0(0x29),             /* Display on */
-};
-
-static uint32_t lcd_panel_config[] = {
-        CMD2(0xb8, 0xff, 0xf9), /* Output control */
-        CMD0(0x11),             /* sleep out */
-        CMD1(0xba, 0x01),       /* Display mode (1) */
-        CMD1(0xbb, 0x00),       /* Display mode (2) */
-        CMD1(0x3a, 0x60),       /* Display mode 18-bit RGB */
-        CMD1(0xbf, 0x10),       /* Drive system change control */
-        CMD1(0xb1, 0x56),       /* Booster operation setup */
-        CMD1(0xb2, 0x33),       /* Booster mode setup */
-        CMD1(0xb3, 0x11),       /* Booster frequency setup */
-        CMD1(0xb4, 0x02),       /* Op amp/system clock */
-        CMD1(0xb5, 0x35),       /* VCS voltage */
-        CMD1(0xb6, 0x40),       /* VCOM voltage */
-        CMD1(0xb7, 0x03),       /* External display signal */
-        CMD1(0xbd, 0x00),       /* ASW slew rate */
-        CMD1(0xbe, 0x00),       /* Dummy data for QuadData operation */
-        CMD1(0xc0, 0x11),       /* Sleep out FR count (A) */
-        CMD1(0xc1, 0x11),       /* Sleep out FR count (B) */
-        CMD1(0xc2, 0x11),       /* Sleep out FR count (C) */
-        CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
-        CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
-        CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
-        CMD1(0xc6, 0xc0),       /* Sleep out FR count (G) */
-        CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
-        CMD1(0xc8, 0x44),       /* Gamma 1 fine tuning (2) */
-        CMD1(0xc9, 0x33),       /* Gamma 1 inclination adjustment */
-        CMD1(0xca, 0x00),       /* Gamma 1 blue offset adjustment */
-        CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
-};
-
-static void ssp_reconfig(struct ssp_dev *dev, int nparam)
-{
-        static int last_nparam = -1;
-
-        /* check if it is necessary to re-config SSP */
-        if (nparam == last_nparam)
-                return;
-
-        ssp_disable(dev);
-        ssp_config(dev, (nparam == 2) ? 0x0010058a : 0x00100581, 0x18, 0, 0);
-
-        last_nparam = nparam;
-}
-
-static void ssp_send_cmd(uint32_t *cmd, int num)
-{
-        static int ssp_initialized;
-        static struct ssp_dev ssp2;
-
-        int i;
-
-        if (!ssp_initialized) {
-                ssp_init(&ssp2, 2, SSP_NO_IRQ);
-                ssp_initialized = 1;
-        }
-
-        clk_enable(ssp2.ssp->clk);
-        for (i = 0; i < num; i++, cmd++) {
-                ssp_reconfig(&ssp2, (*cmd >> 30) & 0x3);
-                ssp_write_word(&ssp2, *cmd & 0x3fffffff);
-
-                /* FIXME: ssp_flush() is mandatory here to work */
-                ssp_flush(&ssp2);
-        }
-        clk_disable(ssp2.ssp->clk);
-}
-
-static void littleton_lcd_power(int on, struct fb_var_screeninfo *var)
-{
-        if (on) {
-                ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_on));
-                ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_reset));
-                if (var->xres > 240) {
-                        /* VGA */
-                        ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_pass_through));
-                        ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
-                        ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_transfer));
-                } else {
-                        /* QVGA */
-                        ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_pass_through));
-                        ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
-                        ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_transfer));
-                }
-        } else
-                ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_off));
-}
-
 static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = {
         [0] = {
                 /* VGA */
@@ -312,7 +160,6 @@ static struct pxafb_mach_info littleton_lcd_info = {
         .modes                  = tpo_tdo24mtea1_modes,
         .num_modes              = 2,
         .lcd_conn               = LCD_COLOR_TFT_16BPP,
-        .pxafb_lcd_power        = littleton_lcd_power,
 };
 
 static void littleton_init_lcd(void)
@@ -323,6 +170,51 @@ static void littleton_init_lcd(void)
 static inline void littleton_init_lcd(void) {};
 #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
 
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+static struct pxa2xx_spi_master littleton_spi_info = {
+        .num_chipselect         = 1,
+};
+
+static void littleton_tdo24m_cs(u32 cmd)
+{
+        gpio_set_value(LITTLETON_GPIO_LCD_CS, !(cmd == PXA2XX_CS_ASSERT));
+}
+
+static struct pxa2xx_spi_chip littleton_tdo24m_chip = {
+        .rx_threshold   = 1,
+        .tx_threshold   = 1,
+        .cs_control     = littleton_tdo24m_cs,
+};
+
+static struct spi_board_info littleton_spi_devices[] __initdata = {
+        {
+                .modalias       = "tdo24m",
+                .max_speed_hz   = 1000000,
+                .bus_num        = 2,
+                .chip_select    = 0,
+                .controller_data= &littleton_tdo24m_chip,
+        },
+};
+
+static void __init littleton_init_spi(void)
+{
+        int err;
+
+        err = gpio_request(LITTLETON_GPIO_LCD_CS, "LCD_CS");
+        if (err) {
+                pr_warning("failed to request GPIO for LCS CS\n");
+                return;
+        }
+
+        gpio_direction_output(LITTLETON_GPIO_LCD_CS, 1);
+
+        pxa2xx_set_spi_info(2, &littleton_spi_info);
+        spi_register_board_info(ARRAY_AND_SIZE(littleton_spi_devices));
+}
+#else
+static inline void littleton_init_spi(void) {}
+#endif
+
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
 static unsigned int littleton_matrix_key_map[] = {
         /* KEY(row, col, key_code) */
@@ -433,6 +325,7 @@ static void __init littleton_init(void)
          */
         platform_device_register(&smc91x_device);
 
+        littleton_init_spi();
         littleton_init_lcd();
         littleton_init_keypad();
         littleton_init_nand();
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index b7038948d1d4..de3f67daaacf 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -40,7 +40,7 @@
 
 #include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa27x.h>
 #include <mach/lpd270.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
@@ -51,6 +51,43 @@
 #include "generic.h"
 #include "devices.h"
 
+static unsigned long lpd270_pin_config[] __initdata = {
+        /* Chip Selects */
+        GPIO15_nCS_1,   /* Mainboard Flash */
+        GPIO78_nCS_2,   /* CPLD + Ethernet */
+
+        /* LCD - 16bpp Active TFT */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+        GPIO16_PWM0_OUT,        /* Backlight */
+
+        /* USB Host */
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+
+        /* AC97 */
+        GPIO45_AC97_SYSCLK,
+
+        GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
+};
 
 static unsigned int lpd270_irq_enabled;
 
@@ -88,8 +125,7 @@ static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
                 GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
                 if (likely(pending)) {
                         irq = LPD270_IRQ(0) + __ffs(pending);
-                        desc = irq_desc + irq;
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
 
                         pending = __raw_readw(LPD270_INT_STATUS) &
                                                 lpd270_irq_enabled;
@@ -265,8 +301,8 @@ static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
 static struct pxafb_mach_info sharp_lq057q3dc02 = {
         .modes                  = &sharp_lq057q3dc02_mode,
         .num_modes              = 1,
-        .lccr0                  = 0x07800080,
-        .lccr3                  = 0x00400000,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
+                                  LCD_ALTERNATE_MAPPING,
 };
 
 /* 12.1" TFT SVGA (LoLo display number 2) */
@@ -287,8 +323,8 @@ static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
 static struct pxafb_mach_info sharp_lq121s1dg31 = {
         .modes                  = &sharp_lq121s1dg31_mode,
         .num_modes              = 1,
-        .lccr0                  = 0x07800080,
-        .lccr3                  = 0x00400000,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
+                                  LCD_ALTERNATE_MAPPING,
 };
 
 /* 3.6" TFT QVGA (LoLo display number 3) */
@@ -309,8 +345,8 @@ static struct pxafb_mode_info sharp_lq036q1da01_mode = {
 static struct pxafb_mach_info sharp_lq036q1da01 = {
         .modes                  = &sharp_lq036q1da01_mode,
         .num_modes              = 1,
-        .lccr0                  = 0x07800080,
-        .lccr3                  = 0x00400000,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
+                                  LCD_ALTERNATE_MAPPING,
 };
 
 /* 6.4" TFT VGA (LoLo display number 5) */
@@ -331,8 +367,8 @@ static struct pxafb_mode_info sharp_lq64d343_mode = {
 static struct pxafb_mach_info sharp_lq64d343 = {
         .modes                  = &sharp_lq64d343_mode,
         .num_modes              = 1,
-        .lccr0                  = 0x07800080,
-        .lccr3                  = 0x00400000,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
+                                  LCD_ALTERNATE_MAPPING,
 };
 
 /* 10.4" TFT VGA (LoLo display number 7) */
@@ -353,8 +389,8 @@ static struct pxafb_mode_info sharp_lq10d368_mode = {
 static struct pxafb_mach_info sharp_lq10d368 = {
         .modes                  = &sharp_lq10d368_mode,
         .num_modes              = 1,
-        .lccr0                  = 0x07800080,
-        .lccr3                  = 0x00400000,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
+                                  LCD_ALTERNATE_MAPPING,
 };
 
 /* 3.5" TFT QVGA (LoLo display number 8) */
@@ -375,8 +411,8 @@ static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
 static struct pxafb_mach_info sharp_lq035q7db02_20 = {
         .modes                  = &sharp_lq035q7db02_20_mode,
         .num_modes              = 1,
-        .lccr0                  = 0x07800080,
-        .lccr3                  = 0x00400000,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
+                                  LCD_ALTERNATE_MAPPING,
 };
 
 static struct pxafb_mach_info *lpd270_lcd_to_use;
@@ -411,27 +447,15 @@ static struct platform_device *platform_devices[] __initdata = {
         &lpd270_flash_device[1],
 };
 
-static int lpd270_ohci_init(struct device *dev)
-{
-        /* setup Port1 GPIO pin. */
-        pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN);   /* USBHPWR1 */
-        pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT);  /* USBHPEN1 */
-
-        /* Set the Power Control Polarity Low and Power Sense
-           Polarity Low to active low. */
-        UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
-                ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
-
-        return 0;
-}
-
 static struct pxaohci_platform_data lpd270_ohci_platform_data = {
         .port_mode      = PMM_PERPORT_MODE,
-        .init           = lpd270_ohci_init,
+        .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
 };
 
 static void __init lpd270_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
+
         lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
         lpd270_flash_data[1].width = 4;
 
@@ -442,12 +466,6 @@ static void __init lpd270_init(void)
          */
         ARB_CNTRL = ARB_CORE_PARK | 0x234;
 
-        /*
-         * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
-         */
-        pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
-        pxa_gpio_mode(GPIO16_PWM0_MD);
-
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
         pxa_set_ac97_info(NULL);
@@ -473,15 +491,6 @@ static void __init lpd270_map_io(void)
         pxa_map_io();
         iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
 
-        /* initialize sleep mode regs (wake-up sources, etc) */
-        PGSR0 = 0x00008800;
-        PGSR1 = 0x00000002;
-        PGSR2 = 0x0001FC00;
-        PGSR3 = 0x00001F81;
-        PWER  = 0xC0000002;
-        PRER  = 0x00000002;
-        PFER  = 0x00000002;
-
         /* for use I SRAM as framebuffer.  */
         PSLR |= 0x00000F04;
         PCFR  = 0x00000066;
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 4ffdff2d9ff1..bff704354c1a 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -57,13 +57,36 @@
 
 static unsigned long lubbock_pin_config[] __initdata = {
         GPIO15_nCS_1,   /* CS1 - Flash */
+        GPIO78_nCS_2,   /* CS2 - Baseboard FGPA */
         GPIO79_nCS_3,   /* CS3 - SMC ethernet */
+        GPIO80_nCS_4,   /* CS4 - SA1111 */
 
         /* SSP data pins */
         GPIO23_SSP1_SCLK,
         GPIO25_SSP1_TXD,
         GPIO26_SSP1_RXD,
 
+        /* LCD - 16bpp DSTN */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+
         /* BTUART */
         GPIO42_BTUART_RXD,
         GPIO43_BTUART_TXD,
@@ -132,8 +155,7 @@ static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
                 GEDR(0) = GPIO_bit(0);  /* clear our parent irq */
                 if (likely(pending)) {
                         irq = LUBBOCK_IRQ(0) + __ffs(pending);
-                        desc = irq_desc + irq;
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
                 }
                 pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
         } while (pending);
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 143f28adaf95..519138bc5f85 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -409,7 +409,7 @@ static struct platform_device backlight = {
  * LEDs
  */
 
-struct gpio_led gpio_leds[] = {
+static struct gpio_led gpio_leds[] = {
         {
                 .name = "magician::vibra",
                 .default_trigger = "none",
@@ -669,18 +669,10 @@ static struct pxamci_platform_data magician_mci_info = {
  * USB OHCI
  */
 
-static int magician_ohci_init(struct device *dev)
-{
-        UHCHR = (UHCHR | UHCHR_SSEP2 | UHCHR_PCPL | UHCHR_CGR) &
-            ~(UHCHR_SSEP1 | UHCHR_SSEP3 | UHCHR_SSE);
-
-        return 0;
-}
-
 static struct pxaohci_platform_data magician_ohci_info = {
-        .port_mode    = PMM_PERPORT_MODE,
-        .init         = magician_ohci_init,
-        .power_budget = 0,
+        .port_mode      = PMM_PERPORT_MODE,
+        .flags          = ENABLE_PORT1 | ENABLE_PORT3 | POWER_CONTROL_LOW,
+        .power_budget   = 0,
 };
 
 
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index d44af761564d..f2c7ad8f2b6b 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -162,8 +162,7 @@ static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
                 GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
                 if (likely(pending)) {
                         irq = MAINSTONE_IRQ(0) + __ffs(pending);
-                        desc = irq_desc + irq;
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
                 }
                 pending = MST_INTSETCLR & mainstone_irq_enabled;
         } while (pending);
@@ -508,19 +507,9 @@ static struct platform_device *platform_devices[] __initdata = {
         &mst_gpio_keys_device,
 };
 
-static int mainstone_ohci_init(struct device *dev)
-{
-        /* Set the Power Control Polarity Low and Power Sense
-           Polarity Low to active low. */
-        UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
-                ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
-
-        return 0;
-}
-
 static struct pxaohci_platform_data mainstone_ohci_platform_data = {
         .port_mode      = PMM_PERPORT_MODE,
-        .init           = mainstone_ohci_init,
+        .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
 };
 
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 925575f10acf..2061c00c8ead 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -25,7 +25,12 @@
 
 #include "generic.h"
 
-#define PGSR(x)         __REG2(0x40F00020, ((x) & 0x60) >> 3)
+#define gpio_to_bank(gpio)      ((gpio) >> 5)
+
+#define PGSR(x)         __REG2(0x40F00020, (x) << 2)
+#define __GAFR(u, x)    __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
+#define GAFR_L(x)       __GAFR(0, x)
+#define GAFR_U(x)       __GAFR(1, x)
 
 #define PWER_WE35       (1 << 24)
 
@@ -38,49 +43,59 @@ struct gpio_desc {
 };
 
 static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
+static int gpio_nr;
 
-static int __mfp_config_lpm(unsigned gpio, unsigned long lpm)
-{
-        unsigned mask = GPIO_bit(gpio);
-
-        /* low power state */
-        switch (lpm) {
-        case MFP_LPM_DRIVE_HIGH:
-                PGSR(gpio) |= mask;
-                break;
-        case MFP_LPM_DRIVE_LOW:
-                PGSR(gpio) &= ~mask;
-                break;
-        case MFP_LPM_INPUT:
-                break;
-        default:
-                pr_warning("%s: invalid low power state for GPIO%d\n",
-                                __func__, gpio);
-                return -EINVAL;
-        }
-        return 0;
-}
+static unsigned long gpdr_lpm[4];
 
 static int __mfp_config_gpio(unsigned gpio, unsigned long c)
 {
         unsigned long gafr, mask = GPIO_bit(gpio);
-        int fn;
+        int bank = gpio_to_bank(gpio);
+        int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
+        int shft = (gpio & 0xf) << 1;
+        int fn = MFP_AF(c);
+        int dir = c & MFP_DIR_OUT;
 
-        fn = MFP_AF(c);
         if (fn > 3)
                 return -EINVAL;
 
-        /* alternate function and direction */
-        gafr = GAFR(gpio) & ~(0x3 << ((gpio & 0xf) * 2));
-        GAFR(gpio) = gafr |  (fn  << ((gpio & 0xf) * 2));
+        /* alternate function and direction at run-time */
+        gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank);
+        gafr = (gafr & ~(0x3 << shft)) | (fn << shft);
 
-        if (c & MFP_DIR_OUT)
+        if (uorl == 0)
+                GAFR_L(bank) = gafr;
+        else
+                GAFR_U(bank) = gafr;
+
+        if (dir == MFP_DIR_OUT)
                 GPDR(gpio) |= mask;
         else
                 GPDR(gpio) &= ~mask;
 
-        if (__mfp_config_lpm(gpio, c & MFP_LPM_STATE_MASK))
-                return -EINVAL;
+        /* alternate function and direction at low power mode */
+        switch (c & MFP_LPM_STATE_MASK) {
+        case MFP_LPM_DRIVE_HIGH:
+                PGSR(bank) |= mask;
+                dir = MFP_DIR_OUT;
+                break;
+        case MFP_LPM_DRIVE_LOW:
+                PGSR(bank) &= ~mask;
+                dir = MFP_DIR_OUT;
+                break;
+        case MFP_LPM_DEFAULT:
+                break;
+        default:
+                /* warning and fall through, treat as MFP_LPM_DEFAULT */
+                pr_warning("%s: GPIO%d: unsupported low power mode\n",
+                                __func__, gpio);
+                break;
+        }
+
+        if (dir == MFP_DIR_OUT)
+                gpdr_lpm[bank] |= mask;
+        else
+                gpdr_lpm[bank] &= ~mask;
 
         /* give early warning if MFP_LPM_CAN_WAKEUP is set on the
          * configurations of those pins not able to wakeup
@@ -91,7 +106,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
                 return -EINVAL;
         }
 
-        if ((c & MFP_LPM_CAN_WAKEUP) && (c & MFP_DIR_OUT)) {
+        if ((c & MFP_LPM_CAN_WAKEUP) && (dir == MFP_DIR_OUT)) {
                 pr_warning("%s: output GPIO%d unable to wakeup\n",
                                 __func__, gpio);
                 return -EINVAL;
@@ -135,7 +150,7 @@ void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
 
 void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
 {
-        unsigned long flags;
+        unsigned long flags, c;
         int gpio;
 
         gpio = __mfp_validate(mfp);
@@ -143,7 +158,11 @@ void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
                 return;
 
         local_irq_save(flags);
-        __mfp_config_lpm(gpio, lpm);
+
+        c = gpio_desc[gpio].config;
+        c = (c & ~MFP_LPM_STATE_MASK) | lpm;
+        __mfp_config_gpio(gpio, c);
+
         local_irq_restore(flags);
 }
 
@@ -187,23 +206,22 @@ int gpio_set_wake(unsigned int gpio, unsigned int on)
 }
 
 #ifdef CONFIG_PXA25x
-static int __init pxa25x_mfp_init(void)
+static void __init pxa25x_mfp_init(void)
 {
         int i;
 
-        if (cpu_is_pxa25x()) {
-                for (i = 0; i <= 84; i++)
-                        gpio_desc[i].valid = 1;
+        for (i = 0; i <= 84; i++)
+                gpio_desc[i].valid = 1;
 
-                for (i = 0; i <= 15; i++) {
-                        gpio_desc[i].can_wakeup = 1;
-                        gpio_desc[i].mask = GPIO_bit(i);
-                }
+        for (i = 0; i <= 15; i++) {
+                gpio_desc[i].can_wakeup = 1;
+                gpio_desc[i].mask = GPIO_bit(i);
         }
 
-        return 0;
+        gpio_nr = 85;
 }
-postcore_initcall(pxa25x_mfp_init);
+#else
+static inline void pxa25x_mfp_init(void) {}
 #endif /* CONFIG_PXA25x */
 
 #ifdef CONFIG_PXA27x
@@ -233,45 +251,106 @@ int keypad_set_wake(unsigned int on)
         return 0;
 }
 
-static int __init pxa27x_mfp_init(void)
+static void __init pxa27x_mfp_init(void)
 {
         int i, gpio;
 
-        if (cpu_is_pxa27x()) {
-                for (i = 0; i <= 120; i++) {
-                        /* skip GPIO2, 5, 6, 7, 8, they are not
-                         * valid pins allow configuration
-                         */
-                        if (i == 2 || i == 5 || i == 6 ||
-                            i == 7 || i == 8)
-                                continue;
+        for (i = 0; i <= 120; i++) {
+                /* skip GPIO2, 5, 6, 7, 8, they are not
+                 * valid pins allow configuration
+                 */
+                if (i == 2 || i == 5 || i == 6 || i == 7 || i == 8)
+                        continue;
 
-                        gpio_desc[i].valid = 1;
-                }
+                gpio_desc[i].valid = 1;
+        }
 
-                /* Keypad GPIOs */
-                for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
-                        gpio = pxa27x_pkwr_gpio[i];
-                        gpio_desc[gpio].can_wakeup = 1;
-                        gpio_desc[gpio].keypad_gpio = 1;
-                        gpio_desc[gpio].mask = 1 << i;
-                }
+        /* Keypad GPIOs */
+        for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
+                gpio = pxa27x_pkwr_gpio[i];
+                gpio_desc[gpio].can_wakeup = 1;
+                gpio_desc[gpio].keypad_gpio = 1;
+                gpio_desc[gpio].mask = 1 << i;
+        }
 
-                /* Overwrite GPIO13 as a PWER wakeup source */
-                for (i = 0; i <= 15; i++) {
-                        /* skip GPIO2, 5, 6, 7, 8 */
-                        if (GPIO_bit(i) & 0x1e4)
-                                continue;
+        /* Overwrite GPIO13 as a PWER wakeup source */
+        for (i = 0; i <= 15; i++) {
+                /* skip GPIO2, 5, 6, 7, 8 */
+                if (GPIO_bit(i) & 0x1e4)
+                        continue;
 
-                        gpio_desc[i].can_wakeup = 1;
-                        gpio_desc[i].mask = GPIO_bit(i);
-                }
+                gpio_desc[i].can_wakeup = 1;
+                gpio_desc[i].mask = GPIO_bit(i);
+        }
+
+        gpio_desc[35].can_wakeup = 1;
+        gpio_desc[35].mask = PWER_WE35;
+
+        gpio_nr = 121;
+}
+#else
+static inline void pxa27x_mfp_init(void) {}
+#endif /* CONFIG_PXA27x */
+
+#ifdef CONFIG_PM
+static unsigned long saved_gafr[2][4];
+static unsigned long saved_gpdr[4];
 
-                gpio_desc[35].can_wakeup = 1;
-                gpio_desc[35].mask = PWER_WE35;
+static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state)
+{
+        int i;
+
+        for (i = 0; i <= gpio_to_bank(gpio_nr); i++) {
+
+                saved_gafr[0][i] = GAFR_L(i);
+                saved_gafr[1][i] = GAFR_U(i);
+                saved_gpdr[i] = GPDR(i * 32);
+
+                GPDR(i * 32) = gpdr_lpm[i];
         }
+        return 0;
+}
 
+static int pxa2xx_mfp_resume(struct sys_device *d)
+{
+        int i;
+
+        for (i = 0; i <= gpio_to_bank(gpio_nr); i++) {
+                GAFR_L(i) = saved_gafr[0][i];
+                GAFR_U(i) = saved_gafr[1][i];
+                GPDR(i * 32) = saved_gpdr[i];
+        }
+        PSSR = PSSR_RDH | PSSR_PH;
         return 0;
 }
-postcore_initcall(pxa27x_mfp_init);
-#endif /* CONFIG_PXA27x */
+#else
+#define pxa2xx_mfp_suspend      NULL
+#define pxa2xx_mfp_resume       NULL
+#endif
+
+struct sysdev_class pxa2xx_mfp_sysclass = {
+        .name           = "mfp",
+        .suspend        = pxa2xx_mfp_suspend,
+        .resume         = pxa2xx_mfp_resume,
+};
+
+static int __init pxa2xx_mfp_init(void)
+{
+        int i;
+
+        if (!cpu_is_pxa2xx())
+                return 0;
+
+        if (cpu_is_pxa25x())
+                pxa25x_mfp_init();
+
+        if (cpu_is_pxa27x())
+                pxa27x_mfp_init();
+
+        /* initialize gafr_run[], pgsr_lpm[] from existing values */
+        for (i = 0; i <= gpio_to_bank(gpio_nr); i++)
+                gpdr_lpm[i] = GPDR(i * 32);
+
+        return sysdev_class_register(&pxa2xx_mfp_sysclass);
+}
+postcore_initcall(pxa2xx_mfp_init);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
new file mode 100644
index 000000000000..0842c531ee4d
--- /dev/null
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -0,0 +1,905 @@
+/*
+ * Handles the Mitac Mio A701 Board
+ *
+ * Copyright (C) 2008 Robert Jarzmik
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/gpio_keys.h>
+#include <linux/pwm_backlight.h>
+#include <linux/rtc.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/pda_power.h>
+#include <linux/power_supply.h>
+#include <linux/wm97xx.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/pxafb.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mmc.h>
+#include <mach/udc.h>
+#include <mach/pxa27x-udc.h>
+
+#include <mach/mioa701.h>
+
+#include "generic.h"
+#include "devices.h"
+
+static unsigned long mioa701_pin_config[] = {
+        /* Mio global */
+        MIO_CFG_OUT(GPIO9_CHARGE_nEN, AF0, DRIVE_LOW),
+        MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW),
+        MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH),
+        MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH),
+
+        /* Backlight PWM 0 */
+        GPIO16_PWM0_OUT,
+
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        MIO_CFG_IN(GPIO78_SDIO_RO, AF0),
+        MIO_CFG_IN(GPIO15_SDIO_INSERT, AF0),
+        MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW),
+
+        /* USB */
+        MIO_CFG_IN(GPIO13_USB_DETECT, AF0),
+        MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW),
+
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+
+        /* Bluetooth */
+        GPIO44_BTUART_CTS,
+        GPIO42_BTUART_RXD,
+        GPIO45_BTUART_RTS,
+        GPIO43_BTUART_TXD,
+        MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW),
+
+        /* GPS */
+        MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW),
+        MIO_CFG_OUT(GPIO26_GPS_ON, AF0, DRIVE_LOW),
+        MIO_CFG_OUT(GPIO27_GPS_RESET, AF0, DRIVE_LOW),
+        MIO_CFG_OUT(GPIO106_GPS_UNKNOWN2, AF0, DRIVE_LOW),
+        MIO_CFG_OUT(GPIO107_GPS_UNKNOWN3, AF0, DRIVE_LOW),
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+
+        /* GSM */
+        MIO_CFG_OUT(GPIO24_GSM_MOD_RESET_CMD, AF0, DRIVE_LOW),
+        MIO_CFG_OUT(GPIO88_GSM_nMOD_ON_CMD, AF0, DRIVE_HIGH),
+        MIO_CFG_OUT(GPIO90_GSM_nMOD_OFF_CMD, AF0, DRIVE_HIGH),
+        MIO_CFG_OUT(GPIO114_GSM_nMOD_DTE_UART_STATE, AF0, DRIVE_HIGH),
+        MIO_CFG_IN(GPIO25_GSM_MOD_ON_STATE, AF0),
+        MIO_CFG_IN(GPIO113_GSM_EVENT, AF0) | WAKEUP_ON_EDGE_BOTH,
+        GPIO34_FFUART_RXD,
+        GPIO35_FFUART_CTS,
+        GPIO36_FFUART_DCD,
+        GPIO37_FFUART_DSR,
+        GPIO39_FFUART_TXD,
+        GPIO40_FFUART_DTR,
+        GPIO41_FFUART_RTS,
+
+        /* Sound */
+        GPIO89_AC97_SYSCLK,
+        MIO_CFG_IN(GPIO12_HPJACK_INSERT, AF0),
+
+        /* Leds */
+        MIO_CFG_OUT(GPIO10_LED_nCharging, AF0, DRIVE_HIGH),
+        MIO_CFG_OUT(GPIO97_LED_nBlue, AF0, DRIVE_HIGH),
+        MIO_CFG_OUT(GPIO98_LED_nOrange, AF0, DRIVE_HIGH),
+        MIO_CFG_OUT(GPIO82_LED_nVibra, AF0, DRIVE_HIGH),
+        MIO_CFG_OUT(GPIO115_LED_nKeyboard, AF0, DRIVE_HIGH),
+
+        /* Keyboard */
+        MIO_CFG_IN(GPIO0_KEY_POWER, AF0) | WAKEUP_ON_EDGE_BOTH,
+        MIO_CFG_IN(GPIO93_KEY_VOLUME_UP, AF0),
+        MIO_CFG_IN(GPIO94_KEY_VOLUME_DOWN, AF0),
+        GPIO100_KP_MKIN_0,
+        GPIO101_KP_MKIN_1,
+        GPIO102_KP_MKIN_2,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+
+        /* Unknown */
+        MFP_CFG_IN(GPIO14, AF0),
+        MFP_CFG_IN(GPIO20, AF0),
+        MFP_CFG_IN(GPIO21, AF0),
+        MFP_CFG_IN(GPIO33, AF0),
+        MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH),
+        MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH),
+        MFP_CFG_OUT(GPIO77, AF0, DRIVE_HIGH),
+        MFP_CFG_IN(GPIO80, AF0),
+        MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH),
+        MFP_CFG_IN(GPIO96, AF0),
+        MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH),
+};
+
+#define MIO_GPIO_IN(num, _desc) \
+        { .gpio = (num), .dir = 0, .desc = (_desc) }
+#define MIO_GPIO_OUT(num, _init, _desc) \
+        { .gpio = (num), .dir = 1, .init = (_init), .desc = (_desc) }
+struct gpio_ress {
+        unsigned gpio : 8;
+        unsigned dir : 1;
+        unsigned init : 1;
+        char *desc;
+};
+
+static int mio_gpio_request(struct gpio_ress *gpios, int size)
+{
+        int i, rc = 0;
+        int gpio;
+        int dir;
+
+        for (i = 0; (!rc) && (i < size); i++) {
+                gpio = gpios[i].gpio;
+                dir = gpios[i].dir;
+                rc = gpio_request(gpio, gpios[i].desc);
+                if (rc) {
+                        printk(KERN_ERR "Error requesting GPIO %d(%s) : %d\n",
+                               gpio, gpios[i].desc, rc);
+                        continue;
+                }
+                if (dir)
+                        gpio_direction_output(gpio, gpios[i].init);
+                else
+                        gpio_direction_input(gpio);
+        }
+        while ((rc) && (--i >= 0))
+                gpio_free(gpios[i].gpio);
+        return rc;
+}
+
+static void mio_gpio_free(struct gpio_ress *gpios, int size)
+{
+        int i;
+
+        for (i = 0; i < size; i++)
+                gpio_free(gpios[i].gpio);
+}
+
+/* LCD Screen and Backlight */
+static struct platform_pwm_backlight_data mioa701_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 100,
+        .dft_brightness = 50,
+        .pwm_period_ns  = 4000 * 1024,  /* Fl = 250kHz */
+};
+
+/*
+ * LTM0305A776C LCD panel timings
+ *
+ * see:
+ *  - the LTM0305A776C datasheet,
+ *  - and the PXA27x Programmers' manual
+ */
+static struct pxafb_mode_info mioa701_ltm0305a776c = {
+        .pixclock               = 220000,       /* CLK=4.545 MHz */
+        .xres                   = 240,
+        .yres                   = 320,
+        .bpp                    = 16,
+        .hsync_len              = 4,
+        .vsync_len              = 2,
+        .left_margin            = 6,
+        .right_margin           = 4,
+        .upper_margin           = 5,
+        .lower_margin           = 3,
+};
+
+static void mioa701_lcd_power(int on, struct fb_var_screeninfo *si)
+{
+        gpio_set_value(GPIO87_LCD_POWER, on);
+}
+
+static struct pxafb_mach_info mioa701_pxafb_info = {
+        .modes                  = &mioa701_ltm0305a776c,
+        .num_modes              = 1,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+        .pxafb_lcd_power        = mioa701_lcd_power,
+};
+
+/*
+ * Keyboard configuration
+ */
+static unsigned int mioa701_matrix_keys[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(0, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_MEDIA),
+        KEY(1, 0, KEY_DOWN),
+        KEY(1, 1, KEY_ENTER),
+        KEY(1, 2, KEY_CONNECT), /* GPS key */
+        KEY(2, 0, KEY_LEFT),
+        KEY(2, 1, KEY_PHONE),   /* Phone Green key */
+        KEY(2, 2, KEY_CAMERA)   /* Camera key */
+};
+static struct pxa27x_keypad_platform_data mioa701_keypad_info = {
+        .matrix_key_rows = 3,
+        .matrix_key_cols = 3,
+        .matrix_key_map = mioa701_matrix_keys,
+        .matrix_key_map_size = ARRAY_SIZE(mioa701_matrix_keys),
+};
+
+/*
+ * GPIO Key Configuration
+ */
+#define MIO_KEY(key, _gpio, _desc, _wakeup) \
+        { .code = (key), .gpio = (_gpio), .active_low = 0, \
+        .desc = (_desc), .type = EV_KEY, .wakeup = (_wakeup) }
+static struct gpio_keys_button mioa701_button_table[] = {
+        MIO_KEY(KEY_EXIT, GPIO0_KEY_POWER, "Power button", 1),
+        MIO_KEY(KEY_VOLUMEUP, GPIO93_KEY_VOLUME_UP, "Volume up", 0),
+        MIO_KEY(KEY_VOLUMEDOWN, GPIO94_KEY_VOLUME_DOWN, "Volume down", 0),
+        MIO_KEY(KEY_HP, GPIO12_HPJACK_INSERT, "HP jack detect", 0)
+};
+
+static struct gpio_keys_platform_data mioa701_gpio_keys_data = {
+        .buttons  = mioa701_button_table,
+        .nbuttons = ARRAY_SIZE(mioa701_button_table),
+};
+
+/*
+ * Leds and vibrator
+ */
+#define ONE_LED(_gpio, _name) \
+{ .gpio = (_gpio), .name = (_name), .active_low = true }
+static struct gpio_led gpio_leds[] = {
+        ONE_LED(GPIO10_LED_nCharging, "mioa701:charging"),
+        ONE_LED(GPIO97_LED_nBlue, "mioa701:blue"),
+        ONE_LED(GPIO98_LED_nOrange, "mioa701:orange"),
+        ONE_LED(GPIO82_LED_nVibra, "mioa701:vibra"),
+        ONE_LED(GPIO115_LED_nKeyboard, "mioa701:keyboard")
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds = gpio_leds,
+        .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+/*
+ * GSM Sagem XS200 chip
+ *
+ * GSM handling was purged from kernel. For history, this is the way to go :
+ *   - init : GPIO24_GSM_MOD_RESET_CMD = 0, GPIO114_GSM_nMOD_DTE_UART_STATE = 1
+ *            GPIO88_GSM_nMOD_ON_CMD = 1, GPIO90_GSM_nMOD_OFF_CMD = 1
+ *   - reset : GPIO24_GSM_MOD_RESET_CMD = 1, msleep(100),
+ *             GPIO24_GSM_MOD_RESET_CMD = 0
+ *   - turn on  : GPIO88_GSM_nMOD_ON_CMD = 0, msleep(1000),
+ *                GPIO88_GSM_nMOD_ON_CMD = 1
+ *   - turn off : GPIO90_GSM_nMOD_OFF_CMD = 0, msleep(1000),
+ *                GPIO90_GSM_nMOD_OFF_CMD = 1
+ */
+static int is_gsm_on(void)
+{
+        int is_on;
+
+        is_on = !!gpio_get_value(GPIO25_GSM_MOD_ON_STATE);
+        return is_on;
+}
+
+irqreturn_t gsm_on_irq(int irq, void *p)
+{
+        printk(KERN_DEBUG "Mioa701: GSM status changed to %s\n",
+               is_gsm_on() ? "on" : "off");
+        return IRQ_HANDLED;
+}
+
+struct gpio_ress gsm_gpios[] = {
+        MIO_GPIO_IN(GPIO25_GSM_MOD_ON_STATE, "GSM state"),
+        MIO_GPIO_IN(GPIO113_GSM_EVENT, "GSM event"),
+};
+
+static int __init gsm_init(void)
+{
+        int rc;
+
+        rc = mio_gpio_request(ARRAY_AND_SIZE(gsm_gpios));
+        if (rc)
+                goto err_gpio;
+        rc = request_irq(gpio_to_irq(GPIO25_GSM_MOD_ON_STATE), gsm_on_irq,
+                         IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                         "GSM XS200 Power Irq", NULL);
+        if (rc)
+                goto err_irq;
+
+        gpio_set_wake(GPIO113_GSM_EVENT, 1);
+        return 0;
+
+err_irq:
+        printk(KERN_ERR "Mioa701: Can't request GSM_ON irq\n");
+        mio_gpio_free(ARRAY_AND_SIZE(gsm_gpios));
+err_gpio:
+        printk(KERN_ERR "Mioa701: gsm not available\n");
+        return rc;
+}
+
+static void gsm_exit(void)
+{
+        free_irq(gpio_to_irq(GPIO25_GSM_MOD_ON_STATE), NULL);
+        mio_gpio_free(ARRAY_AND_SIZE(gsm_gpios));
+}
+
+/*
+ * Bluetooth BRF6150 chip
+ *
+ * BT handling was purged from kernel. For history, this is the way to go :
+ * - turn on  : GPIO83_BT_ON = 1
+ * - turn off : GPIO83_BT_ON = 0
+ */
+
+/*
+ * GPS Sirf Star III chip
+ *
+ * GPS handling was purged from kernel. For history, this is the way to go :
+ * - init : GPIO23_GPS_UNKNOWN1 = 1, GPIO26_GPS_ON = 0, GPIO27_GPS_RESET = 0
+ *          GPIO106_GPS_UNKNOWN2 = 0, GPIO107_GPS_UNKNOWN3 = 0
+ * - turn on  : GPIO27_GPS_RESET = 1, GPIO26_GPS_ON = 1
+ * - turn off : GPIO26_GPS_ON = 0, GPIO27_GPS_RESET = 0
+ */
+
+/*
+ * USB UDC
+ */
+static void udc_power_command(int cmd)
+{
+        switch (cmd) {
+        case PXA2XX_UDC_CMD_DISCONNECT:
+                gpio_set_value(GPIO22_USB_ENABLE, 0);
+                break;
+        case PXA2XX_UDC_CMD_CONNECT:
+                gpio_set_value(GPIO22_USB_ENABLE, 1);
+                break;
+        default:
+                printk(KERN_INFO "udc_control: unknown command (0x%x)!\n", cmd);
+                break;
+        }
+}
+
+static int is_usb_connected(void)
+{
+        return !!gpio_get_value(GPIO13_USB_DETECT);
+}
+
+static struct pxa2xx_udc_mach_info mioa701_udc_info = {
+        .udc_is_connected = is_usb_connected,
+        .udc_command      = udc_power_command,
+};
+
+struct gpio_ress udc_gpios[] = {
+        MIO_GPIO_OUT(GPIO22_USB_ENABLE, 0, "USB Vbus enable")
+};
+
+static int __init udc_init(void)
+{
+        pxa_set_udc_info(&mioa701_udc_info);
+        return mio_gpio_request(ARRAY_AND_SIZE(udc_gpios));
+}
+
+static void udc_exit(void)
+{
+        mio_gpio_free(ARRAY_AND_SIZE(udc_gpios));
+}
+
+/*
+ * SDIO/MMC Card controller
+ */
+static void mci_setpower(struct device *dev, unsigned int vdd)
+{
+        struct pxamci_platform_data *p_d = dev->platform_data;
+
+        if ((1 << vdd) & p_d->ocr_mask)
+                gpio_set_value(GPIO91_SDIO_EN, 1);      /* enable SDIO power */
+        else
+                gpio_set_value(GPIO91_SDIO_EN, 0);      /* disable SDIO power */
+}
+
+static int mci_get_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO78_SDIO_RO);
+}
+
+struct gpio_ress mci_gpios[] = {
+        MIO_GPIO_IN(GPIO78_SDIO_RO,     "SDIO readonly detect"),
+        MIO_GPIO_IN(GPIO15_SDIO_INSERT, "SDIO insertion detect"),
+        MIO_GPIO_OUT(GPIO91_SDIO_EN, 0, "SDIO power enable")
+};
+
+static void mci_exit(struct device *dev, void *data)
+{
+        mio_gpio_free(ARRAY_AND_SIZE(mci_gpios));
+        free_irq(gpio_to_irq(GPIO15_SDIO_INSERT), data);
+}
+
+static struct pxamci_platform_data mioa701_mci_info;
+
+/**
+ * The card detect interrupt isn't debounced so we delay it by 250ms
+ * to give the card a chance to fully insert/eject.
+ */
+static int mci_init(struct device *dev, irq_handler_t detect_int, void *data)
+{
+        int rc;
+        int irq = gpio_to_irq(GPIO15_SDIO_INSERT);
+
+        rc = mio_gpio_request(ARRAY_AND_SIZE(mci_gpios));
+        if (rc)
+                goto err_gpio;
+        /* enable RE/FE interrupt on card insertion and removal */
+        rc = request_irq(irq, detect_int,
+                         IRQF_DISABLED | IRQF_TRIGGER_RISING |
+                         IRQF_TRIGGER_FALLING,
+                         "MMC card detect", data);
+        if (rc)
+                goto err_irq;
+
+        mioa701_mci_info.detect_delay = msecs_to_jiffies(250);
+        return 0;
+
+err_irq:
+        dev_err(dev, "mioa701_mci_init: MMC/SD:"
+                " can't request MMC card detect IRQ\n");
+        mio_gpio_free(ARRAY_AND_SIZE(mci_gpios));
+err_gpio:
+        return rc;
+}
+
+static struct pxamci_platform_data mioa701_mci_info = {
+        .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .init     = mci_init,
+        .get_ro   = mci_get_ro,
+        .setpower = mci_setpower,
+        .exit     = mci_exit,
+};
+
+/* FlashRAM */
+static struct resource strataflash_resource = {
+        .start = PXA_CS0_PHYS,
+        .end   = PXA_CS0_PHYS + SZ_64M - 1,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct physmap_flash_data strataflash_data = {
+        .width = 2,
+        /* .set_vpp = mioa701_set_vpp, */
+};
+
+static struct platform_device strataflash = {
+        .name          = "physmap-flash",
+        .id            = -1,
+        .resource      = &strataflash_resource,
+        .num_resources = 1,
+        .dev = {
+                .platform_data = &strataflash_data,
+        },
+};
+
+/*
+ * Suspend/Resume bootstrap management
+ *
+ * MIO A701 reboot sequence is highly ROM dependant. From the one dissassembled,
+ * this sequence is as follows :
+ *   - disables interrupts
+ *   - initialize SDRAM (self refresh RAM into active RAM)
+ *   - initialize GPIOs (depends on value at 0xa020b020)
+ *   - initialize coprossessors
+ *   - if edge detect on PWR_SCL(GPIO3), then proceed to cold start
+ *   - or if value at 0xa020b000 not equal to 0x0f0f0f0f, proceed to cold start
+ *   - else do a resume, ie. jump to addr 0xa0100000
+ */
+#define RESUME_ENABLE_ADDR      0xa020b000
+#define RESUME_ENABLE_VAL       0x0f0f0f0f
+#define RESUME_BT_ADDR          0xa020b020
+#define RESUME_UNKNOWN_ADDR     0xa020b024
+#define RESUME_VECTOR_ADDR      0xa0100000
+#define BOOTSTRAP_WORDS         mioa701_bootstrap_lg/4
+
+static u32 *save_buffer;
+
+static void install_bootstrap(void)
+{
+        int i;
+        u32 *rom_bootstrap  = phys_to_virt(RESUME_VECTOR_ADDR);
+        u32 *src = &mioa701_bootstrap;
+
+        for (i = 0; i < BOOTSTRAP_WORDS; i++)
+                rom_bootstrap[i] = src[i];
+}
+
+
+static int mioa701_sys_suspend(struct sys_device *sysdev, pm_message_t state)
+{
+        int i = 0, is_bt_on;
+        u32 *mem_resume_vector  = phys_to_virt(RESUME_VECTOR_ADDR);
+        u32 *mem_resume_enabler = phys_to_virt(RESUME_ENABLE_ADDR);
+        u32 *mem_resume_bt      = phys_to_virt(RESUME_BT_ADDR);
+        u32 *mem_resume_unknown = phys_to_virt(RESUME_UNKNOWN_ADDR);
+
+        /* Devices prepare suspend */
+        is_bt_on = gpio_get_value(GPIO83_BT_ON);
+        pxa2xx_mfp_set_lpm(GPIO83_BT_ON,
+                           is_bt_on ? MFP_LPM_DRIVE_HIGH : MFP_LPM_DRIVE_LOW);
+
+        for (i = 0; i < BOOTSTRAP_WORDS; i++)
+                save_buffer[i] = mem_resume_vector[i];
+        save_buffer[i++] = *mem_resume_enabler;
+        save_buffer[i++] = *mem_resume_bt;
+        save_buffer[i++] = *mem_resume_unknown;
+
+        *mem_resume_enabler = RESUME_ENABLE_VAL;
+        *mem_resume_bt      = is_bt_on;
+
+        install_bootstrap();
+        return 0;
+}
+
+static int mioa701_sys_resume(struct sys_device *sysdev)
+{
+        int i = 0;
+        u32 *mem_resume_vector  = phys_to_virt(RESUME_VECTOR_ADDR);
+        u32 *mem_resume_enabler = phys_to_virt(RESUME_ENABLE_ADDR);
+        u32 *mem_resume_bt      = phys_to_virt(RESUME_BT_ADDR);
+        u32 *mem_resume_unknown = phys_to_virt(RESUME_UNKNOWN_ADDR);
+
+        for (i = 0; i < BOOTSTRAP_WORDS; i++)
+                mem_resume_vector[i] = save_buffer[i];
+        *mem_resume_enabler = save_buffer[i++];
+        *mem_resume_bt      = save_buffer[i++];
+        *mem_resume_unknown = save_buffer[i++];
+
+        return 0;
+}
+
+static struct sysdev_class mioa701_sysclass = {
+        .name = "mioa701",
+};
+
+static struct sys_device sysdev_bootstrap = {
+        .cls            = &mioa701_sysclass,
+};
+
+static struct sysdev_driver driver_bootstrap = {
+        .suspend        = &mioa701_sys_suspend,
+        .resume         = &mioa701_sys_resume,
+};
+
+static int __init bootstrap_init(void)
+{
+        int rc;
+        int save_size = mioa701_bootstrap_lg + (sizeof(u32) * 3);
+
+        rc = sysdev_class_register(&mioa701_sysclass);
+        if (rc) {
+                printk(KERN_ERR "Failed registering mioa701 sys class\n");
+                return -ENODEV;
+        }
+        rc = sysdev_register(&sysdev_bootstrap);
+        if (rc) {
+                printk(KERN_ERR "Failed registering mioa701 sys device\n");
+                return -ENODEV;
+        }
+        rc = sysdev_driver_register(&mioa701_sysclass, &driver_bootstrap);
+        if (rc) {
+                printk(KERN_ERR "Failed registering PMU sys driver\n");
+                return -ENODEV;
+        }
+
+        save_buffer = kmalloc(save_size, GFP_KERNEL);
+        if (!save_buffer)
+                return -ENOMEM;
+        printk(KERN_INFO "MioA701: allocated %d bytes for bootstrap\n",
+               save_size);
+        return 0;
+}
+
+static void bootstrap_exit(void)
+{
+        kfree(save_buffer);
+        sysdev_driver_unregister(&mioa701_sysclass, &driver_bootstrap);
+        sysdev_unregister(&sysdev_bootstrap);
+        sysdev_class_unregister(&mioa701_sysclass);
+
+        printk(KERN_CRIT "Unregistering mioa701 suspend will hang next"
+               "resume !!!\n");
+}
+
+/*
+ * Power Supply
+ */
+static char *supplicants[] = {
+        "mioa701_battery"
+};
+
+static void mioa701_set_charge(int flags)
+{
+        gpio_set_value(GPIO9_CHARGE_nEN, !flags);
+}
+
+static struct pda_power_pdata power_pdata = {
+        .is_ac_online   = is_usb_connected,
+        .set_charge = mioa701_set_charge,
+        .supplied_to = supplicants,
+        .num_supplicants = ARRAY_SIZE(supplicants),
+};
+
+static struct resource power_resources[] = {
+        [0] = {
+                .name   = "ac",
+                .start  = gpio_to_irq(GPIO13_USB_DETECT),
+                .end    = gpio_to_irq(GPIO13_USB_DETECT),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
+                IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+
+static struct platform_device power_dev = {
+        .name           = "pda-power",
+        .id             = -1,
+        .resource       = power_resources,
+        .num_resources  = ARRAY_SIZE(power_resources),
+        .dev = {
+                .platform_data  = &power_pdata,
+        },
+};
+
+#if defined(CONFIG_PDA_POWER) && defined(CONFIG_TOUCHSCREEN_WM97XX)
+static struct wm97xx *battery_wm;
+
+static enum power_supply_property battery_props[] = {
+        POWER_SUPPLY_PROP_STATUS,
+        POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+        POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+        POWER_SUPPLY_PROP_VOLTAGE_NOW,
+        POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,   /* Necessary for apm */
+};
+
+static int get_battery_voltage(void)
+{
+        int adc = -1;
+
+        if (battery_wm)
+                adc = wm97xx_read_aux_adc(battery_wm, WM97XX_AUX_ID1);
+        return adc;
+}
+
+static int get_battery_status(struct power_supply *b)
+{
+        int status;
+
+        if (is_usb_connected())
+                status = POWER_SUPPLY_STATUS_CHARGING;
+        else
+                status = POWER_SUPPLY_STATUS_DISCHARGING;
+
+        return status;
+}
+
+static int get_property(struct power_supply *b,
+                        enum power_supply_property psp,
+                        union power_supply_propval *val)
+{
+        int rc = 0;
+
+        switch (psp) {
+        case POWER_SUPPLY_PROP_STATUS:
+                val->intval = get_battery_status(b);
+                break;
+        case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+                val->intval = 0xfd0;
+                break;
+        case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+                val->intval = 0xc00;
+                break;
+        case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+                val->intval = get_battery_voltage();
+                break;
+        case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
+                val->intval = 100;
+                break;
+        default:
+                val->intval = -1;
+                rc = -1;
+        }
+
+        return rc;
+};
+
+static struct power_supply battery_ps = {
+        .name = "mioa701_battery",
+        .type = POWER_SUPPLY_TYPE_BATTERY,
+        .get_property = get_property,
+        .properties = battery_props,
+        .num_properties = ARRAY_SIZE(battery_props),
+};
+
+static int battery_probe(struct platform_device *pdev)
+{
+        struct wm97xx *wm = platform_get_drvdata(pdev);
+        int rc;
+
+        battery_wm = wm;
+
+        rc = power_supply_register(NULL, &battery_ps);
+        if (rc)
+                dev_err(&pdev->dev,
+                "Could not register mioa701 battery -> %d\n", rc);
+        return rc;
+}
+
+static int battery_remove(struct platform_device *pdev)
+{
+        battery_wm = NULL;
+        return 0;
+}
+
+static struct platform_driver mioa701_battery_driver = {
+        .driver = {
+                .name = "wm97xx-battery",
+        },
+        .probe = battery_probe,
+        .remove = battery_remove
+};
+
+static int __init mioa701_battery_init(void)
+{
+        int rc;
+
+        rc = platform_driver_register(&mioa701_battery_driver);
+        if (rc)
+                printk(KERN_ERR "Could not register mioa701 battery driver\n");
+        return rc;
+}
+
+#else
+static int __init mioa701_battery_init(void)
+{
+        return 0;
+}
+#endif
+
+/*
+ * Mio global
+ */
+
+/* Devices */
+#define MIO_PARENT_DEV(var, strname, tparent, pdata)    \
+static struct platform_device var = {                   \
+        .name           = strname,                      \
+        .id             = -1,                           \
+        .dev            = {                             \
+                .platform_data = pdata,                 \
+                .parent = tparent,                      \
+        },                                              \
+};
+#define MIO_SIMPLE_DEV(var, strname, pdata)     \
+        MIO_PARENT_DEV(var, strname, NULL, pdata)
+
+MIO_SIMPLE_DEV(mioa701_gpio_keys, "gpio-keys",      &mioa701_gpio_keys_data)
+MIO_PARENT_DEV(mioa701_backlight, "pwm-backlight",  &pxa27x_device_pwm0.dev,
+                &mioa701_backlight_data);
+MIO_SIMPLE_DEV(mioa701_led,       "leds-gpio",      &gpio_led_info)
+MIO_SIMPLE_DEV(pxa2xx_pcm,        "pxa2xx-pcm",     NULL)
+MIO_SIMPLE_DEV(pxa2xx_ac97,       "pxa2xx-ac97",    NULL)
+MIO_PARENT_DEV(mio_wm9713_codec,  "wm9713-codec",   &pxa2xx_ac97.dev, NULL)
+MIO_SIMPLE_DEV(mioa701_sound,     "mioa701-wm9713", NULL)
+MIO_SIMPLE_DEV(mioa701_board,     "mioa701-board",  NULL)
+
+static struct platform_device *devices[] __initdata = {
+        &mioa701_gpio_keys,
+        &mioa701_backlight,
+        &mioa701_led,
+        &pxa2xx_pcm,
+        &pxa2xx_ac97,
+        &mio_wm9713_codec,
+        &mioa701_sound,
+        &power_dev,
+        &strataflash,
+        &mioa701_board
+};
+
+static void mioa701_machine_exit(void);
+
+static void mioa701_poweroff(void)
+{
+        mioa701_machine_exit();
+        gpio_set_value(GPIO18_POWEROFF, 1);
+}
+
+static void mioa701_restart(char c)
+{
+        mioa701_machine_exit();
+        arm_machine_restart(c);
+}
+
+struct gpio_ress global_gpios[] = {
+        MIO_GPIO_OUT(GPIO9_CHARGE_nEN, 1, "Charger enable"),
+        MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"),
+        MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power")
+};
+
+static void __init mioa701_machine_init(void)
+{
+        PSLR  = 0xff100000; /* SYSDEL=125ms, PWRDEL=125ms, PSLR_SL_ROD=1 */
+        PCFR = PCFR_DC_EN | PCFR_GPR_EN | PCFR_OPDE;
+        RTTR = 32768 - 1; /* Reset crazy WinCE value */
+        UP2OCR = UP2OCR_HXOE;
+
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config));
+        mio_gpio_request(ARRAY_AND_SIZE(global_gpios));
+        bootstrap_init();
+        set_pxa_fb_info(&mioa701_pxafb_info);
+        pxa_set_mci_info(&mioa701_mci_info);
+        pxa_set_keypad_info(&mioa701_keypad_info);
+        udc_init();
+        pm_power_off = mioa701_poweroff;
+        arm_pm_restart = mioa701_restart;
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        gsm_init();
+        mioa701_battery_init();
+}
+
+static void mioa701_machine_exit(void)
+{
+        udc_exit();
+        bootstrap_exit();
+        gsm_exit();
+}
+
+MACHINE_START(MIOA701, "MIO A701")
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = &pxa_map_io,
+        .init_irq       = &pxa27x_init_irq,
+        .init_machine   = mioa701_machine_init,
+        .timer          = &pxa_timer,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/mioa701_bootresume.S b/arch/arm/mach-pxa/mioa701_bootresume.S
new file mode 100644
index 000000000000..a647693d9856
--- /dev/null
+++ b/arch/arm/mach-pxa/mioa701_bootresume.S
@@ -0,0 +1,36 @@
+/* Bootloader to resume MIO A701
+ *
+ * 2007-1-12 Robert Jarzmik
+ *
+ * This code is licenced under the GPLv2.
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Note: Yes, part of the following code is located into the .data section.
+ *       This is to allow jumpaddr to be accessed with a relative load
+ *       while we can't rely on any MMU translation.  We could have put
+ *       sleep_save_sp in the .text section as well, but some setups might
+ *       insist on it to be truly read-only.
+ */
+        .data
+ENTRY(mioa701_bootstrap)
+0:
+        b       1f
+ENTRY(mioa701_jumpaddr)
+        .word   0x40f00008              @ PSPR in no-MMU mode
+1:
+        mov     r0,     #0xa0000000     @ Don't suppose memory access works
+        orr     r0, r0, #0x00200000     @ even if it's supposed to
+        mov     r1, #0
+        str     r1, [r0]                @ Early disable resume for next boot
+        ldr     r0, mioa701_jumpaddr    @ (Murphy's Law)
+        ldr     r0, [r0]
+        mov     pc, r0
+2:
+
+ENTRY(mioa701_bootstrap_lg)
+        .data
+        .word   2b-0b
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
new file mode 100644
index 000000000000..8a73814126b1
--- /dev/null
+++ b/arch/arm/mach-pxa/mp900.c
@@ -0,0 +1,100 @@
+/*
+ *  linux/arch/arm/mach-pxa/mp900.c
+ *
+ *  Support for the NEC MobilePro900/C platform
+ *
+ *  Based on mach-pxa/gumstix.c
+ *
+ *  2007, 2008 Kristoffer Ericson <kristoffer.ericson@gmail.com>
+ *  2007, 2008 Michael Petchkovsky <mkpetch@internode.on.net>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/usb/isp116x.h>
+
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include "generic.h"
+
+static void isp116x_pfm_delay(struct device *dev, int delay)
+{
+
+        /* 400Mhz PXA2 = 2.5ns / instruction */
+
+        int cyc = delay / 10;
+
+        /* 4 Instructions = 4 x 2.5ns = 10ns */
+        __asm__ volatile ("0:\n"
+                "subs %0, %1, #1\n"
+                "bge 0b\n"
+                :"=r" (cyc)
+                :"0"(cyc)
+        );
+}
+
+static struct isp116x_platform_data isp116x_pfm_data = {
+        .remote_wakeup_enable = 1,
+        .delay = isp116x_pfm_delay,
+};
+
+static struct resource isp116x_pfm_resources[] = {
+        [0] =   {
+                .start  = 0x0d000000,
+                .end    = 0x0d000000 + 1,
+                .flags  = IORESOURCE_MEM,
+                },
+        [1] =   {
+                .start  = 0x0d000000 + 4,
+                .end    = 0x0d000000 + 5,
+                .flags  = IORESOURCE_MEM,
+                },
+        [2] =   {
+                .start  = 61,
+                .end    = 61,
+                .flags  = IORESOURCE_IRQ,
+                },
+};
+
+static struct platform_device mp900c_dummy_device = {
+        .name           = "mp900c_dummy",
+        .id             = -1,
+};
+
+static struct platform_device mp900c_usb = {
+        .name           = "isp116x-hcd",
+        .num_resources  = ARRAY_SIZE(isp116x_pfm_resources),
+        .resource       = isp116x_pfm_resources,
+        .dev.platform_data = &isp116x_pfm_data,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &mp900c_dummy_device,
+        &mp900c_usb,
+};
+
+static void __init mp900c_init(void)
+{
+        printk(KERN_INFO "MobilePro 900/C machine init\n");
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+/* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */
+MACHINE_START(NEC_MP900, "MobilePro900/C")
+        .phys_io        = 0x40000000,
+        .boot_params    = 0xa0220100,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .timer          = &pxa_timer,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa25x_init_irq,
+        .init_machine   = mp900c_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index fe924a23debe..4447711c9fc6 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -25,6 +25,8 @@
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
+#include <linux/wm97xx_batt.h>
+#include <linux/power_supply.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -340,6 +342,23 @@ static struct platform_device power_supply = {
 };
 
 /******************************************************************************
+ * WM97xx battery
+ ******************************************************************************/
+static struct wm97xx_batt_info wm97xx_batt_pdata = {
+        .batt_aux       = WM97XX_AUX_ID3,
+        .temp_aux       = WM97XX_AUX_ID2,
+        .charge_gpio    = -1,
+        .max_voltage    = PALMTX_BAT_MAX_VOLTAGE,
+        .min_voltage    = PALMTX_BAT_MIN_VOLTAGE,
+        .batt_mult      = 1000,
+        .batt_div       = 414,
+        .temp_mult      = 1,
+        .temp_div       = 1,
+        .batt_tech      = POWER_SUPPLY_TECHNOLOGY_LIPO,
+        .batt_name      = "main-batt",
+};
+
+/******************************************************************************
  * Framebuffer
  ******************************************************************************/
 static struct pxafb_mode_info palmtx_lcd_modes[] = {
@@ -401,6 +420,7 @@ static void __init palmtx_init(void)
         pxa_set_ac97_info(NULL);
         pxa_set_ficp_info(&palmtx_ficp_platform_data);
         pxa_set_keypad_info(&palmtx_keypad_platform_data);
+        wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
new file mode 100644
index 000000000000..2f730da3bba8
--- /dev/null
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -0,0 +1,554 @@
+/*
+ * Hardware definitions for Palm Zire72
+ *
+ * Authors:
+ *      Vladimir "Farcaller" Pouzanov <farcaller@gmail.com>
+ *      Sergey Lapin <slapin@ossfans.org>
+ *      Alex Osborne <bobofdoom@gmail.com>
+ *      Jan Herman <2hp@seznam.cz>
+ *
+ * Rewrite for mainline:
+ *      Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * (find more info at www.hackndev.com)
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/pda_power.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio.h>
+#include <linux/power_supply.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/audio.h>
+#include <mach/palmz72.h>
+#include <mach/mmc.h>
+#include <mach/pxafb.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/irda.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/udc.h>
+#include <mach/pm.h>
+
+#include "generic.h"
+#include "devices.h"
+
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long palmz72_pin_config[] __initdata = {
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO14_GPIO,    /* SD detect */
+        GPIO115_GPIO,   /* SD RO */
+        GPIO98_GPIO,    /* SD power */
+
+        /* AC97 */
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+
+        /* IrDA */
+        GPIO49_GPIO,    /* ir disable */
+        GPIO46_FICP_RXD,
+        GPIO47_FICP_TXD,
+
+        /* PWM */
+        GPIO16_PWM0_OUT,
+
+        /* USB */
+        GPIO15_GPIO,    /* usb detect */
+        GPIO12_GPIO,    /* usb pullup */
+        GPIO95_GPIO,    /* usb power */
+
+        /* Matrix keypad */
+        GPIO100_KP_MKIN_0       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO97_KP_MKIN_3        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+        GPIO20_GPIO,    /* bl power */
+        GPIO21_GPIO,    /* LCD border switch */
+        GPIO22_GPIO,    /* LCD border color */
+        GPIO96_GPIO,    /* lcd power */
+
+        /* Misc. */
+        GPIO0_GPIO      | WAKEUP_ON_LEVEL_HIGH, /* power detect */
+        GPIO88_GPIO,                            /* green led */
+        GPIO27_GPIO,                            /* WM9712 IRQ */
+};
+
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+static int palmz72_mci_init(struct device *dev,
+                                irq_handler_t palmz72_detect_int, void *data)
+{
+        int err = 0;
+
+        /* Setup an interrupt for detecting card insert/remove events */
+        err = gpio_request(GPIO_NR_PALMZ72_SD_DETECT_N, "SD IRQ");
+        if (err)
+                goto err;
+        err = gpio_direction_input(GPIO_NR_PALMZ72_SD_DETECT_N);
+        if (err)
+                goto err2;
+        err = request_irq(gpio_to_irq(GPIO_NR_PALMZ72_SD_DETECT_N),
+                        palmz72_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
+                        IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+                        "SD/MMC card detect", data);
+        if (err) {
+                printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n",
+                                __func__);
+                goto err2;
+        }
+
+        /* SD_POWER is not actually power, but it is more like chip
+         * select, i.e. it is inverted */
+
+        err = gpio_request(GPIO_NR_PALMZ72_SD_POWER_N, "SD_POWER");
+        if (err)
+                goto err3;
+        err = gpio_direction_output(GPIO_NR_PALMZ72_SD_POWER_N, 0);
+        if (err)
+                goto err4;
+        err = gpio_request(GPIO_NR_PALMZ72_SD_RO, "SD_RO");
+        if (err)
+                goto err4;
+        err = gpio_direction_input(GPIO_NR_PALMZ72_SD_RO);
+        if (err)
+                goto err5;
+
+        printk(KERN_DEBUG "%s: irq registered\n", __func__);
+
+        return 0;
+
+err5:
+        gpio_free(GPIO_NR_PALMZ72_SD_RO);
+err4:
+        gpio_free(GPIO_NR_PALMZ72_SD_POWER_N);
+err3:
+        free_irq(gpio_to_irq(GPIO_NR_PALMZ72_SD_DETECT_N), data);
+err2:
+        gpio_free(GPIO_NR_PALMZ72_SD_DETECT_N);
+err:
+        return err;
+}
+
+static void palmz72_mci_exit(struct device *dev, void *data)
+{
+        gpio_free(GPIO_NR_PALMZ72_SD_POWER_N);
+        free_irq(gpio_to_irq(GPIO_NR_PALMZ72_SD_DETECT_N), data);
+        gpio_free(GPIO_NR_PALMZ72_SD_DETECT_N);
+        gpio_free(GPIO_NR_PALMZ72_SD_RO);
+}
+
+static void palmz72_mci_power(struct device *dev, unsigned int vdd)
+{
+        struct pxamci_platform_data *p_d = dev->platform_data;
+        if (p_d->ocr_mask & (1 << vdd))
+                gpio_set_value(GPIO_NR_PALMZ72_SD_POWER_N, 0);
+        else
+                gpio_set_value(GPIO_NR_PALMZ72_SD_POWER_N, 1);
+}
+
+static int palmz72_mci_ro(struct device *dev)
+{
+        return gpio_get_value(GPIO_NR_PALMZ72_SD_RO);
+}
+
+static struct pxamci_platform_data palmz72_mci_platform_data = {
+        .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .setpower       = palmz72_mci_power,
+        .get_ro         = palmz72_mci_ro,
+        .init           = palmz72_mci_init,
+        .exit           = palmz72_mci_exit,
+};
+
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+static unsigned int palmz72_matrix_keys[] = {
+        KEY(0, 0, KEY_POWER),
+        KEY(0, 1, KEY_F1),
+        KEY(0, 2, KEY_ENTER),
+
+        KEY(1, 0, KEY_F2),
+        KEY(1, 1, KEY_F3),
+        KEY(1, 2, KEY_F4),
+
+        KEY(2, 0, KEY_UP),
+        KEY(2, 2, KEY_DOWN),
+
+        KEY(3, 0, KEY_RIGHT),
+        KEY(3, 2, KEY_LEFT),
+};
+
+static struct pxa27x_keypad_platform_data palmz72_keypad_platform_data = {
+        .matrix_key_rows        = 4,
+        .matrix_key_cols        = 3,
+        .matrix_key_map         = palmz72_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(palmz72_matrix_keys),
+
+        .debounce_interval      = 30,
+};
+
+/******************************************************************************
+ * Backlight
+ ******************************************************************************/
+static int palmz72_backlight_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(GPIO_NR_PALMZ72_BL_POWER, "BL POWER");
+        if (ret)
+                goto err;
+        ret = gpio_direction_output(GPIO_NR_PALMZ72_BL_POWER, 0);
+        if (ret)
+                goto err2;
+        ret = gpio_request(GPIO_NR_PALMZ72_LCD_POWER, "LCD POWER");
+        if (ret)
+                goto err2;
+        ret = gpio_direction_output(GPIO_NR_PALMZ72_LCD_POWER, 0);
+        if (ret)
+                goto err3;
+
+        return 0;
+err3:
+        gpio_free(GPIO_NR_PALMZ72_LCD_POWER);
+err2:
+        gpio_free(GPIO_NR_PALMZ72_BL_POWER);
+err:
+        return ret;
+}
+
+static int palmz72_backlight_notify(int brightness)
+{
+        gpio_set_value(GPIO_NR_PALMZ72_BL_POWER, brightness);
+        gpio_set_value(GPIO_NR_PALMZ72_LCD_POWER, brightness);
+        return brightness;
+}
+
+static void palmz72_backlight_exit(struct device *dev)
+{
+        gpio_free(GPIO_NR_PALMZ72_BL_POWER);
+        gpio_free(GPIO_NR_PALMZ72_LCD_POWER);
+}
+
+static struct platform_pwm_backlight_data palmz72_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = PALMZ72_MAX_INTENSITY,
+        .dft_brightness = PALMZ72_MAX_INTENSITY,
+        .pwm_period_ns  = PALMZ72_PERIOD_NS,
+        .init           = palmz72_backlight_init,
+        .notify         = palmz72_backlight_notify,
+        .exit           = palmz72_backlight_exit,
+};
+
+static struct platform_device palmz72_backlight = {
+        .name   = "pwm-backlight",
+        .dev    = {
+                .parent         = &pxa27x_device_pwm0.dev,
+                .platform_data  = &palmz72_backlight_data,
+        },
+};
+
+/******************************************************************************
+ * IrDA
+ ******************************************************************************/
+static int palmz72_irda_startup(struct device *dev)
+{
+        int err;
+        err = gpio_request(GPIO_NR_PALMZ72_IR_DISABLE, "IR DISABLE");
+        if (err)
+                goto err;
+        err = gpio_direction_output(GPIO_NR_PALMZ72_IR_DISABLE, 1);
+        if (err)
+                gpio_free(GPIO_NR_PALMZ72_IR_DISABLE);
+err:
+        return err;
+}
+
+static void palmz72_irda_shutdown(struct device *dev)
+{
+        gpio_free(GPIO_NR_PALMZ72_IR_DISABLE);
+}
+
+static void palmz72_irda_transceiver_mode(struct device *dev, int mode)
+{
+        gpio_set_value(GPIO_NR_PALMZ72_IR_DISABLE, mode & IR_OFF);
+        pxa2xx_transceiver_mode(dev, mode);
+}
+
+static struct pxaficp_platform_data palmz72_ficp_platform_data = {
+        .startup                = palmz72_irda_startup,
+        .shutdown               = palmz72_irda_shutdown,
+        .transceiver_cap        = IR_SIRMODE | IR_OFF,
+        .transceiver_mode       = palmz72_irda_transceiver_mode,
+};
+
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "palmz72:green:led",
+                .default_trigger        = "none",
+                .gpio                   = GPIO_NR_PALMZ72_LED_GREEN,
+        },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device palmz72_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        }
+};
+
+/******************************************************************************
+ * Power supply
+ ******************************************************************************/
+static int power_supply_init(struct device *dev)
+{
+        int ret;
+
+        ret = gpio_request(GPIO_NR_PALMZ72_POWER_DETECT, "CABLE_STATE_AC");
+        if (ret)
+                goto err1;
+        ret = gpio_direction_input(GPIO_NR_PALMZ72_POWER_DETECT);
+        if (ret)
+                goto err2;
+
+        ret = gpio_request(GPIO_NR_PALMZ72_USB_DETECT_N, "CABLE_STATE_USB");
+        if (ret)
+                goto err2;
+        ret = gpio_direction_input(GPIO_NR_PALMZ72_USB_DETECT_N);
+        if (ret)
+                goto err3;
+
+        return 0;
+err3:
+        gpio_free(GPIO_NR_PALMZ72_USB_DETECT_N);
+err2:
+        gpio_free(GPIO_NR_PALMZ72_POWER_DETECT);
+err1:
+        return ret;
+}
+
+static int palmz72_is_ac_online(void)
+{
+        return gpio_get_value(GPIO_NR_PALMZ72_POWER_DETECT);
+}
+
+static int palmz72_is_usb_online(void)
+{
+        return !gpio_get_value(GPIO_NR_PALMZ72_USB_DETECT_N);
+}
+
+static void power_supply_exit(struct device *dev)
+{
+        gpio_free(GPIO_NR_PALMZ72_USB_DETECT_N);
+        gpio_free(GPIO_NR_PALMZ72_POWER_DETECT);
+}
+
+static char *palmz72_supplicants[] = {
+        "main-battery",
+};
+
+static struct pda_power_pdata power_supply_info = {
+        .init            = power_supply_init,
+        .is_ac_online    = palmz72_is_ac_online,
+        .is_usb_online   = palmz72_is_usb_online,
+        .exit            = power_supply_exit,
+        .supplied_to     = palmz72_supplicants,
+        .num_supplicants = ARRAY_SIZE(palmz72_supplicants),
+};
+
+static struct platform_device power_supply = {
+        .name = "pda-power",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &power_supply_info,
+        },
+};
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+static struct pxafb_mode_info palmz72_lcd_modes[] = {
+{
+        .pixclock       = 115384,
+        .xres           = 320,
+        .yres           = 320,
+        .bpp            = 16,
+
+        .left_margin    = 27,
+        .right_margin   = 7,
+        .upper_margin   = 7,
+        .lower_margin   = 8,
+
+        .hsync_len      = 6,
+        .vsync_len      = 1,
+},
+};
+
+static struct pxafb_mach_info palmz72_lcd_screen = {
+        .modes          = palmz72_lcd_modes,
+        .num_modes      = ARRAY_SIZE(palmz72_lcd_modes),
+        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+};
+
+#ifdef CONFIG_PM
+
+/* We have some black magic here
+ * PalmOS ROM on recover expects special struct physical address
+ * to be transferred via PSPR. Using this struct PalmOS restores
+ * its state after sleep. As for Linux, we need to setup it the
+ * same way. More than that, PalmOS ROM changes some values in memory.
+ * For now only one location is found, which needs special treatment.
+ * Thanks to Alex Osborne, Andrzej Zaborowski, and lots of other people
+ * for reading backtraces for me :)
+ */
+
+#define PALMZ72_SAVE_DWORD ((unsigned long *)0xc0000050)
+
+static struct palmz72_resume_info palmz72_resume_info = {
+        .magic0 = 0xb4e6,
+        .magic1 = 1,
+
+        /* reset state, MMU off etc */
+        .arm_control = 0,
+        .aux_control = 0,
+        .ttb = 0,
+        .domain_access = 0,
+        .process_id = 0,
+};
+
+static unsigned long store_ptr;
+
+/* sys_device for Palm Zire 72 PM */
+
+static int palmz72_pm_suspend(struct sys_device *dev, pm_message_t msg)
+{
+        /* setup the resume_info struct for the original bootloader */
+        palmz72_resume_info.resume_addr = (u32) pxa_cpu_resume;
+
+        /* Storing memory touched by ROM */
+        store_ptr = *PALMZ72_SAVE_DWORD;
+
+        /* Setting PSPR to a proper value */
+        PSPR = virt_to_phys(&palmz72_resume_info);
+
+        return 0;
+}
+
+static int palmz72_pm_resume(struct sys_device *dev)
+{
+        *PALMZ72_SAVE_DWORD = store_ptr;
+        return 0;
+}
+
+static struct sysdev_class palmz72_pm_sysclass = {
+        .name = "palmz72_pm",
+        .suspend = palmz72_pm_suspend,
+        .resume = palmz72_pm_resume,
+};
+
+static struct sys_device palmz72_pm_device = {
+        .cls = &palmz72_pm_sysclass,
+};
+
+static int __init palmz72_pm_init(void)
+{
+        int ret = -ENODEV;
+        if (machine_is_palmz72()) {
+                ret = sysdev_class_register(&palmz72_pm_sysclass);
+                if (ret == 0)
+                        ret = sysdev_register(&palmz72_pm_device);
+        }
+        return ret;
+}
+
+device_initcall(palmz72_pm_init);
+#endif
+
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static struct platform_device *devices[] __initdata = {
+        &palmz72_backlight,
+        &palmz72_leds,
+        &power_supply,
+};
+
+static void __init palmz72_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config));
+        set_pxa_fb_info(&palmz72_lcd_screen);
+        pxa_set_mci_info(&palmz72_mci_platform_data);
+        pxa_set_ac97_info(NULL);
+        pxa_set_ficp_info(&palmz72_ficp_platform_data);
+        pxa_set_keypad_info(&palmz72_keypad_platform_data);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+MACHINE_START(PALMZ72, "Palm Zire72")
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = io_p2v(0x40000000),
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = palmz72_init
+MACHINE_END
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 730b9f6ede1d..36135a02fdc7 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -31,7 +31,7 @@
 #include <asm/mach/arch.h>
 #include <mach/hardware.h>
 #include <mach/pxa-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa27x.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/pcm027.h>
@@ -86,6 +86,28 @@
  * *) CPU internal use only
  */
 
+static unsigned long pcm027_pin_config[] __initdata = {
+        /* Chip Selects */
+        GPIO20_nSDCS_2,
+        GPIO21_nSDCS_3,
+        GPIO15_nCS_1,
+        GPIO78_nCS_2,
+        GPIO80_nCS_4,
+        GPIO33_nCS_5,   /* Ethernet */
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+
+        /* GPIO */
+        GPIO52_GPIO,    /* IRQ from network controller */
+#ifdef CONFIG_LEDS_GPIO
+        GPIO90_GPIO,    /* PCM027_LED_CPU */
+        GPIO91_GPIO,    /* PCM027_LED_HEART_BEAT */
+#endif
+        GPIO114_GPIO,   /* IRQ from CAN controller */
+};
+
 /*
  * SMC91x network controller specific stuff
  */
@@ -206,13 +228,9 @@ static void __init pcm027_init(void)
          */
         ARB_CNTRL = ARB_CORE_PARK | 0x234;
 
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        pxa2xx_mfp_config(pcm027_pin_config, ARRAY_SIZE(pcm027_pin_config));
 
-        /* LEDs (on demand only) */
-#ifdef CONFIG_LEDS_GPIO
-        pxa_gpio_mode(PCM027_LED_CPU | GPIO_OUT);
-        pxa_gpio_mode(PCM027_LED_HEARD_BEAT | GPIO_OUT);
-#endif /* CONFIG_LEDS_GPIO */
+        platform_add_devices(devices, ARRAY_SIZE(devices));
 
         /* at last call the baseboard to initialize itself */
 #ifdef CONFIG_MACH_PCM990_BASEBOARD
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 420c9b3813f6..f601425f1b1e 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -262,8 +262,7 @@ static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
                                         GPIO_bit(PCM990_CTRL_INT_IRQ_GPIO);
                 if (likely(pending)) {
                         irq = PCM027_IRQ(0) + __ffs(pending);
-                        desc = irq_desc + irq;
-                        desc_handle_irq(irq, desc);
+                        generic_handle_irq(irq);
                 }
                 pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
         } while (pending);
@@ -328,36 +327,10 @@ static struct pxamci_platform_data pcm990_mci_platform_data = {
         .exit           = pcm990_mci_exit,
 };
 
-/*
- * init OHCI hardware to work with
- *
- * Note: Only USB port 1 (host only) is connected
- *
- * GPIO88 (USBHPWR#1): overcurrent in, overcurrent when low
- * GPIO89 (USBHPEN#1): power-on out, on when low
- */
-static int pcm990_ohci_init(struct device *dev)
-{
-        /*
-         * disable USB port 2 and 3
-         * power sense is active low
-         */
-        UHCHR = ((UHCHR) | UHCHR_PCPL | UHCHR_PSPL | UHCHR_SSEP2 |
-                                UHCHR_SSEP3) & ~(UHCHR_SSEP1 | UHCHR_SSE);
-        /*
-         * wait 10ms after Power on
-         * overcurrent per port
-         * power switch per port
-         */
-        UHCRHDA = (5<<24) | (1<<11) | (1<<8);   /* FIXME: Required? */
-
-        return 0;
-}
-
 static struct pxaohci_platform_data pcm990_ohci_platform_data = {
         .port_mode      = PMM_PERPORT_MODE,
-        .init           = pcm990_ohci_init,
-        .exit           = NULL,
+        .flags          = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
+        .power_on_delay = 10,
 };
 
 /*
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 1b539e675579..164eb0bb6321 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -86,9 +86,27 @@ static int pxa_pm_valid(suspend_state_t state)
         return -EINVAL;
 }
 
+static int pxa_pm_prepare(void)
+{
+        int ret = 0;
+
+        if (pxa_cpu_pm_fns && pxa_cpu_pm_fns->prepare)
+                ret = pxa_cpu_pm_fns->prepare();
+
+        return ret;
+}
+
+static void pxa_pm_finish(void)
+{
+        if (pxa_cpu_pm_fns && pxa_cpu_pm_fns->finish)
+                pxa_cpu_pm_fns->finish();
+}
+
 static struct platform_suspend_ops pxa_pm_ops = {
         .valid          = pxa_pm_valid,
         .enter          = pxa_pm_enter,
+        .prepare        = pxa_pm_prepare,
+        .finish         = pxa_pm_finish,
 };
 
 static int __init pxa_pm_init(void)
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 3f5f484549b3..2e3bd8b1523b 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -20,6 +20,9 @@
 #include <linux/fb.h>
 #include <linux/pm.h>
 #include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -33,7 +36,7 @@
 
 #include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa25x.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
 #include <mach/i2c.h>
@@ -42,6 +45,7 @@
 #include <mach/pxafb.h>
 #include <mach/sharpsl.h>
 #include <mach/ssp.h>
+#include <mach/pxa2xx_spi.h>
 
 #include <asm/hardware/scoop.h>
 #include <asm/hardware/locomo.h>
@@ -51,6 +55,88 @@
 #include "devices.h"
 #include "sharpsl.h"
 
+static unsigned long poodle_pin_config[] __initdata = {
+        /* I/O */
+        GPIO79_nCS_3,
+        GPIO80_nCS_4,
+        GPIO18_RDY,
+
+        /* Clock */
+        GPIO12_32KHz,
+
+        /* SSP1 */
+        GPIO23_SSP1_SCLK,
+        GPIO25_SSP1_TXD,
+        GPIO26_SSP1_RXD,
+        GPIO24_GPIO,    /* POODLE_GPIO_TP_CS - SFRM as chip select */
+
+        /* I2S */
+        GPIO28_I2S_BITCLK_OUT,
+        GPIO29_I2S_SDATA_IN,
+        GPIO30_I2S_SDATA_OUT,
+        GPIO31_I2S_SYNC,
+        GPIO32_I2S_SYSCLK,
+
+        /* Infra-Red */
+        GPIO47_FICP_TXD,
+        GPIO46_FICP_RXD,
+
+        /* FFUART */
+        GPIO40_FFUART_DTR,
+        GPIO41_FFUART_RTS,
+        GPIO39_FFUART_TXD,
+        GPIO37_FFUART_DSR,
+        GPIO34_FFUART_RXD,
+        GPIO35_FFUART_CTS,
+
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+
+        /* PC Card */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO52_nPCE_1,
+        GPIO53_nPCE_2,
+        GPIO54_nPSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* MMC */
+        GPIO6_MMC_CLK,
+        GPIO8_MMC_CS0,
+
+        /* GPIO */
+        GPIO9_GPIO,     /* POODLE_GPIO_nSD_DETECT */
+        GPIO7_GPIO,     /* POODLE_GPIO_nSD_WP */
+        GPIO3_GPIO,     /* POODLE_GPIO_SD_PWR */
+        GPIO33_GPIO,    /* POODLE_GPIO_SD_PWR1 */
+
+        GPIO20_GPIO,    /* POODLE_GPIO_USB_PULLUP */
+        GPIO22_GPIO,    /* POODLE_GPIO_IR_ON */
+};
+
 static struct resource poodle_scoop_resources[] = {
         [0] = {
                 .start          = 0x10800000,
@@ -62,6 +148,7 @@ static struct resource poodle_scoop_resources[] = {
 static struct scoop_config poodle_scoop_setup = {
         .io_dir         = POODLE_SCOOP_IO_DIR,
         .io_out         = POODLE_SCOOP_IO_OUT,
+        .gpio_base      = POODLE_SCOOP_GPIO_BASE,
 };
 
 struct platform_device poodle_scoop_device = {
@@ -74,27 +161,6 @@ struct platform_device poodle_scoop_device = {
         .resource       = poodle_scoop_resources,
 };
 
-static void poodle_pcmcia_init(void)
-{
-        /* Setup default state of GPIO outputs
-           before we enable them as outputs. */
-        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) |
-                GPIO_bit(GPIO53_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-        pxa_gpio_mode(GPIO52_nPCE_1_MD);
-        pxa_gpio_mode(GPIO53_nPCE_2_MD);
-        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
-}
-
 static struct scoop_pcmcia_dev poodle_pcmcia_scoop[] = {
 {
         .dev        = &poodle_scoop_device.dev,
@@ -107,7 +173,6 @@ static struct scoop_pcmcia_dev poodle_pcmcia_scoop[] = {
 static struct scoop_pcmcia_config poodle_pcmcia_config = {
         .devs         = &poodle_pcmcia_scoop[0],
         .num_devs     = 1,
-        .pcmcia_init  = poodle_pcmcia_init,
 };
 
 EXPORT_SYMBOL(poodle_scoop_device);
@@ -136,62 +201,55 @@ struct platform_device poodle_locomo_device = {
 
 EXPORT_SYMBOL(poodle_locomo_device);
 
-/*
- * Poodle SSP Device
- */
-
-struct platform_device poodle_ssp_device = {
-        .name           = "corgi-ssp",
-        .id             = -1,
-};
-
-struct corgissp_machinfo poodle_ssp_machinfo = {
-        .port           = 1,
-        .cs_lcdcon      = -1,
-        .cs_ads7846     = -1,
-        .cs_max1111     = -1,
-        .clk_lcdcon     = 2,
-        .clk_ads7846    = 36,
-        .clk_max1111    = 2,
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+static struct pxa2xx_spi_master poodle_spi_info = {
+        .num_chipselect = 1,
 };
 
-
-/*
- * Poodle Touch Screen Device
- */
-static struct resource poodlets_resources[] = {
-        [0] = {
-                .start          = POODLE_IRQ_GPIO_TP_INT,
-                .end            = POODLE_IRQ_GPIO_TP_INT,
-                .flags          = IORESOURCE_IRQ,
-        },
+static struct ads7846_platform_data poodle_ads7846_info = {
+        .model                  = 7846,
+        .vref_delay_usecs       = 100,
+        .x_plate_ohms           = 419,
+        .y_plate_ohms           = 486,
+        .gpio_pendown           = POODLE_GPIO_TP_INT,
 };
 
-static unsigned long poodle_get_hsync_invperiod(void)
+static void ads7846_cs(u32 command)
 {
-        return 0;
+        gpio_set_value(POODLE_GPIO_TP_CS, !(command == PXA2XX_CS_ASSERT));
 }
 
-static void poodle_null_hsync(void)
-{
-}
-
-static struct corgits_machinfo  poodle_ts_machinfo = {
-        .get_hsync_invperiod    = poodle_get_hsync_invperiod,
-        .put_hsync              = poodle_null_hsync,
-        .wait_hsync             = poodle_null_hsync,
+static struct pxa2xx_spi_chip poodle_ads7846_chip = {
+        .cs_control             = ads7846_cs,
 };
 
-static struct platform_device poodle_ts_device = {
-        .name           = "corgi-ts",
-        .dev            = {
-                .platform_data  = &poodle_ts_machinfo,
+static struct spi_board_info poodle_spi_devices[] = {
+        {
+                .modalias       = "ads7846",
+                .max_speed_hz   = 10000,
+                .bus_num        = 1,
+                .platform_data  = &poodle_ads7846_info,
+                .controller_data= &poodle_ads7846_chip,
+                .irq            = gpio_to_irq(POODLE_GPIO_TP_INT),
         },
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(poodlets_resources),
-        .resource       = poodlets_resources,
 };
 
+static void __init poodle_init_spi(void)
+{
+        int err;
+
+        err = gpio_request(POODLE_GPIO_TP_CS, "ADS7846_CS");
+        if (err)
+                return;
+
+        gpio_direction_output(POODLE_GPIO_TP_CS, 1);
+
+        pxa2xx_set_spi_info(1, &poodle_spi_info);
+        spi_register_board_info(ARRAY_AND_SIZE(poodle_spi_devices));
+}
+#else
+static inline void poodle_init_spi(void) {}
+#endif
 
 /*
  * MMC/SD Device
@@ -205,22 +263,50 @@ static int poodle_mci_init(struct device *dev, irq_handler_t poodle_detect_int,
 {
         int err;
 
-        /* setup GPIO for PXA25x MMC controller */
-        pxa_gpio_mode(GPIO6_MMCCLK_MD);
-        pxa_gpio_mode(GPIO8_MMCCS0_MD);
-        pxa_gpio_mode(POODLE_GPIO_nSD_DETECT | GPIO_IN);
-        pxa_gpio_mode(POODLE_GPIO_nSD_WP | GPIO_IN);
-        pxa_gpio_mode(POODLE_GPIO_SD_PWR | GPIO_OUT);
-        pxa_gpio_mode(POODLE_GPIO_SD_PWR1 | GPIO_OUT);
+        err = gpio_request(POODLE_GPIO_nSD_DETECT, "nSD_DETECT");
+        if (err)
+                goto err_out;
+
+        err = gpio_request(POODLE_GPIO_nSD_WP, "nSD_WP");
+        if (err)
+                goto err_free_1;
+
+        err = gpio_request(POODLE_GPIO_SD_PWR, "SD_PWR");
+        if (err)
+                goto err_free_2;
+
+        err = gpio_request(POODLE_GPIO_SD_PWR1, "SD_PWR1");
+        if (err)
+                goto err_free_3;
+
+        gpio_direction_input(POODLE_GPIO_nSD_DETECT);
+        gpio_direction_input(POODLE_GPIO_nSD_WP);
+
+        gpio_direction_output(POODLE_GPIO_SD_PWR, 0);
+        gpio_direction_output(POODLE_GPIO_SD_PWR1, 0);
 
         poodle_mci_platform_data.detect_delay = msecs_to_jiffies(250);
 
         err = request_irq(POODLE_IRQ_GPIO_nSD_DETECT, poodle_detect_int,
                           IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                           "MMC card detect", data);
-        if (err)
-                printk(KERN_ERR "poodle_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
+        if (err) {
+                pr_err("%s: MMC/SD: can't request MMC card detect IRQ\n",
+                                __func__);
+                goto err_free_4;
+        }
+
+        return 0;
 
+err_free_4:
+        gpio_free(POODLE_GPIO_SD_PWR1);
+err_free_3:
+        gpio_free(POODLE_GPIO_SD_PWR);
+err_free_2:
+        gpio_free(POODLE_GPIO_nSD_WP);
+err_free_1:
+        gpio_free(POODLE_GPIO_nSD_DETECT);
+err_out:
         return err;
 }
 
@@ -228,18 +314,19 @@ static void poodle_mci_setpower(struct device *dev, unsigned int vdd)
 {
         struct pxamci_platform_data* p_d = dev->platform_data;
 
-        if (( 1 << vdd) & p_d->ocr_mask) {
-                GPSR(POODLE_GPIO_SD_PWR) = GPIO_bit(POODLE_GPIO_SD_PWR);
+        if ((1 << vdd) & p_d->ocr_mask) {
+                gpio_set_value(POODLE_GPIO_SD_PWR, 1);
                 mdelay(2);
-                GPSR(POODLE_GPIO_SD_PWR1) = GPIO_bit(POODLE_GPIO_SD_PWR1);
+                gpio_set_value(POODLE_GPIO_SD_PWR1, 1);
         } else {
-                GPCR(POODLE_GPIO_SD_PWR1) = GPIO_bit(POODLE_GPIO_SD_PWR1);
-                GPCR(POODLE_GPIO_SD_PWR) = GPIO_bit(POODLE_GPIO_SD_PWR);
+                gpio_set_value(POODLE_GPIO_SD_PWR1, 0);
+                gpio_set_value(POODLE_GPIO_SD_PWR, 0);
         }
 }
 
 static int poodle_mci_get_ro(struct device *dev)
 {
+        return !!gpio_get_value(POODLE_GPIO_nSD_WP);
         return GPLR(POODLE_GPIO_nSD_WP) & GPIO_bit(POODLE_GPIO_nSD_WP);
 }
 
@@ -247,6 +334,10 @@ static int poodle_mci_get_ro(struct device *dev)
 static void poodle_mci_exit(struct device *dev, void *data)
 {
         free_irq(POODLE_IRQ_GPIO_nSD_DETECT, data);
+        gpio_free(POODLE_GPIO_SD_PWR1);
+        gpio_free(POODLE_GPIO_SD_PWR);
+        gpio_free(POODLE_GPIO_nSD_WP);
+        gpio_free(POODLE_GPIO_nSD_DETECT);
 }
 
 static struct pxamci_platform_data poodle_mci_platform_data = {
@@ -263,38 +354,41 @@ static struct pxamci_platform_data poodle_mci_platform_data = {
  */
 static void poodle_irda_transceiver_mode(struct device *dev, int mode)
 {
-        if (mode & IR_OFF) {
-                GPSR(POODLE_GPIO_IR_ON) = GPIO_bit(POODLE_GPIO_IR_ON);
-        } else {
-                GPCR(POODLE_GPIO_IR_ON) = GPIO_bit(POODLE_GPIO_IR_ON);
-        }
+        gpio_set_value(POODLE_GPIO_IR_ON, mode & IR_OFF);
         pxa2xx_transceiver_mode(dev, mode);
 }
 
+static int poodle_irda_startup(struct device *dev)
+{
+        int err;
+
+        err = gpio_request(POODLE_GPIO_IR_ON, "IR_ON");
+        if (err)
+                return err;
+
+        gpio_direction_output(POODLE_GPIO_IR_ON, 1);
+        return 0;
+}
+
+static void poodle_irda_shutdown(struct device *dev)
+{
+        gpio_free(POODLE_GPIO_IR_ON);
+}
+
 static struct pxaficp_platform_data poodle_ficp_platform_data = {
-        .transceiver_cap  = IR_SIRMODE | IR_OFF,
-        .transceiver_mode = poodle_irda_transceiver_mode,
+        .transceiver_cap        = IR_SIRMODE | IR_OFF,
+        .transceiver_mode       = poodle_irda_transceiver_mode,
+        .startup                = poodle_irda_startup,
+        .shutdown               = poodle_irda_shutdown,
 };
 
 
 /*
  * USB Device Controller
  */
-static void poodle_udc_command(int cmd)
-{
-        switch(cmd)     {
-        case PXA2XX_UDC_CMD_CONNECT:
-                GPSR(POODLE_GPIO_USB_PULLUP) = GPIO_bit(POODLE_GPIO_USB_PULLUP);
-                break;
-        case PXA2XX_UDC_CMD_DISCONNECT:
-                GPCR(POODLE_GPIO_USB_PULLUP) = GPIO_bit(POODLE_GPIO_USB_PULLUP);
-                break;
-        }
-}
-
 static struct pxa2xx_udc_mach_info udc_info __initdata = {
         /* no connect GPIO; poodle can't tell connection status */
-        .udc_command            = poodle_udc_command,
+        .gpio_pullup    = POODLE_GPIO_USB_PULLUP,
 };
 
 
@@ -316,15 +410,12 @@ static struct pxafb_mode_info poodle_fb_mode = {
 static struct pxafb_mach_info poodle_fb_info = {
         .modes          = &poodle_fb_mode,
         .num_modes      = 1,
-        .lccr0          = LCCR0_Act | LCCR0_Sngl | LCCR0_Color,
-        .lccr3          = 0,
+        .lcd_conn       = LCD_COLOR_TFT_16BPP,
 };
 
 static struct platform_device *devices[] __initdata = {
         &poodle_locomo_device,
         &poodle_scoop_device,
-        &poodle_ssp_device,
-        &poodle_ts_device,
 };
 
 static void poodle_poweroff(void)
@@ -344,59 +435,23 @@ static void __init poodle_init(void)
         pm_power_off = poodle_poweroff;
         arm_pm_restart = poodle_restart;
 
-        /* setup sleep mode values */
-        PWER  = 0x00000002;
-        PFER  = 0x00000000;
-        PRER  = 0x00000002;
-        PGSR0 = 0x00008000;
-        PGSR1 = 0x003F0202;
-        PGSR2 = 0x0001C000;
         PCFR |= PCFR_OPDE;
 
-        /* cpu initialize */
-        /* Pgsr Register */
-        PGSR0 = 0x0146dd80;
-        PGSR1 = 0x03bf0890;
-        PGSR2 = 0x0001c000;
-
-        /* Alternate Register */
-        GAFR0_L = 0x01001000;
-        GAFR0_U = 0x591a8010;
-        GAFR1_L = 0x900a8451;
-        GAFR1_U = 0xaaa5aaaa;
-        GAFR2_L = 0x8aaaaaaa;
-        GAFR2_U = 0x00000002;
-
-        /* Direction Register */
-        GPDR0 = 0xd3f0904c;
-        GPDR1 = 0xfcffb7d3;
-        GPDR2 = 0x0001ffff;
-
-        /* Output Register */
-        GPCR0 = 0x00000000;
-        GPCR1 = 0x00000000;
-        GPCR2 = 0x00000000;
-
-        GPSR0 = 0x00400000;
-        GPSR1 = 0x00000000;
-        GPSR2 = 0x00000000;
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(poodle_pin_config));
+
+        platform_scoop_config = &poodle_pcmcia_config;
+
+        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+        if (ret)
+                pr_warning("poodle: Unable to register LoCoMo device\n");
 
         set_pxa_fb_parent(&poodle_locomo_device.dev);
         set_pxa_fb_info(&poodle_fb_info);
-        pxa_gpio_mode(POODLE_GPIO_USB_PULLUP | GPIO_OUT);
-        pxa_gpio_mode(POODLE_GPIO_IR_ON | GPIO_OUT);
         pxa_set_udc_info(&udc_info);
         pxa_set_mci_info(&poodle_mci_platform_data);
         pxa_set_ficp_info(&poodle_ficp_platform_data);
         pxa_set_i2c_info(NULL);
-
-        platform_scoop_config = &poodle_pcmcia_config;
-
-        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
-        if (ret) {
-                printk(KERN_WARNING "poodle: Unable to register LoCoMo device\n");
-        }
-        corgi_ssp_set_machinfo(&poodle_ssp_machinfo);
+        poodle_init_spi();
 }
 
 static void __init fixup_poodle(struct machine_desc *desc,
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 305452b56e91..25d17a1dab78 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -36,6 +36,12 @@
 #include "devices.h"
 #include "clock.h"
 
+int cpu_is_pxa26x(void)
+{
+        return cpu_is_pxa250() && ((BOOT_DEF & 0x8) == 0);
+}
+EXPORT_SYMBOL_GPL(cpu_is_pxa26x);
+
 /*
  * Various clock factors driven by the CCCR register.
  */
@@ -203,48 +209,21 @@ static struct clk pxa25x_clks[] = {
  * More ones like CP and general purpose register values are preserved
  * with the stack pointer in sleep.S.
  */
-enum {  SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
-
-        SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
-        SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
-        SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
-
+enum {
         SLEEP_SAVE_PSTR,
-
         SLEEP_SAVE_CKEN,
-
         SLEEP_SAVE_COUNT
 };
 
 
 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
 {
-        SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
-
-        SAVE(GAFR0_L); SAVE(GAFR0_U);
-        SAVE(GAFR1_L); SAVE(GAFR1_U);
-        SAVE(GAFR2_L); SAVE(GAFR2_U);
-
         SAVE(CKEN);
         SAVE(PSTR);
-
-        /* Clear GPIO transition detect bits */
-        GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
 }
 
 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
 {
-        /* ensure not to come back here if it wasn't intended */
-        PSPR = 0;
-
-        /* restore registers */
-        RESTORE(GAFR0_L); RESTORE(GAFR0_U);
-        RESTORE(GAFR1_L); RESTORE(GAFR1_U);
-        RESTORE(GAFR2_L); RESTORE(GAFR2_U);
-        RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
-
-        PSSR = PSSR_RDH | PSSR_PH;
-
         RESTORE(CKEN);
         RESTORE(PSTR);
 }
@@ -256,19 +235,32 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state)
 
         switch (state) {
         case PM_SUSPEND_MEM:
-                /* set resume return address */
-                PSPR = virt_to_phys(pxa_cpu_resume);
                 pxa25x_cpu_suspend(PWRMODE_SLEEP);
                 break;
         }
 }
 
+static int pxa25x_cpu_pm_prepare(void)
+{
+        /* set resume return address */
+        PSPR = virt_to_phys(pxa_cpu_resume);
+        return 0;
+}
+
+static void pxa25x_cpu_pm_finish(void)
+{
+        /* ensure not to come back here if it wasn't intended */
+        PSPR = 0;
+}
+
 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
         .save_count     = SLEEP_SAVE_COUNT,
         .valid          = suspend_valid_only_mem,
         .save           = pxa25x_cpu_pm_save,
         .restore        = pxa25x_cpu_pm_restore,
         .enter          = pxa25x_cpu_pm_enter,
+        .prepare        = pxa25x_cpu_pm_prepare,
+        .finish         = pxa25x_cpu_pm_finish,
 };
 
 static void __init pxa25x_init_pm(void)
@@ -330,6 +322,8 @@ static struct sys_device pxa25x_sysdev[] = {
         {
                 .cls    = &pxa_irq_sysclass,
         }, {
+                .cls    = &pxa2xx_mfp_sysclass,
+        }, {
                 .cls    = &pxa_gpio_sysclass,
         },
 };
@@ -338,11 +332,7 @@ static int __init pxa25x_init(void)
 {
         int i, ret = 0;
 
-        /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
-        if (cpu_is_pxa255())
-                clks_register(&pxa25x_hwuart_clk, 1);
-
-        if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
+        if (cpu_is_pxa25x()) {
 
                 reset_status = RCSR;
 
@@ -365,9 +355,11 @@ static int __init pxa25x_init(void)
                         return ret;
         }
 
-        /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
-        if (cpu_is_pxa255())
+        /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
+        if (cpu_is_pxa255() || cpu_is_pxa26x()) {
+                clks_register(&pxa25x_hwuart_clk, 1);
                 ret = platform_device_register(&pxa_device_hwuart);
+        }
 
         return ret;
 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index f9f6a9c31f4b..3e4ab2279c99 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -34,6 +34,13 @@
 #include "devices.h"
 #include "clock.h"
 
+void pxa27x_clear_otgph(void)
+{
+        if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
+                PSSR |= PSSR_OTGPH;
+}
+EXPORT_SYMBOL(pxa27x_clear_otgph);
+
 /* Crystal clock: 13MHz */
 #define BASE_CLK        13000000
 
@@ -183,36 +190,18 @@ static struct clk pxa27x_clks[] = {
  * More ones like CP and general purpose register values are preserved
  * with the stack pointer in sleep.S.
  */
-enum {  SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
-
-        SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
-        SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
-        SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
-        SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
-
+enum {
         SLEEP_SAVE_PSTR,
-
         SLEEP_SAVE_CKEN,
-
         SLEEP_SAVE_MDREFR,
-        SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
-        SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
-
+        SLEEP_SAVE_PCFR,
         SLEEP_SAVE_COUNT
 };
 
 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 {
-        SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
-
-        SAVE(GAFR0_L); SAVE(GAFR0_U);
-        SAVE(GAFR1_L); SAVE(GAFR1_U);
-        SAVE(GAFR2_L); SAVE(GAFR2_U);
-        SAVE(GAFR3_L); SAVE(GAFR3_U);
-
         SAVE(MDREFR);
-        SAVE(PWER); SAVE(PCFR); SAVE(PRER);
-        SAVE(PFER); SAVE(PKWR);
+        SAVE(PCFR);
 
         SAVE(CKEN);
         SAVE(PSTR);
@@ -220,24 +209,12 @@ void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 
 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 {
-        /* ensure not to come back here if it wasn't intended */
-        PSPR = 0;
-
-        /* restore registers */
-        RESTORE(GAFR0_L); RESTORE(GAFR0_U);
-        RESTORE(GAFR1_L); RESTORE(GAFR1_U);
-        RESTORE(GAFR2_L); RESTORE(GAFR2_U);
-        RESTORE(GAFR3_L); RESTORE(GAFR3_U);
-        RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
-
         RESTORE(MDREFR);
-        RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
-        RESTORE(PFER); RESTORE(PKWR);
+        RESTORE(PCFR);
 
         PSSR = PSSR_RDH | PSSR_PH;
 
         RESTORE(CKEN);
-
         RESTORE(PSTR);
 }
 
@@ -259,8 +236,6 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
                 pxa_cpu_standby();
                 break;
         case PM_SUSPEND_MEM:
-                /* set resume return address */
-                PSPR = virt_to_phys(pxa_cpu_resume);
                 pxa27x_cpu_suspend(PWRMODE_SLEEP);
                 break;
         }
@@ -271,12 +246,27 @@ static int pxa27x_cpu_pm_valid(suspend_state_t state)
         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 }
 
+static int pxa27x_cpu_pm_prepare(void)
+{
+        /* set resume return address */
+        PSPR = virt_to_phys(pxa_cpu_resume);
+        return 0;
+}
+
+static void pxa27x_cpu_pm_finish(void)
+{
+        /* ensure not to come back here if it wasn't intended */
+        PSPR = 0;
+}
+
 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
         .save_count     = SLEEP_SAVE_COUNT,
         .save           = pxa27x_cpu_pm_save,
         .restore        = pxa27x_cpu_pm_restore,
         .valid          = pxa27x_cpu_pm_valid,
         .enter          = pxa27x_cpu_pm_enter,
+        .prepare        = pxa27x_cpu_pm_prepare,
+        .finish         = pxa27x_cpu_pm_finish,
 };
 
 static void __init pxa27x_init_pm(void)
@@ -349,7 +339,7 @@ struct platform_device pxa27x_device_i2c_power = {
         .num_resources  = ARRAY_SIZE(i2c_power_resources),
 };
 
-void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
+void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 {
         local_irq_disable();
         PCFR |= PCFR_PI2CEN;
@@ -376,6 +366,8 @@ static struct sys_device pxa27x_sysdev[] = {
         {
                 .cls    = &pxa_irq_sysclass,
         }, {
+                .cls    = &pxa2xx_mfp_sysclass,
+        }, {
                 .cls    = &pxa_gpio_sysclass,
         },
 };
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 03cbc38103ed..b3cd5d0b0f35 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -203,6 +203,19 @@ static const struct clkops clk_pout_ops = {
         .disable        = clk_pout_disable,
 };
 
+static void clk_dummy_enable(struct clk *clk)
+{
+}
+
+static void clk_dummy_disable(struct clk *clk)
+{
+}
+
+static const struct clkops clk_dummy_ops = {
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable,
+};
+
 static struct clk pxa3xx_clks[] = {
         {
                 .name           = "CLK_POUT",
@@ -211,6 +224,13 @@ static struct clk pxa3xx_clks[] = {
                 .delay          = 70,
         },
 
+        /* Power I2C clock is always on */
+        {
+                .name           = "I2CCLK",
+                .ops            = &clk_dummy_ops,
+                .dev            = &pxa3xx_device_i2c_power.dev,
+        },
+
         PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
         PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
         PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),
@@ -509,6 +529,30 @@ void __init pxa3xx_init_irq(void)
  * device registration specific to PXA3xx.
  */
 
+static struct resource i2c_power_resources[] = {
+        {
+                .start  = 0x40f500c0,
+                .end    = 0x40f500d3,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PWRI2C,
+                .end    = IRQ_PWRI2C,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa3xx_device_i2c_power = {
+        .name           = "pxa2xx-i2c",
+        .id             = 1,
+        .resource       = i2c_power_resources,
+        .num_resources  = ARRAY_SIZE(i2c_power_resources),
+};
+
+void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
+{
+        pxa3xx_device_i2c_power.dev.platform_data = info;
+}
+
 static struct platform_device *devices[] __initdata = {
 /*      &pxa_device_udc,        The UDC driver is PXA25x only */
         &pxa_device_ffuart,
@@ -522,6 +566,7 @@ static struct platform_device *devices[] __initdata = {
         &pxa3xx_device_ssp4,
         &pxa27x_device_pwm0,
         &pxa27x_device_pwm1,
+        &pxa3xx_device_i2c_power,
 };
 
 static struct sys_device pxa3xx_sysdev[] = {
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 9996c612c3d6..1b2af575c40f 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -7,7 +7,7 @@
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/proc-fns.h>
 
 #include <mach/pxa-regs.h>
@@ -20,7 +20,7 @@ static void do_hw_reset(void);
 
 static int reset_gpio = -1;
 
-int init_gpio_reset(int gpio)
+int init_gpio_reset(int gpio, int output)
 {
         int rc;
 
@@ -30,9 +30,12 @@ int init_gpio_reset(int gpio)
                 goto out;
         }
 
-        rc = gpio_direction_input(gpio);
+        if (output)
+                rc = gpio_direction_output(gpio, 0);
+        else
+                rc = gpio_direction_input(gpio);
         if (rc) {
-                printk(KERN_ERR "Can't configure reset_gpio for input\n");
+                printk(KERN_ERR "Can't configure reset_gpio\n");
                 gpio_free(gpio);
                 goto out;
         }
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index e804ae09370c..15c2f1a8623b 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -116,24 +116,20 @@ struct battery_thresh  spitz_battery_levels_noac[] = {
         {   0,   0},
 };
 
-/* MAX1111 Commands */
-#define MAXCTRL_PD0      1u << 0
-#define MAXCTRL_PD1      1u << 1
-#define MAXCTRL_SGL      1u << 2
-#define MAXCTRL_UNI      1u << 3
-#define MAXCTRL_SEL_SH   4
-#define MAXCTRL_STR      1u << 7
-
 /*
  * Read MAX1111 ADC
  */
+extern int max1111_read_channel(int);
+
 int sharpsl_pm_pxa_read_max1111(int channel)
 {
         if (machine_is_tosa()) // Ugly, better move this function into another module
             return 0;
 
-        return corgi_ssp_max1111_get((channel << MAXCTRL_SEL_SH) | MAXCTRL_PD0 | MAXCTRL_PD1
-                        | MAXCTRL_SGL | MAXCTRL_UNI | MAXCTRL_STR);
+        /* max1111 accepts channels from 0-3, however,
+         * it is encoded from 0-7 here in the code.
+         */
+        return max1111_read_channel(channel >> 1);
 }
 
 void sharpsl_pm_pxa_init(void)
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index b569f3b4cf3a..524f656dc56d 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -19,16 +19,23 @@
 #include <linux/major.h>
 #include <linux/fs.h>
 #include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 #include <linux/mmc/host.h>
 #include <linux/pm.h>
 #include <linux/backlight.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+#include <linux/spi/corgi_lcd.h>
 
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/system.h>
 
 #include <asm/mach/arch.h>
@@ -37,7 +44,7 @@
 
 #include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
 #include <mach/i2c.h>
@@ -46,7 +53,7 @@
 #include <mach/ohci.h>
 #include <mach/udc.h>
 #include <mach/pxafb.h>
-#include <mach/akita.h>
+#include <mach/pxa2xx_spi.h>
 #include <mach/spitz.h>
 #include <mach/sharpsl.h>
 
@@ -57,6 +64,66 @@
 #include "devices.h"
 #include "sharpsl.h"
 
+static unsigned long spitz_pin_config[] __initdata = {
+        /* Chip Selects */
+        GPIO78_nCS_2,   /* SCOOP #2 */
+        GPIO80_nCS_4,   /* SCOOP #1 */
+
+        /* LCD - 16bpp Active TFT */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+
+        /* PC Card */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO79_PSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO112_MMC_CMD,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+
+        /* GPIOs */
+        GPIO9_GPIO,     /* SPITZ_GPIO_nSD_DETECT */
+        GPIO81_GPIO,    /* SPITZ_GPIO_nSD_WP */
+        GPIO41_GPIO,    /* SPITZ_GPIO_USB_CONNECT */
+        GPIO37_GPIO,    /* SPITZ_GPIO_USB_HOST */
+        GPIO35_GPIO,    /* SPITZ_GPIO_USB_DEVICE */
+        GPIO22_GPIO,    /* SPITZ_GPIO_HSYNC */
+        GPIO94_GPIO,    /* SPITZ_GPIO_CF_CD */
+        GPIO105_GPIO,   /* SPITZ_GPIO_CF_IRQ */
+        GPIO106_GPIO,   /* SPITZ_GPIO_CF2_IRQ */
+
+        GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
+};
+
 /*
  * Spitz SCOOP Device #1
  */
@@ -69,10 +136,11 @@ static struct resource spitz_scoop_resources[] = {
 };
 
 static struct scoop_config spitz_scoop_setup = {
-        .io_dir         = SPITZ_SCP_IO_DIR,
+        .io_dir         = SPITZ_SCP_IO_DIR,
         .io_out         = SPITZ_SCP_IO_OUT,
-        .suspend_clr = SPITZ_SCP_SUS_CLR,
-        .suspend_set = SPITZ_SCP_SUS_SET,
+        .suspend_clr    = SPITZ_SCP_SUS_CLR,
+        .suspend_set    = SPITZ_SCP_SUS_SET,
+        .gpio_base      = SPITZ_SCP_GPIO_BASE,
 };
 
 struct platform_device spitzscoop_device = {
@@ -97,10 +165,11 @@ static struct resource spitz_scoop2_resources[] = {
 };
 
 static struct scoop_config spitz_scoop2_setup = {
-        .io_dir         = SPITZ_SCP2_IO_DIR,
+        .io_dir         = SPITZ_SCP2_IO_DIR,
         .io_out         = SPITZ_SCP2_IO_OUT,
-        .suspend_clr = SPITZ_SCP2_SUS_CLR,
-        .suspend_set = SPITZ_SCP2_SUS_SET,
+        .suspend_clr    = SPITZ_SCP2_SUS_CLR,
+        .suspend_set    = SPITZ_SCP2_SUS_SET,
+        .gpio_base      = SPITZ_SCP2_GPIO_BASE,
 };
 
 struct platform_device spitzscoop2_device = {
@@ -122,7 +191,7 @@ static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
         unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR);
 
         if (new_cpr & 0x0007) {
-                set_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_CF_POWER);
+                gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
                 if (!(cpr & 0x0002) && !(cpr & 0x0004))
                         mdelay(5);
                 if (device == SPITZ_PWR_CF)
@@ -138,34 +207,13 @@ static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
                 if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
                         write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, 0x0000);
                         mdelay(1);
-                        reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_CF_POWER);
+                        gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
                 } else {
                         write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
                 }
         }
 }
 
-static void spitz_pcmcia_init(void)
-{
-        /* Setup default state of GPIO outputs
-           before we enable them as outputs. */
-        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO54_nPCE_2);
-        GPSR(GPIO85_nPCE_1) = GPIO_bit(GPIO85_nPCE_1);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-        pxa_gpio_mode(GPIO85_nPCE_1_MD);
-        pxa_gpio_mode(GPIO54_nPCE_2_MD);
-        pxa_gpio_mode(GPIO104_pSKTSEL_MD);
-}
-
 static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
 {
         /* Only need to override behaviour for slot 0 */
@@ -191,165 +239,169 @@ static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
 static struct scoop_pcmcia_config spitz_pcmcia_config = {
         .devs         = &spitz_pcmcia_scoop[0],
         .num_devs     = 2,
-        .pcmcia_init  = spitz_pcmcia_init,
         .power_ctrl   = spitz_pcmcia_pwr,
 };
 
 EXPORT_SYMBOL(spitzscoop_device);
 EXPORT_SYMBOL(spitzscoop2_device);
 
-
 /*
- * Spitz SSP Device
- *
- * Set the parent as the scoop device because a lot of SSP devices
- * also use scoop functions and this makes the power up/down order
- * work correctly.
+ * Spitz Keyboard Device
  */
-struct platform_device spitzssp_device = {
-        .name           = "corgi-ssp",
-        .dev            = {
-                .parent = &spitzscoop_device.dev,
-        },
+static struct platform_device spitzkbd_device = {
+        .name           = "spitz-keyboard",
         .id             = -1,
 };
 
-struct corgissp_machinfo spitz_ssp_machinfo = {
-        .port           = 2,
-        .cs_lcdcon      = SPITZ_GPIO_LCDCON_CS,
-        .cs_ads7846     = SPITZ_GPIO_ADS7846_CS,
-        .cs_max1111     = SPITZ_GPIO_MAX1111_CS,
-        .clk_lcdcon     = 520,
-        .clk_ads7846    = 14,
-        .clk_max1111    = 56,
-};
-
 
 /*
- * Spitz Backlight Device
+ * Spitz LEDs
  */
-static void spitz_bl_kick_battery(void)
-{
-        void (*kick_batt)(void);
-
-        kick_batt = symbol_get(sharpsl_battery_kick);
-        if (kick_batt) {
-                kick_batt();
-                symbol_put(sharpsl_battery_kick);
-        }
-}
-
-static struct generic_bl_info spitz_bl_machinfo = {
-        .name = "corgi-bl",
-        .default_intensity = 0x1f,
-        .limit_mask = 0x0b,
-        .max_intensity = 0x2f,
-        .kick_battery = spitz_bl_kick_battery,
-};
-
-static struct platform_device spitzbl_device = {
-        .name           = "generic-bl",
-        .dev            = {
-                .platform_data  = &spitz_bl_machinfo,
+static struct gpio_led spitz_gpio_leds[] = {
+        {
+                .name                   = "spitz:amber:charge",
+                .default_trigger        = "sharpsl-charge",
+                .gpio                   = SPITZ_GPIO_LED_ORANGE,
+        },
+        {
+                .name                   = "spitz:green:hddactivity",
+                .default_trigger        = "ide-disk",
+                .gpio                   = SPITZ_GPIO_LED_GREEN,
         },
-        .id             = -1,
 };
 
-
-/*
- * Spitz Keyboard Device
- */
-static struct platform_device spitzkbd_device = {
-        .name           = "spitz-keyboard",
-        .id             = -1,
+static struct gpio_led_platform_data spitz_gpio_leds_info = {
+        .leds           = spitz_gpio_leds,
+        .num_leds       = ARRAY_SIZE(spitz_gpio_leds),
 };
 
-
-/*
- * Spitz LEDs
- */
 static struct platform_device spitzled_device = {
-        .name           = "spitz-led",
+        .name           = "leds-gpio",
         .id             = -1,
+        .dev            = {
+                .platform_data = &spitz_gpio_leds_info,
+        },
 };
 
-/*
- * Spitz Touch Screen Device
- */
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+static struct pxa2xx_spi_master spitz_spi_info = {
+        .num_chipselect = 3,
+};
 
-static unsigned long (*get_hsync_invperiod)(struct device *dev);
+static struct ads7846_platform_data spitz_ads7846_info = {
+        .model                  = 7846,
+        .vref_delay_usecs       = 100,
+        .x_plate_ohms           = 419,
+        .y_plate_ohms           = 486,
+        .gpio_pendown           = SPITZ_GPIO_TP_INT,
+};
 
-static void inline sharpsl_wait_sync(int gpio)
+static void spitz_ads7846_cs(u32 command)
 {
-        while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
-        while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
+        gpio_set_value(SPITZ_GPIO_ADS7846_CS, !(command == PXA2XX_CS_ASSERT));
 }
 
-static struct device *spitz_pxafb_dev;
+static struct pxa2xx_spi_chip spitz_ads7846_chip = {
+        .cs_control             = spitz_ads7846_cs,
+};
 
-static int is_pxafb_device(struct device * dev, void * data)
+static void spitz_bl_kick_battery(void)
 {
-        struct platform_device *pdev = container_of(dev, struct platform_device, dev);
-
-        return (strncmp(pdev->name, "pxa2xx-fb", 9) == 0);
-}
+        void (*kick_batt)(void);
 
-static unsigned long spitz_get_hsync_invperiod(void)
-{
-#ifdef CONFIG_FB_PXA
-        if (!spitz_pxafb_dev) {
-                spitz_pxafb_dev = bus_find_device(&platform_bus_type, NULL, NULL, is_pxafb_device);
-                if (!spitz_pxafb_dev)
-                        return 0;
+        kick_batt = symbol_get(sharpsl_battery_kick);
+        if (kick_batt) {
+                kick_batt();
+                symbol_put(sharpsl_battery_kick);
         }
-        if (!get_hsync_invperiod)
-                get_hsync_invperiod = symbol_get(pxafb_get_hsync_time);
-        if (!get_hsync_invperiod)
-#endif
-                return 0;
-
-        return get_hsync_invperiod(spitz_pxafb_dev);
 }
 
-static void spitz_put_hsync(void)
-{
-        put_device(spitz_pxafb_dev);
-        if (get_hsync_invperiod)
-                symbol_put(pxafb_get_hsync_time);
-        spitz_pxafb_dev = NULL;
-        get_hsync_invperiod = NULL;
-}
+static struct corgi_lcd_platform_data spitz_lcdcon_info = {
+        .init_mode              = CORGI_LCD_MODE_VGA,
+        .max_intensity          = 0x2f,
+        .default_intensity      = 0x1f,
+        .limit_mask             = 0x0b,
+        .gpio_backlight_cont    = SPITZ_GPIO_BACKLIGHT_CONT,
+        .gpio_backlight_on      = SPITZ_GPIO_BACKLIGHT_ON,
+        .kick_battery           = spitz_bl_kick_battery,
+};
 
-static void spitz_wait_hsync(void)
+static void spitz_lcdcon_cs(u32 command)
 {
-        sharpsl_wait_sync(SPITZ_GPIO_HSYNC);
+        gpio_set_value(SPITZ_GPIO_LCDCON_CS, !(command == PXA2XX_CS_ASSERT));
 }
 
-static struct resource spitzts_resources[] = {
-        [0] = {
-                .start          = SPITZ_IRQ_GPIO_TP_INT,
-                .end            = SPITZ_IRQ_GPIO_TP_INT,
-                .flags          = IORESOURCE_IRQ,
-        },
+static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
+        .cs_control     = spitz_lcdcon_cs,
 };
 
-static struct corgits_machinfo  spitz_ts_machinfo = {
-        .get_hsync_invperiod = spitz_get_hsync_invperiod,
-        .put_hsync           = spitz_put_hsync,
-        .wait_hsync          = spitz_wait_hsync,
+static void spitz_max1111_cs(u32 command)
+{
+        gpio_set_value(SPITZ_GPIO_MAX1111_CS, !(command == PXA2XX_CS_ASSERT));
+}
+
+static struct pxa2xx_spi_chip spitz_max1111_chip = {
+        .cs_control     = spitz_max1111_cs,
 };
 
-static struct platform_device spitzts_device = {
-        .name           = "corgi-ts",
-        .dev            = {
-                .parent = &spitzssp_device.dev,
-                .platform_data  = &spitz_ts_machinfo,
+static struct spi_board_info spitz_spi_devices[] = {
+        {
+                .modalias       = "ads7846",
+                .max_speed_hz   = 1200000,
+                .bus_num        = 2,
+                .chip_select    = 0,
+                .platform_data  = &spitz_ads7846_info,
+                .controller_data= &spitz_ads7846_chip,
+                .irq            = gpio_to_irq(SPITZ_GPIO_TP_INT),
+        }, {
+                .modalias       = "corgi-lcd",
+                .max_speed_hz   = 50000,
+                .bus_num        = 2,
+                .chip_select    = 1,
+                .platform_data  = &spitz_lcdcon_info,
+                .controller_data= &spitz_lcdcon_chip,
+        }, {
+                .modalias       = "max1111",
+                .max_speed_hz   = 450000,
+                .bus_num        = 2,
+                .chip_select    = 2,
+                .controller_data= &spitz_max1111_chip,
         },
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(spitzts_resources),
-        .resource       = spitzts_resources,
 };
 
+static void __init spitz_init_spi(void)
+{
+        int err;
+
+        err = gpio_request(SPITZ_GPIO_ADS7846_CS, "ADS7846_CS");
+        if (err)
+                return;
+
+        err = gpio_request(SPITZ_GPIO_LCDCON_CS, "LCDCON_CS");
+        if (err)
+                goto err_free_1;
+
+        err = gpio_request(SPITZ_GPIO_MAX1111_CS, "MAX1111_CS");
+        if (err)
+                goto err_free_2;
+
+        if (machine_is_akita()) {
+                spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
+                spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
+        }
+
+        pxa2xx_set_spi_info(2, &spitz_spi_info);
+        spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
+        return;
+
+err_free_2:
+        gpio_free(SPITZ_GPIO_LCDCON_CS);
+err_free_1:
+        gpio_free(SPITZ_GPIO_ADS7846_CS);
+}
+#else
+static inline void spitz_init_spi(void) {}
+#endif
 
 /*
  * MMC/SD Device
@@ -364,24 +416,35 @@ static int spitz_mci_init(struct device *dev, irq_handler_t spitz_detect_int, vo
 {
         int err;
 
-        /* setup GPIO for PXA27x MMC controller */
-        pxa_gpio_mode(GPIO32_MMCCLK_MD);
-        pxa_gpio_mode(GPIO112_MMCCMD_MD);
-        pxa_gpio_mode(GPIO92_MMCDAT0_MD);
-        pxa_gpio_mode(GPIO109_MMCDAT1_MD);
-        pxa_gpio_mode(GPIO110_MMCDAT2_MD);
-        pxa_gpio_mode(GPIO111_MMCDAT3_MD);
-        pxa_gpio_mode(SPITZ_GPIO_nSD_DETECT | GPIO_IN);
-        pxa_gpio_mode(SPITZ_GPIO_nSD_WP | GPIO_IN);
+        err = gpio_request(SPITZ_GPIO_nSD_DETECT, "nSD_DETECT");
+        if (err)
+                goto err_out;
+
+        err = gpio_request(SPITZ_GPIO_nSD_WP, "nSD_WP");
+        if (err)
+                goto err_free_1;
+
+        gpio_direction_input(SPITZ_GPIO_nSD_DETECT);
+        gpio_direction_input(SPITZ_GPIO_nSD_WP);
 
         spitz_mci_platform_data.detect_delay = msecs_to_jiffies(250);
 
         err = request_irq(SPITZ_IRQ_GPIO_nSD_DETECT, spitz_detect_int,
-                          IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                          IRQF_DISABLED | IRQF_TRIGGER_RISING |
+                          IRQF_TRIGGER_FALLING,
                           "MMC card detect", data);
-        if (err)
-                printk(KERN_ERR "spitz_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
+        if (err) {
+                pr_err("%s: MMC/SD: can't request MMC card detect IRQ\n",
+                                __func__);
+                goto err_free_2;
+        }
+        return 0;
 
+err_free_2:
+        gpio_free(SPITZ_GPIO_nSD_WP);
+err_free_1:
+        gpio_free(SPITZ_GPIO_nSD_DETECT);
+err_out:
         return err;
 }
 
@@ -397,12 +460,14 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
 
 static int spitz_mci_get_ro(struct device *dev)
 {
-        return GPLR(SPITZ_GPIO_nSD_WP) & GPIO_bit(SPITZ_GPIO_nSD_WP);
+        return gpio_get_value(SPITZ_GPIO_nSD_WP);
 }
 
 static void spitz_mci_exit(struct device *dev, void *data)
 {
         free_irq(SPITZ_IRQ_GPIO_nSD_DETECT, data);
+        gpio_free(SPITZ_GPIO_nSD_WP);
+        gpio_free(SPITZ_GPIO_nSD_DETECT);
 }
 
 static struct pxamci_platform_data spitz_mci_platform_data = {
@@ -419,27 +484,24 @@ static struct pxamci_platform_data spitz_mci_platform_data = {
  */
 static int spitz_ohci_init(struct device *dev)
 {
-        /* Only Port 2 is connected */
-        pxa_gpio_mode(SPITZ_GPIO_USB_CONNECT | GPIO_IN);
-        pxa_gpio_mode(SPITZ_GPIO_USB_HOST | GPIO_OUT);
-        pxa_gpio_mode(SPITZ_GPIO_USB_DEVICE | GPIO_IN);
-
-        /* Setup USB Port 2 Output Control Register */
-        UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
-
-        GPSR(SPITZ_GPIO_USB_HOST) = GPIO_bit(SPITZ_GPIO_USB_HOST);
+        int err;
 
-        UHCHR = (UHCHR) &
-                ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
+        err = gpio_request(SPITZ_GPIO_USB_HOST, "USB_HOST");
+        if (err)
+                return err;
 
-        UHCRHDA |= UHCRHDA_NOCP;
+        /* Only Port 2 is connected
+         * Setup USB Port 2 Output Control Register
+         */
+        UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
 
-        return 0;
+        return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
 }
 
 static struct pxaohci_platform_data spitz_ohci_platform_data = {
         .port_mode      = PMM_NPS_MODE,
         .init           = spitz_ohci_init,
+        .flags          = ENABLE_PORT_ALL | NO_OC_PROTECTION,
         .power_budget   = 150,
 };
 
@@ -447,29 +509,50 @@ static struct pxaohci_platform_data spitz_ohci_platform_data = {
 /*
  * Irda
  */
+static int spitz_irda_startup(struct device *dev)
+{
+        int rc;
+
+        rc = gpio_request(SPITZ_GPIO_IR_ON, "IrDA on");
+        if (rc)
+                goto err;
+
+        rc = gpio_direction_output(SPITZ_GPIO_IR_ON, 1);
+        if (rc)
+                goto err_dir;
+
+        return 0;
+
+err_dir:
+        gpio_free(SPITZ_GPIO_IR_ON);
+err:
+        return rc;
+}
+
+static void spitz_irda_shutdown(struct device *dev)
+{
+        gpio_free(SPITZ_GPIO_IR_ON);
+}
+
 static void spitz_irda_transceiver_mode(struct device *dev, int mode)
 {
-        if (mode & IR_OFF)
-                set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_IR_ON);
-        else
-                reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_IR_ON);
+        gpio_set_value(SPITZ_GPIO_IR_ON, mode & IR_OFF);
         pxa2xx_transceiver_mode(dev, mode);
 }
 
 #ifdef CONFIG_MACH_AKITA
 static void akita_irda_transceiver_mode(struct device *dev, int mode)
 {
-        if (mode & IR_OFF)
-                akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_IR_ON);
-        else
-                akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_IR_ON);
+        gpio_set_value(AKITA_GPIO_IR_ON, mode & IR_OFF);
         pxa2xx_transceiver_mode(dev, mode);
 }
 #endif
 
 static struct pxaficp_platform_data spitz_ficp_platform_data = {
-        .transceiver_cap  = IR_SIRMODE | IR_OFF,
-        .transceiver_mode = spitz_irda_transceiver_mode,
+        .transceiver_cap        = IR_SIRMODE | IR_OFF,
+        .transceiver_mode       = spitz_irda_transceiver_mode,
+        .startup                = spitz_irda_startup,
+        .shutdown               = spitz_irda_shutdown,
 };
 
 
@@ -477,14 +560,6 @@ static struct pxaficp_platform_data spitz_ficp_platform_data = {
  * Spitz PXA Framebuffer
  */
 
-static void spitz_lcd_power(int on, struct fb_var_screeninfo *var)
-{
-        if (on)
-                corgi_lcdtg_hw_init(var->xres);
-        else
-                corgi_lcdtg_suspend();
-}
-
 static struct pxafb_mode_info spitz_pxafb_modes[] = {
 {
         .pixclock       = 19231,
@@ -517,18 +592,13 @@ static struct pxafb_mach_info spitz_pxafb_info = {
         .modes          = &spitz_pxafb_modes[0],
         .num_modes      = 2,
         .fixed_modes    = 1,
-        .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act | LCCR0_LDDALT | LCCR0_OUC | LCCR0_CMDIM | LCCR0_RDSTM,
-        .lccr3          = LCCR3_PixRsEdg | LCCR3_OutEnH,
-        .pxafb_lcd_power = spitz_lcd_power,
+        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
 };
 
 
 static struct platform_device *devices[] __initdata = {
         &spitzscoop_device,
-        &spitzssp_device,
         &spitzkbd_device,
-        &spitzts_device,
-        &spitzbl_device,
         &spitzled_device,
 };
 
@@ -548,63 +618,32 @@ static void spitz_restart(char mode)
 
 static void __init common_init(void)
 {
-        init_gpio_reset(SPITZ_GPIO_ON_RESET);
+        init_gpio_reset(SPITZ_GPIO_ON_RESET, 1);
         pm_power_off = spitz_poweroff;
         arm_pm_restart = spitz_restart;
 
         PMCR = 0x00;
 
-        /* setup sleep mode values */
-        PWER  = 0x00000002;
-        PFER  = 0x00000000;
-        PRER  = 0x00000002;
-        PGSR0 = 0x0158C000;
-        PGSR1 = 0x00FF0080;
-        PGSR2 = 0x0001C004;
-
         /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
         PCFR |= PCFR_OPDE;
 
-        corgi_ssp_set_machinfo(&spitz_ssp_machinfo);
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
 
-        pxa_gpio_mode(SPITZ_GPIO_HSYNC | GPIO_IN);
+        spitz_init_spi();
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
         pxa_set_mci_info(&spitz_mci_platform_data);
         pxa_set_ohci_info(&spitz_ohci_platform_data);
         pxa_set_ficp_info(&spitz_ficp_platform_data);
-        set_pxa_fb_parent(&spitzssp_device.dev);
         set_pxa_fb_info(&spitz_pxafb_info);
         pxa_set_i2c_info(NULL);
 }
 
 #if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
-static void spitz_bl_set_intensity(int intensity)
-{
-        if (intensity > 0x10)
-                intensity += 0x10;
-
-        /* Bits 0-4 are accessed via the SSP interface */
-        corgi_ssp_blduty_set(intensity & 0x1f);
-
-        /* Bit 5 is via SCOOP */
-        if (intensity & 0x0020)
-                reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
-        else
-                set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_CONT);
-
-        if (intensity)
-                set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
-        else
-                reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_BACKLIGHT_ON);
-}
-
 static void __init spitz_init(void)
 {
         platform_scoop_config = &spitz_pcmcia_config;
 
-        spitz_bl_machinfo.set_bl_intensity = spitz_bl_set_intensity;
-
         common_init();
 
         platform_device_register(&spitzscoop2_device);
@@ -615,32 +654,17 @@ static void __init spitz_init(void)
 /*
  * Akita IO Expander
  */
-struct platform_device akitaioexp_device = {
-        .name           = "akita-ioexp",
-        .id             = -1,
+static struct pca953x_platform_data akita_ioexp = {
+        .gpio_base              = AKITA_IOEXP_GPIO_BASE,
 };
 
-EXPORT_SYMBOL_GPL(akitaioexp_device);
-
-static void akita_bl_set_intensity(int intensity)
-{
-        if (intensity > 0x10)
-                intensity += 0x10;
-
-        /* Bits 0-4 are accessed via the SSP interface */
-        corgi_ssp_blduty_set(intensity & 0x1f);
-
-        /* Bit 5 is via IO-Expander */
-        if (intensity & 0x0020)
-                akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
-        else
-                akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_CONT);
-
-        if (intensity)
-                akita_set_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
-        else
-                akita_reset_ioexp(&akitaioexp_device.dev, AKITA_IOEXP_BACKLIGHT_ON);
-}
+static struct i2c_board_info akita_i2c_board_info[] = {
+        {
+                .type           = "max7310",
+                .addr           = 0x18,
+                .platform_data  = &akita_ioexp,
+        },
+};
 
 static void __init akita_init(void)
 {
@@ -649,11 +673,10 @@ static void __init akita_init(void)
         /* We just pretend the second element of the array doesn't exist */
         spitz_pcmcia_config.num_devs = 1;
         platform_scoop_config = &spitz_pcmcia_config;
-        spitz_bl_machinfo.set_bl_intensity = akita_bl_set_intensity;
 
-        platform_device_register(&akitaioexp_device);
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info));
 
-        spitzscoop_device.dev.parent = &akitaioexp_device.dev;
         common_init();
 }
 #endif
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 8a40505dfd28..53018db106ac 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -21,7 +21,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
-#include <asm/hardware/scoop.h>
 
 #include <mach/sharpsl.h>
 #include <mach/spitz.h>
@@ -48,44 +47,35 @@ static void spitz_charger_init(void)
 
 static void spitz_measure_temp(int on)
 {
-        if (on)
-                set_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_ADC_TEMP_ON);
-        else
-                reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_ADC_TEMP_ON);
+        gpio_set_value(SPITZ_GPIO_ADC_TEMP_ON, on);
 }
 
 static void spitz_charge(int on)
 {
         if (on) {
                 if (sharpsl_pm.flags & SHARPSL_SUSPENDED) {
-                        set_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_JK_B);
-                        reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_CHRG_ON);
+                        gpio_set_value(SPITZ_GPIO_JK_B, 1);
+                        gpio_set_value(SPITZ_GPIO_CHRG_ON, 0);
                 } else {
-                        reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_JK_B);
-                        reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_CHRG_ON);
+                        gpio_set_value(SPITZ_GPIO_JK_B, 0);
+                        gpio_set_value(SPITZ_GPIO_CHRG_ON, 0);
                 }
         } else {
-                reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_JK_B);
-                set_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_CHRG_ON);
+                gpio_set_value(SPITZ_GPIO_JK_B, 0);
+                gpio_set_value(SPITZ_GPIO_CHRG_ON, 1);
         }
 }
 
 static void spitz_discharge(int on)
 {
-        if (on)
-                set_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_JK_A);
-        else
-                reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_JK_A);
+        gpio_set_value(SPITZ_GPIO_JK_A, on);
 }
 
 /* HACK - For unknown reasons, accurate voltage readings are only made with a load
    on the power bus which the green led on spitz provides */
 static void spitz_discharge1(int on)
 {
-        if (on)
-                set_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_LED_GREEN);
-        else
-                reset_scoop_gpio(&spitzscoop_device.dev, SPITZ_SCP_LED_GREEN);
+        gpio_set_value(SPITZ_GPIO_LED_GREEN, on);
 }
 
 static void spitz_presuspend(void)
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
index 9bd93c5f28b2..2c31ec725688 100644
--- a/arch/arm/mach-pxa/ssp.c
+++ b/arch/arm/mach-pxa/ssp.c
@@ -28,8 +28,8 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/ssp.h>
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 67e18509d7bf..f8a9a62959e5 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -17,9 +17,9 @@
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
 #include <linux/sched.h>
+#include <linux/cnt32_to_63.h>
 
 #include <asm/div64.h>
-#include <asm/cnt32_to_63.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include <mach/pxa-regs.h>
@@ -155,7 +155,7 @@ static void __init pxa_timer_init(void)
         OIER = 0;
         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 
-        if (cpu_is_pxa21x() || cpu_is_pxa25x())
+        if (cpu_is_pxa25x())
                 clock_tick_rate = 3686400;
         else if (machine_is_mainstone())
                 clock_tick_rate = 3249600;
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 5dab30eafddc..130e37e4ebdd 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -50,6 +50,7 @@
 #include <asm/mach/sharpsl_param.h>
 
 #include "generic.h"
+#include "clock.h"
 #include "devices.h"
 
 static unsigned long tosa_pin_config[] = {
@@ -521,6 +522,14 @@ static struct gpio_keys_button tosa_gpio_keys[] = {
                 .wakeup = 1,
                 .active_low = 1,
         },
+        {
+                .type   = EV_SW,
+                .code   = SW_HEADPHONE_INSERT,
+                .gpio   = TOSA_GPIO_EAR_IN,
+                .desc   = "HeadPhone insert",
+                .active_low = 1,
+                .debounce_interval = 300,
+        },
 };
 
 static struct gpio_keys_platform_data tosa_gpio_keys_platform_data = {
@@ -772,7 +781,7 @@ static void __init tosa_init(void)
         gpio_set_wake(MFP_PIN_GPIO1, 1);
         /* We can't pass to gpio-keys since it will drop the Reset altfunc */
 
-        init_gpio_reset(TOSA_GPIO_ON_RESET);
+        init_gpio_reset(TOSA_GPIO_ON_RESET, 0);
 
         pm_power_off = tosa_poweroff;
         arm_pm_restart = tosa_restart;
@@ -792,6 +801,8 @@ static void __init tosa_init(void)
         pxa_set_i2c_info(NULL);
         platform_scoop_config = &tosa_pcmcia_config;
 
+        clk_add_alias("CLK_CK3P6MI", &tc6393xb_device.dev, "GPIO11_CLK", NULL);
+
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 3ed757e6bcc8..a13dbf3c2c05 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -22,8 +22,8 @@
 #include <linux/fb.h>
 #include <linux/ioport.h>
 #include <linux/delay.h>
-#include <linux/serial_8250.h>
-#include <linux/mtd/mtd.h>
+#include <linux/gpio.h>
+#include <linux/dm9000.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 
@@ -31,7 +31,6 @@
 #include <asm/setup.h>
 #include <asm/memory.h>
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 
@@ -40,41 +39,148 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 
+#include <mach/hardware.h>
 #include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/pxa2xx_spi.h>
 #include <mach/trizeps4.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
+#include <mach/i2c.h>
 
 #include "generic.h"
 #include "devices.h"
 
-/********************************************************************************************
+/*      comment out the following line if you want to use the
+ *      Standard UART from PXA for serial / irda transmission
+ *      and acivate it if you have status leds connected */
+#define STATUS_LEDS_ON_STUART_PINS 1
+
+/*****************************************************************************
+ * MultiFunctionPins of CPU
+ *****************************************************************************/
+static unsigned long trizeps4_pin_config[] __initdata = {
+        /* Chip Selects */
+        GPIO15_nCS_1,           /* DiskOnChip CS */
+        GPIO93_GPIO,            /* TRIZEPS4_DOC_IRQ */
+        GPIO94_GPIO,            /* DOC lock */
+
+        GPIO78_nCS_2,           /* DM9000 CS */
+        GPIO101_GPIO,           /* TRIZEPS4_ETH_IRQ */
+
+        GPIO79_nCS_3,           /* Logic CS */
+        GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,       /* Logic irq */
+
+        /* LCD - 16bpp Active TFT */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+
+        /* UART */
+        GPIO9_FFUART_CTS,
+        GPIO10_FFUART_DCD,
+        GPIO16_FFUART_TXD,
+        GPIO33_FFUART_DSR,
+        GPIO38_FFUART_RI,
+        GPIO82_FFUART_DTR,
+        GPIO83_FFUART_RTS,
+        GPIO96_FFUART_RXD,
+
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+#ifdef STATUS_LEDS_ON_STUART_PINS
+        GPIO46_GPIO,
+        GPIO47_GPIO,
+#else
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+#endif
+        /* PCMCIA */
+        GPIO11_GPIO,                    /* TRIZEPS4_CD_IRQ */
+        GPIO13_GPIO,                    /* TRIZEPS4_READY_NINT */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO54_nPCE_2,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+        GPIO102_nPCE_1,
+        GPIO104_PSKTSEL,
+
+        /* MultiMediaCard */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO12_GPIO,                    /* TRIZEPS4_MMC_IRQ */
+
+        /* USB OHCI */
+        GPIO88_USBH1_PWR,               /* USBHPWR1 */
+        GPIO89_USBH1_PEN,               /* USBHPEN1 */
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+};
+
+static unsigned long trizeps4wl_pin_config[] __initdata = {
+        /* SSP 2 */
+        GPIO14_SSP2_SFRM,
+        GPIO19_SSP2_SCLK,
+        GPIO53_GPIO,                    /* TRIZEPS4_SPI_IRQ */
+        GPIO86_SSP2_RXD,
+        GPIO87_SSP2_TXD,
+};
+
+/****************************************************************************
  * ONBOARD FLASH
- ********************************************************************************************/
+ ****************************************************************************/
 static struct mtd_partition trizeps4_partitions[] = {
         {
                 .name =         "Bootloader",
                 .offset =       0x00000000,
                 .size =         0x00040000,
                 .mask_flags =   MTD_WRITEABLE  /* force read-only */
-        },{
+        }, {
                 .name =         "Backup",
                 .offset =       0x00040000,
                 .size =         0x00040000,
-        },{
+        }, {
                 .name =         "Image",
                 .offset =       0x00080000,
                 .size =         0x01080000,
-        },{
+        }, {
                 .name =         "IPSM",
                 .offset =       0x01100000,
                 .size =         0x00e00000,
-        },{
+        }, {
                 .name =         "Registry",
                 .offset =       0x01f00000,
                 .size =         MTDPART_SIZ_FULL,
@@ -105,9 +211,9 @@ static struct platform_device flash_device = {
         .num_resources = 1,
 };
 
-/********************************************************************************************
+/****************************************************************************
  * DAVICOM DM9000 Ethernet
- ********************************************************************************************/
+ ****************************************************************************/
 static struct resource dm9000_resources[] = {
         [0] = {
                 .start  = TRIZEPS4_ETH_PHYS+0x300,
@@ -122,67 +228,68 @@ static struct resource dm9000_resources[] = {
         [2] = {
                 .start  = TRIZEPS4_ETH_IRQ,
                 .end    = TRIZEPS4_ETH_IRQ,
-                .flags  = (IORESOURCE_IRQ | IRQ_TYPE_EDGE_RISING),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         },
 };
 
+static struct dm9000_plat_data tri_dm9000_platdata = {
+        .flags          = DM9000_PLATF_32BITONLY,
+};
+
 static struct platform_device dm9000_device = {
         .name           = "dm9000",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(dm9000_resources),
         .resource       = dm9000_resources,
+        .dev            = {
+                .platform_data = &tri_dm9000_platdata,
+        }
 };
 
-/********************************************************************************************
- * PXA270 serial ports
- ********************************************************************************************/
-static struct plat_serial8250_port tri_serial_ports[] = {
-#ifdef CONFIG_SERIAL_PXA
-        /* this uses the own PXA driver */
+/****************************************************************************
+ * LED's on GPIO pins of PXA
+ ****************************************************************************/
+static struct gpio_led trizeps4_led[] = {
+#ifdef STATUS_LEDS_ON_STUART_PINS
         {
-                0,
-        },
-#else
-        /* this uses the generic 8520 driver */
-        [0] = {
-                .membase        = (void *)&FFUART,
-                .irq            = IRQ_FFUART,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-                .uartclk        = (921600*16),
-        },
-        [1] = {
-                .membase        = (void *)&BTUART,
-                .irq            = IRQ_BTUART,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-                .uartclk        = (921600*16),
+                .name = "led0:orange:heartbeat",        /* */
+                .default_trigger = "heartbeat",
+                .gpio = GPIO_HEARTBEAT_LED,
+                .active_low = 1,
         },
         {
-                0,
+                .name = "led1:yellow:cpubusy",          /* */
+                .default_trigger = "cpu-busy",
+                .gpio = GPIO_SYS_BUSY_LED,
+                .active_low = 1,
         },
 #endif
 };
 
-static struct platform_device uart_devices = {
-        .name           = "serial8250",
-        .id             = 0,
+static struct gpio_led_platform_data trizeps4_led_data = {
+        .leds           = trizeps4_led,
+        .num_leds       = ARRAY_SIZE(trizeps4_led),
+};
+
+static struct platform_device leds_devices = {
+        .name           = "leds-gpio",
+        .id             = -1,
         .dev            = {
-                .platform_data  = tri_serial_ports,
+                .platform_data  = &trizeps4_led_data,
         },
-        .num_resources  = 0,
-        .resource       = NULL,
 };
 
-static struct platform_device * trizeps4_devices[] __initdata = {
+static struct platform_device *trizeps4_devices[] __initdata = {
         &flash_device,
-        &uart_devices,
         &dm9000_device,
+        &leds_devices,
+};
+
+static struct platform_device *trizeps4wl_devices[] __initdata = {
+        &flash_device,
+        &leds_devices,
 };
 
-#ifdef CONFIG_MACH_TRIZEPS4_CONXS
 static short trizeps_conxs_bcr;
 
 /* PCCARD power switching supports only 3,3V */
@@ -192,108 +299,63 @@ void board_pcmcia_power(int power)
                 /* switch power on, put in reset and enable buffers */
                 trizeps_conxs_bcr |= power;
                 trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
-                trizeps_conxs_bcr &= ~(ConXS_BCR_CF_BUF_EN);
-                ConXS_BCR = trizeps_conxs_bcr;
+                trizeps_conxs_bcr &= ~ConXS_BCR_CF_BUF_EN;
+                BCR_writew(trizeps_conxs_bcr);
                 /* wait a little */
                 udelay(2000);
                 /* take reset away */
-                trizeps_conxs_bcr &= ~(ConXS_BCR_CF_RESET);
-                ConXS_BCR = trizeps_conxs_bcr;
+                trizeps_conxs_bcr &= ~ConXS_BCR_CF_RESET;
+                BCR_writew(trizeps_conxs_bcr);
                 udelay(2000);
         } else {
                 /* put in reset */
                 trizeps_conxs_bcr |= ConXS_BCR_CF_RESET;
-                ConXS_BCR = trizeps_conxs_bcr;
+                BCR_writew(trizeps_conxs_bcr);
                 udelay(1000);
                 /* switch power off */
-                trizeps_conxs_bcr &= ~(0xf);
-                ConXS_BCR = trizeps_conxs_bcr;
-
+                trizeps_conxs_bcr &= ~0xf;
+                BCR_writew(trizeps_conxs_bcr);
         }
-        pr_debug("%s: o%s 0x%x\n", __func__, power ? "n": "ff", trizeps_conxs_bcr);
+        pr_debug("%s: o%s 0x%x\n", __func__, power ? "n" : "ff",
+                        trizeps_conxs_bcr);
 }
+EXPORT_SYMBOL(board_pcmcia_power);
 
 /* backlight power switching for LCD panel */
 static void board_backlight_power(int on)
 {
-        if (on) {
+        if (on)
                 trizeps_conxs_bcr |= ConXS_BCR_L_DISP;
-        } else {
+        else
                 trizeps_conxs_bcr &= ~ConXS_BCR_L_DISP;
-        }
-        pr_debug("%s: o%s 0x%x\n", __func__, on ? "n" : "ff", trizeps_conxs_bcr);
-        ConXS_BCR = trizeps_conxs_bcr;
-}
 
-/* Powersupply for MMC/SD cardslot */
-static void board_mci_power(struct device *dev, unsigned int vdd)
-{
-        struct pxamci_platform_data* p_d = dev->platform_data;
-
-        if (( 1 << vdd) & p_d->ocr_mask) {
-                pr_debug("%s: on\n", __func__);
-                /* FIXME fill in values here */
-        } else {
-                pr_debug("%s: off\n", __func__);
-                /* FIXME fill in values here */
-        }
-}
-
-static short trizeps_conxs_ircr;
-
-/* Switch modes and Power for IRDA receiver */
-static void board_irda_mode(struct device *dev, int mode)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-        if (mode & IR_SIRMODE) {
-                /* Slow mode */
-                trizeps_conxs_ircr &= ~ConXS_IRCR_MODE;
-        } else if (mode & IR_FIRMODE) {
-                /* Fast mode */
-                trizeps_conxs_ircr |= ConXS_IRCR_MODE;
-        }
-        pxa2xx_transceiver_mode(dev, mode);
-        if (mode & IR_OFF) {
-                trizeps_conxs_ircr |= ConXS_IRCR_SD;
-        } else {
-                trizeps_conxs_ircr &= ~ConXS_IRCR_SD;
-        }
-        /* FIXME write values to register */
-        local_irq_restore(flags);
+        pr_debug("%s: o%s 0x%x\n", __func__, on ? "n" : "ff",
+                        trizeps_conxs_bcr);
+        BCR_writew(trizeps_conxs_bcr);
 }
 
-#else
-/* for other baseboards define dummies */
-void board_pcmcia_power(int power)      {;}
-#define board_backlight_power           NULL
-#define board_mci_power                 NULL
-#define board_irda_mode                 NULL
-
-#endif          /* CONFIG_MACH_TRIZEPS4_CONXS */
-EXPORT_SYMBOL(board_pcmcia_power);
+/* a I2C based RTC is known on CONXS board */
+static struct i2c_board_info trizeps4_i2c_devices[] __initdata = {
+        { I2C_BOARD_INFO("rtc-pcf8593", 0x51) }
+};
 
-static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int, void *data)
+/****************************************************************************
+ * MMC card slot external to module
+ ****************************************************************************/
+static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int,
+                void *data)
 {
         int err;
-        /* setup GPIO for PXA27x MMC controller */
-        pxa_gpio_mode(GPIO32_MMCCLK_MD);
-        pxa_gpio_mode(GPIO112_MMCCMD_MD);
-        pxa_gpio_mode(GPIO92_MMCDAT0_MD);
-        pxa_gpio_mode(GPIO109_MMCDAT1_MD);
-        pxa_gpio_mode(GPIO110_MMCDAT2_MD);
-        pxa_gpio_mode(GPIO111_MMCDAT3_MD);
-
-        pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);
 
         err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int,
-                          IRQF_DISABLED | IRQF_TRIGGER_RISING,
-                          "MMC card detect", data);
-        if (err)
-                printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
-
-        return err;
+                IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_SAMPLE_RANDOM,
+                "MMC card detect", data);
+        if (err) {
+                printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request"
+                                                "MMC card detect IRQ\n");
+                return -1;
+        }
+        return 0;
 }
 
 static void trizeps4_mci_exit(struct device *dev, void *data)
@@ -303,39 +365,69 @@ static void trizeps4_mci_exit(struct device *dev, void *data)
 
 static struct pxamci_platform_data trizeps4_mci_platform_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .detect_delay   = 1,
         .init           = trizeps4_mci_init,
         .exit           = trizeps4_mci_exit,
-        .setpower       = board_mci_power,
+        .get_ro         = NULL, /* write-protection not supported */
+        .setpower       = NULL, /* power-switching not supported */
 };
 
-static struct pxaficp_platform_data trizeps4_ficp_platform_data = {
-        .transceiver_cap  = IR_SIRMODE | IR_FIRMODE | IR_OFF,
-        .transceiver_mode = board_irda_mode,
-};
+/****************************************************************************
+ * IRDA mode switching on stuart
+ ****************************************************************************/
+#ifndef STATUS_LEDS_ON_STUART_PINS
+static short trizeps_conxs_ircr;
 
-static int trizeps4_ohci_init(struct device *dev)
+static int trizeps4_irda_startup(struct device *dev)
 {
-        /* setup Port1 GPIO pin. */
-        pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);  /* USBHPWR1 */
-        pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
-
-        /* Set the Power Control Polarity Low and Power Sense
-           Polarity Low to active low. */
-        UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
-                ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
-
+        trizeps_conxs_ircr &= ~ConXS_IRCR_SD;
+        IRCR_writew(trizeps_conxs_ircr);
         return 0;
 }
 
-static void trizeps4_ohci_exit(struct device *dev)
+static void trizeps4_irda_shutdown(struct device *dev)
+{
+        trizeps_conxs_ircr |= ConXS_IRCR_SD;
+        IRCR_writew(trizeps_conxs_ircr);
+}
+
+static void trizeps4_irda_transceiver_mode(struct device *dev, int mode)
 {
-        ;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        /* Switch mode */
+        if (mode & IR_SIRMODE)
+                trizeps_conxs_ircr &= ~ConXS_IRCR_MODE; /* Slow mode */
+        else if (mode & IR_FIRMODE) {
+                trizeps_conxs_ircr |= ConXS_IRCR_MODE;  /* Fast mode */
+
+        /* Switch power */
+        if (mode & IR_OFF)
+                trizeps_conxs_ircr |= ConXS_IRCR_SD;
+        else
+                trizeps_conxs_ircr &= ~ConXS_IRCR_SD;
+
+        IRCR_writew(trizeps_conxs_ircr);
+        local_irq_restore(flags);
+
+        pxa2xx_transceiver_mode(dev, mode);
 }
 
+static struct pxaficp_platform_data trizeps4_ficp_platform_data = {
+        .transceiver_cap        = IR_SIRMODE | IR_FIRMODE | IR_OFF,
+        .transceiver_mode       = trizeps4_irda_transceiver_mode,
+        .startup                = trizeps4_irda_startup,
+        .shutdown               = trizeps4_irda_shutdown,
+};
+#endif
+
+/****************************************************************************
+ * OHCI USB port
+ ****************************************************************************/
 static struct pxaohci_platform_data trizeps4_ohci_platform_data = {
         .port_mode      = PMM_PERPORT_MODE,
-        .init           = trizeps4_ohci_init,
-        .exit           = trizeps4_ohci_exit,
+        .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
 };
 
 static struct map_desc trizeps4_io_desc[] __initdata = {
@@ -372,105 +464,80 @@ static struct map_desc trizeps4_io_desc[] __initdata = {
 };
 
 static struct pxafb_mode_info sharp_lcd_mode = {
-    .pixclock           = 78000,
-    .xres               = 640,
-    .yres               = 480,
-    .bpp                = 8,
-    .hsync_len          = 4,
-    .left_margin        = 4,
-    .right_margin       = 4,
-    .vsync_len          = 2,
-    .upper_margin       = 0,
-    .lower_margin       = 0,
-    .sync               = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-    .cmap_greyscale     = 0,
+        .pixclock       = 78000,
+        .xres           = 640,
+        .yres           = 480,
+        .bpp            = 8,
+        .hsync_len      = 4,
+        .left_margin    = 4,
+        .right_margin   = 4,
+        .vsync_len      = 2,
+        .upper_margin   = 0,
+        .lower_margin   = 0,
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+        .cmap_greyscale = 0,
 };
 
 static struct pxafb_mach_info sharp_lcd = {
-    .modes              = &sharp_lcd_mode,
-    .num_modes  = 1,
-    .cmap_inverse       = 0,
-    .cmap_static        = 0,
-    .lccr0              = LCCR0_Color | LCCR0_Pas | LCCR0_Dual,
-    .lccr3              = 0x0340ff02,
-    .pxafb_backlight_power = board_backlight_power,
+        .modes          = &sharp_lcd_mode,
+        .num_modes      = 1,
+        .lcd_conn       = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL,
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+        .pxafb_backlight_power = board_backlight_power,
 };
 
 static struct pxafb_mode_info toshiba_lcd_mode = {
-    .pixclock           = 39720,
-    .xres               = 640,
-    .yres               = 480,
-    .bpp                = 8,
-    .hsync_len          = 63,
-    .left_margin        = 12,
-    .right_margin       = 12,
-    .vsync_len          = 4,
-    .upper_margin       = 32,
-    .lower_margin       = 10,
-    .sync               = 0,
-    .cmap_greyscale     = 0,
+        .pixclock       = 39720,
+        .xres           = 640,
+        .yres           = 480,
+        .bpp            = 8,
+        .hsync_len      = 63,
+        .left_margin    = 12,
+        .right_margin   = 12,
+        .vsync_len      = 4,
+        .upper_margin   = 32,
+        .lower_margin   = 10,
+        .sync           = 0,
+        .cmap_greyscale = 0,
 };
 
 static struct pxafb_mach_info toshiba_lcd = {
-    .modes              = &toshiba_lcd_mode,
-    .num_modes  = 1,
-    .cmap_inverse       = 0,
-    .cmap_static        = 0,
-    .lccr0              = LCCR0_Color | LCCR0_Act,
-    .lccr3              = 0x03400002,
-    .pxafb_backlight_power = board_backlight_power,
+        .modes          = &toshiba_lcd_mode,
+        .num_modes      = 1,
+        .lcd_conn       = (LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL),
+        .cmap_inverse   = 0,
+        .cmap_static    = 0,
+        .pxafb_backlight_power = board_backlight_power,
 };
 
 static void __init trizeps4_init(void)
 {
-        platform_add_devices(trizeps4_devices, ARRAY_SIZE(trizeps4_devices));
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(trizeps4_pin_config));
+        if (machine_is_trizeps4wl()) {
+                pxa2xx_mfp_config(ARRAY_AND_SIZE(trizeps4wl_pin_config));
+                platform_add_devices(trizeps4wl_devices,
+                                        ARRAY_SIZE(trizeps4wl_devices));
+        } else {
+                platform_add_devices(trizeps4_devices,
+                                        ARRAY_SIZE(trizeps4_devices));
+        }
 
-/*      set_pxa_fb_info(&sharp_lcd); */
-        set_pxa_fb_info(&toshiba_lcd);
+        if (0)  /* dont know how to determine LCD */
+                set_pxa_fb_info(&sharp_lcd);
+        else
+                set_pxa_fb_info(&toshiba_lcd);
 
         pxa_set_mci_info(&trizeps4_mci_platform_data);
+#ifndef STATUS_LEDS_ON_STUART_PINS
         pxa_set_ficp_info(&trizeps4_ficp_platform_data);
+#endif
         pxa_set_ohci_info(&trizeps4_ohci_platform_data);
         pxa_set_ac97_info(NULL);
-}
-
-static void __init trizeps4_map_io(void)
-{
-        pxa_map_io();
-        iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
-
-        /* for DiskOnChip */
-        pxa_gpio_mode(GPIO15_nCS_1_MD);
-
-        /* for off-module PIC on ConXS board */
-        pxa_gpio_mode(GPIO_PIC | GPIO_IN);
-
-        /* UCB1400 irq */
-        pxa_gpio_mode(GPIO_UCB1400 | GPIO_IN);
-
-        /* for DM9000 LAN */
-        pxa_gpio_mode(GPIO78_nCS_2_MD);
-        pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
-
-        /* for PCMCIA device */
-        pxa_gpio_mode(GPIO_PCD | GPIO_IN);
-        pxa_gpio_mode(GPIO_PRDY | GPIO_IN);
-
-        /* for I2C adapter */
-        pxa_gpio_mode(GPIO117_I2CSCL_MD);
-        pxa_gpio_mode(GPIO118_I2CSDA_MD);
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, trizeps4_i2c_devices,
+                                        ARRAY_SIZE(trizeps4_i2c_devices));
 
-        /* MMC_DET s.o. */
-        pxa_gpio_mode(GPIO_MMC_DET | GPIO_IN);
-
-        /* whats that for ??? */
-        pxa_gpio_mode(GPIO79_nCS_3_MD);
-
-#ifdef CONFIG_LEDS
-        pxa_gpio_mode( GPIO_SYS_BUSY_LED  | GPIO_OUT);          /* LED1 */
-        pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT);          /* LED2 */
-#endif
-#ifdef CONFIG_MACH_TRIZEPS4_CONXS
 #ifdef CONFIG_IDE_PXA_CF
         /* if boot direct from compact flash dont disable power */
         trizeps_conxs_bcr = 0x0009;
@@ -478,18 +545,24 @@ static void __init trizeps4_map_io(void)
         /* this is the reset value */
         trizeps_conxs_bcr = 0x00A0;
 #endif
-        ConXS_BCR = trizeps_conxs_bcr;
-#endif
+        BCR_writew(trizeps_conxs_bcr);
+        board_backlight_power(1);
+}
+
+static void __init trizeps4_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
 
-#warning FIXME - accessing PM registers directly is deprecated
-        PWER  = 0x00000002;
-        PFER  = 0x00000000;
-        PRER  = 0x00000002;
-        PGSR0 = 0x0158C000;
-        PGSR1 = 0x00FF0080;
-        PGSR2 = 0x0001C004;
-        /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
-        PCFR |= PCFR_OPDE;
+        if ((MSC0 & 0x8) && (BOOT_DEF & 0x1)) {
+                /* if flash is 16 bit wide its a Trizeps4 WL */
+                __machine_arch_type = MACH_TYPE_TRIZEPS4WL;
+                trizeps4_flash_data[0].width = 2;
+        } else {
+                /* if flash is 32 bit wide its a Trizeps4 */
+                __machine_arch_type = MACH_TYPE_TRIZEPS4;
+                trizeps4_flash_data[0].width = 4;
+        }
 }
 
 MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
@@ -503,3 +576,13 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
         .timer          = &pxa_timer,
 MACHINE_END
 
+MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
+        /* MAINTAINER("Jürgen Schindele") */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = TRIZEPS4_SDRAM_BASE + 0x100,
+        .init_machine   = trizeps4_init,
+        .map_io         = trizeps4_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
new file mode 100644
index 000000000000..d7632f63603c
--- /dev/null
+++ b/arch/arm/mach-pxa/viper.c
@@ -0,0 +1,951 @@
+/*
+ *  linux/arch/arm/mach-pxa/viper.c
+ *
+ *  Support for the Arcom VIPER SBC.
+ *
+ *  Author:     Ian Campbell
+ *  Created:    Feb 03, 2003
+ *  Copyright:  Arcom Control Systems
+ *
+ *  Maintained by Marc Zyngier <maz@misterjones.org>
+ *                             <marc.zyngier@altran.com>
+ *
+ * Based on lubbock.c:
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include <linux/memory.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/major.h>
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/sched.h>
+#include <linux/gpio.h>
+#include <linux/i2c-gpio.h>
+#include <linux/serial_8250.h>
+#include <linux/smc91x.h>
+#include <linux/pwm_backlight.h>
+#include <linux/usb/isp116x.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/bitfield.h>
+#include <mach/audio.h>
+#include <mach/pxafb.h>
+#include <mach/mfp-pxa25x.h>
+#include <mach/i2c.h>
+#include <mach/viper.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include "generic.h"
+#include "devices.h"
+
+static unsigned int icr;
+
+static void viper_icr_set_bit(unsigned int bit)
+{
+        icr |= bit;
+        VIPER_ICR = icr;
+}
+
+static void viper_icr_clear_bit(unsigned int bit)
+{
+        icr &= ~bit;
+        VIPER_ICR = icr;
+}
+
+/* This function is used from the pcmcia module to reset the CF */
+void viper_cf_rst(int state)
+{
+        if (state)
+                viper_icr_set_bit(VIPER_ICR_CF_RST);
+        else
+                viper_icr_clear_bit(VIPER_ICR_CF_RST);
+}
+EXPORT_SYMBOL(viper_cf_rst);
+
+/*
+ * The CPLD version register was not present on VIPER boards prior to
+ * v2i1. On v1 boards where the version register is not present we
+ * will just read back the previous value from the databus.
+ *
+ * Therefore we do two reads. The first time we write 0 to the
+ * (read-only) register before reading and the second time we write
+ * 0xff first. If the two reads do not match or they read back as 0xff
+ * or 0x00 then we have version 1 hardware.
+ */
+static u8 viper_hw_version(void)
+{
+        u8 v1, v2;
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        VIPER_VERSION = 0;
+        v1 = VIPER_VERSION;
+        VIPER_VERSION = 0xff;
+        v2 = VIPER_VERSION;
+
+        v1 = (v1 != v2 || v1 == 0xff) ? 0 : v1;
+
+        local_irq_restore(flags);
+        return v1;
+}
+
+/* CPU sysdev */
+static int viper_cpu_suspend(struct sys_device *sysdev, pm_message_t state)
+{
+        viper_icr_set_bit(VIPER_ICR_R_DIS);
+        return 0;
+}
+
+static int viper_cpu_resume(struct sys_device *sysdev)
+{
+        viper_icr_clear_bit(VIPER_ICR_R_DIS);
+        return 0;
+}
+
+static struct sysdev_driver viper_cpu_sysdev_driver = {
+        .suspend        = viper_cpu_suspend,
+        .resume         = viper_cpu_resume,
+};
+
+static unsigned int current_voltage_divisor;
+
+/*
+ * If force is not true then step from existing to new divisor. If
+ * force is true then jump straight to the new divisor. Stepping is
+ * used because if the jump in voltage is too large, the VCC can dip
+ * too low and the regulator cuts out.
+ *
+ * force can be used to initialize the divisor to a know state by
+ * setting the value for the current clock speed, since we are already
+ * running at that speed we know the voltage should be pretty close so
+ * the jump won't be too large
+ */
+static void viper_set_core_cpu_voltage(unsigned long khz, int force)
+{
+        int i = 0;
+        unsigned int divisor = 0;
+        const char *v;
+
+        if (khz < 200000) {
+                v = "1.0"; divisor = 0xfff;
+        } else if (khz < 300000) {
+                v = "1.1"; divisor = 0xde5;
+        } else {
+                v = "1.3"; divisor = 0x325;
+        }
+
+        pr_debug("viper: setting CPU core voltage to %sV at %d.%03dMHz\n",
+                 v, (int)khz / 1000, (int)khz % 1000);
+
+#define STEP 0x100
+        do {
+                int step;
+
+                if (force)
+                        step = divisor;
+                else if (current_voltage_divisor < divisor - STEP)
+                        step = current_voltage_divisor + STEP;
+                else if (current_voltage_divisor > divisor + STEP)
+                        step = current_voltage_divisor - STEP;
+                else
+                        step = divisor;
+                force = 0;
+
+                gpio_set_value(VIPER_PSU_CLK_GPIO, 0);
+                gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0);
+
+                for (i = 1 << 11 ; i > 0 ; i >>= 1) {
+                        udelay(1);
+
+                        gpio_set_value(VIPER_PSU_DATA_GPIO, step & i);
+                        udelay(1);
+
+                        gpio_set_value(VIPER_PSU_CLK_GPIO, 1);
+                        udelay(1);
+
+                        gpio_set_value(VIPER_PSU_CLK_GPIO, 0);
+                }
+                udelay(1);
+
+                gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 1);
+                udelay(1);
+
+                gpio_set_value(VIPER_PSU_nCS_LD_GPIO, 0);
+
+                current_voltage_divisor = step;
+        } while (current_voltage_divisor != divisor);
+}
+
+/* Interrupt handling */
+static unsigned long viper_irq_enabled_mask;
+
+static void viper_ack_irq(unsigned int irq)
+{
+        int viper_irq = irq - PXA_ISA_IRQ(0);
+
+        if (viper_irq < 8)
+                VIPER_LO_IRQ_STATUS = 1 << viper_irq;
+        else
+                VIPER_HI_IRQ_STATUS = 1 << (viper_irq - 8);
+}
+
+static void viper_mask_irq(unsigned int irq)
+{
+        viper_irq_enabled_mask &= ~(1 << (irq - PXA_ISA_IRQ(0)));
+}
+
+static void viper_unmask_irq(unsigned int irq)
+{
+        viper_irq_enabled_mask |= (1 << (irq - PXA_ISA_IRQ(0)));
+}
+
+static inline unsigned long viper_irq_pending(void)
+{
+        return (VIPER_HI_IRQ_STATUS << 8 | VIPER_LO_IRQ_STATUS) &
+                        viper_irq_enabled_mask;
+}
+
+static void viper_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long pending;
+
+        pending = viper_irq_pending();
+        do {
+                if (likely(pending)) {
+                        irq = PXA_ISA_IRQ(0) + __ffs(pending);
+                        generic_handle_irq(irq);
+                }
+                pending = viper_irq_pending();
+        } while (pending);
+}
+
+static struct irq_chip viper_irq_chip = {
+        .name   = "ISA",
+        .ack    = viper_ack_irq,
+        .mask   = viper_mask_irq,
+        .unmask = viper_unmask_irq
+};
+
+static void __init viper_init_irq(void)
+{
+        const int isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, 9, 14, 15 };
+        int irq;
+        int isa_irq;
+
+        pxa25x_init_irq();
+
+        /* setup ISA IRQs */
+        for (irq = 0; irq < ARRAY_SIZE(isa_irqs); irq++) {
+                isa_irq = isa_irqs[irq];
+                set_irq_chip(isa_irq, &viper_irq_chip);
+                set_irq_handler(isa_irq, handle_edge_irq);
+                set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
+        }
+
+        set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
+                                viper_irq_handler);
+        set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
+
+#ifndef CONFIG_SERIAL_PXA
+        /*
+         * 8250 doesn't support IRQ_TYPE being passed as part
+         * of the plat_serial8250_port structure...
+         */
+        set_irq_type(gpio_to_irq(VIPER_UARTA_GPIO), IRQ_TYPE_EDGE_RISING);
+        set_irq_type(gpio_to_irq(VIPER_UARTB_GPIO), IRQ_TYPE_EDGE_RISING);
+#endif
+}
+
+/* Flat Panel */
+static struct pxafb_mode_info fb_mode_info[] = {
+        {
+                .pixclock       = 157500,
+
+                .xres           = 320,
+                .yres           = 240,
+
+                .bpp            = 16,
+
+                .hsync_len      = 63,
+                .left_margin    = 7,
+                .right_margin   = 13,
+
+                .vsync_len      = 20,
+                .upper_margin   = 0,
+                .lower_margin   = 0,
+
+                .sync           = 0,
+        },
+};
+
+static struct pxafb_mach_info fb_info = {
+        .modes                  = fb_mode_info,
+        .num_modes              = 1,
+        .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+};
+
+static int viper_backlight_init(struct device *dev)
+{
+        int ret;
+
+        /* GPIO9 and 10 control FB backlight. Initialise to off */
+        ret = gpio_request(VIPER_BCKLIGHT_EN_GPIO, "Backlight");
+        if (ret)
+                goto err_request_bckl;
+
+        ret = gpio_request(VIPER_LCD_EN_GPIO, "LCD");
+        if (ret)
+                goto err_request_lcd;
+
+        ret = gpio_direction_output(VIPER_BCKLIGHT_EN_GPIO, 0);
+        if (ret)
+                goto err_dir;
+
+        ret = gpio_direction_output(VIPER_LCD_EN_GPIO, 0);
+        if (ret)
+                goto err_dir;
+
+        return 0;
+
+err_dir:
+        gpio_free(VIPER_LCD_EN_GPIO);
+err_request_lcd:
+        gpio_free(VIPER_BCKLIGHT_EN_GPIO);
+err_request_bckl:
+        dev_err(dev, "Failed to setup LCD GPIOs\n");
+
+        return ret;
+}
+
+static int viper_backlight_notify(int brightness)
+{
+        gpio_set_value(VIPER_LCD_EN_GPIO, !!brightness);
+        gpio_set_value(VIPER_BCKLIGHT_EN_GPIO, !!brightness);
+
+        return brightness;
+}
+
+static void viper_backlight_exit(struct device *dev)
+{
+        gpio_free(VIPER_LCD_EN_GPIO);
+        gpio_free(VIPER_BCKLIGHT_EN_GPIO);
+}
+
+static struct platform_pwm_backlight_data viper_backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 100,
+        .dft_brightness = 100,
+        .pwm_period_ns  = 1000000,
+        .init           = viper_backlight_init,
+        .notify         = viper_backlight_notify,
+        .exit           = viper_backlight_exit,
+};
+
+static struct platform_device viper_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent         = &pxa25x_device_pwm0.dev,
+                .platform_data  = &viper_backlight_data,
+        },
+};
+
+/* Ethernet */
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .name   = "smc91x-regs",
+                .start  = VIPER_ETH_PHYS + 0x300,
+                .end    = VIPER_ETH_PHYS + 0x30f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gpio_to_irq(VIPER_ETH_GPIO),
+                .end    = gpio_to_irq(VIPER_ETH_GPIO),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        },
+        [2] = {
+                .name   = "smc91x-data32",
+                .start  = VIPER_ETH_DATA_PHYS,
+                .end    = VIPER_ETH_DATA_PHYS + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct smc91x_platdata viper_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
+static struct platform_device smc91x_device = {
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
+        .dev            = {
+                .platform_data  = &viper_smc91x_info,
+        },
+};
+
+/* i2c */
+static struct i2c_gpio_platform_data i2c_bus_data = {
+        .sda_pin = VIPER_RTC_I2C_SDA_GPIO,
+        .scl_pin = VIPER_RTC_I2C_SCL_GPIO,
+        .udelay  = 10,
+        .timeout = 100,
+};
+
+static struct platform_device i2c_bus_device = {
+        .name           = "i2c-gpio",
+        .id             = 1, /* pxa2xx-i2c is bus 0, so start at 1 */
+        .dev = {
+                .platform_data = &i2c_bus_data,
+        }
+};
+
+static struct i2c_board_info __initdata viper_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("ds1338", 0x68),
+        },
+};
+
+/*
+ * Serial configuration:
+ * You can either have the standard PXA ports driven by the PXA driver,
+ * or all the ports (PXA + 16850) driven by the 8250 driver.
+ * Choose your poison.
+ */
+
+static struct resource viper_serial_resources[] = {
+#ifndef CONFIG_SERIAL_PXA
+        {
+                .start  = 0x40100000,
+                .end    = 0x4010001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x40200000,
+                .end    = 0x4020001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 0x40700000,
+                .end    = 0x4070001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = VIPER_UARTA_PHYS,
+                .end    = VIPER_UARTA_PHYS + 0xf,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = VIPER_UARTB_PHYS,
+                .end    = VIPER_UARTB_PHYS + 0xf,
+                .flags  = IORESOURCE_MEM,
+        },
+#else
+        {
+                0,
+        },
+#endif
+};
+
+static struct plat_serial8250_port serial_platform_data[] = {
+#ifndef CONFIG_SERIAL_PXA
+        /* Internal UARTs */
+        {
+                .membase        = (void *)&FFUART,
+                .mapbase        = __PREG(FFUART),
+                .irq            = IRQ_FFUART,
+                .uartclk        = 921600 * 16,
+                .regshift       = 2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        {
+                .membase        = (void *)&BTUART,
+                .mapbase        = __PREG(BTUART),
+                .irq            = IRQ_BTUART,
+                .uartclk        = 921600 * 16,
+                .regshift       = 2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        {
+                .membase        = (void *)&STUART,
+                .mapbase        = __PREG(STUART),
+                .irq            = IRQ_STUART,
+                .uartclk        = 921600 * 16,
+                .regshift       = 2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .iotype         = UPIO_MEM,
+        },
+        /* External UARTs */
+        {
+                .mapbase        = VIPER_UARTA_PHYS,
+                .irq            = gpio_to_irq(VIPER_UARTA_GPIO),
+                .uartclk        = 1843200,
+                .regshift       = 1,
+                .iotype         = UPIO_MEM,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP |
+                                  UPF_SKIP_TEST,
+        },
+        {
+                .mapbase        = VIPER_UARTB_PHYS,
+                .irq            = gpio_to_irq(VIPER_UARTB_GPIO),
+                .uartclk        = 1843200,
+                .regshift       = 1,
+                .iotype         = UPIO_MEM,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP |
+                                  UPF_SKIP_TEST,
+        },
+#endif
+        { },
+};
+
+static struct platform_device serial_device = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = serial_platform_data,
+        },
+        .num_resources          = ARRAY_SIZE(viper_serial_resources),
+        .resource               = viper_serial_resources,
+};
+
+/* USB */
+static void isp116x_delay(struct device *dev, int delay)
+{
+        ndelay(delay);
+}
+
+static struct resource isp116x_resources[] = {
+        [0] = { /* DATA */
+                .start  = VIPER_USB_PHYS + 0,
+                .end    = VIPER_USB_PHYS + 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = { /* ADDR */
+                .start  = VIPER_USB_PHYS + 2,
+                .end    = VIPER_USB_PHYS + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = gpio_to_irq(VIPER_USB_GPIO),
+                .end    = gpio_to_irq(VIPER_USB_GPIO),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        },
+};
+
+/* (DataBusWidth16|AnalogOCEnable|DREQOutputPolarity|DownstreamPort15KRSel ) */
+static struct isp116x_platform_data isp116x_platform_data = {
+        /* Enable internal resistors on downstream ports */
+        .sel15Kres              = 1,
+        /* On-chip overcurrent protection */
+        .oc_enable              = 1,
+        /* INT output polarity */
+        .int_act_high           = 1,
+        /* INT edge or level triggered */
+        .int_edge_triggered     = 0,
+
+        /* WAKEUP pin connected - NOT SUPPORTED  */
+        /* .remote_wakeup_connected = 0, */
+        /* Wakeup by devices on usb bus enabled */
+        .remote_wakeup_enable   = 0,
+        .delay                  = isp116x_delay,
+};
+
+static struct platform_device isp116x_device = {
+        .name                   = "isp116x-hcd",
+        .id                     = -1,
+        .num_resources          = ARRAY_SIZE(isp116x_resources),
+        .resource               = isp116x_resources,
+        .dev                    = {
+                .platform_data  = &isp116x_platform_data,
+        },
+
+};
+
+/* MTD */
+static struct resource mtd_resources[] = {
+        [0] = { /* RedBoot config + filesystem flash */
+                .start  = VIPER_FLASH_PHYS,
+                .end    = VIPER_FLASH_PHYS + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = { /* Boot flash */
+                .start  = VIPER_BOOT_PHYS,
+                .end    = VIPER_BOOT_PHYS + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = { /*
+                 * SRAM size is actually 256KB, 8bits, with a sparse mapping
+                 * (each byte is on a 16bit boundary).
+                 */
+                .start  = _VIPER_SRAM_BASE,
+                .end    = _VIPER_SRAM_BASE + SZ_512K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct mtd_partition viper_boot_flash_partition = {
+        .name           = "RedBoot",
+        .size           = SZ_1M,
+        .offset         = 0,
+        .mask_flags     = MTD_WRITEABLE,        /* force R/O */
+};
+
+static struct physmap_flash_data viper_flash_data[] = {
+        [0] = {
+                .width          = 2,
+                .parts          = NULL,
+                .nr_parts       = 0,
+        },
+        [1] = {
+                .width          = 2,
+                .parts          = &viper_boot_flash_partition,
+                .nr_parts       = 1,
+        },
+};
+
+static struct platform_device viper_mtd_devices[] = {
+        [0] = {
+                .name           = "physmap-flash",
+                .id             = 0,
+                .dev            = {
+                        .platform_data  = &viper_flash_data[0],
+                },
+                .resource       = &mtd_resources[0],
+                .num_resources  = 1,
+        },
+        [1] = {
+                .name           = "physmap-flash",
+                .id             = 1,
+                .dev            = {
+                        .platform_data  = &viper_flash_data[1],
+                },
+                .resource       = &mtd_resources[1],
+                .num_resources  = 1,
+        },
+};
+
+static struct platform_device *viper_devs[] __initdata = {
+        &smc91x_device,
+        &i2c_bus_device,
+        &serial_device,
+        &isp116x_device,
+        &viper_mtd_devices[0],
+        &viper_mtd_devices[1],
+        &viper_backlight_device,
+};
+
+static mfp_cfg_t viper_pin_config[] __initdata = {
+        /* Chip selects */
+        GPIO15_nCS_1,
+        GPIO78_nCS_2,
+        GPIO79_nCS_3,
+        GPIO80_nCS_4,
+        GPIO33_nCS_5,
+
+        /* FP Backlight */
+        GPIO9_GPIO,                             /* VIPER_BCKLIGHT_EN_GPIO */
+        GPIO10_GPIO,                            /* VIPER_LCD_EN_GPIO */
+        GPIO16_PWM0_OUT,
+
+        /* Ethernet PHY Ready */
+        GPIO18_RDY,
+
+        /* Serial shutdown */
+        GPIO12_GPIO | MFP_LPM_DRIVE_HIGH,       /* VIPER_UART_SHDN_GPIO */
+
+        /* Compact-Flash / PC104 */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO52_nPCE_1,
+        GPIO53_nPCE_2,
+        GPIO54_nPSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+        GPIO8_GPIO,                             /* VIPER_CF_RDY_GPIO */
+        GPIO32_GPIO,                            /* VIPER_CF_CD_GPIO */
+        GPIO82_GPIO,                            /* VIPER_CF_POWER_GPIO */
+
+        /* Integrated UPS control */
+        GPIO20_GPIO,                            /* VIPER_UPS_GPIO */
+
+        /* Vcc regulator control */
+        GPIO6_GPIO,                             /* VIPER_PSU_DATA_GPIO */
+        GPIO11_GPIO,                            /* VIPER_PSU_CLK_GPIO */
+        GPIO19_GPIO,                            /* VIPER_PSU_nCS_LD_GPIO */
+
+        /* i2c busses */
+        GPIO26_GPIO,                            /* VIPER_TPM_I2C_SDA_GPIO */
+        GPIO27_GPIO,                            /* VIPER_TPM_I2C_SCL_GPIO */
+        GPIO83_GPIO,                            /* VIPER_RTC_I2C_SDA_GPIO */
+        GPIO84_GPIO,                            /* VIPER_RTC_I2C_SCL_GPIO */
+
+        /* PC/104 Interrupt */
+        GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,       /* VIPER_CPLD_GPIO */
+};
+
+static unsigned long viper_tpm;
+
+static int __init viper_tpm_setup(char *str)
+{
+        strict_strtoul(str, 10, &viper_tpm);
+        return 1;
+}
+
+__setup("tpm=", viper_tpm_setup);
+
+static void __init viper_tpm_init(void)
+{
+        struct platform_device *tpm_device;
+        struct i2c_gpio_platform_data i2c_tpm_data = {
+                .sda_pin = VIPER_TPM_I2C_SDA_GPIO,
+                .scl_pin = VIPER_TPM_I2C_SCL_GPIO,
+                .udelay  = 10,
+                .timeout = 100,
+        };
+        char *errstr;
+
+        /* Allocate TPM i2c bus if requested */
+        if (!viper_tpm)
+                return;
+
+        tpm_device = platform_device_alloc("i2c-gpio", 2);
+        if (tpm_device) {
+                if (!platform_device_add_data(tpm_device,
+                                              &i2c_tpm_data,
+                                              sizeof(i2c_tpm_data))) {
+                        if (platform_device_add(tpm_device)) {
+                                errstr = "register TPM i2c bus";
+                                goto error_free_tpm;
+                        }
+                } else {
+                        errstr = "allocate TPM i2c bus data";
+                        goto error_free_tpm;
+                }
+        } else {
+                errstr = "allocate TPM i2c device";
+                goto error_tpm;
+        }
+
+        return;
+
+error_free_tpm:
+        kfree(tpm_device);
+error_tpm:
+        pr_err("viper: Couldn't %s, giving up\n", errstr);
+}
+
+static void __init viper_init_vcore_gpios(void)
+{
+        if (gpio_request(VIPER_PSU_DATA_GPIO, "PSU data"))
+                goto err_request_data;
+
+        if (gpio_request(VIPER_PSU_CLK_GPIO, "PSU clock"))
+                goto err_request_clk;
+
+        if (gpio_request(VIPER_PSU_nCS_LD_GPIO, "PSU cs"))
+                goto err_request_cs;
+
+        if (gpio_direction_output(VIPER_PSU_DATA_GPIO, 0) ||
+            gpio_direction_output(VIPER_PSU_CLK_GPIO, 0) ||
+            gpio_direction_output(VIPER_PSU_nCS_LD_GPIO, 0))
+                goto err_dir;
+
+        /* c/should assume redboot set the correct level ??? */
+        viper_set_core_cpu_voltage(get_clk_frequency_khz(0), 1);
+
+        return;
+
+err_dir:
+        gpio_free(VIPER_PSU_nCS_LD_GPIO);
+err_request_cs:
+        gpio_free(VIPER_PSU_CLK_GPIO);
+err_request_clk:
+        gpio_free(VIPER_PSU_DATA_GPIO);
+err_request_data:
+        pr_err("viper: Failed to setup vcore control GPIOs\n");
+}
+
+static void __init viper_init_serial_gpio(void)
+{
+        if (gpio_request(VIPER_UART_SHDN_GPIO, "UARTs shutdown"))
+                goto err_request;
+
+        if (gpio_direction_output(VIPER_UART_SHDN_GPIO, 0))
+                goto err_dir;
+
+        return;
+
+err_dir:
+        gpio_free(VIPER_UART_SHDN_GPIO);
+err_request:
+        pr_err("viper: Failed to setup UART shutdown GPIO\n");
+}
+
+#ifdef CONFIG_CPU_FREQ
+static int viper_cpufreq_notifier(struct notifier_block *nb,
+                                  unsigned long val, void *data)
+{
+        struct cpufreq_freqs *freq = data;
+
+        /* TODO: Adjust timings??? */
+
+        switch (val) {
+        case CPUFREQ_PRECHANGE:
+                if (freq->old < freq->new) {
+                        /* we are getting faster so raise the voltage
+                         * before we change freq */
+                        viper_set_core_cpu_voltage(freq->new, 0);
+                }
+                break;
+        case CPUFREQ_POSTCHANGE:
+                if (freq->old > freq->new) {
+                        /* we are slowing down so drop the power
+                         * after we change freq */
+                        viper_set_core_cpu_voltage(freq->new, 0);
+                }
+                break;
+        case CPUFREQ_RESUMECHANGE:
+                viper_set_core_cpu_voltage(freq->new, 0);
+                break;
+        default:
+                /* ignore */
+                break;
+        }
+
+        return 0;
+}
+
+static struct notifier_block viper_cpufreq_notifier_block = {
+        .notifier_call  = viper_cpufreq_notifier
+};
+
+static void __init viper_init_cpufreq(void)
+{
+        if (cpufreq_register_notifier(&viper_cpufreq_notifier_block,
+                                      CPUFREQ_TRANSITION_NOTIFIER))
+                pr_err("viper: Failed to setup cpufreq notifier\n");
+}
+#else
+static inline void viper_init_cpufreq(void) {}
+#endif
+
+static void viper_power_off(void)
+{
+        pr_notice("Shutting off UPS\n");
+        gpio_set_value(VIPER_UPS_GPIO, 1);
+        /* Spin to death... */
+        while (1);
+}
+
+static void __init viper_init(void)
+{
+        u8 version;
+
+        pm_power_off = viper_power_off;
+
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(viper_pin_config));
+
+        /* Wake-up serial console */
+        viper_init_serial_gpio();
+
+        set_pxa_fb_info(&fb_info);
+
+        /* v1 hardware cannot use the datacs line */
+        version = viper_hw_version();
+        if (version == 0)
+                smc91x_device.num_resources--;
+
+        pxa_set_i2c_info(NULL);
+        platform_add_devices(viper_devs, ARRAY_SIZE(viper_devs));
+
+        viper_init_vcore_gpios();
+        viper_init_cpufreq();
+
+        sysdev_driver_register(&cpu_sysdev_class, &viper_cpu_sysdev_driver);
+
+        if (version) {
+                pr_info("viper: hardware v%di%d detected. "
+                        "CPLD revision %d.\n",
+                        VIPER_BOARD_VERSION(version),
+                        VIPER_BOARD_ISSUE(version),
+                        VIPER_CPLD_REVISION(version));
+                system_rev = (VIPER_BOARD_VERSION(version) << 8) |
+                             (VIPER_BOARD_ISSUE(version) << 4) |
+                             VIPER_CPLD_REVISION(version);
+        } else {
+                pr_info("viper: No version register.\n");
+        }
+
+        i2c_register_board_info(1, ARRAY_AND_SIZE(viper_i2c_devices));
+
+        viper_tpm_init();
+        pxa_set_ac97_info(NULL);
+}
+
+static struct map_desc viper_io_desc[] __initdata = {
+        {
+                .virtual = VIPER_CPLD_BASE,
+                .pfn     = __phys_to_pfn(VIPER_CPLD_PHYS),
+                .length  = 0x00300000,
+                .type    = MT_DEVICE,
+        },
+        {
+                .virtual = VIPER_PC104IO_BASE,
+                .pfn     = __phys_to_pfn(_PCMCIA1IO),
+                .length  = 0x00800000,
+                .type    = MT_DEVICE,
+        },
+};
+
+static void __init viper_map_io(void)
+{
+        pxa_map_io();
+
+        iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc));
+
+        PCFR |= PCFR_OPDE;
+}
+
+MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
+        /* Maintainer: Marc Zyngier <maz@misterjones.org> */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = viper_map_io,
+        .init_irq       = viper_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = viper_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 0cb65b5772fe..813804433466 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -29,6 +29,7 @@
 #include <mach/pxafb.h>
 #include <mach/zylonite.h>
 #include <mach/mmc.h>
+#include <mach/ohci.h>
 #include <mach/pxa27x_keypad.h>
 #include <mach/pxa3xx_nand.h>
 
@@ -423,6 +424,21 @@ static void __init zylonite_init_nand(void)
 static inline void zylonite_init_nand(void) {}
 #endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */
 
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static struct pxaohci_platform_data zylonite_ohci_info = {
+        .port_mode      = PMM_PERPORT_MODE,
+        .flags          = ENABLE_PORT1 | ENABLE_PORT2 |
+                          POWER_CONTROL_LOW | POWER_SENSE_LOW,
+};
+
+static void __init zylonite_init_ohci(void)
+{
+        pxa_set_ohci_info(&zylonite_ohci_info);
+}
+#else
+static inline void zylonite_init_ohci(void) {}
+#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
+
 static void __init zylonite_init(void)
 {
         /* board-processor specific initialization */
@@ -443,6 +459,7 @@ static void __init zylonite_init(void)
         zylonite_init_keypad();
         zylonite_init_nand();
         zylonite_init_leds();
+        zylonite_init_ohci();
 }
 
 MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 095f5c648236..46538885a58a 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -73,6 +73,12 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
         GPIO27_AC97_SDATA_OUT,
         GPIO28_AC97_SYNC,
 
+        /* SSP3 */
+        GPIO91_SSP3_SCLK,
+        GPIO92_SSP3_FRM,
+        GPIO93_SSP3_TXD,
+        GPIO94_SSP3_RXD,
+
         /* WM9713 IRQ */
         GPIO26_GPIO,
 
@@ -113,6 +119,10 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
         GPIO13_MMC2_CLK,
         GPIO14_MMC2_CMD,
 
+        /* USB Host */
+        GPIO0_2_USBH_PEN,
+        GPIO1_2_USBH_PWR,
+
         /* Standard I2C */
         GPIO21_I2C_SCL,
         GPIO22_I2C_SDA,
@@ -209,7 +219,7 @@ static struct pca953x_platform_data gpio_exp[] = {
         },
 };
 
-struct i2c_board_info zylonite_i2c_board_info[] = {
+static struct i2c_board_info zylonite_i2c_board_info[] = {
         {
                 .type           = "pca9539",
                 .addr           = 0x74,
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index 9879d7da2df5..0f244744daae 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -69,6 +69,12 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
         GPIO39_AC97_BITCLK,
         GPIO40_AC97_nACRESET,
 
+        /* SSP3 */
+        GPIO89_SSP3_SCLK,
+        GPIO90_SSP3_FRM,
+        GPIO91_SSP3_TXD,
+        GPIO92_SSP3_RXD,
+
         /* WM9713 IRQ */
         GPIO15_GPIO,
 
@@ -117,6 +123,10 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
         GPIO28_MMC2_CLK,
         GPIO29_MMC2_CMD,
 
+        /* USB Host */
+        GPIO2_2_USBH_PEN,
+        GPIO3_2_USBH_PWR,
+
         /* Debug LEDs */
         GPIO1_2_GPIO | MFP_LPM_DRIVE_HIGH,
         GPIO4_2_GPIO | MFP_LPM_DRIVE_HIGH,
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 4f9c84ab781c..2f04d54711e7 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -27,10 +27,10 @@
 #include <linux/amba/clcd.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 33dbbb41a663..3cea92c70d8f 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -23,9 +23,9 @@
 #define __ASM_ARCH_REALVIEW_H
 
 #include <linux/amba/bus.h>
+#include <linux/io.h>
 
 #include <asm/leds.h>
-#include <asm/io.h>
 
 #define AMBA_DEVICE(name,busid,base,plat)                       \
 static struct amba_device name##_device = {                     \
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
index 4d3c8f3f8053..a2f61c78adbf 100644
--- a/arch/arm/mach-realview/include/mach/system.h
+++ b/arch/arm/mach-realview/include/mach/system.h
@@ -21,8 +21,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <mach/platform.h>
 
 static inline void arch_idle(void)
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index 82fa1f26e026..44d178cd5733 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -17,11 +17,11 @@
 #include <linux/percpu.h>
 #include <linux/clockchips.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 
 #include <asm/hardware/arm_twd.h>
 #include <asm/hardware/gic.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 static DEFINE_PER_CPU(struct clock_event_device, local_clockevent);
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 1907d22f4fed..e102aeb0f76e 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -13,10 +13,10 @@
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/smp.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach-types.h>
 
 #include <mach/board-eb.h>
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 19a9968fc5b9..eb829eb1ebe2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -23,9 +23,9 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 0986cbd15943..cccdb3eb90fe 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -23,9 +23,9 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index f4e7135e3eb5..8b863148ec18 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -23,9 +23,9 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
index 4b19fe484190..7958a30f8932 100644
--- a/arch/arm/mach-rpc/dma.c
+++ b/arch/arm/mach-rpc/dma.c
@@ -14,11 +14,11 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
+#include <linux/io.h>
 
 #include <asm/page.h>
 #include <asm/dma.h>
 #include <asm/fiq.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <asm/uaccess.h>
diff --git a/arch/arm/mach-rpc/include/mach/memory.h b/arch/arm/mach-rpc/include/mach/memory.h
index 05425d558ee7..9bf7e43e2863 100644
--- a/arch/arm/mach-rpc/include/mach/memory.h
+++ b/arch/arm/mach-rpc/include/mach/memory.h
@@ -36,4 +36,12 @@
 #define FLUSH_BASE_PHYS         0x00000000
 #define FLUSH_BASE              0xdf000000
 
+/*
+ * Sparsemem support.  Each section is a maximum of 64MB.  The sections
+ * are offset by 128MB and can cover 128MB, so that gives us a maximum
+ * of 29 physmem bits.
+ */
+#define MAX_PHYSMEM_BITS        29
+#define SECTION_SIZE_BITS       26
+
 #endif
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h
index 54d6e3f2d319..bd7268ba17e2 100644
--- a/arch/arm/mach-rpc/include/mach/system.h
+++ b/arch/arm/mach-rpc/include/mach/system.h
@@ -7,9 +7,9 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/hardware/iomd.h>
-#include <asm/io.h>
 
 static inline void arch_idle(void)
 {
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
index baa9c866d7bf..d5862368c4f2 100644
--- a/arch/arm/mach-rpc/include/mach/uncompress.h
+++ b/arch/arm/mach-rpc/include/mach/uncompress.h
@@ -9,8 +9,8 @@
  */
 #define VIDMEM ((char *)SCREEN_START)
  
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/page.h>
 
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 7a029621db43..9dd15d679c5d 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -1,10 +1,10 @@
 #include <linux/init.h>
 #include <linux/list.h>
+#include <linux/io.h>
 
 #include <asm/mach/irq.h>
 #include <asm/hardware/iomd.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 static void iomd_ack_irq_a(unsigned int irq)
 {
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index ce8470fea887..e88d417736af 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -18,9 +18,9 @@
 #include <linux/device.h>
 #include <linux/serial_8250.h>
 #include <linux/ata_platform.h>
+#include <linux/io.h>
 
 #include <asm/elf.h>
-#include <asm/io.h>
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/page.h>
diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c
index 148d0ddef3e8..7a7ed4174c8c 100644
--- a/arch/arm/mach-s3c2400/gpio.c
+++ b/arch/arm/mach-s3c2400/gpio.c
@@ -24,10 +24,10 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <mach/regs-gpio.h>
 
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index c66021b5fa4d..75738000272b 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -25,12 +25,12 @@
 #include <linux/module.h>
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
 #include <asm/mach-types.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
@@ -130,8 +130,7 @@ bast_irq_pc104_demux(unsigned int irq,
                 for (i = 0; stat != 0; i++, stat >>= 1) {
                         if (stat & 1) {
                                 irqno = bast_pc104_irqs[i];
-                                desc = irq_desc + irqno;
-                                desc_handle_irq(irqno, desc);
+                                generic_handle_irq(irqno);
                         }
                 }
         }
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 1322851d1acb..fef646c36b54 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -31,11 +31,11 @@
 #include <linux/mutex.h>
 #include <linux/delay.h>
 #include <linux/serial_core.h>
+#include <linux/io.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <asm/plat-s3c/regs-serial.h>
 #include <mach/regs-clock.h>
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index c6eefb1d590c..36a3132f39e7 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -25,10 +25,10 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <mach/regs-gpio.h>
 
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
index ec2defebf0d5..43535a0e7186 100644
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -11,7 +11,7 @@
 */
 
 #include <mach/hardware.h>
-#include <asm/io.h>
+#include <linux/io.h>
 
 #include <asm/plat-s3c/regs-watchdog.h>
 #include <mach/regs-clock.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/system.h b/arch/arm/mach-s3c2410/include/mach/system.h
index e9f676bc0116..a8cbca6701e5 100644
--- a/arch/arm/mach-s3c2410/include/mach/system.h
+++ b/arch/arm/mach-s3c2410/include/mach/system.h
@@ -10,8 +10,8 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <mach/map.h>
 #include <mach/idle.h>
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index f0de3c23ce78..527f88a288ec 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -36,6 +36,7 @@
 #include <linux/platform_device.h>
 #include <linux/proc_fs.h>
 #include <linux/serial_core.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -43,7 +44,6 @@
 #include <asm/mach/flash.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <mach/fb.h>
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 24c6334fac89..e4368e6e7e6c 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -22,6 +22,7 @@
 #include <linux/dm9000.h>
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
+#include <linux/io.h>
 
 #include <net/ax88796.h>
 
@@ -34,7 +35,6 @@
 #include <mach/bast-cpld.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index e35933a46d10..85e710f2863b 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -20,13 +20,13 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 80fe2ed0775c..3ece2d04934e 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -25,9 +25,9 @@
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/timer.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index 606ee15911b6..c4dfe3eabe1d 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -25,7 +26,6 @@
 #include <mach/otom-map.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 7d34844debde..97c13192315b 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -32,7 +32,7 @@
 #include <linux/serial_core.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_bitbang.h>
-
+#include <linux/io.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
@@ -43,7 +43,6 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index b88939d72282..d49e58acb03b 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -36,13 +36,13 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index ec87306a8c24..cc2e79fe4f9f 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -33,6 +33,7 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -40,7 +41,6 @@
 #include <asm/mach/flash.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index fbc0213d5485..ed3acb05c855 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -25,6 +25,7 @@
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -36,7 +37,6 @@
 #include <mach/vr1000-cpld.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index ba43ff9e8164..733f8a227775 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -25,9 +25,9 @@
 #include <linux/errno.h>
 #include <linux/time.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 5d977f9c88ac..b1e658c917a0 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -19,13 +19,13 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <mach/regs-clock.h>
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 4dacf8a1750d..eb6fc0bfd47e 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -21,6 +21,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,7 +33,6 @@
 #include <mach/regs-gpio.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <asm/plat-s3c24xx/devs.h>
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index af4b2ce516f9..5fbaac6054f8 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -31,11 +31,11 @@
 #include <linux/mutex.h>
 #include <linux/delay.h>
 #include <linux/serial_core.h>
+#include <linux/io.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <asm/plat-s3c/regs-serial.h>
 #include <mach/regs-clock.h>
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 22fc04a3b533..dcfff6b8b958 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -16,10 +16,10 @@
 #include <linux/init.h>
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
+#include <linux/io.h>
 
 #include <asm/dma.h>
 #include <mach/dma.h>
-#include <asm/io.h>
 
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index ac62b79044f4..41720f2c1fea 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -24,10 +24,10 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
@@ -123,10 +123,10 @@ static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
         subsrc  &= ~submsk;
 
         if (subsrc & INTBIT(IRQ_S3C2412_SDI))
-                desc_handle_irq(IRQ_S3C2412_SDI, irq_desc + IRQ_S3C2412_SDI);
+                generic_handle_irq(IRQ_S3C2412_SDI);
 
         if (subsrc & INTBIT(IRQ_S3C2412_CF))
-                desc_handle_irq(IRQ_S3C2412_CF, irq_desc + IRQ_S3C2412_CF);
+                generic_handle_irq(IRQ_S3C2412_CF);
 }
 
 #define INTMSK_CFSDI    (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 80affb1ee4cd..8f8d9117b968 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -27,7 +28,6 @@
 #include <mach/hardware.h>
 #include <asm/hardware/iomd.h>
 #include <asm/setup.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 7a08b3789915..bb9bf63b2e02 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -17,7 +17,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
-
+#include <linux/io.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
@@ -29,7 +29,6 @@
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index 737523a4e037..9540ef752f73 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -18,9 +18,9 @@
 #include <linux/init.h>
 #include <linux/sysdev.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <mach/regs-power.h>
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index d278010b9f60..42440fc55681 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -20,6 +20,7 @@
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -27,7 +28,6 @@
 
 #include <mach/hardware.h>
 #include <asm/proc-fns.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <mach/reset.h>
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index 95567e6daea1..40503a65bacf 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -33,11 +33,11 @@
 #include <linux/ioport.h>
 #include <linux/mutex.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/atomic.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <mach/regs-clock.h>
 
diff --git a/arch/arm/mach-s3c2440/dsc.c b/arch/arm/mach-s3c2440/dsc.c
index c0c67438d0a4..4f7d06baf0d3 100644
--- a/arch/arm/mach-s3c2440/dsc.c
+++ b/arch/arm/mach-s3c2440/dsc.c
@@ -15,13 +15,13 @@
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 276b823f4e27..33e3ede0a2b3 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -24,10 +24,10 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
@@ -44,7 +44,6 @@ static void s3c_irq_demux_wdtac97(unsigned int irq,
                                   struct irq_desc *desc)
 {
         unsigned int subsrc, submsk;
-        struct irq_desc *mydesc;
 
         /* read the current pending interrupts, and the mask
          * for what it is available */
@@ -58,12 +57,10 @@ static void s3c_irq_demux_wdtac97(unsigned int irq,
 
         if (subsrc != 0) {
                 if (subsrc & 1) {
-                        mydesc = irq_desc + IRQ_S3C2440_WDT;
-                        desc_handle_irq(IRQ_S3C2440_WDT, mydesc);
+                        generic_handle_irq(IRQ_S3C2440_WDT);
                 }
                 if (subsrc & 2) {
-                        mydesc = irq_desc + IRQ_S3C2440_AC97;
-                        desc_handle_irq(IRQ_S3C2440_AC97, mydesc);
+                        generic_handle_irq(IRQ_S3C2440_AC97);
                 }
         }
 }
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 441f4bc09472..19eb0e5269ac 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -19,7 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
-
+#include <linux/io.h>
 #include <linux/sm501.h>
 #include <linux/sm501-regs.h>
 
@@ -32,7 +32,6 @@
 #include <mach/anubis-cpld.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 1a5e7027b41b..49e828d1d4d8 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -21,6 +21,7 @@
 #include <linux/string.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <linux/mtd/map.h>
 
@@ -30,7 +31,6 @@
 
 #include <asm/setup.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 8b83f93b6102..85144aa52c27 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -20,6 +20,7 @@
 #include <linux/serial_core.h>
 #include <linux/clk.h>
 #include <linux/i2c.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -29,7 +30,6 @@
 #include <mach/osiris-cpld.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index e0b07e6a0a18..a4c690456d19 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -23,7 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/serial.h>
-
+#include <linux/io.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
@@ -34,7 +34,6 @@
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index 327c8f371984..7ac60b869e7f 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -21,13 +21,13 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index d6b9a92d284e..c81cdb330712 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -20,13 +20,13 @@
 #include <linux/serial_core.h>
 #include <linux/sysdev.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <asm/plat-s3c24xx/s3c2440.h>
diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c
index 569b5c3d334a..18f2ce4d7b23 100644
--- a/arch/arm/mach-s3c2442/clock.c
+++ b/arch/arm/mach-s3c2442/clock.c
@@ -33,11 +33,11 @@
 #include <linux/ioport.h>
 #include <linux/mutex.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/atomic.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <mach/regs-clock.h>
 
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 6a8d7cced4a2..603b5ea1deab 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -31,11 +31,11 @@
 #include <linux/mutex.h>
 #include <linux/delay.h>
 #include <linux/serial_core.h>
+#include <linux/io.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <mach/regs-s3c2443-clock.h>
 
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index c1ff03aebfda..5d9ee772659b 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -16,10 +16,10 @@
 #include <linux/init.h>
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
+#include <linux/io.h>
 
 #include <asm/dma.h>
 #include <mach/dma.h>
-#include <asm/io.h>
 
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index 9674de7223fd..e44341d7dfef 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -24,10 +24,10 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
@@ -44,7 +44,6 @@ static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
 {
         unsigned int subsrc, submsk;
         unsigned int end;
-        struct irq_desc *mydesc;
 
         /* read the current pending interrupts, and the mask
          * for what it is available */
@@ -57,13 +56,11 @@ static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
         subsrc  &= (1 << len)-1;
 
         end = len + irq;
-        mydesc = irq_desc + irq;
 
         for (; irq < end && subsrc; irq++) {
                 if (subsrc & 1)
-                        desc_handle_irq(irq, mydesc);
+                        generic_handle_irq(irq);
 
-                mydesc++;
                 subsrc >>= 1;
         }
 }
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index e3c0d587bd10..f0d119dc0409 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -21,13 +21,13 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index 37793f924b5e..c973b68cc735 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -20,13 +20,13 @@
 #include <linux/serial_core.h>
 #include <linux/sysdev.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <mach/regs-s3c2443-clock.h>
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index 3efefbdd2527..ab5883b39ddf 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -95,19 +95,19 @@ static int __init badge4_sa1111_init(void)
  *   One-hundred-twenty-seven 32 KiW Main Blocks (8128 Ki b)
  */
 static struct mtd_partition badge4_partitions[] = {
-        {
-                .name           = "BLOB boot loader",
-                .offset         = 0,
-                .size           = 0x0000A000
-        }, {
-                .name           = "params",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 0x00006000
-        }, {
-                .name           = "root",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL
-        }
+        {
+                .name   = "BLOB boot loader",
+                .offset = 0,
+                .size   = 0x0000A000
+        }, {
+                .name   = "params",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = 0x00006000
+        }, {
+                .name   = "root",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL
+        }
 };
 
 static struct flash_platform_data badge4_flash_data = {
@@ -126,7 +126,7 @@ static int five_v_on __initdata = 0;
 
 static int __init five_v_on_setup(char *ignore)
 {
-        five_v_on = 1;
+        five_v_on = 1;
         return 1;
 }
 __setup("five_v_on", five_v_on_setup);
@@ -171,15 +171,15 @@ static int __init badge4_init(void)
         GPCR  = BADGE4_GPIO_TESTPT_J7;
         GPDR |= BADGE4_GPIO_TESTPT_J7;
 
-        /* 5V supply rail. */
-        GPCR  = BADGE4_GPIO_PCMEN5V;            /* initially off */
-        GPDR |= BADGE4_GPIO_PCMEN5V;
+        /* 5V supply rail. */
+        GPCR  = BADGE4_GPIO_PCMEN5V;            /* initially off */
+        GPDR |= BADGE4_GPIO_PCMEN5V;
 
         /* CPLD sdram type inputs; set up by blob */
         //GPDR |= (BADGE4_GPIO_SDTYP1 | BADGE4_GPIO_SDTYP0);
         printk(KERN_DEBUG __FILE__ ": SDRAM CPLD typ1=%d typ0=%d\n",
-               !!(GPLR & BADGE4_GPIO_SDTYP1),
-               !!(GPLR & BADGE4_GPIO_SDTYP0));
+                !!(GPLR & BADGE4_GPIO_SDTYP1),
+                !!(GPLR & BADGE4_GPIO_SDTYP0));
 
         /* SA1111 reset pin; set up by blob */
         //GPSR  = BADGE4_GPIO_SA1111_NRST;
@@ -205,8 +205,8 @@ static int __init badge4_init(void)
         ret = badge4_sa1111_init();
         if (ret < 0)
                 printk(KERN_ERR
-                       "%s: SA-1111 initialization failed (%d)\n",
-                       __func__, ret);
+                        "%s: SA-1111 initialization failed (%d)\n",
+                        __func__, ret);
 
 
         /* maybe turn on 5v0 from the start */
@@ -254,7 +254,7 @@ EXPORT_SYMBOL(badge4_set_5V);
 
 
 static struct map_desc badge4_io_desc[] __initdata = {
-        {       /* SRAM  bank 1 */
+        {       /* SRAM  bank 1 */
                 .virtual        = 0xf1000000,
                 .pfn            = __phys_to_pfn(0x08000000),
                 .length         = 0x00100000,
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index da3a898a6d66..f7fa03478efd 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -88,6 +88,8 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 
+#include <asm/cputype.h>
+
 #include <mach/hardware.h>
 
 #include "generic.h"
@@ -240,7 +242,7 @@ static struct cpufreq_driver sa1100_driver = {
 
 static int __init sa1100_dram_init(void)
 {
-        if ((processor_id & CPU_SA1100_MASK) == CPU_SA1100_ID)
+        if (cpu_is_sa1100())
                 return cpufreq_register_driver(&sa1100_driver);
         else
                 return -ENODEV;
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 029dbfbbafcf..3e4fb214eada 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -23,10 +23,11 @@
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
+#include <asm/cputype.h>
 #include <asm/mach-types.h>
-#include <asm/io.h>
 #include <asm/system.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 1362994c78aa..c1fbd5b5f9c4 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -18,9 +18,9 @@
 #include <linux/ioport.h>
 #include <linux/sched.h>        /* just for sched_clock() - funny that */
 #include <linux/platform_device.h>
+#include <linux/cnt32_to_63.h>
 
 #include <asm/div64.h>
-#include <asm/cnt32_to_63.h>
 #include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -42,7 +42,7 @@ EXPORT_SYMBOL(reset_status);
 static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
          590,   /*  59.0 MHz */
          737,   /*  73.7 MHz */
-         885,   /*  88.5 MHz */
+         885,   /*  88.5 MHz */
         1032,   /* 103.2 MHz */
         1180,   /* 118.0 MHz */
         1327,   /* 132.7 MHz */
@@ -52,10 +52,10 @@ static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
         1917,   /* 191.7 MHz */
         2064,   /* 206.4 MHz */
         2212,   /* 221.2 MHz */
-        2359,   /* 235.9 MHz */
-        2507,   /* 250.7 MHz */
-        2654,   /* 265.4 MHz */
-        2802    /* 280.2 MHz */
+        2359,   /* 235.9 MHz */
+        2507,   /* 250.7 MHz */
+        2654,   /* 265.4 MHz */
+        2802    /* 280.2 MHz */
 };
 
 #if defined(CONFIG_CPU_FREQ_SA1100) || defined(CONFIG_CPU_FREQ_SA1110)
@@ -113,7 +113,7 @@ unsigned int sa11x0_getspeed(unsigned int cpu)
 #else
 /*
  * We still need to provide this so building without cpufreq works.
- */ 
+ */
 unsigned int cpufreq_get(unsigned int cpu)
 {
         return cclk_frequency_100khz[PPCR & 0xf] * 100;
@@ -389,7 +389,7 @@ EXPORT_SYMBOL(sa1100fb_lcd_power);
  */
 
 static struct map_desc standard_io_desc[] __initdata = {
-        {       /* PCM */
+        {       /* PCM */
                 .virtual        =  0xf8000000,
                 .pfn            = __phys_to_pfn(0x80000000),
                 .length         = 0x00100000,
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 62aaf04a3906..4f7ea012e1e5 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -2054,19 +2054,3 @@
                                         /* active display mode)            */
 #define LCCR3_OutEnH    (LCCR3_OEP*0)   /*  Output Enable active High      */
 #define LCCR3_OutEnL    (LCCR3_OEP*1)   /*  Output Enable active Low       */
-
-#ifndef __ASSEMBLY__
-extern unsigned int processor_id;
-#endif
-
-#define CPU_REVISION    (processor_id & 15)
-#define CPU_SA1110_A0   (0)
-#define CPU_SA1110_B0   (4)
-#define CPU_SA1110_B1   (5)
-#define CPU_SA1110_B2   (6)
-#define CPU_SA1110_B4   (8)
-
-#define CPU_SA1100_ID   (0x4401a110)
-#define CPU_SA1100_MASK (0xfffffff0)
-#define CPU_SA1110_ID   (0x6901b110)
-#define CPU_SA1110_MASK (0xfffffff0)
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 5976435f42c2..b70846c096aa 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -36,8 +36,26 @@
 #define io_v2p( x )             \
    ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
 
+#define CPU_SA1110_A0   (0)
+#define CPU_SA1110_B0   (4)
+#define CPU_SA1110_B1   (5)
+#define CPU_SA1110_B2   (6)
+#define CPU_SA1110_B4   (8)
+
+#define CPU_SA1100_ID   (0x4401a110)
+#define CPU_SA1100_MASK (0xfffffff0)
+#define CPU_SA1110_ID   (0x6901b110)
+#define CPU_SA1110_MASK (0xfffffff0)
+
 #ifndef __ASSEMBLY__
 
+#include <asm/cputype.h>
+
+#define CPU_REVISION    (read_cpuid_id() & 15)
+
+#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
+#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
+
 # define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
 # define __PREG(x)      (io_v2p((unsigned long)&(x)))
 
diff --git a/arch/arm/mach-sa1100/include/mach/jornada720.h b/arch/arm/mach-sa1100/include/mach/jornada720.h
index bc120850d313..cc6b4bfcecf6 100644
--- a/arch/arm/mach-sa1100/include/mach/jornada720.h
+++ b/arch/arm/mach-sa1100/include/mach/jornada720.h
@@ -1,10 +1,10 @@
 /*
  * arch/arm/mach-sa1100/include/mach/jornada720.h
  *
- * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728
+ * SSP/MCU communication definitions for HP Jornada 710/720/728
  *
- * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
- *  Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu>
+ * Copyright 2007,2008 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ *  Copyright 2000 John Ankcorn <jca@lcs.mit.edu>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -25,3 +25,8 @@
 #define PWMOFF                  0xDF
 #define TXDUMMY                 0x11
 #define ERRORCODE               0x00
+
+extern void jornada_ssp_start(void);
+extern void jornada_ssp_end(void);
+extern int jornada_ssp_inout(u8 byte);
+extern int jornada_ssp_byte(u8 byte);
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index 29f639e2afc6..1c127b68581d 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -40,23 +40,21 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
 #define __bus_to_virt(x)         __phys_to_virt(x)
 
 /*
- * Because of the wide memory address space between physical RAM banks on the 
- * SA1100, it's much convenient to use Linux's NUMA support to implement our 
- * memory map representation.  Assuming all memory nodes have equal access 
+ * Because of the wide memory address space between physical RAM banks on the
+ * SA1100, it's much convenient to use Linux's SparseMEM support to implement
+ * our memory map representation.  Assuming all memory nodes have equal access
  * characteristics, we then have generic discontiguous memory support.
  *
- * Of course, all this isn't mandatory for SA1100 implementations with only
- * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
- *
- * The nodes are matched with the physical memory bank addresses which are 
- * incidentally the same as virtual addresses.
+ * The sparsemem banks are matched with the physical memory bank addresses
+ * which are incidentally the same as virtual addresses.
  * 
  *      node 0:  0xc0000000 - 0xc7ffffff
  *      node 1:  0xc8000000 - 0xcfffffff
  *      node 2:  0xd0000000 - 0xd7ffffff
  *      node 3:  0xd8000000 - 0xdfffffff
  */
-#define NODE_MEM_SIZE_BITS      27
+#define MAX_PHYSMEM_BITS        32
+#define SECTION_SIZE_BITS       27
 
 /*
  * Cache flushing area - SA1100 zero bank
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 86369a8f0cea..3093d46a9c6f 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -122,14 +122,12 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
                 GEDR = mask;
 
                 irq = IRQ_GPIO11;
-                desc = irq_desc + irq;
                 mask >>= 11;
                 do {
                         if (mask & 1)
-                                desc_handle_irq(irq, desc);
+                                generic_handle_irq(irq);
                         mask >>= 1;
                         irq++;
-                        desc++;
                 } while (mask);
 
                 mask = GEDR & 0xfffff800;
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index 06ea7abd9170..28cf36967977 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -21,8 +21,8 @@
 #include <linux/slab.h>
 
 #include <mach/hardware.h>
-#include <asm/hardware/ssp.h>
 #include <mach/jornada720.h>
+#include <asm/hardware/ssp.h>
 
 static DEFINE_SPINLOCK(jornada_ssp_lock);
 static unsigned long jornada_ssp_flags;
@@ -109,12 +109,12 @@ EXPORT_SYMBOL(jornada_ssp_inout);
  * jornada_ssp_start - enable mcu
  *
  */
-int jornada_ssp_start()
+void jornada_ssp_start(void)
 {
         spin_lock_irqsave(&jornada_ssp_lock, jornada_ssp_flags);
         GPCR = GPIO_GPIO25;
         udelay(50);
-        return 0;
+        return;
 };
 EXPORT_SYMBOL(jornada_ssp_start);
 
@@ -122,11 +122,11 @@ EXPORT_SYMBOL(jornada_ssp_start);
  * jornada_ssp_end - disable mcu and turn off lock
  *
  */
-int jornada_ssp_end()
+void jornada_ssp_end(void)
 {
         GPSR = GPIO_GPIO25;
         spin_unlock_irqrestore(&jornada_ssp_lock, jornada_ssp_flags);
-        return 0;
+        return;
 };
 EXPORT_SYMBOL(jornada_ssp_end);
 
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 4856a6bd2482..6ccd175bc4cf 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -33,8 +33,6 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
         unsigned int irr;
 
         while (1) {
-                struct irq_desc *d;
-
                 /*
                  * Acknowledge the parent IRQ.
                  */
@@ -67,21 +65,18 @@ neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
                         desc->chip->ack(irq);
 
                         if (irr & IRR_ETHERNET) {
-                                d = irq_desc + IRQ_NEPONSET_SMC9196;
-                                desc_handle_irq(IRQ_NEPONSET_SMC9196, d);
+                                generic_handle_irq(IRQ_NEPONSET_SMC9196);
                         }
 
                         if (irr & IRR_USAR) {
-                                d = irq_desc + IRQ_NEPONSET_USAR;
-                                desc_handle_irq(IRQ_NEPONSET_USAR, d);
+                                generic_handle_irq(IRQ_NEPONSET_USAR);
                         }
 
                         desc->chip->unmask(irq);
                 }
 
                 if (irr & IRR_SA1111) {
-                        d = irq_desc + IRQ_NEPONSET_SA1111;
-                        desc_handle_irq(IRQ_NEPONSET_SA1111, d);
+                        generic_handle_irq(IRQ_NEPONSET_SA1111);
                 }
         }
 }
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 83be1c6c5f80..e45d3a1890bc 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -8,11 +8,10 @@
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
 #include <linux/irq.h>
-
+#include <linux/io.h>
 #include <linux/mtd/partitions.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 
@@ -39,8 +38,8 @@
 
 static struct resource smc91x_resources[] = {
         [0] = {
-                .start  =  PLEB_ETH0_P,
-                .end    =  PLEB_ETH0_P | 0x03ffffff,
+                .start  = PLEB_ETH0_P,
+                .end    = PLEB_ETH0_P | 0x03ffffff,
                 .flags  = IORESOURCE_MEM,
         },
 #if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */
@@ -87,15 +86,15 @@ static struct resource pleb_flash_resources[] = {
 static struct mtd_partition pleb_partitions[] = {
         {
                 .name           = "blob",
-                .offset         = 0,
+                .offset         = 0,
                 .size           = 0x00020000,
         }, {
                 .name           = "kernel",
-                .offset         = MTDPART_OFS_APPEND,
+                .offset         = MTDPART_OFS_APPEND,
                 .size           = 0x000e0000,
         }, {
                 .name           = "rootfs",
-                .offset         = MTDPART_OFS_APPEND,
+                .offset         = MTDPART_OFS_APPEND,
                 .size           = 0x00300000,
         }
 };
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 8dd635317959..3c74534f7fee 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -12,6 +12,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/io.h>
 
 #include <asm/irq.h>
 #include <mach/hardware.h>
@@ -27,7 +28,6 @@
 
 #include <linux/serial_core.h>
 #include <linux/ioport.h>
-#include <asm/io.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/ssp.c b/arch/arm/mach-sa1100/ssp.c
index 641f361c56f4..b20ff93b84a5 100644
--- a/arch/arm/mach-sa1100/ssp.c
+++ b/arch/arm/mach-sa1100/ssp.c
@@ -17,8 +17,8 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <asm/hardware/ssp.h>
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 09d9f33d4072..a9400d984451 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -9,10 +9,10 @@
 #include <linux/irq.h>
 #include <linux/sched.h>
 #include <linux/serial_8250.h>
+#include <linux/io.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <asm/io.h>
 #include <asm/leds.h>
 #include <asm/param.h>
 
diff --git a/arch/arm/mach-shark/include/mach/system.h b/arch/arm/mach-shark/include/mach/system.h
index 85aceef6f874..e45bd734a03e 100644
--- a/arch/arm/mach-shark/include/mach/system.h
+++ b/arch/arm/mach-shark/include/mach/system.h
@@ -6,7 +6,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <asm/io.h>
+#include <linux/io.h>
 
 static void arch_reset(char mode)
 {
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index 44b0811b400c..c04eb6a1e2be 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -11,9 +11,9 @@
 #include <linux/init.h>
 #include <linux/fs.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
 
 #include <asm/irq.h>
-#include <asm/io.h>
 #include <asm/mach/irq.h>
 
 /*
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index b1896471aa3c..8bd8d6bb4d92 100644
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -20,10 +20,10 @@
 #include <linux/init.h>
 #include <linux/spinlock.h>
 #include <linux/ioport.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/io.h>
 #include <asm/system.h>
 
 #define LED_STATE_ENABLED       1
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index d75e795c893e..565e0ba0d67e 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -28,11 +28,11 @@
 #include <linux/amba/clcd.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/cnt32_to_63.h>
+#include <linux/io.h>
 
-#include <asm/cnt32_to_63.h>
 #include <asm/system.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
@@ -95,8 +95,7 @@ sic_handle_irq(unsigned int irq, struct irq_desc *desc)
 
                 irq += IRQ_SIC_START;
 
-                desc = irq_desc + irq;
-                desc_handle_irq(irq, desc);
+                generic_handle_irq(irq);
         } while (status);
 }
 
diff --git a/arch/arm/mach-versatile/include/mach/system.h b/arch/arm/mach-versatile/include/mach/system.h
index 91fa559c7cca..c59e6100c7e3 100644
--- a/arch/arm/mach-versatile/include/mach/system.h
+++ b/arch/arm/mach-versatile/include/mach/system.h
@@ -21,8 +21,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <mach/platform.h>
 
 static inline void arch_idle(void)
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 36f23f896503..7161ba23b58a 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -21,9 +21,9 @@
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
index 76375c64413a..bb8ec7724f79 100644
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ b/arch/arm/mach-versatile/versatile_ab.c
@@ -23,9 +23,9 @@
 #include <linux/device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 1725f019fc85..aa051c0884f8 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -23,9 +23,9 @@
 #include <linux/device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index ed15f876c725..330814d1ee25 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -735,6 +735,14 @@ config CACHE_FEROCEON_L2
         help
           This option enables the Feroceon L2 cache controller.
 
+config CACHE_FEROCEON_L2_WRITETHROUGH
+        bool "Force Feroceon L2 cache write through"
+        depends on CACHE_FEROCEON_L2
+        default n
+        help
+          Say Y here to use the Feroceon L2 cache in writethrough mode.
+          Unless you specifically require this, say N for writeback mode.
+
 config CACHE_L2X0
         bool "Enable the L2x0 outer cache controller"
         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 2e27a8c8372b..480f78a3611a 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux arm-specific parts of the memory manager.
 #
 
-obj-y                           := consistent.o extable.o fault.o init.o \
+obj-y                           := dma-mapping.o extable.o fault.o init.o \
                                    iomap.o
 
 obj-$(CONFIG_MMU)               += fault-armv.o flush.o ioremap.o mmap.o \
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index eb90bce38e14..2e6dc040c654 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -30,3 +30,4 @@ ENTRY(v7_early_abort)
          * New designs should not need to patch up faults.
          */
         mov     pc, lr
+ENDPROC(v7_early_abort)
diff --git a/arch/arm/mm/abort-nommu.S b/arch/arm/mm/abort-nommu.S
index a7cc7f9ee45d..625e580945b5 100644
--- a/arch/arm/mm/abort-nommu.S
+++ b/arch/arm/mm/abort-nommu.S
@@ -17,3 +17,4 @@ ENTRY(nommu_early_abort)
         mov     r0, #0                          @ clear r0, r1 (no FSR/FAR)
         mov     r1, #0
         mov     pc, lr
+ENDPROC(nommu_early_abort)
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index e162cca5917f..133e65d166b3 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -17,8 +17,8 @@
 #include <linux/string.h>
 #include <linux/proc_fs.h>
 #include <linux/init.h>
+#include <linux/uaccess.h>
 
-#include <asm/uaccess.h>
 #include <asm/unaligned.h>
 
 #include "fault.h"
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 7b5a25d81576..13cdae8b0d44 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -48,11 +48,12 @@ static inline void l2_clean_mva_range(unsigned long start, unsigned long end)
          * L2 is PIPT and range operations only do a TLB lookup on
          * the start address.
          */
-        BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+        BUG_ON((start ^ end) >> PAGE_SHIFT);
 
         raw_local_irq_save(flags);
-        __asm__("mcr p15, 1, %0, c15, c9, 4" : : "r" (start));
-        __asm__("mcr p15, 1, %0, c15, c9, 5" : : "r" (end));
+        __asm__("mcr p15, 1, %0, c15, c9, 4\n\t"
+                "mcr p15, 1, %1, c15, c9, 5"
+                : : "r" (start), "r" (end));
         raw_local_irq_restore(flags);
 }
 
@@ -80,11 +81,12 @@ static inline void l2_inv_mva_range(unsigned long start, unsigned long end)
          * L2 is PIPT and range operations only do a TLB lookup on
          * the start address.
          */
-        BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
+        BUG_ON((start ^ end) >> PAGE_SHIFT);
 
         raw_local_irq_save(flags);
-        __asm__("mcr p15, 1, %0, c15, c11, 4" : : "r" (start));
-        __asm__("mcr p15, 1, %0, c15, c11, 5" : : "r" (end));
+        __asm__("mcr p15, 1, %0, c15, c11, 4\n\t"
+                "mcr p15, 1, %1, c15, c11, 5"
+                : : "r" (start), "r" (end));
         raw_local_irq_restore(flags);
 }
 
@@ -205,7 +207,7 @@ static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
  * time.  These are necessary because the L2 cache can only be enabled
  * or disabled while the L1 Dcache and Icache are both disabled.
  */
-static void __init invalidate_and_disable_dcache(void)
+static int __init flush_and_disable_dcache(void)
 {
         u32 cr;
 
@@ -217,7 +219,9 @@ static void __init invalidate_and_disable_dcache(void)
                 flush_cache_all();
                 set_cr(cr & ~CR_C);
                 raw_local_irq_restore(flags);
+                return 1;
         }
+        return 0;
 }
 
 static void __init enable_dcache(void)
@@ -225,18 +229,17 @@ static void __init enable_dcache(void)
         u32 cr;
 
         cr = get_cr();
-        if (!(cr & CR_C))
-                set_cr(cr | CR_C);
+        set_cr(cr | CR_C);
 }
 
 static void __init __invalidate_icache(void)
 {
         int dummy;
 
-        __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0\n" : "=r" (dummy));
+        __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : "=r" (dummy));
 }
 
-static void __init invalidate_and_disable_icache(void)
+static int __init invalidate_and_disable_icache(void)
 {
         u32 cr;
 
@@ -244,7 +247,9 @@ static void __init invalidate_and_disable_icache(void)
         if (cr & CR_I) {
                 set_cr(cr & ~CR_I);
                 __invalidate_icache();
+                return 1;
         }
+        return 0;
 }
 
 static void __init enable_icache(void)
@@ -252,8 +257,7 @@ static void __init enable_icache(void)
         u32 cr;
 
         cr = get_cr();
-        if (!(cr & CR_I))
-                set_cr(cr | CR_I);
+        set_cr(cr | CR_I);
 }
 
 static inline u32 read_extra_features(void)
@@ -291,13 +295,17 @@ static void __init enable_l2(void)
 
         u = read_extra_features();
         if (!(u & 0x00400000)) {
+                int i, d;
+
                 printk(KERN_INFO "Feroceon L2: Enabling L2\n");
 
-                invalidate_and_disable_dcache();
-                invalidate_and_disable_icache();
+                d = flush_and_disable_dcache();
+                i = invalidate_and_disable_icache();
                 write_extra_features(u | 0x00400000);
-                enable_icache();
-                enable_dcache();
+                if (i)
+                        enable_icache();
+                if (d)
+                        enable_dcache();
         }
 }
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 76b800a95191..b480f1d3591f 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -18,9 +18,9 @@
  */
 #include <linux/init.h>
 #include <linux/spinlock.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/io.h>
 #include <asm/hardware/cache-l2x0.h>
 
 #define CACHE_LINE_SIZE         32
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 35ffc4d95997..d19c2bec2b1f 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -66,6 +66,7 @@ finished:
         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
         isb
         mov     pc, lr
+ENDPROC(v7_flush_dcache_all)
 
 /*
  *      v7_flush_cache_all()
@@ -85,6 +86,7 @@ ENTRY(v7_flush_kern_cache_all)
         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
         ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
         mov     pc, lr
+ENDPROC(v7_flush_kern_cache_all)
 
 /*
  *      v7_flush_cache_all()
@@ -110,6 +112,8 @@ ENTRY(v7_flush_user_cache_all)
  */
 ENTRY(v7_flush_user_cache_range)
         mov     pc, lr
+ENDPROC(v7_flush_user_cache_all)
+ENDPROC(v7_flush_user_cache_range)
 
 /*
  *      v7_coherent_kern_range(start,end)
@@ -155,6 +159,8 @@ ENTRY(v7_coherent_user_range)
         dsb
         isb
         mov     pc, lr
+ENDPROC(v7_coherent_kern_range)
+ENDPROC(v7_coherent_user_range)
 
 /*
  *      v7_flush_kern_dcache_page(kaddr)
@@ -174,6 +180,7 @@ ENTRY(v7_flush_kern_dcache_page)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_flush_kern_dcache_page)
 
 /*
  *      v7_dma_inv_range(start,end)
@@ -202,6 +209,7 @@ ENTRY(v7_dma_inv_range)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_dma_inv_range)
 
 /*
  *      v7_dma_clean_range(start,end)
@@ -219,6 +227,7 @@ ENTRY(v7_dma_clean_range)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_dma_clean_range)
 
 /*
  *      v7_dma_flush_range(start,end)
@@ -236,6 +245,7 @@ ENTRY(v7_dma_flush_range)
         blo     1b
         dsb
         mov     pc, lr
+ENDPROC(v7_dma_flush_range)
 
         __INITDATA
 
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 158bd96763d3..10b1bae1a258 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -18,10 +18,11 @@
  */
 #include <linux/init.h>
 #include <linux/spinlock.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
+#include <asm/cputype.h>
 #include <asm/cacheflush.h>
-#include <asm/io.h>
 
 #define CR_L2   (1 << 26)
 
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index ded0e96d069d..8d33e2549344 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -28,7 +28,7 @@
  * specific hacks for copying pages efficiently.
  */
 #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
-                                  L_PTE_CACHEABLE)
+                                  L_PTE_MT_MINICACHE)
 
 static DEFINE_SPINLOCK(minicache_lock);
 
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 3adb79257f43..0e21c0767580 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -16,6 +16,7 @@
 #include <asm/shmparam.h>
 #include <asm/tlbflush.h>
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 
 #include "mm.h"
 
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 2e455f82a4d5..bad49331bbf9 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -30,7 +30,7 @@
 #define COPYPAGE_MINICACHE      0xffff8000
 
 #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
-                                  L_PTE_CACHEABLE)
+                                  L_PTE_MT_MINICACHE)
 
 static DEFINE_SPINLOCK(minicache_lock);
 
diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/dma-mapping.c
index db7b3e38ef1d..67960017dc8f 100644
--- a/arch/arm/mm/consistent.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/mm/consistent.c
+ *  linux/arch/arm/mm/dma-mapping.c
  *
  *  Copyright (C) 2000-2004 Russell King
  *
@@ -512,3 +512,105 @@ void dma_cache_maint(const void *start, size_t size, int direction)
         }
 }
 EXPORT_SYMBOL(dma_cache_maint);
+
+/**
+ * dma_map_sg - map a set of SG buffers for streaming mode DMA
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @sg: list of buffers
+ * @nents: number of buffers to map
+ * @dir: DMA transfer direction
+ *
+ * Map a set of buffers described by scatterlist in streaming mode for DMA.
+ * This is the scatter-gather version of the dma_map_single interface.
+ * Here the scatter gather list elements are each tagged with the
+ * appropriate dma address and length.  They are obtained via
+ * sg_dma_{address,length}.
+ *
+ * Device ownership issues as mentioned for dma_map_single are the same
+ * here.
+ */
+int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+                enum dma_data_direction dir)
+{
+        struct scatterlist *s;
+        int i, j;
+
+        for_each_sg(sg, s, nents, i) {
+                s->dma_address = dma_map_page(dev, sg_page(s), s->offset,
+                                                s->length, dir);
+                if (dma_mapping_error(dev, s->dma_address))
+                        goto bad_mapping;
+        }
+        return nents;
+
+ bad_mapping:
+        for_each_sg(sg, s, i, j)
+                dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
+        return 0;
+}
+EXPORT_SYMBOL(dma_map_sg);
+
+/**
+ * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @sg: list of buffers
+ * @nents: number of buffers to unmap (returned from dma_map_sg)
+ * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ *
+ * Unmap a set of streaming mode DMA translations.  Again, CPU access
+ * rules concerning calls here are the same as for dma_unmap_single().
+ */
+void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
+                enum dma_data_direction dir)
+{
+        struct scatterlist *s;
+        int i;
+
+        for_each_sg(sg, s, nents, i)
+                dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
+}
+EXPORT_SYMBOL(dma_unmap_sg);
+
+/**
+ * dma_sync_sg_for_cpu
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @sg: list of buffers
+ * @nents: number of buffers to map (returned from dma_map_sg)
+ * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ */
+void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+                        int nents, enum dma_data_direction dir)
+{
+        struct scatterlist *s;
+        int i;
+
+        for_each_sg(sg, s, nents, i) {
+                dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
+                                        sg_dma_len(s), dir);
+        }
+}
+EXPORT_SYMBOL(dma_sync_sg_for_cpu);
+
+/**
+ * dma_sync_sg_for_device
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @sg: list of buffers
+ * @nents: number of buffers to map (returned from dma_map_sg)
+ * @dir: DMA transfer direction (same as was passed to dma_map_sg)
+ */
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+                        int nents, enum dma_data_direction dir)
+{
+        struct scatterlist *s;
+        int i;
+
+        for_each_sg(sg, s, nents, i) {
+                if (!dmabounce_sync_for_device(dev, sg_dma_address(s), 0,
+                                        sg_dma_len(s), dir))
+                        continue;
+
+                if (!arch_is_coherent())
+                        dma_cache_maint(sg_virt(s), s->length, dir);
+        }
+}
+EXPORT_SYMBOL(dma_sync_sg_for_device);
diff --git a/arch/arm/mm/extable.c b/arch/arm/mm/extable.c
index 9592c3ee4cb2..9d285626bc7d 100644
--- a/arch/arm/mm/extable.c
+++ b/arch/arm/mm/extable.c
@@ -2,7 +2,7 @@
  *  linux/arch/arm/mm/extable.c
  */
 #include <linux/module.h>
-#include <asm/uaccess.h>
+#include <linux/uaccess.h>
 
 int fixup_exception(struct pt_regs *regs)
 {
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index a8ec97b4752e..81d0b8772de3 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -17,11 +17,13 @@
 #include <linux/init.h>
 #include <linux/pagemap.h>
 
+#include <asm/bugs.h>
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 
-static unsigned long shared_pte_mask = L_PTE_CACHEABLE;
+static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
 
 /*
  * We take the easy way out of this problem - we make the
@@ -63,9 +65,10 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
          * If this page isn't present, or is already setup to
          * fault (ie, is old), we can safely ignore any issues.
          */
-        if (ret && pte_val(entry) & shared_pte_mask) {
+        if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
                 flush_cache_page(vma, address, pte_pfn(entry));
-                pte_val(entry) &= ~shared_pte_mask;
+                pte_val(entry) &= ~L_PTE_MT_MASK;
+                pte_val(entry) |= shared_pte_mask;
                 set_pte_at(vma->vm_mm, address, pte, entry);
                 flush_tlb_page(vma, address);
         }
@@ -197,7 +200,7 @@ void __init check_writebuffer_bugs(void)
                 unsigned long *p1, *p2;
                 pgprot_t prot = __pgprot(L_PTE_PRESENT|L_PTE_YOUNG|
                                          L_PTE_DIRTY|L_PTE_WRITE|
-                                         L_PTE_BUFFERABLE);
+                                         L_PTE_MT_BUFFERABLE);
 
                 p1 = vmap(&page, 1, VM_IOREMAP, prot);
                 p2 = vmap(&page, 1, VM_IOREMAP, prot);
@@ -218,7 +221,7 @@ void __init check_writebuffer_bugs(void)
 
         if (v) {
                 printk("failed, %s\n", reason);
-                shared_pte_mask |= L_PTE_BUFFERABLE;
+                shared_pte_mask = L_PTE_MT_UNCACHED;
         } else {
                 printk("ok\n");
         }
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 28ad7ab1c0cd..2df8d9facf57 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -13,11 +13,11 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/kprobes.h>
+#include <linux/uaccess.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
-#include <asm/uaccess.h>
 
 #include "fault.h"
 
@@ -72,9 +72,8 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
                 }
 
                 pmd = pmd_offset(pgd, addr);
-#if PTRS_PER_PMD != 1
-                printk(", *pmd=%08lx", pmd_val(*pmd));
-#endif
+                if (PTRS_PER_PMD != 1)
+                        printk(", *pmd=%08lx", pmd_val(*pmd));
 
                 if (pmd_none(*pmd))
                         break;
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 029ee65fda2b..0fa9bf388f0b 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -12,6 +12,7 @@
 #include <linux/pagemap.h>
 
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
 
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 30a69d67d673..82c4b4217989 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -26,9 +26,42 @@
 
 #include "mm.h"
 
-extern void _text, _etext, __data_start, _end, __init_begin, __init_end;
-extern unsigned long phys_initrd_start;
-extern unsigned long phys_initrd_size;
+static unsigned long phys_initrd_start __initdata = 0;
+static unsigned long phys_initrd_size __initdata = 0;
+
+static void __init early_initrd(char **p)
+{
+        unsigned long start, size;
+
+        start = memparse(*p, p);
+        if (**p == ',') {
+                size = memparse((*p) + 1, p);
+
+                phys_initrd_start = start;
+                phys_initrd_size = size;
+        }
+}
+__early_param("initrd=", early_initrd);
+
+static int __init parse_tag_initrd(const struct tag *tag)
+{
+        printk(KERN_WARNING "ATAG_INITRD is deprecated; "
+                "please update your bootloader.\n");
+        phys_initrd_start = __virt_to_phys(tag->u.initrd.start);
+        phys_initrd_size = tag->u.initrd.size;
+        return 0;
+}
+
+__tagtable(ATAG_INITRD, parse_tag_initrd);
+
+static int __init parse_tag_initrd2(const struct tag *tag)
+{
+        phys_initrd_start = tag->u.initrd.start;
+        phys_initrd_size = tag->u.initrd.size;
+        return 0;
+}
+
+__tagtable(ATAG_INITRD2, parse_tag_initrd2);
 
 /*
  * This is used to pass memory configuration data from paging_init
@@ -36,10 +69,6 @@ extern unsigned long phys_initrd_size;
  */
 static struct meminfo meminfo = { 0, };
 
-#define for_each_nodebank(iter,mi,no)                   \
-        for (iter = 0; iter < mi->nr_banks; iter++)     \
-                if (mi->bank[iter].node == no)
-
 void show_mem(void)
 {
         int free = 0, total = 0, reserved = 0;
@@ -50,14 +79,15 @@ void show_mem(void)
         show_free_areas();
         for_each_online_node(node) {
                 pg_data_t *n = NODE_DATA(node);
-                struct page *map = n->node_mem_map - n->node_start_pfn;
+                struct page *map = pgdat_page_nr(n, 0) - n->node_start_pfn;
 
                 for_each_nodebank (i,mi,node) {
+                        struct membank *bank = &mi->bank[i];
                         unsigned int pfn1, pfn2;
                         struct page *page, *end;
 
-                        pfn1 = __phys_to_pfn(mi->bank[i].start);
-                        pfn2 = __phys_to_pfn(mi->bank[i].size + mi->bank[i].start);
+                        pfn1 = bank_pfn_start(bank);
+                        pfn2 = bank_pfn_end(bank);
 
                         page = map + pfn1;
                         end  = map + pfn2;
@@ -96,17 +126,17 @@ void show_mem(void)
 static unsigned int __init
 find_bootmap_pfn(int node, struct meminfo *mi, unsigned int bootmap_pages)
 {
-        unsigned int start_pfn, bank, bootmap_pfn;
+        unsigned int start_pfn, i, bootmap_pfn;
 
         start_pfn   = PAGE_ALIGN(__pa(&_end)) >> PAGE_SHIFT;
         bootmap_pfn = 0;
 
-        for_each_nodebank(bank, mi, node) {
+        for_each_nodebank(i, mi, node) {
+                struct membank *bank = &mi->bank[i];
                 unsigned int start, end;
 
-                start = mi->bank[bank].start >> PAGE_SHIFT;
-                end   = (mi->bank[bank].size +
-                         mi->bank[bank].start) >> PAGE_SHIFT;
+                start = bank_pfn_start(bank);
+                end   = bank_pfn_end(bank);
 
                 if (end < start_pfn)
                         continue;
@@ -145,13 +175,10 @@ static int __init check_initrd(struct meminfo *mi)
                 initrd_node = -1;
 
                 for (i = 0; i < mi->nr_banks; i++) {
-                        unsigned long bank_end;
-
-                        bank_end = mi->bank[i].start + mi->bank[i].size;
-
-                        if (mi->bank[i].start <= phys_initrd_start &&
-                            end <= bank_end)
-                                initrd_node = mi->bank[i].node;
+                        struct membank *bank = &mi->bank[i];
+                        if (bank_phys_start(bank) <= phys_initrd_start &&
+                            end <= bank_phys_end(bank))
+                                initrd_node = bank->node;
                 }
         }
 
@@ -171,19 +198,17 @@ static inline void map_memory_bank(struct membank *bank)
 #ifdef CONFIG_MMU
         struct map_desc map;
 
-        map.pfn = __phys_to_pfn(bank->start);
-        map.virtual = __phys_to_virt(bank->start);
-        map.length = bank->size;
+        map.pfn = bank_pfn_start(bank);
+        map.virtual = __phys_to_virt(bank_phys_start(bank));
+        map.length = bank_phys_size(bank);
         map.type = MT_MEMORY;
 
         create_mapping(&map);
 #endif
 }
 
-static unsigned long __init
-bootmem_init_node(int node, int initrd_node, struct meminfo *mi)
+static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
 {
-        unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
         unsigned long start_pfn, end_pfn, boot_pfn;
         unsigned int boot_pages;
         pg_data_t *pgdat;
@@ -199,8 +224,8 @@ bootmem_init_node(int node, int initrd_node, struct meminfo *mi)
                 struct membank *bank = &mi->bank[i];
                 unsigned long start, end;
 
-                start = bank->start >> PAGE_SHIFT;
-                end = (bank->start + bank->size) >> PAGE_SHIFT;
+                start = bank_pfn_start(bank);
+                end = bank_pfn_end(bank);
 
                 if (start_pfn > start)
                         start_pfn = start;
@@ -230,8 +255,11 @@ bootmem_init_node(int node, int initrd_node, struct meminfo *mi)
         pgdat = NODE_DATA(node);
         init_bootmem_node(pgdat, boot_pfn, start_pfn, end_pfn);
 
-        for_each_nodebank(i, mi, node)
-                free_bootmem_node(pgdat, mi->bank[i].start, mi->bank[i].size);
+        for_each_nodebank(i, mi, node) {
+                struct membank *bank = &mi->bank[i];
+                free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
+                memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
+        }
 
         /*
          * Reserve the bootmem bitmap for this node.
@@ -239,31 +267,39 @@ bootmem_init_node(int node, int initrd_node, struct meminfo *mi)
         reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
                              boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
 
-        /*
-         * Reserve any special node zero regions.
-         */
-        if (node == 0)
-                reserve_node_zero(pgdat);
+        return end_pfn;
+}
 
+static void __init bootmem_reserve_initrd(int node)
+{
 #ifdef CONFIG_BLK_DEV_INITRD
-        /*
-         * If the initrd is in this node, reserve its memory.
-         */
-        if (node == initrd_node) {
-                int res = reserve_bootmem_node(pgdat, phys_initrd_start,
-                                     phys_initrd_size, BOOTMEM_EXCLUSIVE);
-
-                if (res == 0) {
-                        initrd_start = __phys_to_virt(phys_initrd_start);
-                        initrd_end = initrd_start + phys_initrd_size;
-                } else {
-                        printk(KERN_ERR
-                                "INITRD: 0x%08lx+0x%08lx overlaps in-use "
-                                "memory region - disabling initrd\n",
-                                phys_initrd_start, phys_initrd_size);
-                }
+        pg_data_t *pgdat = NODE_DATA(node);
+        int res;
+
+        res = reserve_bootmem_node(pgdat, phys_initrd_start,
+                             phys_initrd_size, BOOTMEM_EXCLUSIVE);
+
+        if (res == 0) {
+                initrd_start = __phys_to_virt(phys_initrd_start);
+                initrd_end = initrd_start + phys_initrd_size;
+        } else {
+                printk(KERN_ERR
+                        "INITRD: 0x%08lx+0x%08lx overlaps in-use "
+                        "memory region - disabling initrd\n",
+                        phys_initrd_start, phys_initrd_size);
         }
 #endif
+}
+
+static void __init bootmem_free_node(int node, struct meminfo *mi)
+{
+        unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
+        unsigned long start_pfn, end_pfn;
+        pg_data_t *pgdat = NODE_DATA(node);
+        int i;
+
+        start_pfn = pgdat->bdata->node_min_pfn;
+        end_pfn = pgdat->bdata->node_low_pfn;
 
         /*
          * initialise the zones within this node.
@@ -284,7 +320,7 @@ bootmem_init_node(int node, int initrd_node, struct meminfo *mi)
          */
         zhole_size[0] = zone_size[0];
         for_each_nodebank(i, mi, node)
-                zhole_size[0] -= mi->bank[i].size >> PAGE_SHIFT;
+                zhole_size[0] -= bank_pfn_size(&mi->bank[i]);
 
         /*
          * Adjust the sizes according to any special requirements for
@@ -293,21 +329,12 @@ bootmem_init_node(int node, int initrd_node, struct meminfo *mi)
         arch_adjust_zones(node, zone_size, zhole_size);
 
         free_area_init_node(node, zone_size, start_pfn, zhole_size);
-
-        return end_pfn;
 }
 
 void __init bootmem_init(struct meminfo *mi)
 {
         unsigned long memend_pfn = 0;
-        int node, initrd_node, i;
-
-        /*
-         * Invalidate the node number for empty or invalid memory banks
-         */
-        for (i = 0; i < mi->nr_banks; i++)
-                if (mi->bank[i].size == 0 || mi->bank[i].node >= MAX_NUMNODES)
-                        mi->bank[i].node = -1;
+        int node, initrd_node;
 
         memcpy(&meminfo, mi, sizeof(meminfo));
 
@@ -320,9 +347,19 @@ void __init bootmem_init(struct meminfo *mi)
          * Run through each node initialising the bootmem allocator.
          */
         for_each_node(node) {
-                unsigned long end_pfn;
+                unsigned long end_pfn = bootmem_init_node(node, mi);
 
-                end_pfn = bootmem_init_node(node, initrd_node, mi);
+                /*
+                 * Reserve any special node zero regions.
+                 */
+                if (node == 0)
+                        reserve_node_zero(NODE_DATA(node));
+
+                /*
+                 * If the initrd is in this node, reserve its memory.
+                 */
+                if (node == initrd_node)
+                        bootmem_reserve_initrd(node);
 
                 /*
                  * Remember the highest memory PFN.
@@ -331,6 +368,19 @@ void __init bootmem_init(struct meminfo *mi)
                         memend_pfn = end_pfn;
         }
 
+        /*
+         * sparse_init() needs the bootmem allocator up and running.
+         */
+        sparse_init();
+
+        /*
+         * Now free memory in each node - free_area_init_node needs
+         * the sparse mem_map arrays initialized by sparse_init()
+         * for memmap_init_zone(), otherwise all PFNs are invalid.
+         */
+        for_each_node(node)
+                bootmem_free_node(node, mi);
+
         high_memory = __va(memend_pfn << PAGE_SHIFT);
 
         /*
@@ -401,7 +451,9 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
          * information on the command line.
          */
         for_each_nodebank(i, mi, node) {
-                bank_start = mi->bank[i].start >> PAGE_SHIFT;
+                struct membank *bank = &mi->bank[i];
+
+                bank_start = bank_pfn_start(bank);
                 if (bank_start < prev_bank_end) {
                         printk(KERN_ERR "MEM: unordered memory banks.  "
                                 "Not freeing memmap.\n");
@@ -415,8 +467,7 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
                 if (prev_bank_end && prev_bank_end != bank_start)
                         free_memmap(node, prev_bank_end, bank_start);
 
-                prev_bank_end = (mi->bank[i].start +
-                                 mi->bank[i].size) >> PAGE_SHIFT;
+                prev_bank_end = bank_pfn_end(bank);
         }
 }
 
@@ -461,8 +512,8 @@ void __init mem_init(void)
 
         num_physpages = 0;
         for (i = 0; i < meminfo.nr_banks; i++) {
-                num_physpages += meminfo.bank[i].size >> PAGE_SHIFT;
-                printk(" %ldMB", meminfo.bank[i].size >> 20);
+                num_physpages += bank_pfn_size(&meminfo.bank[i]);
+                printk(" %ldMB", bank_phys_size(&meminfo.bank[i]) >> 20);
         }
 
         printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c
index 7429f8c01015..ffad039cbb73 100644
--- a/arch/arm/mm/iomap.c
+++ b/arch/arm/mm/iomap.c
@@ -7,8 +7,7 @@
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/ioport.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 #ifdef __io
 void __iomem *ioport_map(unsigned long port, unsigned int nr)
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index b81dbf9ffb77..18373f73f2fc 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -24,9 +24,10 @@
 #include <linux/errno.h>
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
+#include <linux/io.h>
 
+#include <asm/cputype.h>
 #include <asm/cacheflush.h>
-#include <asm/io.h>
 #include <asm/mmu_context.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
@@ -55,8 +56,7 @@ static int remap_area_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
                 if (!pte_none(*pte))
                         goto bad;
 
-                set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot),
-                            type->prot_pte_ext);
+                set_pte_ext(pte, pfn_pte(phys_addr >> PAGE_SHIFT, prot), 0);
                 phys_addr += PAGE_SIZE;
         } while (pte++, addr += PAGE_SIZE, addr != end);
         return 0;
@@ -332,15 +332,14 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
-void __iounmap(volatile void __iomem *addr)
+void __iounmap(volatile void __iomem *io_addr)
 {
+        void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
 #ifndef CONFIG_SMP
         struct vm_struct **p, *tmp;
 #endif
         unsigned int section_mapping = 0;
 
-        addr = (volatile void __iomem *)(PAGE_MASK & (unsigned long)addr);
-
 #ifndef CONFIG_SMP
         /*
          * If this is a section based mapping we need to handle it
@@ -351,7 +350,7 @@ void __iounmap(volatile void __iomem *addr)
          */
         write_lock(&vmlist_lock);
         for (p = &vmlist ; (tmp = *p) ; p = &tmp->next) {
-                if((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) {
+                if ((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) {
                         if (tmp->flags & VM_ARM_SECTION_MAPPING) {
                                 *p = tmp->next;
                                 unmap_area_sections((unsigned long)tmp->addr,
@@ -366,6 +365,6 @@ void __iounmap(volatile void __iomem *addr)
 #endif
 
         if (!section_mapping)
-                vunmap((void __force *)addr);
+                vunmap(addr);
 }
 EXPORT_SYMBOL(__iounmap);
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 7647c597fc59..5d9f53907b4e 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -18,7 +18,6 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
 
 struct mem_type {
         unsigned int prot_pte;
-        unsigned int prot_pte_ext;
         unsigned int prot_l1;
         unsigned int prot_sect;
         unsigned int domain;
@@ -35,3 +34,5 @@ struct pglist_data;
 void __init create_mapping(struct map_desc *md);
 void __init bootmem_init(struct meminfo *mi);
 void reserve_node_zero(struct pglist_data *pgdat);
+
+extern void _text, _stext, _etext, __data_start, _end, __init_begin, __init_end;
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 3f6dc40b8353..5358fcc7f61e 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -6,6 +6,8 @@
 #include <linux/mman.h>
 #include <linux/shm.h>
 #include <linux/sched.h>
+#include <linux/io.h>
+#include <asm/cputype.h>
 #include <asm/system.h>
 
 #define COLOUR_ALIGN(addr,pgoff)                \
@@ -37,8 +39,8 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
          * caches alias.  This is indicated by bits 9 and 21 of the
          * cache type register.
          */
-        cache_type = read_cpuid(CPUID_CACHETYPE);
-        if (cache_type != read_cpuid(CPUID_ID)) {
+        cache_type = read_cpuid_cachetype();
+        if (cache_type != read_cpuid_id()) {
                 aliasing = (cache_type | cache_type >> 12) & (1 << 11);
                 if (aliasing)
                         do_align = filp || flags & MAP_SHARED;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index a713e40e1f1a..8ba754064559 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -15,6 +15,7 @@
 #include <linux/mman.h>
 #include <linux/nodemask.h>
 
+#include <asm/cputype.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/sizes.h>
@@ -27,9 +28,6 @@
 
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 
-extern void _stext, _etext, __data_start, _end;
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-
 /*
  * empty_zero_page is a special page that is used for
  * zero-initialized data and COW.
@@ -68,27 +66,27 @@ static struct cachepolicy cache_policies[] __initdata = {
                 .policy         = "uncached",
                 .cr_mask        = CR_W|CR_C,
                 .pmd            = PMD_SECT_UNCACHED,
-                .pte            = 0,
+                .pte            = L_PTE_MT_UNCACHED,
         }, {
                 .policy         = "buffered",
                 .cr_mask        = CR_C,
                 .pmd            = PMD_SECT_BUFFERED,
-                .pte            = PTE_BUFFERABLE,
+                .pte            = L_PTE_MT_BUFFERABLE,
         }, {
                 .policy         = "writethrough",
                 .cr_mask        = 0,
                 .pmd            = PMD_SECT_WT,
-                .pte            = PTE_CACHEABLE,
+                .pte            = L_PTE_MT_WRITETHROUGH,
         }, {
                 .policy         = "writeback",
                 .cr_mask        = 0,
                 .pmd            = PMD_SECT_WB,
-                .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
+                .pte            = L_PTE_MT_WRITEBACK,
         }, {
                 .policy         = "writealloc",
                 .cr_mask        = 0,
                 .pmd            = PMD_SECT_WBWA,
-                .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
+                .pte            = L_PTE_MT_WRITEALLOC,
         }
 };
 
@@ -186,35 +184,28 @@ void adjust_cr(unsigned long mask, unsigned long set)
 
 static struct mem_type mem_types[] = {
         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
-                .prot_pte       = PROT_PTE_DEVICE,
+                .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
+                                  L_PTE_SHARED,
                 .prot_l1        = PMD_TYPE_TABLE,
                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_UNCACHED,
                 .domain         = DOMAIN_IO,
         },
         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
-                .prot_pte       = PROT_PTE_DEVICE,
-                .prot_pte_ext   = PTE_EXT_TEX(2),
+                .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
                 .prot_l1        = PMD_TYPE_TABLE,
                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
                 .domain         = DOMAIN_IO,
         },
         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
-                .prot_pte       = PROT_PTE_DEVICE | L_PTE_CACHEABLE | L_PTE_BUFFERABLE,
+                .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
                 .prot_l1        = PMD_TYPE_TABLE,
                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
                 .domain         = DOMAIN_IO,
         },      
-        [MT_DEVICE_IXP2000] = {   /* IXP2400 requires XCB=101 for on-chip I/O */
-                .prot_pte       = PROT_PTE_DEVICE,
-                .prot_l1        = PMD_TYPE_TABLE,
-                .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE |
-                                  PMD_SECT_TEX(1),
-                .domain         = DOMAIN_IO,
-        },
         [MT_DEVICE_WC] = {      /* ioremap_wc */
-                .prot_pte       = PROT_PTE_DEVICE,
+                .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
                 .prot_l1        = PMD_TYPE_TABLE,
-                .prot_sect      = PROT_SECT_DEVICE,
+                .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE,
                 .domain         = DOMAIN_IO,
         },
         [MT_CACHECLEAN] = {
@@ -259,7 +250,7 @@ static void __init build_mem_type_table(void)
 {
         struct cachepolicy *cp;
         unsigned int cr = get_cr();
-        unsigned int user_pgprot, kern_pgprot;
+        unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
         int cpu_arch = cpu_architecture();
         int i;
 
@@ -277,6 +268,9 @@ static void __init build_mem_type_table(void)
                         cachepolicy = CPOLICY_WRITEBACK;
                 ecc_mask = 0;
         }
+#ifdef CONFIG_SMP
+        cachepolicy = CPOLICY_WRITEALLOC;
+#endif
 
         /*
          * On non-Xscale3 ARMv5-and-older systems, use CB=01
@@ -285,11 +279,8 @@ static void __init build_mem_type_table(void)
          * in xsc3 parlance, Uncached Normal in ARMv6 parlance).
          */
         if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
-                mem_types[MT_DEVICE_WC].prot_pte_ext |= PTE_EXT_TEX(1);
                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
-        } else {
-                mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_BUFFERABLE;
-                mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
+                mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE;
         }
 
         /*
@@ -312,7 +303,15 @@ static void __init build_mem_type_table(void)
         }
 
         cp = &cache_policies[cachepolicy];
-        kern_pgprot = user_pgprot = cp->pte;
+        vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
+
+#ifndef CONFIG_SMP
+        /*
+         * Only use write-through for non-SMP systems
+         */
+        if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
+                vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
+#endif
 
         /*
          * Enable CPU-specific coherency if supported.
@@ -340,7 +339,6 @@ static void __init build_mem_type_table(void)
                 /*
                  * Mark the device area as "shared device"
                  */
-                mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
                 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 
 #ifdef CONFIG_SMP
@@ -349,30 +347,21 @@ static void __init build_mem_type_table(void)
                  */
                 user_pgprot |= L_PTE_SHARED;
                 kern_pgprot |= L_PTE_SHARED;
+                vecs_pgprot |= L_PTE_SHARED;
                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 #endif
         }
 
         for (i = 0; i < 16; i++) {
                 unsigned long v = pgprot_val(protection_map[i]);
-                v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
-                protection_map[i] = __pgprot(v);
+                protection_map[i] = __pgprot(v | user_pgprot);
         }
 
-        mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
-        mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
+        mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
+        mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 
-        if (cpu_arch >= CPU_ARCH_ARMv5) {
-#ifndef CONFIG_SMP
-                /*
-                 * Only use write-through for non-SMP systems
-                 */
-                mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
-                mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
-#endif
-        } else {
+        if (cpu_arch < CPU_ARCH_ARMv5)
                 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
-        }
 
         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
@@ -420,8 +409,7 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 
         pte = pte_offset_kernel(pmd, addr);
         do {
-                set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
-                            type->prot_pte_ext);
+                set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
                 pfn++;
         } while (pte++, addr += PAGE_SIZE, addr != end);
 }
@@ -588,12 +576,35 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
                 create_mapping(io_desc + i);
 }
 
+static unsigned long __initdata vmalloc_reserve = SZ_128M;
+
+/*
+ * vmalloc=size forces the vmalloc area to be exactly 'size'
+ * bytes. This can be used to increase (or decrease) the vmalloc
+ * area - the default is 128m.
+ */
+static void __init early_vmalloc(char **arg)
+{
+        vmalloc_reserve = memparse(*arg, arg);
+
+        if (vmalloc_reserve < SZ_16M) {
+                vmalloc_reserve = SZ_16M;
+                printk(KERN_WARNING
+                        "vmalloc area too small, limiting to %luMB\n",
+                        vmalloc_reserve >> 20);
+        }
+}
+__early_param("vmalloc=", early_vmalloc);
+
+#define VMALLOC_MIN     (void *)(VMALLOC_END - vmalloc_reserve)
+
 static int __init check_membank_valid(struct membank *mb)
 {
         /*
-         * Check whether this memory region has non-zero size.
+         * Check whether this memory region has non-zero size or
+         * invalid node number.
          */
-        if (mb->size == 0)
+        if (mb->size == 0 || mb->node >= MAX_NUMNODES)
                 return 0;
 
         /*
@@ -627,8 +638,7 @@ static int __init check_membank_valid(struct membank *mb)
 
 static void __init sanity_check_meminfo(struct meminfo *mi)
 {
-        int i;
-        int j;
+        int i, j;
 
         for (i = 0, j = 0; i < mi->nr_banks; i++) {
                 if (check_membank_valid(&mi->bank[i]))
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 63c62fdea521..07b62b238979 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -7,16 +7,14 @@
 #include <linux/mm.h>
 #include <linux/pagemap.h>
 #include <linux/bootmem.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/io.h>
 #include <asm/page.h>
 #include <asm/mach/arch.h>
 
 #include "mm.h"
 
-extern void _stext, __data_start, _end;
-
 /*
  * Reserve the various regions of node 0
  */
@@ -43,12 +41,26 @@ void __init reserve_node_zero(pg_data_t *pgdat)
                         BOOTMEM_DEFAULT);
 }
 
+static void __init sanity_check_meminfo(struct meminfo *mi)
+{
+        int i, j;
+
+        for (i = 0, j = 0; i < mi->nr_banks; i++) {
+                struct membank *mb = &mi->bank[i];
+
+                if (mb->size != 0 && mb->node < MAX_NUMNODES)
+                        mi->bank[j++] = mi->bank[i];
+        }
+        mi->nr_banks = j;
+}
+
 /*
  * paging_init() sets up the page tables, initialises the zone memory
  * maps, and sets up the zero page, bad page and bad page tables.
  */
 void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
 {
+        sanity_check_meminfo(mi);
         bootmem_init(mi);
 }
 
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 5673f4d6113b..b5551bf010aa 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -29,7 +29,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
@@ -399,29 +399,7 @@ ENTRY(cpu_arm1020_switch_mm)
         .align  5
 ENTRY(cpu_arm1020_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        eor     r3, r1, #0x0a                   @ C & small page?
-        tst     r3, #0x0b
-        biceq   r2, r2, #4
-#endif
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext
         mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         mcr     p15, 0, r0, c7, c10, 4
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 4343fdb0e9e5..8bc6740c29eb 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -29,7 +29,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
@@ -383,29 +383,7 @@ ENTRY(cpu_arm1020e_switch_mm)
         .align  5
 ENTRY(cpu_arm1020e_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        eor     r3, r1, #0x0a                   @ C & small page?
-        tst     r3, #0x0b
-        biceq   r2, r2, #4
-#endif
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext
         mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 2a4ea1659e96..2cd03e66c0a3 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
@@ -365,29 +365,7 @@ ENTRY(cpu_arm1022_switch_mm)
         .align  5
 ENTRY(cpu_arm1022_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        eor     r3, r1, #0x0a                   @ C & small page?
-        tst     r3, #0x0b
-        biceq   r2, r2, #4
-#endif
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext
         mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 77a1babd421c..ad961a897f6e 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
@@ -354,29 +354,7 @@ ENTRY(cpu_arm1026_switch_mm)
         .align  5
 ENTRY(cpu_arm1026_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        eor     r3, r1, #0x0a                   @ C & small page?
-        tst     r3, #0x0b
-        biceq   r2, r2, #4
-#endif
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext
         mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index c371fc87776e..80d6e1de069a 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -15,11 +15,13 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 
+#include "proc-macros.S"
+
 ENTRY(cpu_arm6_dcache_clean_area)
 ENTRY(cpu_arm7_dcache_clean_area)
                 mov     pc, lr
@@ -214,30 +216,13 @@ ENTRY(cpu_arm7_switch_mm)
  *         : r1 = value to set
  * Purpose : Set a PTE and flush it out of any WB cache
  */
-                .align  5
+        .align  5
 ENTRY(cpu_arm6_set_pte_ext)
 ENTRY(cpu_arm7_set_pte_ext)
 #ifdef CONFIG_MMU
-                str     r1, [r0], #-2048                @ linux version
-
-                eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-                bic     r2, r1, #PTE_SMALL_AP_MASK
-                bic     r2, r2, #PTE_TYPE_MASK
-                orr     r2, r2, #PTE_TYPE_SMALL
-
-                tst     r1, #L_PTE_USER                 @ User?
-                orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-                tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-                orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-                tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young
-                movne   r2, #0
-
-                str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext wc_disable=0
 #endif /* CONFIG_MMU */
-                mov     pc, lr
+        mov     pc, lr
 
 /*
  * Function: _arm6_7_reset
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index eda733d30455..85ae18695f10 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -36,7 +36,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
@@ -93,29 +93,12 @@ ENTRY(cpu_arm720_switch_mm)
  *         : r1 = value to set
  * Purpose : Set a PTE and flush it out of any WB cache
  */
-                .align  5
+        .align  5
 ENTRY(cpu_arm720_set_pte_ext)
 #ifdef CONFIG_MMU
-                str     r1, [r0], #-2048                @ linux version
-
-                eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-                bic     r2, r1, #PTE_SMALL_AP_MASK
-                bic     r2, r2, #PTE_TYPE_MASK
-                orr     r2, r2, #PTE_TYPE_SMALL
-
-                tst     r1, #L_PTE_USER                 @ User?
-                orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-                tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-                orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-                tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young
-                movne   r2, #0
-
-                str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext wc_disable=0
 #endif
-                mov     pc, lr
+        mov     pc, lr
 
 /*
  * Function: arm720_reset
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 3a57376c8bc9..4f95bee63e95 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 7b3ecdeb5370..93e05fa7bed4 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 28cdb060df45..914d688394fc 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -28,7 +28,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -351,33 +351,11 @@ ENTRY(cpu_arm920_switch_mm)
         .align  5
 ENTRY(cpu_arm920_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        eor     r3, r2, #0x0a                   @ C & small page?
-        tst     r3, #0x0b
-        biceq   r2, r2, #4
-#endif
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext
         mov     r0, r0
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-#endif /* CONFIG_MMU */
+#endif
         mov     pc, lr
 
         __INIT
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 94ddcb4a4b76..51c9c9859e58 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -29,7 +29,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -355,29 +355,7 @@ ENTRY(cpu_arm922_switch_mm)
         .align  5
 ENTRY(cpu_arm922_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        eor     r3, r2, #0x0a                   @ C & small page?
-        tst     r3, #0x0b
-        biceq   r2, r2, #4
-#endif
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext
         mov     r0, r0
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index d045812f3399..2724526d89c1 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -52,7 +52,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -398,29 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
         .align  5
 ENTRY(cpu_arm925_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        eor     r3, r2, #0x0a                   @ C & small page?
-        tst     r3, #0x0b
-        biceq   r2, r2, #4
-#endif
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext
         mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 4cd33169a7c9..54466937bff9 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -28,7 +28,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -359,29 +359,7 @@ ENTRY(cpu_arm926_switch_mm)
         .align  5
 ENTRY(cpu_arm926_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-        eor     r3, r2, #0x0a                   @ C & small page?
-        tst     r3, #0x0b
-        biceq   r2, r2, #4
-#endif
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext
         mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 551244d5ca19..f595117caf55 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -11,7 +11,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 6168c6160dee..e03f6ff1fb26 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -13,7 +13,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index c85c1f50e396..be6c11d2b3fb 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index f2e5884c513a..0fe1f8fc3488 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -22,7 +22,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -80,7 +80,8 @@ ENTRY(cpu_feroceon_proc_fin)
         msr     cpsr_c, ip
         bl      feroceon_flush_kern_cache_all
 
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
         mov     r0, #0
         mcr     p15, 1, r0, c15, c9, 0          @ clean L2
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
@@ -389,7 +390,8 @@ ENTRY(feroceon_range_cache_fns)
 
         .align  5
 ENTRY(cpu_feroceon_dcache_clean_area)
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
         mov     r2, r0
         mov     r3, r1
 #endif
@@ -397,7 +399,8 @@ ENTRY(cpu_feroceon_dcache_clean_area)
         add     r0, r0, #CACHE_DLINESIZE
         subs    r1, r1, #CACHE_DLINESIZE
         bhi     1b
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
 1:      mcr     p15, 1, r2, c15, c9, 1          @ clean L2 entry
         add     r2, r2, #CACHE_DLINESIZE
         subs    r3, r3, #CACHE_DLINESIZE
@@ -446,27 +449,11 @@ ENTRY(cpu_feroceon_switch_mm)
         .align  5
 ENTRY(cpu_feroceon_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext wc_disable=0
         mov     r0, r0
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
         mcr     p15, 1, r0, c15, c9, 1          @ clean L2 entry
 #endif
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index b13150052a76..54b1f721dec8 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -71,3 +71,173 @@
         mov     \reg, #16                       @ size offset
         mov     \reg, \reg, lsl \tmp            @ actual cache line size
         .endm
+
+
+/*
+ * Sanity check the PTE configuration for the code below - which makes
+ * certain assumptions about how these bits are layed out.
+ */
+#if L_PTE_SHARED != PTE_EXT_SHARED
+#error PTE shared bit mismatch
+#endif
+#if L_PTE_BUFFERABLE != PTE_BUFFERABLE
+#error PTE bufferable bit mismatch
+#endif
+#if L_PTE_CACHEABLE != PTE_CACHEABLE
+#error PTE cacheable bit mismatch
+#endif
+#if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
+     L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
+#error Invalid Linux PTE bit settings
+#endif
+
+/*
+ * The ARMv6 and ARMv7 set_pte_ext translation function.
+ *
+ * Permission translation:
+ *  YUWD  APX AP1 AP0   SVC     User
+ *  0xxx   0   0   0    no acc  no acc
+ *  100x   1   0   1    r/o     no acc
+ *  10x0   1   0   1    r/o     no acc
+ *  1011   0   0   1    r/w     no acc
+ *  110x   0   1   0    r/w     r/o
+ *  11x0   0   1   0    r/w     r/o
+ *  1111   0   1   1    r/w     r/w
+ */
+        .macro  armv6_mt_table pfx
+\pfx\()_mt_table:
+        .long   0x00                                            @ L_PTE_MT_UNCACHED
+        .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_BUFFERABLE
+        .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
+        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
+        .long   PTE_BUFFERABLE                                  @ L_PTE_MT_DEV_SHARED
+        .long   0x00                                            @ unused
+        .long   0x00                                            @ L_PTE_MT_MINICACHE (not present)
+        .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
+        .long   0x00                                            @ unused
+        .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_DEV_WC
+        .long   0x00                                            @ unused
+        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_DEV_CACHED
+        .long   PTE_EXT_TEX(2)                                  @ L_PTE_MT_DEV_NONSHARED
+        .long   0x00                                            @ unused
+        .long   0x00                                            @ unused
+        .long   0x00                                            @ unused
+        .endm
+
+        .macro  armv6_set_pte_ext pfx
+        str     r1, [r0], #-2048                @ linux version
+
+        bic     r3, r1, #0x000003fc
+        bic     r3, r3, #PTE_TYPE_MASK
+        orr     r3, r3, r2
+        orr     r3, r3, #PTE_EXT_AP0 | 2
+
+        adr     ip, \pfx\()_mt_table
+        and     r2, r1, #L_PTE_MT_MASK
+        ldr     r2, [ip, r2]
+
+        tst     r1, #L_PTE_WRITE
+        tstne   r1, #L_PTE_DIRTY
+        orreq   r3, r3, #PTE_EXT_APX
+
+        tst     r1, #L_PTE_USER
+        orrne   r3, r3, #PTE_EXT_AP1
+        tstne   r3, #PTE_EXT_APX
+        bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+
+        tst     r1, #L_PTE_EXEC
+        orreq   r3, r3, #PTE_EXT_XN
+
+        orr     r3, r3, r2
+
+        tst     r1, #L_PTE_YOUNG
+        tstne   r1, #L_PTE_PRESENT
+        moveq   r3, #0
+
+        str     r3, [r0]
+        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
+        .endm
+
+
+/*
+ * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
+ * covering most CPUs except Xscale and Xscale 3.
+ *
+ * Permission translation:
+ *  YUWD   AP   SVC     User
+ *  0xxx  0x00  no acc  no acc
+ *  100x  0x00  r/o     no acc
+ *  10x0  0x00  r/o     no acc
+ *  1011  0x55  r/w     no acc
+ *  110x  0xaa  r/w     r/o
+ *  11x0  0xaa  r/w     r/o
+ *  1111  0xff  r/w     r/w
+ */
+        .macro  armv3_set_pte_ext wc_disable=1
+        str     r1, [r0], #-2048                @ linux version
+
+        eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
+
+        bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
+        bic     r2, r2, #PTE_TYPE_MASK
+        orr     r2, r2, #PTE_TYPE_SMALL
+
+        tst     r3, #L_PTE_USER                 @ user?
+        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
+
+        tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ write and dirty?
+        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
+
+        tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
+        movne   r2, #0
+
+        .if     \wc_disable
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+        tst     r2, #PTE_CACHEABLE
+        bicne   r2, r2, #PTE_BUFFERABLE
+#endif
+        .endif
+        str     r2, [r0]                        @ hardware version
+        .endm
+
+
+/*
+ * Xscale set_pte_ext translation, split into two halves to cope
+ * with work-arounds.  r3 must be preserved by code between these
+ * two macros.
+ *
+ * Permission translation:
+ *  YUWD  AP    SVC     User
+ *  0xxx  00    no acc  no acc
+ *  100x  00    r/o     no acc
+ *  10x0  00    r/o     no acc
+ *  1011  01    r/w     no acc
+ *  110x  10    r/w     r/o
+ *  11x0  10    r/w     r/o
+ *  1111  11    r/w     r/w
+ */
+        .macro  xscale_set_pte_ext_prologue
+        str     r1, [r0], #-2048                @ linux version
+
+        eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
+
+        bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
+        orr     r2, r2, #PTE_TYPE_EXT           @ extended page
+
+        tst     r3, #L_PTE_USER                 @ user?
+        orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
+
+        tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ write and dirty?
+        orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
+                                                @ combined with user -> user r/w
+        .endm
+
+        .macro  xscale_set_pte_ext_epilogue
+        tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
+        movne   r2, #0                          @ no -> fault
+
+        str     r2, [r0]                        @ hardware version
+        mov     ip, #0
+        mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
+        mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
+        .endm
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index bbe10576c861..90a7e5279f29 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -17,7 +17,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <mach/hardware.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
@@ -153,24 +153,7 @@ ENTRY(cpu_sa110_switch_mm)
         .align  5
 ENTRY(cpu_sa110_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext wc_disable=0
         mov     r0, r0
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 871ba018252e..451e2d953e2a 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -22,7 +22,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <mach/hardware.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
@@ -166,24 +166,7 @@ ENTRY(cpu_sa1100_switch_mm)
         .align  5
 ENTRY(cpu_sa1100_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        bic     r2, r1, #PTE_SMALL_AP_MASK
-        bic     r2, r2, #PTE_TYPE_MASK
-        orr     r2, r2, #PTE_TYPE_SMALL
-
-        tst     r1, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-        tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-        tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0
-
-        str     r2, [r0]                        @ hardware version
+        armv3_set_pte_ext wc_disable=0
         mov     r0, r0
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5702ec58b2a2..294943b85973 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -13,7 +13,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
@@ -114,46 +114,12 @@ ENTRY(cpu_v6_switch_mm)
  *                (hardware version is stored at -1024 bytes)
  *      - pte   - PTE value to store
  *      - ext   - value for extended PTE bits
- *
- *      Permissions:
- *        YUWD  APX AP1 AP0     SVC     User
- *        0xxx   0   0   0      no acc  no acc
- *        100x   1   0   1      r/o     no acc
- *        10x0   1   0   1      r/o     no acc
- *        1011   0   0   1      r/w     no acc
- *        110x   0   1   0      r/w     r/o
- *        11x0   0   1   0      r/w     r/o
- *        1111   0   1   1      r/w     r/w
  */
+        armv6_mt_table cpu_v6
+
 ENTRY(cpu_v6_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
-
-        bic     r3, r1, #0x000003f0
-        bic     r3, r3, #0x00000003
-        orr     r3, r3, r2
-        orr     r3, r3, #PTE_EXT_AP0 | 2
-
-        tst     r1, #L_PTE_WRITE
-        tstne   r1, #L_PTE_DIRTY
-        orreq   r3, r3, #PTE_EXT_APX
-
-        tst     r1, #L_PTE_USER
-        orrne   r3, r3, #PTE_EXT_AP1
-        tstne   r3, #PTE_EXT_APX
-        bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
-
-        tst     r1, #L_PTE_YOUNG
-        biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
-
-        tst     r1, #L_PTE_EXEC
-        orreq   r3, r3, #PTE_EXT_XN
-
-        tst     r1, #L_PTE_PRESENT
-        moveq   r3, #0
-
-        str     r3, [r0]
-        mcr     p15, 0, r0, c7, c10, 1 @ flush_pte
+        armv6_set_pte_ext cpu_v6
 #endif
         mov     pc, lr
 
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b49f9a4c82c8..34e424041927 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -12,7 +12,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
@@ -25,9 +25,11 @@
 
 ENTRY(cpu_v7_proc_init)
         mov     pc, lr
+ENDPROC(cpu_v7_proc_init)
 
 ENTRY(cpu_v7_proc_fin)
         mov     pc, lr
+ENDPROC(cpu_v7_proc_fin)
 
 /*
  *      cpu_v7_reset(loc)
@@ -43,6 +45,7 @@ ENTRY(cpu_v7_proc_fin)
         .align  5
 ENTRY(cpu_v7_reset)
         mov     pc, r0
+ENDPROC(cpu_v7_reset)
 
 /*
  *      cpu_v7_do_idle()
@@ -52,8 +55,9 @@ ENTRY(cpu_v7_reset)
  *      IRQs are already disabled.
  */
 ENTRY(cpu_v7_do_idle)
-        .long   0xe320f003                      @ ARM V7 WFI instruction
+        wfi
         mov     pc, lr
+ENDPROC(cpu_v7_do_idle)
 
 ENTRY(cpu_v7_dcache_clean_area)
 #ifndef TLB_CAN_READ_FROM_L1_CACHE
@@ -65,6 +69,7 @@ ENTRY(cpu_v7_dcache_clean_area)
         dsb
 #endif
         mov     pc, lr
+ENDPROC(cpu_v7_dcache_clean_area)
 
 /*
  *      cpu_v7_switch_mm(pgd_phys, tsk)
@@ -89,6 +94,7 @@ ENTRY(cpu_v7_switch_mm)
         isb
 #endif
         mov     pc, lr
+ENDPROC(cpu_v7_switch_mm)
 
 /*
  *      cpu_v7_set_pte_ext(ptep, pte)
@@ -99,26 +105,19 @@ ENTRY(cpu_v7_switch_mm)
  *                (hardware version is stored at -1024 bytes)
  *      - pte   - PTE value to store
  *      - ext   - value for extended PTE bits
- *
- *      Permissions:
- *        YUWD  APX AP1 AP0     SVC     User
- *        0xxx   0   0   0      no acc  no acc
- *        100x   1   0   1      r/o     no acc
- *        10x0   1   0   1      r/o     no acc
- *        1011   0   0   1      r/w     no acc
- *        110x   0   1   0      r/w     r/o
- *        11x0   0   1   0      r/w     r/o
- *        1111   0   1   1      r/w     r/w
  */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
         str     r1, [r0], #-2048                @ linux version
 
         bic     r3, r1, #0x000003f0
-        bic     r3, r3, #0x00000003
+        bic     r3, r3, #PTE_TYPE_MASK
         orr     r3, r3, r2
         orr     r3, r3, #PTE_EXT_AP0 | 2
 
+        tst     r2, #1 << 4
+        orrne   r3, r3, #PTE_EXT_TEX(1)
+
         tst     r1, #L_PTE_WRITE
         tstne   r1, #L_PTE_DIRTY
         orreq   r3, r3, #PTE_EXT_APX
@@ -128,19 +127,18 @@ ENTRY(cpu_v7_set_pte_ext)
         tstne   r3, #PTE_EXT_APX
         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
 
-        tst     r1, #L_PTE_YOUNG
-        biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
-
         tst     r1, #L_PTE_EXEC
         orreq   r3, r3, #PTE_EXT_XN
 
-        tst     r1, #L_PTE_PRESENT
+        tst     r1, #L_PTE_YOUNG
+        tstne   r1, #L_PTE_PRESENT
         moveq   r3, #0
 
         str     r3, [r0]
         mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
 #endif
         mov     pc, lr
+ENDPROC(cpu_v7_set_pte_ext)
 
 cpu_v7_name:
         .ascii  "ARMv7 Processor"
@@ -182,12 +180,17 @@ __v7_setup:
         mov     r10, #0x1f                      @ domains 0, 1 = manager
         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
 #endif
+        ldr     r5, =0x40e040e0
+        ldr     r6, =0xff0aa1a8
+        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
+        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
         adr     r5, v7_crval
         ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0, 0           @ read control register
         bic     r0, r0, r5                      @ clear bits them
         orr     r0, r0, r6                      @ set them
         mov     pc, lr                          @ return to head.S:__ret
+ENDPROC(__v7_setup)
 
         /*
          *         V X F   I D LR
@@ -197,7 +200,7 @@ __v7_setup:
          */
         .type   v7_crval, #object
 v7_crval:
-        crval   clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
+        crval   clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
 
 __v7_setup_stack:
         .space  4 * 11                          @ 11 registers
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 7bd9e7197f60..04dc8b65401b 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -27,7 +27,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <mach/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/pgtable-hwdef.h>
@@ -345,38 +345,38 @@ ENTRY(cpu_xsc3_switch_mm)
  * cpu_xsc3_set_pte_ext(ptep, pte, ext)
  *
  * Set a PTE and flush it out
- *
  */
+cpu_xsc3_mt_table:
+        .long   0x00                                            @ L_PTE_MT_UNCACHED
+        .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_BUFFERABLE
+        .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
+        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
+        .long   PTE_EXT_TEX(1) | PTE_BUFFERABLE                 @ L_PTE_MT_DEV_SHARED
+        .long   0x00                                            @ unused
+        .long   0x00                                            @ L_PTE_MT_MINICACHE (not present)
+        .long   PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
+        .long   0x00                                            @ unused
+        .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_DEV_WC
+        .long   0x00                                            @ unused
+        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_DEV_CACHED
+        .long   PTE_EXT_TEX(2)                                  @ L_PTE_MT_DEV_NONSHARED
+        .long   0x00                                            @ unused
+        .long   0x00                                            @ unused
+        .long   0x00                                            @ unused
+
         .align  5
 ENTRY(cpu_xsc3_set_pte_ext)
-        str     r1, [r0], #-2048                @ linux version
+        xscale_set_pte_ext_prologue
 
-        bic     r2, r1, #0xff0                  @ keep C, B bits
-        orr     r2, r2, #PTE_TYPE_EXT           @ extended page
         tst     r1, #L_PTE_SHARED               @ shared?
-        orrne   r2, r2, #0x200
-
-        eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        tst     r3, #L_PTE_USER                 @ user?
-        orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
-
-        tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ write and dirty?
-        orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
-                                                @ combined with user -> user r/w
-
-        @ If it's cacheable, it needs to be in L2 also.
-        eor     ip, r1, #L_PTE_CACHEABLE
-        tst     ip, #L_PTE_CACHEABLE
-        orreq   r2, r2, #PTE_EXT_TEX(0x5)
-
-        tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
-        movne   r2, #0                          @ no -> fault
-
-        str     r2, [r0]                        @ hardware version
-        mov     ip, #0
-        mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
-        mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
+        and     r1, r1, #L_PTE_MT_MASK
+        adr     ip, cpu_xsc3_mt_table
+        ldr     ip, [ip, r1]
+        orrne   r2, r2, #PTE_EXT_COHERENT       @ interlock: mask in coherent bit
+        bic     r2, r2, #0x0c                   @ clear old C,B bits
+        orr     r2, r2, ip
+
+        xscale_set_pte_ext_epilogue
         mov     pc, lr
 
         .ltorg
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2dd85273976f..0cce37b93937 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -23,7 +23,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/page.h>
@@ -406,8 +406,6 @@ ENTRY(cpu_xscale_dcache_clean_area)
 
 /* =============================== PageTable ============================== */
 
-#define PTE_CACHE_WRITE_ALLOCATE 0
-
 /*
  * cpu_xscale_switch_mm(pgd)
  *
@@ -431,56 +429,42 @@ ENTRY(cpu_xscale_switch_mm)
  *
  * Errata 40: must set memory to write-through for user read-only pages.
  */
+cpu_xscale_mt_table:
+        .long   0x00                                            @ L_PTE_MT_UNCACHED
+        .long   PTE_BUFFERABLE                                  @ L_PTE_MT_BUFFERABLE
+        .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
+        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
+        .long   PTE_EXT_TEX(1) | PTE_BUFFERABLE                 @ L_PTE_MT_DEV_SHARED
+        .long   0x00                                            @ unused
+        .long   PTE_EXT_TEX(1) | PTE_CACHEABLE                  @ L_PTE_MT_MINICACHE
+        .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
+        .long   0x00                                            @ unused
+        .long   PTE_BUFFERABLE                                  @ L_PTE_MT_DEV_WC
+        .long   0x00                                            @ unused
+        .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_DEV_CACHED
+        .long   0x00                                            @ L_PTE_MT_DEV_NONSHARED
+        .long   0x00                                            @ unused
+        .long   0x00                                            @ unused
+        .long   0x00                                            @ unused
+
         .align  5
 ENTRY(cpu_xscale_set_pte_ext)
-        str     r1, [r0], #-2048                @ linux version
-
-        bic     r2, r1, #0xff0
-        orr     r2, r2, #PTE_TYPE_EXT           @ extended page
-
-        eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-        tst     r3, #L_PTE_USER                 @ User?
-        orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
-
-        tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-        orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
-                                                @ combined with user -> user r/w
-
-        @
-        @ Handle the X bit.  We want to set this bit for the minicache
-        @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
-        @ and we have a writeable, cacheable region.  If we ignore the
-        @ U and E bits, we can allow user space to use the minicache as
-        @ well.
-        @
-        @  X = (C & ~W & ~B) | (C & W & B & write_allocate)
-        @
-        eor     ip, r1, #L_PTE_CACHEABLE
-        tst     ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
-#if PTE_CACHE_WRITE_ALLOCATE
-        eorne   ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
-        tstne   ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
-#endif
-        orreq   r2, r2, #PTE_EXT_TEX(1)
+        xscale_set_pte_ext_prologue
 
         @
-        @ Erratum 40: The B bit must be cleared for a user read-only
-        @ cacheable page.
-        @
-        @  B = B & ~(U & C & ~W)
+        @ Erratum 40: must set memory to write-through for user read-only pages
         @
-        and     ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
-        teq     ip, #L_PTE_USER | L_PTE_CACHEABLE
-        biceq   r2, r2, #PTE_BUFFERABLE
+        and     ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2)
+        teq     ip, #L_PTE_MT_WRITEBACK | L_PTE_USER
 
-        tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-        movne   r2, #0                          @ no -> fault
+        moveq   r1, #L_PTE_MT_WRITETHROUGH
+        and     r1, r1, #L_PTE_MT_MASK
+        adr     ip, cpu_xscale_mt_table
+        ldr     ip, [ip, r1]
+        bic     r2, r2, #0x0c
+        orr     r2, r2, ip
 
-        str     r2, [r0]                        @ hardware version
-        mov     ip, #0
-        mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
-        mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
+        xscale_set_pte_ext_epilogue
         mov     pc, lr
 
 
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index b56dda8052f7..24ba5109f2e7 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -51,6 +51,7 @@ ENTRY(v7wbi_flush_user_tlb_range)
         mcr     p15, 0, ip, c7, c5, 6           @ flush BTAC/BTB
         dsb
         mov     pc, lr
+ENDPROC(v7wbi_flush_user_tlb_range)
 
 /*
  *      v7wbi_flush_kern_tlb_range(start,end)
@@ -77,6 +78,7 @@ ENTRY(v7wbi_flush_kern_tlb_range)
         dsb
         isb
         mov     pc, lr
+ENDPROC(v7wbi_flush_kern_tlb_range)
 
         .section ".text.init", #alloc, #execinstr
 
diff --git a/arch/arm/nwfpe/fpa11_cpdt.c b/arch/arm/nwfpe/fpa11_cpdt.c
index 79f8e67cc6c1..d31c49f953b1 100644
--- a/arch/arm/nwfpe/fpa11_cpdt.c
+++ b/arch/arm/nwfpe/fpa11_cpdt.c
@@ -26,7 +26,7 @@
 #include "fpmodule.h"
 #include "fpmodule.inl"
 
-#include <asm/uaccess.h>
+#include <linux/uaccess.h>
 
 static inline void loadSingle(const unsigned int Fn, const unsigned int __user *pMem)
 {
diff --git a/arch/arm/oprofile/Makefile b/arch/arm/oprofile/Makefile
index e61d0cc520b7..88e31f549f50 100644
--- a/arch/arm/oprofile/Makefile
+++ b/arch/arm/oprofile/Makefile
@@ -11,3 +11,4 @@ oprofile-$(CONFIG_CPU_XSCALE)		+= op_model_xscale.o
 oprofile-$(CONFIG_OPROFILE_ARM11_CORE)  += op_model_arm11_core.o
 oprofile-$(CONFIG_OPROFILE_ARMV6)       += op_model_v6.o
 oprofile-$(CONFIG_OPROFILE_MPCORE)      += op_model_mpcore.o
+oprofile-$(CONFIG_OPROFILE_ARMV7)       += op_model_v7.o
diff --git a/arch/arm/oprofile/backtrace.c b/arch/arm/oprofile/backtrace.c
index f5ebf30151fa..cefc21c2eee4 100644
--- a/arch/arm/oprofile/backtrace.c
+++ b/arch/arm/oprofile/backtrace.c
@@ -16,8 +16,8 @@
 #include <linux/oprofile.h>
 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <linux/uaccess.h>
 #include <asm/ptrace.h>
-#include <asm/uaccess.h>
 
 #include "../kernel/stacktrace.h"
 
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index 0a5cf3a6438b..3fcd752d6146 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -145,6 +145,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         spec = &op_mpcore_spec;
 #endif
 
+#ifdef CONFIG_OPROFILE_ARMV7
+        spec = &op_armv7_spec;
+#endif
+
         if (spec) {
                 ret = spec->init();
                 if (ret < 0)
diff --git a/arch/arm/oprofile/op_arm_model.h b/arch/arm/oprofile/op_arm_model.h
index 4899c629aa03..8c4e4f6a1de3 100644
--- a/arch/arm/oprofile/op_arm_model.h
+++ b/arch/arm/oprofile/op_arm_model.h
@@ -26,6 +26,7 @@ extern struct op_arm_model_spec op_xscale_spec;
 
 extern struct op_arm_model_spec op_armv6_spec;
 extern struct op_arm_model_spec op_mpcore_spec;
+extern struct op_arm_model_spec op_armv7_spec;
 
 extern void arm_backtrace(struct pt_regs * const regs, unsigned int depth);
 
diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c
index 92db6e035c65..4de366e8b4c5 100644
--- a/arch/arm/oprofile/op_model_mpcore.c
+++ b/arch/arm/oprofile/op_model_mpcore.c
@@ -36,8 +36,8 @@
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c
new file mode 100644
index 000000000000..f20295f14adb
--- /dev/null
+++ b/arch/arm/oprofile/op_model_v7.c
@@ -0,0 +1,411 @@
+/**
+ * op_model_v7.c
+ * ARM V7 (Cortex A8) Event Monitor Driver
+ *
+ * Copyright 2008 Jean Pihet <jpihet@mvista.com>
+ * Copyright 2004 ARM SMP Development Team
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/oprofile.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/smp.h>
+
+#include "op_counter.h"
+#include "op_arm_model.h"
+#include "op_model_v7.h"
+
+/* #define DEBUG */
+
+
+/*
+ * ARM V7 PMNC support
+ */
+
+static u32 cnt_en[CNTMAX];
+
+static inline void armv7_pmnc_write(u32 val)
+{
+        val &= PMNC_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
+}
+
+static inline u32 armv7_pmnc_read(void)
+{
+        u32 val;
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
+        return val;
+}
+
+static inline u32 armv7_pmnc_enable_counter(unsigned int cnt)
+{
+        u32 val;
+
+        if (cnt >= CNTMAX) {
+                printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), cnt);
+                return -1;
+        }
+
+        if (cnt == CCNT)
+                val = CNTENS_C;
+        else
+                val = (1 << (cnt - CNT0));
+
+        val &= CNTENS_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
+
+        return cnt;
+}
+
+static inline u32 armv7_pmnc_disable_counter(unsigned int cnt)
+{
+        u32 val;
+
+        if (cnt >= CNTMAX) {
+                printk(KERN_ERR "oprofile: CPU%u disabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), cnt);
+                return -1;
+        }
+
+        if (cnt == CCNT)
+                val = CNTENC_C;
+        else
+                val = (1 << (cnt - CNT0));
+
+        val &= CNTENC_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
+
+        return cnt;
+}
+
+static inline u32 armv7_pmnc_enable_intens(unsigned int cnt)
+{
+        u32 val;
+
+        if (cnt >= CNTMAX) {
+                printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter"
+                        " interrupt enable %d\n", smp_processor_id(), cnt);
+                return -1;
+        }
+
+        if (cnt == CCNT)
+                val = INTENS_C;
+        else
+                val = (1 << (cnt - CNT0));
+
+        val &= INTENS_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
+
+        return cnt;
+}
+
+static inline u32 armv7_pmnc_getreset_flags(void)
+{
+        u32 val;
+
+        /* Read */
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+
+        /* Write to clear flags */
+        val &= FLAG_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
+
+        return val;
+}
+
+static inline int armv7_pmnc_select_counter(unsigned int cnt)
+{
+        u32 val;
+
+        if ((cnt == CCNT) || (cnt >= CNTMAX)) {
+                printk(KERN_ERR "oprofile: CPU%u selecting wrong PMNC counteri"
+                        " %d\n", smp_processor_id(), cnt);
+                return -1;
+        }
+
+        val = (cnt - CNT0) & SELECT_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
+
+        return cnt;
+}
+
+static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val)
+{
+        if (armv7_pmnc_select_counter(cnt) == cnt) {
+                val &= EVTSEL_MASK;
+                asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
+        }
+}
+
+static void armv7_pmnc_reset_counter(unsigned int cnt)
+{
+        u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
+        u32 val = -(u32)counter_config[cpu_cnt].count;
+
+        switch (cnt) {
+        case CCNT:
+                armv7_pmnc_disable_counter(cnt);
+
+                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
+
+                if (cnt_en[cnt] != 0)
+                    armv7_pmnc_enable_counter(cnt);
+
+                break;
+
+        case CNT0:
+        case CNT1:
+        case CNT2:
+        case CNT3:
+                armv7_pmnc_disable_counter(cnt);
+
+                if (armv7_pmnc_select_counter(cnt) == cnt)
+                    asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val));
+
+                if (cnt_en[cnt] != 0)
+                    armv7_pmnc_enable_counter(cnt);
+
+                break;
+
+        default:
+                printk(KERN_ERR "oprofile: CPU%u resetting wrong PMNC counter"
+                        " %d\n", smp_processor_id(), cnt);
+                break;
+        }
+}
+
+int armv7_setup_pmnc(void)
+{
+        unsigned int cnt;
+
+        if (armv7_pmnc_read() & PMNC_E) {
+                printk(KERN_ERR "oprofile: CPU%u PMNC still enabled when setup"
+                        " new event counter.\n", smp_processor_id());
+                return -EBUSY;
+        }
+
+        /*
+         * Initialize & Reset PMNC: C bit, D bit and P bit.
+         *  Note: Using a slower count for CCNT (D bit: divide by 64) results
+         *   in a more stable system
+         */
+        armv7_pmnc_write(PMNC_P | PMNC_C | PMNC_D);
+
+
+        for (cnt = CCNT; cnt < CNTMAX; cnt++) {
+                unsigned long event;
+                u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
+
+                /*
+                 * Disable counter
+                 */
+                armv7_pmnc_disable_counter(cnt);
+                cnt_en[cnt] = 0;
+
+                if (!counter_config[cpu_cnt].enabled)
+                        continue;
+
+                event = counter_config[cpu_cnt].event & 255;
+
+                /*
+                 * Set event (if destined for PMNx counters)
+                 * We don't need to set the event if it's a cycle count
+                 */
+                if (cnt != CCNT)
+                        armv7_pmnc_write_evtsel(cnt, event);
+
+                /*
+                 * Enable interrupt for this counter
+                 */
+                armv7_pmnc_enable_intens(cnt);
+
+                /*
+                 * Reset counter
+                 */
+                armv7_pmnc_reset_counter(cnt);
+
+                /*
+                 * Enable counter
+                 */
+                armv7_pmnc_enable_counter(cnt);
+                cnt_en[cnt] = 1;
+        }
+
+        return 0;
+}
+
+static inline void armv7_start_pmnc(void)
+{
+        armv7_pmnc_write(armv7_pmnc_read() | PMNC_E);
+}
+
+static inline void armv7_stop_pmnc(void)
+{
+        armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E);
+}
+
+/*
+ * CPU counters' IRQ handler (one IRQ per CPU)
+ */
+static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg)
+{
+        struct pt_regs *regs = get_irq_regs();
+        unsigned int cnt;
+        u32 flags;
+
+
+        /*
+         * Stop IRQ generation
+         */
+        armv7_stop_pmnc();
+
+        /*
+         * Get and reset overflow status flags
+         */
+        flags = armv7_pmnc_getreset_flags();
+
+        /*
+         * Cycle counter
+         */
+        if (flags & FLAG_C) {
+                u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), CCNT);
+                armv7_pmnc_reset_counter(CCNT);
+                oprofile_add_sample(regs, cpu_cnt);
+        }
+
+        /*
+         * PMNC counters 0:3
+         */
+        for (cnt = CNT0; cnt < CNTMAX; cnt++) {
+                if (flags & (1 << (cnt - CNT0))) {
+                        u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt);
+                        armv7_pmnc_reset_counter(cnt);
+                        oprofile_add_sample(regs, cpu_cnt);
+                }
+        }
+
+        /*
+         * Allow IRQ generation
+         */
+        armv7_start_pmnc();
+
+        return IRQ_HANDLED;
+}
+
+int armv7_request_interrupts(int *irqs, int nr)
+{
+        unsigned int i;
+        int ret = 0;
+
+        for (i = 0; i < nr; i++) {
+                ret = request_irq(irqs[i], armv7_pmnc_interrupt,
+                                IRQF_DISABLED, "CP15 PMNC", NULL);
+                if (ret != 0) {
+                        printk(KERN_ERR "oprofile: unable to request IRQ%u"
+                                " for ARMv7\n",
+                               irqs[i]);
+                        break;
+                }
+        }
+
+        if (i != nr)
+                while (i-- != 0)
+                        free_irq(irqs[i], NULL);
+
+        return ret;
+}
+
+void armv7_release_interrupts(int *irqs, int nr)
+{
+        unsigned int i;
+
+        for (i = 0; i < nr; i++)
+                free_irq(irqs[i], NULL);
+}
+
+#ifdef DEBUG
+static void armv7_pmnc_dump_regs(void)
+{
+        u32 val;
+        unsigned int cnt;
+
+        printk(KERN_INFO "PMNC registers dump:\n");
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
+        printk(KERN_INFO "PMNC  =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
+        printk(KERN_INFO "CNTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
+        printk(KERN_INFO "INTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+        printk(KERN_INFO "FLAGS =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
+        printk(KERN_INFO "SELECT=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
+        printk(KERN_INFO "CCNT  =0x%08x\n", val);
+
+        for (cnt = CNT0; cnt < CNTMAX; cnt++) {
+                armv7_pmnc_select_counter(cnt);
+                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] count =0x%08x\n", cnt-CNT0, val);
+                asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", cnt-CNT0, val);
+        }
+}
+#endif
+
+
+static int irqs[] = {
+#ifdef CONFIG_ARCH_OMAP3
+        INT_34XX_BENCH_MPU_EMUL,
+#endif
+};
+
+static void armv7_pmnc_stop(void)
+{
+#ifdef DEBUG
+        armv7_pmnc_dump_regs();
+#endif
+        armv7_stop_pmnc();
+        armv7_release_interrupts(irqs, ARRAY_SIZE(irqs));
+}
+
+static int armv7_pmnc_start(void)
+{
+        int ret;
+
+#ifdef DEBUG
+        armv7_pmnc_dump_regs();
+#endif
+        ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs));
+        if (ret >= 0)
+                armv7_start_pmnc();
+
+        return ret;
+}
+
+static int armv7_detect_pmnc(void)
+{
+        return 0;
+}
+
+struct op_arm_model_spec op_armv7_spec = {
+        .init           = armv7_detect_pmnc,
+        .num_counters   = 5,
+        .setup_ctrs     = armv7_setup_pmnc,
+        .start          = armv7_pmnc_start,
+        .stop           = armv7_pmnc_stop,
+        .name           = "arm/armv7",
+};
diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h
new file mode 100644
index 000000000000..0e19bcc2e100
--- /dev/null
+++ b/arch/arm/oprofile/op_model_v7.h
@@ -0,0 +1,103 @@
+/**
+ * op_model_v7.h
+ * ARM v7 (Cortex A8) Event Monitor Driver
+ *
+ * Copyright 2008 Jean Pihet <jpihet@mvista.com>
+ * Copyright 2004 ARM SMP Development Team
+ * Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
+ * Copyright 2000-2004 MontaVista Software Inc
+ * Copyright 2004 Dave Jiang <dave.jiang@intel.com>
+ * Copyright 2004 Intel Corporation
+ * Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
+ * Copyright 2004 Oprofile Authors
+ *
+ * Read the file COPYING
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OP_MODEL_V7_H
+#define OP_MODEL_V7_H
+
+/*
+ * Per-CPU PMNC: config reg
+ */
+#define PMNC_E          (1 << 0)        /* Enable all counters */
+#define PMNC_P          (1 << 1)        /* Reset all counters */
+#define PMNC_C          (1 << 2)        /* Cycle counter reset */
+#define PMNC_D          (1 << 3)        /* CCNT counts every 64th cpu cycle */
+#define PMNC_X          (1 << 4)        /* Export to ETM */
+#define PMNC_DP         (1 << 5)        /* Disable CCNT if non-invasive debug*/
+#define PMNC_MASK       0x3f            /* Mask for writable bits */
+
+/*
+ * Available counters
+ */
+#define CCNT            0
+#define CNT0            1
+#define CNT1            2
+#define CNT2            3
+#define CNT3            4
+#define CNTMAX          5
+
+#define CPU_COUNTER(cpu, counter)       ((cpu) * CNTMAX + (counter))
+
+/*
+ * CNTENS: counters enable reg
+ */
+#define CNTENS_P0       (1 << 0)
+#define CNTENS_P1       (1 << 1)
+#define CNTENS_P2       (1 << 2)
+#define CNTENS_P3       (1 << 3)
+#define CNTENS_C        (1 << 31)
+#define CNTENS_MASK     0x8000000f      /* Mask for writable bits */
+
+/*
+ * CNTENC: counters disable reg
+ */
+#define CNTENC_P0       (1 << 0)
+#define CNTENC_P1       (1 << 1)
+#define CNTENC_P2       (1 << 2)
+#define CNTENC_P3       (1 << 3)
+#define CNTENC_C        (1 << 31)
+#define CNTENC_MASK     0x8000000f      /* Mask for writable bits */
+
+/*
+ * INTENS: counters overflow interrupt enable reg
+ */
+#define INTENS_P0       (1 << 0)
+#define INTENS_P1       (1 << 1)
+#define INTENS_P2       (1 << 2)
+#define INTENS_P3       (1 << 3)
+#define INTENS_C        (1 << 31)
+#define INTENS_MASK     0x8000000f      /* Mask for writable bits */
+
+/*
+ * EVTSEL: Event selection reg
+ */
+#define EVTSEL_MASK     0x7f            /* Mask for writable bits */
+
+/*
+ * SELECT: Counter selection reg
+ */
+#define SELECT_MASK     0x1f            /* Mask for writable bits */
+
+/*
+ * FLAG: counters overflow flag status reg
+ */
+#define FLAG_P0         (1 << 0)
+#define FLAG_P1         (1 << 1)
+#define FLAG_P2         (1 << 2)
+#define FLAG_P3         (1 << 3)
+#define FLAG_C          (1 << 31)
+#define FLAG_MASK       0x8000000f      /* Mask for writable bits */
+
+
+int armv7_setup_pmu(void);
+int armv7_start_pmu(void);
+int armv7_stop_pmu(void);
+int armv7_request_interrupts(int *, int);
+void armv7_release_interrupts(int *, int);
+
+#endif
diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c
index 7c3289c2acd7..724ab9ce2526 100644
--- a/arch/arm/oprofile/op_model_xscale.c
+++ b/arch/arm/oprofile/op_model_xscale.c
@@ -22,7 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 
-#include <asm/system.h>
+#include <asm/cputype.h>
 
 #include "op_counter.h"
 #include "op_arm_model.h"
diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c
index 6dcbcc4ad419..4efe392859ee 100644
--- a/arch/arm/plat-iop/i2c.c
+++ b/arch/arm/plat-iop/i2c.c
@@ -18,7 +18,7 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_core.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-iop/io.c b/arch/arm/plat-iop/io.c
index 39dcfb4bdc71..ed0bbece0d61 100644
--- a/arch/arm/plat-iop/io.c
+++ b/arch/arm/plat-iop/io.c
@@ -18,8 +18,8 @@
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 void * __iomem __iop3xx_ioremap(unsigned long cookie, size_t size,
         unsigned int mtype)
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 54708bf9cb15..77fa7cc7d162 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -17,7 +17,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/signal.h>
 #include <asm/system.h>
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index c53fefb6aac4..3695bbe3ee28 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -18,8 +18,8 @@
 #include <linux/time.h>
 #include <linux/init.h>
 #include <linux/timex.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/uaccess.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index e14eaad11dd5..b2a7e3fad117 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -23,4 +23,15 @@ source "arch/arm/mach-mx3/Kconfig"
 
 endmenu
 
+config MXC_IRQ_PRIOR
+        bool "Use IRQ priority"
+        depends on ARCH_MXC
+        help
+          Select this if you want to use prioritized IRQ handling.
+          This feature prevents higher priority ISR to be interrupted
+          by lower priority IRQ even IRQF_DISABLED flag is not set.
+          This may be useful in embedded applications, where are strong
+          requirements for timing.
+          Say N here, unless you have a specialized requirement.
+
 endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index db66e9ae8414..067556f7c91f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Common support
-obj-y := irq.o clock.o gpio.o time.o
+obj-y := irq.o clock.o gpio.o time.o devices.o
 
-obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o
+obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
new file mode 100644
index 000000000000..c66748267c45
--- /dev/null
+++ b/arch/arm/plat-mxc/devices.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+int __init mxc_register_device(struct platform_device *pdev, void *data)
+{
+        int ret;
+
+        pdev->dev.platform_data = data;
+
+        ret = platform_device_register(pdev);
+        if (ret)
+                pr_debug("Unable to register platform device '%s': %d\n",
+                         pdev->name, ret);
+
+        return ret;
+}
+
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
new file mode 100644
index 000000000000..b296f19fd89a
--- /dev/null
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -0,0 +1,840 @@
+/*
+ *  linux/arch/arm/plat-mxc/dma-mx1-mx2.c
+ *
+ *  i.MX DMA registration and IRQ dispatching
+ *
+ * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
+ * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/scatterlist.h>
+#include <linux/io.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <asm/dma.h>
+#include <mach/dma-mx1-mx2.h>
+
+#define DMA_DCR     0x00                /* Control Register */
+#define DMA_DISR    0x04                /* Interrupt status Register */
+#define DMA_DIMR    0x08                /* Interrupt mask Register */
+#define DMA_DBTOSR  0x0c                /* Burst timeout status Register */
+#define DMA_DRTOSR  0x10                /* Request timeout Register */
+#define DMA_DSESR   0x14                /* Transfer Error Status Register */
+#define DMA_DBOSR   0x18                /* Buffer overflow status Register */
+#define DMA_DBTOCR  0x1c                /* Burst timeout control Register */
+#define DMA_WSRA    0x40                /* W-Size Register A */
+#define DMA_XSRA    0x44                /* X-Size Register A */
+#define DMA_YSRA    0x48                /* Y-Size Register A */
+#define DMA_WSRB    0x4c                /* W-Size Register B */
+#define DMA_XSRB    0x50                /* X-Size Register B */
+#define DMA_YSRB    0x54                /* Y-Size Register B */
+#define DMA_SAR(x)  (0x80 + ((x) << 6)) /* Source Address Registers */
+#define DMA_DAR(x)  (0x84 + ((x) << 6)) /* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
+#define DMA_CCR(x)  (0x8c + ((x) << 6)) /* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
+#define DMA_BLR(x)  (0x94 + ((x) << 6)) /* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff)
+#define CNTR_CNT(x)        ((x) & 0xffffff)
+#define CCR_ACRPT          (1<<14)
+#define CCR_DMOD_LINEAR    (0x0 << 12)
+#define CCR_DMOD_2D        (0x1 << 12)
+#define CCR_DMOD_FIFO      (0x2 << 12)
+#define CCR_DMOD_EOBFIFO   (0x3 << 12)
+#define CCR_SMOD_LINEAR    (0x0 << 10)
+#define CCR_SMOD_2D        (0x1 << 10)
+#define CCR_SMOD_FIFO      (0x2 << 10)
+#define CCR_SMOD_EOBFIFO   (0x3 << 10)
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        (0x0 << 6)
+#define CCR_DSIZ_8         (0x1 << 6)
+#define CCR_DSIZ_16        (0x2 << 6)
+#define CCR_SSIZ_32        (0x0 << 4)
+#define CCR_SSIZ_8         (0x1 << 4)
+#define CCR_SSIZ_16        (0x2 << 4)
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
+
+/*
+ * struct imx_dma_channel - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ *            (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imx_dma_channel only as extension to it.
+ */
+
+struct imx_dma_channel {
+        const char *name;
+        void (*irq_handler) (int, void *);
+        void (*err_handler) (int, void *, int errcode);
+        void (*prog_handler) (int, void *, struct scatterlist *);
+        void *data;
+        dmamode_t  dma_mode;
+        struct scatterlist *sg;
+        unsigned int resbytes;
+        int dma_num;
+
+        int in_use;
+
+        u32 ccr_from_device;
+        u32 ccr_to_device;
+
+        struct timer_list watchdog;
+
+        int hw_chaining;
+};
+
+static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
+
+static struct clk *dma_clk;
+
+static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
+{
+        if (cpu_is_mx27())
+                return imxdma->hw_chaining;
+        else
+                return 0;
+}
+
+
+/*
+ * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long now;
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return 0;
+        }
+
+        now = min(imxdma->resbytes, sg->length);
+        imxdma->resbytes -= now;
+
+        if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+                __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel));
+        else
+                __raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel));
+
+        __raw_writel(now, DMA_BASE + DMA_CNTR(channel));
+
+        pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+                "size 0x%08x\n", channel,
+                 __raw_readl(DMA_BASE + DMA_DAR(channel)),
+                 __raw_readl(DMA_BASE + DMA_SAR(channel)),
+                 __raw_readl(DMA_BASE + DMA_CNTR(channel)));
+
+        return now;
+}
+
+/**
+ * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
+ * device transfer
+ *
+ * @channel: i.MX DMA channel number
+ * @dma_address: the DMA/physical memory address of the linear data block
+ *              to transfer
+ * @dma_length: length of the data block in bytes
+ * @dev_addr: physical device port address
+ * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
+ *           or %DMA_MODE_WRITE from memory to the device
+ *
+ * Return value: if incorrect parameters are provided -%EINVAL.
+ *              Zero indicates success.
+ */
+int
+imx_dma_setup_single(int channel, dma_addr_t dma_address,
+                     unsigned int dma_length, unsigned int dev_addr,
+                     dmamode_t dmamode)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+        imxdma->sg = NULL;
+        imxdma->dma_mode = dmamode;
+
+        if (!dma_address) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if (!dma_length) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+                pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+                        "dev_addr=0x%08x for read\n",
+                        channel, __func__, (unsigned int)dma_address,
+                        dma_length, dev_addr);
+
+                __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
+                __raw_writel(dma_address, DMA_BASE + DMA_DAR(channel));
+                __raw_writel(imxdma->ccr_from_device,
+                                DMA_BASE + DMA_CCR(channel));
+        } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+                pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+                        "dev_addr=0x%08x for write\n",
+                        channel, __func__, (unsigned int)dma_address,
+                        dma_length, dev_addr);
+
+                __raw_writel(dma_address, DMA_BASE + DMA_SAR(channel));
+                __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
+                __raw_writel(imxdma->ccr_to_device,
+                                DMA_BASE + DMA_CCR(channel));
+        } else {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        __raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel));
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_single);
+
+/**
+ * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
+ * @channel: i.MX DMA channel number
+ * @sg: pointer to the scatter-gather list/vector
+ * @sgcount: scatter-gather list hungs count
+ * @dma_length: total length of the transfer request in bytes
+ * @dev_addr: physical device port address
+ * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
+ *           or %DMA_MODE_WRITE from memory to the device
+ *
+ * The function sets up DMA channel state and registers to be ready for
+ * transfer specified by provided parameters. The scatter-gather emulation
+ * is set up according to the parameters.
+ *
+ * The full preparation of the transfer requires setup of more register
+ * by the caller before imx_dma_enable() can be called.
+ *
+ * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
+ *
+ * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
+ *
+ * %CCR(channel) has to specify transfer parameters, the next settings is
+ * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
+ * specified
+ *
+ * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
+ *
+ * The typical setup for %DMA_MODE_WRITE is specified by next options
+ * combination
+ *
+ * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
+ *
+ * Be careful here and do not mistakenly mix source and target device
+ * port sizes constants, they are really different:
+ * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
+ * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
+ *
+ * Return value: if incorrect parameters are provided -%EINVAL.
+ * Zero indicates success.
+ */
+int
+imx_dma_setup_sg(int channel,
+                 struct scatterlist *sg, unsigned int sgcount,
+                 unsigned int dma_length, unsigned int dev_addr,
+                 dmamode_t dmamode)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+        if (imxdma->in_use)
+                return -EBUSY;
+
+        imxdma->sg = sg;
+        imxdma->dma_mode = dmamode;
+        imxdma->resbytes = dma_length;
+
+        if (!sg || !sgcount) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if (!sg->length) {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+                pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+                        "dev_addr=0x%08x for read\n",
+                        channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+                __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel));
+                __raw_writel(imxdma->ccr_from_device,
+                                DMA_BASE + DMA_CCR(channel));
+        } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+                pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+                        "dev_addr=0x%08x for write\n",
+                        channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+                __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel));
+                __raw_writel(imxdma->ccr_to_device,
+                                DMA_BASE + DMA_CCR(channel));
+        } else {
+                printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+                       channel);
+                return -EINVAL;
+        }
+
+        imx_dma_sg_next(channel, sg);
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_sg);
+
+int
+imx_dma_config_channel(int channel, unsigned int config_port,
+        unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        u32 dreq = 0;
+
+        imxdma->hw_chaining = 0;
+
+        if (hw_chaining) {
+                imxdma->hw_chaining = 1;
+                if (!imx_dma_hw_chain(imxdma))
+                        return -EINVAL;
+        }
+
+        if (dmareq)
+                dreq = CCR_REN;
+
+        imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
+        imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+        __raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel));
+
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_config_channel);
+
+void imx_dma_config_burstlen(int channel, unsigned int burstlen)
+{
+        __raw_writel(burstlen, DMA_BASE + DMA_BLR(channel));
+}
+EXPORT_SYMBOL(imx_dma_config_burstlen);
+
+/**
+ * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
+ * handlers
+ * @channel: i.MX DMA channel number
+ * @irq_handler: the pointer to the function called if the transfer
+ *              ends successfully
+ * @err_handler: the pointer to the function called if the premature
+ *              end caused by error occurs
+ * @data: user specified value to be passed to the handlers
+ */
+int
+imx_dma_setup_handlers(int channel,
+                       void (*irq_handler) (int, void *),
+                       void (*err_handler) (int, void *, int),
+                       void *data)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return -ENODEV;
+        }
+
+        local_irq_save(flags);
+        __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
+        imxdma->irq_handler = irq_handler;
+        imxdma->err_handler = err_handler;
+        imxdma->data = data;
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_handlers);
+
+/**
+ * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
+ * handlers
+ * @channel: i.MX DMA channel number
+ * @prog_handler: the pointer to the function called if the transfer progresses
+ */
+int
+imx_dma_setup_progression_handler(int channel,
+                        void (*prog_handler) (int, void*, struct scatterlist*))
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return -ENODEV;
+        }
+
+        local_irq_save(flags);
+        imxdma->prog_handler = prog_handler;
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_progression_handler);
+
+/**
+ * imx_dma_enable - function to start i.MX DMA channel operation
+ * @channel: i.MX DMA channel number
+ *
+ * The channel has to be allocated by driver through imx_dma_request()
+ * or imx_dma_request_by_prio() function.
+ * The transfer parameters has to be set to the channel registers through
+ * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
+ * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
+ * be set prior this function call by the channel user.
+ */
+void imx_dma_enable(int channel)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+                       __func__, channel);
+                return;
+        }
+
+        if (imxdma->in_use)
+                return;
+
+        local_irq_save(flags);
+
+        __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel),
+                DMA_BASE + DMA_DIMR);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN |
+                CCR_ACRPT,
+                DMA_BASE + DMA_CCR(channel));
+
+#ifdef CONFIG_ARCH_MX2
+        if (imxdma->sg && imx_dma_hw_chain(imxdma)) {
+                imxdma->sg = sg_next(imxdma->sg);
+                if (imxdma->sg) {
+                        u32 tmp;
+                        imx_dma_sg_next(channel, imxdma->sg);
+                        tmp = __raw_readl(DMA_BASE + DMA_CCR(channel));
+                        __raw_writel(tmp | CCR_RPT | CCR_ACRPT,
+                                DMA_BASE + DMA_CCR(channel));
+                }
+        }
+#endif
+        imxdma->in_use = 1;
+
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_enable);
+
+/**
+ * imx_dma_disable - stop, finish i.MX DMA channel operatin
+ * @channel: i.MX DMA channel number
+ */
+void imx_dma_disable(int channel)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+
+        pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+        if (imx_dma_hw_chain(imxdma))
+                del_timer(&imxdma->watchdog);
+
+        local_irq_save(flags);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel),
+                DMA_BASE + DMA_DIMR);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
+                DMA_BASE + DMA_CCR(channel));
+        __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
+        imxdma->in_use = 0;
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_disable);
+
+static void imx_dma_watchdog(unsigned long chno)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
+
+        __raw_writel(0, DMA_BASE + DMA_CCR(chno));
+        imxdma->in_use = 0;
+        imxdma->sg = NULL;
+
+        if (imxdma->err_handler)
+                imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
+}
+
+static irqreturn_t dma_err_handler(int irq, void *dev_id)
+{
+        int i, disr;
+        struct imx_dma_channel *imxdma;
+        unsigned int err_mask;
+        int errcode;
+
+        disr = __raw_readl(DMA_BASE + DMA_DISR);
+
+        err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) |
+                   __raw_readl(DMA_BASE + DMA_DRTOSR) |
+                   __raw_readl(DMA_BASE + DMA_DSESR)  |
+                   __raw_readl(DMA_BASE + DMA_DBOSR);
+
+        if (!err_mask)
+                return IRQ_HANDLED;
+
+        __raw_writel(disr & err_mask, DMA_BASE + DMA_DISR);
+
+        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+                if (!(err_mask & (1 << i)))
+                        continue;
+                imxdma = &imx_dma_channels[i];
+                errcode = 0;
+
+                if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) {
+                        __raw_writel(1 << i, DMA_BASE + DMA_DBTOSR);
+                        errcode |= IMX_DMA_ERR_BURST;
+                }
+                if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) {
+                        __raw_writel(1 << i, DMA_BASE + DMA_DRTOSR);
+                        errcode |= IMX_DMA_ERR_REQUEST;
+                }
+                if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) {
+                        __raw_writel(1 << i, DMA_BASE + DMA_DSESR);
+                        errcode |= IMX_DMA_ERR_TRANSFER;
+                }
+                if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) {
+                        __raw_writel(1 << i, DMA_BASE + DMA_DBOSR);
+                        errcode |= IMX_DMA_ERR_BUFFER;
+                }
+                if (imxdma->name && imxdma->err_handler) {
+                        imxdma->err_handler(i, imxdma->data, errcode);
+                        continue;
+                }
+
+                imx_dma_channels[i].sg = NULL;
+
+                printk(KERN_WARNING
+                       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
+                       i, imxdma->name,
+                       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
+                       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
+                       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+                       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
+        }
+        return IRQ_HANDLED;
+}
+
+static void dma_irq_handle_channel(int chno)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
+
+        if (!imxdma->name) {
+                /*
+                 * IRQ for an unregistered DMA channel:
+                 * let's clear the interrupts and disable it.
+                 */
+                printk(KERN_WARNING
+                       "spurious IRQ for DMA channel %d\n", chno);
+                return;
+        }
+
+        if (imxdma->sg) {
+                u32 tmp;
+                struct scatterlist *current_sg = imxdma->sg;
+                imxdma->sg = sg_next(imxdma->sg);
+
+                if (imxdma->sg) {
+                        imx_dma_sg_next(chno, imxdma->sg);
+
+                        tmp = __raw_readl(DMA_BASE + DMA_CCR(chno));
+
+                        if (imx_dma_hw_chain(imxdma)) {
+                                /* FIXME: The timeout should probably be
+                                 * configurable
+                                 */
+                                mod_timer(&imxdma->watchdog,
+                                        jiffies + msecs_to_jiffies(500));
+
+                                tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+                                __raw_writel(tmp, DMA_BASE +
+                                                DMA_CCR(chno));
+                        } else {
+                                __raw_writel(tmp & ~CCR_CEN, DMA_BASE +
+                                                DMA_CCR(chno));
+                                tmp |= CCR_CEN;
+                        }
+
+                        __raw_writel(tmp, DMA_BASE + DMA_CCR(chno));
+
+                        if (imxdma->prog_handler)
+                                imxdma->prog_handler(chno, imxdma->data,
+                                                current_sg);
+
+                        return;
+                }
+
+                if (imx_dma_hw_chain(imxdma)) {
+                        del_timer(&imxdma->watchdog);
+                        return;
+                }
+        }
+
+        __raw_writel(0, DMA_BASE + DMA_CCR(chno));
+        imxdma->in_use = 0;
+        if (imxdma->irq_handler)
+                imxdma->irq_handler(chno, imxdma->data);
+}
+
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+        int i, disr;
+
+#ifdef CONFIG_ARCH_MX2
+        dma_err_handler(irq, dev_id);
+#endif
+
+        disr = __raw_readl(DMA_BASE + DMA_DISR);
+
+        pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+                     disr);
+
+        __raw_writel(disr, DMA_BASE + DMA_DISR);
+        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+                if (disr & (1 << i))
+                        dma_irq_handle_channel(i);
+        }
+
+        return IRQ_HANDLED;
+}
+
+/**
+ * imx_dma_request - request/allocate specified channel number
+ * @channel: i.MX DMA channel number
+ * @name: the driver/caller own non-%NULL identification
+ */
+int imx_dma_request(int channel, const char *name)
+{
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+        unsigned long flags;
+        int ret;
+
+        /* basic sanity checks */
+        if (!name)
+                return -EINVAL;
+
+        if (channel >= IMX_DMA_CHANNELS) {
+                printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
+                       __func__, channel);
+                return -EINVAL;
+        }
+
+        local_irq_save(flags);
+        if (imxdma->name) {
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
+
+#ifdef CONFIG_ARCH_MX2
+        ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA",
+                        NULL);
+        if (ret) {
+                printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n",
+                                MXC_INT_DMACH0 + channel, channel);
+                return ret;
+        }
+        init_timer(&imxdma->watchdog);
+        imxdma->watchdog.function = &imx_dma_watchdog;
+        imxdma->watchdog.data = channel;
+#endif
+
+        imxdma->name = name;
+        imxdma->irq_handler = NULL;
+        imxdma->err_handler = NULL;
+        imxdma->data = NULL;
+        imxdma->sg = NULL;
+
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(imx_dma_request);
+
+/**
+ * imx_dma_free - release previously acquired channel
+ * @channel: i.MX DMA channel number
+ */
+void imx_dma_free(int channel)
+{
+        unsigned long flags;
+        struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+        if (!imxdma->name) {
+                printk(KERN_CRIT
+                       "%s: trying to free free channel %d\n",
+                       __func__, channel);
+                return;
+        }
+
+        local_irq_save(flags);
+        /* Disable interrupts */
+        __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel),
+                DMA_BASE + DMA_DIMR);
+        __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN,
+                DMA_BASE + DMA_CCR(channel));
+        imxdma->name = NULL;
+
+#ifdef CONFIG_ARCH_MX2
+        free_irq(MXC_INT_DMACH0 + channel, NULL);
+#endif
+
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_free);
+
+/**
+ * imx_dma_request_by_prio - find and request some of free channels best
+ * suiting requested priority
+ * @channel: i.MX DMA channel number
+ * @name: the driver/caller own non-%NULL identification
+ *
+ * This function tries to find a free channel in the specified priority group
+ * This function tries to find a free channel in the specified priority group
+ * if the priority cannot be achieved it tries to look for free channel
+ * in the higher and then even lower priority groups.
+ *
+ * Return value: If there is no free channel to allocate, -%ENODEV is returned.
+ *               On successful allocation channel is returned.
+ */
+int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
+{
+        int i;
+        int best;
+
+        switch (prio) {
+        case (DMA_PRIO_HIGH):
+                best = 8;
+                break;
+        case (DMA_PRIO_MEDIUM):
+                best = 4;
+                break;
+        case (DMA_PRIO_LOW):
+        default:
+                best = 0;
+                break;
+        }
+
+        for (i = best; i < IMX_DMA_CHANNELS; i++)
+                if (!imx_dma_request(i, name))
+                        return i;
+
+        for (i = best - 1; i >= 0; i--)
+                if (!imx_dma_request(i, name))
+                        return i;
+
+        printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
+
+        return -ENODEV;
+}
+EXPORT_SYMBOL(imx_dma_request_by_prio);
+
+static int __init imx_dma_init(void)
+{
+        int ret = 0;
+        int i;
+
+        dma_clk = clk_get(NULL, "dma_clk");
+        clk_enable(dma_clk);
+
+        /* reset DMA module */
+        __raw_writel(DCR_DRST, DMA_BASE + DMA_DCR);
+
+#ifdef CONFIG_ARCH_MX1
+        ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
+        if (ret) {
+                printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
+                return ret;
+        }
+
+        ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
+        if (ret) {
+                printk(KERN_CRIT "Wow!  Can't register ERRIRQ for DMA\n");
+                free_irq(DMA_INT, NULL);
+                return ret;
+        }
+#endif
+        /* enable DMA module */
+        __raw_writel(DCR_DEN, DMA_BASE + DMA_DCR);
+
+        /* clear all interrupts */
+        __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR);
+
+        /* disable interrupts */
+        __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR);
+
+        for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+                imx_dma_channels[i].sg = NULL;
+                imx_dma_channels[i].dma_num = i;
+        }
+
+        return ret;
+}
+
+arch_initcall(imx_dma_init);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 1bc6fb0f9a83..745b48864f93 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -90,6 +90,9 @@
 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
 
+#define MXC_EXP_IO_BASE         (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES)
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
+
 #define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 0)
 #define EXPIO_INT_PB_IRQ        (MXC_EXP_IO_BASE + 1)
 #define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 24caa2b7c91d..d21f78e78819 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -39,7 +39,7 @@ struct clk {
         /* Register bit position for clock's enable/disable control. */
         u8 enable_shift;
         /* Register address for clock's enable/disable control. */
-        u32 enable_reg;
+        void __iomem *enable_reg;
         u32 flags;
         /* get the current clock rate (always a fresh value) */
         unsigned long (*get_rate) (struct clk *);
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index a6d2e24aab15..6350287a59b9 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -11,10 +11,13 @@
 #ifndef __ASM_ARCH_MXC_COMMON_H__
 #define __ASM_ARCH_MXC_COMMON_H__
 
+struct platform_device;
+
 extern void mxc_map_io(void);
 extern void mxc_init_irq(void);
 extern void mxc_timer_init(const char *clk_timer);
 extern int mxc_clocks_init(unsigned long fref);
 extern int mxc_register_gpios(void);
+extern int mxc_register_device(struct platform_device *pdev, void *data);
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
new file mode 100644
index 000000000000..e85fd946116c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -0,0 +1,89 @@
+/*
+ *  linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+ *
+ *  i.MX DMA registration and IRQ dispatching
+ *
+ * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
+ * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
+ * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <asm/dma.h>
+
+#ifndef __ASM_ARCH_MXC_DMA_H
+#define __ASM_ARCH_MXC_DMA_H
+
+#define IMX_DMA_CHANNELS  16
+
+#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
+
+#define IMX_DMA_MEMSIZE_32      (0 << 4)
+#define IMX_DMA_MEMSIZE_8       (1 << 4)
+#define IMX_DMA_MEMSIZE_16      (2 << 4)
+#define IMX_DMA_TYPE_LINEAR     (0 << 10)
+#define IMX_DMA_TYPE_2D         (1 << 10)
+#define IMX_DMA_TYPE_FIFO       (2 << 10)
+
+#define IMX_DMA_ERR_BURST     (1 << 0)
+#define IMX_DMA_ERR_REQUEST   (1 << 1)
+#define IMX_DMA_ERR_TRANSFER  (1 << 2)
+#define IMX_DMA_ERR_BUFFER    (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
+
+int
+imx_dma_config_channel(int channel, unsigned int config_port,
+        unsigned int config_mem, unsigned int dmareq, int hw_chaining);
+
+void
+imx_dma_config_burstlen(int channel, unsigned int burstlen);
+
+int
+imx_dma_setup_single(int channel, dma_addr_t dma_address,
+                unsigned int dma_length, unsigned int dev_addr,
+                dmamode_t dmamode);
+
+int
+imx_dma_setup_sg(int channel, struct scatterlist *sg,
+                unsigned int sgcount, unsigned int dma_length,
+                unsigned int dev_addr, dmamode_t dmamode);
+
+int
+imx_dma_setup_handlers(int channel,
+                void (*irq_handler) (int, void *),
+                void (*err_handler) (int, void *, int), void *data);
+
+int
+imx_dma_setup_progression_handler(int channel,
+                void (*prog_handler) (int, void*, struct scatterlist*));
+
+void imx_dma_enable(int channel);
+
+void imx_dma_disable(int channel);
+
+int imx_dma_request(int channel, const char *name);
+
+void imx_dma_free(int channel);
+
+enum imx_dma_prio {
+        DMA_PRIO_HIGH = 0,
+        DMA_PRIO_MEDIUM = 1,
+        DMA_PRIO_LOW = 2
+};
+
+int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
+
+#endif  /* _ASM_ARCH_MXC_DMA_H */
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index b542433afb1b..11632028f7d1 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -9,11 +9,17 @@
  * published by the Free Software Foundation.
  */
 
+#define AVIC_NIMASK     0x04
+
         @ this macro disables fast irq (not implemented)
         .macro  disable_fiq
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+#ifdef CONFIG_MXC_IRQ_PRIOR
+        ldr     r4, [\base, #AVIC_NIMASK]
+#endif
         .endm
 
         .macro  arch_ret_to_user, tmp1, tmp2
@@ -23,7 +29,6 @@
         @ and returns its number in irqnr
         @ and returns if an interrupt occured in irqstat
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
         @ Load offset & priority of the highest priority
         @ interrupt pending from AVIC_NIVECSR
         ldr     \irqstat, [\base, #0x40]
@@ -32,6 +37,11 @@
         mov     \irqnr, \irqstat, asr #16
         @ set zero flag if IRQ + 1 == 0
         adds    \tmp, \irqnr, #1
+#ifdef CONFIG_MXC_IRQ_PRIOR
+        bicne   \tmp, \irqstat, #0xFFFFFFE0
+        strne   \tmp, [\base, #AVIC_NIMASK]
+        streq   r4, [\base, #AVIC_NIMASK]
+#endif
         .endm
 
         @ irq priority table (not used)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
index 076d37b38eb2..3d09bfd6c53d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
@@ -247,6 +247,11 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
 #endif
 
 #ifdef CONFIG_ARCH_MX2
+#define PA0_PF_USBH2_CLK        (GPIO_PORTA | GPIO_PF | 0)
+#define PA1_PF_USBH2_DIR        (GPIO_PORTA | GPIO_PF | 1)
+#define PA2_PF_USBH2_DATA7      (GPIO_PORTA | GPIO_PF | 2)
+#define PA3_PF_USBH2_NXT        (GPIO_PORTA | GPIO_PF | 3)
+#define PA4_PF_USBH2_STP        (GPIO_PORTA | GPIO_PF | 4)
 #define PA5_PF_LSCLK            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
 #define PA6_PF_LD0              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
 #define PA7_PF_LD1              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
@@ -294,6 +299,16 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
 #define PB20_AF_UART5_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
 #define PB21_PF_CSI_HSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
 #define PB21_AF_UART5_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 21)
+#define PB22_PF_USBH1_SUSP      (GPIO_PORTB | GPIO_PF | 22)
+#define PB23_PF_USB_PWR         (GPIO_PORTB | GPIO_PF | 23)
+#define PB24_PF_USB_OC_B        (GPIO_PORTB | GPIO_PF | 24)
+#define PB25_PF_USBH1_RCV       (GPIO_PORTB | GPIO_PF | 25)
+#define PB26_PF_USBH1_FS        (GPIO_PORTB | GPIO_PF | 26)
+#define PB27_PF_USBH1_OE_B      (GPIO_PORTB | GPIO_PF | 27)
+#define PB28_PF_USBH1_TXDM      (GPIO_PORTB | GPIO_PF | 28)
+#define PB29_PF_USBH1_TXDP      (GPIO_PORTB | GPIO_PF | 29)
+#define PB30_PF_USBH1_RXDM      (GPIO_PORTB | GPIO_PF | 30)
+#define PB31_PF_USBH1_RXDP      (GPIO_PORTB | GPIO_PF | 31)
 #define PB26_AF_UART4_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_PF | 26)
 #define PB28_AF_UART4_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
 #define PB29_AF_UART4_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
@@ -335,8 +350,15 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
 #define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
 #define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
 #define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD19_AF_USBH2_DATA4     (GPIO_PORTD | GPIO_AF | 19)
+#define PD20_AF_USBH2_DATA3     (GPIO_PORTD | GPIO_AF | 20)
+#define PD21_AF_USBH2_DATA6     (GPIO_PORTD | GPIO_AF | 21)
+#define PD22_AF_USBH2_DATA0     (GPIO_PORTD | GPIO_AF | 22)
+#define PD23_AF_USBH2_DATA2     (GPIO_PORTD | GPIO_AF | 23)
+#define PD24_AF_USBH2_DATA1     (GPIO_PORTD | GPIO_AF | 24)
 #define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 25)
 #define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 26)
+#define PD26_AF_USBH2_DATA5     (GPIO_PORTD | GPIO_AF | 26)
 #define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 27)
 #define PD28_PF_CSPI1_SS0       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 28)
 #define PD29_PF_CSPI1_SCLK      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 29)
@@ -355,6 +377,8 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
 #define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
 #define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
 #define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
+#define PE16_AF_RTCK            (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16)
+#define PE16_PF_RTCK            (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16)
 #define PE18_AF_CSPI3_MISO      (GPIO_PORTE | GPIO_IN  | GPIO_AF | 18)
 #define PE21_AF_CSPI3_SS        (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
 #define PE22_AF_CSPI3_MOSI      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 7509e7692f08..c9f39c2fb8c6 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -491,6 +491,26 @@ enum iomux_pins {
 #define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SS0__SS0         IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SS1__SS1         IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_SS2__SS2         IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SS0__SS0         IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SS1__SS1         IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI2_SS2__SS2         IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI3_MOSI__MOSI       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI3_MISO__MISO       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI3_SCLK__SCLK       IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC)
+/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
+ * cspi1_ss1*/
 
 /*
  * This function configures the pad value for a IOMUX pin.
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 228c4f68ccdf..b55bba35e18a 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -12,5 +12,6 @@
 #define __ASM_ARCH_MXC_IRQS_H__
 
 #include <mach/hardware.h>
+extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
 
 #endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 212ecc246626..a86db64744a1 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -128,6 +128,7 @@
  * it returns 0xDEADBEEF
  */
 #define IO_ADDRESS(x)   \
+        (void __iomem *) \
         (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
                 AIPI_IO_ADDRESS(x) : \
         ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index a7373e4a56cb..0536f8917bc0 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -198,6 +198,7 @@
  * it returns 0xDEADBEEF
  */
 #define IO_ADDRESS(x)   \
+        (void __iomem *) \
         (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
         ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
         ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 332eda4dbd3b..f6caab062131 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -33,4 +33,10 @@
 # define cpu_is_mx27() (0)
 #endif
 
+#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
+#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
+#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
+#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
+#endif
+
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 1053b666c676..d862c9e5f8db 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -18,7 +18,7 @@
  */
 
 #include <linux/irq.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/common.h>
 
 #define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
@@ -30,14 +30,7 @@
 #define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
 #define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
 #define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
-#define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
-#define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
-#define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
-#define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
-#define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
-#define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
-#define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
-#define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
+#define AVIC_NIPRIORITY(x)      (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
 #define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
 #define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
 #define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
@@ -54,6 +47,24 @@
 #define IIM_PROD_REV_SH         3
 #define IIM_PROD_REV_LEN        5
 
+#ifdef CONFIG_MXC_IRQ_PRIOR
+void imx_irq_set_priority(unsigned char irq, unsigned char prio)
+{
+        unsigned int temp;
+        unsigned int mask = 0x0F << irq % 8 * 4;
+
+        if (irq > 63)
+                return;
+
+        temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
+        temp &= ~mask;
+        temp |= prio & mask;
+
+        __raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
+}
+EXPORT_SYMBOL(imx_irq_set_priority);
+#endif
+
 /* Disable interrupt number "irq" in the AVIC */
 static void mxc_mask_irq(unsigned int irq)
 {
@@ -101,10 +112,9 @@ void __init mxc_init_irq(void)
                 set_irq_flags(i, IRQF_VALID);
         }
 
-        /* Set WDOG2's interrupt the highest priority level (bit 28-31) */
-        reg = __raw_readl(AVIC_NIPRIORITY6);
-        reg |= (0xF << 28);
-        __raw_writel(reg, AVIC_NIPRIORITY6);
+        /* Set default priority value (0) for all IRQ's */
+        for (i = 0; i < 8; i++)
+                __raw_writel(0, AVIC_NIPRIORITY(i));
 
         /* init architectures chained interrupt handler */
         mxc_register_gpios();
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 197974defbe4..bf6a10c5fc4f 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -22,8 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/cpufreq.h>
 #include <linux/debugfs.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
 
 #include <mach/clock.h>
 
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index f4dff423ae7c..8bdf0ead0cf3 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -18,12 +18,12 @@
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <asm/io.h>
 #include <asm/setup.h>
 
 #include <mach/common.h>
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index ae1de308aaad..b2690242a390 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -20,9 +20,9 @@
 #include <linux/init.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/system.h>
 
 #define VERY_HI_RATE    900000000
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index 5b73bb274452..e31154b15d9e 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -12,9 +12,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <mach/board.h>
 #include <mach/gpio.h>
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 9422dee7de84..2f4c0cabfd34 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -11,8 +11,8 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/system.h>
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 187e3d8bfdfe..a716ecd1db27 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -13,14 +13,15 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
 #include <mach/tc.h>
 #include <mach/board.h>
+#include <mach/mmc.h>
 #include <mach/mux.h>
 #include <mach/gpio.h>
 #include <mach/menelaus.h>
@@ -194,25 +195,38 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 
 /*-------------------------------------------------------------------------*/
 
-#if     defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+#if     defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
+        defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
-#ifdef CONFIG_ARCH_OMAP24XX
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 #define OMAP_MMC1_BASE          0x4809c000
-#define OMAP_MMC1_INT           INT_24XX_MMC_IRQ
+#define OMAP_MMC1_END           (OMAP_MMC1_BASE + 0x1fc)
+#define OMAP_MMC1_INT           INT_24XX_MMC_IRQ
+
+#define OMAP_MMC2_BASE          0x480b4000
+#define OMAP_MMC2_END           (OMAP_MMC2_BASE + 0x1fc)
+#define OMAP_MMC2_INT           INT_24XX_MMC2_IRQ
+
 #else
+
 #define OMAP_MMC1_BASE          0xfffb7800
+#define OMAP_MMC1_END           (OMAP_MMC1_BASE + 0x7f)
 #define OMAP_MMC1_INT           INT_MMC
-#endif
+
 #define OMAP_MMC2_BASE          0xfffb7c00      /* omap16xx only */
+#define OMAP_MMC2_END           (OMAP_MMC2_BASE + 0x7f)
+#define OMAP_MMC2_INT           INT_1610_MMC2
+
+#endif
 
-static struct omap_mmc_conf mmc1_conf;
+static struct omap_mmc_platform_data mmc1_data;
 
 static u64 mmc1_dmamask = 0xffffffff;
 
 static struct resource mmc1_resources[] = {
         {
                 .start          = OMAP_MMC1_BASE,
-                .end            = OMAP_MMC1_BASE + 0x7f,
+                .end            = OMAP_MMC1_END,
                 .flags          = IORESOURCE_MEM,
         },
         {
@@ -226,26 +240,27 @@ static struct platform_device mmc_omap_device1 = {
         .id             = 1,
         .dev = {
                 .dma_mask       = &mmc1_dmamask,
-                .platform_data  = &mmc1_conf,
+                .platform_data  = &mmc1_data,
         },
         .num_resources  = ARRAY_SIZE(mmc1_resources),
         .resource       = mmc1_resources,
 };
 
-#ifdef  CONFIG_ARCH_OMAP16XX
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \
+        defined(CONFIG_ARCH_OMAP34XX)
 
-static struct omap_mmc_conf mmc2_conf;
+static struct omap_mmc_platform_data mmc2_data;
 
 static u64 mmc2_dmamask = 0xffffffff;
 
 static struct resource mmc2_resources[] = {
         {
                 .start          = OMAP_MMC2_BASE,
-                .end            = OMAP_MMC2_BASE + 0x7f,
+                .end            = OMAP_MMC2_END,
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = INT_1610_MMC2,
+                .start          = OMAP_MMC2_INT,
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -255,26 +270,19 @@ static struct platform_device mmc_omap_device2 = {
         .id             = 2,
         .dev = {
                 .dma_mask       = &mmc2_dmamask,
-                .platform_data  = &mmc2_conf,
+                .platform_data  = &mmc2_data,
         },
         .num_resources  = ARRAY_SIZE(mmc2_resources),
         .resource       = mmc2_resources,
 };
 #endif
 
-static void __init omap_init_mmc(void)
+static inline void omap_init_mmc_conf(const struct omap_mmc_config *mmc_conf)
 {
-        const struct omap_mmc_config    *mmc_conf;
-        const struct omap_mmc_conf      *mmc;
-
-        /* NOTE:  assumes MMC was never (wrongly) enabled */
-        mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
-        if (!mmc_conf)
+        if (cpu_is_omap2430() || cpu_is_omap34xx())
                 return;
 
-        /* block 1 is always available and has just one pinout option */
-        mmc = &mmc_conf->mmc[0];
-        if (mmc->enabled) {
+        if (mmc_conf->mmc[0].enabled) {
                 if (cpu_is_omap24xx()) {
                         omap_cfg_reg(H18_24XX_MMC_CMD);
                         omap_cfg_reg(H15_24XX_MMC_CLKI);
@@ -292,7 +300,7 @@ static void __init omap_init_mmc(void)
                                 omap_cfg_reg(P20_1710_MMC_DATDIR0);
                         }
                 }
-                if (mmc->wire4) {
+                if (mmc_conf->mmc[0].wire4) {
                         if (cpu_is_omap24xx()) {
                                 omap_cfg_reg(H14_24XX_MMC_DAT1);
                                 omap_cfg_reg(E19_24XX_MMC_DAT2);
@@ -303,25 +311,22 @@ static void __init omap_init_mmc(void)
                         } else {
                                 omap_cfg_reg(MMC_DAT1);
                                 /* NOTE:  DAT2 can be on W10 (here) or M15 */
-                                if (!mmc->nomux)
+                                if (!mmc_conf->mmc[0].nomux)
                                         omap_cfg_reg(MMC_DAT2);
                                 omap_cfg_reg(MMC_DAT3);
                         }
                 }
-                mmc1_conf = *mmc;
-                (void) platform_device_register(&mmc_omap_device1);
         }
 
 #ifdef  CONFIG_ARCH_OMAP16XX
         /* block 2 is on newer chips, and has many pinout options */
-        mmc = &mmc_conf->mmc[1];
-        if (mmc->enabled) {
-                if (!mmc->nomux) {
+        if (mmc_conf->mmc[1].enabled) {
+                if (!mmc_conf->mmc[1].nomux) {
                         omap_cfg_reg(Y8_1610_MMC2_CMD);
                         omap_cfg_reg(Y10_1610_MMC2_CLK);
                         omap_cfg_reg(R18_1610_MMC2_CLKIN);
                         omap_cfg_reg(W8_1610_MMC2_DAT0);
-                        if (mmc->wire4) {
+                        if (mmc_conf->mmc[1].wire4) {
                                 omap_cfg_reg(V8_1610_MMC2_DAT1);
                                 omap_cfg_reg(W15_1610_MMC2_DAT2);
                                 omap_cfg_reg(R10_1610_MMC2_DAT3);
@@ -337,14 +342,55 @@ static void __init omap_init_mmc(void)
                 if (cpu_is_omap1710())
                         omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
                                      MOD_CONF_CTRL_1);
-                mmc2_conf = *mmc;
+        }
+#endif
+}
+
+static void __init omap_init_mmc(void)
+{
+        const struct omap_mmc_config    *mmc_conf;
+
+        /* NOTE:  assumes MMC was never (wrongly) enabled */
+        mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
+        if (!mmc_conf)
+                return;
+
+        omap_init_mmc_conf(mmc_conf);
+
+        if (mmc_conf->mmc[0].enabled) {
+                mmc1_data.conf = mmc_conf->mmc[0];
+                (void) platform_device_register(&mmc_omap_device1);
+        }
+
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \
+        defined(CONFIG_ARCH_OMAP34XX)
+        if (mmc_conf->mmc[1].enabled) {
+                mmc2_data.conf = mmc_conf->mmc[1];
                 (void) platform_device_register(&mmc_omap_device2);
         }
 #endif
-        return;
 }
+
+void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info)
+{
+        switch (host) {
+        case 1:
+                mmc1_data = *info;
+                break;
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \
+        defined(CONFIG_ARCH_OMAP34XX)
+        case 2:
+                mmc2_data = *info;
+                break;
+#endif
+        default:
+                BUG();
+        }
+}
+
 #else
 static inline void omap_init_mmc(void) {}
+void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info) {}
 #endif
 
 /*-------------------------------------------------------------------------*/
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 743a4abcd85d..606fcffdcefc 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -32,9 +32,9 @@
 #include <linux/list.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <mach/dmtimer.h>
-#include <asm/io.h>
 #include <mach/irqs.h>
 
 /* register offsets */
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index 17a92a31e746..ce6b4baeedec 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -27,9 +27,9 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/bootmem.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/mach/map.h>
 
 #include <mach/board.h>
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 9e1341ebc14e..5935ae4e550b 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -17,6 +17,7 @@
 #include <linux/sysdev.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -24,8 +25,6 @@
 #include <mach/gpio.h>
 #include <asm/mach/irq.h>
 
-#include <asm/io.h>
-
 /*
  * OMAP1510 GPIO registers
  */
@@ -1051,13 +1050,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
                 gpio_irq = bank->virtual_irq_start;
                 for (; isr != 0; isr >>= 1, gpio_irq++) {
-                        struct irq_desc *d;
-
                         if (!(isr & 1))
                                 continue;
-                        d = irq_desc + gpio_irq;
 
-                        desc_handle_irq(gpio_irq, d);
+                        generic_handle_irq(gpio_irq);
                 }
         }
         /* if bank has any level sensitive GPIO pin interrupt
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 94ce2780e8ee..8c71e288860f 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -26,8 +26,8 @@
 #ifndef __ASM_ARCH_OMAP_GPIO_H
 #define __ASM_ARCH_OMAP_GPIO_H
 
+#include <linux/io.h>
 #include <mach/irqs.h>
-#include <asm/io.h>
 
 #define OMAP_MPUIO_BASE                 (void __iomem *)0xfffb5000
 
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 17248bbf3f27..62aa7dfb9464 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -280,6 +280,8 @@
 #define INT_24XX_USB_IRQ_OTG    80
 #define INT_24XX_MMC_IRQ        83
 
+#define INT_34XX_BENCH_MPU_EMUL 3
+
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
  * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES     192
diff --git a/arch/arm/plat-omap/include/mach/mtd-xip.h b/arch/arm/plat-omap/include/mach/mtd-xip.h
index 5cee7e16a1b4..39b591ff54bb 100644
--- a/arch/arm/plat-omap/include/mach/mtd-xip.h
+++ b/arch/arm/plat-omap/include/mach/mtd-xip.h
@@ -3,7 +3,7 @@
  *
  * Do not include this file directly. It's included from linux/mtd/xip.h
  *
- * Author: Vladimir Barinov <vbarinov@ru.mvista.com>
+ * Author: Vladimir Barinov <vbarinov@embeddedalley.com>
  *
  * (c) 2005 MontaVista Software, Inc.  This file is licensed under the
  * terms of the GNU General Public License version 2.  This program is
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 1d7aec1a691a..b52ce053e6f2 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -30,7 +30,7 @@
 #include <linux/blkdev.h>
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <mach/mailbox.h>
 #include "mailbox.h"
 
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 847df208c46c..80b040fd5ca7 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -25,8 +25,8 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
 #include <asm/system.h>
-#include <asm/io.h>
 #include <linux/spinlock.h>
 #include <mach/mux.h>
 
diff --git a/arch/arm/plat-omap/ocpi.c b/arch/arm/plat-omap/ocpi.c
index 8bdbf979a257..ebe0c73c8901 100644
--- a/arch/arm/plat-omap/ocpi.c
+++ b/arch/arm/plat-omap/ocpi.c
@@ -31,8 +31,8 @@
 #include <linux/spinlock.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <mach/hardware.h>
 
 #define OCPI_BASE               0xfffec320
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index ac67eeb6ca6a..e0003e0746e7 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -15,9 +15,9 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <asm/tlb.h>
-#include <asm/io.h>
 #include <asm/cacheflush.h>
 
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 777485e0636b..67ca1e216df7 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -27,8 +27,8 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/usb/otg.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index 54d4b8e2263c..400541359bfb 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -39,10 +39,10 @@
 #include <linux/clk.h>
 #include <linux/mutex.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 1863a1b1bc49..d528f460f6bc 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -25,6 +25,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,7 +33,6 @@
 
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 89ce60eabd5b..9c607bbc9343 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -29,11 +29,11 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/delay.h>
 #include <asm/cacheflush.h>
 
 #include <asm/mach/arch.h>
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index d6fb76578b11..6b13b5455dfc 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -19,13 +19,13 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <mach/fb.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <asm/plat-s3c/regs-serial.h>
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 08c2aaf14c41..d6344461a83b 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -26,11 +26,11 @@
 #include <linux/slab.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/dma.h>
 
 #include <asm/mach/dma.h>
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index dd27334e3d7e..4a899c279eb5 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -26,10 +26,10 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <mach/regs-gpio.h>
 
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 36cefe176835..590fc5a3ab06 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -55,10 +55,10 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
@@ -468,7 +468,6 @@ static void s3c_irq_demux_adc(unsigned int irq,
 {
         unsigned int subsrc, submsk;
         unsigned int offset = 9;
-        struct irq_desc *mydesc;
 
         /* read the current pending interrupts, and the mask
          * for what it is available */
@@ -482,12 +481,10 @@ static void s3c_irq_demux_adc(unsigned int irq,
 
         if (subsrc != 0) {
                 if (subsrc & 1) {
-                        mydesc = irq_desc + IRQ_TC;
-                        desc_handle_irq(IRQ_TC, mydesc);
+                        generic_handle_irq(IRQ_TC);
                 }
                 if (subsrc & 2) {
-                        mydesc = irq_desc + IRQ_ADC;
-                        desc_handle_irq(IRQ_ADC, mydesc);
+                        generic_handle_irq(IRQ_ADC);
                 }
         }
 }
@@ -496,7 +493,6 @@ static void s3c_irq_demux_uart(unsigned int start)
 {
         unsigned int subsrc, submsk;
         unsigned int offset = start - IRQ_S3CUART_RX0;
-        struct irq_desc *desc;
 
         /* read the current pending interrupts, and the mask
          * for what it is available */
@@ -512,20 +508,14 @@ static void s3c_irq_demux_uart(unsigned int start)
         subsrc &= 7;
 
         if (subsrc != 0) {
-                desc = irq_desc + start;
-
                 if (subsrc & 1)
-                        desc_handle_irq(start, desc);
-
-                desc++;
+                        generic_handle_irq(start);
 
                 if (subsrc & 2)
-                        desc_handle_irq(start+1, desc);
-
-                desc++;
+                        generic_handle_irq(start+1);
 
                 if (subsrc & 4)
-                        desc_handle_irq(start+2, desc);
+                        generic_handle_irq(start+2);
         }
 }
 
@@ -572,7 +562,7 @@ s3c_irq_demux_extint8(unsigned int irq,
                 eintpnd &= ~(1<<irq);
 
                 irq += (IRQ_EINT4 - 4);
-                desc_handle_irq(irq, irq_desc + irq);
+                generic_handle_irq(irq);
         }
 
 }
@@ -595,7 +585,7 @@ s3c_irq_demux_extint4t7(unsigned int irq,
 
                 irq += (IRQ_EINT4 - 4);
 
-                desc_handle_irq(irq, irq_desc + irq);
+                generic_handle_irq(irq);
         }
 }
 
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
index e6705014b2a0..0a074d35890a 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -20,12 +20,12 @@
 #include <linux/init.h>
 #include <linux/sysdev.h>
 #include <linux/device.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index fc4b731a949c..d3934b1119a9 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -35,10 +35,10 @@
 #include <linux/ioport.h>
 #include <linux/delay.h>
 #include <linux/serial_core.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
 #include <mach/hardware.h>
-#include <asm/io.h>
 
 #include <asm/plat-s3c/regs-serial.h>
 #include <mach/regs-clock.h>
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
index 8a5fffde6631..119647a5eaa6 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
@@ -33,11 +33,11 @@
 #include <linux/ioport.h>
 #include <linux/mutex.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/atomic.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <mach/regs-clock.h>
 
diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/plat-s3c24xx/s3c244x-irq.c
index f3dc38cf1de4..0601c5f3230b 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-irq.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-irq.c
@@ -24,10 +24,10 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/io.h>
 
 #include <asm/mach/irq.h>
 
@@ -44,7 +44,6 @@ static void s3c_irq_demux_cam(unsigned int irq,
                               struct irq_desc *desc)
 {
         unsigned int subsrc, submsk;
-        struct irq_desc *mydesc;
 
         /* read the current pending interrupts, and the mask
          * for what it is available */
@@ -58,12 +57,10 @@ static void s3c_irq_demux_cam(unsigned int irq,
 
         if (subsrc != 0) {
                 if (subsrc & 1) {
-                        mydesc = irq_desc + IRQ_S3C2440_CAM_C;
-                        desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc);
+                        generic_handle_irq(IRQ_S3C2440_CAM_C);
                 }
                 if (subsrc & 2) {
-                        mydesc = irq_desc + IRQ_S3C2440_CAM_P;
-                        desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc);
+                        generic_handle_irq(IRQ_S3C2440_CAM_P);
                 }
         }
 }
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index 281b4804ed38..146863a69aeb 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -20,13 +20,13 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 
 #include <mach/regs-clock.h>
diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
index b471a21ae2e4..64bfa19ae951 100644
--- a/arch/arm/plat-s3c24xx/time.c
+++ b/arch/arm/plat-s3c24xx/time.c
@@ -25,12 +25,12 @@
 #include <linux/irq.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <mach/map.h>
 #include <asm/plat-s3c/regs-timer.h>
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 56281c030a7b..43aa2020f85c 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Wed Aug 13 21:56:02 2008
+# Last update: Thu Sep 25 10:10:50 2008
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -1810,7 +1810,7 @@ kriss_sensor		MACH_KRISS_SENSOR	KRISS_SENSOR		1819
 pilz_pmi5               MACH_PILZ_PMI5          PILZ_PMI5               1820
 jade                    MACH_JADE               JADE                    1821
 ks8695_softplc          MACH_KS8695_SOFTPLC     KS8695_SOFTPLC          1822
-gprisc3                 MACH_GPRISC4            GPRISC4                 1823
+gprisc3                 MACH_GPRISC3            GPRISC3                 1823
 stamp9260               MACH_STAMP9260          STAMP9260               1824
 smdk6430                MACH_SMDK6430           SMDK6430                1825
 smdkc100                MACH_SMDKC100           SMDKC100                1826
@@ -1859,5 +1859,43 @@ kbio9260		MACH_KBIO9260		KBIO9260		1868
 ginza                   MACH_GINZA              GINZA                   1869
 a636n                   MACH_A636N              A636N                   1870
 imx27ipcam              MACH_IMX27IPCAM         IMX27IPCAM              1871
-nenoc                   MACH_NEMOC              NEMOC                   1872
+nemoc                   MACH_NEMOC              NEMOC                   1872
 geneva                  MACH_GENEVA             GENEVA                  1873
+htcpharos               MACH_HTCPHAROS          HTCPHAROS               1874
+neonc                   MACH_NEONC              NEONC                   1875
+nas7100                 MACH_NAS7100            NAS7100                 1876
+teuphone                MACH_TEUPHONE           TEUPHONE                1877
+annax_eth2              MACH_ANNAX_ETH2         ANNAX_ETH2              1878
+csb733                  MACH_CSB733             CSB733                  1879
+bk3                     MACH_BK3                BK3                     1880
+omap_em32               MACH_OMAP_EM32          OMAP_EM32               1881
+et9261cp                MACH_ET9261CP           ET9261CP                1882
+jasperc                 MACH_JASPERC            JASPERC                 1883
+issi_arm9               MACH_ISSI_ARM9          ISSI_ARM9               1884
+ued                     MACH_UED                UED                     1885
+esiblade                MACH_ESIBLADE           ESIBLADE                1886
+eye02                   MACH_EYE02              EYE02                   1887
+imx27kbd                MACH_IMX27KBD           IMX27KBD                1888
+sst61vc010_fpga         MACH_SST61VC010_FPGA    SST61VC010_FPGA         1889
+kixvp435                MACH_KIXVP435           KIXVP435                1890
+kixnp435                MACH_KIXNP435           KIXNP435                1891
+africa                  MACH_AFRICA             AFRICA                  1892
+nh233                   MACH_NH233              NH233                   1893
+rd88f6183ap_ge          MACH_RD88F6183AP_GE     RD88F6183AP_GE          1894
+bcm4760                 MACH_BCM4760            BCM4760                 1895
+eddy_v2                 MACH_EDDY_V2            EDDY_V2                 1896
+realview_pba8           MACH_REALVIEW_PBA8      REALVIEW_PBA8           1897
+hid_a7                  MACH_HID_A7             HID_A7                  1898
+hero                    MACH_HERO               HERO                    1899
+omap_poseidon           MACH_OMAP_POSEIDON      OMAP_POSEIDON           1900
+realview_pbx            MACH_REALVIEW_PBX       REALVIEW_PBX            1901
+micro9s                 MACH_MICRO9S            MICRO9S                 1902
+mako                    MACH_MAKO               MAKO                    1903
+xdaflame                MACH_XDAFLAME           XDAFLAME                1904
+phidget_sbc2            MACH_PHIDGET_SBC2       PHIDGET_SBC2            1905
+limestone               MACH_LIMESTONE          LIMESTONE               1906
+iprobe_c32              MACH_IPROBE_C32         IPROBE_C32              1907
+rut100                  MACH_RUT100             RUT100                  1908
+asusp535                MACH_ASUSP535           ASUSP535                1909
+htcraphael              MACH_HTCRAPHAEL         HTCRAPHAEL              1910
+sygdg1                  MACH_SYGDG1             SYGDG1                  1911
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index 806ce26d5243..ba592a9e6fb3 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -21,13 +21,13 @@
 #include <asm/assembler.h>
 #include <asm/vfpmacros.h>
 
-        .globl  do_vfp
-do_vfp:
+ENTRY(do_vfp)
         enable_irq
         ldr     r4, .LCvfp
         ldr     r11, [r10, #TI_CPU]     @ CPU number
         add     r10, r10, #TI_VFPSTATE  @ r10 = workspace
         ldr     pc, [r4]                @ call VFP entry point
+ENDPROC(do_vfp)
 
 ENTRY(vfp_null_entry)
         mov     pc, lr
@@ -40,11 +40,11 @@ ENDPROC(vfp_null_entry)
 @ failure to the VFP initialisation code.
 
         __INIT
-        .globl  vfp_testing_entry
-vfp_testing_entry:
+ENTRY(vfp_testing_entry)
         ldr     r0, VFP_arch_address
         str     r5, [r0]                @ known non-zero value
         mov     pc, r9                  @ we have handled the fault
+ENDPROC(vfp_testing_entry)
 
 VFP_arch_address:
         .word   VFP_arch
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 353f9e5c7919..a62dcf7098ba 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -68,8 +68,7 @@
 @  r11 = CPU number
 @  lr  = failure return
 
-        .globl  vfp_support_entry
-vfp_support_entry:
+ENTRY(vfp_support_entry)
         DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
 
         VFPFMRX r1, FPEXC               @ Is the VFP enabled?
@@ -165,11 +164,10 @@ process_exception:
                                         @ code will raise an exception if
                                         @ required. If not, the user code will
                                         @ retry the faulted instruction
+ENDPROC(vfp_support_entry)
 
 #ifdef CONFIG_SMP
-        .globl  vfp_save_state
-        .type   vfp_save_state, %function
-vfp_save_state:
+ENTRY(vfp_save_state)
         @ Save the current VFP state
         @ r0 - save location
         @ r1 - FPEXC
@@ -182,13 +180,13 @@ vfp_save_state:
         VFPFMRX r12, FPINST2, NE        @ FPINST2 if needed (and present)
         stmia   r0, {r1, r2, r3, r12}   @ save FPEXC, FPSCR, FPINST, FPINST2
         mov     pc, lr
+ENDPROC(vfp_save_state)
 #endif
 
 last_VFP_context_address:
         .word   last_VFP_context
 
-        .globl  vfp_get_float
-vfp_get_float:
+ENTRY(vfp_get_float)
         add     pc, pc, r0, lsl #3
         mov     r0, r0
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
@@ -197,9 +195,9 @@ vfp_get_float:
         mrc     p10, 0, r0, c\dr, c0, 4 @ fmrs  r0, s1
         mov     pc, lr
         .endr
+ENDPROC(vfp_get_float)
 
-        .globl  vfp_put_float
-vfp_put_float:
+ENTRY(vfp_put_float)
         add     pc, pc, r1, lsl #3
         mov     r0, r0
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
@@ -208,9 +206,9 @@ vfp_put_float:
         mcr     p10, 0, r0, c\dr, c0, 4 @ fmsr  r0, s1
         mov     pc, lr
         .endr
+ENDPROC(vfp_put_float)
 
-        .globl  vfp_get_double
-vfp_get_double:
+ENTRY(vfp_get_double)
         add     pc, pc, r0, lsl #3
         mov     r0, r0
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
@@ -229,9 +227,9 @@ vfp_get_double:
         mov     r0, #0
         mov     r1, #0
         mov     pc, lr
+ENDPROC(vfp_get_double)
 
-        .globl  vfp_put_double
-vfp_put_double:
+ENTRY(vfp_put_double)
         add     pc, pc, r2, lsl #3
         mov     r0, r0
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
@@ -245,3 +243,4 @@ vfp_put_double:
         mov     pc, lr
         .endr
 #endif
+ENDPROC(vfp_put_double)
diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
index ee4c292683e1..dfc3443e23aa 100644
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
@@ -325,7 +325,7 @@ static int __init atstk1002_init(void)
 #ifdef CONFIG_BOARD_ATSTK100X_SPI1
         at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
 #endif
-#ifndef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
+#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
         at32_add_device_mci(0, MCI_PDATA);
 #endif
 #ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
diff --git a/arch/avr32/boot/images/.gitignore b/arch/avr32/boot/images/.gitignore
new file mode 100644
index 000000000000..64ea9d0141d2
--- /dev/null
+++ b/arch/avr32/boot/images/.gitignore
@@ -0,0 +1,4 @@
+uImage
+uImage.srec
+vmlinux.cso
+sfdwarf.log
diff --git a/arch/avr32/kernel/.gitignore b/arch/avr32/kernel/.gitignore
new file mode 100644
index 000000000000..c5f676c3c224
--- /dev/null
+++ b/arch/avr32/kernel/.gitignore
@@ -0,0 +1 @@
+vmlinux.lds
diff --git a/arch/avr32/kernel/avr32_ksyms.c b/arch/avr32/kernel/avr32_ksyms.c
index 84a7d44edc67..11e310c567a9 100644
--- a/arch/avr32/kernel/avr32_ksyms.c
+++ b/arch/avr32/kernel/avr32_ksyms.c
@@ -58,6 +58,7 @@ EXPORT_SYMBOL(find_first_zero_bit);
 EXPORT_SYMBOL(find_next_zero_bit);
 EXPORT_SYMBOL(find_first_bit);
 EXPORT_SYMBOL(find_next_bit);
+EXPORT_SYMBOL(generic_find_next_le_bit);
 EXPORT_SYMBOL(generic_find_next_zero_le_bit);
 
 /* I/O primitives (lib/io-*.S) */
diff --git a/arch/avr32/kernel/syscall-stubs.S b/arch/avr32/kernel/syscall-stubs.S
index 890286a1e62b..673178e235f3 100644
--- a/arch/avr32/kernel/syscall-stubs.S
+++ b/arch/avr32/kernel/syscall-stubs.S
@@ -109,3 +109,12 @@ __sys_epoll_pwait:
         rcall   sys_epoll_pwait
         sub     sp, -4
         popm    pc
+
+        .global __sys_sync_file_range
+        .type   __sys_sync_file_range,@function
+__sys_sync_file_range:
+        pushm   lr
+        st.w    --sp, ARG6
+        rcall   sys_sync_file_range
+        sub     sp, -4
+        popm    pc
diff --git a/arch/avr32/kernel/syscall_table.S b/arch/avr32/kernel/syscall_table.S
index 478bda4c4a09..7ee0057613b3 100644
--- a/arch/avr32/kernel/syscall_table.S
+++ b/arch/avr32/kernel/syscall_table.S
@@ -275,7 +275,7 @@ sys_call_table:
         .long   sys_set_robust_list
         .long   sys_get_robust_list     /* 260 */
         .long   __sys_splice
-        .long   sys_sync_file_range
+        .long   __sys_sync_file_range
         .long   sys_tee
         .long   sys_vmsplice
         .long   __sys_epoll_pwait       /* 265 */
diff --git a/arch/avr32/kernel/traps.c b/arch/avr32/kernel/traps.c
index b835c4c01368..0d987373bc01 100644
--- a/arch/avr32/kernel/traps.c
+++ b/arch/avr32/kernel/traps.c
@@ -116,15 +116,15 @@ asmlinkage void do_nmi(unsigned long ecr, struct pt_regs *regs)
         switch (ret) {
         case NOTIFY_OK:
         case NOTIFY_STOP:
-                return;
+                break;
         case NOTIFY_BAD:
                 die("Fatal Non-Maskable Interrupt", regs, SIGINT);
         default:
+                printk(KERN_ALERT "Got NMI, but nobody cared. Disabling...\n");
+                nmi_disable();
                 break;
         }
-
-        printk(KERN_ALERT "Got NMI, but nobody cared. Disabling...\n");
-        nmi_disable();
+        nmi_exit();
 }
 
 asmlinkage void do_critical_exception(unsigned long ecr, struct pt_regs *regs)
diff --git a/arch/avr32/lib/findbit.S b/arch/avr32/lib/findbit.S
index c6b91dee857c..997b33b2288a 100644
--- a/arch/avr32/lib/findbit.S
+++ b/arch/avr32/lib/findbit.S
@@ -123,6 +123,36 @@ ENTRY(find_next_bit)
         brgt    1b
         retal   r11
 
+ENTRY(generic_find_next_le_bit)
+        lsr     r8, r10, 5
+        sub     r9, r11, r10
+        retle   r11
+
+        lsl     r8, 2
+        add     r12, r8
+        andl    r10, 31, COH
+        breq    1f
+
+        /* offset is not word-aligned. Handle the first (32 - r10) bits */
+        ldswp.w r8, r12[0]
+        sub     r12, -4
+        lsr     r8, r8, r10
+        brne    .L_found
+
+        /* r9 = r9 - (32 - r10) = r9 + r10 - 32 */
+        add     r9, r10
+        sub     r9, 32
+        retle   r11
+
+        /* Main loop. offset must be word-aligned */
+1:      ldswp.w r8, r12[0]
+        cp.w    r8, 0
+        brne    .L_found
+        sub     r12, -4
+        sub     r9, 32
+        brgt    1b
+        retal   r11
+
 ENTRY(generic_find_next_zero_le_bit)
         lsr     r8, r10, 5
         sub     r9, r11, r10
diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c
index 952a24b2f5a9..52e16c6436f9 100644
--- a/arch/cris/arch-v32/kernel/smp.c
+++ b/arch/cris/arch-v32/kernel/smp.c
@@ -178,6 +178,7 @@ void __init smp_callin(void)
         unmask_irq(IPI_INTR_VECT);
         unmask_irq(TIMER0_INTR_VECT);
         preempt_disable();
+        notify_cpu_starting(cpu);
         local_irq_enable();
 
         cpu_set(cpu, cpu_online_map);
diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h
index 9f0df9bd46b7..06ff1ba21465 100644
--- a/arch/ia64/include/asm/dma-mapping.h
+++ b/arch/ia64/include/asm/dma-mapping.h
@@ -8,7 +8,9 @@
 #include <asm/machvec.h>
 #include <linux/scatterlist.h>
 
-#define dma_alloc_coherent      platform_dma_alloc_coherent
+#define dma_alloc_coherent(dev, size, handle, gfp)      \
+        platform_dma_alloc_coherent(dev, size, handle, (gfp) | GFP_DMA)
+
 /* coherent mem. is cheap */
 static inline void *
 dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
diff --git a/arch/ia64/include/asm/elf.h b/arch/ia64/include/asm/elf.h
index 5e0c1a6bce8d..2acb6b6543c9 100644
--- a/arch/ia64/include/asm/elf.h
+++ b/arch/ia64/include/asm/elf.h
@@ -266,4 +266,19 @@ do {									\
         }                                                               \
 } while (0)
 
+/*
+ * format for entries in the Global Offset Table
+ */
+struct got_entry {
+        uint64_t val;
+};
+
+/*
+ * Layout of the Function Descriptor
+ */
+struct fdesc {
+        uint64_t ip;
+        uint64_t gp;
+};
+
 #endif /* _ASM_IA64_ELF_H */
diff --git a/arch/ia64/include/asm/sections.h b/arch/ia64/include/asm/sections.h
index a7acad2bc2f0..1a873b36a4a1 100644
--- a/arch/ia64/include/asm/sections.h
+++ b/arch/ia64/include/asm/sections.h
@@ -6,9 +6,14 @@
  *      David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
+#include <linux/elf.h>
+#include <linux/uaccess.h>
 #include <asm-generic/sections.h>
 
 extern char __per_cpu_start[], __per_cpu_end[], __phys_per_cpu_start[];
+#ifdef  CONFIG_SMP
+extern char __cpu0_per_cpu[];
+#endif
 extern char __start___vtop_patchlist[], __end___vtop_patchlist[];
 extern char __start___rse_patchlist[], __end___rse_patchlist[];
 extern char __start___mckinley_e9_bundles[], __end___mckinley_e9_bundles[];
@@ -22,7 +27,16 @@ extern char __start_unwind[], __end_unwind[];
 extern char __start_ivt_text[], __end_ivt_text[];
 
 #undef dereference_function_descriptor
-void *dereference_function_descriptor(void *);
+static inline void *dereference_function_descriptor(void *ptr)
+{
+        struct fdesc *desc = ptr;
+        void *p;
+
+        if (!probe_kernel_address(&desc->ip, p))
+                ptr = p;
+        return ptr;
+}
+
 
 #endif /* _ASM_IA64_SECTIONS_H */
 
diff --git a/arch/ia64/include/asm/sn/bte.h b/arch/ia64/include/asm/sn/bte.h
index a0d214f43115..5efecf06c9a4 100644
--- a/arch/ia64/include/asm/sn/bte.h
+++ b/arch/ia64/include/asm/sn/bte.h
@@ -223,10 +223,11 @@ extern void bte_error_handler(unsigned long);
  * until the transfer is complete.  In order to get the asynch
  * version of bte_copy, you must perform this check yourself.
  */
-#define BTE_UNALIGNED_COPY(src, dest, len, mode)                        \
-        (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) ||             \
-          (dest & L1_CACHE_MASK)) ?                                     \
-         bte_unaligned_copy(src, dest, len, mode) :                     \
+#define BTE_UNALIGNED_COPY(src, dest, len, mode)                        \
+        (((len & (L1_CACHE_BYTES - 1)) ||                               \
+          (src & (L1_CACHE_BYTES - 1)) ||                               \
+          (dest & (L1_CACHE_BYTES - 1))) ?                              \
+         bte_unaligned_copy(src, dest, len, mode) :                     \
          bte_copy(src, dest, len, mode, NULL))
 
 
diff --git a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c
index d45f215bc8fc..51b75cea7018 100644
--- a/arch/ia64/kernel/efi.c
+++ b/arch/ia64/kernel/efi.c
@@ -1232,9 +1232,10 @@ efi_initialize_iomem_resources(struct resource *code_resource,
                                 if (md->attribute & EFI_MEMORY_WP) {
                                         name = "System ROM";
                                         flags |= IORESOURCE_READONLY;
-                                } else {
+                                } else if (md->attribute == EFI_MEMORY_UC)
+                                        name = "Uncached RAM";
+                                else
                                         name = "System RAM";
-                                }
                                 break;
 
                         case EFI_ACPI_MEMORY_NVS:
diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S
index 8bdea8eb62e3..66e491d8baac 100644
--- a/arch/ia64/kernel/head.S
+++ b/arch/ia64/kernel/head.S
@@ -367,16 +367,17 @@ start_ap:
         ;;
 #else
 (isAP)  br.few 2f
-        mov r20=r19
-        sub r19=r19,r18
+        movl r20=__cpu0_per_cpu
         ;;
         shr.u r18=r18,3
 1:
-        ld8 r21=[r20],8;;
-        st8[r19]=r21,8
+        ld8 r21=[r19],8;;
+        st8[r20]=r21,8
         adds r18=-1,r18;;
         cmp4.lt p7,p6=0,r18
 (p7)    br.cond.dptk.few 1b
+        mov r19=r20
+        ;;
 2:
 #endif
         tpa r19=r19
diff --git a/arch/ia64/kernel/module.c b/arch/ia64/kernel/module.c
index 545626f66a4c..aaa7d901521f 100644
--- a/arch/ia64/kernel/module.c
+++ b/arch/ia64/kernel/module.c
@@ -31,11 +31,9 @@
 #include <linux/elf.h>
 #include <linux/moduleloader.h>
 #include <linux/string.h>
-#include <linux/uaccess.h>
 #include <linux/vmalloc.h>
 
 #include <asm/patch.h>
-#include <asm/sections.h>
 #include <asm/unaligned.h>
 
 #define ARCH_MODULE_DEBUG 0
@@ -137,15 +135,6 @@ static const char *reloc_name[256] = {
 
 #undef N
 
-struct got_entry {
-        uint64_t val;
-};
-
-struct fdesc {
-        uint64_t ip;
-        uint64_t gp;
-};
-
 /* Opaque struct for insns, to protect against derefs. */
 struct insn;
 
@@ -943,13 +932,3 @@ module_arch_cleanup (struct module *mod)
         if (mod->arch.core_unw_table)
                 unw_remove_unwind_table(mod->arch.core_unw_table);
 }
-
-void *dereference_function_descriptor(void *ptr)
-{
-        struct fdesc *desc = ptr;
-        void *p;
-
-        if (!probe_kernel_address(&desc->ip, p))
-                ptr = p;
-        return ptr;
-}
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index c27d5b2c182b..de636b215677 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -616,7 +616,9 @@ setup_arch (char **cmdline_p)
                 ia64_mca_init();
 
         platform_setup(cmdline_p);
+#ifndef CONFIG_IA64_HP_SIM
         check_sal_cache_flush();
+#endif
         paging_init();
 }
 
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index bcea81e432fd..1dcbb85fc4ee 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -401,6 +401,7 @@ smp_callin (void)
         spin_lock(&vector_lock);
         /* Setup the per cpu irq handling data structures */
         __setup_vector_irq(cpuid);
+        notify_cpu_starting(cpuid);
         cpu_set(cpuid, cpu_online_map);
         per_cpu(cpu_state, cpuid) = CPU_ONLINE;
         spin_unlock(&vector_lock);
@@ -741,16 +742,14 @@ int __cpu_disable(void)
                         return -EBUSY;
         }
 
-        cpu_clear(cpu, cpu_online_map);
-
         if (migrate_platform_irqs(cpu)) {
                 cpu_set(cpu, cpu_online_map);
                 return (-EBUSY);
         }
 
         remove_siblinginfo(cpu);
-        cpu_clear(cpu, cpu_online_map);
         fixup_irqs();
+        cpu_clear(cpu, cpu_online_map);
         local_flush_tlb_all();
         cpu_clear(cpu, cpu_callin_map);
         return 0;
diff --git a/arch/ia64/kernel/vmlinux.lds.S b/arch/ia64/kernel/vmlinux.lds.S
index de71da811cd6..10a7d47e8510 100644
--- a/arch/ia64/kernel/vmlinux.lds.S
+++ b/arch/ia64/kernel/vmlinux.lds.S
@@ -215,9 +215,6 @@ SECTIONS
   /* Per-cpu data: */
   percpu : { } :percpu
   . = ALIGN(PERCPU_PAGE_SIZE);
-#ifdef  CONFIG_SMP
-  . = . + PERCPU_PAGE_SIZE;     /* cpu0 per-cpu space */
-#endif
   __phys_per_cpu_start = .;
   .data.percpu PERCPU_ADDR : AT(__phys_per_cpu_start - LOAD_OFFSET)
         {
@@ -233,6 +230,11 @@ SECTIONS
   data : { } :data
   .data : AT(ADDR(.data) - LOAD_OFFSET)
         {
+#ifdef  CONFIG_SMP
+  . = ALIGN(PERCPU_PAGE_SIZE);
+                __cpu0_per_cpu = .;
+  . = . + PERCPU_PAGE_SIZE;     /* cpu0 per-cpu space */
+#endif
                 DATA_DATA
                 *(.data1)
                 *(.gnu.linkonce.d*)
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 7a37d06376be..cd0d1a7284b7 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -38,6 +38,7 @@
 #include <asm/cacheflush.h>
 #include <asm/div64.h>
 #include <asm/tlb.h>
+#include <asm/elf.h>
 
 #include "misc.h"
 #include "vti.h"
@@ -61,12 +62,6 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
         { NULL }
 };
 
-
-struct fdesc{
-    unsigned long ip;
-    unsigned long gp;
-};
-
 static void kvm_flush_icache(unsigned long start, unsigned long len)
 {
         int l;
diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c
index e566ff43884a..0ee085efbe29 100644
--- a/arch/ia64/mm/contig.c
+++ b/arch/ia64/mm/contig.c
@@ -163,7 +163,7 @@ per_cpu_init (void)
          * get_zeroed_page().
          */
         if (first_time) {
-                void *cpu0_data = __phys_per_cpu_start - PERCPU_PAGE_SIZE;
+                void *cpu0_data = __cpu0_per_cpu;
 
                 first_time=0;
 
diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
index 78026aabaa7f..d8c5fcd89e5b 100644
--- a/arch/ia64/mm/discontig.c
+++ b/arch/ia64/mm/discontig.c
@@ -144,7 +144,7 @@ static void *per_cpu_node_setup(void *cpu_data, int node)
 
         for_each_possible_early_cpu(cpu) {
                 if (cpu == 0) {
-                        void *cpu0_data = __phys_per_cpu_start - PERCPU_PAGE_SIZE;
+                        void *cpu0_data = __cpu0_per_cpu;
                         __per_cpu_offset[cpu] = (char*)cpu0_data -
                                 __per_cpu_start;
                 } else if (node == node_cpuid[cpu].nid) {
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index 529462c01570..79165122501c 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -420,8 +420,10 @@ tioca_dma_mapped(struct pci_dev *pdev, u64 paddr, size_t req_size)
                 entry = find_next_zero_bit(map, mapsize, last_entry);
         }
 
-        if (entry > mapsize)
+        if (entry > mapsize) {
+                kfree(ca_dmamap);
                 goto map_return;
+        }
 
         for (i = 0; i < entries; i++)
                 set_bit(entry + i, map);
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index a5f864c445b2..f57113f1f892 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -216,10 +216,6 @@ config MEMORY_SIZE
         default "01000000" if PLAT_M32104UT
         default "00800000" if PLAT_OAKS32R
 
-config NOHIGHMEM
-        bool
-        default y
-
 config ARCH_DISCONTIGMEM_ENABLE
         bool "Internal RAM Support"
         depends on CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104
@@ -410,11 +406,7 @@ config PCI_DIRECT
 source "drivers/pci/Kconfig"
 
 config ISA
-        bool "ISA support"
-        help
-          Find out whether you have ISA slots on your motherboard.  ISA is the
-          name of a bus system, i.e. the way the CPU talks to the other stuff
-          inside your box.  If you have ISA, say Y, otherwise N.
+        bool
 
 source "drivers/pcmcia/Kconfig"
 
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S
index d4eaa2fd1818..612d35b082a6 100644
--- a/arch/m32r/kernel/entry.S
+++ b/arch/m32r/kernel/entry.S
@@ -143,7 +143,7 @@ ret_from_intr:
         and3    r4, r4, #0x8000         ; check BSM bit
 #endif
         beqz    r4, resume_kernel
-ENTRY(resume_userspace)
+resume_userspace:
         DISABLE_INTERRUPTS(r4)          ; make sure we don't miss an interrupt
                                         ; setting need_resched or sigpending
                                         ; between sampling and the iret
diff --git a/arch/m32r/kernel/head.S b/arch/m32r/kernel/head.S
index dab7436d7bbe..40180778a5c7 100644
--- a/arch/m32r/kernel/head.S
+++ b/arch/m32r/kernel/head.S
@@ -29,7 +29,6 @@ __INITDATA
         .global _end
 ENTRY(stext)
 ENTRY(_stext)
-ENTRY(startup_32)
         /* Setup up the stack pointer */
         LDIMM   (r0, spi_stack_top)
         LDIMM   (r1, spu_stack_top)
diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c
index d0c5b0b7da2f..2aeae4670098 100644
--- a/arch/m32r/kernel/irq.c
+++ b/arch/m32r/kernel/irq.c
@@ -22,9 +22,6 @@
 #include <linux/module.h>
 #include <asm/uaccess.h>
 
-atomic_t irq_err_count;
-atomic_t irq_mis_count;
-
 /*
  * Generic, controller-independent functions:
  */
@@ -63,9 +60,6 @@ int show_interrupts(struct seq_file *p, void *v)
                 seq_putc(p, '\n');
 skip:
                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        } else if (i == NR_IRQS) {
-                seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
-                seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
         }
         return 0;
 }
diff --git a/arch/m32r/kernel/m32r_ksyms.c b/arch/m32r/kernel/m32r_ksyms.c
index 16bcb189a383..22624b51d4d3 100644
--- a/arch/m32r/kernel/m32r_ksyms.c
+++ b/arch/m32r/kernel/m32r_ksyms.c
@@ -14,6 +14,7 @@
 #include <asm/delay.h>
 #include <asm/irq.h>
 #include <asm/tlbflush.h>
+#include <asm/pgtable.h>
 
 /* platform dependent support */
 EXPORT_SYMBOL(boot_cpu_data);
@@ -65,6 +66,7 @@ EXPORT_SYMBOL(memset);
 EXPORT_SYMBOL(copy_page);
 EXPORT_SYMBOL(clear_page);
 EXPORT_SYMBOL(strlen);
+EXPORT_SYMBOL(empty_zero_page);
 
 EXPORT_SYMBOL(_inb);
 EXPORT_SYMBOL(_inw);
diff --git a/arch/m32r/kernel/process.c b/arch/m32r/kernel/process.c
index a689e2978b6e..5be4faaf5b1c 100644
--- a/arch/m32r/kernel/process.c
+++ b/arch/m32r/kernel/process.c
@@ -35,8 +35,6 @@
 
 #include <linux/err.h>
 
-static int hlt_counter=0;
-
 /*
  * Return saved PC of a blocked thread.
  */
@@ -48,31 +46,16 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
 /*
  * Powermanagement idle function, if any..
  */
-void (*pm_idle)(void) = NULL;
-EXPORT_SYMBOL(pm_idle);
+static void (*pm_idle)(void) = NULL;
 
 void (*pm_power_off)(void) = NULL;
 EXPORT_SYMBOL(pm_power_off);
 
-void disable_hlt(void)
-{
-        hlt_counter++;
-}
-
-EXPORT_SYMBOL(disable_hlt);
-
-void enable_hlt(void)
-{
-        hlt_counter--;
-}
-
-EXPORT_SYMBOL(enable_hlt);
-
 /*
  * We use this is we don't have any better
  * idle routine..
  */
-void default_idle(void)
+static void default_idle(void)
 {
         /* M32R_FIXME: Please use "cpu_sleep" mode.  */
         cpu_relax();
@@ -260,15 +243,6 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long spu,
         return 0;
 }
 
-/*
- * Capture the user space registers if the task is not running (in user space)
- */
-int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
-{
-        /* M32R_FIXME */
-        return 1;
-}
-
 asmlinkage int sys_fork(unsigned long r0, unsigned long r1, unsigned long r2,
         unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6,
         struct pt_regs regs)
diff --git a/arch/m32r/kernel/smp.c b/arch/m32r/kernel/smp.c
index 7577f971ea4e..929e5c9d3ad9 100644
--- a/arch/m32r/kernel/smp.c
+++ b/arch/m32r/kernel/smp.c
@@ -84,7 +84,7 @@ void smp_send_timer(void);
 void smp_ipi_timer_interrupt(struct pt_regs *);
 void smp_local_timer_interrupt(void);
 
-void send_IPI_allbutself(int, int);
+static void send_IPI_allbutself(int, int);
 static void send_IPI_mask(cpumask_t, int, int);
 unsigned long send_IPI_mask_phys(cpumask_t, int, int);
 
@@ -722,7 +722,7 @@ void smp_local_timer_interrupt(void)
  * ---------- --- --------------------------------------------------------
  *
  *==========================================================================*/
-void send_IPI_allbutself(int ipi_num, int try)
+static void send_IPI_allbutself(int ipi_num, int try)
 {
         cpumask_t cpumask;
 
diff --git a/arch/m32r/kernel/smpboot.c b/arch/m32r/kernel/smpboot.c
index 2c03ac1d005f..fc2994811f15 100644
--- a/arch/m32r/kernel/smpboot.c
+++ b/arch/m32r/kernel/smpboot.c
@@ -498,6 +498,8 @@ static void __init smp_online(void)
 {
         int cpu_id = smp_processor_id();
 
+        notify_cpu_starting(cpu_id);
+
         local_irq_enable();
 
         /* Get our bogomips. */
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
index 994cc1556355..6ea017727cce 100644
--- a/arch/m32r/kernel/time.c
+++ b/arch/m32r/kernel/time.c
@@ -34,7 +34,6 @@
 #include <asm/hw_irq.h>
 
 #ifdef CONFIG_SMP
-extern void send_IPI_allbutself(int, int);
 extern void smp_local_timer_interrupt(void);
 #endif
 
@@ -188,7 +187,7 @@ static long last_rtc_update = 0;
  * timer_interrupt() needs to keep up the real-time clock,
  * as well as call the "do_timer()" routine every clocktick
  */
-irqreturn_t timer_interrupt(int irq, void *dev_id)
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
 {
 #ifndef CONFIG_SMP
         profile_tick(CPU_PROFILING);
@@ -228,7 +227,7 @@ irqreturn_t timer_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-struct irqaction irq0 = {
+static struct irqaction irq0 = {
         .handler = timer_interrupt,
         .flags = IRQF_DISABLED,
         .mask = CPU_MASK_NONE,
diff --git a/arch/m32r/kernel/traps.c b/arch/m32r/kernel/traps.c
index 46159a4e644b..03b14e55cd89 100644
--- a/arch/m32r/kernel/traps.c
+++ b/arch/m32r/kernel/traps.c
@@ -61,7 +61,7 @@ extern unsigned long	eit_vector[];
         ((unsigned long)func - (unsigned long)eit_vector - entry*4)/4 \
         + 0xff000000UL
 
-void    set_eit_vector_entries(void)
+static void set_eit_vector_entries(void)
 {
         extern void default_eit_handler(void);
         extern void system_call(void);
@@ -121,9 +121,9 @@ void __init trap_init(void)
         cpu_init();
 }
 
-int kstack_depth_to_print = 24;
+static int kstack_depth_to_print = 24;
 
-void show_trace(struct task_struct *task, unsigned long *stack)
+static void show_trace(struct task_struct *task, unsigned long *stack)
 {
         unsigned long addr;
 
@@ -224,7 +224,7 @@ bad:
         printk("\n");
 }
 
-DEFINE_SPINLOCK(die_lock);
+static DEFINE_SPINLOCK(die_lock);
 
 void die(const char * str, struct pt_regs * regs, long err)
 {
diff --git a/arch/m32r/lib/delay.c b/arch/m32r/lib/delay.c
index 59bfc34e0d9f..ced549be80f5 100644
--- a/arch/m32r/lib/delay.c
+++ b/arch/m32r/lib/delay.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/param.h>
+#include <linux/module.h>
 #ifdef CONFIG_SMP
 #include <linux/sched.h>
 #include <asm/current.h>
@@ -121,3 +122,4 @@ void __ndelay(unsigned long nsecs)
 {
         __const_udelay(nsecs * 0x00005);  /* 2**32 / 1000000000 (rounded up) */
 }
+EXPORT_SYMBOL(__ndelay);
diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig
index 8e2a0f5faf53..8bd61a640fc9 100644
--- a/arch/m68k/configs/amiga_defconfig
+++ b/arch/m68k/configs/amiga_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:00 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -166,10 +172,6 @@ CONFIG_GENERIC_ISA_DMA=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_ZORRO_NAMES=y
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -183,6 +185,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -413,6 +416,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -432,7 +436,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -460,6 +466,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -470,6 +477,7 @@ CONFIG_BLK_DEV_IDE=y
 #
 # Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
@@ -489,8 +497,6 @@ CONFIG_BLK_DEV_GAYLE=y
 CONFIG_BLK_DEV_IDEDOUBLER=y
 CONFIG_BLK_DEV_BUDDHA=y
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD_ONLY is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
@@ -556,6 +562,7 @@ CONFIG_A2091_SCSI=y
 CONFIG_GVP11_SCSI=y
 CONFIG_SCSI_A4000T=y
 CONFIG_SCSI_ZORRO7XX=y
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -564,7 +571,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -573,13 +580,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -722,6 +725,7 @@ CONFIG_INPUT_M68K_BEEP=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -757,6 +761,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -768,8 +773,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -844,10 +851,6 @@ CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=m
 CONFIG_DMASOUND_PAULA=m
 CONFIG_DMASOUND=m
@@ -861,6 +864,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 
@@ -899,6 +903,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -958,6 +963,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -980,7 +986,6 @@ CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
 CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=m
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -989,7 +994,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -1054,6 +1058,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -1113,6 +1119,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1154,6 +1164,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig
index e2d511e2a1d1..c41b854c0284 100644
--- a/arch/m68k/configs/apollo_defconfig
+++ b/arch/m68k/configs/apollo_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:01 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -161,10 +167,6 @@ CONFIG_HEARTBEAT=y
 CONFIG_PROC_HARDWARE=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -178,6 +180,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -411,6 +414,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -430,7 +434,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -448,6 +454,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -499,6 +506,7 @@ CONFIG_SCSI_SRP_TGT_ATTRS=y
 CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ISCSI_TCP=m
 # CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -507,7 +515,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -516,13 +524,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -532,7 +536,6 @@ CONFIG_VETH=m
 # CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
 # CONFIG_MII is not set
-CONFIG_APOLLO_ELPLUS=y
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -627,6 +630,7 @@ CONFIG_SERIO_LIBPS2=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -657,6 +661,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -668,8 +673,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -738,10 +745,6 @@ CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 # CONFIG_LOGO_LINUX_VGA16 is not set
 # CONFIG_LOGO_LINUX_CLUT224 is not set
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
@@ -753,6 +756,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -789,6 +793,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -848,6 +853,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -860,18 +866,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -880,7 +885,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -944,6 +948,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -1003,6 +1009,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1044,6 +1054,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig
index 6e20d656adaf..654c5acb9e86 100644
--- a/arch/m68k/configs/atari_defconfig
+++ b/arch/m68k/configs/atari_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:02 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -162,10 +168,6 @@ CONFIG_HEARTBEAT=y
 CONFIG_PROC_HARDWARE=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -179,6 +181,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -409,6 +412,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -428,7 +432,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -452,6 +458,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -462,6 +469,7 @@ CONFIG_BLK_DEV_IDE=y
 #
 # Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
@@ -479,8 +487,6 @@ CONFIG_IDE_PROC_FS=y
 # CONFIG_BLK_DEV_PLATFORM is not set
 CONFIG_BLK_DEV_FALCON_IDE=y
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD_ONLY is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
@@ -530,6 +536,7 @@ CONFIG_ISCSI_TCP=m
 CONFIG_ATARI_SCSI=y
 # CONFIG_ATARI_SCSI_TOSHIBA_DELAY is not set
 # CONFIG_ATARI_SCSI_RESET_BOOT is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -538,7 +545,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -547,13 +554,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -666,6 +669,7 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -700,6 +704,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -711,8 +716,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -782,10 +789,6 @@ CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=m
 CONFIG_DMASOUND_ATARI=m
 CONFIG_DMASOUND=m
@@ -799,6 +802,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 
@@ -806,11 +810,8 @@ CONFIG_HIDRAW=y
 # Character devices
 #
 CONFIG_ATARI_MFPSER=m
-CONFIG_ATARI_SCC=y
-CONFIG_ATARI_SCC_DMA=y
 CONFIG_ATARI_MIDI=m
 CONFIG_ATARI_DSP56K=m
-# CONFIG_SERIAL_CONSOLE is not set
 
 #
 # File systems
@@ -820,8 +821,10 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
+CONFIG_EXT4DEV_FS=y
+# CONFIG_EXT4DEV_FS_XATTR is not set
 CONFIG_JBD=y
+CONFIG_JBD2=y
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -840,6 +843,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -899,6 +903,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -920,7 +925,6 @@ CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-CONFIG_SUNRPC_BIND34=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -929,7 +933,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -994,6 +997,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -1053,6 +1058,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1094,6 +1103,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig
index a0a9b30bb502..2e44af0fe54a 100644
--- a/arch/m68k/configs/bvme6000_defconfig
+++ b/arch/m68k/configs/bvme6000_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:03 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -163,10 +169,6 @@ CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -180,6 +182,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -413,6 +416,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -432,7 +436,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -450,6 +456,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -503,6 +510,7 @@ CONFIG_ISCSI_TCP=m
 CONFIG_53C700_BE_BUS=y
 # CONFIG_SCSI_DEBUG is not set
 CONFIG_BVME6000_SCSI=y
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -511,7 +519,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -520,13 +528,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -631,6 +635,7 @@ CONFIG_SERIO_LIBPS2=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -661,6 +666,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -672,8 +678,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -708,10 +716,6 @@ CONFIG_SSB_POSSIBLE=y
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
@@ -723,6 +727,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -759,6 +764,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -818,6 +824,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -830,18 +837,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -850,7 +856,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -915,6 +920,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -974,6 +981,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1015,6 +1026,7 @@ CONFIG_BITREVERSE=m
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=m
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig
index 6778041de262..3570fc89b089 100644
--- a/arch/m68k/configs/hp300_defconfig
+++ b/arch/m68k/configs/hp300_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:04 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -162,10 +168,6 @@ CONFIG_HEARTBEAT=y
 CONFIG_PROC_HARDWARE=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -179,6 +181,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -412,6 +415,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -431,7 +435,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -449,6 +455,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -500,6 +507,7 @@ CONFIG_SCSI_SRP_TGT_ATTRS=y
 CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ISCSI_TCP=m
 # CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -508,7 +516,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -517,13 +525,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -636,6 +640,7 @@ CONFIG_SERIO_LIBPS2=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -666,6 +671,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -677,8 +683,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -747,10 +755,6 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
@@ -762,6 +766,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -796,6 +801,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -855,6 +861,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -867,18 +874,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -887,7 +893,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -951,6 +956,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -1010,6 +1017,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1051,6 +1062,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig
index 7cd375740348..db6e8822594a 100644
--- a/arch/m68k/configs/mac_defconfig
+++ b/arch/m68k/configs/mac_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:06 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -163,10 +169,6 @@ CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -180,6 +182,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -413,6 +416,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -432,7 +436,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -450,6 +456,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -460,6 +467,7 @@ CONFIG_BLK_DEV_IDE=y
 #
 # Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
@@ -477,8 +485,6 @@ CONFIG_IDE_PROC_FS=y
 # CONFIG_BLK_DEV_PLATFORM is not set
 CONFIG_BLK_DEV_MAC_IDE=y
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD_ONLY is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
@@ -527,6 +533,7 @@ CONFIG_ISCSI_TCP=m
 # CONFIG_SCSI_DEBUG is not set
 CONFIG_MAC_SCSI=y
 CONFIG_SCSI_MAC_ESP=y
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -535,7 +542,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -544,9 +551,6 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_MACINTOSH_DRIVERS=y
@@ -559,7 +563,6 @@ CONFIG_ADB_CUDA=y
 CONFIG_INPUT_ADBHID=y
 CONFIG_MAC_EMUMOUSEBTN=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -670,6 +673,7 @@ CONFIG_SERIO_LIBPS2=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -700,6 +704,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -711,8 +716,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -784,10 +791,6 @@ CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_LOGO_MAC_CLUT224=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
@@ -799,6 +802,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -836,6 +840,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -895,6 +900,7 @@ CONFIG_HFSPLUS_FS=y
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -917,7 +923,6 @@ CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
 CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=m
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -926,7 +931,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -991,6 +995,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -1050,6 +1056,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=m
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1091,6 +1101,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig
index 0747fa3984df..1a806102b999 100644
--- a/arch/m68k/configs/multi_defconfig
+++ b/arch/m68k/configs/multi_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:07 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -173,10 +179,6 @@ CONFIG_GENERIC_ISA_DMA=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_ZORRO_NAMES=y
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -190,6 +192,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -427,6 +430,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -446,7 +450,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -476,6 +482,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -486,6 +493,7 @@ CONFIG_BLK_DEV_IDE=y
 #
 # Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
@@ -508,8 +516,6 @@ CONFIG_BLK_DEV_FALCON_IDE=y
 CONFIG_BLK_DEV_MAC_IDE=y
 CONFIG_BLK_DEV_Q40IDE=y
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD_ONLY is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
@@ -584,6 +590,7 @@ CONFIG_MVME147_SCSI=y
 CONFIG_MVME16x_SCSI=y
 CONFIG_BVME6000_SCSI=y
 CONFIG_SUN3X_ESP=y
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -592,7 +599,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -601,9 +608,6 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_MACINTOSH_DRIVERS=y
@@ -616,7 +620,6 @@ CONFIG_ADB_CUDA=y
 CONFIG_INPUT_ADBHID=y
 CONFIG_MAC_EMUMOUSEBTN=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -632,7 +635,6 @@ CONFIG_A2065=m
 CONFIG_HYDRA=m
 CONFIG_ZORRO8390=m
 CONFIG_APNE=m
-CONFIG_APOLLO_ELPLUS=y
 CONFIG_MAC8390=y
 CONFIG_MAC89x0=m
 CONFIG_MACSONIC=m
@@ -791,6 +793,7 @@ CONFIG_SERIO_LIBPS2=y
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -827,6 +830,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -838,8 +842,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -923,10 +929,6 @@ CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_LOGO_MAC_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=m
 CONFIG_DMASOUND_ATARI=m
 CONFIG_DMASOUND_PAULA=m
@@ -942,6 +944,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
 
@@ -949,8 +952,6 @@ CONFIG_HIDRAW=y
 # Character devices
 #
 CONFIG_ATARI_MFPSER=m
-CONFIG_ATARI_SCC=y
-CONFIG_ATARI_SCC_DMA=y
 CONFIG_ATARI_MIDI=m
 CONFIG_ATARI_DSP56K=m
 CONFIG_AMIGA_BUILTIN_SERIAL=y
@@ -972,8 +973,10 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
+CONFIG_EXT4DEV_FS=y
+# CONFIG_EXT4DEV_FS_XATTR is not set
 CONFIG_JBD=y
+CONFIG_JBD2=y
 CONFIG_REISERFS_FS=m
 # CONFIG_REISERFS_CHECK is not set
 # CONFIG_REISERFS_PROC_INFO is not set
@@ -992,6 +995,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -1051,6 +1055,7 @@ CONFIG_HFSPLUS_FS=y
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -1063,18 +1068,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1083,7 +1087,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -1152,6 +1155,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -1211,6 +1216,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1252,6 +1261,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig
index e7a8246840b5..cacb5aef6a37 100644
--- a/arch/m68k/configs/mvme147_defconfig
+++ b/arch/m68k/configs/mvme147_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:08 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -163,10 +169,6 @@ CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -180,6 +182,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -413,6 +416,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -432,7 +436,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -450,6 +456,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -502,6 +509,7 @@ CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ISCSI_TCP=m
 # CONFIG_SCSI_DEBUG is not set
 CONFIG_MVME147_SCSI=y
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -510,7 +518,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -519,13 +527,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -630,6 +634,7 @@ CONFIG_SERIO_LIBPS2=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -660,6 +665,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -671,8 +677,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -707,10 +715,6 @@ CONFIG_SSB_POSSIBLE=y
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
@@ -722,6 +726,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -758,6 +763,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -817,6 +823,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -829,18 +836,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -849,7 +855,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -914,6 +919,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -973,6 +980,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1014,6 +1025,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig
index ab536eb172bb..a183e25e348d 100644
--- a/arch/m68k/configs/mvme16x_defconfig
+++ b/arch/m68k/configs/mvme16x_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:09 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -163,10 +169,6 @@ CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -180,6 +182,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -413,6 +416,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -432,7 +436,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -450,6 +456,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -503,6 +510,7 @@ CONFIG_ISCSI_TCP=m
 CONFIG_53C700_BE_BUS=y
 # CONFIG_SCSI_DEBUG is not set
 CONFIG_MVME16x_SCSI=y
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -511,7 +519,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -520,13 +528,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -631,6 +635,7 @@ CONFIG_SERIO_LIBPS2=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -661,6 +666,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -672,8 +678,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -708,10 +716,6 @@ CONFIG_SSB_POSSIBLE=y
 # Console display driver support
 #
 CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
@@ -723,6 +727,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -760,6 +765,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -819,6 +825,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -831,18 +838,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -851,7 +857,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -916,6 +921,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -975,6 +982,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1016,6 +1027,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig
index e05be687b500..72eaff0776b8 100644
--- a/arch/m68k/configs/q40_defconfig
+++ b/arch/m68k/configs/q40_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:10 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -163,10 +169,6 @@ CONFIG_ISA=y
 CONFIG_GENERIC_ISA_DMA=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -180,6 +182,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -410,6 +413,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -429,7 +433,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -448,6 +454,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -458,6 +465,7 @@ CONFIG_BLK_DEV_IDE=y
 #
 # Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
 CONFIG_BLK_DEV_IDEDISK=y
 # CONFIG_IDEDISK_MULTI_MODE is not set
@@ -475,8 +483,6 @@ CONFIG_IDE_PROC_FS=y
 # CONFIG_BLK_DEV_PLATFORM is not set
 CONFIG_BLK_DEV_Q40IDE=y
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD_ONLY is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
@@ -536,6 +542,7 @@ CONFIG_ISCSI_TCP=m
 # CONFIG_SCSI_SYM53C416 is not set
 # CONFIG_SCSI_T128 is not set
 # CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -544,7 +551,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -553,13 +560,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -680,6 +683,7 @@ CONFIG_SERIO_LIBPS2=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -711,6 +715,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -722,8 +727,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -792,10 +799,6 @@ CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
 CONFIG_SOUND=m
 CONFIG_DMASOUND_Q40=m
 CONFIG_DMASOUND=m
@@ -809,6 +812,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -843,6 +847,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -902,6 +907,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -924,7 +930,6 @@ CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -933,7 +938,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -997,6 +1001,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -1056,6 +1062,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1097,6 +1107,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig
index 296340d2b315..cb62b96d766e 100644
--- a/arch/m68k/configs/sun3_defconfig
+++ b/arch/m68k/configs/sun3_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:11 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -149,10 +155,6 @@ CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -166,6 +168,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -399,6 +402,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -418,7 +422,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -436,6 +442,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -488,6 +495,7 @@ CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ISCSI_TCP=m
 # CONFIG_SCSI_DEBUG is not set
 CONFIG_SUN3_SCSI=y
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -496,7 +504,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -505,13 +513,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -527,7 +531,6 @@ CONFIG_SUN3_82586=y
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
 # CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -617,6 +620,7 @@ CONFIG_SERIO_LIBPS2=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -647,19 +651,20 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -727,10 +732,6 @@ CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
@@ -776,6 +777,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -835,6 +837,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -847,18 +850,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -867,7 +869,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -932,6 +933,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -991,6 +994,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1032,6 +1039,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig
index 8d3a416c92bf..04b4363a7050 100644
--- a/arch/m68k/configs/sun3x_defconfig
+++ b/arch/m68k/configs/sun3x_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc4
-# Wed May 28 22:47:35 2008
+# Linux kernel version: 2.6.27-rc6
+# Wed Sep 10 09:02:12 2008
 #
 CONFIG_M68K=y
 CONFIG_MMU=y
@@ -52,7 +52,6 @@ CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
@@ -75,10 +74,16 @@ CONFIG_SLAB=y
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
 # CONFIG_HAVE_OPROFILE is not set
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
 # CONFIG_HAVE_KPROBES is not set
 # CONFIG_HAVE_KRETPROBES is not set
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
 # CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+# CONFIG_HAVE_CLK is not set
 CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
@@ -95,6 +100,7 @@ CONFIG_BLOCK=y
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
 CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
@@ -160,10 +166,6 @@ CONFIG_BINFMT_MISC=m
 CONFIG_PROC_HARDWARE=y
 CONFIG_ZONE_DMA=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
@@ -177,6 +179,7 @@ CONFIG_XFRM=y
 # CONFIG_XFRM_SUB_POLICY is not set
 CONFIG_XFRM_MIGRATE=y
 # CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
 CONFIG_NET_KEY=y
 CONFIG_NET_KEY_MIGRATE=y
 CONFIG_INET=y
@@ -410,6 +413,7 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # CONFIG_CFG80211 is not set
 CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_EXT_SYSFS is not set
 # CONFIG_MAC80211 is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
@@ -429,7 +433,9 @@ CONFIG_IEEE80211_CRYPT_TKIP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
@@ -447,6 +453,7 @@ CONFIG_CDROM_PKTCDVD=m
 CONFIG_CDROM_PKTCDVD_BUFFERS=8
 # CONFIG_CDROM_PKTCDVD_WCACHE is not set
 CONFIG_ATA_OVER_ETH=m
+# CONFIG_BLK_DEV_HD is not set
 CONFIG_MISC_DEVICES=y
 # CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
@@ -499,6 +506,7 @@ CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ISCSI_TCP=m
 # CONFIG_SCSI_DEBUG is not set
 CONFIG_SUN3X_ESP=y
+# CONFIG_SCSI_DH is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
 CONFIG_MD_LINEAR=m
@@ -507,7 +515,7 @@ CONFIG_MD_RAID1=m
 # CONFIG_MD_RAID10 is not set
 CONFIG_MD_RAID456=m
 CONFIG_MD_RAID5_RESHAPE=y
-CONFIG_MD_MULTIPATH=m
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_MD_FAULTY is not set
 CONFIG_BLK_DEV_DM=m
 # CONFIG_DM_DEBUG is not set
@@ -516,13 +524,9 @@ CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
 CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_EMC=m
-CONFIG_DM_MULTIPATH_RDAC=m
-CONFIG_DM_MULTIPATH_HP=m
 # CONFIG_DM_DELAY is not set
 CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
 CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 CONFIG_MACVLAN=m
@@ -627,6 +631,7 @@ CONFIG_SERIO_LIBPS2=m
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
@@ -657,6 +662,7 @@ CONFIG_GEN_RTC_X=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 
 #
@@ -668,8 +674,10 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multifunction device drivers
 #
+# CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
 
 #
 # Multimedia devices
@@ -737,10 +745,6 @@ CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=m
@@ -752,6 +756,7 @@ CONFIG_HIDRAW=y
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
 # CONFIG_UIO is not set
 
 #
@@ -786,6 +791,7 @@ CONFIG_XFS_FS=m
 CONFIG_OCFS2_FS=m
 CONFIG_OCFS2_FS_O2CB=m
 CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
 # CONFIG_OCFS2_DEBUG_MASKLOG is not set
 # CONFIG_OCFS2_DEBUG_FS is not set
 CONFIG_DNOTIFY=y
@@ -845,6 +851,7 @@ CONFIG_HFSPLUS_FS=m
 CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
 CONFIG_HPFS_FS=m
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_ROMFS_FS is not set
@@ -857,18 +864,17 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
 # CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
-CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
-CONFIG_SUNRPC_BIND34=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -877,7 +883,6 @@ CONFIG_SMB_NLS_REMOTE="cp437"
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 CONFIG_CODA_FS=m
-# CONFIG_CODA_FS_OLD_API is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -942,6 +947,8 @@ CONFIG_MAGIC_SYSRQ=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_SAMPLES is not set
 
 #
@@ -1001,6 +1008,10 @@ CONFIG_CRYPTO_CRC32C=m
 CONFIG_CRYPTO_MD4=m
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA1=m
 CONFIG_CRYPTO_SHA256=m
 CONFIG_CRYPTO_SHA512=m
@@ -1042,6 +1053,7 @@ CONFIG_BITREVERSE=y
 # CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 49896a2a1d72..cd5fbf6f0784 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -211,6 +211,7 @@ config MIPS_MALTA
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_MIPS_CMP if BROKEN  # because SYNC_R4K is broken
         select SYS_SUPPORTS_MULTITHREADING
         select SYS_SUPPORTS_SMARTMIPS
         help
@@ -567,7 +568,7 @@ config MIKROTIK_RB532
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SWAP_IO_SPACE
         select BOOT_RAW
-        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
         help
           Support the Mikrotik(tm) RouterBoard 532 series,
           based on the IDT RC32434 SoC.
@@ -597,7 +598,7 @@ config WR_PPMC
 
 endchoice
 
-source "arch/mips/au1000/Kconfig"
+source "arch/mips/alchemy/Kconfig"
 source "arch/mips/basler/excite/Kconfig"
 source "arch/mips/jazz/Kconfig"
 source "arch/mips/lasat/Kconfig"
@@ -609,11 +610,6 @@ source "arch/mips/vr41xx/Kconfig"
 
 endmenu
 
-config GENERIC_LOCKBREAK
-        bool
-        default y
-        depends on SMP && PREEMPT
-
 config RWSEM_GENERIC_SPINLOCK
         bool
         default y
@@ -1272,6 +1268,13 @@ config CPU_SUPPORTS_32BIT_KERNEL
 config CPU_SUPPORTS_64BIT_KERNEL
         bool
 
+#
+# Set to y for ptrace access to watch registers.
+#
+config HARDWARE_WATCHPOINTS
+       bool
+       default y if CPU_MIPS32 || CPU_MIPS64
+
 menu "Kernel type"
 
 choice
@@ -1403,7 +1406,6 @@ config MIPS_MT_SMTC
         depends on CPU_MIPS32_R2
         #depends on CPU_MIPS64_R2               # once there is hardware ...
         depends on SYS_SUPPORTS_MULTITHREADING
-        select GENERIC_CLOCKEVENTS_BROADCAST
         select CPU_MIPSR2_IRQ_VI
         select CPU_MIPSR2_IRQ_EI
         select MIPS_MT
@@ -1451,32 +1453,17 @@ config MIPS_VPE_LOADER
           Includes a loader for loading an elf relocatable object
           onto another VPE and running it.
 
-config MIPS_MT_SMTC_INSTANT_REPLAY
-        bool "Low-latency Dispatch of Deferred SMTC IPIs"
-        depends on MIPS_MT_SMTC && !PREEMPT
-        default y
-        help
-          SMTC pseudo-interrupts between TCs are deferred and queued
-          if the target TC is interrupt-inhibited (IXMT). In the first
-          SMTC prototypes, these queued IPIs were serviced on return
-          to user mode, or on entry into the kernel idle loop. The
-          INSTANT_REPLAY option dispatches them as part of local_irq_restore()
-          processing, which adds runtime overhead (hence the option to turn
-          it off), but ensures that IPIs are handled promptly even under
-          heavy I/O interrupt load.
-
 config MIPS_MT_SMTC_IM_BACKSTOP
         bool "Use per-TC register bits as backstop for inhibited IM bits"
         depends on MIPS_MT_SMTC
-        default y
+        default n
         help
           To support multiple TC microthreads acting as "CPUs" within
           a VPE, VPE-wide interrupt mask bits must be specially manipulated
           during interrupt handling. To support legacy drivers and interrupt
           controller management code, SMTC has a "backstop" to track and
           if necessary restore the interrupt mask. This has some performance
-          impact on interrupt service overhead. Disable it only if you know
-          what you are doing.
+          impact on interrupt service overhead.
 
 config MIPS_MT_SMTC_IRQAFF
         bool "Support IRQ affinity API"
@@ -1486,10 +1473,8 @@ config MIPS_MT_SMTC_IRQAFF
           Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)
           for SMTC Linux kernel. Requires platform support, of which
           an example can be found in the MIPS kernel i8259 and Malta
-          platform code.  It is recommended that MIPS_MT_SMTC_INSTANT_REPLAY
-          be enabled if MIPS_MT_SMTC_IRQAFF is used. Adds overhead to
-          interrupt dispatch, and should be used only if you know what
-          you are doing.
+          platform code.  Adds some overhead to interrupt dispatch, and
+          should be used only if you know what you are doing.
 
 config MIPS_VPE_LOADER_TOM
         bool "Load VPE program into memory hidden from linux"
@@ -1517,6 +1502,18 @@ config MIPS_APSP_KSPD
           "exit" syscall notifying other kernel modules the SP program is
           exiting.  You probably want to say yes here.
 
+config MIPS_CMP
+        bool "MIPS CMP framework support"
+        depends on SYS_SUPPORTS_MIPS_CMP
+        select SYNC_R4K if BROKEN
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_SCHED_SMT if SMP
+        select WEAK_ORDERING
+        default n
+        help
+          This is a placeholder option for the GCMP work. It will need to
+          be handled differently...
+
 config SB1_PASS_1_WORKAROUNDS
         bool
         depends on CPU_SB1_PASS_1
@@ -1693,6 +1690,9 @@ config SMP
 config SMP_UP
         bool
 
+config SYS_SUPPORTS_MIPS_CMP
+        bool
+
 config SYS_SUPPORTS_SMP
         bool
 
@@ -1740,17 +1740,6 @@ config NR_CPUS
           performance should round up your number of processors to the next
           power of two.
 
-config MIPS_CMP
-        bool "MIPS CMP framework support"
-        depends on SMP
-        select SYNC_R4K
-        select SYS_SUPPORTS_SCHED_SMT
-        select WEAK_ORDERING
-        default n
-        help
-          This is a placeholder option for the GCMP work. It will need to
-          be handled differently...
-
 source "kernel/time/Kconfig"
 
 #
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9aab51caf16a..7f39fd8a91fe 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -170,123 +170,123 @@ libs-$(CONFIG_SIBYTE_CFE)	+= arch/mips/sibyte/cfe/
 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
 #
 core-$(CONFIG_MACH_JAZZ)        += arch/mips/jazz/
-cflags-$(CONFIG_MACH_JAZZ)      += -Iinclude/asm-mips/mach-jazz
+cflags-$(CONFIG_MACH_JAZZ)      += -I$(srctree)/arch/mips/include/asm/mach-jazz
 load-$(CONFIG_MACH_JAZZ)        += 0xffffffff80080000
 
 #
 # Common Alchemy Au1x00 stuff
 #
-core-$(CONFIG_SOC_AU1X00)       += arch/mips/au1000/common/
-cflags-$(CONFIG_SOC_AU1X00)     += -Iinclude/asm-mips/mach-au1x00
+core-$(CONFIG_SOC_AU1X00)       += arch/mips/alchemy/common/
+cflags-$(CONFIG_SOC_AU1X00)     += -I$(srctree)/arch/mips/include/asm/mach-au1x00
 
 #
 # AMD Alchemy Pb1000 eval board
 #
-libs-$(CONFIG_MIPS_PB1000)      += arch/mips/au1000/pb1000/
-cflags-$(CONFIG_MIPS_PB1000)    += -Iinclude/asm-mips/mach-pb1x00
+libs-$(CONFIG_MIPS_PB1000)      += arch/mips/alchemy/pb1000/
+cflags-$(CONFIG_MIPS_PB1000)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1000)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Pb1100 eval board
 #
-libs-$(CONFIG_MIPS_PB1100)      += arch/mips/au1000/pb1100/
-cflags-$(CONFIG_MIPS_PB1100)    += -Iinclude/asm-mips/mach-pb1x00
+libs-$(CONFIG_MIPS_PB1100)      += arch/mips/alchemy/pb1100/
+cflags-$(CONFIG_MIPS_PB1100)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1100)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Pb1500 eval board
 #
-libs-$(CONFIG_MIPS_PB1500)      += arch/mips/au1000/pb1500/
-cflags-$(CONFIG_MIPS_PB1500)    += -Iinclude/asm-mips/mach-pb1x00
+libs-$(CONFIG_MIPS_PB1500)      += arch/mips/alchemy/pb1500/
+cflags-$(CONFIG_MIPS_PB1500)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1500)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Pb1550 eval board
 #
-libs-$(CONFIG_MIPS_PB1550)      += arch/mips/au1000/pb1550/
-cflags-$(CONFIG_MIPS_PB1550)    += -Iinclude/asm-mips/mach-pb1x00
+libs-$(CONFIG_MIPS_PB1550)      += arch/mips/alchemy/pb1550/
+cflags-$(CONFIG_MIPS_PB1550)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1550)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Pb1200 eval board
 #
-libs-$(CONFIG_MIPS_PB1200)      += arch/mips/au1000/pb1200/
-cflags-$(CONFIG_MIPS_PB1200)    += -Iinclude/asm-mips/mach-pb1x00
+libs-$(CONFIG_MIPS_PB1200)      += arch/mips/alchemy/pb1200/
+cflags-$(CONFIG_MIPS_PB1200)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1200)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Db1000 eval board
 #
-libs-$(CONFIG_MIPS_DB1000)      += arch/mips/au1000/db1x00/
-cflags-$(CONFIG_MIPS_DB1000)    += -Iinclude/asm-mips/mach-db1x00
+libs-$(CONFIG_MIPS_DB1000)      += arch/mips/alchemy/db1x00/
+cflags-$(CONFIG_MIPS_DB1000)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_DB1000)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Db1100 eval board
 #
-libs-$(CONFIG_MIPS_DB1100)      += arch/mips/au1000/db1x00/
-cflags-$(CONFIG_MIPS_DB1100)    += -Iinclude/asm-mips/mach-db1x00
+libs-$(CONFIG_MIPS_DB1100)      += arch/mips/alchemy/db1x00/
+cflags-$(CONFIG_MIPS_DB1100)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_DB1100)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Db1500 eval board
 #
-libs-$(CONFIG_MIPS_DB1500)      += arch/mips/au1000/db1x00/
-cflags-$(CONFIG_MIPS_DB1500)    += -Iinclude/asm-mips/mach-db1x00
+libs-$(CONFIG_MIPS_DB1500)      += arch/mips/alchemy/db1x00/
+cflags-$(CONFIG_MIPS_DB1500)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_DB1500)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Db1550 eval board
 #
-libs-$(CONFIG_MIPS_DB1550)      += arch/mips/au1000/db1x00/
-cflags-$(CONFIG_MIPS_DB1550)    += -Iinclude/asm-mips/mach-db1x00
+libs-$(CONFIG_MIPS_DB1550)      += arch/mips/alchemy/db1x00/
+cflags-$(CONFIG_MIPS_DB1550)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_DB1550)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Db1200 eval board
 #
-libs-$(CONFIG_MIPS_DB1200)      += arch/mips/au1000/pb1200/
-cflags-$(CONFIG_MIPS_DB1200)    += -Iinclude/asm-mips/mach-db1x00
+libs-$(CONFIG_MIPS_DB1200)      += arch/mips/alchemy/pb1200/
+cflags-$(CONFIG_MIPS_DB1200)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_DB1200)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Bosporus eval board
 #
-libs-$(CONFIG_MIPS_BOSPORUS)    += arch/mips/au1000/db1x00/
-cflags-$(CONFIG_MIPS_BOSPORUS)  += -Iinclude/asm-mips/mach-db1x00
+libs-$(CONFIG_MIPS_BOSPORUS)    += arch/mips/alchemy/db1x00/
+cflags-$(CONFIG_MIPS_BOSPORUS)  += -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_BOSPORUS)    += 0xffffffff80100000
 
 #
 # AMD Alchemy Mirage eval board
 #
-libs-$(CONFIG_MIPS_MIRAGE)      += arch/mips/au1000/db1x00/
-cflags-$(CONFIG_MIPS_MIRAGE)    += -Iinclude/asm-mips/mach-db1x00
+libs-$(CONFIG_MIPS_MIRAGE)      += arch/mips/alchemy/db1x00/
+cflags-$(CONFIG_MIPS_MIRAGE)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_MIRAGE)      += 0xffffffff80100000
 
 #
 # 4G-Systems eval board
 #
-libs-$(CONFIG_MIPS_MTX1)        += arch/mips/au1000/mtx-1/
+libs-$(CONFIG_MIPS_MTX1)        += arch/mips/alchemy/mtx-1/
 load-$(CONFIG_MIPS_MTX1)        += 0xffffffff80100000
 
 #
 # MyCable eval board
 #
-libs-$(CONFIG_MIPS_XXS1500)     += arch/mips/au1000/xxs1500/
+libs-$(CONFIG_MIPS_XXS1500)     += arch/mips/alchemy/xxs1500/
 load-$(CONFIG_MIPS_XXS1500)     += 0xffffffff80100000
 
 #
 # Cobalt Server
 #
 core-$(CONFIG_MIPS_COBALT)      += arch/mips/cobalt/
-cflags-$(CONFIG_MIPS_COBALT)    += -Iinclude/asm-mips/mach-cobalt
+cflags-$(CONFIG_MIPS_COBALT)    += -I$(srctree)/arch/mips/include/asm/mach-cobalt
 load-$(CONFIG_MIPS_COBALT)      += 0xffffffff80080000
 
 #
 # DECstation family
 #
 core-$(CONFIG_MACH_DECSTATION)  += arch/mips/dec/
-cflags-$(CONFIG_MACH_DECSTATION)+= -Iinclude/asm-mips/mach-dec
+cflags-$(CONFIG_MACH_DECSTATION)+= -I$(srctree)/arch/mips/include/asm/mach-dec
 libs-$(CONFIG_MACH_DECSTATION)  += arch/mips/dec/prom/
 load-$(CONFIG_MACH_DECSTATION)  += 0xffffffff80040000
 
@@ -294,7 +294,7 @@ load-$(CONFIG_MACH_DECSTATION)	+= 0xffffffff80040000
 # Wind River PPMC Board (4KC + GT64120)
 #
 core-$(CONFIG_WR_PPMC)          += arch/mips/gt64120/wrppmc/
-cflags-$(CONFIG_WR_PPMC)                += -Iinclude/asm-mips/mach-wrppmc
+cflags-$(CONFIG_WR_PPMC)                += -I$(srctree)/arch/mips/include/asm/mach-wrppmc
 load-$(CONFIG_WR_PPMC)          += 0xffffffff80100000
 
 #
@@ -302,13 +302,13 @@ load-$(CONFIG_WR_PPMC)		+= 0xffffffff80100000
 #
 core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/
 load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000
-cflags-$(CONFIG_LEMOTE_FULONG) += -Iinclude/asm-mips/mach-lemote
+cflags-$(CONFIG_LEMOTE_FULONG) += -I$(srctree)/arch/mips/include/asm/mach-lemote
 
 #
 # MIPS Malta board
 #
 core-$(CONFIG_MIPS_MALTA)       += arch/mips/mti-malta/
-cflags-$(CONFIG_MIPS_MALTA)     += -Iinclude/asm-mips/mach-malta
+cflags-$(CONFIG_MIPS_MALTA)     += -I$(srctree)/arch/mips/include/asm/mach-malta
 load-$(CONFIG_MIPS_MALTA)       += 0xffffffff80100000
 all-$(CONFIG_MIPS_MALTA)        := vmlinux.bin
 
@@ -316,14 +316,14 @@ all-$(CONFIG_MIPS_MALTA)	:= vmlinux.bin
 # MIPS SIM
 #
 core-$(CONFIG_MIPS_SIM)         += arch/mips/mipssim/
-cflags-$(CONFIG_MIPS_SIM)       += -Iinclude/asm-mips/mach-mipssim
+cflags-$(CONFIG_MIPS_SIM)       += -I$(srctree)/arch/mips/include/asm/mach-mipssim
 load-$(CONFIG_MIPS_SIM)         += 0x80100000
 
 #
 # PMC-Sierra MSP SOCs
 #
 core-$(CONFIG_PMC_MSP)          += arch/mips/pmc-sierra/msp71xx/
-cflags-$(CONFIG_PMC_MSP)        += -Iinclude/asm-mips/pmc-sierra/msp71xx \
+cflags-$(CONFIG_PMC_MSP)        += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
                                         -mno-branch-likely
 load-$(CONFIG_PMC_MSP)          += 0xffffffff80100000
 
@@ -331,28 +331,28 @@ load-$(CONFIG_PMC_MSP)		+= 0xffffffff80100000
 # PMC-Sierra Yosemite
 #
 core-$(CONFIG_PMC_YOSEMITE)     += arch/mips/pmc-sierra/yosemite/
-cflags-$(CONFIG_PMC_YOSEMITE)   += -Iinclude/asm-mips/mach-yosemite
+cflags-$(CONFIG_PMC_YOSEMITE)   += -I$(srctree)/arch/mips/include/asm/mach-yosemite
 load-$(CONFIG_PMC_YOSEMITE)     += 0xffffffff80100000
 
 #
 # Basler eXcite
 #
 core-$(CONFIG_BASLER_EXCITE)    += arch/mips/basler/excite/
-cflags-$(CONFIG_BASLER_EXCITE)  += -Iinclude/asm-mips/mach-excite
+cflags-$(CONFIG_BASLER_EXCITE)  += -I$(srctree)/arch/mips/include/asm/mach-excite
 load-$(CONFIG_BASLER_EXCITE)    += 0x80100000
 
 #
 # LASAT platforms
 #
 core-$(CONFIG_LASAT)            += arch/mips/lasat/
-cflags-$(CONFIG_LASAT)          += -Iinclude/asm-mips/mach-lasat
+cflags-$(CONFIG_LASAT)          += -I$(srctree)/arch/mips/include/asm/mach-lasat
 load-$(CONFIG_LASAT)            += 0xffffffff80000000
 
 #
 # Common VR41xx
 #
 core-$(CONFIG_MACH_VR41XX)      += arch/mips/vr41xx/common/
-cflags-$(CONFIG_MACH_VR41XX)    += -Iinclude/asm-mips/mach-vr41xx
+cflags-$(CONFIG_MACH_VR41XX)    += -I$(srctree)/arch/mips/include/asm/mach-vr41xx
 
 #
 # ZAO Networks Capcella (VR4131)
@@ -385,13 +385,13 @@ load-$(CONFIG_TANBAC_TB022X)	+= 0xffffffff80000000
 # Common NXP PNX8550
 #
 core-$(CONFIG_SOC_PNX8550)      += arch/mips/nxp/pnx8550/common/
-cflags-$(CONFIG_SOC_PNX8550)    += -Iinclude/asm-mips/mach-pnx8550
+cflags-$(CONFIG_SOC_PNX8550)    += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
 
 #
 # NXP PNX8550 JBS board
 #
 libs-$(CONFIG_PNX8550_JBS)      += arch/mips/nxp/pnx8550/jbs/
-#cflags-$(CONFIG_PNX8550_JBS)   += -Iinclude/asm-mips/mach-pnx8550
+#cflags-$(CONFIG_PNX8550_JBS)   += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
 load-$(CONFIG_PNX8550_JBS)      += 0xffffffff80060000
 
 # NXP PNX8550 STB810 board
@@ -402,7 +402,7 @@ load-$(CONFIG_PNX8550_STB810)	+= 0xffffffff80060000
 # NEC EMMA2RH boards
 #
 core-$(CONFIG_EMMA2RH)          += arch/mips/emma2rh/common/
-cflags-$(CONFIG_EMMA2RH)        += -Iinclude/asm-mips/mach-emma2rh
+cflags-$(CONFIG_EMMA2RH)        += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
 
 # NEC EMMA2RH Mark-eins
 core-$(CONFIG_MARKEINS)         += arch/mips/emma2rh/markeins/
@@ -418,7 +418,7 @@ load-$(CONFIG_MARKEINS)         += 0xffffffff88100000
 # address by 8kb.
 #
 core-$(CONFIG_SGI_IP22)         += arch/mips/sgi-ip22/
-cflags-$(CONFIG_SGI_IP22)       += -Iinclude/asm-mips/mach-ip22
+cflags-$(CONFIG_SGI_IP22)       += -I$(srctree)/arch/mips/include/asm/mach-ip22
 ifdef CONFIG_32BIT
 load-$(CONFIG_SGI_IP22)         += 0xffffffff88002000
 endif
@@ -435,7 +435,7 @@ endif
 #
 ifdef CONFIG_SGI_IP27
 core-$(CONFIG_SGI_IP27)         += arch/mips/sgi-ip27/
-cflags-$(CONFIG_SGI_IP27)       += -Iinclude/asm-mips/mach-ip27
+cflags-$(CONFIG_SGI_IP27)       += -I$(srctree)/arch/mips/include/asm/mach-ip27
 ifdef CONFIG_MAPPED_KERNEL
 load-$(CONFIG_SGI_IP27)         += 0xc00000004001c000
 OBJCOPYFLAGS                    := --change-addresses=0x3fffffff80000000
@@ -460,7 +460,7 @@ ifdef CONFIG_SGI_IP28
   endif
 endif
 core-$(CONFIG_SGI_IP28)         += arch/mips/sgi-ip22/
-cflags-$(CONFIG_SGI_IP28)       += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28
+cflags-$(CONFIG_SGI_IP28)       += -mr10k-cache-barrier=1 -I$(srctree)/arch/mips/include/asm/mach-ip28
 load-$(CONFIG_SGI_IP28)         += 0xa800000020004000
 
 #
@@ -472,7 +472,7 @@ load-$(CONFIG_SGI_IP28)		+= 0xa800000020004000
 # will break.
 #
 core-$(CONFIG_SGI_IP32)         += arch/mips/sgi-ip32/
-cflags-$(CONFIG_SGI_IP32)       += -Iinclude/asm-mips/mach-ip32
+cflags-$(CONFIG_SGI_IP32)       += -I$(srctree)/arch/mips/include/asm/mach-ip32
 load-$(CONFIG_SGI_IP32)         += 0xffffffff80004000
 
 #
@@ -484,22 +484,22 @@ load-$(CONFIG_SGI_IP32)		+= 0xffffffff80004000
 #
 core-$(CONFIG_SIBYTE_BCM112X)   += arch/mips/sibyte/sb1250/
 core-$(CONFIG_SIBYTE_BCM112X)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte \
+cflags-$(CONFIG_SIBYTE_BCM112X) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
                         -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
 
 core-$(CONFIG_SIBYTE_SB1250)    += arch/mips/sibyte/sb1250/
 core-$(CONFIG_SIBYTE_SB1250)    += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_SB1250)  += -Iinclude/asm-mips/mach-sibyte \
+cflags-$(CONFIG_SIBYTE_SB1250)  += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
                         -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
 
 core-$(CONFIG_SIBYTE_BCM1x55)   += arch/mips/sibyte/bcm1480/
 core-$(CONFIG_SIBYTE_BCM1x55)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM1x55) += -Iinclude/asm-mips/mach-sibyte \
+cflags-$(CONFIG_SIBYTE_BCM1x55) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
                         -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
 
 core-$(CONFIG_SIBYTE_BCM1x80)   += arch/mips/sibyte/bcm1480/
 core-$(CONFIG_SIBYTE_BCM1x80)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM1x80) += -Iinclude/asm-mips/mach-sibyte \
+cflags-$(CONFIG_SIBYTE_BCM1x80) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
                         -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
 
 #
@@ -529,14 +529,14 @@ load-$(CONFIG_SIBYTE_BIGSUR)	:= 0xffffffff80100000
 # Broadcom BCM47XX boards
 #
 core-$(CONFIG_BCM47XX)          += arch/mips/bcm47xx/
-cflags-$(CONFIG_BCM47XX)        += -Iinclude/asm-mips/mach-bcm47xx
+cflags-$(CONFIG_BCM47XX)        += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
 load-$(CONFIG_BCM47XX)          := 0xffffffff80001000
 
 #
 # SNI RM
 #
 core-$(CONFIG_SNI_RM)           += arch/mips/sni/
-cflags-$(CONFIG_SNI_RM)         += -Iinclude/asm-mips/mach-rm
+cflags-$(CONFIG_SNI_RM)         += -I$(srctree)/arch/mips/include/asm/mach-rm
 ifdef CONFIG_CPU_LITTLE_ENDIAN
 load-$(CONFIG_SNI_RM)           += 0xffffffff80600000
 else
@@ -548,10 +548,10 @@ all-$(CONFIG_SNI_RM)		:= vmlinux.ecoff
 # Common TXx9
 #
 core-$(CONFIG_MACH_TX39XX)      += arch/mips/txx9/generic/
-cflags-$(CONFIG_MACH_TX39XX) += -Iinclude/asm-mips/mach-tx39xx
+cflags-$(CONFIG_MACH_TX39XX) += -I$(srctree)/arch/mips/include/asm/mach-tx39xx
 load-$(CONFIG_MACH_TX39XX)      += 0xffffffff80050000
 core-$(CONFIG_MACH_TX49XX)      += arch/mips/txx9/generic/
-cflags-$(CONFIG_MACH_TX49XX) += -Iinclude/asm-mips/mach-tx49xx
+cflags-$(CONFIG_MACH_TX49XX) += -I$(srctree)/arch/mips/include/asm/mach-tx49xx
 load-$(CONFIG_MACH_TX49XX)      += 0xffffffff80100000
 
 #
@@ -563,21 +563,17 @@ core-$(CONFIG_TOSHIBA_JMR3927)	+= arch/mips/txx9/jmr3927/
 # Routerboard 532 board
 #
 core-$(CONFIG_MIKROTIK_RB532)   += arch/mips/rb532/
-cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434
+cflags-$(CONFIG_MIKROTIK_RB532) += -I$(srctree)/arch/mips/include/asm/mach-rc32434
 load-$(CONFIG_MIKROTIK_RB532)   += 0xffffffff80101000
 
 #
-# Toshiba RBTX4927 board or
-# Toshiba RBTX4937 board
+# Toshiba RBTX49XX boards
 #
 core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
-
-#
-# Toshiba RBTX4938 board
-#
 core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
+core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
 
-cflags-y                        += -Iinclude/asm-mips/mach-generic
+cflags-y                        += -I$(srctree)/arch/mips/include/asm/mach-generic
 drivers-$(CONFIG_PCI)           += arch/mips/pci/
 
 ifdef CONFIG_32BIT
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/alchemy/Kconfig
index e4a057d80ab6..e4a057d80ab6 100644
--- a/arch/mips/au1000/Kconfig
+++ b/arch/mips/alchemy/Kconfig
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/alchemy/common/Makefile
index df48fd65bbf3..df48fd65bbf3 100644
--- a/arch/mips/au1000/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/alchemy/common/au1xxx_irqmap.c
index c7ca1596394c..c7ca1596394c 100644
--- a/arch/mips/au1000/common/au1xxx_irqmap.c
+++ b/arch/mips/alchemy/common/au1xxx_irqmap.c
diff --git a/arch/mips/au1000/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index 043429d17c5f..043429d17c5f 100644
--- a/arch/mips/au1000/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/alchemy/common/cputable.c
index ba6430bc2d03..ba6430bc2d03 100644
--- a/arch/mips/au1000/common/cputable.c
+++ b/arch/mips/alchemy/common/cputable.c
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 601ee9180ee4..601ee9180ee4 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
diff --git a/arch/mips/au1000/common/dma.c b/arch/mips/alchemy/common/dma.c
index d6fbda232e6a..d6fbda232e6a 100644
--- a/arch/mips/au1000/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
diff --git a/arch/mips/au1000/common/gpio.c b/arch/mips/alchemy/common/gpio.c
index b485d94ce8a5..e660ddd611c4 100644
--- a/arch/mips/au1000/common/gpio.c
+++ b/arch/mips/alchemy/common/gpio.c
@@ -48,7 +48,7 @@ static void au1xxx_gpio2_write(unsigned gpio, int value)
 {
         gpio -= AU1XXX_GPIO_BASE;
 
-        gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | (value << gpio);
+        gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
 }
 
 static int au1xxx_gpio2_direction_input(unsigned gpio)
@@ -61,7 +61,8 @@ static int au1xxx_gpio2_direction_input(unsigned gpio)
 static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
 {
         gpio -= AU1XXX_GPIO_BASE;
-        gpio2->dir = (0x01 << gpio) | (value << gpio);
+        gpio2->dir |= 0x01 << gpio;
+        gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
         return 0;
 }
 
@@ -90,6 +91,7 @@ static int au1xxx_gpio1_direction_input(unsigned gpio)
 static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
 {
         gpio1->trioutclr = (0x01 & gpio);
+        au1xxx_gpio1_write(gpio, value);
         return 0;
 }
 
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/alchemy/common/irq.c
index 40c6ceceb5f9..40c6ceceb5f9 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/alchemy/common/pci.c
index 7866cf50cf99..7866cf50cf99 100644
--- a/arch/mips/au1000/common/pci.c
+++ b/arch/mips/alchemy/common/pci.c
diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/alchemy/common/platform.c
index dc8a67efac28..dc8a67efac28 100644
--- a/arch/mips/au1000/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/alchemy/common/power.c
index bd854a6d1d89..bd854a6d1d89 100644
--- a/arch/mips/au1000/common/power.c
+++ b/arch/mips/alchemy/common/power.c
diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/alchemy/common/prom.c
index 18b310b475ca..18b310b475ca 100644
--- a/arch/mips/au1000/common/prom.c
+++ b/arch/mips/alchemy/common/prom.c
diff --git a/arch/mips/au1000/common/puts.c b/arch/mips/alchemy/common/puts.c
index 55bbe24d45b6..55bbe24d45b6 100644
--- a/arch/mips/au1000/common/puts.c
+++ b/arch/mips/alchemy/common/puts.c
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/alchemy/common/reset.c
index d555429c8d6f..d555429c8d6f 100644
--- a/arch/mips/au1000/common/reset.c
+++ b/arch/mips/alchemy/common/reset.c
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/alchemy/common/setup.c
index 1ac6b06f42a3..1ac6b06f42a3 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
diff --git a/arch/mips/au1000/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 4b3cf021a454..3006e270c8bc 100644
--- a/arch/mips/au1000/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -79,12 +79,12 @@ LEAF(save_and_sleep)
 /* Put SDRAM into self refresh.  Preload instructions into cache,
  * issue a precharge, then auto refresh, then sleep commands to it.
  */
-        la      t0, sdsleep
+        la      t0, sdsleep
         .set    mips3
-        cache   0x14, 0(t0)
-        cache   0x14, 32(t0)
-        cache   0x14, 64(t0)
-        cache   0x14, 96(t0)
+        cache   0x14, 0(t0)
+        cache   0x14, 32(t0)
+        cache   0x14, 64(t0)
+        cache   0x14, 96(t0)
         .set    mips0
 
 sdsleep:
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/alchemy/common/time.c
index 563d9390a872..563d9390a872 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/alchemy/common/time.c
diff --git a/arch/mips/au1000/db1x00/Makefile b/arch/mips/alchemy/db1x00/Makefile
index 274db3b55d82..274db3b55d82 100644
--- a/arch/mips/au1000/db1x00/Makefile
+++ b/arch/mips/alchemy/db1x00/Makefile
diff --git a/arch/mips/au1000/db1x00/board_setup.c b/arch/mips/alchemy/db1x00/board_setup.c
index 9e5ccbbfcedd..9e5ccbbfcedd 100644
--- a/arch/mips/au1000/db1x00/board_setup.c
+++ b/arch/mips/alchemy/db1x00/board_setup.c
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/alchemy/db1x00/init.c
index 847413514964..847413514964 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/alchemy/db1x00/init.c
diff --git a/arch/mips/au1000/db1x00/irqmap.c b/arch/mips/alchemy/db1x00/irqmap.c
index 94c090e8bf7a..94c090e8bf7a 100644
--- a/arch/mips/au1000/db1x00/irqmap.c
+++ b/arch/mips/alchemy/db1x00/irqmap.c
diff --git a/arch/mips/au1000/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
index 7c67b3d33bec..7c67b3d33bec 100644
--- a/arch/mips/au1000/mtx-1/Makefile
+++ b/arch/mips/alchemy/mtx-1/Makefile
diff --git a/arch/mips/au1000/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 3f8079186cf2..3f8079186cf2 100644
--- a/arch/mips/au1000/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
index 3bae13c28954..3bae13c28954 100644
--- a/arch/mips/au1000/mtx-1/init.c
+++ b/arch/mips/alchemy/mtx-1/init.c
diff --git a/arch/mips/au1000/mtx-1/irqmap.c b/arch/mips/alchemy/mtx-1/irqmap.c
index f2bf02951e9c..f2bf02951e9c 100644
--- a/arch/mips/au1000/mtx-1/irqmap.c
+++ b/arch/mips/alchemy/mtx-1/irqmap.c
diff --git a/arch/mips/au1000/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c
index 8b5914d1241f..8b5914d1241f 100644
--- a/arch/mips/au1000/mtx-1/platform.c
+++ b/arch/mips/alchemy/mtx-1/platform.c
diff --git a/arch/mips/au1000/pb1000/Makefile b/arch/mips/alchemy/pb1000/Makefile
index 99bbec0ca41b..99bbec0ca41b 100644
--- a/arch/mips/au1000/pb1000/Makefile
+++ b/arch/mips/alchemy/pb1000/Makefile
diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/alchemy/pb1000/board_setup.c
index 25df167a95b3..25df167a95b3 100644
--- a/arch/mips/au1000/pb1000/board_setup.c
+++ b/arch/mips/alchemy/pb1000/board_setup.c
diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/alchemy/pb1000/init.c
index 8a9c7d57208d..8a9c7d57208d 100644
--- a/arch/mips/au1000/pb1000/init.c
+++ b/arch/mips/alchemy/pb1000/init.c
diff --git a/arch/mips/au1000/pb1000/irqmap.c b/arch/mips/alchemy/pb1000/irqmap.c
index b3d56b0af321..b3d56b0af321 100644
--- a/arch/mips/au1000/pb1000/irqmap.c
+++ b/arch/mips/alchemy/pb1000/irqmap.c
diff --git a/arch/mips/au1000/pb1100/Makefile b/arch/mips/alchemy/pb1100/Makefile
index 793e97c49e46..793e97c49e46 100644
--- a/arch/mips/au1000/pb1100/Makefile
+++ b/arch/mips/alchemy/pb1100/Makefile
diff --git a/arch/mips/au1000/pb1100/board_setup.c b/arch/mips/alchemy/pb1100/board_setup.c
index c0bfd59a7a36..c0bfd59a7a36 100644
--- a/arch/mips/au1000/pb1100/board_setup.c
+++ b/arch/mips/alchemy/pb1100/board_setup.c
diff --git a/arch/mips/au1000/pb1100/init.c b/arch/mips/alchemy/pb1100/init.c
index 7c6792308bc5..7c6792308bc5 100644
--- a/arch/mips/au1000/pb1100/init.c
+++ b/arch/mips/alchemy/pb1100/init.c
diff --git a/arch/mips/au1000/pb1100/irqmap.c b/arch/mips/alchemy/pb1100/irqmap.c
index 9b7dd8b41283..9b7dd8b41283 100644
--- a/arch/mips/au1000/pb1100/irqmap.c
+++ b/arch/mips/alchemy/pb1100/irqmap.c
diff --git a/arch/mips/au1000/pb1200/Makefile b/arch/mips/alchemy/pb1200/Makefile
index d678adf7ce85..d678adf7ce85 100644
--- a/arch/mips/au1000/pb1200/Makefile
+++ b/arch/mips/alchemy/pb1200/Makefile
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/alchemy/pb1200/board_setup.c
index 6cb2115059ad..6cb2115059ad 100644
--- a/arch/mips/au1000/pb1200/board_setup.c
+++ b/arch/mips/alchemy/pb1200/board_setup.c
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/alchemy/pb1200/init.c
index e9b2a0fd48ae..e9b2a0fd48ae 100644
--- a/arch/mips/au1000/pb1200/init.c
+++ b/arch/mips/alchemy/pb1200/init.c
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/alchemy/pb1200/irqmap.c
index 2a505ad8715b..2a505ad8715b 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/alchemy/pb1200/irqmap.c
diff --git a/arch/mips/au1000/pb1200/platform.c b/arch/mips/alchemy/pb1200/platform.c
index f8fb0aeac571..f8fb0aeac571 100644
--- a/arch/mips/au1000/pb1200/platform.c
+++ b/arch/mips/alchemy/pb1200/platform.c
diff --git a/arch/mips/au1000/pb1500/Makefile b/arch/mips/alchemy/pb1500/Makefile
index 602f38df20bb..602f38df20bb 100644
--- a/arch/mips/au1000/pb1500/Makefile
+++ b/arch/mips/alchemy/pb1500/Makefile
diff --git a/arch/mips/au1000/pb1500/board_setup.c b/arch/mips/alchemy/pb1500/board_setup.c
index 035771c6e5b8..035771c6e5b8 100644
--- a/arch/mips/au1000/pb1500/board_setup.c
+++ b/arch/mips/alchemy/pb1500/board_setup.c
diff --git a/arch/mips/au1000/pb1500/init.c b/arch/mips/alchemy/pb1500/init.c
index 3b6e395cf952..3b6e395cf952 100644
--- a/arch/mips/au1000/pb1500/init.c
+++ b/arch/mips/alchemy/pb1500/init.c
diff --git a/arch/mips/au1000/pb1500/irqmap.c b/arch/mips/alchemy/pb1500/irqmap.c
index 39c4682766a8..39c4682766a8 100644
--- a/arch/mips/au1000/pb1500/irqmap.c
+++ b/arch/mips/alchemy/pb1500/irqmap.c
diff --git a/arch/mips/au1000/pb1550/Makefile b/arch/mips/alchemy/pb1550/Makefile
index 7d8beca87fa5..7d8beca87fa5 100644
--- a/arch/mips/au1000/pb1550/Makefile
+++ b/arch/mips/alchemy/pb1550/Makefile
diff --git a/arch/mips/au1000/pb1550/board_setup.c b/arch/mips/alchemy/pb1550/board_setup.c
index 0ed76b64b6ab..0ed76b64b6ab 100644
--- a/arch/mips/au1000/pb1550/board_setup.c
+++ b/arch/mips/alchemy/pb1550/board_setup.c
diff --git a/arch/mips/au1000/pb1550/init.c b/arch/mips/alchemy/pb1550/init.c
index e1055a13a1a0..e1055a13a1a0 100644
--- a/arch/mips/au1000/pb1550/init.c
+++ b/arch/mips/alchemy/pb1550/init.c
diff --git a/arch/mips/au1000/pb1550/irqmap.c b/arch/mips/alchemy/pb1550/irqmap.c
index a02a4d1fa899..a02a4d1fa899 100644
--- a/arch/mips/au1000/pb1550/irqmap.c
+++ b/arch/mips/alchemy/pb1550/irqmap.c
diff --git a/arch/mips/au1000/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
index db3c526f64d8..db3c526f64d8 100644
--- a/arch/mips/au1000/xxs1500/Makefile
+++ b/arch/mips/alchemy/xxs1500/Makefile
diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 4c587acac5c3..4c587acac5c3 100644
--- a/arch/mips/au1000/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
index 7516434760a1..7516434760a1 100644
--- a/arch/mips/au1000/xxs1500/init.c
+++ b/arch/mips/alchemy/xxs1500/init.c
diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/alchemy/xxs1500/irqmap.c
index edf06ed11870..edf06ed11870 100644
--- a/arch/mips/au1000/xxs1500/irqmap.c
+++ b/arch/mips/alchemy/xxs1500/irqmap.c
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
new file mode 100644
index 000000000000..7897f05e3165
--- /dev/null
+++ b/arch/mips/include/asm/Kbuild
@@ -0,0 +1,3 @@
+include include/asm-generic/Kbuild.asm
+
+header-y += cachectl.h sgidefs.h sysmips.h
diff --git a/arch/mips/include/asm/a.out.h b/arch/mips/include/asm/a.out.h
new file mode 100644
index 000000000000..cad8371422ab
--- /dev/null
+++ b/arch/mips/include/asm/a.out.h
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_A_OUT_H
+#define _ASM_A_OUT_H
+
+#ifdef __KERNEL__
+
+
+#endif
+
+struct exec
+{
+        unsigned long a_info;   /* Use macros N_MAGIC, etc for access */
+        unsigned a_text;        /* length of text, in bytes */
+        unsigned a_data;        /* length of data, in bytes */
+        unsigned a_bss;         /* length of uninitialized data area for
+                                    file, in bytes */
+        unsigned a_syms;        /* length of symbol table data in file,
+                                   in bytes */
+        unsigned a_entry;       /* start address */
+        unsigned a_trsize;      /* length of relocation info for text, in
+                                    bytes */
+        unsigned a_drsize;      /* length of relocation info for data, in bytes */
+};
+
+#define N_TRSIZE(a)     ((a).a_trsize)
+#define N_DRSIZE(a)     ((a).a_drsize)
+#define N_SYMSIZE(a)    ((a).a_syms)
+
+#endif /* _ASM_A_OUT_H */
diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h
new file mode 100644
index 000000000000..1dd74fbdc09b
--- /dev/null
+++ b/arch/mips/include/asm/abi.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005, 06 by Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2005 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_ABI_H
+#define _ASM_ABI_H
+
+#include <asm/signal.h>
+#include <asm/siginfo.h>
+
+struct mips_abi {
+        int (* const setup_frame)(struct k_sigaction * ka,
+                                  struct pt_regs *regs, int signr,
+                                  sigset_t *set);
+        int (* const setup_rt_frame)(struct k_sigaction * ka,
+                               struct pt_regs *regs, int signr,
+                               sigset_t *set, siginfo_t *info);
+        const unsigned long     restart;
+};
+
+#endif /* _ASM_ABI_H */
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
new file mode 100644
index 000000000000..569f80aacbd2
--- /dev/null
+++ b/arch/mips/include/asm/addrspace.h
@@ -0,0 +1,154 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ADDRSPACE_H
+#define _ASM_ADDRSPACE_H
+
+#include <spaces.h>
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ATYPE_
+#define _ATYPE32_
+#define _ATYPE64_
+#define _CONST64_(x)    x
+#else
+#define _ATYPE_         __PTRDIFF_TYPE__
+#define _ATYPE32_       int
+#define _ATYPE64_       __s64
+#ifdef CONFIG_64BIT
+#define _CONST64_(x)    x ## L
+#else
+#define _CONST64_(x)    x ## LL
+#endif
+#endif
+
+/*
+ *  32-bit MIPS address spaces
+ */
+#ifdef __ASSEMBLY__
+#define _ACAST32_
+#define _ACAST64_
+#else
+#define _ACAST32_               (_ATYPE_)(_ATYPE32_)    /* widen if necessary */
+#define _ACAST64_               (_ATYPE64_)             /* do _not_ narrow */
+#endif
+
+/*
+ * Returns the kernel segment base of a given address
+ */
+#define KSEGX(a)                ((_ACAST32_ (a)) & 0xe0000000)
+
+/*
+ * Returns the physical address of a CKSEGx / XKPHYS address
+ */
+#define CPHYSADDR(a)            ((_ACAST32_(a)) & 0x1fffffff)
+#define XPHYSADDR(a)            ((_ACAST64_(a)) &                       \
+                                 _CONST64_(0x000000ffffffffff))
+
+#ifdef CONFIG_64BIT
+
+/*
+ * Memory segments (64bit kernel mode addresses)
+ * The compatibility segments use the full 64-bit sign extended value.  Note
+ * the R8000 doesn't have them so don't reference these in generic MIPS code.
+ */
+#define XKUSEG                  _CONST64_(0x0000000000000000)
+#define XKSSEG                  _CONST64_(0x4000000000000000)
+#define XKPHYS                  _CONST64_(0x8000000000000000)
+#define XKSEG                   _CONST64_(0xc000000000000000)
+#define CKSEG0                  _CONST64_(0xffffffff80000000)
+#define CKSEG1                  _CONST64_(0xffffffffa0000000)
+#define CKSSEG                  _CONST64_(0xffffffffc0000000)
+#define CKSEG3                  _CONST64_(0xffffffffe0000000)
+
+#define CKSEG0ADDR(a)           (CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)           (CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a)           (CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a)           (CPHYSADDR(a) | CKSEG3)
+
+#else
+
+#define CKSEG0ADDR(a)           (CPHYSADDR(a) | KSEG0)
+#define CKSEG1ADDR(a)           (CPHYSADDR(a) | KSEG1)
+#define CKSEG2ADDR(a)           (CPHYSADDR(a) | KSEG2)
+#define CKSEG3ADDR(a)           (CPHYSADDR(a) | KSEG3)
+
+/*
+ * Map an address to a certain kernel segment
+ */
+#define KSEG0ADDR(a)            (CPHYSADDR(a) | KSEG0)
+#define KSEG1ADDR(a)            (CPHYSADDR(a) | KSEG1)
+#define KSEG2ADDR(a)            (CPHYSADDR(a) | KSEG2)
+#define KSEG3ADDR(a)            (CPHYSADDR(a) | KSEG3)
+
+/*
+ * Memory segments (32bit kernel mode addresses)
+ * These are the traditional names used in the 32-bit universe.
+ */
+#define KUSEG                   0x00000000
+#define KSEG0                   0x80000000
+#define KSEG1                   0xa0000000
+#define KSEG2                   0xc0000000
+#define KSEG3                   0xe0000000
+
+#define CKUSEG                  0x00000000
+#define CKSEG0                  0x80000000
+#define CKSEG1                  0xa0000000
+#define CKSEG2                  0xc0000000
+#define CKSEG3                  0xe0000000
+
+#endif
+
+/*
+ * Cache modes for XKPHYS address conversion macros
+ */
+#define K_CALG_COH_EXCL1_NOL2   0
+#define K_CALG_COH_SHRL1_NOL2   1
+#define K_CALG_UNCACHED         2
+#define K_CALG_NONCOHERENT      3
+#define K_CALG_COH_EXCL         4
+#define K_CALG_COH_SHAREABLE    5
+#define K_CALG_NOTUSED          6
+#define K_CALG_UNCACHED_ACCEL   7
+
+/*
+ * 64-bit address conversions
+ */
+#define PHYS_TO_XKSEG_UNCACHED(p)       PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
+#define PHYS_TO_XKSEG_CACHED(p)         PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
+#define XKPHYS_TO_PHYS(p)               ((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm, a)           (_CONST64_(0x8000000000000000) | \
+                                         (_CONST64_(cm) << 59) | (a))
+
+/*
+ * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
+ * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
+ * R8000 implements most with its 48-bit physical address space.
+ */
+#define TO_PHYS_MASK    _CONST64_(0x07ffffffffffffff)   /* 2^^59 - 1 */
+
+#ifndef CONFIG_CPU_R8000
+
+/*
+ * The R8000 doesn't have the 32-bit compat spaces so we don't define them
+ * in order to catch bugs in the source code.
+ */
+
+#define COMPAT_K1BASE32         _CONST64_(0xffffffffa0000000)
+#define PHYS_TO_COMPATK1(x)     ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
+
+#endif
+
+#define KDM_TO_PHYS(x)          (_ACAST64_ (x) & TO_PHYS_MASK)
+#define PHYS_TO_K0(x)           (_ACAST64_ (x) | CAC_BASE)
+
+#endif /* _ASM_ADDRSPACE_H */
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
new file mode 100644
index 000000000000..608cfcfbb3ea
--- /dev/null
+++ b/arch/mips/include/asm/asm.h
@@ -0,0 +1,409 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
+ * Copyright (C) 1999 by Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ *
+ * Some useful macros for MIPS assembler code
+ *
+ * Some of the routines below contain useless nops that will be optimized
+ * away by gas in -O mode. These nops are however required to fill delay
+ * slots in noreorder mode.
+ */
+#ifndef __ASM_ASM_H
+#define __ASM_ASM_H
+
+#include <asm/sgidefs.h>
+
+#ifndef CAT
+#ifdef __STDC__
+#define __CAT(str1, str2) str1##str2
+#else
+#define __CAT(str1, str2) str1/**/str2
+#endif
+#define CAT(str1, str2) __CAT(str1, str2)
+#endif
+
+/*
+ * PIC specific declarations
+ * Not used for the kernel but here seems to be the right place.
+ */
+#ifdef __PIC__
+#define CPRESTORE(register)                             \
+                .cprestore register
+#define CPADD(register)                                 \
+                .cpadd  register
+#define CPLOAD(register)                                \
+                .cpload register
+#else
+#define CPRESTORE(register)
+#define CPADD(register)
+#define CPLOAD(register)
+#endif
+
+/*
+ * LEAF - declare leaf routine
+ */
+#define LEAF(symbol)                                    \
+                .globl  symbol;                         \
+                .align  2;                              \
+                .type   symbol, @function;              \
+                .ent    symbol, 0;                      \
+symbol:         .frame  sp, 0, ra
+
+/*
+ * NESTED - declare nested routine entry point
+ */
+#define NESTED(symbol, framesize, rpc)                  \
+                .globl  symbol;                         \
+                .align  2;                              \
+                .type   symbol, @function;              \
+                .ent    symbol, 0;                       \
+symbol:         .frame  sp, framesize, rpc
+
+/*
+ * END - mark end of function
+ */
+#define END(function)                                   \
+                .end    function;                       \
+                .size   function, .-function
+
+/*
+ * EXPORT - export definition of symbol
+ */
+#define EXPORT(symbol)                                  \
+                .globl  symbol;                         \
+symbol:
+
+/*
+ * FEXPORT - export definition of a function symbol
+ */
+#define FEXPORT(symbol)                                 \
+                .globl  symbol;                         \
+                .type   symbol, @function;              \
+symbol:
+
+/*
+ * ABS - export absolute symbol
+ */
+#define ABS(symbol,value)                               \
+                .globl  symbol;                         \
+symbol          =       value
+
+#define PANIC(msg)                                      \
+                .set    push;                           \
+                .set    reorder;                        \
+                PTR_LA  a0, 8f;                          \
+                jal     panic;                          \
+9:              b       9b;                             \
+                .set    pop;                            \
+                TEXT(msg)
+
+/*
+ * Print formatted string
+ */
+#ifdef CONFIG_PRINTK
+#define PRINT(string)                                   \
+                .set    push;                           \
+                .set    reorder;                        \
+                PTR_LA  a0, 8f;                          \
+                jal     printk;                         \
+                .set    pop;                            \
+                TEXT(string)
+#else
+#define PRINT(string)
+#endif
+
+#define TEXT(msg)                                       \
+                .pushsection .data;                     \
+8:              .asciiz msg;                            \
+                .popsection;
+
+/*
+ * Build text tables
+ */
+#define TTABLE(string)                                  \
+                .pushsection .text;                     \
+                .word   1f;                             \
+                .popsection                             \
+                .pushsection .data;                     \
+1:              .asciiz string;                         \
+                .popsection
+
+/*
+ * MIPS IV pref instruction.
+ * Use with .set noreorder only!
+ *
+ * MIPS IV implementations are free to treat this as a nop.  The R5000
+ * is one of them.  So we should have an option not to use this instruction.
+ */
+#ifdef CONFIG_CPU_HAS_PREFETCH
+
+#define PREF(hint,addr)                                 \
+                .set    push;                           \
+                .set    mips4;                          \
+                pref    hint, addr;                     \
+                .set    pop
+
+#define PREFX(hint,addr)                                \
+                .set    push;                           \
+                .set    mips4;                          \
+                prefx   hint, addr;                     \
+                .set    pop
+
+#else /* !CONFIG_CPU_HAS_PREFETCH */
+
+#define PREF(hint, addr)
+#define PREFX(hint, addr)
+
+#endif /* !CONFIG_CPU_HAS_PREFETCH */
+
+/*
+ * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
+ */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
+#define MOVN(rd, rs, rt)                                \
+                .set    push;                           \
+                .set    reorder;                        \
+                beqz    rt, 9f;                         \
+                move    rd, rs;                         \
+                .set    pop;                            \
+9:
+#define MOVZ(rd, rs, rt)                                \
+                .set    push;                           \
+                .set    reorder;                        \
+                bnez    rt, 9f;                         \
+                move    rd, rs;                         \
+                .set    pop;                            \
+9:
+#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
+#define MOVN(rd, rs, rt)                                \
+                .set    push;                           \
+                .set    noreorder;                      \
+                bnezl   rt, 9f;                         \
+                 move   rd, rs;                         \
+                .set    pop;                            \
+9:
+#define MOVZ(rd, rs, rt)                                \
+                .set    push;                           \
+                .set    noreorder;                      \
+                beqzl   rt, 9f;                         \
+                 move   rd, rs;                         \
+                .set    pop;                            \
+9:
+#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
+    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+#define MOVN(rd, rs, rt)                                \
+                movn    rd, rs, rt
+#define MOVZ(rd, rs, rt)                                \
+                movz    rd, rs, rt
+#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
+
+/*
+ * Stack alignment
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define ALSZ    7
+#define ALMASK  ~7
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define ALSZ    15
+#define ALMASK  ~15
+#endif
+
+/*
+ * Macros to handle different pointer/register sizes for 32/64-bit code
+ */
+
+/*
+ * Size of a register
+ */
+#ifdef __mips64
+#define SZREG   8
+#else
+#define SZREG   4
+#endif
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define REG_S           sw
+#define REG_L           lw
+#define REG_SUBU        subu
+#define REG_ADDU        addu
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define REG_S           sd
+#define REG_L           ld
+#define REG_SUBU        dsubu
+#define REG_ADDU        daddu
+#endif
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#if (_MIPS_SZINT == 32)
+#define INT_ADD         add
+#define INT_ADDU        addu
+#define INT_ADDI        addi
+#define INT_ADDIU       addiu
+#define INT_SUB         sub
+#define INT_SUBU        subu
+#define INT_L           lw
+#define INT_S           sw
+#define INT_SLL         sll
+#define INT_SLLV        sllv
+#define INT_SRL         srl
+#define INT_SRLV        srlv
+#define INT_SRA         sra
+#define INT_SRAV        srav
+#endif
+
+#if (_MIPS_SZINT == 64)
+#define INT_ADD         dadd
+#define INT_ADDU        daddu
+#define INT_ADDI        daddi
+#define INT_ADDIU       daddiu
+#define INT_SUB         dsub
+#define INT_SUBU        dsubu
+#define INT_L           ld
+#define INT_S           sd
+#define INT_SLL         dsll
+#define INT_SLLV        dsllv
+#define INT_SRL         dsrl
+#define INT_SRLV        dsrlv
+#define INT_SRA         dsra
+#define INT_SRAV        dsrav
+#endif
+
+/*
+ * How to add/sub/load/store/shift C long variables.
+ */
+#if (_MIPS_SZLONG == 32)
+#define LONG_ADD        add
+#define LONG_ADDU       addu
+#define LONG_ADDI       addi
+#define LONG_ADDIU      addiu
+#define LONG_SUB        sub
+#define LONG_SUBU       subu
+#define LONG_L          lw
+#define LONG_S          sw
+#define LONG_SLL        sll
+#define LONG_SLLV       sllv
+#define LONG_SRL        srl
+#define LONG_SRLV       srlv
+#define LONG_SRA        sra
+#define LONG_SRAV       srav
+
+#define LONG            .word
+#define LONGSIZE        4
+#define LONGMASK        3
+#define LONGLOG         2
+#endif
+
+#if (_MIPS_SZLONG == 64)
+#define LONG_ADD        dadd
+#define LONG_ADDU       daddu
+#define LONG_ADDI       daddi
+#define LONG_ADDIU      daddiu
+#define LONG_SUB        dsub
+#define LONG_SUBU       dsubu
+#define LONG_L          ld
+#define LONG_S          sd
+#define LONG_SLL        dsll
+#define LONG_SLLV       dsllv
+#define LONG_SRL        dsrl
+#define LONG_SRLV       dsrlv
+#define LONG_SRA        dsra
+#define LONG_SRAV       dsrav
+
+#define LONG            .dword
+#define LONGSIZE        8
+#define LONGMASK        7
+#define LONGLOG         3
+#endif
+
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#if (_MIPS_SZPTR == 32)
+#define PTR_ADD         add
+#define PTR_ADDU        addu
+#define PTR_ADDI        addi
+#define PTR_ADDIU       addiu
+#define PTR_SUB         sub
+#define PTR_SUBU        subu
+#define PTR_L           lw
+#define PTR_S           sw
+#define PTR_LA          la
+#define PTR_LI          li
+#define PTR_SLL         sll
+#define PTR_SLLV        sllv
+#define PTR_SRL         srl
+#define PTR_SRLV        srlv
+#define PTR_SRA         sra
+#define PTR_SRAV        srav
+
+#define PTR_SCALESHIFT  2
+
+#define PTR             .word
+#define PTRSIZE         4
+#define PTRLOG          2
+#endif
+
+#if (_MIPS_SZPTR == 64)
+#define PTR_ADD         dadd
+#define PTR_ADDU        daddu
+#define PTR_ADDI        daddi
+#define PTR_ADDIU       daddiu
+#define PTR_SUB         dsub
+#define PTR_SUBU        dsubu
+#define PTR_L           ld
+#define PTR_S           sd
+#define PTR_LA          dla
+#define PTR_LI          dli
+#define PTR_SLL         dsll
+#define PTR_SLLV        dsllv
+#define PTR_SRL         dsrl
+#define PTR_SRLV        dsrlv
+#define PTR_SRA         dsra
+#define PTR_SRAV        dsrav
+
+#define PTR_SCALESHIFT  3
+
+#define PTR             .dword
+#define PTRSIZE         8
+#define PTRLOG          3
+#endif
+
+/*
+ * Some cp0 registers were extended to 64bit for MIPS III.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define MFC0            mfc0
+#define MTC0            mtc0
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define MFC0            dmfc0
+#define MTC0            dmtc0
+#endif
+
+#define SSNOP           sll zero, zero, 1
+
+#ifdef CONFIG_SGI_IP28
+/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
+#include <asm/cacheops.h>
+#define R10KCBARRIER(addr)  cache   Cache_Barrier, addr;
+#else
+#define R10KCBARRIER(addr)
+#endif
+
+#endif /* __ASM_ASM_H */
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
new file mode 100644
index 000000000000..5de3963f511e
--- /dev/null
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -0,0 +1,158 @@
+/*
+ * asmmacro.h: Assembler macros to make things easier to read.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1998, 1999, 2003 Ralf Baechle
+ */
+#ifndef _ASM_ASMMACRO_32_H
+#define _ASM_ASMMACRO_32_H
+
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/fpregdef.h>
+#include <asm/mipsregs.h>
+
+        .macro  fpu_save_double thread status tmp1=t0
+        cfc1    \tmp1,  fcr31
+        sdc1    $f0,  THREAD_FPR0(\thread)
+        sdc1    $f2,  THREAD_FPR2(\thread)
+        sdc1    $f4,  THREAD_FPR4(\thread)
+        sdc1    $f6,  THREAD_FPR6(\thread)
+        sdc1    $f8,  THREAD_FPR8(\thread)
+        sdc1    $f10, THREAD_FPR10(\thread)
+        sdc1    $f12, THREAD_FPR12(\thread)
+        sdc1    $f14, THREAD_FPR14(\thread)
+        sdc1    $f16, THREAD_FPR16(\thread)
+        sdc1    $f18, THREAD_FPR18(\thread)
+        sdc1    $f20, THREAD_FPR20(\thread)
+        sdc1    $f22, THREAD_FPR22(\thread)
+        sdc1    $f24, THREAD_FPR24(\thread)
+        sdc1    $f26, THREAD_FPR26(\thread)
+        sdc1    $f28, THREAD_FPR28(\thread)
+        sdc1    $f30, THREAD_FPR30(\thread)
+        sw      \tmp1, THREAD_FCR31(\thread)
+        .endm
+
+        .macro  fpu_save_single thread tmp=t0
+        cfc1    \tmp,  fcr31
+        swc1    $f0,  THREAD_FPR0(\thread)
+        swc1    $f1,  THREAD_FPR1(\thread)
+        swc1    $f2,  THREAD_FPR2(\thread)
+        swc1    $f3,  THREAD_FPR3(\thread)
+        swc1    $f4,  THREAD_FPR4(\thread)
+        swc1    $f5,  THREAD_FPR5(\thread)
+        swc1    $f6,  THREAD_FPR6(\thread)
+        swc1    $f7,  THREAD_FPR7(\thread)
+        swc1    $f8,  THREAD_FPR8(\thread)
+        swc1    $f9,  THREAD_FPR9(\thread)
+        swc1    $f10, THREAD_FPR10(\thread)
+        swc1    $f11, THREAD_FPR11(\thread)
+        swc1    $f12, THREAD_FPR12(\thread)
+        swc1    $f13, THREAD_FPR13(\thread)
+        swc1    $f14, THREAD_FPR14(\thread)
+        swc1    $f15, THREAD_FPR15(\thread)
+        swc1    $f16, THREAD_FPR16(\thread)
+        swc1    $f17, THREAD_FPR17(\thread)
+        swc1    $f18, THREAD_FPR18(\thread)
+        swc1    $f19, THREAD_FPR19(\thread)
+        swc1    $f20, THREAD_FPR20(\thread)
+        swc1    $f21, THREAD_FPR21(\thread)
+        swc1    $f22, THREAD_FPR22(\thread)
+        swc1    $f23, THREAD_FPR23(\thread)
+        swc1    $f24, THREAD_FPR24(\thread)
+        swc1    $f25, THREAD_FPR25(\thread)
+        swc1    $f26, THREAD_FPR26(\thread)
+        swc1    $f27, THREAD_FPR27(\thread)
+        swc1    $f28, THREAD_FPR28(\thread)
+        swc1    $f29, THREAD_FPR29(\thread)
+        swc1    $f30, THREAD_FPR30(\thread)
+        swc1    $f31, THREAD_FPR31(\thread)
+        sw      \tmp, THREAD_FCR31(\thread)
+        .endm
+
+        .macro  fpu_restore_double thread status tmp=t0
+        lw      \tmp, THREAD_FCR31(\thread)
+        ldc1    $f0,  THREAD_FPR0(\thread)
+        ldc1    $f2,  THREAD_FPR2(\thread)
+        ldc1    $f4,  THREAD_FPR4(\thread)
+        ldc1    $f6,  THREAD_FPR6(\thread)
+        ldc1    $f8,  THREAD_FPR8(\thread)
+        ldc1    $f10, THREAD_FPR10(\thread)
+        ldc1    $f12, THREAD_FPR12(\thread)
+        ldc1    $f14, THREAD_FPR14(\thread)
+        ldc1    $f16, THREAD_FPR16(\thread)
+        ldc1    $f18, THREAD_FPR18(\thread)
+        ldc1    $f20, THREAD_FPR20(\thread)
+        ldc1    $f22, THREAD_FPR22(\thread)
+        ldc1    $f24, THREAD_FPR24(\thread)
+        ldc1    $f26, THREAD_FPR26(\thread)
+        ldc1    $f28, THREAD_FPR28(\thread)
+        ldc1    $f30, THREAD_FPR30(\thread)
+        ctc1    \tmp, fcr31
+        .endm
+
+        .macro  fpu_restore_single thread tmp=t0
+        lw      \tmp, THREAD_FCR31(\thread)
+        lwc1    $f0,  THREAD_FPR0(\thread)
+        lwc1    $f1,  THREAD_FPR1(\thread)
+        lwc1    $f2,  THREAD_FPR2(\thread)
+        lwc1    $f3,  THREAD_FPR3(\thread)
+        lwc1    $f4,  THREAD_FPR4(\thread)
+        lwc1    $f5,  THREAD_FPR5(\thread)
+        lwc1    $f6,  THREAD_FPR6(\thread)
+        lwc1    $f7,  THREAD_FPR7(\thread)
+        lwc1    $f8,  THREAD_FPR8(\thread)
+        lwc1    $f9,  THREAD_FPR9(\thread)
+        lwc1    $f10, THREAD_FPR10(\thread)
+        lwc1    $f11, THREAD_FPR11(\thread)
+        lwc1    $f12, THREAD_FPR12(\thread)
+        lwc1    $f13, THREAD_FPR13(\thread)
+        lwc1    $f14, THREAD_FPR14(\thread)
+        lwc1    $f15, THREAD_FPR15(\thread)
+        lwc1    $f16, THREAD_FPR16(\thread)
+        lwc1    $f17, THREAD_FPR17(\thread)
+        lwc1    $f18, THREAD_FPR18(\thread)
+        lwc1    $f19, THREAD_FPR19(\thread)
+        lwc1    $f20, THREAD_FPR20(\thread)
+        lwc1    $f21, THREAD_FPR21(\thread)
+        lwc1    $f22, THREAD_FPR22(\thread)
+        lwc1    $f23, THREAD_FPR23(\thread)
+        lwc1    $f24, THREAD_FPR24(\thread)
+        lwc1    $f25, THREAD_FPR25(\thread)
+        lwc1    $f26, THREAD_FPR26(\thread)
+        lwc1    $f27, THREAD_FPR27(\thread)
+        lwc1    $f28, THREAD_FPR28(\thread)
+        lwc1    $f29, THREAD_FPR29(\thread)
+        lwc1    $f30, THREAD_FPR30(\thread)
+        lwc1    $f31, THREAD_FPR31(\thread)
+        ctc1    \tmp, fcr31
+        .endm
+
+        .macro  cpu_save_nonscratch thread
+        LONG_S  s0, THREAD_REG16(\thread)
+        LONG_S  s1, THREAD_REG17(\thread)
+        LONG_S  s2, THREAD_REG18(\thread)
+        LONG_S  s3, THREAD_REG19(\thread)
+        LONG_S  s4, THREAD_REG20(\thread)
+        LONG_S  s5, THREAD_REG21(\thread)
+        LONG_S  s6, THREAD_REG22(\thread)
+        LONG_S  s7, THREAD_REG23(\thread)
+        LONG_S  sp, THREAD_REG29(\thread)
+        LONG_S  fp, THREAD_REG30(\thread)
+        .endm
+
+        .macro  cpu_restore_nonscratch thread
+        LONG_L  s0, THREAD_REG16(\thread)
+        LONG_L  s1, THREAD_REG17(\thread)
+        LONG_L  s2, THREAD_REG18(\thread)
+        LONG_L  s3, THREAD_REG19(\thread)
+        LONG_L  s4, THREAD_REG20(\thread)
+        LONG_L  s5, THREAD_REG21(\thread)
+        LONG_L  s6, THREAD_REG22(\thread)
+        LONG_L  s7, THREAD_REG23(\thread)
+        LONG_L  sp, THREAD_REG29(\thread)
+        LONG_L  fp, THREAD_REG30(\thread)
+        LONG_L  ra, THREAD_REG31(\thread)
+        .endm
+
+#endif /* _ASM_ASMMACRO_32_H */
diff --git a/arch/mips/include/asm/asmmacro-64.h b/arch/mips/include/asm/asmmacro-64.h
new file mode 100644
index 000000000000..225feefcb25d
--- /dev/null
+++ b/arch/mips/include/asm/asmmacro-64.h
@@ -0,0 +1,139 @@
+/*
+ * asmmacro.h: Assembler macros to make things easier to read.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1998, 1999 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ASMMACRO_64_H
+#define _ASM_ASMMACRO_64_H
+
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/fpregdef.h>
+#include <asm/mipsregs.h>
+
+        .macro  fpu_save_16even thread tmp=t0
+        cfc1    \tmp, fcr31
+        sdc1    $f0,  THREAD_FPR0(\thread)
+        sdc1    $f2,  THREAD_FPR2(\thread)
+        sdc1    $f4,  THREAD_FPR4(\thread)
+        sdc1    $f6,  THREAD_FPR6(\thread)
+        sdc1    $f8,  THREAD_FPR8(\thread)
+        sdc1    $f10, THREAD_FPR10(\thread)
+        sdc1    $f12, THREAD_FPR12(\thread)
+        sdc1    $f14, THREAD_FPR14(\thread)
+        sdc1    $f16, THREAD_FPR16(\thread)
+        sdc1    $f18, THREAD_FPR18(\thread)
+        sdc1    $f20, THREAD_FPR20(\thread)
+        sdc1    $f22, THREAD_FPR22(\thread)
+        sdc1    $f24, THREAD_FPR24(\thread)
+        sdc1    $f26, THREAD_FPR26(\thread)
+        sdc1    $f28, THREAD_FPR28(\thread)
+        sdc1    $f30, THREAD_FPR30(\thread)
+        sw      \tmp, THREAD_FCR31(\thread)
+        .endm
+
+        .macro  fpu_save_16odd thread
+        sdc1    $f1,  THREAD_FPR1(\thread)
+        sdc1    $f3,  THREAD_FPR3(\thread)
+        sdc1    $f5,  THREAD_FPR5(\thread)
+        sdc1    $f7,  THREAD_FPR7(\thread)
+        sdc1    $f9,  THREAD_FPR9(\thread)
+        sdc1    $f11, THREAD_FPR11(\thread)
+        sdc1    $f13, THREAD_FPR13(\thread)
+        sdc1    $f15, THREAD_FPR15(\thread)
+        sdc1    $f17, THREAD_FPR17(\thread)
+        sdc1    $f19, THREAD_FPR19(\thread)
+        sdc1    $f21, THREAD_FPR21(\thread)
+        sdc1    $f23, THREAD_FPR23(\thread)
+        sdc1    $f25, THREAD_FPR25(\thread)
+        sdc1    $f27, THREAD_FPR27(\thread)
+        sdc1    $f29, THREAD_FPR29(\thread)
+        sdc1    $f31, THREAD_FPR31(\thread)
+        .endm
+
+        .macro  fpu_save_double thread status tmp
+        sll     \tmp, \status, 5
+        bgez    \tmp, 2f
+        fpu_save_16odd \thread
+2:
+        fpu_save_16even \thread \tmp
+        .endm
+
+        .macro  fpu_restore_16even thread tmp=t0
+        lw      \tmp, THREAD_FCR31(\thread)
+        ldc1    $f0,  THREAD_FPR0(\thread)
+        ldc1    $f2,  THREAD_FPR2(\thread)
+        ldc1    $f4,  THREAD_FPR4(\thread)
+        ldc1    $f6,  THREAD_FPR6(\thread)
+        ldc1    $f8,  THREAD_FPR8(\thread)
+        ldc1    $f10, THREAD_FPR10(\thread)
+        ldc1    $f12, THREAD_FPR12(\thread)
+        ldc1    $f14, THREAD_FPR14(\thread)
+        ldc1    $f16, THREAD_FPR16(\thread)
+        ldc1    $f18, THREAD_FPR18(\thread)
+        ldc1    $f20, THREAD_FPR20(\thread)
+        ldc1    $f22, THREAD_FPR22(\thread)
+        ldc1    $f24, THREAD_FPR24(\thread)
+        ldc1    $f26, THREAD_FPR26(\thread)
+        ldc1    $f28, THREAD_FPR28(\thread)
+        ldc1    $f30, THREAD_FPR30(\thread)
+        ctc1    \tmp, fcr31
+        .endm
+
+        .macro  fpu_restore_16odd thread
+        ldc1    $f1,  THREAD_FPR1(\thread)
+        ldc1    $f3,  THREAD_FPR3(\thread)
+        ldc1    $f5,  THREAD_FPR5(\thread)
+        ldc1    $f7,  THREAD_FPR7(\thread)
+        ldc1    $f9,  THREAD_FPR9(\thread)
+        ldc1    $f11, THREAD_FPR11(\thread)
+        ldc1    $f13, THREAD_FPR13(\thread)
+        ldc1    $f15, THREAD_FPR15(\thread)
+        ldc1    $f17, THREAD_FPR17(\thread)
+        ldc1    $f19, THREAD_FPR19(\thread)
+        ldc1    $f21, THREAD_FPR21(\thread)
+        ldc1    $f23, THREAD_FPR23(\thread)
+        ldc1    $f25, THREAD_FPR25(\thread)
+        ldc1    $f27, THREAD_FPR27(\thread)
+        ldc1    $f29, THREAD_FPR29(\thread)
+        ldc1    $f31, THREAD_FPR31(\thread)
+        .endm
+
+        .macro  fpu_restore_double thread status tmp
+        sll     \tmp, \status, 5
+        bgez    \tmp, 1f                                # 16 register mode?
+
+        fpu_restore_16odd \thread
+1:      fpu_restore_16even \thread \tmp
+        .endm
+
+        .macro  cpu_save_nonscratch thread
+        LONG_S  s0, THREAD_REG16(\thread)
+        LONG_S  s1, THREAD_REG17(\thread)
+        LONG_S  s2, THREAD_REG18(\thread)
+        LONG_S  s3, THREAD_REG19(\thread)
+        LONG_S  s4, THREAD_REG20(\thread)
+        LONG_S  s5, THREAD_REG21(\thread)
+        LONG_S  s6, THREAD_REG22(\thread)
+        LONG_S  s7, THREAD_REG23(\thread)
+        LONG_S  sp, THREAD_REG29(\thread)
+        LONG_S  fp, THREAD_REG30(\thread)
+        .endm
+
+        .macro  cpu_restore_nonscratch thread
+        LONG_L  s0, THREAD_REG16(\thread)
+        LONG_L  s1, THREAD_REG17(\thread)
+        LONG_L  s2, THREAD_REG18(\thread)
+        LONG_L  s3, THREAD_REG19(\thread)
+        LONG_L  s4, THREAD_REG20(\thread)
+        LONG_L  s5, THREAD_REG21(\thread)
+        LONG_L  s6, THREAD_REG22(\thread)
+        LONG_L  s7, THREAD_REG23(\thread)
+        LONG_L  sp, THREAD_REG29(\thread)
+        LONG_L  fp, THREAD_REG30(\thread)
+        LONG_L  ra, THREAD_REG31(\thread)
+        .endm
+
+#endif /* _ASM_ASMMACRO_64_H */
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
new file mode 100644
index 000000000000..7a881755800f
--- /dev/null
+++ b/arch/mips/include/asm/asmmacro.h
@@ -0,0 +1,82 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef _ASM_ASMMACRO_H
+#define _ASM_ASMMACRO_H
+
+#include <asm/hazards.h>
+
+#ifdef CONFIG_32BIT
+#include <asm/asmmacro-32.h>
+#endif
+#ifdef CONFIG_64BIT
+#include <asm/asmmacro-64.h>
+#endif
+#ifdef CONFIG_MIPS_MT_SMTC
+#include <asm/mipsmtregs.h>
+#endif
+
+#ifdef CONFIG_MIPS_MT_SMTC
+        .macro  local_irq_enable reg=t0
+        mfc0    \reg, CP0_TCSTATUS
+        ori     \reg, \reg, TCSTATUS_IXMT
+        xori    \reg, \reg, TCSTATUS_IXMT
+        mtc0    \reg, CP0_TCSTATUS
+        _ehb
+        .endm
+
+        .macro  local_irq_disable reg=t0
+        mfc0    \reg, CP0_TCSTATUS
+        ori     \reg, \reg, TCSTATUS_IXMT
+        mtc0    \reg, CP0_TCSTATUS
+        _ehb
+        .endm
+#else
+        .macro  local_irq_enable reg=t0
+        mfc0    \reg, CP0_STATUS
+        ori     \reg, \reg, 1
+        mtc0    \reg, CP0_STATUS
+        irq_enable_hazard
+        .endm
+
+        .macro  local_irq_disable reg=t0
+        mfc0    \reg, CP0_STATUS
+        ori     \reg, \reg, 1
+        xori    \reg, \reg, 1
+        mtc0    \reg, CP0_STATUS
+        irq_disable_hazard
+        .endm
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+/*
+ * Temporary until all gas have MT ASE support
+ */
+        .macro  DMT     reg=0
+        .word   0x41600bc1 | (\reg << 16)
+        .endm
+
+        .macro  EMT     reg=0
+        .word   0x41600be1 | (\reg << 16)
+        .endm
+
+        .macro  DVPE    reg=0
+        .word   0x41600001 | (\reg << 16)
+        .endm
+
+        .macro  EVPE    reg=0
+        .word   0x41600021 | (\reg << 16)
+        .endm
+
+        .macro  MFTR    rt=0, rd=0, u=0, sel=0
+         .word  0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
+        .endm
+
+        .macro  MTTR    rt=0, rd=0, u=0, sel=0
+         .word  0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
+        .endm
+
+#endif /* _ASM_ASMMACRO_H */
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
new file mode 100644
index 000000000000..1232be3885b0
--- /dev/null
+++ b/arch/mips/include/asm/atomic.h
@@ -0,0 +1,801 @@
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ *
+ * But use these as seldom as possible since they are much more slower
+ * than regular operations.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
+ */
+#ifndef _ASM_ATOMIC_H
+#define _ASM_ATOMIC_H
+
+#include <linux/irqflags.h>
+#include <asm/barrier.h>
+#include <asm/cpu-features.h>
+#include <asm/war.h>
+#include <asm/system.h>
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i)    { (i) }
+
+/*
+ * atomic_read - read atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically reads the value of @v.
+ */
+#define atomic_read(v)          ((v)->counter)
+
+/*
+ * atomic_set - set atomic variable
+ * @v: pointer of type atomic_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+#define atomic_set(v, i)                ((v)->counter = (i))
+
+/*
+ * atomic_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v.
+ */
+static __inline__ void atomic_add(int i, atomic_t * v)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %1          # atomic_add            \n"
+                "       addu    %0, %2                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %1          # atomic_add            \n"
+                "       addu    %0, %2                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                v->counter += i;
+                raw_local_irq_restore(flags);
+        }
+}
+
+/*
+ * atomic_sub - subtract the atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static __inline__ void atomic_sub(int i, atomic_t * v)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %1          # atomic_sub            \n"
+                "       subu    %0, %2                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %1          # atomic_sub            \n"
+                "       subu    %0, %2                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                v->counter -= i;
+                raw_local_irq_restore(flags);
+        }
+}
+
+/*
+ * Same as above, but return the result value
+ */
+static __inline__ int atomic_add_return(int i, atomic_t * v)
+{
+        unsigned long result;
+
+        smp_llsc_mb();
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %1, %2          # atomic_add_return     \n"
+                "       addu    %0, %1, %3                              \n"
+                "       sc      %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %1, %2          # atomic_add_return     \n"
+                "       addu    %0, %1, %3                              \n"
+                "       sc      %0, %2                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                result = v->counter;
+                result += i;
+                v->counter = result;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return result;
+}
+
+static __inline__ int atomic_sub_return(int i, atomic_t * v)
+{
+        unsigned long result;
+
+        smp_llsc_mb();
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %1, %2          # atomic_sub_return     \n"
+                "       subu    %0, %1, %3                              \n"
+                "       sc      %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %1, %2          # atomic_sub_return     \n"
+                "       subu    %0, %1, %3                              \n"
+                "       sc      %0, %2                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                result = v->counter;
+                result -= i;
+                v->counter = result;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return result;
+}
+
+/*
+ * atomic_sub_if_positive - conditionally subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically test @v and subtract @i if @v is greater or equal than @i.
+ * The function returns the old value of @v minus @i.
+ */
+static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
+{
+        unsigned long result;
+
+        smp_llsc_mb();
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
+                "       subu    %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                "       sc      %0, %2                                  \n"
+                "       .set    noreorder                               \n"
+                "       beqzl   %0, 1b                                  \n"
+                "        subu   %0, %1, %3                              \n"
+                "       .set    reorder                                 \n"
+                "1:                                                     \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
+                "       subu    %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                "       sc      %0, %2                                  \n"
+                "       .set    noreorder                               \n"
+                "       beqz    %0, 2f                                  \n"
+                "        subu   %0, %1, %3                              \n"
+                "       .set    reorder                                 \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "1:                                                     \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                result = v->counter;
+                result -= i;
+                if (result >= 0)
+                        v->counter = result;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return result;
+}
+
+#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
+
+/**
+ * atomic_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+#define atomic_dec_return(v) atomic_sub_return(1, (v))
+#define atomic_inc_return(v) atomic_add_return(1, (v))
+
+/*
+ * atomic_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+/*
+ * atomic_dec_and_test - decrement by 1 and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
+
+/*
+ * atomic_dec_if_positive - decrement by 1 if old value positive
+ * @v: pointer of type atomic_t
+ */
+#define atomic_dec_if_positive(v)       atomic_sub_if_positive(1, v)
+
+/*
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+#define atomic_inc(v) atomic_add(1, (v))
+
+/*
+ * atomic_dec - decrement and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1.
+ */
+#define atomic_dec(v) atomic_sub(1, (v))
+
+/*
+ * atomic_add_negative - add and test if negative
+ * @v: pointer of type atomic_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @v and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0)
+
+#ifdef CONFIG_64BIT
+
+typedef struct { volatile long counter; } atomic64_t;
+
+#define ATOMIC64_INIT(i)    { (i) }
+
+/*
+ * atomic64_read - read atomic variable
+ * @v: pointer of type atomic64_t
+ *
+ */
+#define atomic64_read(v)        ((v)->counter)
+
+/*
+ * atomic64_set - set atomic variable
+ * @v: pointer of type atomic64_t
+ * @i: required value
+ */
+#define atomic64_set(v, i)      ((v)->counter = (i))
+
+/*
+ * atomic64_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically adds @i to @v.
+ */
+static __inline__ void atomic64_add(long i, atomic64_t * v)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %0, %1          # atomic64_add          \n"
+                "       addu    %0, %2                                  \n"
+                "       scd     %0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %0, %1          # atomic64_add          \n"
+                "       addu    %0, %2                                  \n"
+                "       scd     %0, %1                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                v->counter += i;
+                raw_local_irq_restore(flags);
+        }
+}
+
+/*
+ * atomic64_sub - subtract the atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static __inline__ void atomic64_sub(long i, atomic64_t * v)
+{
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %0, %1          # atomic64_sub          \n"
+                "       subu    %0, %2                                  \n"
+                "       scd     %0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %0, %1          # atomic64_sub          \n"
+                "       subu    %0, %2                                  \n"
+                "       scd     %0, %1                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter));
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                v->counter -= i;
+                raw_local_irq_restore(flags);
+        }
+}
+
+/*
+ * Same as above, but return the result value
+ */
+static __inline__ long atomic64_add_return(long i, atomic64_t * v)
+{
+        unsigned long result;
+
+        smp_llsc_mb();
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %1, %2          # atomic64_add_return   \n"
+                "       addu    %0, %1, %3                              \n"
+                "       scd     %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %1, %2          # atomic64_add_return   \n"
+                "       addu    %0, %1, %3                              \n"
+                "       scd     %0, %2                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                result = v->counter;
+                result += i;
+                v->counter = result;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return result;
+}
+
+static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
+{
+        unsigned long result;
+
+        smp_llsc_mb();
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %1, %2          # atomic64_sub_return   \n"
+                "       subu    %0, %1, %3                              \n"
+                "       scd     %0, %2                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %1, %2          # atomic64_sub_return   \n"
+                "       subu    %0, %1, %3                              \n"
+                "       scd     %0, %2                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                result = v->counter;
+                result -= i;
+                v->counter = result;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return result;
+}
+
+/*
+ * atomic64_sub_if_positive - conditionally subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically test @v and subtract @i if @v is greater or equal than @i.
+ * The function returns the old value of @v minus @i.
+ */
+static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
+{
+        unsigned long result;
+
+        smp_llsc_mb();
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
+                "       dsubu   %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                "       scd     %0, %2                                  \n"
+                "       .set    noreorder                               \n"
+                "       beqzl   %0, 1b                                  \n"
+                "        dsubu  %0, %1, %3                              \n"
+                "       .set    reorder                                 \n"
+                "1:                                                     \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
+                "       dsubu   %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                "       scd     %0, %2                                  \n"
+                "       .set    noreorder                               \n"
+                "       beqz    %0, 2f                                  \n"
+                "        dsubu  %0, %1, %3                              \n"
+                "       .set    reorder                                 \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "1:                                                     \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                : "Ir" (i), "m" (v->counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                result = v->counter;
+                result -= i;
+                if (result >= 0)
+                        v->counter = result;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return result;
+}
+
+#define atomic64_cmpxchg(v, o, n) \
+        ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
+
+/**
+ * atomic64_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic64_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
+#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
+#define atomic64_inc_return(v) atomic64_add_return(1, (v))
+
+/*
+ * atomic64_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
+
+/*
+ * atomic64_inc_and_test - increment and test
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
+
+/*
+ * atomic64_dec_and_test - decrement by 1 and test
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically decrements @v by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
+
+/*
+ * atomic64_dec_if_positive - decrement by 1 if old value positive
+ * @v: pointer of type atomic64_t
+ */
+#define atomic64_dec_if_positive(v)     atomic64_sub_if_positive(1, v)
+
+/*
+ * atomic64_inc - increment atomic variable
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically increments @v by 1.
+ */
+#define atomic64_inc(v) atomic64_add(1, (v))
+
+/*
+ * atomic64_dec - decrement and test
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically decrements @v by 1.
+ */
+#define atomic64_dec(v) atomic64_sub(1, (v))
+
+/*
+ * atomic64_add_negative - add and test if negative
+ * @v: pointer of type atomic64_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @v and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0)
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * atomic*_return operations are serializing but not the non-*_return
+ * versions.
+ */
+#define smp_mb__before_atomic_dec()     smp_llsc_mb()
+#define smp_mb__after_atomic_dec()      smp_llsc_mb()
+#define smp_mb__before_atomic_inc()     smp_llsc_mb()
+#define smp_mb__after_atomic_inc()      smp_llsc_mb()
+
+#include <asm-generic/atomic.h>
+
+#endif /* _ASM_ATOMIC_H */
diff --git a/arch/mips/include/asm/auxvec.h b/arch/mips/include/asm/auxvec.h
new file mode 100644
index 000000000000..7cf7f2d21943
--- /dev/null
+++ b/arch/mips/include/asm/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_AUXVEC_H
+#define _ASM_AUXVEC_H
+
+#endif /* _ASM_AUXVEC_H */
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
new file mode 100644
index 000000000000..8e9ac313ca3b
--- /dev/null
+++ b/arch/mips/include/asm/barrier.h
@@ -0,0 +1,155 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_BARRIER_H
+#define __ASM_BARRIER_H
+
+/*
+ * read_barrier_depends - Flush all pending reads that subsequents reads
+ * depend on.
+ *
+ * No data-dependent reads from memory-like regions are ever reordered
+ * over this barrier.  All reads preceding this primitive are guaranteed
+ * to access memory (but not necessarily other CPUs' caches) before any
+ * reads following this primitive that depend on the data return by
+ * any of the preceding reads.  This primitive is much lighter weight than
+ * rmb() on most CPUs, and is never heavier weight than is
+ * rmb().
+ *
+ * These ordering constraints are respected by both the local CPU
+ * and the compiler.
+ *
+ * Ordering is not guaranteed by anything other than these primitives,
+ * not even by data dependencies.  See the documentation for
+ * memory_barrier() for examples and URLs to more information.
+ *
+ * For example, the following code would force ordering (the initial
+ * value of "a" is zero, "b" is one, and "p" is "&a"):
+ *
+ * <programlisting>
+ *      CPU 0                           CPU 1
+ *
+ *      b = 2;
+ *      memory_barrier();
+ *      p = &b;                         q = p;
+ *                                      read_barrier_depends();
+ *                                      d = *q;
+ * </programlisting>
+ *
+ * because the read of "*q" depends on the read of "p" and these
+ * two reads are separated by a read_barrier_depends().  However,
+ * the following code, with the same initial values for "a" and "b":
+ *
+ * <programlisting>
+ *      CPU 0                           CPU 1
+ *
+ *      a = 2;
+ *      memory_barrier();
+ *      b = 3;                          y = b;
+ *                                      read_barrier_depends();
+ *                                      x = a;
+ * </programlisting>
+ *
+ * does not enforce ordering, since there is no data dependency between
+ * the read of "a" and the read of "b".  Therefore, on some CPUs, such
+ * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
+ * in cases like this where there are no data dependencies.
+ */
+
+#define read_barrier_depends()          do { } while(0)
+#define smp_read_barrier_depends()      do { } while(0)
+
+#ifdef CONFIG_CPU_HAS_SYNC
+#define __sync()                                \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                ".set   mips2\n\t"              \
+                "sync\n\t"                      \
+                ".set   pop"                    \
+                : /* no output */               \
+                : /* no input */                \
+                : "memory")
+#else
+#define __sync()        do { } while(0)
+#endif
+
+#define __fast_iob()                            \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                "lw     $0,%0\n\t"              \
+                "nop\n\t"                       \
+                ".set   pop"                    \
+                : /* no output */               \
+                : "m" (*(int *)CKSEG1)          \
+                : "memory")
+
+#define fast_wmb()      __sync()
+#define fast_rmb()      __sync()
+#define fast_mb()       __sync()
+#ifdef CONFIG_SGI_IP28
+#define fast_iob()                              \
+        __asm__ __volatile__(                   \
+                ".set   push\n\t"               \
+                ".set   noreorder\n\t"          \
+                "lw     $0,%0\n\t"              \
+                "sync\n\t"                      \
+                "lw     $0,%0\n\t"              \
+                ".set   pop"                    \
+                : /* no output */               \
+                : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
+                : "memory")
+#else
+#define fast_iob()                              \
+        do {                                    \
+                __sync();                       \
+                __fast_iob();                   \
+        } while (0)
+#endif
+
+#ifdef CONFIG_CPU_HAS_WB
+
+#include <asm/wbflush.h>
+
+#define wmb()           fast_wmb()
+#define rmb()           fast_rmb()
+#define mb()            wbflush()
+#define iob()           wbflush()
+
+#else /* !CONFIG_CPU_HAS_WB */
+
+#define wmb()           fast_wmb()
+#define rmb()           fast_rmb()
+#define mb()            fast_mb()
+#define iob()           fast_iob()
+
+#endif /* !CONFIG_CPU_HAS_WB */
+
+#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
+#define __WEAK_ORDERING_MB      "       sync    \n"
+#else
+#define __WEAK_ORDERING_MB      "               \n"
+#endif
+#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
+#define __WEAK_LLSC_MB          "       sync    \n"
+#else
+#define __WEAK_LLSC_MB          "               \n"
+#endif
+
+#define smp_mb()        __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
+#define smp_rmb()       __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
+#define smp_wmb()       __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
+
+#define set_mb(var, value) \
+        do { var = value; smp_mb(); } while (0)
+
+#define smp_llsc_mb()   __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
+#define smp_llsc_rmb()  __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
+#define smp_llsc_wmb()  __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
+
+#endif /* __ASM_BARRIER_H */
diff --git a/arch/mips/include/asm/bcache.h b/arch/mips/include/asm/bcache.h
new file mode 100644
index 000000000000..0ba9d6ef76a7
--- /dev/null
+++ b/arch/mips/include/asm/bcache.h
@@ -0,0 +1,60 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1997, 1999 by Ralf Baechle
+ * Copyright (c) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BCACHE_H
+#define _ASM_BCACHE_H
+
+
+/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
+   chipset implemented caches.  On machines with other CPUs the CPU does the
+   cache thing itself. */
+struct bcache_ops {
+        void (*bc_enable)(void);
+        void (*bc_disable)(void);
+        void (*bc_wback_inv)(unsigned long page, unsigned long size);
+        void (*bc_inv)(unsigned long page, unsigned long size);
+};
+
+extern void indy_sc_init(void);
+
+#ifdef CONFIG_BOARD_SCACHE
+
+extern struct bcache_ops *bcops;
+
+static inline void bc_enable(void)
+{
+        bcops->bc_enable();
+}
+
+static inline void bc_disable(void)
+{
+        bcops->bc_disable();
+}
+
+static inline void bc_wback_inv(unsigned long page, unsigned long size)
+{
+        bcops->bc_wback_inv(page, size);
+}
+
+static inline void bc_inv(unsigned long page, unsigned long size)
+{
+        bcops->bc_inv(page, size);
+}
+
+#else /* !defined(CONFIG_BOARD_SCACHE) */
+
+/* Not R4000 / R4400 / R4600 / R5000.  */
+
+#define bc_enable() do { } while (0)
+#define bc_disable() do { } while (0)
+#define bc_wback_inv(page, size) do { } while (0)
+#define bc_inv(page, size) do { } while (0)
+
+#endif /* !defined(CONFIG_BOARD_SCACHE) */
+
+#endif /* _ASM_BCACHE_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
new file mode 100644
index 000000000000..49df8c4c9d25
--- /dev/null
+++ b/arch/mips/include/asm/bitops.h
@@ -0,0 +1,672 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994 - 1997, 99, 2000, 06, 07  Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BITOPS_H
+#define _ASM_BITOPS_H
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <linux/compiler.h>
+#include <linux/irqflags.h>
+#include <linux/types.h>
+#include <asm/barrier.h>
+#include <asm/bug.h>
+#include <asm/byteorder.h>              /* sigh ... */
+#include <asm/cpu-features.h>
+#include <asm/sgidefs.h>
+#include <asm/war.h>
+
+#if _MIPS_SZLONG == 32
+#define SZLONG_LOG 5
+#define SZLONG_MASK 31UL
+#define __LL            "ll     "
+#define __SC            "sc     "
+#define __INS           "ins    "
+#define __EXT           "ext    "
+#elif _MIPS_SZLONG == 64
+#define SZLONG_LOG 6
+#define SZLONG_MASK 63UL
+#define __LL            "lld    "
+#define __SC            "scd    "
+#define __INS           "dins    "
+#define __EXT           "dext    "
+#endif
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()      smp_llsc_mb()
+#define smp_mb__after_clear_bit()       smp_llsc_mb()
+
+/*
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+        unsigned short bit = nr & SZLONG_MASK;
+        unsigned long temp;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1                  # set_bit       \n"
+                "       or      %0, %2                                  \n"
+                "       " __SC  "%0, %1                                 \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (1UL << bit), "m" (*m));
+#ifdef CONFIG_CPU_MIPSR2
+        } else if (__builtin_constant_p(bit)) {
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1                  # set_bit       \n"
+                "       " __INS "%0, %4, %2, 1                          \n"
+                "       " __SC "%0, %1                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (bit), "m" (*m), "r" (~0));
+#endif /* CONFIG_CPU_MIPSR2 */
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1                  # set_bit       \n"
+                "       or      %0, %2                                  \n"
+                "       " __SC  "%0, %1                                 \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (1UL << bit), "m" (*m));
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                *a |= mask;
+                raw_local_irq_restore(flags);
+        }
+}
+
+/*
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+        unsigned short bit = nr & SZLONG_MASK;
+        unsigned long temp;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1                  # clear_bit     \n"
+                "       and     %0, %2                                  \n"
+                "       " __SC "%0, %1                                  \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (~(1UL << bit)), "m" (*m));
+#ifdef CONFIG_CPU_MIPSR2
+        } else if (__builtin_constant_p(bit)) {
+                __asm__ __volatile__(
+                "1:     " __LL "%0, %1                  # clear_bit     \n"
+                "       " __INS "%0, $0, %2, 1                          \n"
+                "       " __SC "%0, %1                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (bit), "m" (*m));
+#endif /* CONFIG_CPU_MIPSR2 */
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1                  # clear_bit     \n"
+                "       and     %0, %2                                  \n"
+                "       " __SC "%0, %1                                  \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (~(1UL << bit)), "m" (*m));
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                *a &= ~mask;
+                raw_local_irq_restore(flags);
+        }
+}
+
+/*
+ * clear_bit_unlock - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and implies release semantics before the memory
+ * operation. It can be used for an unlock.
+ */
+static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
+{
+        smp_mb__before_clear_bit();
+        clear_bit(nr, addr);
+}
+
+/*
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to change
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
+{
+        unsigned short bit = nr & SZLONG_MASK;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                           \n"
+                "1:     " __LL "%0, %1          # change_bit    \n"
+                "       xor     %0, %2                          \n"
+                "       " __SC  "%0, %1                         \n"
+                "       beqzl   %0, 1b                          \n"
+                "       .set    mips0                           \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (1UL << bit), "m" (*m));
+        } else if (cpu_has_llsc) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                           \n"
+                "1:     " __LL "%0, %1          # change_bit    \n"
+                "       xor     %0, %2                          \n"
+                "       " __SC  "%0, %1                         \n"
+                "       beqz    %0, 2f                          \n"
+                "       .subsection 2                           \n"
+                "2:     b       1b                              \n"
+                "       .previous                               \n"
+                "       .set    mips0                           \n"
+                : "=&r" (temp), "=m" (*m)
+                : "ir" (1UL << bit), "m" (*m));
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                *a ^= mask;
+                raw_local_irq_restore(flags);
+        }
+}
+
+/*
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_set_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        unsigned short bit = nr & SZLONG_MASK;
+        unsigned long res;
+
+        smp_llsc_mb();
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
+                "       or      %2, %0, %3                              \n"
+                "       " __SC  "%2, %1                                 \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       and     %2, %0, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << bit), "m" (*m)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
+                "       or      %2, %0, %3                              \n"
+                "       " __SC  "%2, %1                                 \n"
+                "       beqz    %2, 2f                                  \n"
+                "        and    %2, %0, %3                              \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "        nop                                            \n"
+                "       .previous                                       \n"
+                "       .set    pop                                     \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << bit), "m" (*m)
+                : "memory");
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                res = (mask & *a);
+                *a |= mask;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return res != 0;
+}
+
+/*
+ * test_and_set_bit_lock - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and implies acquire ordering semantics
+ * after the memory operation.
+ */
+static inline int test_and_set_bit_lock(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        unsigned short bit = nr & SZLONG_MASK;
+        unsigned long res;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
+                "       or      %2, %0, %3                              \n"
+                "       " __SC  "%2, %1                                 \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       and     %2, %0, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << bit), "m" (*m)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
+                "       or      %2, %0, %3                              \n"
+                "       " __SC  "%2, %1                                 \n"
+                "       beqz    %2, 2f                                  \n"
+                "        and    %2, %0, %3                              \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "        nop                                            \n"
+                "       .previous                                       \n"
+                "       .set    pop                                     \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << bit), "m" (*m)
+                : "memory");
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                res = (mask & *a);
+                *a |= mask;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return res != 0;
+}
+/*
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_clear_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        unsigned short bit = nr & SZLONG_MASK;
+        unsigned long res;
+
+        smp_llsc_mb();
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
+                "       or      %2, %0, %3                              \n"
+                "       xor     %2, %3                                  \n"
+                "       " __SC  "%2, %1                                 \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       and     %2, %0, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << bit), "m" (*m)
+                : "memory");
+#ifdef CONFIG_CPU_MIPSR2
+        } else if (__builtin_constant_p(nr)) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
+                "       " __EXT "%2, %0, %3, 1                          \n"
+                "       " __INS "%0, $0, %3, 1                          \n"
+                "       " __SC  "%0, %1                                 \n"
+                "       beqz    %0, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "ir" (bit), "m" (*m)
+                : "memory");
+#endif
+        } else if (cpu_has_llsc) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
+                "       or      %2, %0, %3                              \n"
+                "       xor     %2, %3                                  \n"
+                "       " __SC  "%2, %1                                 \n"
+                "       beqz    %2, 2f                                  \n"
+                "        and    %2, %0, %3                              \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "        nop                                            \n"
+                "       .previous                                       \n"
+                "       .set    pop                                     \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << bit), "m" (*m)
+                : "memory");
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                res = (mask & *a);
+                *a &= ~mask;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return res != 0;
+}
+
+/*
+ * test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_change_bit(unsigned long nr,
+        volatile unsigned long *addr)
+{
+        unsigned short bit = nr & SZLONG_MASK;
+        unsigned long res;
+
+        smp_llsc_mb();
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
+                "       xor     %2, %0, %3                              \n"
+                "       " __SC  "%2, %1                                 \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       and     %2, %0, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << bit), "m" (*m)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    noreorder                               \n"
+                "       .set    mips3                                   \n"
+                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
+                "       xor     %2, %0, %3                              \n"
+                "       " __SC  "\t%2, %1                               \n"
+                "       beqz    %2, 2f                                  \n"
+                "        and    %2, %0, %3                              \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "        nop                                            \n"
+                "       .previous                                       \n"
+                "       .set    pop                                     \n"
+                : "=&r" (temp), "=m" (*m), "=&r" (res)
+                : "r" (1UL << bit), "m" (*m)
+                : "memory");
+        } else {
+                volatile unsigned long *a = addr;
+                unsigned long mask;
+                unsigned long flags;
+
+                a += nr >> SZLONG_LOG;
+                mask = 1UL << bit;
+                raw_local_irq_save(flags);
+                res = (mask & *a);
+                *a ^= mask;
+                raw_local_irq_restore(flags);
+        }
+
+        smp_llsc_mb();
+
+        return res != 0;
+}
+
+#include <asm-generic/bitops/non-atomic.h>
+
+/*
+ * __clear_bit_unlock - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * __clear_bit() is non-atomic and implies release semantics before the memory
+ * operation. It can be used for an unlock if no other CPUs can concurrently
+ * modify other bits in the word.
+ */
+static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
+{
+        smp_mb();
+        __clear_bit(nr, addr);
+}
+
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
+
+/*
+ * Return the bit position (0..63) of the most significant 1 bit in a word
+ * Returns -1 if no 1 bit exists
+ */
+static inline unsigned long __fls(unsigned long x)
+{
+        int lz;
+
+        if (sizeof(x) == 4) {
+                __asm__(
+                "       .set    push                                    \n"
+                "       .set    mips32                                  \n"
+                "       clz     %0, %1                                  \n"
+                "       .set    pop                                     \n"
+                : "=r" (lz)
+                : "r" (x));
+
+                return 31 - lz;
+        }
+
+        BUG_ON(sizeof(x) != 8);
+
+        __asm__(
+        "       .set    push                                            \n"
+        "       .set    mips64                                          \n"
+        "       dclz    %0, %1                                          \n"
+        "       .set    pop                                             \n"
+        : "=r" (lz)
+        : "r" (x));
+
+        return 63 - lz;
+}
+
+/*
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Returns 0..SZLONG-1
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+        return __fls(word & -word);
+}
+
+/*
+ * fls - find last bit set.
+ * @word: The word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static inline int fls(int word)
+{
+        __asm__("clz %0, %1" : "=r" (word) : "r" (word));
+
+        return 32 - word;
+}
+
+#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
+static inline int fls64(__u64 word)
+{
+        __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
+
+        return 64 - word;
+}
+#else
+#include <asm-generic/bitops/fls64.h>
+#endif
+
+/*
+ * ffs - find first bit set.
+ * @word: The word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static inline int ffs(int word)
+{
+        if (!word)
+                return 0;
+
+        return fls(word & -word);
+}
+
+#else
+
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/fls64.h>
+
+#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
+
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/find.h>
+
+#ifdef __KERNEL__
+
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/hweight.h>
+#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/minix.h>
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_BITOPS_H */
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
new file mode 100644
index 000000000000..610fe3af7a03
--- /dev/null
+++ b/arch/mips/include/asm/bootinfo.h
@@ -0,0 +1,110 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2003 by Ralf Baechle
+ * Copyright (C) 1995, 1996 Andreas Busse
+ * Copyright (C) 1995, 1996 Stoned Elipot
+ * Copyright (C) 1995, 1996 Paul M. Antoine.
+ */
+#ifndef _ASM_BOOTINFO_H
+#define _ASM_BOOTINFO_H
+
+#include <linux/types.h>
+#include <asm/setup.h>
+
+/*
+ * The MACH_ IDs are sort of equivalent to PCI product IDs.  As such the
+ * numbers do not necessarily reflect technical relations or similarities
+ * between systems.
+ */
+
+/*
+ * Valid machtype values for group unknown
+ */
+#define  MACH_UNKNOWN           0       /* whatever...                  */
+
+/*
+ * Valid machtype for group DEC
+ */
+#define  MACH_DSUNKNOWN         0
+#define  MACH_DS23100           1       /* DECstation 2100 or 3100      */
+#define  MACH_DS5100            2       /* DECsystem 5100               */
+#define  MACH_DS5000_200        3       /* DECstation 5000/200          */
+#define  MACH_DS5000_1XX        4       /* DECstation 5000/120, 125, 133, 150 */
+#define  MACH_DS5000_XX         5       /* DECstation 5000/20, 25, 33, 50 */
+#define  MACH_DS5000_2X0        6       /* DECstation 5000/240, 260     */
+#define  MACH_DS5400            7       /* DECsystem 5400               */
+#define  MACH_DS5500            8       /* DECsystem 5500               */
+#define  MACH_DS5800            9       /* DECsystem 5800               */
+#define  MACH_DS5900            10      /* DECsystem 5900               */
+
+/*
+ * Valid machtype for group PMC-MSP
+ */
+#define MACH_MSP4200_EVAL       0       /* PMC-Sierra MSP4200 Evaluation */
+#define MACH_MSP4200_GW         1       /* PMC-Sierra MSP4200 Gateway demo */
+#define MACH_MSP4200_FPGA       2       /* PMC-Sierra MSP4200 Emulation */
+#define MACH_MSP7120_EVAL       3       /* PMC-Sierra MSP7120 Evaluation */
+#define MACH_MSP7120_GW         4       /* PMC-Sierra MSP7120 Residential GW */
+#define MACH_MSP7120_FPGA       5       /* PMC-Sierra MSP7120 Emulation */
+#define MACH_MSP_OTHER        255       /* PMC-Sierra unknown board type */
+
+/*
+ * Valid machtype for group Mikrotik
+ */
+#define MACH_MIKROTIK_RB532     0       /* Mikrotik RouterBoard 532     */
+#define MACH_MIKROTIK_RB532A    1       /* Mikrotik RouterBoard 532A    */
+
+#define CL_SIZE                 COMMAND_LINE_SIZE
+
+extern char *system_type;
+const char *get_system_type(void);
+
+extern unsigned long mips_machtype;
+
+#define BOOT_MEM_MAP_MAX        32
+#define BOOT_MEM_RAM            1
+#define BOOT_MEM_ROM_DATA       2
+#define BOOT_MEM_RESERVED       3
+
+/*
+ * A memory map that's built upon what was determined
+ * or specified on the command line.
+ */
+struct boot_mem_map {
+        int nr_map;
+        struct boot_mem_map_entry {
+                phys_t addr;    /* start of memory segment */
+                phys_t size;    /* size of memory segment */
+                long type;              /* type of memory segment */
+        } map[BOOT_MEM_MAP_MAX];
+};
+
+extern struct boot_mem_map boot_mem_map;
+
+extern void add_memory_region(phys_t start, phys_t size, long type);
+
+extern void prom_init(void);
+extern void prom_free_prom_memory(void);
+
+extern void free_init_pages(const char *what,
+                            unsigned long begin, unsigned long end);
+
+/*
+ * Initial kernel command line, usually setup by prom_init()
+ */
+extern char arcs_cmdline[CL_SIZE];
+
+/*
+ * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
+ */
+extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
+
+/*
+ * Platform memory detection hook called by setup_arch
+ */
+extern void plat_mem_setup(void);
+
+#endif /* _ASM_BOOTINFO_H */
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
new file mode 100644
index 000000000000..37c6857c8d4a
--- /dev/null
+++ b/arch/mips/include/asm/branch.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
+ */
+#ifndef _ASM_BRANCH_H
+#define _ASM_BRANCH_H
+
+#include <asm/ptrace.h>
+
+static inline int delay_slot(struct pt_regs *regs)
+{
+        return regs->cp0_cause & CAUSEF_BD;
+}
+
+static inline unsigned long exception_epc(struct pt_regs *regs)
+{
+        if (!delay_slot(regs))
+                return regs->cp0_epc;
+
+        return regs->cp0_epc + 4;
+}
+
+extern int __compute_return_epc(struct pt_regs *regs);
+
+static inline int compute_return_epc(struct pt_regs *regs)
+{
+        if (!delay_slot(regs)) {
+                regs->cp0_epc += 4;
+                return 0;
+        }
+
+        return __compute_return_epc(regs);
+}
+
+#endif /* _ASM_BRANCH_H */
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
new file mode 100644
index 000000000000..25b980c91e7e
--- /dev/null
+++ b/arch/mips/include/asm/break.h
@@ -0,0 +1,34 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 2003 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_BREAK_H
+#define __ASM_BREAK_H
+
+/*
+ * The following break codes are or were in use for specific purposes in
+ * other MIPS operating systems.  Linux/MIPS doesn't use all of them.  The
+ * unused ones are here as placeholders; we might encounter them in
+ * non-Linux/MIPS object files or make use of them in the future.
+ */
+#define BRK_USERBP      0       /* User bp (used by debuggers) */
+#define BRK_KERNELBP    1       /* Break in the kernel */
+#define BRK_ABORT       2       /* Sometimes used by abort(3) to SIGIOT */
+#define BRK_BD_TAKEN    3       /* For bd slot emulation - not implemented */
+#define BRK_BD_NOTTAKEN 4       /* For bd slot emulation - not implemented */
+#define BRK_SSTEPBP     5       /* User bp (used by debuggers) */
+#define BRK_OVERFLOW    6       /* Overflow check */
+#define BRK_DIVZERO     7       /* Divide by zero check */
+#define BRK_RANGE       8       /* Range error check */
+#define BRK_STACKOVERFLOW 9     /* For Ada stackchecking */
+#define BRK_NORLD       10      /* No rld found - not used by Linux/MIPS */
+#define _BRK_THREADBP   11      /* For threads, user bp (used by debuggers) */
+#define BRK_BUG         512     /* Used by BUG() */
+#define BRK_KDB         513     /* Used in KDB_ENTER() */
+#define BRK_MULOVF      1023    /* Multiply overflow */
+
+#endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h
new file mode 100644
index 000000000000..7eb63de808bc
--- /dev/null
+++ b/arch/mips/include/asm/bug.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_BUG_H
+#define __ASM_BUG_H
+
+#include <asm/sgidefs.h>
+
+#ifdef CONFIG_BUG
+
+#include <asm/break.h>
+
+#define BUG()                                                           \
+do {                                                                    \
+        __asm__ __volatile__("break %0" : : "i" (BRK_BUG));             \
+} while (0)
+
+#define HAVE_ARCH_BUG
+
+#if (_MIPS_ISA > _MIPS_ISA_MIPS1)
+
+#define BUG_ON(condition)                                               \
+do {                                                                    \
+        __asm__ __volatile__("tne $0, %0, %1"                           \
+                             : : "r" (condition), "i" (BRK_BUG));       \
+} while (0)
+
+#define HAVE_ARCH_BUG_ON
+
+#endif /* _MIPS_ISA > _MIPS_ISA_MIPS1 */
+
+#endif
+
+#include <asm-generic/bug.h>
+
+#endif /* __ASM_BUG_H */
diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h
new file mode 100644
index 000000000000..9dc10df32078
--- /dev/null
+++ b/arch/mips/include/asm/bugs.h
@@ -0,0 +1,53 @@
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Copyright (C) 2007  Maciej W. Rozycki
+ *
+ * Needs:
+ *      void check_bugs(void);
+ */
+#ifndef _ASM_BUGS_H
+#define _ASM_BUGS_H
+
+#include <linux/bug.h>
+#include <linux/delay.h>
+
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+
+extern int daddiu_bug;
+
+extern void check_bugs64_early(void);
+
+extern void check_bugs32(void);
+extern void check_bugs64(void);
+
+static inline void check_bugs_early(void)
+{
+#ifdef CONFIG_64BIT
+        check_bugs64_early();
+#endif
+}
+
+static inline void check_bugs(void)
+{
+        unsigned int cpu = smp_processor_id();
+
+        cpu_data[cpu].udelay_val = loops_per_jiffy;
+        check_bugs32();
+#ifdef CONFIG_64BIT
+        check_bugs64();
+#endif
+}
+
+static inline int r4k_daddiu_bug(void)
+{
+#ifdef CONFIG_64BIT
+        WARN_ON(daddiu_bug < 0);
+        return daddiu_bug != 0;
+#else
+        return 0;
+#endif
+}
+
+#endif /* _ASM_BUGS_H */
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
new file mode 100644
index 000000000000..fe7dc2d59b69
--- /dev/null
+++ b/arch/mips/include/asm/byteorder.h
@@ -0,0 +1,76 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
+
+#include <linux/compiler.h>
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+        __asm__(
+        "       wsbh    %0, %1                  \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+#define __arch__swab16(x)       ___arch__swab16(x)
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+        __asm__(
+        "       wsbh    %0, %1                  \n"
+        "       rotr    %0, %0, 16              \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+#define __arch__swab32(x)       ___arch__swab32(x)
+
+#ifdef CONFIG_CPU_MIPS64_R2
+
+static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+{
+        __asm__(
+        "       dsbh    %0, %1                  \n"
+        "       dshd    %0, %0                  \n"
+        "       drotr   %0, %0, 32              \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+
+#define __arch__swab64(x)       ___arch__swab64(x)
+
+#endif /* CONFIG_CPU_MIPS64_R2 */
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#if defined(__MIPSEB__)
+#  include <linux/byteorder/big_endian.h>
+#elif defined(__MIPSEL__)
+#  include <linux/byteorder/little_endian.h>
+#else
+#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
new file mode 100644
index 000000000000..37f175c42bb5
--- /dev/null
+++ b/arch/mips/include/asm/cache.h
@@ -0,0 +1,20 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+#include <kmalloc.h>
+
+#define L1_CACHE_SHIFT          CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+#define SMP_CACHE_SHIFT         L1_CACHE_SHIFT
+#define SMP_CACHE_BYTES         L1_CACHE_BYTES
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h
new file mode 100644
index 000000000000..f3ce721861d3
--- /dev/null
+++ b/arch/mips/include/asm/cachectl.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ */
+#ifndef _ASM_CACHECTL
+#define _ASM_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE  (1<<0)          /* flush instruction cache        */
+#define DCACHE  (1<<1)          /* writeback and flush data cache */
+#define BCACHE  (ICACHE|DCACHE) /* flush both caches              */
+
+/*
+ * Caching modes for the cachectl(2) call
+ *
+ * cachectl(2) is currently not supported and returns ENOSYS.
+ */
+#define CACHEABLE       0       /* make pages cacheable */
+#define UNCACHEABLE     1       /* make pages uncacheable */
+
+#endif  /* _ASM_CACHECTL */
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
new file mode 100644
index 000000000000..03b1d69b142f
--- /dev/null
+++ b/arch/mips/include/asm/cacheflush.h
@@ -0,0 +1,116 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_CACHEFLUSH_H
+#define _ASM_CACHEFLUSH_H
+
+/* Keep includes the same across arches.  */
+#include <linux/mm.h>
+#include <asm/cpu-features.h>
+
+/* Cache flushing:
+ *
+ *  - flush_cache_all() flushes entire cache
+ *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
+ *  - flush_cache_dup mm(mm) handles cache flushing when forking
+ *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
+ *  - flush_cache_range(vma, start, end) flushes a range of pages
+ *  - flush_icache_range(start, end) flush a range of instructions
+ *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
+ *
+ * MIPS specific flush operations:
+ *
+ *  - flush_cache_sigtramp() flush signal trampoline
+ *  - flush_icache_all() flush the entire instruction cache
+ *  - flush_data_cache_page() flushes a page from the data cache
+ */
+extern void (*flush_cache_all)(void);
+extern void (*__flush_cache_all)(void);
+extern void (*flush_cache_mm)(struct mm_struct *mm);
+#define flush_cache_dup_mm(mm)  do { (void) (mm); } while (0)
+extern void (*flush_cache_range)(struct vm_area_struct *vma,
+        unsigned long start, unsigned long end);
+extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
+extern void __flush_dcache_page(struct page *page);
+
+static inline void flush_dcache_page(struct page *page)
+{
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
+                __flush_dcache_page(page);
+
+}
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+#define ARCH_HAS_FLUSH_ANON_PAGE
+extern void __flush_anon_page(struct page *, unsigned long);
+static inline void flush_anon_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vmaddr)
+{
+        if (cpu_has_dc_aliases && PageAnon(page))
+                __flush_anon_page(page, vmaddr);
+}
+
+static inline void flush_icache_page(struct vm_area_struct *vma,
+        struct page *page)
+{
+}
+
+extern void (*flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);
+
+extern void (*__flush_cache_vmap)(void);
+
+static inline void flush_cache_vmap(unsigned long start, unsigned long end)
+{
+        if (cpu_has_dc_aliases)
+                __flush_cache_vmap();
+}
+
+extern void (*__flush_cache_vunmap)(void);
+
+static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
+{
+        if (cpu_has_dc_aliases)
+                __flush_cache_vunmap();
+}
+
+extern void copy_to_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len);
+
+extern void copy_from_user_page(struct vm_area_struct *vma,
+        struct page *page, unsigned long vaddr, void *dst, const void *src,
+        unsigned long len);
+
+extern void (*flush_cache_sigtramp)(unsigned long addr);
+extern void (*flush_icache_all)(void);
+extern void (*local_flush_data_cache_page)(void * addr);
+extern void (*flush_data_cache_page)(unsigned long addr);
+
+/*
+ * This flag is used to indicate that the page pointed to by a pte
+ * is dirty and requires cleaning before returning it to the user.
+ */
+#define PG_dcache_dirty                 PG_arch_1
+
+#define Page_dcache_dirty(page)         \
+        test_bit(PG_dcache_dirty, &(page)->flags)
+#define SetPageDcacheDirty(page)        \
+        set_bit(PG_dcache_dirty, &(page)->flags)
+#define ClearPageDcacheDirty(page)      \
+        clear_bit(PG_dcache_dirty, &(page)->flags)
+
+/* Run kernel code uncached, useful for cache probing functions. */
+unsigned long run_uncached(void *func);
+
+extern void *kmap_coherent(struct page *page, unsigned long addr);
+extern void kunmap_coherent(void);
+
+#endif /* _ASM_CACHEFLUSH_H */
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
new file mode 100644
index 000000000000..256ad2cc6eb8
--- /dev/null
+++ b/arch/mips/include/asm/cacheops.h
@@ -0,0 +1,85 @@
+/*
+ * Cache operations for the cache instruction.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_CACHEOPS_H
+#define __ASM_CACHEOPS_H
+
+/*
+ * Cache Operations available on all MIPS processors with R4000-style caches
+ */
+#define Index_Invalidate_I      0x00
+#define Index_Writeback_Inv_D   0x01
+#define Index_Load_Tag_I        0x04
+#define Index_Load_Tag_D        0x05
+#define Index_Store_Tag_I       0x08
+#define Index_Store_Tag_D       0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I        0x00
+#else
+#define Hit_Invalidate_I        0x10
+#endif
+#define Hit_Invalidate_D        0x11
+#define Hit_Writeback_Inv_D     0x15
+
+/*
+ * R4000-specific cacheops
+ */
+#define Create_Dirty_Excl_D     0x0d
+#define Fill                    0x14
+#define Hit_Writeback_I         0x18
+#define Hit_Writeback_D         0x19
+
+/*
+ * R4000SC and R4400SC-specific cacheops
+ */
+#define Index_Invalidate_SI     0x02
+#define Index_Writeback_Inv_SD  0x03
+#define Index_Load_Tag_SI       0x06
+#define Index_Load_Tag_SD       0x07
+#define Index_Store_Tag_SI      0x0A
+#define Index_Store_Tag_SD      0x0B
+#define Create_Dirty_Excl_SD    0x0f
+#define Hit_Invalidate_SI       0x12
+#define Hit_Invalidate_SD       0x13
+#define Hit_Writeback_Inv_SD    0x17
+#define Hit_Writeback_SD        0x1b
+#define Hit_Set_Virtual_SI      0x1e
+#define Hit_Set_Virtual_SD      0x1f
+
+/*
+ * R5000-specific cacheops
+ */
+#define R5K_Page_Invalidate_S   0x17
+
+/*
+ * RM7000-specific cacheops
+ */
+#define Page_Invalidate_T       0x16
+
+/*
+ * R10000-specific cacheops
+ *
+ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
+ * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
+ */
+#define Index_Writeback_Inv_S   0x03
+#define Index_Load_Tag_S        0x07
+#define Index_Store_Tag_S       0x0B
+#define Hit_Invalidate_S        0x13
+#define Cache_Barrier           0x14
+#define Hit_Writeback_Inv_S     0x17
+#define Index_Load_Data_I       0x18
+#define Index_Load_Data_D       0x19
+#define Index_Load_Data_S       0x1b
+#define Index_Store_Data_I      0x1c
+#define Index_Store_Data_D      0x1d
+#define Index_Store_Data_S      0x1f
+
+#endif  /* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
new file mode 100644
index 000000000000..290485ac5407
--- /dev/null
+++ b/arch/mips/include/asm/checksum.h
@@ -0,0 +1,260 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2001 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 Thiemo Seufer.
+ * Copyright (C) 2002 Maciej W. Rozycki
+ */
+#ifndef _ASM_CHECKSUM_H
+#define _ASM_CHECKSUM_H
+
+#include <linux/in6.h>
+
+#include <asm/uaccess.h>
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+__wsum csum_partial(const void *buff, int len, __wsum sum);
+
+__wsum __csum_partial_copy_user(const void *src, void *dst,
+                                int len, __wsum sum, int *err_ptr);
+
+/*
+ * this is a new version of the above that records errors it finds in *errp,
+ * but continues and zeros the rest of the buffer.
+ */
+static inline
+__wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len,
+                                   __wsum sum, int *err_ptr)
+{
+        might_sleep();
+        return __csum_partial_copy_user((__force void *)src, dst,
+                                        len, sum, err_ptr);
+}
+
+/*
+ * Copy and checksum to user
+ */
+#define HAVE_CSUM_COPY_USER
+static inline
+__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len,
+                             __wsum sum, int *err_ptr)
+{
+        might_sleep();
+        if (access_ok(VERIFY_WRITE, dst, len))
+                return __csum_partial_copy_user(src, (__force void *)dst,
+                                                len, sum, err_ptr);
+        if (len)
+                *err_ptr = -EFAULT;
+
+        return (__force __wsum)-1; /* invalid checksum */
+}
+
+/*
+ * the same as csum_partial, but copies from user space (but on MIPS
+ * we have just one address space, so this is identical to the above)
+ */
+__wsum csum_partial_copy_nocheck(const void *src, void *dst,
+                                       int len, __wsum sum);
+
+/*
+ *      Fold a partial checksum without adding pseudo headers
+ */
+static inline __sum16 csum_fold(__wsum sum)
+{
+        __asm__(
+        "       .set    push            # csum_fold\n"
+        "       .set    noat            \n"
+        "       sll     $1, %0, 16      \n"
+        "       addu    %0, $1          \n"
+        "       sltu    $1, %0, $1      \n"
+        "       srl     %0, %0, 16      \n"
+        "       addu    %0, $1          \n"
+        "       xori    %0, 0xffff      \n"
+        "       .set    pop"
+        : "=r" (sum)
+        : "0" (sum));
+
+        return (__force __sum16)sum;
+}
+
+/*
+ *      This is a version of ip_compute_csum() optimized for IP headers,
+ *      which always checksum on 4 octet boundaries.
+ *
+ *      By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
+ *      Arnt Gulbrandsen.
+ */
+static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+        const unsigned int *word = iph;
+        const unsigned int *stop = word + ihl;
+        unsigned int csum;
+        int carry;
+
+        csum = word[0];
+        csum += word[1];
+        carry = (csum < word[1]);
+        csum += carry;
+
+        csum += word[2];
+        carry = (csum < word[2]);
+        csum += carry;
+
+        csum += word[3];
+        carry = (csum < word[3]);
+        csum += carry;
+
+        word += 4;
+        do {
+                csum += *word;
+                carry = (csum < *word);
+                csum += carry;
+                word++;
+        } while (word != stop);
+
+        return csum_fold(csum);
+}
+
+static inline __wsum csum_tcpudp_nofold(__be32 saddr,
+        __be32 daddr, unsigned short len, unsigned short proto,
+        __wsum sum)
+{
+        __asm__(
+        "       .set    push            # csum_tcpudp_nofold\n"
+        "       .set    noat            \n"
+#ifdef CONFIG_32BIT
+        "       addu    %0, %2          \n"
+        "       sltu    $1, %0, %2      \n"
+        "       addu    %0, $1          \n"
+
+        "       addu    %0, %3          \n"
+        "       sltu    $1, %0, %3      \n"
+        "       addu    %0, $1          \n"
+
+        "       addu    %0, %4          \n"
+        "       sltu    $1, %0, %4      \n"
+        "       addu    %0, $1          \n"
+#endif
+#ifdef CONFIG_64BIT
+        "       daddu   %0, %2          \n"
+        "       daddu   %0, %3          \n"
+        "       daddu   %0, %4          \n"
+        "       dsll32  $1, %0, 0       \n"
+        "       daddu   %0, $1          \n"
+        "       dsra32  %0, %0, 0       \n"
+#endif
+        "       .set    pop"
+        : "=r" (sum)
+        : "0" ((__force unsigned long)daddr),
+          "r" ((__force unsigned long)saddr),
+#ifdef __MIPSEL__
+          "r" ((proto + len) << 8),
+#else
+          "r" (proto + len),
+#endif
+          "r" ((__force unsigned long)sum));
+
+        return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
+                                                   unsigned short len,
+                                                   unsigned short proto,
+                                                   __wsum sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+                                          const struct in6_addr *daddr,
+                                          __u32 len, unsigned short proto,
+                                          __wsum sum)
+{
+        __asm__(
+        "       .set    push            # csum_ipv6_magic\n"
+        "       .set    noreorder       \n"
+        "       .set    noat            \n"
+        "       addu    %0, %5          # proto (long in network byte order)\n"
+        "       sltu    $1, %0, %5      \n"
+        "       addu    %0, $1          \n"
+
+        "       addu    %0, %6          # csum\n"
+        "       sltu    $1, %0, %6      \n"
+        "       lw      %1, 0(%2)       # four words source address\n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 4(%2)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 8(%2)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 12(%2)      \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 0(%3)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 4(%3)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 8(%3)       \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       lw      %1, 12(%3)      \n"
+        "       addu    %0, $1          \n"
+        "       addu    %0, %1          \n"
+        "       sltu    $1, %0, %1      \n"
+
+        "       addu    %0, $1          # Add final carry\n"
+        "       .set    pop"
+        : "=r" (sum), "=r" (proto)
+        : "r" (saddr), "r" (daddr),
+          "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
+
+        return csum_fold(sum);
+}
+
+#endif /* _ASM_CHECKSUM_H */
diff --git a/arch/mips/include/asm/cmp.h b/arch/mips/include/asm/cmp.h
new file mode 100644
index 000000000000..89a73fb93ae6
--- /dev/null
+++ b/arch/mips/include/asm/cmp.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_CMP_H
+#define _ASM_CMP_H
+
+/*
+ * Definitions for CMP multitasking on MIPS cores
+ */
+struct task_struct;
+
+extern void cmp_smp_setup(void);
+extern void cmp_smp_finish(void);
+extern void cmp_boot_secondary(int cpu, struct task_struct *t);
+extern void cmp_init_secondary(void);
+extern void cmp_cpus_done(void);
+extern void cmp_prepare_cpus(unsigned int max_cpus);
+
+/* This is platform specific */
+extern void cmp_send_ipi(int cpu, unsigned int action);
+#endif /*  _ASM_CMP_H */
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
new file mode 100644
index 000000000000..4a812c3ceb90
--- /dev/null
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -0,0 +1,124 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_CMPXCHG_H
+#define __ASM_CMPXCHG_H
+
+#include <linux/irqflags.h>
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+#define __cmpxchg_asm(ld, st, m, old, new)                              \
+({                                                                      \
+        __typeof(*(m)) __ret;                                           \
+                                                                        \
+        if (cpu_has_llsc && R10000_LLSC_WAR) {                          \
+                __asm__ __volatile__(                                   \
+                "       .set    push                            \n"     \
+                "       .set    noat                            \n"     \
+                "       .set    mips3                           \n"     \
+                "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
+                "       bne     %0, %z3, 2f                     \n"     \
+                "       .set    mips0                           \n"     \
+                "       move    $1, %z4                         \n"     \
+                "       .set    mips3                           \n"     \
+                "       " st "  $1, %1                          \n"     \
+                "       beqzl   $1, 1b                          \n"     \
+                "2:                                             \n"     \
+                "       .set    pop                             \n"     \
+                : "=&r" (__ret), "=R" (*m)                              \
+                : "R" (*m), "Jr" (old), "Jr" (new)                      \
+                : "memory");                                            \
+        } else if (cpu_has_llsc) {                                      \
+                __asm__ __volatile__(                                   \
+                "       .set    push                            \n"     \
+                "       .set    noat                            \n"     \
+                "       .set    mips3                           \n"     \
+                "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
+                "       bne     %0, %z3, 2f                     \n"     \
+                "       .set    mips0                           \n"     \
+                "       move    $1, %z4                         \n"     \
+                "       .set    mips3                           \n"     \
+                "       " st "  $1, %1                          \n"     \
+                "       beqz    $1, 3f                          \n"     \
+                "2:                                             \n"     \
+                "       .subsection 2                           \n"     \
+                "3:     b       1b                              \n"     \
+                "       .previous                               \n"     \
+                "       .set    pop                             \n"     \
+                : "=&r" (__ret), "=R" (*m)                              \
+                : "R" (*m), "Jr" (old), "Jr" (new)                      \
+                : "memory");                                            \
+        } else {                                                        \
+                unsigned long __flags;                                  \
+                                                                        \
+                raw_local_irq_save(__flags);                            \
+                __ret = *m;                                             \
+                if (__ret == old)                                       \
+                        *m = new;                                       \
+                raw_local_irq_restore(__flags);                         \
+        }                                                               \
+                                                                        \
+        __ret;                                                          \
+})
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg().
+ */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+#define __cmpxchg(ptr, old, new, barrier)                               \
+({                                                                      \
+        __typeof__(ptr) __ptr = (ptr);                                  \
+        __typeof__(*(ptr)) __old = (old);                               \
+        __typeof__(*(ptr)) __new = (new);                               \
+        __typeof__(*(ptr)) __res = 0;                                   \
+                                                                        \
+        barrier;                                                        \
+                                                                        \
+        switch (sizeof(*(__ptr))) {                                     \
+        case 4:                                                         \
+                __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
+                break;                                                  \
+        case 8:                                                         \
+                if (sizeof(long) == 8) {                                \
+                        __res = __cmpxchg_asm("lld", "scd", __ptr,      \
+                                           __old, __new);               \
+                        break;                                          \
+                }                                                       \
+        default:                                                        \
+                __cmpxchg_called_with_bad_pointer();                    \
+                break;                                                  \
+        }                                                               \
+                                                                        \
+        barrier;                                                        \
+                                                                        \
+        __res;                                                          \
+})
+
+#define cmpxchg(ptr, old, new)          __cmpxchg(ptr, old, new, smp_llsc_mb())
+#define cmpxchg_local(ptr, old, new)    __cmpxchg(ptr, old, new, )
+
+#define cmpxchg64(ptr, o, n)                                            \
+  ({                                                                    \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg((ptr), (o), (n));                                       \
+  })
+
+#ifdef CONFIG_64BIT
+#define cmpxchg64_local(ptr, o, n)                                      \
+  ({                                                                    \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg_local((ptr), (o), (n));                                 \
+  })
+#else
+#include <asm-generic/cmpxchg-local.h>
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+#endif
+
+#endif /* __ASM_CMPXCHG_H */
diff --git a/arch/mips/include/asm/compat-signal.h b/arch/mips/include/asm/compat-signal.h
new file mode 100644
index 000000000000..368a99e5c3e1
--- /dev/null
+++ b/arch/mips/include/asm/compat-signal.h
@@ -0,0 +1,119 @@
+#ifndef __ASM_COMPAT_SIGNAL_H
+#define __ASM_COMPAT_SIGNAL_H
+
+#include <linux/bug.h>
+#include <linux/compat.h>
+#include <linux/compiler.h>
+
+#include <asm/signal.h>
+#include <asm/siginfo.h>
+
+#include <asm/uaccess.h>
+
+#define SI_PAD_SIZE32   ((SI_MAX_SIZE/sizeof(int)) - 3)
+
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_code;
+        int si_errno;
+
+        union {
+                int _pad[SI_PAD_SIZE32];
+
+                /* kill() */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        compat_uid_t _uid;      /* sender's uid */
+                } _kill;
+
+                /* SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        compat_uid_t _uid;      /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+
+                /* IRIX SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        compat_clock_t _utime;
+                        int _status;            /* exit code */
+                        compat_clock_t _stime;
+                } _irix_sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        s32 _addr; /* faulting insn/memory ref. */
+                } _sigfault;
+
+                /* SIGPOLL, SIGXFSZ (To do ...)  */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+
+                /* POSIX.1b timers */
+                struct {
+                        timer_t _tid;           /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;/* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        compat_uid_t _uid;      /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
+        } _sifields;
+} compat_siginfo_t;
+
+static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
+        const sigset_t *s)
+{
+        int err;
+
+        BUG_ON(sizeof(*d) != sizeof(*s));
+        BUG_ON(_NSIG_WORDS != 2);
+
+        err  = __put_user(s->sig[0],       &d->sig[0]);
+        err |= __put_user(s->sig[0] >> 32, &d->sig[1]);
+        err |= __put_user(s->sig[1],       &d->sig[2]);
+        err |= __put_user(s->sig[1] >> 32, &d->sig[3]);
+
+        return err;
+}
+
+static inline int __copy_conv_sigset_from_user(sigset_t *d,
+        const compat_sigset_t __user *s)
+{
+        int err;
+        union sigset_u {
+                sigset_t        s;
+                compat_sigset_t c;
+        } *u = (union sigset_u *) d;
+
+        BUG_ON(sizeof(*d) != sizeof(*s));
+        BUG_ON(_NSIG_WORDS != 2);
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        err  = __get_user(u->c.sig[1], &s->sig[0]);
+        err |= __get_user(u->c.sig[0], &s->sig[1]);
+        err |= __get_user(u->c.sig[3], &s->sig[2]);
+        err |= __get_user(u->c.sig[2], &s->sig[3]);
+#endif
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        err  = __get_user(u->c.sig[0], &s->sig[0]);
+        err |= __get_user(u->c.sig[1], &s->sig[1]);
+        err |= __get_user(u->c.sig[2], &s->sig[2]);
+        err |= __get_user(u->c.sig[3], &s->sig[3]);
+#endif
+
+        return err;
+}
+
+#endif /* __ASM_COMPAT_SIGNAL_H */
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
new file mode 100644
index 000000000000..ac5d541368e9
--- /dev/null
+++ b/arch/mips/include/asm/compat.h
@@ -0,0 +1,221 @@
+#ifndef _ASM_COMPAT_H
+#define _ASM_COMPAT_H
+/*
+ * Architecture specific compatibility types
+ */
+#include <linux/types.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+
+#define COMPAT_USER_HZ  100
+
+typedef u32             compat_size_t;
+typedef s32             compat_ssize_t;
+typedef s32             compat_time_t;
+typedef s32             compat_clock_t;
+typedef s32             compat_suseconds_t;
+
+typedef s32             compat_pid_t;
+typedef s32             __compat_uid_t;
+typedef s32             __compat_gid_t;
+typedef __compat_uid_t  __compat_uid32_t;
+typedef __compat_gid_t  __compat_gid32_t;
+typedef u32             compat_mode_t;
+typedef u32             compat_ino_t;
+typedef u32             compat_dev_t;
+typedef s32             compat_off_t;
+typedef s64             compat_loff_t;
+typedef u32             compat_nlink_t;
+typedef s32             compat_ipc_pid_t;
+typedef s32             compat_daddr_t;
+typedef s32             compat_caddr_t;
+typedef struct {
+        s32     val[2];
+} compat_fsid_t;
+typedef s32             compat_timer_t;
+typedef s32             compat_key_t;
+
+typedef s32             compat_int_t;
+typedef s32             compat_long_t;
+typedef s64             compat_s64;
+typedef u32             compat_uint_t;
+typedef u32             compat_ulong_t;
+typedef u64             compat_u64;
+
+struct compat_timespec {
+        compat_time_t   tv_sec;
+        s32             tv_nsec;
+};
+
+struct compat_timeval {
+        compat_time_t   tv_sec;
+        s32             tv_usec;
+};
+
+struct compat_stat {
+        compat_dev_t    st_dev;
+        s32             st_pad1[3];
+        compat_ino_t    st_ino;
+        compat_mode_t   st_mode;
+        compat_nlink_t  st_nlink;
+        __compat_uid_t  st_uid;
+        __compat_gid_t  st_gid;
+        compat_dev_t    st_rdev;
+        s32             st_pad2[2];
+        compat_off_t    st_size;
+        s32             st_pad3;
+        compat_time_t   st_atime;
+        s32             st_atime_nsec;
+        compat_time_t   st_mtime;
+        s32             st_mtime_nsec;
+        compat_time_t   st_ctime;
+        s32             st_ctime_nsec;
+        s32             st_blksize;
+        s32             st_blocks;
+        s32             st_pad4[14];
+};
+
+struct compat_flock {
+        short           l_type;
+        short           l_whence;
+        compat_off_t    l_start;
+        compat_off_t    l_len;
+        s32             l_sysid;
+        compat_pid_t    l_pid;
+        short           __unused;
+        s32             pad[4];
+};
+
+#define F_GETLK64       33
+#define F_SETLK64       34
+#define F_SETLKW64      35
+
+struct compat_flock64 {
+        short           l_type;
+        short           l_whence;
+        compat_loff_t   l_start;
+        compat_loff_t   l_len;
+        compat_pid_t    l_pid;
+};
+
+struct compat_statfs {
+        int             f_type;
+        int             f_bsize;
+        int             f_frsize;
+        int             f_blocks;
+        int             f_bfree;
+        int             f_files;
+        int             f_ffree;
+        int             f_bavail;
+        compat_fsid_t   f_fsid;
+        int             f_namelen;
+        int             f_spare[6];
+};
+
+#define COMPAT_RLIM_INFINITY    0x7fffffffUL
+
+typedef u32             compat_old_sigset_t;    /* at least 32 bits */
+
+#define _COMPAT_NSIG            128             /* Don't ask !$@#% ...  */
+#define _COMPAT_NSIG_BPW        32
+
+typedef u32             compat_sigset_word;
+
+#define COMPAT_OFF_T_MAX        0x7fffffff
+#define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
+
+/*
+ * A pointer passed in from user mode. This should not
+ * be used for syscall parameters, just declare them
+ * as pointers because the syscall entry code will have
+ * appropriately converted them already.
+ */
+typedef u32             compat_uptr_t;
+
+static inline void __user *compat_ptr(compat_uptr_t uptr)
+{
+        /* cast to a __user pointer via "unsigned long" makes sparse happy */
+        return (void __user *)(unsigned long)(long)uptr;
+}
+
+static inline compat_uptr_t ptr_to_compat(void __user *uptr)
+{
+        return (u32)(unsigned long)uptr;
+}
+
+static inline void __user *compat_alloc_user_space(long len)
+{
+        struct pt_regs *regs = (struct pt_regs *)
+                ((unsigned long) current_thread_info() + THREAD_SIZE - 32) - 1;
+
+        return (void __user *) (regs->regs[29] - len);
+}
+
+struct compat_ipc64_perm {
+        compat_key_t key;
+        __compat_uid32_t uid;
+        __compat_gid32_t gid;
+        __compat_uid32_t cuid;
+        __compat_gid32_t cgid;
+        compat_mode_t mode;
+        unsigned short seq;
+        unsigned short __pad2;
+        compat_ulong_t __unused1;
+        compat_ulong_t __unused2;
+};
+
+struct compat_semid64_ds {
+        struct compat_ipc64_perm sem_perm;
+        compat_time_t   sem_otime;
+        compat_time_t   sem_ctime;
+        compat_ulong_t  sem_nsems;
+        compat_ulong_t  __unused1;
+        compat_ulong_t  __unused2;
+};
+
+struct compat_msqid64_ds {
+        struct compat_ipc64_perm msg_perm;
+#ifndef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused1;
+#endif
+        compat_time_t   msg_stime;
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused1;
+#endif
+#ifndef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused2;
+#endif
+        compat_time_t   msg_rtime;
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused2;
+#endif
+#ifndef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused3;
+#endif
+        compat_time_t   msg_ctime;
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+        compat_ulong_t  __unused3;
+#endif
+        compat_ulong_t  msg_cbytes;
+        compat_ulong_t  msg_qnum;
+        compat_ulong_t  msg_qbytes;
+        compat_pid_t    msg_lspid;
+        compat_pid_t    msg_lrpid;
+        compat_ulong_t  __unused4;
+        compat_ulong_t  __unused5;
+};
+
+struct compat_shmid64_ds {
+        struct compat_ipc64_perm shm_perm;
+        compat_size_t   shm_segsz;
+        compat_time_t   shm_atime;
+        compat_time_t   shm_dtime;
+        compat_time_t   shm_ctime;
+        compat_pid_t    shm_cpid;
+        compat_pid_t    shm_lpid;
+        compat_ulong_t  shm_nattch;
+        compat_ulong_t  __unused1;
+        compat_ulong_t  __unused2;
+};
+
+#endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/compiler.h b/arch/mips/include/asm/compiler.h
new file mode 100644
index 000000000000..71f5c5cfc58a
--- /dev/null
+++ b/arch/mips/include/asm/compiler.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2004, 2007  Maciej W. Rozycki
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_COMPILER_H
+#define _ASM_COMPILER_H
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
+#define GCC_IMM_ASM() "n"
+#define GCC_REG_ACCUM "$0"
+#else
+#define GCC_IMM_ASM() "rn"
+#define GCC_REG_ACCUM "accum"
+#endif
+
+#endif /* _ASM_COMPILER_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
new file mode 100644
index 000000000000..5ea701fc3425
--- /dev/null
+++ b/arch/mips/include/asm/cpu-features.h
@@ -0,0 +1,219 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+#include <cpu-feature-overrides.h>
+
+#ifndef current_cpu_type
+#define current_cpu_type()      current_cpu_data.cputype
+#endif
+
+/*
+ * SMP assumption: Options of CPU 0 are a superset of all processors.
+ * This is true for all known MIPS systems.
+ */
+#ifndef cpu_has_tlb
+#define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
+#endif
+#ifndef cpu_has_4kex
+#define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
+#endif
+#ifndef cpu_has_3k_cache
+#define cpu_has_3k_cache        (cpu_data[0].options & MIPS_CPU_3K_CACHE)
+#endif
+#define cpu_has_6k_cache        0
+#define cpu_has_8k_cache        0
+#ifndef cpu_has_4k_cache
+#define cpu_has_4k_cache        (cpu_data[0].options & MIPS_CPU_4K_CACHE)
+#endif
+#ifndef cpu_has_tx39_cache
+#define cpu_has_tx39_cache      (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
+#endif
+#ifndef cpu_has_fpu
+#define cpu_has_fpu             (current_cpu_data.options & MIPS_CPU_FPU)
+#define raw_cpu_has_fpu         (raw_current_cpu_data.options & MIPS_CPU_FPU)
+#else
+#define raw_cpu_has_fpu         cpu_has_fpu
+#endif
+#ifndef cpu_has_32fpr
+#define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
+#endif
+#ifndef cpu_has_counter
+#define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
+#endif
+#ifndef cpu_has_watch
+#define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
+#endif
+#ifndef cpu_has_divec
+#define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
+#endif
+#ifndef cpu_has_vce
+#define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
+#endif
+#ifndef cpu_has_cache_cdex_p
+#define cpu_has_cache_cdex_p    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
+#endif
+#ifndef cpu_has_cache_cdex_s
+#define cpu_has_cache_cdex_s    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
+#endif
+#ifndef cpu_has_prefetch
+#define cpu_has_prefetch        (cpu_data[0].options & MIPS_CPU_PREFETCH)
+#endif
+#ifndef cpu_has_mcheck
+#define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
+#endif
+#ifndef cpu_has_ejtag
+#define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
+#endif
+#ifndef cpu_has_llsc
+#define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
+#endif
+#ifndef cpu_has_mips16
+#define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
+#endif
+#ifndef cpu_has_mdmx
+#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
+#endif
+#ifndef cpu_has_mips3d
+#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#endif
+#ifndef cpu_has_smartmips
+#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
+#endif
+#ifndef cpu_has_vtag_icache
+#define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
+#endif
+#ifndef cpu_has_dc_aliases
+#define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
+#endif
+#ifndef cpu_has_ic_fills_f_dc
+#define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
+#endif
+#ifndef cpu_has_pindexed_dcache
+#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+#endif
+
+/*
+ * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
+ * such as the R10000 have I-Caches that snoop local stores; the embedded ones
+ * don't.  For maintaining I-cache coherency this means we need to flush the
+ * D-cache all the way back to whever the I-cache does refills from, so the
+ * I-cache has a chance to see the new data at all.  Then we have to flush the
+ * I-cache also.
+ * Note we may have been rescheduled and may no longer be running on the CPU
+ * that did the store so we can't optimize this into only doing the flush on
+ * the local CPU.
+ */
+#ifndef cpu_icache_snoops_remote_store
+#ifdef CONFIG_SMP
+#define cpu_icache_snoops_remote_store  (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
+#else
+#define cpu_icache_snoops_remote_store  1
+#endif
+#endif
+
+# ifndef cpu_has_mips32r1
+# define cpu_has_mips32r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
+# endif
+# ifndef cpu_has_mips32r2
+# define cpu_has_mips32r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
+# endif
+# ifndef cpu_has_mips64r1
+# define cpu_has_mips64r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
+# endif
+# ifndef cpu_has_mips64r2
+# define cpu_has_mips64r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
+# endif
+
+/*
+ * Shortcuts ...
+ */
+#define cpu_has_mips32  (cpu_has_mips32r1 | cpu_has_mips32r2)
+#define cpu_has_mips64  (cpu_has_mips64r1 | cpu_has_mips64r2)
+#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
+#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
+
+#ifndef cpu_has_dsp
+#define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
+#endif
+
+#ifndef cpu_has_mipsmt
+#define cpu_has_mipsmt          (cpu_data[0].ases & MIPS_ASE_MIPSMT)
+#endif
+
+#ifndef cpu_has_userlocal
+#define cpu_has_userlocal       (cpu_data[0].options & MIPS_CPU_ULRI)
+#endif
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits         (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs          0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses        0
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex                0
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits                 1
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg         1
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs          1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses        1
+# endif
+#endif
+
+#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
+# define cpu_has_vint           (cpu_data[0].options & MIPS_CPU_VINT)
+#elif !defined(cpu_has_vint)
+# define cpu_has_vint                   0
+#endif
+
+#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
+# define cpu_has_veic           (cpu_data[0].options & MIPS_CPU_VEIC)
+#elif !defined(cpu_has_veic)
+# define cpu_has_veic                   0
+#endif
+
+#ifndef cpu_has_inclusive_pcaches
+#define cpu_has_inclusive_pcaches       (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
+#endif
+
+#ifndef cpu_dcache_line_size
+#define cpu_dcache_line_size()  cpu_data[0].dcache.linesz
+#endif
+#ifndef cpu_icache_line_size
+#define cpu_icache_line_size()  cpu_data[0].icache.linesz
+#endif
+#ifndef cpu_scache_line_size
+#define cpu_scache_line_size()  cpu_data[0].scache.linesz
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
new file mode 100644
index 000000000000..744cd8fb107f
--- /dev/null
+++ b/arch/mips/include/asm/cpu-info.h
@@ -0,0 +1,90 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004  Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_INFO_H
+#define __ASM_CPU_INFO_H
+
+#include <linux/types.h>
+
+#include <asm/cache.h>
+
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+        unsigned int waysize;   /* Bytes per way */
+        unsigned short sets;    /* Number of lines per set */
+        unsigned char ways;     /* Number of ways */
+        unsigned char linesz;   /* Size of line in bytes */
+        unsigned char waybit;   /* Bits to select in a cache set */
+        unsigned char flags;    /* Flags describing cache properties */
+};
+
+/*
+ * Flag definitions
+ */
+#define MIPS_CACHE_NOT_PRESENT  0x00000001
+#define MIPS_CACHE_VTAG         0x00000002      /* Virtually tagged cache */
+#define MIPS_CACHE_ALIASES      0x00000004      /* Cache could have aliases */
+#define MIPS_CACHE_IC_F_DC      0x00000008      /* Ic can refill from D-cache */
+#define MIPS_IC_SNOOPS_REMOTE   0x00000010      /* Ic snoops remote stores */
+#define MIPS_CACHE_PINDEX       0x00000020      /* Physically indexed cache */
+
+struct cpuinfo_mips {
+        unsigned long           udelay_val;
+        unsigned long           asid_cache;
+
+        /*
+         * Capability and feature descriptor structure for MIPS CPU
+         */
+        unsigned long           options;
+        unsigned long           ases;
+        unsigned int            processor_id;
+        unsigned int            fpu_id;
+        unsigned int            cputype;
+        int                     isa_level;
+        int                     tlbsize;
+        struct cache_desc       icache; /* Primary I-cache */
+        struct cache_desc       dcache; /* Primary D or combined I/D cache */
+        struct cache_desc       scache; /* Secondary cache */
+        struct cache_desc       tcache; /* Tertiary/split secondary cache */
+        int                     srsets; /* Shadow register sets */
+        int                     core;   /* physical core number */
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
+        /*
+         * In the MIPS MT "SMTC" model, each TC is considered
+         * to be a "CPU" for the purposes of scheduling, but
+         * exception resources, ASID spaces, etc, are common
+         * to all TCs within the same VPE.
+         */
+        int                     vpe_id;  /* Virtual Processor number */
+#endif
+#ifdef CONFIG_MIPS_MT_SMTC
+        int                     tc_id;   /* Thread Context number */
+#endif
+        void                    *data;  /* Additional data */
+        unsigned int            watch_reg_count;   /* Number that exist */
+        unsigned int            watch_reg_use_cnt; /* Usable by ptrace */
+#define NUM_WATCH_REGS 4
+        u16                     watch_reg_masks[NUM_WATCH_REGS];
+} __attribute__((aligned(SMP_CACHE_BYTES)));
+
+extern struct cpuinfo_mips cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
+
+extern void cpu_probe(void);
+extern void cpu_report(void);
+
+extern const char *__cpu_name[];
+#define cpu_name_string()       __cpu_name[smp_processor_id()]
+
+#endif /* __ASM_CPU_INFO_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
new file mode 100644
index 000000000000..229a786101d9
--- /dev/null
+++ b/arch/mips/include/asm/cpu.h
@@ -0,0 +1,267 @@
+/*
+ * cpu.h: Values of the PRId register used to match up
+ *        various MIPS cpu types.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 2004  Maciej W. Rozycki
+ */
+#ifndef _ASM_CPU_H
+#define _ASM_CPU_H
+
+/* Assigned Company values for bits 23:16 of the PRId Register
+   (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
+   MTI, the PRId register is defined in this (backwards compatible)
+   way:
+
+  +----------------+----------------+----------------+----------------+
+  | Company Options| Company ID     | Processor ID   | Revision       |
+  +----------------+----------------+----------------+----------------+
+   31            24 23            16 15             8 7
+
+   I don't have docs for all the previous processors, but my impression is
+   that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
+   spec.
+*/
+
+#define PRID_COMP_LEGACY        0x000000
+#define PRID_COMP_MIPS          0x010000
+#define PRID_COMP_BROADCOM      0x020000
+#define PRID_COMP_ALCHEMY       0x030000
+#define PRID_COMP_SIBYTE        0x040000
+#define PRID_COMP_SANDCRAFT     0x050000
+#define PRID_COMP_NXP           0x060000
+#define PRID_COMP_TOSHIBA       0x070000
+#define PRID_COMP_LSI           0x080000
+#define PRID_COMP_LEXRA         0x0b0000
+
+
+/*
+ * Assigned values for the product ID register.  In order to detect a
+ * certain CPU type exactly eventually additional registers may need to
+ * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
+ */
+#define PRID_IMP_R2000          0x0100
+#define PRID_IMP_AU1_REV1       0x0100
+#define PRID_IMP_AU1_REV2       0x0200
+#define PRID_IMP_R3000          0x0200          /* Same as R2000A  */
+#define PRID_IMP_R6000          0x0300          /* Same as R3000A  */
+#define PRID_IMP_R4000          0x0400
+#define PRID_IMP_R6000A         0x0600
+#define PRID_IMP_R10000         0x0900
+#define PRID_IMP_R4300          0x0b00
+#define PRID_IMP_VR41XX         0x0c00
+#define PRID_IMP_R12000         0x0e00
+#define PRID_IMP_R14000         0x0f00
+#define PRID_IMP_R8000          0x1000
+#define PRID_IMP_PR4450         0x1200
+#define PRID_IMP_R4600          0x2000
+#define PRID_IMP_R4700          0x2100
+#define PRID_IMP_TX39           0x2200
+#define PRID_IMP_R4640          0x2200
+#define PRID_IMP_R4650          0x2200          /* Same as R4640 */
+#define PRID_IMP_R5000          0x2300
+#define PRID_IMP_TX49           0x2d00
+#define PRID_IMP_SONIC          0x2400
+#define PRID_IMP_MAGIC          0x2500
+#define PRID_IMP_RM7000         0x2700
+#define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
+#define PRID_IMP_RM9000         0x3400
+#define PRID_IMP_LOONGSON1      0x4200
+#define PRID_IMP_R5432          0x5400
+#define PRID_IMP_R5500          0x5500
+#define PRID_IMP_LOONGSON2      0x6300
+
+#define PRID_IMP_UNKNOWN        0xff00
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_MIPS
+ */
+
+#define PRID_IMP_4KC            0x8000
+#define PRID_IMP_5KC            0x8100
+#define PRID_IMP_20KC           0x8200
+#define PRID_IMP_4KEC           0x8400
+#define PRID_IMP_4KSC           0x8600
+#define PRID_IMP_25KF           0x8800
+#define PRID_IMP_5KE            0x8900
+#define PRID_IMP_4KECR2         0x9000
+#define PRID_IMP_4KEMPR2        0x9100
+#define PRID_IMP_4KSD           0x9200
+#define PRID_IMP_24K            0x9300
+#define PRID_IMP_34K            0x9500
+#define PRID_IMP_24KE           0x9600
+#define PRID_IMP_74K            0x9700
+#define PRID_IMP_1004K          0x9900
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
+ */
+
+#define PRID_IMP_SB1            0x0100
+#define PRID_IMP_SB1A           0x1100
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
+ */
+
+#define PRID_IMP_SR71000        0x0400
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
+ */
+
+#define PRID_IMP_BCM4710        0x4000
+#define PRID_IMP_BCM3302        0x9000
+
+/*
+ * Definitions for 7:0 on legacy processors
+ */
+
+#define PRID_REV_MASK           0x00ff
+
+#define PRID_REV_TX4927         0x0022
+#define PRID_REV_TX4937         0x0030
+#define PRID_REV_R4400          0x0040
+#define PRID_REV_R3000A         0x0030
+#define PRID_REV_R3000          0x0020
+#define PRID_REV_R2000A         0x0010
+#define PRID_REV_TX3912         0x0010
+#define PRID_REV_TX3922         0x0030
+#define PRID_REV_TX3927         0x0040
+#define PRID_REV_VR4111         0x0050
+#define PRID_REV_VR4181         0x0050  /* Same as VR4111 */
+#define PRID_REV_VR4121         0x0060
+#define PRID_REV_VR4122         0x0070
+#define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
+#define PRID_REV_VR4130         0x0080
+#define PRID_REV_34K_V1_0_2     0x0022
+
+/*
+ * Older processors used to encode processor version and revision in two
+ * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
+ * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
+ * the patch number.  *ARGH*
+ */
+#define PRID_REV_ENCODE_44(ver, rev)                                    \
+        ((ver) << 4 | (rev))
+#define PRID_REV_ENCODE_332(ver, rev, patch)                            \
+        ((ver) << 5 | (rev) << 2 | (patch))
+
+/*
+ * FPU implementation/revision register (CP1 control register 0).
+ *
+ * +---------------------------------+----------------+----------------+
+ * | 0                               | Implementation | Revision       |
+ * +---------------------------------+----------------+----------------+
+ *  31                             16 15             8 7              0
+ */
+
+#define FPIR_IMP_NONE           0x0000
+
+enum cpu_type_enum {
+        CPU_UNKNOWN,
+
+        /*
+         * R2000 class processors
+         */
+        CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
+        CPU_R3081, CPU_R3081E,
+
+        /*
+         * R6000 class processors
+         */
+        CPU_R6000, CPU_R6000A,
+
+        /*
+         * R4000 class processors
+         */
+        CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
+        CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
+        CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
+        CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
+        CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
+        CPU_SR71000, CPU_RM9000, CPU_TX49XX,
+
+        /*
+         * R8000 class processors
+         */
+        CPU_R8000,
+
+        /*
+         * TX3900 class processors
+         */
+        CPU_TX3912, CPU_TX3922, CPU_TX3927,
+
+        /*
+         * MIPS32 class processors
+         */
+        CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
+        CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
+        CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
+
+        /*
+         * MIPS64 class processors
+         */
+        CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
+
+        CPU_LAST
+};
+
+
+/*
+ * ISA Level encodings
+ *
+ */
+#define MIPS_CPU_ISA_I          0x00000001
+#define MIPS_CPU_ISA_II         0x00000002
+#define MIPS_CPU_ISA_III        0x00000004
+#define MIPS_CPU_ISA_IV         0x00000008
+#define MIPS_CPU_ISA_V          0x00000010
+#define MIPS_CPU_ISA_M32R1      0x00000020
+#define MIPS_CPU_ISA_M32R2      0x00000040
+#define MIPS_CPU_ISA_M64R1      0x00000080
+#define MIPS_CPU_ISA_M64R2      0x00000100
+
+#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
+        MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
+#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
+        MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
+
+/*
+ * CPU Option encodings
+ */
+#define MIPS_CPU_TLB            0x00000001 /* CPU has TLB */
+#define MIPS_CPU_4KEX           0x00000002 /* "R4K" exception model */
+#define MIPS_CPU_3K_CACHE       0x00000004 /* R3000-style caches */
+#define MIPS_CPU_4K_CACHE       0x00000008 /* R4000-style caches */
+#define MIPS_CPU_TX39_CACHE     0x00000010 /* TX3900-style caches */
+#define MIPS_CPU_FPU            0x00000020 /* CPU has FPU */
+#define MIPS_CPU_32FPR          0x00000040 /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER        0x00000080 /* Cycle count/compare */
+#define MIPS_CPU_WATCH          0x00000100 /* watchpoint registers */
+#define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
+#define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
+#define MIPS_CPU_CACHE_CDEX_P   0x00000800 /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_CACHE_CDEX_S   0x00001000 /* ... same for seconary cache ... */
+#define MIPS_CPU_MCHECK         0x00002000 /* Machine check exception */
+#define MIPS_CPU_EJTAG          0x00004000 /* EJTAG exception */
+#define MIPS_CPU_NOFPUEX        0x00008000 /* no FPU exception */
+#define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
+#define MIPS_CPU_INCLUSIVE_CACHES       0x00020000 /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
+#define MIPS_CPU_VINT           0x00080000 /* CPU supports MIPSR2 vectored interrupts */
+#define MIPS_CPU_VEIC           0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
+#define MIPS_CPU_ULRI           0x00200000 /* CPU has ULRI feature */
+
+/*
+ * CPU ASE encodings
+ */
+#define MIPS_ASE_MIPS16         0x00000001 /* code compression */
+#define MIPS_ASE_MDMX           0x00000002 /* MIPS digital media extension */
+#define MIPS_ASE_MIPS3D         0x00000004 /* MIPS-3D */
+#define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
+#define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
+#define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
+
+
+#endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/asm/cputime.h b/arch/mips/include/asm/cputime.h
new file mode 100644
index 000000000000..c00eacbdd979
--- /dev/null
+++ b/arch/mips/include/asm/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __MIPS_CPUTIME_H
+#define __MIPS_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __MIPS_CPUTIME_H */
diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h
new file mode 100644
index 000000000000..559db66b9790
--- /dev/null
+++ b/arch/mips/include/asm/current.h
@@ -0,0 +1,23 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2002 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_CURRENT_H
+#define _ASM_CURRENT_H
+
+#include <linux/thread_info.h>
+
+struct task_struct;
+
+static inline struct task_struct * get_current(void)
+{
+        return current_thread_info()->task;
+}
+
+#define current         get_current()
+
+#endif /* _ASM_CURRENT_H */
diff --git a/arch/mips/include/asm/debug.h b/arch/mips/include/asm/debug.h
new file mode 100644
index 000000000000..1fd5a2b39445
--- /dev/null
+++ b/arch/mips/include/asm/debug.h
@@ -0,0 +1,48 @@
+/*
+ * Debug macros for run-time debugging.
+ * Turned on/off with CONFIG_RUNTIME_DEBUG option.
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef _ASM_DEBUG_H
+#define _ASM_DEBUG_H
+
+
+/*
+ * run-time macros for catching spurious errors.  Eable CONFIG_RUNTIME_DEBUG in
+ * kernel hacking config menu to use them.
+ *
+ * Use them as run-time debugging aid.  NEVER USE THEM AS ERROR HANDLING CODE!!!
+ */
+
+#ifdef CONFIG_RUNTIME_DEBUG
+
+#include <linux/kernel.h>
+
+#define db_assert(x)  if (!(x)) { \
+        panic("assertion failed at %s:%d: %s", __FILE__, __LINE__, #x); }
+#define db_warn(x)  if (!(x)) { \
+        printk(KERN_WARNING "warning at %s:%d: %s", __FILE__, __LINE__, #x); }
+#define db_verify(x, y) db_assert(x y)
+#define db_verify_warn(x, y) db_warn(x y)
+#define db_run(x)  do { x; } while (0)
+
+#else
+
+#define db_assert(x)
+#define db_warn(x)
+#define db_verify(x, y) x
+#define db_verify_warn(x, y) x
+#define db_run(x)
+
+#endif
+
+#endif /* _ASM_DEBUG_H */
diff --git a/arch/mips/include/asm/dec/ecc.h b/arch/mips/include/asm/dec/ecc.h
new file mode 100644
index 000000000000..707ffdbc9add
--- /dev/null
+++ b/arch/mips/include/asm/dec/ecc.h
@@ -0,0 +1,55 @@
+/*
+ *      include/asm-mips/dec/ecc.h
+ *
+ *      ECC handling logic definitions common to DECstation/DECsystem
+ *      5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and
+ *      DECsystem 5900 (KN03), 5900/260 (KN05) systems.
+ *
+ *      Copyright (C) 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_ECC_H
+#define __ASM_MIPS_DEC_ECC_H
+
+/*
+ * Error Address Register bits.
+ * The register is r/wc -- any write clears it.
+ */
+#define KN0X_EAR_VALID          (1<<31)         /* error data valid, bus IRQ */
+#define KN0X_EAR_CPU            (1<<30)         /* CPU/DMA transaction */
+#define KN0X_EAR_WRITE          (1<<29)         /* write/read transaction */
+#define KN0X_EAR_ECCERR         (1<<28)         /* ECC/timeout or overrun */
+#define KN0X_EAR_RES_27         (1<<27)         /* unused */
+#define KN0X_EAR_ADDRESS        (0x7ffffff<<0)  /* address involved */
+
+/*
+ * Error Syndrome Register bits.
+ * The register is frozen when EAR.VALID is set, otherwise it records bits
+ * from the last memory read.  The register is r/wc -- any write clears it.
+ */
+#define KN0X_ESR_VLDHI          (1<<31)         /* error data valid hi word */
+#define KN0X_ESR_CHKHI          (0x7f<<24)      /* check bits read from mem */
+#define KN0X_ESR_SNGHI          (1<<23)         /* single/double bit error */
+#define KN0X_ESR_SYNHI          (0x7f<<16)      /* syndrome from ECC logic */
+#define KN0X_ESR_VLDLO          (1<<15)         /* error data valid lo word */
+#define KN0X_ESR_CHKLO          (0x7f<<8)       /* check bits read from mem */
+#define KN0X_ESR_SNGLO          (1<<7)          /* single/double bit error */
+#define KN0X_ESR_SYNLO          (0x7f<<0)       /* syndrome from ECC logic */
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+
+struct pt_regs;
+
+extern void dec_ecc_be_init(void);
+extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id);
+#endif
+
+#endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/arch/mips/include/asm/dec/interrupts.h b/arch/mips/include/asm/dec/interrupts.h
new file mode 100644
index 000000000000..e10d341067c8
--- /dev/null
+++ b/arch/mips/include/asm/dec/interrupts.h
@@ -0,0 +1,126 @@
+/*
+ * Miscellaneous definitions used to initialise the interrupt vector table
+ * with the machine-specific interrupt routines.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 by Paul M. Antoine.
+ * reworked 1998 by Harald Koerfgen.
+ * Copyright (C) 2001, 2002, 2003  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_DEC_INTERRUPTS_H
+#define __ASM_DEC_INTERRUPTS_H
+
+#include <irq.h>
+#include <asm/mipsregs.h>
+
+
+/*
+ * The list of possible system devices which provide an
+ * interrupt.  Not all devices exist on a given system.
+ */
+#define DEC_IRQ_CASCADE         0       /* cascade from CSR or I/O ASIC */
+
+/* Ordinary interrupts */
+#define DEC_IRQ_AB_RECV         1       /* ACCESS.bus receive */
+#define DEC_IRQ_AB_XMIT         2       /* ACCESS.bus transmit */
+#define DEC_IRQ_DZ11            3       /* DZ11 (DC7085) serial */
+#define DEC_IRQ_ASC             4       /* ASC (NCR53C94) SCSI */
+#define DEC_IRQ_FLOPPY          5       /* 82077 FDC */
+#define DEC_IRQ_FPU             6       /* R3k FPU */
+#define DEC_IRQ_HALT            7       /* HALT button or from ACCESS.Bus */
+#define DEC_IRQ_ISDN            8       /* Am79C30A ISDN */
+#define DEC_IRQ_LANCE           9       /* LANCE (Am7990) Ethernet */
+#define DEC_IRQ_BUS             10      /* memory, I/O bus read/write errors */
+#define DEC_IRQ_PSU             11      /* power supply unit warning */
+#define DEC_IRQ_RTC             12      /* DS1287 RTC */
+#define DEC_IRQ_SCC0            13      /* SCC (Z85C30) serial #0 */
+#define DEC_IRQ_SCC1            14      /* SCC (Z85C30) serial #1 */
+#define DEC_IRQ_SII             15      /* SII (DC7061) SCSI */
+#define DEC_IRQ_TC0             16      /* TURBOchannel slot #0 */
+#define DEC_IRQ_TC1             17      /* TURBOchannel slot #1 */
+#define DEC_IRQ_TC2             18      /* TURBOchannel slot #2 */
+#define DEC_IRQ_TIMER           19      /* ARC periodic timer */
+#define DEC_IRQ_VIDEO           20      /* framebuffer */
+
+/* I/O ASIC DMA interrupts */
+#define DEC_IRQ_ASC_MERR        21      /* ASC memory read error */
+#define DEC_IRQ_ASC_ERR         22      /* ASC page overrun */
+#define DEC_IRQ_ASC_DMA         23      /* ASC buffer pointer loaded */
+#define DEC_IRQ_FLOPPY_ERR      24      /* FDC error */
+#define DEC_IRQ_ISDN_ERR        25      /* ISDN memory read/overrun error */
+#define DEC_IRQ_ISDN_RXDMA      26      /* ISDN recv buffer pointer loaded */
+#define DEC_IRQ_ISDN_TXDMA      27      /* ISDN xmit buffer pointer loaded */
+#define DEC_IRQ_LANCE_MERR      28      /* LANCE memory read error */
+#define DEC_IRQ_SCC0A_RXERR     29      /* SCC0A (printer) receive overrun */
+#define DEC_IRQ_SCC0A_RXDMA     30      /* SCC0A receive half page */
+#define DEC_IRQ_SCC0A_TXERR     31      /* SCC0A xmit memory read/overrun */
+#define DEC_IRQ_SCC0A_TXDMA     32      /* SCC0A transmit page end */
+#define DEC_IRQ_AB_RXERR        33      /* ACCESS.bus receive overrun */
+#define DEC_IRQ_AB_RXDMA        34      /* ACCESS.bus receive half page */
+#define DEC_IRQ_AB_TXERR        35      /* ACCESS.bus xmit memory read/ovrn */
+#define DEC_IRQ_AB_TXDMA        36      /* ACCESS.bus transmit page end */
+#define DEC_IRQ_SCC1A_RXERR     37      /* SCC1A (modem) receive overrun */
+#define DEC_IRQ_SCC1A_RXDMA     38      /* SCC1A receive half page */
+#define DEC_IRQ_SCC1A_TXERR     39      /* SCC1A xmit memory read/overrun */
+#define DEC_IRQ_SCC1A_TXDMA     40      /* SCC1A transmit page end */
+
+/* TC5 & TC6 are virtual slots for KN02's onboard devices */
+#define DEC_IRQ_TC5             DEC_IRQ_ASC     /* virtual PMAZ-AA */
+#define DEC_IRQ_TC6             DEC_IRQ_LANCE   /* virtual PMAD-AA */
+
+#define DEC_NR_INTS             41
+
+
+/* Largest of cpu mask_nr tables. */
+#define DEC_MAX_CPU_INTS        6
+/* Largest of asic mask_nr tables. */
+#define DEC_MAX_ASIC_INTS       9
+
+
+/*
+ * CPU interrupt bits common to all systems.
+ */
+#define DEC_CPU_INR_FPU         7       /* R3k FPU */
+#define DEC_CPU_INR_SW1         1       /* software #1 */
+#define DEC_CPU_INR_SW0         0       /* software #0 */
+
+#define DEC_CPU_IRQ_BASE        MIPS_CPU_IRQ_BASE       /* first IRQ assigned to CPU */
+
+#define DEC_CPU_IRQ_NR(n)       ((n) + DEC_CPU_IRQ_BASE)
+#define DEC_CPU_IRQ_MASK(n)     (1 << ((n) + CAUSEB_IP))
+#define DEC_CPU_IRQ_ALL         (0xff << CAUSEB_IP)
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Interrupt table structures to hide differences between systems.
+ */
+typedef union { int i; void *p; } int_ptr;
+extern int dec_interrupt[DEC_NR_INTS];
+extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
+extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
+extern int cpu_fpu_mask;
+
+
+/*
+ * Common interrupt routine prototypes for all DECStations
+ */
+extern void kn02_io_int(void);
+extern void kn02xa_io_int(void);
+extern void kn03_io_int(void);
+extern void asic_dma_int(void);
+extern void asic_all_int(void);
+extern void kn02_all_int(void);
+extern void cpu_all_int(void);
+
+extern void dec_intr_unimplemented(void);
+extern void asic_intr_unimplemented(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h
new file mode 100644
index 000000000000..98badd6bf22d
--- /dev/null
+++ b/arch/mips/include/asm/dec/ioasic.h
@@ -0,0 +1,38 @@
+/*
+ *      include/asm-mips/dec/ioasic.h
+ *
+ *      DEC I/O ASIC access operations.
+ *
+ *      Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_DEC_IOASIC_H
+#define __ASM_DEC_IOASIC_H
+
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+extern spinlock_t ioasic_ssr_lock;
+
+extern volatile u32 *ioasic_base;
+
+static inline void ioasic_write(unsigned int reg, u32 v)
+{
+        ioasic_base[reg / 4] = v;
+}
+
+static inline u32 ioasic_read(unsigned int reg)
+{
+        return ioasic_base[reg / 4];
+}
+
+extern void init_ioasic_irqs(int base);
+
+extern void dec_ioasic_clocksource_init(void);
+
+#endif /* __ASM_DEC_IOASIC_H */
diff --git a/arch/mips/include/asm/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h
new file mode 100644
index 000000000000..4cbc1f8a1129
--- /dev/null
+++ b/arch/mips/include/asm/dec/ioasic_addrs.h
@@ -0,0 +1,152 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Definitions for the address map in the JUNKIO Asic
+ *
+ * Created with Information from:
+ *
+ * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
+ *
+ * and the Mach Sources
+ *
+ * Copyright (C) 199x  the Anonymous
+ * Copyright (C) 2002, 2003  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
+#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
+
+#define IOASIC_SLOT_SIZE 0x00040000
+
+/*
+ * Address ranges decoded by the I/O ASIC for onboard devices.
+ */
+#define IOASIC_SYS_ROM  (0*IOASIC_SLOT_SIZE)    /* system board ROM */
+#define IOASIC_IOCTL    (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
+#define IOASIC_ESAR     (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
+#define IOASIC_LANCE    (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
+#define IOASIC_SCC0     (4*IOASIC_SLOT_SIZE)    /* SCC #0 */
+#define IOASIC_VDAC_HI  (5*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
+#define IOASIC_SCC1     (6*IOASIC_SLOT_SIZE)    /* SCC #1 (3min, 3max+) */
+#define IOASIC_VDAC_LO  (7*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
+#define IOASIC_TOY      (8*IOASIC_SLOT_SIZE)    /* RTC */
+#define IOASIC_ISDN     (9*IOASIC_SLOT_SIZE)    /* ISDN (maxine) */
+#define IOASIC_ERRADDR  (9*IOASIC_SLOT_SIZE)    /* bus error address (3max+) */
+#define IOASIC_CHKSYN   (10*IOASIC_SLOT_SIZE)   /* ECC syndrome (3max+) */
+#define IOASIC_ACC_BUS  (10*IOASIC_SLOT_SIZE)   /* ACCESS.bus (maxine) */
+#define IOASIC_MCR      (11*IOASIC_SLOT_SIZE)   /* memory control (3max+) */
+#define IOASIC_FLOPPY   (11*IOASIC_SLOT_SIZE)   /* FDC (maxine) */
+#define IOASIC_SCSI     (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define IOASIC_FDC_DMA  (13*IOASIC_SLOT_SIZE)   /* FDC DMA (maxine) */
+#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE)   /* ??? */
+#define IOASIC_RES_15   (15*IOASIC_SLOT_SIZE)   /* unused? */
+
+
+/*
+ * Offsets for I/O ASIC registers
+ * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
+ */
+                                        /* all systems */
+#define IO_REG_SCSI_DMA_P       0x00    /* SCSI DMA Pointer */
+#define IO_REG_SCSI_DMA_BP      0x10    /* SCSI DMA Buffer Pointer */
+#define IO_REG_LANCE_DMA_P      0x20    /* LANCE DMA Pointer */
+#define IO_REG_SCC0A_T_DMA_P    0x30    /* SCC0A Transmit DMA Pointer */
+#define IO_REG_SCC0A_R_DMA_P    0x40    /* SCC0A Receive DMA Pointer */
+
+                                        /* except Maxine */
+#define IO_REG_SCC1A_T_DMA_P    0x50    /* SCC1A Transmit DMA Pointer */
+#define IO_REG_SCC1A_R_DMA_P    0x60    /* SCC1A Receive DMA Pointer */
+
+                                        /* Maxine */
+#define IO_REG_AB_T_DMA_P       0x50    /* ACCESS.bus Transmit DMA Pointer */
+#define IO_REG_AB_R_DMA_P       0x60    /* ACCESS.bus Receive DMA Pointer */
+#define IO_REG_FLOPPY_DMA_P     0x70    /* Floppy DMA Pointer */
+#define IO_REG_ISDN_T_DMA_P     0x80    /* ISDN Transmit DMA Pointer */
+#define IO_REG_ISDN_T_DMA_BP    0x90    /* ISDN Transmit DMA Buffer Pointer */
+#define IO_REG_ISDN_R_DMA_P     0xa0    /* ISDN Receive DMA Pointer */
+#define IO_REG_ISDN_R_DMA_BP    0xb0    /* ISDN Receive DMA Buffer Pointer */
+
+                                        /* all systems */
+#define IO_REG_DATA_0           0xc0    /* System Data Buffer 0 */
+#define IO_REG_DATA_1           0xd0    /* System Data Buffer 1 */
+#define IO_REG_DATA_2           0xe0    /* System Data Buffer 2 */
+#define IO_REG_DATA_3           0xf0    /* System Data Buffer 3 */
+
+                                        /* all systems */
+#define IO_REG_SSR              0x100   /* System Support Register */
+#define IO_REG_SIR              0x110   /* System Interrupt Register */
+#define IO_REG_SIMR             0x120   /* System Interrupt Mask Reg. */
+#define IO_REG_SAR              0x130   /* System Address Register */
+
+                                        /* Maxine */
+#define IO_REG_ISDN_T_DATA      0x140   /* ISDN Xmit Data Register */
+#define IO_REG_ISDN_R_DATA      0x150   /* ISDN Receive Data Register */
+
+                                        /* all systems */
+#define IO_REG_LANCE_SLOT       0x160   /* LANCE I/O Slot Register */
+#define IO_REG_SCSI_SLOT        0x170   /* SCSI Slot Register */
+#define IO_REG_SCC0A_SLOT       0x180   /* SCC0A DMA Slot Register */
+
+                                        /* except Maxine */
+#define IO_REG_SCC1A_SLOT       0x190   /* SCC1A DMA Slot Register */
+
+                                        /* Maxine */
+#define IO_REG_AB_SLOT          0x190   /* ACCESS.bus DMA Slot Register */
+#define IO_REG_FLOPPY_SLOT      0x1a0   /* Floppy Slot Register */
+
+                                        /* all systems */
+#define IO_REG_SCSI_SCR         0x1b0   /* SCSI Partial-Word DMA Control */
+#define IO_REG_SCSI_SDR0        0x1c0   /* SCSI DMA Partial Word 0 */
+#define IO_REG_SCSI_SDR1        0x1d0   /* SCSI DMA Partial Word 1 */
+#define IO_REG_FCTR             0x1e0   /* Free-Running Counter */
+#define IO_REG_RES_31           0x1f0   /* unused */
+
+
+/*
+ * The upper 16 bits of the System Support Register are a part of the
+ * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
+ * machines.  The exception is the Maxine, which makes use of the
+ * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
+ * wiring.
+ */
+                                                /* all systems */
+#define IO_SSR_SCC0A_TX_DMA_EN  (1<<31)         /* SCC0A transmit DMA enable */
+#define IO_SSR_SCC0A_RX_DMA_EN  (1<<30)         /* SCC0A receive DMA enable */
+#define IO_SSR_RES_27           (1<<27)         /* unused */
+#define IO_SSR_RES_26           (1<<26)         /* unused */
+#define IO_SSR_RES_25           (1<<25)         /* unused */
+#define IO_SSR_RES_24           (1<<24)         /* unused */
+#define IO_SSR_RES_23           (1<<23)         /* unused */
+#define IO_SSR_SCSI_DMA_DIR     (1<<18)         /* SCSI DMA direction */
+#define IO_SSR_SCSI_DMA_EN      (1<<17)         /* SCSI DMA enable */
+#define IO_SSR_LANCE_DMA_EN     (1<<16)         /* LANCE DMA enable */
+
+                                                /* except Maxine */
+#define IO_SSR_SCC1A_TX_DMA_EN  (1<<29)         /* SCC1A transmit DMA enable */
+#define IO_SSR_SCC1A_RX_DMA_EN  (1<<28)         /* SCC1A receive DMA enable */
+#define IO_SSR_RES_22           (1<<22)         /* unused */
+#define IO_SSR_RES_21           (1<<21)         /* unused */
+#define IO_SSR_RES_20           (1<<20)         /* unused */
+#define IO_SSR_RES_19           (1<<19)         /* unused */
+
+                                                /* Maxine */
+#define IO_SSR_AB_TX_DMA_EN     (1<<29)         /* ACCESS.bus xmit DMA enable */
+#define IO_SSR_AB_RX_DMA_EN     (1<<28)         /* ACCESS.bus recv DMA enable */
+#define IO_SSR_FLOPPY_DMA_DIR   (1<<22)         /* Floppy DMA direction */
+#define IO_SSR_FLOPPY_DMA_EN    (1<<21)         /* Floppy DMA enable */
+#define IO_SSR_ISDN_TX_DMA_EN   (1<<20)         /* ISDN transmit DMA enable */
+#define IO_SSR_ISDN_RX_DMA_EN   (1<<19)         /* ISDN receive DMA enable */
+
+/*
+ * The lower 16 bits are system-specific.  Bits 15,11:8 are common and
+ * defined here.  The rest is defined in system-specific headers.
+ */
+#define KN0X_IO_SSR_DIAGDN      (1<<15)         /* diagnostic jumper */
+#define KN0X_IO_SSR_SCC_RST     (1<<11)         /* ~SCC0,1 (Z85C30) reset */
+#define KN0X_IO_SSR_RTC_RST     (1<<10)         /* ~RTC (DS1287) reset */
+#define KN0X_IO_SSR_ASC_RST     (1<<9)          /* ~ASC (NCR53C94) reset */
+#define KN0X_IO_SSR_LANCE_RST   (1<<8)          /* ~LANCE (Am7990) reset */
+
+#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */
diff --git a/arch/mips/include/asm/dec/ioasic_ints.h b/arch/mips/include/asm/dec/ioasic_ints.h
new file mode 100644
index 000000000000..9aaa9869615f
--- /dev/null
+++ b/arch/mips/include/asm/dec/ioasic_ints.h
@@ -0,0 +1,74 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Definitions for the interrupt related bits in the I/O ASIC
+ * interrupt status register (and the interrupt mask register, of course)
+ *
+ * Created with Information from:
+ *
+ * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
+ *
+ * and the Mach Sources
+ *
+ * Copyright (C) 199x  the Anonymous
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+
+#ifndef __ASM_DEC_IOASIC_INTS_H
+#define __ASM_DEC_IOASIC_INTS_H
+
+/*
+ * The upper 16 bits are a part of the I/O ASIC's internal DMA engine
+ * and thus are common to all I/O ASIC machines.  The exception is
+ * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise
+ * unused) and has a different SCC wiring.
+ */
+                                        /* all systems */
+#define IO_INR_SCC0A_TXDMA      31      /* SCC0A transmit page end */
+#define IO_INR_SCC0A_TXERR      30      /* SCC0A transmit memory read error */
+#define IO_INR_SCC0A_RXDMA      29      /* SCC0A receive half page */
+#define IO_INR_SCC0A_RXERR      28      /* SCC0A receive overrun */
+#define IO_INR_ASC_DMA          19      /* ASC buffer pointer loaded */
+#define IO_INR_ASC_ERR          18      /* ASC page overrun */
+#define IO_INR_ASC_MERR         17      /* ASC memory read error */
+#define IO_INR_LANCE_MERR       16      /* LANCE memory read error */
+
+                                        /* except Maxine */
+#define IO_INR_SCC1A_TXDMA      27      /* SCC1A transmit page end */
+#define IO_INR_SCC1A_TXERR      26      /* SCC1A transmit memory read error */
+#define IO_INR_SCC1A_RXDMA      25      /* SCC1A receive half page */
+#define IO_INR_SCC1A_RXERR      24      /* SCC1A receive overrun */
+#define IO_INR_RES_23           23      /* unused */
+#define IO_INR_RES_22           22      /* unused */
+#define IO_INR_RES_21           21      /* unused */
+#define IO_INR_RES_20           20      /* unused */
+
+                                        /* Maxine */
+#define IO_INR_AB_TXDMA         27      /* ACCESS.bus transmit page end */
+#define IO_INR_AB_TXERR         26      /* ACCESS.bus xmit memory read error */
+#define IO_INR_AB_RXDMA         25      /* ACCESS.bus receive half page */
+#define IO_INR_AB_RXERR         24      /* ACCESS.bus receive overrun */
+#define IO_INR_FLOPPY_ERR       23      /* FDC error */
+#define IO_INR_ISDN_TXDMA       22      /* ISDN xmit buffer pointer loaded */
+#define IO_INR_ISDN_RXDMA       21      /* ISDN recv buffer pointer loaded */
+#define IO_INR_ISDN_ERR         20      /* ISDN memory read/overrun error */
+
+#define IO_INR_DMA              16      /* first DMA IRQ */
+
+/*
+ * The lower 16 bits are system-specific and thus defined in
+ * system-specific headers.
+ */
+
+
+#define IO_IRQ_BASE             8       /* first IRQ assigned to I/O ASIC */
+#define IO_IRQ_LINES            32      /* number of I/O ASIC interrupts */
+
+#define IO_IRQ_NR(n)            ((n) + IO_IRQ_BASE)
+#define IO_IRQ_MASK(n)          (1 << (n))
+#define IO_IRQ_ALL              0x0000ffff
+#define IO_IRQ_DMA              0xffff0000
+
+#endif /* __ASM_DEC_IOASIC_INTS_H */
diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
new file mode 100644
index 000000000000..28fa717ac423
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn01.h
@@ -0,0 +1,90 @@
+/*
+ * Hardware info about DECstation DS2100/3100 systems (otherwise known as
+ * pmin/pmax or KN01).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN01_H
+#define __ASM_MIPS_DEC_KN01_H
+
+#define KN01_SLOT_BASE  0x10000000
+#define KN01_SLOT_SIZE  0x01000000
+
+/*
+ * Address ranges for devices.
+ */
+#define KN01_PMASK      (0*KN01_SLOT_SIZE)      /* color plane mask */
+#define KN01_PCC        (1*KN01_SLOT_SIZE)      /* PCC (DC503) cursor */
+#define KN01_VDAC       (2*KN01_SLOT_SIZE)      /* color map */
+#define KN01_RES_3      (3*KN01_SLOT_SIZE)      /* unused */
+#define KN01_RES_4      (4*KN01_SLOT_SIZE)      /* unused */
+#define KN01_RES_5      (5*KN01_SLOT_SIZE)      /* unused */
+#define KN01_RES_6      (6*KN01_SLOT_SIZE)      /* unused */
+#define KN01_ERRADDR    (7*KN01_SLOT_SIZE)      /* write error address */
+#define KN01_LANCE      (8*KN01_SLOT_SIZE)      /* LANCE (Am7990) Ethernet */
+#define KN01_LANCE_MEM  (9*KN01_SLOT_SIZE)      /* LANCE buffer memory */
+#define KN01_SII        (10*KN01_SLOT_SIZE)     /* SII (DC7061) SCSI */
+#define KN01_SII_MEM    (11*KN01_SLOT_SIZE)     /* SII buffer memory */
+#define KN01_DZ11       (12*KN01_SLOT_SIZE)     /* DZ11 (DC7085) serial */
+#define KN01_RTC        (13*KN01_SLOT_SIZE)     /* DS1287 RTC (bytes #0) */
+#define KN01_ESAR       (13*KN01_SLOT_SIZE)     /* MAC address (bytes #1) */
+#define KN01_CSR        (14*KN01_SLOT_SIZE)     /* system ctrl & status reg */
+#define KN01_SYS_ROM    (15*KN01_SLOT_SIZE)     /* system board ROM */
+
+
+/*
+ * Frame buffer memory address.
+ */
+#define KN01_VFB_MEM    0x0fc00000
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN01_CPU_INR_BUS        6       /* memory, I/O bus read/write errors */
+#define KN01_CPU_INR_VIDEO      6       /* PCC area detect #2 */
+#define KN01_CPU_INR_RTC        5       /* DS1287 RTC */
+#define KN01_CPU_INR_DZ11       4       /* DZ11 (DC7085) serial */
+#define KN01_CPU_INR_LANCE      3       /* LANCE (Am7990) Ethernet */
+#define KN01_CPU_INR_SII        2       /* SII (DC7061) SCSI */
+
+
+/*
+ * System Control & Status Register bits.
+ */
+#define KN01_CSR_MNFMOD         (1<<15) /* MNFMOD manufacturing jumper */
+#define KN01_CSR_STATUS         (1<<14) /* self-test result status output */
+#define KN01_CSR_PARDIS         (1<<13) /* parity error disable */
+#define KN01_CSR_CRSRTST        (1<<12) /* PCC test output */
+#define KN01_CSR_MONO           (1<<11) /* mono/color fb SIMM installed */
+#define KN01_CSR_MEMERR         (1<<10) /* write timeout error status & ack*/
+#define KN01_CSR_VINT           (1<<9)  /* PCC area detect #2 status & ack */
+#define KN01_CSR_TXDIS          (1<<8)  /* DZ11 transmit disable */
+#define KN01_CSR_VBGTRG         (1<<2)  /* blue DAC voltage over green (r/o) */
+#define KN01_CSR_VRGTRG         (1<<1)  /* red DAC voltage over green (r/o) */
+#define KN01_CSR_VRGTRB         (1<<0)  /* red DAC voltage over blue (r/o) */
+#define KN01_CSR_LEDS           (0xff<<0) /* ~diagnostic LEDs (w/o) */
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+struct pt_regs;
+
+extern u16 cached_kn01_csr;
+extern spinlock_t kn01_lock;
+
+extern void dec_kn01_be_init(void);
+extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id);
+#endif
+
+#endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/arch/mips/include/asm/dec/kn02.h b/arch/mips/include/asm/dec/kn02.h
new file mode 100644
index 000000000000..93430b5f4724
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02.h
@@ -0,0 +1,91 @@
+/*
+ * Hardware info about DECstation 5000/200 systems (otherwise known as
+ * 3max or KN02).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN02_H
+#define __ASM_MIPS_DEC_KN02_H
+
+#define KN02_SLOT_BASE  0x1fc00000
+#define KN02_SLOT_SIZE  0x00080000
+
+/*
+ * Address ranges decoded by the "system slot" logic for onboard devices.
+ */
+#define KN02_SYS_ROM    (0*KN02_SLOT_SIZE)      /* system board ROM */
+#define KN02_RES_1      (1*KN02_SLOT_SIZE)      /* unused */
+#define KN02_CHKSYN     (2*KN02_SLOT_SIZE)      /* ECC syndrome */
+#define KN02_ERRADDR    (3*KN02_SLOT_SIZE)      /* bus error address */
+#define KN02_DZ11       (4*KN02_SLOT_SIZE)      /* DZ11 (DC7085) serial */
+#define KN02_RTC        (5*KN02_SLOT_SIZE)      /* DS1287 RTC */
+#define KN02_CSR        (6*KN02_SLOT_SIZE)      /* system ctrl & status reg */
+#define KN02_SYS_ROM_7  (7*KN02_SLOT_SIZE)      /* system board ROM (alias) */
+
+
+/*
+ * System Control & Status Register bits.
+ */
+#define KN02_CSR_RES_28         (0xf<<28)       /* unused */
+#define KN02_CSR_PSU            (1<<27)         /* power supply unit warning */
+#define KN02_CSR_NVRAM          (1<<26)         /* ~NVRAM clear jumper */
+#define KN02_CSR_REFEVEN        (1<<25)         /* mem refresh bank toggle */
+#define KN02_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
+#define KN02_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
+#define KN02_CSR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
+#define KN02_CSR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
+#define KN02_CSR_CORRECT        (1<<13)         /* ECC correct/check */
+#define KN02_CSR_LEDIAG         (1<<12)         /* ECC diagn. latch strobe */
+#define KN02_CSR_TXDIS          (1<<11)         /* DZ11 transmit disable */
+#define KN02_CSR_BNK32M         (1<<10)         /* 32M/8M stride */
+#define KN02_CSR_DIAGDN         (1<<9)          /* DIAGDN manufact. jumper */
+#define KN02_CSR_BAUD38         (1<<8)          /* DZ11 38/19kbps ext. rate */
+#define KN02_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
+#define KN02_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
+
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN02_CPU_INR_RES_6      6       /* unused */
+#define KN02_CPU_INR_BUS        5       /* memory, I/O bus read/write errors */
+#define KN02_CPU_INR_RES_4      4       /* unused */
+#define KN02_CPU_INR_RTC        3       /* DS1287 RTC */
+#define KN02_CPU_INR_CASCADE    2       /* CSR cascade */
+
+/*
+ * CSR interrupt bits.
+ */
+#define KN02_CSR_INR_DZ11       7       /* DZ11 (DC7085) serial */
+#define KN02_CSR_INR_LANCE      6       /* LANCE (Am7990) Ethernet */
+#define KN02_CSR_INR_ASC        5       /* ASC (NCR53C94) SCSI */
+#define KN02_CSR_INR_RES_4      4       /* unused */
+#define KN02_CSR_INR_RES_3      3       /* unused */
+#define KN02_CSR_INR_TC2        2       /* TURBOchannel slot #2 */
+#define KN02_CSR_INR_TC1        1       /* TURBOchannel slot #1 */
+#define KN02_CSR_INR_TC0        0       /* TURBOchannel slot #0 */
+
+
+#define KN02_IRQ_BASE           8       /* first IRQ assigned to CSR */
+#define KN02_IRQ_LINES          8       /* number of CSR interrupts */
+
+#define KN02_IRQ_NR(n)          ((n) + KN02_IRQ_BASE)
+#define KN02_IRQ_MASK(n)        (1 << (n))
+#define KN02_IRQ_ALL            0xff
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+extern u32 cached_kn02_csr;
+extern void init_kn02_irqs(int base);
+#endif
+
+#endif /* __ASM_MIPS_DEC_KN02_H */
diff --git a/arch/mips/include/asm/dec/kn02ba.h b/arch/mips/include/asm/dec/kn02ba.h
new file mode 100644
index 000000000000..c957a4f1b32d
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02ba.h
@@ -0,0 +1,67 @@
+/*
+ *      include/asm-mips/dec/kn02ba.h
+ *
+ *      DECstation 5000/1xx (3min or KN02-BA) definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_KN02BA_H
+#define __ASM_MIPS_DEC_KN02BA_H
+
+#include <asm/dec/kn02xa.h>             /* For common definitions. */
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN02BA_CPU_INR_HALT     6       /* HALT button */
+#define KN02BA_CPU_INR_CASCADE  5       /* I/O ASIC cascade */
+#define KN02BA_CPU_INR_TC2      4       /* TURBOchannel slot #2 */
+#define KN02BA_CPU_INR_TC1      3       /* TURBOchannel slot #1 */
+#define KN02BA_CPU_INR_TC0      2       /* TURBOchannel slot #0 */
+
+/*
+ * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
+ */
+#define KN02BA_IO_INR_RES_15    15      /* unused */
+#define KN02BA_IO_INR_NVRAM     14      /* (*) NVRAM clear jumper */
+#define KN02BA_IO_INR_RES_13    13      /* unused */
+#define KN02BA_IO_INR_BUS       12      /* memory, I/O bus read/write errors */
+#define KN02BA_IO_INR_RES_11    11      /* unused */
+#define KN02BA_IO_INR_NRMOD     10      /* (*) NRMOD manufacturing jumper */
+#define KN02BA_IO_INR_ASC       9       /* ASC (NCR53C94) SCSI */
+#define KN02BA_IO_INR_LANCE     8       /* LANCE (Am7990) Ethernet */
+#define KN02BA_IO_INR_SCC1      7       /* SCC (Z85C30) serial #1 */
+#define KN02BA_IO_INR_SCC0      6       /* SCC (Z85C30) serial #0 */
+#define KN02BA_IO_INR_RTC       5       /* DS1287 RTC */
+#define KN02BA_IO_INR_PSU       4       /* power supply unit warning */
+#define KN02BA_IO_INR_RES_3     3       /* unused */
+#define KN02BA_IO_INR_ASC_DATA  2       /* SCSI data ready (for PIO) */
+#define KN02BA_IO_INR_PBNC      1       /* ~HALT button debouncer */
+#define KN02BA_IO_INR_PBNO      0       /* HALT button debouncer */
+
+
+/*
+ * Memory Error Register bits.
+ */
+#define KN02BA_MER_RES_27       (1<<27)         /* unused */
+
+/*
+ * Memory Size Register bits.
+ */
+#define KN02BA_MSR_RES_17       (0x3ff<<17)     /* unused */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN02BA_IO_SSR_TXDIS1    (1<<14)         /* SCC1 transmit disable */
+#define KN02BA_IO_SSR_TXDIS0    (1<<13)         /* SCC0 transmit disable */
+#define KN02BA_IO_SSR_RES_12    (1<<12)         /* unused */
+
+#define KN02BA_IO_SSR_LEDS      (0xff<<0)       /* ~diagnostic LEDs */
+
+#endif /* __ASM_MIPS_DEC_KN02BA_H */
diff --git a/arch/mips/include/asm/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h
new file mode 100644
index 000000000000..92c0fe256099
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02ca.h
@@ -0,0 +1,79 @@
+/*
+ *      include/asm-mips/dec/kn02ca.h
+ *
+ *      Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_KN02CA_H
+#define __ASM_MIPS_DEC_KN02CA_H
+
+#include <asm/dec/kn02xa.h>             /* For common definitions. */
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN02CA_CPU_INR_HALT     6       /* HALT from ACCESS.Bus */
+#define KN02CA_CPU_INR_CASCADE  5       /* I/O ASIC cascade */
+#define KN02CA_CPU_INR_BUS      4       /* memory, I/O bus read/write errors */
+#define KN02CA_CPU_INR_RTC      3       /* DS1287 RTC */
+#define KN02CA_CPU_INR_TIMER    2       /* ARC periodic timer */
+
+/*
+ * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
+ */
+#define KN02CA_IO_INR_FLOPPY    15      /* 82077 FDC */
+#define KN02CA_IO_INR_NVRAM     14      /* (*) NVRAM clear jumper */
+#define KN02CA_IO_INR_POWERON   13      /* (*) ACCESS.Bus/power-on reset */
+#define KN02CA_IO_INR_TC0       12      /* TURBOchannel slot #0 */
+#define KN02CA_IO_INR_TIMER     12      /* ARC periodic timer (?) */
+#define KN02CA_IO_INR_ISDN      11      /* Am79C30A ISDN */
+#define KN02CA_IO_INR_NRMOD     10      /* (*) NRMOD manufacturing jumper */
+#define KN02CA_IO_INR_ASC       9       /* ASC (NCR53C94) SCSI */
+#define KN02CA_IO_INR_LANCE     8       /* LANCE (Am7990) Ethernet */
+#define KN02CA_IO_INR_HDFLOPPY  7       /* (*) HD (1.44MB) floppy status */
+#define KN02CA_IO_INR_SCC0      6       /* SCC (Z85C30) serial #0 */
+#define KN02CA_IO_INR_TC1       5       /* TURBOchannel slot #1 */
+#define KN02CA_IO_INR_XDFLOPPY  4       /* (*) XD (2.88MB) floppy status */
+#define KN02CA_IO_INR_VIDEO     3       /* framebuffer */
+#define KN02CA_IO_INR_XVIDEO    2       /* ~framebuffer */
+#define KN02CA_IO_INR_AB_XMIT   1       /* ACCESS.bus transmit */
+#define KN02CA_IO_INR_AB_RECV   0       /* ACCESS.bus receive */
+
+
+/*
+ * Memory Error Register bits.
+ */
+#define KN02CA_MER_INTR         (1<<27)         /* ARC IRQ status & ack */
+
+/*
+ * Memory Size Register bits.
+ */
+#define KN02CA_MSR_INTREN       (1<<26)         /* ARC periodic IRQ enable */
+#define KN02CA_MSR_MS10EN       (1<<25)         /* 10/1ms IRQ period select */
+#define KN02CA_MSR_PFORCE       (0xf<<21)       /* byte lane error force */
+#define KN02CA_MSR_MABEN        (1<<20)         /* A side VFB address enable */
+#define KN02CA_MSR_LASTBANK     (0x7<<17)       /* onboard RAM bank # */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN03CA_IO_SSR_RES_14    (1<<14)         /* unused */
+#define KN03CA_IO_SSR_RES_13    (1<<13)         /* unused */
+#define KN03CA_IO_SSR_ISDN_RST  (1<<12)         /* ~ISDN (Am79C30A) reset */
+
+#define KN03CA_IO_SSR_FLOPPY_RST (1<<7)         /* ~FDC (82077) reset */
+#define KN03CA_IO_SSR_VIDEO_RST (1<<6)          /* ~framebuffer reset */
+#define KN03CA_IO_SSR_AB_RST    (1<<5)          /* ACCESS.bus reset */
+#define KN03CA_IO_SSR_RES_4     (1<<4)          /* unused */
+#define KN03CA_IO_SSR_RES_3     (1<<4)          /* unused */
+#define KN03CA_IO_SSR_RES_2     (1<<2)          /* unused */
+#define KN03CA_IO_SSR_RES_1     (1<<1)          /* unused */
+#define KN03CA_IO_SSR_LED       (1<<0)          /* power LED */
+
+#endif /* __ASM_MIPS_DEC_KN02CA_H */
diff --git a/arch/mips/include/asm/dec/kn02xa.h b/arch/mips/include/asm/dec/kn02xa.h
new file mode 100644
index 000000000000..b56b4577f6ef
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn02xa.h
@@ -0,0 +1,84 @@
+/*
+ * Hardware info common to DECstation 5000/1xx systems (otherwise
+ * known as 3min or kn02ba) and Personal DECstations 5000/xx ones
+ * (otherwise known as maxine or kn02ca).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
+ *
+ * These are addresses which have to be known early in the boot process.
+ * For other addresses refer to tc.h, ioasic_addrs.h and friends.
+ */
+#ifndef __ASM_MIPS_DEC_KN02XA_H
+#define __ASM_MIPS_DEC_KN02XA_H
+
+#include <asm/dec/ioasic_addrs.h>
+
+#define KN02XA_SLOT_BASE        0x1c000000
+
+/*
+ * Memory control ASIC registers.
+ */
+#define KN02XA_MER              0x0c400000      /* memory error register */
+#define KN02XA_MSR              0x0c800000      /* memory size register */
+
+/*
+ * CPU control ASIC registers.
+ */
+#define KN02XA_MEM_CONF         0x0e000000      /* write timeout config */
+#define KN02XA_EAR              0x0e000004      /* error address register */
+#define KN02XA_BOOT0            0x0e000008      /* boot 0 register */
+#define KN02XA_MEM_INTR         0x0e00000c      /* write err IRQ stat & ack */
+
+/*
+ * Memory Error Register bits, common definitions.
+ * The rest is defined in system-specific headers.
+ */
+#define KN02XA_MER_RES_28       (0xf<<28)       /* unused */
+#define KN02XA_MER_RES_17       (0x3ff<<17)     /* unused */
+#define KN02XA_MER_PAGERR       (1<<16)         /* 2k page boundary error */
+#define KN02XA_MER_TRANSERR     (1<<15)         /* transfer length error */
+#define KN02XA_MER_PARDIS       (1<<14)         /* parity error disable */
+#define KN02XA_MER_SIZE         (1<<13)         /* r/o mirror of MSR_SIZE */
+#define KN02XA_MER_RES_12       (1<<12)         /* unused */
+#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask: */
+#define KN02XA_MER_BYTERR_3     (0x8<<8)        /* byte lane #3 */
+#define KN02XA_MER_BYTERR_2     (0x4<<8)        /* byte lane #2 */
+#define KN02XA_MER_BYTERR_1     (0x2<<8)        /* byte lane #1 */
+#define KN02XA_MER_BYTERR_0     (0x1<<8)        /* byte lane #0 */
+#define KN02XA_MER_RES_0        (0xff<<0)       /* unused */
+
+/*
+ * Memory Size Register bits, common definitions.
+ * The rest is defined in system-specific headers.
+ */
+#define KN02XA_MSR_RES_27       (0x1f<<27)      /* unused */
+#define KN02XA_MSR_RES_14       (0x7<<14)       /* unused */
+#define KN02XA_MSR_SIZE         (1<<13)         /* 16M/4M stride */
+#define KN02XA_MSR_RES_0        (0x1fff<<0)     /* unused */
+
+/*
+ * Error Address Register bits.
+ */
+#define KN02XA_EAR_RES_29       (0x7<<29)       /* unused */
+#define KN02XA_EAR_ADDRESS      (0x7ffffff<<2)  /* address involved */
+#define KN02XA_EAR_RES_0        (0x3<<0)        /* unused */
+
+
+#ifndef __ASSEMBLY__
+
+#include <linux/interrupt.h>
+
+struct pt_regs;
+
+extern void dec_kn02xa_be_init(void);
+extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
+extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id);
+#endif
+
+#endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/arch/mips/include/asm/dec/kn03.h b/arch/mips/include/asm/dec/kn03.h
new file mode 100644
index 000000000000..edede923ffb8
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn03.h
@@ -0,0 +1,74 @@
+/*
+ * Hardware info about DECstation 5000/2x0 systems (otherwise known as
+ * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which
+ * differ mechanically but are otherwise identical (both are known as
+ * KN03).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
+ * are by courtesy of Chris Fraser.
+ * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
+ */
+#ifndef __ASM_MIPS_DEC_KN03_H
+#define __ASM_MIPS_DEC_KN03_H
+
+#include <asm/dec/ecc.h>
+#include <asm/dec/ioasic_addrs.h>
+
+#define KN03_SLOT_BASE          0x1f800000
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN03_CPU_INR_HALT       6       /* HALT button */
+#define KN03_CPU_INR_BUS        5       /* memory, I/O bus read/write errors */
+#define KN03_CPU_INR_RES_4      4       /* unused */
+#define KN03_CPU_INR_RTC        3       /* DS1287 RTC */
+#define KN03_CPU_INR_CASCADE    2       /* I/O ASIC cascade */
+
+/*
+ * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
+ */
+#define KN03_IO_INR_3MAXP       15      /* (*) 3max+/bigmax ID */
+#define KN03_IO_INR_NVRAM       14      /* (*) NVRAM clear jumper */
+#define KN03_IO_INR_TC2         13      /* TURBOchannel slot #2 */
+#define KN03_IO_INR_TC1         12      /* TURBOchannel slot #1 */
+#define KN03_IO_INR_TC0         11      /* TURBOchannel slot #0 */
+#define KN03_IO_INR_NRMOD       10      /* (*) NRMOD manufacturing jumper */
+#define KN03_IO_INR_ASC         9       /* ASC (NCR53C94) SCSI */
+#define KN03_IO_INR_LANCE       8       /* LANCE (Am7990) Ethernet */
+#define KN03_IO_INR_SCC1        7       /* SCC (Z85C30) serial #1 */
+#define KN03_IO_INR_SCC0        6       /* SCC (Z85C30) serial #0 */
+#define KN03_IO_INR_RTC         5       /* DS1287 RTC */
+#define KN03_IO_INR_PSU         4       /* power supply unit warning */
+#define KN03_IO_INR_RES_3       3       /* unused */
+#define KN03_IO_INR_ASC_DATA    2       /* SCSI data ready (for PIO) */
+#define KN03_IO_INR_PBNC        1       /* ~HALT button debouncer */
+#define KN03_IO_INR_PBNO        0       /* HALT button debouncer */
+
+
+/*
+ * Memory Control Register bits.
+ */
+#define KN03_MCR_RES_16         (0xffff<<16)    /* unused */
+#define KN03_MCR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
+#define KN03_MCR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
+#define KN03_MCR_CORRECT        (1<<13)         /* ECC correct/check */
+#define KN03_MCR_RES_11         (0x3<<12)       /* unused */
+#define KN03_MCR_BNK32M         (1<<10)         /* 32M/8M stride */
+#define KN03_MCR_RES_7          (0x7<<7)        /* unused */
+#define KN03_MCR_CHECK          (0x7f<<0)       /* diagnostic check bits */
+
+/*
+ * I/O ASIC System Support Register bits.
+ */
+#define KN03_IO_SSR_TXDIS1      (1<<14)         /* SCC1 transmit disable */
+#define KN03_IO_SSR_TXDIS0      (1<<13)         /* SCC0 transmit disable */
+#define KN03_IO_SSR_RES_12      (1<<12)         /* unused */
+
+#define KN03_IO_SSR_LEDS        (0xff<<0)       /* ~diagnostic LEDs */
+
+#endif /* __ASM_MIPS_DEC_KN03_H */
diff --git a/arch/mips/include/asm/dec/kn05.h b/arch/mips/include/asm/dec/kn05.h
new file mode 100644
index 000000000000..56d22dc8803a
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn05.h
@@ -0,0 +1,76 @@
+/*
+ *      include/asm-mips/dec/kn05.h
+ *
+ *      DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
+ *      or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
+ *      KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
+ *      definitions.
+ *
+ *      Copyright (C) 2002, 2003, 2005, 2008  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      WARNING!  All this information is pure guesswork based on the
+ *      ROM.  It is provided here in hope it will give someone some
+ *      food for thought.  No documentation for the KN05 nor the KN04
+ *      module has been located so far.
+ */
+#ifndef __ASM_MIPS_DEC_KN05_H
+#define __ASM_MIPS_DEC_KN05_H
+
+#include <asm/dec/ioasic_addrs.h>
+
+/*
+ * The oncard MB (Memory Buffer) ASIC provides an additional address
+ * decoder.  Certain address ranges within the "high" 16 slots are
+ * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
+ * Others are handled locally.  "Low" slots are always passed.
+ */
+#define KN4K_SLOT_BASE  0x1fc00000
+
+#define KN4K_MB_ROM     (0*IOASIC_SLOT_SIZE)    /* KN05/KN04 card ROM */
+#define KN4K_IOCTL      (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
+#define KN4K_ESAR       (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
+#define KN4K_LANCE      (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
+#define KN4K_MB_INT     (4*IOASIC_SLOT_SIZE)    /* MB interrupt register */
+#define KN4K_MB_EA      (5*IOASIC_SLOT_SIZE)    /* MB error address? */
+#define KN4K_MB_EC      (6*IOASIC_SLOT_SIZE)    /* MB error ??? */
+#define KN4K_MB_CSR     (7*IOASIC_SLOT_SIZE)    /* MB control & status */
+#define KN4K_RES_08     (8*IOASIC_SLOT_SIZE)    /* unused? */
+#define KN4K_RES_09     (9*IOASIC_SLOT_SIZE)    /* unused? */
+#define KN4K_RES_10     (10*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_11     (11*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_SCSI       (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define KN4K_RES_13     (13*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_14     (14*IOASIC_SLOT_SIZE)   /* unused? */
+#define KN4K_RES_15     (15*IOASIC_SLOT_SIZE)   /* unused? */
+
+/*
+ * Bits for the MB interrupt register.
+ * The register appears read-only.
+ */
+#define KN4K_MB_INT_TC          (1<<0)          /* TURBOchannel? */
+#define KN4K_MB_INT_RTC         (1<<1)          /* RTC? */
+#define KN4K_MB_INT_MT          (1<<3)          /* I/O ASIC cascade */
+
+/*
+ * Bits for the MB control & status register.
+ * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
+ */
+#define KN4K_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
+#define KN4K_MB_CSR_F           (1<<1)          /* ??? */
+#define KN4K_MB_CSR_ECC         (0xff<<2)       /* ??? */
+#define KN4K_MB_CSR_OD          (1<<10)         /* ??? */
+#define KN4K_MB_CSR_CP          (1<<11)         /* ??? */
+#define KN4K_MB_CSR_UNC         (1<<12)         /* ??? */
+#define KN4K_MB_CSR_IM          (1<<13)         /* ??? */
+#define KN4K_MB_CSR_NC          (1<<14)         /* ??? */
+#define KN4K_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
+#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* CPU Int[4:0] mask */
+#define KN4K_MB_CSR_FW          (1<<21)         /* ??? */
+#define KN4K_MB_CSR_W           (1<<31)         /* ??? */
+
+#endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/arch/mips/include/asm/dec/kn230.h b/arch/mips/include/asm/dec/kn230.h
new file mode 100644
index 000000000000..ff1bf17de8d8
--- /dev/null
+++ b/arch/mips/include/asm/dec/kn230.h
@@ -0,0 +1,26 @@
+/*
+ *      include/asm-mips/dec/kn230.h
+ *
+ *      DECsystem 5100 (MIPSmate or KN230) definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_KN230_H
+#define __ASM_MIPS_DEC_KN230_H
+
+/*
+ * CPU interrupt bits.
+ */
+#define KN230_CPU_INR_HALT      6       /* HALT button */
+#define KN230_CPU_INR_BUS       5       /* memory, I/O bus read/write errors */
+#define KN230_CPU_INR_RTC       4       /* DS1287 RTC */
+#define KN230_CPU_INR_SII       3       /* SII (DC7061) SCSI */
+#define KN230_CPU_INR_LANCE     3       /* LANCE (Am7990) Ethernet */
+#define KN230_CPU_INR_DZ11      2       /* DZ11 (DC7085) serial */
+
+#endif /* __ASM_MIPS_DEC_KN230_H */
diff --git a/arch/mips/include/asm/dec/machtype.h b/arch/mips/include/asm/dec/machtype.h
new file mode 100644
index 000000000000..a6ecdebc430a
--- /dev/null
+++ b/arch/mips/include/asm/dec/machtype.h
@@ -0,0 +1,27 @@
+/*
+ * Various machine type macros
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1998, 2000 Harald Koerfgen
+ */
+
+#ifndef __ASM_DEC_MACHTYPE_H
+#define __ASM_DEC_MACHTYPE_H
+
+#include <asm/bootinfo.h>
+
+#define TURBOCHANNEL    (mips_machtype == MACH_DS5000_200 || \
+                         mips_machtype == MACH_DS5000_1XX || \
+                         mips_machtype == MACH_DS5000_XX  || \
+                         mips_machtype == MACH_DS5000_2X0 || \
+                         mips_machtype == MACH_DS5900)
+
+#define IOASIC          (mips_machtype == MACH_DS5000_1XX || \
+                         mips_machtype == MACH_DS5000_XX  || \
+                         mips_machtype == MACH_DS5000_2X0 || \
+                         mips_machtype == MACH_DS5900)
+
+#endif
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
new file mode 100644
index 000000000000..b9c8203688d5
--- /dev/null
+++ b/arch/mips/include/asm/dec/prom.h
@@ -0,0 +1,174 @@
+/*
+ *      include/asm-mips/dec/prom.h
+ *
+ *      DECstation PROM interface.
+ *
+ *      Copyright (C) 2002  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      Based on arch/mips/dec/prom/prom.h by the Anonymous.
+ */
+#ifndef _ASM_DEC_PROM_H
+#define _ASM_DEC_PROM_H
+
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+
+/*
+ * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
+ * Many of these will work for MIPSen as well!
+ */
+#define VEC_RESET               (u64 *)CKSEG1ADDR(0x1fc00000)
+                                                        /* Prom base address */
+
+#define PMAX_PROM_ENTRY(x)      (VEC_RESET + (x))       /* Prom jump table */
+
+#define PMAX_PROM_HALT          PMAX_PROM_ENTRY(2)      /* valid on MIPSen */
+#define PMAX_PROM_AUTOBOOT      PMAX_PROM_ENTRY(5)      /* valid on MIPSen */
+#define PMAX_PROM_OPEN          PMAX_PROM_ENTRY(6)
+#define PMAX_PROM_READ          PMAX_PROM_ENTRY(7)
+#define PMAX_PROM_CLOSE         PMAX_PROM_ENTRY(10)
+#define PMAX_PROM_LSEEK         PMAX_PROM_ENTRY(11)
+#define PMAX_PROM_GETCHAR       PMAX_PROM_ENTRY(12)
+#define PMAX_PROM_PUTCHAR       PMAX_PROM_ENTRY(13)     /* 12 on MIPSen */
+#define PMAX_PROM_GETS          PMAX_PROM_ENTRY(15)
+#define PMAX_PROM_PRINTF        PMAX_PROM_ENTRY(17)
+#define PMAX_PROM_GETENV        PMAX_PROM_ENTRY(33)     /* valid on MIPSen */
+
+
+/*
+ * Magic number indicating REX PROM available on DECstation.  Found in
+ * register a2 on transfer of control to program from PROM.
+ */
+#define REX_PROM_MAGIC          0x30464354
+
+#ifdef CONFIG_64BIT
+
+#define prom_is_rex(magic)      1       /* KN04 and KN05 are REX PROMs.  */
+
+#else /* !CONFIG_64BIT */
+
+#define prom_is_rex(magic)      ((magic) == REX_PROM_MAGIC)
+
+#endif /* !CONFIG_64BIT */
+
+
+/*
+ * 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
+ * DS5000/2x0.
+ */
+#define REX_PROM_GETBITMAP      0x84/4  /* get mem bitmap */
+#define REX_PROM_GETCHAR        0x24/4  /* getch() */
+#define REX_PROM_GETENV         0x64/4  /* get env. variable */
+#define REX_PROM_GETSYSID       0x80/4  /* get system id */
+#define REX_PROM_GETTCINFO      0xa4/4
+#define REX_PROM_PRINTF         0x30/4  /* printf() */
+#define REX_PROM_SLOTADDR       0x6c/4  /* slotaddr */
+#define REX_PROM_BOOTINIT       0x54/4  /* open() */
+#define REX_PROM_BOOTREAD       0x58/4  /* read() */
+#define REX_PROM_CLEARCACHE     0x7c/4
+
+
+/*
+ * Used by rex_getbitmap().
+ */
+typedef struct {
+        int pagesize;
+        unsigned char bitmap[0];
+} memmap;
+
+
+/*
+ * Function pointers as read from a PROM's callback vector.
+ */
+extern int (*__rex_bootinit)(void);
+extern int (*__rex_bootread)(void);
+extern int (*__rex_getbitmap)(memmap *);
+extern unsigned long *(*__rex_slot_address)(int);
+extern void *(*__rex_gettcinfo)(void);
+extern int (*__rex_getsysid)(void);
+extern void (*__rex_clear_cache)(void);
+
+extern int (*__prom_getchar)(void);
+extern char *(*__prom_getenv)(char *);
+extern int (*__prom_printf)(char *, ...);
+
+extern int (*__pmax_open)(char*, int);
+extern int (*__pmax_lseek)(int, long, int);
+extern int (*__pmax_read)(int, void *, int);
+extern int (*__pmax_close)(int);
+
+
+#ifdef CONFIG_64BIT
+
+/*
+ * On MIPS64 we have to call PROM functions via a helper
+ * dispatcher to accomodate ABI incompatibilities.
+ */
+#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
+                                 __asm__(#fun " = call_o32")
+
+int __DEC_PROM_O32(_rex_bootinit, (int (*)(void)));
+int __DEC_PROM_O32(_rex_bootread, (int (*)(void)));
+int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *));
+unsigned long *__DEC_PROM_O32(_rex_slot_address,
+                             (unsigned long *(*)(int), int));
+void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void)));
+int __DEC_PROM_O32(_rex_getsysid, (int (*)(void)));
+void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void)));
+
+int __DEC_PROM_O32(_prom_getchar, (int (*)(void)));
+char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *));
+int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...));
+
+
+#define rex_bootinit()          _rex_bootinit(__rex_bootinit)
+#define rex_bootread()          _rex_bootread(__rex_bootread)
+#define rex_getbitmap(x)        _rex_getbitmap(__rex_getbitmap, x)
+#define rex_slot_address(x)     _rex_slot_address(__rex_slot_address, x)
+#define rex_gettcinfo()         _rex_gettcinfo(__rex_gettcinfo)
+#define rex_getsysid()          _rex_getsysid(__rex_getsysid)
+#define rex_clear_cache()       _rex_clear_cache(__rex_clear_cache)
+
+#define prom_getchar()          _prom_getchar(__prom_getchar)
+#define prom_getenv(x)          _prom_getenv(__prom_getenv, x)
+#define prom_printf(x...)       _prom_printf(__prom_printf, x)
+
+#else /* !CONFIG_64BIT */
+
+/*
+ * On plain MIPS we just call PROM functions directly.
+ */
+#define rex_bootinit            __rex_bootinit
+#define rex_bootread            __rex_bootread
+#define rex_getbitmap           __rex_getbitmap
+#define rex_slot_address        __rex_slot_address
+#define rex_gettcinfo           __rex_gettcinfo
+#define rex_getsysid            __rex_getsysid
+#define rex_clear_cache         __rex_clear_cache
+
+#define prom_getchar            __prom_getchar
+#define prom_getenv             __prom_getenv
+#define prom_printf             __prom_printf
+
+#define pmax_open               __pmax_open
+#define pmax_lseek              __pmax_lseek
+#define pmax_read               __pmax_read
+#define pmax_close              __pmax_close
+
+#endif /* !CONFIG_64BIT */
+
+
+extern void prom_meminit(u32);
+extern void prom_identify_arch(u32);
+extern void prom_init_cmdline(s32, s32 *, u32);
+
+extern void register_prom_console(void);
+extern void unregister_prom_console(void);
+
+#endif /* _ASM_DEC_PROM_H */
diff --git a/arch/mips/include/asm/dec/system.h b/arch/mips/include/asm/dec/system.h
new file mode 100644
index 000000000000..b2afaccd6831
--- /dev/null
+++ b/arch/mips/include/asm/dec/system.h
@@ -0,0 +1,19 @@
+/*
+ *      include/asm-mips/dec/system.h
+ *
+ *      Generic DECstation/DECsystem bits.
+ *
+ *      Copyright (C) 2005, 2006  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_DEC_SYSTEM_H
+#define __ASM_DEC_SYSTEM_H
+
+extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
+extern int dec_tc_bus;
+
+#endif /* __ASM_DEC_SYSTEM_H */
diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h
new file mode 100644
index 000000000000..b0bccd2c4ed5
--- /dev/null
+++ b/arch/mips/include/asm/delay.h
@@ -0,0 +1,112 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 by Waldorf Electronics
+ * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2007  Maciej W. Rozycki
+ */
+#ifndef _ASM_DELAY_H
+#define _ASM_DELAY_H
+
+#include <linux/param.h>
+#include <linux/smp.h>
+
+#include <asm/compiler.h>
+#include <asm/war.h>
+
+static inline void __delay(unsigned long loops)
+{
+        if (sizeof(long) == 4)
+                __asm__ __volatile__ (
+                "       .set    noreorder                               \n"
+                "       .align  3                                       \n"
+                "1:     bnez    %0, 1b                                  \n"
+                "       subu    %0, 1                                   \n"
+                "       .set    reorder                                 \n"
+                : "=r" (loops)
+                : "0" (loops));
+        else if (sizeof(long) == 8 && !DADDI_WAR)
+                __asm__ __volatile__ (
+                "       .set    noreorder                               \n"
+                "       .align  3                                       \n"
+                "1:     bnez    %0, 1b                                  \n"
+                "       dsubu   %0, 1                                   \n"
+                "       .set    reorder                                 \n"
+                : "=r" (loops)
+                : "0" (loops));
+        else if (sizeof(long) == 8 && DADDI_WAR)
+                __asm__ __volatile__ (
+                "       .set    noreorder                               \n"
+                "       .align  3                                       \n"
+                "1:     bnez    %0, 1b                                  \n"
+                "       dsubu   %0, %2                                  \n"
+                "       .set    reorder                                 \n"
+                : "=r" (loops)
+                : "0" (loops), "r" (1));
+}
+
+
+/*
+ * Division by multiplication: you don't have to worry about
+ * loss of precision.
+ *
+ * Use only for very small delays ( < 1 msec).  Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays.  This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+
+static inline void __udelay(unsigned long usecs, unsigned long lpj)
+{
+        unsigned long hi, lo;
+
+        /*
+         * The rates of 128 is rounded wrongly by the catchall case
+         * for 64-bit.  Excessive precission?  Probably ...
+         */
+#if defined(CONFIG_64BIT) && (HZ == 128)
+        usecs *= 0x0008637bd05af6c7UL;          /* 2**64 / (1000000 / HZ) */
+#elif defined(CONFIG_64BIT)
+        usecs *= (0x8000000000000000UL / (500000 / HZ));
+#else /* 32-bit junk follows here */
+        usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) +
+                                   0x80000000ULL) >> 32);
+#endif
+
+        if (sizeof(long) == 4)
+                __asm__("multu\t%2, %3"
+                : "=h" (usecs), "=l" (lo)
+                : "r" (usecs), "r" (lpj)
+                : GCC_REG_ACCUM);
+        else if (sizeof(long) == 8 && !R4000_WAR)
+                __asm__("dmultu\t%2, %3"
+                : "=h" (usecs), "=l" (lo)
+                : "r" (usecs), "r" (lpj)
+                : GCC_REG_ACCUM);
+        else if (sizeof(long) == 8 && R4000_WAR)
+                __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
+                : "=r" (usecs), "=h" (hi), "=l" (lo)
+                : "r" (usecs), "r" (lpj)
+                : GCC_REG_ACCUM);
+
+        __delay(usecs);
+}
+
+#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
+
+#define udelay(usecs) __udelay((usecs), __udelay_val)
+
+/* make sure "usecs *= ..." in udelay do not overflow. */
+#if HZ >= 1000
+#define MAX_UDELAY_MS   1
+#elif HZ <= 200
+#define MAX_UDELAY_MS   5
+#else
+#define MAX_UDELAY_MS   (1000 / HZ)
+#endif
+
+#endif /* _ASM_DELAY_H */
diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h
new file mode 100644
index 000000000000..d8f9872b0e2d
--- /dev/null
+++ b/arch/mips/include/asm/device.h
@@ -0,0 +1,7 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#include <asm-generic/device.h>
+
diff --git a/arch/mips/include/asm/div64.h b/arch/mips/include/asm/div64.h
new file mode 100644
index 000000000000..d1d699105c11
--- /dev/null
+++ b/arch/mips/include/asm/div64.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2000, 2004  Maciej W. Rozycki
+ * Copyright (C) 2003, 07 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_DIV64_H
+#define _ASM_DIV64_H
+
+#include <linux/types.h>
+
+#if (_MIPS_SZLONG == 32)
+
+#include <asm/compiler.h>
+
+/*
+ * No traps on overflows for any of these...
+ */
+
+#define do_div64_32(res, high, low, base) ({ \
+        unsigned long __quot32, __mod32; \
+        unsigned long __cf, __tmp, __tmp2, __i; \
+        \
+        __asm__(".set   push\n\t" \
+                ".set   noat\n\t" \
+                ".set   noreorder\n\t" \
+                "move   %2, $0\n\t" \
+                "move   %3, $0\n\t" \
+                "b      1f\n\t" \
+                " li    %4, 0x21\n" \
+                "0:\n\t" \
+                "sll    $1, %0, 0x1\n\t" \
+                "srl    %3, %0, 0x1f\n\t" \
+                "or     %0, $1, %5\n\t" \
+                "sll    %1, %1, 0x1\n\t" \
+                "sll    %2, %2, 0x1\n" \
+                "1:\n\t" \
+                "bnez   %3, 2f\n\t" \
+                " sltu  %5, %0, %z6\n\t" \
+                "bnez   %5, 3f\n" \
+                "2:\n\t" \
+                " addiu %4, %4, -1\n\t" \
+                "subu   %0, %0, %z6\n\t" \
+                "addiu  %2, %2, 1\n" \
+                "3:\n\t" \
+                "bnez   %4, 0b\n\t" \
+                " srl   %5, %1, 0x1f\n\t" \
+                ".set   pop" \
+                : "=&r" (__mod32), "=&r" (__tmp), \
+                  "=&r" (__quot32), "=&r" (__cf), \
+                  "=&r" (__i), "=&r" (__tmp2) \
+                : "Jr" (base), "0" (high), "1" (low)); \
+        \
+        (res) = __quot32; \
+        __mod32; })
+
+#define do_div(n, base) ({ \
+        unsigned long long __quot; \
+        unsigned long __mod; \
+        unsigned long long __div; \
+        unsigned long __upper, __low, __high, __base; \
+        \
+        __div = (n); \
+        __base = (base); \
+        \
+        __high = __div >> 32; \
+        __low = __div; \
+        __upper = __high; \
+        \
+        if (__high) \
+                __asm__("divu   $0, %z2, %z3" \
+                        : "=h" (__upper), "=l" (__high) \
+                        : "Jr" (__high), "Jr" (__base) \
+                        : GCC_REG_ACCUM); \
+        \
+        __mod = do_div64_32(__low, __upper, __low, __base); \
+        \
+        __quot = __high; \
+        __quot = __quot << 32 | __low; \
+        (n) = __quot; \
+        __mod; })
+
+#endif /* (_MIPS_SZLONG == 32) */
+
+#if (_MIPS_SZLONG == 64)
+
+/*
+ * Hey, we're already 64-bit, no
+ * need to play games..
+ */
+#define do_div(n, base) ({ \
+        unsigned long __quot; \
+        unsigned int __mod; \
+        unsigned long __div; \
+        unsigned int __base; \
+        \
+        __div = (n); \
+        __base = (base); \
+        \
+        __mod = __div % __base; \
+        __quot = __div / __base; \
+        \
+        (n) = __quot; \
+        __mod; })
+
+#endif /* (_MIPS_SZLONG == 64) */
+
+#endif /* _ASM_DIV64_H */
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..c64afb40cd06
--- /dev/null
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -0,0 +1,81 @@
+#ifndef _ASM_DMA_MAPPING_H
+#define _ASM_DMA_MAPPING_H
+
+#include <asm/scatterlist.h>
+#include <asm/cache.h>
+
+void *dma_alloc_noncoherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, gfp_t flag);
+
+void dma_free_noncoherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, gfp_t flag);
+
+void dma_free_coherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+
+extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
+        enum dma_data_direction direction);
+extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction);
+extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+        enum dma_data_direction direction);
+extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
+        unsigned long offset, size_t size, enum dma_data_direction direction);
+extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+        size_t size, enum dma_data_direction direction);
+extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+        int nhwentries, enum dma_data_direction direction);
+extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
+        size_t size, enum dma_data_direction direction);
+extern void dma_sync_single_for_device(struct device *dev,
+        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
+extern void dma_sync_single_range_for_cpu(struct device *dev,
+        dma_addr_t dma_handle, unsigned long offset, size_t size,
+        enum dma_data_direction direction);
+extern void dma_sync_single_range_for_device(struct device *dev,
+        dma_addr_t dma_handle, unsigned long offset, size_t size,
+        enum dma_data_direction direction);
+extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+        int nelems, enum dma_data_direction direction);
+extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+        int nelems, enum dma_data_direction direction);
+extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
+extern int dma_supported(struct device *dev, u64 mask);
+
+static inline int
+dma_set_mask(struct device *dev, u64 mask)
+{
+        if(!dev->dma_mask || !dma_supported(dev, mask))
+                return -EIO;
+
+        *dev->dma_mask = mask;
+
+        return 0;
+}
+
+static inline int
+dma_get_cache_alignment(void)
+{
+        /* XXX Largest on any MIPS */
+        return 128;
+}
+
+extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr);
+
+extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+               enum dma_data_direction direction);
+
+#if 0
+#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
+
+extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+        dma_addr_t device_addr, size_t size, int flags);
+extern void dma_release_declared_memory(struct device *dev);
+extern void * dma_mark_declared_memory_occupied(struct device *dev,
+        dma_addr_t device_addr, size_t size);
+#endif
+
+#endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
new file mode 100644
index 000000000000..1353c81065d1
--- /dev/null
+++ b/arch/mips/include/asm/dma.h
@@ -0,0 +1,315 @@
+/*
+ * linux/include/asm/dma.h: Defines for using and allocating dma channels.
+ * Written by Hennus Bergman, 1992.
+ * High DMA channel support & info by Hannu Savolainen
+ * and John Boyd, Nov. 1992.
+ *
+ * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
+ * and can only be used for expansion cards. Onboard DMA controllers, such
+ * as the R4030 on Jazz boards behave totally different!
+ */
+
+#ifndef _ASM_DMA_H
+#define _ASM_DMA_H
+
+#include <asm/io.h>                     /* need byte IO */
+#include <linux/spinlock.h>             /* And spinlocks */
+#include <linux/delay.h>
+#include <asm/system.h>
+
+
+#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
+#define dma_outb        outb_p
+#else
+#define dma_outb        outb
+#endif
+
+#define dma_inb         inb
+
+/*
+ * NOTES about DMA transfers:
+ *
+ *  controller 1: channels 0-3, byte operations, ports 00-1F
+ *  controller 2: channels 4-7, word operations, ports C0-DF
+ *
+ *  - ALL registers are 8 bits only, regardless of transfer size
+ *  - channel 4 is not used - cascades 1 into 2.
+ *  - channels 0-3 are byte - addresses/counts are for physical bytes
+ *  - channels 5-7 are word - addresses/counts are for physical words
+ *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
+ *  - transfer count loaded to registers is 1 less than actual count
+ *  - controller 2 offsets are all even (2x offsets for controller 1)
+ *  - page registers for 5-7 don't use data bit 0, represent 128K pages
+ *  - page registers for 0-3 use bit 0, represent 64K pages
+ *
+ * DMA transfers are limited to the lower 16MB of _physical_ memory.
+ * Note that addresses loaded into registers must be _physical_ addresses,
+ * not logical addresses (which may differ if paging is active).
+ *
+ *  Address mapping for channels 0-3:
+ *
+ *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *    |  ...  |   |  ... |   |  ... |
+ *   P7  ...  P0  A7 ... A0  A7 ... A0
+ * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
+ *
+ *  Address mapping for channels 5-7:
+ *
+ *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
+ *    |  ...  |   \   \   ... \  \  \  ... \  \
+ *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
+ *    |  ...  |     \   \   ... \  \  \  ... \
+ *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
+ * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
+ *
+ * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
+ * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
+ * the hardware level, so odd-byte transfers aren't possible).
+ *
+ * Transfer count (_not # bytes_) is limited to 64K, represented as actual
+ * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.
+ *
+ */
+
+#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN
+#define MAX_DMA_CHANNELS        8
+#endif
+
+/*
+ * The maximum address in KSEG0 that we can perform a DMA transfer to on this
+ * platform.  This describes only the PC style part of the DMA logic like on
+ * Deskstations or Acer PICA but not the much more versatile DMA logic used
+ * for the local devices on Acer PICA or Magnums.
+ */
+#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
+/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
+#define MAX_DMA_ADDRESS         PAGE_OFFSET
+#else
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
+#endif
+#define MAX_DMA_PFN             PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+#define MAX_DMA32_PFN           (1UL << (32 - PAGE_SHIFT))
+
+/* 8237 DMA controllers */
+#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
+#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
+
+/* DMA controller registers */
+#define DMA1_CMD_REG            0x08    /* command register (w) */
+#define DMA1_STAT_REG           0x08    /* status register (r) */
+#define DMA1_REQ_REG            0x09    /* request register (w) */
+#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
+#define DMA1_MODE_REG           0x0B    /* mode register (w) */
+#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
+#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
+#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
+#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
+#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
+
+#define DMA2_CMD_REG            0xD0    /* command register (w) */
+#define DMA2_STAT_REG           0xD0    /* status register (r) */
+#define DMA2_REQ_REG            0xD2    /* request register (w) */
+#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
+#define DMA2_MODE_REG           0xD6    /* mode register (w) */
+#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
+#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
+#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
+#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
+#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
+
+#define DMA_ADDR_0              0x00    /* DMA address registers */
+#define DMA_ADDR_1              0x02
+#define DMA_ADDR_2              0x04
+#define DMA_ADDR_3              0x06
+#define DMA_ADDR_4              0xC0
+#define DMA_ADDR_5              0xC4
+#define DMA_ADDR_6              0xC8
+#define DMA_ADDR_7              0xCC
+
+#define DMA_CNT_0               0x01    /* DMA count registers */
+#define DMA_CNT_1               0x03
+#define DMA_CNT_2               0x05
+#define DMA_CNT_3               0x07
+#define DMA_CNT_4               0xC2
+#define DMA_CNT_5               0xC6
+#define DMA_CNT_6               0xCA
+#define DMA_CNT_7               0xCE
+
+#define DMA_PAGE_0              0x87    /* DMA page registers */
+#define DMA_PAGE_1              0x83
+#define DMA_PAGE_2              0x81
+#define DMA_PAGE_3              0x82
+#define DMA_PAGE_5              0x8B
+#define DMA_PAGE_6              0x89
+#define DMA_PAGE_7              0x8A
+
+#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
+#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
+#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
+
+#define DMA_AUTOINIT    0x10
+
+extern spinlock_t  dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&dma_spin_lock, flags);
+        return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(dmanr,  DMA1_MASK_REG);
+        else
+                dma_outb(dmanr & 3,  DMA2_MASK_REG);
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(dmanr | 4,  DMA1_MASK_REG);
+        else
+                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while holding the DMA lock ! ---
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+        if (dmanr<=3)
+                dma_outb(0,  DMA1_CLEAR_FF_REG);
+        else
+                dma_outb(0,  DMA2_CLEAR_FF_REG);
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+        if (dmanr<=3)
+                dma_outb(mode | dmanr,  DMA1_MODE_REG);
+        else
+                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
+}
+
+/* Set only the page register bits of the transfer address.
+ * This is used for successive transfers when we know the contents of
+ * the lower 16 bits of the DMA current address register, but a 64k boundary
+ * may have been crossed.
+ */
+static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
+{
+        switch(dmanr) {
+                case 0:
+                        dma_outb(pagenr, DMA_PAGE_0);
+                        break;
+                case 1:
+                        dma_outb(pagenr, DMA_PAGE_1);
+                        break;
+                case 2:
+                        dma_outb(pagenr, DMA_PAGE_2);
+                        break;
+                case 3:
+                        dma_outb(pagenr, DMA_PAGE_3);
+                        break;
+                case 5:
+                        dma_outb(pagenr & 0xfe, DMA_PAGE_5);
+                        break;
+                case 6:
+                        dma_outb(pagenr & 0xfe, DMA_PAGE_6);
+                        break;
+                case 7:
+                        dma_outb(pagenr & 0xfe, DMA_PAGE_7);
+                        break;
+        }
+}
+
+
+/* Set transfer address & page bits for specific DMA channel.
+ * Assumes dma flipflop is clear.
+ */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+        set_dma_page(dmanr, a>>16);
+        if (dmanr <= 3)  {
+            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+        }  else  {
+            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
+        }
+}
+
+
+/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
+ * a specific DMA channel.
+ * You must ensure the parameters are valid.
+ * NOTE: from a manual: "the number of transfers is one more
+ * than the initial word count"! This is taken into account.
+ * Assumes dma flip-flop is clear.
+ * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        count--;
+        if (dmanr <= 3)  {
+            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
+        } else {
+            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
+        }
+}
+
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ *
+ * Assumes DMA flip-flop is clear.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
+                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
+
+        /* using short to get 16-bit wrap around */
+        unsigned short count;
+
+        count = 1 + dma_inb(io_port);
+        count += dma_inb(io_port) << 8;
+
+        return (dmanr<=3)? count : (count<<1);
+}
+
+
+/* These are in kernel/dma.c: */
+extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
+extern void free_dma(unsigned int dmanr);       /* release it again */
+
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+#endif /* _ASM_DMA_H */
diff --git a/arch/mips/include/asm/ds1286.h b/arch/mips/include/asm/ds1286.h
new file mode 100644
index 000000000000..6983b6ff0af3
--- /dev/null
+++ b/arch/mips/include/asm/ds1286.h
@@ -0,0 +1,15 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Machine dependent access functions for RTC registers.
+ *
+ * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_DS1286_H
+#define _ASM_DS1286_H
+
+#include <ds1286.h>
+
+#endif /* _ASM_DS1286_H */
diff --git a/arch/mips/include/asm/ds1287.h b/arch/mips/include/asm/ds1287.h
new file mode 100644
index 000000000000..ba1702e86931
--- /dev/null
+++ b/arch/mips/include/asm/ds1287.h
@@ -0,0 +1,27 @@
+/*
+ *  DS1287 timer functions.
+ *
+ *  Copyright (C) 2008  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef __ASM_DS1287_H
+#define __ASM_DS1287_H
+
+extern int ds1287_timer_state(void);
+extern void ds1287_set_base_clock(unsigned int clock);
+extern int ds1287_clockevent_init(int irq);
+
+#endif
diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h
new file mode 100644
index 000000000000..e9bfc0813c72
--- /dev/null
+++ b/arch/mips/include/asm/dsp.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2005 Mips Technologies
+ * Author: Chris Dearman, chris@mips.com derived from fpu.h
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_DSP_H
+#define _ASM_DSP_H
+
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/hazards.h>
+#include <asm/mipsregs.h>
+
+#define DSP_DEFAULT     0x00000000
+#define DSP_MASK        0x3ff
+
+#define __enable_dsp_hazard()                                           \
+do {                                                                    \
+        asm("_ehb");                                                    \
+} while (0)
+
+static inline void __init_dsp(void)
+{
+        mthi1(0);
+        mtlo1(0);
+        mthi2(0);
+        mtlo2(0);
+        mthi3(0);
+        mtlo3(0);
+        wrdsp(DSP_DEFAULT, DSP_MASK);
+}
+
+static inline void init_dsp(void)
+{
+        if (cpu_has_dsp)
+                __init_dsp();
+}
+
+#define __save_dsp(tsk)                                                 \
+do {                                                                    \
+        tsk->thread.dsp.dspr[0] = mfhi1();                              \
+        tsk->thread.dsp.dspr[1] = mflo1();                              \
+        tsk->thread.dsp.dspr[2] = mfhi2();                              \
+        tsk->thread.dsp.dspr[3] = mflo2();                              \
+        tsk->thread.dsp.dspr[4] = mfhi3();                              \
+        tsk->thread.dsp.dspr[5] = mflo3();                              \
+        tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK);                   \
+} while (0)
+
+#define save_dsp(tsk)                                                   \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __save_dsp(tsk);                                        \
+} while (0)
+
+#define __restore_dsp(tsk)                                              \
+do {                                                                    \
+        mthi1(tsk->thread.dsp.dspr[0]);                                 \
+        mtlo1(tsk->thread.dsp.dspr[1]);                                 \
+        mthi2(tsk->thread.dsp.dspr[2]);                                 \
+        mtlo2(tsk->thread.dsp.dspr[3]);                                 \
+        mthi3(tsk->thread.dsp.dspr[4]);                                 \
+        mtlo3(tsk->thread.dsp.dspr[5]);                                 \
+        wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK);                    \
+} while (0)
+
+#define restore_dsp(tsk)                                                \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __restore_dsp(tsk);                                     \
+} while (0)
+
+#define __get_dsp_regs(tsk)                                             \
+({                                                                      \
+        if (tsk == current)                                             \
+                __save_dsp(current);                                    \
+                                                                        \
+        tsk->thread.dsp.dspr;                                           \
+})
+
+#endif /* _ASM_DSP_H */
diff --git a/arch/mips/include/asm/edac.h b/arch/mips/include/asm/edac.h
new file mode 100644
index 000000000000..4da0c1fe30d9
--- /dev/null
+++ b/arch/mips/include/asm/edac.h
@@ -0,0 +1,34 @@
+#ifndef ASM_EDAC_H
+#define ASM_EDAC_H
+
+/* ECC atomic, DMA, SMP and interrupt safe scrub function */
+
+static inline void atomic_scrub(void *va, u32 size)
+{
+        unsigned long *virt_addr = va;
+        unsigned long temp;
+        u32 i;
+
+        for (i = 0; i < size / sizeof(unsigned long); i++) {
+                /*
+                 * Very carefully read and write to memory atomically
+                 * so we are interrupt, DMA and SMP safe.
+                 *
+                 * Intel: asm("lock; addl $0, %0"::"m"(*virt_addr));
+                 */
+
+                __asm__ __volatile__ (
+                "       .set    mips2                                   \n"
+                "1:     ll      %0, %1          # atomic_scrub          \n"
+                "       addu    %0, $0                                  \n"
+                "       sc      %0, %1                                  \n"
+                "       beqz    %0, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (temp), "=m" (*virt_addr)
+                : "m" (*virt_addr));
+
+                virt_addr++;
+        }
+}
+
+#endif
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
new file mode 100644
index 000000000000..f69f7acba637
--- /dev/null
+++ b/arch/mips/include/asm/elf.h
@@ -0,0 +1,371 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Much of this is taken from binutils and GNU libc ...
+ */
+#ifndef _ASM_ELF_H
+#define _ASM_ELF_H
+
+
+/* ELF header e_flags defines. */
+/* MIPS architecture level. */
+#define EF_MIPS_ARCH_1          0x00000000      /* -mips1 code.  */
+#define EF_MIPS_ARCH_2          0x10000000      /* -mips2 code.  */
+#define EF_MIPS_ARCH_3          0x20000000      /* -mips3 code.  */
+#define EF_MIPS_ARCH_4          0x30000000      /* -mips4 code.  */
+#define EF_MIPS_ARCH_5          0x40000000      /* -mips5 code.  */
+#define EF_MIPS_ARCH_32         0x50000000      /* MIPS32 code.  */
+#define EF_MIPS_ARCH_64         0x60000000      /* MIPS64 code.  */
+#define EF_MIPS_ARCH_32R2       0x70000000      /* MIPS32 R2 code.  */
+#define EF_MIPS_ARCH_64R2       0x80000000      /* MIPS64 R2 code.  */
+
+/* The ABI of a file. */
+#define EF_MIPS_ABI_O32         0x00001000      /* O32 ABI.  */
+#define EF_MIPS_ABI_O64         0x00002000      /* O32 extended for 64 bit.  */
+
+#define PT_MIPS_REGINFO         0x70000000
+#define PT_MIPS_RTPROC          0x70000001
+#define PT_MIPS_OPTIONS         0x70000002
+
+/* Flags in the e_flags field of the header */
+#define EF_MIPS_NOREORDER       0x00000001
+#define EF_MIPS_PIC             0x00000002
+#define EF_MIPS_CPIC            0x00000004
+#define EF_MIPS_ABI2            0x00000020
+#define EF_MIPS_OPTIONS_FIRST   0x00000080
+#define EF_MIPS_32BITMODE       0x00000100
+#define EF_MIPS_ABI             0x0000f000
+#define EF_MIPS_ARCH            0xf0000000
+
+#define DT_MIPS_RLD_VERSION     0x70000001
+#define DT_MIPS_TIME_STAMP      0x70000002
+#define DT_MIPS_ICHECKSUM       0x70000003
+#define DT_MIPS_IVERSION        0x70000004
+#define DT_MIPS_FLAGS           0x70000005
+        #define RHF_NONE        0x00000000
+        #define RHF_HARDWAY     0x00000001
+        #define RHF_NOTPOT      0x00000002
+        #define RHF_SGI_ONLY    0x00000010
+#define DT_MIPS_BASE_ADDRESS    0x70000006
+#define DT_MIPS_CONFLICT        0x70000008
+#define DT_MIPS_LIBLIST         0x70000009
+#define DT_MIPS_LOCAL_GOTNO     0x7000000a
+#define DT_MIPS_CONFLICTNO      0x7000000b
+#define DT_MIPS_LIBLISTNO       0x70000010
+#define DT_MIPS_SYMTABNO        0x70000011
+#define DT_MIPS_UNREFEXTNO      0x70000012
+#define DT_MIPS_GOTSYM          0x70000013
+#define DT_MIPS_HIPAGENO        0x70000014
+#define DT_MIPS_RLD_MAP         0x70000016
+
+#define R_MIPS_NONE             0
+#define R_MIPS_16               1
+#define R_MIPS_32               2
+#define R_MIPS_REL32            3
+#define R_MIPS_26               4
+#define R_MIPS_HI16             5
+#define R_MIPS_LO16             6
+#define R_MIPS_GPREL16          7
+#define R_MIPS_LITERAL          8
+#define R_MIPS_GOT16            9
+#define R_MIPS_PC16             10
+#define R_MIPS_CALL16           11
+#define R_MIPS_GPREL32          12
+/* The remaining relocs are defined on Irix, although they are not
+   in the MIPS ELF ABI.  */
+#define R_MIPS_UNUSED1          13
+#define R_MIPS_UNUSED2          14
+#define R_MIPS_UNUSED3          15
+#define R_MIPS_SHIFT5           16
+#define R_MIPS_SHIFT6           17
+#define R_MIPS_64               18
+#define R_MIPS_GOT_DISP         19
+#define R_MIPS_GOT_PAGE         20
+#define R_MIPS_GOT_OFST         21
+/*
+ * The following two relocation types are specified in the MIPS ABI
+ * conformance guide version 1.2 but not yet in the psABI.
+ */
+#define R_MIPS_GOTHI16          22
+#define R_MIPS_GOTLO16          23
+#define R_MIPS_SUB              24
+#define R_MIPS_INSERT_A         25
+#define R_MIPS_INSERT_B         26
+#define R_MIPS_DELETE           27
+#define R_MIPS_HIGHER           28
+#define R_MIPS_HIGHEST          29
+/*
+ * The following two relocation types are specified in the MIPS ABI
+ * conformance guide version 1.2 but not yet in the psABI.
+ */
+#define R_MIPS_CALLHI16         30
+#define R_MIPS_CALLLO16         31
+/*
+ * This range is reserved for vendor specific relocations.
+ */
+#define R_MIPS_LOVENDOR         100
+#define R_MIPS_HIVENDOR         127
+
+#define SHN_MIPS_ACCOMON        0xff00          /* Allocated common symbols */
+#define SHN_MIPS_TEXT           0xff01          /* Allocated test symbols.  */
+#define SHN_MIPS_DATA           0xff02          /* Allocated data symbols.  */
+#define SHN_MIPS_SCOMMON        0xff03          /* Small common symbols */
+#define SHN_MIPS_SUNDEFINED     0xff04          /* Small undefined symbols */
+
+#define SHT_MIPS_LIST           0x70000000
+#define SHT_MIPS_CONFLICT       0x70000002
+#define SHT_MIPS_GPTAB          0x70000003
+#define SHT_MIPS_UCODE          0x70000004
+#define SHT_MIPS_DEBUG          0x70000005
+#define SHT_MIPS_REGINFO        0x70000006
+#define SHT_MIPS_PACKAGE        0x70000007
+#define SHT_MIPS_PACKSYM        0x70000008
+#define SHT_MIPS_RELD           0x70000009
+#define SHT_MIPS_IFACE          0x7000000b
+#define SHT_MIPS_CONTENT        0x7000000c
+#define SHT_MIPS_OPTIONS        0x7000000d
+#define SHT_MIPS_SHDR           0x70000010
+#define SHT_MIPS_FDESC          0x70000011
+#define SHT_MIPS_EXTSYM         0x70000012
+#define SHT_MIPS_DENSE          0x70000013
+#define SHT_MIPS_PDESC          0x70000014
+#define SHT_MIPS_LOCSYM         0x70000015
+#define SHT_MIPS_AUXSYM         0x70000016
+#define SHT_MIPS_OPTSYM         0x70000017
+#define SHT_MIPS_LOCSTR         0x70000018
+#define SHT_MIPS_LINE           0x70000019
+#define SHT_MIPS_RFDESC         0x7000001a
+#define SHT_MIPS_DELTASYM       0x7000001b
+#define SHT_MIPS_DELTAINST      0x7000001c
+#define SHT_MIPS_DELTACLASS     0x7000001d
+#define SHT_MIPS_DWARF          0x7000001e
+#define SHT_MIPS_DELTADECL      0x7000001f
+#define SHT_MIPS_SYMBOL_LIB     0x70000020
+#define SHT_MIPS_EVENTS         0x70000021
+#define SHT_MIPS_TRANSLATE      0x70000022
+#define SHT_MIPS_PIXIE          0x70000023
+#define SHT_MIPS_XLATE          0x70000024
+#define SHT_MIPS_XLATE_DEBUG    0x70000025
+#define SHT_MIPS_WHIRL          0x70000026
+#define SHT_MIPS_EH_REGION      0x70000027
+#define SHT_MIPS_XLATE_OLD      0x70000028
+#define SHT_MIPS_PDR_EXCEPTION  0x70000029
+
+#define SHF_MIPS_GPREL          0x10000000
+#define SHF_MIPS_MERGE          0x20000000
+#define SHF_MIPS_ADDR           0x40000000
+#define SHF_MIPS_STRING         0x80000000
+#define SHF_MIPS_NOSTRIP        0x08000000
+#define SHF_MIPS_LOCAL          0x04000000
+#define SHF_MIPS_NAMES          0x02000000
+#define SHF_MIPS_NODUPES        0x01000000
+
+#ifndef ELF_ARCH
+/* ELF register definitions */
+#define ELF_NGREG       45
+#define ELF_NFPREG      33
+
+typedef unsigned long elf_greg_t;
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef double elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+
+#ifdef CONFIG_32BIT
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(hdr)                                             \
+({                                                                      \
+        int __res = 1;                                                  \
+        struct elfhdr *__h = (hdr);                                     \
+                                                                        \
+        if (__h->e_machine != EM_MIPS)                                  \
+                __res = 0;                                              \
+        if (__h->e_ident[EI_CLASS] != ELFCLASS32)                       \
+                __res = 0;                                              \
+        if ((__h->e_flags & EF_MIPS_ABI2) != 0)                         \
+                __res = 0;                                              \
+        if (((__h->e_flags & EF_MIPS_ABI) != 0) &&                      \
+            ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32))          \
+                __res = 0;                                              \
+                                                                        \
+        __res;                                                          \
+})
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS32
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(hdr)                                             \
+({                                                                      \
+        int __res = 1;                                                  \
+        struct elfhdr *__h = (hdr);                                     \
+                                                                        \
+        if (__h->e_machine != EM_MIPS)                                  \
+                __res = 0;                                              \
+        if (__h->e_ident[EI_CLASS] != ELFCLASS64)                       \
+                __res = 0;                                              \
+                                                                        \
+        __res;                                                          \
+})
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS64
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#ifdef __MIPSEB__
+#define ELF_DATA        ELFDATA2MSB
+#elif __MIPSEL__
+#define ELF_DATA        ELFDATA2LSB
+#endif
+#define ELF_ARCH        EM_MIPS
+
+#endif /* !defined(ELF_ARCH) */
+
+struct mips_abi;
+
+extern struct mips_abi mips_abi;
+extern struct mips_abi mips_abi_32;
+extern struct mips_abi mips_abi_n32;
+
+#ifdef CONFIG_32BIT
+
+#define SET_PERSONALITY(ex, ibcs2)                                      \
+do {                                                                    \
+        if (ibcs2)                                                      \
+                set_personality(PER_SVR4);                              \
+        set_personality(PER_LINUX);                                     \
+                                                                        \
+        current->thread.abi = &mips_abi;                                \
+} while (0)
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#ifdef CONFIG_MIPS32_N32
+#define __SET_PERSONALITY32_N32()                                       \
+        do {                                                            \
+                set_thread_flag(TIF_32BIT_ADDR);                        \
+                current->thread.abi = &mips_abi_n32;                    \
+        } while (0)
+#else
+#define __SET_PERSONALITY32_N32()                                       \
+        do { } while (0)
+#endif
+
+#ifdef CONFIG_MIPS32_O32
+#define __SET_PERSONALITY32_O32()                                       \
+        do {                                                            \
+                set_thread_flag(TIF_32BIT_REGS);                        \
+                set_thread_flag(TIF_32BIT_ADDR);                        \
+                current->thread.abi = &mips_abi_32;                     \
+        } while (0)
+#else
+#define __SET_PERSONALITY32_O32()                                       \
+        do { } while (0)
+#endif
+
+#ifdef CONFIG_MIPS32_COMPAT
+#define __SET_PERSONALITY32(ex)                                         \
+do {                                                                    \
+        if ((((ex).e_flags & EF_MIPS_ABI2) != 0) &&                     \
+             ((ex).e_flags & EF_MIPS_ABI) == 0)                         \
+                __SET_PERSONALITY32_N32();                              \
+        else                                                            \
+                __SET_PERSONALITY32_O32();                              \
+} while (0)
+#else
+#define __SET_PERSONALITY32(ex) do { } while (0)
+#endif
+
+#define SET_PERSONALITY(ex, ibcs2)                                      \
+do {                                                                    \
+        clear_thread_flag(TIF_32BIT_REGS);                              \
+        clear_thread_flag(TIF_32BIT_ADDR);                              \
+                                                                        \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)                       \
+                __SET_PERSONALITY32(ex);                                \
+        else                                                            \
+                current->thread.abi = &mips_abi;                        \
+                                                                        \
+        if (ibcs2)                                                      \
+                set_personality(PER_SVR4);                              \
+        else if (current->personality != PER_LINUX32)                   \
+                set_personality(PER_LINUX);                             \
+} while (0)
+
+#endif /* CONFIG_64BIT */
+
+struct task_struct;
+
+extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
+extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
+extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
+
+#define ELF_CORE_COPY_REGS(elf_regs, regs)                      \
+        elf_dump_regs((elf_greg_t *)&(elf_regs), regs);
+#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
+#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs)                   \
+        dump_task_fpu(tsk, elf_fpregs)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  This could be done in userspace,
+   but it's not easy, and we've already done it here.  */
+
+#define ELF_HWCAP       (0)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.
+
+   For the moment, we have only optimizations for the Intel generations,
+   but that could change... */
+
+#define ELF_PLATFORM  (NULL)
+
+/*
+ * See comments in asm-alpha/elf.h, this is the same thing
+ * on the MIPS.
+ */
+#define ELF_PLAT_INIT(_r, load_addr)    do { \
+        _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0;      \
+        _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0;      \
+        _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0;   \
+        _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0;  \
+        _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0;  \
+        _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0;  \
+        _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0;  \
+        _r->regs[30] = _r->regs[31] = 0;                                \
+} while (0)
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#ifndef ELF_ET_DYN_BASE
+#define ELF_ET_DYN_BASE         (TASK_SIZE / 3 * 2)
+#endif
+
+#endif /* _ASM_ELF_H */
diff --git a/arch/mips/include/asm/emergency-restart.h b/arch/mips/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/arch/mips/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/mips/include/asm/emma2rh/emma2rh.h b/arch/mips/include/asm/emma2rh/emma2rh.h
new file mode 100644
index 000000000000..6a1af0af51e3
--- /dev/null
+++ b/arch/mips/include/asm/emma2rh/emma2rh.h
@@ -0,0 +1,333 @@
+/*
+ *  include/asm-mips/emma2rh/emma2rh.h
+ *      This file is EMMA2RH common header.
+ *
+ *  Copyright (C) NEC Electronics Corporation 2005-2006
+ *
+ *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
+ *          Copyright 2001 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_EMMA2RH_EMMA2RH_H
+#define __ASM_EMMA2RH_EMMA2RH_H
+
+#include <irq.h>
+
+/*
+ * EMMA2RH registers
+ */
+#define REGBASE 0x10000000
+
+#define EMMA2RH_BHIF_STRAP_0    (0x000010+REGBASE)
+#define EMMA2RH_BHIF_INT_ST_0   (0x000030+REGBASE)
+#define EMMA2RH_BHIF_INT_ST_1   (0x000034+REGBASE)
+#define EMMA2RH_BHIF_INT_ST_2   (0x000038+REGBASE)
+#define EMMA2RH_BHIF_INT_EN_0   (0x000040+REGBASE)
+#define EMMA2RH_BHIF_INT_EN_1   (0x000044+REGBASE)
+#define EMMA2RH_BHIF_INT_EN_2   (0x000048+REGBASE)
+#define EMMA2RH_BHIF_INT1_EN_0  (0x000050+REGBASE)
+#define EMMA2RH_BHIF_INT1_EN_1  (0x000054+REGBASE)
+#define EMMA2RH_BHIF_INT1_EN_2  (0x000058+REGBASE)
+#define EMMA2RH_BHIF_SW_INT     (0x000070+REGBASE)
+#define EMMA2RH_BHIF_SW_INT_EN  (0x000080+REGBASE)
+#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
+#define EMMA2RH_BHIF_MAIN_CTRL  (0x0000b4+REGBASE)
+#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS   (0x0000c0+REGBASE)
+#define EMMA2RH_GPIO_DIR        (0x110d20+REGBASE)
+#define EMMA2RH_GPIO_INT_ST     (0x110d30+REGBASE)
+#define EMMA2RH_GPIO_INT_MASK   (0x110d3c+REGBASE)
+#define EMMA2RH_GPIO_INT_MODE   (0x110d48+REGBASE)
+#define EMMA2RH_GPIO_INT_CND_A  (0x110d54+REGBASE)
+#define EMMA2RH_GPIO_INT_CND_B  (0x110d60+REGBASE)
+#define EMMA2RH_PBRD_INT_EN     (0x100010+REGBASE)
+#define EMMA2RH_PBRD_CLKSEL     (0x100028+REGBASE)
+#define EMMA2RH_PFUR0_BASE      (0x101000+REGBASE)
+#define EMMA2RH_PFUR1_BASE      (0x102000+REGBASE)
+#define EMMA2RH_PFUR2_BASE      (0x103000+REGBASE)
+#define EMMA2RH_PIIC0_BASE      (0x107000+REGBASE)
+#define EMMA2RH_PIIC1_BASE      (0x108000+REGBASE)
+#define EMMA2RH_PIIC2_BASE      (0x109000+REGBASE)
+#define EMMA2RH_PCI_CONTROL     (0x200000+REGBASE)
+#define EMMA2RH_PCI_ARBIT_CTR   (0x200004+REGBASE)
+#define EMMA2RH_PCI_IWIN0_CTR   (0x200010+REGBASE)
+#define EMMA2RH_PCI_IWIN1_CTR   (0x200014+REGBASE)
+#define EMMA2RH_PCI_INIT_ESWP   (0x200018+REGBASE)
+#define EMMA2RH_PCI_INT         (0x200020+REGBASE)
+#define EMMA2RH_PCI_INT_EN      (0x200024+REGBASE)
+#define EMMA2RH_PCI_TWIN_CTR    (0x200030+REGBASE)
+#define EMMA2RH_PCI_TWIN_BADR   (0x200034+REGBASE)
+#define EMMA2RH_PCI_TWIN0_DADR  (0x200038+REGBASE)
+#define EMMA2RH_PCI_TWIN1_DADR  (0x20003c+REGBASE)
+
+/*
+ *  Memory map (physical address)
+ *
+ *  Note most of the following address must be properly aligned by the
+ *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
+ *  PCI_IO_BASE must be aligned along 16MB boundary.
+ */
+
+/* the actual ram size is detected at run-time */
+#define EMMA2RH_RAM_BASE        0x00000000
+#define EMMA2RH_RAM_SIZE        0x10000000      /* less than 256MB */
+
+#define EMMA2RH_IO_BASE         0x10000000
+#define EMMA2RH_IO_SIZE         0x01000000      /* 16 MB */
+
+#define EMMA2RH_GENERALIO_BASE  0x11000000
+#define EMMA2RH_GENERALIO_SIZE  0x01000000      /* 16 MB */
+
+#define EMMA2RH_PCI_IO_BASE     0x12000000
+#define EMMA2RH_PCI_IO_SIZE     0x02000000      /* 32 MB */
+
+#define EMMA2RH_PCI_MEM_BASE    0x14000000
+#define EMMA2RH_PCI_MEM_SIZE    0x08000000      /* 128 MB */
+
+#define EMMA2RH_ROM_BASE        0x1c000000
+#define EMMA2RH_ROM_SIZE        0x04000000      /* 64 MB */
+
+#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
+#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
+
+#define NUM_CPU_IRQ             8
+#define NUM_EMMA2RH_IRQ         96
+
+#define CPU_EMMA2RH_CASCADE     2
+#define CPU_IRQ_BASE            MIPS_CPU_IRQ_BASE
+#define EMMA2RH_IRQ_BASE        (CPU_IRQ_BASE + NUM_CPU_IRQ)
+
+/*
+ * emma2rh irq defs
+ */
+
+#define EMMA2RH_IRQ_INT0        (0 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT1        (1 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT2        (2 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT3        (3 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT4        (4 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT5        (5 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT6        (6 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT7        (7 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT8        (8 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT9        (9 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT10       (10 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT11       (11 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT12       (12 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT13       (13 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT14       (14 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT15       (15 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT16       (16 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT17       (17 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT18       (18 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT19       (19 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT20       (20 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT21       (21 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT22       (22 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT23       (23 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT24       (24 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT25       (25 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT26       (26 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT27       (27 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT28       (28 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT29       (29 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT30       (30 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT31       (31 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT32       (32 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT33       (33 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT34       (34 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT35       (35 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT36       (36 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT37       (37 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT38       (38 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT39       (39 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT40       (40 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT41       (41 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT42       (42 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT43       (43 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT44       (44 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT45       (45 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT46       (46 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT47       (47 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT48       (48 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT49       (49 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT50       (50 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT51       (51 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT52       (52 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT53       (53 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT54       (54 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT55       (55 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT56       (56 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT57       (57 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT58       (58 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT59       (59 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT60       (60 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT61       (61 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT62       (62 + EMMA2RH_IRQ_BASE)
+#define EMMA2RH_IRQ_INT63       (63 + EMMA2RH_IRQ_BASE)
+
+#define EMMA2RH_IRQ_PFUR0       EMMA2RH_IRQ_INT49
+#define EMMA2RH_IRQ_PFUR1       EMMA2RH_IRQ_INT50
+#define EMMA2RH_IRQ_PFUR2       EMMA2RH_IRQ_INT51
+#define EMMA2RH_IRQ_PIIC0       EMMA2RH_IRQ_INT56
+#define EMMA2RH_IRQ_PIIC1       EMMA2RH_IRQ_INT57
+#define EMMA2RH_IRQ_PIIC2       EMMA2RH_IRQ_INT58
+
+/*
+ *  EMMA2RH Register Access
+ */
+
+#define EMMA2RH_BASE (0xa0000000)
+
+static inline void emma2rh_sync(void)
+{
+        volatile u32 *p = (volatile u32 *)0xbfc00000;
+        (void)(*p);
+}
+
+static inline void emma2rh_out32(u32 offset, u32 val)
+{
+        *(volatile u32 *)(EMMA2RH_BASE | offset) = val;
+        emma2rh_sync();
+}
+
+static inline u32 emma2rh_in32(u32 offset)
+{
+        u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
+        emma2rh_sync();
+        return val;
+}
+
+static inline void emma2rh_out16(u32 offset, u16 val)
+{
+        *(volatile u16 *)(EMMA2RH_BASE | offset) = val;
+        emma2rh_sync();
+}
+
+static inline u16 emma2rh_in16(u32 offset)
+{
+        u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
+        emma2rh_sync();
+        return val;
+}
+
+static inline void emma2rh_out8(u32 offset, u8 val)
+{
+        *(volatile u8 *)(EMMA2RH_BASE | offset) = val;
+        emma2rh_sync();
+}
+
+static inline u8 emma2rh_in8(u32 offset)
+{
+        u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
+        emma2rh_sync();
+        return val;
+}
+
+/**
+ * IIC registers map
+ **/
+
+/*---------------------------------------------------------------------------*/
+/* CNT - Control register (00H R/W)                                          */
+/*---------------------------------------------------------------------------*/
+#define SPT         0x00000001
+#define STT         0x00000002
+#define ACKE        0x00000004
+#define WTIM        0x00000008
+#define SPIE        0x00000010
+#define WREL        0x00000020
+#define LREL        0x00000040
+#define IICE        0x00000080
+#define CNT_RESERVED    0x000000ff      /* reserved bit 0 */
+
+#define I2C_EMMA_START      (IICE | STT)
+#define I2C_EMMA_STOP       (IICE | SPT)
+#define I2C_EMMA_REPSTART   I2C_EMMA_START
+
+/*---------------------------------------------------------------------------*/
+/* STA - Status register (10H Read)                                          */
+/*---------------------------------------------------------------------------*/
+#define MSTS        0x00000080
+#define ALD         0x00000040
+#define EXC         0x00000020
+#define COI         0x00000010
+#define TRC         0x00000008
+#define ACKD        0x00000004
+#define STD         0x00000002
+#define SPD         0x00000001
+
+/*---------------------------------------------------------------------------*/
+/* CSEL - Clock select register (20H R/W)                                    */
+/*---------------------------------------------------------------------------*/
+#define FCL         0x00000080
+#define ND50        0x00000040
+#define CLD         0x00000020
+#define DAD         0x00000010
+#define SMC         0x00000008
+#define DFC         0x00000004
+#define CL          0x00000003
+#define CSEL_RESERVED   0x000000ff      /* reserved bit 0 */
+
+#define FAST397     0x0000008b
+#define FAST297     0x0000008a
+#define FAST347     0x0000000b
+#define FAST260     0x0000000a
+#define FAST130     0x00000008
+#define STANDARD108 0x00000083
+#define STANDARD83  0x00000082
+#define STANDARD95  0x00000003
+#define STANDARD73  0x00000002
+#define STANDARD36  0x00000001
+#define STANDARD71  0x00000000
+
+/*---------------------------------------------------------------------------*/
+/* SVA - Slave address register (30H R/W)                                    */
+/*---------------------------------------------------------------------------*/
+#define SVA         0x000000fe
+
+/*---------------------------------------------------------------------------*/
+/* SHR - Shift register (40H R/W)                                            */
+/*---------------------------------------------------------------------------*/
+#define SR          0x000000ff
+
+/*---------------------------------------------------------------------------*/
+/* INT - Interrupt register (50H R/W)                                        */
+/* INTM - Interrupt mask register (60H R/W)                                  */
+/*---------------------------------------------------------------------------*/
+#define INTE0       0x00000001
+
+/***********************************************************************
+ * I2C registers
+ ***********************************************************************
+ */
+#define I2C_EMMA_CNT            0x00
+#define I2C_EMMA_STA            0x10
+#define I2C_EMMA_CSEL           0x20
+#define I2C_EMMA_SVA            0x30
+#define I2C_EMMA_SHR            0x40
+#define I2C_EMMA_INT            0x50
+#define I2C_EMMA_INTM           0x60
+
+/*
+ * include the board dependent part
+ */
+#if defined(CONFIG_MARKEINS)
+#include <asm/emma2rh/markeins.h>
+#else
+#error "Unknown EMMA2RH board!"
+#endif
+
+#endif /* __ASM_EMMA2RH_EMMA2RH_H */
diff --git a/arch/mips/include/asm/emma2rh/markeins.h b/arch/mips/include/asm/emma2rh/markeins.h
new file mode 100644
index 000000000000..973b0628490d
--- /dev/null
+++ b/arch/mips/include/asm/emma2rh/markeins.h
@@ -0,0 +1,75 @@
+/*
+ *  include/asm-mips/emma2rh/markeins.h
+ *      This file is EMMA2RH board depended header.
+ *
+ *  Copyright (C) NEC Electronics Corporation 2005-2006
+ *
+ *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
+ *          Copyright 2001 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef MARKEINS_H
+#define MARKEINS_H
+
+#define NUM_EMMA2RH_IRQ_SW      32
+#define NUM_EMMA2RH_IRQ_GPIO    32
+
+#define EMMA2RH_SW_CASCADE      (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
+#define EMMA2RH_GPIO_CASCADE    (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
+
+#define EMMA2RH_SW_IRQ_BASE     (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
+#define EMMA2RH_GPIO_IRQ_BASE   (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
+
+#define EMMA2RH_SW_IRQ_INT0     (0+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT1     (1+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT2     (2+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT3     (3+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT4     (4+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT5     (5+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT6     (6+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT7     (7+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT8     (8+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT9     (9+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT10    (10+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT11    (11+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT12    (12+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT13    (13+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT14    (14+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT15    (15+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT16    (16+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT17    (17+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT18    (18+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT19    (19+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT20    (20+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT21    (21+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT22    (22+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT23    (23+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT24    (24+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT25    (25+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT26    (26+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT27    (27+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT28    (28+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT29    (29+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT30    (30+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT31    (31+EMMA2RH_SW_IRQ_BASE)
+
+#define MARKEINS_PCI_IRQ_INTA   EMMA2RH_GPIO_IRQ_BASE+15
+#define MARKEINS_PCI_IRQ_INTB   EMMA2RH_GPIO_IRQ_BASE+16
+#define MARKEINS_PCI_IRQ_INTC   EMMA2RH_GPIO_IRQ_BASE+17
+#define MARKEINS_PCI_IRQ_INTD   EMMA2RH_GPIO_IRQ_BASE+18
+
+#endif /* CONFIG_MARKEINS */
diff --git a/arch/mips/include/asm/errno.h b/arch/mips/include/asm/errno.h
new file mode 100644
index 000000000000..3c0d840e4577
--- /dev/null
+++ b/arch/mips/include/asm/errno.h
@@ -0,0 +1,131 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle
+ */
+#ifndef _ASM_ERRNO_H
+#define _ASM_ERRNO_H
+
+/*
+ * These error numbers are intended to be MIPS ABI compatible
+ */
+
+#include <asm-generic/errno-base.h>
+
+#define ENOMSG          35      /* No message of desired type */
+#define EIDRM           36      /* Identifier removed */
+#define ECHRNG          37      /* Channel number out of range */
+#define EL2NSYNC        38      /* Level 2 not synchronized */
+#define EL3HLT          39      /* Level 3 halted */
+#define EL3RST          40      /* Level 3 reset */
+#define ELNRNG          41      /* Link number out of range */
+#define EUNATCH         42      /* Protocol driver not attached */
+#define ENOCSI          43      /* No CSI structure available */
+#define EL2HLT          44      /* Level 2 halted */
+#define EDEADLK         45      /* Resource deadlock would occur */
+#define ENOLCK          46      /* No record locks available */
+#define EBADE           50      /* Invalid exchange */
+#define EBADR           51      /* Invalid request descriptor */
+#define EXFULL          52      /* Exchange full */
+#define ENOANO          53      /* No anode */
+#define EBADRQC         54      /* Invalid request code */
+#define EBADSLT         55      /* Invalid slot */
+#define EDEADLOCK       56      /* File locking deadlock error */
+#define EBFONT          59      /* Bad font file format */
+#define ENOSTR          60      /* Device not a stream */
+#define ENODATA         61      /* No data available */
+#define ETIME           62      /* Timer expired */
+#define ENOSR           63      /* Out of streams resources */
+#define ENONET          64      /* Machine is not on the network */
+#define ENOPKG          65      /* Package not installed */
+#define EREMOTE         66      /* Object is remote */
+#define ENOLINK         67      /* Link has been severed */
+#define EADV            68      /* Advertise error */
+#define ESRMNT          69      /* Srmount error */
+#define ECOMM           70      /* Communication error on send */
+#define EPROTO          71      /* Protocol error */
+#define EDOTDOT         73      /* RFS specific error */
+#define EMULTIHOP       74      /* Multihop attempted */
+#define EBADMSG         77      /* Not a data message */
+#define ENAMETOOLONG    78      /* File name too long */
+#define EOVERFLOW       79      /* Value too large for defined data type */
+#define ENOTUNIQ        80      /* Name not unique on network */
+#define EBADFD          81      /* File descriptor in bad state */
+#define EREMCHG         82      /* Remote address changed */
+#define ELIBACC         83      /* Can not access a needed shared library */
+#define ELIBBAD         84      /* Accessing a corrupted shared library */
+#define ELIBSCN         85      /* .lib section in a.out corrupted */
+#define ELIBMAX         86      /* Attempting to link in too many shared libraries */
+#define ELIBEXEC        87      /* Cannot exec a shared library directly */
+#define EILSEQ          88      /* Illegal byte sequence */
+#define ENOSYS          89      /* Function not implemented */
+#define ELOOP           90      /* Too many symbolic links encountered */
+#define ERESTART        91      /* Interrupted system call should be restarted */
+#define ESTRPIPE        92      /* Streams pipe error */
+#define ENOTEMPTY       93      /* Directory not empty */
+#define EUSERS          94      /* Too many users */
+#define ENOTSOCK        95      /* Socket operation on non-socket */
+#define EDESTADDRREQ    96      /* Destination address required */
+#define EMSGSIZE        97      /* Message too long */
+#define EPROTOTYPE      98      /* Protocol wrong type for socket */
+#define ENOPROTOOPT     99      /* Protocol not available */
+#define EPROTONOSUPPORT 120     /* Protocol not supported */
+#define ESOCKTNOSUPPORT 121     /* Socket type not supported */
+#define EOPNOTSUPP      122     /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT    123     /* Protocol family not supported */
+#define EAFNOSUPPORT    124     /* Address family not supported by protocol */
+#define EADDRINUSE      125     /* Address already in use */
+#define EADDRNOTAVAIL   126     /* Cannot assign requested address */
+#define ENETDOWN        127     /* Network is down */
+#define ENETUNREACH     128     /* Network is unreachable */
+#define ENETRESET       129     /* Network dropped connection because of reset */
+#define ECONNABORTED    130     /* Software caused connection abort */
+#define ECONNRESET      131     /* Connection reset by peer */
+#define ENOBUFS         132     /* No buffer space available */
+#define EISCONN         133     /* Transport endpoint is already connected */
+#define ENOTCONN        134     /* Transport endpoint is not connected */
+#define EUCLEAN         135     /* Structure needs cleaning */
+#define ENOTNAM         137     /* Not a XENIX named type file */
+#define ENAVAIL         138     /* No XENIX semaphores available */
+#define EISNAM          139     /* Is a named type file */
+#define EREMOTEIO       140     /* Remote I/O error */
+#define EINIT           141     /* Reserved */
+#define EREMDEV         142     /* Error 142 */
+#define ESHUTDOWN       143     /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS    144     /* Too many references: cannot splice */
+#define ETIMEDOUT       145     /* Connection timed out */
+#define ECONNREFUSED    146     /* Connection refused */
+#define EHOSTDOWN       147     /* Host is down */
+#define EHOSTUNREACH    148     /* No route to host */
+#define EWOULDBLOCK     EAGAIN  /* Operation would block */
+#define EALREADY        149     /* Operation already in progress */
+#define EINPROGRESS     150     /* Operation now in progress */
+#define ESTALE          151     /* Stale NFS file handle */
+#define ECANCELED       158     /* AIO operation canceled */
+
+/*
+ * These error are Linux extensions.
+ */
+#define ENOMEDIUM       159     /* No medium found */
+#define EMEDIUMTYPE     160     /* Wrong medium type */
+#define ENOKEY          161     /* Required key not available */
+#define EKEYEXPIRED     162     /* Key has expired */
+#define EKEYREVOKED     163     /* Key has been revoked */
+#define EKEYREJECTED    164     /* Key was rejected by service */
+
+/* for robust mutexes */
+#define EOWNERDEAD      165     /* Owner died */
+#define ENOTRECOVERABLE 166     /* State not recoverable */
+
+#define EDQUOT          1133    /* Quota exceeded */
+
+#ifdef __KERNEL__
+
+/* The biggest error number defined here or in <linux/errno.h>. */
+#define EMAXERRNO       1133
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_ERRNO_H */
diff --git a/arch/mips/include/asm/fb.h b/arch/mips/include/asm/fb.h
new file mode 100644
index 000000000000..bd3f68c9ddfc
--- /dev/null
+++ b/arch/mips/include/asm/fb.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+                                unsigned long off)
+{
+        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+}
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+        return 0;
+}
+
+#endif /* _ASM_FB_H_ */
diff --git a/arch/mips/include/asm/fcntl.h b/arch/mips/include/asm/fcntl.h
new file mode 100644
index 000000000000..2a52333a062d
--- /dev/null
+++ b/arch/mips/include/asm/fcntl.h
@@ -0,0 +1,61 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
+ */
+#ifndef _ASM_FCNTL_H
+#define _ASM_FCNTL_H
+
+
+#define O_APPEND        0x0008
+#define O_SYNC          0x0010
+#define O_NONBLOCK      0x0080
+#define O_CREAT         0x0100  /* not fcntl */
+#define O_TRUNC         0x0200  /* not fcntl */
+#define O_EXCL          0x0400  /* not fcntl */
+#define O_NOCTTY        0x0800  /* not fcntl */
+#define FASYNC          0x1000  /* fcntl, for BSD compatibility */
+#define O_LARGEFILE     0x2000  /* allow large file opens */
+#define O_DIRECT        0x8000  /* direct disk access hint */
+
+#define F_GETLK         14
+#define F_SETLK         6
+#define F_SETLKW        7
+
+#define F_SETOWN        24      /*  for sockets. */
+#define F_GETOWN        23      /*  for sockets. */
+
+#ifndef __mips64
+#define F_GETLK64       33      /*  using 'struct flock64' */
+#define F_SETLK64       34
+#define F_SETLKW64      35
+#endif
+
+/*
+ * The flavours of struct flock.  "struct flock" is the ABI compliant
+ * variant.  Finally struct flock64 is the LFS variant of struct flock.  As
+ * a historic accident and inconsistence with the ABI definition it doesn't
+ * contain all the same fields as struct flock.
+ */
+
+#ifdef CONFIG_32BIT
+
+struct flock {
+        short   l_type;
+        short   l_whence;
+        off_t   l_start;
+        off_t   l_len;
+        long    l_sysid;
+        __kernel_pid_t l_pid;
+        long    pad[4];
+};
+
+#define HAVE_ARCH_STRUCT_FLOCK
+
+#endif /* CONFIG_32BIT */
+
+#include <asm-generic/fcntl.h>
+
+#endif /* _ASM_FCNTL_H */
diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
new file mode 100644
index 000000000000..9cc8522a394f
--- /dev/null
+++ b/arch/mips/include/asm/fixmap.h
@@ -0,0 +1,118 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ */
+
+#ifndef _ASM_FIXMAP_H
+#define _ASM_FIXMAP_H
+
+#include <asm/page.h>
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+/*
+ * Here we define all the compile-time 'special' virtual
+ * addresses. The point is to have a constant address at
+ * compile time, but to set the physical address only
+ * in the boot process. We allocate these special  addresses
+ * from the end of virtual memory (0xfffff000) backwards.
+ * Also this lets us do fail-safe vmalloc(), we
+ * can guarantee that these special addresses and
+ * vmalloc()-ed addresses never overlap.
+ *
+ * these 'compile-time allocated' memory buffers are
+ * fixed-size 4k pages. (or larger if used with an increment
+ * highger than 1) use fixmap_set(idx,phys) to associate
+ * physical memory with fixmap indices.
+ *
+ * TLB entries of such buffers will not be flushed across
+ * task switches.
+ */
+
+/*
+ * on UP currently we will have no trace of the fixmap mechanizm,
+ * no page table allocations, etc. This might change in the
+ * future, say framebuffers for the console driver(s) could be
+ * fix-mapped?
+ */
+enum fixed_addresses {
+#define FIX_N_COLOURS 8
+        FIX_CMAP_BEGIN,
+#ifdef CONFIG_MIPS_MT_SMTC
+        FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS),
+#else
+        FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
+#endif
+#ifdef CONFIG_HIGHMEM
+        /* reserved pte's for temporary kernel mappings */
+        FIX_KMAP_BEGIN = FIX_CMAP_END + 1,
+        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+        __end_of_fixed_addresses
+};
+
+/*
+ * used by vmalloc.c.
+ *
+ * Leave one empty page between vmalloc'ed areas and
+ * the start of the fixmap, and leave one page empty
+ * at the top of mem..
+ */
+#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
+#define FIXADDR_TOP     ((unsigned long)(long)(int)(0xff000000 - 0x20000))
+#else
+#define FIXADDR_TOP     ((unsigned long)(long)(int)0xfffe0000)
+#endif
+#define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
+#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
+
+#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+extern void __this_fixmap_does_not_exist(void);
+
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without tranlation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static inline unsigned long fix_to_virt(const unsigned int idx)
+{
+        /*
+         * this branch gets completely eliminated after inlining,
+         * except when someone tries to use fixaddr indices in an
+         * illegal way. (such as mixing up address types or using
+         * out-of-range indices).
+         *
+         * If it doesn't get removed, the linker will complain
+         * loudly with a reasonably clear error message..
+         */
+        if (idx >= __end_of_fixed_addresses)
+                __this_fixmap_does_not_exist();
+
+        return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+        return __virt_to_fix(vaddr);
+}
+
+/*
+ * Called from pgtable_init()
+ */
+extern void fixrange_init(unsigned long start, unsigned long end,
+        pgd_t *pgd_base);
+
+
+#endif
diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h
new file mode 100644
index 000000000000..992d232adc83
--- /dev/null
+++ b/arch/mips/include/asm/floppy.h
@@ -0,0 +1,56 @@
+/*
+ * Architecture specific parts of the Floppy driver
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 - 2000 Ralf Baechle
+ */
+#ifndef _ASM_FLOPPY_H
+#define _ASM_FLOPPY_H
+
+#include <linux/dma-mapping.h>
+
+static inline void fd_cacheflush(char * addr, long size)
+{
+        dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL);
+}
+
+#define MAX_BUFFER_SECTORS 24
+
+
+/*
+ * And on Mips's the CMOS info fails also ...
+ *
+ * FIXME: This information should come from the ARC configuration tree
+ *        or whereever a particular machine has stored this ...
+ */
+#define FLOPPY0_TYPE            fd_drive_type(0)
+#define FLOPPY1_TYPE            fd_drive_type(1)
+
+#define FDC1                    fd_getfdaddr1();
+
+#define N_FDC 1                 /* do you *really* want a second controller? */
+#define N_DRIVE 8
+
+/*
+ * The DMA channel used by the floppy controller cannot access data at
+ * addresses >= 16MB
+ *
+ * Went back to the 1MB limit, as some people had problems with the floppy
+ * driver otherwise. It doesn't matter much for performance anyway, as most
+ * floppy accesses go through the track buffer.
+ *
+ * On MIPSes using vdma, this actually means that *all* transfers go thru
+ * the * track buffer since 0x1000000 is always smaller than KSEG0/1.
+ * Actually this needs to be a bit more complicated since the so much different
+ * hardware available with MIPS CPUs ...
+ */
+#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
+
+#define EXTRA_FLOPPY_PARAMS
+
+#include <floppy.h>
+
+#endif /* _ASM_FLOPPY_H */
diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h
new file mode 100644
index 000000000000..2b5fddc8f487
--- /dev/null
+++ b/arch/mips/include/asm/fpregdef.h
@@ -0,0 +1,99 @@
+/*
+ * Definitions for the FPU register names
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 Ralf Baechle
+ * Copyright (C) 1985 MIPS Computer Systems, Inc.
+ * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_FPREGDEF_H
+#define _ASM_FPREGDEF_H
+
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * These definitions only cover the R3000-ish 16/32 register model.
+ * But we're trying to be R3000 friendly anyway ...
+ */
+#define fv0     $f0      /* return value */
+#define fv0f    $f1
+#define fv1     $f2
+#define fv1f    $f3
+#define fa0     $f12     /* argument registers */
+#define fa0f    $f13
+#define fa1     $f14
+#define fa1f    $f15
+#define ft0     $f4      /* caller saved */
+#define ft0f    $f5
+#define ft1     $f6
+#define ft1f    $f7
+#define ft2     $f8
+#define ft2f    $f9
+#define ft3     $f10
+#define ft3f    $f11
+#define ft4     $f16
+#define ft4f    $f17
+#define ft5     $f18
+#define ft5f    $f19
+#define fs0     $f20     /* callee saved */
+#define fs0f    $f21
+#define fs1     $f22
+#define fs1f    $f23
+#define fs2     $f24
+#define fs2f    $f25
+#define fs3     $f26
+#define fs3f    $f27
+#define fs4     $f28
+#define fs4f    $f29
+#define fs5     $f30
+#define fs5f    $f31
+
+#define fcr31   $31      /* FPU status register */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define fv0     $f0     /* return value */
+#define fv1     $f2
+#define fa0     $f12    /* argument registers */
+#define fa1     $f13
+#define fa2     $f14
+#define fa3     $f15
+#define fa4     $f16
+#define fa5     $f17
+#define fa6     $f18
+#define fa7     $f19
+#define ft0     $f4     /* caller saved */
+#define ft1     $f5
+#define ft2     $f6
+#define ft3     $f7
+#define ft4     $f8
+#define ft5     $f9
+#define ft6     $f10
+#define ft7     $f11
+#define ft8     $f20
+#define ft9     $f21
+#define ft10    $f22
+#define ft11    $f23
+#define ft12    $f1
+#define ft13    $f3
+#define fs0     $f24    /* callee saved */
+#define fs1     $f25
+#define fs2     $f26
+#define fs3     $f27
+#define fs4     $f28
+#define fs5     $f29
+#define fs6     $f30
+#define fs7     $f31
+
+#define fcr31   $31
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _ASM_FPREGDEF_H */
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
new file mode 100644
index 000000000000..8a3ef247659a
--- /dev/null
+++ b/arch/mips/include/asm/fpu.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2002 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_FPU_H
+#define _ASM_FPU_H
+
+#include <linux/sched.h>
+#include <linux/thread_info.h>
+#include <linux/bitops.h>
+
+#include <asm/mipsregs.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/hazards.h>
+#include <asm/processor.h>
+#include <asm/current.h>
+
+#ifdef CONFIG_MIPS_MT_FPAFF
+#include <asm/mips_mt.h>
+#endif
+
+struct sigcontext;
+struct sigcontext32;
+
+extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
+extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
+
+extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
+extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
+
+extern void fpu_emulator_init_fpu(void);
+extern int fpu_emulator_save_context(struct sigcontext __user *sc);
+extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
+extern void _init_fpu(void);
+extern void _save_fp(struct task_struct *);
+extern void _restore_fp(struct task_struct *);
+
+#define __enable_fpu()                                                  \
+do {                                                                    \
+        set_c0_status(ST0_CU1);                                         \
+        enable_fpu_hazard();                                            \
+} while (0)
+
+#define __disable_fpu()                                                 \
+do {                                                                    \
+        clear_c0_status(ST0_CU1);                                       \
+        disable_fpu_hazard();                                           \
+} while (0)
+
+#define enable_fpu()                                                    \
+do {                                                                    \
+        if (cpu_has_fpu)                                                \
+                __enable_fpu();                                         \
+} while (0)
+
+#define disable_fpu()                                                   \
+do {                                                                    \
+        if (cpu_has_fpu)                                                \
+                __disable_fpu();                                        \
+} while (0)
+
+
+#define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
+
+static inline int __is_fpu_owner(void)
+{
+        return test_thread_flag(TIF_USEDFPU);
+}
+
+static inline int is_fpu_owner(void)
+{
+        return cpu_has_fpu && __is_fpu_owner();
+}
+
+static inline void __own_fpu(void)
+{
+        __enable_fpu();
+        KSTK_STATUS(current) |= ST0_CU1;
+        set_thread_flag(TIF_USEDFPU);
+}
+
+static inline void own_fpu_inatomic(int restore)
+{
+        if (cpu_has_fpu && !__is_fpu_owner()) {
+                __own_fpu();
+                if (restore)
+                        _restore_fp(current);
+        }
+}
+
+static inline void own_fpu(int restore)
+{
+        preempt_disable();
+        own_fpu_inatomic(restore);
+        preempt_enable();
+}
+
+static inline void lose_fpu(int save)
+{
+        preempt_disable();
+        if (is_fpu_owner()) {
+                if (save)
+                        _save_fp(current);
+                KSTK_STATUS(current) &= ~ST0_CU1;
+                clear_thread_flag(TIF_USEDFPU);
+                __disable_fpu();
+        }
+        preempt_enable();
+}
+
+static inline void init_fpu(void)
+{
+        preempt_disable();
+        if (cpu_has_fpu) {
+                __own_fpu();
+                _init_fpu();
+        } else {
+                fpu_emulator_init_fpu();
+        }
+        preempt_enable();
+}
+
+static inline void save_fp(struct task_struct *tsk)
+{
+        if (cpu_has_fpu)
+                _save_fp(tsk);
+}
+
+static inline void restore_fp(struct task_struct *tsk)
+{
+        if (cpu_has_fpu)
+                _restore_fp(tsk);
+}
+
+static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
+{
+        if (tsk == current) {
+                preempt_disable();
+                if (is_fpu_owner())
+                        _save_fp(current);
+                preempt_enable();
+        }
+
+        return tsk->thread.fpu.fpr;
+}
+
+#endif /* _ASM_FPU_H */
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
new file mode 100644
index 000000000000..2731c38bd7ae
--- /dev/null
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -0,0 +1,37 @@
+/*
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Further private data for which no space exists in mips_fpu_struct.
+ * This should be subsumed into the mips_fpu_struct structure as
+ * defined in processor.h as soon as the absurd wired absolute assembler
+ * offsets become dynamic at compile time.
+ *
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ */
+#ifndef _ASM_FPU_EMULATOR_H
+#define _ASM_FPU_EMULATOR_H
+
+struct mips_fpu_emulator_stats {
+        unsigned int emulated;
+        unsigned int loads;
+        unsigned int stores;
+        unsigned int cp1ops;
+        unsigned int cp1xops;
+        unsigned int errors;
+};
+
+extern struct mips_fpu_emulator_stats fpuemustats;
+
+#endif /* _ASM_FPU_EMULATOR_H */
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
new file mode 100644
index 000000000000..b9cce90346cf
--- /dev/null
+++ b/arch/mips/include/asm/futex.h
@@ -0,0 +1,203 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2006  Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/barrier.h>
+#include <asm/errno.h>
+#include <asm/war.h>
+
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)              \
+{                                                                       \
+        if (cpu_has_llsc && R10000_LLSC_WAR) {                          \
+                __asm__ __volatile__(                                   \
+                "       .set    push                            \n"     \
+                "       .set    noat                            \n"     \
+                "       .set    mips3                           \n"     \
+                "1:     ll      %1, %4  # __futex_atomic_op     \n"     \
+                "       .set    mips0                           \n"     \
+                "       " insn  "                               \n"     \
+                "       .set    mips3                           \n"     \
+                "2:     sc      $1, %2                          \n"     \
+                "       beqzl   $1, 1b                          \n"     \
+                __WEAK_LLSC_MB                                          \
+                "3:                                             \n"     \
+                "       .set    pop                             \n"     \
+                "       .set    mips0                           \n"     \
+                "       .section .fixup,\"ax\"                  \n"     \
+                "4:     li      %0, %6                          \n"     \
+                "       j       3b                              \n"     \
+                "       .previous                               \n"     \
+                "       .section __ex_table,\"a\"               \n"     \
+                "       "__UA_ADDR "\t1b, 4b                    \n"     \
+                "       "__UA_ADDR "\t2b, 4b                    \n"     \
+                "       .previous                               \n"     \
+                : "=r" (ret), "=&r" (oldval), "=R" (*uaddr)             \
+                : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)    \
+                : "memory");                                            \
+        } else if (cpu_has_llsc) {                                      \
+                __asm__ __volatile__(                                   \
+                "       .set    push                            \n"     \
+                "       .set    noat                            \n"     \
+                "       .set    mips3                           \n"     \
+                "1:     ll      %1, %4  # __futex_atomic_op     \n"     \
+                "       .set    mips0                           \n"     \
+                "       " insn  "                               \n"     \
+                "       .set    mips3                           \n"     \
+                "2:     sc      $1, %2                          \n"     \
+                "       beqz    $1, 1b                          \n"     \
+                __WEAK_LLSC_MB                                          \
+                "3:                                             \n"     \
+                "       .set    pop                             \n"     \
+                "       .set    mips0                           \n"     \
+                "       .section .fixup,\"ax\"                  \n"     \
+                "4:     li      %0, %6                          \n"     \
+                "       j       3b                              \n"     \
+                "       .previous                               \n"     \
+                "       .section __ex_table,\"a\"               \n"     \
+                "       "__UA_ADDR "\t1b, 4b                    \n"     \
+                "       "__UA_ADDR "\t2b, 4b                    \n"     \
+                "       .previous                               \n"     \
+                : "=r" (ret), "=&r" (oldval), "=R" (*uaddr)             \
+                : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)    \
+                : "memory");                                            \
+        } else                                                          \
+                ret = -ENOSYS;                                          \
+}
+
+static inline int
+futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        pagefault_disable();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+                __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
+                break;
+
+        case FUTEX_OP_ADD:
+                __futex_atomic_op("addu $1, %1, %z5",
+                                  ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_OR:
+                __futex_atomic_op("or   $1, %1, %z5",
+                                  ret, oldval, uaddr, oparg);
+                break;
+        case FUTEX_OP_ANDN:
+                __futex_atomic_op("and  $1, %1, %z5",
+                                  ret, oldval, uaddr, ~oparg);
+                break;
+        case FUTEX_OP_XOR:
+                __futex_atomic_op("xor  $1, %1, %z5",
+                                  ret, oldval, uaddr, oparg);
+                break;
+        default:
+                ret = -ENOSYS;
+        }
+
+        pagefault_enable();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+        int retval;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "# futex_atomic_cmpxchg_inatomic                        \n"
+                "       .set    push                                    \n"
+                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %2                                  \n"
+                "       bne     %0, %z3, 3f                             \n"
+                "       .set    mips0                                   \n"
+                "       move    $1, %z4                                 \n"
+                "       .set    mips3                                   \n"
+                "2:     sc      $1, %1                                  \n"
+                "       beqzl   $1, 1b                                  \n"
+                __WEAK_LLSC_MB
+                "3:                                                     \n"
+                "       .set    pop                                     \n"
+                "       .section .fixup,\"ax\"                          \n"
+                "4:     li      %0, %5                                  \n"
+                "       j       3b                                      \n"
+                "       .previous                                       \n"
+                "       .section __ex_table,\"a\"                       \n"
+                "       "__UA_ADDR "\t1b, 4b                            \n"
+                "       "__UA_ADDR "\t2b, 4b                            \n"
+                "       .previous                                       \n"
+                : "=&r" (retval), "=R" (*uaddr)
+                : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "# futex_atomic_cmpxchg_inatomic                        \n"
+                "       .set    push                                    \n"
+                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %2                                  \n"
+                "       bne     %0, %z3, 3f                             \n"
+                "       .set    mips0                                   \n"
+                "       move    $1, %z4                                 \n"
+                "       .set    mips3                                   \n"
+                "2:     sc      $1, %1                                  \n"
+                "       beqz    $1, 1b                                  \n"
+                __WEAK_LLSC_MB
+                "3:                                                     \n"
+                "       .set    pop                                     \n"
+                "       .section .fixup,\"ax\"                          \n"
+                "4:     li      %0, %5                                  \n"
+                "       j       3b                                      \n"
+                "       .previous                                       \n"
+                "       .section __ex_table,\"a\"                       \n"
+                "       "__UA_ADDR "\t1b, 4b                            \n"
+                "       "__UA_ADDR "\t2b, 4b                            \n"
+                "       .previous                                       \n"
+                : "=&r" (retval), "=R" (*uaddr)
+                : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
+                : "memory");
+        } else
+                return -ENOSYS;
+
+        return retval;
+}
+
+#endif
+#endif /* _ASM_FUTEX_H */
diff --git a/arch/mips/include/asm/fw/arc/hinv.h b/arch/mips/include/asm/fw/arc/hinv.h
new file mode 100644
index 000000000000..e6ff4add04e2
--- /dev/null
+++ b/arch/mips/include/asm/fw/arc/hinv.h
@@ -0,0 +1,175 @@
+/*
+ * ARCS hardware/memory inventory/configuration and system ID definitions.
+ */
+#ifndef _ASM_ARC_HINV_H
+#define _ASM_ARC_HINV_H
+
+#include <asm/sgidefs.h>
+#include <asm/fw/arc/types.h>
+
+/* configuration query defines */
+typedef enum configclass {
+        SystemClass,
+        ProcessorClass,
+        CacheClass,
+#ifndef _NT_PROM
+        MemoryClass,
+        AdapterClass,
+        ControllerClass,
+        PeripheralClass
+#else   /* _NT_PROM */
+        AdapterClass,
+        ControllerClass,
+        PeripheralClass,
+        MemoryClass
+#endif  /* _NT_PROM */
+} CONFIGCLASS;
+
+typedef enum configtype {
+        ARC,
+        CPU,
+        FPU,
+        PrimaryICache,
+        PrimaryDCache,
+        SecondaryICache,
+        SecondaryDCache,
+        SecondaryCache,
+#ifndef _NT_PROM
+        Memory,
+#endif
+        EISAAdapter,
+        TCAdapter,
+        SCSIAdapter,
+        DTIAdapter,
+        MultiFunctionAdapter,
+        DiskController,
+        TapeController,
+        CDROMController,
+        WORMController,
+        SerialController,
+        NetworkController,
+        DisplayController,
+        ParallelController,
+        PointerController,
+        KeyboardController,
+        AudioController,
+        OtherController,
+        DiskPeripheral,
+        FloppyDiskPeripheral,
+        TapePeripheral,
+        ModemPeripheral,
+        MonitorPeripheral,
+        PrinterPeripheral,
+        PointerPeripheral,
+        KeyboardPeripheral,
+        TerminalPeripheral,
+        LinePeripheral,
+        NetworkPeripheral,
+#ifdef  _NT_PROM
+        Memory,
+#endif
+        OtherPeripheral,
+
+        /* new stuff for IP30 */
+        /* added without moving anything */
+        /* except ANONYMOUS. */
+
+        XTalkAdapter,
+        PCIAdapter,
+        GIOAdapter,
+        TPUAdapter,
+
+        Anonymous
+} CONFIGTYPE;
+
+typedef enum {
+        Failed = 1,
+        ReadOnly = 2,
+        Removable = 4,
+        ConsoleIn = 8,
+        ConsoleOut = 16,
+        Input = 32,
+        Output = 64
+} IDENTIFIERFLAG;
+
+#ifndef NULL                    /* for GetChild(NULL); */
+#define NULL    0
+#endif
+
+union key_u {
+        struct {
+#ifdef  _MIPSEB
+                unsigned char  c_bsize;         /* block size in lines */
+                unsigned char  c_lsize;         /* line size in bytes/tag */
+                unsigned short c_size;          /* cache size in 4K pages */
+#else   /* _MIPSEL */
+                unsigned short c_size;          /* cache size in 4K pages */
+                unsigned char  c_lsize;         /* line size in bytes/tag */
+                unsigned char  c_bsize;         /* block size in lines */
+#endif  /* _MIPSEL */
+        } cache;
+        ULONG FullKey;
+};
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+#define SGI_ARCS_VERS   64                      /* sgi 64-bit version */
+#define SGI_ARCS_REV    0                       /* rev .00 */
+#else
+#define SGI_ARCS_VERS   1                       /* first version */
+#define SGI_ARCS_REV    10                      /* rev .10, 3/04/92 */
+#endif
+
+typedef struct component {
+        CONFIGCLASS     Class;
+        CONFIGTYPE      Type;
+        IDENTIFIERFLAG  Flags;
+        USHORT          Version;
+        USHORT          Revision;
+        ULONG           Key;
+        ULONG           AffinityMask;
+        ULONG           ConfigurationDataSize;
+        ULONG           IdentifierLength;
+        char            *Identifier;
+} COMPONENT;
+
+/* internal structure that holds pathname parsing data */
+struct cfgdata {
+        char *name;                     /* full name */
+        int minlen;                     /* minimum length to match */
+        CONFIGTYPE type;                /* type of token */
+};
+
+/* System ID */
+typedef struct systemid {
+        CHAR VendorId[8];
+        CHAR ProductId[8];
+} SYSTEMID;
+
+/* memory query functions */
+typedef enum memorytype {
+        ExceptionBlock,
+        SPBPage,                        /* ARCS == SystemParameterBlock */
+#ifndef _NT_PROM
+        FreeContiguous,
+        FreeMemory,
+        BadMemory,
+        LoadedProgram,
+        FirmwareTemporary,
+        FirmwarePermanent
+#else   /* _NT_PROM */
+        FreeMemory,
+        BadMemory,
+        LoadedProgram,
+        FirmwareTemporary,
+        FirmwarePermanent,
+        FreeContiguous
+#endif  /* _NT_PROM */
+} MEMORYTYPE;
+
+typedef struct memorydescriptor {
+        MEMORYTYPE      Type;
+        LONG            BasePage;
+        LONG            PageCount;
+} MEMORYDESCRIPTOR;
+
+#endif /* _ASM_ARC_HINV_H */
diff --git a/arch/mips/include/asm/fw/arc/types.h b/arch/mips/include/asm/fw/arc/types.h
new file mode 100644
index 000000000000..b9adcd6f0860
--- /dev/null
+++ b/arch/mips/include/asm/fw/arc/types.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1999 Ralf Baechle (ralf@gnu.org)
+ * Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ARC_TYPES_H
+#define _ASM_ARC_TYPES_H
+
+
+#ifdef CONFIG_ARC32
+
+typedef char            CHAR;
+typedef short           SHORT;
+typedef long            LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
+typedef long            LONG __attribute__ ((__mode__ (__SI__)));
+typedef unsigned char   UCHAR;
+typedef unsigned short  USHORT;
+typedef unsigned long   ULONG __attribute__ ((__mode__ (__SI__)));
+typedef void            VOID;
+
+/* The pointer types.  Note that we're using a 64-bit compiler but all
+   pointer in the ARC structures are only 32-bit, so we need some disgusting
+   workarounds.  Keep your vomit bag handy.  */
+typedef LONG            _PCHAR;
+typedef LONG            _PSHORT;
+typedef LONG            _PLARGE_INTEGER;
+typedef LONG            _PLONG;
+typedef LONG            _PUCHAR;
+typedef LONG            _PUSHORT;
+typedef LONG            _PULONG;
+typedef LONG            _PVOID;
+
+#endif /* CONFIG_ARC32 */
+
+#ifdef CONFIG_ARC64
+
+typedef char            CHAR;
+typedef short           SHORT;
+typedef long            LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
+typedef long            LONG __attribute__ ((__mode__ (__DI__)));
+typedef unsigned char   UCHAR;
+typedef unsigned short  USHORT;
+typedef unsigned long   ULONG __attribute__ ((__mode__ (__DI__)));
+typedef void            VOID;
+
+/* The pointer types.  We're 64-bit and the firmware is also 64-bit, so
+   live is sane ...  */
+typedef CHAR            *_PCHAR;
+typedef SHORT           *_PSHORT;
+typedef LARGE_INTEGER   *_PLARGE_INTEGER;
+typedef LONG            *_PLONG;
+typedef UCHAR           *_PUCHAR;
+typedef USHORT          *_PUSHORT;
+typedef ULONG           *_PULONG;
+typedef VOID            *_PVOID;
+
+#endif /* CONFIG_ARC64  */
+
+typedef CHAR            *PCHAR;
+typedef SHORT           *PSHORT;
+typedef LARGE_INTEGER   *PLARGE_INTEGER;
+typedef LONG            *PLONG;
+typedef UCHAR           *PUCHAR;
+typedef USHORT          *PUSHORT;
+typedef ULONG           *PULONG;
+typedef VOID            *PVOID;
+
+/*
+ * Return type of ArcGetDisplayStatus()
+ */
+typedef struct {
+        USHORT  CursorXPosition;
+        USHORT  CursorYPosition;
+        USHORT  CursorMaxXPosition;
+        USHORT  CursorMaxYPosition;
+        USHORT  ForegroundColor;
+        USHORT  BackgroundColor;
+        UCHAR   HighIntensity;
+        UCHAR   Underscored;
+        UCHAR   ReverseVideo;
+} DISPLAY_STATUS;
+
+#endif /* _ASM_ARC_TYPES_H */
diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h
new file mode 100644
index 000000000000..0995575db320
--- /dev/null
+++ b/arch/mips/include/asm/fw/cfe/cfe_api.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+/*
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * This file contains declarations for doing callbacks to
+ * cfe from an application.  It should be the only header
+ * needed by the application to use this library
+ *
+ * Authors:  Mitch Lichtenberg, Chris Demetriou
+ */
+#ifndef CFE_API_H
+#define CFE_API_H
+
+#include <linux/types.h>
+#include <linux/string.h>
+
+typedef long intptr_t;
+
+
+/*
+ * Constants
+ */
+
+/* Seal indicating CFE's presence, passed to user program. */
+#define CFE_EPTSEAL 0x43464531
+
+#define CFE_MI_RESERVED 0       /* memory is reserved, do not use */
+#define CFE_MI_AVAILABLE 1      /* memory is available */
+
+#define CFE_FLG_WARMSTART     0x00000001
+#define CFE_FLG_FULL_ARENA    0x00000001
+#define CFE_FLG_ENV_PERMANENT 0x00000001
+
+#define CFE_CPU_CMD_START 1
+#define CFE_CPU_CMD_STOP 0
+
+#define CFE_STDHANDLE_CONSOLE   0
+
+#define CFE_DEV_NETWORK         1
+#define CFE_DEV_DISK            2
+#define CFE_DEV_FLASH           3
+#define CFE_DEV_SERIAL          4
+#define CFE_DEV_CPU             5
+#define CFE_DEV_NVRAM           6
+#define CFE_DEV_CLOCK           7
+#define CFE_DEV_OTHER           8
+#define CFE_DEV_MASK            0x0F
+
+#define CFE_CACHE_FLUSH_D       1
+#define CFE_CACHE_INVAL_I       2
+#define CFE_CACHE_INVAL_D       4
+#define CFE_CACHE_INVAL_L2      8
+
+#define CFE_FWI_64BIT           0x00000001
+#define CFE_FWI_32BIT           0x00000002
+#define CFE_FWI_RELOC           0x00000004
+#define CFE_FWI_UNCACHED        0x00000008
+#define CFE_FWI_MULTICPU        0x00000010
+#define CFE_FWI_FUNCSIM         0x00000020
+#define CFE_FWI_RTLSIM          0x00000040
+
+typedef struct {
+        int64_t fwi_version;            /* major, minor, eco version */
+        int64_t fwi_totalmem;           /* total installed mem */
+        int64_t fwi_flags;              /* various flags */
+        int64_t fwi_boardid;            /* board ID */
+        int64_t fwi_bootarea_va;        /* VA of boot area */
+        int64_t fwi_bootarea_pa;        /* PA of boot area */
+        int64_t fwi_bootarea_size;      /* size of boot area */
+} cfe_fwinfo_t;
+
+
+/*
+ * Defines and prototypes for functions which take no arguments.
+ */
+int64_t cfe_getticks(void);
+
+/*
+ * Defines and prototypes for the rest of the functions.
+ */
+int cfe_close(int handle);
+int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1);
+int cfe_cpu_stop(int cpu);
+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
+int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length,
+                uint64_t * type);
+int cfe_exit(int warm, int status);
+int cfe_flushcache(int flg);
+int cfe_getdevinfo(char *name);
+int cfe_getenv(char *name, char *dest, int destlen);
+int cfe_getfwinfo(cfe_fwinfo_t * info);
+int cfe_getstdhandle(int flg);
+int cfe_init(uint64_t handle, uint64_t ept);
+int cfe_inpstat(int handle);
+int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
+              int length, int *retlen, uint64_t offset);
+int cfe_open(char *name);
+int cfe_read(int handle, unsigned char *buffer, int length);
+int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
+                int length);
+int cfe_setenv(char *name, char *val);
+int cfe_write(int handle, unsigned char *buffer, int length);
+int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer,
+                 int length);
+
+#endif                          /* CFE_API_H */
diff --git a/arch/mips/include/asm/fw/cfe/cfe_error.h b/arch/mips/include/asm/fw/cfe/cfe_error.h
new file mode 100644
index 000000000000..b80374636279
--- /dev/null
+++ b/arch/mips/include/asm/fw/cfe/cfe_error.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+/*
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * CFE's global error code list is here.
+ *
+ * Author:  Mitch Lichtenberg
+ */
+
+#define CFE_OK                   0
+#define CFE_ERR                 -1      /* generic error */
+#define CFE_ERR_INV_COMMAND     -2
+#define CFE_ERR_EOF             -3
+#define CFE_ERR_IOERR           -4
+#define CFE_ERR_NOMEM           -5
+#define CFE_ERR_DEVNOTFOUND     -6
+#define CFE_ERR_DEVOPEN         -7
+#define CFE_ERR_INV_PARAM       -8
+#define CFE_ERR_ENVNOTFOUND     -9
+#define CFE_ERR_ENVREADONLY     -10
+
+#define CFE_ERR_NOTELF          -11
+#define CFE_ERR_NOT32BIT        -12
+#define CFE_ERR_WRONGENDIAN     -13
+#define CFE_ERR_BADELFVERS      -14
+#define CFE_ERR_NOTMIPS         -15
+#define CFE_ERR_BADELFFMT       -16
+#define CFE_ERR_BADADDR         -17
+
+#define CFE_ERR_FILENOTFOUND    -18
+#define CFE_ERR_UNSUPPORTED     -19
+
+#define CFE_ERR_HOSTUNKNOWN     -20
+
+#define CFE_ERR_TIMEOUT         -21
+
+#define CFE_ERR_PROTOCOLERR     -22
+
+#define CFE_ERR_NETDOWN         -23
+#define CFE_ERR_NONAMESERVER    -24
+
+#define CFE_ERR_NOHANDLES       -25
+#define CFE_ERR_ALREADYBOUND    -26
+
+#define CFE_ERR_CANNOTSET       -27
+#define CFE_ERR_NOMORE          -28
+#define CFE_ERR_BADFILESYS      -29
+#define CFE_ERR_FSNOTAVAIL      -30
+
+#define CFE_ERR_INVBOOTBLOCK    -31
+#define CFE_ERR_WRONGDEVTYPE    -32
+#define CFE_ERR_BBCHECKSUM      -33
+#define CFE_ERR_BOOTPROGCHKSUM  -34
+
+#define CFE_ERR_LDRNOTAVAIL     -35
+
+#define CFE_ERR_NOTREADY        -36
+
+#define CFE_ERR_GETMEM          -37
+#define CFE_ERR_SETMEM          -38
+
+#define CFE_ERR_NOTCONN         -39
+#define CFE_ERR_ADDRINUSE       -40
diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h
new file mode 100644
index 000000000000..d74a8a4ca861
--- /dev/null
+++ b/arch/mips/include/asm/gcmpregs.h
@@ -0,0 +1,117 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ *
+ * Multiprocessor Subsystem Register Definitions
+ *
+ */
+#ifndef _ASM_GCMPREGS_H
+#define _ASM_GCMPREGS_H
+
+
+/* Offsets to major blocks within GCMP from GCMP base */
+#define GCMP_GCB_OFS            0x0000 /* Global Control Block */
+#define GCMP_CLCB_OFS           0x2000 /* Core Local Control Block */
+#define GCMP_COCB_OFS           0x4000 /* Core Other Control Block */
+#define GCMP_GDB_OFS            0x8000 /* Global Debug Block */
+
+/* Offsets to individual GCMP registers from GCMP base */
+#define GCMPOFS(block, tag, reg)        (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
+
+#define GCMPGCBOFS(reg)         GCMPOFS(GCB, GCB, reg)
+#define GCMPCLCBOFS(reg)        GCMPOFS(CLCB, CCB, reg)
+#define GCMPCOCBOFS(reg)        GCMPOFS(COCB, CCB, reg)
+#define GCMPGDBOFS(reg)         GCMPOFS(GDB, GDB, reg)
+
+/* GCMP register access */
+#define GCMPGCB(reg)                    REGP(_gcmp_base, GCMPGCBOFS(reg))
+#define GCMPCLCB(reg)                   REGP(_gcmp_base, GCMPCLCBOFS(reg))
+#define GCMPCOCB(reg)                   REGP(_gcmp_base, GCMPCOCBOFS(reg))
+#define GCMPGDB(reg)                    REGP(_gcmp_base, GCMPGDBOFS(reg))
+
+/* Mask generation */
+#define GCMPMSK(block, reg, bits)       (MSK(bits)<<GCMP_##block##_##reg##_SHF)
+#define GCMPGCBMSK(reg, bits)           GCMPMSK(GCB, reg, bits)
+#define GCMPCCBMSK(reg, bits)           GCMPMSK(CCB, reg, bits)
+#define GCMPGDBMSK(reg, bits)           GCMPMSK(GDB, reg, bits)
+
+/* GCB registers */
+#define GCMP_GCB_GC_OFS                 0x0000  /* Global Config Register */
+#define  GCMP_GCB_GC_NUMIOCU_SHF        8
+#define  GCMP_GCB_GC_NUMIOCU_MSK        GCMPGCBMSK(GC_NUMIOCU, 4)
+#define  GCMP_GCB_GC_NUMCORES_SHF       0
+#define  GCMP_GCB_GC_NUMCORES_MSK       GCMPGCBMSK(GC_NUMCORES, 8)
+#define GCMP_GCB_GCMPB_OFS              0x0008          /* Global GCMP Base */
+#define  GCMP_GCB_GCMPB_GCMPBASE_SHF    15
+#define  GCMP_GCB_GCMPB_GCMPBASE_MSK    GCMPGCBMSK(GCMPB_GCMPBASE, 17)
+#define  GCMP_GCB_GCMPB_CMDEFTGT_SHF    0
+#define  GCMP_GCB_GCMPB_CMDEFTGT_MSK    GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
+#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM    0
+#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM1   1
+#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
+#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
+#define GCMP_GCB_CCMC_OFS               0x0010  /* Global CM Control */
+#define GCMP_GCB_GCSRAP_OFS             0x0020  /* Global CSR Access Privilege */
+#define  GCMP_GCB_GCSRAP_CMACCESS_SHF   0
+#define  GCMP_GCB_GCSRAP_CMACCESS_MSK   GCMPGCBMSK(GCSRAP_CMACCESS, 8)
+#define GCMP_GCB_GCMPREV_OFS            0x0030  /* GCMP Revision Register */
+#define GCMP_GCB_GCMEM_OFS              0x0040  /* Global CM Error Mask */
+#define GCMP_GCB_GCMEC_OFS              0x0048  /* Global CM Error Cause */
+#define  GCMP_GCB_GMEC_ERROR_TYPE_SHF   27
+#define  GCMP_GCB_GMEC_ERROR_TYPE_MSK   GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
+#define  GCMP_GCB_GMEC_ERROR_INFO_SHF   0
+#define  GCMP_GCB_GMEC_ERROR_INFO_MSK   GCMPGCBMSK(GMEC_ERROR_INFO, 27)
+#define GCMP_GCB_GCMEA_OFS              0x0050  /* Global CM Error Address */
+#define GCMP_GCB_GCMEO_OFS              0x0058  /* Global CM Error Multiple */
+#define  GCMP_GCB_GMEO_ERROR_2ND_SHF    0
+#define  GCMP_GCB_GMEO_ERROR_2ND_MSK    GCMPGCBMSK(GMEO_ERROR_2ND, 5)
+#define GCMP_GCB_GICBA_OFS              0x0080  /* Global Interrupt Controller Base Address */
+#define  GCMP_GCB_GICBA_BASE_SHF        17
+#define  GCMP_GCB_GICBA_BASE_MSK        GCMPGCBMSK(GICBA_BASE, 15)
+#define  GCMP_GCB_GICBA_EN_SHF          0
+#define  GCMP_GCB_GICBA_EN_MSK          GCMPGCBMSK(GICBA_EN, 1)
+
+/* GCB Regions */
+#define GCMP_GCB_CMxBASE_OFS(n)         (0x0090+16*(n))         /* Global Region[0-3] Base Address */
+#define  GCMP_GCB_CMxBASE_BASE_SHF      16
+#define  GCMP_GCB_CMxBASE_BASE_MSK      GCMPGCBMSK(CMxBASE_BASE, 16)
+#define GCMP_GCB_CMxMASK_OFS(n)         (0x0098+16*(n))         /* Global Region[0-3] Address Mask */
+#define  GCMP_GCB_CMxMASK_MASK_SHF      16
+#define  GCMP_GCB_CMxMASK_MASK_MSK      GCMPGCBMSK(CMxMASK_MASK, 16)
+#define  GCMP_GCB_CMxMASK_CMREGTGT_SHF  0
+#define  GCMP_GCB_CMxMASK_CMREGTGT_MSK  GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
+#define  GCMP_GCB_CMxMASK_CMREGTGT_MEM   0
+#define  GCMP_GCB_CMxMASK_CMREGTGT_MEM1  1
+#define  GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
+#define  GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3
+
+
+/* Core local/Core other control block registers */
+#define GCMP_CCB_RESETR_OFS             0x0000                  /* Reset Release */
+#define  GCMP_CCB_RESETR_INRESET_SHF    0
+#define  GCMP_CCB_RESETR_INRESET_MSK    GCMPCCBMSK(RESETR_INRESET, 16)
+#define GCMP_CCB_COHCTL_OFS             0x0008                  /* Coherence Control */
+#define  GCMP_CCB_COHCTL_DOMAIN_SHF     0
+#define  GCMP_CCB_COHCTL_DOMAIN_MSK     GCMPCCBMSK(COHCTL_DOMAIN, 8)
+#define GCMP_CCB_CFG_OFS                0x0010                  /* Config */
+#define  GCMP_CCB_CFG_IOCUTYPE_SHF      10
+#define  GCMP_CCB_CFG_IOCUTYPE_MSK      GCMPCCBMSK(CFG_IOCUTYPE, 2)
+#define   GCMP_CCB_CFG_IOCUTYPE_CPU     0
+#define   GCMP_CCB_CFG_IOCUTYPE_NCIOCU  1
+#define   GCMP_CCB_CFG_IOCUTYPE_CIOCU   2
+#define  GCMP_CCB_CFG_NUMVPE_SHF        0
+#define  GCMP_CCB_CFG_NUMVPE_MSK        GCMPCCBMSK(CFG_NUMVPE, 10)
+#define GCMP_CCB_OTHER_OFS              0x0018          /* Other Address */
+#define  GCMP_CCB_OTHER_CORENUM_SHF     16
+#define  GCMP_CCB_OTHER_CORENUM_MSK     GCMPCCBMSK(OTHER_CORENUM, 16)
+#define GCMP_CCB_RESETBASE_OFS          0x0020          /* Reset Exception Base */
+#define  GCMP_CCB_RESETBASE_BEV_SHF     12
+#define  GCMP_CCB_RESETBASE_BEV_MSK     GCMPCCBMSK(RESETBASE_BEV, 20)
+#define GCMP_CCB_ID_OFS                 0x0028          /* Identification */
+#define GCMP_CCB_DINTGROUP_OFS          0x0030          /* DINT Group Participate */
+#define GCMP_CCB_DBGGROUP_OFS           0x0100          /* DebugBreak Group */
+
+#endif /* _ASM_GCMPREGS_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
new file mode 100644
index 000000000000..954807d9d66a
--- /dev/null
+++ b/arch/mips/include/asm/gic.h
@@ -0,0 +1,487 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ *
+ * GIC Register Definitions
+ *
+ */
+#ifndef _ASM_GICREGS_H
+#define _ASM_GICREGS_H
+
+#undef  GICISBYTELITTLEENDIAN
+#define GICISWORDLITTLEENDIAN
+
+/* Constants */
+#define GIC_POL_POS                     1
+#define GIC_POL_NEG                     0
+#define GIC_TRIG_EDGE                   1
+#define GIC_TRIG_LEVEL                  0
+
+#define GIC_NUM_INTRS                   32
+
+#define MSK(n) ((1 << (n)) - 1)
+#define REG32(addr)             (*(volatile unsigned int *) (addr))
+#define REG(base, offs)         REG32((unsigned long)(base) + offs##_##OFS)
+#define REGP(base, phys)        REG32((unsigned long)(base) + (phys))
+
+/* Accessors */
+#define GIC_REG(segment, offset) \
+        REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
+#define GIC_REG_ADDR(segment, offset) \
+        REG32(_gic_base + segment##_##SECTION_OFS + offset)
+
+#define GIC_ABS_REG(segment, offset) \
+       (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
+#define GIC_REG_ABS_ADDR(segment, offset) \
+       (_gic_base + segment##_##SECTION_OFS + offset)
+
+#ifdef GICISBYTELITTLEENDIAN
+#define GICREAD(reg, data)      (data) = (reg), (data) = le32_to_cpu(data)
+#define GICWRITE(reg, data)     (reg) = cpu_to_le32(data)
+#define GICBIS(reg, bits)                       \
+        ({unsigned int data;                    \
+                GICREAD(reg, data);             \
+                data |= bits;                   \
+                GICWRITE(reg, data);            \
+        })
+
+#else
+#define GICREAD(reg, data)      (data) = (reg)
+#define GICWRITE(reg, data)     (reg) = (data)
+#define GICBIS(reg, bits)       (reg) |= (bits)
+#endif
+
+
+/* GIC Address Space */
+#define SHARED_SECTION_OFS              0x0000
+#define SHARED_SECTION_SIZE             0x8000
+#define VPE_LOCAL_SECTION_OFS           0x8000
+#define VPE_LOCAL_SECTION_SIZE          0x4000
+#define VPE_OTHER_SECTION_OFS           0xc000
+#define VPE_OTHER_SECTION_SIZE          0x4000
+#define USM_VISIBLE_SECTION_OFS         0x10000
+#define USM_VISIBLE_SECTION_SIZE        0x10000
+
+/* Register Map for Shared Section */
+#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
+
+#define GIC_SH_CONFIG_OFS               0x0000
+
+/* Shared Global Counter */
+#define GIC_SH_COUNTER_31_00_OFS        0x0010
+#define GIC_SH_COUNTER_63_32_OFS        0x0014
+
+/* Interrupt Polarity */
+#define GIC_SH_POL_31_0_OFS             0x0100
+#define GIC_SH_POL_63_32_OFS            0x0104
+#define GIC_SH_POL_95_64_OFS            0x0108
+#define GIC_SH_POL_127_96_OFS           0x010c
+#define GIC_SH_POL_159_128_OFS          0x0110
+#define GIC_SH_POL_191_160_OFS          0x0114
+#define GIC_SH_POL_223_192_OFS          0x0118
+#define GIC_SH_POL_255_224_OFS          0x011c
+
+/* Edge/Level Triggering */
+#define GIC_SH_TRIG_31_0_OFS            0x0180
+#define GIC_SH_TRIG_63_32_OFS           0x0184
+#define GIC_SH_TRIG_95_64_OFS           0x0188
+#define GIC_SH_TRIG_127_96_OFS          0x018c
+#define GIC_SH_TRIG_159_128_OFS         0x0190
+#define GIC_SH_TRIG_191_160_OFS         0x0194
+#define GIC_SH_TRIG_223_192_OFS         0x0198
+#define GIC_SH_TRIG_255_224_OFS         0x019c
+
+/* Dual Edge Triggering */
+#define GIC_SH_DUAL_31_0_OFS            0x0200
+#define GIC_SH_DUAL_63_32_OFS           0x0204
+#define GIC_SH_DUAL_95_64_OFS           0x0208
+#define GIC_SH_DUAL_127_96_OFS          0x020c
+#define GIC_SH_DUAL_159_128_OFS         0x0210
+#define GIC_SH_DUAL_191_160_OFS         0x0214
+#define GIC_SH_DUAL_223_192_OFS         0x0218
+#define GIC_SH_DUAL_255_224_OFS         0x021c
+
+/* Set/Clear corresponding bit in Edge Detect Register */
+#define GIC_SH_WEDGE_OFS                0x0280
+
+/* Reset Mask - Disables Interrupt */
+#define GIC_SH_RMASK_31_0_OFS           0x0300
+#define GIC_SH_RMASK_63_32_OFS          0x0304
+#define GIC_SH_RMASK_95_64_OFS          0x0308
+#define GIC_SH_RMASK_127_96_OFS         0x030c
+#define GIC_SH_RMASK_159_128_OFS        0x0310
+#define GIC_SH_RMASK_191_160_OFS        0x0314
+#define GIC_SH_RMASK_223_192_OFS        0x0318
+#define GIC_SH_RMASK_255_224_OFS        0x031c
+
+/* Set Mask (WO) - Enables Interrupt */
+#define GIC_SH_SMASK_31_0_OFS           0x0380
+#define GIC_SH_SMASK_63_32_OFS          0x0384
+#define GIC_SH_SMASK_95_64_OFS          0x0388
+#define GIC_SH_SMASK_127_96_OFS         0x038c
+#define GIC_SH_SMASK_159_128_OFS        0x0390
+#define GIC_SH_SMASK_191_160_OFS        0x0394
+#define GIC_SH_SMASK_223_192_OFS        0x0398
+#define GIC_SH_SMASK_255_224_OFS        0x039c
+
+/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
+#define GIC_SH_MASK_31_0_OFS            0x0400
+#define GIC_SH_MASK_63_32_OFS           0x0404
+#define GIC_SH_MASK_95_64_OFS           0x0408
+#define GIC_SH_MASK_127_96_OFS          0x040c
+#define GIC_SH_MASK_159_128_OFS         0x0410
+#define GIC_SH_MASK_191_160_OFS         0x0414
+#define GIC_SH_MASK_223_192_OFS         0x0418
+#define GIC_SH_MASK_255_224_OFS         0x041c
+
+/* Pending Global Interrupts (RO) */
+#define GIC_SH_PEND_31_0_OFS            0x0480
+#define GIC_SH_PEND_63_32_OFS           0x0484
+#define GIC_SH_PEND_95_64_OFS           0x0488
+#define GIC_SH_PEND_127_96_OFS          0x048c
+#define GIC_SH_PEND_159_128_OFS         0x0490
+#define GIC_SH_PEND_191_160_OFS         0x0494
+#define GIC_SH_PEND_223_192_OFS         0x0498
+#define GIC_SH_PEND_255_224_OFS         0x049c
+
+#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
+
+/* Maps Interrupt X to a Pin */
+#define GIC_SH_MAP_TO_PIN(intr) \
+        (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
+
+#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
+
+/* Maps Interrupt X to a VPE */
+#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
+        (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
+#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)  (1 << ((vpe) % 32))
+
+/* Polarity : Reset Value is always 0 */
+#define GIC_SH_SET_POLARITY_OFS         0x0100
+#define GIC_SET_POLARITY(intr, pol) \
+        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
+
+/* Triggering : Reset Value is always 0 */
+#define GIC_SH_SET_TRIGGER_OFS          0x0180
+#define GIC_SET_TRIGGER(intr, trig) \
+        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
+
+/* Mask manipulation */
+#define GIC_SH_SMASK_OFS                0x0380
+#define GIC_SET_INTR_MASK(intr, val) \
+        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
+
+#define GIC_SH_RMASK_OFS                0x0300
+#define GIC_CLR_INTR_MASK(intr, val) \
+        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
+
+/* Register Map for Local Section */
+#define GIC_VPE_CTL_OFS                 0x0000
+#define GIC_VPE_PEND_OFS                0x0004
+#define GIC_VPE_MASK_OFS                0x0008
+#define GIC_VPE_RMASK_OFS               0x000c
+#define GIC_VPE_SMASK_OFS               0x0010
+#define GIC_VPE_WD_MAP_OFS              0x0040
+#define GIC_VPE_COMPARE_MAP_OFS         0x0044
+#define GIC_VPE_TIMER_MAP_OFS           0x0048
+#define GIC_VPE_PERFCTR_MAP_OFS         0x0050
+#define GIC_VPE_SWINT0_MAP_OFS          0x0054
+#define GIC_VPE_SWINT1_MAP_OFS          0x0058
+#define GIC_VPE_OTHER_ADDR_OFS          0x0080
+#define GIC_VPE_WD_CONFIG0_OFS          0x0090
+#define GIC_VPE_WD_COUNT0_OFS           0x0094
+#define GIC_VPE_WD_INITIAL0_OFS         0x0098
+#define GIC_VPE_COMPARE_LO_OFS          0x00a0
+#define GIC_VPE_COMPARE_HI              0x00a4
+
+#define GIC_VPE_EIC_SHADOW_SET_BASE     0x0100
+#define GIC_VPE_EIC_SS(intr) \
+        (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
+
+#define GIC_VPE_EIC_VEC_BASE            0x0800
+#define GIC_VPE_EIC_VEC(intr) \
+        (GIC_VPE_EIC_VEC_BASE + (4 * intr))
+
+#define GIC_VPE_TENABLE_NMI_OFS         0x1000
+#define GIC_VPE_TENABLE_YQ_OFS          0x1004
+#define GIC_VPE_TENABLE_INT_31_0_OFS    0x1080
+#define GIC_VPE_TENABLE_INT_63_32_OFS   0x1084
+
+/* User Mode Visible Section Register Map */
+#define GIC_UMV_SH_COUNTER_31_00_OFS    0x0000
+#define GIC_UMV_SH_COUNTER_63_32_OFS    0x0004
+
+#else /* CONFIG_CPU_BIG_ENDIAN */
+
+#define GIC_SH_CONFIG_OFS               0x0000
+
+/* Shared Global Counter */
+#define GIC_SH_COUNTER_31_00_OFS        0x0014
+#define GIC_SH_COUNTER_63_32_OFS        0x0010
+
+/* Interrupt Polarity */
+#define GIC_SH_POL_31_0_OFS             0x0104
+#define GIC_SH_POL_63_32_OFS            0x0100
+#define GIC_SH_POL_95_64_OFS            0x010c
+#define GIC_SH_POL_127_96_OFS           0x0108
+#define GIC_SH_POL_159_128_OFS          0x0114
+#define GIC_SH_POL_191_160_OFS          0x0110
+#define GIC_SH_POL_223_192_OFS          0x011c
+#define GIC_SH_POL_255_224_OFS          0x0118
+
+/* Edge/Level Triggering */
+#define GIC_SH_TRIG_31_0_OFS            0x0184
+#define GIC_SH_TRIG_63_32_OFS           0x0180
+#define GIC_SH_TRIG_95_64_OFS           0x018c
+#define GIC_SH_TRIG_127_96_OFS          0x0188
+#define GIC_SH_TRIG_159_128_OFS         0x0194
+#define GIC_SH_TRIG_191_160_OFS         0x0190
+#define GIC_SH_TRIG_223_192_OFS         0x019c
+#define GIC_SH_TRIG_255_224_OFS         0x0198
+
+/* Dual Edge Triggering */
+#define GIC_SH_DUAL_31_0_OFS            0x0204
+#define GIC_SH_DUAL_63_32_OFS           0x0200
+#define GIC_SH_DUAL_95_64_OFS           0x020c
+#define GIC_SH_DUAL_127_96_OFS          0x0208
+#define GIC_SH_DUAL_159_128_OFS         0x0214
+#define GIC_SH_DUAL_191_160_OFS         0x0210
+#define GIC_SH_DUAL_223_192_OFS         0x021c
+#define GIC_SH_DUAL_255_224_OFS         0x0218
+
+/* Set/Clear corresponding bit in Edge Detect Register */
+#define GIC_SH_WEDGE_OFS                0x0280
+
+/* Reset Mask - Disables Interrupt */
+#define GIC_SH_RMASK_31_0_OFS           0x0304
+#define GIC_SH_RMASK_63_32_OFS          0x0300
+#define GIC_SH_RMASK_95_64_OFS          0x030c
+#define GIC_SH_RMASK_127_96_OFS         0x0308
+#define GIC_SH_RMASK_159_128_OFS        0x0314
+#define GIC_SH_RMASK_191_160_OFS        0x0310
+#define GIC_SH_RMASK_223_192_OFS        0x031c
+#define GIC_SH_RMASK_255_224_OFS        0x0318
+
+/* Set Mask (WO) - Enables Interrupt */
+#define GIC_SH_SMASK_31_0_OFS           0x0384
+#define GIC_SH_SMASK_63_32_OFS          0x0380
+#define GIC_SH_SMASK_95_64_OFS          0x038c
+#define GIC_SH_SMASK_127_96_OFS         0x0388
+#define GIC_SH_SMASK_159_128_OFS        0x0394
+#define GIC_SH_SMASK_191_160_OFS        0x0390
+#define GIC_SH_SMASK_223_192_OFS        0x039c
+#define GIC_SH_SMASK_255_224_OFS        0x0398
+
+/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
+#define GIC_SH_MASK_31_0_OFS            0x0404
+#define GIC_SH_MASK_63_32_OFS           0x0400
+#define GIC_SH_MASK_95_64_OFS           0x040c
+#define GIC_SH_MASK_127_96_OFS          0x0408
+#define GIC_SH_MASK_159_128_OFS         0x0414
+#define GIC_SH_MASK_191_160_OFS         0x0410
+#define GIC_SH_MASK_223_192_OFS         0x041c
+#define GIC_SH_MASK_255_224_OFS         0x0418
+
+/* Pending Global Interrupts (RO) */
+#define GIC_SH_PEND_31_0_OFS            0x0484
+#define GIC_SH_PEND_63_32_OFS           0x0480
+#define GIC_SH_PEND_95_64_OFS           0x048c
+#define GIC_SH_PEND_127_96_OFS          0x0488
+#define GIC_SH_PEND_159_128_OFS         0x0494
+#define GIC_SH_PEND_191_160_OFS         0x0490
+#define GIC_SH_PEND_223_192_OFS         0x049c
+#define GIC_SH_PEND_255_224_OFS         0x0498
+
+#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
+
+/* Maps Interrupt X to a Pin */
+#define GIC_SH_MAP_TO_PIN(intr) \
+        (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
+
+#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
+
+/*
+ * Maps Interrupt X to a VPE.  This is more complex than the LE case, as
+ * odd and even registers need to be transposed.  It does work - trust me!
+ */
+#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
+        (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
+        (((((vpe) / 32) ^ 1) - 1) * 4))
+#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)  (1 << ((vpe) % 32))
+
+/* Polarity */
+#define GIC_SH_SET_POLARITY_OFS         0x0100
+#define GIC_SET_POLARITY(intr, pol) \
+        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
+
+/* Triggering */
+#define GIC_SH_SET_TRIGGER_OFS          0x0180
+#define GIC_SET_TRIGGER(intr, trig) \
+        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
+
+/* Mask manipulation */
+#define GIC_SH_SMASK_OFS                0x0380
+#define GIC_SET_INTR_MASK(intr, val) \
+        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
+
+#define GIC_SH_RMASK_OFS                0x0300
+#define GIC_CLR_INTR_MASK(intr, val) \
+        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
+
+/* Register Map for Local Section */
+#define GIC_VPE_CTL_OFS                 0x0000
+#define GIC_VPE_PEND_OFS                0x0004
+#define GIC_VPE_MASK_OFS                0x0008
+#define GIC_VPE_RMASK_OFS               0x000c
+#define GIC_VPE_SMASK_OFS               0x0010
+#define GIC_VPE_WD_MAP_OFS              0x0040
+#define GIC_VPE_COMPARE_MAP_OFS         0x0044
+#define GIC_VPE_TIMER_MAP_OFS           0x0048
+#define GIC_VPE_PERFCTR_MAP_OFS         0x0050
+#define GIC_VPE_SWINT0_MAP_OFS          0x0054
+#define GIC_VPE_SWINT1_MAP_OFS          0x0058
+#define GIC_VPE_OTHER_ADDR_OFS          0x0080
+#define GIC_VPE_WD_CONFIG0_OFS          0x0090
+#define GIC_VPE_WD_COUNT0_OFS           0x0094
+#define GIC_VPE_WD_INITIAL0_OFS         0x0098
+#define GIC_VPE_COMPARE_LO_OFS          0x00a4
+#define GIC_VPE_COMPARE_HI_OFS          0x00a0
+
+#define GIC_VPE_EIC_SHADOW_SET_BASE     0x0100
+#define GIC_VPE_EIC_SS(intr) \
+        (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
+
+#define GIC_VPE_EIC_VEC_BASE            0x0800
+#define GIC_VPE_EIC_VEC(intr) \
+        (GIC_VPE_EIC_VEC_BASE + (4 * intr))
+
+#define GIC_VPE_TENABLE_NMI_OFS         0x1000
+#define GIC_VPE_TENABLE_YQ_OFS          0x1004
+#define GIC_VPE_TENABLE_INT_31_0_OFS    0x1080
+#define GIC_VPE_TENABLE_INT_63_32_OFS   0x1084
+
+/* User Mode Visible Section Register Map */
+#define GIC_UMV_SH_COUNTER_31_00_OFS    0x0004
+#define GIC_UMV_SH_COUNTER_63_32_OFS    0x0000
+
+#endif /* !LE */
+
+/* Masks */
+#define GIC_SH_CONFIG_COUNTSTOP_SHF     28
+#define GIC_SH_CONFIG_COUNTSTOP_MSK     (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
+
+#define GIC_SH_CONFIG_COUNTBITS_SHF     24
+#define GIC_SH_CONFIG_COUNTBITS_MSK     (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
+
+#define GIC_SH_CONFIG_NUMINTRS_SHF      16
+#define GIC_SH_CONFIG_NUMINTRS_MSK      (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
+
+#define GIC_SH_CONFIG_NUMVPES_SHF       0
+#define GIC_SH_CONFIG_NUMVPES_MSK       (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
+
+#define GIC_SH_WEDGE_SET(intr)          (intr | (0x1 << 31))
+#define GIC_SH_WEDGE_CLR(intr)          (intr & ~(0x1 << 31))
+
+#define GIC_MAP_TO_PIN_SHF              31
+#define GIC_MAP_TO_PIN_MSK              (MSK(1) << GIC_MAP_TO_PIN_SHF)
+#define GIC_MAP_TO_NMI_SHF              30
+#define GIC_MAP_TO_NMI_MSK              (MSK(1) << GIC_MAP_TO_NMI_SHF)
+#define GIC_MAP_TO_YQ_SHF               29
+#define GIC_MAP_TO_YQ_MSK               (MSK(1) << GIC_MAP_TO_YQ_SHF)
+#define GIC_MAP_SHF                     0
+#define GIC_MAP_MSK                     (MSK(6) << GIC_MAP_SHF)
+
+/* GIC_VPE_CTL Masks */
+#define GIC_VPE_CTL_PERFCNT_RTBL_SHF    2
+#define GIC_VPE_CTL_PERFCNT_RTBL_MSK    (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
+#define GIC_VPE_CTL_TIMER_RTBL_SHF      1
+#define GIC_VPE_CTL_TIMER_RTBL_MSK      (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
+#define GIC_VPE_CTL_EIC_MODE_SHF        0
+#define GIC_VPE_CTL_EIC_MODE_MSK        (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
+
+/* GIC_VPE_PEND Masks */
+#define GIC_VPE_PEND_WD_SHF             0
+#define GIC_VPE_PEND_WD_MSK             (MSK(1) << GIC_VPE_PEND_WD_SHF)
+#define GIC_VPE_PEND_CMP_SHF            1
+#define GIC_VPE_PEND_CMP_MSK            (MSK(1) << GIC_VPE_PEND_CMP_SHF)
+#define GIC_VPE_PEND_TIMER_SHF          2
+#define GIC_VPE_PEND_TIMER_MSK          (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
+#define GIC_VPE_PEND_PERFCOUNT_SHF      3
+#define GIC_VPE_PEND_PERFCOUNT_MSK      (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
+#define GIC_VPE_PEND_SWINT0_SHF         4
+#define GIC_VPE_PEND_SWINT0_MSK         (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
+#define GIC_VPE_PEND_SWINT1_SHF         5
+#define GIC_VPE_PEND_SWINT1_MSK         (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
+
+/* GIC_VPE_RMASK Masks */
+#define GIC_VPE_RMASK_WD_SHF            0
+#define GIC_VPE_RMASK_WD_MSK            (MSK(1) << GIC_VPE_RMASK_WD_SHF)
+#define GIC_VPE_RMASK_CMP_SHF           1
+#define GIC_VPE_RMASK_CMP_MSK           (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
+#define GIC_VPE_RMASK_TIMER_SHF         2
+#define GIC_VPE_RMASK_TIMER_MSK         (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
+#define GIC_VPE_RMASK_PERFCNT_SHF       3
+#define GIC_VPE_RMASK_PERFCNT_MSK       (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
+#define GIC_VPE_RMASK_SWINT0_SHF        4
+#define GIC_VPE_RMASK_SWINT0_MSK        (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
+#define GIC_VPE_RMASK_SWINT1_SHF        5
+#define GIC_VPE_RMASK_SWINT1_MSK        (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
+
+/* GIC_VPE_SMASK Masks */
+#define GIC_VPE_SMASK_WD_SHF            0
+#define GIC_VPE_SMASK_WD_MSK            (MSK(1) << GIC_VPE_SMASK_WD_SHF)
+#define GIC_VPE_SMASK_CMP_SHF           1
+#define GIC_VPE_SMASK_CMP_MSK           (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
+#define GIC_VPE_SMASK_TIMER_SHF         2
+#define GIC_VPE_SMASK_TIMER_MSK         (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
+#define GIC_VPE_SMASK_PERFCNT_SHF       3
+#define GIC_VPE_SMASK_PERFCNT_MSK       (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
+#define GIC_VPE_SMASK_SWINT0_SHF        4
+#define GIC_VPE_SMASK_SWINT0_MSK        (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
+#define GIC_VPE_SMASK_SWINT1_SHF        5
+#define GIC_VPE_SMASK_SWINT1_MSK        (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
+
+/*
+ * Set the Mapping of Interrupt X to a VPE.
+ */
+#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
+        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
+                 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
+
+struct gic_pcpu_mask {
+       DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
+};
+
+struct gic_pending_regs {
+       DECLARE_BITMAP(pending, GIC_NUM_INTRS);
+};
+
+struct gic_intrmask_regs {
+       DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
+};
+
+/*
+ * Interrupt Meta-data specification. The ipiflag helps
+ * in building ipi_map.
+ */
+struct gic_intr_map {
+        unsigned int intrnum;   /* Ext Intr Num         */
+        unsigned int cpunum;    /* Directed to this CPU */
+        unsigned int pin;       /* Directed to this Pin */
+        unsigned int polarity;  /* Polarity : +/-       */
+        unsigned int trigtype;  /* Trigger  : Edge/Levl */
+        unsigned int ipiflag;   /* Is used for IPI ?    */
+};
+
+extern void gic_init(unsigned long gic_base_addr,
+        unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
+        unsigned int intrmap_size, unsigned int irqbase);
+
+extern unsigned int gic_get_int(void);
+extern void gic_send_ipi(unsigned int intr);
+
+#endif /* _ASM_GICREGS_H */
diff --git a/arch/mips/include/asm/gpio.h b/arch/mips/include/asm/gpio.h
new file mode 100644
index 000000000000..06e46faf862d
--- /dev/null
+++ b/arch/mips/include/asm/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_MIPS_GPIO_H
+#define __ASM_MIPS_GPIO_H
+
+#include <gpio.h>
+
+#endif /* __ASM_MIPS_GPIO_H */
diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h
new file mode 100644
index 000000000000..e64b41093c49
--- /dev/null
+++ b/arch/mips/include/asm/gt64120.h
@@ -0,0 +1,580 @@
+/*
+ * Copyright (C) 2000, 2004, 2005  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef _ASM_GT64120_H
+#define _ASM_GT64120_H
+
+#include <linux/clocksource.h>
+
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#define MSK(n)                  ((1 << (n)) - 1)
+
+/*
+ *  Register offset addresses
+ */
+/* CPU Configuration.  */
+#define GT_CPU_OFS              0x000
+
+#define GT_MULTI_OFS            0x120
+
+/* CPU Address Decode.  */
+#define GT_SCS10LD_OFS          0x008
+#define GT_SCS10HD_OFS          0x010
+#define GT_SCS32LD_OFS          0x018
+#define GT_SCS32HD_OFS          0x020
+#define GT_CS20LD_OFS           0x028
+#define GT_CS20HD_OFS           0x030
+#define GT_CS3BOOTLD_OFS        0x038
+#define GT_CS3BOOTHD_OFS        0x040
+#define GT_PCI0IOLD_OFS         0x048
+#define GT_PCI0IOHD_OFS         0x050
+#define GT_PCI0M0LD_OFS         0x058
+#define GT_PCI0M0HD_OFS         0x060
+#define GT_ISD_OFS              0x068
+
+#define GT_PCI0M1LD_OFS         0x080
+#define GT_PCI0M1HD_OFS         0x088
+#define GT_PCI1IOLD_OFS         0x090
+#define GT_PCI1IOHD_OFS         0x098
+#define GT_PCI1M0LD_OFS         0x0a0
+#define GT_PCI1M0HD_OFS         0x0a8
+#define GT_PCI1M1LD_OFS         0x0b0
+#define GT_PCI1M1HD_OFS         0x0b8
+#define GT_PCI1M1LD_OFS         0x0b0
+#define GT_PCI1M1HD_OFS         0x0b8
+
+#define GT_SCS10AR_OFS          0x0d0
+#define GT_SCS32AR_OFS          0x0d8
+#define GT_CS20R_OFS            0x0e0
+#define GT_CS3BOOTR_OFS         0x0e8
+
+#define GT_PCI0IOREMAP_OFS      0x0f0
+#define GT_PCI0M0REMAP_OFS      0x0f8
+#define GT_PCI0M1REMAP_OFS      0x100
+#define GT_PCI1IOREMAP_OFS      0x108
+#define GT_PCI1M0REMAP_OFS      0x110
+#define GT_PCI1M1REMAP_OFS      0x118
+
+/* CPU Error Report.  */
+#define GT_CPUERR_ADDRLO_OFS    0x070
+#define GT_CPUERR_ADDRHI_OFS    0x078
+
+#define GT_CPUERR_DATALO_OFS    0x128                   /* GT-64120A only  */
+#define GT_CPUERR_DATAHI_OFS    0x130                   /* GT-64120A only  */
+#define GT_CPUERR_PARITY_OFS    0x138                   /* GT-64120A only  */
+
+/* CPU Sync Barrier.  */
+#define GT_PCI0SYNC_OFS         0x0c0
+#define GT_PCI1SYNC_OFS         0x0c8
+
+/* SDRAM and Device Address Decode.  */
+#define GT_SCS0LD_OFS           0x400
+#define GT_SCS0HD_OFS           0x404
+#define GT_SCS1LD_OFS           0x408
+#define GT_SCS1HD_OFS           0x40c
+#define GT_SCS2LD_OFS           0x410
+#define GT_SCS2HD_OFS           0x414
+#define GT_SCS3LD_OFS           0x418
+#define GT_SCS3HD_OFS           0x41c
+#define GT_CS0LD_OFS            0x420
+#define GT_CS0HD_OFS            0x424
+#define GT_CS1LD_OFS            0x428
+#define GT_CS1HD_OFS            0x42c
+#define GT_CS2LD_OFS            0x430
+#define GT_CS2HD_OFS            0x434
+#define GT_CS3LD_OFS            0x438
+#define GT_CS3HD_OFS            0x43c
+#define GT_BOOTLD_OFS           0x440
+#define GT_BOOTHD_OFS           0x444
+
+#define GT_ADERR_OFS            0x470
+
+/* SDRAM Configuration.  */
+#define GT_SDRAM_CFG_OFS        0x448
+
+#define GT_SDRAM_OPMODE_OFS     0x474
+#define GT_SDRAM_BM_OFS         0x478
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c
+
+/* SDRAM Parameters.  */
+#define GT_SDRAM_B0_OFS         0x44c
+#define GT_SDRAM_B1_OFS         0x450
+#define GT_SDRAM_B2_OFS         0x454
+#define GT_SDRAM_B3_OFS         0x458
+
+/* Device Parameters.  */
+#define GT_DEV_B0_OFS           0x45c
+#define GT_DEV_B1_OFS           0x460
+#define GT_DEV_B2_OFS           0x464
+#define GT_DEV_B3_OFS           0x468
+#define GT_DEV_BOOT_OFS         0x46c
+
+/* ECC.  */
+#define GT_ECC_ERRDATALO        0x480                   /* GT-64120A only  */
+#define GT_ECC_ERRDATAHI        0x484                   /* GT-64120A only  */
+#define GT_ECC_MEM              0x488                   /* GT-64120A only  */
+#define GT_ECC_CALC             0x48c                   /* GT-64120A only  */
+#define GT_ECC_ERRADDR          0x490                   /* GT-64120A only  */
+
+/* DMA Record.  */
+#define GT_DMA0_CNT_OFS         0x800
+#define GT_DMA1_CNT_OFS         0x804
+#define GT_DMA2_CNT_OFS         0x808
+#define GT_DMA3_CNT_OFS         0x80c
+#define GT_DMA0_SA_OFS          0x810
+#define GT_DMA1_SA_OFS          0x814
+#define GT_DMA2_SA_OFS          0x818
+#define GT_DMA3_SA_OFS          0x81c
+#define GT_DMA0_DA_OFS          0x820
+#define GT_DMA1_DA_OFS          0x824
+#define GT_DMA2_DA_OFS          0x828
+#define GT_DMA3_DA_OFS          0x82c
+#define GT_DMA0_NEXT_OFS        0x830
+#define GT_DMA1_NEXT_OFS        0x834
+#define GT_DMA2_NEXT_OFS        0x838
+#define GT_DMA3_NEXT_OFS        0x83c
+
+#define GT_DMA0_CUR_OFS         0x870
+#define GT_DMA1_CUR_OFS         0x874
+#define GT_DMA2_CUR_OFS         0x878
+#define GT_DMA3_CUR_OFS         0x87c
+
+/* DMA Channel Control.  */
+#define GT_DMA0_CTRL_OFS        0x840
+#define GT_DMA1_CTRL_OFS        0x844
+#define GT_DMA2_CTRL_OFS        0x848
+#define GT_DMA3_CTRL_OFS        0x84c
+
+/* DMA Arbiter.  */
+#define GT_DMA_ARB_OFS          0x860
+
+/* Timer/Counter.  */
+#define GT_TC0_OFS              0x850
+#define GT_TC1_OFS              0x854
+#define GT_TC2_OFS              0x858
+#define GT_TC3_OFS              0x85c
+
+#define GT_TC_CONTROL_OFS       0x864
+
+/* PCI Internal.  */
+#define GT_PCI0_CMD_OFS         0xc00
+#define GT_PCI0_TOR_OFS         0xc04
+#define GT_PCI0_BS_SCS10_OFS    0xc08
+#define GT_PCI0_BS_SCS32_OFS    0xc0c
+#define GT_PCI0_BS_CS20_OFS     0xc10
+#define GT_PCI0_BS_CS3BT_OFS    0xc14
+
+#define GT_PCI1_IACK_OFS        0xc30
+#define GT_PCI0_IACK_OFS        0xc34
+
+#define GT_PCI0_BARE_OFS        0xc3c
+#define GT_PCI0_PREFMBR_OFS     0xc40
+
+#define GT_PCI0_SCS10_BAR_OFS   0xc48
+#define GT_PCI0_SCS32_BAR_OFS   0xc4c
+#define GT_PCI0_CS20_BAR_OFS    0xc50
+#define GT_PCI0_CS3BT_BAR_OFS   0xc54
+#define GT_PCI0_SSCS10_BAR_OFS  0xc58
+#define GT_PCI0_SSCS32_BAR_OFS  0xc5c
+
+#define GT_PCI0_SCS3BT_BAR_OFS  0xc64
+
+#define GT_PCI1_CMD_OFS         0xc80
+#define GT_PCI1_TOR_OFS         0xc84
+#define GT_PCI1_BS_SCS10_OFS    0xc88
+#define GT_PCI1_BS_SCS32_OFS    0xc8c
+#define GT_PCI1_BS_CS20_OFS     0xc90
+#define GT_PCI1_BS_CS3BT_OFS    0xc94
+
+#define GT_PCI1_BARE_OFS        0xcbc
+#define GT_PCI1_PREFMBR_OFS     0xcc0
+
+#define GT_PCI1_SCS10_BAR_OFS   0xcc8
+#define GT_PCI1_SCS32_BAR_OFS   0xccc
+#define GT_PCI1_CS20_BAR_OFS    0xcd0
+#define GT_PCI1_CS3BT_BAR_OFS   0xcd4
+#define GT_PCI1_SSCS10_BAR_OFS  0xcd8
+#define GT_PCI1_SSCS32_BAR_OFS  0xcdc
+
+#define GT_PCI1_SCS3BT_BAR_OFS  0xce4
+
+#define GT_PCI1_CFGADDR_OFS     0xcf0
+#define GT_PCI1_CFGDATA_OFS     0xcf4
+#define GT_PCI0_CFGADDR_OFS     0xcf8
+#define GT_PCI0_CFGDATA_OFS     0xcfc
+
+/* Interrupts.  */
+#define GT_INTRCAUSE_OFS        0xc18
+#define GT_INTRMASK_OFS         0xc1c
+
+#define GT_PCI0_ICMASK_OFS      0xc24
+#define GT_PCI0_SERR0MASK_OFS   0xc28
+
+#define GT_CPU_INTSEL_OFS       0xc70
+#define GT_PCI0_INTSEL_OFS      0xc74
+
+#define GT_HINTRCAUSE_OFS       0xc98
+#define GT_HINTRMASK_OFS        0xc9c
+
+#define GT_PCI0_HICMASK_OFS     0xca4
+#define GT_PCI1_SERR1MASK_OFS   0xca8
+
+
+/*
+ * I2O Support Registers
+ */
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE              0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE              0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE             0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE             0x01c
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE              0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE       0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE        0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE             0x02c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE      0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE       0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE    0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE   0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE                 0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE            0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE     0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE     0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE     0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE     0x06c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE    0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE    0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE    0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE    0x07c
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE              0x1c10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE              0x1c14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE             0x1c18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE             0x1c1c
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE              0x1c20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE       0x1c24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE        0x1c28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE             0x1c2c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE      0x1c30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE       0x1c34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE    0x1c40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE   0x1c44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE                 0x1c50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE            0x1c54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE     0x1c60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE     0x1c64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE     0x1c68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE     0x1c6c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE    0x1c70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE    0x1c74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE    0x1c78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE    0x1c7c
+
+/*
+ *  Register encodings
+ */
+#define GT_CPU_ENDIAN_SHF       12
+#define GT_CPU_ENDIAN_MSK       (MSK(1) << GT_CPU_ENDIAN_SHF)
+#define GT_CPU_ENDIAN_BIT       GT_CPU_ENDIAN_MSK
+#define GT_CPU_WR_SHF           16
+#define GT_CPU_WR_MSK           (MSK(1) << GT_CPU_WR_SHF)
+#define GT_CPU_WR_BIT           GT_CPU_WR_MSK
+#define GT_CPU_WR_DXDXDXDX      0
+#define GT_CPU_WR_DDDD          1
+
+
+#define GT_PCI_DCRM_SHF         21
+#define GT_PCI_LD_SHF           0
+#define GT_PCI_LD_MSK           (MSK(15) << GT_PCI_LD_SHF)
+#define GT_PCI_HD_SHF           0
+#define GT_PCI_HD_MSK           (MSK(7) << GT_PCI_HD_SHF)
+#define GT_PCI_REMAP_SHF        0
+#define GT_PCI_REMAP_MSK        (MSK(11) << GT_PCI_REMAP_SHF)
+
+
+#define GT_CFGADDR_CFGEN_SHF    31
+#define GT_CFGADDR_CFGEN_MSK    (MSK(1) << GT_CFGADDR_CFGEN_SHF)
+#define GT_CFGADDR_CFGEN_BIT    GT_CFGADDR_CFGEN_MSK
+
+#define GT_CFGADDR_BUSNUM_SHF   16
+#define GT_CFGADDR_BUSNUM_MSK   (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
+
+#define GT_CFGADDR_DEVNUM_SHF   11
+#define GT_CFGADDR_DEVNUM_MSK   (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
+
+#define GT_CFGADDR_FUNCNUM_SHF  8
+#define GT_CFGADDR_FUNCNUM_MSK  (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
+
+#define GT_CFGADDR_REGNUM_SHF   2
+#define GT_CFGADDR_REGNUM_MSK   (MSK(6) << GT_CFGADDR_REGNUM_SHF)
+
+
+#define GT_SDRAM_BM_ORDER_SHF   2
+#define GT_SDRAM_BM_ORDER_MSK   (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
+#define GT_SDRAM_BM_ORDER_BIT   GT_SDRAM_BM_ORDER_MSK
+#define GT_SDRAM_BM_ORDER_SUB   1
+#define GT_SDRAM_BM_ORDER_LIN   0
+
+#define GT_SDRAM_BM_RSVD_ALL1   0xffb
+
+
+#define GT_SDRAM_ADDRDECODE_ADDR_SHF    0
+#define GT_SDRAM_ADDRDECODE_ADDR_MSK    (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
+#define GT_SDRAM_ADDRDECODE_ADDR_0      0
+#define GT_SDRAM_ADDRDECODE_ADDR_1      1
+#define GT_SDRAM_ADDRDECODE_ADDR_2      2
+#define GT_SDRAM_ADDRDECODE_ADDR_3      3
+#define GT_SDRAM_ADDRDECODE_ADDR_4      4
+#define GT_SDRAM_ADDRDECODE_ADDR_5      5
+#define GT_SDRAM_ADDRDECODE_ADDR_6      6
+#define GT_SDRAM_ADDRDECODE_ADDR_7      7
+
+
+#define GT_SDRAM_B0_CASLAT_SHF          0
+#define GT_SDRAM_B0_CASLAT_MSK          (MSK(2) << GT_SDRAM_B0__SHF)
+#define GT_SDRAM_B0_CASLAT_2            1
+#define GT_SDRAM_B0_CASLAT_3            2
+
+#define GT_SDRAM_B0_FTDIS_SHF           2
+#define GT_SDRAM_B0_FTDIS_MSK           (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
+#define GT_SDRAM_B0_FTDIS_BIT           GT_SDRAM_B0_FTDIS_MSK
+
+#define GT_SDRAM_B0_SRASPRCHG_SHF       3
+#define GT_SDRAM_B0_SRASPRCHG_MSK       (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
+#define GT_SDRAM_B0_SRASPRCHG_BIT       GT_SDRAM_B0_SRASPRCHG_MSK
+#define GT_SDRAM_B0_SRASPRCHG_2         0
+#define GT_SDRAM_B0_SRASPRCHG_3         1
+
+#define GT_SDRAM_B0_B0COMPAB_SHF        4
+#define GT_SDRAM_B0_B0COMPAB_MSK        (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
+#define GT_SDRAM_B0_B0COMPAB_BIT        GT_SDRAM_B0_B0COMPAB_MSK
+
+#define GT_SDRAM_B0_64BITINT_SHF        5
+#define GT_SDRAM_B0_64BITINT_MSK        (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
+#define GT_SDRAM_B0_64BITINT_BIT        GT_SDRAM_B0_64BITINT_MSK
+#define GT_SDRAM_B0_64BITINT_2          0
+#define GT_SDRAM_B0_64BITINT_4          1
+
+#define GT_SDRAM_B0_BW_SHF              6
+#define GT_SDRAM_B0_BW_MSK              (MSK(1) << GT_SDRAM_B0_BW_SHF)
+#define GT_SDRAM_B0_BW_BIT              GT_SDRAM_B0_BW_MSK
+#define GT_SDRAM_B0_BW_32               0
+#define GT_SDRAM_B0_BW_64               1
+
+#define GT_SDRAM_B0_BLODD_SHF           7
+#define GT_SDRAM_B0_BLODD_MSK           (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
+#define GT_SDRAM_B0_BLODD_BIT           GT_SDRAM_B0_BLODD_MSK
+
+#define GT_SDRAM_B0_PAR_SHF             8
+#define GT_SDRAM_B0_PAR_MSK             (MSK(1) << GT_SDRAM_B0_PAR_SHF)
+#define GT_SDRAM_B0_PAR_BIT             GT_SDRAM_B0_PAR_MSK
+
+#define GT_SDRAM_B0_BYPASS_SHF          9
+#define GT_SDRAM_B0_BYPASS_MSK          (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
+#define GT_SDRAM_B0_BYPASS_BIT          GT_SDRAM_B0_BYPASS_MSK
+
+#define GT_SDRAM_B0_SRAS2SCAS_SHF       10
+#define GT_SDRAM_B0_SRAS2SCAS_MSK       (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
+#define GT_SDRAM_B0_SRAS2SCAS_BIT       GT_SDRAM_B0_SRAS2SCAS_MSK
+#define GT_SDRAM_B0_SRAS2SCAS_2         0
+#define GT_SDRAM_B0_SRAS2SCAS_3         1
+
+#define GT_SDRAM_B0_SIZE_SHF            11
+#define GT_SDRAM_B0_SIZE_MSK            (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
+#define GT_SDRAM_B0_SIZE_BIT            GT_SDRAM_B0_SIZE_MSK
+#define GT_SDRAM_B0_SIZE_16M            0
+#define GT_SDRAM_B0_SIZE_64M            1
+
+#define GT_SDRAM_B0_EXTPAR_SHF          12
+#define GT_SDRAM_B0_EXTPAR_MSK          (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
+#define GT_SDRAM_B0_EXTPAR_BIT          GT_SDRAM_B0_EXTPAR_MSK
+
+#define GT_SDRAM_B0_BLEN_SHF            13
+#define GT_SDRAM_B0_BLEN_MSK            (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
+#define GT_SDRAM_B0_BLEN_BIT            GT_SDRAM_B0_BLEN_MSK
+#define GT_SDRAM_B0_BLEN_8              0
+#define GT_SDRAM_B0_BLEN_4              1
+
+
+#define GT_SDRAM_CFG_REFINT_SHF         0
+#define GT_SDRAM_CFG_REFINT_MSK         (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
+
+#define GT_SDRAM_CFG_NINTERLEAVE_SHF    14
+#define GT_SDRAM_CFG_NINTERLEAVE_MSK    (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
+#define GT_SDRAM_CFG_NINTERLEAVE_BIT    GT_SDRAM_CFG_NINTERLEAVE_MSK
+
+#define GT_SDRAM_CFG_RMW_SHF            15
+#define GT_SDRAM_CFG_RMW_MSK            (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
+#define GT_SDRAM_CFG_RMW_BIT            GT_SDRAM_CFG_RMW_MSK
+
+#define GT_SDRAM_CFG_NONSTAGREF_SHF     16
+#define GT_SDRAM_CFG_NONSTAGREF_MSK     (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
+#define GT_SDRAM_CFG_NONSTAGREF_BIT     GT_SDRAM_CFG_NONSTAGREF_MSK
+
+#define GT_SDRAM_CFG_DUPCNTL_SHF        19
+#define GT_SDRAM_CFG_DUPCNTL_MSK        (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
+#define GT_SDRAM_CFG_DUPCNTL_BIT        GT_SDRAM_CFG_DUPCNTL_MSK
+
+#define GT_SDRAM_CFG_DUPBA_SHF          20
+#define GT_SDRAM_CFG_DUPBA_MSK          (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
+#define GT_SDRAM_CFG_DUPBA_BIT          GT_SDRAM_CFG_DUPBA_MSK
+
+#define GT_SDRAM_CFG_DUPEOT0_SHF        21
+#define GT_SDRAM_CFG_DUPEOT0_MSK        (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
+#define GT_SDRAM_CFG_DUPEOT0_BIT        GT_SDRAM_CFG_DUPEOT0_MSK
+
+#define GT_SDRAM_CFG_DUPEOT1_SHF        22
+#define GT_SDRAM_CFG_DUPEOT1_MSK        (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
+#define GT_SDRAM_CFG_DUPEOT1_BIT        GT_SDRAM_CFG_DUPEOT1_MSK
+
+#define GT_SDRAM_OPMODE_OP_SHF          0
+#define GT_SDRAM_OPMODE_OP_MSK          (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
+#define GT_SDRAM_OPMODE_OP_NORMAL       0
+#define GT_SDRAM_OPMODE_OP_NOP          1
+#define GT_SDRAM_OPMODE_OP_PRCHG        2
+#define GT_SDRAM_OPMODE_OP_MODE         3
+#define GT_SDRAM_OPMODE_OP_CBR          4
+
+#define GT_TC_CONTROL_ENTC0_SHF         0
+#define GT_TC_CONTROL_ENTC0_MSK         (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
+#define GT_TC_CONTROL_ENTC0_BIT         GT_TC_CONTROL_ENTC0_MSK
+#define GT_TC_CONTROL_SELTC0_SHF        1
+#define GT_TC_CONTROL_SELTC0_MSK        (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
+#define GT_TC_CONTROL_SELTC0_BIT        GT_TC_CONTROL_SELTC0_MSK
+
+
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF  0
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK  (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT  GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_SWSCS32DIS_SHF     1
+#define GT_PCI0_BARE_SWSCS32DIS_MSK     (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
+#define GT_PCI0_BARE_SWSCS32DIS_BIT     GT_PCI0_BARE_SWSCS32DIS_MSK
+
+#define GT_PCI0_BARE_SWSCS10DIS_SHF     2
+#define GT_PCI0_BARE_SWSCS10DIS_MSK     (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
+#define GT_PCI0_BARE_SWSCS10DIS_BIT     GT_PCI0_BARE_SWSCS10DIS_MSK
+
+#define GT_PCI0_BARE_INTIODIS_SHF       3
+#define GT_PCI0_BARE_INTIODIS_MSK       (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
+#define GT_PCI0_BARE_INTIODIS_BIT       GT_PCI0_BARE_INTIODIS_MSK
+
+#define GT_PCI0_BARE_INTMEMDIS_SHF      4
+#define GT_PCI0_BARE_INTMEMDIS_MSK      (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
+#define GT_PCI0_BARE_INTMEMDIS_BIT      GT_PCI0_BARE_INTMEMDIS_MSK
+
+#define GT_PCI0_BARE_CS3BOOTDIS_SHF     5
+#define GT_PCI0_BARE_CS3BOOTDIS_MSK     (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_CS3BOOTDIS_BIT     GT_PCI0_BARE_CS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_CS20DIS_SHF        6
+#define GT_PCI0_BARE_CS20DIS_MSK        (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
+#define GT_PCI0_BARE_CS20DIS_BIT        GT_PCI0_BARE_CS20DIS_MSK
+
+#define GT_PCI0_BARE_SCS32DIS_SHF       7
+#define GT_PCI0_BARE_SCS32DIS_MSK       (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
+#define GT_PCI0_BARE_SCS32DIS_BIT       GT_PCI0_BARE_SCS32DIS_MSK
+
+#define GT_PCI0_BARE_SCS10DIS_SHF       8
+#define GT_PCI0_BARE_SCS10DIS_MSK       (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
+#define GT_PCI0_BARE_SCS10DIS_BIT       GT_PCI0_BARE_SCS10DIS_MSK
+
+
+#define GT_INTRCAUSE_MASABORT0_SHF      18
+#define GT_INTRCAUSE_MASABORT0_MSK      (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
+#define GT_INTRCAUSE_MASABORT0_BIT      GT_INTRCAUSE_MASABORT0_MSK
+
+#define GT_INTRCAUSE_TARABORT0_SHF      19
+#define GT_INTRCAUSE_TARABORT0_MSK      (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
+#define GT_INTRCAUSE_TARABORT0_BIT      GT_INTRCAUSE_TARABORT0_MSK
+
+
+#define GT_PCI0_CFGADDR_REGNUM_SHF      2
+#define GT_PCI0_CFGADDR_REGNUM_MSK      (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
+#define GT_PCI0_CFGADDR_FUNCTNUM_SHF    8
+#define GT_PCI0_CFGADDR_FUNCTNUM_MSK    (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
+#define GT_PCI0_CFGADDR_DEVNUM_SHF      11
+#define GT_PCI0_CFGADDR_DEVNUM_MSK      (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
+#define GT_PCI0_CFGADDR_BUSNUM_SHF      16
+#define GT_PCI0_CFGADDR_BUSNUM_MSK      (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_SHF    31
+#define GT_PCI0_CFGADDR_CONFIGEN_MSK    (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_BIT    GT_PCI0_CFGADDR_CONFIGEN_MSK
+
+#define GT_PCI0_CMD_MBYTESWAP_SHF       0
+#define GT_PCI0_CMD_MBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
+#define GT_PCI0_CMD_MBYTESWAP_BIT       GT_PCI0_CMD_MBYTESWAP_MSK
+#define GT_PCI0_CMD_MWORDSWAP_SHF       10
+#define GT_PCI0_CMD_MWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
+#define GT_PCI0_CMD_MWORDSWAP_BIT       GT_PCI0_CMD_MWORDSWAP_MSK
+#define GT_PCI0_CMD_SBYTESWAP_SHF       16
+#define GT_PCI0_CMD_SBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
+#define GT_PCI0_CMD_SBYTESWAP_BIT       GT_PCI0_CMD_SBYTESWAP_MSK
+#define GT_PCI0_CMD_SWORDSWAP_SHF       11
+#define GT_PCI0_CMD_SWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
+#define GT_PCI0_CMD_SWORDSWAP_BIT       GT_PCI0_CMD_SWORDSWAP_MSK
+
+#define GT_INTR_T0EXP_SHF               8
+#define GT_INTR_T0EXP_MSK               (MSK(1) << GT_INTR_T0EXP_SHF)
+#define GT_INTR_T0EXP_BIT               GT_INTR_T0EXP_MSK
+#define GT_INTR_RETRYCTR0_SHF           20
+#define GT_INTR_RETRYCTR0_MSK           (MSK(1) << GT_INTR_RETRYCTR0_SHF)
+#define GT_INTR_RETRYCTR0_BIT           GT_INTR_RETRYCTR0_MSK
+
+/*
+ *  Misc
+ */
+#define GT_DEF_PCI0_IO_BASE     0x10000000UL
+#define GT_DEF_PCI0_IO_SIZE     0x02000000UL
+#define GT_DEF_PCI0_MEM0_BASE   0x12000000UL
+#define GT_DEF_PCI0_MEM0_SIZE   0x02000000UL
+#define GT_DEF_BASE             0x14000000UL
+
+#define GT_MAX_BANKSIZE         (256 * 1024 * 1024)     /* Max 256MB bank  */
+#define GT_LATTIM_MIN           6                       /* Minimum lat  */
+
+/*
+ * The gt64120_dep.h file must define the following macros
+ *
+ *   GT_READ(ofs, data_pointer)
+ *   GT_WRITE(ofs, data)           - read/write GT64120 registers in 32bit
+ *
+ *   TIMER      - gt64120 timer irq, temporary solution until
+ *                full gt64120 cascade interrupt support is in place
+ */
+
+#include <mach-gt64120.h>
+
+/*
+ * Because of an error/peculiarity in the Galileo chip, we need to swap the
+ * bytes when running bigendian.  We also provide non-swapping versions.
+ */
+#define __GT_READ(ofs)                                                  \
+        (*(volatile u32 *)(GT64120_BASE+(ofs)))
+#define __GT_WRITE(ofs, data)                                           \
+        do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
+#define GT_READ(ofs)            le32_to_cpu(__GT_READ(ofs))
+#define GT_WRITE(ofs, data)     __GT_WRITE(ofs, cpu_to_le32(data))
+
+extern void gt641xx_set_base_clock(unsigned int clock);
+extern int gt641xx_timer0_state(void);
+
+#endif /* _ASM_GT64120_H */
diff --git a/arch/mips/include/asm/hardirq.h b/arch/mips/include/asm/hardirq.h
new file mode 100644
index 000000000000..90bf399e6dd9
--- /dev/null
+++ b/arch/mips/include/asm/hardirq.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 98, 99, 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_HARDIRQ_H
+#define _ASM_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/irq.h>
+
+typedef struct {
+        unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+extern void ack_bad_irq(unsigned int irq);
+
+#endif /* _ASM_HARDIRQ_H */
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
new file mode 100644
index 000000000000..2de638f84c86
--- /dev/null
+++ b/arch/mips/include/asm/hazards.h
@@ -0,0 +1,271 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) MIPS Technologies, Inc.
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef _ASM_HAZARDS_H
+#define _ASM_HAZARDS_H
+
+#ifdef __ASSEMBLY__
+#define ASMMACRO(name, code...) .macro name; code; .endm
+#else
+
+#include <asm/cpu-features.h>
+
+#define ASMMACRO(name, code...)                                         \
+__asm__(".macro " #name "; " #code "; .endm");                          \
+                                                                        \
+static inline void name(void)                                           \
+{                                                                       \
+        __asm__ __volatile__ (#name);                                   \
+}
+
+/*
+ * MIPS R2 instruction hazard barrier.   Needs to be called as a subroutine.
+ */
+extern void mips_ihb(void);
+
+#endif
+
+ASMMACRO(_ssnop,
+         sll    $0, $0, 1
+        )
+
+ASMMACRO(_ehb,
+         sll    $0, $0, 3
+        )
+
+/*
+ * TLB hazards
+ */
+#if defined(CONFIG_CPU_MIPSR2)
+
+/*
+ * MIPSR2 defines ehb for hazard avoidance
+ */
+
+ASMMACRO(mtc0_tlbw_hazard,
+         _ehb
+        )
+ASMMACRO(tlbw_use_hazard,
+         _ehb
+        )
+ASMMACRO(tlb_probe_hazard,
+         _ehb
+        )
+ASMMACRO(irq_enable_hazard,
+         _ehb
+        )
+ASMMACRO(irq_disable_hazard,
+        _ehb
+        )
+ASMMACRO(back_to_back_c0_hazard,
+         _ehb
+        )
+/*
+ * gcc has a tradition of misscompiling the previous construct using the
+ * address of a label as argument to inline assembler.  Gas otoh has the
+ * annoying difference between la and dla which are only usable for 32-bit
+ * rsp. 64-bit code, so can't be used without conditional compilation.
+ * The alterantive is switching the assembler to 64-bit code which happens
+ * to work right even for 32-bit code ...
+ */
+#define instruction_hazard()                                            \
+do {                                                                    \
+        unsigned long tmp;                                              \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    mips64r2                                \n"     \
+        "       dla     %0, 1f                                  \n"     \
+        "       jr.hb   %0                                      \n"     \
+        "       .set    mips0                                   \n"     \
+        "1:                                                     \n"     \
+        : "=r" (tmp));                                                  \
+} while (0)
+
+#elif defined(CONFIG_CPU_MIPSR1)
+
+/*
+ * These are slightly complicated by the fact that we guarantee R1 kernels to
+ * run fine on R2 processors.
+ */
+ASMMACRO(mtc0_tlbw_hazard,
+        _ssnop; _ssnop; _ehb
+        )
+ASMMACRO(tlbw_use_hazard,
+        _ssnop; _ssnop; _ssnop; _ehb
+        )
+ASMMACRO(tlb_probe_hazard,
+         _ssnop; _ssnop; _ssnop; _ehb
+        )
+ASMMACRO(irq_enable_hazard,
+         _ssnop; _ssnop; _ssnop; _ehb
+        )
+ASMMACRO(irq_disable_hazard,
+        _ssnop; _ssnop; _ssnop; _ehb
+        )
+ASMMACRO(back_to_back_c0_hazard,
+         _ssnop; _ssnop; _ssnop; _ehb
+        )
+/*
+ * gcc has a tradition of misscompiling the previous construct using the
+ * address of a label as argument to inline assembler.  Gas otoh has the
+ * annoying difference between la and dla which are only usable for 32-bit
+ * rsp. 64-bit code, so can't be used without conditional compilation.
+ * The alterantive is switching the assembler to 64-bit code which happens
+ * to work right even for 32-bit code ...
+ */
+#define __instruction_hazard()                                          \
+do {                                                                    \
+        unsigned long tmp;                                              \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    mips64r2                                \n"     \
+        "       dla     %0, 1f                                  \n"     \
+        "       jr.hb   %0                                      \n"     \
+        "       .set    mips0                                   \n"     \
+        "1:                                                     \n"     \
+        : "=r" (tmp));                                                  \
+} while (0)
+
+#define instruction_hazard()                                            \
+do {                                                                    \
+        if (cpu_has_mips_r2)                                            \
+                __instruction_hazard();                                 \
+} while (0)
+
+#elif defined(CONFIG_CPU_R10000)
+
+/*
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ */
+
+ASMMACRO(mtc0_tlbw_hazard,
+        )
+ASMMACRO(tlbw_use_hazard,
+        )
+ASMMACRO(tlb_probe_hazard,
+        )
+ASMMACRO(irq_enable_hazard,
+        )
+ASMMACRO(irq_disable_hazard,
+        )
+ASMMACRO(back_to_back_c0_hazard,
+        )
+#define instruction_hazard() do { } while (0)
+
+#elif defined(CONFIG_CPU_RM9000)
+
+/*
+ * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
+ * use of the JTLB for instructions should not occur for 4 cpu cycles and use
+ * for data translations should not occur for 3 cpu cycles.
+ */
+
+ASMMACRO(mtc0_tlbw_hazard,
+         _ssnop; _ssnop; _ssnop; _ssnop
+        )
+ASMMACRO(tlbw_use_hazard,
+         _ssnop; _ssnop; _ssnop; _ssnop
+        )
+ASMMACRO(tlb_probe_hazard,
+         _ssnop; _ssnop; _ssnop; _ssnop
+        )
+ASMMACRO(irq_enable_hazard,
+        )
+ASMMACRO(irq_disable_hazard,
+        )
+ASMMACRO(back_to_back_c0_hazard,
+        )
+#define instruction_hazard() do { } while (0)
+
+#elif defined(CONFIG_CPU_SB1)
+
+/*
+ * Mostly like R4000 for historic reasons
+ */
+ASMMACRO(mtc0_tlbw_hazard,
+        )
+ASMMACRO(tlbw_use_hazard,
+        )
+ASMMACRO(tlb_probe_hazard,
+        )
+ASMMACRO(irq_enable_hazard,
+        )
+ASMMACRO(irq_disable_hazard,
+         _ssnop; _ssnop; _ssnop
+        )
+ASMMACRO(back_to_back_c0_hazard,
+        )
+#define instruction_hazard() do { } while (0)
+
+#else
+
+/*
+ * Finally the catchall case for all other processors including R4000, R4400,
+ * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
+ *
+ * The taken branch will result in a two cycle penalty for the two killed
+ * instructions on R4000 / R4400.  Other processors only have a single cycle
+ * hazard so this is nice trick to have an optimal code for a range of
+ * processors.
+ */
+ASMMACRO(mtc0_tlbw_hazard,
+        nop; nop
+        )
+ASMMACRO(tlbw_use_hazard,
+        nop; nop; nop
+        )
+ASMMACRO(tlb_probe_hazard,
+         nop; nop; nop
+        )
+ASMMACRO(irq_enable_hazard,
+         _ssnop; _ssnop; _ssnop;
+        )
+ASMMACRO(irq_disable_hazard,
+        nop; nop; nop
+        )
+ASMMACRO(back_to_back_c0_hazard,
+         _ssnop; _ssnop; _ssnop;
+        )
+#define instruction_hazard() do { } while (0)
+
+#endif
+
+
+/* FPU hazards */
+
+#if defined(CONFIG_CPU_SB1)
+ASMMACRO(enable_fpu_hazard,
+         .set   push;
+         .set   mips64;
+         .set   noreorder;
+         _ssnop;
+         bnezl  $0, .+4;
+         _ssnop;
+         .set   pop
+)
+ASMMACRO(disable_fpu_hazard,
+)
+
+#elif defined(CONFIG_CPU_MIPSR2)
+ASMMACRO(enable_fpu_hazard,
+         _ehb
+)
+ASMMACRO(disable_fpu_hazard,
+         _ehb
+)
+#else
+ASMMACRO(enable_fpu_hazard,
+         nop; nop; nop; nop
+)
+ASMMACRO(disable_fpu_hazard,
+         _ehb
+)
+#endif
+
+#endif /* _ASM_HAZARDS_H */
diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h
new file mode 100644
index 000000000000..4374ab2adc75
--- /dev/null
+++ b/arch/mips/include/asm/highmem.h
@@ -0,0 +1,67 @@
+/*
+ * highmem.h: virtual kernel memory mappings for high memory
+ *
+ * Used in CONFIG_HIGHMEM systems for memory pages which
+ * are not addressable by direct kernel virtual addresses.
+ *
+ * Copyright (C) 1999 Gerhard Wichert, Siemens AG
+ *                    Gerhard.Wichert@pdb.siemens.de
+ *
+ *
+ * Redesigned the x86 32-bit VM architecture to deal with
+ * up to 16 Terabyte physical memory. With current x86 CPUs
+ * we now support up to 64 Gigabytes physical RAM.
+ *
+ * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
+ */
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/uaccess.h>
+#include <asm/kmap_types.h>
+
+/* undef for production */
+#define HIGHMEM_DEBUG 1
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *kmap_pte;
+extern pgprot_t kmap_prot;
+extern pte_t *pkmap_page_table;
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+#define LAST_PKMAP 1024
+#define LAST_PKMAP_MASK (LAST_PKMAP-1)
+#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+extern void * kmap_high(struct page *page);
+extern void kunmap_high(struct page *page);
+
+extern void *__kmap(struct page *page);
+extern void __kunmap(struct page *page);
+extern void *__kmap_atomic(struct page *page, enum km_type type);
+extern void __kunmap_atomic(void *kvaddr, enum km_type type);
+extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
+extern struct page *__kmap_atomic_to_page(void *ptr);
+
+#define kmap                    __kmap
+#define kunmap                  __kunmap
+#define kmap_atomic             __kmap_atomic
+#define kunmap_atomic           __kunmap_atomic
+#define kmap_atomic_to_page     __kmap_atomic_to_page
+
+#define flush_cache_kmaps()     flush_cache_all()
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/mips/include/asm/hw_irq.h b/arch/mips/include/asm/hw_irq.h
new file mode 100644
index 000000000000..aca05a43a97b
--- /dev/null
+++ b/arch/mips/include/asm/hw_irq.h
@@ -0,0 +1,20 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 2001, 2002 by Ralf Baechle
+ */
+#ifndef __ASM_HW_IRQ_H
+#define __ASM_HW_IRQ_H
+
+#include <asm/atomic.h>
+
+extern atomic_t irq_err_count;
+
+/*
+ * interrupt-retrigger: NOP for now. This may not be apropriate for all
+ * machines, we'll see ...
+ */
+
+#endif /* __ASM_HW_IRQ_H */
diff --git a/arch/mips/include/asm/i8253.h b/arch/mips/include/asm/i8253.h
new file mode 100644
index 000000000000..5dabc870b322
--- /dev/null
+++ b/arch/mips/include/asm/i8253.h
@@ -0,0 +1,21 @@
+/*
+ *  Machine specific IO port address definition for generic.
+ *  Written by Osamu Tomita <tomita@cinet.co.jp>
+ */
+#ifndef __ASM_I8253_H
+#define __ASM_I8253_H
+
+#include <linux/spinlock.h>
+
+/* i8253A PIT registers */
+#define PIT_MODE                0x43
+#define PIT_CH0                 0x40
+#define PIT_CH2                 0x42
+
+#define PIT_TICK_RATE           1193182UL
+
+extern spinlock_t i8253_lock;
+
+extern void setup_pit_timer(void);
+
+#endif /* __ASM_I8253_H */
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
new file mode 100644
index 000000000000..8572a2d90484
--- /dev/null
+++ b/arch/mips/include/asm/i8259.h
@@ -0,0 +1,86 @@
+/*
+ *      include/asm-mips/i8259.h
+ *
+ *      i8259A interrupt definitions.
+ *
+ *      Copyright (C) 2003  Maciej W. Rozycki
+ *      Copyright (C) 2003  Ralf Baechle <ralf@linux-mips.org>
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_I8259_H
+#define _ASM_I8259_H
+
+#include <linux/compiler.h>
+#include <linux/spinlock.h>
+
+#include <asm/io.h>
+#include <irq.h>
+
+/* i8259A PIC registers */
+#define PIC_MASTER_CMD          0x20
+#define PIC_MASTER_IMR          0x21
+#define PIC_MASTER_ISR          PIC_MASTER_CMD
+#define PIC_MASTER_POLL         PIC_MASTER_ISR
+#define PIC_MASTER_OCW3         PIC_MASTER_ISR
+#define PIC_SLAVE_CMD           0xa0
+#define PIC_SLAVE_IMR           0xa1
+
+/* i8259A PIC related value */
+#define PIC_CASCADE_IR          2
+#define MASTER_ICW4_DEFAULT     0x01
+#define SLAVE_ICW4_DEFAULT      0x01
+#define PIC_ICW4_AEOI           2
+
+extern spinlock_t i8259A_lock;
+
+extern int i8259A_irq_pending(unsigned int irq);
+extern void make_8259A_irq(unsigned int irq);
+
+extern void init_i8259_irqs(void);
+
+/*
+ * Do the traditional i8259 interrupt polling thing.  This is for the few
+ * cases where no better interrupt acknowledge method is available and we
+ * absolutely must touch the i8259.
+ */
+static inline int i8259_irq(void)
+{
+        int irq;
+
+        spin_lock(&i8259A_lock);
+
+        /* Perform an interrupt acknowledge cycle on controller 1. */
+        outb(0x0C, PIC_MASTER_CMD);             /* prepare for poll */
+        irq = inb(PIC_MASTER_CMD) & 7;
+        if (irq == PIC_CASCADE_IR) {
+                /*
+                 * Interrupt is cascaded so perform interrupt
+                 * acknowledge on controller 2.
+                 */
+                outb(0x0C, PIC_SLAVE_CMD);              /* prepare for poll */
+                irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
+        }
+
+        if (unlikely(irq == 7)) {
+                /*
+                 * This may be a spurious interrupt.
+                 *
+                 * Read the interrupt status register (ISR). If the most
+                 * significant bit is not set then there is no valid
+                 * interrupt.
+                 */
+                outb(0x0B, PIC_MASTER_ISR);             /* ISR register */
+                if(~inb(PIC_MASTER_ISR) & 0x80)
+                        irq = -1;
+        }
+
+        spin_unlock(&i8259A_lock);
+
+        return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
+}
+
+#endif /* _ASM_I8259_H */
diff --git a/arch/mips/include/asm/ide.h b/arch/mips/include/asm/ide.h
new file mode 100644
index 000000000000..bb674c3b0303
--- /dev/null
+++ b/arch/mips/include/asm/ide.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This file contains the MIPS architecture specific IDE code.
+ */
+#ifndef __ASM_IDE_H
+#define __ASM_IDE_H
+
+#include <ide.h>
+
+#endif /* __ASM_IDE_H */
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
new file mode 100644
index 000000000000..6489f00731ca
--- /dev/null
+++ b/arch/mips/include/asm/inst.h
@@ -0,0 +1,394 @@
+/*
+ * Format of an instruction in memory.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 2000 by Ralf Baechle
+ * Copyright (C) 2006 by Thiemo Seufer
+ */
+#ifndef _ASM_INST_H
+#define _ASM_INST_H
+
+/*
+ * Major opcodes; before MIPS IV cop1x was called cop3.
+ */
+enum major_op {
+        spec_op, bcond_op, j_op, jal_op,
+        beq_op, bne_op, blez_op, bgtz_op,
+        addi_op, addiu_op, slti_op, sltiu_op,
+        andi_op, ori_op, xori_op, lui_op,
+        cop0_op, cop1_op, cop2_op, cop1x_op,
+        beql_op, bnel_op, blezl_op, bgtzl_op,
+        daddi_op, daddiu_op, ldl_op, ldr_op,
+        spec2_op, jalx_op, mdmx_op, spec3_op,
+        lb_op, lh_op, lwl_op, lw_op,
+        lbu_op, lhu_op, lwr_op, lwu_op,
+        sb_op, sh_op, swl_op, sw_op,
+        sdl_op, sdr_op, swr_op, cache_op,
+        ll_op, lwc1_op, lwc2_op, pref_op,
+        lld_op, ldc1_op, ldc2_op, ld_op,
+        sc_op, swc1_op, swc2_op, major_3b_op,
+        scd_op, sdc1_op, sdc2_op, sd_op
+};
+
+/*
+ * func field of spec opcode.
+ */
+enum spec_op {
+        sll_op, movc_op, srl_op, sra_op,
+        sllv_op, pmon_op, srlv_op, srav_op,
+        jr_op, jalr_op, movz_op, movn_op,
+        syscall_op, break_op, spim_op, sync_op,
+        mfhi_op, mthi_op, mflo_op, mtlo_op,
+        dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
+        mult_op, multu_op, div_op, divu_op,
+        dmult_op, dmultu_op, ddiv_op, ddivu_op,
+        add_op, addu_op, sub_op, subu_op,
+        and_op, or_op, xor_op, nor_op,
+        spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
+        dadd_op, daddu_op, dsub_op, dsubu_op,
+        tge_op, tgeu_op, tlt_op, tltu_op,
+        teq_op, spec5_unused_op, tne_op, spec6_unused_op,
+        dsll_op, spec7_unused_op, dsrl_op, dsra_op,
+        dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
+};
+
+/*
+ * func field of spec2 opcode.
+ */
+enum spec2_op {
+        madd_op, maddu_op, mul_op, spec2_3_unused_op,
+        msub_op, msubu_op, /* more unused ops */
+        clz_op = 0x20, clo_op,
+        dclz_op = 0x24, dclo_op,
+        sdbpp_op = 0x3f
+};
+
+/*
+ * func field of spec3 opcode.
+ */
+enum spec3_op {
+        ext_op, dextm_op, dextu_op, dext_op,
+        ins_op, dinsm_op, dinsu_op, dins_op,
+        bshfl_op = 0x20,
+        dbshfl_op = 0x24,
+        rdhwr_op = 0x3b
+};
+
+/*
+ * rt field of bcond opcodes.
+ */
+enum rt_op {
+        bltz_op, bgez_op, bltzl_op, bgezl_op,
+        spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
+        tgei_op, tgeiu_op, tlti_op, tltiu_op,
+        teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
+        bltzal_op, bgezal_op, bltzall_op, bgezall_op,
+        rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
+        rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
+        bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
+};
+
+/*
+ * rs field of cop opcodes.
+ */
+enum cop_op {
+        mfc_op        = 0x00, dmfc_op       = 0x01,
+        cfc_op        = 0x02, mtc_op        = 0x04,
+        dmtc_op       = 0x05, ctc_op        = 0x06,
+        bc_op         = 0x08, cop_op        = 0x10,
+        copm_op       = 0x18
+};
+
+/*
+ * rt field of cop.bc_op opcodes
+ */
+enum bcop_op {
+        bcf_op, bct_op, bcfl_op, bctl_op
+};
+
+/*
+ * func field of cop0 coi opcodes.
+ */
+enum cop0_coi_func {
+        tlbr_op       = 0x01, tlbwi_op      = 0x02,
+        tlbwr_op      = 0x06, tlbp_op       = 0x08,
+        rfe_op        = 0x10, eret_op       = 0x18
+};
+
+/*
+ * func field of cop0 com opcodes.
+ */
+enum cop0_com_func {
+        tlbr1_op      = 0x01, tlbw_op       = 0x02,
+        tlbp1_op      = 0x08, dctr_op       = 0x09,
+        dctw_op       = 0x0a
+};
+
+/*
+ * fmt field of cop1 opcodes.
+ */
+enum cop1_fmt {
+        s_fmt, d_fmt, e_fmt, q_fmt,
+        w_fmt, l_fmt
+};
+
+/*
+ * func field of cop1 instructions using d, s or w format.
+ */
+enum cop1_sdw_func {
+        fadd_op      =  0x00, fsub_op      =  0x01,
+        fmul_op      =  0x02, fdiv_op      =  0x03,
+        fsqrt_op     =  0x04, fabs_op      =  0x05,
+        fmov_op      =  0x06, fneg_op      =  0x07,
+        froundl_op   =  0x08, ftruncl_op   =  0x09,
+        fceill_op    =  0x0a, ffloorl_op   =  0x0b,
+        fround_op    =  0x0c, ftrunc_op    =  0x0d,
+        fceil_op     =  0x0e, ffloor_op    =  0x0f,
+        fmovc_op     =  0x11, fmovz_op     =  0x12,
+        fmovn_op     =  0x13, frecip_op    =  0x15,
+        frsqrt_op    =  0x16, fcvts_op     =  0x20,
+        fcvtd_op     =  0x21, fcvte_op     =  0x22,
+        fcvtw_op     =  0x24, fcvtl_op     =  0x25,
+        fcmp_op      =  0x30
+};
+
+/*
+ * func field of cop1x opcodes (MIPS IV).
+ */
+enum cop1x_func {
+        lwxc1_op     =  0x00, ldxc1_op     =  0x01,
+        pfetch_op    =  0x07, swxc1_op     =  0x08,
+        sdxc1_op     =  0x09, madd_s_op    =  0x20,
+        madd_d_op    =  0x21, madd_e_op    =  0x22,
+        msub_s_op    =  0x28, msub_d_op    =  0x29,
+        msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
+        nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
+        nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
+        nmsub_e_op   =  0x3a
+};
+
+/*
+ * func field for mad opcodes (MIPS IV).
+ */
+enum mad_func {
+        madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
+        nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
+};
+
+/*
+ * Damn ...  bitfields depend from byteorder :-(
+ */
+#ifdef __MIPSEB__
+struct j_format {       /* Jump format */
+        unsigned int opcode : 6;
+        unsigned int target : 26;
+};
+
+struct i_format {       /* Immediate format (addi, lw, ...) */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int rt : 5;
+        signed int simmediate : 16;
+};
+
+struct u_format {       /* Unsigned immediate format (ori, xori, ...) */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int rt : 5;
+        unsigned int uimmediate : 16;
+};
+
+struct c_format {       /* Cache (>= R6000) format */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int c_op : 3;
+        unsigned int cache : 2;
+        unsigned int simmediate : 16;
+};
+
+struct r_format {       /* Register format */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int rt : 5;
+        unsigned int rd : 5;
+        unsigned int re : 5;
+        unsigned int func : 6;
+};
+
+struct p_format {       /* Performance counter format (R10000) */
+        unsigned int opcode : 6;
+        unsigned int rs : 5;
+        unsigned int rt : 5;
+        unsigned int rd : 5;
+        unsigned int re : 5;
+        unsigned int func : 6;
+};
+
+struct f_format {       /* FPU register format */
+        unsigned int opcode : 6;
+        unsigned int : 1;
+        unsigned int fmt : 4;
+        unsigned int rt : 5;
+        unsigned int rd : 5;
+        unsigned int re : 5;
+        unsigned int func : 6;
+};
+
+struct ma_format {      /* FPU multipy and add format (MIPS IV) */
+        unsigned int opcode : 6;
+        unsigned int fr : 5;
+        unsigned int ft : 5;
+        unsigned int fs : 5;
+        unsigned int fd : 5;
+        unsigned int func : 4;
+        unsigned int fmt : 2;
+};
+
+#elif defined(__MIPSEL__)
+
+struct j_format {       /* Jump format */
+        unsigned int target : 26;
+        unsigned int opcode : 6;
+};
+
+struct i_format {       /* Immediate format */
+        signed int simmediate : 16;
+        unsigned int rt : 5;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct u_format {       /* Unsigned immediate format */
+        unsigned int uimmediate : 16;
+        unsigned int rt : 5;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct c_format {       /* Cache (>= R6000) format */
+        unsigned int simmediate : 16;
+        unsigned int cache : 2;
+        unsigned int c_op : 3;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct r_format {       /* Register format */
+        unsigned int func : 6;
+        unsigned int re : 5;
+        unsigned int rd : 5;
+        unsigned int rt : 5;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct p_format {       /* Performance counter format (R10000) */
+        unsigned int func : 6;
+        unsigned int re : 5;
+        unsigned int rd : 5;
+        unsigned int rt : 5;
+        unsigned int rs : 5;
+        unsigned int opcode : 6;
+};
+
+struct f_format {       /* FPU register format */
+        unsigned int func : 6;
+        unsigned int re : 5;
+        unsigned int rd : 5;
+        unsigned int rt : 5;
+        unsigned int fmt : 4;
+        unsigned int : 1;
+        unsigned int opcode : 6;
+};
+
+struct ma_format {      /* FPU multipy and add format (MIPS IV) */
+        unsigned int fmt : 2;
+        unsigned int func : 4;
+        unsigned int fd : 5;
+        unsigned int fs : 5;
+        unsigned int ft : 5;
+        unsigned int fr : 5;
+        unsigned int opcode : 6;
+};
+
+#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
+#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
+#endif
+
+union mips_instruction {
+        unsigned int word;
+        unsigned short halfword[2];
+        unsigned char byte[4];
+        struct j_format j_format;
+        struct i_format i_format;
+        struct u_format u_format;
+        struct c_format c_format;
+        struct r_format r_format;
+        struct f_format f_format;
+        struct ma_format ma_format;
+};
+
+/* HACHACHAHCAHC ...  */
+
+/* In case some other massaging is needed, keep MIPSInst as wrapper */
+
+#define MIPSInst(x) x
+
+#define I_OPCODE_SFT    26
+#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
+
+#define I_JTARGET_SFT   0
+#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
+
+#define I_RS_SFT        21
+#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
+
+#define I_RT_SFT        16
+#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
+
+#define I_IMM_SFT       0
+#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
+#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
+
+#define I_CACHEOP_SFT   18
+#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
+
+#define I_CACHESEL_SFT  16
+#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
+
+#define I_RD_SFT        11
+#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
+
+#define I_RE_SFT        6
+#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
+
+#define I_FUNC_SFT      0
+#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
+
+#define I_FFMT_SFT      21
+#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
+
+#define I_FT_SFT        16
+#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
+
+#define I_FS_SFT        11
+#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
+
+#define I_FD_SFT        6
+#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
+
+#define I_FR_SFT        21
+#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
+
+#define I_FMA_FUNC_SFT  2
+#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
+
+#define I_FMA_FFMT_SFT  0
+#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
+
+typedef unsigned int mips_instruction;
+
+#endif /* _ASM_INST_H */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
new file mode 100644
index 000000000000..501a40b9f18d
--- /dev/null
+++ b/arch/mips/include/asm/io.h
@@ -0,0 +1,589 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995 Waldorf GmbH
+ * Copyright (C) 1994 - 2000, 06 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
+ *      Author: Maciej W. Rozycki <macro@mips.com>
+ */
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm-generic/iomap.h>
+#include <asm/page.h>
+#include <asm/pgtable-bits.h>
+#include <asm/processor.h>
+#include <asm/string.h>
+
+#include <ioremap.h>
+#include <mangle-port.h>
+
+/*
+ * Slowdown I/O port space accesses for antique hardware.
+ */
+#undef CONF_SLOWDOWN_IO
+
+/*
+ * Raw operations are never swapped in software.  OTOH values that raw
+ * operations are working on may or may not have been swapped by the bus
+ * hardware.  An example use would be for flash memory that's used for
+ * execute in place.
+ */
+# define __raw_ioswabb(a, x)    (x)
+# define __raw_ioswabw(a, x)    (x)
+# define __raw_ioswabl(a, x)    (x)
+# define __raw_ioswabq(a, x)    (x)
+# define ____raw_ioswabq(a, x)  (x)
+
+/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
+
+#define IO_SPACE_LIMIT 0xffff
+
+/*
+ * On MIPS I/O ports are memory mapped, so we access them using normal
+ * load/store instructions. mips_io_port_base is the virtual address to
+ * which all ports are being mapped.  For sake of efficiency some code
+ * assumes that this is an address that can be loaded with a single lui
+ * instruction, so the lower 16 bits must be zero.  Should be true on
+ * on any sane architecture; generic code does not use this assumption.
+ */
+extern const unsigned long mips_io_port_base;
+
+/*
+ * Gcc will generate code to load the value of mips_io_port_base after each
+ * function call which may be fairly wasteful in some cases.  So we don't
+ * play quite by the book.  We tell gcc mips_io_port_base is a long variable
+ * which solves the code generation issue.  Now we need to violate the
+ * aliasing rules a little to make initialization possible and finally we
+ * will need the barrier() to fight side effects of the aliasing chat.
+ * This trickery will eventually collapse under gcc's optimizer.  Oh well.
+ */
+static inline void set_io_port_base(unsigned long base)
+{
+        * (unsigned long *) &mips_io_port_base = base;
+        barrier();
+}
+
+/*
+ * Thanks to James van Artsdalen for a better timing-fix than
+ * the two short jumps: using outb's to a nonexistent port seems
+ * to guarantee better timings even on fast machines.
+ *
+ * On the other hand, I'd like to be sure of a non-existent port:
+ * I feel a bit unsafe about using 0x80 (should be safe, though)
+ *
+ *              Linus
+ *
+ */
+
+#define __SLOW_DOWN_IO \
+        __asm__ __volatile__( \
+                "sb\t$0,0x80(%0)" \
+                : : "r" (mips_io_port_base));
+
+#ifdef CONF_SLOWDOWN_IO
+#ifdef REALLY_SLOW_IO
+#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
+#else
+#define SLOW_DOWN_IO __SLOW_DOWN_IO
+#endif
+#else
+#define SLOW_DOWN_IO
+#endif
+
+/*
+ *     virt_to_phys    -       map virtual addresses to physical
+ *     @address: address to remap
+ *
+ *     The returned physical address is the physical (CPU) mapping for
+ *     the memory address given. It is only valid to use this function on
+ *     addresses directly mapped or allocated via kmalloc.
+ *
+ *     This function does not give bus mappings for DMA transfers. In
+ *     almost all conceivable cases a device driver should not be using
+ *     this function
+ */
+static inline unsigned long virt_to_phys(volatile const void *address)
+{
+        return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET;
+}
+
+/*
+ *     phys_to_virt    -       map physical address to virtual
+ *     @address: address to remap
+ *
+ *     The returned virtual address is a current CPU mapping for
+ *     the memory address given. It is only valid to use this function on
+ *     addresses that have a kernel mapping
+ *
+ *     This function does not handle bus mappings for DMA transfers. In
+ *     almost all conceivable cases a device driver should not be using
+ *     this function
+ */
+static inline void * phys_to_virt(unsigned long address)
+{
+        return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
+}
+
+/*
+ * ISA I/O bus memory addresses are 1:1 with the physical address.
+ */
+static inline unsigned long isa_virt_to_bus(volatile void * address)
+{
+        return (unsigned long)address - PAGE_OFFSET;
+}
+
+static inline void * isa_bus_to_virt(unsigned long address)
+{
+        return (void *)(address + PAGE_OFFSET);
+}
+
+#define isa_page_to_bus page_to_phys
+
+/*
+ * However PCI ones are not necessarily 1:1 and therefore these interfaces
+ * are forbidden in portable PCI drivers.
+ *
+ * Allow them for x86 for legacy drivers, though.
+ */
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+/*
+ * Change "struct page" to physical address.
+ */
+#define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
+
+extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
+extern void __iounmap(const volatile void __iomem *addr);
+
+static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        void __iomem *addr = plat_ioremap(offset, size, flags);
+
+        if (addr)
+                return addr;
+
+#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
+
+        if (cpu_has_64bit_addresses) {
+                u64 base = UNCAC_BASE;
+
+                /*
+                 * R10000 supports a 2 bit uncached attribute therefore
+                 * UNCAC_BASE may not equal IO_BASE.
+                 */
+                if (flags == _CACHE_UNCACHED)
+                        base = (u64) IO_BASE;
+                return (void __iomem *) (unsigned long) (base + offset);
+        } else if (__builtin_constant_p(offset) &&
+                   __builtin_constant_p(size) && __builtin_constant_p(flags)) {
+                phys_t phys_addr, last_addr;
+
+                phys_addr = fixup_bigphys_addr(offset, size);
+
+                /* Don't allow wraparound or zero size. */
+                last_addr = phys_addr + size - 1;
+                if (!size || last_addr < phys_addr)
+                        return NULL;
+
+                /*
+                 * Map uncached objects in the low 512MB of address
+                 * space using KSEG1.
+                 */
+                if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
+                    flags == _CACHE_UNCACHED)
+                        return (void __iomem *)
+                                (unsigned long)CKSEG1ADDR(phys_addr);
+        }
+
+        return __ioremap(offset, size, flags);
+
+#undef __IS_LOW512
+}
+
+/*
+ * ioremap     -   map bus memory into CPU space
+ * @offset:    bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * ioremap performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ */
+#define ioremap(offset, size)                                           \
+        __ioremap_mode((offset), (size), _CACHE_UNCACHED)
+
+/*
+ * ioremap_nocache     -   map bus memory into CPU space
+ * @offset:    bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked uncachable
+ * on the CPU as well as honouring existing caching rules from things like
+ * the PCI bus. Note that there are other caches and buffers on many
+ * busses. In paticular driver authors should read up on PCI writes
+ *
+ * It's useful if some control registers are in such an area and
+ * write combining or read caching is not desirable:
+ */
+#define ioremap_nocache(offset, size)                                   \
+        __ioremap_mode((offset), (size), _CACHE_UNCACHED)
+
+/*
+ * ioremap_cachable -   map bus memory into CPU space
+ * @offset:         bus address of the memory
+ * @size:           size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked cachable by
+ * the CPU.  Also enables full write-combining.  Useful for some
+ * memory-like regions on I/O busses.
+ */
+#define ioremap_cachable(offset, size)                                  \
+        __ioremap_mode((offset), (size), _page_cachable_default)
+
+/*
+ * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
+ * requests a cachable mapping, ioremap_uncached_accelerated requests a
+ * mapping using the uncached accelerated mode which isn't supported on
+ * all processors.
+ */
+#define ioremap_cacheable_cow(offset, size)                             \
+        __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
+#define ioremap_uncached_accelerated(offset, size)                      \
+        __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
+
+static inline void iounmap(const volatile void __iomem *addr)
+{
+        if (plat_iounmap(addr))
+                return;
+
+#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
+
+        if (cpu_has_64bit_addresses ||
+            (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
+                return;
+
+        __iounmap(addr);
+
+#undef __IS_KSEG1
+}
+
+#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
+                                                                        \
+static inline void pfx##write##bwlq(type val,                           \
+                                    volatile void __iomem *mem)         \
+{                                                                       \
+        volatile type *__mem;                                           \
+        type __val;                                                     \
+                                                                        \
+        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
+                                                                        \
+        __val = pfx##ioswab##bwlq(__mem, val);                          \
+                                                                        \
+        if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+                *__mem = __val;                                         \
+        else if (cpu_has_64bits) {                                      \
+                unsigned long __flags;                                  \
+                type __tmp;                                             \
+                                                                        \
+                if (irq)                                                \
+                        local_irq_save(__flags);                        \
+                __asm__ __volatile__(                                   \
+                        ".set   mips3"          "\t\t# __writeq""\n\t"  \
+                        "dsll32 %L0, %L0, 0"                    "\n\t"  \
+                        "dsrl32 %L0, %L0, 0"                    "\n\t"  \
+                        "dsll32 %M0, %M0, 0"                    "\n\t"  \
+                        "or     %L0, %L0, %M0"                  "\n\t"  \
+                        "sd     %L0, %2"                        "\n\t"  \
+                        ".set   mips0"                          "\n"    \
+                        : "=r" (__tmp)                                  \
+                        : "0" (__val), "m" (*__mem));                   \
+                if (irq)                                                \
+                        local_irq_restore(__flags);                     \
+        } else                                                          \
+                BUG();                                                  \
+}                                                                       \
+                                                                        \
+static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
+{                                                                       \
+        volatile type *__mem;                                           \
+        type __val;                                                     \
+                                                                        \
+        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
+                                                                        \
+        if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+                __val = *__mem;                                         \
+        else if (cpu_has_64bits) {                                      \
+                unsigned long __flags;                                  \
+                                                                        \
+                if (irq)                                                \
+                        local_irq_save(__flags);                        \
+                __asm__ __volatile__(                                   \
+                        ".set   mips3"          "\t\t# __readq" "\n\t"  \
+                        "ld     %L0, %1"                        "\n\t"  \
+                        "dsra32 %M0, %L0, 0"                    "\n\t"  \
+                        "sll    %L0, %L0, 0"                    "\n\t"  \
+                        ".set   mips0"                          "\n"    \
+                        : "=r" (__val)                                  \
+                        : "m" (*__mem));                                \
+                if (irq)                                                \
+                        local_irq_restore(__flags);                     \
+        } else {                                                        \
+                __val = 0;                                              \
+                BUG();                                                  \
+        }                                                               \
+                                                                        \
+        return pfx##ioswab##bwlq(__mem, __val);                         \
+}
+
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
+                                                                        \
+static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
+{                                                                       \
+        volatile type *__addr;                                          \
+        type __val;                                                     \
+                                                                        \
+        __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+                                                                        \
+        __val = pfx##ioswab##bwlq(__addr, val);                         \
+                                                                        \
+        /* Really, we want this to be atomic */                         \
+        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
+                                                                        \
+        *__addr = __val;                                                \
+        slow;                                                           \
+}                                                                       \
+                                                                        \
+static inline type pfx##in##bwlq##p(unsigned long port)                 \
+{                                                                       \
+        volatile type *__addr;                                          \
+        type __val;                                                     \
+                                                                        \
+        __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+                                                                        \
+        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
+                                                                        \
+        __val = *__addr;                                                \
+        slow;                                                           \
+                                                                        \
+        return pfx##ioswab##bwlq(__addr, __val);                        \
+}
+
+#define __BUILD_MEMORY_PFX(bus, bwlq, type)                             \
+                                                                        \
+__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
+
+#define BUILDIO_MEM(bwlq, type)                                         \
+                                                                        \
+__BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
+__BUILD_MEMORY_PFX(, bwlq, type)                                        \
+__BUILD_MEMORY_PFX(__mem_, bwlq, type)                                  \
+
+BUILDIO_MEM(b, u8)
+BUILDIO_MEM(w, u16)
+BUILDIO_MEM(l, u32)
+BUILDIO_MEM(q, u64)
+
+#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
+
+#define BUILDIO_IOPORT(bwlq, type)                                      \
+        __BUILD_IOPORT_PFX(, bwlq, type)                                \
+        __BUILD_IOPORT_PFX(__mem_, bwlq, type)
+
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+#ifdef CONFIG_64BIT
+BUILDIO_IOPORT(q, u64)
+#endif
+
+#define __BUILDIO(bwlq, type)                                           \
+                                                                        \
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
+
+__BUILDIO(q, u64)
+
+#define readb_relaxed                   readb
+#define readw_relaxed                   readw
+#define readl_relaxed                   readl
+#define readq_relaxed                   readq
+
+/*
+ * Some code tests for these symbols
+ */
+#define readq                           readq
+#define writeq                          writeq
+
+#define __BUILD_MEMORY_STRING(bwlq, type)                               \
+                                                                        \
+static inline void writes##bwlq(volatile void __iomem *mem,             \
+                                const void *addr, unsigned int count)   \
+{                                                                       \
+        const volatile type *__addr = addr;                             \
+                                                                        \
+        while (count--) {                                               \
+                __mem_write##bwlq(*__addr, mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
+                               unsigned int count)                      \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = __mem_read##bwlq(mem);                        \
+                __addr++;                                               \
+        }                                                               \
+}
+
+#define __BUILD_IOPORT_STRING(bwlq, type)                               \
+                                                                        \
+static inline void outs##bwlq(unsigned long port, const void *addr,     \
+                              unsigned int count)                       \
+{                                                                       \
+        const volatile type *__addr = addr;                             \
+                                                                        \
+        while (count--) {                                               \
+                __mem_out##bwlq(*__addr, port);                         \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void ins##bwlq(unsigned long port, void *addr,            \
+                             unsigned int count)                        \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = __mem_in##bwlq(port);                         \
+                __addr++;                                               \
+        }                                                               \
+}
+
+#define BUILDSTRING(bwlq, type)                                         \
+                                                                        \
+__BUILD_MEMORY_STRING(bwlq, type)                                       \
+__BUILD_IOPORT_STRING(bwlq, type)
+
+BUILDSTRING(b, u8)
+BUILDSTRING(w, u16)
+BUILDSTRING(l, u32)
+#ifdef CONFIG_64BIT
+BUILDSTRING(q, u64)
+#endif
+
+
+/* Depends on MIPS II instruction set */
+#define mmiowb() asm volatile ("sync" ::: "memory")
+
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+        memset((void __force *) addr, val, count);
+}
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
+{
+        memcpy(dst, (void __force *) src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
+{
+        memcpy((void __force *) dst, src, count);
+}
+
+/*
+ * The caches on some architectures aren't dma-coherent and have need to
+ * handle this in software.  There are three types of operations that
+ * can be applied to dma buffers.
+ *
+ *  - dma_cache_wback_inv(start, size) makes caches and coherent by
+ *    writing the content of the caches back to memory, if necessary.
+ *    The function also invalidates the affected part of the caches as
+ *    necessary before DMA transfers from outside to memory.
+ *  - dma_cache_wback(start, size) makes caches and coherent by
+ *    writing the content of the caches back to memory, if necessary.
+ *    The function also invalidates the affected part of the caches as
+ *    necessary before DMA transfers from outside to memory.
+ *  - dma_cache_inv(start, size) invalidates the affected parts of the
+ *    caches.  Dirty lines of the caches may be written back or simply
+ *    be discarded.  This operation is necessary before dma operations
+ *    to the memory.
+ *
+ * This API used to be exported; it now is for arch code internal use only.
+ */
+#ifdef CONFIG_DMA_NONCOHERENT
+
+extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
+extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+
+#define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start, size)
+#define dma_cache_wback(start, size)            _dma_cache_wback(start, size)
+#define dma_cache_inv(start, size)              _dma_cache_inv(start, size)
+
+#else /* Sane hardware */
+
+#define dma_cache_wback_inv(start,size) \
+        do { (void) (start); (void) (size); } while (0)
+#define dma_cache_wback(start,size)     \
+        do { (void) (start); (void) (size); } while (0)
+#define dma_cache_inv(start,size)       \
+        do { (void) (start); (void) (size); } while (0)
+
+#endif /* CONFIG_DMA_NONCOHERENT */
+
+/*
+ * Read a 32-bit register that requires a 64-bit read cycle on the bus.
+ * Avoid interrupt mucking, just adjust the address for 4-byte access.
+ * Assume the addresses are 8-byte aligned.
+ */
+#ifdef __MIPSEB__
+#define __CSR_32_ADJUST 4
+#else
+#define __CSR_32_ADJUST 0
+#endif
+
+#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif /* _ASM_IO_H */
diff --git a/arch/mips/include/asm/ioctl.h b/arch/mips/include/asm/ioctl.h
new file mode 100644
index 000000000000..85067e248a83
--- /dev/null
+++ b/arch/mips/include/asm/ioctl.h
@@ -0,0 +1,94 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle
+ */
+#ifndef _ASM_IOCTL_H
+#define _ASM_IOCTL_H
+
+/*
+ * The original linux ioctl numbering scheme was just a general
+ * "anything goes" setup, where more or less random numbers were
+ * assigned.  Sorry, I was clueless when I started out on this.
+ *
+ * On the alpha, we'll try to clean it up a bit, using a more sane
+ * ioctl numbering, and also trying to be compatible with OSF/1 in
+ * the process. I'd like to clean it up for the i386 as well, but
+ * it's so painful recognizing both the new and the old numbers..
+ *
+ * The same applies for for the MIPS ABI; in fact even the macros
+ * from Linux/Alpha fit almost perfectly.
+ */
+
+#define _IOC_NRBITS     8
+#define _IOC_TYPEBITS   8
+#define _IOC_SIZEBITS   13
+#define _IOC_DIRBITS    3
+
+#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
+#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT    0
+#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
+#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
+#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
+
+/*
+ * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
+ * And this turns out useful to catch old ioctl numbers in header
+ * files for us.
+ */
+#define _IOC_NONE       1U
+#define _IOC_READ       2U
+#define _IOC_WRITE      4U
+
+/*
+ * The following are included for compatibility
+ */
+#define _IOC_VOID       0x20000000
+#define _IOC_OUT        0x40000000
+#define _IOC_IN         0x80000000
+#define _IOC_INOUT      (IOC_IN|IOC_OUT)
+
+#define _IOC(dir, type, nr, size) \
+        (((dir)  << _IOC_DIRSHIFT) | \
+         ((type) << _IOC_TYPESHIFT) | \
+         ((nr)   << _IOC_NRSHIFT) | \
+         ((size) << _IOC_SIZESHIFT))
+
+/* provoke compile error for invalid uses of size argument */
+extern unsigned int __invalid_size_argument_for_IOC;
+#define _IOC_TYPECHECK(t) \
+        ((sizeof(t) == sizeof(t[1]) && \
+          sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
+          sizeof(t) : __invalid_size_argument_for_IOC)
+
+/* used to create numbers */
+#define _IO(type, nr)           _IOC(_IOC_NONE, (type), (nr), 0)
+#define _IOR(type, nr, size)    _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
+#define _IOW(type, nr, size)    _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
+#define _IOWR(type, nr, size)   _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
+#define _IOR_BAD(type, nr, size)        _IOC(_IOC_READ, (type), (nr), sizeof(size))
+#define _IOW_BAD(type, nr, size)        _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
+#define _IOWR_BAD(type, nr, size)       _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size))
+
+
+/* used to decode them.. */
+#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+
+/* ...and for the drivers/sound files... */
+
+#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
+
+#endif /* _ASM_IOCTL_H */
diff --git a/arch/mips/include/asm/ioctls.h b/arch/mips/include/asm/ioctls.h
new file mode 100644
index 000000000000..3f04a995ec54
--- /dev/null
+++ b/arch/mips/include/asm/ioctls.h
@@ -0,0 +1,109 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2001 Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_IOCTLS_H
+#define __ASM_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+#define TCGETA          0x5401
+#define TCSETA          0x5402  /* Clashes with SNDCTL_TMR_START sound ioctl */
+#define TCSETAW         0x5403
+#define TCSETAF         0x5404
+
+#define TCSBRK          0x5405
+#define TCXONC          0x5406
+#define TCFLSH          0x5407
+
+#define TCGETS          0x540d
+#define TCSETS          0x540e
+#define TCSETSW         0x540f
+#define TCSETSF         0x5410
+
+#define TIOCEXCL        0x740d          /* set exclusive use of tty */
+#define TIOCNXCL        0x740e          /* reset exclusive use of tty */
+#define TIOCOUTQ        0x7472          /* output queue size */
+#define TIOCSTI         0x5472          /* simulate terminal input */
+#define TIOCMGET        0x741d          /* get all modem bits */
+#define TIOCMBIS        0x741b          /* bis modem bits */
+#define TIOCMBIC        0x741c          /* bic modem bits */
+#define TIOCMSET        0x741a          /* set all modem bits */
+#define TIOCPKT         0x5470          /* pty: set/clear packet mode */
+#define  TIOCPKT_DATA           0x00    /* data packet */
+#define  TIOCPKT_FLUSHREAD      0x01    /* flush packet */
+#define  TIOCPKT_FLUSHWRITE     0x02    /* flush packet */
+#define  TIOCPKT_STOP           0x04    /* stop output */
+#define  TIOCPKT_START          0x08    /* start output */
+#define  TIOCPKT_NOSTOP         0x10    /* no more ^S, ^Q */
+#define  TIOCPKT_DOSTOP         0x20    /* now do ^S ^Q */
+/* #define  TIOCPKT_IOCTL               0x40    state change of pty driver */
+#define TIOCSWINSZ      _IOW('t', 103, struct winsize)  /* set window size */
+#define TIOCGWINSZ      _IOR('t', 104, struct winsize)  /* get window size */
+#define TIOCNOTTY       0x5471          /* void tty association */
+#define TIOCSETD        0x7401
+#define TIOCGETD        0x7400
+
+#define FIOCLEX         0x6601
+#define FIONCLEX        0x6602
+#define FIOASYNC        0x667d
+#define FIONBIO         0x667e
+#define FIOQSIZE        0x667f
+
+#define TIOCGLTC        0x7474                  /* get special local chars */
+#define TIOCSLTC        0x7475                  /* set special local chars */
+#define TIOCSPGRP       _IOW('t', 118, int)     /* set pgrp of tty */
+#define TIOCGPGRP       _IOR('t', 119, int)     /* get pgrp of tty */
+#define TIOCCONS        _IOW('t', 120, int)     /* become virtual console */
+
+#define FIONREAD        0x467f
+#define TIOCINQ         FIONREAD
+
+#define TIOCGETP        0x7408
+#define TIOCSETP        0x7409
+#define TIOCSETN        0x740a                  /* TIOCSETP wo flush */
+
+/* #define TIOCSETA     _IOW('t', 20, struct termios) set termios struct */
+/* #define TIOCSETAW    _IOW('t', 21, struct termios) drain output, set */
+/* #define TIOCSETAF    _IOW('t', 22, struct termios) drn out, fls in, set */
+/* #define TIOCGETD     _IOR('t', 26, int)      get line discipline */
+/* #define TIOCSETD     _IOW('t', 27, int)      set line discipline */
+                                                /* 127-124 compat */
+
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x7416  /* Return the session ID of FD */
+#define TCGETS2         _IOR('T', 0x2A, struct termios2)
+#define TCSETS2         _IOW('T', 0x2B, struct termios2)
+#define TCSETSW2        _IOW('T', 0x2C, struct termios2)
+#define TCSETSF2        _IOW('T', 0x2D, struct termios2)
+#define TIOCGPTN        _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T', 0x31, int)  /* Lock/unlock Pty */
+
+/* I hope the range from 0x5480 on is free ... */
+#define TIOCSCTTY       0x5480          /* become controlling tty */
+#define TIOCGSOFTCAR    0x5481
+#define TIOCSSOFTCAR    0x5482
+#define TIOCLINUX       0x5483
+#define TIOCGSERIAL     0x5484
+#define TIOCSSERIAL     0x5485
+#define TCSBRKP         0x5486  /* Needed for POSIX tcsendbreak() */
+#define TIOCSERCONFIG   0x5488
+#define TIOCSERGWILD    0x5489
+#define TIOCSERSWILD    0x548a
+#define TIOCGLCKTRMIOS  0x548b
+#define TIOCSLCKTRMIOS  0x548c
+#define TIOCSERGSTRUCT  0x548d /* For debugging only */
+#define TIOCSERGETLSR   0x548e /* Get line status register */
+#define TIOCSERGETMULTI 0x548f /* Get multiport config  */
+#define TIOCSERSETMULTI 0x5490 /* Set multiport config */
+#define TIOCMIWAIT      0x5491 /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x5492 /* read serial port inline interrupt counts */
+#define TIOCGHAYESESP   0x5493 /* Get Hayes ESP configuration */
+#define TIOCSHAYESESP   0x5494 /* Set Hayes ESP configuration */
+
+#endif /* __ASM_IOCTLS_H */
diff --git a/arch/mips/include/asm/ip32/crime.h b/arch/mips/include/asm/ip32/crime.h
new file mode 100644
index 000000000000..7c36b0e5b1c6
--- /dev/null
+++ b/arch/mips/include/asm/ip32/crime.h
@@ -0,0 +1,158 @@
+/*
+ * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory
+ * Engine)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Harald Koerfgen
+ */
+
+#ifndef __ASM_CRIME_H__
+#define __ASM_CRIME_H__
+
+/*
+ * Address map
+ */
+#define CRIME_BASE      0x14000000      /* physical */
+
+struct sgi_crime {
+        volatile unsigned long id;
+#define CRIME_ID_MASK                   0xff
+#define CRIME_ID_IDBITS                 0xf0
+#define CRIME_ID_IDVALUE                0xa0
+#define CRIME_ID_REV                    0x0f
+#define CRIME_REV_PETTY                 0x00
+#define CRIME_REV_11                    0x11
+#define CRIME_REV_13                    0x13
+#define CRIME_REV_14                    0x14
+
+        volatile unsigned long control;
+#define CRIME_CONTROL_MASK              0x3fff
+#define CRIME_CONTROL_TRITON_SYSADC     0x2000
+#define CRIME_CONTROL_CRIME_SYSADC      0x1000
+#define CRIME_CONTROL_HARD_RESET        0x0800
+#define CRIME_CONTROL_SOFT_RESET        0x0400
+#define CRIME_CONTROL_DOG_ENA           0x0200
+#define CRIME_CONTROL_ENDIANESS         0x0100
+#define CRIME_CONTROL_ENDIAN_BIG        0x0100
+#define CRIME_CONTROL_ENDIAN_LITTLE     0x0000
+#define CRIME_CONTROL_CQUEUE_HWM        0x000f
+#define CRIME_CONTROL_CQUEUE_SHFT       0
+#define CRIME_CONTROL_WBUF_HWM          0x00f0
+#define CRIME_CONTROL_WBUF_SHFT         8
+
+        volatile unsigned long istat;
+        volatile unsigned long imask;
+        volatile unsigned long soft_int;
+        volatile unsigned long hard_int;
+#define MACE_VID_IN1_INT                BIT(0)
+#define MACE_VID_IN2_INT                BIT(1)
+#define MACE_VID_OUT_INT                BIT(2)
+#define MACE_ETHERNET_INT               BIT(3)
+#define MACE_SUPERIO_INT                BIT(4)
+#define MACE_MISC_INT                   BIT(5)
+#define MACE_AUDIO_INT                  BIT(6)
+#define MACE_PCI_BRIDGE_INT             BIT(7)
+#define MACEPCI_SCSI0_INT               BIT(8)
+#define MACEPCI_SCSI1_INT               BIT(9)
+#define MACEPCI_SLOT0_INT               BIT(10)
+#define MACEPCI_SLOT1_INT               BIT(11)
+#define MACEPCI_SLOT2_INT               BIT(12)
+#define MACEPCI_SHARED0_INT             BIT(13)
+#define MACEPCI_SHARED1_INT             BIT(14)
+#define MACEPCI_SHARED2_INT             BIT(15)
+#define CRIME_GBE0_INT                  BIT(16)
+#define CRIME_GBE1_INT                  BIT(17)
+#define CRIME_GBE2_INT                  BIT(18)
+#define CRIME_GBE3_INT                  BIT(19)
+#define CRIME_CPUERR_INT                BIT(20)
+#define CRIME_MEMERR_INT                BIT(21)
+#define CRIME_RE_EMPTY_E_INT            BIT(22)
+#define CRIME_RE_FULL_E_INT             BIT(23)
+#define CRIME_RE_IDLE_E_INT             BIT(24)
+#define CRIME_RE_EMPTY_L_INT            BIT(25)
+#define CRIME_RE_FULL_L_INT             BIT(26)
+#define CRIME_RE_IDLE_L_INT             BIT(27)
+#define CRIME_SOFT0_INT                 BIT(28)
+#define CRIME_SOFT1_INT                 BIT(29)
+#define CRIME_SOFT2_INT                 BIT(30)
+#define CRIME_SYSCORERR_INT             CRIME_SOFT2_INT
+#define CRIME_VICE_INT                  BIT(31)
+/* Masks for deciding who handles the interrupt */
+#define CRIME_MACE_INT_MASK             0x8f
+#define CRIME_MACEISA_INT_MASK          0x70
+#define CRIME_MACEPCI_INT_MASK          0xff00
+#define CRIME_CRIME_INT_MASK            0xffff0000
+
+        volatile unsigned long watchdog;
+#define CRIME_DOG_POWER_ON_RESET        0x00010000
+#define CRIME_DOG_WARM_RESET            0x00080000
+#define CRIME_DOG_TIMEOUT               (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
+#define CRIME_DOG_VALUE                 0x00007fff
+
+        volatile unsigned long timer;
+#define CRIME_MASTER_FREQ               66666500        /* Crime upcounter frequency */
+#define CRIME_NS_PER_TICK               15              /* for delay_calibrate */
+
+        volatile unsigned long cpu_error_addr;
+#define CRIME_CPU_ERROR_ADDR_MASK       0x3ffffffff
+
+        volatile unsigned long cpu_error_stat;
+#define CRIME_CPU_ERROR_MASK            0x7             /* cpu error stat is 3 bits */
+#define CRIME_CPU_ERROR_CPU_ILL_ADDR    0x4
+#define CRIME_CPU_ERROR_VICE_WRT_PRTY   0x2
+#define CRIME_CPU_ERROR_CPU_WRT_PRTY    0x1
+
+        unsigned long _pad0[54];
+
+        volatile unsigned long mc_ctrl;
+        volatile unsigned long bank_ctrl[8];
+#define CRIME_MEM_BANK_CONTROL_MASK             0x11f   /* 9 bits 7:5 reserved */
+#define CRIME_MEM_BANK_CONTROL_ADDR             0x01f
+#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE       0x100
+#define CRIME_MAXBANKS                          8
+
+        volatile unsigned long mem_ref_counter;
+#define CRIME_MEM_REF_COUNTER_MASK      0x3ff           /* 10bit */
+
+        volatile unsigned long mem_error_stat;
+#define CRIME_MEM_ERROR_STAT_MASK       0x0ff7ffff      /* 28-bit register */
+#define CRIME_MEM_ERROR_MACE_ID         0x0000007f
+#define CRIME_MEM_ERROR_MACE_ACCESS     0x00000080
+#define CRIME_MEM_ERROR_RE_ID           0x00007f00
+#define CRIME_MEM_ERROR_RE_ACCESS       0x00008000
+#define CRIME_MEM_ERROR_GBE_ACCESS      0x00010000
+#define CRIME_MEM_ERROR_VICE_ACCESS     0x00020000
+#define CRIME_MEM_ERROR_CPU_ACCESS      0x00040000
+#define CRIME_MEM_ERROR_RESERVED        0x00080000
+#define CRIME_MEM_ERROR_SOFT_ERR        0x00100000
+#define CRIME_MEM_ERROR_HARD_ERR        0x00200000
+#define CRIME_MEM_ERROR_MULTIPLE        0x00400000
+#define CRIME_MEM_ERROR_ECC             0x01800000
+#define CRIME_MEM_ERROR_MEM_ECC_RD      0x00800000
+#define CRIME_MEM_ERROR_MEM_ECC_RMW     0x01000000
+#define CRIME_MEM_ERROR_INV             0x0e000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
+
+        volatile unsigned long mem_error_addr;
+#define CRIME_MEM_ERROR_ADDR_MASK       0x3fffffff
+
+        volatile unsigned long mem_ecc_syn;
+#define CRIME_MEM_ERROR_ECC_SYN_MASK    0xffffffff
+
+        volatile unsigned long mem_ecc_chk;
+#define CRIME_MEM_ERROR_ECC_CHK_MASK    0xffffffff
+
+        volatile unsigned long mem_ecc_repl;
+#define CRIME_MEM_ERROR_ECC_REPL_MASK   0xffffffff
+};
+
+extern struct sgi_crime __iomem *crime;
+
+#define CRIME_HI_MEM_BASE       0x40000000      /* this is where whole 1G of RAM is mapped */
+
+#endif /* __ASM_CRIME_H__ */
diff --git a/arch/mips/include/asm/ip32/ip32_ints.h b/arch/mips/include/asm/ip32/ip32_ints.h
new file mode 100644
index 000000000000..85bc5302bce0
--- /dev/null
+++ b/arch/mips/include/asm/ip32/ip32_ints.h
@@ -0,0 +1,114 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Harald Koerfgen
+ */
+
+#ifndef __ASM_IP32_INTS_H
+#define __ASM_IP32_INTS_H
+
+#include <asm/irq.h>
+
+/*
+ * This list reflects the assignment of interrupt numbers to
+ * interrupting events.  Order is fairly irrelevant to handling
+ * priority.  This differs from irix.
+ */
+
+enum ip32_irq_no {
+        /*
+         * CPU interrupts are 0 ... 7
+         */
+
+        CRIME_IRQ_BASE                  = MIPS_CPU_IRQ_BASE + 8,
+
+        /*
+         * MACE
+         */
+        MACE_VID_IN1_IRQ                = CRIME_IRQ_BASE,
+        MACE_VID_IN2_IRQ,
+        MACE_VID_OUT_IRQ,
+        MACE_ETHERNET_IRQ,
+        /* SUPERIO, MISC, and AUDIO are MACEISA */
+        __MACE_SUPERIO,
+        __MACE_MISC,
+        __MACE_AUDIO,
+        MACE_PCI_BRIDGE_IRQ,
+
+        /*
+         * MACEPCI
+         */
+        MACEPCI_SCSI0_IRQ,
+        MACEPCI_SCSI1_IRQ,
+        MACEPCI_SLOT0_IRQ,
+        MACEPCI_SLOT1_IRQ,
+        MACEPCI_SLOT2_IRQ,
+        MACEPCI_SHARED0_IRQ,
+        MACEPCI_SHARED1_IRQ,
+        MACEPCI_SHARED2_IRQ,
+
+        /*
+         * CRIME
+         */
+        CRIME_GBE0_IRQ,
+        CRIME_GBE1_IRQ,
+        CRIME_GBE2_IRQ,
+        CRIME_GBE3_IRQ,
+        CRIME_CPUERR_IRQ,
+        CRIME_MEMERR_IRQ,
+        CRIME_RE_EMPTY_E_IRQ,
+        CRIME_RE_FULL_E_IRQ,
+        CRIME_RE_IDLE_E_IRQ,
+        CRIME_RE_EMPTY_L_IRQ,
+        CRIME_RE_FULL_L_IRQ,
+        CRIME_RE_IDLE_L_IRQ,
+        CRIME_SOFT0_IRQ,
+        CRIME_SOFT1_IRQ,
+        CRIME_SOFT2_IRQ,
+        CRIME_SYSCORERR_IRQ             = CRIME_SOFT2_IRQ,
+        CRIME_VICE_IRQ,
+
+        /*
+         * MACEISA
+         */
+        MACEISA_AUDIO_SW_IRQ,
+        MACEISA_AUDIO_SC_IRQ,
+        MACEISA_AUDIO1_DMAT_IRQ,
+        MACEISA_AUDIO1_OF_IRQ,
+        MACEISA_AUDIO2_DMAT_IRQ,
+        MACEISA_AUDIO2_MERR_IRQ,
+        MACEISA_AUDIO3_DMAT_IRQ,
+        MACEISA_AUDIO3_MERR_IRQ,
+        MACEISA_RTC_IRQ,
+        MACEISA_KEYB_IRQ,
+        /* MACEISA_KEYB_POLL is not an IRQ */
+        __MACEISA_KEYB_POLL,
+        MACEISA_MOUSE_IRQ,
+        /* MACEISA_MOUSE_POLL is not an IRQ */
+        __MACEISA_MOUSE_POLL,
+        MACEISA_TIMER0_IRQ,
+        MACEISA_TIMER1_IRQ,
+        MACEISA_TIMER2_IRQ,
+        MACEISA_PARALLEL_IRQ,
+        MACEISA_PAR_CTXA_IRQ,
+        MACEISA_PAR_CTXB_IRQ,
+        MACEISA_PAR_MERR_IRQ,
+        MACEISA_SERIAL1_IRQ,
+        MACEISA_SERIAL1_TDMAT_IRQ,
+        MACEISA_SERIAL1_TDMAPR_IRQ,
+        MACEISA_SERIAL1_TDMAME_IRQ,
+        MACEISA_SERIAL1_RDMAT_IRQ,
+        MACEISA_SERIAL1_RDMAOR_IRQ,
+        MACEISA_SERIAL2_IRQ,
+        MACEISA_SERIAL2_TDMAT_IRQ,
+        MACEISA_SERIAL2_TDMAPR_IRQ,
+        MACEISA_SERIAL2_TDMAME_IRQ,
+        MACEISA_SERIAL2_RDMAT_IRQ,
+        MACEISA_SERIAL2_RDMAOR_IRQ,
+
+        IP32_IRQ_MAX                    = MACEISA_SERIAL2_RDMAOR_IRQ
+};
+
+#endif /* __ASM_IP32_INTS_H */
diff --git a/arch/mips/include/asm/ip32/mace.h b/arch/mips/include/asm/ip32/mace.h
new file mode 100644
index 000000000000..d08d7c672139
--- /dev/null
+++ b/arch/mips/include/asm/ip32/mace.h
@@ -0,0 +1,365 @@
+/*
+ * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Harald Koerfgen
+ * Copyright (C) 2004 Ladislav Michl
+ */
+
+#ifndef __ASM_MACE_H__
+#define __ASM_MACE_H__
+
+/*
+ * Address map
+ */
+#define MACE_BASE       0x1f000000      /* physical */
+
+/*
+ * PCI interface
+ */
+struct mace_pci {
+        volatile unsigned int error_addr;
+        volatile unsigned int error;
+#define MACEPCI_ERROR_MASTER_ABORT              BIT(31)
+#define MACEPCI_ERROR_TARGET_ABORT              BIT(30)
+#define MACEPCI_ERROR_DATA_PARITY_ERR           BIT(29)
+#define MACEPCI_ERROR_RETRY_ERR                 BIT(28)
+#define MACEPCI_ERROR_ILLEGAL_CMD               BIT(27)
+#define MACEPCI_ERROR_SYSTEM_ERR                BIT(26)
+#define MACEPCI_ERROR_INTERRUPT_TEST            BIT(25)
+#define MACEPCI_ERROR_PARITY_ERR                BIT(24)
+#define MACEPCI_ERROR_OVERRUN                   BIT(23)
+#define MACEPCI_ERROR_RSVD                      BIT(22)
+#define MACEPCI_ERROR_MEMORY_ADDR               BIT(21)
+#define MACEPCI_ERROR_CONFIG_ADDR               BIT(20)
+#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID   BIT(19)
+#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID   BIT(18)
+#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID    BIT(17)
+#define MACEPCI_ERROR_RETRY_ADDR_VALID          BIT(16)
+#define MACEPCI_ERROR_SIG_TABORT                BIT(4)
+#define MACEPCI_ERROR_DEVSEL_MASK               0xc0
+#define MACEPCI_ERROR_DEVSEL_FAST               0
+#define MACEPCI_ERROR_DEVSEL_MED                0x40
+#define MACEPCI_ERROR_DEVSEL_SLOW               0x80
+#define MACEPCI_ERROR_FBB                       BIT(1)
+#define MACEPCI_ERROR_66MHZ                     BIT(0)
+        volatile unsigned int control;
+#define MACEPCI_CONTROL_INT(x)                  BIT(x)
+#define MACEPCI_CONTROL_INT_MASK                0xff
+#define MACEPCI_CONTROL_SERR_ENA                BIT(8)
+#define MACEPCI_CONTROL_ARB_N6                  BIT(9)
+#define MACEPCI_CONTROL_PARITY_ERR              BIT(10)
+#define MACEPCI_CONTROL_MRMRA_ENA               BIT(11)
+#define MACEPCI_CONTROL_ARB_N3                  BIT(12)
+#define MACEPCI_CONTROL_ARB_N4                  BIT(13)
+#define MACEPCI_CONTROL_ARB_N5                  BIT(14)
+#define MACEPCI_CONTROL_PARK_LIU                BIT(15)
+#define MACEPCI_CONTROL_INV_INT(x)              BIT(16+x)
+#define MACEPCI_CONTROL_INV_INT_MASK            0x00ff0000
+#define MACEPCI_CONTROL_OVERRUN_INT             BIT(24)
+#define MACEPCI_CONTROL_PARITY_INT              BIT(25)
+#define MACEPCI_CONTROL_SERR_INT                BIT(26)
+#define MACEPCI_CONTROL_IT_INT                  BIT(27)
+#define MACEPCI_CONTROL_RE_INT                  BIT(28)
+#define MACEPCI_CONTROL_DPED_INT                BIT(29)
+#define MACEPCI_CONTROL_TAR_INT                 BIT(30)
+#define MACEPCI_CONTROL_MAR_INT                 BIT(31)
+        volatile unsigned int rev;
+        unsigned int _pad[0xcf8/4 - 4];
+        volatile unsigned int config_addr;
+        union {
+                volatile unsigned char b[4];
+                volatile unsigned short w[2];
+                volatile unsigned int l;
+        } config_data;
+};
+#define MACEPCI_LOW_MEMORY              0x1a000000
+#define MACEPCI_LOW_IO                  0x18000000
+#define MACEPCI_SWAPPED_VIEW            0
+#define MACEPCI_NATIVE_VIEW             0x40000000
+#define MACEPCI_IO                      0x80000000
+#define MACEPCI_HI_MEMORY               0x280000000
+#define MACEPCI_HI_IO                   0x100000000
+
+/*
+ * Video interface
+ */
+struct mace_video {
+        unsigned long xxx;      /* later... */
+};
+
+/*
+ * Ethernet interface
+ */
+struct mace_ethernet {
+        volatile unsigned long mac_ctrl;
+        volatile unsigned long int_stat;
+        volatile unsigned long dma_ctrl;
+        volatile unsigned long timer;
+        volatile unsigned long tx_int_al;
+        volatile unsigned long rx_int_al;
+        volatile unsigned long tx_info;
+        volatile unsigned long tx_info_al;
+        volatile unsigned long rx_buff;
+        volatile unsigned long rx_buff_al1;
+        volatile unsigned long rx_buff_al2;
+        volatile unsigned long diag;
+        volatile unsigned long phy_data;
+        volatile unsigned long phy_regs;
+        volatile unsigned long phy_trans_go;
+        volatile unsigned long backoff_seed;
+        /*===================================*/
+        volatile unsigned long imq_reserved[4];
+        volatile unsigned long mac_addr;
+        volatile unsigned long mac_addr2;
+        volatile unsigned long mcast_filter;
+        volatile unsigned long tx_ring_base;
+        /* Following are read-only registers for debugging */
+        volatile unsigned long tx_pkt1_hdr;
+        volatile unsigned long tx_pkt1_ptr[3];
+        volatile unsigned long tx_pkt2_hdr;
+        volatile unsigned long tx_pkt2_ptr[3];
+        /*===================================*/
+        volatile unsigned long rx_fifo;
+};
+
+/*
+ * Peripherals
+ */
+
+/* Audio registers */
+struct mace_audio {
+        volatile unsigned long control;
+        volatile unsigned long codec_control;           /* codec status control */
+        volatile unsigned long codec_mask;              /* codec status input mask */
+        volatile unsigned long codec_read;              /* codec status read data */
+        struct {
+                volatile unsigned long control;         /* channel control */
+                volatile unsigned long read_ptr;        /* channel read pointer */
+                volatile unsigned long write_ptr;       /* channel write pointer */
+                volatile unsigned long depth;           /* channel depth */
+        } chan[3];
+};
+
+
+/* register definitions for parallel port DMA */
+struct mace_parport {
+        /* 0 - do nothing,
+         * 1 - pulse terminal count to the device after buffer is drained */
+#define MACEPAR_CONTEXT_LASTFLAG        BIT(63)
+        /* Should not cross 4K page boundary */
+#define MACEPAR_CONTEXT_DATA_BOUND      0x0000000000001000UL
+#define MACEPAR_CONTEXT_DATALEN_MASK    0x00000fff00000000UL
+#define MACEPAR_CONTEXT_DATALEN_SHIFT   32
+        /* Can be arbitrarily aligned on any byte boundary on output,
+         * 64 byte aligned on input */
+#define MACEPAR_CONTEXT_BASEADDR_MASK   0x00000000ffffffffUL
+        volatile u64 context_a;
+        volatile u64 context_b;
+        /* 0 - mem->device, 1 - device->mem */
+#define MACEPAR_CTLSTAT_DIRECTION       BIT(0)
+        /* 0 - channel frozen, 1 - channel enabled */
+#define MACEPAR_CTLSTAT_ENABLE          BIT(1)
+        /* 0 - channel active, 1 - complete channel reset */
+#define MACEPAR_CTLSTAT_RESET           BIT(2)
+#define MACEPAR_CTLSTAT_CTXB_VALID      BIT(3)
+#define MACEPAR_CTLSTAT_CTXA_VALID      BIT(4)
+        volatile u64 cntlstat;          /* Control/Status register */
+#define MACEPAR_DIAG_CTXINUSE           BIT(0)
+        /* 1 - Dma engine is enabled and processing something */
+#define MACEPAR_DIAG_DMACTIVE           BIT(1)
+        /* Counter of bytes left */
+#define MACEPAR_DIAG_CTRMASK            0x0000000000003ffcUL
+#define MACEPAR_DIAG_CTRSHIFT           2
+        volatile u64 diagnostic;        /* RO: diagnostic register */
+};
+
+/* ISA Control and DMA registers */
+struct mace_isactrl {
+        volatile unsigned long ringbase;
+#define MACEISA_RINGBUFFERS_SIZE        (8 * 4096)
+
+        volatile unsigned long misc;
+#define MACEISA_FLASH_WE                BIT(0)  /* 1=> Enable FLASH writes */
+#define MACEISA_PWD_CLEAR               BIT(1)  /* 1=> PWD CLEAR jumper detected */
+#define MACEISA_NIC_DEASSERT            BIT(2)
+#define MACEISA_NIC_DATA                BIT(3)
+#define MACEISA_LED_RED                 BIT(4)  /* 0=> Illuminate red LED */
+#define MACEISA_LED_GREEN               BIT(5)  /* 0=> Illuminate green LED */
+#define MACEISA_DP_RAM_ENABLE           BIT(6)
+
+        volatile unsigned long istat;
+        volatile unsigned long imask;
+#define MACEISA_AUDIO_SW_INT            BIT(0)
+#define MACEISA_AUDIO_SC_INT            BIT(1)
+#define MACEISA_AUDIO1_DMAT_INT         BIT(2)
+#define MACEISA_AUDIO1_OF_INT           BIT(3)
+#define MACEISA_AUDIO2_DMAT_INT         BIT(4)
+#define MACEISA_AUDIO2_MERR_INT         BIT(5)
+#define MACEISA_AUDIO3_DMAT_INT         BIT(6)
+#define MACEISA_AUDIO3_MERR_INT         BIT(7)
+#define MACEISA_RTC_INT                 BIT(8)
+#define MACEISA_KEYB_INT                BIT(9)
+#define MACEISA_KEYB_POLL_INT           BIT(10)
+#define MACEISA_MOUSE_INT               BIT(11)
+#define MACEISA_MOUSE_POLL_INT          BIT(12)
+#define MACEISA_TIMER0_INT              BIT(13)
+#define MACEISA_TIMER1_INT              BIT(14)
+#define MACEISA_TIMER2_INT              BIT(15)
+#define MACEISA_PARALLEL_INT            BIT(16)
+#define MACEISA_PAR_CTXA_INT            BIT(17)
+#define MACEISA_PAR_CTXB_INT            BIT(18)
+#define MACEISA_PAR_MERR_INT            BIT(19)
+#define MACEISA_SERIAL1_INT             BIT(20)
+#define MACEISA_SERIAL1_TDMAT_INT       BIT(21)
+#define MACEISA_SERIAL1_TDMAPR_INT      BIT(22)
+#define MACEISA_SERIAL1_TDMAME_INT      BIT(23)
+#define MACEISA_SERIAL1_RDMAT_INT       BIT(24)
+#define MACEISA_SERIAL1_RDMAOR_INT      BIT(25)
+#define MACEISA_SERIAL2_INT             BIT(26)
+#define MACEISA_SERIAL2_TDMAT_INT       BIT(27)
+#define MACEISA_SERIAL2_TDMAPR_INT      BIT(28)
+#define MACEISA_SERIAL2_TDMAME_INT      BIT(29)
+#define MACEISA_SERIAL2_RDMAT_INT       BIT(30)
+#define MACEISA_SERIAL2_RDMAOR_INT      BIT(31)
+
+        volatile unsigned long _pad[0x2000/8 - 4];
+
+        volatile unsigned long dp_ram[0x400];
+        struct mace_parport parport;
+};
+
+/* Keyboard & Mouse registers
+ * -> drivers/input/serio/maceps2.c */
+struct mace_ps2port {
+        volatile unsigned long tx;
+        volatile unsigned long rx;
+        volatile unsigned long control;
+        volatile unsigned long status;
+};
+
+struct mace_ps2 {
+        struct mace_ps2port keyb;
+        struct mace_ps2port mouse;
+};
+
+/* I2C registers
+ * -> drivers/i2c/algos/i2c-algo-sgi.c */
+struct mace_i2c {
+        volatile unsigned long config;
+#define MACEI2C_RESET           BIT(0)
+#define MACEI2C_FAST            BIT(1)
+#define MACEI2C_DATA_OVERRIDE   BIT(2)
+#define MACEI2C_CLOCK_OVERRIDE  BIT(3)
+#define MACEI2C_DATA_STATUS     BIT(4)
+#define MACEI2C_CLOCK_STATUS    BIT(5)
+        volatile unsigned long control;
+        volatile unsigned long data;
+};
+
+/* Timer registers */
+typedef union {
+        volatile unsigned long ust_msc;
+        struct reg {
+                volatile unsigned int ust;
+                volatile unsigned int msc;
+        } reg;
+} timer_reg;
+
+struct mace_timers {
+        volatile unsigned long ust;
+#define MACE_UST_PERIOD_NS      960
+
+        volatile unsigned long compare1;
+        volatile unsigned long compare2;
+        volatile unsigned long compare3;
+
+        timer_reg audio_in;
+        timer_reg audio_out1;
+        timer_reg audio_out2;
+        timer_reg video_in1;
+        timer_reg video_in2;
+        timer_reg video_out;
+};
+
+struct mace_perif {
+        struct mace_audio audio;
+        char _pad0[0x10000 - sizeof(struct mace_audio)];
+
+        struct mace_isactrl ctrl;
+        char _pad1[0x10000 - sizeof(struct mace_isactrl)];
+
+        struct mace_ps2 ps2;
+        char _pad2[0x10000 - sizeof(struct mace_ps2)];
+
+        struct mace_i2c i2c;
+        char _pad3[0x10000 - sizeof(struct mace_i2c)];
+
+        struct mace_timers timers;
+        char _pad4[0x10000 - sizeof(struct mace_timers)];
+};
+
+
+/*
+ * ISA peripherals
+ */
+
+/* Parallel port */
+struct mace_parallel {
+};
+
+struct mace_ecp1284 {   /* later... */
+};
+
+/* Serial port */
+struct mace_serial {
+        volatile unsigned long xxx;     /* later... */
+};
+
+struct mace_isa {
+        struct mace_parallel parallel;
+        char _pad1[0x8000 - sizeof(struct mace_parallel)];
+
+        struct mace_ecp1284 ecp1284;
+        char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
+
+        struct mace_serial serial1;
+        char _pad3[0x8000 - sizeof(struct mace_serial)];
+
+        struct mace_serial serial2;
+        char _pad4[0x8000 - sizeof(struct mace_serial)];
+
+        volatile unsigned char rtc[0x10000];
+};
+
+struct sgi_mace {
+        char _reserved[0x80000];
+
+        struct mace_pci pci;
+        char _pad0[0x80000 - sizeof(struct mace_pci)];
+
+        struct mace_video video_in1;
+        char _pad1[0x80000 - sizeof(struct mace_video)];
+
+        struct mace_video video_in2;
+        char _pad2[0x80000 - sizeof(struct mace_video)];
+
+        struct mace_video video_out;
+        char _pad3[0x80000 - sizeof(struct mace_video)];
+
+        struct mace_ethernet eth;
+        char _pad4[0x80000 - sizeof(struct mace_ethernet)];
+
+        struct mace_perif perif;
+        char _pad5[0x80000 - sizeof(struct mace_perif)];
+
+        struct mace_isa isa;
+        char _pad6[0x80000 - sizeof(struct mace_isa)];
+};
+
+extern struct sgi_mace __iomem *mace;
+
+#endif /* __ASM_MACE_H__ */
diff --git a/arch/mips/include/asm/ipcbuf.h b/arch/mips/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..d47d08f264e7
--- /dev/null
+++ b/arch/mips/include/asm/ipcbuf.h
@@ -0,0 +1,28 @@
+#ifndef _ASM_IPCBUF_H
+#define _ASM_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for alpha architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit seq
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t  key;
+        __kernel_uid_t  uid;
+        __kernel_gid_t  gid;
+        __kernel_uid_t  cuid;
+        __kernel_gid_t  cgid;
+        __kernel_mode_t mode;
+        unsigned short  seq;
+        unsigned short  __pad1;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+
+#endif /* _ASM_IPCBUF_H */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
new file mode 100644
index 000000000000..a58f0eecc68f
--- /dev/null
+++ b/arch/mips/include/asm/irq.h
@@ -0,0 +1,163 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
+ */
+#ifndef _ASM_IRQ_H
+#define _ASM_IRQ_H
+
+#include <linux/linkage.h>
+
+#include <asm/mipsmtregs.h>
+
+#include <irq.h>
+
+#ifdef CONFIG_I8259
+static inline int irq_canonicalize(int irq)
+{
+        return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
+}
+#else
+#define irq_canonicalize(irq) (irq)     /* Sane hardware, sane code ... */
+#endif
+
+#ifdef CONFIG_MIPS_MT_SMTC
+
+struct irqaction;
+
+extern unsigned long irq_hwmask[];
+extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
+                          unsigned long hwmask);
+
+static inline void smtc_im_ack_irq(unsigned int irq)
+{
+        if (irq_hwmask[irq] & ST0_IM)
+                set_c0_status(irq_hwmask[irq] & ST0_IM);
+}
+
+#else
+
+static inline void smtc_im_ack_irq(unsigned int irq)
+{
+}
+
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
+#include <linux/cpumask.h>
+
+extern void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity);
+extern void smtc_forward_irq(unsigned int irq);
+
+/*
+ * IRQ affinity hook invoked at the beginning of interrupt dispatch
+ * if option is enabled.
+ *
+ * Up through Linux 2.6.22 (at least) cpumask operations are very
+ * inefficient on MIPS.  Initial prototypes of SMTC IRQ affinity
+ * used a "fast path" per-IRQ-descriptor cache of affinity information
+ * to reduce latency.  As there is a project afoot to optimize the
+ * cpumask implementations, this version is optimistically assuming
+ * that cpumask.h macro overhead is reasonable during interrupt dispatch.
+ */
+#define IRQ_AFFINITY_HOOK(irq)                                          \
+do {                                                                    \
+    if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) {       \
+        smtc_forward_irq(irq);                                          \
+        irq_exit();                                                     \
+        return;                                                         \
+    }                                                                   \
+} while (0)
+
+#else /* Not doing SMTC affinity */
+
+#define IRQ_AFFINITY_HOOK(irq) do { } while (0)
+
+#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
+
+#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
+
+/*
+ * Clear interrupt mask handling "backstop" if irq_hwmask
+ * entry so indicates. This implies that the ack() or end()
+ * functions will take over re-enabling the low-level mask.
+ * Otherwise it will be done on return from exception.
+ */
+#define __DO_IRQ_SMTC_HOOK(irq)                                         \
+do {                                                                    \
+        IRQ_AFFINITY_HOOK(irq);                                         \
+        if (irq_hwmask[irq] & 0x0000ff00)                               \
+                write_c0_tccontext(read_c0_tccontext() &                \
+                                   ~(irq_hwmask[irq] & 0x0000ff00));    \
+} while (0)
+
+#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq)                                \
+do {                                                                    \
+        if (irq_hwmask[irq] & 0x0000ff00)                               \
+                write_c0_tccontext(read_c0_tccontext() &                \
+                                   ~(irq_hwmask[irq] & 0x0000ff00));    \
+} while (0)
+
+#else
+
+#define __DO_IRQ_SMTC_HOOK(irq)                                         \
+do {                                                                    \
+        IRQ_AFFINITY_HOOK(irq);                                         \
+} while (0)
+#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
+
+#endif
+
+/*
+ * do_IRQ handles all normal device IRQ's (the special
+ * SMP cross-CPU interrupts have their own specific
+ * handlers).
+ *
+ * Ideally there should be away to get this into kernel/irq/handle.c to
+ * avoid the overhead of a call for just a tiny function ...
+ */
+#define do_IRQ(irq)                                                     \
+do {                                                                    \
+        irq_enter();                                                    \
+        __DO_IRQ_SMTC_HOOK(irq);                                        \
+        generic_handle_irq(irq);                                        \
+        irq_exit();                                                     \
+} while (0)
+
+#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
+/*
+ * To avoid inefficient and in some cases pathological re-checking of
+ * IRQ affinity, we have this variant that skips the affinity check.
+ */
+
+
+#define do_IRQ_no_affinity(irq)                                         \
+do {                                                                    \
+        irq_enter();                                                    \
+        __NO_AFFINITY_IRQ_SMTC_HOOK(irq);                               \
+        generic_handle_irq(irq);                                        \
+        irq_exit();                                                     \
+} while (0)
+
+#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
+
+extern void arch_init_irq(void);
+extern void spurious_interrupt(void);
+
+extern int allocate_irqno(void);
+extern void alloc_legacy_irqno(void);
+extern void free_irqno(unsigned int irq);
+
+/*
+ * Before R2 the timer and performance counter interrupts were both fixed to
+ * IE7.  Since R2 their number has to be read from the c0_intctl register.
+ */
+#define CP0_LEGACY_COMPARE_IRQ 7
+
+extern int cp0_compare_irq;
+extern int cp0_perfcount_irq;
+
+#endif /* _ASM_IRQ_H */
diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
new file mode 100644
index 000000000000..ef6a07cddb23
--- /dev/null
+++ b/arch/mips/include/asm/irq_cpu.h
@@ -0,0 +1,20 @@
+/*
+ *      include/asm-mips/irq_cpu.h
+ *
+ *      MIPS CPU interrupt definitions.
+ *
+ *      Copyright (C) 2002  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_IRQ_CPU_H
+#define _ASM_IRQ_CPU_H
+
+extern void mips_cpu_irq_init(void);
+extern void rm7k_cpu_irq_init(void);
+extern void rm9k_cpu_irq_init(void);
+
+#endif /* _ASM_IRQ_CPU_H */
diff --git a/arch/mips/include/asm/irq_gt641xx.h b/arch/mips/include/asm/irq_gt641xx.h
new file mode 100644
index 000000000000..f9a7c3ac2e66
--- /dev/null
+++ b/arch/mips/include/asm/irq_gt641xx.h
@@ -0,0 +1,60 @@
+/*
+ *  Galileo/Marvell GT641xx IRQ definitions.
+ *
+ *  Copyright (C) 2007  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#ifndef _ASM_IRQ_GT641XX_H
+#define _ASM_IRQ_GT641XX_H
+
+#ifndef GT641XX_IRQ_BASE
+#define GT641XX_IRQ_BASE                8
+#endif
+
+#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ         (GT641XX_IRQ_BASE + 1)
+#define GT641XX_DMA_OUT_OF_RANGE_IRQ            (GT641XX_IRQ_BASE + 2)
+#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ     (GT641XX_IRQ_BASE + 3)
+#define GT641XX_DMA0_IRQ                        (GT641XX_IRQ_BASE + 4)
+#define GT641XX_DMA1_IRQ                        (GT641XX_IRQ_BASE + 5)
+#define GT641XX_DMA2_IRQ                        (GT641XX_IRQ_BASE + 6)
+#define GT641XX_DMA3_IRQ                        (GT641XX_IRQ_BASE + 7)
+#define GT641XX_TIMER0_IRQ                      (GT641XX_IRQ_BASE + 8)
+#define GT641XX_TIMER1_IRQ                      (GT641XX_IRQ_BASE + 9)
+#define GT641XX_TIMER2_IRQ                      (GT641XX_IRQ_BASE + 10)
+#define GT641XX_TIMER3_IRQ                      (GT641XX_IRQ_BASE + 11)
+#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ     (GT641XX_IRQ_BASE + 12)
+#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ     (GT641XX_IRQ_BASE + 13)
+#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ    (GT641XX_IRQ_BASE + 14)
+#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ      (GT641XX_IRQ_BASE + 15)
+#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ         (GT641XX_IRQ_BASE + 16)
+#define GT641XX_MEMORY_ERROR_IRQ                (GT641XX_IRQ_BASE + 17)
+#define GT641XX_PCI_0_MASTER_ABORT_IRQ          (GT641XX_IRQ_BASE + 18)
+#define GT641XX_PCI_0_TARGET_ABORT_IRQ          (GT641XX_IRQ_BASE + 19)
+#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ         (GT641XX_IRQ_BASE + 20)
+#define GT641XX_CPU_INT0_IRQ                    (GT641XX_IRQ_BASE + 21)
+#define GT641XX_CPU_INT1_IRQ                    (GT641XX_IRQ_BASE + 22)
+#define GT641XX_CPU_INT2_IRQ                    (GT641XX_IRQ_BASE + 23)
+#define GT641XX_CPU_INT3_IRQ                    (GT641XX_IRQ_BASE + 24)
+#define GT641XX_CPU_INT4_IRQ                    (GT641XX_IRQ_BASE + 25)
+#define GT641XX_PCI_INT0_IRQ                    (GT641XX_IRQ_BASE + 26)
+#define GT641XX_PCI_INT1_IRQ                    (GT641XX_IRQ_BASE + 27)
+#define GT641XX_PCI_INT2_IRQ                    (GT641XX_IRQ_BASE + 28)
+#define GT641XX_PCI_INT3_IRQ                    (GT641XX_IRQ_BASE + 29)
+
+extern void gt641xx_irq_dispatch(void);
+extern void gt641xx_irq_init(void);
+
+#endif /* _ASM_IRQ_GT641XX_H */
diff --git a/arch/mips/include/asm/irq_regs.h b/arch/mips/include/asm/irq_regs.h
new file mode 100644
index 000000000000..33bd2a06de57
--- /dev/null
+++ b/arch/mips/include/asm/irq_regs.h
@@ -0,0 +1,21 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_IRQ_REGS_H
+#define __ASM_IRQ_REGS_H
+
+#define ARCH_HAS_OWN_IRQ_REGS
+
+#include <linux/thread_info.h>
+
+static inline struct pt_regs *get_irq_regs(void)
+{
+        return current_thread_info()->regs;
+}
+
+#endif /* __ASM_IRQ_REGS_H */
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
new file mode 100644
index 000000000000..701ec0ba8fa9
--- /dev/null
+++ b/arch/mips/include/asm/irqflags.h
@@ -0,0 +1,283 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <asm/hazards.h>
+
+__asm__(
+        "       .macro  raw_local_irq_enable                            \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    $1, $2, 1       # SMTC - clear TCStatus.IXMT    \n"
+        "       ori     $1, 0x400                                       \n"
+        "       xori    $1, 0x400                                       \n"
+        "       mtc0    $1, $2, 1                                       \n"
+#elif defined(CONFIG_CPU_MIPSR2)
+        "       ei                                                      \n"
+#else
+        "       mfc0    $1,$12                                          \n"
+        "       ori     $1,0x1f                                         \n"
+        "       xori    $1,0x1e                                         \n"
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       irq_enable_hazard                                       \n"
+        "       .set    pop                                             \n"
+        "       .endm");
+
+extern void smtc_ipi_replay(void);
+
+static inline void raw_local_irq_enable(void)
+{
+#ifdef CONFIG_MIPS_MT_SMTC
+        /*
+         * SMTC kernel needs to do a software replay of queued
+         * IPIs, at the cost of call overhead on each local_irq_enable()
+         */
+        smtc_ipi_replay();
+#endif
+        __asm__ __volatile__(
+                "raw_local_irq_enable"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory");
+}
+
+
+/*
+ * For cli() we have to insert nops to make sure that the new value
+ * has actually arrived in the status register before the end of this
+ * macro.
+ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
+ * no nops at all.
+ */
+/*
+ * For TX49, operating only IE bit is not enough.
+ *
+ * If mfc0 $12 follows store and the mfc0 is last instruction of a
+ * page and fetching the next instruction causes TLB miss, the result
+ * of the mfc0 might wrongly contain EXL bit.
+ *
+ * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
+ *
+ * Workaround: mask EXL bit of the result or place a nop before mfc0.
+ */
+__asm__(
+        "       .macro  raw_local_irq_disable\n"
+        "       .set    push                                            \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    $1, $2, 1                                       \n"
+        "       ori     $1, 0x400                                       \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $2, 1                                       \n"
+#elif defined(CONFIG_CPU_MIPSR2)
+        "       di                                                      \n"
+#else
+        "       mfc0    $1,$12                                          \n"
+        "       ori     $1,0x1f                                         \n"
+        "       xori    $1,0x1f                                         \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1,$12                                          \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
+
+static inline void raw_local_irq_disable(void)
+{
+        __asm__ __volatile__(
+                "raw_local_irq_disable"
+                : /* no outputs */
+                : /* no inputs */
+                : "memory");
+}
+
+__asm__(
+        "       .macro  raw_local_save_flags flags                      \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    \\flags, $2, 1                                  \n"
+#else
+        "       mfc0    \\flags, $12                                    \n"
+#endif
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
+
+#define raw_local_save_flags(x)                                         \
+__asm__ __volatile__(                                                   \
+        "raw_local_save_flags %0"                                       \
+        : "=r" (x))
+
+__asm__(
+        "       .macro  raw_local_irq_save result                       \n"
+        "       .set    push                                            \n"
+        "       .set    reorder                                         \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "       mfc0    \\result, $2, 1                                 \n"
+        "       ori     $1, \\result, 0x400                             \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $2, 1                                       \n"
+        "       andi    \\result, \\result, 0x400                       \n"
+#elif defined(CONFIG_CPU_MIPSR2)
+        "       di      \\result                                        \n"
+        "       andi    \\result, 1                                     \n"
+#else
+        "       mfc0    \\result, $12                                   \n"
+        "       ori     $1, \\result, 0x1f                              \n"
+        "       xori    $1, 0x1f                                        \n"
+        "       .set    noreorder                                       \n"
+        "       mtc0    $1, $12                                         \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
+
+#define raw_local_irq_save(x)                                           \
+__asm__ __volatile__(                                                   \
+        "raw_local_irq_save\t%0"                                        \
+        : "=r" (x)                                                      \
+        : /* no inputs */                                               \
+        : "memory")
+
+__asm__(
+        "       .macro  raw_local_irq_restore flags                     \n"
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+#ifdef CONFIG_MIPS_MT_SMTC
+        "mfc0   $1, $2, 1                                               \n"
+        "andi   \\flags, 0x400                                          \n"
+        "ori    $1, 0x400                                               \n"
+        "xori   $1, 0x400                                               \n"
+        "or     \\flags, $1                                             \n"
+        "mtc0   \\flags, $2, 1                                          \n"
+#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
+        /*
+         * Slow, but doesn't suffer from a relativly unlikely race
+         * condition we're having since days 1.
+         */
+        "       beqz    \\flags, 1f                                     \n"
+        "        di                                                     \n"
+        "       ei                                                      \n"
+        "1:                                                             \n"
+#elif defined(CONFIG_CPU_MIPSR2)
+        /*
+         * Fast, dangerous.  Life is fun, life is good.
+         */
+        "       mfc0    $1, $12                                         \n"
+        "       ins     $1, \\flags, 0, 1                               \n"
+        "       mtc0    $1, $12                                         \n"
+#else
+        "       mfc0    $1, $12                                         \n"
+        "       andi    \\flags, 1                                      \n"
+        "       ori     $1, 0x1f                                        \n"
+        "       xori    $1, 0x1f                                        \n"
+        "       or      \\flags, $1                                     \n"
+        "       mtc0    \\flags, $12                                    \n"
+#endif
+        "       irq_disable_hazard                                      \n"
+        "       .set    pop                                             \n"
+        "       .endm                                                   \n");
+
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+        unsigned long __tmp1;
+
+#ifdef CONFIG_MIPS_MT_SMTC
+        /*
+         * SMTC kernel needs to do a software replay of queued
+         * IPIs, at the cost of branch and call overhead on each
+         * local_irq_restore()
+         */
+        if (unlikely(!(flags & 0x0400)))
+                smtc_ipi_replay();
+#endif
+
+        __asm__ __volatile__(
+                "raw_local_irq_restore\t%0"
+                : "=r" (__tmp1)
+                : "0" (flags)
+                : "memory");
+}
+
+static inline void __raw_local_irq_restore(unsigned long flags)
+{
+        unsigned long __tmp1;
+
+        __asm__ __volatile__(
+                "raw_local_irq_restore\t%0"
+                : "=r" (__tmp1)
+                : "0" (flags)
+                : "memory");
+}
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+#ifdef CONFIG_MIPS_MT_SMTC
+        /*
+         * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
+         */
+        return flags & 0x400;
+#else
+        return !(flags & 1);
+#endif
+}
+
+#endif
+
+/*
+ * Do the CPU's IRQ-state tracing from assembly code.
+ */
+#ifdef CONFIG_TRACE_IRQFLAGS
+/* Reload some registers clobbered by trace_hardirqs_on */
+#ifdef CONFIG_64BIT
+# define TRACE_IRQS_RELOAD_REGS                                         \
+        LONG_L  $11, PT_R11(sp);                                        \
+        LONG_L  $10, PT_R10(sp);                                        \
+        LONG_L  $9, PT_R9(sp);                                          \
+        LONG_L  $8, PT_R8(sp);                                          \
+        LONG_L  $7, PT_R7(sp);                                          \
+        LONG_L  $6, PT_R6(sp);                                          \
+        LONG_L  $5, PT_R5(sp);                                          \
+        LONG_L  $4, PT_R4(sp);                                          \
+        LONG_L  $2, PT_R2(sp)
+#else
+# define TRACE_IRQS_RELOAD_REGS                                         \
+        LONG_L  $7, PT_R7(sp);                                          \
+        LONG_L  $6, PT_R6(sp);                                          \
+        LONG_L  $5, PT_R5(sp);                                          \
+        LONG_L  $4, PT_R4(sp);                                          \
+        LONG_L  $2, PT_R2(sp)
+#endif
+# define TRACE_IRQS_ON                                                  \
+        CLI;    /* make sure trace_hardirqs_on() is called in kernel level */ \
+        jal     trace_hardirqs_on
+# define TRACE_IRQS_ON_RELOAD                                           \
+        TRACE_IRQS_ON;                                                  \
+        TRACE_IRQS_RELOAD_REGS
+# define TRACE_IRQS_OFF                                                 \
+        jal     trace_hardirqs_off
+#else
+# define TRACE_IRQS_ON
+# define TRACE_IRQS_ON_RELOAD
+# define TRACE_IRQS_OFF
+#endif
+
+#endif /* _ASM_IRQFLAGS_H */
diff --git a/arch/mips/include/asm/isadep.h b/arch/mips/include/asm/isadep.h
new file mode 100644
index 000000000000..24c6cda79377
--- /dev/null
+++ b/arch/mips/include/asm/isadep.h
@@ -0,0 +1,34 @@
+/*
+ * Various ISA level dependent constants.
+ * Most of the following constants reflect the different layout
+ * of Coprocessor 0 registers.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ */
+
+#ifndef __ASM_ISADEP_H
+#define __ASM_ISADEP_H
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+/*
+ * R2000 or R3000
+ */
+
+/*
+ * kernel or user mode? (CP0_STATUS)
+ */
+#define KU_MASK 0x08
+#define KU_USER 0x08
+#define KU_KERN 0x00
+
+#else
+/*
+ * kernel or user mode?
+ */
+#define KU_MASK 0x18
+#define KU_USER 0x10
+#define KU_KERN 0x00
+
+#endif
+
+#endif /* __ASM_ISADEP_H */
diff --git a/arch/mips/include/asm/jazz.h b/arch/mips/include/asm/jazz.h
new file mode 100644
index 000000000000..83f449dec95e
--- /dev/null
+++ b/arch/mips/include/asm/jazz.h
@@ -0,0 +1,310 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
+ */
+#ifndef __ASM_JAZZ_H
+#define __ASM_JAZZ_H
+
+/*
+ * The addresses below are virtual address. The mappings are
+ * created on startup via wired entries in the tlb. The Mips
+ * Magnum R3000 and R4000 machines are similar in many aspects,
+ * but many hardware register are accessible at 0xb9000000 in
+ * instead of 0xe0000000.
+ */
+
+#define JAZZ_LOCAL_IO_SPACE     0xe0000000
+
+/*
+ * Revision numbers in PICA_ASIC_REVISION
+ *
+ * 0xf0000000 - Rev1
+ * 0xf0000001 - Rev2
+ * 0xf0000002 - Rev3
+ */
+#define PICA_ASIC_REVISION      0xe0000008
+
+/*
+ * The segments of the seven segment LED are mapped
+ * to the control bits as follows:
+ *
+ *         (7)
+ *      ---------
+ *      |       |
+ *  (2) |       | (6)
+ *      |  (1)  |
+ *      ---------
+ *      |       |
+ *  (3) |       | (5)
+ *      |  (4)  |
+ *      --------- . (0)
+ */
+#define PICA_LED                0xe000f000
+
+/*
+ * Some characters for the LED control registers
+ * The original Mips machines seem to have a LED display
+ * with integrated decoder while the Acer machines can
+ * control each of the seven segments and the dot independently.
+ * It's only a toy, anyway...
+ */
+#define LED_DOT                 0x01
+#define LED_SPACE               0x00
+#define LED_0                   0xfc
+#define LED_1                   0x60
+#define LED_2                   0xda
+#define LED_3                   0xf2
+#define LED_4                   0x66
+#define LED_5                   0xb6
+#define LED_6                   0xbe
+#define LED_7                   0xe0
+#define LED_8                   0xfe
+#define LED_9                   0xf6
+#define LED_A                   0xee
+#define LED_b                   0x3e
+#define LED_C                   0x9c
+#define LED_d                   0x7a
+#define LED_E                   0x9e
+#define LED_F                   0x8e
+
+#ifndef __ASSEMBLY__
+
+static __inline__ void pica_set_led(unsigned int bits)
+{
+        volatile unsigned int *led_register = (unsigned int *) PICA_LED;
+
+        *led_register = bits;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Base address of the Sonic Ethernet adapter in Jazz machines.
+ */
+#define JAZZ_ETHERNET_BASE  0xe0001000
+
+/*
+ * Base address of the 53C94 SCSI hostadapter in Jazz machines.
+ */
+#define JAZZ_SCSI_BASE          0xe0002000
+
+/*
+ * i8042 keyboard controller for JAZZ and PICA chipsets.
+ * This address is just a guess and seems to differ from
+ * other mips machines such as RC3xxx...
+ */
+#define JAZZ_KEYBOARD_ADDRESS   0xe0005000
+#define JAZZ_KEYBOARD_DATA      0xe0005000
+#define JAZZ_KEYBOARD_COMMAND   0xe0005001
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+        unsigned char data;
+        unsigned char command;
+} jazz_keyboard_hardware;
+
+#define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS)
+
+typedef struct {
+        unsigned char pad0[3];
+        unsigned char data;
+        unsigned char pad1[3];
+        unsigned char command;
+} mips_keyboard_hardware;
+
+/*
+ * For now. Needs to be changed for RC3xxx support. See below.
+ */
+#define keyboard_hardware       jazz_keyboard_hardware
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * i8042 keyboard controller for most other Mips machines.
+ */
+#define MIPS_KEYBOARD_ADDRESS   0xb9005000
+#define MIPS_KEYBOARD_DATA      0xb9005003
+#define MIPS_KEYBOARD_COMMAND   0xb9005007
+
+/*
+ * Serial and parallel ports (WD 16C552) on the Mips JAZZ
+ */
+#define JAZZ_SERIAL1_BASE       (unsigned int)0xe0006000
+#define JAZZ_SERIAL2_BASE       (unsigned int)0xe0007000
+#define JAZZ_PARALLEL_BASE      (unsigned int)0xe0008000
+
+/*
+ * Dummy Device Address. Used in jazzdma.c
+ */
+#define JAZZ_DUMMY_DEVICE       0xe000d000
+
+/*
+ * JAZZ timer registers and interrupt no.
+ * Note that the hardware timer interrupt is actually on
+ * cpu level 6, but to keep compatibility with PC stuff
+ * it is remapped to vector 0. See arch/mips/kernel/entry.S.
+ */
+#define JAZZ_TIMER_INTERVAL     0xe0000228
+#define JAZZ_TIMER_REGISTER     0xe0000230
+
+/*
+ * DRAM configuration register
+ */
+#ifndef __ASSEMBLY__
+#ifdef __MIPSEL__
+typedef struct {
+        unsigned int bank2 : 3;
+        unsigned int bank1 : 3;
+        unsigned int mem_bus_width : 1;
+        unsigned int reserved2 : 1;
+        unsigned int page_mode : 1;
+        unsigned int reserved1 : 23;
+} dram_configuration;
+#else /* defined (__MIPSEB__) */
+typedef struct {
+        unsigned int reserved1 : 23;
+        unsigned int page_mode : 1;
+        unsigned int reserved2 : 1;
+        unsigned int mem_bus_width : 1;
+        unsigned int bank1 : 3;
+        unsigned int bank2 : 3;
+} dram_configuration;
+#endif
+#endif /* !__ASSEMBLY__ */
+
+#define PICA_DRAM_CONFIG        0xe00fffe0
+
+/*
+ * JAZZ interrupt control registers
+ */
+#define JAZZ_IO_IRQ_SOURCE      0xe0010000
+#define JAZZ_IO_IRQ_ENABLE      0xe0010002
+
+/*
+ * JAZZ Interrupt Level definitions
+ *
+ * This is somewhat broken.  For reasons which nobody can remember anymore
+ * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
+ */
+#define JAZZ_IRQ_START          24
+#define JAZZ_IRQ_END            (24 + 9)
+#define JAZZ_PARALLEL_IRQ       (JAZZ_IRQ_START + 0)
+#define JAZZ_FLOPPY_IRQ         (JAZZ_IRQ_START + 1)
+#define JAZZ_SOUND_IRQ          (JAZZ_IRQ_START + 2)
+#define JAZZ_VIDEO_IRQ          (JAZZ_IRQ_START + 3)
+#define JAZZ_ETHERNET_IRQ       (JAZZ_IRQ_START + 4)
+#define JAZZ_SCSI_IRQ           (JAZZ_IRQ_START + 5)
+#define JAZZ_KEYBOARD_IRQ       (JAZZ_IRQ_START + 6)
+#define JAZZ_MOUSE_IRQ          (JAZZ_IRQ_START + 7)
+#define JAZZ_SERIAL1_IRQ        (JAZZ_IRQ_START + 8)
+#define JAZZ_SERIAL2_IRQ        (JAZZ_IRQ_START + 9)
+
+#define JAZZ_TIMER_IRQ          (MIPS_CPU_IRQ_BASE+6)
+
+
+/*
+ * JAZZ DMA Channels
+ * Note: Channels 4...7 are not used with respect to the Acer PICA-61
+ * chipset which does not provide these DMA channels.
+ */
+#define JAZZ_SCSI_DMA           0              /* SCSI */
+#define JAZZ_FLOPPY_DMA         1              /* FLOPPY */
+#define JAZZ_AUDIOL_DMA         2              /* AUDIO L */
+#define JAZZ_AUDIOR_DMA         3              /* AUDIO R */
+
+/*
+ * JAZZ R4030 MCT_ADR chip (DMA controller)
+ * Note: Virtual Addresses !
+ */
+#define JAZZ_R4030_CONFIG       0xE0000000      /* R4030 config register */
+#define JAZZ_R4030_REVISION     0xE0000008      /* same as PICA_ASIC_REVISION */
+#define JAZZ_R4030_INV_ADDR     0xE0000010      /* Invalid Address register */
+
+#define JAZZ_R4030_TRSTBL_BASE  0xE0000018      /* Translation Table Base */
+#define JAZZ_R4030_TRSTBL_LIM   0xE0000020      /* Translation Table Limit */
+#define JAZZ_R4030_TRSTBL_INV   0xE0000028      /* Translation Table Invalidate */
+
+#define JAZZ_R4030_CACHE_MTNC   0xE0000030      /* Cache Maintenance */
+#define JAZZ_R4030_R_FAIL_ADDR  0xE0000038      /* Remote Failed Address */
+#define JAZZ_R4030_M_FAIL_ADDR  0xE0000040      /* Memory Failed Address */
+
+#define JAZZ_R4030_CACHE_PTAG   0xE0000048      /* I/O Cache Physical Tag */
+#define JAZZ_R4030_CACHE_LTAG   0xE0000050      /* I/O Cache Logical Tag */
+#define JAZZ_R4030_CACHE_BMASK  0xE0000058      /* I/O Cache Byte Mask */
+#define JAZZ_R4030_CACHE_BWIN   0xE0000060      /* I/O Cache Buffer Window */
+
+/*
+ * Remote Speed Registers.
+ *
+ *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
+ *  4: RTC,       5: Kb./Mouse  6: serial 1,  7: serial 2,
+ *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
+ * 12: reserved, 13: free,     14: 7seg LED, 15: ???
+ */
+#define JAZZ_R4030_REM_SPEED    0xE0000070      /* 16 Remote Speed Registers */
+                                                /* 0xE0000070,78,80... 0xE00000E8 */
+#define JAZZ_R4030_IRQ_ENABLE   0xE00000E8      /* Internal Interrupt Enable */
+#define JAZZ_R4030_INVAL_ADDR   0xE0000010      /* Invalid address Register */
+#define JAZZ_R4030_IRQ_SOURCE   0xE0000200      /* Interrupt Source Register */
+#define JAZZ_R4030_I386_ERROR   0xE0000208      /* i386/EISA Bus Error */
+
+/*
+ * Virtual (E)ISA controller address
+ */
+#define JAZZ_EISA_IRQ_ACK       0xE0000238      /* EISA interrupt acknowledge */
+
+/*
+ * Access the R4030 DMA and I/O Controller
+ */
+#ifndef __ASSEMBLY__
+
+static inline void r4030_delay(void)
+{
+__asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        ".set\treorder");
+}
+
+static inline unsigned short r4030_read_reg16(unsigned long addr)
+{
+        unsigned short ret = *((volatile unsigned short *)addr);
+        r4030_delay();
+        return ret;
+}
+
+static inline unsigned int r4030_read_reg32(unsigned long addr)
+{
+        unsigned int ret = *((volatile unsigned int *)addr);
+        r4030_delay();
+        return ret;
+}
+
+static inline void r4030_write_reg16(unsigned long addr, unsigned val)
+{
+        *((volatile unsigned short *)addr) = val;
+        r4030_delay();
+}
+
+static inline void r4030_write_reg32(unsigned long addr, unsigned val)
+{
+        *((volatile unsigned int *)addr) = val;
+        r4030_delay();
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#define JAZZ_FDC_BASE   0xe0003000
+#define JAZZ_RTC_BASE   0xe0004000
+#define JAZZ_PORT_BASE  0xe2000000
+
+#define JAZZ_EISA_BASE  0xe3000000
+
+#endif /* __ASM_JAZZ_H */
diff --git a/arch/mips/include/asm/jazzdma.h b/arch/mips/include/asm/jazzdma.h
new file mode 100644
index 000000000000..8bb37bba68f0
--- /dev/null
+++ b/arch/mips/include/asm/jazzdma.h
@@ -0,0 +1,95 @@
+/*
+ * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support
+ */
+#ifndef _ASM_JAZZDMA_H
+#define _ASM_JAZZDMA_H
+
+/*
+ * Prototypes and macros
+ */
+extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size);
+extern int vdma_free(unsigned long laddr);
+extern int vdma_remap(unsigned long laddr, unsigned long paddr,
+                      unsigned long size);
+extern unsigned long vdma_phys2log(unsigned long paddr);
+extern unsigned long vdma_log2phys(unsigned long laddr);
+extern void vdma_stats(void);           /* for debugging only */
+
+extern void vdma_enable(int channel);
+extern void vdma_disable(int channel);
+extern void vdma_set_mode(int channel, int mode);
+extern void vdma_set_addr(int channel, long addr);
+extern void vdma_set_count(int channel, int count);
+extern int vdma_get_residue(int channel);
+extern int vdma_get_enable(int channel);
+
+/*
+ * some definitions used by the driver functions
+ */
+#define VDMA_PAGESIZE           4096
+#define VDMA_PGTBL_ENTRIES      4096
+#define VDMA_PGTBL_SIZE         (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES)
+#define VDMA_PAGE_EMPTY         0xff000000
+
+/*
+ * Macros to get page no. and offset of a given address
+ * Note that VDMA_PAGE() works for physical addresses only
+ */
+#define VDMA_PAGE(a)            ((unsigned int)(a) >> 12)
+#define VDMA_OFFSET(a)          ((unsigned int)(a) & (VDMA_PAGESIZE-1))
+
+/*
+ * error code returned by vdma_alloc()
+ * (See also arch/mips/kernel/jazzdma.c)
+ */
+#define VDMA_ERROR              0xffffffff
+
+/*
+ * VDMA pagetable entry description
+ */
+typedef volatile struct VDMA_PGTBL_ENTRY {
+        unsigned int frame;             /* physical frame no. */
+        unsigned int owner;             /* owner of this entry (0=free) */
+} VDMA_PGTBL_ENTRY;
+
+
+/*
+ * DMA channel control registers
+ * in the R4030 MCT_ADR chip
+ */
+#define JAZZ_R4030_CHNL_MODE    0xE0000100      /* 8 DMA Channel Mode Registers, */
+                                                /* 0xE0000100,120,140... */
+#define JAZZ_R4030_CHNL_ENABLE  0xE0000108      /* 8 DMA Channel Enable Regs, */
+                                                /* 0xE0000108,128,148... */
+#define JAZZ_R4030_CHNL_COUNT   0xE0000110      /* 8 DMA Channel Byte Cnt Regs, */
+                                                /* 0xE0000110,130,150... */
+#define JAZZ_R4030_CHNL_ADDR    0xE0000118      /* 8 DMA Channel Address Regs, */
+                                                /* 0xE0000118,138,158... */
+
+/* channel enable register bits */
+
+#define R4030_CHNL_ENABLE        (1<<0)
+#define R4030_CHNL_WRITE         (1<<1)
+#define R4030_TC_INTR            (1<<8)
+#define R4030_MEM_INTR           (1<<9)
+#define R4030_ADDR_INTR          (1<<10)
+
+/*
+ * Channel mode register bits
+ */
+#define R4030_MODE_ATIME_40      (0) /* device access time on remote bus */
+#define R4030_MODE_ATIME_80      (1)
+#define R4030_MODE_ATIME_120     (2)
+#define R4030_MODE_ATIME_160     (3)
+#define R4030_MODE_ATIME_200     (4)
+#define R4030_MODE_ATIME_240     (5)
+#define R4030_MODE_ATIME_280     (6)
+#define R4030_MODE_ATIME_320     (7)
+#define R4030_MODE_WIDTH_8       (1<<3) /* device data bus width */
+#define R4030_MODE_WIDTH_16      (2<<3)
+#define R4030_MODE_WIDTH_32      (3<<3)
+#define R4030_MODE_INTR_EN       (1<<5)
+#define R4030_MODE_BURST         (1<<6) /* Rev. 2 only */
+#define R4030_MODE_FAST_ACK      (1<<7) /* Rev. 2 only */
+
+#endif /* _ASM_JAZZDMA_H */
diff --git a/arch/mips/include/asm/kdebug.h b/arch/mips/include/asm/kdebug.h
new file mode 100644
index 000000000000..5bf62aafc890
--- /dev/null
+++ b/arch/mips/include/asm/kdebug.h
@@ -0,0 +1,13 @@
+#ifndef _ASM_MIPS_KDEBUG_H
+#define _ASM_MIPS_KDEBUG_H
+
+#include <linux/notifier.h>
+
+enum die_val {
+        DIE_OOPS = 1,
+        DIE_FP,
+        DIE_TRAP,
+        DIE_RI,
+};
+
+#endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/arch/mips/include/asm/kexec.h b/arch/mips/include/asm/kexec.h
new file mode 100644
index 000000000000..4314892aaebb
--- /dev/null
+++ b/arch/mips/include/asm/kexec.h
@@ -0,0 +1,30 @@
+/*
+ * kexec.h for kexec
+ * Created by <nschichan@corp.free.fr> on Thu Oct 12 14:59:34 2006
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2.  See the file COPYING for more details.
+ */
+
+#ifndef _MIPS_KEXEC
+# define _MIPS_KEXEC
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000)
+ /* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000)
+
+#define KEXEC_CONTROL_PAGE_SIZE 4096
+
+/* The native architecture */
+#define KEXEC_ARCH KEXEC_ARCH_MIPS
+
+static inline void crash_setup_regs(struct pt_regs *newregs,
+                                    struct pt_regs *oldregs)
+{
+        /* Dummy implementation for now */
+}
+
+#endif /* !_MIPS_KEXEC */
diff --git a/arch/mips/include/asm/kgdb.h b/arch/mips/include/asm/kgdb.h
new file mode 100644
index 000000000000..48223b09396c
--- /dev/null
+++ b/arch/mips/include/asm/kgdb.h
@@ -0,0 +1,44 @@
+#ifndef __ASM_KGDB_H_
+#define __ASM_KGDB_H_
+
+#ifdef __KERNEL__
+
+#include <asm/sgidefs.h>
+
+#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
+        (_MIPS_ISA == _MIPS_ISA_MIPS32)
+
+#define KGDB_GDB_REG_SIZE 32
+
+#elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
+        (_MIPS_ISA == _MIPS_ISA_MIPS64)
+
+#ifdef CONFIG_32BIT
+#define KGDB_GDB_REG_SIZE 32
+#else /* CONFIG_CPU_32BIT */
+#define KGDB_GDB_REG_SIZE 64
+#endif
+#else
+#error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA"
+#endif /* _MIPS_ISA */
+
+#define BUFMAX                  2048
+#if (KGDB_GDB_REG_SIZE == 32)
+#define NUMREGBYTES             (90*sizeof(u32))
+#define NUMCRITREGBYTES         (12*sizeof(u32))
+#else
+#define NUMREGBYTES             (90*sizeof(u64))
+#define NUMCRITREGBYTES         (12*sizeof(u64))
+#endif
+#define BREAK_INSTR_SIZE        4
+#define CACHE_FLUSH_IS_SAFE     0
+
+extern void arch_kgdb_breakpoint(void);
+extern int kgdb_early_setup;
+extern void *saved_vectors[32];
+extern void handle_exception(struct pt_regs *regs);
+extern void breakinst(void);
+
+#endif                          /* __KERNEL__ */
+
+#endif /* __ASM_KGDB_H_ */
diff --git a/arch/mips/include/asm/kmap_types.h b/arch/mips/include/asm/kmap_types.h
new file mode 100644
index 000000000000..806aae3c5338
--- /dev/null
+++ b/arch/mips/include/asm/kmap_types.h
@@ -0,0 +1,30 @@
+#ifndef _ASM_KMAP_TYPES_H
+#define _ASM_KMAP_TYPES_H
+
+
+#ifdef CONFIG_DEBUG_HIGHMEM
+# define D(n) __KM_FENCE_##n ,
+#else
+# define D(n)
+#endif
+
+enum km_type {
+D(0)    KM_BOUNCE_READ,
+D(1)    KM_SKB_SUNRPC_DATA,
+D(2)    KM_SKB_DATA_SOFTIRQ,
+D(3)    KM_USER0,
+D(4)    KM_USER1,
+D(5)    KM_BIO_SRC_IRQ,
+D(6)    KM_BIO_DST_IRQ,
+D(7)    KM_PTE0,
+D(8)    KM_PTE1,
+D(9)    KM_IRQ0,
+D(10)   KM_IRQ1,
+D(11)   KM_SOFTIRQ0,
+D(12)   KM_SOFTIRQ1,
+D(13)   KM_TYPE_NR
+};
+
+#undef D
+
+#endif
diff --git a/arch/mips/include/asm/kspd.h b/arch/mips/include/asm/kspd.h
new file mode 100644
index 000000000000..4e9e724c8935
--- /dev/null
+++ b/arch/mips/include/asm/kspd.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#ifndef _ASM_KSPD_H
+#define _ASM_KSPD_H
+
+struct kspd_notifications {
+        void (*kspd_sp_exit)(int sp_id);
+
+        struct list_head list;
+};
+
+#ifdef CONFIG_MIPS_APSP_KSPD
+extern void kspd_notify(struct kspd_notifications *notify);
+#else
+static inline void kspd_notify(struct kspd_notifications *notify)
+{
+}
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/lasat/ds1603.h b/arch/mips/include/asm/lasat/ds1603.h
new file mode 100644
index 000000000000..edcd7544b358
--- /dev/null
+++ b/arch/mips/include/asm/lasat/ds1603.h
@@ -0,0 +1,18 @@
+#include <asm/addrspace.h>
+
+/* Lasat 100    */
+#define DS1603_REG_100          (KSEG1ADDR(0x1c810000))
+#define DS1603_RST_100          (1 << 2)
+#define DS1603_CLK_100          (1 << 0)
+#define DS1603_DATA_SHIFT_100   1
+#define DS1603_DATA_100         (1 << DS1603_DATA_SHIFT_100)
+
+/* Lasat 200    */
+#define DS1603_REG_200          (KSEG1ADDR(0x11000000))
+#define DS1603_RST_200          (1 << 3)
+#define DS1603_CLK_200          (1 << 4)
+#define DS1603_DATA_200         (1 << 5)
+
+#define DS1603_DATA_REG_200             (DS1603_REG_200 + 0x10000)
+#define DS1603_DATA_READ_SHIFT_200      9
+#define DS1603_DATA_READ_200    (1 << DS1603_DATA_READ_SHIFT_200)
diff --git a/arch/mips/include/asm/lasat/eeprom.h b/arch/mips/include/asm/lasat/eeprom.h
new file mode 100644
index 000000000000..3dac203697fa
--- /dev/null
+++ b/arch/mips/include/asm/lasat/eeprom.h
@@ -0,0 +1,17 @@
+#include <asm/addrspace.h>
+
+/* lasat 100 */
+#define AT93C_REG_100               KSEG1ADDR(0x1c810000)
+#define AT93C_RDATA_REG_100         AT93C_REG_100
+#define AT93C_RDATA_SHIFT_100       4
+#define AT93C_WDATA_SHIFT_100       4
+#define AT93C_CS_M_100              (1 << 5)
+#define AT93C_CLK_M_100             (1 << 3)
+
+/* lasat 200 */
+#define AT93C_REG_200           KSEG1ADDR(0x11000000)
+#define AT93C_RDATA_REG_200     (AT93C_REG_200+0x10000)
+#define AT93C_RDATA_SHIFT_200   8
+#define AT93C_WDATA_SHIFT_200   2
+#define AT93C_CS_M_200          (1 << 0)
+#define AT93C_CLK_M_200         (1 << 1)
diff --git a/arch/mips/include/asm/lasat/head.h b/arch/mips/include/asm/lasat/head.h
new file mode 100644
index 000000000000..f5589f31a197
--- /dev/null
+++ b/arch/mips/include/asm/lasat/head.h
@@ -0,0 +1,22 @@
+/*
+ * Image header stuff
+ */
+#ifndef _HEAD_H
+#define _HEAD_H
+
+#define LASAT_K_MAGIC0_VAL      0xfedeabba
+#define LASAT_K_MAGIC1_VAL      0x00bedead
+
+#ifndef _LANGUAGE_ASSEMBLY
+#include <linux/types.h>
+struct bootloader_header {
+        u32 magic[2];
+        u32 version;
+        u32 image_start;
+        u32 image_size;
+        u32 kernel_start;
+        u32 kernel_entry;
+};
+#endif
+
+#endif /* _HEAD_H */
diff --git a/arch/mips/include/asm/lasat/lasat.h b/arch/mips/include/asm/lasat/lasat.h
new file mode 100644
index 000000000000..caeba1e302a2
--- /dev/null
+++ b/arch/mips/include/asm/lasat/lasat.h
@@ -0,0 +1,258 @@
+/*
+ * lasat.h
+ *
+ * Thomas Horsten <thh@lasat.com>
+ * Copyright (C) 2000 LASAT Networks A/S.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Configuration for LASAT boards, loads the appropriate include files.
+ */
+#ifndef _LASAT_H
+#define _LASAT_H
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+extern struct lasat_misc {
+        volatile u32 *reset_reg;
+        volatile u32 *flash_wp_reg;
+        u32 flash_wp_bit;
+} *lasat_misc;
+
+enum lasat_mtdparts {
+        LASAT_MTD_BOOTLOADER,
+        LASAT_MTD_SERVICE,
+        LASAT_MTD_NORMAL,
+        LASAT_MTD_CONFIG,
+        LASAT_MTD_FS,
+        LASAT_MTD_LAST
+};
+
+/*
+ * The format of the data record in the EEPROM.
+ * See Documentation/LASAT/eeprom.txt for a detailed description
+ * of the fields in this struct, and the LASAT Hardware Configuration
+ * field specification for a detailed description of the config
+ * field.
+ */
+#include <linux/types.h>
+
+#define LASAT_EEPROM_VERSION 7
+struct lasat_eeprom_struct {
+        unsigned int  version;
+        unsigned int  cfg[3];
+        unsigned char hwaddr[6];
+        unsigned char print_partno[12];
+        unsigned char term0;
+        unsigned char print_serial[14];
+        unsigned char term1;
+        unsigned char prod_partno[12];
+        unsigned char term2;
+        unsigned char prod_serial[14];
+        unsigned char term3;
+        unsigned char passwd_hash[16];
+        unsigned char pwdnull;
+        unsigned char vendid;
+        unsigned char ts_ref;
+        unsigned char ts_signoff;
+        unsigned char reserved[11];
+        unsigned char debugaccess;
+        unsigned short prid;
+        unsigned int  serviceflag;
+        unsigned int  ipaddr;
+        unsigned int  netmask;
+        unsigned int  crc32;
+};
+
+struct lasat_eeprom_struct_pre7 {
+        unsigned int  version;
+        unsigned int  flags[3];
+        unsigned char hwaddr0[6];
+        unsigned char hwaddr1[6];
+        unsigned char print_partno[9];
+        unsigned char term0;
+        unsigned char print_serial[14];
+        unsigned char term1;
+        unsigned char prod_partno[9];
+        unsigned char term2;
+        unsigned char prod_serial[14];
+        unsigned char term3;
+        unsigned char passwd_hash[24];
+        unsigned char pwdnull;
+        unsigned char vendor;
+        unsigned char ts_ref;
+        unsigned char ts_signoff;
+        unsigned char reserved[6];
+        unsigned int  writecount;
+        unsigned int  ipaddr;
+        unsigned int  netmask;
+        unsigned int  crc32;
+};
+
+/* Configuration descriptor encoding - see the doc for details */
+
+#define LASAT_W0_DSCTYPE(v)             (((v))         & 0xf)
+#define LASAT_W0_BMID(v)                (((v) >> 0x04) & 0xf)
+#define LASAT_W0_CPUTYPE(v)             (((v) >> 0x08) & 0xf)
+#define LASAT_W0_BUSSPEED(v)            (((v) >> 0x0c) & 0xf)
+#define LASAT_W0_CPUCLK(v)              (((v) >> 0x10) & 0xf)
+#define LASAT_W0_SDRAMBANKSZ(v)         (((v) >> 0x14) & 0xf)
+#define LASAT_W0_SDRAMBANKS(v)          (((v) >> 0x18) & 0xf)
+#define LASAT_W0_L2CACHE(v)             (((v) >> 0x1c) & 0xf)
+
+#define LASAT_W1_EDHAC(v)               (((v))         & 0xf)
+#define LASAT_W1_HIFN(v)                (((v) >> 0x04) & 0x1)
+#define LASAT_W1_ISDN(v)                (((v) >> 0x05) & 0x1)
+#define LASAT_W1_IDE(v)                 (((v) >> 0x06) & 0x1)
+#define LASAT_W1_HDLC(v)                (((v) >> 0x07) & 0x1)
+#define LASAT_W1_USVERSION(v)           (((v) >> 0x08) & 0x1)
+#define LASAT_W1_4MACS(v)               (((v) >> 0x09) & 0x1)
+#define LASAT_W1_EXTSERIAL(v)           (((v) >> 0x0a) & 0x1)
+#define LASAT_W1_FLASHSIZE(v)           (((v) >> 0x0c) & 0xf)
+#define LASAT_W1_PCISLOTS(v)            (((v) >> 0x10) & 0xf)
+#define LASAT_W1_PCI1OPT(v)             (((v) >> 0x14) & 0xf)
+#define LASAT_W1_PCI2OPT(v)             (((v) >> 0x18) & 0xf)
+#define LASAT_W1_PCI3OPT(v)             (((v) >> 0x1c) & 0xf)
+
+/* Routines specific to LASAT boards */
+
+#define LASAT_BMID_MASQUERADE2          0
+#define LASAT_BMID_MASQUERADEPRO        1
+#define LASAT_BMID_SAFEPIPE25           2
+#define LASAT_BMID_SAFEPIPE50           3
+#define LASAT_BMID_SAFEPIPE100          4
+#define LASAT_BMID_SAFEPIPE5000         5
+#define LASAT_BMID_SAFEPIPE7000         6
+#define LASAT_BMID_SAFEPIPE1000         7
+#if 0
+#define LASAT_BMID_SAFEPIPE30           7
+#define LASAT_BMID_SAFEPIPE5100         8
+#define LASAT_BMID_SAFEPIPE7100         9
+#endif
+#define LASAT_BMID_UNKNOWN              0xf
+#define LASAT_MAX_BMID_NAMES            9   /* no larger than 15! */
+
+#define LASAT_HAS_EDHAC                 (1 << 0)
+#define LASAT_EDHAC_FAST                (1 << 1)
+#define LASAT_HAS_EADI                  (1 << 2)
+#define LASAT_HAS_HIFN                  (1 << 3)
+#define LASAT_HAS_ISDN                  (1 << 4)
+#define LASAT_HAS_LEASEDLINE_IF         (1 << 5)
+#define LASAT_HAS_HDC                   (1 << 6)
+
+#define LASAT_PRID_MASQUERADE2          0
+#define LASAT_PRID_MASQUERADEPRO        1
+#define LASAT_PRID_SAFEPIPE25           2
+#define LASAT_PRID_SAFEPIPE50           3
+#define LASAT_PRID_SAFEPIPE100          4
+#define LASAT_PRID_SAFEPIPE5000         5
+#define LASAT_PRID_SAFEPIPE7000         6
+#define LASAT_PRID_SAFEPIPE30           7
+#define LASAT_PRID_SAFEPIPE5100         8
+#define LASAT_PRID_SAFEPIPE7100         9
+
+#define LASAT_PRID_SAFEPIPE1110         10
+#define LASAT_PRID_SAFEPIPE3020         11
+#define LASAT_PRID_SAFEPIPE3030         12
+#define LASAT_PRID_SAFEPIPE5020         13
+#define LASAT_PRID_SAFEPIPE5030         14
+#define LASAT_PRID_SAFEPIPE1120         15
+#define LASAT_PRID_SAFEPIPE1130         16
+#define LASAT_PRID_SAFEPIPE6010         17
+#define LASAT_PRID_SAFEPIPE6110         18
+#define LASAT_PRID_SAFEPIPE6210         19
+#define LASAT_PRID_SAFEPIPE1020         20
+#define LASAT_PRID_SAFEPIPE1040         21
+#define LASAT_PRID_SAFEPIPE1060         22
+
+struct lasat_info {
+        unsigned int  li_cpu_hz;
+        unsigned int  li_bus_hz;
+        unsigned int  li_bmid;
+        unsigned int  li_memsize;
+        unsigned int  li_flash_size;
+        unsigned int  li_prid;
+        unsigned char li_bmstr[16];
+        unsigned char li_namestr[32];
+        unsigned char li_typestr[16];
+        /* Info on the Flash layout */
+        unsigned int  li_flash_base;
+        unsigned long li_flashpart_base[LASAT_MTD_LAST];
+        unsigned long li_flashpart_size[LASAT_MTD_LAST];
+        struct lasat_eeprom_struct li_eeprom_info;
+        unsigned int  li_eeprom_upgrade_version;
+        unsigned int  li_debugaccess;
+};
+
+extern struct lasat_info lasat_board_info;
+
+static inline unsigned long lasat_flash_partition_start(int partno)
+{
+        if (partno < 0 || partno >= LASAT_MTD_LAST)
+                return 0;
+
+        return lasat_board_info.li_flashpart_base[partno];
+}
+
+static inline unsigned long lasat_flash_partition_size(int partno)
+{
+        if (partno < 0 || partno >= LASAT_MTD_LAST)
+                return 0;
+
+        return lasat_board_info.li_flashpart_size[partno];
+}
+
+/* Called from setup() to initialize the global board_info struct */
+extern int lasat_init_board_info(void);
+
+/* Write the modified EEPROM info struct */
+extern void lasat_write_eeprom_info(void);
+
+#define N_MACHTYPES             2
+/* for calibration of delays */
+
+/* the lasat_ndelay function is necessary because it is used at an
+ * early stage of the boot process where ndelay is not calibrated.
+ * It is used for the bit-banging rtc and eeprom drivers */
+
+#include <linux/delay.h>
+
+/* calculating with the slowest board with 100 MHz clock */
+#define LASAT_100_DIVIDER 20
+/* All 200's run at 250 MHz clock */
+#define LASAT_200_DIVIDER 8
+
+extern unsigned int lasat_ndelay_divider;
+
+static inline void lasat_ndelay(unsigned int ns)
+{
+        __delay(ns / lasat_ndelay_divider);
+}
+
+#define IS_LASAT_200()     (current_cpu_data.cputype == CPU_R5000)
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+#define LASAT_SERVICEMODE_MAGIC_1     0xdeadbeef
+#define LASAT_SERVICEMODE_MAGIC_2     0xfedeabba
+
+/* Lasat 100 boards */
+#define LASAT_GT_BASE           (KSEG1ADDR(0x14000000))
+
+/* Lasat 200 boards */
+#define Vrc5074_PHYS_BASE       0x1fa00000
+#define Vrc5074_BASE            (KSEG1ADDR(Vrc5074_PHYS_BASE))
+#define PCI_WINDOW1             0x1a000000
+
+#endif /* _LASAT_H */
diff --git a/arch/mips/include/asm/lasat/lasatint.h b/arch/mips/include/asm/lasat/lasatint.h
new file mode 100644
index 000000000000..e0d2458b43d0
--- /dev/null
+++ b/arch/mips/include/asm/lasat/lasatint.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_LASAT_LASATINT_H
+#define __ASM_LASAT_LASATINT_H
+
+/* lasat 100 */
+#define LASAT_INT_STATUS_REG_100        (KSEG1ADDR(0x1c880000))
+#define LASAT_INT_MASK_REG_100          (KSEG1ADDR(0x1c890000))
+#define LASATINT_MASK_SHIFT_100         0
+
+/* lasat 200 */
+#define LASAT_INT_STATUS_REG_200        (KSEG1ADDR(0x1104003c))
+#define LASAT_INT_MASK_REG_200          (KSEG1ADDR(0x1104003c))
+#define LASATINT_MASK_SHIFT_200         16
+
+#endif /* __ASM_LASAT_LASATINT_H */
diff --git a/arch/mips/include/asm/lasat/picvue.h b/arch/mips/include/asm/lasat/picvue.h
new file mode 100644
index 000000000000..42a492edc40e
--- /dev/null
+++ b/arch/mips/include/asm/lasat/picvue.h
@@ -0,0 +1,15 @@
+/* Lasat 100 */
+#define PVC_REG_100             KSEG1ADDR(0x1c820000)
+#define PVC_DATA_SHIFT_100      0
+#define PVC_DATA_M_100          0xFF
+#define PVC_E_100               (1 << 8)
+#define PVC_RW_100              (1 << 9)
+#define PVC_RS_100              (1 << 10)
+
+/* Lasat 200 */
+#define PVC_REG_200             KSEG1ADDR(0x11000000)
+#define PVC_DATA_SHIFT_200      24
+#define PVC_DATA_M_200          (0xFF << PVC_DATA_SHIFT_200)
+#define PVC_E_200               (1 << 16)
+#define PVC_RW_200              (1 << 17)
+#define PVC_RS_200              (1 << 18)
diff --git a/arch/mips/include/asm/lasat/serial.h b/arch/mips/include/asm/lasat/serial.h
new file mode 100644
index 000000000000..1c37d70579b8
--- /dev/null
+++ b/arch/mips/include/asm/lasat/serial.h
@@ -0,0 +1,13 @@
+#include <asm/lasat/lasat.h>
+
+/* Lasat 100 boards serial configuration */
+#define LASAT_BASE_BAUD_100             (7372800 / 16)
+#define LASAT_UART_REGS_BASE_100        0x1c8b0000
+#define LASAT_UART_REGS_SHIFT_100       2
+#define LASATINT_UART_100               16
+
+/* * LASAT 200 boards serial configuration */
+#define LASAT_BASE_BAUD_200             (100000000 / 16 / 12)
+#define LASAT_UART_REGS_BASE_200        (Vrc5074_PHYS_BASE + 0x0300)
+#define LASAT_UART_REGS_SHIFT_200       3
+#define LASATINT_UART_200               21
diff --git a/arch/mips/include/asm/linkage.h b/arch/mips/include/asm/linkage.h
new file mode 100644
index 000000000000..e9a940d1b0c6
--- /dev/null
+++ b/arch/mips/include/asm/linkage.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#ifdef __ASSEMBLY__
+#include <asm/asm.h>
+#endif
+
+#define __weak __attribute__((weak))
+
+#endif
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
new file mode 100644
index 000000000000..f96fd59e0845
--- /dev/null
+++ b/arch/mips/include/asm/local.h
@@ -0,0 +1,221 @@
+#ifndef _ARCH_MIPS_LOCAL_H
+#define _ARCH_MIPS_LOCAL_H
+
+#include <linux/percpu.h>
+#include <linux/bitops.h>
+#include <asm/atomic.h>
+#include <asm/cmpxchg.h>
+#include <asm/war.h>
+
+typedef struct
+{
+        atomic_long_t a;
+} local_t;
+
+#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
+
+#define local_read(l)   atomic_long_read(&(l)->a)
+#define local_set(l, i) atomic_long_set(&(l)->a, (i))
+
+#define local_add(i, l) atomic_long_add((i), (&(l)->a))
+#define local_sub(i, l) atomic_long_sub((i), (&(l)->a))
+#define local_inc(l)    atomic_long_inc(&(l)->a)
+#define local_dec(l)    atomic_long_dec(&(l)->a)
+
+/*
+ * Same as above, but return the result value
+ */
+static __inline__ long local_add_return(long i, local_t * l)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_add_return      \n"
+                "       addu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_add_return      \n"
+                "       addu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqz    %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                result = l->a.counter;
+                result += i;
+                l->a.counter = result;
+                local_irq_restore(flags);
+        }
+
+        return result;
+}
+
+static __inline__ long local_sub_return(long i, local_t * l)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_sub_return      \n"
+                "       subu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_sub_return      \n"
+                "       subu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqz    %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                result = l->a.counter;
+                result -= i;
+                l->a.counter = result;
+                local_irq_restore(flags);
+        }
+
+        return result;
+}
+
+#define local_cmpxchg(l, o, n) \
+        ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
+#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
+
+/**
+ * local_add_unless - add unless the number is a given value
+ * @l: pointer of type local_t
+ * @a: the amount to add to l...
+ * @u: ...unless l is equal to u.
+ *
+ * Atomically adds @a to @l, so long as it was not @u.
+ * Returns non-zero if @l was not @u, and zero otherwise.
+ */
+#define local_add_unless(l, a, u)                               \
+({                                                              \
+        long c, old;                                            \
+        c = local_read(l);                                      \
+        while (c != (u) && (old = local_cmpxchg((l), c, c + (a))) != c) \
+                c = old;                                        \
+        c != (u);                                               \
+})
+#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
+
+#define local_dec_return(l) local_sub_return(1, (l))
+#define local_inc_return(l) local_add_return(1, (l))
+
+/*
+ * local_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @l: pointer of type local_t
+ *
+ * Atomically subtracts @i from @l and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0)
+
+/*
+ * local_inc_and_test - increment and test
+ * @l: pointer of type local_t
+ *
+ * Atomically increments @l by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define local_inc_and_test(l) (local_inc_return(l) == 0)
+
+/*
+ * local_dec_and_test - decrement by 1 and test
+ * @l: pointer of type local_t
+ *
+ * Atomically decrements @l by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+#define local_dec_and_test(l) (local_sub_return(1, (l)) == 0)
+
+/*
+ * local_add_negative - add and test if negative
+ * @l: pointer of type local_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @l and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+#define local_add_negative(i, l) (local_add_return(i, (l)) < 0)
+
+/* Use these for per-cpu local_t variables: on some archs they are
+ * much more efficient than these naive implementations.  Note they take
+ * a variable, not an address.
+ */
+
+#define __local_inc(l)          ((l)->a.counter++)
+#define __local_dec(l)          ((l)->a.counter++)
+#define __local_add(i, l)       ((l)->a.counter+=(i))
+#define __local_sub(i, l)       ((l)->a.counter-=(i))
+
+/* Need to disable preemption for the cpu local counters otherwise we could
+   still access a variable of a previous CPU in a non atomic way. */
+#define cpu_local_wrap_v(l)             \
+        ({ local_t res__;               \
+           preempt_disable();           \
+           res__ = (l);                 \
+           preempt_enable();            \
+           res__; })
+#define cpu_local_wrap(l)               \
+        ({ preempt_disable();           \
+           l;                           \
+           preempt_enable(); })         \
+
+#define cpu_local_read(l)    cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
+#define cpu_local_set(l, i)  cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
+#define cpu_local_inc(l)     cpu_local_wrap(local_inc(&__get_cpu_var(l)))
+#define cpu_local_dec(l)     cpu_local_wrap(local_dec(&__get_cpu_var(l)))
+#define cpu_local_add(i, l)  cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
+#define cpu_local_sub(i, l)  cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
+
+#define __cpu_local_inc(l)      cpu_local_inc(l)
+#define __cpu_local_dec(l)      cpu_local_dec(l)
+#define __cpu_local_add(i, l)   cpu_local_add((i), (l))
+#define __cpu_local_sub(i, l)   cpu_local_sub((i), (l))
+
+#endif /* _ARCH_MIPS_LOCAL_H */
diff --git a/arch/mips/include/asm/m48t35.h b/arch/mips/include/asm/m48t35.h
new file mode 100644
index 000000000000..f44852e9a96d
--- /dev/null
+++ b/arch/mips/include/asm/m48t35.h
@@ -0,0 +1,27 @@
+/*
+ *  Registers for the SGS-Thomson M48T35 Timekeeper RAM chip
+ */
+#ifndef _ASM_M48T35_H
+#define _ASM_M48T35_H
+
+#include <linux/spinlock.h>
+
+extern spinlock_t rtc_lock;
+
+struct m48t35_rtc {
+        volatile u8     pad[0x7ff8];    /* starts at 0x7ff8 */
+        volatile u8     control;
+        volatile u8     sec;
+        volatile u8     min;
+        volatile u8     hour;
+        volatile u8     day;
+        volatile u8     date;
+        volatile u8     month;
+        volatile u8     year;
+};
+
+#define M48T35_RTC_SET          0x80
+#define M48T35_RTC_STOPPED      0x80
+#define M48T35_RTC_READ         0x40
+
+#endif /* _ASM_M48T35_H */
diff --git a/arch/mips/include/asm/m48t37.h b/arch/mips/include/asm/m48t37.h
new file mode 100644
index 000000000000..cabf86264f36
--- /dev/null
+++ b/arch/mips/include/asm/m48t37.h
@@ -0,0 +1,35 @@
+/*
+ *  Registers for the SGS-Thomson M48T37 Timekeeper RAM chip
+ */
+#ifndef _ASM_M48T37_H
+#define _ASM_M48T37_H
+
+#include <linux/spinlock.h>
+
+extern spinlock_t rtc_lock;
+
+struct m48t37_rtc {
+        volatile u8     pad[0x7ff0];    /* NVRAM */
+        volatile u8     flags;
+        volatile u8     century;
+        volatile u8     alarm_sec;
+        volatile u8     alarm_min;
+        volatile u8     alarm_hour;
+        volatile u8     alarm_data;
+        volatile u8     interrupts;
+        volatile u8     watchdog;
+        volatile u8     control;
+        volatile u8     sec;
+        volatile u8     min;
+        volatile u8     hour;
+        volatile u8     day;
+        volatile u8     date;
+        volatile u8     month;
+        volatile u8     year;
+};
+
+#define M48T37_RTC_SET          0x80
+#define M48T37_RTC_STOPPED      0x80
+#define M48T37_RTC_READ         0x40
+
+#endif /* _ASM_M48T37_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
new file mode 100644
index 000000000000..0d302bad4492
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -0,0 +1,1772 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Include file for Alchemy Semiconductor's Au1k CPU.
+ *
+ * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+ /*
+  * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
+  */
+
+#ifndef _AU1000_H_
+#define _AU1000_H_
+
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+#include <linux/delay.h>
+#include <linux/types.h>
+
+#include <linux/io.h>
+#include <linux/irq.h>
+
+/* cpu pipeline flush */
+void static inline au_sync(void)
+{
+        __asm__ volatile ("sync");
+}
+
+void static inline au_sync_udelay(int us)
+{
+        __asm__ volatile ("sync");
+        udelay(us);
+}
+
+void static inline au_sync_delay(int ms)
+{
+        __asm__ volatile ("sync");
+        mdelay(ms);
+}
+
+void static inline au_writeb(u8 val, unsigned long reg)
+{
+        *(volatile u8 *)reg = val;
+}
+
+void static inline au_writew(u16 val, unsigned long reg)
+{
+        *(volatile u16 *)reg = val;
+}
+
+void static inline au_writel(u32 val, unsigned long reg)
+{
+        *(volatile u32 *)reg = val;
+}
+
+static inline u8 au_readb(unsigned long reg)
+{
+        return *(volatile u8 *)reg;
+}
+
+static inline u16 au_readw(unsigned long reg)
+{
+        return *(volatile u16 *)reg;
+}
+
+static inline u32 au_readl(unsigned long reg)
+{
+        return *(volatile u32 *)reg;
+}
+
+
+/* arch/mips/au1000/common/clocks.c */
+extern void set_au1x00_speed(unsigned int new_freq);
+extern unsigned int get_au1x00_speed(void);
+extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
+extern unsigned long get_au1x00_uart_baud_base(void);
+extern void set_au1x00_lcd_clock(void);
+extern unsigned int get_au1x00_lcd_clock(void);
+
+/*
+ * Every board describes its IRQ mapping with this table.
+ */
+struct au1xxx_irqmap {
+        int     im_irq;
+        int     im_type;
+        int     im_request;
+};
+
+/*
+ * init_IRQ looks for a table with this name.
+ */
+extern struct au1xxx_irqmap au1xxx_irq_map[];
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+/*
+ * SDRAM register offsets
+ */
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
+    defined(CONFIG_SOC_AU1100)
+#define MEM_SDMODE0             0x0000
+#define MEM_SDMODE1             0x0004
+#define MEM_SDMODE2             0x0008
+#define MEM_SDADDR0             0x000C
+#define MEM_SDADDR1             0x0010
+#define MEM_SDADDR2             0x0014
+#define MEM_SDREFCFG            0x0018
+#define MEM_SDPRECMD            0x001C
+#define MEM_SDAUTOREF           0x0020
+#define MEM_SDWRMD0             0x0024
+#define MEM_SDWRMD1             0x0028
+#define MEM_SDWRMD2             0x002C
+#define MEM_SDSLEEP             0x0030
+#define MEM_SDSMCKE             0x0034
+
+/*
+ * MEM_SDMODE register content definitions
+ */
+#define MEM_SDMODE_F            (1 << 22)
+#define MEM_SDMODE_SR           (1 << 21)
+#define MEM_SDMODE_BS           (1 << 20)
+#define MEM_SDMODE_RS           (3 << 18)
+#define MEM_SDMODE_CS           (7 << 15)
+#define MEM_SDMODE_TRAS         (15 << 11)
+#define MEM_SDMODE_TMRD         (3 << 9)
+#define MEM_SDMODE_TWR          (3 << 7)
+#define MEM_SDMODE_TRP          (3 << 5)
+#define MEM_SDMODE_TRCD         (3 << 3)
+#define MEM_SDMODE_TCL          (7 << 0)
+
+#define MEM_SDMODE_BS_2Bank     (0 << 20)
+#define MEM_SDMODE_BS_4Bank     (1 << 20)
+#define MEM_SDMODE_RS_11Row     (0 << 18)
+#define MEM_SDMODE_RS_12Row     (1 << 18)
+#define MEM_SDMODE_RS_13Row     (2 << 18)
+#define MEM_SDMODE_RS_N(N)      ((N) << 18)
+#define MEM_SDMODE_CS_7Col      (0 << 15)
+#define MEM_SDMODE_CS_8Col      (1 << 15)
+#define MEM_SDMODE_CS_9Col      (2 << 15)
+#define MEM_SDMODE_CS_10Col     (3 << 15)
+#define MEM_SDMODE_CS_11Col     (4 << 15)
+#define MEM_SDMODE_CS_N(N)      ((N) << 15)
+#define MEM_SDMODE_TRAS_N(N)    ((N) << 11)
+#define MEM_SDMODE_TMRD_N(N)    ((N) << 9)
+#define MEM_SDMODE_TWR_N(N)     ((N) << 7)
+#define MEM_SDMODE_TRP_N(N)     ((N) << 5)
+#define MEM_SDMODE_TRCD_N(N)    ((N) << 3)
+#define MEM_SDMODE_TCL_N(N)     ((N) << 0)
+
+/*
+ * MEM_SDADDR register contents definitions
+ */
+#define MEM_SDADDR_E            (1 << 20)
+#define MEM_SDADDR_CSBA         (0x03FF << 10)
+#define MEM_SDADDR_CSMASK       (0x03FF << 0)
+#define MEM_SDADDR_CSBA_N(N)    ((N) & (0x03FF << 22) >> 12)
+#define MEM_SDADDR_CSMASK_N(N)  ((N)&(0x03FF << 22) >> 22)
+
+/*
+ * MEM_SDREFCFG register content definitions
+ */
+#define MEM_SDREFCFG_TRC        (15 << 28)
+#define MEM_SDREFCFG_TRPM       (3 << 26)
+#define MEM_SDREFCFG_E          (1 << 25)
+#define MEM_SDREFCFG_RE         (0x1ffffff << 0)
+#define MEM_SDREFCFG_TRC_N(N)   ((N) << MEM_SDREFCFG_TRC)
+#define MEM_SDREFCFG_TRPM_N(N)  ((N) << MEM_SDREFCFG_TRPM)
+#define MEM_SDREFCFG_REF_N(N)   (N)
+#endif
+
+/***********************************************************************/
+
+/*
+ * Au1550 SDRAM Register Offsets
+ */
+
+/***********************************************************************/
+
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+#define MEM_SDMODE0             0x0800
+#define MEM_SDMODE1             0x0808
+#define MEM_SDMODE2             0x0810
+#define MEM_SDADDR0             0x0820
+#define MEM_SDADDR1             0x0828
+#define MEM_SDADDR2             0x0830
+#define MEM_SDCONFIGA           0x0840
+#define MEM_SDCONFIGB           0x0848
+#define MEM_SDSTAT              0x0850
+#define MEM_SDERRADDR           0x0858
+#define MEM_SDSTRIDE0           0x0860
+#define MEM_SDSTRIDE1           0x0868
+#define MEM_SDSTRIDE2           0x0870
+#define MEM_SDWRMD0             0x0880
+#define MEM_SDWRMD1             0x0888
+#define MEM_SDWRMD2             0x0890
+#define MEM_SDPRECMD            0x08C0
+#define MEM_SDAUTOREF           0x08C8
+#define MEM_SDSREF              0x08D0
+#define MEM_SDSLEEP             MEM_SDSREF
+
+#endif
+
+/*
+ * Physical base addresses for integrated peripherals
+ */
+
+#ifdef CONFIG_SOC_AU1000
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define IRDA_PHYS_ADDR          0x10300000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MAC1_PHYS_ADDR          0x10510000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART2_PHYS_ADDR         0x11300000
+#define UART3_PHYS_ADDR         0x11400000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define SYS_PHYS_ADDR           0x11900000
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
+
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1500
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR           0x14005000
+#define MAC0_PHYS_ADDR          0x11500000
+#define MAC1_PHYS_ADDR          0x11510000
+#define MACEN_PHYS_ADDR         0x11520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define PCI_MEM_PHYS_ADDR       0x400000000ULL
+#define PCI_IO_PHYS_ADDR        0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR   0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
+
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1100
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define SD0_PHYS_ADDR           0x10600000
+#define SD1_PHYS_ADDR           0x10680000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define IRDA_PHYS_ADDR          0x10300000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART3_PHYS_ADDR         0x11400000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define LCD_PHYS_ADDR           0x15000000
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1550
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define USBH_PHYS_ADDR          0x14020000
+#define USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR           0x14005000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MAC1_PHYS_ADDR          0x10510000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define DDMA_PHYS_ADDR          0x14002000
+#define PE_PHYS_ADDR            0x14008000
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define PSC2_PHYS_ADDR          0x10A00000
+#define PSC3_PHYS_ADDR          0x10B00000
+#define PCI_MEM_PHYS_ADDR       0x400000000ULL
+#define PCI_IO_PHYS_ADDR        0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR   0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1200
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define AES_PHYS_ADDR           0x10300000
+#define CIM_PHYS_ADDR           0x14004000
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define USBM_PHYS_ADDR          0x14020000
+#define USBH_PHYS_ADDR          0x14020100
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define DDMA_PHYS_ADDR          0x14002000
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define SD0_PHYS_ADDR           0x10600000
+#define SD1_PHYS_ADDR           0x10680000
+#define LCD_PHYS_ADDR           0x15000000
+#define SWCNT_PHYS_ADDR         0x1110010C
+#define MAEFE_PHYS_ADDR         0x14012000
+#define MAEBE_PHYS_ADDR         0x14010000
+#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
+#endif
+
+/* Static Bus Controller */
+#define MEM_STCFG0              0xB4001000
+#define MEM_STTIME0             0xB4001004
+#define MEM_STADDR0             0xB4001008
+
+#define MEM_STCFG1              0xB4001010
+#define MEM_STTIME1             0xB4001014
+#define MEM_STADDR1             0xB4001018
+
+#define MEM_STCFG2              0xB4001020
+#define MEM_STTIME2             0xB4001024
+#define MEM_STADDR2             0xB4001028
+
+#define MEM_STCFG3              0xB4001030
+#define MEM_STTIME3             0xB4001034
+#define MEM_STADDR3             0xB4001038
+
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+#define MEM_STNDCTL             0xB4001100
+#define MEM_STSTAT              0xB4001104
+
+#define MEM_STNAND_CMD          0x0
+#define MEM_STNAND_ADDR         0x4
+#define MEM_STNAND_DATA         0x20
+#endif
+
+/* Interrupt Controller 0 */
+#define IC0_CFG0RD              0xB0400040
+#define IC0_CFG0SET             0xB0400040
+#define IC0_CFG0CLR             0xB0400044
+
+#define IC0_CFG1RD              0xB0400048
+#define IC0_CFG1SET             0xB0400048
+#define IC0_CFG1CLR             0xB040004C
+
+#define IC0_CFG2RD              0xB0400050
+#define IC0_CFG2SET             0xB0400050
+#define IC0_CFG2CLR             0xB0400054
+
+#define IC0_REQ0INT             0xB0400054
+#define IC0_SRCRD               0xB0400058
+#define IC0_SRCSET              0xB0400058
+#define IC0_SRCCLR              0xB040005C
+#define IC0_REQ1INT             0xB040005C
+
+#define IC0_ASSIGNRD            0xB0400060
+#define IC0_ASSIGNSET           0xB0400060
+#define IC0_ASSIGNCLR           0xB0400064
+
+#define IC0_WAKERD              0xB0400068
+#define IC0_WAKESET             0xB0400068
+#define IC0_WAKECLR             0xB040006C
+
+#define IC0_MASKRD              0xB0400070
+#define IC0_MASKSET             0xB0400070
+#define IC0_MASKCLR             0xB0400074
+
+#define IC0_RISINGRD            0xB0400078
+#define IC0_RISINGCLR           0xB0400078
+#define IC0_FALLINGRD           0xB040007C
+#define IC0_FALLINGCLR          0xB040007C
+
+#define IC0_TESTBIT             0xB0400080
+
+/* Interrupt Controller 1 */
+#define IC1_CFG0RD              0xB1800040
+#define IC1_CFG0SET             0xB1800040
+#define IC1_CFG0CLR             0xB1800044
+
+#define IC1_CFG1RD              0xB1800048
+#define IC1_CFG1SET             0xB1800048
+#define IC1_CFG1CLR             0xB180004C
+
+#define IC1_CFG2RD              0xB1800050
+#define IC1_CFG2SET             0xB1800050
+#define IC1_CFG2CLR             0xB1800054
+
+#define IC1_REQ0INT             0xB1800054
+#define IC1_SRCRD               0xB1800058
+#define IC1_SRCSET              0xB1800058
+#define IC1_SRCCLR              0xB180005C
+#define IC1_REQ1INT             0xB180005C
+
+#define IC1_ASSIGNRD            0xB1800060
+#define IC1_ASSIGNSET           0xB1800060
+#define IC1_ASSIGNCLR           0xB1800064
+
+#define IC1_WAKERD              0xB1800068
+#define IC1_WAKESET             0xB1800068
+#define IC1_WAKECLR             0xB180006C
+
+#define IC1_MASKRD              0xB1800070
+#define IC1_MASKSET             0xB1800070
+#define IC1_MASKCLR             0xB1800074
+
+#define IC1_RISINGRD            0xB1800078
+#define IC1_RISINGCLR           0xB1800078
+#define IC1_FALLINGRD           0xB180007C
+#define IC1_FALLINGCLR          0xB180007C
+
+#define IC1_TESTBIT             0xB1800080
+
+/* Interrupt Configuration Modes */
+#define INTC_INT_DISABLED               0x0
+#define INTC_INT_RISE_EDGE              0x1
+#define INTC_INT_FALL_EDGE              0x2
+#define INTC_INT_RISE_AND_FALL_EDGE     0x3
+#define INTC_INT_HIGH_LEVEL             0x5
+#define INTC_INT_LOW_LEVEL              0x6
+#define INTC_INT_HIGH_AND_LOW_LEVEL     0x7
+
+/* Interrupt Numbers */
+/* Au1000 */
+#ifdef CONFIG_SOC_AU1000
+enum soc_au1000_ints {
+        AU1000_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
+        AU1000_UART0_INT        = AU1000_FIRST_INT,
+        AU1000_UART1_INT,                               /* au1000 */
+        AU1000_UART2_INT,                               /* au1000 */
+        AU1000_UART3_INT,
+        AU1000_SSI0_INT,                                /* au1000 */
+        AU1000_SSI1_INT,                                /* au1000 */
+        AU1000_DMA_INT_BASE,
+
+        AU1000_TOY_INT          = AU1000_FIRST_INT + 14,
+        AU1000_TOY_MATCH0_INT,
+        AU1000_TOY_MATCH1_INT,
+        AU1000_TOY_MATCH2_INT,
+        AU1000_RTC_INT,
+        AU1000_RTC_MATCH0_INT,
+        AU1000_RTC_MATCH1_INT,
+        AU1000_RTC_MATCH2_INT,
+        AU1000_IRDA_TX_INT,                             /* au1000 */
+        AU1000_IRDA_RX_INT,                             /* au1000 */
+        AU1000_USB_DEV_REQ_INT,
+        AU1000_USB_DEV_SUS_INT,
+        AU1000_USB_HOST_INT,
+        AU1000_ACSYNC_INT,
+        AU1000_MAC0_DMA_INT,
+        AU1000_MAC1_DMA_INT,
+        AU1000_I2S_UO_INT,                              /* au1000 */
+        AU1000_AC97C_INT,
+        AU1000_GPIO_0,
+        AU1000_GPIO_1,
+        AU1000_GPIO_2,
+        AU1000_GPIO_3,
+        AU1000_GPIO_4,
+        AU1000_GPIO_5,
+        AU1000_GPIO_6,
+        AU1000_GPIO_7,
+        AU1000_GPIO_8,
+        AU1000_GPIO_9,
+        AU1000_GPIO_10,
+        AU1000_GPIO_11,
+        AU1000_GPIO_12,
+        AU1000_GPIO_13,
+        AU1000_GPIO_14,
+        AU1000_GPIO_15,
+        AU1000_GPIO_16,
+        AU1000_GPIO_17,
+        AU1000_GPIO_18,
+        AU1000_GPIO_19,
+        AU1000_GPIO_20,
+        AU1000_GPIO_21,
+        AU1000_GPIO_22,
+        AU1000_GPIO_23,
+        AU1000_GPIO_24,
+        AU1000_GPIO_25,
+        AU1000_GPIO_26,
+        AU1000_GPIO_27,
+        AU1000_GPIO_28,
+        AU1000_GPIO_29,
+        AU1000_GPIO_30,
+        AU1000_GPIO_31,
+};
+
+#define UART0_ADDR              0xB1100000
+#define UART1_ADDR              0xB1200000
+#define UART2_ADDR              0xB1300000
+#define UART3_ADDR              0xB1400000
+
+#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
+#define USB_HOST_CONFIG         0xB017FFFC
+
+#define AU1000_ETH0_BASE        0xB0500000
+#define AU1000_ETH1_BASE        0xB0510000
+#define AU1000_MAC0_ENABLE      0xB0520000
+#define AU1000_MAC1_ENABLE      0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif /* CONFIG_SOC_AU1000 */
+
+/* Au1500 */
+#ifdef CONFIG_SOC_AU1500
+enum soc_au1500_ints {
+        AU1500_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
+        AU1500_UART0_INT        = AU1500_FIRST_INT,
+        AU1000_PCI_INTA,                                /* au1500 */
+        AU1000_PCI_INTB,                                /* au1500 */
+        AU1500_UART3_INT,
+        AU1000_PCI_INTC,                                /* au1500 */
+        AU1000_PCI_INTD,                                /* au1500 */
+        AU1000_DMA_INT_BASE,
+
+        AU1000_TOY_INT          = AU1500_FIRST_INT + 14,
+        AU1000_TOY_MATCH0_INT,
+        AU1000_TOY_MATCH1_INT,
+        AU1000_TOY_MATCH2_INT,
+        AU1000_RTC_INT,
+        AU1000_RTC_MATCH0_INT,
+        AU1000_RTC_MATCH1_INT,
+        AU1000_RTC_MATCH2_INT,
+        AU1500_PCI_ERR_INT,
+        AU1500_RESERVED_INT,
+        AU1000_USB_DEV_REQ_INT,
+        AU1000_USB_DEV_SUS_INT,
+        AU1000_USB_HOST_INT,
+        AU1000_ACSYNC_INT,
+        AU1500_MAC0_DMA_INT,
+        AU1500_MAC1_DMA_INT,
+        AU1000_AC97C_INT        = AU1500_FIRST_INT + 31,
+        AU1000_GPIO_0,
+        AU1000_GPIO_1,
+        AU1000_GPIO_2,
+        AU1000_GPIO_3,
+        AU1000_GPIO_4,
+        AU1000_GPIO_5,
+        AU1000_GPIO_6,
+        AU1000_GPIO_7,
+        AU1000_GPIO_8,
+        AU1000_GPIO_9,
+        AU1000_GPIO_10,
+        AU1000_GPIO_11,
+        AU1000_GPIO_12,
+        AU1000_GPIO_13,
+        AU1000_GPIO_14,
+        AU1000_GPIO_15,
+        AU1500_GPIO_200,
+        AU1500_GPIO_201,
+        AU1500_GPIO_202,
+        AU1500_GPIO_203,
+        AU1500_GPIO_20,
+        AU1500_GPIO_204,
+        AU1500_GPIO_205,
+        AU1500_GPIO_23,
+        AU1500_GPIO_24,
+        AU1500_GPIO_25,
+        AU1500_GPIO_26,
+        AU1500_GPIO_27,
+        AU1500_GPIO_28,
+        AU1500_GPIO_206,
+        AU1500_GPIO_207,
+        AU1500_GPIO_208_215,
+};
+
+/* shortcuts */
+#define INTA AU1000_PCI_INTA
+#define INTB AU1000_PCI_INTB
+#define INTC AU1000_PCI_INTC
+#define INTD AU1000_PCI_INTD
+
+#define UART0_ADDR              0xB1100000
+#define UART3_ADDR              0xB1400000
+
+#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
+#define USB_HOST_CONFIG         0xB017fffc
+
+#define AU1500_ETH0_BASE        0xB1500000
+#define AU1500_ETH1_BASE        0xB1510000
+#define AU1500_MAC0_ENABLE      0xB1520000
+#define AU1500_MAC1_ENABLE      0xB1520004
+#define NUM_ETH_INTERFACES 2
+#endif /* CONFIG_SOC_AU1500 */
+
+/* Au1100 */
+#ifdef CONFIG_SOC_AU1100
+enum soc_au1100_ints {
+        AU1100_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
+        AU1100_UART0_INT,
+        AU1100_UART1_INT,
+        AU1100_SD_INT,
+        AU1100_UART3_INT,
+        AU1000_SSI0_INT,
+        AU1000_SSI1_INT,
+        AU1000_DMA_INT_BASE,
+
+        AU1000_TOY_INT          = AU1100_FIRST_INT + 14,
+        AU1000_TOY_MATCH0_INT,
+        AU1000_TOY_MATCH1_INT,
+        AU1000_TOY_MATCH2_INT,
+        AU1000_RTC_INT,
+        AU1000_RTC_MATCH0_INT,
+        AU1000_RTC_MATCH1_INT,
+        AU1000_RTC_MATCH2_INT,
+        AU1000_IRDA_TX_INT,
+        AU1000_IRDA_RX_INT,
+        AU1000_USB_DEV_REQ_INT,
+        AU1000_USB_DEV_SUS_INT,
+        AU1000_USB_HOST_INT,
+        AU1000_ACSYNC_INT,
+        AU1100_MAC0_DMA_INT,
+        AU1100_GPIO_208_215,
+        AU1100_LCD_INT,
+        AU1000_AC97C_INT,
+        AU1000_GPIO_0,
+        AU1000_GPIO_1,
+        AU1000_GPIO_2,
+        AU1000_GPIO_3,
+        AU1000_GPIO_4,
+        AU1000_GPIO_5,
+        AU1000_GPIO_6,
+        AU1000_GPIO_7,
+        AU1000_GPIO_8,
+        AU1000_GPIO_9,
+        AU1000_GPIO_10,
+        AU1000_GPIO_11,
+        AU1000_GPIO_12,
+        AU1000_GPIO_13,
+        AU1000_GPIO_14,
+        AU1000_GPIO_15,
+        AU1000_GPIO_16,
+        AU1000_GPIO_17,
+        AU1000_GPIO_18,
+        AU1000_GPIO_19,
+        AU1000_GPIO_20,
+        AU1000_GPIO_21,
+        AU1000_GPIO_22,
+        AU1000_GPIO_23,
+        AU1000_GPIO_24,
+        AU1000_GPIO_25,
+        AU1000_GPIO_26,
+        AU1000_GPIO_27,
+        AU1000_GPIO_28,
+        AU1000_GPIO_29,
+        AU1000_GPIO_30,
+        AU1000_GPIO_31,
+};
+
+#define UART0_ADDR              0xB1100000
+#define UART1_ADDR              0xB1200000
+#define UART3_ADDR              0xB1400000
+
+#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
+#define USB_HOST_CONFIG         0xB017FFFC
+
+#define AU1100_ETH0_BASE        0xB0500000
+#define AU1100_MAC0_ENABLE      0xB0520000
+#define NUM_ETH_INTERFACES 1
+#endif /* CONFIG_SOC_AU1100 */
+
+#ifdef CONFIG_SOC_AU1550
+enum soc_au1550_ints {
+        AU1550_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
+        AU1550_UART0_INT        = AU1550_FIRST_INT,
+        AU1550_PCI_INTA,
+        AU1550_PCI_INTB,
+        AU1550_DDMA_INT,
+        AU1550_CRYPTO_INT,
+        AU1550_PCI_INTC,
+        AU1550_PCI_INTD,
+        AU1550_PCI_RST_INT,
+        AU1550_UART1_INT,
+        AU1550_UART3_INT,
+        AU1550_PSC0_INT,
+        AU1550_PSC1_INT,
+        AU1550_PSC2_INT,
+        AU1550_PSC3_INT,
+        AU1000_TOY_INT,
+        AU1000_TOY_MATCH0_INT,
+        AU1000_TOY_MATCH1_INT,
+        AU1000_TOY_MATCH2_INT,
+        AU1000_RTC_INT,
+        AU1000_RTC_MATCH0_INT,
+        AU1000_RTC_MATCH1_INT,
+        AU1000_RTC_MATCH2_INT,
+
+        AU1550_NAND_INT                 = AU1550_FIRST_INT + 23,
+        AU1550_USB_DEV_REQ_INT,
+        AU1000_USB_DEV_REQ_INT          = AU1550_USB_DEV_REQ_INT,
+        AU1550_USB_DEV_SUS_INT,
+        AU1000_USB_DEV_SUS_INT          = AU1550_USB_DEV_SUS_INT,
+        AU1550_USB_HOST_INT,
+        AU1000_USB_HOST_INT             = AU1550_USB_HOST_INT,
+        AU1550_MAC0_DMA_INT,
+        AU1550_MAC1_DMA_INT,
+        AU1000_GPIO_0                   = AU1550_FIRST_INT + 32,
+        AU1000_GPIO_1,
+        AU1000_GPIO_2,
+        AU1000_GPIO_3,
+        AU1000_GPIO_4,
+        AU1000_GPIO_5,
+        AU1000_GPIO_6,
+        AU1000_GPIO_7,
+        AU1000_GPIO_8,
+        AU1000_GPIO_9,
+        AU1000_GPIO_10,
+        AU1000_GPIO_11,
+        AU1000_GPIO_12,
+        AU1000_GPIO_13,
+        AU1000_GPIO_14,
+        AU1000_GPIO_15,
+        AU1550_GPIO_200,
+        AU1500_GPIO_201_205,                    /* Logical or of GPIO201:205 */
+        AU1500_GPIO_16,
+        AU1500_GPIO_17,
+        AU1500_GPIO_20,
+        AU1500_GPIO_21,
+        AU1500_GPIO_22,
+        AU1500_GPIO_23,
+        AU1500_GPIO_24,
+        AU1500_GPIO_25,
+        AU1500_GPIO_26,
+        AU1500_GPIO_27,
+        AU1500_GPIO_28,
+        AU1500_GPIO_206,
+        AU1500_GPIO_207,
+        AU1500_GPIO_208_218,                    /* Logical or of GPIO208:218 */
+};
+
+/* shortcuts */
+#define INTA AU1550_PCI_INTA
+#define INTB AU1550_PCI_INTB
+#define INTC AU1550_PCI_INTC
+#define INTD AU1550_PCI_INTD
+
+#define UART0_ADDR              0xB1100000
+#define UART1_ADDR              0xB1200000
+#define UART3_ADDR              0xB1400000
+
+#define USB_OHCI_BASE           0x14020000      /* phys addr for ioremap */
+#define USB_OHCI_LEN            0x00060000
+#define USB_HOST_CONFIG         0xB4027ffc
+
+#define AU1550_ETH0_BASE        0xB0500000
+#define AU1550_ETH1_BASE        0xB0510000
+#define AU1550_MAC0_ENABLE      0xB0520000
+#define AU1550_MAC1_ENABLE      0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif /* CONFIG_SOC_AU1550 */
+
+#ifdef CONFIG_SOC_AU1200
+enum soc_au1200_ints {
+        AU1200_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
+        AU1200_UART0_INT        = AU1200_FIRST_INT,
+        AU1200_SWT_INT,
+        AU1200_SD_INT,
+        AU1200_DDMA_INT,
+        AU1200_MAE_BE_INT,
+        AU1200_GPIO_200,
+        AU1200_GPIO_201,
+        AU1200_GPIO_202,
+        AU1200_UART1_INT,
+        AU1200_MAE_FE_INT,
+        AU1200_PSC0_INT,
+        AU1200_PSC1_INT,
+        AU1200_AES_INT,
+        AU1200_CAMERA_INT,
+        AU1000_TOY_INT,
+        AU1000_TOY_MATCH0_INT,
+        AU1000_TOY_MATCH1_INT,
+        AU1000_TOY_MATCH2_INT,
+        AU1000_RTC_INT,
+        AU1000_RTC_MATCH0_INT,
+        AU1000_RTC_MATCH1_INT,
+        AU1000_RTC_MATCH2_INT,
+
+        AU1200_NAND_INT         = AU1200_FIRST_INT + 23,
+        AU1200_GPIO_204,
+        AU1200_GPIO_205,
+        AU1200_GPIO_206,
+        AU1200_GPIO_207,
+        AU1200_GPIO_208_215,                    /* Logical OR of 208:215 */
+        AU1200_USB_INT,
+        AU1000_USB_HOST_INT     = AU1200_USB_INT,
+        AU1200_LCD_INT,
+        AU1200_MAE_BOTH_INT,
+        AU1000_GPIO_0,
+        AU1000_GPIO_1,
+        AU1000_GPIO_2,
+        AU1000_GPIO_3,
+        AU1000_GPIO_4,
+        AU1000_GPIO_5,
+        AU1000_GPIO_6,
+        AU1000_GPIO_7,
+        AU1000_GPIO_8,
+        AU1000_GPIO_9,
+        AU1000_GPIO_10,
+        AU1000_GPIO_11,
+        AU1000_GPIO_12,
+        AU1000_GPIO_13,
+        AU1000_GPIO_14,
+        AU1000_GPIO_15,
+        AU1000_GPIO_16,
+        AU1000_GPIO_17,
+        AU1000_GPIO_18,
+        AU1000_GPIO_19,
+        AU1000_GPIO_20,
+        AU1000_GPIO_21,
+        AU1000_GPIO_22,
+        AU1000_GPIO_23,
+        AU1000_GPIO_24,
+        AU1000_GPIO_25,
+        AU1000_GPIO_26,
+        AU1000_GPIO_27,
+        AU1000_GPIO_28,
+        AU1000_GPIO_29,
+        AU1000_GPIO_30,
+        AU1000_GPIO_31,
+};
+
+#define UART0_ADDR              0xB1100000
+#define UART1_ADDR              0xB1200000
+
+#define USB_UOC_BASE            0x14020020
+#define USB_UOC_LEN             0x20
+#define USB_OHCI_BASE           0x14020100
+#define USB_OHCI_LEN            0x100
+#define USB_EHCI_BASE           0x14020200
+#define USB_EHCI_LEN            0x100
+#define USB_UDC_BASE            0x14022000
+#define USB_UDC_LEN             0x2000
+#define USB_MSR_BASE            0xB4020000
+#define USB_MSR_MCFG            4
+#define USBMSRMCFG_OMEMEN       0
+#define USBMSRMCFG_OBMEN        1
+#define USBMSRMCFG_EMEMEN       2
+#define USBMSRMCFG_EBMEN        3
+#define USBMSRMCFG_DMEMEN       4
+#define USBMSRMCFG_DBMEN        5
+#define USBMSRMCFG_GMEMEN       6
+#define USBMSRMCFG_OHCCLKEN     16
+#define USBMSRMCFG_EHCCLKEN     17
+#define USBMSRMCFG_UDCCLKEN     18
+#define USBMSRMCFG_PHYPLLEN     19
+#define USBMSRMCFG_RDCOMB       30
+#define USBMSRMCFG_PFEN         31
+
+#endif /* CONFIG_SOC_AU1200 */
+
+#define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
+#define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
+#define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_BASE + 32)
+#define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
+
+#define AU1000_MAX_INTR         AU1000_INTC1_INT_LAST
+#define INTX                    0xFF                    /* not valid */
+
+/* Programmable Counters 0 and 1 */
+#define SYS_BASE                0xB1900000
+#define SYS_COUNTER_CNTRL       (SYS_BASE + 0x14)
+#  define SYS_CNTRL_E1S         (1 << 23)
+#  define SYS_CNTRL_T1S         (1 << 20)
+#  define SYS_CNTRL_M21         (1 << 19)
+#  define SYS_CNTRL_M11         (1 << 18)
+#  define SYS_CNTRL_M01         (1 << 17)
+#  define SYS_CNTRL_C1S         (1 << 16)
+#  define SYS_CNTRL_BP          (1 << 14)
+#  define SYS_CNTRL_EN1         (1 << 13)
+#  define SYS_CNTRL_BT1         (1 << 12)
+#  define SYS_CNTRL_EN0         (1 << 11)
+#  define SYS_CNTRL_BT0         (1 << 10)
+#  define SYS_CNTRL_E0          (1 << 8)
+#  define SYS_CNTRL_E0S         (1 << 7)
+#  define SYS_CNTRL_32S         (1 << 5)
+#  define SYS_CNTRL_T0S         (1 << 4)
+#  define SYS_CNTRL_M20         (1 << 3)
+#  define SYS_CNTRL_M10         (1 << 2)
+#  define SYS_CNTRL_M00         (1 << 1)
+#  define SYS_CNTRL_C0S         (1 << 0)
+
+/* Programmable Counter 0 Registers */
+#define SYS_TOYTRIM             (SYS_BASE + 0)
+#define SYS_TOYWRITE            (SYS_BASE + 4)
+#define SYS_TOYMATCH0           (SYS_BASE + 8)
+#define SYS_TOYMATCH1           (SYS_BASE + 0xC)
+#define SYS_TOYMATCH2           (SYS_BASE + 0x10)
+#define SYS_TOYREAD             (SYS_BASE + 0x40)
+
+/* Programmable Counter 1 Registers */
+#define SYS_RTCTRIM             (SYS_BASE + 0x44)
+#define SYS_RTCWRITE            (SYS_BASE + 0x48)
+#define SYS_RTCMATCH0           (SYS_BASE + 0x4C)
+#define SYS_RTCMATCH1           (SYS_BASE + 0x50)
+#define SYS_RTCMATCH2           (SYS_BASE + 0x54)
+#define SYS_RTCREAD             (SYS_BASE + 0x58)
+
+/* I2S Controller */
+#define I2S_DATA                0xB1000000
+#  define I2S_DATA_MASK         0xffffff
+#define I2S_CONFIG              0xB1000004
+#  define I2S_CONFIG_XU         (1 << 25)
+#  define I2S_CONFIG_XO         (1 << 24)
+#  define I2S_CONFIG_RU         (1 << 23)
+#  define I2S_CONFIG_RO         (1 << 22)
+#  define I2S_CONFIG_TR         (1 << 21)
+#  define I2S_CONFIG_TE         (1 << 20)
+#  define I2S_CONFIG_TF         (1 << 19)
+#  define I2S_CONFIG_RR         (1 << 18)
+#  define I2S_CONFIG_RE         (1 << 17)
+#  define I2S_CONFIG_RF         (1 << 16)
+#  define I2S_CONFIG_PD         (1 << 11)
+#  define I2S_CONFIG_LB         (1 << 10)
+#  define I2S_CONFIG_IC         (1 << 9)
+#  define I2S_CONFIG_FM_BIT     7
+#  define I2S_CONFIG_FM_MASK    (0x3 << I2S_CONFIG_FM_BIT)
+#    define I2S_CONFIG_FM_I2S   (0x0 << I2S_CONFIG_FM_BIT)
+#    define I2S_CONFIG_FM_LJ    (0x1 << I2S_CONFIG_FM_BIT)
+#    define I2S_CONFIG_FM_RJ    (0x2 << I2S_CONFIG_FM_BIT)
+#  define I2S_CONFIG_TN         (1 << 6)
+#  define I2S_CONFIG_RN         (1 << 5)
+#  define I2S_CONFIG_SZ_BIT     0
+#  define I2S_CONFIG_SZ_MASK    (0x1F << I2S_CONFIG_SZ_BIT)
+
+#define I2S_CONTROL             0xB1000008
+#  define I2S_CONTROL_D         (1 << 1)
+#  define I2S_CONTROL_CE        (1 << 0)
+
+/* USB Host Controller */
+#ifndef USB_OHCI_LEN
+#define USB_OHCI_LEN            0x00100000
+#endif
+
+#ifndef CONFIG_SOC_AU1200
+
+/* USB Device Controller */
+#define USBD_EP0RD              0xB0200000
+#define USBD_EP0WR              0xB0200004
+#define USBD_EP2WR              0xB0200008
+#define USBD_EP3WR              0xB020000C
+#define USBD_EP4RD              0xB0200010
+#define USBD_EP5RD              0xB0200014
+#define USBD_INTEN              0xB0200018
+#define USBD_INTSTAT            0xB020001C
+#  define USBDEV_INT_SOF        (1 << 12)
+#  define USBDEV_INT_HF_BIT     6
+#  define USBDEV_INT_HF_MASK    (0x3f << USBDEV_INT_HF_BIT)
+#  define USBDEV_INT_CMPLT_BIT  0
+#  define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
+#define USBD_CONFIG             0xB0200020
+#define USBD_EP0CS              0xB0200024
+#define USBD_EP2CS              0xB0200028
+#define USBD_EP3CS              0xB020002C
+#define USBD_EP4CS              0xB0200030
+#define USBD_EP5CS              0xB0200034
+#  define USBDEV_CS_SU          (1 << 14)
+#  define USBDEV_CS_NAK         (1 << 13)
+#  define USBDEV_CS_ACK         (1 << 12)
+#  define USBDEV_CS_BUSY        (1 << 11)
+#  define USBDEV_CS_TSIZE_BIT   1
+#  define USBDEV_CS_TSIZE_MASK  (0x3ff << USBDEV_CS_TSIZE_BIT)
+#  define USBDEV_CS_STALL       (1 << 0)
+#define USBD_EP0RDSTAT          0xB0200040
+#define USBD_EP0WRSTAT          0xB0200044
+#define USBD_EP2WRSTAT          0xB0200048
+#define USBD_EP3WRSTAT          0xB020004C
+#define USBD_EP4RDSTAT          0xB0200050
+#define USBD_EP5RDSTAT          0xB0200054
+#  define USBDEV_FSTAT_FLUSH    (1 << 6)
+#  define USBDEV_FSTAT_UF       (1 << 5)
+#  define USBDEV_FSTAT_OF       (1 << 4)
+#  define USBDEV_FSTAT_FCNT_BIT 0
+#  define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
+#define USBD_ENABLE             0xB0200058
+#  define USBDEV_ENABLE         (1 << 1)
+#  define USBDEV_CE             (1 << 0)
+
+#endif /* !CONFIG_SOC_AU1200 */
+
+/* Ethernet Controllers  */
+
+/* 4 byte offsets from AU1000_ETH_BASE */
+#define MAC_CONTROL             0x0
+#  define MAC_RX_ENABLE         (1 << 2)
+#  define MAC_TX_ENABLE         (1 << 3)
+#  define MAC_DEF_CHECK         (1 << 5)
+#  define MAC_SET_BL(X)         (((X) & 0x3) << 6)
+#  define MAC_AUTO_PAD          (1 << 8)
+#  define MAC_DISABLE_RETRY     (1 << 10)
+#  define MAC_DISABLE_BCAST     (1 << 11)
+#  define MAC_LATE_COL          (1 << 12)
+#  define MAC_HASH_MODE         (1 << 13)
+#  define MAC_HASH_ONLY         (1 << 15)
+#  define MAC_PASS_ALL          (1 << 16)
+#  define MAC_INVERSE_FILTER    (1 << 17)
+#  define MAC_PROMISCUOUS       (1 << 18)
+#  define MAC_PASS_ALL_MULTI    (1 << 19)
+#  define MAC_FULL_DUPLEX       (1 << 20)
+#  define MAC_NORMAL_MODE       0
+#  define MAC_INT_LOOPBACK      (1 << 21)
+#  define MAC_EXT_LOOPBACK      (1 << 22)
+#  define MAC_DISABLE_RX_OWN    (1 << 23)
+#  define MAC_BIG_ENDIAN        (1 << 30)
+#  define MAC_RX_ALL            (1 << 31)
+#define MAC_ADDRESS_HIGH        0x4
+#define MAC_ADDRESS_LOW         0x8
+#define MAC_MCAST_HIGH          0xC
+#define MAC_MCAST_LOW           0x10
+#define MAC_MII_CNTRL           0x14
+#  define MAC_MII_BUSY          (1 << 0)
+#  define MAC_MII_READ          0
+#  define MAC_MII_WRITE         (1 << 1)
+#  define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
+#  define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
+#define MAC_MII_DATA            0x18
+#define MAC_FLOW_CNTRL          0x1C
+#  define MAC_FLOW_CNTRL_BUSY   (1 << 0)
+#  define MAC_FLOW_CNTRL_ENABLE (1 << 1)
+#  define MAC_PASS_CONTROL      (1 << 2)
+#  define MAC_SET_PAUSE(X)      (((X) & 0xffff) << 16)
+#define MAC_VLAN1_TAG           0x20
+#define MAC_VLAN2_TAG           0x24
+
+/* Ethernet Controller Enable */
+
+#  define MAC_EN_CLOCK_ENABLE   (1 << 0)
+#  define MAC_EN_RESET0         (1 << 1)
+#  define MAC_EN_TOSS           (0 << 2)
+#  define MAC_EN_CACHEABLE      (1 << 3)
+#  define MAC_EN_RESET1         (1 << 4)
+#  define MAC_EN_RESET2         (1 << 5)
+#  define MAC_DMA_RESET         (1 << 6)
+
+/* Ethernet Controller DMA Channels */
+
+#define MAC0_TX_DMA_ADDR        0xB4004000
+#define MAC1_TX_DMA_ADDR        0xB4004200
+/* offsets from MAC_TX_RING_ADDR address */
+#define MAC_TX_BUFF0_STATUS     0x0
+#  define TX_FRAME_ABORTED      (1 << 0)
+#  define TX_JAB_TIMEOUT        (1 << 1)
+#  define TX_NO_CARRIER         (1 << 2)
+#  define TX_LOSS_CARRIER       (1 << 3)
+#  define TX_EXC_DEF            (1 << 4)
+#  define TX_LATE_COLL_ABORT    (1 << 5)
+#  define TX_EXC_COLL           (1 << 6)
+#  define TX_UNDERRUN           (1 << 7)
+#  define TX_DEFERRED           (1 << 8)
+#  define TX_LATE_COLL          (1 << 9)
+#  define TX_COLL_CNT_MASK      (0xF << 10)
+#  define TX_PKT_RETRY          (1 << 31)
+#define MAC_TX_BUFF0_ADDR       0x4
+#  define TX_DMA_ENABLE         (1 << 0)
+#  define TX_T_DONE             (1 << 1)
+#  define TX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
+#define MAC_TX_BUFF0_LEN        0x8
+#define MAC_TX_BUFF1_STATUS     0x10
+#define MAC_TX_BUFF1_ADDR       0x14
+#define MAC_TX_BUFF1_LEN        0x18
+#define MAC_TX_BUFF2_STATUS     0x20
+#define MAC_TX_BUFF2_ADDR       0x24
+#define MAC_TX_BUFF2_LEN        0x28
+#define MAC_TX_BUFF3_STATUS     0x30
+#define MAC_TX_BUFF3_ADDR       0x34
+#define MAC_TX_BUFF3_LEN        0x38
+
+#define MAC0_RX_DMA_ADDR        0xB4004100
+#define MAC1_RX_DMA_ADDR        0xB4004300
+/* offsets from MAC_RX_RING_ADDR */
+#define MAC_RX_BUFF0_STATUS     0x0
+#  define RX_FRAME_LEN_MASK     0x3fff
+#  define RX_WDOG_TIMER         (1 << 14)
+#  define RX_RUNT               (1 << 15)
+#  define RX_OVERLEN            (1 << 16)
+#  define RX_COLL               (1 << 17)
+#  define RX_ETHER              (1 << 18)
+#  define RX_MII_ERROR          (1 << 19)
+#  define RX_DRIBBLING          (1 << 20)
+#  define RX_CRC_ERROR          (1 << 21)
+#  define RX_VLAN1              (1 << 22)
+#  define RX_VLAN2              (1 << 23)
+#  define RX_LEN_ERROR          (1 << 24)
+#  define RX_CNTRL_FRAME        (1 << 25)
+#  define RX_U_CNTRL_FRAME      (1 << 26)
+#  define RX_MCAST_FRAME        (1 << 27)
+#  define RX_BCAST_FRAME        (1 << 28)
+#  define RX_FILTER_FAIL        (1 << 29)
+#  define RX_PACKET_FILTER      (1 << 30)
+#  define RX_MISSED_FRAME       (1 << 31)
+
+#  define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
+                    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
+                    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
+#define MAC_RX_BUFF0_ADDR       0x4
+#  define RX_DMA_ENABLE         (1 << 0)
+#  define RX_T_DONE             (1 << 1)
+#  define RX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
+#  define RX_SET_BUFF_ADDR(X)   ((X) & 0xffffffc0)
+#define MAC_RX_BUFF1_STATUS     0x10
+#define MAC_RX_BUFF1_ADDR       0x14
+#define MAC_RX_BUFF2_STATUS     0x20
+#define MAC_RX_BUFF2_ADDR       0x24
+#define MAC_RX_BUFF3_STATUS     0x30
+#define MAC_RX_BUFF3_ADDR       0x34
+
+/* UARTS 0-3 */
+#define UART_BASE               UART0_ADDR
+#ifdef  CONFIG_SOC_AU1200
+#define UART_DEBUG_BASE         UART1_ADDR
+#else
+#define UART_DEBUG_BASE         UART3_ADDR
+#endif
+
+#define UART_RX         0       /* Receive buffer */
+#define UART_TX         4       /* Transmit buffer */
+#define UART_IER        8       /* Interrupt Enable Register */
+#define UART_IIR        0xC     /* Interrupt ID Register */
+#define UART_FCR        0x10    /* FIFO Control Register */
+#define UART_LCR        0x14    /* Line Control Register */
+#define UART_MCR        0x18    /* Modem Control Register */
+#define UART_LSR        0x1C    /* Line Status Register */
+#define UART_MSR        0x20    /* Modem Status Register */
+#define UART_CLK        0x28    /* Baud Rate Clock Divider */
+#define UART_MOD_CNTRL  0x100   /* Module Control */
+
+#define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK   0xF0 /* Mask for the FIFO trigger range */
+#define UART_FCR_R_TRIGGER_1    0x00 /* Mask for receive trigger set at 1 */
+#define UART_FCR_R_TRIGGER_4    0x40 /* Mask for receive trigger set at 4 */
+#define UART_FCR_R_TRIGGER_8    0x80 /* Mask for receive trigger set at 8 */
+#define UART_FCR_R_TRIGGER_14   0xA0 /* Mask for receive trigger set at 14 */
+#define UART_FCR_T_TRIGGER_0    0x00 /* Mask for transmit trigger set at 0 */
+#define UART_FCR_T_TRIGGER_4    0x10 /* Mask for transmit trigger set at 4 */
+#define UART_FCR_T_TRIGGER_8    0x20 /* Mask for transmit trigger set at 8 */
+#define UART_FCR_T_TRIGGER_12   0x30 /* Mask for transmit trigger set at 12 */
+
+/*
+ * These are the definitions for the Line Control Register
+ */
+#define UART_LCR_SBC    0x40    /* Set break control */
+#define UART_LCR_SPAR   0x20    /* Stick parity (?) */
+#define UART_LCR_EPAR   0x10    /* Even parity select */
+#define UART_LCR_PARITY 0x08    /* Parity Enable */
+#define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
+#define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
+#define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
+#define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
+#define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_TEMT   0x40    /* Transmitter empty */
+#define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
+#define UART_LSR_BI     0x10    /* Break interrupt indicator */
+#define UART_LSR_FE     0x08    /* Frame error indicator */
+#define UART_LSR_PE     0x04    /* Parity error indicator */
+#define UART_LSR_OE     0x02    /* Overrun error indicator */
+#define UART_LSR_DR     0x01    /* Receiver data ready */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT 0x01    /* No interrupts pending */
+#define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
+#define UART_IIR_MSI    0x00    /* Modem status interrupt */
+#define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
+#define UART_IIR_RDI    0x04    /* Receiver data interrupt */
+#define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
+#define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
+#define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
+#define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
+#define UART_MCR_OUT2   0x08    /* Out2 complement */
+#define UART_MCR_OUT1   0x04    /* Out1 complement */
+#define UART_MCR_RTS    0x02    /* RTS complement */
+#define UART_MCR_DTR    0x01    /* DTR complement */
+
+/*
+ * These are the definitions for the Modem Status Register
+ */
+#define UART_MSR_DCD    0x80    /* Data Carrier Detect */
+#define UART_MSR_RI     0x40    /* Ring Indicator */
+#define UART_MSR_DSR    0x20    /* Data Set Ready */
+#define UART_MSR_CTS    0x10    /* Clear to Send */
+#define UART_MSR_DDCD   0x08    /* Delta DCD */
+#define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
+#define UART_MSR_DDSR   0x02    /* Delta DSR */
+#define UART_MSR_DCTS   0x01    /* Delta CTS */
+#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
+
+/* SSIO */
+#define SSI0_STATUS             0xB1600000
+#  define SSI_STATUS_BF         (1 << 4)
+#  define SSI_STATUS_OF         (1 << 3)
+#  define SSI_STATUS_UF         (1 << 2)
+#  define SSI_STATUS_D          (1 << 1)
+#  define SSI_STATUS_B          (1 << 0)
+#define SSI0_INT                0xB1600004
+#  define SSI_INT_OI            (1 << 3)
+#  define SSI_INT_UI            (1 << 2)
+#  define SSI_INT_DI            (1 << 1)
+#define SSI0_INT_ENABLE         0xB1600008
+#  define SSI_INTE_OIE          (1 << 3)
+#  define SSI_INTE_UIE          (1 << 2)
+#  define SSI_INTE_DIE          (1 << 1)
+#define SSI0_CONFIG             0xB1600020
+#  define SSI_CONFIG_AO         (1 << 24)
+#  define SSI_CONFIG_DO         (1 << 23)
+#  define SSI_CONFIG_ALEN_BIT   20
+#  define SSI_CONFIG_ALEN_MASK  (0x7 << 20)
+#  define SSI_CONFIG_DLEN_BIT   16
+#  define SSI_CONFIG_DLEN_MASK  (0x7 << 16)
+#  define SSI_CONFIG_DD         (1 << 11)
+#  define SSI_CONFIG_AD         (1 << 10)
+#  define SSI_CONFIG_BM_BIT     8
+#  define SSI_CONFIG_BM_MASK    (0x3 << 8)
+#  define SSI_CONFIG_CE         (1 << 7)
+#  define SSI_CONFIG_DP         (1 << 6)
+#  define SSI_CONFIG_DL         (1 << 5)
+#  define SSI_CONFIG_EP         (1 << 4)
+#define SSI0_ADATA              0xB1600024
+#  define SSI_AD_D              (1 << 24)
+#  define SSI_AD_ADDR_BIT       16
+#  define SSI_AD_ADDR_MASK      (0xff << 16)
+#  define SSI_AD_DATA_BIT       0
+#  define SSI_AD_DATA_MASK      (0xfff << 0)
+#define SSI0_CLKDIV             0xB1600028
+#define SSI0_CONTROL            0xB1600100
+#  define SSI_CONTROL_CD        (1 << 1)
+#  define SSI_CONTROL_E         (1 << 0)
+
+/* SSI1 */
+#define SSI1_STATUS             0xB1680000
+#define SSI1_INT                0xB1680004
+#define SSI1_INT_ENABLE         0xB1680008
+#define SSI1_CONFIG             0xB1680020
+#define SSI1_ADATA              0xB1680024
+#define SSI1_CLKDIV             0xB1680028
+#define SSI1_ENABLE             0xB1680100
+
+/*
+ * Register content definitions
+ */
+#define SSI_STATUS_BF           (1 << 4)
+#define SSI_STATUS_OF           (1 << 3)
+#define SSI_STATUS_UF           (1 << 2)
+#define SSI_STATUS_D            (1 << 1)
+#define SSI_STATUS_B            (1 << 0)
+
+/* SSI_INT */
+#define SSI_INT_OI              (1 << 3)
+#define SSI_INT_UI              (1 << 2)
+#define SSI_INT_DI              (1 << 1)
+
+/* SSI_INTEN */
+#define SSI_INTEN_OIE           (1 << 3)
+#define SSI_INTEN_UIE           (1 << 2)
+#define SSI_INTEN_DIE           (1 << 1)
+
+#define SSI_CONFIG_AO           (1 << 24)
+#define SSI_CONFIG_DO           (1 << 23)
+#define SSI_CONFIG_ALEN         (7 << 20)
+#define SSI_CONFIG_DLEN         (15 << 16)
+#define SSI_CONFIG_DD           (1 << 11)
+#define SSI_CONFIG_AD           (1 << 10)
+#define SSI_CONFIG_BM           (3 << 8)
+#define SSI_CONFIG_CE           (1 << 7)
+#define SSI_CONFIG_DP           (1 << 6)
+#define SSI_CONFIG_DL           (1 << 5)
+#define SSI_CONFIG_EP           (1 << 4)
+#define SSI_CONFIG_ALEN_N(N)    ((N-1) << 20)
+#define SSI_CONFIG_DLEN_N(N)    ((N-1) << 16)
+#define SSI_CONFIG_BM_HI        (0 << 8)
+#define SSI_CONFIG_BM_LO        (1 << 8)
+#define SSI_CONFIG_BM_CY        (2 << 8)
+
+#define SSI_ADATA_D             (1 << 24)
+#define SSI_ADATA_ADDR          (0xFF << 16)
+#define SSI_ADATA_DATA          0x0FFF
+#define SSI_ADATA_ADDR_N(N)     (N << 16)
+
+#define SSI_ENABLE_CD           (1 << 1)
+#define SSI_ENABLE_E            (1 << 0)
+
+/* IrDA Controller */
+#define IRDA_BASE               0xB0300000
+#define IR_RING_PTR_STATUS      (IRDA_BASE + 0x00)
+#define IR_RING_BASE_ADDR_H     (IRDA_BASE + 0x04)
+#define IR_RING_BASE_ADDR_L     (IRDA_BASE + 0x08)
+#define IR_RING_SIZE            (IRDA_BASE + 0x0C)
+#define IR_RING_PROMPT          (IRDA_BASE + 0x10)
+#define IR_RING_ADDR_CMPR       (IRDA_BASE + 0x14)
+#define IR_INT_CLEAR            (IRDA_BASE + 0x18)
+#define IR_CONFIG_1             (IRDA_BASE + 0x20)
+#  define IR_RX_INVERT_LED      (1 << 0)
+#  define IR_TX_INVERT_LED      (1 << 1)
+#  define IR_ST                 (1 << 2)
+#  define IR_SF                 (1 << 3)
+#  define IR_SIR                (1 << 4)
+#  define IR_MIR                (1 << 5)
+#  define IR_FIR                (1 << 6)
+#  define IR_16CRC              (1 << 7)
+#  define IR_TD                 (1 << 8)
+#  define IR_RX_ALL             (1 << 9)
+#  define IR_DMA_ENABLE         (1 << 10)
+#  define IR_RX_ENABLE          (1 << 11)
+#  define IR_TX_ENABLE          (1 << 12)
+#  define IR_LOOPBACK           (1 << 14)
+#  define IR_SIR_MODE           (IR_SIR | IR_DMA_ENABLE | \
+                                 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+#define IR_SIR_FLAGS            (IRDA_BASE + 0x24)
+#define IR_ENABLE               (IRDA_BASE + 0x28)
+#  define IR_RX_STATUS          (1 << 9)
+#  define IR_TX_STATUS          (1 << 10)
+#define IR_READ_PHY_CONFIG      (IRDA_BASE + 0x2C)
+#define IR_WRITE_PHY_CONFIG     (IRDA_BASE + 0x30)
+#define IR_MAX_PKT_LEN          (IRDA_BASE + 0x34)
+#define IR_RX_BYTE_CNT          (IRDA_BASE + 0x38)
+#define IR_CONFIG_2             (IRDA_BASE + 0x3C)
+#  define IR_MODE_INV           (1 << 0)
+#  define IR_ONE_PIN            (1 << 1)
+#define IR_INTERFACE_CONFIG     (IRDA_BASE + 0x40)
+
+/* GPIO */
+#define SYS_PINFUNC             0xB190002C
+#  define SYS_PF_USB            (1 << 15)       /* 2nd USB device/host */
+#  define SYS_PF_U3             (1 << 14)       /* GPIO23/U3TXD */
+#  define SYS_PF_U2             (1 << 13)       /* GPIO22/U2TXD */
+#  define SYS_PF_U1             (1 << 12)       /* GPIO21/U1TXD */
+#  define SYS_PF_SRC            (1 << 11)       /* GPIO6/SROMCKE */
+#  define SYS_PF_CK5            (1 << 10)       /* GPIO3/CLK5 */
+#  define SYS_PF_CK4            (1 << 9)        /* GPIO2/CLK4 */
+#  define SYS_PF_IRF            (1 << 8)        /* GPIO15/IRFIRSEL */
+#  define SYS_PF_UR3            (1 << 7)        /* GPIO[14:9]/UART3 */
+#  define SYS_PF_I2D            (1 << 6)        /* GPIO8/I2SDI */
+#  define SYS_PF_I2S            (1 << 5)        /* I2S/GPIO[29:31] */
+#  define SYS_PF_NI2            (1 << 4)        /* NI2/GPIO[24:28] */
+#  define SYS_PF_U0             (1 << 3)        /* U0TXD/GPIO20 */
+#  define SYS_PF_RD             (1 << 2)        /* IRTXD/GPIO19 */
+#  define SYS_PF_A97            (1 << 1)        /* AC97/SSL1 */
+#  define SYS_PF_S0             (1 << 0)        /* SSI_0/GPIO[16:18] */
+
+/* Au1100 only */
+#  define SYS_PF_PC             (1 << 18)       /* PCMCIA/GPIO[207:204] */
+#  define SYS_PF_LCD            (1 << 17)       /* extern lcd/GPIO[203:200] */
+#  define SYS_PF_CS             (1 << 16)       /* EXTCLK0/32KHz to gpio2 */
+#  define SYS_PF_EX0            (1 << 9)        /* GPIO2/clock */
+
+/* Au1550 only.  Redefines lots of pins */
+#  define SYS_PF_PSC2_MASK      (7 << 17)
+#  define SYS_PF_PSC2_AC97      0
+#  define SYS_PF_PSC2_SPI       0
+#  define SYS_PF_PSC2_I2S       (1 << 17)
+#  define SYS_PF_PSC2_SMBUS     (3 << 17)
+#  define SYS_PF_PSC2_GPIO      (7 << 17)
+#  define SYS_PF_PSC3_MASK      (7 << 20)
+#  define SYS_PF_PSC3_AC97      0
+#  define SYS_PF_PSC3_SPI       0
+#  define SYS_PF_PSC3_I2S       (1 << 20)
+#  define SYS_PF_PSC3_SMBUS     (3 << 20)
+#  define SYS_PF_PSC3_GPIO      (7 << 20)
+#  define SYS_PF_PSC1_S1        (1 << 1)
+#  define SYS_PF_MUST_BE_SET    ((1 << 5) | (1 << 2))
+
+/* Au1200 only */
+#ifdef CONFIG_SOC_AU1200
+#define SYS_PINFUNC_DMA         (1 << 31)
+#define SYS_PINFUNC_S0A         (1 << 30)
+#define SYS_PINFUNC_S1A         (1 << 29)
+#define SYS_PINFUNC_LP0         (1 << 28)
+#define SYS_PINFUNC_LP1         (1 << 27)
+#define SYS_PINFUNC_LD16        (1 << 26)
+#define SYS_PINFUNC_LD8         (1 << 25)
+#define SYS_PINFUNC_LD1         (1 << 24)
+#define SYS_PINFUNC_LD0         (1 << 23)
+#define SYS_PINFUNC_P1A         (3 << 21)
+#define SYS_PINFUNC_P1B         (1 << 20)
+#define SYS_PINFUNC_FS3         (1 << 19)
+#define SYS_PINFUNC_P0A         (3 << 17)
+#define SYS_PINFUNC_CS          (1 << 16)
+#define SYS_PINFUNC_CIM         (1 << 15)
+#define SYS_PINFUNC_P1C         (1 << 14)
+#define SYS_PINFUNC_U1T         (1 << 12)
+#define SYS_PINFUNC_U1R         (1 << 11)
+#define SYS_PINFUNC_EX1         (1 << 10)
+#define SYS_PINFUNC_EX0         (1 << 9)
+#define SYS_PINFUNC_U0R         (1 << 8)
+#define SYS_PINFUNC_MC          (1 << 7)
+#define SYS_PINFUNC_S0B         (1 << 6)
+#define SYS_PINFUNC_S0C         (1 << 5)
+#define SYS_PINFUNC_P0B         (1 << 4)
+#define SYS_PINFUNC_U0T         (1 << 3)
+#define SYS_PINFUNC_S1B         (1 << 2)
+#endif
+
+#define SYS_TRIOUTRD            0xB1900100
+#define SYS_TRIOUTCLR           0xB1900100
+#define SYS_OUTPUTRD            0xB1900108
+#define SYS_OUTPUTSET           0xB1900108
+#define SYS_OUTPUTCLR           0xB190010C
+#define SYS_PINSTATERD          0xB1900110
+#define SYS_PININPUTEN          0xB1900110
+
+/* GPIO2, Au1500, Au1550 only */
+#define GPIO2_BASE              0xB1700000
+#define GPIO2_DIR               (GPIO2_BASE + 0)
+#define GPIO2_OUTPUT            (GPIO2_BASE + 8)
+#define GPIO2_PINSTATE          (GPIO2_BASE + 0xC)
+#define GPIO2_INTENABLE         (GPIO2_BASE + 0x10)
+#define GPIO2_ENABLE            (GPIO2_BASE + 0x14)
+
+/* Power Management */
+#define SYS_SCRATCH0            0xB1900018
+#define SYS_SCRATCH1            0xB190001C
+#define SYS_WAKEMSK             0xB1900034
+#define SYS_ENDIAN              0xB1900038
+#define SYS_POWERCTRL           0xB190003C
+#define SYS_WAKESRC             0xB190005C
+#define SYS_SLPPWR              0xB1900078
+#define SYS_SLEEP               0xB190007C
+
+/* Clock Controller */
+#define SYS_FREQCTRL0           0xB1900020
+#  define SYS_FC_FRDIV2_BIT     22
+#  define SYS_FC_FRDIV2_MASK    (0xff << SYS_FC_FRDIV2_BIT)
+#  define SYS_FC_FE2            (1 << 21)
+#  define SYS_FC_FS2            (1 << 20)
+#  define SYS_FC_FRDIV1_BIT     12
+#  define SYS_FC_FRDIV1_MASK    (0xff << SYS_FC_FRDIV1_BIT)
+#  define SYS_FC_FE1            (1 << 11)
+#  define SYS_FC_FS1            (1 << 10)
+#  define SYS_FC_FRDIV0_BIT     2
+#  define SYS_FC_FRDIV0_MASK    (0xff << SYS_FC_FRDIV0_BIT)
+#  define SYS_FC_FE0            (1 << 1)
+#  define SYS_FC_FS0            (1 << 0)
+#define SYS_FREQCTRL1           0xB1900024
+#  define SYS_FC_FRDIV5_BIT     22
+#  define SYS_FC_FRDIV5_MASK    (0xff << SYS_FC_FRDIV5_BIT)
+#  define SYS_FC_FE5            (1 << 21)
+#  define SYS_FC_FS5            (1 << 20)
+#  define SYS_FC_FRDIV4_BIT     12
+#  define SYS_FC_FRDIV4_MASK    (0xff << SYS_FC_FRDIV4_BIT)
+#  define SYS_FC_FE4            (1 << 11)
+#  define SYS_FC_FS4            (1 << 10)
+#  define SYS_FC_FRDIV3_BIT     2
+#  define SYS_FC_FRDIV3_MASK    (0xff << SYS_FC_FRDIV3_BIT)
+#  define SYS_FC_FE3            (1 << 1)
+#  define SYS_FC_FS3            (1 << 0)
+#define SYS_CLKSRC              0xB1900028
+#  define SYS_CS_ME1_BIT        27
+#  define SYS_CS_ME1_MASK       (0x7 << SYS_CS_ME1_BIT)
+#  define SYS_CS_DE1            (1 << 26)
+#  define SYS_CS_CE1            (1 << 25)
+#  define SYS_CS_ME0_BIT        22
+#  define SYS_CS_ME0_MASK       (0x7 << SYS_CS_ME0_BIT)
+#  define SYS_CS_DE0            (1 << 21)
+#  define SYS_CS_CE0            (1 << 20)
+#  define SYS_CS_MI2_BIT        17
+#  define SYS_CS_MI2_MASK       (0x7 << SYS_CS_MI2_BIT)
+#  define SYS_CS_DI2            (1 << 16)
+#  define SYS_CS_CI2            (1 << 15)
+#ifdef CONFIG_SOC_AU1100
+#  define SYS_CS_ML_BIT         7
+#  define SYS_CS_ML_MASK        (0x7 << SYS_CS_ML_BIT)
+#  define SYS_CS_DL             (1 << 6)
+#  define SYS_CS_CL             (1 << 5)
+#else
+#  define SYS_CS_MUH_BIT        12
+#  define SYS_CS_MUH_MASK       (0x7 << SYS_CS_MUH_BIT)
+#  define SYS_CS_DUH            (1 << 11)
+#  define SYS_CS_CUH            (1 << 10)
+#  define SYS_CS_MUD_BIT        7
+#  define SYS_CS_MUD_MASK       (0x7 << SYS_CS_MUD_BIT)
+#  define SYS_CS_DUD            (1 << 6)
+#  define SYS_CS_CUD            (1 << 5)
+#endif
+#  define SYS_CS_MIR_BIT        2
+#  define SYS_CS_MIR_MASK       (0x7 << SYS_CS_MIR_BIT)
+#  define SYS_CS_DIR            (1 << 1)
+#  define SYS_CS_CIR            (1 << 0)
+
+#  define SYS_CS_MUX_AUX        0x1
+#  define SYS_CS_MUX_FQ0        0x2
+#  define SYS_CS_MUX_FQ1        0x3
+#  define SYS_CS_MUX_FQ2        0x4
+#  define SYS_CS_MUX_FQ3        0x5
+#  define SYS_CS_MUX_FQ4        0x6
+#  define SYS_CS_MUX_FQ5        0x7
+#define SYS_CPUPLL              0xB1900060
+#define SYS_AUXPLL              0xB1900064
+
+/* AC97 Controller */
+#define AC97C_CONFIG            0xB0000000
+#  define AC97C_RECV_SLOTS_BIT  13
+#  define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
+#  define AC97C_XMIT_SLOTS_BIT  3
+#  define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
+#  define AC97C_SG              (1 << 2)
+#  define AC97C_SYNC            (1 << 1)
+#  define AC97C_RESET           (1 << 0)
+#define AC97C_STATUS            0xB0000004
+#  define AC97C_XU              (1 << 11)
+#  define AC97C_XO              (1 << 10)
+#  define AC97C_RU              (1 << 9)
+#  define AC97C_RO              (1 << 8)
+#  define AC97C_READY           (1 << 7)
+#  define AC97C_CP              (1 << 6)
+#  define AC97C_TR              (1 << 5)
+#  define AC97C_TE              (1 << 4)
+#  define AC97C_TF              (1 << 3)
+#  define AC97C_RR              (1 << 2)
+#  define AC97C_RE              (1 << 1)
+#  define AC97C_RF              (1 << 0)
+#define AC97C_DATA              0xB0000008
+#define AC97C_CMD               0xB000000C
+#  define AC97C_WD_BIT          16
+#  define AC97C_READ            (1 << 7)
+#  define AC97C_INDEX_MASK      0x7f
+#define AC97C_CNTRL             0xB0000010
+#  define AC97C_RS              (1 << 1)
+#  define AC97C_CE              (1 << 0)
+
+/* Secure Digital (SD) Controller */
+#define SD0_XMIT_FIFO   0xB0600000
+#define SD0_RECV_FIFO   0xB0600004
+#define SD1_XMIT_FIFO   0xB0680000
+#define SD1_RECV_FIFO   0xB0680004
+
+#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
+/* Au1500 PCI Controller */
+#define Au1500_CFG_BASE         0xB4005000      /* virtual, KSEG1 addr */
+#define Au1500_PCI_CMEM         (Au1500_CFG_BASE + 0)
+#define Au1500_PCI_CFG          (Au1500_CFG_BASE + 4)
+#  define PCI_ERROR             ((1 << 22) | (1 << 23) | (1 << 24) | \
+                                 (1 << 25) | (1 << 26) | (1 << 27))
+#define Au1500_PCI_B2BMASK_CCH  (Au1500_CFG_BASE + 8)
+#define Au1500_PCI_B2B0_VID     (Au1500_CFG_BASE + 0xC)
+#define Au1500_PCI_B2B1_ID      (Au1500_CFG_BASE + 0x10)
+#define Au1500_PCI_MWMASK_DEV   (Au1500_CFG_BASE + 0x14)
+#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
+#define Au1500_PCI_ERR_ADDR     (Au1500_CFG_BASE + 0x1C)
+#define Au1500_PCI_SPEC_INTACK  (Au1500_CFG_BASE + 0x20)
+#define Au1500_PCI_ID           (Au1500_CFG_BASE + 0x100)
+#define Au1500_PCI_STATCMD      (Au1500_CFG_BASE + 0x104)
+#define Au1500_PCI_CLASSREV     (Au1500_CFG_BASE + 0x108)
+#define Au1500_PCI_HDRTYPE      (Au1500_CFG_BASE + 0x10C)
+#define Au1500_PCI_MBAR         (Au1500_CFG_BASE + 0x110)
+
+#define Au1500_PCI_HDR          0xB4005100      /* virtual, KSEG1 addr */
+
+/*
+ * All of our structures, like PCI resource, have 32-bit members.
+ * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
+ * hard to store 0x4 0000 0000 in a 32-bit type.  We require a small patch
+ * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
+ * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
+ * addresses.  For PCI I/O, it's simpler because we get to do the ioremap
+ * ourselves and then adjust the device's resources.
+ */
+#define Au1500_EXT_CFG          0x600000000ULL
+#define Au1500_EXT_CFG_TYPE1    0x680000000ULL
+#define Au1500_PCI_IO_START     0x500000000ULL
+#define Au1500_PCI_IO_END       0x5000FFFFFULL
+#define Au1500_PCI_MEM_START    0x440000000ULL
+#define Au1500_PCI_MEM_END      0x44FFFFFFFULL
+
+#define PCI_IO_START    0x00001000
+#define PCI_IO_END      0x000FFFFF
+#define PCI_MEM_START   0x40000000
+#define PCI_MEM_END     0x4FFFFFFF
+
+#define PCI_FIRST_DEVFN (0 << 3)
+#define PCI_LAST_DEVFN  (19 << 3)
+
+#define IOPORT_RESOURCE_START   0x00001000      /* skip legacy probing */
+#define IOPORT_RESOURCE_END     0xffffffff
+#define IOMEM_RESOURCE_START    0x10000000
+#define IOMEM_RESOURCE_END      0xffffffff
+
+#else /* Au1000 and Au1100 and Au1200 */
+
+/* Don't allow any legacy ports probing */
+#define IOPORT_RESOURCE_START   0x10000000
+#define IOPORT_RESOURCE_END     0xffffffff
+#define IOMEM_RESOURCE_START    0x10000000
+#define IOMEM_RESOURCE_END      0xffffffff
+
+#define PCI_IO_START    0
+#define PCI_IO_END      0
+#define PCI_MEM_START   0
+#define PCI_MEM_END     0
+#define PCI_FIRST_DEVFN 0
+#define PCI_LAST_DEVFN  0
+
+#endif
+
+#ifndef _LANGUAGE_ASSEMBLY
+typedef volatile struct {
+        /* 0x0000 */ u32 toytrim;
+        /* 0x0004 */ u32 toywrite;
+        /* 0x0008 */ u32 toymatch0;
+        /* 0x000C */ u32 toymatch1;
+        /* 0x0010 */ u32 toymatch2;
+        /* 0x0014 */ u32 cntrctrl;
+        /* 0x0018 */ u32 scratch0;
+        /* 0x001C */ u32 scratch1;
+        /* 0x0020 */ u32 freqctrl0;
+        /* 0x0024 */ u32 freqctrl1;
+        /* 0x0028 */ u32 clksrc;
+        /* 0x002C */ u32 pinfunc;
+        /* 0x0030 */ u32 reserved0;
+        /* 0x0034 */ u32 wakemsk;
+        /* 0x0038 */ u32 endian;
+        /* 0x003C */ u32 powerctrl;
+        /* 0x0040 */ u32 toyread;
+        /* 0x0044 */ u32 rtctrim;
+        /* 0x0048 */ u32 rtcwrite;
+        /* 0x004C */ u32 rtcmatch0;
+        /* 0x0050 */ u32 rtcmatch1;
+        /* 0x0054 */ u32 rtcmatch2;
+        /* 0x0058 */ u32 rtcread;
+        /* 0x005C */ u32 wakesrc;
+        /* 0x0060 */ u32 cpupll;
+        /* 0x0064 */ u32 auxpll;
+        /* 0x0068 */ u32 reserved1;
+        /* 0x006C */ u32 reserved2;
+        /* 0x0070 */ u32 reserved3;
+        /* 0x0074 */ u32 reserved4;
+        /* 0x0078 */ u32 slppwr;
+        /* 0x007C */ u32 sleep;
+        /* 0x0080 */ u32 reserved5[32];
+        /* 0x0100 */ u32 trioutrd;
+#define trioutclr trioutrd
+        /* 0x0104 */ u32 reserved6;
+        /* 0x0108 */ u32 outputrd;
+#define outputset outputrd
+        /* 0x010C */ u32 outputclr;
+        /* 0x0110 */ u32 pinstaterd;
+#define pininputen pinstaterd
+} AU1X00_SYS;
+
+static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
+
+#endif
+
+/*
+ * Processor information based on PRID.
+ * Copied from PowerPC.
+ */
+#ifndef _LANGUAGE_ASSEMBLY
+struct cpu_spec {
+        /* CPU is matched via (PRID & prid_mask) == prid_value */
+        unsigned int    prid_mask;
+        unsigned int    prid_value;
+
+        char            *cpu_name;
+        unsigned char   cpu_od;         /* Set Config[OD] */
+        unsigned char   cpu_bclk;       /* Enable BCLK switching */
+        unsigned char   cpu_pll_wo;     /* sys_cpupll reg. write-only */
+};
+
+extern struct cpu_spec  cpu_specs[];
+extern struct cpu_spec  *cur_cpu_spec[];
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
new file mode 100644
index 000000000000..c333b4e1cd44
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -0,0 +1,458 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Defines for using and allocating DMA channels on the Alchemy
+ *      Au1x00 MIPS processors.
+ *
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#ifndef __ASM_AU1000_DMA_H
+#define __ASM_AU1000_DMA_H
+
+#include <linux/io.h>           /* need byte IO */
+#include <linux/spinlock.h>     /* And spinlocks */
+#include <linux/delay.h>
+#include <asm/system.h>
+
+#define NUM_AU1000_DMA_CHANNELS 8
+
+/* DMA Channel Base Addresses */
+#define DMA_CHANNEL_BASE        0xB4002000
+#define DMA_CHANNEL_LEN         0x00000100
+
+/* DMA Channel Register Offsets */
+#define DMA_MODE_SET            0x00000000
+#define DMA_MODE_READ           DMA_MODE_SET
+#define DMA_MODE_CLEAR          0x00000004
+/* DMA Mode register bits follow */
+#define DMA_DAH_MASK            (0x0f << 20)
+#define DMA_DID_BIT             16
+#define DMA_DID_MASK            (0x0f << DMA_DID_BIT)
+#define DMA_DS                  (1 << 15)
+#define DMA_BE                  (1 << 13)
+#define DMA_DR                  (1 << 12)
+#define DMA_TS8                 (1 << 11)
+#define DMA_DW_BIT              9
+#define DMA_DW_MASK             (0x03 << DMA_DW_BIT)
+#define DMA_DW8                 (0 << DMA_DW_BIT)
+#define DMA_DW16                (1 << DMA_DW_BIT)
+#define DMA_DW32                (2 << DMA_DW_BIT)
+#define DMA_NC                  (1 << 8)
+#define DMA_IE                  (1 << 7)
+#define DMA_HALT                (1 << 6)
+#define DMA_GO                  (1 << 5)
+#define DMA_AB                  (1 << 4)
+#define DMA_D1                  (1 << 3)
+#define DMA_BE1                 (1 << 2)
+#define DMA_D0                  (1 << 1)
+#define DMA_BE0                 (1 << 0)
+
+#define DMA_PERIPHERAL_ADDR     0x00000008
+#define DMA_BUFFER0_START       0x0000000C
+#define DMA_BUFFER1_START       0x00000014
+#define DMA_BUFFER0_COUNT       0x00000010
+#define DMA_BUFFER1_COUNT       0x00000018
+#define DMA_BAH_BIT     16
+#define DMA_BAH_MASK    (0x0f << DMA_BAH_BIT)
+#define DMA_COUNT_BIT   0
+#define DMA_COUNT_MASK  (0xffff << DMA_COUNT_BIT)
+
+/* DMA Device IDs follow */
+enum {
+        DMA_ID_UART0_TX = 0,
+        DMA_ID_UART0_RX,
+        DMA_ID_GP04,
+        DMA_ID_GP05,
+        DMA_ID_AC97C_TX,
+        DMA_ID_AC97C_RX,
+        DMA_ID_UART3_TX,
+        DMA_ID_UART3_RX,
+        DMA_ID_USBDEV_EP0_RX,
+        DMA_ID_USBDEV_EP0_TX,
+        DMA_ID_USBDEV_EP2_TX,
+        DMA_ID_USBDEV_EP3_TX,
+        DMA_ID_USBDEV_EP4_RX,
+        DMA_ID_USBDEV_EP5_RX,
+        DMA_ID_I2S_TX,
+        DMA_ID_I2S_RX,
+        DMA_NUM_DEV
+};
+
+/* DMA Device ID's for 2nd bank (AU1100) follow */
+enum {
+        DMA_ID_SD0_TX = 0,
+        DMA_ID_SD0_RX,
+        DMA_ID_SD1_TX,
+        DMA_ID_SD1_RX,
+        DMA_NUM_DEV_BANK2
+};
+
+struct dma_chan {
+        int dev_id;             /* this channel is allocated if >= 0, */
+                                /* free otherwise */
+        unsigned int io;
+        const char *dev_str;
+        int irq;
+        void *irq_dev;
+        unsigned int fifo_addr;
+        unsigned int mode;
+};
+
+/* These are in arch/mips/au1000/common/dma.c */
+extern struct dma_chan au1000_dma_table[];
+extern int request_au1000_dma(int dev_id,
+                              const char *dev_str,
+                              irq_handler_t irqhandler,
+                              unsigned long irqflags,
+                              void *irq_dev_id);
+extern void free_au1000_dma(unsigned int dmanr);
+extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
+                                int length, int *eof, void *data);
+extern void dump_au1000_dma_channel(unsigned int dmanr);
+extern spinlock_t au1000_dma_spin_lock;
+
+static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
+{
+        if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
+            au1000_dma_table[dmanr].dev_id < 0)
+                return NULL;
+        return &au1000_dma_table[dmanr];
+}
+
+static inline unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&au1000_dma_spin_lock, flags);
+        return flags;
+}
+
+static inline void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
+}
+
+/*
+ * Set the DMA buffer enable bits in the mode register.
+ */
+static inline void enable_dma_buffer0(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
+}
+
+static inline void enable_dma_buffer1(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
+}
+static inline void enable_dma_buffers(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
+}
+
+static inline void start_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        au_writel(DMA_GO, chan->io + DMA_MODE_SET);
+}
+
+#define DMA_HALT_POLL 0x5000
+
+static inline void halt_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        int i;
+
+        if (!chan)
+                return;
+        au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
+
+        /* Poll the halt bit */
+        for (i = 0; i < DMA_HALT_POLL; i++)
+                if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
+                        break;
+        if (i == DMA_HALT_POLL)
+                printk(KERN_INFO "halt_dma: HALT poll expired!\n");
+}
+
+static inline void disable_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+
+        halt_dma(dmanr);
+
+        /* Now we can disable the buffers */
+        au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
+}
+
+static inline int dma_halted(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return 1;
+        return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
+}
+
+/* Initialize a DMA channel. */
+static inline void init_dma(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+        u32 mode;
+
+        if (!chan)
+                return;
+
+        disable_dma(dmanr);
+
+        /* Set device FIFO address */
+        au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
+
+        mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
+        if (chan->irq)
+                mode |= DMA_IE;
+
+        au_writel(~mode, chan->io + DMA_MODE_CLEAR);
+        au_writel(mode,  chan->io + DMA_MODE_SET);
+}
+
+/*
+ * Set mode for a specific DMA channel
+ */
+static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        /*
+         * set_dma_mode is only allowed to change endianess, direction,
+         * transfer size, device FIFO width, and coherency settings.
+         * Make sure anything else is masked off.
+         */
+        mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
+        chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
+        chan->mode |= mode;
+}
+
+static inline unsigned int get_dma_mode(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return 0;
+        return chan->mode;
+}
+
+static inline int get_dma_active_buffer(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return -1;
+        return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
+}
+
+/*
+ * Set the device FIFO address for a specific DMA channel - only
+ * applicable to GPO4 and GPO5. All the other devices have fixed
+ * FIFO addresses.
+ */
+static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+
+        if (chan->mode & DMA_DS)        /* second bank of device IDs */
+                return;
+
+        if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
+                return;
+
+        au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
+}
+
+/*
+ * Clear the DMA buffer done bits in the mode register.
+ */
+static inline void clear_dma_done0(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
+}
+
+static inline void clear_dma_done1(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
+}
+
+/*
+ * This does nothing - not applicable to Au1000 DMA.
+ */
+static inline void set_dma_page(unsigned int dmanr, char pagenr)
+{
+}
+
+/*
+ * Set Buffer 0 transfer address for specific DMA channel.
+ */
+static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        au_writel(a, chan->io + DMA_BUFFER0_START);
+}
+
+/*
+ * Set Buffer 1 transfer address for specific DMA channel.
+ */
+static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        au_writel(a, chan->io + DMA_BUFFER1_START);
+}
+
+
+/*
+ * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
+ */
+static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        count &= DMA_COUNT_MASK;
+        au_writel(count, chan->io + DMA_BUFFER0_COUNT);
+}
+
+/*
+ * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
+ */
+static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        count &= DMA_COUNT_MASK;
+        au_writel(count, chan->io + DMA_BUFFER1_COUNT);
+}
+
+/*
+ * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
+ */
+static inline void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return;
+        count &= DMA_COUNT_MASK;
+        au_writel(count, chan->io + DMA_BUFFER0_COUNT);
+        au_writel(count, chan->io + DMA_BUFFER1_COUNT);
+}
+
+/*
+ * Returns which buffer has its done bit set in the mode register.
+ * Returns -1 if neither or both done bits set.
+ */
+static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return 0;
+        return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
+}
+
+
+/*
+ * Returns the DMA channel's Buffer Done IRQ number.
+ */
+static inline int get_dma_done_irq(unsigned int dmanr)
+{
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return -1;
+        return chan->irq;
+}
+
+/*
+ * Get DMA residue count. Returns the number of _bytes_ left to transfer.
+ */
+static inline int get_dma_residue(unsigned int dmanr)
+{
+        int curBufCntReg, count;
+        struct dma_chan *chan = get_dma_chan(dmanr);
+
+        if (!chan)
+                return 0;
+
+        curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
+            DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
+
+        count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
+
+        if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
+                count <<= 1;
+        else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
+                count <<= 2;
+
+        return count;
+}
+
+#endif /* __ASM_AU1000_DMA_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h b/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
new file mode 100644
index 000000000000..d8c96fda5549
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
@@ -0,0 +1,56 @@
+/*
+ * FILE NAME au1000_gpio.h
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      API to Alchemy Au1xx0 GPIO device.
+ *
+ *  Author: MontaVista Software, Inc.  <source@mvista.com>
+ *          Steve Longerbeam
+ *
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AU1000_GPIO_H
+#define __AU1000_GPIO_H
+
+#include <linux/ioctl.h>
+
+#define AU1000GPIO_IOC_MAGIC 'A'
+
+#define AU1000GPIO_IN           _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
+#define AU1000GPIO_SET          _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
+#define AU1000GPIO_CLEAR        _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
+#define AU1000GPIO_OUT          _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
+#define AU1000GPIO_TRISTATE     _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
+#define AU1000GPIO_AVAIL_MASK   _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
+
+#ifdef __KERNEL__
+extern u32 get_au1000_avail_gpio_mask(void);
+extern int au1000gpio_tristate(u32 data);
+extern int au1000gpio_in(u32 *data);
+extern int au1000gpio_set(u32 data);
+extern int au1000gpio_clear(u32 data);
+extern int au1000gpio_out(u32 data);
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
new file mode 100644
index 000000000000..c35e20918490
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -0,0 +1,208 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Defines for using the MMC/SD controllers on the
+ *      Alchemy Au1100 mips processor.
+ *
+ * Copyright (c) 2003 Embedded Edge, LLC.
+ * Author: Embedded Edge, LLC.
+ *              dan@embeddededge.com or tim@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+/*
+ * AU1100 MMC/SD definitions.
+ *
+ * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary"
+ *    June, 2003
+ */
+
+#ifndef __ASM_AU1100_MMC_H
+#define __ASM_AU1100_MMC_H
+
+#include <linux/leds.h>
+
+struct au1xmmc_platform_data {
+        int(*cd_setup)(void *mmc_host, int on);
+        int(*card_inserted)(void *mmc_host);
+        int(*card_readonly)(void *mmc_host);
+        void(*set_power)(void *mmc_host, int state);
+        struct led_classdev *led;
+};
+
+#define SD0_BASE        0xB0600000
+#define SD1_BASE        0xB0680000
+
+
+/*
+ *  Register offsets.
+ */
+#define SD_TXPORT       (0x0000)
+#define SD_RXPORT       (0x0004)
+#define SD_CONFIG       (0x0008)
+#define SD_ENABLE       (0x000C)
+#define SD_CONFIG2      (0x0010)
+#define SD_BLKSIZE      (0x0014)
+#define SD_STATUS       (0x0018)
+#define SD_DEBUG        (0x001C)
+#define SD_CMD          (0x0020)
+#define SD_CMDARG       (0x0024)
+#define SD_RESP3        (0x0028)
+#define SD_RESP2        (0x002C)
+#define SD_RESP1        (0x0030)
+#define SD_RESP0        (0x0034)
+#define SD_TIMEOUT      (0x0038)
+
+
+/*
+ *  SD_TXPORT bit definitions.
+ */
+#define SD_TXPORT_TXD   (0x000000ff)
+
+
+/*
+ *  SD_RXPORT bit definitions.
+ */
+#define SD_RXPORT_RXD   (0x000000ff)
+
+
+/*
+ *  SD_CONFIG bit definitions.
+ */
+#define SD_CONFIG_DIV   (0x000001ff)
+#define SD_CONFIG_DE    (0x00000200)
+#define SD_CONFIG_NE    (0x00000400)
+#define SD_CONFIG_TU    (0x00000800)
+#define SD_CONFIG_TO    (0x00001000)
+#define SD_CONFIG_RU    (0x00002000)
+#define SD_CONFIG_RO    (0x00004000)
+#define SD_CONFIG_I     (0x00008000)
+#define SD_CONFIG_CR    (0x00010000)
+#define SD_CONFIG_RAT   (0x00020000)
+#define SD_CONFIG_DD    (0x00040000)
+#define SD_CONFIG_DT    (0x00080000)
+#define SD_CONFIG_SC    (0x00100000)
+#define SD_CONFIG_RC    (0x00200000)
+#define SD_CONFIG_WC    (0x00400000)
+#define SD_CONFIG_xxx   (0x00800000)
+#define SD_CONFIG_TH    (0x01000000)
+#define SD_CONFIG_TE    (0x02000000)
+#define SD_CONFIG_TA    (0x04000000)
+#define SD_CONFIG_RH    (0x08000000)
+#define SD_CONFIG_RA    (0x10000000)
+#define SD_CONFIG_RF    (0x20000000)
+#define SD_CONFIG_CD    (0x40000000)
+#define SD_CONFIG_SI    (0x80000000)
+
+
+/*
+ *  SD_ENABLE bit definitions.
+ */
+#define SD_ENABLE_CE    (0x00000001)
+#define SD_ENABLE_R     (0x00000002)
+
+
+/*
+ *  SD_CONFIG2 bit definitions.
+ */
+#define SD_CONFIG2_EN   (0x00000001)
+#define SD_CONFIG2_FF   (0x00000002)
+#define SD_CONFIG2_xx1  (0x00000004)
+#define SD_CONFIG2_DF   (0x00000008)
+#define SD_CONFIG2_DC   (0x00000010)
+#define SD_CONFIG2_xx2  (0x000000e0)
+#define SD_CONFIG2_WB   (0x00000100)
+#define SD_CONFIG2_RW   (0x00000200)
+
+
+/*
+ *  SD_BLKSIZE bit definitions.
+ */
+#define SD_BLKSIZE_BS   (0x000007ff)
+#define SD_BLKSIZE_BS_SHIFT      (0)
+#define SD_BLKSIZE_BC   (0x01ff0000)
+#define SD_BLKSIZE_BC_SHIFT     (16)
+
+
+/*
+ *  SD_STATUS bit definitions.
+ */
+#define SD_STATUS_DCRCW (0x00000007)
+#define SD_STATUS_xx1   (0x00000008)
+#define SD_STATUS_CB    (0x00000010)
+#define SD_STATUS_DB    (0x00000020)
+#define SD_STATUS_CF    (0x00000040)
+#define SD_STATUS_D3    (0x00000080)
+#define SD_STATUS_xx2   (0x00000300)
+#define SD_STATUS_NE    (0x00000400)
+#define SD_STATUS_TU    (0x00000800)
+#define SD_STATUS_TO    (0x00001000)
+#define SD_STATUS_RU    (0x00002000)
+#define SD_STATUS_RO    (0x00004000)
+#define SD_STATUS_I     (0x00008000)
+#define SD_STATUS_CR    (0x00010000)
+#define SD_STATUS_RAT   (0x00020000)
+#define SD_STATUS_DD    (0x00040000)
+#define SD_STATUS_DT    (0x00080000)
+#define SD_STATUS_SC    (0x00100000)
+#define SD_STATUS_RC    (0x00200000)
+#define SD_STATUS_WC    (0x00400000)
+#define SD_STATUS_xx3   (0x00800000)
+#define SD_STATUS_TH    (0x01000000)
+#define SD_STATUS_TE    (0x02000000)
+#define SD_STATUS_TA    (0x04000000)
+#define SD_STATUS_RH    (0x08000000)
+#define SD_STATUS_RA    (0x10000000)
+#define SD_STATUS_RF    (0x20000000)
+#define SD_STATUS_CD    (0x40000000)
+#define SD_STATUS_SI    (0x80000000)
+
+
+/*
+ *  SD_CMD bit definitions.
+ */
+#define SD_CMD_GO       (0x00000001)
+#define SD_CMD_RY       (0x00000002)
+#define SD_CMD_xx1      (0x0000000c)
+#define SD_CMD_CT_MASK  (0x000000f0)
+#define SD_CMD_CT_0     (0x00000000)
+#define SD_CMD_CT_1     (0x00000010)
+#define SD_CMD_CT_2     (0x00000020)
+#define SD_CMD_CT_3     (0x00000030)
+#define SD_CMD_CT_4     (0x00000040)
+#define SD_CMD_CT_5     (0x00000050)
+#define SD_CMD_CT_6     (0x00000060)
+#define SD_CMD_CT_7     (0x00000070)
+#define SD_CMD_CI       (0x0000ff00)
+#define SD_CMD_CI_SHIFT         (8)
+#define SD_CMD_RT_MASK  (0x00ff0000)
+#define SD_CMD_RT_0     (0x00000000)
+#define SD_CMD_RT_1     (0x00010000)
+#define SD_CMD_RT_2     (0x00020000)
+#define SD_CMD_RT_3     (0x00030000)
+#define SD_CMD_RT_4     (0x00040000)
+#define SD_CMD_RT_5     (0x00050000)
+#define SD_CMD_RT_6     (0x00060000)
+#define SD_CMD_RT_1B    (0x00810000)
+
+
+#endif /* __ASM_AU1100_MMC_H */
+
diff --git a/arch/mips/include/asm/mach-au1x00/au1550_spi.h b/arch/mips/include/asm/mach-au1x00/au1550_spi.h
new file mode 100644
index 000000000000..08e1958e9410
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1550_spi.h
@@ -0,0 +1,15 @@
+/*
+ * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
+ */
+
+#ifndef _AU1550_SPI_H_
+#define _AU1550_SPI_H_
+
+struct au1550_spi_info {
+        u32 mainclk_hz;         /* main input clock frequency of PSC */
+        u16 num_chipselect;     /* number of chipselects supported */
+        void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
+        void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h
new file mode 100644
index 000000000000..1b3655090ed3
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx.h
@@ -0,0 +1,43 @@
+/*
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AU1XXX_H_
+#define _AU1XXX_H_
+
+#include <asm/mach-au1x00/au1000.h>
+
+#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
+    defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
+#include <asm/mach-db1x00/db1x00.h>
+
+#elif defined(CONFIG_MIPS_PB1550)
+#include <asm/mach-pb1x00/pb1550.h>
+
+#elif defined(CONFIG_MIPS_PB1200)
+#include <asm/mach-pb1x00/pb1200.h>
+
+#elif defined(CONFIG_MIPS_DB1200)
+#include <asm/mach-db1x00/db1200.h>
+
+#endif
+
+#endif /* _AU1XXX_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
new file mode 100644
index 000000000000..44a67bf05dc1
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -0,0 +1,386 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Include file for Alchemy Semiconductor's Au1550 Descriptor
+ *      Based DMA Controller.
+ *
+ * Copyright 2004 Embedded Edge, LLC
+ *      dan@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Specifics for the Au1xxx Descriptor-Based DMA Controller,
+ * first seen in the AU1550 part.
+ */
+#ifndef _AU1000_DBDMA_H_
+#define _AU1000_DBDMA_H_
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+/*
+ * The DMA base addresses.
+ * The channels are every 256 bytes (0x0100) from the channel 0 base.
+ * Interrupt status/enable is bits 15:0 for channels 15 to zero.
+ */
+#define DDMA_GLOBAL_BASE        0xb4003000
+#define DDMA_CHANNEL_BASE       0xb4002000
+
+typedef volatile struct dbdma_global {
+        u32     ddma_config;
+        u32     ddma_intstat;
+        u32     ddma_throttle;
+        u32     ddma_inten;
+} dbdma_global_t;
+
+/* General Configuration. */
+#define DDMA_CONFIG_AF          (1 << 2)
+#define DDMA_CONFIG_AH          (1 << 1)
+#define DDMA_CONFIG_AL          (1 << 0)
+
+#define DDMA_THROTTLE_EN        (1 << 31)
+
+/* The structure of a DMA Channel. */
+typedef volatile struct au1xxx_dma_channel {
+        u32     ddma_cfg;       /* See below */
+        u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
+        u32     ddma_statptr;   /* word aligned pointer to status word */
+        u32     ddma_dbell;     /* A write activates channel operation */
+        u32     ddma_irq;       /* If bit 0 set, interrupt pending */
+        u32     ddma_stat;      /* See below */
+        u32     ddma_bytecnt;   /* Byte count, valid only when chan idle */
+        /* Remainder, up to the 256 byte boundary, is reserved. */
+} au1x_dma_chan_t;
+
+#define DDMA_CFG_SED    (1 << 9)        /* source DMA level/edge detect */
+#define DDMA_CFG_SP     (1 << 8)        /* source DMA polarity */
+#define DDMA_CFG_DED    (1 << 7)        /* destination DMA level/edge detect */
+#define DDMA_CFG_DP     (1 << 6)        /* destination DMA polarity */
+#define DDMA_CFG_SYNC   (1 << 5)        /* Sync static bus controller */
+#define DDMA_CFG_PPR    (1 << 4)        /* PCI posted read/write control */
+#define DDMA_CFG_DFN    (1 << 3)        /* Descriptor fetch non-coherent */
+#define DDMA_CFG_SBE    (1 << 2)        /* Source big endian */
+#define DDMA_CFG_DBE    (1 << 1)        /* Destination big endian */
+#define DDMA_CFG_EN     (1 << 0)        /* Channel enable */
+
+/*
+ * Always set when descriptor processing done, regardless of
+ * interrupt enable state.  Reflected in global intstat, don't
+ * clear this until global intstat is read/used.
+ */
+#define DDMA_IRQ_IN     (1 << 0)
+
+#define DDMA_STAT_DB    (1 << 2)        /* Doorbell pushed */
+#define DDMA_STAT_V     (1 << 1)        /* Descriptor valid */
+#define DDMA_STAT_H     (1 << 0)        /* Channel Halted */
+
+/*
+ * "Standard" DDMA Descriptor.
+ * Must be 32-byte aligned.
+ */
+typedef volatile struct au1xxx_ddma_desc {
+        u32     dscr_cmd0;              /* See below */
+        u32     dscr_cmd1;              /* See below */
+        u32     dscr_source0;           /* source phys address */
+        u32     dscr_source1;           /* See below */
+        u32     dscr_dest0;             /* Destination address */
+        u32     dscr_dest1;             /* See below */
+        u32     dscr_stat;              /* completion status */
+        u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
+        /*
+         * First 32 bytes are HW specific!!!
+         * Lets have some SW data following -- make sure it's 32 bytes.
+         */
+        u32     sw_status;
+        u32     sw_context;
+        u32     sw_reserved[6];
+} au1x_ddma_desc_t;
+
+#define DSCR_CMD0_V             (1 << 31)       /* Descriptor valid */
+#define DSCR_CMD0_MEM           (1 << 30)       /* mem-mem transfer */
+#define DSCR_CMD0_SID_MASK      (0x1f << 25)    /* Source ID */
+#define DSCR_CMD0_DID_MASK      (0x1f << 20)    /* Destination ID */
+#define DSCR_CMD0_SW_MASK       (0x3 << 18)     /* Source Width */
+#define DSCR_CMD0_DW_MASK       (0x3 << 16)     /* Destination Width */
+#define DSCR_CMD0_ARB           (0x1 << 15)     /* Set for Hi Pri */
+#define DSCR_CMD0_DT_MASK       (0x3 << 13)     /* Descriptor Type */
+#define DSCR_CMD0_SN            (0x1 << 12)     /* Source non-coherent */
+#define DSCR_CMD0_DN            (0x1 << 11)     /* Destination non-coherent */
+#define DSCR_CMD0_SM            (0x1 << 10)     /* Stride mode */
+#define DSCR_CMD0_IE            (0x1 << 8)      /* Interrupt Enable */
+#define DSCR_CMD0_SP            (0x1 << 4)      /* Status pointer select */
+#define DSCR_CMD0_CV            (0x1 << 2)      /* Clear Valid when done */
+#define DSCR_CMD0_ST_MASK       (0x3 << 0)      /* Status instruction */
+
+#define SW_STATUS_INUSE         (1 << 0)
+
+/* Command 0 device IDs. */
+#ifdef CONFIG_SOC_AU1550
+#define DSCR_CMD0_UART0_TX      0
+#define DSCR_CMD0_UART0_RX      1
+#define DSCR_CMD0_UART3_TX      2
+#define DSCR_CMD0_UART3_RX      3
+#define DSCR_CMD0_DMA_REQ0      4
+#define DSCR_CMD0_DMA_REQ1      5
+#define DSCR_CMD0_DMA_REQ2      6
+#define DSCR_CMD0_DMA_REQ3      7
+#define DSCR_CMD0_USBDEV_RX0    8
+#define DSCR_CMD0_USBDEV_TX0    9
+#define DSCR_CMD0_USBDEV_TX1    10
+#define DSCR_CMD0_USBDEV_TX2    11
+#define DSCR_CMD0_USBDEV_RX3    12
+#define DSCR_CMD0_USBDEV_RX4    13
+#define DSCR_CMD0_PSC0_TX       14
+#define DSCR_CMD0_PSC0_RX       15
+#define DSCR_CMD0_PSC1_TX       16
+#define DSCR_CMD0_PSC1_RX       17
+#define DSCR_CMD0_PSC2_TX       18
+#define DSCR_CMD0_PSC2_RX       19
+#define DSCR_CMD0_PSC3_TX       20
+#define DSCR_CMD0_PSC3_RX       21
+#define DSCR_CMD0_PCI_WRITE     22
+#define DSCR_CMD0_NAND_FLASH    23
+#define DSCR_CMD0_MAC0_RX       24
+#define DSCR_CMD0_MAC0_TX       25
+#define DSCR_CMD0_MAC1_RX       26
+#define DSCR_CMD0_MAC1_TX       27
+#endif /* CONFIG_SOC_AU1550 */
+
+#ifdef CONFIG_SOC_AU1200
+#define DSCR_CMD0_UART0_TX      0
+#define DSCR_CMD0_UART0_RX      1
+#define DSCR_CMD0_UART1_TX      2
+#define DSCR_CMD0_UART1_RX      3
+#define DSCR_CMD0_DMA_REQ0      4
+#define DSCR_CMD0_DMA_REQ1      5
+#define DSCR_CMD0_MAE_BE        6
+#define DSCR_CMD0_MAE_FE        7
+#define DSCR_CMD0_SDMS_TX0      8
+#define DSCR_CMD0_SDMS_RX0      9
+#define DSCR_CMD0_SDMS_TX1      10
+#define DSCR_CMD0_SDMS_RX1      11
+#define DSCR_CMD0_AES_TX        13
+#define DSCR_CMD0_AES_RX        12
+#define DSCR_CMD0_PSC0_TX       14
+#define DSCR_CMD0_PSC0_RX       15
+#define DSCR_CMD0_PSC1_TX       16
+#define DSCR_CMD0_PSC1_RX       17
+#define DSCR_CMD0_CIM_RXA       18
+#define DSCR_CMD0_CIM_RXB       19
+#define DSCR_CMD0_CIM_RXC       20
+#define DSCR_CMD0_MAE_BOTH      21
+#define DSCR_CMD0_LCD           22
+#define DSCR_CMD0_NAND_FLASH    23
+#define DSCR_CMD0_PSC0_SYNC     24
+#define DSCR_CMD0_PSC1_SYNC     25
+#define DSCR_CMD0_CIM_SYNC      26
+#endif /* CONFIG_SOC_AU1200 */
+
+#define DSCR_CMD0_THROTTLE      30
+#define DSCR_CMD0_ALWAYS        31
+#define DSCR_NDEV_IDS           32
+/* This macro is used to find/create custom device types */
+#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
+                                  ((d) & 0xFF))
+#define DSCR_CUSTOM2DEV_ID(x)   ((x) & 0xFF)
+
+#define DSCR_CMD0_SID(x)        (((x) & 0x1f) << 25)
+#define DSCR_CMD0_DID(x)        (((x) & 0x1f) << 20)
+
+/* Source/Destination transfer width. */
+#define DSCR_CMD0_BYTE          0
+#define DSCR_CMD0_HALFWORD      1
+#define DSCR_CMD0_WORD          2
+
+#define DSCR_CMD0_SW(x)         (((x) & 0x3) << 18)
+#define DSCR_CMD0_DW(x)         (((x) & 0x3) << 16)
+
+/* DDMA Descriptor Type. */
+#define DSCR_CMD0_STANDARD      0
+#define DSCR_CMD0_LITERAL       1
+#define DSCR_CMD0_CMP_BRANCH    2
+
+#define DSCR_CMD0_DT(x)         (((x) & 0x3) << 13)
+
+/* Status Instruction. */
+#define DSCR_CMD0_ST_NOCHANGE   0       /* Don't change */
+#define DSCR_CMD0_ST_CURRENT    1       /* Write current status */
+#define DSCR_CMD0_ST_CMD0       2       /* Write cmd0 with V cleared */
+#define DSCR_CMD0_ST_BYTECNT    3       /* Write remaining byte count */
+
+#define DSCR_CMD0_ST(x)         (((x) & 0x3) << 0)
+
+/* Descriptor Command 1. */
+#define DSCR_CMD1_SUPTR_MASK    (0xf << 28)     /* upper 4 bits of src addr */
+#define DSCR_CMD1_DUPTR_MASK    (0xf << 24)     /* upper 4 bits of dest addr */
+#define DSCR_CMD1_FL_MASK       (0x3 << 22)     /* Flag bits */
+#define DSCR_CMD1_BC_MASK       (0x3fffff)      /* Byte count */
+
+/* Flag description. */
+#define DSCR_CMD1_FL_MEM_STRIDE0        0
+#define DSCR_CMD1_FL_MEM_STRIDE1        1
+#define DSCR_CMD1_FL_MEM_STRIDE2        2
+
+#define DSCR_CMD1_FL(x)         (((x) & 0x3) << 22)
+
+/* Source1, 1-dimensional stride. */
+#define DSCR_SRC1_STS_MASK      (3 << 30)       /* Src xfer size */
+#define DSCR_SRC1_SAM_MASK      (3 << 28)       /* Src xfer movement */
+#define DSCR_SRC1_SB_MASK       (0x3fff << 14)  /* Block size */
+#define DSCR_SRC1_SB(x)         (((x) & 0x3fff) << 14)
+#define DSCR_SRC1_SS_MASK       (0x3fff << 0)   /* Stride */
+#define DSCR_SRC1_SS(x)         (((x) & 0x3fff) << 0)
+
+/* Dest1, 1-dimensional stride. */
+#define DSCR_DEST1_DTS_MASK     (3 << 30)       /* Dest xfer size */
+#define DSCR_DEST1_DAM_MASK     (3 << 28)       /* Dest xfer movement */
+#define DSCR_DEST1_DB_MASK      (0x3fff << 14)  /* Block size */
+#define DSCR_DEST1_DB(x)        (((x) & 0x3fff) << 14)
+#define DSCR_DEST1_DS_MASK      (0x3fff << 0)   /* Stride */
+#define DSCR_DEST1_DS(x)        (((x) & 0x3fff) << 0)
+
+#define DSCR_xTS_SIZE1          0
+#define DSCR_xTS_SIZE2          1
+#define DSCR_xTS_SIZE4          2
+#define DSCR_xTS_SIZE8          3
+#define DSCR_SRC1_STS(x)        (((x) & 3) << 30)
+#define DSCR_DEST1_DTS(x)       (((x) & 3) << 30)
+
+#define DSCR_xAM_INCREMENT      0
+#define DSCR_xAM_DECREMENT      1
+#define DSCR_xAM_STATIC         2
+#define DSCR_xAM_BURST          3
+#define DSCR_SRC1_SAM(x)        (((x) & 3) << 28)
+#define DSCR_DEST1_DAM(x)       (((x) & 3) << 28)
+
+/* The next descriptor pointer. */
+#define DSCR_NXTPTR_MASK        (0x07ffffff)
+#define DSCR_NXTPTR(x)          ((x) >> 5)
+#define DSCR_GET_NXTPTR(x)      ((x) << 5)
+#define DSCR_NXTPTR_MS          (1 << 27)
+
+/* The number of DBDMA channels. */
+#define NUM_DBDMA_CHANS 16
+
+/*
+ * DDMA API definitions
+ * FIXME: may not fit to this header file
+ */
+typedef struct dbdma_device_table {
+        u32     dev_id;
+        u32     dev_flags;
+        u32     dev_tsize;
+        u32     dev_devwidth;
+        u32     dev_physaddr;           /* If FIFO */
+        u32     dev_intlevel;
+        u32     dev_intpolarity;
+} dbdev_tab_t;
+
+
+typedef struct dbdma_chan_config {
+        spinlock_t      lock;
+
+        u32                     chan_flags;
+        u32                     chan_index;
+        dbdev_tab_t             *chan_src;
+        dbdev_tab_t             *chan_dest;
+        au1x_dma_chan_t         *chan_ptr;
+        au1x_ddma_desc_t        *chan_desc_base;
+        au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
+        void                    *chan_callparam;
+        void                    (*chan_callback)(int, void *);
+} chan_tab_t;
+
+#define DEV_FLAGS_INUSE         (1 << 0)
+#define DEV_FLAGS_ANYUSE        (1 << 1)
+#define DEV_FLAGS_OUT           (1 << 2)
+#define DEV_FLAGS_IN            (1 << 3)
+#define DEV_FLAGS_BURSTABLE     (1 << 4)
+#define DEV_FLAGS_SYNC          (1 << 5)
+/* end DDMA API definitions */
+
+/*
+ * External functions for drivers to use.
+ * Use this to allocate a DBDMA channel.  The device IDs are one of
+ * the DSCR_CMD0 devices IDs, which is usually redefined to a more
+ * meaningful name.  The 'callback' is called during DMA completion
+ * interrupt.
+ */
+extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
+                                   void (*callback)(int, void *),
+                                   void *callparam);
+
+#define DBDMA_MEM_CHAN  DSCR_CMD0_ALWAYS
+
+/* Set the device width of an in/out FIFO. */
+u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
+
+/* Allocate a ring of descriptors for DBDMA. */
+u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
+
+/* Put buffers on source/destination descriptors. */
+u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
+u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
+
+/* Get a buffer from the destination descriptor. */
+u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
+
+void au1xxx_dbdma_stop(u32 chanid);
+void au1xxx_dbdma_start(u32 chanid);
+void au1xxx_dbdma_reset(u32 chanid);
+u32 au1xxx_get_dma_residue(u32 chanid);
+
+void au1xxx_dbdma_chan_free(u32 chanid);
+void au1xxx_dbdma_dump(u32 chanid);
+
+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
+
+u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
+extern void au1xxx_ddma_del_device(u32 devid);
+void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
+
+/*
+ * Some compatibilty macros -- needed to make changes to API
+ * without breaking existing drivers.
+ */
+#define au1xxx_dbdma_put_source(chanid, buf, nbytes)                    \
+        _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)       \
+        _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
+#define put_source_flags(chanid, buf, nbytes, flags)                    \
+        au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
+
+#define au1xxx_dbdma_put_dest(chanid, buf, nbytes)                      \
+        _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)         \
+        _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
+#define put_dest_flags(chanid, buf, nbytes, flags)                      \
+        au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
+
+/*
+ *      Flags for the put_source/put_dest functions.
+ */
+#define DDMA_FLAGS_IE   (1 << 0)
+#define DDMA_FLAGS_NOIE (1 << 1)
+
+#endif /* _LANGUAGE_ASSEMBLY */
+#endif /* _AU1000_DBDMA_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
new file mode 100644
index 000000000000..60638b8969ba
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
@@ -0,0 +1,194 @@
+/*
+ * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00   Aug. 02 2005
+ *
+ * BRIEF MODULE DESCRIPTION
+ * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
+ *
+ * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
+ *       Interface and Linux Device Driver" Application Note.
+ */
+
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+#define DMA_WAIT_TIMEOUT        100
+#define NUM_DESCRIPTORS         PRD_ENTRIES
+#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
+#define NUM_DESCRIPTORS         2
+#endif
+
+#ifndef AU1XXX_ATA_RQSIZE
+#define AU1XXX_ATA_RQSIZE       128
+#endif
+
+/* Disable Burstable-Support for DBDMA */
+#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
+#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON  0
+#endif
+
+#ifdef CONFIG_PM
+/*
+ * This will enable the device to be powered up when write() or read()
+ * is called. If this is not defined, the driver will return -EBUSY.
+ */
+#define WAKE_ON_ACCESS 1
+
+typedef struct {
+        spinlock_t              lock;   /* Used to block on state transitions */
+        au1xxx_power_dev_t      *dev;   /* Power Managers device structure */
+        unsigned                stopped; /* Used to signal device is stopped */
+} pm_state;
+#endif
+
+typedef struct {
+        u32                     tx_dev_id, rx_dev_id, target_dev_id;
+        u32                     tx_chan, rx_chan;
+        void                    *tx_desc_head, *rx_desc_head;
+        ide_hwif_t              *hwif;
+#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
+        ide_drive_t             *drive;
+        struct dbdma_cmd        *dma_table_cpu;
+        dma_addr_t              dma_table_dma;
+#endif
+        int                     irq;
+        u32                     regbase;
+#ifdef CONFIG_PM
+        pm_state                pm;
+#endif
+} _auide_hwif;
+
+/******************************************************************************/
+/* PIO Mode timing calculation :                                              */
+/*                                                                            */
+/* Static Bus Spec   ATA Spec                                                 */
+/*      Tcsoe      =    t1                                                    */
+/*      Toecs      =    t9                                                    */
+/*      Twcs       =    t9                                                    */
+/*      Tcsh       =    t2i | t2                                              */
+/*      Tcsoff     =    t2i | t2                                              */
+/*      Twp        =    t2                                                    */
+/*      Tcsw       =    t1                                                    */
+/*      Tpm        =    0                                                     */
+/*      Ta         =    t1+t2                                                 */
+/******************************************************************************/
+
+#define TCSOE_MASK              (0x07 << 29)
+#define TOECS_MASK              (0x07 << 26)
+#define TWCS_MASK               (0x07 << 28)
+#define TCSH_MASK               (0x0F << 24)
+#define TCSOFF_MASK             (0x07 << 20)
+#define TWP_MASK                (0x3F << 14)
+#define TCSW_MASK               (0x0F << 10)
+#define TPM_MASK                (0x0F << 6)
+#define TA_MASK                 (0x3F << 0)
+#define TS_MASK                 (1 << 8)
+
+/* Timing parameters PIO mode 0 */
+#define SBC_IDE_PIO0_TCSOE      (0x04 << 29)
+#define SBC_IDE_PIO0_TOECS      (0x01 << 26)
+#define SBC_IDE_PIO0_TWCS       (0x02 << 28)
+#define SBC_IDE_PIO0_TCSH       (0x08 << 24)
+#define SBC_IDE_PIO0_TCSOFF     (0x07 << 20)
+#define SBC_IDE_PIO0_TWP        (0x10 << 14)
+#define SBC_IDE_PIO0_TCSW       (0x04 << 10)
+#define SBC_IDE_PIO0_TPM        (0x00 << 6)
+#define SBC_IDE_PIO0_TA         (0x15 << 0)
+/* Timing parameters PIO mode 1 */
+#define SBC_IDE_PIO1_TCSOE      (0x03 << 29)
+#define SBC_IDE_PIO1_TOECS      (0x01 << 26)
+#define SBC_IDE_PIO1_TWCS       (0x01 << 28)
+#define SBC_IDE_PIO1_TCSH       (0x06 << 24)
+#define SBC_IDE_PIO1_TCSOFF     (0x06 << 20)
+#define SBC_IDE_PIO1_TWP        (0x08 << 14)
+#define SBC_IDE_PIO1_TCSW       (0x03 << 10)
+#define SBC_IDE_PIO1_TPM        (0x00 << 6)
+#define SBC_IDE_PIO1_TA         (0x0B << 0)
+/* Timing parameters PIO mode 2 */
+#define SBC_IDE_PIO2_TCSOE      (0x05 << 29)
+#define SBC_IDE_PIO2_TOECS      (0x01 << 26)
+#define SBC_IDE_PIO2_TWCS       (0x01 << 28)
+#define SBC_IDE_PIO2_TCSH       (0x07 << 24)
+#define SBC_IDE_PIO2_TCSOFF     (0x07 << 20)
+#define SBC_IDE_PIO2_TWP        (0x1F << 14)
+#define SBC_IDE_PIO2_TCSW       (0x05 << 10)
+#define SBC_IDE_PIO2_TPM        (0x00 << 6)
+#define SBC_IDE_PIO2_TA         (0x22 << 0)
+/* Timing parameters PIO mode 3 */
+#define SBC_IDE_PIO3_TCSOE      (0x05 << 29)
+#define SBC_IDE_PIO3_TOECS      (0x01 << 26)
+#define SBC_IDE_PIO3_TWCS       (0x01 << 28)
+#define SBC_IDE_PIO3_TCSH       (0x0D << 24)
+#define SBC_IDE_PIO3_TCSOFF     (0x0D << 20)
+#define SBC_IDE_PIO3_TWP        (0x15 << 14)
+#define SBC_IDE_PIO3_TCSW       (0x05 << 10)
+#define SBC_IDE_PIO3_TPM        (0x00 << 6)
+#define SBC_IDE_PIO3_TA         (0x1A << 0)
+/* Timing parameters PIO mode 4 */
+#define SBC_IDE_PIO4_TCSOE      (0x04 << 29)
+#define SBC_IDE_PIO4_TOECS      (0x01 << 26)
+#define SBC_IDE_PIO4_TWCS       (0x01 << 28)
+#define SBC_IDE_PIO4_TCSH       (0x04 << 24)
+#define SBC_IDE_PIO4_TCSOFF     (0x04 << 20)
+#define SBC_IDE_PIO4_TWP        (0x0D << 14)
+#define SBC_IDE_PIO4_TCSW       (0x03 << 10)
+#define SBC_IDE_PIO4_TPM        (0x00 << 6)
+#define SBC_IDE_PIO4_TA         (0x12 << 0)
+/* Timing parameters MDMA mode 0 */
+#define SBC_IDE_MDMA0_TCSOE     (0x03 << 29)
+#define SBC_IDE_MDMA0_TOECS     (0x01 << 26)
+#define SBC_IDE_MDMA0_TWCS      (0x01 << 28)
+#define SBC_IDE_MDMA0_TCSH      (0x07 << 24)
+#define SBC_IDE_MDMA0_TCSOFF    (0x07 << 20)
+#define SBC_IDE_MDMA0_TWP       (0x0C << 14)
+#define SBC_IDE_MDMA0_TCSW      (0x03 << 10)
+#define SBC_IDE_MDMA0_TPM       (0x00 << 6)
+#define SBC_IDE_MDMA0_TA        (0x0F << 0)
+/* Timing parameters MDMA mode 1 */
+#define SBC_IDE_MDMA1_TCSOE     (0x05 << 29)
+#define SBC_IDE_MDMA1_TOECS     (0x01 << 26)
+#define SBC_IDE_MDMA1_TWCS      (0x01 << 28)
+#define SBC_IDE_MDMA1_TCSH      (0x05 << 24)
+#define SBC_IDE_MDMA1_TCSOFF    (0x05 << 20)
+#define SBC_IDE_MDMA1_TWP       (0x0F << 14)
+#define SBC_IDE_MDMA1_TCSW      (0x05 << 10)
+#define SBC_IDE_MDMA1_TPM       (0x00 << 6)
+#define SBC_IDE_MDMA1_TA        (0x15 << 0)
+/* Timing parameters MDMA mode 2 */
+#define SBC_IDE_MDMA2_TCSOE     (0x04 << 29)
+#define SBC_IDE_MDMA2_TOECS     (0x01 << 26)
+#define SBC_IDE_MDMA2_TWCS      (0x01 << 28)
+#define SBC_IDE_MDMA2_TCSH      (0x04 << 24)
+#define SBC_IDE_MDMA2_TCSOFF    (0x04 << 20)
+#define SBC_IDE_MDMA2_TWP       (0x0D << 14)
+#define SBC_IDE_MDMA2_TCSW      (0x04 << 10)
+#define SBC_IDE_MDMA2_TPM       (0x00 << 6)
+#define SBC_IDE_MDMA2_TA        (0x12 << 0)
+
+#define SBC_IDE_TIMING(mode) \
+        (SBC_IDE_##mode##_TWCS | \
+         SBC_IDE_##mode##_TCSH | \
+         SBC_IDE_##mode##_TCSOFF | \
+         SBC_IDE_##mode##_TWP | \
+         SBC_IDE_##mode##_TCSW | \
+         SBC_IDE_##mode##_TPM | \
+         SBC_IDE_##mode##_TA)
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
new file mode 100644
index 000000000000..892b7f168eb4
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -0,0 +1,505 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Include file for Alchemy Semiconductor's Au1k CPU.
+ *
+ * Copyright 2004 Embedded Edge, LLC
+ *      dan@embeddededge.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* Specifics for the Au1xxx Programmable Serial Controllers, first
+ * seen in the AU1550 part.
+ */
+#ifndef _AU1000_PSC_H_
+#define _AU1000_PSC_H_
+
+/* The PSC base addresses.  */
+#ifdef CONFIG_SOC_AU1550
+#define PSC0_BASE_ADDR          0xb1a00000
+#define PSC1_BASE_ADDR          0xb1b00000
+#define PSC2_BASE_ADDR          0xb0a00000
+#define PSC3_BASE_ADDR          0xb0b00000
+#endif
+
+#ifdef CONFIG_SOC_AU1200
+#define PSC0_BASE_ADDR          0xb1a00000
+#define PSC1_BASE_ADDR          0xb1b00000
+#endif
+
+/*
+ * The PSC select and control registers are common to all protocols.
+ */
+#define PSC_SEL_OFFSET          0x00000000
+#define PSC_CTRL_OFFSET         0x00000004
+
+#define PSC_SEL_CLK_MASK        (3 << 4)
+#define PSC_SEL_CLK_INTCLK      (0 << 4)
+#define PSC_SEL_CLK_EXTCLK      (1 << 4)
+#define PSC_SEL_CLK_SERCLK      (2 << 4)
+
+#define PSC_SEL_PS_MASK         0x00000007
+#define PSC_SEL_PS_DISABLED     0
+#define PSC_SEL_PS_SPIMODE      2
+#define PSC_SEL_PS_I2SMODE      3
+#define PSC_SEL_PS_AC97MODE     4
+#define PSC_SEL_PS_SMBUSMODE    5
+
+#define PSC_CTRL_DISABLE        0
+#define PSC_CTRL_SUSPEND        2
+#define PSC_CTRL_ENABLE         3
+
+/* AC97 Registers. */
+#define PSC_AC97CFG_OFFSET      0x00000008
+#define PSC_AC97MSK_OFFSET      0x0000000c
+#define PSC_AC97PCR_OFFSET      0x00000010
+#define PSC_AC97STAT_OFFSET     0x00000014
+#define PSC_AC97EVNT_OFFSET     0x00000018
+#define PSC_AC97TXRX_OFFSET     0x0000001c
+#define PSC_AC97CDC_OFFSET      0x00000020
+#define PSC_AC97RST_OFFSET      0x00000024
+#define PSC_AC97GPO_OFFSET      0x00000028
+#define PSC_AC97GPI_OFFSET      0x0000002c
+
+#define AC97_PSC_SEL            (AC97_PSC_BASE + PSC_SEL_OFFSET)
+#define AC97_PSC_CTRL           (AC97_PSC_BASE + PSC_CTRL_OFFSET)
+#define PSC_AC97CFG             (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
+#define PSC_AC97MSK             (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
+#define PSC_AC97PCR             (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
+#define PSC_AC97STAT            (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
+#define PSC_AC97EVNT            (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
+#define PSC_AC97TXRX            (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
+#define PSC_AC97CDC             (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
+#define PSC_AC97RST             (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
+#define PSC_AC97GPO             (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
+#define PSC_AC97GPI             (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
+
+/* AC97 Config Register. */
+#define PSC_AC97CFG_RT_MASK     (3 << 30)
+#define PSC_AC97CFG_RT_FIFO1    (0 << 30)
+#define PSC_AC97CFG_RT_FIFO2    (1 << 30)
+#define PSC_AC97CFG_RT_FIFO4    (2 << 30)
+#define PSC_AC97CFG_RT_FIFO8    (3 << 30)
+
+#define PSC_AC97CFG_TT_MASK     (3 << 28)
+#define PSC_AC97CFG_TT_FIFO1    (0 << 28)
+#define PSC_AC97CFG_TT_FIFO2    (1 << 28)
+#define PSC_AC97CFG_TT_FIFO4    (2 << 28)
+#define PSC_AC97CFG_TT_FIFO8    (3 << 28)
+
+#define PSC_AC97CFG_DD_DISABLE  (1 << 27)
+#define PSC_AC97CFG_DE_ENABLE   (1 << 26)
+#define PSC_AC97CFG_SE_ENABLE   (1 << 25)
+
+#define PSC_AC97CFG_LEN_MASK    (0xf << 21)
+#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
+#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
+#define PSC_AC97CFG_GE_ENABLE   (1)
+
+/* Enable slots 3-12. */
+#define PSC_AC97CFG_TXSLOT_ENA(x)       (1 << (((x) - 3) + 11))
+#define PSC_AC97CFG_RXSLOT_ENA(x)       (1 << (((x) - 3) + 1))
+
+/*
+ * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
+ * The only sensible numbers are 7, 9, or possibly 11.  Nah, just do the
+ * arithmetic in the macro.
+ */
+#define PSC_AC97CFG_SET_LEN(x)  (((((x) - 2) / 2) & 0xf) << 21)
+#define PSC_AC97CFG_GET_LEN(x)  (((((x) >> 21) & 0xf) * 2) + 2)
+
+/* AC97 Mask Register. */
+#define PSC_AC97MSK_GR          (1 << 25)
+#define PSC_AC97MSK_CD          (1 << 24)
+#define PSC_AC97MSK_RR          (1 << 13)
+#define PSC_AC97MSK_RO          (1 << 12)
+#define PSC_AC97MSK_RU          (1 << 11)
+#define PSC_AC97MSK_TR          (1 << 10)
+#define PSC_AC97MSK_TO          (1 << 9)
+#define PSC_AC97MSK_TU          (1 << 8)
+#define PSC_AC97MSK_RD          (1 << 5)
+#define PSC_AC97MSK_TD          (1 << 4)
+#define PSC_AC97MSK_ALLMASK     (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
+                                 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
+                                 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
+                                 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
+                                 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
+
+/* AC97 Protocol Control Register. */
+#define PSC_AC97PCR_RC          (1 << 6)
+#define PSC_AC97PCR_RP          (1 << 5)
+#define PSC_AC97PCR_RS          (1 << 4)
+#define PSC_AC97PCR_TC          (1 << 2)
+#define PSC_AC97PCR_TP          (1 << 1)
+#define PSC_AC97PCR_TS          (1 << 0)
+
+/* AC97 Status register (read only). */
+#define PSC_AC97STAT_CB         (1 << 26)
+#define PSC_AC97STAT_CP         (1 << 25)
+#define PSC_AC97STAT_CR         (1 << 24)
+#define PSC_AC97STAT_RF         (1 << 13)
+#define PSC_AC97STAT_RE         (1 << 12)
+#define PSC_AC97STAT_RR         (1 << 11)
+#define PSC_AC97STAT_TF         (1 << 10)
+#define PSC_AC97STAT_TE         (1 << 9)
+#define PSC_AC97STAT_TR         (1 << 8)
+#define PSC_AC97STAT_RB         (1 << 5)
+#define PSC_AC97STAT_TB         (1 << 4)
+#define PSC_AC97STAT_DI         (1 << 2)
+#define PSC_AC97STAT_DR         (1 << 1)
+#define PSC_AC97STAT_SR         (1 << 0)
+
+/* AC97 Event Register. */
+#define PSC_AC97EVNT_GR         (1 << 25)
+#define PSC_AC97EVNT_CD         (1 << 24)
+#define PSC_AC97EVNT_RR         (1 << 13)
+#define PSC_AC97EVNT_RO         (1 << 12)
+#define PSC_AC97EVNT_RU         (1 << 11)
+#define PSC_AC97EVNT_TR         (1 << 10)
+#define PSC_AC97EVNT_TO         (1 << 9)
+#define PSC_AC97EVNT_TU         (1 << 8)
+#define PSC_AC97EVNT_RD         (1 << 5)
+#define PSC_AC97EVNT_TD         (1 << 4)
+
+/* CODEC Command Register. */
+#define PSC_AC97CDC_RD          (1 << 25)
+#define PSC_AC97CDC_ID_MASK     (3 << 23)
+#define PSC_AC97CDC_INDX_MASK   (0x7f << 16)
+#define PSC_AC97CDC_ID(x)       (((x) & 0x03) << 23)
+#define PSC_AC97CDC_INDX(x)     (((x) & 0x7f) << 16)
+
+/* AC97 Reset Control Register. */
+#define PSC_AC97RST_RST         (1 << 1)
+#define PSC_AC97RST_SNC         (1 << 0)
+
+/* PSC in I2S Mode. */
+typedef struct  psc_i2s {
+        u32     psc_sel;
+        u32     psc_ctrl;
+        u32     psc_i2scfg;
+        u32     psc_i2smsk;
+        u32     psc_i2spcr;
+        u32     psc_i2sstat;
+        u32     psc_i2sevent;
+        u32     psc_i2stxrx;
+        u32     psc_i2sudf;
+} psc_i2s_t;
+
+#define PSC_I2SCFG_OFFSET       0x08
+#define PSC_I2SMASK_OFFSET      0x0C
+#define PSC_I2SPCR_OFFSET       0x10
+#define PSC_I2SSTAT_OFFSET      0x14
+#define PSC_I2SEVENT_OFFSET     0x18
+#define PSC_I2SRXTX_OFFSET      0x1C
+#define PSC_I2SUDF_OFFSET       0x20
+
+/* I2S Config Register. */
+#define PSC_I2SCFG_RT_MASK      (3 << 30)
+#define PSC_I2SCFG_RT_FIFO1     (0 << 30)
+#define PSC_I2SCFG_RT_FIFO2     (1 << 30)
+#define PSC_I2SCFG_RT_FIFO4     (2 << 30)
+#define PSC_I2SCFG_RT_FIFO8     (3 << 30)
+
+#define PSC_I2SCFG_TT_MASK      (3 << 28)
+#define PSC_I2SCFG_TT_FIFO1     (0 << 28)
+#define PSC_I2SCFG_TT_FIFO2     (1 << 28)
+#define PSC_I2SCFG_TT_FIFO4     (2 << 28)
+#define PSC_I2SCFG_TT_FIFO8     (3 << 28)
+
+#define PSC_I2SCFG_DD_DISABLE   (1 << 27)
+#define PSC_I2SCFG_DE_ENABLE    (1 << 26)
+#define PSC_I2SCFG_SET_WS(x)    (((((x) / 2) - 1) & 0x7f) << 16)
+#define PSC_I2SCFG_WS(n)        ((n & 0xFF) << 16)
+#define PSC_I2SCFG_WS_MASK      (PSC_I2SCFG_WS(0x3F))
+#define PSC_I2SCFG_WI           (1 << 15)
+
+#define PSC_I2SCFG_DIV_MASK     (3 << 13)
+#define PSC_I2SCFG_DIV2         (0 << 13)
+#define PSC_I2SCFG_DIV4         (1 << 13)
+#define PSC_I2SCFG_DIV8         (2 << 13)
+#define PSC_I2SCFG_DIV16        (3 << 13)
+
+#define PSC_I2SCFG_BI           (1 << 12)
+#define PSC_I2SCFG_BUF          (1 << 11)
+#define PSC_I2SCFG_MLJ          (1 << 10)
+#define PSC_I2SCFG_XM           (1 << 9)
+
+/* The word length equation is simply LEN+1. */
+#define PSC_I2SCFG_SET_LEN(x)   ((((x) - 1) & 0x1f) << 4)
+#define PSC_I2SCFG_GET_LEN(x)   ((((x) >> 4) & 0x1f) + 1)
+
+#define PSC_I2SCFG_LB           (1 << 2)
+#define PSC_I2SCFG_MLF          (1 << 1)
+#define PSC_I2SCFG_MS           (1 << 0)
+
+/* I2S Mask Register. */
+#define PSC_I2SMSK_RR           (1 << 13)
+#define PSC_I2SMSK_RO           (1 << 12)
+#define PSC_I2SMSK_RU           (1 << 11)
+#define PSC_I2SMSK_TR           (1 << 10)
+#define PSC_I2SMSK_TO           (1 << 9)
+#define PSC_I2SMSK_TU           (1 << 8)
+#define PSC_I2SMSK_RD           (1 << 5)
+#define PSC_I2SMSK_TD           (1 << 4)
+#define PSC_I2SMSK_ALLMASK      (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
+                                 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
+                                 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
+                                 PSC_I2SMSK_RD | PSC_I2SMSK_TD)
+
+/* I2S Protocol Control Register. */
+#define PSC_I2SPCR_RC           (1 << 6)
+#define PSC_I2SPCR_RP           (1 << 5)
+#define PSC_I2SPCR_RS           (1 << 4)
+#define PSC_I2SPCR_TC           (1 << 2)
+#define PSC_I2SPCR_TP           (1 << 1)
+#define PSC_I2SPCR_TS           (1 << 0)
+
+/* I2S Status register (read only). */
+#define PSC_I2SSTAT_RF          (1 << 13)
+#define PSC_I2SSTAT_RE          (1 << 12)
+#define PSC_I2SSTAT_RR          (1 << 11)
+#define PSC_I2SSTAT_TF          (1 << 10)
+#define PSC_I2SSTAT_TE          (1 << 9)
+#define PSC_I2SSTAT_TR          (1 << 8)
+#define PSC_I2SSTAT_RB          (1 << 5)
+#define PSC_I2SSTAT_TB          (1 << 4)
+#define PSC_I2SSTAT_DI          (1 << 2)
+#define PSC_I2SSTAT_DR          (1 << 1)
+#define PSC_I2SSTAT_SR          (1 << 0)
+
+/* I2S Event Register. */
+#define PSC_I2SEVNT_RR          (1 << 13)
+#define PSC_I2SEVNT_RO          (1 << 12)
+#define PSC_I2SEVNT_RU          (1 << 11)
+#define PSC_I2SEVNT_TR          (1 << 10)
+#define PSC_I2SEVNT_TO          (1 << 9)
+#define PSC_I2SEVNT_TU          (1 << 8)
+#define PSC_I2SEVNT_RD          (1 << 5)
+#define PSC_I2SEVNT_TD          (1 << 4)
+
+/* PSC in SPI Mode. */
+typedef struct  psc_spi {
+        u32     psc_sel;
+        u32     psc_ctrl;
+        u32     psc_spicfg;
+        u32     psc_spimsk;
+        u32     psc_spipcr;
+        u32     psc_spistat;
+        u32     psc_spievent;
+        u32     psc_spitxrx;
+} psc_spi_t;
+
+/* SPI Config Register. */
+#define PSC_SPICFG_RT_MASK      (3 << 30)
+#define PSC_SPICFG_RT_FIFO1     (0 << 30)
+#define PSC_SPICFG_RT_FIFO2     (1 << 30)
+#define PSC_SPICFG_RT_FIFO4     (2 << 30)
+#define PSC_SPICFG_RT_FIFO8     (3 << 30)
+
+#define PSC_SPICFG_TT_MASK      (3 << 28)
+#define PSC_SPICFG_TT_FIFO1     (0 << 28)
+#define PSC_SPICFG_TT_FIFO2     (1 << 28)
+#define PSC_SPICFG_TT_FIFO4     (2 << 28)
+#define PSC_SPICFG_TT_FIFO8     (3 << 28)
+
+#define PSC_SPICFG_DD_DISABLE   (1 << 27)
+#define PSC_SPICFG_DE_ENABLE    (1 << 26)
+#define PSC_SPICFG_CLR_BAUD(x)  ((x) & ~((0x3f) << 15))
+#define PSC_SPICFG_SET_BAUD(x)  (((x) & 0x3f) << 15)
+
+#define PSC_SPICFG_SET_DIV(x)   (((x) & 0x03) << 13)
+#define PSC_SPICFG_DIV2         0
+#define PSC_SPICFG_DIV4         1
+#define PSC_SPICFG_DIV8         2
+#define PSC_SPICFG_DIV16        3
+
+#define PSC_SPICFG_BI           (1 << 12)
+#define PSC_SPICFG_PSE          (1 << 11)
+#define PSC_SPICFG_CGE          (1 << 10)
+#define PSC_SPICFG_CDE          (1 << 9)
+
+#define PSC_SPICFG_CLR_LEN(x)   ((x) & ~((0x1f) << 4))
+#define PSC_SPICFG_SET_LEN(x)   (((x-1) & 0x1f) << 4)
+
+#define PSC_SPICFG_LB           (1 << 3)
+#define PSC_SPICFG_MLF          (1 << 1)
+#define PSC_SPICFG_MO           (1 << 0)
+
+/* SPI Mask Register. */
+#define PSC_SPIMSK_MM           (1 << 16)
+#define PSC_SPIMSK_RR           (1 << 13)
+#define PSC_SPIMSK_RO           (1 << 12)
+#define PSC_SPIMSK_RU           (1 << 11)
+#define PSC_SPIMSK_TR           (1 << 10)
+#define PSC_SPIMSK_TO           (1 << 9)
+#define PSC_SPIMSK_TU           (1 << 8)
+#define PSC_SPIMSK_SD           (1 << 5)
+#define PSC_SPIMSK_MD           (1 << 4)
+#define PSC_SPIMSK_ALLMASK      (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
+                                 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
+                                 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
+                                 PSC_SPIMSK_MD)
+
+/* SPI Protocol Control Register. */
+#define PSC_SPIPCR_RC           (1 << 6)
+#define PSC_SPIPCR_SP           (1 << 5)
+#define PSC_SPIPCR_SS           (1 << 4)
+#define PSC_SPIPCR_TC           (1 << 2)
+#define PSC_SPIPCR_MS           (1 << 0)
+
+/* SPI Status register (read only). */
+#define PSC_SPISTAT_RF          (1 << 13)
+#define PSC_SPISTAT_RE          (1 << 12)
+#define PSC_SPISTAT_RR          (1 << 11)
+#define PSC_SPISTAT_TF          (1 << 10)
+#define PSC_SPISTAT_TE          (1 << 9)
+#define PSC_SPISTAT_TR          (1 << 8)
+#define PSC_SPISTAT_SB          (1 << 5)
+#define PSC_SPISTAT_MB          (1 << 4)
+#define PSC_SPISTAT_DI          (1 << 2)
+#define PSC_SPISTAT_DR          (1 << 1)
+#define PSC_SPISTAT_SR          (1 << 0)
+
+/* SPI Event Register. */
+#define PSC_SPIEVNT_MM          (1 << 16)
+#define PSC_SPIEVNT_RR          (1 << 13)
+#define PSC_SPIEVNT_RO          (1 << 12)
+#define PSC_SPIEVNT_RU          (1 << 11)
+#define PSC_SPIEVNT_TR          (1 << 10)
+#define PSC_SPIEVNT_TO          (1 << 9)
+#define PSC_SPIEVNT_TU          (1 << 8)
+#define PSC_SPIEVNT_SD          (1 << 5)
+#define PSC_SPIEVNT_MD          (1 << 4)
+
+/* Transmit register control. */
+#define PSC_SPITXRX_LC          (1 << 29)
+#define PSC_SPITXRX_SR          (1 << 28)
+
+/* PSC in SMBus (I2C) Mode. */
+typedef struct  psc_smb {
+        u32     psc_sel;
+        u32     psc_ctrl;
+        u32     psc_smbcfg;
+        u32     psc_smbmsk;
+        u32     psc_smbpcr;
+        u32     psc_smbstat;
+        u32     psc_smbevnt;
+        u32     psc_smbtxrx;
+        u32     psc_smbtmr;
+} psc_smb_t;
+
+/* SMBus Config Register. */
+#define PSC_SMBCFG_RT_MASK      (3 << 30)
+#define PSC_SMBCFG_RT_FIFO1     (0 << 30)
+#define PSC_SMBCFG_RT_FIFO2     (1 << 30)
+#define PSC_SMBCFG_RT_FIFO4     (2 << 30)
+#define PSC_SMBCFG_RT_FIFO8     (3 << 30)
+
+#define PSC_SMBCFG_TT_MASK      (3 << 28)
+#define PSC_SMBCFG_TT_FIFO1     (0 << 28)
+#define PSC_SMBCFG_TT_FIFO2     (1 << 28)
+#define PSC_SMBCFG_TT_FIFO4     (2 << 28)
+#define PSC_SMBCFG_TT_FIFO8     (3 << 28)
+
+#define PSC_SMBCFG_DD_DISABLE   (1 << 27)
+#define PSC_SMBCFG_DE_ENABLE    (1 << 26)
+
+#define PSC_SMBCFG_SET_DIV(x)   (((x) & 0x03) << 13)
+#define PSC_SMBCFG_DIV2         0
+#define PSC_SMBCFG_DIV4         1
+#define PSC_SMBCFG_DIV8         2
+#define PSC_SMBCFG_DIV16        3
+
+#define PSC_SMBCFG_GCE          (1 << 9)
+#define PSC_SMBCFG_SFM          (1 << 8)
+
+#define PSC_SMBCFG_SET_SLV(x)   (((x) & 0x7f) << 1)
+
+/* SMBus Mask Register. */
+#define PSC_SMBMSK_DN           (1 << 30)
+#define PSC_SMBMSK_AN           (1 << 29)
+#define PSC_SMBMSK_AL           (1 << 28)
+#define PSC_SMBMSK_RR           (1 << 13)
+#define PSC_SMBMSK_RO           (1 << 12)
+#define PSC_SMBMSK_RU           (1 << 11)
+#define PSC_SMBMSK_TR           (1 << 10)
+#define PSC_SMBMSK_TO           (1 << 9)
+#define PSC_SMBMSK_TU           (1 << 8)
+#define PSC_SMBMSK_SD           (1 << 5)
+#define PSC_SMBMSK_MD           (1 << 4)
+#define PSC_SMBMSK_ALLMASK      (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
+                                 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
+                                 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
+                                 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
+                                 PSC_SMBMSK_MD)
+
+/* SMBus Protocol Control Register. */
+#define PSC_SMBPCR_DC           (1 << 2)
+#define PSC_SMBPCR_MS           (1 << 0)
+
+/* SMBus Status register (read only). */
+#define PSC_SMBSTAT_BB          (1 << 28)
+#define PSC_SMBSTAT_RF          (1 << 13)
+#define PSC_SMBSTAT_RE          (1 << 12)
+#define PSC_SMBSTAT_RR          (1 << 11)
+#define PSC_SMBSTAT_TF          (1 << 10)
+#define PSC_SMBSTAT_TE          (1 << 9)
+#define PSC_SMBSTAT_TR          (1 << 8)
+#define PSC_SMBSTAT_SB          (1 << 5)
+#define PSC_SMBSTAT_MB          (1 << 4)
+#define PSC_SMBSTAT_DI          (1 << 2)
+#define PSC_SMBSTAT_DR          (1 << 1)
+#define PSC_SMBSTAT_SR          (1 << 0)
+
+/* SMBus Event Register. */
+#define PSC_SMBEVNT_DN          (1 << 30)
+#define PSC_SMBEVNT_AN          (1 << 29)
+#define PSC_SMBEVNT_AL          (1 << 28)
+#define PSC_SMBEVNT_RR          (1 << 13)
+#define PSC_SMBEVNT_RO          (1 << 12)
+#define PSC_SMBEVNT_RU          (1 << 11)
+#define PSC_SMBEVNT_TR          (1 << 10)
+#define PSC_SMBEVNT_TO          (1 << 9)
+#define PSC_SMBEVNT_TU          (1 << 8)
+#define PSC_SMBEVNT_SD          (1 << 5)
+#define PSC_SMBEVNT_MD          (1 << 4)
+#define PSC_SMBEVNT_ALLCLR      (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
+                                 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
+                                 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
+                                 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
+                                 PSC_SMBEVNT_MD)
+
+/* Transmit register control. */
+#define PSC_SMBTXRX_RSR         (1 << 28)
+#define PSC_SMBTXRX_STP         (1 << 29)
+#define PSC_SMBTXRX_DATAMASK    0xff
+
+/* SMBus protocol timers register. */
+#define PSC_SMBTMR_SET_TH(x)    (((x) & 0x03) << 30)
+#define PSC_SMBTMR_SET_PS(x)    (((x) & 0x1f) << 25)
+#define PSC_SMBTMR_SET_PU(x)    (((x) & 0x1f) << 20)
+#define PSC_SMBTMR_SET_SH(x)    (((x) & 0x1f) << 15)
+#define PSC_SMBTMR_SET_SU(x)    (((x) & 0x1f) << 10)
+#define PSC_SMBTMR_SET_CL(x)    (((x) & 0x1f) << 5)
+#define PSC_SMBTMR_SET_CH(x)    (((x) & 0x1f) << 0)
+
+#endif /* _AU1000_PSC_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
new file mode 100644
index 000000000000..2dc61e009a08
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -0,0 +1,69 @@
+#ifndef _AU1XXX_GPIO_H_
+#define _AU1XXX_GPIO_H_
+
+#include <linux/types.h>
+
+#define AU1XXX_GPIO_BASE        200
+
+struct au1x00_gpio2 {
+        u32     dir;
+        u32     reserved;
+        u32     output;
+        u32     pinstate;
+        u32     inten;
+        u32     enable;
+};
+
+extern int au1xxx_gpio_get_value(unsigned gpio);
+extern void au1xxx_gpio_set_value(unsigned gpio, int value);
+extern int au1xxx_gpio_direction_input(unsigned gpio);
+extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
+
+
+/* Wrappers for the arch-neutral GPIO API */
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        /* Not yet implemented */
+        return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+        /* Not yet implemented */
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+        return au1xxx_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        return au1xxx_gpio_direction_output(gpio, value);
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return au1xxx_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        au1xxx_gpio_set_value(gpio, value);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return gpio;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq;
+}
+
+/* For cansleep */
+#include <asm-generic/gpio.h>
+
+#endif /* _AU1XXX_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h
new file mode 100644
index 000000000000..364cea2dc71f
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/ioremap.h
@@ -0,0 +1,42 @@
+/*
+ *      include/asm-mips/mach-au1x00/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_AU1X00_IOREMAP_H
+#define __ASM_MACH_AU1X00_IOREMAP_H
+
+#include <linux/types.h>
+
+#ifdef CONFIG_64BIT_PHYS_ADDR
+extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
+#else
+static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+#endif
+
+/*
+ * Allow physical addresses to be fixed up to help 36-bit peripherals.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return __fixup_bigphys_addr(phys_addr, size);
+}
+
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return 0;
+}
+
+#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h
new file mode 100644
index 000000000000..e38715577c51
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/prom.h
@@ -0,0 +1,13 @@
+#ifndef __AU1X00_PROM_H
+#define __AU1X00_PROM_H
+
+extern int prom_argc;
+extern char **prom_argv;
+extern char **prom_envp;
+
+extern void prom_init_cmdline(void);
+extern char *prom_getcmdline(void);
+extern char *prom_getenv(char *envname);
+extern int prom_get_ethernet_addr(char *ethernet_addr);
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/war.h b/arch/mips/include/asm/mach-au1x00/war.h
new file mode 100644
index 000000000000..dd57d03d68ba
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H
+#define __ASM_MIPS_MACH_AU1X00_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
new file mode 100644
index 000000000000..d008f47a28bd
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef __ASM_BCM47XX_H
+#define __ASM_BCM47XX_H
+
+/* SSB bus */
+extern struct ssb_bus ssb_bcm47xx;
+
+#endif /* __ASM_BCM47XX_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
new file mode 100644
index 000000000000..cfc8f4d618ce
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
@@ -0,0 +1,59 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
+ */
+
+#ifndef __BCM47XX_GPIO_H
+#define __BCM47XX_GPIO_H
+
+#define BCM47XX_EXTIF_GPIO_LINES        5
+#define BCM47XX_CHIPCO_GPIO_LINES       16
+
+extern int bcm47xx_gpio_to_irq(unsigned gpio);
+extern int bcm47xx_gpio_get_value(unsigned gpio);
+extern void bcm47xx_gpio_set_value(unsigned gpio, int value);
+extern int bcm47xx_gpio_direction_input(unsigned gpio);
+extern int bcm47xx_gpio_direction_output(unsigned gpio, int value);
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+       return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return bcm47xx_gpio_to_irq(gpio);
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return bcm47xx_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        bcm47xx_gpio_set_value(gpio, value);
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+        return bcm47xx_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        return bcm47xx_gpio_direction_output(gpio, value);
+}
+
+
+/* cansleep wrappers */
+#include <asm-generic/gpio.h>
+
+#endif /* __BCM47XX_GPIO_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/war.h b/arch/mips/include/asm/mach-bcm47xx/war.h
new file mode 100644
index 000000000000..4a2b7986b582
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H
+#define __ASM_MIPS_MACH_BCM947XX_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-cobalt/cobalt.h b/arch/mips/include/asm/mach-cobalt/cobalt.h
new file mode 100644
index 000000000000..5b9fce73f11d
--- /dev/null
+++ b/arch/mips/include/asm/mach-cobalt/cobalt.h
@@ -0,0 +1,22 @@
+/*
+ * The Cobalt board ID information.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 Cobalt Microserver
+ * Copyright (C) 1997, 2003 Ralf Baechle
+ * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
+ */
+#ifndef __ASM_COBALT_H
+#define __ASM_COBALT_H
+
+extern int cobalt_board_id;
+
+#define COBALT_BRD_ID_QUBE1    0x3
+#define COBALT_BRD_ID_RAQ1     0x4
+#define COBALT_BRD_ID_QUBE2    0x5
+#define COBALT_BRD_ID_RAQ2     0x6
+
+#endif /* __ASM_COBALT_H */
diff --git a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
new file mode 100644
index 000000000000..b3314cf53194
--- /dev/null
+++ b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
+
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_fpu             1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_watch           0
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_inclusive_pcaches       0
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  0
+
+#ifdef CONFIG_64BIT
+#define cpu_has_llsc            0
+#else
+#define cpu_has_llsc            1
+#endif
+
+#define cpu_has_mips16          0
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+#define cpu_has_vtag_icache     0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_icache_snoops_remote_store  0
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-cobalt/irq.h b/arch/mips/include/asm/mach-cobalt/irq.h
new file mode 100644
index 000000000000..57c8c9ac5851
--- /dev/null
+++ b/arch/mips/include/asm/mach-cobalt/irq.h
@@ -0,0 +1,57 @@
+/*
+ * Cobalt IRQ definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 Cobalt Microserver
+ * Copyright (C) 1997, 2003 Ralf Baechle
+ * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
+ * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ */
+#ifndef _ASM_COBALT_IRQ_H
+#define _ASM_COBALT_IRQ_H
+
+/*
+ * i8259 interrupts used on Cobalt:
+ *
+ *      8  - RTC
+ *      9  - PCI slot
+ *      14 - IDE0
+ *      15 - IDE1(no connector on board)
+ */
+#define I8259A_IRQ_BASE                 0
+
+#define PCISLOT_IRQ                     (I8259A_IRQ_BASE + 9)
+
+/*
+ * CPU interrupts used on Cobalt:
+ *
+ *      0 - Software interrupt 0 (unused)
+ *      1 - Software interrupt 0 (unused)
+ *      2 - cascade GT64111
+ *      3 - ethernet or SCSI host controller
+ *      4 - ethernet
+ *      5 - 16550 UART
+ *      6 - cascade i8259
+ *      7 - CP0 counter
+ */
+#define MIPS_CPU_IRQ_BASE               16
+
+#define GT641XX_CASCADE_IRQ             (MIPS_CPU_IRQ_BASE + 2)
+#define RAQ2_SCSI_IRQ                   (MIPS_CPU_IRQ_BASE + 3)
+#define ETH0_IRQ                        (MIPS_CPU_IRQ_BASE + 3)
+#define QUBE1_ETH0_IRQ                  (MIPS_CPU_IRQ_BASE + 4)
+#define ETH1_IRQ                        (MIPS_CPU_IRQ_BASE + 4)
+#define SERIAL_IRQ                      (MIPS_CPU_IRQ_BASE + 5)
+#define SCSI_IRQ                        (MIPS_CPU_IRQ_BASE + 5)
+#define I8259_CASCADE_IRQ               (MIPS_CPU_IRQ_BASE + 6)
+
+#define GT641XX_IRQ_BASE                24
+
+#include <asm/irq_gt641xx.h>
+
+#define NR_IRQS                                 (GT641XX_PCI_INT3_IRQ + 1)
+
+#endif /* _ASM_COBALT_IRQ_H */
diff --git a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
new file mode 100644
index 000000000000..ae9c5523c7ef
--- /dev/null
+++ b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2006  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#ifndef _COBALT_MACH_GT64120_H
+#define _COBALT_MACH_GT64120_H
+
+/*
+ * Cobalt uses GT64111. GT64111 is almost the same as GT64120.
+ */
+
+#define GT64120_BASE    CKSEG1ADDR(GT_DEF_BASE)
+
+#endif /* _COBALT_MACH_GT64120_H */
diff --git a/arch/mips/include/asm/mach-cobalt/war.h b/arch/mips/include/asm/mach-cobalt/war.h
new file mode 100644
index 000000000000..97884fd18ac0
--- /dev/null
+++ b/arch/mips/include/asm/mach-cobalt/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_COBALT_WAR_H
+#define __ASM_MIPS_MACH_COBALT_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
new file mode 100644
index 000000000000..27f26102b1bb
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -0,0 +1,230 @@
+/*
+ * AMD Alchemy DBAu1200 Reference Board
+ * Board register defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_DB1200_H
+#define __ASM_DB1200_H
+
+#include <linux/types.h>
+#include <asm/mach-au1x00/au1xxx_psc.h>
+
+#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC1_RX
+
+/*
+ * SPI and SMB are muxed on the DBAu1200 board.
+ * Refer to board documentation.
+ */
+#define SPI_PSC_BASE            PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE          PSC0_BASE_ADDR
+/*
+ * AC'97 and I2S are muxed on the DBAu1200 board.
+ * Refer to board documentation.
+ */
+#define AC97_PSC_BASE           PSC1_BASE_ADDR
+#define I2S_PSC_BASE            PSC1_BASE_ADDR
+
+#define BCSR_KSEG1_ADDR         0xB9800000
+
+typedef volatile struct
+{
+        /*00*/  u16 whoami;
+                u16 reserved0;
+        /*04*/  u16 status;
+                u16 reserved1;
+        /*08*/  u16 switches;
+                u16 reserved2;
+        /*0C*/  u16 resets;
+                u16 reserved3;
+
+        /*10*/  u16 pcmcia;
+                u16 reserved4;
+        /*14*/  u16 board;
+                u16 reserved5;
+        /*18*/  u16 disk_leds;
+                u16 reserved6;
+        /*1C*/  u16 system;
+                u16 reserved7;
+
+        /*20*/  u16 intclr;
+                u16 reserved8;
+        /*24*/  u16 intset;
+                u16 reserved9;
+        /*28*/  u16 intclr_mask;
+                u16 reserved10;
+        /*2C*/  u16 intset_mask;
+                u16 reserved11;
+
+        /*30*/  u16 sig_status;
+                u16 reserved12;
+        /*34*/  u16 int_status;
+                u16 reserved13;
+        /*38*/  u16 reserved14;
+                u16 reserved15;
+        /*3C*/  u16 reserved16;
+                u16 reserved17;
+
+} BCSR;
+
+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID        0x000F
+#define BCSR_WHOAMI_CPLD        0x00F0
+#define BCSR_WHOAMI_BOARD       0x0F00
+
+#define BCSR_STATUS_PCMCIA0VS   0x0003
+#define BCSR_STATUS_PCMCIA1VS   0x000C
+#define BCSR_STATUS_SWAPBOOT    0x0040
+#define BCSR_STATUS_FLASHBUSY   0x0100
+#define BCSR_STATUS_IDECBLID    0x0200
+#define BCSR_STATUS_SD0WP       0x0400
+#define BCSR_STATUS_U0RXD       0x1000
+#define BCSR_STATUS_U1RXD       0x2000
+
+#define BCSR_SWITCHES_OCTAL     0x00FF
+#define BCSR_SWITCHES_DIP_1     0x0080
+#define BCSR_SWITCHES_DIP_2     0x0040
+#define BCSR_SWITCHES_DIP_3     0x0020
+#define BCSR_SWITCHES_DIP_4     0x0010
+#define BCSR_SWITCHES_DIP_5     0x0008
+#define BCSR_SWITCHES_DIP_6     0x0004
+#define BCSR_SWITCHES_DIP_7     0x0002
+#define BCSR_SWITCHES_DIP_8     0x0001
+#define BCSR_SWITCHES_ROTARY    0x0F00
+
+#define BCSR_RESETS_ETH         0x0001
+#define BCSR_RESETS_CAMERA      0x0002
+#define BCSR_RESETS_DC          0x0004
+#define BCSR_RESETS_IDE         0x0008
+#define BCSR_RESETS_TV          0x0010
+/* Not resets but in the same register */
+#define BCSR_RESETS_PWMR1MUX    0x0800
+#define BCSR_RESETS_PCS0MUX     0x1000
+#define BCSR_RESETS_PCS1MUX     0x2000
+#define BCSR_RESETS_SPISEL      0x4000
+
+#define BCSR_PCMCIA_PC0VPP      0x0003
+#define BCSR_PCMCIA_PC0VCC      0x000C
+#define BCSR_PCMCIA_PC0DRVEN    0x0010
+#define BCSR_PCMCIA_PC0RST      0x0080
+#define BCSR_PCMCIA_PC1VPP      0x0300
+#define BCSR_PCMCIA_PC1VCC      0x0C00
+#define BCSR_PCMCIA_PC1DRVEN    0x1000
+#define BCSR_PCMCIA_PC1RST      0x8000
+
+#define BCSR_BOARD_LCDVEE       0x0001
+#define BCSR_BOARD_LCDVDD       0x0002
+#define BCSR_BOARD_LCDBL        0x0004
+#define BCSR_BOARD_CAMSNAP      0x0010
+#define BCSR_BOARD_CAMPWR       0x0020
+#define BCSR_BOARD_SD0PWR       0x0040
+
+#define BCSR_LEDS_DECIMALS      0x0003
+#define BCSR_LEDS_LED0          0x0100
+#define BCSR_LEDS_LED1          0x0200
+#define BCSR_LEDS_LED2          0x0400
+#define BCSR_LEDS_LED3          0x0800
+
+#define BCSR_SYSTEM_POWEROFF    0x4000
+#define BCSR_SYSTEM_RESET       0x8000
+
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE            0x0001
+#define BCSR_INT_ETH            0x0002
+#define BCSR_INT_PC0            0x0004
+#define BCSR_INT_PC0STSCHG      0x0008
+#define BCSR_INT_PC1            0x0010
+#define BCSR_INT_PC1STSCHG      0x0020
+#define BCSR_INT_DC             0x0040
+#define BCSR_INT_FLASHBUSY      0x0080
+#define BCSR_INT_PC0INSERT      0x0100
+#define BCSR_INT_PC0EJECT       0x0200
+#define BCSR_INT_PC1INSERT      0x0400
+#define BCSR_INT_PC1EJECT       0x0800
+#define BCSR_INT_SD0INSERT      0x1000
+#define BCSR_INT_SD0EJECT       0x2000
+
+#define SMC91C111_PHYS_ADDR     0x19000300
+#define SMC91C111_INT           DB1200_ETH_INT
+
+#define IDE_PHYS_ADDR           0x18800000
+#define IDE_REG_SHIFT           5
+#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
+#define IDE_INT                 DB1200_IDE_INT
+#define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
+#define IDE_RQSIZE              128
+
+#define NAND_PHYS_ADDR          0x20000000
+
+/*
+ * External Interrupts for DBAu1200 as of 8/6/2004.
+ * Bit positions in the CPLD registers can be calculated by taking
+ * the interrupt define and subtracting the DB1200_INT_BEGIN value.
+ *
+ *   Example: IDE bis pos is  = 64 - 64
+ *            ETH bit pos is  = 65 - 64
+ */
+enum external_pb1200_ints {
+        DB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
+
+        DB1200_IDE_INT          = DB1200_INT_BEGIN,
+        DB1200_ETH_INT,
+        DB1200_PC0_INT,
+        DB1200_PC0_STSCHG_INT,
+        DB1200_PC1_INT,
+        DB1200_PC1_STSCHG_INT,
+        DB1200_DC_INT,
+        DB1200_FLASHBUSY_INT,
+        DB1200_PC0_INSERT_INT,
+        DB1200_PC0_EJECT_INT,
+        DB1200_PC1_INSERT_INT,
+        DB1200_PC1_EJECT_INT,
+        DB1200_SD0_INSERT_INT,
+        DB1200_SD0_EJECT_INT,
+
+        DB1200_INT_END          = DB1200_INT_BEGIN + 15,
+};
+
+
+/*
+ * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
+ */
+#define PCMCIA_MAX_SOCK  1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
+
+#define BOARD_PC0_INT   DB1200_PC0_INT
+#define BOARD_PC1_INT   DB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
+
+/* NAND chip select */
+#define NAND_CS 1
+
+#endif /* __ASM_DB1200_H */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
new file mode 100644
index 000000000000..1a515b8c870f
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -0,0 +1,179 @@
+/*
+ * AMD Alchemy DBAu1x00 Reference Boards
+ *
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_DB1X00_H
+#define __ASM_DB1X00_H
+
+#include <asm/mach-au1x00/au1xxx_psc.h>
+
+#ifdef CONFIG_MIPS_DB1550
+
+#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC3_RX
+
+#define SPI_PSC_BASE            PSC0_BASE_ADDR
+#define AC97_PSC_BASE           PSC1_BASE_ADDR
+#define SMBUS_PSC_BASE          PSC2_BASE_ADDR
+#define I2S_PSC_BASE            PSC3_BASE_ADDR
+
+#define BCSR_KSEG1_ADDR         0xAF000000
+#define NAND_PHYS_ADDR          0x20000000
+
+#else
+#define BCSR_KSEG1_ADDR 0xAE000000
+#endif
+
+/*
+ * Overlay data structure of the DBAu1x00 board registers.
+ * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
+ */
+typedef volatile struct
+{
+        /*00*/  unsigned short whoami;
+        unsigned short reserved0;
+        /*04*/  unsigned short status;
+        unsigned short reserved1;
+        /*08*/  unsigned short switches;
+        unsigned short reserved2;
+        /*0C*/  unsigned short resets;
+        unsigned short reserved3;
+        /*10*/  unsigned short pcmcia;
+        unsigned short reserved4;
+        /*14*/  unsigned short specific;
+        unsigned short reserved5;
+        /*18*/  unsigned short leds;
+        unsigned short reserved6;
+        /*1C*/  unsigned short swreset;
+        unsigned short reserved7;
+
+} BCSR;
+
+
+/*
+ * Register/mask bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID                0x000F
+#define BCSR_WHOAMI_CPLD                0x00F0
+#define BCSR_WHOAMI_BOARD               0x0F00
+
+#define BCSR_STATUS_PC0VS               0x0003
+#define BCSR_STATUS_PC1VS               0x000C
+#define BCSR_STATUS_PC0FI               0x0010
+#define BCSR_STATUS_PC1FI               0x0020
+#define BCSR_STATUS_FLASHBUSY           0x0100
+#define BCSR_STATUS_ROMBUSY             0x0400
+#define BCSR_STATUS_SWAPBOOT            0x2000
+#define BCSR_STATUS_FLASHDEN            0xC000
+
+#define BCSR_SWITCHES_DIP               0x00FF
+#define BCSR_SWITCHES_DIP_1             0x0080
+#define BCSR_SWITCHES_DIP_2             0x0040
+#define BCSR_SWITCHES_DIP_3             0x0020
+#define BCSR_SWITCHES_DIP_4             0x0010
+#define BCSR_SWITCHES_DIP_5             0x0008
+#define BCSR_SWITCHES_DIP_6             0x0004
+#define BCSR_SWITCHES_DIP_7             0x0002
+#define BCSR_SWITCHES_DIP_8             0x0001
+#define BCSR_SWITCHES_ROTARY            0x0F00
+
+#define BCSR_RESETS_PHY0                0x0001
+#define BCSR_RESETS_PHY1                0x0002
+#define BCSR_RESETS_DC                  0x0004
+#define BCSR_RESETS_FIR_SEL             0x2000
+#define BCSR_RESETS_IRDA_MODE_MASK      0xC000
+#define BCSR_RESETS_IRDA_MODE_FULL      0x0000
+#define BCSR_RESETS_IRDA_MODE_OFF       0x4000
+#define BCSR_RESETS_IRDA_MODE_2_3       0x8000
+#define BCSR_RESETS_IRDA_MODE_1_3       0xC000
+
+#define BCSR_PCMCIA_PC0VPP              0x0003
+#define BCSR_PCMCIA_PC0VCC              0x000C
+#define BCSR_PCMCIA_PC0DRVEN            0x0010
+#define BCSR_PCMCIA_PC0RST              0x0080
+#define BCSR_PCMCIA_PC1VPP              0x0300
+#define BCSR_PCMCIA_PC1VCC              0x0C00
+#define BCSR_PCMCIA_PC1DRVEN            0x1000
+#define BCSR_PCMCIA_PC1RST              0x8000
+
+#define BCSR_BOARD_PCIM66EN             0x0001
+#define BCSR_BOARD_SD0_PWR              0x0040
+#define BCSR_BOARD_SD1_PWR              0x0080
+#define BCSR_BOARD_PCIM33               0x0100
+#define BCSR_BOARD_GPIO200RST           0x0400
+#define BCSR_BOARD_PCICFG               0x1000
+#define BCSR_BOARD_SD0_WP               0x4000
+#define BCSR_BOARD_SD1_WP               0x8000
+
+#define BCSR_LEDS_DECIMALS              0x0003
+#define BCSR_LEDS_LED0                  0x0100
+#define BCSR_LEDS_LED1                  0x0200
+#define BCSR_LEDS_LED2                  0x0400
+#define BCSR_LEDS_LED3                  0x0800
+
+#define BCSR_SWRESET_RESET              0x0080
+
+/* PCMCIA DBAu1x00 specific defines */
+#define PCMCIA_MAX_SOCK  1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT)\
+        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
+
+/*
+ * NAND defines
+ *
+ * Timing values as described in databook, * ns value stripped of the
+ * lower 2 bits.
+ * These defines are here rather than an Au1550 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                (18 >> 2)
+#define NAND_T_PUL              (30 >> 2)
+#define NAND_T_SU               (30 >> 2)
+#define NAND_T_WH               (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+
+#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
+                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
+                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
+#define NAND_CS         1
+
+/* Should be done by YAMON */
+#define NAND_STCFG      0x00400005 /* 8-bit NAND */
+#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
+#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
+
+#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-dec/mc146818rtc.h b/arch/mips/include/asm/mach-dec/mc146818rtc.h
new file mode 100644
index 000000000000..6724e99e43e1
--- /dev/null
+++ b/arch/mips/include/asm/mach-dec/mc146818rtc.h
@@ -0,0 +1,43 @@
+/*
+ * RTC definitions for DECstation style attached Dallas DS1287 chip.
+ *
+ * Copyright (C) 1998, 2001 by Ralf Baechle
+ * Copyright (C) 1998 by Harald Koerfgen
+ * Copyright (C) 2002, 2005  Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_RTC_DEC_H
+#define __ASM_MIPS_DEC_RTC_DEC_H
+
+#include <linux/types.h>
+#include <asm/addrspace.h>
+#include <asm/dec/system.h>
+
+extern volatile u8 *dec_rtc_base;
+
+#define ARCH_RTC_LOCATION
+
+#define RTC_PORT(x)     CPHYSADDR((long)dec_rtc_base)
+#define RTC_IO_EXTENT   dec_kn_slot_size
+#define RTC_IOMAPPED    0
+#undef RTC_IRQ
+
+#define RTC_DEC_YEAR    0x3f    /* Where we store the real year on DECs.  */
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        return dec_rtc_base[addr * 4];
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        dec_rtc_base[addr * 4] = data;
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#endif /* __ASM_MIPS_DEC_RTC_DEC_H */
diff --git a/arch/mips/include/asm/mach-dec/war.h b/arch/mips/include/asm/mach-dec/war.h
new file mode 100644
index 000000000000..ca5e2ef909ad
--- /dev/null
+++ b/arch/mips/include/asm/mach-dec/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_DEC_WAR_H
+#define __ASM_MIPS_MACH_DEC_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_DEC_WAR_H */
diff --git a/arch/mips/include/asm/mach-emma2rh/irq.h b/arch/mips/include/asm/mach-emma2rh/irq.h
new file mode 100644
index 000000000000..5439eb856461
--- /dev/null
+++ b/arch/mips/include/asm/mach-emma2rh/irq.h
@@ -0,0 +1,15 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_EMMA2RH_IRQ_H
+#define __ASM_MACH_EMMA2RH_IRQ_H
+
+#define NR_IRQS 256
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
diff --git a/arch/mips/include/asm/mach-emma2rh/war.h b/arch/mips/include/asm/mach-emma2rh/war.h
new file mode 100644
index 000000000000..b660a4c30e6a
--- /dev/null
+++ b/arch/mips/include/asm/mach-emma2rh/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H
+#define __ASM_MIPS_MACH_EMMA2RH_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */
diff --git a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
new file mode 100644
index 000000000000..107104c3cd12
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
@@ -0,0 +1,48 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
+ * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Basler eXcite has an RM9122 processor.
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_icache_snoops_remote_store  0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h
new file mode 100644
index 000000000000..4c29ba44992c
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/excite.h
@@ -0,0 +1,154 @@
+#ifndef __EXCITE_H__
+#define __EXCITE_H__
+
+#include <linux/init.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+
+#define EXCITE_CPU_EXT_CLOCK 100000000
+
+#if !defined(__ASSEMBLY__)
+void __init excite_kgdb_init(void);
+void excite_procfs_init(void);
+extern unsigned long memsize;
+extern char modetty[];
+extern u32 unit_id;
+#endif
+
+/* Base name for XICAP devices */
+#define XICAP_NAME      "xicap_gpi"
+
+/* OCD register offsets */
+#define LKB0            0x0038
+#define LKB5            0x0128
+#define LKM5            0x012C
+#define LKB7            0x0138
+#define LKM7            0x013c
+#define LKB8            0x0140
+#define LKM8            0x0144
+#define LKB9            0x0148
+#define LKM9            0x014c
+#define LKB10           0x0150
+#define LKM10           0x0154
+#define LKB11           0x0158
+#define LKM11           0x015c
+#define LKB12           0x0160
+#define LKM12           0x0164
+#define LKB13           0x0168
+#define LKM13           0x016c
+#define LDP0            0x0200
+#define LDP1            0x0210
+#define LDP2            0x0220
+#define LDP3            0x0230
+#define INTPIN0         0x0A40
+#define INTPIN1         0x0A44
+#define INTPIN2         0x0A48
+#define INTPIN3         0x0A4C
+#define INTPIN4         0x0A50
+#define INTPIN5         0x0A54
+#define INTPIN6         0x0A58
+#define INTPIN7         0x0A5C
+
+
+
+
+/* TITAN register offsets */
+#define CPRR            0x0004
+#define CPDSR           0x0008
+#define CPTC0R          0x000c
+#define CPTC1R          0x0010
+#define CPCFG0          0x0020
+#define CPCFG1          0x0024
+#define CPDST0A         0x0028
+#define CPDST0B         0x002c
+#define CPDST1A         0x0030
+#define CPDST1B         0x0034
+#define CPXDSTA         0x0038
+#define CPXDSTB         0x003c
+#define CPXCISRA        0x0048
+#define CPXCISRB        0x004c
+#define CPGIG0ER        0x0050
+#define CPGIG1ER        0x0054
+#define CPGRWL          0x0068
+#define CPURSLMT        0x00f8
+#define UACFG           0x0200
+#define UAINTS          0x0204
+#define SDRXFCIE        0x4828
+#define SDTXFCIE        0x4928
+#define INTP0Status0    0x1B00
+#define INTP0Mask0      0x1B04
+#define INTP0Set0       0x1B08
+#define INTP0Clear0     0x1B0C
+#define GXCFG           0x5000
+#define GXDMADRPFX      0x5018
+#define GXDMA_DESCADR   0x501c
+#define GXCH0TDESSTRT   0x5054
+
+/* IRQ definitions */
+#define NMICONFIG               0xac0
+#define TITAN_MSGINT    0xc4
+#define TITAN_IRQ       ((TITAN_MSGINT / 0x20) + 2)
+#define FPGA0_MSGINT    0x5a
+#define FPGA0_IRQ       ((FPGA0_MSGINT / 0x20) + 2)
+#define FPGA1_MSGINT    0x7b
+#define FPGA1_IRQ       ((FPGA1_MSGINT / 0x20) + 2)
+#define PHY_MSGINT      0x9c
+#define PHY_IRQ         ((PHY_MSGINT   / 0x20) + 2)
+
+#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
+/* Pre-release units used interrupt pin #9 */
+#define USB_IRQ         11
+#else
+/* Re-designed units use interrupt pin #1 */
+#define USB_MSGINT      0x39
+#define USB_IRQ         ((USB_MSGINT / 0x20) + 2)
+#endif
+#define TIMER_IRQ       12
+
+
+/* Device address ranges */
+#define EXCITE_OFFS_OCD         0x1fffc000
+#define EXCITE_SIZE_OCD         (16 * 1024)
+#define EXCITE_PHYS_OCD         CPHYSADDR(EXCITE_OFFS_OCD)
+#define EXCITE_ADDR_OCD         CKSEG1ADDR(EXCITE_OFFS_OCD)
+
+#define EXCITE_OFFS_SCRAM       0x1fffa000
+#define EXCITE_SIZE_SCRAM       (8 << 10)
+#define EXCITE_PHYS_SCRAM       CPHYSADDR(EXCITE_OFFS_SCRAM)
+#define EXCITE_ADDR_SCRAM       CKSEG1ADDR(EXCITE_OFFS_SCRAM)
+
+#define EXCITE_OFFS_PCI_IO      0x1fff8000
+#define EXCITE_SIZE_PCI_IO      (8 << 10)
+#define EXCITE_PHYS_PCI_IO      CPHYSADDR(EXCITE_OFFS_PCI_IO)
+#define EXCITE_ADDR_PCI_IO      CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
+
+#define EXCITE_OFFS_TITAN       0x1fff0000
+#define EXCITE_SIZE_TITAN       (32 << 10)
+#define EXCITE_PHYS_TITAN       CPHYSADDR(EXCITE_OFFS_TITAN)
+#define EXCITE_ADDR_TITAN       CKSEG1ADDR(EXCITE_OFFS_TITAN)
+
+#define EXCITE_OFFS_PCI_MEM     0x1ffe0000
+#define EXCITE_SIZE_PCI_MEM     (64 << 10)
+#define EXCITE_PHYS_PCI_MEM     CPHYSADDR(EXCITE_OFFS_PCI_MEM)
+#define EXCITE_ADDR_PCI_MEM     CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
+
+#define EXCITE_OFFS_FPGA        0x1ffdc000
+#define EXCITE_SIZE_FPGA        (16 << 10)
+#define EXCITE_PHYS_FPGA        CPHYSADDR(EXCITE_OFFS_FPGA)
+#define EXCITE_ADDR_FPGA        CKSEG1ADDR(EXCITE_OFFS_FPGA)
+
+#define EXCITE_OFFS_NAND        0x1ffd8000
+#define EXCITE_SIZE_NAND        (16 << 10)
+#define EXCITE_PHYS_NAND        CPHYSADDR(EXCITE_OFFS_NAND)
+#define EXCITE_ADDR_NAND        CKSEG1ADDR(EXCITE_OFFS_NAND)
+
+#define EXCITE_OFFS_BOOTROM     0x1f000000
+#define EXCITE_SIZE_BOOTROM     (8 << 20)
+#define EXCITE_PHYS_BOOTROM     CPHYSADDR(EXCITE_OFFS_BOOTROM)
+#define EXCITE_ADDR_BOOTROM     CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
+
+/* FPGA address offsets */
+#define EXCITE_FPGA_DPR         0x0104  /* dual-ported ram */
+#define EXCITE_FPGA_SYSCTL      0x0200  /* system control register block */
+
+#endif /* __EXCITE_H__ */
diff --git a/arch/mips/include/asm/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h
new file mode 100644
index 000000000000..0a1ef69bece7
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/excite_fpga.h
@@ -0,0 +1,80 @@
+#ifndef EXCITE_FPGA_H_INCLUDED
+#define EXCITE_FPGA_H_INCLUDED
+
+
+/**
+ * Address alignment of the individual FPGA bytes.
+ * The address arrangement of the individual bytes of the FPGA is two
+ * byte aligned at the embedded MK2 platform.
+ */
+#ifdef EXCITE_CCI_FPGA_MK2
+typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
+#else
+typedef unsigned char excite_cci_fpga_align_t;
+#endif
+
+
+/**
+ * Size of Dual Ported RAM.
+ */
+#define EXCITE_DPR_SIZE 263
+
+
+/**
+ * Size of Reserved Status Fields in Dual Ported RAM.
+ */
+#define EXCITE_DPR_STATUS_SIZE 7
+
+
+
+/**
+ * FPGA.
+ * Hardware register layout of the FPGA interface. The FPGA must accessed
+ * byte wise solely.
+ * @see EXCITE_CCI_DPR_MK2
+ */
+typedef struct excite_fpga {
+
+        /**
+         * Dual Ported RAM.
+         */
+        excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
+
+        /**
+         * Status.
+         */
+        excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
+
+#ifdef EXCITE_CCI_FPGA_MK2
+        /**
+         * RM9000 Interrupt.
+         * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
+         */
+        excite_cci_fpga_align_t rm9k_int;
+#else
+        /**
+         * MK2 Interrupt.
+         * Write access initiates interrupt at the ARM processor of the MK2.
+         */
+        excite_cci_fpga_align_t mk2_int;
+
+        excite_cci_fpga_align_t gap[0x1000-0x10f];
+
+        /**
+         * IRQ Source/Acknowledge.
+         */
+        excite_cci_fpga_align_t rm9k_irq_src;
+
+        /**
+         * IRQ Mask.
+         * Set bits enable the related interrupt.
+         */
+        excite_cci_fpga_align_t rm9k_irq_mask;
+#endif
+
+
+} excite_fpga;
+
+
+
+#endif  /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/include/asm/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h
new file mode 100644
index 000000000000..c4cf6140622e
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/excite_nandflash.h
@@ -0,0 +1,7 @@
+#ifndef __EXCITE_NANDFLASH_H__
+#define __EXCITE_NANDFLASH_H__
+
+/* Resource names */
+#define EXCITE_NANDFLASH_RESOURCE_REGS  "excite_nandflash_regs"
+
+#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h
new file mode 100644
index 000000000000..94705a46f72e
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/rm9k_eth.h
@@ -0,0 +1,23 @@
+#if !defined(__RM9K_ETH_H__)
+#define __RM9K_ETH_H__
+
+#define RM9K_GE_NAME                    "rm9k_ge"
+
+/* Resource names */
+#define RM9K_GE_RESOURCE_MAC            "rm9k_ge_mac"
+#define RM9K_GE_RESOURCE_MSTAT          "rm9k_ge_mstat"
+#define RM9K_GE_RESOURCE_PKTPROC        "rm9k_ge_pktproc"
+#define RM9K_GE_RESOURCE_XDMA           "rm9k_ge_xdma"
+#define RM9K_GE_RESOURCE_FIFO_RX        "rm9k_ge_fifo_rx"
+#define RM9K_GE_RESOURCE_FIFO_TX        "rm9k_ge_fifo_tx"
+#define RM9K_GE_RESOURCE_FIFOMEM_RX     "rm9k_ge_fifo_memory_rx"
+#define RM9K_GE_RESOURCE_FIFOMEM_TX     "rm9k_ge_fifo_memory_tx"
+#define RM9K_GE_RESOURCE_PHY            "rm9k_ge_phy"
+#define RM9K_GE_RESOURCE_DMADESC_RX     "rm9k_ge_dmadesc_rx"
+#define RM9K_GE_RESOURCE_DMADESC_TX     "rm9k_ge_dmadesc_tx"
+#define RM9K_GE_RESOURCE_IRQ_MAIN       "rm9k_ge_irq_main"
+#define RM9K_GE_RESOURCE_IRQ_PHY        "rm9k_ge_irq_phy"
+#define RM9K_GE_RESOURCE_GPI_SLICE      "rm9k_ge_gpi_slice"
+#define RM9K_GE_RESOURCE_MDIO_CHANNEL   "rm9k_ge_mdio_channel"
+
+#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
new file mode 100644
index 000000000000..3fa3c08d2da7
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
@@ -0,0 +1,12 @@
+#ifndef __RM9K_WDT_H__
+#define __RM9K_WDT_H__
+
+/* Device name */
+#define WDT_NAME                "wdt_gpi"
+
+/* Resource names */
+#define WDT_RESOURCE_REGS       "excite_watchdog_regs"
+#define WDT_RESOURCE_IRQ        "excite_watchdog_irq"
+#define WDT_RESOURCE_COUNTER    "excite_watchdog_counter"
+
+#endif /* __RM9K_WDT_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
new file mode 100644
index 000000000000..009577734a8d
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
@@ -0,0 +1,16 @@
+#ifndef __EXCITE_XICAP_H__
+#define __EXCITE_XICAP_H__
+
+
+/* Resource names */
+#define XICAP_RESOURCE_FIFO_RX          "xicap_fifo_rx"
+#define XICAP_RESOURCE_FIFO_TX          "xicap_fifo_tx"
+#define XICAP_RESOURCE_XDMA             "xicap_xdma"
+#define XICAP_RESOURCE_DMADESC          "xicap_dmadesc"
+#define XICAP_RESOURCE_PKTPROC          "xicap_pktproc"
+#define XICAP_RESOURCE_IRQ              "xicap_irq"
+#define XICAP_RESOURCE_GPI_SLICE        "xicap_gpi_slice"
+#define XICAP_RESOURCE_FIFO_BLK         "xicap_fifo_blocks"
+#define XICAP_RESOURCE_PKT_STREAM       "xicap_pkt_stream"
+
+#endif /* __EXCITE_XICAP_H__ */
diff --git a/arch/mips/include/asm/mach-excite/war.h b/arch/mips/include/asm/mach-excite/war.h
new file mode 100644
index 000000000000..1f82180c1598
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H
+#define __ASM_MIPS_MACH_EXCITE_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             1
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */
diff --git a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
new file mode 100644
index 000000000000..7c185bb06f13
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+
+/* Intentionally empty file ...  */
+
+#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
new file mode 100644
index 000000000000..76e04e7feb84
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -0,0 +1,45 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
+ *
+ */
+#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
+#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
+
+struct device;
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+        size_t size)
+{
+        return virt_to_phys(addr);
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
+{
+        return page_to_phys(page);
+}
+
+static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+        return dma_addr;
+}
+
+static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+{
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+#ifdef CONFIG_DMA_COHERENT
+        return 1;
+#endif
+#ifdef CONFIG_DMA_NONCOHERENT
+        return 0;
+#endif
+}
+
+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
new file mode 100644
index 000000000000..001a8ce17c17
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -0,0 +1,139 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_FLOPPY_H
+#define __ASM_MACH_GENERIC_FLOPPY_H
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+
+#include <asm/bootinfo.h>
+#include <asm/cachectl.h>
+#include <asm/dma.h>
+#include <asm/floppy.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pgtable.h>
+
+/*
+ * How to access the FDC's registers.
+ */
+static inline unsigned char fd_inb(unsigned int port)
+{
+        return inb_p(port);
+}
+
+static inline void fd_outb(unsigned char value, unsigned int port)
+{
+        outb_p(value, port);
+}
+
+/*
+ * How to access the floppy DMA functions.
+ */
+static inline void fd_enable_dma(void)
+{
+        enable_dma(FLOPPY_DMA);
+}
+
+static inline void fd_disable_dma(void)
+{
+        disable_dma(FLOPPY_DMA);
+}
+
+static inline int fd_request_dma(void)
+{
+        return request_dma(FLOPPY_DMA, "floppy");
+}
+
+static inline void fd_free_dma(void)
+{
+        free_dma(FLOPPY_DMA);
+}
+
+static inline void fd_clear_dma_ff(void)
+{
+        clear_dma_ff(FLOPPY_DMA);
+}
+
+static inline void fd_set_dma_mode(char mode)
+{
+        set_dma_mode(FLOPPY_DMA, mode);
+}
+
+static inline void fd_set_dma_addr(char *addr)
+{
+        set_dma_addr(FLOPPY_DMA, (unsigned long) addr);
+}
+
+static inline void fd_set_dma_count(unsigned int count)
+{
+        set_dma_count(FLOPPY_DMA, count);
+}
+
+static inline int fd_get_dma_residue(void)
+{
+        return get_dma_residue(FLOPPY_DMA);
+}
+
+static inline void fd_enable_irq(void)
+{
+        enable_irq(FLOPPY_IRQ);
+}
+
+static inline void fd_disable_irq(void)
+{
+        disable_irq(FLOPPY_IRQ);
+}
+
+static inline int fd_request_irq(void)
+{
+        return request_irq(FLOPPY_IRQ, floppy_interrupt,
+                           IRQF_DISABLED, "floppy", NULL);
+}
+
+static inline void fd_free_irq(void)
+{
+        free_irq(FLOPPY_IRQ, NULL);
+}
+
+#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
+
+
+static inline unsigned long fd_getfdaddr1(void)
+{
+        return 0x3f0;
+}
+
+static inline unsigned long fd_dma_mem_alloc(unsigned long size)
+{
+        unsigned long mem;
+
+        mem = __get_dma_pages(GFP_KERNEL, get_order(size));
+
+        return mem;
+}
+
+static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
+{
+        free_pages(addr, get_order(size));
+}
+
+static inline unsigned long fd_drive_type(unsigned long n)
+{
+        if (n == 0)
+                return 4;       /* 3,5", 1.44mb */
+
+        return 0;
+}
+
+#endif /* __ASM_MACH_GENERIC_FLOPPY_H */
diff --git a/arch/mips/include/asm/mach-generic/gpio.h b/arch/mips/include/asm/mach-generic/gpio.h
new file mode 100644
index 000000000000..b4e70208da64
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/gpio.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_MACH_GENERIC_GPIO_H
+#define __ASM_MACH_GENERIC_GPIO_H
+
+#ifdef CONFIG_GPIOLIB
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#else
+int gpio_request(unsigned gpio, const char *label);
+void gpio_free(unsigned gpio);
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_value(unsigned gpio, int value);
+#endif
+int gpio_to_irq(unsigned gpio);
+int irq_to_gpio(unsigned irq);
+
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+
+#endif /* __ASM_MACH_GENERIC_GPIO_H */
diff --git a/arch/mips/include/asm/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h
new file mode 100644
index 000000000000..73008f7bdc93
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/ide.h
@@ -0,0 +1,167 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994-1996  Linus Torvalds & authors
+ *
+ * Copied from i386; many of the especially older MIPS or ISA-based platforms
+ * are basically identical.  Using this file probably implies i8259 PIC
+ * support in a system but the very least interrupt numbers 0 - 15 need to
+ * be put aside for legacy devices.
+ */
+#ifndef __ASM_MACH_GENERIC_IDE_H
+#define __ASM_MACH_GENERIC_IDE_H
+
+#ifdef __KERNEL__
+
+#include <linux/pci.h>
+#include <linux/stddef.h>
+#include <asm/processor.h>
+
+static __inline__ int ide_probe_legacy(void)
+{
+#ifdef CONFIG_PCI
+        struct pci_dev *dev;
+        /*
+         * This can be called on the ide_setup() path, super-early in
+         * boot.  But the down_read() will enable local interrupts,
+         * which can cause some machines to crash.  So here we detect
+         * and flag that situation and bail out early.
+         */
+        if (no_pci_devices())
+                return 0;
+        dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL);
+        if (dev)
+                goto found;
+        dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
+        if (dev)
+                goto found;
+        return 0;
+found:
+        pci_dev_put(dev);
+        return 1;
+#elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
+        return 1;
+#else
+        return 0;
+#endif
+}
+
+/* MIPS port and memory-mapped I/O string operations.  */
+static inline void __ide_flush_prologue(void)
+{
+#ifdef CONFIG_SMP
+        if (cpu_has_dc_aliases)
+                preempt_disable();
+#endif
+}
+
+static inline void __ide_flush_epilogue(void)
+{
+#ifdef CONFIG_SMP
+        if (cpu_has_dc_aliases)
+                preempt_enable();
+#endif
+}
+
+static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
+{
+        if (cpu_has_dc_aliases) {
+                unsigned long end = addr + size;
+
+                while (addr < end) {
+                        local_flush_data_cache_page((void *)addr);
+                        addr += PAGE_SIZE;
+                }
+        }
+}
+
+/*
+ * insw() and gang might be called with interrupts disabled, so we can't
+ * send IPIs for flushing due to the potencial of deadlocks, see the comment
+ * above smp_call_function() in arch/mips/kernel/smp.c.  We work around the
+ * problem by disabling preemption so we know we actually perform the flush
+ * on the processor that actually has the lines to be flushed which hopefully
+ * is even better for performance anyway.
+ */
+static inline void __ide_insw(unsigned long port, void *addr,
+        unsigned int count)
+{
+        __ide_flush_prologue();
+        insw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
+{
+        __ide_flush_prologue();
+        insl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_outsw(unsigned long port, const void *addr,
+        unsigned long count)
+{
+        __ide_flush_prologue();
+        outsw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_outsl(unsigned long port, const void *addr,
+        unsigned long count)
+{
+        __ide_flush_prologue();
+        outsl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
+{
+        __ide_flush_prologue();
+        readsw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
+{
+        __ide_flush_prologue();
+        readsl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
+{
+        __ide_flush_prologue();
+        writesw(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 2);
+        __ide_flush_epilogue();
+}
+
+static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
+{
+        __ide_flush_prologue();
+        writesl(port, addr, count);
+        __ide_flush_dcache_range((unsigned long)addr, count * 4);
+        __ide_flush_epilogue();
+}
+
+/* ide_insw calls insw, not __ide_insw.  Why? */
+#undef insw
+#undef insl
+#undef outsw
+#undef outsl
+#define insw(port, addr, count) __ide_insw(port, addr, count)
+#define insl(port, addr, count) __ide_insl(port, addr, count)
+#define outsw(port, addr, count) __ide_outsw(port, addr, count)
+#define outsl(port, addr, count) __ide_outsl(port, addr, count)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_MACH_GENERIC_IDE_H */
diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h
new file mode 100644
index 000000000000..b379938d47f0
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/ioremap.h
@@ -0,0 +1,34 @@
+/*
+ *      include/asm-mips/mach-generic/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return 0;
+}
+
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
new file mode 100644
index 000000000000..70d9a25132c5
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -0,0 +1,45 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_IRQ_H
+#define __ASM_MACH_GENERIC_IRQ_H
+
+#ifndef NR_IRQS
+#define NR_IRQS 128
+#endif
+
+#ifdef CONFIG_I8259
+#ifndef I8259A_IRQ_BASE
+#define I8259A_IRQ_BASE 0
+#endif
+#endif
+
+#ifdef CONFIG_IRQ_CPU
+
+#ifndef MIPS_CPU_IRQ_BASE
+#ifdef CONFIG_I8259
+#define MIPS_CPU_IRQ_BASE 16
+#else
+#define MIPS_CPU_IRQ_BASE 0
+#endif /* CONFIG_I8259 */
+#endif
+
+#ifdef CONFIG_IRQ_CPU_RM7K
+#ifndef RM7K_CPU_IRQ_BASE
+#define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
+#endif
+#endif
+
+#ifdef CONFIG_IRQ_CPU_RM9K
+#ifndef RM9K_CPU_IRQ_BASE
+#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
+#endif
+#endif
+
+#endif /* CONFIG_IRQ_CPU */
+
+#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-generic/kernel-entry-init.h b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
new file mode 100644
index 000000000000..7e66505fa574
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/kernel-entry-init.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
+
+/* Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+.macro  kernel_entry_setup
+.endm
+
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+
+
+#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-generic/kmalloc.h b/arch/mips/include/asm/mach-generic/kmalloc.h
new file mode 100644
index 000000000000..b8e6deba352f
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/kmalloc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_MACH_GENERIC_KMALLOC_H
+#define __ASM_MACH_GENERIC_KMALLOC_H
+
+
+#ifndef CONFIG_DMA_COHERENT
+/*
+ * Total overkill for most systems but need as a safe default.
+ * Set this one if any device in the system might do non-coherent DMA.
+ */
+#define ARCH_KMALLOC_MINALIGN   128
+#endif
+
+#endif /* __ASM_MACH_GENERIC_KMALLOC_H */
diff --git a/arch/mips/include/asm/mach-generic/mangle-port.h b/arch/mips/include/asm/mach-generic/mangle-port.h
new file mode 100644
index 000000000000..f49dc990214b
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/mangle-port.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  (port)
+#define __swizzle_addr_w(port)  (port)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          le16_to_cpu(x)
+# define __mem_ioswabw(a, x)    (x)
+# define ioswabl(a, x)          le32_to_cpu(x)
+# define __mem_ioswabl(a, x)    (x)
+# define ioswabq(a, x)          le64_to_cpu(x)
+# define __mem_ioswabq(a, x)    (x)
+
+#else
+
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          (x)
+# define __mem_ioswabw(a, x)    cpu_to_le16(x)
+# define ioswabl(a, x)          (x)
+# define __mem_ioswabl(a, x)    cpu_to_le32(x)
+# define ioswabq(a, x)          (x)
+# define __mem_ioswabq(a, x)    cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-generic/mc146818rtc.h b/arch/mips/include/asm/mach-generic/mc146818rtc.h
new file mode 100644
index 000000000000..0b9a942f079d
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/mc146818rtc.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_GENERIC_MC146818RTC_H
+#define __ASM_MACH_GENERIC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        return inb_p(RTC_PORT(1));
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        outb_p(data, RTC_PORT(1));
+}
+
+#define RTC_ALWAYS_BCD  1
+
+#ifndef mc146818_decode_year
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
new file mode 100644
index 000000000000..c9fa4b14968d
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -0,0 +1,85 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_GENERIC_SPACES_H
+#define _ASM_MACH_GENERIC_SPACES_H
+
+#include <linux/const.h>
+
+/*
+ * This gives the physical RAM offset.
+ */
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET             _AC(0, UL)
+#endif
+
+#ifdef CONFIG_32BIT
+
+#define CAC_BASE                _AC(0x80000000, UL)
+#define IO_BASE                 _AC(0xa0000000, UL)
+#define UNCAC_BASE              _AC(0xa0000000, UL)
+
+#ifndef MAP_BASE
+#define MAP_BASE                _AC(0xc0000000, UL)
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START           _AC(0x20000000, UL)
+#endif
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#ifndef CAC_BASE
+#ifdef CONFIG_DMA_NONCOHERENT
+#define CAC_BASE                _AC(0x9800000000000000, UL)
+#else
+#define CAC_BASE                _AC(0xa800000000000000, UL)
+#endif
+#endif
+
+#ifndef IO_BASE
+#define IO_BASE                 _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef UNCAC_BASE
+#define UNCAC_BASE              _AC(0x9000000000000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#define MAP_BASE                _AC(0xc000000000000000, UL)
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ * Fixme: 59 bits is a fictive number and makes assumptions about processors
+ * in the distant future.  Nobody will care for a few years :-)
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START           (_AC(1, UL) << _AC(59, UL))
+#endif
+
+#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * This handles the memory map.
+ */
+#ifndef PAGE_OFFSET
+#define PAGE_OFFSET             (CAC_BASE + PHYS_OFFSET)
+#endif
+
+#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/include/asm/mach-generic/topology.h b/arch/mips/include/asm/mach-generic/topology.h
new file mode 100644
index 000000000000..5428f333a02c
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/topology.h
@@ -0,0 +1 @@
+#include <asm-generic/topology.h>
diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
new file mode 100644
index 000000000000..9c8735158da1
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 07 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * IP22 with a variety of processors so we can't use defaults for everything.
+ */
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+#define cpu_has_fpu             1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_cache_cdex_p    1
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0               /* Needs to change for R8000 */
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc   0
+
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip22/ds1286.h b/arch/mips/include/asm/mach-ip22/ds1286.h
new file mode 100644
index 000000000000..f19f1eafbc71
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/ds1286.h
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_IP22_DS1286_H
+#define __ASM_MACH_IP22_DS1286_H
+
+#include <asm/sgi/hpc3.h>
+
+#define rtc_read(reg)           (hpc3c0->rtcregs[(reg)] & 0xff)
+#define rtc_write(data, reg)    do { hpc3c0->rtcregs[(reg)] = (data); } while(0)
+
+#endif /* __ASM_MACH_IP22_DS1286_H */
diff --git a/arch/mips/include/asm/mach-ip22/spaces.h b/arch/mips/include/asm/mach-ip22/spaces.h
new file mode 100644
index 000000000000..7f9fa6f66059
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/spaces.h
@@ -0,0 +1,27 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP22_SPACES_H
+#define _ASM_MACH_IP22_SPACES_H
+
+
+#ifdef CONFIG_64BIT
+
+#define PAGE_OFFSET             0xffffffff80000000UL
+
+#define CAC_BASE                0xffffffff80000000
+#define IO_BASE                 0xffffffffa0000000
+#define UNCAC_BASE              0xffffffffa0000000
+#define MAP_BASE                0xc000000000000000
+
+#endif /* CONFIG_64BIT */
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
new file mode 100644
index 000000000000..a44fa9656a82
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -0,0 +1,29 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_IP22_WAR_H
+#define __ASM_MIPS_MACH_IP22_WAR_H
+
+/*
+ * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
+ */
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     1
+#define R4600_V1_HIT_CACHEOP_WAR        1
+#define R4600_V2_HIT_CACHEOP_WAR        1
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
new file mode 100644
index 000000000000..7d3112b148d9
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -0,0 +1,54 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 07 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * IP27 only comes with R10000 family processors all using the same config
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_icache_snoops_remote_store  1
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_6k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_8k_cache        0
+#define cpu_has_tx39_cache      0
+
+#define cpu_has_inclusive_pcaches       1
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  64
+#define cpu_scache_line_size()  128
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
new file mode 100644
index 000000000000..ed7e6222dc15
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -0,0 +1,50 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
+ *
+ */
+#ifndef __ASM_MACH_IP27_DMA_COHERENCE_H
+#define __ASM_MACH_IP27_DMA_COHERENCE_H
+
+#include <asm/pci/bridge.h>
+
+#define pdev_to_baddr(pdev, addr) \
+        (BRIDGE_CONTROLLER(pdev->bus)->baddr + (addr))
+#define dev_to_baddr(dev, addr) \
+        pdev_to_baddr(to_pci_dev(dev), (addr))
+
+struct device;
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+        size_t size)
+{
+        dma_addr_t pa = dev_to_baddr(dev, virt_to_phys(addr));
+
+        return pa;
+}
+
+static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+{
+        dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page));
+
+        return pa;
+}
+
+static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+        return dma_addr & ~(0xffUL << 56);
+}
+
+static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+{
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+        return 1;               /* IP27 non-cohernet mode is unsupported */
+}
+
+#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-ip27/irq.h b/arch/mips/include/asm/mach-ip27/irq.h
new file mode 100644
index 000000000000..cf4384bfa846
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/irq.h
@@ -0,0 +1,22 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 01, 02, 03 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2001 Kanoj Sarcar
+ */
+#ifndef __ASM_MACH_IP27_IRQ_H
+#define __ASM_MACH_IP27_IRQ_H
+
+/*
+ * A hardwired interrupt number is completly stupid for this system - a
+ * large configuration might have thousands if not tenthousands of
+ * interrupts.
+ */
+#define NR_IRQS 256
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_IP27_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
new file mode 100644
index 000000000000..624d66c7f290
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
@@ -0,0 +1,59 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H
+#define __ASM_MACH_IP27_KERNEL_ENTRY_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn0/hubni.h>
+#include <asm/sn/klkernvars.h>
+
+/*
+ * Returns the local nasid into res.
+ */
+        .macro GET_NASID_ASM res
+        dli     \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
+        ld      \res, (\res)
+        and     \res, NSRI_NODEID_MASK
+        dsrl    \res, NSRI_NODEID_SHFT
+        .endm
+
+/*
+ * Intentionally empty macro, used in head.S. Override in
+ * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
+ */
+        .macro  kernel_entry_setup
+        GET_NASID_ASM   t1
+        move            t2, t1                  # text and data are here
+        MAPPED_KERNEL_SETUP_TLB
+        .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+        .macro  smp_slave_setup
+        GET_NASID_ASM   t1
+        dli     t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
+                    KLDIR_OFF_POINTER + CAC_BASE
+        dsll    t1, NASID_SHFT
+        or      t0, t0, t1
+        ld      t0, 0(t0)                       # t0 points to kern_vars struct
+        lh      t1, KV_RO_NASID_OFFSET(t0)
+        lh      t2, KV_RW_NASID_OFFSET(t0)
+        MAPPED_KERNEL_SETUP_TLB
+
+        /*
+         * We might not get launched at the address the kernel is linked to,
+         * so we jump there.
+         */
+        PTR_LA  t0, 0f
+        jr      t0
+0:
+        .endm
+
+#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-ip27/kmalloc.h b/arch/mips/include/asm/mach-ip27/kmalloc.h
new file mode 100644
index 000000000000..426bd049b2d7
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/kmalloc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_MACH_IP27_KMALLOC_H
+#define __ASM_MACH_IP27_KMALLOC_H
+
+/*
+ * All happy, no need to define ARCH_KMALLOC_MINALIGN
+ */
+
+#endif /* __ASM_MACH_IP27_KMALLOC_H */
diff --git a/arch/mips/include/asm/mach-ip27/mangle-port.h b/arch/mips/include/asm/mach-ip27/mangle-port.h
new file mode 100644
index 000000000000..f6e4912ea062
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/mangle-port.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP27_MANGLE_PORT_H
+#define __ASM_MACH_IP27_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  (port)
+#define __swizzle_addr_w(port)  ((port) ^ 2)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          (x)
+# define __mem_ioswabw(a, x)    cpu_to_le16(x)
+# define ioswabl(a, x)          (x)
+# define __mem_ioswabl(a, x)    cpu_to_le32(x)
+# define ioswabq(a, x)          (x)
+# define __mem_ioswabq(a, x)    cpu_to_le32(x)
+
+#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h
new file mode 100644
index 000000000000..986a3b9b59a7
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/mmzone.h
@@ -0,0 +1,36 @@
+#ifndef _ASM_MACH_MMZONE_H
+#define _ASM_MACH_MMZONE_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/hub.h>
+
+#define pa_to_nid(addr)         NASID_TO_COMPACT_NODEID(NASID_GET(addr))
+
+#define LEVELS_PER_SLICE        128
+
+struct slice_data {
+        unsigned long irq_enable_mask[2];
+        int level_to_irq[LEVELS_PER_SLICE];
+};
+
+struct hub_data {
+        kern_vars_t     kern_vars;
+        DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
+        cpumask_t       h_cpus;
+        unsigned long slice_map;
+        unsigned long irq_alloc_mask[2];
+        struct slice_data slice[2];
+};
+
+struct node_data {
+        struct pglist_data pglist;
+        struct hub_data hub;
+};
+
+extern struct node_data *__node_data[];
+
+#define NODE_DATA(n)            (&__node_data[(n)]->pglist)
+#define hub_data(n)             (&__node_data[(n)]->hub)
+
+#endif /* _ASM_MACH_MMZONE_H */
diff --git a/arch/mips/include/asm/mach-ip27/spaces.h b/arch/mips/include/asm/mach-ip27/spaces.h
new file mode 100644
index 000000000000..b18802a0b17e
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/spaces.h
@@ -0,0 +1,30 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP27_SPACES_H
+#define _ASM_MACH_IP27_SPACES_H
+
+/*
+ * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
+ * uncached memory addressing.
+ */
+
+#define HSPEC_BASE              0x9000000000000000
+#define IO_BASE                 0x9200000000000000
+#define MSPEC_BASE              0x9400000000000000
+#define UNCAC_BASE              0x9600000000000000
+
+#define TO_MSPEC(x)             (MSPEC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_HSPEC(x)             (HSPEC_BASE | ((x) & TO_PHYS_MASK))
+
+#define HIGHMEM_START           (~0UL)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_IP27_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
new file mode 100644
index 000000000000..7785bec732f2
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -0,0 +1,59 @@
+#ifndef _ASM_MACH_TOPOLOGY_H
+#define _ASM_MACH_TOPOLOGY_H    1
+
+#include <asm/sn/hub.h>
+#include <asm/sn/types.h>
+#include <asm/mmzone.h>
+
+struct cpuinfo_ip27 {
+//      cpuid_t         p_cpuid;        /* PROM assigned cpuid */
+        cnodeid_t       p_nodeid;       /* my node ID in compact-id-space */
+        nasid_t         p_nasid;        /* my node ID in numa-as-id-space */
+        unsigned char   p_slice;        /* Physical position on node board */
+#if 0
+        unsigned long           loops_per_sec;
+        unsigned long           ipi_count;
+        unsigned long           irq_attempt[NR_IRQS];
+        unsigned long           smp_local_irq_count;
+        unsigned long           prof_multiplier;
+        unsigned long           prof_counter;
+#endif
+};
+
+extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
+
+#define cpu_to_node(cpu)        (sn_cpu_info[(cpu)].p_nodeid)
+#define parent_node(node)       (node)
+#define node_to_cpumask(node)   (hub_data(node)->h_cpus)
+#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
+struct pci_bus;
+extern int pcibus_to_node(struct pci_bus *);
+
+#define pcibus_to_cpumask(bus)  (cpu_online_map)
+
+extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
+
+#define node_distance(from, to) (__node_distances[(from)][(to)])
+
+/* sched_domains SD_NODE_INIT for SGI IP27 machines */
+#define SD_NODE_INIT (struct sched_domain) {            \
+        .span                   = CPU_MASK_NONE,        \
+        .parent                 = NULL,                 \
+        .child                  = NULL,                 \
+        .groups                 = NULL,                 \
+        .min_interval           = 8,                    \
+        .max_interval           = 32,                   \
+        .busy_factor            = 32,                   \
+        .imbalance_pct          = 125,                  \
+        .cache_nice_tries       = 1,                    \
+        .flags                  = SD_LOAD_BALANCE       \
+                                | SD_BALANCE_EXEC       \
+                                | SD_WAKE_BALANCE,      \
+        .last_balance           = jiffies,              \
+        .balance_interval       = 1,                    \
+        .nr_balance_failed      = 0,                    \
+}
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
new file mode 100644
index 000000000000..e2ddcc9b1fff
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_IP27_WAR_H
+#define __ASM_MIPS_MACH_IP27_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 1
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
new file mode 100644
index 000000000000..9a53b326f848
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
@@ -0,0 +1,50 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ * 6/2004       pf
+ */
+#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * IP28 only comes with R10000 family processors all using the same config
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0 /* see probe_pcache() */
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_icache_snoops_remote_store  1
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+
+#define cpu_has_inclusive_pcaches       1
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  64
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip28/ds1286.h b/arch/mips/include/asm/mach-ip28/ds1286.h
new file mode 100644
index 000000000000..471bb9a33e0f
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip28/ds1286.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_MACH_IP28_DS1286_H
+#define __ASM_MACH_IP28_DS1286_H
+#include <asm/mach-ip22/ds1286.h>
+#endif /* __ASM_MACH_IP28_DS1286_H */
diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h
new file mode 100644
index 000000000000..05aabb27e5e7
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip28/spaces.h
@@ -0,0 +1,22 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ * 2004 pf
+ */
+#ifndef _ASM_MACH_IP28_SPACES_H
+#define _ASM_MACH_IP28_SPACES_H
+
+#define CAC_BASE                0xa800000000000000
+
+#define HIGHMEM_START           (~0UL)
+
+#define PHYS_OFFSET             _AC(0x20000000, UL)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_IP28_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
new file mode 100644
index 000000000000..a1baafab486a
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_IP28_WAR_H
+#define __ASM_MIPS_MACH_IP28_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 1
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
new file mode 100644
index 000000000000..6782fccebe8d
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
@@ -0,0 +1,50 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Ilya A. Volynets-Evenbakh
+ * Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
+
+
+/*
+ * R5000 has an interesting "restriction":  ll(d)/sc(d)
+ * instructions to XKPHYS region simply do uncached bus
+ * requests. This breaks all the atomic bitops functions.
+ * so, for 64bit IP32 kernel we just don't use ll/sc.
+ * This does not affect luserland.
+ */
+#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT)
+#define cpu_has_llsc            0
+#else
+#define cpu_has_llsc            1
+#endif
+
+/* Settings which are common for all ip32 CPUs */
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_fpu             1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_mips16          0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+#define cpu_has_vtag_icache     0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_4k_cache        1
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
new file mode 100644
index 000000000000..a5511ebb2d53
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -0,0 +1,72 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
+ *
+ */
+#ifndef __ASM_MACH_IP32_DMA_COHERENCE_H
+#define __ASM_MACH_IP32_DMA_COHERENCE_H
+
+#include <asm/ip32/crime.h>
+
+struct device;
+
+/*
+ * Few notes.
+ * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
+ * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
+ *    native-endian)
+ * 3. All other devices see memory as one big chunk at 0x40000000
+ * 4. Non-PCI devices will pass NULL as struct device*
+ *
+ * Thus we translate differently, depending on device.
+ */
+
+#define RAM_OFFSET_MASK 0x3fffffffUL
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+        size_t size)
+{
+        dma_addr_t pa = virt_to_phys(addr) & RAM_OFFSET_MASK;
+
+        if (dev == NULL)
+                pa += CRIME_HI_MEM_BASE;
+
+        return pa;
+}
+
+static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+{
+        dma_addr_t pa;
+
+        pa = page_to_phys(page) & RAM_OFFSET_MASK;
+
+        if (dev == NULL)
+                pa += CRIME_HI_MEM_BASE;
+
+        return pa;
+}
+
+/* This is almost certainly wrong but it's what dma-ip32.c used to use  */
+static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+        unsigned long addr = dma_addr & RAM_OFFSET_MASK;
+
+        if (dma_addr >= 256*1024*1024)
+                addr += CRIME_HI_MEM_BASE;
+
+        return addr;
+}
+
+static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+{
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+        return 0;               /* IP32 is non-cohernet */
+}
+
+#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-ip32/kmalloc.h b/arch/mips/include/asm/mach-ip32/kmalloc.h
new file mode 100644
index 000000000000..b1e0be60f720
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip32/kmalloc.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_MACH_IP32_KMALLOC_H
+#define __ASM_MACH_IP32_KMALLOC_H
+
+
+#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000)
+#define ARCH_KMALLOC_MINALIGN   32
+#else
+#define ARCH_KMALLOC_MINALIGN   128
+#endif
+
+#endif /* __ASM_MACH_IP32_KMALLOC_H */
diff --git a/arch/mips/include/asm/mach-ip32/mangle-port.h b/arch/mips/include/asm/mach-ip32/mangle-port.h
new file mode 100644
index 000000000000..f1d0f1756a9f
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip32/mangle-port.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ladislav Michl
+ * Copyright (C) 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_IP32_MANGLE_PORT_H
+#define __ASM_MACH_IP32_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)  ((port) ^ 3)
+#define __swizzle_addr_w(port)  ((port) ^ 2)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          (x)
+# define __mem_ioswabw(a, x)    cpu_to_le16(x)
+# define ioswabl(a, x)          (x)
+# define __mem_ioswabl(a, x)    cpu_to_le32(x)
+# define ioswabq(a, x)          (x)
+# define __mem_ioswabq(a, x)    cpu_to_le32(x)
+
+#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-ip32/mc146818rtc.h b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
new file mode 100644
index 000000000000..c28ba8d84076
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ * Copyright (C) 2000 Harald Koerfgen
+ *
+ * RTC routines for IP32 style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_IP32_MC146818RTC_H
+#define __ASM_MACH_IP32_MC146818RTC_H
+
+#include <asm/ip32/mace.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+
+static unsigned char CMOS_READ(unsigned long addr)
+{
+        return mace->isa.rtc[addr << 8];
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        mace->isa.rtc[addr << 8] = data;
+}
+
+/*
+ * FIXME: Do it right. For now just assume that noone lives in 20th century
+ * and no O2 user in 22th century ;-)
+ */
+#define mc146818_decode_year(year) ((year) + 2000)
+
+#define RTC_ALWAYS_BCD  0
+
+#endif /* __ASM_MACH_IP32_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
new file mode 100644
index 000000000000..d194056dcd7a
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_IP32_WAR_H
+#define __ASM_MIPS_MACH_IP32_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
new file mode 100644
index 000000000000..d66979a124a8
--- /dev/null
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -0,0 +1,40 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_JAZZ_DMA_COHERENCE_H
+#define __ASM_MACH_JAZZ_DMA_COHERENCE_H
+
+#include <asm/jazzdma.h>
+
+struct device;
+
+static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+{
+        return vdma_alloc(virt_to_phys(addr), size);
+}
+
+static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+{
+        return vdma_alloc(page_to_phys(page), PAGE_SIZE);
+}
+
+static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+        return vdma_log2phys(dma_addr);
+}
+
+static void plat_unmap_dma_mem(dma_addr_t dma_addr)
+{
+        vdma_free(dma_addr);
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+        return 0;
+}
+
+#endif /* __ASM_MACH_JAZZ_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
new file mode 100644
index 000000000000..56e9ca6ae426
--- /dev/null
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -0,0 +1,135 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_JAZZ_FLOPPY_H
+#define __ASM_MACH_JAZZ_FLOPPY_H
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <asm/addrspace.h>
+#include <asm/jazz.h>
+#include <asm/jazzdma.h>
+#include <asm/pgtable.h>
+
+static inline unsigned char fd_inb(unsigned int port)
+{
+        unsigned char c;
+
+        c = *(volatile unsigned char *) port;
+        udelay(1);
+
+        return c;
+}
+
+static inline void fd_outb(unsigned char value, unsigned int port)
+{
+        *(volatile unsigned char *) port = value;
+}
+
+/*
+ * How to access the floppy DMA functions.
+ */
+static inline void fd_enable_dma(void)
+{
+        vdma_enable(JAZZ_FLOPPY_DMA);
+}
+
+static inline void fd_disable_dma(void)
+{
+        vdma_disable(JAZZ_FLOPPY_DMA);
+}
+
+static inline int fd_request_dma(void)
+{
+        return 0;
+}
+
+static inline void fd_free_dma(void)
+{
+}
+
+static inline void fd_clear_dma_ff(void)
+{
+}
+
+static inline void fd_set_dma_mode(char mode)
+{
+        vdma_set_mode(JAZZ_FLOPPY_DMA, mode);
+}
+
+static inline void fd_set_dma_addr(char *a)
+{
+        vdma_set_addr(JAZZ_FLOPPY_DMA, vdma_phys2log(CPHYSADDR((unsigned long)a)));
+}
+
+static inline void fd_set_dma_count(unsigned int count)
+{
+        vdma_set_count(JAZZ_FLOPPY_DMA, count);
+}
+
+static inline int fd_get_dma_residue(void)
+{
+        return vdma_get_residue(JAZZ_FLOPPY_DMA);
+}
+
+static inline void fd_enable_irq(void)
+{
+}
+
+static inline void fd_disable_irq(void)
+{
+}
+
+static inline int fd_request_irq(void)
+{
+        return request_irq(FLOPPY_IRQ, floppy_interrupt,
+                           IRQF_DISABLED, "floppy", NULL);
+}
+
+static inline void fd_free_irq(void)
+{
+        free_irq(FLOPPY_IRQ, NULL);
+}
+
+static inline unsigned long fd_getfdaddr1(void)
+{
+        return JAZZ_FDC_BASE;
+}
+
+static inline unsigned long fd_dma_mem_alloc(unsigned long size)
+{
+        unsigned long mem;
+
+        mem = __get_dma_pages(GFP_KERNEL, get_order(size));
+        if(!mem)
+                return 0;
+        vdma_alloc(CPHYSADDR(mem), size);       /* XXX error checking */
+
+        return mem;
+}
+
+static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
+{
+        vdma_free(vdma_phys2log(CPHYSADDR(addr)));
+        free_pages(addr, get_order(size));
+}
+
+static inline unsigned long fd_drive_type(unsigned long n)
+{
+        /* XXX This is wrong for machines with ED 2.88mb disk drives like the
+           Olivetti M700.  Anyway, we should suck this from the ARC
+           firmware.  */
+        if (n == 0)
+                return 4;       /* 3,5", 1.44mb */
+
+        return 0;
+}
+
+#endif /* __ASM_MACH_JAZZ_FLOPPY_H */
diff --git a/arch/mips/include/asm/mach-jazz/mc146818rtc.h b/arch/mips/include/asm/mach-jazz/mc146818rtc.h
new file mode 100644
index 000000000000..987f727afe25
--- /dev/null
+++ b/arch/mips/include/asm/mach-jazz/mc146818rtc.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ * Copyright (C) 2007 Thomas Bogendoerfer
+ *
+ * RTC routines for Jazz style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_JAZZ_MC146818RTC_H
+#define __ASM_MACH_JAZZ_MC146818RTC_H
+
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/jazz.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        return *(volatile char *)JAZZ_RTC_BASE;
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        *(volatile char *)JAZZ_RTC_BASE = data;
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#define mc146818_decode_year(year) ((year) + 1980)
+
+#endif /* __ASM_MACH_JAZZ_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-jazz/war.h b/arch/mips/include/asm/mach-jazz/war.h
new file mode 100644
index 000000000000..6158ee861bfd
--- /dev/null
+++ b/arch/mips/include/asm/mach-jazz/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H
+#define __ASM_MIPS_MACH_JAZZ_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */
diff --git a/arch/mips/include/asm/mach-lasat/irq.h b/arch/mips/include/asm/mach-lasat/irq.h
new file mode 100644
index 000000000000..3a282419d5f9
--- /dev/null
+++ b/arch/mips/include/asm/mach-lasat/irq.h
@@ -0,0 +1,13 @@
+#ifndef _ASM_MACH_LASAT_IRQ_H
+#define _ASM_MACH_LASAT_IRQ_H
+
+#define LASAT_CASCADE_IRQ       (MIPS_CPU_IRQ_BASE + 2)
+
+#define LASAT_IRQ_BASE          8
+#define LASAT_IRQ_END           23
+
+#define NR_IRQS                 24
+
+#include_next <irq.h>
+
+#endif /* _ASM_MACH_LASAT_IRQ_H */
diff --git a/arch/mips/include/asm/mach-lasat/mach-gt64120.h b/arch/mips/include/asm/mach-lasat/mach-gt64120.h
new file mode 100644
index 000000000000..1a9ad45cc135
--- /dev/null
+++ b/arch/mips/include/asm/mach-lasat/mach-gt64120.h
@@ -0,0 +1,27 @@
+/*
+ *  This is a direct copy of the ev96100.h file, with a global
+ * search and replace.  The numbers are the same.
+ *
+ *  The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
+#define _ASM_GT64120_LASAT_GT64120_DEP_H
+
+/*
+ *   GT64120 config space base address on Lasat 100
+ */
+#define GT64120_BASE    (KSEG1ADDR(0x14000000))
+
+/*
+ *   PCI Bus allocation
+ *
+ *   (Guessing ...)
+ */
+#define GT_PCI_MEM_BASE 0x12000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL
+#define GT_PCI_IO_BASE  0x10000000UL
+#define GT_PCI_IO_SIZE  0x02000000UL
+#define GT_ISA_IO_BASE  PCI_IO_BASE
+
+#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */
diff --git a/arch/mips/include/asm/mach-lasat/war.h b/arch/mips/include/asm/mach-lasat/war.h
new file mode 100644
index 000000000000..bb1e0325c9be
--- /dev/null
+++ b/arch/mips/include/asm/mach-lasat/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_LASAT_WAR_H
+#define __ASM_MIPS_MACH_LASAT_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
new file mode 100644
index 000000000000..7e914777ebc4
--- /dev/null
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -0,0 +1,42 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006, 07  Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ */
+#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H
+#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H
+
+struct device;
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+                                          size_t size)
+{
+        return virt_to_phys(addr) | 0x80000000;
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+                                               struct page *page)
+{
+        return page_to_phys(page) | 0x80000000;
+}
+
+static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+        return dma_addr & 0x7fffffff;
+}
+
+static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+{
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+        return 0;
+}
+
+#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-lemote/mc146818rtc.h b/arch/mips/include/asm/mach-lemote/mc146818rtc.h
new file mode 100644
index 000000000000..ed5147e11085
--- /dev/null
+++ b/arch/mips/include/asm/mach-lemote/mc146818rtc.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H
+#define __ASM_MACH_LEMOTE_MC146818RTC_H
+
+#include <linux/io.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        return inb_p(RTC_PORT(1));
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        outb_p(data, RTC_PORT(1));
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#ifndef mc146818_decode_year
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
+#endif
+
+#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-lemote/war.h b/arch/mips/include/asm/mach-lemote/war.h
new file mode 100644
index 000000000000..05f89e0f2a11
--- /dev/null
+++ b/arch/mips/include/asm/mach-lemote/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H
+#define __ASM_MIPS_MACH_LEMOTE_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */
diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
new file mode 100644
index 000000000000..7f3e3f9bd23a
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
@@ -0,0 +1,72 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Chris Dearman
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
+
+
+/*
+ * CPU feature overrides for MIPS boards
+ */
+#ifdef CONFIG_CPU_MIPS32
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#ifdef CONFIG_CPU_HAS_LLSC
+#define cpu_has_llsc            1
+#else
+#define cpu_has_llsc            0
+#endif
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_inclusive_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
+#endif
+
+#ifdef CONFIG_CPU_MIPS64
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_inclusive_pcaches ? */
+#define cpu_icache_snoops_remote_store 1
+#endif
+
+#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-malta/irq.h b/arch/mips/include/asm/mach-malta/irq.h
new file mode 100644
index 000000000000..9b9da26683c2
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/irq.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_MACH_MIPS_IRQ_H
+#define __ASM_MACH_MIPS_IRQ_H
+
+
+#define NR_IRQS 256
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
new file mode 100644
index 000000000000..0b793e7bf67e
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Chris Dearman (chris@mips.com)
+ * Copyright (C) 2007 Mips Technologies, Inc.
+ */
+#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+
+        .macro  kernel_entry_setup
+#ifdef CONFIG_MIPS_MT_SMTC
+        mfc0    t0, CP0_CONFIG
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 1
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 2
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 3
+        and     t0, 1<<2
+        bnez    t0, 0f
+9:
+        /* Assume we came from YAMON... */
+        PTR_LA  v0, 0x9fc00534  /* YAMON print */
+        lw      v0, (v0)
+        move    a0, zero
+        PTR_LA  a1, nonmt_processor
+        jal     v0
+
+        PTR_LA  v0, 0x9fc00520  /* YAMON exit */
+        lw      v0, (v0)
+        li      a0, 1
+        jal     v0
+
+1:      b       1b
+
+        __INITDATA
+nonmt_processor:
+        .asciz  "SMTC kernel requires the MT ASE to run\n"
+        __FINIT
+0:
+#endif
+        .endm
+
+/*
+ * Do SMP slave processor setup necessary before we can safely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+
+#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-malta/mach-gt64120.h b/arch/mips/include/asm/mach-malta/mach-gt64120.h
new file mode 100644
index 000000000000..0f863148f3b6
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/mach-gt64120.h
@@ -0,0 +1,19 @@
+/*
+ *  This is a direct copy of the ev96100.h file, with a global
+ * search and replace.  The numbers are the same.
+ *
+ *  The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H
+#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H
+
+#define MIPS_GT_BASE    0x1be00000
+
+extern unsigned long _pcictrl_gt64120;
+/*
+ *   GT64120 config space base address
+ */
+#define GT64120_BASE    _pcictrl_gt64120
+
+#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
diff --git a/arch/mips/include/asm/mach-malta/mc146818rtc.h b/arch/mips/include/asm/mach-malta/mc146818rtc.h
new file mode 100644
index 000000000000..ea612f37f614
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/mc146818rtc.h
@@ -0,0 +1,48 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2003 by Ralf Baechle
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * RTC routines for Malta style attached PIIX4 device, which contains a
+ * Motorola MC146818A-compatible Real Time Clock.
+ */
+#ifndef __ASM_MACH_MALTA_MC146818RTC_H
+#define __ASM_MACH_MALTA_MC146818RTC_H
+
+#include <asm/io.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/malta.h>
+
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb(addr, MALTA_RTC_ADR_REG);
+        return inb(MALTA_RTC_DAT_REG);
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb(addr, MALTA_RTC_ADR_REG);
+        outb(data, MALTA_RTC_DAT_REG);
+}
+
+#define RTC_ALWAYS_BCD  0
+
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
+
+#endif /* __ASM_MACH_MALTA_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
new file mode 100644
index 000000000000..7c6931d5f45f
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
+#define __ASM_MIPS_MACH_MIPS_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        1
+#define MIPS_CACHE_SYNC_WAR             1
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
new file mode 100644
index 000000000000..779b02205737
--- /dev/null
+++ b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
@@ -0,0 +1,65 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Chris Dearman
+ */
+#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
+
+
+/*
+ * CPU feature overrides for MIPS boards
+ */
+#ifdef CONFIG_CPU_MIPS32
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+#define cpu_has_fpu             0
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_inclusive_pcaches ? */
+#endif
+
+#ifdef CONFIG_CPU_MIPS64
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_inclusive_pcaches ? */
+#endif
+
+#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-mipssim/war.h b/arch/mips/include/asm/mach-mipssim/war.h
new file mode 100644
index 000000000000..c8a74a3515e0
--- /dev/null
+++ b/arch/mips/include/asm/mach-mipssim/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
+#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
new file mode 100644
index 000000000000..622c58710e5b
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
@@ -0,0 +1,34 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
+#define __ASM_MACH_AU1XX_MC146818RTC_H
+
+#include <asm/io.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#define RTC_PORT(x)     (0x0c000000 + (x))
+#define RTC_IRQ         8
+#define PB1500_RTC_ADDR 0x0c000000
+
+static inline unsigned char CMOS_READ(unsigned long offset)
+{
+        offset <<= 2;
+        return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
+{
+        offset <<= 2;
+        au_writel(data, offset + PB1500_RTC_ADDR);
+}
+
+#define RTC_ALWAYS_BCD  1
+
+#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
new file mode 100644
index 000000000000..6d1ff9060e44
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h
@@ -0,0 +1,87 @@
+/*
+ * Alchemy Semi Pb1000 Referrence Board
+ *
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1000_H
+#define __ASM_PB1000_H
+
+/* PCMCIA PB1000 specific defines */
+#define PCMCIA_MAX_SOCK  1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
+
+#define PB1000_PCR              0xBE000000
+#  define PCR_SLOT_0_VPP0       (1 << 0)
+#  define PCR_SLOT_0_VPP1       (1 << 1)
+#  define PCR_SLOT_0_VCC0       (1 << 2)
+#  define PCR_SLOT_0_VCC1       (1 << 3)
+#  define PCR_SLOT_0_RST        (1 << 4)
+#  define PCR_SLOT_1_VPP0       (1 << 8)
+#  define PCR_SLOT_1_VPP1       (1 << 9)
+#  define PCR_SLOT_1_VCC0       (1 << 10)
+#  define PCR_SLOT_1_VCC1       (1 << 11)
+#  define PCR_SLOT_1_RST        (1 << 12)
+
+#define PB1000_MDR              0xBE000004
+#  define MDR_PI                (1 << 5)        /* PCMCIA int latch  */
+#  define MDR_EPI               (1 << 14)       /* enable PCMCIA int */
+#  define MDR_CPI               (1 << 15)       /* clear  PCMCIA int  */
+
+#define PB1000_ACR1             0xBE000008
+#  define ACR1_SLOT_0_CD1       (1 << 0)        /* card detect 1        */
+#  define ACR1_SLOT_0_CD2       (1 << 1)        /* card detect 2        */
+#  define ACR1_SLOT_0_READY     (1 << 2)        /* ready                */
+#  define ACR1_SLOT_0_STATUS    (1 << 3)        /* status change        */
+#  define ACR1_SLOT_0_VS1       (1 << 4)        /* voltage sense 1      */
+#  define ACR1_SLOT_0_VS2       (1 << 5)        /* voltage sense 2      */
+#  define ACR1_SLOT_0_INPACK    (1 << 6)        /* inpack pin status    */
+#  define ACR1_SLOT_1_CD1       (1 << 8)        /* card detect 1        */
+#  define ACR1_SLOT_1_CD2       (1 << 9)        /* card detect 2        */
+#  define ACR1_SLOT_1_READY     (1 << 10)       /* ready                */
+#  define ACR1_SLOT_1_STATUS    (1 << 11)       /* status change        */
+#  define ACR1_SLOT_1_VS1       (1 << 12)       /* voltage sense 1      */
+#  define ACR1_SLOT_1_VS2       (1 << 13)       /* voltage sense 2      */
+#  define ACR1_SLOT_1_INPACK    (1 << 14)       /* inpack pin status    */
+
+#define CPLD_AUX0               0xBE00000C
+#define CPLD_AUX1               0xBE000010
+#define CPLD_AUX2               0xBE000014
+
+/* Voltage levels */
+
+/* VPPEN1 - VPPEN0 */
+#define VPP_GND ((0 << 1) | (0 << 0))
+#define VPP_5V  ((1 << 1) | (0 << 0))
+#define VPP_3V  ((0 << 1) | (1 << 0))
+#define VPP_12V ((0 << 1) | (1 << 0))
+#define VPP_HIZ ((1 << 1) | (1 << 0))
+
+/* VCCEN1 - VCCEN0 */
+#define VCC_3V  ((0 << 1) | (1 << 0))
+#define VCC_5V  ((1 << 1) | (0 << 0))
+#define VCC_HIZ ((0 << 1) | (0 << 0))
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
+#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h
new file mode 100644
index 000000000000..b1a60f1cbd02
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1100.h
@@ -0,0 +1,85 @@
+/*
+ * Alchemy Semi Pb1100 Referrence Board
+ *
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1100_H
+#define __ASM_PB1100_H
+
+#define PB1100_IDENT            0xAE000000
+#define BOARD_STATUS_REG        0xAE000004
+#  define PB1100_ROM_SEL        (1 << 15)
+#  define PB1100_ROM_SIZ        (1 << 14)
+#  define PB1100_SWAP_BOOT      (1 << 13)
+#  define PB1100_FLASH_WP       (1 << 12)
+#  define PB1100_ROM_H_STS      (1 << 11)
+#  define PB1100_ROM_L_STS      (1 << 10)
+#  define PB1100_FLASH_H_STS    (1 << 9)
+#  define PB1100_FLASH_L_STS    (1 << 8)
+#  define PB1100_SRAM_SIZ       (1 << 7)
+#  define PB1100_TSC_BUSY       (1 << 6)
+#  define PB1100_PCMCIA_VS_MASK (3 << 4)
+#  define PB1100_RS232_CD       (1 << 3)
+#  define PB1100_RS232_CTS      (1 << 2)
+#  define PB1100_RS232_DSR      (1 << 1)
+#  define PB1100_RS232_RI       (1 << 0)
+
+#define PB1100_IRDA_RS232       0xAE00000C
+#  define PB1100_IRDA_FULL      (0 << 14)       /* full power           */
+#  define PB1100_IRDA_SHUTDOWN  (1 << 14)
+#  define PB1100_IRDA_TT        (2 << 14)       /* 2/3 power            */
+#  define PB1100_IRDA_OT        (3 << 14)       /* 1/3 power            */
+#  define PB1100_IRDA_FIR       (1 << 13)
+
+#define PCMCIA_BOARD_REG        0xAE000010
+#  define PB1100_SD_WP1_RO      (1 << 15)       /* read only            */
+#  define PB1100_SD_WP0_RO      (1 << 14)       /* read only            */
+#  define PB1100_SD_PWR1        (1 << 11)       /* applies power to SD1 */
+#  define PB1100_SD_PWR0        (1 << 10)       /* applies power to SD0 */
+#  define PB1100_SEL_SD_CONN1   (1 << 9)
+#  define PB1100_SEL_SD_CONN0   (1 << 8)
+#  define PC_DEASSERT_RST       (1 << 7)
+#  define PC_DRV_EN             (1 << 4)
+
+#define PB1100_G_CONTROL        0xAE000014      /* graphics control     */
+
+#define PB1100_RST_VDDI         0xAE00001C
+#  define PB1100_SOFT_RESET     (1 << 15)       /* clear to reset the board */
+#  define PB1100_VDDI_MASK      0x1F
+
+#define PB1100_LEDS             0xAE000018
+
+/*
+ * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
+ * 7:0  is the LED Display's decimal points.
+ */
+#define PB1100_HEX_LED          0xAE000018
+
+/* PCMCIA Pb1100 specific defines */
+#define PCMCIA_MAX_SOCK  0
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
+
+#endif /* __ASM_PB1100_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
new file mode 100644
index 000000000000..c8618df88cb5
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -0,0 +1,259 @@
+/*
+ * AMD Alchemy Pb1200 Referrence Board
+ * Board Registers defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1200_H
+#define __ASM_PB1200_H
+
+#include <linux/types.h>
+#include <asm/mach-au1x00/au1xxx_psc.h>
+
+#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC1_RX
+
+/*
+ * SPI and SMB are muxed on the Pb1200 board.
+ * Refer to board documentation.
+ */
+#define SPI_PSC_BASE            PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE          PSC0_BASE_ADDR
+/*
+ * AC97 and I2S are muxed on the Pb1200 board.
+ * Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE            PSC1_BASE_ADDR
+
+#define BCSR_KSEG1_ADDR 0xAD800000
+
+typedef volatile struct
+{
+        /*00*/  u16 whoami;
+                u16 reserved0;
+        /*04*/  u16 status;
+                u16 reserved1;
+        /*08*/  u16 switches;
+                u16 reserved2;
+        /*0C*/  u16 resets;
+                u16 reserved3;
+
+        /*10*/  u16 pcmcia;
+                u16 reserved4;
+        /*14*/  u16 board;
+                u16 reserved5;
+        /*18*/  u16 disk_leds;
+                u16 reserved6;
+        /*1C*/  u16 system;
+                u16 reserved7;
+
+        /*20*/  u16 intclr;
+                u16 reserved8;
+        /*24*/  u16 intset;
+                u16 reserved9;
+        /*28*/  u16 intclr_mask;
+                u16 reserved10;
+        /*2C*/  u16 intset_mask;
+                u16 reserved11;
+
+        /*30*/  u16 sig_status;
+                u16 reserved12;
+        /*34*/  u16 int_status;
+                u16 reserved13;
+        /*38*/  u16 reserved14;
+                u16 reserved15;
+        /*3C*/  u16 reserved16;
+                u16 reserved17;
+
+} BCSR;
+
+static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID        0x000F
+#define BCSR_WHOAMI_CPLD        0x00F0
+#define BCSR_WHOAMI_BOARD       0x0F00
+
+#define BCSR_STATUS_PCMCIA0VS   0x0003
+#define BCSR_STATUS_PCMCIA1VS   0x000C
+#define BCSR_STATUS_SWAPBOOT    0x0040
+#define BCSR_STATUS_FLASHBUSY   0x0100
+#define BCSR_STATUS_IDECBLID    0x0200
+#define BCSR_STATUS_SD0WP       0x0400
+#define BCSR_STATUS_SD1WP       0x0800
+#define BCSR_STATUS_U0RXD       0x1000
+#define BCSR_STATUS_U1RXD       0x2000
+
+#define BCSR_SWITCHES_OCTAL     0x00FF
+#define BCSR_SWITCHES_DIP_1     0x0080
+#define BCSR_SWITCHES_DIP_2     0x0040
+#define BCSR_SWITCHES_DIP_3     0x0020
+#define BCSR_SWITCHES_DIP_4     0x0010
+#define BCSR_SWITCHES_DIP_5     0x0008
+#define BCSR_SWITCHES_DIP_6     0x0004
+#define BCSR_SWITCHES_DIP_7     0x0002
+#define BCSR_SWITCHES_DIP_8     0x0001
+#define BCSR_SWITCHES_ROTARY    0x0F00
+
+#define BCSR_RESETS_ETH         0x0001
+#define BCSR_RESETS_CAMERA      0x0002
+#define BCSR_RESETS_DC          0x0004
+#define BCSR_RESETS_IDE         0x0008
+/* not resets but in the same register */
+#define BCSR_RESETS_WSCFSM      0x0800
+#define BCSR_RESETS_PCS0MUX     0x1000
+#define BCSR_RESETS_PCS1MUX     0x2000
+#define BCSR_RESETS_SPISEL      0x4000
+#define BCSR_RESETS_SD1MUX      0x8000
+
+#define BCSR_PCMCIA_PC0VPP      0x0003
+#define BCSR_PCMCIA_PC0VCC      0x000C
+#define BCSR_PCMCIA_PC0DRVEN    0x0010
+#define BCSR_PCMCIA_PC0RST      0x0080
+#define BCSR_PCMCIA_PC1VPP      0x0300
+#define BCSR_PCMCIA_PC1VCC      0x0C00
+#define BCSR_PCMCIA_PC1DRVEN    0x1000
+#define BCSR_PCMCIA_PC1RST      0x8000
+
+#define BCSR_BOARD_LCDVEE       0x0001
+#define BCSR_BOARD_LCDVDD       0x0002
+#define BCSR_BOARD_LCDBL        0x0004
+#define BCSR_BOARD_CAMSNAP      0x0010
+#define BCSR_BOARD_CAMPWR       0x0020
+#define BCSR_BOARD_SD0PWR       0x0040
+#define BCSR_BOARD_SD1PWR       0x0080
+
+#define BCSR_LEDS_DECIMALS      0x00FF
+#define BCSR_LEDS_LED0          0x0100
+#define BCSR_LEDS_LED1          0x0200
+#define BCSR_LEDS_LED2          0x0400
+#define BCSR_LEDS_LED3          0x0800
+
+#define BCSR_SYSTEM_VDDI        0x001F
+#define BCSR_SYSTEM_POWEROFF    0x4000
+#define BCSR_SYSTEM_RESET       0x8000
+
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE            0x0001
+#define BCSR_INT_ETH            0x0002
+#define BCSR_INT_PC0            0x0004
+#define BCSR_INT_PC0STSCHG      0x0008
+#define BCSR_INT_PC1            0x0010
+#define BCSR_INT_PC1STSCHG      0x0020
+#define BCSR_INT_DC             0x0040
+#define BCSR_INT_FLASHBUSY      0x0080
+#define BCSR_INT_PC0INSERT      0x0100
+#define BCSR_INT_PC0EJECT       0x0200
+#define BCSR_INT_PC1INSERT      0x0400
+#define BCSR_INT_PC1EJECT       0x0800
+#define BCSR_INT_SD0INSERT      0x1000
+#define BCSR_INT_SD0EJECT       0x2000
+#define BCSR_INT_SD1INSERT      0x4000
+#define BCSR_INT_SD1EJECT       0x8000
+
+#define SMC91C111_PHYS_ADDR     0x0D000300
+#define SMC91C111_INT           PB1200_ETH_INT
+
+#define IDE_PHYS_ADDR           0x0C800000
+#define IDE_REG_SHIFT           5
+#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
+#define IDE_INT                 PB1200_IDE_INT
+#define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
+#define IDE_RQSIZE              128
+
+#define NAND_PHYS_ADDR  0x1C000000
+
+/*
+ * Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an Au1200 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                (18 >> 2)
+#define NAND_T_PUL              (30 >> 2)
+#define NAND_T_SU               (30 >> 2)
+#define NAND_T_WH               (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+
+#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
+                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
+                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
+
+/*
+ * External Interrupts for Pb1200 as of 8/6/2004.
+ * Bit positions in the CPLD registers can be calculated by taking
+ * the interrupt define and subtracting the PB1200_INT_BEGIN value.
+ *
+ *   Example: IDE bis pos is  = 64 - 64
+ *            ETH bit pos is  = 65 - 64
+ */
+enum external_pb1200_ints {
+        PB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
+
+        PB1200_IDE_INT          = PB1200_INT_BEGIN,
+        PB1200_ETH_INT,
+        PB1200_PC0_INT,
+        PB1200_PC0_STSCHG_INT,
+        PB1200_PC1_INT,
+        PB1200_PC1_STSCHG_INT,
+        PB1200_DC_INT,
+        PB1200_FLASHBUSY_INT,
+        PB1200_PC0_INSERT_INT,
+        PB1200_PC0_EJECT_INT,
+        PB1200_PC1_INSERT_INT,
+        PB1200_PC1_EJECT_INT,
+        PB1200_SD0_INSERT_INT,
+        PB1200_SD0_EJECT_INT,
+        PB1200_SD1_INSERT_INT,
+        PB1200_SD1_EJECT_INT,
+
+        PB1200_INT_END          = PB1200_INT_BEGIN + 15
+};
+
+/*
+ * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
+ */
+#define PCMCIA_MAX_SOCK  1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
+
+#define BOARD_PC0_INT   PB1200_PC0_INT
+#define BOARD_PC1_INT   PB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
+
+/* NAND chip select */
+#define NAND_CS 1
+
+#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h
new file mode 100644
index 000000000000..da51a2eb7b82
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1500.h
@@ -0,0 +1,49 @@
+/*
+ * Alchemy Semi Pb1500 Referrence Board
+ *
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1500_H
+#define __ASM_PB1500_H
+
+#define IDENT_BOARD_REG         0xAE000000
+#define BOARD_STATUS_REG        0xAE000004
+#define PCI_BOARD_REG           0xAE000010
+#define PCMCIA_BOARD_REG        0xAE000010
+#  define PC_DEASSERT_RST             0x80
+#  define PC_DRV_EN                   0x10
+#define PB1500_G_CONTROL        0xAE000014
+#define PB1500_RST_VDDI         0xAE00001C
+#define PB1500_LEDS             0xAE000018
+
+#define PB1500_HEX_LED          0xAF000004
+#define PB1500_HEX_LED_BLANK    0xAF000008
+
+/* PCMCIA Pb1500 specific defines */
+#define PCMCIA_MAX_SOCK  0
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
+
+#endif /* __ASM_PB1500_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
new file mode 100644
index 000000000000..6704a11497db
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -0,0 +1,177 @@
+/*
+ * AMD Alchemy Semi PB1550 Referrence Board
+ * Board Registers defines.
+ *
+ * Copyright 2004 Embedded Edge LLC.
+ * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1550_H
+#define __ASM_PB1550_H
+
+#include <linux/types.h>
+#include <asm/mach-au1x00/au1xxx_psc.h>
+
+#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC3_RX
+
+#define SPI_PSC_BASE            PSC0_BASE_ADDR
+#define AC97_PSC_BASE           PSC1_BASE_ADDR
+#define SMBUS_PSC_BASE          PSC2_BASE_ADDR
+#define I2S_PSC_BASE            PSC3_BASE_ADDR
+
+#define BCSR_PHYS_ADDR 0xAF000000
+
+typedef volatile struct
+{
+        /*00*/  u16 whoami;
+                u16 reserved0;
+        /*04*/  u16 status;
+                u16 reserved1;
+        /*08*/  u16 switches;
+                u16 reserved2;
+        /*0C*/  u16 resets;
+                u16 reserved3;
+        /*10*/  u16 pcmcia;
+                u16 reserved4;
+        /*14*/  u16 pci;
+                u16 reserved5;
+        /*18*/  u16 leds;
+                u16 reserved6;
+        /*1C*/  u16 system;
+                u16 reserved7;
+
+} BCSR;
+
+static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
+
+/*
+ * Register bit definitions for the BCSRs
+ */
+#define BCSR_WHOAMI_DCID        0x000F
+#define BCSR_WHOAMI_CPLD        0x00F0
+#define BCSR_WHOAMI_BOARD       0x0F00
+
+#define BCSR_STATUS_PCMCIA0VS   0x0003
+#define BCSR_STATUS_PCMCIA1VS   0x000C
+#define BCSR_STATUS_PCMCIA0FI   0x0010
+#define BCSR_STATUS_PCMCIA1FI   0x0020
+#define BCSR_STATUS_SWAPBOOT    0x0040
+#define BCSR_STATUS_SRAMWIDTH   0x0080
+#define BCSR_STATUS_FLASHBUSY   0x0100
+#define BCSR_STATUS_ROMBUSY     0x0200
+#define BCSR_STATUS_USBOTGID    0x0800
+#define BCSR_STATUS_U0RXD       0x1000
+#define BCSR_STATUS_U1RXD       0x2000
+#define BCSR_STATUS_U3RXD       0x8000
+
+#define BCSR_SWITCHES_OCTAL     0x00FF
+#define BCSR_SWITCHES_DIP_1     0x0080
+#define BCSR_SWITCHES_DIP_2     0x0040
+#define BCSR_SWITCHES_DIP_3     0x0020
+#define BCSR_SWITCHES_DIP_4     0x0010
+#define BCSR_SWITCHES_DIP_5     0x0008
+#define BCSR_SWITCHES_DIP_6     0x0004
+#define BCSR_SWITCHES_DIP_7     0x0002
+#define BCSR_SWITCHES_DIP_8     0x0001
+#define BCSR_SWITCHES_ROTARY    0x0F00
+
+#define BCSR_RESETS_PHY0        0x0001
+#define BCSR_RESETS_PHY1        0x0002
+#define BCSR_RESETS_DC          0x0004
+#define BCSR_RESETS_WSC         0x2000
+#define BCSR_RESETS_SPISEL      0x4000
+#define BCSR_RESETS_DMAREQ      0x8000
+
+#define BCSR_PCMCIA_PC0VPP      0x0003
+#define BCSR_PCMCIA_PC0VCC      0x000C
+#define BCSR_PCMCIA_PC0DRVEN    0x0010
+#define BCSR_PCMCIA_PC0RST      0x0080
+#define BCSR_PCMCIA_PC1VPP      0x0300
+#define BCSR_PCMCIA_PC1VCC      0x0C00
+#define BCSR_PCMCIA_PC1DRVEN    0x1000
+#define BCSR_PCMCIA_PC1RST      0x8000
+
+#define BCSR_PCI_M66EN          0x0001
+#define BCSR_PCI_M33            0x0100
+#define BCSR_PCI_EXTERNARB      0x0200
+#define BCSR_PCI_GPIO200RST     0x0400
+#define BCSR_PCI_CLKOUT         0x0800
+#define BCSR_PCI_CFGHOST        0x1000
+
+#define BCSR_LEDS_DECIMALS      0x00FF
+#define BCSR_LEDS_LED0          0x0100
+#define BCSR_LEDS_LED1          0x0200
+#define BCSR_LEDS_LED2          0x0400
+#define BCSR_LEDS_LED3          0x0800
+
+#define BCSR_SYSTEM_VDDI        0x001F
+#define BCSR_SYSTEM_POWEROFF    0x4000
+#define BCSR_SYSTEM_RESET       0x8000
+
+#define PCMCIA_MAX_SOCK  1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
+
+#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
+#define PB1550_BOTH_BANKS
+#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
+#define PB1550_BOOT_ONLY
+#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
+#define PB1550_USER_ONLY
+#endif
+
+/*
+ * Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an SOC1550 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                (18 >> 2)
+#define NAND_T_PUL              (30 >> 2)
+#define NAND_T_SU               (30 >> 2)
+#define NAND_T_WH               (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+
+#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
+                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
+                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
+
+#define NAND_CS 1
+
+/* Should be done by YAMON */
+#define NAND_STCFG      0x00400005 /* 8-bit NAND */
+#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
+#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
+
+#endif /* __ASM_PB1550_H */
diff --git a/arch/mips/include/asm/mach-pnx8550/cm.h b/arch/mips/include/asm/mach-pnx8550/cm.h
new file mode 100644
index 000000000000..bb0a56c7d011
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/cm.h
@@ -0,0 +1,43 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   Clock module specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_CM_H
+#define __PNX8550_CM_H
+
+#define PNX8550_CM_BASE 0xBBE47000
+
+#define PNX8550_CM_PLL0_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
+#define PNX8550_CM_PLL1_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
+#define PNX8550_CM_PLL2_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
+#define PNX8550_CM_PLL3_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
+
+// Table not complete.....
+
+#define PNX8550_CM_PLL_BLOCKED_MASK     0x80000000
+#define PNX8550_CM_PLL_LOCK_MASK        0x40000000
+#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
+#define PNX8550_CM_PLL_N_MASK           0x01ff0000
+#define PNX8550_CM_PLL_M_MASK           0x00003f00
+#define PNX8550_CM_PLL_P_MASK           0x0000000c
+#define PNX8550_CM_PLL_PD_MASK          0x00000002
+
+
+#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/glb.h b/arch/mips/include/asm/mach-pnx8550/glb.h
new file mode 100644
index 000000000000..07aa85e609bc
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/glb.h
@@ -0,0 +1,86 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   PNX8550 global definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_GLB_H
+#define __PNX8550_GLB_H
+
+#define PNX8550_GLB1_BASE       0xBBE63000
+#define PNX8550_GLB2_BASE       0xBBE4d000
+#define PNX8550_RESET_BASE      0xBBE60000
+
+/* PCI Inta Output Enable Registers */
+#define PNX8550_GLB2_ENAB_INTA_O        *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
+
+/* Bit 1:Enable DAC Powerdown
+     0:DACs are enabled and are working normally
+     1:DACs are powerdown
+*/
+#define PNX8550_GLB_DAC_PD      0x2
+/*   Bit 0:Enable of PCI inta output
+     0 = Disable PCI inta output
+     1 = Enable PCI inta output
+*/
+#define PNX8550_GLB_ENABLE_INTA_O 0x1
+
+/* PCI Direct Mappings */
+#define PNX8550_PCIMEM          0x12000000
+#define PNX8550_PCIMEM_SIZE     0x08000000
+#define PNX8550_PCIIO           0x1c000000
+#define PNX8550_PCIIO_SIZE      0x02000000      /* 32M */
+
+#define PNX8550_PORT_BASE       KSEG1
+
+// GPIO def
+#define PNX8550_GPIO_BASE       0x1Be00000
+
+#define PNX8550_GPIO_DIRQ0       (PNX8550_GPIO_BASE + 0x104500)
+#define PNX8550_GPIO_MC1         (PNX8550_GPIO_BASE + 0x104004)
+#define PNX8550_GPIO_MC_31_BIT   30
+#define PNX8550_GPIO_MC_30_BIT   28
+#define PNX8550_GPIO_MC_29_BIT   26
+#define PNX8550_GPIO_MC_28_BIT   24
+#define PNX8550_GPIO_MC_27_BIT   22
+#define PNX8550_GPIO_MC_26_BIT   20
+#define PNX8550_GPIO_MC_25_BIT   18
+#define PNX8550_GPIO_MC_24_BIT   16
+#define PNX8550_GPIO_MC_23_BIT   14
+#define PNX8550_GPIO_MC_22_BIT   12
+#define PNX8550_GPIO_MC_21_BIT   10
+#define PNX8550_GPIO_MC_20_BIT   8
+#define PNX8550_GPIO_MC_19_BIT   6
+#define PNX8550_GPIO_MC_18_BIT   4
+#define PNX8550_GPIO_MC_17_BIT   2
+#define PNX8550_GPIO_MC_16_BIT   0
+
+#define PNX8550_GPIO_MODE_PRIMOP    0x1
+#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
+#define PNX8550_GPIO_MODE_OPENDR    0x3
+
+// RESET module
+#define PNX8550_RST_CTL             *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
+#define PNX8550_RST_CAUSE           *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
+#define PNX8550_RST_EN_WATCHDOG     *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
+
+#define PNX8550_RST_REL_MIPS_RST_N     0x8
+#define PNX8550_RST_DO_SW_RST          0x4
+#define PNX8550_RST_REL_SYS_RST_OUT    0x2
+#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
+#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/int.h b/arch/mips/include/asm/mach-pnx8550/int.h
new file mode 100644
index 000000000000..0e0668b524f4
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/int.h
@@ -0,0 +1,140 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   Interrupt specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_INT_H
+#define __PNX8550_INT_H
+
+#define PNX8550_GIC_BASE        0xBBE3E000
+
+#define PNX8550_GIC_PRIMASK_0   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
+#define PNX8550_GIC_PRIMASK_1   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
+#define PNX8550_GIC_VECTOR_0    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
+#define PNX8550_GIC_VECTOR_1    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
+#define PNX8550_GIC_PEND_1_31   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
+#define PNX8550_GIC_PEND_32_63  *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
+#define PNX8550_GIC_PEND_64_70  *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
+#define PNX8550_GIC_FEATURES    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
+#define PNX8550_GIC_REQ(x)      *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
+#define PNX8550_GIC_MOD_ID      *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
+
+// cp0 is two software + six hw exceptions
+#define PNX8550_INT_CP0_TOTINT  8
+#define PNX8550_INT_CP0_MIN     0
+#define PNX8550_INT_CP0_MAX     (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
+
+#define MIPS_CPU_GIC_IRQ        2
+#define MIPS_CPU_TIMER_IRQ      7
+
+// GIC are 71 exceptions connected to cp0's first hardware exception
+#define PNX8550_INT_GIC_TOTINT  71
+#define PNX8550_INT_GIC_MIN     (PNX8550_INT_CP0_MAX+1)
+#define PNX8550_INT_GIC_MAX     (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
+
+#define PNX8550_INT_UNDEF              (PNX8550_INT_GIC_MIN+0)
+#define PNX8550_INT_IPC_TARGET0_MIPS   (PNX8550_INT_GIC_MIN+1)
+#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
+#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
+#define PNX8550_INT_RESERVED_4         (PNX8550_INT_GIC_MIN+4)
+#define PNX8550_INT_USB                (PNX8550_INT_GIC_MIN+5)
+#define PNX8550_INT_GPIO_EQ1           (PNX8550_INT_GIC_MIN+6)
+#define PNX8550_INT_GPIO_EQ2           (PNX8550_INT_GIC_MIN+7)
+#define PNX8550_INT_GPIO_EQ3           (PNX8550_INT_GIC_MIN+8)
+#define PNX8550_INT_GPIO_EQ4           (PNX8550_INT_GIC_MIN+9)
+
+#define PNX8550_INT_GPIO_EQ5           (PNX8550_INT_GIC_MIN+10)
+#define PNX8550_INT_GPIO_EQ6           (PNX8550_INT_GIC_MIN+11)
+#define PNX8550_INT_RESERVED_12        (PNX8550_INT_GIC_MIN+12)
+#define PNX8550_INT_QVCP1              (PNX8550_INT_GIC_MIN+13)
+#define PNX8550_INT_QVCP2              (PNX8550_INT_GIC_MIN+14)
+#define PNX8550_INT_I2C1               (PNX8550_INT_GIC_MIN+15)
+#define PNX8550_INT_I2C2               (PNX8550_INT_GIC_MIN+16)
+#define PNX8550_INT_ISO_UART1          (PNX8550_INT_GIC_MIN+17)
+#define PNX8550_INT_ISO_UART2          (PNX8550_INT_GIC_MIN+18)
+#define PNX8550_INT_UART1              (PNX8550_INT_GIC_MIN+19)
+
+#define PNX8550_INT_UART2              (PNX8550_INT_GIC_MIN+20)
+#define PNX8550_INT_QNTR               (PNX8550_INT_GIC_MIN+21)
+#define PNX8550_INT_RESERVED22         (PNX8550_INT_GIC_MIN+22)
+#define PNX8550_INT_T_DSC              (PNX8550_INT_GIC_MIN+23)
+#define PNX8550_INT_M_DSC              (PNX8550_INT_GIC_MIN+24)
+#define PNX8550_INT_RESERVED25         (PNX8550_INT_GIC_MIN+25)
+#define PNX8550_INT_2D_DRAW_ENG        (PNX8550_INT_GIC_MIN+26)
+#define PNX8550_INT_MEM_BASED_SCALAR1  (PNX8550_INT_GIC_MIN+27)
+#define PNX8550_INT_VIDEO_MPEG         (PNX8550_INT_GIC_MIN+28)
+#define PNX8550_INT_VIDEO_INPUT_P1     (PNX8550_INT_GIC_MIN+29)
+
+#define PNX8550_INT_VIDEO_INPUT_P2     (PNX8550_INT_GIC_MIN+30)
+#define PNX8550_INT_SPDI1              (PNX8550_INT_GIC_MIN+31)
+#define PNX8550_INT_SPDO               (PNX8550_INT_GIC_MIN+32)
+#define PNX8550_INT_AUDIO_INPUT1       (PNX8550_INT_GIC_MIN+33)
+#define PNX8550_INT_AUDIO_OUTPUT1      (PNX8550_INT_GIC_MIN+34)
+#define PNX8550_INT_AUDIO_INPUT2       (PNX8550_INT_GIC_MIN+35)
+#define PNX8550_INT_AUDIO_OUTPUT2      (PNX8550_INT_GIC_MIN+36)
+#define PNX8550_INT_MEMBASED_SCALAR2   (PNX8550_INT_GIC_MIN+37)
+#define PNX8550_INT_VPK                (PNX8550_INT_GIC_MIN+38)
+#define PNX8550_INT_MPEG1_MIPS         (PNX8550_INT_GIC_MIN+39)
+
+#define PNX8550_INT_MPEG1_TM           (PNX8550_INT_GIC_MIN+40)
+#define PNX8550_INT_MPEG2_MIPS         (PNX8550_INT_GIC_MIN+41)
+#define PNX8550_INT_MPEG2_TM           (PNX8550_INT_GIC_MIN+42)
+#define PNX8550_INT_TS_DMA             (PNX8550_INT_GIC_MIN+43)
+#define PNX8550_INT_EDMA               (PNX8550_INT_GIC_MIN+44)
+#define PNX8550_INT_TM_DEBUG1          (PNX8550_INT_GIC_MIN+45)
+#define PNX8550_INT_TM_DEBUG2          (PNX8550_INT_GIC_MIN+46)
+#define PNX8550_INT_PCI_INTA           (PNX8550_INT_GIC_MIN+47)
+#define PNX8550_INT_CLOCK_MODULE       (PNX8550_INT_GIC_MIN+48)
+#define PNX8550_INT_PCI_XIO_INTA_PCI   (PNX8550_INT_GIC_MIN+49)
+
+#define PNX8550_INT_PCI_XIO_INTB_DMA   (PNX8550_INT_GIC_MIN+50)
+#define PNX8550_INT_PCI_XIO_INTC_GPPM  (PNX8550_INT_GIC_MIN+51)
+#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
+#define PNX8550_INT_DVD_CSS            (PNX8550_INT_GIC_MIN+53)
+#define PNX8550_INT_VLD                (PNX8550_INT_GIC_MIN+54)
+#define PNX8550_INT_GPIO_TSU_7_0       (PNX8550_INT_GIC_MIN+55)
+#define PNX8550_INT_GPIO_TSU_15_8      (PNX8550_INT_GIC_MIN+56)
+#define PNX8550_INT_GPIO_CTU_IR        (PNX8550_INT_GIC_MIN+57)
+#define PNX8550_INT_GPIO0              (PNX8550_INT_GIC_MIN+58)
+#define PNX8550_INT_GPIO1              (PNX8550_INT_GIC_MIN+59)
+
+#define PNX8550_INT_GPIO2              (PNX8550_INT_GIC_MIN+60)
+#define PNX8550_INT_GPIO3              (PNX8550_INT_GIC_MIN+61)
+#define PNX8550_INT_GPIO4              (PNX8550_INT_GIC_MIN+62)
+#define PNX8550_INT_GPIO5              (PNX8550_INT_GIC_MIN+63)
+#define PNX8550_INT_GPIO6              (PNX8550_INT_GIC_MIN+64)
+#define PNX8550_INT_GPIO7              (PNX8550_INT_GIC_MIN+65)
+#define PNX8550_INT_PMAN_SECURITY      (PNX8550_INT_GIC_MIN+66)
+#define PNX8550_INT_I2C3               (PNX8550_INT_GIC_MIN+67)
+#define PNX8550_INT_RESERVED_68        (PNX8550_INT_GIC_MIN+68)
+#define PNX8550_INT_SPDI2              (PNX8550_INT_GIC_MIN+69)
+
+#define PNX8550_INT_I2C4               (PNX8550_INT_GIC_MIN+70)
+
+// Timer are 3 exceptions connected to cp0's 7th hardware exception
+#define PNX8550_INT_TIMER_TOTINT       3
+#define PNX8550_INT_TIMER_MIN          (PNX8550_INT_GIC_MAX+1)
+#define PNX8550_INT_TIMER_MAX          (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
+
+#define PNX8550_INT_TIMER1             (PNX8550_INT_TIMER_MIN+0)
+#define PNX8550_INT_TIMER2             (PNX8550_INT_TIMER_MIN+1)
+#define PNX8550_INT_TIMER3             (PNX8550_INT_TIMER_MIN+2)
+#define PNX8550_INT_WATCHDOG           PNX8550_INT_TIMER3
+
+#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h b/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
new file mode 100644
index 000000000000..bdde00c9199b
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
@@ -0,0 +1,262 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 Embedded Alley Solutions, Inc
+ */
+#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
+#define __ASM_MACH_KERNEL_ENTRY_INIT_H
+
+#include <asm/cacheops.h>
+#include <asm/addrspace.h>
+
+#define CO_CONFIGPR_VALID  0x3F1F41FF    /* valid bits to write to ConfigPR */
+#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
+#define CACHE_OPC      0xBC000000  /* MIPS cache instruction opcode */
+#define ICACHE_LINE_SIZE        32      /* Instruction cache line size bytes */
+#define DCACHE_LINE_SIZE        32      /* Data cache line size in bytes */
+
+#define ICACHE_SET_COUNT        256     /* Instruction cache set count */
+#define DCACHE_SET_COUNT        128     /* Data cache set count */
+
+#define ICACHE_SET_SIZE         (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
+#define DCACHE_SET_SIZE         (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
+
+        .macro  kernel_entry_setup
+        .set    push
+        .set    noreorder
+        /*
+         * PNX8550 entry point, when running a non compressed
+         * kernel. When loading a zImage, the head.S code in
+         * arch/mips/zboot/pnx8550 will init the caches and,
+         * decompress the kernel, and branch to kernel_entry.
+                 */
+cache_begin:    li      t0, (1<<28)
+        mtc0    t0, CP0_STATUS /* cp0 usable */
+        HAZARD_CP0
+
+        mtc0    zero, CP0_CAUSE
+        HAZARD_CP0
+
+
+        /* Set static virtual to phys address translation and TLB disabled */
+        mfc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+
+        and     t0, ~((1<<19) | (1<<20))     /* TLB/MAP cleared */
+        mtc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+
+        /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
+
+        init_icache
+        nop
+        init_dcache
+        nop
+
+        cachePr4450ICReset
+        nop
+
+        cachePr4450DCReset
+        nop
+
+        /* read ConfigPR into t0 */
+        mfc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+
+        /*  enable the TLB */
+        or      t0, (1<<19)
+
+        /* disable the ICACHE: at least 10x slower */
+        /* or      t0, (1<<26) */
+
+        /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set  */
+        /* or      t0, (1<<27) */
+
+        and     t0, CO_CONFIGPR_VALID
+
+        /* enable TLB. */
+        mtc0    t0, CP0_CONFIG, 7
+        HAZARD_CP0
+cache_end:
+        /* Setup CMEM_0 to MMIO address space, 2MB */
+        lui    t0, 0x1BE0
+        addi   t0, t0, 0x3
+        mtc0   $8, $22, 4
+        nop
+
+        /* Setup CMEM_1, 128MB */
+        lui    t0, 0x1000
+        addi   t0, t0, 0xf
+        mtc0   $8, $22, 5
+        nop
+
+
+        /* Setup CMEM_2, 32MB */
+        lui    t0, 0x1C00
+        addi   t0, t0, 0xb
+        mtc0   $8, $22, 6
+        nop
+
+        /* Setup CMEM_3, 0MB */
+        lui    t0, 0x0
+        addi   t0, t0, 0x0
+        mtc0   $8, $22, 7
+        nop
+
+        /* Enable cache */
+        mfc0    t0, CP0_CONFIG
+        HAZARD_CP0
+        and     t0, t0, 0xFFFFFFF8
+        or      t0, t0, 3
+        mtc0    t0, CP0_CONFIG
+        HAZARD_CP0
+        .set    pop
+        .endm
+
+        .macro  init_icache
+        .set    push
+        .set    noreorder
+
+        /* Get Cache Configuration */
+        mfc0    t3, CP0_CONFIG, 1
+        HAZARD_CP0
+
+        /* get cache Line size */
+
+        srl   t1, t3, 19   /* C0_CONFIGPR_IL_SHIFT */
+        andi  t1, t1, 0x7  /* C0_CONFIGPR_IL_MASK */
+        beq   t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
+        nop
+        addiu t0, t1, 1
+        ori   t1, zero, 1
+        sllv  t1, t1, t0
+
+        /* get max cache Index */
+        srl   t2, t3, 22  /* C0_CONFIGPR_IS_SHIFT */
+        andi  t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
+        addiu t0, t2, 6
+        ori   t2, zero, 1
+        sllv  t2, t2, t0
+
+        /* get max cache way */
+        srl   t3, t3, 16  /* C0_CONFIGPR_IA_SHIFT */
+        andi  t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
+        addiu t3, t3, 1
+
+        /* total no of cache lines */
+        multu t2, t3             /* max index * max way */
+        mflo  t2
+        addiu t2, t2, -1
+
+        move  t0, zero
+pr4450_next_instruction_cache_set:
+        cache  Index_Invalidate_I, 0(t0)
+        addu  t0, t0, t1         /* add bytes in a line */
+        bne   t2, zero, pr4450_next_instruction_cache_set
+        addiu t2, t2, -1   /* reduce no of lines to invalidate by one */
+pr4450_instr_cache_invalidated:
+        .set    pop
+        .endm
+
+        .macro  init_dcache
+        .set    push
+        .set    noreorder
+        move t1, zero
+
+        /* Store Tag Information */
+        mtc0    zero, CP0_TAGLO, 0
+        HAZARD_CP0
+
+        mtc0    zero, CP0_TAGHI, 0
+        HAZARD_CP0
+
+        /* Cache size is 16384 = 512 lines x 32 bytes per line */
+        or       t2, zero, (128*4)-1  /* 512 lines  */
+        /* Invalidate all lines */
+2:
+        cache Index_Store_Tag_D, 0(t1)
+        addiu    t2, t2, -1
+        bne      t2, zero, 2b
+        addiu    t1, t1, 32        /* 32 bytes in a line */
+        .set pop
+        .endm
+
+        .macro  cachePr4450ICReset
+        .set    push
+        .set    noreorder
+
+        /* Save CP0 status reg on entry; */
+        /* disable interrupts during cache reset */
+        mfc0    t0, CP0_STATUS      /* T0 = interrupt status on entry */
+        HAZARD_CP0
+
+        mtc0    zero, CP0_STATUS   /* disable CPU interrupts */
+        HAZARD_CP0
+
+        or      t1, zero, zero              /* T1 = starting cache index (0) */
+        ori     t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
+
+        icache_invd_loop:
+        /* 9 == register t1 */
+        .word   CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
+                (0 * ICACHE_SET_SIZE)  /* invalidate inst cache WAY0 */
+        .word   CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
+                (1 * ICACHE_SET_SIZE)  /* invalidate inst cache WAY1 */
+
+        addiu   t1, t1, ICACHE_LINE_SIZE    /* T1 = next cache line index */
+        bne     t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
+        addiu   t2, t2, -1        /* decrement T2 set cnt (delay slot) */
+
+        /* Initialize the latches in the instruction cache tag */
+        /* that drive the way selection tri-state bus drivers, by doing a */
+        /* dummy load while the instruction cache is still disabled. */
+        /* TODO: Is this needed ? */
+        la      t1, KSEG0            /* T1 = cached memory base address */
+        lw      zero, 0x0000(t1)      /* (dummy read of first memory word) */
+
+        mtc0    t0, CP0_STATUS        /* restore interrupt status on entry */
+        HAZARD_CP0
+        .set    pop
+        .endm
+
+        .macro  cachePr4450DCReset
+        .set    push
+        .set    noreorder
+        mfc0    t0, CP0_STATUS           /* T0 = interrupt status on entry */
+        HAZARD_CP0
+        mtc0    zero, CP0_STATUS         /* disable CPU interrupts */
+        HAZARD_CP0
+
+        /* Writeback/invalidate entire data cache sets/ways/lines */
+        or      t1, zero, zero              /* T1 = starting cache index (0) */
+        ori     t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
+
+        dcache_wbinvd_loop:
+        /* 9 == register t1 */
+        .word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (0 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY0 */
+        .word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (1 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY1 */
+        .word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (2 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY2 */
+        .word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
+                (3 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY3 */
+
+        addiu   t1, t1, DCACHE_LINE_SIZE  /* T1 = next data cache line index */
+        bne     t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
+        addiu   t2, t2, -1          /* decrement T2 set cnt (delay slot) */
+
+        /* Initialize the latches in the data cache tag that drive the way
+        selection tri-state bus drivers, by doing a dummy load while the
+        data cache is still in the disabled mode.  TODO: Is this needed ? */
+        la      t1, KSEG0            /* T1 = cached memory base address */
+        lw      zero, 0x0000(t1)      /* (dummy read of first memory word) */
+
+        mtc0    t0, CP0_STATUS       /* restore interrupt status on entry */
+        HAZARD_CP0
+        .set    pop
+        .endm
+
+#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-pnx8550/nand.h b/arch/mips/include/asm/mach-pnx8550/nand.h
new file mode 100644
index 000000000000..aefbc514ab09
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/nand.h
@@ -0,0 +1,121 @@
+#ifndef __PNX8550_NAND_H
+#define __PNX8550_NAND_H
+
+#define PNX8550_NAND_BASE_ADDR   0x10000000
+#define PNX8550_PCIXIO_BASE      0xBBE40000
+
+#define PNX8550_DMA_EXT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
+#define PNX8550_DMA_INT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
+#define PNX8550_DMA_TRANS_SIZE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
+#define PNX8550_DMA_CTRL         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
+#define PNX8550_XIO_SEL0         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
+#define PNX8550_GPXIO_ADDR       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
+#define PNX8550_GPXIO_WR         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
+#define PNX8550_GPXIO_RD         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
+#define PNX8550_GPXIO_CTRL       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
+#define PNX8550_XIO_FLASH_CTRL   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
+#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
+#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
+#define PNX8550_GPXIO_INT_CLEAR  *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
+#define PNX8550_DMA_INT_STATUS   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
+#define PNX8550_DMA_INT_ENABLE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
+#define PNX8550_DMA_INT_CLEAR    *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
+
+#define PNX8550_XIO_SEL0_EN_16BIT    0x00800000
+#define PNX8550_XIO_SEL0_USE_ACK     0x00400000
+#define PNX8550_XIO_SEL0_REN_HIGH    0x00100000
+#define PNX8550_XIO_SEL0_REN_LOW     0x00040000
+#define PNX8550_XIO_SEL0_WEN_HIGH    0x00010000
+#define PNX8550_XIO_SEL0_WEN_LOW     0x00004000
+#define PNX8550_XIO_SEL0_WAIT        0x00000200
+#define PNX8550_XIO_SEL0_OFFSET      0x00000020
+#define PNX8550_XIO_SEL0_TYPE_68360  0x00000000
+#define PNX8550_XIO_SEL0_TYPE_NOR    0x00000008
+#define PNX8550_XIO_SEL0_TYPE_NAND   0x00000010
+#define PNX8550_XIO_SEL0_TYPE_IDE    0x00000018
+#define PNX8550_XIO_SEL0_SIZE_8MB    0x00000000
+#define PNX8550_XIO_SEL0_SIZE_16MB   0x00000002
+#define PNX8550_XIO_SEL0_SIZE_32MB   0x00000004
+#define PNX8550_XIO_SEL0_SIZE_64MB   0x00000006
+#define PNX8550_XIO_SEL0_ENAB        0x00000001
+
+#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT)  | \
+                              (PNX8550_XIO_SEL0_REN_HIGH*0)| \
+                              (PNX8550_XIO_SEL0_REN_LOW*2) | \
+                              (PNX8550_XIO_SEL0_WEN_HIGH*0)| \
+                              (PNX8550_XIO_SEL0_WEN_LOW*2) | \
+                              (PNX8550_XIO_SEL0_WAIT*4)    | \
+                              (PNX8550_XIO_SEL0_OFFSET*0)  | \
+                              (PNX8550_XIO_SEL0_TYPE_NAND) | \
+                              (PNX8550_XIO_SEL0_SIZE_32MB) | \
+                              (PNX8550_XIO_SEL0_ENAB))
+
+#define PNX8550_GPXIO_PENDING        0x00000200
+#define PNX8550_GPXIO_DONE           0x00000100
+#define PNX8550_GPXIO_CLR_DONE       0x00000080
+#define PNX8550_GPXIO_INIT           0x00000040
+#define PNX8550_GPXIO_READ_CMD       0x00000010
+#define PNX8550_GPXIO_BEN            0x0000000F
+
+#define PNX8550_XIO_FLASH_64MB       0x00200000
+#define PNX8550_XIO_FLASH_INC_DATA   0x00100000
+#define PNX8550_XIO_FLASH_CMD_PH     0x000C0000
+#define PNX8550_XIO_FLASH_CMD_PH2    0x00080000
+#define PNX8550_XIO_FLASH_CMD_PH1    0x00040000
+#define PNX8550_XIO_FLASH_CMD_PH0    0x00000000
+#define PNX8550_XIO_FLASH_ADR_PH     0x00030000
+#define PNX8550_XIO_FLASH_ADR_PH3    0x00030000
+#define PNX8550_XIO_FLASH_ADR_PH2    0x00020000
+#define PNX8550_XIO_FLASH_ADR_PH1    0x00010000
+#define PNX8550_XIO_FLASH_ADR_PH0    0x00000000
+#define PNX8550_XIO_FLASH_CMD_B(x)   ((x<<8) & 0x0000FF00)
+#define PNX8550_XIO_FLASH_CMD_A(x)   (x & 0x000000FF)
+
+#define PNX8550_XIO_INT_ACK          0x00004000
+#define PNX8550_XIO_INT_COMPL        0x00002000
+#define PNX8550_XIO_INT_NONSUP       0x00000200
+#define PNX8550_XIO_INT_ABORT        0x00000004
+
+#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
+#define PNX8550_DMA_CTRL_SND2XIO     0x00000200
+#define PNX8550_DMA_CTRL_FIX_ADDR    0x00000100
+#define PNX8550_DMA_CTRL_BURST_8     0x00000000
+#define PNX8550_DMA_CTRL_BURST_16    0x00000020
+#define PNX8550_DMA_CTRL_BURST_32    0x00000040
+#define PNX8550_DMA_CTRL_BURST_64    0x00000060
+#define PNX8550_DMA_CTRL_BURST_128   0x00000080
+#define PNX8550_DMA_CTRL_BURST_256   0x000000A0
+#define PNX8550_DMA_CTRL_BURST_512   0x000000C0
+#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
+#define PNX8550_DMA_CTRL_INIT_DMA    0x00000010
+#define PNX8550_DMA_CTRL_CMD_TYPE    0x0000000F
+
+/* see PCI system arch, page 100 for the full list: */
+#define PNX8550_DMA_CTRL_PCI_CMD_READ    0x00000006
+#define PNX8550_DMA_CTRL_PCI_CMD_WRITE   0x00000007
+
+#define PNX8550_DMA_INT_STAT_ACK_DONE   (1<<14)
+#define PNX8550_DMA_INT_STAT_DMA_DONE   (1<<12)
+#define PNX8550_DMA_INT_STAT_DMA_ERR    (1<<9)
+#define PNX8550_DMA_INT_STAT_PERR5      (1<<5)
+#define PNX8550_DMA_INT_STAT_PERR4      (1<<4)
+#define PNX8550_DMA_INT_STAT_M_ABORT    (1<<2)
+#define PNX8550_DMA_INT_STAT_T_ABORT    (1<<1)
+
+#define PNX8550_DMA_INT_EN_ACK_DONE     (1<<14)
+#define PNX8550_DMA_INT_EN_DMA_DONE     (1<<12)
+#define PNX8550_DMA_INT_EN_DMA_ERR      (1<<9)
+#define PNX8550_DMA_INT_EN_PERR5        (1<<5)
+#define PNX8550_DMA_INT_EN_PERR4        (1<<4)
+#define PNX8550_DMA_INT_EN_M_ABORT      (1<<2)
+#define PNX8550_DMA_INT_EN_T_ABORT      (1<<1)
+
+#define PNX8550_DMA_INT_CLR_ACK_DONE    (1<<14)
+#define PNX8550_DMA_INT_CLR_DMA_DONE    (1<<12)
+#define PNX8550_DMA_INT_CLR_DMA_ERR     (1<<9)
+#define PNX8550_DMA_INT_CLR_PERR5       (1<<5)
+#define PNX8550_DMA_INT_CLR_PERR4       (1<<4)
+#define PNX8550_DMA_INT_CLR_M_ABORT     (1<<2)
+#define PNX8550_DMA_INT_CLR_T_ABORT     (1<<1)
+
+#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/pci.h b/arch/mips/include/asm/mach-pnx8550/pci.h
new file mode 100644
index 000000000000..b921508d701b
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/pci.h
@@ -0,0 +1,185 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * PCI specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_PCI_H
+#define __PNX8550_PCI_H
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+#define PCI_CMD_IOR                     0x20
+#define PCI_CMD_IOW                     0x30
+#define PCI_CMD_CONFIG_READ             0xa0
+#define PCI_CMD_CONFIG_WRITE            0xb0
+
+#define PCI_IO_TIMEOUT                  1000
+#define PCI_IO_RETRY                    5
+/* Timeout for IO and CFG accesses.
+   This is in 1/1024 th of a jiffie(=10ms)
+   i.e. approx 10us */
+#define PCI_IO_JIFFIES_TIMEOUT          40
+#define PCI_IO_JIFFIES_SHIFT            10
+
+#define PCI_BYTE_ENABLE_MASK            0x0000000f
+#define PCI_CFG_BUS_SHIFT               16
+#define PCI_CFG_FUNC_SHIFT              8
+#define PCI_CFG_REG_SHIFT               2
+
+#define PCI_BASE                  0x1be00000
+#define PCI_SETUP                 0x00040010
+#define PCI_DIS_REQGNT           (1<<30)
+#define PCI_DIS_REQGNTA          (1<<29)
+#define PCI_DIS_REQGNTB          (1<<28)
+#define PCI_D2_SUPPORT           (1<<27)
+#define PCI_D1_SUPPORT           (1<<26)
+#define PCI_EN_TA                (1<<24)
+#define PCI_EN_PCI2MMI           (1<<23)
+#define PCI_EN_XIO               (1<<22)
+#define PCI_BASE18_PREF          (1<<21)
+#define SIZE_16M                 0x3
+#define SIZE_32M                 0x4
+#define SIZE_64M                 0x5
+#define SIZE_128M                0x6
+#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
+#define PCI_SETUP_BASE18_EN      (1<<17)
+#define PCI_SETUP_BASE14_PREF    (1<<16)
+#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
+#define PCI_SETUP_BASE14_EN      (1<<11)
+#define PCI_SETUP_BASE10_PREF    (1<<10)
+#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
+#define PCI_SETUP_CFGMANAGE_EN   (1<<1)
+#define PCI_SETUP_PCIARB_EN      (1<<0)
+
+#define PCI_CTRL                  0x040014
+#define PCI_SWPB_DCS_PCI         (1<<16)
+#define PCI_SWPB_PCI_PCI         (1<<15)
+#define PCI_SWPB_PCI_DCS         (1<<14)
+#define PCI_REG_WR_POST          (1<<13)
+#define PCI_XIO_WR_POST          (1<<12)
+#define PCI_PCI2_WR_POST         (1<<13)
+#define PCI_PCI1_WR_POST         (1<<12)
+#define PCI_SERR_SEEN            (1<<11)
+#define PCI_B10_SPEC_RD          (1<<6)
+#define PCI_B14_SPEC_RD          (1<<5)
+#define PCI_B18_SPEC_RD          (1<<4)
+#define PCI_B10_NOSUBWORD        (1<<3)
+#define PCI_B14_NOSUBWORD        (1<<2)
+#define PCI_B18_NOSUBWORD        (1<<1)
+#define PCI_RETRY_TMREN          (1<<0)
+
+#define PCI_BASE1_LO              0x040018
+#define PCI_BASE1_HI              0x04001C
+#define PCI_BASE2_LO              0x040020
+#define PCI_BASE2_HI              0x040024
+#define PCI_RDLIFETIM             0x040028
+#define PCI_GPPM_ADDR             0x04002C
+#define PCI_GPPM_WDAT             0x040030
+#define PCI_GPPM_RDAT             0x040034
+#define PCI_GPPM_CTRL             0x040038
+#define GPPM_DONE                (1<<10)
+#define INIT_PCI_CYCLE           (1<<9)
+#define GPPM_CMD(X)              (((X)&0xf)<<4)
+#define GPPM_BYTEEN(X)           ((X)&0xf)
+#define PCI_UNLOCKREG             0x04003C
+#define UNLOCK_SSID(X)           (((X)&0xff)<<8)
+#define UNLOCK_SETUP(X)          (((X)&0xff)<<0)
+#define UNLOCK_MAGIC             0xCA
+#define PCI_DEV_VEND_ID           0x040040
+#define DEVICE_ID(X)             (((X)>>16)&0xffff)
+#define VENDOR_ID(X)             (((X)&0xffff))
+#define PCI_CFG_CMDSTAT           0x040044
+#define PCI_CFG_STATUS(X)            (((X)>>16)&0xffff)
+#define PCI_CFG_COMMAND(X)           ((X)&0xffff)
+#define PCI_CLASS_REV             0x040048
+#define PCI_CLASSCODE(X)         (((X)>>8)&0xffffff)
+#define PCI_REVID(X)             ((X)&0xff)
+#define PCI_LAT_TMR     0x04004c
+#define PCI_BASE10      0x040050
+#define PCI_BASE14      0x040054
+#define PCI_BASE18      0x040058
+#define PCI_SUBSYS_ID   0x04006c
+#define PCI_CAP_PTR     0x040074
+#define PCI_CFG_MISC    0x04007c
+#define PCI_PMC         0x040080
+#define PCI_PWR_STATE   0x040084
+#define PCI_IO          0x040088
+#define PCI_SLVTUNING   0x04008C
+#define PCI_DMATUNING   0x040090
+#define PCI_DMAEADDR    0x040800
+#define PCI_DMAIADDR    0x040804
+#define PCI_DMALEN      0x040808
+#define PCI_DMACTRL     0x04080C
+#define PCI_XIOCTRL     0x040810
+#define PCI_SEL0PROF    0x040814
+#define PCI_SEL1PROF    0x040818
+#define PCI_SEL2PROF    0x04081C
+#define PCI_GPXIOADDR   0x040820
+#define PCI_NANDCTRLS   0x400830
+#define PCI_SEL3PROF    0x040834
+#define PCI_SEL4PROF    0x040838
+#define PCI_GPXIO_STAT  0x040FB0
+#define PCI_GPXIO_IMASK 0x040FB4
+#define PCI_GPXIO_ICLR  0x040FB8
+#define PCI_GPXIO_ISET  0x040FBC
+#define PCI_GPPM_STATUS 0x040FC0
+#define GPPM_DONE      (1<<10)
+#define GPPM_ERR       (1<<9)
+#define GPPM_MPAR_ERR  (1<<8)
+#define GPPM_PAR_ERR   (1<<7)
+#define GPPM_R_MABORT  (1<<2)
+#define GPPM_R_TABORT  (1<<1)
+#define PCI_GPPM_IMASK  0x040FC4
+#define PCI_GPPM_ICLR   0x040FC8
+#define PCI_GPPM_ISET   0x040FCC
+#define PCI_DMA_STATUS  0x040FD0
+#define PCI_DMA_IMASK   0x040FD4
+#define PCI_DMA_ICLR    0x040FD8
+#define PCI_DMA_ISET    0x040FDC
+#define PCI_ISTATUS     0x040FE0
+#define PCI_IMASK       0x040FE4
+#define PCI_ICLR        0x040FE8
+#define PCI_ISET        0x040FEC
+#define PCI_MOD_ID      0x040FFC
+
+/*
+ *  PCI configuration cycle AD bus definition
+ */
+/* Type 0 */
+#define PCI_CFG_TYPE0_REG_SHF           0
+#define PCI_CFG_TYPE0_FUNC_SHF          8
+
+/* Type 1 */
+#define PCI_CFG_TYPE1_REG_SHF           0
+#define PCI_CFG_TYPE1_FUNC_SHF          8
+#define PCI_CFG_TYPE1_DEV_SHF           11
+#define PCI_CFG_TYPE1_BUS_SHF           16
+
+/*
+ *  Ethernet device DP83816 definition
+ */
+#define DP83816_IRQ_ETHER               66
+
+#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/uart.h b/arch/mips/include/asm/mach-pnx8550/uart.h
new file mode 100644
index 000000000000..ad7608d44874
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/uart.h
@@ -0,0 +1,30 @@
+#ifndef __IP3106_UART_H
+#define __IP3106_UART_H
+
+#include <int.h>
+
+/* early macros for kgdb use. fixme: clean this up */
+
+#define UART_BASE               0xbbe4a000      /* PNX8550 */
+
+#define PNX8550_UART_PORT0      (UART_BASE)
+#define PNX8550_UART_PORT1      (UART_BASE + 0x1000)
+
+#define PNX8550_UART_INT(x)             (PNX8550_INT_GIC_MIN+19+x)
+#define IRQ_TO_UART(x)                  (x-PNX8550_INT_GIC_MIN-19)
+
+/* early macros needed for prom/kgdb */
+
+#define ip3106_lcr(base, port)    *(volatile u32 *)(base+(port*0x1000) + 0x000)
+#define ip3106_mcr(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x004)
+#define ip3106_baud(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0x008)
+#define ip3106_cfg(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x00C)
+#define ip3106_fifo(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0x028)
+#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
+#define ip3106_ien(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
+#define ip3106_iclr(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
+#define ip3106_iset(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
+#define ip3106_pd(base, port)    *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
+#define ip3106_mid(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
+
+#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/usb.h b/arch/mips/include/asm/mach-pnx8550/usb.h
new file mode 100644
index 000000000000..483b7fc65d41
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/usb.h
@@ -0,0 +1,32 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *  USB specific definitions
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+
+#ifndef __PNX8550_USB_H
+#define __PNX8550_USB_H
+
+/*
+ * USB Host controller
+ */
+
+#define PNX8550_USB_OHCI_OP_BASE        0x1be48000
+#define PNX8550_USB_OHCI_OP_LEN         0x1000
+
+#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/war.h b/arch/mips/include/asm/mach-pnx8550/war.h
new file mode 100644
index 000000000000..d0458dd082f9
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H
+#define __ASM_MIPS_MACH_PNX8550_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f3bc7efa2608
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
@@ -0,0 +1,81 @@
+/*
+ *  IDT RC32434 specific CPU feature overrides
+ *
+ *  Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This file was derived from: include/asm-mips/cpu-features.h
+ *      Copyright (C) 2003, 2004 Ralf Baechle
+ *      Copyright (C) 2004 Maciej W. Rozycki
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the
+ *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ *  Boston, MA  02110-1301, USA.
+ */
+#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
+ */
+#define cpu_has_tlb                     1
+#define cpu_has_4kex                    1
+#define cpu_has_3k_cache                0
+#define cpu_has_4k_cache                1
+#define cpu_has_tx39_cache              0
+#define cpu_has_sb1_cache               0
+#define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
+#define cpu_has_counter                 1
+#define cpu_has_watch                   1
+#define cpu_has_divec                   1
+#define cpu_has_vce                     0
+#define cpu_has_cache_cdex_p            0
+#define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
+#define cpu_has_mcheck                  1
+#define cpu_has_ejtag                   1
+#define cpu_has_llsc                    1
+
+#define cpu_has_mips16                  0
+#define cpu_has_mdmx                    0
+#define cpu_has_mips3d                  0
+#define cpu_has_smartmips               0
+
+#define cpu_has_vtag_icache             0
+/* #define cpu_has_dc_aliases           ? */
+/* #define cpu_has_ic_fills_f_dc        ? */
+/* #define cpu_has_pindexed_dcache      ? */
+
+/* #define cpu_icache_snoops_remote_store       ? */
+
+#define cpu_has_mips32r1                1
+#define cpu_has_mips32r2                0
+#define cpu_has_mips64r1                0
+#define cpu_has_mips64r2                0
+
+#define cpu_has_dsp                     0
+#define cpu_has_mipsmt                  0
+
+/* #define cpu_has_nofpuex              ? */
+#define cpu_has_64bits                  0
+#define cpu_has_64bit_zero_reg          0
+#define cpu_has_64bit_gp_regs           0
+#define cpu_has_64bit_addresses         0
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()          16
+#define cpu_icache_line_size()          16
+
+#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-rc32434/ddr.h b/arch/mips/include/asm/mach-rc32434/ddr.h
new file mode 100644
index 000000000000..291e2cf9dde0
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/ddr.h
@@ -0,0 +1,141 @@
+/*
+ *  Definitions for the DDR registers
+ *
+ *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _ASM_RC32434_DDR_H_
+#define _ASM_RC32434_DDR_H_
+
+#include <asm/mach-rc32434/rb.h>
+
+/* DDR register structure */
+struct ddr_ram {
+        u32 ddrbase;
+        u32 ddrmask;
+        u32 res1;
+        u32 res2;
+        u32 ddrc;
+        u32 ddrabase;
+        u32 ddramask;
+        u32 ddramap;
+        u32 ddrcust;
+        u32 ddrrdc;
+        u32 ddrspare;
+};
+
+#define DDR0_PHYS_ADDR          0x18018000
+
+/* DDR banks masks */
+#define DDR_MASK                0xffff0000
+#define DDR0_BASE_MSK           DDR_MASK
+#define DDR1_BASE_MSK           DDR_MASK
+
+/* DDR bank0 registers */
+#define RC32434_DDR0_ATA_BIT            5
+#define RC32434_DDR0_ATA_MSK            0x000000E0
+#define RC32434_DDR0_DBW_BIT            8
+#define RC32434_DDR0_DBW_MSK            0x00000100
+#define RC32434_DDR0_WR_BIT             9
+#define RC32434_DDR0_WR_MSK             0x00000600
+#define RC32434_DDR0_PS_BIT             11
+#define RC32434_DDR0_PS_MSK             0x00001800
+#define RC32434_DDR0_DTYPE_BIT          13
+#define RC32434_DDR0_DTYPE_MSK          0x0000e000
+#define RC32434_DDR0_RFC_BIT            16
+#define RC32434_DDR0_RFC_MSK            0x000f0000
+#define RC32434_DDR0_RP_BIT             20
+#define RC32434_DDR0_RP_MSK             0x00300000
+#define RC32434_DDR0_AP_BIT             22
+#define RC32434_DDR0_AP_MSK             0x00400000
+#define RC32434_DDR0_RCD_BIT            23
+#define RC32434_DDR0_RCD_MSK            0x01800000
+#define RC32434_DDR0_CL_BIT             25
+#define RC32434_DDR0_CL_MSK             0x06000000
+#define RC32434_DDR0_DBM_BIT            27
+#define RC32434_DDR0_DBM_MSK            0x08000000
+#define RC32434_DDR0_SDS_BIT            28
+#define RC32434_DDR0_SDS_MSK            0x10000000
+#define RC32434_DDR0_ATP_BIT            29
+#define RC32434_DDR0_ATP_MSK            0x60000000
+#define RC32434_DDR0_RE_BIT             31
+#define RC32434_DDR0_RE_MSK             0x80000000
+
+/* DDR bank C registers */
+#define RC32434_DDRC_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_DDRC_CES_BIT            0
+#define RC32434_DDRC_ACE_BIT            1
+
+/* Custom DDR bank registers */
+#define RC32434_DCST_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_DCST_CS_BIT             0
+#define RC32434_DCST_CS_MSK             0x00000003
+#define RC32434_DCST_WE_BIT             2
+#define RC32434_DCST_RAS_BIT            3
+#define RC32434_DCST_CAS_BIT            4
+#define RC32434_DSCT_CKE_BIT            5
+#define RC32434_DSCT_BA_BIT             6
+#define RC32434_DSCT_BA_MSK             0x000000c0
+
+/* DDR QSC registers */
+#define RC32434_QSC_DM_BIT              0
+#define RC32434_QSC_DM_MSK              0x00000003
+#define RC32434_QSC_DQSBS_BIT           2
+#define RC32434_QSC_DQSBS_MSK           0x000000fc
+#define RC32434_QSC_DB_BIT              8
+#define RC32434_QSC_DB_MSK              0x00000100
+#define RC32434_QSC_DBSP_BIT            9
+#define RC32434_QSC_DBSP_MSK            0x01fffe00
+#define RC32434_QSC_BDP_BIT             25
+#define RC32434_QSC_BDP_MSK             0x7e000000
+
+/* DDR LLC registers */
+#define RC32434_LLC_EAO_BIT             0
+#define RC32434_LLC_EAO_MSK             0x00000001
+#define RC32434_LLC_EO_BIT              1
+#define RC32434_LLC_EO_MSK              0x0000003e
+#define RC32434_LLC_FS_BIT              6
+#define RC32434_LLC_FS_MSK              0x000000c0
+#define RC32434_LLC_AS_BIT              8
+#define RC32434_LLC_AS_MSK              0x00000700
+#define RC32434_LLC_SP_BIT              11
+#define RC32434_LLC_SP_MSK              0x001ff800
+
+/* DDR LLFC registers */
+#define RC32434_LLFC_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_LLFC_MEN_BIT            0
+#define RC32434_LLFC_EAN_BIT            1
+#define RC32434_LLFC_FF_BIT             2
+
+/* DDR DLLTA registers */
+#define RC32434_DLLTA_ADDR_BIT          2
+#define RC32434_DLLTA_ADDR_MSK          0xfffffffc
+
+/* DDR DLLED registers */
+#define RC32434_DLLED_MSK(x)            BIT_TO_MASK(x)
+#define RC32434_DLLED_DBE_BIT           0
+#define RC32434_DLLED_DTE_BIT           1
+
+#endif  /* _ASM_RC32434_DDR_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/dma.h b/arch/mips/include/asm/mach-rc32434/dma.h
new file mode 100644
index 000000000000..5f898b5873f7
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/dma.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ *              All rights reserved.
+ *
+ * DMA register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date   : 20011005
+ */
+
+#ifndef __ASM_RC32434_DMA_H
+#define __ASM_RC32434_DMA_H
+
+#include <asm/mach-rc32434/rb.h>
+
+#define DMA0_BASE_ADDR                  0x18040000
+
+/*
+ * DMA descriptor (in physical memory).
+ */
+
+struct dma_desc {
+        u32 control;                    /* Control. use DMAD_* */
+        u32 ca;                         /* Current Address. */
+        u32 devcs;                      /* Device control and status. */
+        u32 link;                       /* Next descriptor in chain. */
+};
+
+#define DMA_DESC_SIZ                    sizeof(struct dma_desc)
+#define DMA_DESC_COUNT_BIT              0
+#define DMA_DESC_COUNT_MSK              0x0003ffff
+#define DMA_DESC_DS_BIT                 20
+#define DMA_DESC_DS_MSK                 0x00300000
+
+#define DMA_DESC_DEV_CMD_BIT            22
+#define DMA_DESC_DEV_CMD_MSK            0x01c00000
+
+/* DMA command sizes */
+#define DMA_DESC_DEV_CMD_BYTE           0
+#define DMA_DESC_DEV_CMD_HLF_WD         1
+#define DMA_DESC_DEV_CMD_WORD           2
+#define DMA_DESC_DEV_CMD_2WORDS         3
+#define DMA_DESC_DEV_CMD_4WORDS         4
+#define DMA_DESC_DEV_CMD_6WORDS         5
+#define DMA_DESC_DEV_CMD_8WORDS         6
+#define DMA_DESC_DEV_CMD_16WORDS        7
+
+/* DMA descriptors interrupts */
+#define DMA_DESC_COF                    (1 << 25) /* Chain on finished */
+#define DMA_DESC_COD                    (1 << 26) /* Chain on done */
+#define DMA_DESC_IOF                    (1 << 27) /* Interrupt on finished */
+#define DMA_DESC_IOD                    (1 << 28) /* Interrupt on done */
+#define DMA_DESC_TERM                   (1 << 29) /* Terminated */
+#define DMA_DESC_DONE                   (1 << 30) /* Done */
+#define DMA_DESC_FINI                   (1 << 31) /* Finished */
+
+/*
+ * DMA register (within Internal Register Map).
+ */
+
+struct dma_reg {
+        u32 dmac;               /* Control. */
+        u32 dmas;               /* Status. */
+        u32 dmasm;              /* Mask. */
+        u32 dmadptr;            /* Descriptor pointer. */
+        u32 dmandptr;           /* Next descriptor pointer. */
+};
+
+/* DMA channels specific registers */
+#define DMA_CHAN_RUN_BIT                (1 << 0)
+#define DMA_CHAN_DONE_BIT               (1 << 1)
+#define DMA_CHAN_MODE_BIT               (1 << 2)
+#define DMA_CHAN_MODE_MSK               0x0000000c
+#define  DMA_CHAN_MODE_AUTO             0
+#define  DMA_CHAN_MODE_BURST            1
+#define  DMA_CHAN_MODE_XFRT             2
+#define  DMA_CHAN_MODE_RSVD             3
+#define DMA_CHAN_ACT_BIT                (1 << 4)
+
+/* DMA status registers */
+#define DMA_STAT_FINI                   (1 << 0)
+#define DMA_STAT_DONE                   (1 << 1)
+#define DMA_STAT_CHAIN                  (1 << 2)
+#define DMA_STAT_ERR                    (1 << 3)
+#define DMA_STAT_HALT                   (1 << 4)
+
+/*
+ * DMA channel definitions
+ */
+
+#define DMA_CHAN_ETH_RCV                0
+#define DMA_CHAN_ETH_XMT                1
+#define DMA_CHAN_MEM_TO_FIFO            2
+#define DMA_CHAN_FIFO_TO_MEM            3
+#define DMA_CHAN_PCI_TO_MEM             4
+#define DMA_CHAN_MEM_TO_PCI             5
+#define DMA_CHAN_COUNT                  6
+
+struct dma_channel {
+        struct dma_reg ch[DMA_CHAN_COUNT];
+};
+
+#endif  /* __ASM_RC32434_DMA_H */
diff --git a/arch/mips/include/asm/mach-rc32434/dma_v.h b/arch/mips/include/asm/mach-rc32434/dma_v.h
new file mode 100644
index 000000000000..173a9f9146cd
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/dma_v.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ *              All rights reserved.
+ *
+ * DMA register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date   : 20011005
+ */
+
+#ifndef _ASM_RC32434_DMA_V_H_
+#define _ASM_RC32434_DMA_V_H_
+
+#include  <asm/mach-rc32434/dma.h>
+#include  <asm/mach-rc32434/rc32434.h>
+
+#define DMA_CHAN_OFFSET         0x14
+#define IS_DMA_USED(X)          (((X) & \
+                                (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
+                                != 0)
+#define DMA_COUNT(count)        ((count) & DMA_DESC_COUNT_MSK)
+
+#define DMA_HALT_TIMEOUT        500
+
+static inline int rc32434_halt_dma(struct dma_reg *ch)
+{
+        int timeout = 1;
+        if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
+                __raw_writel(0, &ch->dmac);
+                for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
+                        if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
+                                __raw_writel(0, &ch->dmas);
+                                break;
+                        }
+                }
+        }
+
+        return timeout ? 0 : 1;
+}
+
+static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
+{
+        __raw_writel(0, &ch->dmandptr);
+        __raw_writel(dma_addr, &ch->dmadptr);
+}
+
+static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
+{
+        __raw_writel(dma_addr, &ch->dmandptr);
+}
+
+#endif  /* _ASM_RC32434_DMA_V_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/eth.h b/arch/mips/include/asm/mach-rc32434/eth.h
new file mode 100644
index 000000000000..a25cbc56173d
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/eth.h
@@ -0,0 +1,220 @@
+/*
+ *  Definitions for the Ethernet registers
+ *
+ *  Copyright 2002 Allend Stichter <allen.stichter@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_RC32434_ETH_H
+#define __ASM_RC32434_ETH_H
+
+
+#define ETH0_BASE_ADDR          0x18060000
+
+struct eth_regs {
+        u32 ethintfc;
+        u32 ethfifott;
+        u32 etharc;
+        u32 ethhash0;
+        u32 ethhash1;
+        u32 ethu0[4];           /* Reserved. */
+        u32 ethpfs;
+        u32 ethmcp;
+        u32 eth_u1[10];         /* Reserved. */
+        u32 ethspare;
+        u32 eth_u2[42];         /* Reserved. */
+        u32 ethsal0;
+        u32 ethsah0;
+        u32 ethsal1;
+        u32 ethsah1;
+        u32 ethsal2;
+        u32 ethsah2;
+        u32 ethsal3;
+        u32 ethsah3;
+        u32 ethrbc;
+        u32 ethrpc;
+        u32 ethrupc;
+        u32 ethrfc;
+        u32 ethtbc;
+        u32 ethgpf;
+        u32 eth_u9[50];         /* Reserved. */
+        u32 ethmac1;
+        u32 ethmac2;
+        u32 ethipgt;
+        u32 ethipgr;
+        u32 ethclrt;
+        u32 ethmaxf;
+        u32 eth_u10;            /* Reserved. */
+        u32 ethmtest;
+        u32 miimcfg;
+        u32 miimcmd;
+        u32 miimaddr;
+        u32 miimwtd;
+        u32 miimrdd;
+        u32 miimind;
+        u32 eth_u11;            /* Reserved. */
+        u32 eth_u12;            /* Reserved. */
+        u32 ethcfsa0;
+        u32 ethcfsa1;
+        u32 ethcfsa2;
+};
+
+/* Ethernet interrupt registers */
+#define ETH_INT_FC_EN           (1 << 0)
+#define ETH_INT_FC_ITS          (1 << 1)
+#define ETH_INT_FC_RIP          (1 << 2)
+#define ETH_INT_FC_JAM          (1 << 3)
+#define ETH_INT_FC_OVR          (1 << 4)
+#define ETH_INT_FC_UND          (1 << 5)
+#define ETH_INT_FC_IOC          0x000000c0
+
+/* Ethernet FIFO registers */
+#define ETH_FIFI_TT_TTH_BIT     0
+#define ETH_FIFO_TT_TTH         0x0000007f
+
+/* Ethernet ARC/multicast registers */
+#define ETH_ARC_PRO             (1 << 0)
+#define ETH_ARC_AM              (1 << 1)
+#define ETH_ARC_AFM             (1 << 2)
+#define ETH_ARC_AB              (1 << 3)
+
+/* Ethernet SAL registers */
+#define ETH_SAL_BYTE_5          0x000000ff
+#define ETH_SAL_BYTE_4          0x0000ff00
+#define ETH_SAL_BYTE_3          0x00ff0000
+#define ETH_SAL_BYTE_2          0xff000000
+
+/* Ethernet SAH registers */
+#define ETH_SAH_BYTE1           0x000000ff
+#define ETH_SAH_BYTE0           0x0000ff00
+
+/* Ethernet GPF register */
+#define ETH_GPF_PTV             0x0000ffff
+
+/* Ethernet PFG register */
+#define ETH_PFS_PFD             (1 << 0)
+
+/* Ethernet CFSA[0-3] registers */
+#define ETH_CFSA0_CFSA4         0x000000ff
+#define ETH_CFSA0_CFSA5         0x0000ff00
+#define ETH_CFSA1_CFSA2         0x000000ff
+#define ETH_CFSA1_CFSA3         0x0000ff00
+#define ETH_CFSA1_CFSA0         0x000000ff
+#define ETH_CFSA1_CFSA1         0x0000ff00
+
+/* Ethernet MAC1 registers */
+#define ETH_MAC1_RE             (1 << 0)
+#define ETH_MAC1_PAF            (1 << 1)
+#define ETH_MAC1_RFC            (1 << 2)
+#define ETH_MAC1_TFC            (1 << 3)
+#define ETH_MAC1_LB             (1 << 4)
+#define ETH_MAC1_MR             (1 << 31)
+
+/* Ethernet MAC2 registers */
+#define ETH_MAC2_FD             (1 << 0)
+#define ETH_MAC2_FLC            (1 << 1)
+#define ETH_MAC2_HFE            (1 << 2)
+#define ETH_MAC2_DC             (1 << 3)
+#define ETH_MAC2_CEN            (1 << 4)
+#define ETH_MAC2_PE             (1 << 5)
+#define ETH_MAC2_VPE            (1 << 6)
+#define ETH_MAC2_APE            (1 << 7)
+#define ETH_MAC2_PPE            (1 << 8)
+#define ETH_MAC2_LPE            (1 << 9)
+#define ETH_MAC2_NB             (1 << 12)
+#define ETH_MAC2_BP             (1 << 13)
+#define ETH_MAC2_ED             (1 << 14)
+
+/* Ethernet IPGT register */
+#define ETH_IPGT                0x0000007f
+
+/* Ethernet IPGR registers */
+#define ETH_IPGR_IPGR2          0x0000007f
+#define ETH_IPGR_IPGR1          0x00007f00
+
+/* Ethernet CLRT registers */
+#define ETH_CLRT_MAX_RET        0x0000000f
+#define ETH_CLRT_COL_WIN        0x00003f00
+
+/* Ethernet MAXF register */
+#define ETH_MAXF                0x0000ffff
+
+/* Ethernet test registers */
+#define ETH_TEST_REG            (1 << 2)
+#define ETH_MCP_DIV             0x000000ff
+
+/* MII registers */
+#define ETH_MII_CFG_RSVD        0x0000000c
+#define ETH_MII_CMD_RD          (1 << 0)
+#define ETH_MII_CMD_SCN         (1 << 1)
+#define ETH_MII_REG_ADDR        0x0000001f
+#define ETH_MII_PHY_ADDR        0x00001f00
+#define ETH_MII_WTD_DATA        0x0000ffff
+#define ETH_MII_RDD_DATA        0x0000ffff
+#define ETH_MII_IND_BSY         (1 << 0)
+#define ETH_MII_IND_SCN         (1 << 1)
+#define ETH_MII_IND_NV          (1 << 2)
+
+/*
+ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
+ */
+
+#define ETH_RX_FD               (1 << 0)
+#define ETH_RX_LD               (1 << 1)
+#define ETH_RX_ROK              (1 << 2)
+#define ETH_RX_FM               (1 << 3)
+#define ETH_RX_MP               (1 << 4)
+#define ETH_RX_BP               (1 << 5)
+#define ETH_RX_VLT              (1 << 6)
+#define ETH_RX_CF               (1 << 7)
+#define ETH_RX_OVR              (1 << 8)
+#define ETH_RX_CRC              (1 << 9)
+#define ETH_RX_CV               (1 << 10)
+#define ETH_RX_DB               (1 << 11)
+#define ETH_RX_LE               (1 << 12)
+#define ETH_RX_LOR              (1 << 13)
+#define ETH_RX_CES              (1 << 14)
+#define ETH_RX_LEN_BIT          16
+#define ETH_RX_LEN              0xffff0000
+
+#define ETH_TX_FD               (1 << 0)
+#define ETH_TX_LD               (1 << 1)
+#define ETH_TX_OEN              (1 << 2)
+#define ETH_TX_PEN              (1 << 3)
+#define ETH_TX_CEN              (1 << 4)
+#define ETH_TX_HEN              (1 << 5)
+#define ETH_TX_TOK              (1 << 6)
+#define ETH_TX_MP               (1 << 7)
+#define ETH_TX_BP               (1 << 8)
+#define ETH_TX_UND              (1 << 9)
+#define ETH_TX_OF               (1 << 10)
+#define ETH_TX_ED               (1 << 11)
+#define ETH_TX_EC               (1 << 12)
+#define ETH_TX_LC               (1 << 13)
+#define ETH_TX_TD               (1 << 14)
+#define ETH_TX_CRC              (1 << 15)
+#define ETH_TX_LE               (1 << 16)
+#define ETH_TX_CC               0x001E0000
+
+#endif  /* __ASM_RC32434_ETH_H */
diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
new file mode 100644
index 000000000000..c8e554eafce3
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2002 Integrated Device Technology, Inc.
+ *      All rights reserved.
+ *
+ * GPIO register definition.
+ *
+ * Author : ryan.holmQVist@idt.com
+ * Date   : 20011005
+ * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ */
+
+#ifndef _RC32434_GPIO_H_
+#define _RC32434_GPIO_H_
+
+#include <linux/types.h>
+#include <asm-generic/gpio.h>
+
+#define NR_BUILTIN_GPIO         32
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+
+#define gpio_to_irq(gpio)       (8 + 4 * 32 + gpio)
+#define irq_to_gpio(irq)        (irq - (8 + 4 * 32))
+
+struct rb532_gpio_reg {
+        u32   gpiofunc;   /* GPIO Function Register
+                           * gpiofunc[x]==0 bit = gpio
+                           * func[x]==1  bit = altfunc
+                           */
+        u32   gpiocfg;    /* GPIO Configuration Register
+                           * gpiocfg[x]==0 bit = input
+                           * gpiocfg[x]==1 bit = output
+                           */
+        u32   gpiod;      /* GPIO Data Register
+                           * gpiod[x] read/write gpio pinX status
+                           */
+        u32   gpioilevel; /* GPIO Interrupt Status Register
+                           * interrupt level (see gpioistat)
+                           */
+        u32   gpioistat;  /* Gpio Interrupt Status Register
+                           * istat[x] = (gpiod[x] == level[x])
+                           * cleared in ISR (STICKY bits)
+                           */
+        u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
+};
+
+/* UART GPIO signals */
+#define RC32434_UART0_SOUT      (1 << 0)
+#define RC32434_UART0_SIN       (1 << 1)
+#define RC32434_UART0_RTS       (1 << 2)
+#define RC32434_UART0_CTS       (1 << 3)
+
+/* M & P bus GPIO signals */
+#define RC32434_MP_BIT_22       (1 << 4)
+#define RC32434_MP_BIT_23       (1 << 5)
+#define RC32434_MP_BIT_24       (1 << 6)
+#define RC32434_MP_BIT_25       (1 << 7)
+
+/* CPU GPIO signals */
+#define RC32434_CPU_GPIO        (1 << 8)
+
+/* Reserved GPIO signals */
+#define RC32434_AF_SPARE_6      (1 << 9)
+#define RC32434_AF_SPARE_4      (1 << 10)
+#define RC32434_AF_SPARE_3      (1 << 11)
+#define RC32434_AF_SPARE_2      (1 << 12)
+
+/* PCI messaging unit */
+#define RC32434_PCI_MSU_GPIO    (1 << 13)
+
+/* NAND GPIO signals */
+#define GPIO_RDY                8
+#define GPIO_WPX        9
+#define GPIO_ALE                10
+#define GPIO_CLE                11
+
+/* Compact Flash GPIO pin */
+#define CF_GPIO_NUM             13
+
+extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
+extern unsigned get_434_reg(unsigned reg_offs);
+extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
+extern unsigned char get_latch_u5(void);
+
+#endif /* _RC32434_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/integ.h b/arch/mips/include/asm/mach-rc32434/integ.h
new file mode 100644
index 000000000000..fa65bc3d8807
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/integ.h
@@ -0,0 +1,59 @@
+/*
+ *  Definitions for the Watchdog registers
+ *
+ *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __RC32434_INTEG_H__
+#define __RC32434_INTEG_H__
+
+#include <asm/mach-rc32434/rb.h>
+
+#define INTEG0_BASE_ADDR        0x18030030
+
+struct integ {
+        u32 errcs;                      /* sticky use ERRCS_ */
+        u32 wtcount;                    /* Watchdog timer count reg. */
+        u32 wtcompare;                  /* Watchdog timer timeout value. */
+        u32 wtc;                        /* Watchdog timer control. use WTC_ */
+};
+
+/* Error counters */
+#define RC32434_ERR_WTO         0
+#define RC32434_ERR_WNE         1
+#define RC32434_ERR_UCW         2
+#define RC32434_ERR_UCR         3
+#define RC32434_ERR_UPW         4
+#define RC32434_ERR_UPR         5
+#define RC32434_ERR_UDW         6
+#define RC32434_ERR_UDR         7
+#define RC32434_ERR_SAE         8
+#define RC32434_ERR_WRE         9
+
+/* Watchdog control bits */
+#define RC32434_WTC_EN          0
+#define RC32434_WTC_TO          1
+
+#endif  /* __RC32434_INTEG_H__ */
diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h
new file mode 100644
index 000000000000..56738d8ec4e2
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/irq.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_RC32434_IRQ_H
+#define __ASM_RC32434_IRQ_H
+
+#define NR_IRQS 256
+
+#include <asm/mach-generic/irq.h>
+#include <asm/mach-rc32434/rb.h>
+
+/* Interrupt Controller */
+#define IC_GROUP0_PEND          (REGBASE + 0x38000)
+#define IC_GROUP0_MASK          (REGBASE + 0x38008)
+#define IC_GROUP_OFFSET         0x0C
+
+#define NUM_INTR_GROUPS         5
+
+/* 16550 UARTs */
+#define GROUP0_IRQ_BASE         8       /* GRP2 IRQ numbers start here */
+                                        /* GRP3 IRQ numbers start here */
+#define GROUP1_IRQ_BASE         (GROUP0_IRQ_BASE + 32)
+                                        /* GRP4 IRQ numbers start here */
+#define GROUP2_IRQ_BASE         (GROUP1_IRQ_BASE + 32)
+                                        /* GRP5 IRQ numbers start here */
+#define GROUP3_IRQ_BASE         (GROUP2_IRQ_BASE + 32)
+#define GROUP4_IRQ_BASE         (GROUP3_IRQ_BASE + 32)
+
+#define UART0_IRQ               (GROUP3_IRQ_BASE + 0)
+
+#define ETH0_DMA_RX_IRQ         (GROUP1_IRQ_BASE + 0)
+#define ETH0_DMA_TX_IRQ         (GROUP1_IRQ_BASE + 1)
+#define ETH0_RX_OVR_IRQ         (GROUP3_IRQ_BASE + 9)
+#define ETH0_TX_UND_IRQ         (GROUP3_IRQ_BASE + 10)
+
+#endif  /* __ASM_RC32434_IRQ_H */
diff --git a/arch/mips/include/asm/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h
new file mode 100644
index 000000000000..410638f2af74
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/pci.h
@@ -0,0 +1,481 @@
+/*
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
+ *
+ * Initial Release
+ */
+
+#ifndef _ASM_RC32434_PCI_H_
+#define _ASM_RC32434_PCI_H_
+
+#define epld_mask ((volatile unsigned char *)0xB900000d)
+
+#define PCI0_BASE_ADDR          0x18080000
+#define PCI_LBA_COUNT           4
+
+struct pci_map {
+        u32 address;            /* Address. */
+        u32 control;            /* Control. */
+        u32 mapping;            /* mapping. */
+};
+
+struct pci_reg {
+        u32 pcic;
+        u32 pcis;
+        u32 pcism;
+        u32 pcicfga;
+        u32 pcicfgd;
+        volatile struct pci_map pcilba[PCI_LBA_COUNT];
+        u32 pcidac;
+        u32 pcidas;
+        u32 pcidasm;
+        u32 pcidad;
+        u32 pcidma8c;
+        u32 pcidma9c;
+        u32 pcitc;
+};
+
+#define PCI_MSU_COUNT           2
+
+struct pci_msu {
+        u32 pciim[PCI_MSU_COUNT];
+        u32 pciom[PCI_MSU_COUNT];
+        u32 pciid;
+        u32 pciiic;
+        u32 pciiim;
+        u32 pciiod;
+        u32 pciioic;
+        u32 pciioim;
+};
+
+/*
+ * PCI Control Register
+ */
+
+#define PCI_CTL_EN              (1 << 0)
+#define PCI_CTL_TNR             (1 << 1)
+#define PCI_CTL_SCE             (1 << 2)
+#define PCI_CTL_IEN             (1 << 3)
+#define PCI_CTL_AAA             (1 << 4)
+#define PCI_CTL_EAP             (1 << 5)
+#define PCI_CTL_PCIM_BIT        6
+#define PCI_CTL_PCIM            0x000001c0
+
+#define PCI_CTL_PCIM_DIS        0
+#define PCI_CTL_PCIM_TNR        1 /* Satellite - target not ready */
+#define PCI_CTL_PCIM_SUS        2 /* Satellite - suspended CPU. */
+#define PCI_CTL_PCIM_EXT        3 /* Host - external arbiter. */
+#define PCI_CTL PCIM_PRIO       4 /* Host - fixed priority arb. */
+#define PCI_CTL_PCIM_RR         5 /* Host - round robin priority. */
+#define PCI_CTL_PCIM_RSVD6      6
+#define PCI_CTL_PCIM_RSVD7      7
+
+#define PCI_CTL_IGM             (1 << 9)
+
+/*
+ * PCI Status Register
+ */
+
+#define PCI_STAT_EED            (1 << 0)
+#define PCI_STAT_WR             (1 << 1)
+#define PCI_STAT_NMI            (1 << 2)
+#define PCI_STAT_II             (1 << 3)
+#define PCI_STAT_CWE            (1 << 4)
+#define PCI_STAT_CRE            (1 << 5)
+#define PCI_STAT_MDPE           (1 << 6)
+#define PCI_STAT_STA            (1 << 7)
+#define PCI_STAT_RTA            (1 << 8)
+#define PCI_STAT_RMA            (1 << 9)
+#define PCI_STAT_SSE            (1 << 10)
+#define PCI_STAT_OSE            (1 << 11)
+#define PCI_STAT_PE             (1 << 12)
+#define PCI_STAT_TAE            (1 << 13)
+#define PCI_STAT_RLE            (1 << 14)
+#define PCI_STAT_BME            (1 << 15)
+#define PCI_STAT_PRD            (1 << 16)
+#define PCI_STAT_RIP            (1 << 17)
+
+/*
+ * PCI Status Mask Register
+ */
+
+#define PCI_STATM_EED           PCI_STAT_EED
+#define PCI_STATM_WR            PCI_STAT_WR
+#define PCI_STATM_NMI           PCI_STAT_NMI
+#define PCI_STATM_II            PCI_STAT_II
+#define PCI_STATM_CWE           PCI_STAT_CWE
+#define PCI_STATM_CRE           PCI_STAT_CRE
+#define PCI_STATM_MDPE          PCI_STAT_MDPE
+#define PCI_STATM_STA           PCI_STAT_STA
+#define PCI_STATM_RTA           PCI_STAT_RTA
+#define PCI_STATM_RMA           PCI_STAT_RMA
+#define PCI_STATM_SSE           PCI_STAT_SSE
+#define PCI_STATM_OSE           PCI_STAT_OSE
+#define PCI_STATM_PE            PCI_STAT_PE
+#define PCI_STATM_TAE           PCI_STAT_TAE
+#define PCI_STATM_RLE           PCI_STAT_RLE
+#define PCI_STATM_BME           PCI_STAT_BME
+#define PCI_STATM_PRD           PCI_STAT_PRD
+#define PCI_STATM_RIP           PCI_STAT_RIP
+
+/*
+ * PCI Configuration Address Register
+ */
+#define PCI_CFGA_REG_BIT        2
+#define PCI_CFGA_REG            0x000000fc
+#define  PCI_CFGA_REG_ID        (0x00 >> 2)     /* use PCFGID */
+#define  PCI_CFGA_REG_04        (0x04 >> 2)     /* use PCFG04_ */
+#define  PCI_CFGA_REG_08        (0x08 >> 2)     /* use PCFG08_ */
+#define  PCI_CFGA_REG_0C        (0x0C >> 2)     /* use PCFG0C_ */
+#define  PCI_CFGA_REG_PBA0      (0x10 >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_PBA1      (0x14 >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_PBA2      (0x18 >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_PBA3      (0x1c >> 2)     /* use PCIPBA_ */
+#define  PCI_CFGA_REG_SUBSYS    (0x2c >> 2)     /* use PCFGSS_ */
+#define  PCI_CFGA_REG_3C        (0x3C >> 2)     /* use PCFG3C_ */
+#define  PCI_CFGA_REG_PBBA0C    (0x44 >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA0M     (0x48 >> 2)
+#define  PCI_CFGA_REG_PBA1C     (0x4c >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA1M     (0x50 >> 2)
+#define  PCI_CFGA_REG_PBA2C     (0x54 >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA2M     (0x58 >> 2)
+#define  PCI_CFGA_REG_PBA3C     (0x5c >> 2)     /* use PCIPBAC_ */
+#define  PCI_CFGA_REG_PBA3M     (0x60 >> 2)
+#define  PCI_CFGA_REG_PMGT      (0x64 >> 2)
+#define PCI_CFGA_FUNC_BIT       8
+#define PCI_CFGA_FUNC           0x00000700
+#define PCI_CFGA_DEV_BIT        11
+#define PCI_CFGA_DEV            0x0000f800
+#define PCI_CFGA_DEV_INTERN     0
+#define PCI_CFGA_BUS_BIT        16
+#define PCI CFGA_BUS            0x00ff0000
+#define PCI_CFGA_BUS_TYPE0      0
+#define PCI_CFGA_EN             (1 << 31)
+
+/* PCI CFG04 commands */
+#define PCI_CFG04_CMD_IO_ENA    (1 << 0)
+#define PCI_CFG04_CMD_MEM_ENA   (1 << 1)
+#define PCI_CFG04_CMD_BM_ENA    (1 << 2)
+#define PCI_CFG04_CMD_MW_INV    (1 << 4)
+#define PCI_CFG04_CMD_PAR_ENA   (1 << 6)
+#define PCI_CFG04_CMD_SER_ENA   (1 << 8)
+#define PCI_CFG04_CMD_FAST_ENA  (1 << 9)
+
+/* PCI CFG04 status fields */
+#define PCI_CFG04_STAT_BIT      16
+#define PCI_CFG04_STAT          0xffff0000
+#define PCI_CFG04_STAT_66_MHZ   (1 << 21)
+#define PCI_CFG04_STAT_FBB      (1 << 23)
+#define PCI_CFG04_STAT_MDPE     (1 << 24)
+#define PCI_CFG04_STAT_DST      (1 << 25)
+#define PCI_CFG04_STAT_STA      (1 << 27)
+#define PCI_CFG04_STAT_RTA      (1 << 28)
+#define PCI_CFG04_STAT_RMA      (1 << 29)
+#define PCI_CFG04_STAT_SSE      (1 << 30)
+#define PCI_CFG04_STAT_PE       (1 << 31)
+
+#define PCI_PBA_MSI             (1 << 0)
+#define PCI_PBA_P               (1 << 2)
+
+/* PCI PBAC registers */
+#define PCI_PBAC_MSI            (1 << 0)
+#define PCI_PBAC_P              (1 << 1)
+#define PCI_PBAC_SIZE_BIT       2
+#define PCI_PBAC_SIZE           0x0000007c
+#define PCI_PBAC_SB             (1 << 7)
+#define PCI_PBAC_PP             (1 << 8)
+#define PCI_PBAC_MR_BIT         9
+#define PCI_PBAC_MR             0x00000600
+#define  PCI_PBAC_MR_RD         0
+#define  PCI_PBAC_MR_RD_LINE    1
+#define  PCI_PBAC_MR_RD_MULT    2
+#define PCI_PBAC_MRL            (1 << 11)
+#define PCI_PBAC_MRM            (1 << 12)
+#define PCI_PBAC_TRP            (1 << 13)
+
+#define PCI_CFG40_TRDY_TIM      0x000000ff
+#define PCI_CFG40_RET_LIM       0x0000ff00
+
+/*
+ * PCI Local Base Address [0|1|2|3] Register
+ */
+
+#define PCI_LBA_BADDR_BIT       0
+#define PCI_LBA_BADDR           0xffffff00
+
+/*
+ * PCI Local Base Address Control Register
+ */
+
+#define PCI_LBAC_MSI            (1 << 0)
+#define  PCI_LBAC_MSI_MEM       0
+#define  PCI_LBAC_MSI_IO        1
+#define PCI_LBAC_SIZE_BIT       2
+#define PCI_LBAC_SIZE           0x0000007c
+#define PCI_LBAC_SB             (1 << 7)
+#define PCI_LBAC_RT             (1 << 8)
+#define  PCI_LBAC_RT_NO_PREF    0
+#define  PCI_LBAC_RT_PREF       1
+
+/*
+ * PCI Local Base Address [0|1|2|3] Mapping Register
+ */
+#define PCI_LBAM_MADDR_BIT      8
+#define PCI_LBAM_MADDR          0xffffff00
+
+/*
+ * PCI Decoupled Access Control Register
+ */
+#define PCI_DAC_DEN             (1 << 0)
+
+/*
+ * PCI Decoupled Access Status Register
+ */
+#define PCI_DAS_D               (1 << 0)
+#define PCI_DAS_B               (1 << 1)
+#define PCI_DAS_E               (1 << 2)
+#define PCI_DAS_OFE             (1 << 3)
+#define PCI_DAS_OFF             (1 << 4)
+#define PCI_DAS_IFE             (1 << 5)
+#define PCI_DAS_IFF             (1 << 6)
+
+/*
+ * PCI DMA Channel 8 Configuration Register
+ */
+#define PCI_DMA8C_MBS_BIT       0
+#define PCI_DMA8C_MBS           0x00000fff /* Maximum Burst Size. */
+#define PCI_DMA8C_OUR           (1 << 12)
+
+/*
+ * PCI DMA Channel 9 Configuration Register
+ */
+#define PCI_DMA9C_MBS_BIT       0       /* Maximum Burst Size. */
+#define PCI_DMA9C_MBS           0x00000fff
+
+/*
+ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
+ */
+
+#define PCI_DMAD_PT_BIT         22              /* in DEVCMD field (descriptor) */
+#define PCI_DMAD_PT             0x00c00000      /* preferred transaction field */
+/* These are for reads (DMA channel 8) */
+#define PCI_DMAD_DEVCMD_MR      0               /* memory read */
+#define PCI_DMAD_DEVCMD_MRL     1               /* memory read line */
+#define PCI_DMAD_DEVCMD_MRM     2               /* memory read multiple */
+#define PCI_DMAD_DEVCMD_IOR     3               /* I/O read */
+/* These are for writes (DMA channel 9) */
+#define PCI_DMAD_DEVCMD_MW      0               /* memory write */
+#define PCI_DMAD_DEVCMD_MWI     1               /* memory write invalidate */
+#define PCI_DMAD_DEVCMD_IOW     3               /* I/O write */
+
+/* Swap byte field applies to both DMA channel 8 and 9 */
+#define PCI_DMAD_SB             (1 << 24)       /* swap byte field */
+
+
+/*
+ * PCI Target Control Register
+ */
+
+#define PCI_TC_RTIMER_BIT       0
+#define PCI_TC_RTIMER           0x000000ff
+#define PCI_TC_DTIMER_BIT       8
+#define PCI_TC_DTIMER           0x0000ff00
+#define PCI_TC_RDR              (1 << 18)
+#define PCI_TC_DDT              (1 << 19)
+
+/*
+ * PCI messaging unit [applies to both inbound and outbound registers ]
+ */
+#define PCI_MSU_M0              (1 << 0)
+#define PCI_MSU_M1              (1 << 1)
+#define PCI_MSU_DB              (1 << 2)
+
+#define PCI_MSG_ADDR            0xB8088010
+#define PCI0_ADDR               0xB8080000
+#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
+#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
+
+#define PCIM_SHFT               0x6
+#define PCIM_BIT_LEN            0x7
+#define PCIM_H_EA               0x3
+#define PCIM_H_IA_FIX           0x4
+#define PCIM_H_IA_RR            0x5
+#if 0
+#define PCI_ADDR_START          0x13000000
+#endif
+
+#define PCI_ADDR_START          0x50000000
+
+#define CPUTOPCI_MEM_WIN        0x02000000
+#define CPUTOPCI_IO_WIN         0x00100000
+#define PCILBA_SIZE_SHFT        2
+#define PCILBA_SIZE_MASK        0x1F
+#define SIZE_256MB              0x1C
+#define SIZE_128MB              0x1B
+#define SIZE_64MB               0x1A
+#define SIZE_32MB               0x19
+#define SIZE_16MB               0x18
+#define SIZE_4MB                0x16
+#define SIZE_2MB                0x15
+#define SIZE_1MB                0x14
+#define KORINA_CONFIG0_ADDR     0x80000000
+#define KORINA_CONFIG1_ADDR     0x80000004
+#define KORINA_CONFIG2_ADDR     0x80000008
+#define KORINA_CONFIG3_ADDR     0x8000000C
+#define KORINA_CONFIG4_ADDR     0x80000010
+#define KORINA_CONFIG5_ADDR     0x80000014
+#define KORINA_CONFIG6_ADDR     0x80000018
+#define KORINA_CONFIG7_ADDR     0x8000001C
+#define KORINA_CONFIG8_ADDR     0x80000020
+#define KORINA_CONFIG9_ADDR     0x80000024
+#define KORINA_CONFIG10_ADDR    0x80000028
+#define KORINA_CONFIG11_ADDR    0x8000002C
+#define KORINA_CONFIG12_ADDR    0x80000030
+#define KORINA_CONFIG13_ADDR    0x80000034
+#define KORINA_CONFIG14_ADDR    0x80000038
+#define KORINA_CONFIG15_ADDR    0x8000003C
+#define KORINA_CONFIG16_ADDR    0x80000040
+#define KORINA_CONFIG17_ADDR    0x80000044
+#define KORINA_CONFIG18_ADDR    0x80000048
+#define KORINA_CONFIG19_ADDR    0x8000004C
+#define KORINA_CONFIG20_ADDR    0x80000050
+#define KORINA_CONFIG21_ADDR    0x80000054
+#define KORINA_CONFIG22_ADDR    0x80000058
+#define KORINA_CONFIG23_ADDR    0x8000005C
+#define KORINA_CONFIG24_ADDR    0x80000060
+#define KORINA_CONFIG25_ADDR    0x80000064
+#define KORINA_CMD              (PCI_CFG04_CMD_IO_ENA | \
+                                 PCI_CFG04_CMD_MEM_ENA | \
+                                 PCI_CFG04_CMD_BM_ENA | \
+                                 PCI_CFG04_CMD_MW_INV | \
+                                 PCI_CFG04_CMD_PAR_ENA | \
+                                 PCI_CFG04_CMD_SER_ENA)
+
+#define KORINA_STAT             (PCI_CFG04_STAT_MDPE | \
+                                 PCI_CFG04_STAT_STA | \
+                                 PCI_CFG04_STAT_RTA | \
+                                 PCI_CFG04_STAT_RMA | \
+                                 PCI_CFG04_STAT_SSE | \
+                                 PCI_CFG04_STAT_PE)
+
+#define KORINA_CNFG1            ((KORINA_STAT<<16)|KORINA_CMD)
+
+#define KORINA_REVID            0
+#define KORINA_CLASS_CODE       0
+#define KORINA_CNFG2            ((KORINA_CLASS_CODE<<8) | \
+                                  KORINA_REVID)
+
+#define KORINA_CACHE_LINE_SIZE  4
+#define KORINA_MASTER_LAT       0x3c
+#define KORINA_HEADER_TYPE      0
+#define KORINA_BIST             0
+
+#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
+                      (KORINA_HEADER_TYPE<<16) | \
+                      (KORINA_MASTER_LAT<<8) | \
+                      KORINA_CACHE_LINE_SIZE)
+
+#define KORINA_BAR0     0x00000008      /* 128 MB Memory */
+#define KORINA_BAR1     0x18800001      /* 1 MB IO */
+#define KORINA_BAR2     0x18000001      /* 2 MB IO window for Korina
+                                           internal Registers */
+#define KORINA_BAR3     0x48000008      /* Spare 128 MB Memory */
+
+#define KORINA_CNFG4    KORINA_BAR0
+#define KORINA_CNFG5    KORINA_BAR1
+#define KORINA_CNFG6    KORINA_BAR2
+#define KORINA_CNFG7    KORINA_BAR3
+
+#define KORINA_SUBSYS_VENDOR_ID 0x011d
+#define KORINA_SUBSYSTEM_ID     0x0214
+#define KORINA_CNFG8            0
+#define KORINA_CNFG9            0
+#define KORINA_CNFG10           0
+#define KORINA_CNFG11   ((KORINA_SUBSYS_VENDOR_ID<<16) | \
+                          KORINA_SUBSYSTEM_ID)
+#define KORINA_INT_LINE         1
+#define KORINA_INT_PIN          1
+#define KORINA_MIN_GNT          8
+#define KORINA_MAX_LAT          0x38
+#define KORINA_CNFG12           0
+#define KORINA_CNFG13           0
+#define KORINA_CNFG14           0
+#define KORINA_CNFG15   ((KORINA_MAX_LAT<<24) | \
+                         (KORINA_MIN_GNT<<16) | \
+                         (KORINA_INT_PIN<<8)  | \
+                          KORINA_INT_LINE)
+#define KORINA_RETRY_LIMIT      0x80
+#define KORINA_TRDY_LIMIT       0x80
+#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
+                        KORINA_TRDY_LIMIT)
+#define PCI_PBAxC_R             0x0
+#define PCI_PBAxC_RL            0x1
+#define PCI_PBAxC_RM            0x2
+#define SIZE_SHFT               2
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA0C    (PCI_PBAC_MRL | PCI_PBAC_SB | \
+                          ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
+                          PCI_PBAC_PP | \
+                          (SIZE_128MB<<SIZE_SHFT) | \
+                           PCI_PBAC_P)
+#else
+#define KORINA_PBA0C    (PCI_PBAC_MRL | \
+                          ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
+                          PCI_PBAC_PP | \
+                          (SIZE_128MB<<SIZE_SHFT) | \
+                           PCI_PBAC_P)
+#endif
+#define KORINA_CNFG17   KORINA_PBA0C
+#define KORINA_PBA0M    0x0
+#define KORINA_CNFG18   KORINA_PBA0M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA1C    ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
+                          PCI_PBAC_MSI)
+#else
+#define KORINA_PBA1C    ((SIZE_1MB<<SIZE_SHFT) | \
+                          PCI_PBAC_MSI)
+#endif
+#define KORINA_CNFG19   KORINA_PBA1C
+#define KORINA_PBA1M    0x0
+#define KORINA_CNFG20   KORINA_PBA1M
+
+#if defined(__MIPSEB__)
+#define KORINA_PBA2C    ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
+                          PCI_PBAC_MSI)
+#else
+#define KORINA_PBA2C    ((SIZE_2MB<<SIZE_SHFT) | \
+                          PCI_PBAC_MSI)
+#endif
+#define KORINA_CNFG21   KORINA_PBA2C
+#define KORINA_PBA2M    0x18000000
+#define KORINA_CNFG22   KORINA_PBA2M
+#define KORINA_PBA3C    0
+#define KORINA_CNFG23   KORINA_PBA3C
+#define KORINA_PBA3M    0
+#define KORINA_CNFG24   KORINA_PBA3M
+
+#define PCITC_DTIMER_VAL        8
+#define PCITC_RTIMER_VAL        0x10
+
+#endif  /* __ASM_RC32434_PCI_H */
diff --git a/arch/mips/include/asm/mach-rc32434/prom.h b/arch/mips/include/asm/mach-rc32434/prom.h
new file mode 100644
index 000000000000..660707f1bcce
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/prom.h
@@ -0,0 +1,40 @@
+/*
+ *  Definitions for the PROM
+ *
+ *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#define PROM_ENTRY(x)           (0xbfc00000 + ((x) * 8))
+
+#define SR_NMI                  0x00180000
+#define SERIAL_SPEED_ENTRY      0x00000001
+
+#define FREQ_TAG                "HZ="
+#define KMAC_TAG                "kmac="
+#define MEM_TAG                 "mem="
+#define BOARD_TAG               "board="
+
+#define BOARD_RB532             "500"
+#define BOARD_RB532A            "500r5"
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
new file mode 100644
index 000000000000..79e8ef67d0d3
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -0,0 +1,84 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *  GNU General Public License for more details.
+ *
+ *  Copyright (C) 2004 IDT Inc.
+ *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ */
+#ifndef __ASM_RC32434_RB_H
+#define __ASM_RC32434_RB_H
+
+#include <linux/genhd.h>
+
+#define REGBASE         0x18000000
+#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
+#define UART0BASE       0x58000
+#define RST             (1 << 15)
+#define DEV0BASE        0x010000
+#define DEV0MASK        0x010004
+#define DEV0C           0x010008
+#define DEV0T           0x01000C
+#define DEV1BASE        0x010010
+#define DEV1MASK        0x010014
+#define DEV1C           0x010018
+#define DEV1TC          0x01001C
+#define DEV2BASE        0x010020
+#define DEV2MASK        0x010024
+#define DEV2C           0x010028
+#define DEV2TC          0x01002C
+#define DEV3BASE        0x010030
+#define DEV3MASK        0x010034
+#define DEV3C           0x010038
+#define DEV3TC          0x01003C
+#define BTCS            0x010040
+#define BTCOMPARE       0x010044
+#define GPIOBASE        0x050000
+#define GPIOCFG         0x050004
+#define GPIOD           0x050008
+#define GPIOILEVEL      0x05000C
+#define GPIOISTAT       0x050010
+#define GPIONMIEN       0x050014
+#define IMASK6          0x038038
+#define LO_WPX          (1 << 0)
+#define LO_ALE          (1 << 1)
+#define LO_CLE          (1 << 2)
+#define LO_CEX          (1 << 3)
+#define LO_FOFF         (1 << 5)
+#define LO_SPICS        (1 << 6)
+#define LO_ULED         (1 << 7)
+
+#define BIT_TO_MASK(x)  (1 << x)
+
+struct dev_reg {
+        u32     base;
+        u32     mask;
+        u32     ctl;
+        u32     timing;
+};
+
+struct korina_device {
+        char *name;
+        unsigned char mac[6];
+        struct net_device *dev;
+};
+
+struct cf_device {
+        int gpio_pin;
+        void *dev;
+        struct gendisk *gd;
+};
+
+struct mpmc_device {
+        unsigned char   state;
+        spinlock_t      lock;
+        void __iomem    *base;
+};
+
+#endif  /* __ASM_RC32434_RB_H */
diff --git a/arch/mips/include/asm/mach-rc32434/rc32434.h b/arch/mips/include/asm/mach-rc32434/rc32434.h
new file mode 100644
index 000000000000..fce25d4231fc
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/rc32434.h
@@ -0,0 +1,19 @@
+/*
+ * Definitions for IDT RC323434 CPU.
+ */
+
+#ifndef _ASM_RC32434_RC32434_H_
+#define _ASM_RC32434_RC32434_H_
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#define IDT_CLOCK_MULT          2
+
+/* cpu pipeline flush */
+static inline void rc32434_sync(void)
+{
+        __asm__ volatile ("sync");
+}
+
+#endif  /* _ASM_RC32434_RC32434_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/timer.h b/arch/mips/include/asm/mach-rc32434/timer.h
new file mode 100644
index 000000000000..e49b1d57a017
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/timer.h
@@ -0,0 +1,65 @@
+/*
+ *  Definitions for timer registers
+ *
+ *  Copyright 2004 Philip Rischel <rischelp@idt.com>
+ *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_RC32434_TIMER_H
+#define __ASM_RC32434_TIMER_H
+
+#include <asm/mach-rc32434/rb.h>
+
+#define TIMER0_BASE_ADDR                0x18028000
+#define TIMER_COUNT                     3
+
+struct timer_counter {
+        u32 count;
+        u32 compare;
+        u32 ctc;                /*use CTC_ */
+};
+
+struct timer {
+        struct timer_counter tim[TIMER_COUNT];
+        u32 rcount;     /* use RCOUNT_ */
+        u32 rcompare;   /* use RCOMPARE_ */
+        u32 rtc;        /* use RTC_ */
+};
+
+#define RC32434_CTC_EN_BIT              0
+#define RC32434_CTC_TO_BIT              1
+
+/* Real time clock registers */
+#define RC32434_RTC_MSK(x)              BIT_TO_MASK(x)
+#define RC32434_RTC_CE_BIT              0
+#define RC32434_RTC_TO_BIT              1
+#define RC32434_RTC_RQE_BIT             2
+
+/* Counter registers */
+#define RC32434_RCOUNT_BIT              0
+#define RC32434_RCOUNT_MSK              0x0000ffff
+#define RC32434_RCOMP_BIT               0
+#define RC32434_RCOMP_MSK               0x0000ffff
+
+#endif  /* __ASM_RC32434_TIMER_H */
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
new file mode 100644
index 000000000000..3ddf187e98a6
--- /dev/null
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
+#define __ASM_MIPS_MACH_MIPS_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        1
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
new file mode 100644
index 000000000000..ccf543363537
--- /dev/null
+++ b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
@@ -0,0 +1,43 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors.
+ */
+#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
+
+#include <cpu-feature-overrides.h>
+
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+#define cpu_has_fpu             1
+#define cpu_has_32fpr           1
+#define cpu_has_counter         1
+#define cpu_has_watch           0
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_cache_cdex_p    1
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-rm/mc146818rtc.h b/arch/mips/include/asm/mach-rm/mc146818rtc.h
new file mode 100644
index 000000000000..145bce096fe9
--- /dev/null
+++ b/arch/mips/include/asm/mach-rm/mc146818rtc.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip with ARC epoch.
+ */
+#ifndef __ASM_MACH_RM_MC146818RTC_H
+#define __ASM_MACH_RM_MC146818RTC_H
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
+#else
+#define mc146818_decode_year(year) ((year) + 1980)
+#endif
+
+#include_next <mc146818rtc.h>
+
+#endif /* __ASM_MACH_RM_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
new file mode 100644
index 000000000000..948d3129a114
--- /dev/null
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -0,0 +1,29 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_RM_WAR_H
+#define __ASM_MIPS_MACH_RM_WAR_H
+
+/*
+ * The RM200C seems to have been shipped only with V2.0 R4600s
+ */
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        1
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_RM_WAR_H */
diff --git a/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
new file mode 100644
index 000000000000..1c1f92415b9a
--- /dev/null
+++ b/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Sibyte are MIPS64 processors wired to a specific configuration
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          1
+#define cpu_has_ejtag           1
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        1
+#define cpu_has_mips64r2        0
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+#endif /* __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
new file mode 100644
index 000000000000..7950ef4f032c
--- /dev/null
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -0,0 +1,37 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
+#define __ASM_MIPS_MACH_SIBYTE_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+
+#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
+    defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
+
+#define BCM1250_M3_WAR  1
+#define SIBYTE_1956_WAR 1
+
+#else
+
+#define BCM1250_M3_WAR  0
+#define SIBYTE_1956_WAR 0
+
+#endif
+
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
diff --git a/arch/mips/include/asm/mach-tx39xx/ioremap.h b/arch/mips/include/asm/mach-tx39xx/ioremap.h
new file mode 100644
index 000000000000..93c6c04ffda3
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx39xx/ioremap.h
@@ -0,0 +1,38 @@
+/*
+ *      include/asm-mips/mach-tx39xx/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_TX39XX_IOREMAP_H
+#define __ASM_MACH_TX39XX_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+#define TXX9_DIRECTMAP_BASE     0xff000000ul
+        if (offset >= TXX9_DIRECTMAP_BASE &&
+            offset < TXX9_DIRECTMAP_BASE + 0xff0000)
+                return (void __iomem *)offset;
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
+}
+
+#endif /* __ASM_MACH_TX39XX_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-tx39xx/mangle-port.h b/arch/mips/include/asm/mach-tx39xx/mangle-port.h
new file mode 100644
index 000000000000..ef0b502fd8b7
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx39xx/mangle-port.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H
+#define __ASM_MACH_TX39XX_MANGLE_PORT_H
+
+#if defined(CONFIG_TOSHIBA_JMR3927)
+extern unsigned long (*__swizzle_addr_b)(unsigned long port);
+#define NEEDS_TXX9_SWIZZLE_ADDR_B
+#else
+#define __swizzle_addr_b(port)  (port)
+#endif
+#define __swizzle_addr_w(port)  (port)
+#define __swizzle_addr_l(port)  (port)
+#define __swizzle_addr_q(port)  (port)
+
+#define ioswabb(a, x)           (x)
+#define __mem_ioswabb(a, x)     (x)
+#define ioswabw(a, x)           le16_to_cpu(x)
+#define __mem_ioswabw(a, x)     (x)
+#define ioswabl(a, x)           le32_to_cpu(x)
+#define __mem_ioswabl(a, x)     (x)
+#define ioswabq(a, x)           le64_to_cpu(x)
+#define __mem_ioswabq(a, x)     (x)
+
+#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-tx39xx/war.h b/arch/mips/include/asm/mach-tx39xx/war.h
new file mode 100644
index 000000000000..433814616359
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx39xx/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H
+#define __ASM_MIPS_MACH_TX39XX_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
new file mode 100644
index 000000000000..275eaf92c748
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_llsc    1
+#define cpu_has_64bits  1
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_has_mips16          0
+#define cpu_has_mdmx            0
+#define cpu_has_mips3d          0
+#define cpu_has_smartmips       0
+#define cpu_has_vtag_icache     0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp     0
+#define cpu_has_mipsmt  0
+#define cpu_has_userlocal       0
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/ioremap.h b/arch/mips/include/asm/mach-tx49xx/ioremap.h
new file mode 100644
index 000000000000..1e7beae72229
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/ioremap.h
@@ -0,0 +1,43 @@
+/*
+ *      include/asm-mips/mach-tx49xx/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_TX49XX_IOREMAP_H
+#define __ASM_MACH_TX49XX_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+#ifdef CONFIG_64BIT
+#define TXX9_DIRECTMAP_BASE     0xfff000000ul
+#else
+#define TXX9_DIRECTMAP_BASE     0xff000000ul
+#endif
+        if (offset >= TXX9_DIRECTMAP_BASE &&
+            offset < TXX9_DIRECTMAP_BASE + 0x400000)
+                return (void __iomem *)(unsigned long)(int)offset;
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return (unsigned long)addr >=
+                (unsigned long)(int)(TXX9_DIRECTMAP_BASE & 0xffffffff);
+}
+
+#endif /* __ASM_MACH_TX49XX_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
new file mode 100644
index 000000000000..913ff196259d
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_MACH_TX49XX_KMALLOC_H
+#define __ASM_MACH_TX49XX_KMALLOC_H
+
+/*
+ * All happy, no need to define ARCH_KMALLOC_MINALIGN
+ */
+
+#endif /* __ASM_MACH_TX49XX_KMALLOC_H */
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
new file mode 100644
index 000000000000..39b5d1177c57
--- /dev/null
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
+#define __ASM_MIPS_MACH_TX49XX_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     1
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-vr41xx/irq.h b/arch/mips/include/asm/mach-vr41xx/irq.h
new file mode 100644
index 000000000000..862058d3f81b
--- /dev/null
+++ b/arch/mips/include/asm/mach-vr41xx/irq.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_MACH_VR41XX_IRQ_H
+#define __ASM_MACH_VR41XX_IRQ_H
+
+#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
+
+#include_next <irq.h>
+
+#endif /* __ASM_MACH_VR41XX_IRQ_H */
diff --git a/arch/mips/include/asm/mach-vr41xx/war.h b/arch/mips/include/asm/mach-vr41xx/war.h
new file mode 100644
index 000000000000..56a38926412a
--- /dev/null
+++ b/arch/mips/include/asm/mach-vr41xx/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H
+#define __ASM_MIPS_MACH_VR41XX_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
new file mode 100644
index 000000000000..83746b84a5ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
@@ -0,0 +1,83 @@
+/*
+ * This is a direct copy of the ev96100.h file, with a global
+ * search and replace.  The numbers are the same.
+ *
+ * The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef __ASM_MIPS_GT64120_H
+#define __ASM_MIPS_GT64120_H
+
+/*
+ * This is the CPU physical memory map of PPMC Board:
+ *
+ *    0x00000000-0x03FFFFFF      - 64MB SDRAM (SCS[0]#)
+ *    0x1C000000-0x1C000000      - LED (CS0)
+ *    0x1C800000-0x1C800007      - UART 16550 port (CS1)
+ *    0x1F000000-0x1F000000      - MailBox (CS3)
+ *    0x1FC00000-0x20000000      - 4MB Flash (BOOT CS)
+ */
+
+#define WRPPMC_SDRAM_SCS0_BASE  0x00000000
+#define WRPPMC_SDRAM_SCS0_SIZE  0x04000000
+
+#define WRPPMC_UART16550_BASE   0x1C800000
+#define WRPPMC_UART16550_CLOCK  3686400 /* 3.68MHZ */
+
+#define WRPPMC_LED_BASE         0x1C000000
+#define WRPPMC_MBOX_BASE        0x1F000000
+
+#define WRPPMC_BOOTROM_BASE     0x1FC00000
+#define WRPPMC_BOOTROM_SIZE     0x00400000 /* 4M Flash */
+
+#define WRPPMC_MIPS_TIMER_IRQ   7 /* MIPS compare/count timer interrupt */
+#define WRPPMC_UART16550_IRQ    6
+#define WRPPMC_PCI_INTA_IRQ     3
+
+/*
+ * PCI Bus I/O and Memory resources allocation
+ *
+ * NOTE: We only have PCI_0 hose interface
+ */
+#define GT_PCI_MEM_BASE 0x13000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL
+#define GT_PCI_IO_BASE  0x11000000UL
+#define GT_PCI_IO_SIZE  0x02000000UL
+
+/*
+ * PCI interrupts will come in on either the INTA or INTD interrupt lines,
+ * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
+ * boards, they all either come in on IntD or they all come in on IntA, they
+ * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
+ * "requested" interrupt numbers and go through the list whenever we get an
+ * IntA/D.
+ *
+ * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
+ * INTD is 11.
+ */
+#define GT_TIMER        4
+#define GT_INTA         2
+#define GT_INTD         5
+
+#ifndef __ASSEMBLY__
+
+/*
+ * GT64120 internal register space base address
+ */
+extern unsigned long gt64120_base;
+
+#define GT64120_BASE    (gt64120_base)
+
+/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
+#undef WRPPMC_EARLY_DEBUG
+
+#ifdef WRPPMC_EARLY_DEBUG
+extern void wrppmc_led_on(int mask);
+extern void wrppmc_led_off(int mask);
+extern void wrppmc_early_printk(const char *fmt, ...);
+#else
+#define wrppmc_early_printk(fmt, ...) do {} while (0)
+#endif /* WRPPMC_EARLY_DEBUG */
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_MIPS_GT64120_H */
diff --git a/arch/mips/include/asm/mach-wrppmc/war.h b/arch/mips/include/asm/mach-wrppmc/war.h
new file mode 100644
index 000000000000..ac48629bb1ce
--- /dev/null
+++ b/arch/mips/include/asm/mach-wrppmc/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
+#define __ASM_MIPS_MACH_WRPPMC_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */
diff --git a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
new file mode 100644
index 000000000000..470e5e9e10d6
--- /dev/null
+++ b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Momentum Jaguar ATX always has the RM9000 processor.
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-yosemite/war.h b/arch/mips/include/asm/mach-yosemite/war.h
new file mode 100644
index 000000000000..e5c6d53efc86
--- /dev/null
+++ b/arch/mips/include/asm/mach-yosemite/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
+#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             1
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
diff --git a/arch/mips/include/asm/mc146818-time.h b/arch/mips/include/asm/mc146818-time.h
new file mode 100644
index 000000000000..cdc379a0a94e
--- /dev/null
+++ b/arch/mips/include/asm/mc146818-time.h
@@ -0,0 +1,119 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_MC146818_TIME_H
+#define __ASM_MC146818_TIME_H
+
+#include <linux/bcd.h>
+#include <linux/mc146818rtc.h>
+#include <linux/time.h>
+
+/*
+ * For check timing call set_rtc_mmss() 500ms; used in timer interrupt.
+ */
+#define USEC_AFTER      500000
+#define USEC_BEFORE     500000
+
+/*
+ * In order to set the CMOS clock precisely, set_rtc_mmss has to be
+ * called 500 ms after the second nowtime has started, because when
+ * nowtime is written into the registers of the CMOS clock, it will
+ * jump to the next second precisely 500 ms later. Check the Motorola
+ * MC146818A or Dallas DS12887 data sheet for details.
+ *
+ * BUG: This routine does not handle hour overflow properly; it just
+ *      sets the minutes. Usually you'll only notice that after reboot!
+ */
+static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
+{
+        int real_seconds, real_minutes, cmos_minutes;
+        unsigned char save_control, save_freq_select;
+        int retval = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+        save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
+        CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
+
+        save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
+        CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
+
+        cmos_minutes = CMOS_READ(RTC_MINUTES);
+        if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
+                BCD_TO_BIN(cmos_minutes);
+
+        /*
+         * since we're only adjusting minutes and seconds,
+         * don't interfere with hour overflow. This avoids
+         * messing with unknown time zones but requires your
+         * RTC not to be off by more than 15 minutes
+         */
+        real_seconds = nowtime % 60;
+        real_minutes = nowtime / 60;
+        if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
+                real_minutes += 30;             /* correct for half hour time zone */
+        real_minutes %= 60;
+
+        if (abs(real_minutes - cmos_minutes) < 30) {
+                if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+                        BIN_TO_BCD(real_seconds);
+                        BIN_TO_BCD(real_minutes);
+                }
+                CMOS_WRITE(real_seconds, RTC_SECONDS);
+                CMOS_WRITE(real_minutes, RTC_MINUTES);
+        } else {
+                printk(KERN_WARNING
+                       "set_rtc_mmss: can't update from %d to %d\n",
+                       cmos_minutes, real_minutes);
+                retval = -1;
+        }
+
+        /* The following flags have to be released exactly in this order,
+         * otherwise the DS12887 (popular MC146818A clone with integrated
+         * battery and quartz) will not reset the oscillator and will not
+         * update precisely 500 ms later. You won't find this mentioned in
+         * the Dallas Semiconductor data sheets, but who believes data
+         * sheets anyway ...                           -- Markus Kuhn
+         */
+        CMOS_WRITE(save_control, RTC_CONTROL);
+        CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
+        spin_unlock_irqrestore(&rtc_lock, flags);
+
+        return retval;
+}
+
+static inline unsigned long mc146818_get_cmos_time(void)
+{
+        unsigned int year, mon, day, hour, min, sec;
+        unsigned long flags;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+
+        do {
+                sec = CMOS_READ(RTC_SECONDS);
+                min = CMOS_READ(RTC_MINUTES);
+                hour = CMOS_READ(RTC_HOURS);
+                day = CMOS_READ(RTC_DAY_OF_MONTH);
+                mon = CMOS_READ(RTC_MONTH);
+                year = CMOS_READ(RTC_YEAR);
+        } while (sec != CMOS_READ(RTC_SECONDS));
+
+        if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+                BCD_TO_BIN(sec);
+                BCD_TO_BIN(min);
+                BCD_TO_BIN(hour);
+                BCD_TO_BIN(day);
+                BCD_TO_BIN(mon);
+                BCD_TO_BIN(year);
+        }
+        spin_unlock_irqrestore(&rtc_lock, flags);
+        year = mc146818_decode_year(year);
+
+        return mktime(year, mon, day, hour, min, sec);
+}
+
+#endif /* __ASM_MC146818_TIME_H */
diff --git a/arch/mips/include/asm/mc146818rtc.h b/arch/mips/include/asm/mc146818rtc.h
new file mode 100644
index 000000000000..68b4da6d520b
--- /dev/null
+++ b/arch/mips/include/asm/mc146818rtc.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Machine dependent access functions for RTC registers.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2000 Ralf Baechle
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
+
+#include <mc146818rtc.h>
+
+#endif /* _ASM_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
new file mode 100644
index 000000000000..a0f04bb99c99
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -0,0 +1,436 @@
+/*
+ * Bonito Register Map
+ *
+ * This file is the original bonito.h from Algorithmics with minor changes
+ * to fit into linux.
+ *
+ * Copyright (c) 1999 Algorithmics Ltd
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2001 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * Algorithmics gives permission for anyone to use and modify this file
+ * without any obligation or license condition except that you retain
+ * this copyright message in any source redistribution in whole or part.
+ *
+ */
+
+/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
+/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
+
+#ifndef _ASM_MIPS_BOARDS_BONITO64_H
+#define _ASM_MIPS_BOARDS_BONITO64_H
+
+#ifdef __ASSEMBLY__
+
+/* offsets from base register */
+#define BONITO(x)       (x)
+
+#elif defined(CONFIG_LEMOTE_FULONG)
+
+#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
+#define BONITO_IRQ_BASE   32
+
+#else
+
+/*
+ * Algorithmics Bonito64 system controller register base.
+ */
+extern unsigned long _pcictrl_bonito;
+extern unsigned long _pcictrl_bonito_pcicfg;
+
+#define BONITO(x)               *(volatile u32 *)(_pcictrl_bonito + (x))
+
+#endif /* __ASSEMBLY__ */
+
+
+#define BONITO_BOOT_BASE                0x1fc00000
+#define BONITO_BOOT_SIZE                0x00100000
+#define BONITO_BOOT_TOP                 (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
+#define BONITO_FLASH_BASE               0x1c000000
+#define BONITO_FLASH_SIZE               0x03000000
+#define BONITO_FLASH_TOP                (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
+#define BONITO_SOCKET_BASE              0x1f800000
+#define BONITO_SOCKET_SIZE              0x00400000
+#define BONITO_SOCKET_TOP               (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
+#define BONITO_REG_BASE                 0x1fe00000
+#define BONITO_REG_SIZE                 0x00040000
+#define BONITO_REG_TOP                  (BONITO_REG_BASE+BONITO_REG_SIZE-1)
+#define BONITO_DEV_BASE                 0x1ff00000
+#define BONITO_DEV_SIZE                 0x00100000
+#define BONITO_DEV_TOP                  (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
+#define BONITO_PCILO_BASE               0x10000000
+#define BONITO_PCILO_SIZE               0x0c000000
+#define BONITO_PCILO_TOP                (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
+#define BONITO_PCILO0_BASE              0x10000000
+#define BONITO_PCILO1_BASE              0x14000000
+#define BONITO_PCILO2_BASE              0x18000000
+#define BONITO_PCIHI_BASE               0x20000000
+#define BONITO_PCIHI_SIZE               0x20000000
+#define BONITO_PCIHI_TOP                (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
+#define BONITO_PCIIO_BASE               0x1fd00000
+#define BONITO_PCIIO_SIZE               0x00100000
+#define BONITO_PCIIO_TOP                (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
+#define BONITO_PCICFG_BASE              0x1fe80000
+#define BONITO_PCICFG_SIZE              0x00080000
+#define BONITO_PCICFG_TOP               (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
+
+
+/* Bonito Register Bases */
+
+#define BONITO_PCICONFIGBASE            0x00
+#define BONITO_REGBASE                  0x100
+
+
+/* PCI Configuration  Registers */
+
+#define BONITO_PCI_REG(x)               BONITO(BONITO_PCICONFIGBASE + (x))
+#define BONITO_PCIDID                   BONITO_PCI_REG(0x00)
+#define BONITO_PCICMD                   BONITO_PCI_REG(0x04)
+#define BONITO_PCICLASS                 BONITO_PCI_REG(0x08)
+#define BONITO_PCILTIMER                BONITO_PCI_REG(0x0c)
+#define BONITO_PCIBASE0                 BONITO_PCI_REG(0x10)
+#define BONITO_PCIBASE1                 BONITO_PCI_REG(0x14)
+#define BONITO_PCIBASE2                 BONITO_PCI_REG(0x18)
+#define BONITO_PCIEXPRBASE              BONITO_PCI_REG(0x30)
+#define BONITO_PCIINT                   BONITO_PCI_REG(0x3c)
+
+#define BONITO_PCICMD_PERR_CLR          0x80000000
+#define BONITO_PCICMD_SERR_CLR          0x40000000
+#define BONITO_PCICMD_MABORT_CLR        0x20000000
+#define BONITO_PCICMD_MTABORT_CLR       0x10000000
+#define BONITO_PCICMD_TABORT_CLR        0x08000000
+#define BONITO_PCICMD_MPERR_CLR         0x01000000
+#define BONITO_PCICMD_PERRRESPEN        0x00000040
+#define BONITO_PCICMD_ASTEPEN           0x00000080
+#define BONITO_PCICMD_SERREN            0x00000100
+#define BONITO_PCILTIMER_BUSLATENCY     0x0000ff00
+#define BONITO_PCILTIMER_BUSLATENCY_SHIFT       8
+
+
+
+
+/* 1. Bonito h/w Configuration */
+/* Power on register */
+
+#define BONITO_BONPONCFG                BONITO(BONITO_REGBASE + 0x00)
+
+#define BONITO_BONPONCFG_SYSCONTROLLERRD        0x00040000
+#define BONITO_BONPONCFG_ROMCS1SAMP     0x00020000
+#define BONITO_BONPONCFG_ROMCS0SAMP     0x00010000
+#define BONITO_BONPONCFG_CPUBIGEND      0x00004000
+/* Added by RPF 11-9-00 */
+#define BONITO_BONPONCFG_BURSTORDER     0x00001000
+/* --- */
+#define BONITO_BONPONCFG_CPUPARITY      0x00002000
+#define BONITO_BONPONCFG_CPUTYPE        0x00000007
+#define BONITO_BONPONCFG_CPUTYPE_SHIFT  0
+#define BONITO_BONPONCFG_PCIRESET_OUT   0x00000008
+#define BONITO_BONPONCFG_IS_ARBITER     0x00000010
+#define BONITO_BONPONCFG_ROMBOOT        0x000000c0
+#define BONITO_BONPONCFG_ROMBOOT_SHIFT  6
+
+#define BONITO_BONPONCFG_ROMBOOT_FLASH  (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_SDRAM  (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+#define BONITO_BONPONCFG_ROMBOOT_CPURESET       (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
+
+#define BONITO_BONPONCFG_ROMCS0WIDTH    0x00000100
+#define BONITO_BONPONCFG_ROMCS1WIDTH    0x00000200
+#define BONITO_BONPONCFG_ROMCS0FAST     0x00000400
+#define BONITO_BONPONCFG_ROMCS1FAST     0x00000800
+#define BONITO_BONPONCFG_CONFIG_DIS     0x00000020
+
+
+/* Other Bonito configuration */
+
+#define BONITO_BONGENCFG_OFFSET         0x4
+#define BONITO_BONGENCFG                BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
+
+#define BONITO_BONGENCFG_DEBUGMODE      0x00000001
+#define BONITO_BONGENCFG_SNOOPEN        0x00000002
+#define BONITO_BONGENCFG_CPUSELFRESET   0x00000004
+
+#define BONITO_BONGENCFG_FORCE_IRQA     0x00000008
+#define BONITO_BONGENCFG_IRQA_ISOUT     0x00000010
+#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
+#define BONITO_BONGENCFG_BYTESWAP       0x00000040
+
+#define BONITO_BONGENCFG_UNCACHED       0x00000080
+#define BONITO_BONGENCFG_PREFETCHEN     0x00000100
+#define BONITO_BONGENCFG_WBEHINDEN      0x00000200
+#define BONITO_BONGENCFG_CACHEALG       0x00000c00
+#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
+#define BONITO_BONGENCFG_PCIQUEUE       0x00001000
+#define BONITO_BONGENCFG_CACHESTOP      0x00002000
+#define BONITO_BONGENCFG_MSTRBYTESWAP   0x00004000
+#define BONITO_BONGENCFG_BUSERREN       0x00008000
+#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
+#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT       0x00020000
+
+/* 2. IO & IDE configuration */
+
+#define BONITO_IODEVCFG                 BONITO(BONITO_REGBASE + 0x08)
+
+/* 3. IO & IDE configuration */
+
+#define BONITO_SDCFG                    BONITO(BONITO_REGBASE + 0x0c)
+
+/* 4. PCI address map control */
+
+#define BONITO_PCIMAP                   BONITO(BONITO_REGBASE + 0x10)
+#define BONITO_PCIMEMBASECFG            BONITO(BONITO_REGBASE + 0x14)
+#define BONITO_PCIMAP_CFG               BONITO(BONITO_REGBASE + 0x18)
+
+/* 5. ICU & GPIO regs */
+
+/* GPIO Regs - r/w */
+
+#define BONITO_GPIODATA_OFFSET          0x1c
+#define BONITO_GPIODATA                 BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
+#define BONITO_GPIOIE                   BONITO(BONITO_REGBASE + 0x20)
+
+/* ICU Configuration Regs - r/w */
+
+#define BONITO_INTEDGE                  BONITO(BONITO_REGBASE + 0x24)
+#define BONITO_INTSTEER                 BONITO(BONITO_REGBASE + 0x28)
+#define BONITO_INTPOL                   BONITO(BONITO_REGBASE + 0x2c)
+
+/* ICU Enable Regs - IntEn & IntISR are r/o. */
+
+#define BONITO_INTENSET                 BONITO(BONITO_REGBASE + 0x30)
+#define BONITO_INTENCLR                 BONITO(BONITO_REGBASE + 0x34)
+#define BONITO_INTEN                    BONITO(BONITO_REGBASE + 0x38)
+#define BONITO_INTISR                   BONITO(BONITO_REGBASE + 0x3c)
+
+/* PCI mail boxes */
+
+#define BONITO_PCIMAIL0_OFFSET          0x40
+#define BONITO_PCIMAIL1_OFFSET          0x44
+#define BONITO_PCIMAIL2_OFFSET          0x48
+#define BONITO_PCIMAIL3_OFFSET          0x4c
+#define BONITO_PCIMAIL0                 BONITO(BONITO_REGBASE + 0x40)
+#define BONITO_PCIMAIL1                 BONITO(BONITO_REGBASE + 0x44)
+#define BONITO_PCIMAIL2                 BONITO(BONITO_REGBASE + 0x48)
+#define BONITO_PCIMAIL3                 BONITO(BONITO_REGBASE + 0x4c)
+
+
+/* 6. PCI cache */
+
+#define BONITO_PCICACHECTRL             BONITO(BONITO_REGBASE + 0x50)
+#define BONITO_PCICACHETAG              BONITO(BONITO_REGBASE + 0x54)
+
+#define BONITO_PCIBADADDR               BONITO(BONITO_REGBASE + 0x58)
+#define BONITO_PCIMSTAT                 BONITO(BONITO_REGBASE + 0x5c)
+
+
+/*
+#define BONITO_PCIRDPOST                BONITO(BONITO_REGBASE + 0x60)
+#define BONITO_PCIDATA                  BONITO(BONITO_REGBASE + 0x64)
+*/
+
+/* 7. IDE DMA & Copier */
+
+#define BONITO_CONFIGBASE               0x000
+#define BONITO_BONITOBASE               0x100
+#define BONITO_LDMABASE                 0x200
+#define BONITO_COPBASE                  0x300
+#define BONITO_REG_BLOCKMASK            0x300
+
+#define BONITO_LDMACTRL                 BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMASTAT                 BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMAADDR                 BONITO(BONITO_LDMABASE + 0x4)
+#define BONITO_LDMAGO                   BONITO(BONITO_LDMABASE + 0x8)
+#define BONITO_LDMADATA                 BONITO(BONITO_LDMABASE + 0xc)
+
+#define BONITO_COPCTRL                  BONITO(BONITO_COPBASE + 0x0)
+#define BONITO_COPSTAT                  BONITO(BONITO_COPBASE + 0x0)
+#define BONITO_COPPADDR                 BONITO(BONITO_COPBASE + 0x4)
+#define BONITO_COPDADDR                 BONITO(BONITO_COPBASE + 0x8)
+#define BONITO_COPGO                    BONITO(BONITO_COPBASE + 0xc)
+
+
+/* ###### Bit Definitions for individual Registers #### */
+
+/* Gen DMA. */
+
+#define BONITO_IDECOPDADDR_DMA_DADDR    0x0ffffffc
+#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT      2
+#define BONITO_IDECOPPADDR_DMA_PADDR    0xfffffffc
+#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT      2
+#define BONITO_IDECOPGO_DMA_SIZE        0x0000fffe
+#define BONITO_IDECOPGO_DMA_SIZE_SHIFT  0
+#define BONITO_IDECOPGO_DMA_WRITE       0x00010000
+#define BONITO_IDECOPGO_DMAWCOUNT       0x000f0000
+#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
+
+#define BONITO_IDECOPCTRL_DMA_STARTBIT  0x80000000
+#define BONITO_IDECOPCTRL_DMA_RSTBIT    0x40000000
+
+/* DRAM - sdCfg */
+
+#define BONITO_SDCFG_AROWBITS           0x00000003
+#define BONITO_SDCFG_AROWBITS_SHIFT     0
+#define BONITO_SDCFG_ACOLBITS           0x0000000c
+#define BONITO_SDCFG_ACOLBITS_SHIFT     2
+#define BONITO_SDCFG_ABANKBIT           0x00000010
+#define BONITO_SDCFG_ASIDES             0x00000020
+#define BONITO_SDCFG_AABSENT            0x00000040
+#define BONITO_SDCFG_AWIDTH64           0x00000080
+
+#define BONITO_SDCFG_BROWBITS           0x00000300
+#define BONITO_SDCFG_BROWBITS_SHIFT     8
+#define BONITO_SDCFG_BCOLBITS           0x00000c00
+#define BONITO_SDCFG_BCOLBITS_SHIFT     10
+#define BONITO_SDCFG_BBANKBIT           0x00001000
+#define BONITO_SDCFG_BSIDES             0x00002000
+#define BONITO_SDCFG_BABSENT            0x00004000
+#define BONITO_SDCFG_BWIDTH64           0x00008000
+
+#define BONITO_SDCFG_EXTRDDATA          0x00010000
+#define BONITO_SDCFG_EXTRASCAS          0x00020000
+#define BONITO_SDCFG_EXTPRECH           0x00040000
+#define BONITO_SDCFG_EXTRASWIDTH        0x00180000
+#define BONITO_SDCFG_EXTRASWIDTH_SHIFT  19
+/* Changed by RPF 11-9-00 */
+#define BONITO_SDCFG_DRAMMODESET        0x00200000
+/* --- */
+#define BONITO_SDCFG_DRAMEXTREGS        0x00400000
+#define BONITO_SDCFG_DRAMPARITY         0x00800000
+/* Added by RPF 11-9-00 */
+#define BONITO_SDCFG_DRAMBURSTLEN       0x03000000
+#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
+#define BONITO_SDCFG_DRAMMODESET_DONE   0x80000000
+/* --- */
+
+/* PCI Cache - pciCacheCtrl */
+
+#define BONITO_PCICACHECTRL_CACHECMD    0x00000007
+#define BONITO_PCICACHECTRL_CACHECMD_SHIFT      0
+#define BONITO_PCICACHECTRL_CACHECMDLINE        0x00000018
+#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT  3
+#define BONITO_PCICACHECTRL_CMDEXEC     0x00000020
+
+#define BONITO_PCICACHECTRL_IOBCCOH_PRES        0x00000100
+#define BONITO_PCICACHECTRL_IOBCCOH_EN  0x00000200
+#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400
+#define BONITO_PCICACHECTRL_CPUCOH_EN   0x00000800
+
+#define BONITO_IODEVCFG_BUFFBIT_CS0     0x00000001
+#define BONITO_IODEVCFG_SPEEDBIT_CS0    0x00000002
+#define BONITO_IODEVCFG_MOREABITS_CS0   0x00000004
+
+#define BONITO_IODEVCFG_BUFFBIT_CS1     0x00000008
+#define BONITO_IODEVCFG_SPEEDBIT_CS1    0x00000010
+#define BONITO_IODEVCFG_MOREABITS_CS1   0x00000020
+
+#define BONITO_IODEVCFG_BUFFBIT_CS2     0x00000040
+#define BONITO_IODEVCFG_SPEEDBIT_CS2    0x00000080
+#define BONITO_IODEVCFG_MOREABITS_CS2   0x00000100
+
+#define BONITO_IODEVCFG_BUFFBIT_CS3     0x00000200
+#define BONITO_IODEVCFG_SPEEDBIT_CS3    0x00000400
+#define BONITO_IODEVCFG_MOREABITS_CS3   0x00000800
+
+#define BONITO_IODEVCFG_BUFFBIT_IDE     0x00001000
+#define BONITO_IODEVCFG_SPEEDBIT_IDE    0x00002000
+#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
+#define BONITO_IODEVCFG_MODEBIT_IDE     0x00008000
+#define BONITO_IODEVCFG_DMAON_IDE       0x001f0000
+#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
+#define BONITO_IODEVCFG_DMAOFF_IDE      0x01e00000
+#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT        21
+#define BONITO_IODEVCFG_EPROMSPLIT      0x02000000
+/* Added by RPF 11-9-00 */
+#define BONITO_IODEVCFG_CPUCLOCKPERIOD  0xfc000000
+#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26
+/* --- */
+
+/* gpio */
+#define BONITO_GPIO_GPIOW               0x000003ff
+#define BONITO_GPIO_GPIOW_SHIFT         0
+#define BONITO_GPIO_GPIOR               0x01ff0000
+#define BONITO_GPIO_GPIOR_SHIFT         16
+#define BONITO_GPIO_GPINR               0xfe000000
+#define BONITO_GPIO_GPINR_SHIFT         25
+#define BONITO_GPIO_IOW(N)              (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
+#define BONITO_GPIO_IOR(N)              (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
+#define BONITO_GPIO_INR(N)              (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
+
+/* ICU */
+#define BONITO_ICU_MBOXES               0x0000000f
+#define BONITO_ICU_MBOXES_SHIFT         0
+#define BONITO_ICU_DMARDY               0x00000010
+#define BONITO_ICU_DMAEMPTY             0x00000020
+#define BONITO_ICU_COPYRDY              0x00000040
+#define BONITO_ICU_COPYEMPTY            0x00000080
+#define BONITO_ICU_COPYERR              0x00000100
+#define BONITO_ICU_PCIIRQ               0x00000200
+#define BONITO_ICU_MASTERERR            0x00000400
+#define BONITO_ICU_SYSTEMERR            0x00000800
+#define BONITO_ICU_DRAMPERR             0x00001000
+#define BONITO_ICU_RETRYERR             0x00002000
+#define BONITO_ICU_GPIOS                0x01ff0000
+#define BONITO_ICU_GPIOS_SHIFT          16
+#define BONITO_ICU_GPINS                0x7e000000
+#define BONITO_ICU_GPINS_SHIFT          25
+#define BONITO_ICU_MBOX(N)              (1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
+#define BONITO_ICU_GPIO(N)              (1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
+#define BONITO_ICU_GPIN(N)              (1<<(BONITO_ICU_GPINS_SHIFT+(N)))
+
+/* pcimap */
+
+#define BONITO_PCIMAP_PCIMAP_LO0        0x0000003f
+#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT  0
+#define BONITO_PCIMAP_PCIMAP_LO1        0x00000fc0
+#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT  6
+#define BONITO_PCIMAP_PCIMAP_LO2        0x0003f000
+#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT  12
+#define BONITO_PCIMAP_PCIMAP_2          0x00040000
+#define BONITO_PCIMAP_WIN(WIN, ADDR)    ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
+
+#define BONITO_PCIMAP_WINSIZE           (1<<26)
+#define BONITO_PCIMAP_WINOFFSET(ADDR)   ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
+#define BONITO_PCIMAP_WINBASE(ADDR)     ((ADDR) << 26)
+
+/* pcimembaseCfg */
+
+#define BONITO_PCIMEMBASECFG_MASK               0xf0000000
+#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK      0x0000001f
+#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT        0
+#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS     0x000003e0
+#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT       5
+#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED    0x00000400
+#define BONITO_PCIMEMBASECFG_MEMBASE0_IO        0x00000800
+
+#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK      0x0001f000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT        12
+#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS     0x003e0000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT       17
+#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED    0x00400000
+#define BONITO_PCIMEMBASECFG_MEMBASE1_IO        0x00800000
+
+#define BONITO_PCIMEMBASECFG_ASHIFT     23
+#define BONITO_PCIMEMBASECFG_AMASK              0x007fffff
+#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE)     (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
+#define BONITO_PCIMEMBASECFGBASE(WIN, BASE)     (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
+
+#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG)  (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
+
+
+#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+
+#define BONITO_PCITOPHYS(WIN, ADDR, CFG)          ( \
+                                                  (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
+                                                  (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
+                                                )
+
+/* PCICmd */
+
+#define BONITO_PCICMD_MEMEN             0x00000002
+#define BONITO_PCICMD_MSTREN            0x00000004
+
+
+#endif /* _ASM_MIPS_BOARDS_BONITO64_H */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
new file mode 100644
index 000000000000..7f0b034dd9a5
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -0,0 +1,104 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Defines of the MIPS boards specific address-MAP, registers, etc.
+ */
+#ifndef __ASM_MIPS_BOARDS_GENERIC_H
+#define __ASM_MIPS_BOARDS_GENERIC_H
+
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+#include <asm/mips-boards/bonito64.h>
+
+/*
+ * Display register base.
+ */
+#define ASCII_DISPLAY_WORD_BASE    0x1f000410
+#define ASCII_DISPLAY_POS_BASE     0x1f000418
+
+
+/*
+ * Yamon Prom print address.
+ */
+#define YAMON_PROM_PRINT_ADDR      0x1fc00504
+
+
+/*
+ * Reset register.
+ */
+#define SOFTRES_REG       0x1f000500
+#define GORESET           0x42
+
+/*
+ * Revision register.
+ */
+#define MIPS_REVISION_REG                  0x1fc00010
+#define MIPS_REVISION_CORID_QED_RM5261     0
+#define MIPS_REVISION_CORID_CORE_LV        1
+#define MIPS_REVISION_CORID_BONITO64       2
+#define MIPS_REVISION_CORID_CORE_20K       3
+#define MIPS_REVISION_CORID_CORE_FPGA      4
+#define MIPS_REVISION_CORID_CORE_MSC       5
+#define MIPS_REVISION_CORID_CORE_EMUL      6
+#define MIPS_REVISION_CORID_CORE_FPGA2     7
+#define MIPS_REVISION_CORID_CORE_FPGAR2    8
+#define MIPS_REVISION_CORID_CORE_FPGA3     9
+#define MIPS_REVISION_CORID_CORE_24K       10
+#define MIPS_REVISION_CORID_CORE_FPGA4     11
+#define MIPS_REVISION_CORID_CORE_FPGA5     12
+
+/**** Artificial corid defines ****/
+/*
+ *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
+ *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
+ */
+#define MIPS_REVISION_CORID_CORE_EMUL_BON  -1
+#define MIPS_REVISION_CORID_CORE_EMUL_MSC  -2
+
+#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
+
+extern int mips_revision_corid;
+
+#define MIPS_REVISION_SCON_OTHER           0
+#define MIPS_REVISION_SCON_SOCITSC         1
+#define MIPS_REVISION_SCON_SOCITSCP        2
+
+/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
+#define MIPS_REVISION_SCON_UNKNOWN         -1
+#define MIPS_REVISION_SCON_GT64120         -2
+#define MIPS_REVISION_SCON_BONITO          -3
+#define MIPS_REVISION_SCON_BRTL            -4
+#define MIPS_REVISION_SCON_SOCIT           -5
+#define MIPS_REVISION_SCON_ROCIT           -6
+
+#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
+
+extern int mips_revision_sconid;
+
+extern void mips_reboot_setup(void);
+
+#ifdef CONFIG_PCI
+extern void mips_pcibios_init(void);
+#else
+#define mips_pcibios_init() do { } while (0)
+#endif
+
+#ifdef CONFIG_KGDB
+extern void kgdb_config(void);
+#endif
+
+#endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/arch/mips/include/asm/mips-boards/launch.h b/arch/mips/include/asm/mips-boards/launch.h
new file mode 100644
index 000000000000..d8ae7f95a522
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/launch.h
@@ -0,0 +1,35 @@
+/*
+ *
+ */
+
+#ifndef _ASSEMBLER_
+
+struct cpulaunch {
+    unsigned long       pc;
+    unsigned long       gp;
+    unsigned long       sp;
+    unsigned long       a0;
+    unsigned long       _pad[3]; /* pad to cache line size to avoid thrashing */
+    unsigned long       flags;
+};
+
+#else
+
+#define LOG2CPULAUNCH   5
+#define LAUNCH_PC       0
+#define LAUNCH_GP       4
+#define LAUNCH_SP       8
+#define LAUNCH_A0       12
+#define LAUNCH_FLAGS    28
+
+#endif
+
+#define LAUNCH_FREADY   1
+#define LAUNCH_FGO      2
+#define LAUNCH_FGONE    4
+
+#define CPULAUNCH       0x00000f00
+#define NCPULAUNCH      8
+
+/* Polling period in count cycles for secondary CPU's */
+#define LAUNCHPERIOD    10000
diff --git a/arch/mips/include/asm/mips-boards/malta.h b/arch/mips/include/asm/mips-boards/malta.h
new file mode 100644
index 000000000000..c1891578fa65
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/malta.h
@@ -0,0 +1,102 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Defines of the Malta board specific address-MAP, registers, etc.
+ */
+#ifndef __ASM_MIPS_BOARDS_MALTA_H
+#define __ASM_MIPS_BOARDS_MALTA_H
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/mips-boards/msc01_pci.h>
+#include <asm/gt64120.h>
+
+/* Mips interrupt controller found in SOCit variations */
+#define MIPS_MSC01_IC_REG_BASE          0x1bc40000
+#define MIPS_SOCITSC_IC_REG_BASE        0x1ffa0000
+
+/*
+ * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
+ * Bonito system controllers.
+ */
+#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
+#define MALTA_BONITO_PORT_BASE  ((unsigned long)ioremap (0x1fd00000, 0x10000))
+#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
+
+static inline unsigned long get_gt_port_base(unsigned long reg)
+{
+        unsigned long addr;
+        addr = GT_READ(reg);
+        return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
+}
+
+static inline unsigned long get_msc_port_base(unsigned long reg)
+{
+        unsigned long addr;
+        MSC_READ(reg, addr);
+        return (unsigned long) ioremap(addr, 0x10000);
+}
+
+/*
+ * GCMP Specific definitions
+ */
+#define GCMP_BASE_ADDR                  0x1fbf8000
+#define GCMP_ADDRSPACE_SZ               (256 * 1024)
+
+/*
+ * GIC Specific definitions
+ */
+#define GIC_BASE_ADDR                   0x1bdc0000
+#define GIC_ADDRSPACE_SZ                (128 * 1024)
+
+/*
+ * MSC01 BIU Specific definitions
+ * FIXME : These should be elsewhere ?
+ */
+#define MSC01_BIU_REG_BASE              0x1bc80000
+#define MSC01_BIU_ADDRSPACE_SZ          (256 * 1024)
+#define MSC01_SC_CFG_OFS                0x0110
+#define MSC01_SC_CFG_GICPRES_MSK        0x00000004
+#define MSC01_SC_CFG_GICPRES_SHF        2
+#define MSC01_SC_CFG_GICENA_SHF         3
+
+/*
+ * Malta RTC-device indirect register access.
+ */
+#define MALTA_RTC_ADR_REG       0x70
+#define MALTA_RTC_DAT_REG       0x71
+
+/*
+ * Malta SMSC FDC37M817 Super I/O Controller register.
+ */
+#define SMSC_CONFIG_REG         0x3f0
+#define SMSC_DATA_REG           0x3f1
+
+#define SMSC_CONFIG_DEVNUM      0x7
+#define SMSC_CONFIG_ACTIVATE    0x30
+#define SMSC_CONFIG_ENTER       0x55
+#define SMSC_CONFIG_EXIT        0xaa
+
+#define SMSC_CONFIG_DEVNUM_FLOPPY     0
+
+#define SMSC_CONFIG_ACTIVATE_ENABLE   1
+
+#define SMSC_WRITE(x, a)     outb(x, a)
+
+#define MALTA_JMPRS_REG         0x1f000210
+
+#endif /* __ASM_MIPS_BOARDS_MALTA_H */
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
new file mode 100644
index 000000000000..cea872fc6f5c
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -0,0 +1,110 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Defines for the Malta interrupt controller.
+ *
+ */
+#ifndef _MIPS_MALTAINT_H
+#define _MIPS_MALTAINT_H
+
+#include <irq.h>
+
+/*
+ * Interrupts 0..15 are used for Malta ISA compatible interrupts
+ */
+#define MALTA_INT_BASE          0
+
+/* CPU interrupt offsets */
+#define MIPSCPU_INT_SW0         0
+#define MIPSCPU_INT_SW1         1
+#define MIPSCPU_INT_MB0         2
+#define MIPSCPU_INT_I8259A      MIPSCPU_INT_MB0
+#define MIPSCPU_INT_MB1         3
+#define MIPSCPU_INT_SMI         MIPSCPU_INT_MB1
+#define MIPSCPU_INT_IPI0        MIPSCPU_INT_MB1 /* GIC IPI */
+#define MIPSCPU_INT_MB2         4
+#define MIPSCPU_INT_IPI1        MIPSCPU_INT_MB2 /* GIC IPI */
+#define MIPSCPU_INT_MB3         5
+#define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
+#define MIPSCPU_INT_MB4         6
+#define MIPSCPU_INT_CORELO      MIPSCPU_INT_MB4
+
+/*
+ * Interrupts 64..127 are used for Soc-it Classic interrupts
+ */
+#define MSC01C_INT_BASE         64
+
+/* SOC-it Classic interrupt offsets */
+#define MSC01C_INT_TMR          0
+#define MSC01C_INT_PCI          1
+
+/*
+ * Interrupts 64..127 are used for Soc-it EIC interrupts
+ */
+#define MSC01E_INT_BASE         64
+
+/* SOC-it EIC interrupt offsets */
+#define MSC01E_INT_SW0          1
+#define MSC01E_INT_SW1          2
+#define MSC01E_INT_MB0          3
+#define MSC01E_INT_I8259A       MSC01E_INT_MB0
+#define MSC01E_INT_MB1          4
+#define MSC01E_INT_SMI          MSC01E_INT_MB1
+#define MSC01E_INT_MB2          5
+#define MSC01E_INT_MB3          6
+#define MSC01E_INT_COREHI       MSC01E_INT_MB3
+#define MSC01E_INT_MB4          7
+#define MSC01E_INT_CORELO       MSC01E_INT_MB4
+#define MSC01E_INT_TMR          8
+#define MSC01E_INT_PCI          9
+#define MSC01E_INT_PERFCTR      10
+#define MSC01E_INT_CPUCTR       11
+
+/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
+#define GIC_CPU_INT0            0 /* Core Interrupt 2   */
+#define GIC_CPU_INT1            1 /* .                  */
+#define GIC_CPU_INT2            2 /* .                  */
+#define GIC_CPU_INT3            3 /* .                  */
+#define GIC_CPU_INT4            4 /* .                  */
+#define GIC_CPU_INT5            5 /* Core Interrupt 5   */
+
+#define GIC_EXT_INTR(x)         x
+
+/* Dummy data */
+#define X                       0xdead
+
+/* External Interrupts used for IPI */
+#define GIC_IPI_EXT_INTR_RESCHED_VPE0   16
+#define GIC_IPI_EXT_INTR_CALLFNC_VPE0   17
+#define GIC_IPI_EXT_INTR_RESCHED_VPE1   18
+#define GIC_IPI_EXT_INTR_CALLFNC_VPE1   19
+#define GIC_IPI_EXT_INTR_RESCHED_VPE2   20
+#define GIC_IPI_EXT_INTR_CALLFNC_VPE2   21
+#define GIC_IPI_EXT_INTR_RESCHED_VPE3   22
+#define GIC_IPI_EXT_INTR_CALLFNC_VPE3   23
+
+#define MIPS_GIC_IRQ_BASE       (MIPS_CPU_IRQ_BASE + 8)
+
+#ifndef __ASSEMBLY__
+extern void maltaint_init(void);
+#endif
+
+#endif /* !(_MIPS_MALTAINT_H) */
diff --git a/arch/mips/include/asm/mips-boards/msc01_pci.h b/arch/mips/include/asm/mips-boards/msc01_pci.h
new file mode 100644
index 000000000000..e036b7dd6deb
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/msc01_pci.h
@@ -0,0 +1,258 @@
+/*
+ * PCI Register definitions for the MIPS System Controller.
+ *
+ * Copyright (C) 2002, 2005  MIPS Technologies, Inc.  All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H
+#define __ASM_MIPS_BOARDS_MSC01_PCI_H
+
+/*
+ * Register offset addresses
+ */
+
+#define MSC01_PCI_ID_OFS                0x0000
+#define MSC01_PCI_SC2PMBASL_OFS         0x0208
+#define MSC01_PCI_SC2PMMSKL_OFS         0x0218
+#define MSC01_PCI_SC2PMMAPL_OFS         0x0228
+#define MSC01_PCI_SC2PIOBASL_OFS        0x0248
+#define MSC01_PCI_SC2PIOMSKL_OFS        0x0258
+#define MSC01_PCI_SC2PIOMAPL_OFS        0x0268
+#define MSC01_PCI_P2SCMSKL_OFS          0x0308
+#define MSC01_PCI_P2SCMAPL_OFS          0x0318
+#define MSC01_PCI_INTCFG_OFS            0x0600
+#define MSC01_PCI_INTSTAT_OFS           0x0608
+#define MSC01_PCI_CFGADDR_OFS           0x0610
+#define MSC01_PCI_CFGDATA_OFS           0x0618
+#define MSC01_PCI_IACK_OFS              0x0620
+#define MSC01_PCI_HEAD0_OFS             0x2000  /* DevID, VendorID */
+#define MSC01_PCI_HEAD1_OFS             0x2008  /* Status, Command */
+#define MSC01_PCI_HEAD2_OFS             0x2010  /* Class code, RevID */
+#define MSC01_PCI_HEAD3_OFS             0x2018  /* bist, header, latency */
+#define MSC01_PCI_HEAD4_OFS             0x2020  /* BAR 0 */
+#define MSC01_PCI_HEAD5_OFS             0x2028  /* BAR 1 */
+#define MSC01_PCI_HEAD6_OFS             0x2030  /* BAR 2 */
+#define MSC01_PCI_HEAD7_OFS             0x2038  /* BAR 3 */
+#define MSC01_PCI_HEAD8_OFS             0x2040  /* BAR 4 */
+#define MSC01_PCI_HEAD9_OFS             0x2048  /* BAR 5 */
+#define MSC01_PCI_HEAD10_OFS            0x2050  /* CardBus CIS Ptr */
+#define MSC01_PCI_HEAD11_OFS            0x2058  /* SubSystem ID, -VendorID */
+#define MSC01_PCI_HEAD12_OFS            0x2060  /* ROM BAR */
+#define MSC01_PCI_HEAD13_OFS            0x2068  /* Capabilities ptr */
+#define MSC01_PCI_HEAD14_OFS            0x2070  /* reserved */
+#define MSC01_PCI_HEAD15_OFS            0x2078  /* Maxl, ming, intpin, int */
+#define MSC01_PCI_BAR0_OFS              0x2220
+#define MSC01_PCI_CFG_OFS               0x2380
+#define MSC01_PCI_SWAP_OFS              0x2388
+
+
+/*****************************************************************************
+ * Register encodings
+ ****************************************************************************/
+
+#define MSC01_PCI_ID_ID_SHF             16
+#define MSC01_PCI_ID_ID_MSK             0x00ff0000
+#define MSC01_PCI_ID_ID_HOSTBRIDGE      82
+#define MSC01_PCI_ID_MAR_SHF            8
+#define MSC01_PCI_ID_MAR_MSK            0x0000ff00
+#define MSC01_PCI_ID_MIR_SHF            0
+#define MSC01_PCI_ID_MIR_MSK            0x000000ff
+
+#define MSC01_PCI_SC2PMBASL_BAS_SHF     24
+#define MSC01_PCI_SC2PMBASL_BAS_MSK     0xff000000
+
+#define MSC01_PCI_SC2PMMSKL_MSK_SHF     24
+#define MSC01_PCI_SC2PMMSKL_MSK_MSK     0xff000000
+
+#define MSC01_PCI_SC2PMMAPL_MAP_SHF     24
+#define MSC01_PCI_SC2PMMAPL_MAP_MSK     0xff000000
+
+#define MSC01_PCI_SC2PIOBASL_BAS_SHF    24
+#define MSC01_PCI_SC2PIOBASL_BAS_MSK    0xff000000
+
+#define MSC01_PCI_SC2PIOMSKL_MSK_SHF    24
+#define MSC01_PCI_SC2PIOMSKL_MSK_MSK    0xff000000
+
+#define MSC01_PCI_SC2PIOMAPL_MAP_SHF    24
+#define MSC01_PCI_SC2PIOMAPL_MAP_MSK    0xff000000
+
+#define MSC01_PCI_P2SCMSKL_MSK_SHF      24
+#define MSC01_PCI_P2SCMSKL_MSK_MSK      0xff000000
+
+#define MSC01_PCI_P2SCMAPL_MAP_SHF      24
+#define MSC01_PCI_P2SCMAPL_MAP_MSK      0xff000000
+
+#define MSC01_PCI_INTCFG_RST_SHF        10
+#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
+#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
+#define MSC01_PCI_INTCFG_MWE_SHF        9
+#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
+#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
+#define MSC01_PCI_INTCFG_DTO_SHF        8
+#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
+#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
+#define MSC01_PCI_INTCFG_MA_SHF         7
+#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
+#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
+#define MSC01_PCI_INTCFG_TA_SHF         6
+#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
+#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
+#define MSC01_PCI_INTCFG_RTY_SHF        5
+#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
+#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
+#define MSC01_PCI_INTCFG_MWP_SHF        4
+#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
+#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
+#define MSC01_PCI_INTCFG_MRP_SHF        3
+#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
+#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
+#define MSC01_PCI_INTCFG_SWP_SHF        2
+#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
+#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
+#define MSC01_PCI_INTCFG_SRP_SHF        1
+#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
+#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
+#define MSC01_PCI_INTCFG_SE_SHF         0
+#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
+#define MSC01_PCI_INTCFG_SE_BIT         0x00000001
+
+#define MSC01_PCI_INTSTAT_RST_SHF       10
+#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
+#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
+#define MSC01_PCI_INTSTAT_MWE_SHF       9
+#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
+#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
+#define MSC01_PCI_INTSTAT_DTO_SHF       8
+#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
+#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
+#define MSC01_PCI_INTSTAT_MA_SHF        7
+#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
+#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
+#define MSC01_PCI_INTSTAT_TA_SHF        6
+#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
+#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
+#define MSC01_PCI_INTSTAT_RTY_SHF       5
+#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
+#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
+#define MSC01_PCI_INTSTAT_MWP_SHF       4
+#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
+#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
+#define MSC01_PCI_INTSTAT_MRP_SHF       3
+#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
+#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
+#define MSC01_PCI_INTSTAT_SWP_SHF       2
+#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
+#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
+#define MSC01_PCI_INTSTAT_SRP_SHF       1
+#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002
+#define MSC01_PCI_INTSTAT_SRP_BIT       0x00000002
+#define MSC01_PCI_INTSTAT_SE_SHF        0
+#define MSC01_PCI_INTSTAT_SE_MSK        0x00000001
+#define MSC01_PCI_INTSTAT_SE_BIT        0x00000001
+
+#define MSC01_PCI_CFGADDR_BNUM_SHF      16
+#define MSC01_PCI_CFGADDR_BNUM_MSK      0x00ff0000
+#define MSC01_PCI_CFGADDR_DNUM_SHF      11
+#define MSC01_PCI_CFGADDR_DNUM_MSK      0x0000f800
+#define MSC01_PCI_CFGADDR_FNUM_SHF      8
+#define MSC01_PCI_CFGADDR_FNUM_MSK      0x00000700
+#define MSC01_PCI_CFGADDR_RNUM_SHF      2
+#define MSC01_PCI_CFGADDR_RNUM_MSK      0x000000fc
+
+#define MSC01_PCI_CFGDATA_DATA_SHF      0
+#define MSC01_PCI_CFGDATA_DATA_MSK      0xffffffff
+
+/* The defines below are ONLY valid for a MEM bar! */
+#define MSC01_PCI_BAR0_SIZE_SHF         4
+#define MSC01_PCI_BAR0_SIZE_MSK         0xfffffff0
+#define MSC01_PCI_BAR0_P_SHF            3
+#define MSC01_PCI_BAR0_P_MSK            0x00000008
+#define MSC01_PCI_BAR0_P_BIT            MSC01_PCI_BAR0_P_MSK
+#define MSC01_PCI_BAR0_D_SHF            1
+#define MSC01_PCI_BAR0_D_MSK            0x00000006
+#define MSC01_PCI_BAR0_T_SHF            0
+#define MSC01_PCI_BAR0_T_MSK            0x00000001
+#define MSC01_PCI_BAR0_T_BIT            MSC01_PCI_BAR0_T_MSK
+
+
+#define MSC01_PCI_CFG_RA_SHF            17
+#define MSC01_PCI_CFG_RA_MSK            0x00020000
+#define MSC01_PCI_CFG_RA_BIT            MSC01_PCI_CFG_RA_MSK
+#define MSC01_PCI_CFG_G_SHF             16
+#define MSC01_PCI_CFG_G_MSK             0x00010000
+#define MSC01_PCI_CFG_G_BIT             MSC01_PCI_CFG_G_MSK
+#define MSC01_PCI_CFG_EN_SHF            15
+#define MSC01_PCI_CFG_EN_MSK            0x00008000
+#define MSC01_PCI_CFG_EN_BIT            MSC01_PCI_CFG_EN_MSK
+#define MSC01_PCI_CFG_MAXRTRY_SHF       0
+#define MSC01_PCI_CFG_MAXRTRY_MSK       0x00000fff
+
+#define MSC01_PCI_SWAP_IO_SHF           18
+#define MSC01_PCI_SWAP_IO_MSK           0x000c0000
+#define MSC01_PCI_SWAP_MEM_SHF          16
+#define MSC01_PCI_SWAP_MEM_MSK          0x00030000
+#define MSC01_PCI_SWAP_BAR0_SHF         0
+#define MSC01_PCI_SWAP_BAR0_MSK         0x00000003
+#define MSC01_PCI_SWAP_NOSWAP           0
+#define MSC01_PCI_SWAP_BYTESWAP         1
+
+/*
+ * MIPS System controller PCI register base.
+ *
+ * FIXME - are these macros specific to Malta and co or to the MSC?  If the
+ * latter, they should be moved elsewhere.
+ */
+#define MIPS_MSC01_PCI_REG_BASE         0x1bd00000
+#define MIPS_SOCITSC_PCI_REG_BASE       0x1ff10000
+
+extern unsigned long _pcictrl_msc;
+
+#define MSC01_PCI_REG_BASE      _pcictrl_msc
+
+#define MSC_WRITE(reg, data)    do { *(volatile u32 *)(reg) = data; } while (0)
+#define MSC_READ(reg, data)     do { data = *(volatile u32 *)(reg); } while (0)
+
+/*
+ * Registers absolute addresses
+ */
+
+#define MSC01_PCI_ID            (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
+#define MSC01_PCI_SC2PMBASL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
+#define MSC01_PCI_SC2PMMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
+#define MSC01_PCI_SC2PMMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
+#define MSC01_PCI_SC2PIOBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
+#define MSC01_PCI_SC2PIOMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
+#define MSC01_PCI_SC2PIOMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
+#define MSC01_PCI_P2SCMSKL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
+#define MSC01_PCI_P2SCMAPL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
+#define MSC01_PCI_INTCFG        (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
+#define MSC01_PCI_INTSTAT       (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
+#define MSC01_PCI_CFGADDR       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
+#define MSC01_PCI_CFGDATA       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
+#define MSC01_PCI_IACK          (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
+#define MSC01_PCI_HEAD0         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
+#define MSC01_PCI_HEAD1         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
+#define MSC01_PCI_HEAD2         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS)
+#define MSC01_PCI_HEAD3         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS)
+#define MSC01_PCI_HEAD4         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS)
+#define MSC01_PCI_HEAD5         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS)
+#define MSC01_PCI_HEAD6         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS)
+#define MSC01_PCI_HEAD7         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS)
+#define MSC01_PCI_HEAD8         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS)
+#define MSC01_PCI_HEAD9         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS)
+#define MSC01_PCI_HEAD10        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS)
+#define MSC01_PCI_HEAD11        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD12        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD13        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD14        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_HEAD15        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
+#define MSC01_PCI_BAR0          (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
+#define MSC01_PCI_CFG           (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
+#define MSC01_PCI_SWAP          (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
+
+#endif /* __ASM_MIPS_BOARDS_MSC01_PCI_H */
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
new file mode 100644
index 000000000000..2971d60f2e95
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -0,0 +1,80 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Register definitions for Intel PIIX4 South Bridge Device.
+ */
+#ifndef __ASM_MIPS_BOARDS_PIIX4_H
+#define __ASM_MIPS_BOARDS_PIIX4_H
+
+/************************************************************************
+ *  IO register offsets
+ ************************************************************************/
+#define PIIX4_ICTLR1_ICW1       0x20
+#define PIIX4_ICTLR1_ICW2       0x21
+#define PIIX4_ICTLR1_ICW3       0x21
+#define PIIX4_ICTLR1_ICW4       0x21
+#define PIIX4_ICTLR2_ICW1       0xa0
+#define PIIX4_ICTLR2_ICW2       0xa1
+#define PIIX4_ICTLR2_ICW3       0xa1
+#define PIIX4_ICTLR2_ICW4       0xa1
+#define PIIX4_ICTLR1_OCW1       0x21
+#define PIIX4_ICTLR1_OCW2       0x20
+#define PIIX4_ICTLR1_OCW3       0x20
+#define PIIX4_ICTLR1_OCW4       0x20
+#define PIIX4_ICTLR2_OCW1       0xa1
+#define PIIX4_ICTLR2_OCW2       0xa0
+#define PIIX4_ICTLR2_OCW3       0xa0
+#define PIIX4_ICTLR2_OCW4       0xa0
+
+
+/************************************************************************
+ *  Register encodings.
+ ************************************************************************/
+#define PIIX4_OCW2_NSEOI        (0x1 << 5)
+#define PIIX4_OCW2_SEOI         (0x3 << 5)
+#define PIIX4_OCW2_RNSEOI       (0x5 << 5)
+#define PIIX4_OCW2_RAEOIS       (0x4 << 5)
+#define PIIX4_OCW2_RAEOIC       (0x0 << 5)
+#define PIIX4_OCW2_RSEOI        (0x7 << 5)
+#define PIIX4_OCW2_SP           (0x6 << 5)
+#define PIIX4_OCW2_NOP          (0x2 << 5)
+
+#define PIIX4_OCW2_SEL          (0x0 << 3)
+
+#define PIIX4_OCW2_ILS_0        0
+#define PIIX4_OCW2_ILS_1        1
+#define PIIX4_OCW2_ILS_2        2
+#define PIIX4_OCW2_ILS_3        3
+#define PIIX4_OCW2_ILS_4        4
+#define PIIX4_OCW2_ILS_5        5
+#define PIIX4_OCW2_ILS_6        6
+#define PIIX4_OCW2_ILS_7        7
+#define PIIX4_OCW2_ILS_8        0
+#define PIIX4_OCW2_ILS_9        1
+#define PIIX4_OCW2_ILS_10       2
+#define PIIX4_OCW2_ILS_11       3
+#define PIIX4_OCW2_ILS_12       4
+#define PIIX4_OCW2_ILS_13       5
+#define PIIX4_OCW2_ILS_14       6
+#define PIIX4_OCW2_ILS_15       7
+
+#define PIIX4_OCW3_SEL          (0x1 << 3)
+
+#define PIIX4_OCW3_IRR          0x2
+#define PIIX4_OCW3_ISR          0x3
+
+#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h
new file mode 100644
index 000000000000..a9db576a9768
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/prom.h
@@ -0,0 +1,47 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * MIPS boards bootprom interface for the Linux kernel.
+ *
+ */
+
+#ifndef _MIPS_PROM_H
+#define _MIPS_PROM_H
+
+extern char *prom_getcmdline(void);
+extern char *prom_getenv(char *name);
+extern void prom_init_cmdline(void);
+extern void prom_meminit(void);
+extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
+extern void mips_display_message(const char *str);
+extern void mips_display_word(unsigned int num);
+extern void mips_scroll_message(void);
+extern int get_ethernet_addr(char *ethernet_addr);
+
+/* Memory descriptor management. */
+#define PROM_MAX_PMEMBLOCKS    32
+struct prom_pmemblock {
+        unsigned long base; /* Within KSEG0. */
+        unsigned int size;  /* In bytes. */
+        unsigned int type;  /* free or prom memory */
+};
+
+#endif /* !(_MIPS_PROM_H) */
diff --git a/arch/mips/include/asm/mips-boards/sim.h b/arch/mips/include/asm/mips-boards/sim.h
new file mode 100644
index 000000000000..acb7c2331d98
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/sim.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#ifndef _ASM_MIPS_BOARDS_SIM_H
+#define _ASM_MIPS_BOARDS_SIM_H
+
+#define STATS_ON        1
+#define STATS_OFF       2
+#define STATS_CLEAR     3
+#define STATS_DUMP      4
+#define TRACE_ON                5
+#define TRACE_OFF       6
+
+
+#define simcfg(code)                                            \
+({                                         \
+        __asm__  __volatile__( \
+        "sltiu $0,$0, %0" \
+                ::"i"(code)                                     \
+                ); \
+})
+
+
+
+#endif
diff --git a/arch/mips/include/asm/mips-boards/simint.h b/arch/mips/include/asm/mips-boards/simint.h
new file mode 100644
index 000000000000..8ef6db76d5c1
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/simint.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef _MIPS_SIMINT_H
+#define _MIPS_SIMINT_H
+
+#include <irq.h>
+
+#define SIM_INT_BASE            0
+#define MIPSCPU_INT_MB0         2
+#define MIPS_CPU_TIMER_IRQ      7
+
+
+#define MSC01E_INT_BASE         64
+
+#define MSC01E_INT_CPUCTR       11
+
+#endif
diff --git a/arch/mips/include/asm/mips_mt.h b/arch/mips/include/asm/mips_mt.h
new file mode 100644
index 000000000000..ac7935203f89
--- /dev/null
+++ b/arch/mips/include/asm/mips_mt.h
@@ -0,0 +1,26 @@
+/*
+ * Definitions and decalrations for MIPS MT support
+ * that are common between SMTC, VSMP, and/or AP/SP
+ * kernel models.
+ */
+#ifndef __ASM_MIPS_MT_H
+#define __ASM_MIPS_MT_H
+
+#include <linux/cpumask.h>
+
+/*
+ * How many VPEs and TCs is Linux allowed to use?  0 means no limit.
+ */
+extern int tclimit;
+extern int vpelimit;
+
+extern cpumask_t mt_fpu_cpumask;
+extern unsigned long mt_fpemul_threshold;
+
+extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value);
+extern void mips_mt_set_cpuoptions(void);
+
+struct class;
+extern struct class *mt_class;
+
+#endif /* __ASM_MIPS_MT_H */
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
new file mode 100644
index 000000000000..c9420aa97e32
--- /dev/null
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -0,0 +1,395 @@
+/*
+ * MT regs definitions, follows on from mipsregs.h
+ * Copyright (C) 2004 - 2005 MIPS Technologies, Inc.  All rights reserved.
+ * Elizabeth Clarke et. al.
+ *
+ */
+#ifndef _ASM_MIPSMTREGS_H
+#define _ASM_MIPSMTREGS_H
+
+#include <asm/mipsregs.h>
+#include <asm/war.h>
+
+#ifndef __ASSEMBLY__
+
+/*
+ * C macros
+ */
+
+#define read_c0_mvpcontrol()            __read_32bit_c0_register($0, 1)
+#define write_c0_mvpcontrol(val)        __write_32bit_c0_register($0, 1, val)
+
+#define read_c0_mvpconf0()              __read_32bit_c0_register($0, 2)
+#define read_c0_mvpconf1()              __read_32bit_c0_register($0, 3)
+
+#define read_c0_vpecontrol()            __read_32bit_c0_register($1, 1)
+#define write_c0_vpecontrol(val)        __write_32bit_c0_register($1, 1, val)
+
+#define read_c0_vpeconf0()              __read_32bit_c0_register($1, 2)
+#define write_c0_vpeconf0(val)          __write_32bit_c0_register($1, 2, val)
+
+#define read_c0_tcstatus()              __read_32bit_c0_register($2, 1)
+#define write_c0_tcstatus(val)          __write_32bit_c0_register($2, 1, val)
+
+#define read_c0_tcbind()                __read_32bit_c0_register($2, 2)
+
+#define read_c0_tccontext()             __read_32bit_c0_register($2, 5)
+#define write_c0_tccontext(val)         __write_32bit_c0_register($2, 5, val)
+
+#else /* Assembly */
+/*
+ * Macros for use in assembly language code
+ */
+
+#define CP0_MVPCONTROL          $0, 1
+#define CP0_MVPCONF0            $0, 2
+#define CP0_MVPCONF1            $0, 3
+#define CP0_VPECONTROL          $1, 1
+#define CP0_VPECONF0            $1, 2
+#define CP0_VPECONF1            $1, 3
+#define CP0_YQMASK              $1, 4
+#define CP0_VPESCHEDULE $1, 5
+#define CP0_VPESCHEFBK          $1, 6
+#define CP0_TCSTATUS            $2, 1
+#define CP0_TCBIND              $2, 2
+#define CP0_TCRESTART           $2, 3
+#define CP0_TCHALT              $2, 4
+#define CP0_TCCONTEXT           $2, 5
+#define CP0_TCSCHEDULE          $2, 6
+#define CP0_TCSCHEFBK           $2, 7
+#define CP0_SRSCONF0            $6, 1
+#define CP0_SRSCONF1            $6, 2
+#define CP0_SRSCONF2            $6, 3
+#define CP0_SRSCONF3            $6, 4
+#define CP0_SRSCONF4            $6, 5
+
+#endif
+
+/* MVPControl fields */
+#define MVPCONTROL_EVP          (_ULCAST_(1))
+
+#define MVPCONTROL_VPC_SHIFT    1
+#define MVPCONTROL_VPC          (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
+
+#define MVPCONTROL_STLB_SHIFT   2
+#define MVPCONTROL_STLB         (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
+
+
+/* MVPConf0 fields */
+#define MVPCONF0_PTC_SHIFT      0
+#define MVPCONF0_PTC            ( _ULCAST_(0xff))
+#define MVPCONF0_PVPE_SHIFT     10
+#define MVPCONF0_PVPE           ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
+#define MVPCONF0_TCA_SHIFT      15
+#define MVPCONF0_TCA            ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
+#define MVPCONF0_PTLBE_SHIFT    16
+#define MVPCONF0_PTLBE          (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
+#define MVPCONF0_TLBS_SHIFT     29
+#define MVPCONF0_TLBS           (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
+#define MVPCONF0_M_SHIFT        31
+#define MVPCONF0_M              (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
+
+
+/* config3 fields */
+#define CONFIG3_MT_SHIFT        2
+#define CONFIG3_MT              (_ULCAST_(1) << CONFIG3_MT_SHIFT)
+
+
+/* VPEControl fields (per VPE) */
+#define VPECONTROL_TARGTC       (_ULCAST_(0xff))
+
+#define VPECONTROL_TE_SHIFT     15
+#define VPECONTROL_TE           (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
+#define VPECONTROL_EXCPT_SHIFT  16
+#define VPECONTROL_EXCPT        (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
+
+/* Thread Exception Codes for EXCPT field */
+#define THREX_TU                0
+#define THREX_TO                1
+#define THREX_IYQ               2
+#define THREX_GSX               3
+#define THREX_YSCH              4
+#define THREX_GSSCH             5
+
+#define VPECONTROL_GSI_SHIFT    20
+#define VPECONTROL_GSI          (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
+#define VPECONTROL_YSI_SHIFT    21
+#define VPECONTROL_YSI          (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
+
+/* VPEConf0 fields (per VPE) */
+#define VPECONF0_VPA_SHIFT      0
+#define VPECONF0_VPA            (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
+#define VPECONF0_MVP_SHIFT      1
+#define VPECONF0_MVP            (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
+#define VPECONF0_XTC_SHIFT      21
+#define VPECONF0_XTC            (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
+
+/* TCStatus fields (per TC) */
+#define TCSTATUS_TASID          (_ULCAST_(0xff))
+#define TCSTATUS_IXMT_SHIFT     10
+#define TCSTATUS_IXMT           (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
+#define TCSTATUS_TKSU_SHIFT     11
+#define TCSTATUS_TKSU           (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
+#define TCSTATUS_A_SHIFT        13
+#define TCSTATUS_A              (_ULCAST_(1) << TCSTATUS_A_SHIFT)
+#define TCSTATUS_DA_SHIFT       15
+#define TCSTATUS_DA             (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
+#define TCSTATUS_DT_SHIFT       20
+#define TCSTATUS_DT             (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
+#define TCSTATUS_TDS_SHIFT      21
+#define TCSTATUS_TDS            (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
+#define TCSTATUS_TSST_SHIFT     22
+#define TCSTATUS_TSST           (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
+#define TCSTATUS_RNST_SHIFT     23
+#define TCSTATUS_RNST           (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
+/* Codes for RNST */
+#define TC_RUNNING              0
+#define TC_WAITING              1
+#define TC_YIELDING             2
+#define TC_GATED                3
+
+#define TCSTATUS_TMX_SHIFT      27
+#define TCSTATUS_TMX            (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
+/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
+
+/* TCBind */
+#define TCBIND_CURVPE_SHIFT     0
+#define TCBIND_CURVPE           (_ULCAST_(0xf))
+
+#define TCBIND_CURTC_SHIFT      21
+
+#define TCBIND_CURTC            (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
+
+/* TCHalt */
+#define TCHALT_H                (_ULCAST_(1))
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned int dvpe(void)
+{
+        int res = 0;
+
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41610001              # dvpe $1               \n"
+        "       move    %0, $1                                          \n"
+        "       ehb                                                     \n"
+        "       .set    pop                                             \n"
+        : "=r" (res));
+
+        instruction_hazard();
+
+        return res;
+}
+
+static inline void __raw_evpe(void)
+{
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    noreorder                                       \n"
+        "       .set    noat                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41600021              # evpe                  \n"
+        "       ehb                                                     \n"
+        "       .set    pop                                             \n");
+}
+
+/* Enable virtual processor execution if previous suggested it should be.
+   EVPE_ENABLE to force */
+
+#define EVPE_ENABLE MVPCONTROL_EVP
+
+static inline void evpe(int previous)
+{
+        if ((previous & MVPCONTROL_EVP))
+                __raw_evpe();
+}
+
+static inline unsigned int dmt(void)
+{
+        int res;
+
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .set    noat                                            \n"
+        "       .word   0x41610BC1                      # dmt $1        \n"
+        "       ehb                                                     \n"
+        "       move    %0, $1                                          \n"
+        "       .set    pop                                             \n"
+        : "=r" (res));
+
+        instruction_hazard();
+
+        return res;
+}
+
+static inline void __raw_emt(void)
+{
+        __asm__ __volatile__(
+        "       .set    noreorder                                       \n"
+        "       .set    mips32r2                                        \n"
+        "       .word   0x41600be1                      # emt           \n"
+        "       ehb                                                     \n"
+        "       .set    mips0                                           \n"
+        "       .set    reorder");
+}
+
+/* enable multi-threaded execution if previous suggested it should be.
+   EMT_ENABLE to force */
+
+#define EMT_ENABLE VPECONTROL_TE
+
+static inline void emt(int previous)
+{
+        if ((previous & EMT_ENABLE))
+                __raw_emt();
+}
+
+static inline void ehb(void)
+{
+        __asm__ __volatile__(
+        "       .set    mips32r2                                \n"
+        "       ehb                                             \n"
+        "       .set    mips0                                   \n");
+}
+
+#define mftc0(rt,sel)                                                   \
+({                                                                      \
+         unsigned long  __res;                                          \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       # mftc0 $1, $" #rt ", " #sel "                  \n"     \
+        "       .word   0x41000800 | (" #rt " << 16) | " #sel " \n"     \
+        "       move    %0, $1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+
+#define mftgpr(rt)                                                      \
+({                                                                      \
+        unsigned long __res;                                            \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       # mftgpr $1," #rt "                             \n"     \
+        "       .word   0x41000820 | (" #rt " << 16)            \n"     \
+        "       move    %0, $1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+
+#define mftr(rt, u, sel)                                                        \
+({                                                                      \
+        unsigned long __res;                                            \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       mftr    %0, " #rt ", " #u ", " #sel "           \n"     \
+        : "=r" (__res));                                                \
+                                                                        \
+        __res;                                                          \
+})
+
+#define mttgpr(rd,v)                                                    \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mttgpr $1, " #rd "                            \n"     \
+        "       .word   0x41810020 | (" #rd " << 11)            \n"     \
+        "       .set    pop                                     \n"     \
+        : : "r" (v));                                                   \
+} while (0)
+
+#define mttc0(rd, sel, v)                                                       \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    mips32r2                                \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mttc0 %0," #rd ", " #sel "                    \n"     \
+        "       .word   0x41810000 | (" #rd " << 11) | " #sel " \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (v));                                                     \
+})
+
+
+#define mttr(rd, u, sel, v)                                             \
+({                                                                      \
+        __asm__ __volatile__(                                           \
+        "mttr   %0," #rd ", " #u ", " #sel                              \
+        : : "r" (v));                                                   \
+})
+
+
+#define settc(tc)                                                       \
+do {                                                                    \
+        write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
+        ehb();                                                          \
+} while (0)
+
+
+/* you *must* set the target tc (settc) before trying to use these */
+#define read_vpe_c0_vpecontrol()        mftc0(1, 1)
+#define write_vpe_c0_vpecontrol(val)    mttc0(1, 1, val)
+#define read_vpe_c0_vpeconf0()          mftc0(1, 2)
+#define write_vpe_c0_vpeconf0(val)      mttc0(1, 2, val)
+#define read_vpe_c0_count()             mftc0(9, 0)
+#define write_vpe_c0_count(val)         mttc0(9, 0, val)
+#define read_vpe_c0_status()            mftc0(12, 0)
+#define write_vpe_c0_status(val)        mttc0(12, 0, val)
+#define read_vpe_c0_cause()             mftc0(13, 0)
+#define write_vpe_c0_cause(val)         mttc0(13, 0, val)
+#define read_vpe_c0_config()            mftc0(16, 0)
+#define write_vpe_c0_config(val)        mttc0(16, 0, val)
+#define read_vpe_c0_config1()           mftc0(16, 1)
+#define write_vpe_c0_config1(val)       mttc0(16, 1, val)
+#define read_vpe_c0_config7()           mftc0(16, 7)
+#define write_vpe_c0_config7(val)       mttc0(16, 7, val)
+#define read_vpe_c0_ebase()             mftc0(15, 1)
+#define write_vpe_c0_ebase(val)         mttc0(15, 1, val)
+#define write_vpe_c0_compare(val)       mttc0(11, 0, val)
+#define read_vpe_c0_badvaddr()          mftc0(8, 0)
+#define read_vpe_c0_epc()               mftc0(14, 0)
+#define write_vpe_c0_epc(val)           mttc0(14, 0, val)
+
+
+/* TC */
+#define read_tc_c0_tcstatus()           mftc0(2, 1)
+#define write_tc_c0_tcstatus(val)       mttc0(2, 1, val)
+#define read_tc_c0_tcbind()             mftc0(2, 2)
+#define write_tc_c0_tcbind(val)         mttc0(2, 2, val)
+#define read_tc_c0_tcrestart()          mftc0(2, 3)
+#define write_tc_c0_tcrestart(val)      mttc0(2, 3, val)
+#define read_tc_c0_tchalt()             mftc0(2, 4)
+#define write_tc_c0_tchalt(val)         mttc0(2, 4, val)
+#define read_tc_c0_tccontext()          mftc0(2, 5)
+#define write_tc_c0_tccontext(val)      mttc0(2, 5, val)
+
+/* GPR */
+#define read_tc_gpr_sp()                mftgpr(29)
+#define write_tc_gpr_sp(val)            mttgpr(29, val)
+#define read_tc_gpr_gp()                mftgpr(28)
+#define write_tc_gpr_gp(val)            mttgpr(28, val)
+
+__BUILD_SET_C0(mvpcontrol)
+
+#endif /* Not __ASSEMBLY__ */
+
+#endif
diff --git a/arch/mips/include/asm/mipsprom.h b/arch/mips/include/asm/mipsprom.h
new file mode 100644
index 000000000000..146d41b67adc
--- /dev/null
+++ b/arch/mips/include/asm/mipsprom.h
@@ -0,0 +1,76 @@
+#ifndef __ASM_MIPS_PROM_H
+#define __ASM_MIPS_PROM_H
+
+#define PROM_RESET              0
+#define PROM_EXEC               1
+#define PROM_RESTART            2
+#define PROM_REINIT             3
+#define PROM_REBOOT             4
+#define PROM_AUTOBOOT           5
+#define PROM_OPEN               6
+#define PROM_READ               7
+#define PROM_WRITE              8
+#define PROM_IOCTL              9
+#define PROM_CLOSE              10
+#define PROM_GETCHAR            11
+#define PROM_PUTCHAR            12
+#define PROM_SHOWCHAR           13      /* XXX */
+#define PROM_GETS               14      /* XXX */
+#define PROM_PUTS               15      /* XXX */
+#define PROM_PRINTF             16      /* XXX */
+
+/* What are these for? */
+#define PROM_INITPROTO          17      /* XXX */
+#define PROM_PROTOENABLE        18      /* XXX */
+#define PROM_PROTODISABLE       19      /* XXX */
+#define PROM_GETPKT             20      /* XXX */
+#define PROM_PUTPKT             21      /* XXX */
+
+/* More PROM shit.  Probably has to do with VME RMW cycles??? */
+#define PROM_ORW_RMW            22      /* XXX */
+#define PROM_ORH_RMW            23      /* XXX */
+#define PROM_ORB_RMW            24      /* XXX */
+#define PROM_ANDW_RMW           25      /* XXX */
+#define PROM_ANDH_RMW           26      /* XXX */
+#define PROM_ANDB_RMW           27      /* XXX */
+
+/* Cache handling stuff */
+#define PROM_FLUSHCACHE         28      /* XXX */
+#define PROM_CLEARCACHE         29      /* XXX */
+
+/* Libc alike stuff */
+#define PROM_SETJMP             30      /* XXX */
+#define PROM_LONGJMP            31      /* XXX */
+#define PROM_BEVUTLB            32      /* XXX */
+#define PROM_GETENV             33      /* XXX */
+#define PROM_SETENV             34      /* XXX */
+#define PROM_ATOB               35      /* XXX */
+#define PROM_STRCMP             36      /* XXX */
+#define PROM_STRLEN             37      /* XXX */
+#define PROM_STRCPY             38      /* XXX */
+#define PROM_STRCAT             39      /* XXX */
+
+/* Misc stuff */
+#define PROM_PARSER             40      /* XXX */
+#define PROM_RANGE              41      /* XXX */
+#define PROM_ARGVIZE            42      /* XXX */
+#define PROM_HELP               43      /* XXX */
+
+/* Entry points for some PROM commands */
+#define PROM_DUMPCMD            44      /* XXX */
+#define PROM_SETENVCMD          45      /* XXX */
+#define PROM_UNSETENVCMD        46      /* XXX */
+#define PROM_PRINTENVCMD        47      /* XXX */
+#define PROM_BEVEXCEPT          48      /* XXX */
+#define PROM_ENABLECMD          49      /* XXX */
+#define PROM_DISABLECMD         50      /* XXX */
+
+#define PROM_CLEARNOFAULT       51      /* XXX */
+#define PROM_NOTIMPLEMENT       52      /* XXX */
+
+#define PROM_NV_GET             53      /* XXX */
+#define PROM_NV_SET             54      /* XXX */
+
+extern char *prom_getenv(char *);
+
+#endif /* __ASM_MIPS_PROM_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
new file mode 100644
index 000000000000..979866000da4
--- /dev/null
+++ b/arch/mips/include/asm/mipsregs.h
@@ -0,0 +1,1526 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Modified for further R[236]000 support by Paul M. Antoine, 1996.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ * Copyright (C) 2003, 2004  Maciej W. Rozycki
+ */
+#ifndef _ASM_MIPSREGS_H
+#define _ASM_MIPSREGS_H
+
+#include <linux/linkage.h>
+#include <asm/hazards.h>
+#include <asm/war.h>
+
+/*
+ * The following macros are especially useful for __asm__
+ * inline assembler.
+ */
+#ifndef __STR
+#define __STR(x) #x
+#endif
+#ifndef STR
+#define STR(x) __STR(x)
+#endif
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ULCAST_
+#else
+#define _ULCAST_ (unsigned long)
+#endif
+
+/*
+ * Coprocessor 0 register names
+ */
+#define CP0_INDEX $0
+#define CP0_RANDOM $1
+#define CP0_ENTRYLO0 $2
+#define CP0_ENTRYLO1 $3
+#define CP0_CONF $3
+#define CP0_CONTEXT $4
+#define CP0_PAGEMASK $5
+#define CP0_WIRED $6
+#define CP0_INFO $7
+#define CP0_BADVADDR $8
+#define CP0_COUNT $9
+#define CP0_ENTRYHI $10
+#define CP0_COMPARE $11
+#define CP0_STATUS $12
+#define CP0_CAUSE $13
+#define CP0_EPC $14
+#define CP0_PRID $15
+#define CP0_CONFIG $16
+#define CP0_LLADDR $17
+#define CP0_WATCHLO $18
+#define CP0_WATCHHI $19
+#define CP0_XCONTEXT $20
+#define CP0_FRAMEMASK $21
+#define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
+#define CP0_PERFORMANCE $25
+#define CP0_ECC $26
+#define CP0_CACHEERR $27
+#define CP0_TAGLO $28
+#define CP0_TAGHI $29
+#define CP0_ERROREPC $30
+#define CP0_DESAVE $31
+
+/*
+ * R4640/R4650 cp0 register names.  These registers are listed
+ * here only for completeness; without MMU these CPUs are not useable
+ * by Linux.  A future ELKS port might take make Linux run on them
+ * though ...
+ */
+#define CP0_IBASE $0
+#define CP0_IBOUND $1
+#define CP0_DBASE $2
+#define CP0_DBOUND $3
+#define CP0_CALG $17
+#define CP0_IWATCH $18
+#define CP0_DWATCH $19
+
+/*
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  $26
+#define CP0_S1_DERRADDR1  $27
+#define CP0_S1_INTCONTROL $20
+
+/*
+ * Coprocessor 0 Set 2 register names
+ */
+#define CP0_S2_SRSCTL     $12   /* MIPSR2 */
+
+/*
+ * Coprocessor 0 Set 3 register names
+ */
+#define CP0_S3_SRSMAP     $12   /* MIPSR2 */
+
+/*
+ *  TX39 Series
+ */
+#define CP0_TX39_CACHE  $7
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION   $0
+#define CP1_STATUS     $31
+
+/*
+ * FPU Status Register Values
+ */
+/*
+ * Status Register Values
+ */
+
+#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
+#define FPU_CSR_COND    0x00800000      /* $fcc0 */
+#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
+#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
+#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
+#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
+#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
+#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
+#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
+#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X   0x0003f000
+#define FPU_CSR_UNI_X   0x00020000
+#define FPU_CSR_INV_X   0x00010000
+#define FPU_CSR_DIV_X   0x00008000
+#define FPU_CSR_OVF_X   0x00004000
+#define FPU_CSR_UDF_X   0x00002000
+#define FPU_CSR_INE_X   0x00001000
+
+#define FPU_CSR_ALL_E   0x00000f80
+#define FPU_CSR_INV_E   0x00000800
+#define FPU_CSR_DIV_E   0x00000400
+#define FPU_CSR_OVF_E   0x00000200
+#define FPU_CSR_UDF_E   0x00000100
+#define FPU_CSR_INE_E   0x00000080
+
+#define FPU_CSR_ALL_S   0x0000007c
+#define FPU_CSR_INV_S   0x00000040
+#define FPU_CSR_DIV_S   0x00000020
+#define FPU_CSR_OVF_S   0x00000010
+#define FPU_CSR_UDF_S   0x00000008
+#define FPU_CSR_INE_S   0x00000004
+
+/* rounding mode */
+#define FPU_CSR_RN      0x0     /* nearest */
+#define FPU_CSR_RZ      0x1     /* towards zero */
+#define FPU_CSR_RU      0x2     /* towards +Infinity */
+#define FPU_CSR_RD      0x3     /* towards -Infinity */
+
+
+/*
+ * Values for PageMask register
+ */
+#ifdef CONFIG_CPU_VR41XX
+
+/* Why doesn't stupidity hurt ... */
+
+#define PM_1K           0x00000000
+#define PM_4K           0x00001800
+#define PM_16K          0x00007800
+#define PM_64K          0x0001f800
+#define PM_256K         0x0007f800
+
+#else
+
+#define PM_4K           0x00000000
+#define PM_16K          0x00006000
+#define PM_64K          0x0001e000
+#define PM_256K         0x0007e000
+#define PM_1M           0x001fe000
+#define PM_4M           0x007fe000
+#define PM_16M          0x01ffe000
+#define PM_64M          0x07ffe000
+#define PM_256M         0x1fffe000
+
+#endif
+
+/*
+ * Default page size for a given kernel configuration
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PM_DEFAULT_MASK PM_4K
+#elif defined(CONFIG_PAGE_SIZE_16KB)
+#define PM_DEFAULT_MASK PM_16K
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+#define PM_DEFAULT_MASK PM_64K
+#else
+#error Bad page size configuration!
+#endif
+
+
+/*
+ * Values used for computation of new tlb entries
+ */
+#define PL_4K           12
+#define PL_16K          14
+#define PL_64K          16
+#define PL_256K         18
+#define PL_1M           20
+#define PL_4M           22
+#define PL_16M          24
+#define PL_64M          26
+#define PL_256M         28
+
+/*
+ * R4x00 interrupt enable / cause bits
+ */
+#define IE_SW0          (_ULCAST_(1) <<  8)
+#define IE_SW1          (_ULCAST_(1) <<  9)
+#define IE_IRQ0         (_ULCAST_(1) << 10)
+#define IE_IRQ1         (_ULCAST_(1) << 11)
+#define IE_IRQ2         (_ULCAST_(1) << 12)
+#define IE_IRQ3         (_ULCAST_(1) << 13)
+#define IE_IRQ4         (_ULCAST_(1) << 14)
+#define IE_IRQ5         (_ULCAST_(1) << 15)
+
+/*
+ * R4x00 interrupt cause bits
+ */
+#define C_SW0           (_ULCAST_(1) <<  8)
+#define C_SW1           (_ULCAST_(1) <<  9)
+#define C_IRQ0          (_ULCAST_(1) << 10)
+#define C_IRQ1          (_ULCAST_(1) << 11)
+#define C_IRQ2          (_ULCAST_(1) << 12)
+#define C_IRQ3          (_ULCAST_(1) << 13)
+#define C_IRQ4          (_ULCAST_(1) << 14)
+#define C_IRQ5          (_ULCAST_(1) << 15)
+
+/*
+ * Bitfields in the R4xx0 cp0 status register
+ */
+#define ST0_IE                  0x00000001
+#define ST0_EXL                 0x00000002
+#define ST0_ERL                 0x00000004
+#define ST0_KSU                 0x00000018
+#  define KSU_USER              0x00000010
+#  define KSU_SUPERVISOR        0x00000008
+#  define KSU_KERNEL            0x00000000
+#define ST0_UX                  0x00000020
+#define ST0_SX                  0x00000040
+#define ST0_KX                  0x00000080
+#define ST0_DE                  0x00010000
+#define ST0_CE                  0x00020000
+
+/*
+ * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
+ * cacheops in userspace.  This bit exists only on RM7000 and RM9000
+ * processors.
+ */
+#define ST0_CO                  0x08000000
+
+/*
+ * Bitfields in the R[23]000 cp0 status register.
+ */
+#define ST0_IEC                 0x00000001
+#define ST0_KUC                 0x00000002
+#define ST0_IEP                 0x00000004
+#define ST0_KUP                 0x00000008
+#define ST0_IEO                 0x00000010
+#define ST0_KUO                 0x00000020
+/* bits 6 & 7 are reserved on R[23]000 */
+#define ST0_ISC                 0x00010000
+#define ST0_SWC                 0x00020000
+#define ST0_CM                  0x00080000
+
+/*
+ * Bits specific to the R4640/R4650
+ */
+#define ST0_UM                  (_ULCAST_(1) <<  4)
+#define ST0_IL                  (_ULCAST_(1) << 23)
+#define ST0_DL                  (_ULCAST_(1) << 24)
+
+/*
+ * Enable the MIPS MDMX and DSP ASEs
+ */
+#define ST0_MX                  0x01000000
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT     19
+#define TX39_CONF_ICS_MASK      0x00380000
+#define TX39_CONF_ICS_1KB       0x00000000
+#define TX39_CONF_ICS_2KB       0x00080000
+#define TX39_CONF_ICS_4KB       0x00100000
+#define TX39_CONF_ICS_8KB       0x00180000
+#define TX39_CONF_ICS_16KB      0x00200000
+
+#define TX39_CONF_DCS_SHIFT     16
+#define TX39_CONF_DCS_MASK      0x00070000
+#define TX39_CONF_DCS_1KB       0x00000000
+#define TX39_CONF_DCS_2KB       0x00010000
+#define TX39_CONF_DCS_4KB       0x00020000
+#define TX39_CONF_DCS_8KB       0x00030000
+#define TX39_CONF_DCS_16KB      0x00040000
+
+#define TX39_CONF_CWFON         0x00004000
+#define TX39_CONF_WBON          0x00002000
+#define TX39_CONF_RF_SHIFT      10
+#define TX39_CONF_RF_MASK       0x00000c00
+#define TX39_CONF_DOZE          0x00000200
+#define TX39_CONF_HALT          0x00000100
+#define TX39_CONF_LOCK          0x00000080
+#define TX39_CONF_ICE           0x00000020
+#define TX39_CONF_DCE           0x00000010
+#define TX39_CONF_IRSIZE_SHIFT  2
+#define TX39_CONF_IRSIZE_MASK   0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT  0
+#define TX39_CONF_DRSIZE_MASK   0x00000003
+
+/*
+ * Status register bits available in all MIPS CPUs.
+ */
+#define ST0_IM                  0x0000ff00
+#define  STATUSB_IP0            8
+#define  STATUSF_IP0            (_ULCAST_(1) <<  8)
+#define  STATUSB_IP1            9
+#define  STATUSF_IP1            (_ULCAST_(1) <<  9)
+#define  STATUSB_IP2            10
+#define  STATUSF_IP2            (_ULCAST_(1) << 10)
+#define  STATUSB_IP3            11
+#define  STATUSF_IP3            (_ULCAST_(1) << 11)
+#define  STATUSB_IP4            12
+#define  STATUSF_IP4            (_ULCAST_(1) << 12)
+#define  STATUSB_IP5            13
+#define  STATUSF_IP5            (_ULCAST_(1) << 13)
+#define  STATUSB_IP6            14
+#define  STATUSF_IP6            (_ULCAST_(1) << 14)
+#define  STATUSB_IP7            15
+#define  STATUSF_IP7            (_ULCAST_(1) << 15)
+#define  STATUSB_IP8            0
+#define  STATUSF_IP8            (_ULCAST_(1) <<  0)
+#define  STATUSB_IP9            1
+#define  STATUSF_IP9            (_ULCAST_(1) <<  1)
+#define  STATUSB_IP10           2
+#define  STATUSF_IP10           (_ULCAST_(1) <<  2)
+#define  STATUSB_IP11           3
+#define  STATUSF_IP11           (_ULCAST_(1) <<  3)
+#define  STATUSB_IP12           4
+#define  STATUSF_IP12           (_ULCAST_(1) <<  4)
+#define  STATUSB_IP13           5
+#define  STATUSF_IP13           (_ULCAST_(1) <<  5)
+#define  STATUSB_IP14           6
+#define  STATUSF_IP14           (_ULCAST_(1) <<  6)
+#define  STATUSB_IP15           7
+#define  STATUSF_IP15           (_ULCAST_(1) <<  7)
+#define ST0_CH                  0x00040000
+#define ST0_SR                  0x00100000
+#define ST0_TS                  0x00200000
+#define ST0_BEV                 0x00400000
+#define ST0_RE                  0x02000000
+#define ST0_FR                  0x04000000
+#define ST0_CU                  0xf0000000
+#define ST0_CU0                 0x10000000
+#define ST0_CU1                 0x20000000
+#define ST0_CU2                 0x40000000
+#define ST0_CU3                 0x80000000
+#define ST0_XX                  0x80000000      /* MIPS IV naming */
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 cause register.
+ *
+ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
+ */
+#define  CAUSEB_EXCCODE         2
+#define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
+#define  CAUSEB_IP              8
+#define  CAUSEF_IP              (_ULCAST_(255) <<  8)
+#define  CAUSEB_IP0             8
+#define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
+#define  CAUSEB_IP1             9
+#define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
+#define  CAUSEB_IP2             10
+#define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
+#define  CAUSEB_IP3             11
+#define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
+#define  CAUSEB_IP4             12
+#define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
+#define  CAUSEB_IP5             13
+#define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
+#define  CAUSEB_IP6             14
+#define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
+#define  CAUSEB_IP7             15
+#define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
+#define  CAUSEB_IV              23
+#define  CAUSEF_IV              (_ULCAST_(1)   << 23)
+#define  CAUSEB_CE              28
+#define  CAUSEF_CE              (_ULCAST_(3)   << 28)
+#define  CAUSEB_BD              31
+#define  CAUSEF_BD              (_ULCAST_(1)   << 31)
+
+/*
+ * Bits in the coprocessor 0 config register.
+ */
+/* Generic bits.  */
+#define CONF_CM_CACHABLE_NO_WA          0
+#define CONF_CM_CACHABLE_WA             1
+#define CONF_CM_UNCACHED                2
+#define CONF_CM_CACHABLE_NONCOHERENT    3
+#define CONF_CM_CACHABLE_CE             4
+#define CONF_CM_CACHABLE_COW            5
+#define CONF_CM_CACHABLE_CUW            6
+#define CONF_CM_CACHABLE_ACCELERATED    7
+#define CONF_CM_CMASK                   7
+#define CONF_BE                 (_ULCAST_(1) << 15)
+
+/* Bits common to various processors.  */
+#define CONF_CU                 (_ULCAST_(1) <<  3)
+#define CONF_DB                 (_ULCAST_(1) <<  4)
+#define CONF_IB                 (_ULCAST_(1) <<  5)
+#define CONF_DC                 (_ULCAST_(7) <<  6)
+#define CONF_IC                 (_ULCAST_(7) <<  9)
+#define CONF_EB                 (_ULCAST_(1) << 13)
+#define CONF_EM                 (_ULCAST_(1) << 14)
+#define CONF_SM                 (_ULCAST_(1) << 16)
+#define CONF_SC                 (_ULCAST_(1) << 17)
+#define CONF_EW                 (_ULCAST_(3) << 18)
+#define CONF_EP                 (_ULCAST_(15)<< 24)
+#define CONF_EC                 (_ULCAST_(7) << 28)
+#define CONF_CM                 (_ULCAST_(1) << 31)
+
+/* Bits specific to the R4xx0.  */
+#define R4K_CONF_SW             (_ULCAST_(1) << 20)
+#define R4K_CONF_SS             (_ULCAST_(1) << 21)
+#define R4K_CONF_SB             (_ULCAST_(3) << 22)
+
+/* Bits specific to the R5000.  */
+#define R5K_CONF_SE             (_ULCAST_(1) << 12)
+#define R5K_CONF_SS             (_ULCAST_(3) << 20)
+
+/* Bits specific to the RM7000.  */
+#define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
+#define RM7K_CONF_TE            (_ULCAST_(1) << 12)
+#define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
+#define RM7K_CONF_TC            (_ULCAST_(1) << 17)
+#define RM7K_CONF_SI            (_ULCAST_(3) << 20)
+#define RM7K_CONF_SC            (_ULCAST_(1) << 31)
+
+/* Bits specific to the R10000.  */
+#define R10K_CONF_DN            (_ULCAST_(3) <<  3)
+#define R10K_CONF_CT            (_ULCAST_(1) <<  5)
+#define R10K_CONF_PE            (_ULCAST_(1) <<  6)
+#define R10K_CONF_PM            (_ULCAST_(3) <<  7)
+#define R10K_CONF_EC            (_ULCAST_(15)<<  9)
+#define R10K_CONF_SB            (_ULCAST_(1) << 13)
+#define R10K_CONF_SK            (_ULCAST_(1) << 14)
+#define R10K_CONF_SS            (_ULCAST_(7) << 16)
+#define R10K_CONF_SC            (_ULCAST_(7) << 19)
+#define R10K_CONF_DC            (_ULCAST_(7) << 26)
+#define R10K_CONF_IC            (_ULCAST_(7) << 29)
+
+/* Bits specific to the VR41xx.  */
+#define VR41_CONF_CS            (_ULCAST_(1) << 12)
+#define VR41_CONF_P4K           (_ULCAST_(1) << 13)
+#define VR41_CONF_BP            (_ULCAST_(1) << 16)
+#define VR41_CONF_M16           (_ULCAST_(1) << 20)
+#define VR41_CONF_AD            (_ULCAST_(1) << 23)
+
+/* Bits specific to the R30xx.  */
+#define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
+#define R30XX_CONF_REV          (_ULCAST_(1) << 22)
+#define R30XX_CONF_AC           (_ULCAST_(1) << 23)
+#define R30XX_CONF_RF           (_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
+#define R30XX_CONF_SB           (_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
+
+/* Bits specific to the TX49.  */
+#define TX49_CONF_DC            (_ULCAST_(1) << 16)
+#define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
+#define TX49_CONF_HALT          (_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
+
+/* Bits specific to the MIPS32/64 PRA.  */
+#define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
+#define MIPS_CONF_AR            (_ULCAST_(7) << 10)
+#define MIPS_CONF_AT            (_ULCAST_(3) << 13)
+#define MIPS_CONF_M             (_ULCAST_(1) << 31)
+
+/*
+ * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
+ */
+#define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
+#define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
+#define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
+#define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
+#define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
+#define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
+#define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
+#define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
+#define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
+
+#define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
+#define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
+#define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
+#define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
+#define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
+#define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
+#define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
+#define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
+
+#define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
+#define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
+#define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
+#define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
+#define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
+#define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
+#define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
+#define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
+#define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
+
+#define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
+
+#define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
+
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S             (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D             (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W             (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L             (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Functions to access the R10000 performance counters.  These are basically
+ * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
+ * performance counter number encoded into bits 1 ... 5 of the instruction.
+ * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
+ * disassembler these will look like an access to sel 0 or 1.
+ */
+#define read_r10k_perf_cntr(counter)                            \
+({                                                              \
+        unsigned int __res;                                     \
+        __asm__ __volatile__(                                   \
+        "mfpc\t%0, %1"                                          \
+        : "=r" (__res)                                          \
+        : "i" (counter));                                       \
+                                                                \
+        __res;                                                  \
+})
+
+#define write_r10k_perf_cntr(counter,val)                       \
+do {                                                            \
+        __asm__ __volatile__(                                   \
+        "mtpc\t%0, %1"                                          \
+        :                                                       \
+        : "r" (val), "i" (counter));                            \
+} while (0)
+
+#define read_r10k_perf_event(counter)                           \
+({                                                              \
+        unsigned int __res;                                     \
+        __asm__ __volatile__(                                   \
+        "mfps\t%0, %1"                                          \
+        : "=r" (__res)                                          \
+        : "i" (counter));                                       \
+                                                                \
+        __res;                                                  \
+})
+
+#define write_r10k_perf_cntl(counter,val)                       \
+do {                                                            \
+        __asm__ __volatile__(                                   \
+        "mtps\t%0, %1"                                          \
+        :                                                       \
+        : "r" (val), "i" (counter));                            \
+} while (0)
+
+
+/*
+ * Macros to access the system control coprocessor
+ */
+
+#define __read_32bit_c0_register(source, sel)                           \
+({ int __res;                                                           \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        "mfc0\t%0, " #source "\n\t"                     \
+                        : "=r" (__res));                                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips32\n\t"                              \
+                        "mfc0\t%0, " #source ", " #sel "\n\t"           \
+                        ".set\tmips0\n\t"                               \
+                        : "=r" (__res));                                \
+        __res;                                                          \
+})
+
+#define __read_64bit_c0_register(source, sel)                           \
+({ unsigned long long __res;                                            \
+        if (sizeof(unsigned long) == 4)                                 \
+                __res = __read_64bit_c0_split(source, sel);             \
+        else if (sel == 0)                                              \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips3\n\t"                               \
+                        "dmfc0\t%0, " #source "\n\t"                    \
+                        ".set\tmips0"                                   \
+                        : "=r" (__res));                                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc0\t%0, " #source ", " #sel "\n\t"          \
+                        ".set\tmips0"                                   \
+                        : "=r" (__res));                                \
+        __res;                                                          \
+})
+
+#define __write_32bit_c0_register(register, sel, value)                 \
+do {                                                                    \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        "mtc0\t%z0, " #register "\n\t"                  \
+                        : : "Jr" ((unsigned int)(value)));              \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips32\n\t"                              \
+                        "mtc0\t%z0, " #register ", " #sel "\n\t"        \
+                        ".set\tmips0"                                   \
+                        : : "Jr" ((unsigned int)(value)));              \
+} while (0)
+
+#define __write_64bit_c0_register(register, sel, value)                 \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4)                                 \
+                __write_64bit_c0_split(register, sel, value);           \
+        else if (sel == 0)                                              \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips3\n\t"                               \
+                        "dmtc0\t%z0, " #register "\n\t"                 \
+                        ".set\tmips0"                                   \
+                        : : "Jr" (value));                              \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
+                        ".set\tmips0"                                   \
+                        : : "Jr" (value));                              \
+} while (0)
+
+#define __read_ulong_c0_register(reg, sel)                              \
+        ((sizeof(unsigned long) == 4) ?                                 \
+        (unsigned long) __read_32bit_c0_register(reg, sel) :            \
+        (unsigned long) __read_64bit_c0_register(reg, sel))
+
+#define __write_ulong_c0_register(reg, sel, val)                        \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4)                                 \
+                __write_32bit_c0_register(reg, sel, val);               \
+        else                                                            \
+                __write_64bit_c0_register(reg, sel, val);               \
+} while (0)
+
+/*
+ * On RM7000/RM9000 these are uses to access cop0 set 1 registers
+ */
+#define __read_32bit_c0_ctrl_register(source)                           \
+({ int __res;                                                           \
+        __asm__ __volatile__(                                           \
+                "cfc0\t%0, " #source "\n\t"                             \
+                : "=r" (__res));                                        \
+        __res;                                                          \
+})
+
+#define __write_32bit_c0_ctrl_register(register, value)                 \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+                "ctc0\t%z0, " #register "\n\t"                          \
+                : : "Jr" ((unsigned int)(value)));                      \
+} while (0)
+
+/*
+ * These versions are only needed for systems with more than 38 bits of
+ * physical address space running the 32-bit kernel.  That's none atm :-)
+ */
+#define __read_64bit_c0_split(source, sel)                              \
+({                                                                      \
+        unsigned long long __val;                                       \
+        unsigned long __flags;                                          \
+                                                                        \
+        local_irq_save(__flags);                                        \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc0\t%M0, " #source "\n\t"                   \
+                        "dsll\t%L0, %M0, 32\n\t"                        \
+                        "dsrl\t%M0, %M0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        ".set\tmips0"                                   \
+                        : "=r" (__val));                                \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
+                        "dsll\t%L0, %M0, 32\n\t"                        \
+                        "dsrl\t%M0, %M0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        ".set\tmips0"                                   \
+                        : "=r" (__val));                                \
+        local_irq_restore(__flags);                                     \
+                                                                        \
+        __val;                                                          \
+})
+
+#define __write_64bit_c0_split(source, sel, val)                        \
+do {                                                                    \
+        unsigned long __flags;                                          \
+                                                                        \
+        local_irq_save(__flags);                                        \
+        if (sel == 0)                                                   \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc0\t%L0, " #source "\n\t"                   \
+                        ".set\tmips0"                                   \
+                        : : "r" (val));                                 \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
+                        ".set\tmips0"                                   \
+                        : : "r" (val));                                 \
+        local_irq_restore(__flags);                                     \
+} while (0)
+
+#define read_c0_index()         __read_32bit_c0_register($0, 0)
+#define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
+
+#define read_c0_random()        __read_32bit_c0_register($1, 0)
+#define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
+
+#define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
+
+#define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
+
+#define read_c0_conf()          __read_32bit_c0_register($3, 0)
+#define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
+
+#define read_c0_context()       __read_ulong_c0_register($4, 0)
+#define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
+
+#define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
+
+#define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
+
+#define read_c0_wired()         __read_32bit_c0_register($6, 0)
+#define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
+
+#define read_c0_info()          __read_32bit_c0_register($7, 0)
+
+#define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
+#define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
+#define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
+
+#define read_c0_count()         __read_32bit_c0_register($9, 0)
+#define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
+
+#define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
+#define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
+
+#define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
+#define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
+
+#define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
+
+#define read_c0_compare()       __read_32bit_c0_register($11, 0)
+#define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
+
+#define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
+#define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
+
+#define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
+#define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
+
+#define read_c0_status()        __read_32bit_c0_register($12, 0)
+#ifdef CONFIG_MIPS_MT_SMTC
+#define write_c0_status(val)                                            \
+do {                                                                    \
+        __write_32bit_c0_register($12, 0, val);                         \
+        __ehb();                                                        \
+} while (0)
+#else
+/*
+ * Legacy non-SMTC code, which may be hazardous
+ * but which might not support EHB
+ */
+#define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+#define read_c0_cause()         __read_32bit_c0_register($13, 0)
+#define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
+
+#define read_c0_epc()           __read_ulong_c0_register($14, 0)
+#define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
+
+#define read_c0_prid()          __read_32bit_c0_register($15, 0)
+
+#define read_c0_config()        __read_32bit_c0_register($16, 0)
+#define read_c0_config1()       __read_32bit_c0_register($16, 1)
+#define read_c0_config2()       __read_32bit_c0_register($16, 2)
+#define read_c0_config3()       __read_32bit_c0_register($16, 3)
+#define read_c0_config4()       __read_32bit_c0_register($16, 4)
+#define read_c0_config5()       __read_32bit_c0_register($16, 5)
+#define read_c0_config6()       __read_32bit_c0_register($16, 6)
+#define read_c0_config7()       __read_32bit_c0_register($16, 7)
+#define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
+#define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
+#define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
+#define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
+#define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
+
+/*
+ * The WatchLo register.  There may be upto 8 of them.
+ */
+#define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
+#define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
+#define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
+#define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
+#define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
+#define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
+#define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
+#define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
+#define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
+#define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
+#define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
+#define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
+#define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
+#define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
+#define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
+#define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
+
+/*
+ * The WatchHi register.  There may be upto 8 of them.
+ */
+#define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
+#define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
+#define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
+#define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
+#define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
+#define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
+#define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
+#define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
+
+#define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
+#define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
+#define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
+#define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
+#define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
+#define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
+#define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
+#define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
+
+#define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
+
+#define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
+#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
+
+#define read_c0_framemask()     __read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
+
+/* RM9000 PerfControl performance counter control register */
+#define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
+#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_diag()          __read_32bit_c0_register($22, 0)
+#define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_diag1()         __read_32bit_c0_register($22, 1)
+#define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_diag2()         __read_32bit_c0_register($22, 2)
+#define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_diag3()         __read_32bit_c0_register($22, 3)
+#define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_diag4()         __read_32bit_c0_register($22, 4)
+#define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_diag5()         __read_32bit_c0_register($22, 5)
+#define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_debug()         __read_32bit_c0_register($23, 0)
+#define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
+
+#define read_c0_depc()          __read_ulong_c0_register($24, 0)
+#define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
+
+/*
+ * MIPS32 / MIPS64 performance counters
+ */
+#define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
+#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
+#define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
+#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
+#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
+#define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
+#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
+#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
+#define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
+#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
+#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
+#define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
+#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
+
+/* RM9000 PerfCount performance counter register */
+#define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
+#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
+
+#define read_c0_ecc()           __read_32bit_c0_register($26, 0)
+#define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
+
+#define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+
+#define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
+
+#define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+
+#define read_c0_taglo()         __read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
+
+#define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
+#define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
+
+#define read_c0_taghi()         __read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
+
+#define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
+
+/* MIPSR2 */
+#define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
+#define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
+
+#define read_c0_intctl()        __read_32bit_c0_register($12, 1)
+#define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
+
+#define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
+#define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
+
+#define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
+#define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
+
+#define read_c0_ebase()         __read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define read_32bit_cp1_register(source)                         \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+        ".set\tpush\n\t"                                        \
+        ".set\treorder\n\t"                                     \
+        "cfc1\t%0,"STR(source)"\n\t"                            \
+        ".set\tpop"                                             \
+        : "=r" (__res));                                        \
+        __res;})
+
+#define rddsp(mask)                                                     \
+({                                                                      \
+        unsigned int __res;                                             \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                            \n"             \
+        "       .set    noat                            \n"             \
+        "       # rddsp $1, %x1                         \n"             \
+        "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
+        "       move    %0, $1                          \n"             \
+        "       .set    pop                             \n"             \
+        : "=r" (__res)                                                  \
+        : "i" (mask));                                                  \
+        __res;                                                          \
+})
+
+#define wrdsp(val, mask)                                                \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # wrdsp $1, %x1                                 \n"     \
+        "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (val), "i" (mask));                                       \
+} while (0)
+
+#if 0   /* Need DSP ASE capable assembler ... */
+#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
+#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
+#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
+#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
+
+#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
+#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
+#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
+#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
+
+#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
+#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
+#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
+#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
+
+#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
+#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
+#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
+#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
+
+#else
+
+#define mfhi0()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac0                \n"                     \
+        "       .word   0x00000810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mfhi1()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac1                \n"                     \
+        "       .word   0x00200810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mfhi2()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac2                \n"                     \
+        "       .word   0x00400810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mfhi3()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mfhi  %0, $ac3                \n"                     \
+        "       .word   0x00600810              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mflo0()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac0                \n"                     \
+        "       .word   0x00000812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mflo1()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac1                \n"                     \
+        "       .word   0x00200812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mflo2()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac2                \n"                     \
+        "       .word   0x00400812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mflo3()                                                         \
+({                                                                      \
+        unsigned long __treg;                                           \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    push                    \n"                     \
+        "       .set    noat                    \n"                     \
+        "       # mflo  %0, $ac3                \n"                     \
+        "       .word   0x00600812              \n"                     \
+        "       move    %0, $1                  \n"                     \
+        "       .set    pop                     \n"                     \
+        : "=r" (__treg));                                               \
+        __treg;                                                         \
+})
+
+#define mthi0(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac0                                \n"     \
+        "       .word   0x00200011                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mthi1(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac1                                \n"     \
+        "       .word   0x00200811                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mthi2(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac2                                \n"     \
+        "       .word   0x00201011                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mthi3(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mthi  $1, $ac3                                \n"     \
+        "       .word   0x00201811                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mtlo0(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac0                                \n"     \
+        "       .word   0x00200013                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mtlo1(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac1                                \n"     \
+        "       .word   0x00200813                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mtlo2(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac2                                \n"     \
+        "       .word   0x00201013                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#define mtlo3(x)                                                        \
+do {                                                                    \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noat                                    \n"     \
+        "       move    $1, %0                                  \n"     \
+        "       # mtlo  $1, $ac3                                \n"     \
+        "       .word   0x00201813                              \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+} while (0)
+
+#endif
+
+/*
+ * TLB operations.
+ *
+ * It is responsibility of the caller to take care of any TLB hazards.
+ */
+static inline void tlb_probe(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbp\n\t"
+                ".set reorder");
+}
+
+static inline void tlb_read(void)
+{
+#if MIPS34K_MISSED_ITLB_WAR
+        int res = 0;
+
+        __asm__ __volatile__(
+        "       .set    push                                    \n"
+        "       .set    noreorder                               \n"
+        "       .set    noat                                    \n"
+        "       .set    mips32r2                                \n"
+        "       .word   0x41610001              # dvpe $1       \n"
+        "       move    %0, $1                                  \n"
+        "       ehb                                             \n"
+        "       .set    pop                                     \n"
+        : "=r" (res));
+
+        instruction_hazard();
+#endif
+
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbr\n\t"
+                ".set reorder");
+
+#if MIPS34K_MISSED_ITLB_WAR
+        if ((res & _ULCAST_(1)))
+                __asm__ __volatile__(
+                "       .set    push                            \n"
+                "       .set    noreorder                       \n"
+                "       .set    noat                            \n"
+                "       .set    mips32r2                        \n"
+                "       .word   0x41600021      # evpe          \n"
+                "       ehb                                     \n"
+                "       .set    pop                             \n");
+#endif
+}
+
+static inline void tlb_write_indexed(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbwi\n\t"
+                ".set reorder");
+}
+
+static inline void tlb_write_random(void)
+{
+        __asm__ __volatile__(
+                ".set noreorder\n\t"
+                "tlbwr\n\t"
+                ".set reorder");
+}
+
+/*
+ * Manipulate bits in a c0 register.
+ */
+#ifndef CONFIG_MIPS_MT_SMTC
+/*
+ * SMTC Linux requires shutting-down microthread scheduling
+ * during CP0 register read-modify-write sequences.
+ */
+#define __BUILD_SET_C0(name)                                    \
+static inline unsigned int                                      \
+set_c0_##name(unsigned int set)                                 \
+{                                                               \
+        unsigned int res;                                       \
+                                                                \
+        res = read_c0_##name();                                 \
+        res |= set;                                             \
+        write_c0_##name(res);                                   \
+                                                                \
+        return res;                                             \
+}                                                               \
+                                                                \
+static inline unsigned int                                      \
+clear_c0_##name(unsigned int clear)                             \
+{                                                               \
+        unsigned int res;                                       \
+                                                                \
+        res = read_c0_##name();                                 \
+        res &= ~clear;                                          \
+        write_c0_##name(res);                                   \
+                                                                \
+        return res;                                             \
+}                                                               \
+                                                                \
+static inline unsigned int                                      \
+change_c0_##name(unsigned int change, unsigned int new)         \
+{                                                               \
+        unsigned int res;                                       \
+                                                                \
+        res = read_c0_##name();                                 \
+        res &= ~change;                                         \
+        res |= (new & change);                                  \
+        write_c0_##name(res);                                   \
+                                                                \
+        return res;                                             \
+}
+
+#else /* SMTC versions that manage MT scheduling */
+
+#include <linux/irqflags.h>
+
+/*
+ * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
+ * header file recursion.
+ */
+static inline unsigned int __dmt(void)
+{
+        int res;
+
+        __asm__ __volatile__(
+        "       .set    push                                            \n"
+        "       .set    mips32r2                                        \n"
+        "       .set    noat                                            \n"
+        "       .word   0x41610BC1                      # dmt $1        \n"
+        "       ehb                                                     \n"
+        "       move    %0, $1                                          \n"
+        "       .set    pop                                             \n"
+        : "=r" (res));
+
+        instruction_hazard();
+
+        return res;
+}
+
+#define __VPECONTROL_TE_SHIFT   15
+#define __VPECONTROL_TE         (1UL << __VPECONTROL_TE_SHIFT)
+
+#define __EMT_ENABLE            __VPECONTROL_TE
+
+static inline void __emt(unsigned int previous)
+{
+        if ((previous & __EMT_ENABLE))
+                __asm__ __volatile__(
+                "       .set    mips32r2                                \n"
+                "       .word   0x41600be1              # emt           \n"
+                "       ehb                                             \n"
+                "       .set    mips0                                   \n");
+}
+
+static inline void __ehb(void)
+{
+        __asm__ __volatile__(
+        "       .set    mips32r2                                        \n"
+        "       ehb                                                     \n"             "       .set    mips0                                           \n");
+}
+
+/*
+ * Note that local_irq_save/restore affect TC-specific IXMT state,
+ * not Status.IE as in non-SMTC kernel.
+ */
+
+#define __BUILD_SET_C0(name)                                    \
+static inline unsigned int                                      \
+set_c0_##name(unsigned int set)                                 \
+{                                                               \
+        unsigned int res;                                       \
+        unsigned int omt;                                       \
+        unsigned long flags;                                    \
+                                                                \
+        local_irq_save(flags);                                  \
+        omt = __dmt();                                          \
+        res = read_c0_##name();                                 \
+        res |= set;                                             \
+        write_c0_##name(res);                                   \
+        __emt(omt);                                             \
+        local_irq_restore(flags);                               \
+                                                                \
+        return res;                                             \
+}                                                               \
+                                                                \
+static inline unsigned int                                      \
+clear_c0_##name(unsigned int clear)                             \
+{                                                               \
+        unsigned int res;                                       \
+        unsigned int omt;                                       \
+        unsigned long flags;                                    \
+                                                                \
+        local_irq_save(flags);                                  \
+        omt = __dmt();                                          \
+        res = read_c0_##name();                                 \
+        res &= ~clear;                                          \
+        write_c0_##name(res);                                   \
+        __emt(omt);                                             \
+        local_irq_restore(flags);                               \
+                                                                \
+        return res;                                             \
+}                                                               \
+                                                                \
+static inline unsigned int                                      \
+change_c0_##name(unsigned int change, unsigned int new)         \
+{                                                               \
+        unsigned int res;                                       \
+        unsigned int omt;                                       \
+        unsigned long flags;                                    \
+                                                                \
+        local_irq_save(flags);                                  \
+                                                                \
+        omt = __dmt();                                          \
+        res = read_c0_##name();                                 \
+        res &= ~change;                                         \
+        res |= (new & change);                                  \
+        write_c0_##name(res);                                   \
+        __emt(omt);                                             \
+        local_irq_restore(flags);                               \
+                                                                \
+        return res;                                             \
+}
+#endif
+
+__BUILD_SET_C0(status)
+__BUILD_SET_C0(cause)
+__BUILD_SET_C0(config)
+__BUILD_SET_C0(intcontrol)
+__BUILD_SET_C0(intctl)
+__BUILD_SET_C0(srsmap)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_MIPSREGS_H */
diff --git a/arch/mips/include/asm/mman.h b/arch/mips/include/asm/mman.h
new file mode 100644
index 000000000000..e4d6f1fb1cf7
--- /dev/null
+++ b/arch/mips/include/asm/mman.h
@@ -0,0 +1,77 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2002 by Ralf Baechle
+ */
+#ifndef _ASM_MMAN_H
+#define _ASM_MMAN_H
+
+/*
+ * Protections are chosen from these bits, OR'd together.  The
+ * implementation does not necessarily support PROT_EXEC or PROT_WRITE
+ * without PROT_READ.  The only guarantees are that no writing will be
+ * allowed without PROT_WRITE and no access will be allowed for PROT_NONE.
+ */
+#define PROT_NONE       0x00            /* page can not be accessed */
+#define PROT_READ       0x01            /* page can be read */
+#define PROT_WRITE      0x02            /* page can be written */
+#define PROT_EXEC       0x04            /* page can be executed */
+/*                      0x08               reserved for PROT_EXEC_NOFLUSH */
+#define PROT_SEM        0x10            /* page may be used for atomic ops */
+#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
+#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
+
+/*
+ * Flags for mmap
+ */
+#define MAP_SHARED      0x001           /* Share changes */
+#define MAP_PRIVATE     0x002           /* Changes are private */
+#define MAP_TYPE        0x00f           /* Mask for type of mapping */
+#define MAP_FIXED       0x010           /* Interpret addr exactly */
+
+/* not used by linux, but here to make sure we don't clash with ABI defines */
+#define MAP_RENAME      0x020           /* Assign page to file */
+#define MAP_AUTOGROW    0x040           /* File may grow by writing */
+#define MAP_LOCAL       0x080           /* Copy on fork/sproc */
+#define MAP_AUTORSRV    0x100           /* Logical swap reserved on demand */
+
+/* These are linux-specific */
+#define MAP_NORESERVE   0x0400          /* don't check for reservations */
+#define MAP_ANONYMOUS   0x0800          /* don't use a file */
+#define MAP_GROWSDOWN   0x1000          /* stack-like segment */
+#define MAP_DENYWRITE   0x2000          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x4000          /* mark it as an executable */
+#define MAP_LOCKED      0x8000          /* pages are locked */
+#define MAP_POPULATE    0x10000         /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x20000         /* do not block on IO */
+
+/*
+ * Flags for msync
+ */
+#define MS_ASYNC        0x0001          /* sync memory asynchronously */
+#define MS_INVALIDATE   0x0002          /* invalidate mappings & caches */
+#define MS_SYNC         0x0004          /* synchronous memory sync */
+
+/*
+ * Flags for mlockall
+ */
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+
+#define MADV_NORMAL     0               /* no further special treatment */
+#define MADV_RANDOM     1               /* expect random page references */
+#define MADV_SEQUENTIAL 2               /* expect sequential page references */
+#define MADV_WILLNEED   3               /* will need these pages */
+#define MADV_DONTNEED   4               /* don't need these pages */
+
+/* common parameters: try to keep these consistent across architectures */
+#define MADV_REMOVE     9               /* remove these pages & resources */
+#define MADV_DONTFORK   10              /* don't inherit across fork */
+#define MADV_DOFORK     11              /* do inherit across fork */
+
+/* compatibility flags */
+#define MAP_FILE        0
+
+#endif /* _ASM_MMAN_H */
diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h
new file mode 100644
index 000000000000..4063edd79623
--- /dev/null
+++ b/arch/mips/include/asm/mmu.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_MMU_H
+#define __ASM_MMU_H
+
+typedef unsigned long mm_context_t[NR_CPUS];
+
+#endif /* __ASM_MMU_H */
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
new file mode 100644
index 000000000000..d7f3eb03ad12
--- /dev/null
+++ b/arch/mips/include/asm/mmu_context.h
@@ -0,0 +1,297 @@
+/*
+ * Switch a MMU context.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MMU_CONTEXT_H
+#define _ASM_MMU_CONTEXT_H
+
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#ifdef CONFIG_MIPS_MT_SMTC
+#include <asm/mipsmtregs.h>
+#include <asm/smtc.h>
+#endif /* SMTC */
+#include <asm-generic/mm_hooks.h>
+
+/*
+ * For the fast tlb miss handlers, we keep a per cpu array of pointers
+ * to the current pgd for each processor. Also, the proc. id is stuffed
+ * into the context register.
+ */
+extern unsigned long pgd_current[];
+
+#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
+        pgd_current[smp_processor_id()] = (unsigned long)(pgd)
+
+#ifdef CONFIG_32BIT
+#define TLBMISS_HANDLER_SETUP()                                         \
+        write_c0_context((unsigned long) smp_processor_id() << 25);     \
+        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
+#endif
+#ifdef CONFIG_64BIT
+#define TLBMISS_HANDLER_SETUP()                                         \
+        write_c0_context((unsigned long) smp_processor_id() << 26);     \
+        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
+#endif
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+#define ASID_INC        0x40
+#define ASID_MASK       0xfc0
+
+#elif defined(CONFIG_CPU_R8000)
+
+#define ASID_INC        0x10
+#define ASID_MASK       0xff0
+
+#elif defined(CONFIG_CPU_RM9000)
+
+#define ASID_INC        0x1
+#define ASID_MASK       0xfff
+
+/* SMTC/34K debug hack - but maybe we'll keep it */
+#elif defined(CONFIG_MIPS_MT_SMTC)
+
+#define ASID_INC        0x1
+extern unsigned long smtc_asid_mask;
+#define ASID_MASK       (smtc_asid_mask)
+#define HW_ASID_MASK    0xff
+/* End SMTC/34K debug hack */
+#else /* FIXME: not correct for R6000 */
+
+#define ASID_INC        0x1
+#define ASID_MASK       0xff
+
+#endif
+
+#define cpu_context(cpu, mm)    ((mm)->context[cpu])
+#define cpu_asid(cpu, mm)       (cpu_context((cpu), (mm)) & ASID_MASK)
+#define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+/*
+ *  All unused by hardware upper bits will be considered
+ *  as a software asid extension.
+ */
+#define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
+#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
+
+#ifndef CONFIG_MIPS_MT_SMTC
+/* Normal, classic MIPS get_new_mmu_context */
+static inline void
+get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
+{
+        unsigned long asid = asid_cache(cpu);
+
+        if (! ((asid += ASID_INC) & ASID_MASK) ) {
+                if (cpu_has_vtag_icache)
+                        flush_icache_all();
+                local_flush_tlb_all();  /* start new asid cycle */
+                if (!asid)              /* fix version if needed */
+                        asid = ASID_FIRST_VERSION;
+        }
+        cpu_context(cpu, mm) = asid_cache(cpu) = asid;
+}
+
+#else /* CONFIG_MIPS_MT_SMTC */
+
+#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
+
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+/*
+ * Initialize the context related info for a new mm_struct
+ * instance.
+ */
+static inline int
+init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+        int i;
+
+        for_each_online_cpu(i)
+                cpu_context(i, mm) = 0;
+
+        return 0;
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        unsigned int cpu = smp_processor_id();
+        unsigned long flags;
+#ifdef CONFIG_MIPS_MT_SMTC
+        unsigned long oldasid;
+        unsigned long mtflags;
+        int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
+        local_irq_save(flags);
+        mtflags = dvpe();
+#else /* Not SMTC */
+        local_irq_save(flags);
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+        /* Check if our ASID is of an older version and thus invalid */
+        if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
+                get_new_mmu_context(next, cpu);
+#ifdef CONFIG_MIPS_MT_SMTC
+        /*
+         * If the EntryHi ASID being replaced happens to be
+         * the value flagged at ASID recycling time as having
+         * an extended life, clear the bit showing it being
+         * in use by this "CPU", and if that's the last bit,
+         * free up the ASID value for use and flush any old
+         * instances of it from the TLB.
+         */
+        oldasid = (read_c0_entryhi() & ASID_MASK);
+        if(smtc_live_asid[mytlb][oldasid]) {
+                smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
+                if(smtc_live_asid[mytlb][oldasid] == 0)
+                        smtc_flush_tlb_asid(oldasid);
+        }
+        /*
+         * Tread softly on EntryHi, and so long as we support
+         * having ASID_MASK smaller than the hardware maximum,
+         * make sure no "soft" bits become "hard"...
+         */
+        write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
+                        | (cpu_context(cpu, next) & ASID_MASK));
+        ehb(); /* Make sure it propagates to TCStatus */
+        evpe(mtflags);
+#else
+        write_c0_entryhi(cpu_context(cpu, next));
+#endif /* CONFIG_MIPS_MT_SMTC */
+        TLBMISS_HANDLER_SETUP_PGD(next->pgd);
+
+        /*
+         * Mark current->active_mm as not "active" anymore.
+         * We don't want to mislead possible IPI tlb flush routines.
+         */
+        cpu_clear(cpu, prev->cpu_vm_mask);
+        cpu_set(cpu, next->cpu_vm_mask);
+
+        local_irq_restore(flags);
+}
+
+/*
+ * Destroy context related info for an mm_struct that is about
+ * to be put to rest.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+}
+
+#define deactivate_mm(tsk, mm)  do { } while (0)
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+static inline void
+activate_mm(struct mm_struct *prev, struct mm_struct *next)
+{
+        unsigned long flags;
+        unsigned int cpu = smp_processor_id();
+
+#ifdef CONFIG_MIPS_MT_SMTC
+        unsigned long oldasid;
+        unsigned long mtflags;
+        int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+        local_irq_save(flags);
+
+        /* Unconditionally get a new ASID.  */
+        get_new_mmu_context(next, cpu);
+
+#ifdef CONFIG_MIPS_MT_SMTC
+        /* See comments for similar code above */
+        mtflags = dvpe();
+        oldasid = read_c0_entryhi() & ASID_MASK;
+        if(smtc_live_asid[mytlb][oldasid]) {
+                smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
+                if(smtc_live_asid[mytlb][oldasid] == 0)
+                         smtc_flush_tlb_asid(oldasid);
+        }
+        /* See comments for similar code above */
+        write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
+                         (cpu_context(cpu, next) & ASID_MASK));
+        ehb(); /* Make sure it propagates to TCStatus */
+        evpe(mtflags);
+#else
+        write_c0_entryhi(cpu_context(cpu, next));
+#endif /* CONFIG_MIPS_MT_SMTC */
+        TLBMISS_HANDLER_SETUP_PGD(next->pgd);
+
+        /* mark mmu ownership change */
+        cpu_clear(cpu, prev->cpu_vm_mask);
+        cpu_set(cpu, next->cpu_vm_mask);
+
+        local_irq_restore(flags);
+}
+
+/*
+ * If mm is currently active_mm, we can't really drop it.  Instead,
+ * we will get a new one for it.
+ */
+static inline void
+drop_mmu_context(struct mm_struct *mm, unsigned cpu)
+{
+        unsigned long flags;
+#ifdef CONFIG_MIPS_MT_SMTC
+        unsigned long oldasid;
+        /* Can't use spinlock because called from TLB flush within DVPE */
+        unsigned int prevvpe;
+        int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+        local_irq_save(flags);
+
+        if (cpu_isset(cpu, mm->cpu_vm_mask))  {
+                get_new_mmu_context(mm, cpu);
+#ifdef CONFIG_MIPS_MT_SMTC
+                /* See comments for similar code above */
+                prevvpe = dvpe();
+                oldasid = (read_c0_entryhi() & ASID_MASK);
+                if (smtc_live_asid[mytlb][oldasid]) {
+                        smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
+                        if(smtc_live_asid[mytlb][oldasid] == 0)
+                                smtc_flush_tlb_asid(oldasid);
+                }
+                /* See comments for similar code above */
+                write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
+                                | cpu_asid(cpu, mm));
+                ehb(); /* Make sure it propagates to TCStatus */
+                evpe(prevvpe);
+#else /* not CONFIG_MIPS_MT_SMTC */
+                write_c0_entryhi(cpu_asid(cpu, mm));
+#endif /* CONFIG_MIPS_MT_SMTC */
+        } else {
+                /* will get a new context next time */
+#ifndef CONFIG_MIPS_MT_SMTC
+                cpu_context(cpu, mm) = 0;
+#else /* SMTC */
+                int i;
+
+                /* SMTC shares the TLB (and ASIDs) across VPEs */
+                for_each_online_cpu(i) {
+                    if((smtc_status & SMTC_TLB_SHARED)
+                    || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
+                        cpu_context(i, mm) = 0;
+                }
+#endif /* CONFIG_MIPS_MT_SMTC */
+        }
+        local_irq_restore(flags);
+}
+
+#endif /* _ASM_MMU_CONTEXT_H */
diff --git a/arch/mips/include/asm/mmzone.h b/arch/mips/include/asm/mmzone.h
new file mode 100644
index 000000000000..f53ec54c92ff
--- /dev/null
+++ b/arch/mips/include/asm/mmzone.h
@@ -0,0 +1,17 @@
+/*
+ * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99
+ * Rewritten for Linux 2.6 by Christoph Hellwig (hch@lst.de) Jan 2004
+ */
+#ifndef _ASM_MMZONE_H_
+#define _ASM_MMZONE_H_
+
+#include <asm/page.h>
+#include <mmzone.h>
+
+#ifdef CONFIG_DISCONTIGMEM
+
+#define pfn_to_nid(pfn)         pa_to_nid((pfn) << PAGE_SHIFT)
+
+#endif /* CONFIG_DISCONTIGMEM */
+
+#endif /* _ASM_MMZONE_H_ */
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
new file mode 100644
index 000000000000..de6d09ebbd80
--- /dev/null
+++ b/arch/mips/include/asm/module.h
@@ -0,0 +1,136 @@
+#ifndef _ASM_MODULE_H
+#define _ASM_MODULE_H
+
+#include <linux/list.h>
+#include <asm/uaccess.h>
+
+struct mod_arch_specific {
+        /* Data Bus Error exception tables */
+        struct list_head dbe_list;
+        const struct exception_table_entry *dbe_start;
+        const struct exception_table_entry *dbe_end;
+};
+
+typedef uint8_t Elf64_Byte;             /* Type for a 8-bit quantity.  */
+
+typedef struct {
+        Elf64_Addr r_offset;                    /* Address of relocation.  */
+        Elf64_Word r_sym;                       /* Symbol index.  */
+        Elf64_Byte r_ssym;                      /* Special symbol.  */
+        Elf64_Byte r_type3;                     /* Third relocation.  */
+        Elf64_Byte r_type2;                     /* Second relocation.  */
+        Elf64_Byte r_type;                      /* First relocation.  */
+} Elf64_Mips_Rel;
+
+typedef struct {
+        Elf64_Addr r_offset;                    /* Address of relocation.  */
+        Elf64_Word r_sym;                       /* Symbol index.  */
+        Elf64_Byte r_ssym;                      /* Special symbol.  */
+        Elf64_Byte r_type3;                     /* Third relocation.  */
+        Elf64_Byte r_type2;                     /* Second relocation.  */
+        Elf64_Byte r_type;                      /* First relocation.  */
+        Elf64_Sxword r_addend;                  /* Addend.  */
+} Elf64_Mips_Rela;
+
+#ifdef CONFIG_32BIT
+
+#define Elf_Shdr        Elf32_Shdr
+#define Elf_Sym         Elf32_Sym
+#define Elf_Ehdr        Elf32_Ehdr
+#define Elf_Addr        Elf32_Addr
+
+#define Elf_Mips_Rel    Elf32_Rel
+#define Elf_Mips_Rela   Elf32_Rela
+
+#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info)
+#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info)
+
+#endif
+
+#ifdef CONFIG_64BIT
+
+#define Elf_Shdr        Elf64_Shdr
+#define Elf_Sym         Elf64_Sym
+#define Elf_Ehdr        Elf64_Ehdr
+#define Elf_Addr        Elf64_Addr
+
+#define Elf_Mips_Rel    Elf64_Mips_Rel
+#define Elf_Mips_Rela   Elf64_Mips_Rela
+
+#define ELF_MIPS_R_SYM(rel) (rel.r_sym)
+#define ELF_MIPS_R_TYPE(rel) (rel.r_type)
+
+#endif
+
+#ifdef CONFIG_MODULES
+/* Given an address, look for it in the exception tables. */
+const struct exception_table_entry*search_module_dbetables(unsigned long addr);
+#else
+/* Given an address, look for it in the exception tables. */
+static inline const struct exception_table_entry *
+search_module_dbetables(unsigned long addr)
+{
+        return NULL;
+}
+#endif
+
+#ifdef CONFIG_CPU_MIPS32_R1
+#define MODULE_PROC_FAMILY "MIPS32_R1 "
+#elif defined CONFIG_CPU_MIPS32_R2
+#define MODULE_PROC_FAMILY "MIPS32_R2 "
+#elif defined CONFIG_CPU_MIPS64_R1
+#define MODULE_PROC_FAMILY "MIPS64_R1 "
+#elif defined CONFIG_CPU_MIPS64_R2
+#define MODULE_PROC_FAMILY "MIPS64_R2 "
+#elif defined CONFIG_CPU_R3000
+#define MODULE_PROC_FAMILY "R3000 "
+#elif defined CONFIG_CPU_TX39XX
+#define MODULE_PROC_FAMILY "TX39XX "
+#elif defined CONFIG_CPU_VR41XX
+#define MODULE_PROC_FAMILY "VR41XX "
+#elif defined CONFIG_CPU_R4300
+#define MODULE_PROC_FAMILY "R4300 "
+#elif defined CONFIG_CPU_R4X00
+#define MODULE_PROC_FAMILY "R4X00 "
+#elif defined CONFIG_CPU_TX49XX
+#define MODULE_PROC_FAMILY "TX49XX "
+#elif defined CONFIG_CPU_R5000
+#define MODULE_PROC_FAMILY "R5000 "
+#elif defined CONFIG_CPU_R5432
+#define MODULE_PROC_FAMILY "R5432 "
+#elif defined CONFIG_CPU_R6000
+#define MODULE_PROC_FAMILY "R6000 "
+#elif defined CONFIG_CPU_NEVADA
+#define MODULE_PROC_FAMILY "NEVADA "
+#elif defined CONFIG_CPU_R8000
+#define MODULE_PROC_FAMILY "R8000 "
+#elif defined CONFIG_CPU_R10000
+#define MODULE_PROC_FAMILY "R10000 "
+#elif defined CONFIG_CPU_RM7000
+#define MODULE_PROC_FAMILY "RM7000 "
+#elif defined CONFIG_CPU_RM9000
+#define MODULE_PROC_FAMILY "RM9000 "
+#elif defined CONFIG_CPU_SB1
+#define MODULE_PROC_FAMILY "SB1 "
+#elif defined CONFIG_CPU_LOONGSON2
+#define MODULE_PROC_FAMILY "LOONGSON2 "
+#else
+#error MODULE_PROC_FAMILY undefined for your processor configuration
+#endif
+
+#ifdef CONFIG_32BIT
+#define MODULE_KERNEL_TYPE "32BIT "
+#elif defined CONFIG_64BIT
+#define MODULE_KERNEL_TYPE "64BIT "
+#endif
+
+#ifdef CONFIG_MIPS_MT_SMTC
+#define MODULE_KERNEL_SMTC "MT_SMTC "
+#else
+#define MODULE_KERNEL_SMTC ""
+#endif
+
+#define MODULE_ARCH_VERMAGIC \
+        MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC
+
+#endif /* _ASM_MODULE_H */
diff --git a/arch/mips/include/asm/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h
new file mode 100644
index 000000000000..7989b9ffc1d2
--- /dev/null
+++ b/arch/mips/include/asm/msc01_ic.h
@@ -0,0 +1,148 @@
+/*
+ * PCI Register definitions for the MIPS System Controller.
+ *
+ * Copyright (C) 2004 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
+#define __ASM_MIPS_BOARDS_MSC01_IC_H
+
+/*****************************************************************************
+ * Register offset addresses
+ *****************************************************************************/
+
+#define MSC01_IC_RST_OFS     0x00008    /* Software reset              */
+#define MSC01_IC_ENAL_OFS    0x00100    /* Int_in enable mask 31:0     */
+#define MSC01_IC_ENAH_OFS    0x00108    /* Int_in enable mask 63:32    */
+#define MSC01_IC_DISL_OFS    0x00120    /* Int_in disable mask 31:0    */
+#define MSC01_IC_DISH_OFS    0x00128    /* Int_in disable mask 63:32   */
+#define MSC01_IC_ISBL_OFS    0x00140    /* Raw int_in 31:0             */
+#define MSC01_IC_ISBH_OFS    0x00148    /* Raw int_in 63:32            */
+#define MSC01_IC_ISAL_OFS    0x00160    /* Masked int_in 31:0          */
+#define MSC01_IC_ISAH_OFS    0x00168    /* Masked int_in 63:32         */
+#define MSC01_IC_LVL_OFS     0x00180    /* Disable priority int_out    */
+#define MSC01_IC_RAMW_OFS    0x00180    /* Shadow set RAM (EI)         */
+#define MSC01_IC_OSB_OFS     0x00188    /* Raw int_out                 */
+#define MSC01_IC_OSA_OFS     0x00190    /* Masked int_out              */
+#define MSC01_IC_GENA_OFS    0x00198    /* Global HW int enable        */
+#define MSC01_IC_BASE_OFS    0x001a0    /* Base address of IC_VEC      */
+#define MSC01_IC_VEC_OFS     0x001b0    /* Active int's vector address */
+#define MSC01_IC_EOI_OFS     0x001c0    /* Enable lower level ints     */
+#define MSC01_IC_CFG_OFS     0x001c8    /* Configuration register      */
+#define MSC01_IC_TRLD_OFS    0x001d0    /* Interval timer reload val   */
+#define MSC01_IC_TVAL_OFS    0x001e0    /* Interval timer current val  */
+#define MSC01_IC_TCFG_OFS    0x001f0    /* Interval timer config       */
+#define MSC01_IC_SUP_OFS     0x00200    /* Set up int_in line 0        */
+#define MSC01_IC_ENA_OFS     0x00800    /* Int_in enable mask 63:0     */
+#define MSC01_IC_DIS_OFS     0x00820    /* Int_in disable mask 63:0    */
+#define MSC01_IC_ISB_OFS     0x00840    /* Raw int_in 63:0             */
+#define MSC01_IC_ISA_OFS     0x00860    /* Masked int_in 63:0          */
+
+/*****************************************************************************
+ * Register field encodings
+ *****************************************************************************/
+
+#define MSC01_IC_RST_RST_SHF      0
+#define MSC01_IC_RST_RST_MSK      0x00000001
+#define MSC01_IC_RST_RST_BIT      MSC01_IC_RST_RST_MSK
+#define MSC01_IC_LVL_LVL_SHF      0
+#define MSC01_IC_LVL_LVL_MSK      0x000000ff
+#define MSC01_IC_LVL_SPUR_SHF     16
+#define MSC01_IC_LVL_SPUR_MSK     0x00010000
+#define MSC01_IC_LVL_SPUR_BIT     MSC01_IC_LVL_SPUR_MSK
+#define MSC01_IC_RAMW_RIPL_SHF    0
+#define MSC01_IC_RAMW_RIPL_MSK    0x0000003f
+#define MSC01_IC_RAMW_DATA_SHF    6
+#define MSC01_IC_RAMW_DATA_MSK    0x00000fc0
+#define MSC01_IC_RAMW_ADDR_SHF    25
+#define MSC01_IC_RAMW_ADDR_MSK    0x7e000000
+#define MSC01_IC_RAMW_READ_SHF    31
+#define MSC01_IC_RAMW_READ_MSK    0x80000000
+#define MSC01_IC_RAMW_READ_BIT    MSC01_IC_RAMW_READ_MSK
+#define MSC01_IC_OSB_OSB_SHF      0
+#define MSC01_IC_OSB_OSB_MSK      0x000000ff
+#define MSC01_IC_OSA_OSA_SHF      0
+#define MSC01_IC_OSA_OSA_MSK      0x000000ff
+#define MSC01_IC_GENA_GENA_SHF    0
+#define MSC01_IC_GENA_GENA_MSK    0x00000001
+#define MSC01_IC_GENA_GENA_BIT    MSC01_IC_GENA_GENA_MSK
+#define MSC01_IC_CFG_DIS_SHF      0
+#define MSC01_IC_CFG_DIS_MSK      0x00000001
+#define MSC01_IC_CFG_DIS_BIT      MSC01_IC_CFG_DIS_MSK
+#define MSC01_IC_CFG_SHFT_SHF     8
+#define MSC01_IC_CFG_SHFT_MSK     0x00000f00
+#define MSC01_IC_TCFG_ENA_SHF     0
+#define MSC01_IC_TCFG_ENA_MSK     0x00000001
+#define MSC01_IC_TCFG_ENA_BIT     MSC01_IC_TCFG_ENA_MSK
+#define MSC01_IC_TCFG_INT_SHF     8
+#define MSC01_IC_TCFG_INT_MSK     0x00000100
+#define MSC01_IC_TCFG_INT_BIT     MSC01_IC_TCFG_INT_MSK
+#define MSC01_IC_TCFG_EDGE_SHF    16
+#define MSC01_IC_TCFG_EDGE_MSK    0x00010000
+#define MSC01_IC_TCFG_EDGE_BIT    MSC01_IC_TCFG_EDGE_MSK
+#define MSC01_IC_SUP_PRI_SHF      0
+#define MSC01_IC_SUP_PRI_MSK      0x00000007
+#define MSC01_IC_SUP_EDGE_SHF     8
+#define MSC01_IC_SUP_EDGE_MSK     0x00000100
+#define MSC01_IC_SUP_EDGE_BIT     MSC01_IC_SUP_EDGE_MSK
+#define MSC01_IC_SUP_STEP         8
+
+/*
+ * MIPS System controller interrupt register base.
+ *
+ */
+
+/*****************************************************************************
+ * Absolute register addresses
+ *****************************************************************************/
+
+#define MSC01_IC_RST     (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
+#define MSC01_IC_ENAL    (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
+#define MSC01_IC_ENAH    (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
+#define MSC01_IC_DISL    (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
+#define MSC01_IC_DISH    (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
+#define MSC01_IC_ISBL    (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
+#define MSC01_IC_ISBH    (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
+#define MSC01_IC_ISAL    (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
+#define MSC01_IC_ISAH    (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
+#define MSC01_IC_LVL     (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
+#define MSC01_IC_RAMW    (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
+#define MSC01_IC_OSB     (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
+#define MSC01_IC_OSA     (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
+#define MSC01_IC_GENA    (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
+#define MSC01_IC_BASE    (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
+#define MSC01_IC_VEC     (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
+#define MSC01_IC_EOI     (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
+#define MSC01_IC_CFG     (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
+#define MSC01_IC_TRLD    (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
+#define MSC01_IC_TVAL    (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
+#define MSC01_IC_TCFG    (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
+#define MSC01_IC_SUP     (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
+#define MSC01_IC_ENA     (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
+#define MSC01_IC_DIS     (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
+#define MSC01_IC_ISB     (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
+#define MSC01_IC_ISA     (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
+
+/*
+ * Soc-it interrupts are configurable.
+ * Every board describes its IRQ mapping with this table.
+ */
+typedef struct msc_irqmap {
+        int     im_irq;
+        int     im_type;
+        int     im_lvl;
+} msc_irqmap_t;
+
+/* im_type */
+#define MSC01_IRQ_LEVEL         0
+#define MSC01_IRQ_EDGE          1
+
+extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
+extern void ll_msc_irq(void);
+
+#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
+
diff --git a/arch/mips/include/asm/msgbuf.h b/arch/mips/include/asm/msgbuf.h
new file mode 100644
index 000000000000..0d6c7f14de31
--- /dev/null
+++ b/arch/mips/include/asm/msgbuf.h
@@ -0,0 +1,47 @@
+#ifndef _ASM_MSGBUF_H
+#define _ASM_MSGBUF_H
+
+
+/*
+ * The msqid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - extension of time_t to 64-bit on 32-bitsystem to solve the y2038 problem
+ * - 2 miscellaneous unsigned long values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused1;
+#endif
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused1;
+#endif
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused2;
+#endif
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused2;
+#endif
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused3;
+#endif
+        __kernel_time_t msg_ctime;      /* last change time */
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused3;
+#endif
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif /* _ASM_MSGBUF_H */
diff --git a/arch/mips/include/asm/mutex.h b/arch/mips/include/asm/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/arch/mips/include/asm/mutex.h
@@ -0,0 +1,9 @@
+/*
+ * Pull in the generic implementation for the mutex fastpath.
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+
+#include <asm-generic/mutex-dec.h>
diff --git a/arch/mips/include/asm/nile4.h b/arch/mips/include/asm/nile4.h
new file mode 100644
index 000000000000..c3ca959aa4d9
--- /dev/null
+++ b/arch/mips/include/asm/nile4.h
@@ -0,0 +1,310 @@
+/*
+ *  asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
+ *
+ *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
+ *                     Sony Software Development Center Europe (SDCE), Brussels
+ *
+ *  This file is based on the following documentation:
+ *
+ *      NEC Vrc 5074 System Controller Data Sheet, June 1998
+ */
+
+#ifndef _ASM_NILE4_H
+#define _ASM_NILE4_H
+
+#define NILE4_BASE              0xbfa00000
+#define NILE4_SIZE              0x00200000              /* 2 MB */
+
+
+    /*
+     *  Physical Device Address Registers (PDARs)
+     */
+
+#define NILE4_SDRAM0    0x0000  /* SDRAM Bank 0 [R/W] */
+#define NILE4_SDRAM1    0x0008  /* SDRAM Bank 1 [R/W] */
+#define NILE4_DCS2      0x0010  /* Device Chip-Select 2 [R/W] */
+#define NILE4_DCS3      0x0018  /* Device Chip-Select 3 [R/W] */
+#define NILE4_DCS4      0x0020  /* Device Chip-Select 4 [R/W] */
+#define NILE4_DCS5      0x0028  /* Device Chip-Select 5 [R/W] */
+#define NILE4_DCS6      0x0030  /* Device Chip-Select 6 [R/W] */
+#define NILE4_DCS7      0x0038  /* Device Chip-Select 7 [R/W] */
+#define NILE4_DCS8      0x0040  /* Device Chip-Select 8 [R/W] */
+#define NILE4_PCIW0     0x0060  /* PCI Address Window 0 [R/W] */
+#define NILE4_PCIW1     0x0068  /* PCI Address Window 1 [R/W] */
+#define NILE4_INTCS     0x0070  /* Controller Internal Registers and Devices */
+                                /* [R/W] */
+#define NILE4_BOOTCS    0x0078  /* Boot ROM Chip-Select [R/W] */
+
+
+    /*
+     *  CPU Interface Registers
+     */
+
+#define NILE4_CPUSTAT   0x0080  /* CPU Status [R/W] */
+#define NILE4_INTCTRL   0x0088  /* Interrupt Control [R/W] */
+#define NILE4_INTSTAT0  0x0090  /* Interrupt Status 0 [R] */
+#define NILE4_INTSTAT1  0x0098  /* Interrupt Status 1 and CPU Interrupt */
+                                /* Enable [R/W] */
+#define NILE4_INTCLR    0x00A0  /* Interrupt Clear [R/W] */
+#define NILE4_INTPPES   0x00A8  /* PCI Interrupt Control [R/W] */
+
+
+    /*
+     *  Memory-Interface Registers
+     */
+
+#define NILE4_MEMCTRL   0x00C0  /* Memory Control */
+#define NILE4_ACSTIME   0x00C8  /* Memory Access Timing [R/W] */
+#define NILE4_CHKERR    0x00D0  /* Memory Check Error Status [R] */
+
+
+    /*
+     *  PCI-Bus Registers
+     */
+
+#define NILE4_PCICTRL   0x00E0  /* PCI Control [R/W] */
+#define NILE4_PCIARB    0x00E8  /* PCI Arbiter [R/W] */
+#define NILE4_PCIINIT0  0x00F0  /* PCI Master (Initiator) 0 [R/W] */
+#define NILE4_PCIINIT1  0x00F8  /* PCI Master (Initiator) 1 [R/W] */
+#define NILE4_PCIERR    0x00B8  /* PCI Error [R/W] */
+
+
+    /*
+     *  Local-Bus Registers
+     */
+
+#define NILE4_LCNFG     0x0100  /* Local Bus Configuration [R/W] */
+#define NILE4_LCST2     0x0110  /* Local Bus Chip-Select Timing 2 [R/W] */
+#define NILE4_LCST3     0x0118  /* Local Bus Chip-Select Timing 3 [R/W] */
+#define NILE4_LCST4     0x0120  /* Local Bus Chip-Select Timing 4 [R/W] */
+#define NILE4_LCST5     0x0128  /* Local Bus Chip-Select Timing 5 [R/W] */
+#define NILE4_LCST6     0x0130  /* Local Bus Chip-Select Timing 6 [R/W] */
+#define NILE4_LCST7     0x0138  /* Local Bus Chip-Select Timing 7 [R/W] */
+#define NILE4_LCST8     0x0140  /* Local Bus Chip-Select Timing 8 [R/W] */
+#define NILE4_DCSFN     0x0150  /* Device Chip-Select Muxing and Output */
+                                /* Enables [R/W] */
+#define NILE4_DCSIO     0x0158  /* Device Chip-Selects As I/O Bits [R/W] */
+#define NILE4_BCST      0x0178  /* Local Boot Chip-Select Timing [R/W] */
+
+
+    /*
+     *  DMA Registers
+     */
+
+#define NILE4_DMACTRL0  0x0180  /* DMA Control 0 [R/W] */
+#define NILE4_DMASRCA0  0x0188  /* DMA Source Address 0 [R/W] */
+#define NILE4_DMADESA0  0x0190  /* DMA Destination Address 0 [R/W] */
+#define NILE4_DMACTRL1  0x0198  /* DMA Control 1 [R/W] */
+#define NILE4_DMASRCA1  0x01A0  /* DMA Source Address 1 [R/W] */
+#define NILE4_DMADESA1  0x01A8  /* DMA Destination Address 1 [R/W] */
+
+
+    /*
+     *  Timer Registers
+     */
+
+#define NILE4_T0CTRL    0x01C0  /* SDRAM Refresh Control [R/W] */
+#define NILE4_T0CNTR    0x01C8  /* SDRAM Refresh Counter [R/W] */
+#define NILE4_T1CTRL    0x01D0  /* CPU-Bus Read Time-Out Control [R/W] */
+#define NILE4_T1CNTR    0x01D8  /* CPU-Bus Read Time-Out Counter [R/W] */
+#define NILE4_T2CTRL    0x01E0  /* General-Purpose Timer Control [R/W] */
+#define NILE4_T2CNTR    0x01E8  /* General-Purpose Timer Counter [R/W] */
+#define NILE4_T3CTRL    0x01F0  /* Watchdog Timer Control [R/W] */
+#define NILE4_T3CNTR    0x01F8  /* Watchdog Timer Counter [R/W] */
+
+
+    /*
+     *  PCI Configuration Space Registers
+     */
+
+#define NILE4_PCI_BASE  0x0200
+
+#define NILE4_VID       0x0200  /* PCI Vendor ID [R] */
+#define NILE4_DID       0x0202  /* PCI Device ID [R] */
+#define NILE4_PCICMD    0x0204  /* PCI Command [R/W] */
+#define NILE4_PCISTS    0x0206  /* PCI Status [R/W] */
+#define NILE4_REVID     0x0208  /* PCI Revision ID [R] */
+#define NILE4_CLASS     0x0209  /* PCI Class Code [R] */
+#define NILE4_CLSIZ     0x020C  /* PCI Cache Line Size [R/W] */
+#define NILE4_MLTIM     0x020D  /* PCI Latency Timer [R/W] */
+#define NILE4_HTYPE     0x020E  /* PCI Header Type [R] */
+#define NILE4_BIST      0x020F  /* BIST [R] (unimplemented) */
+#define NILE4_BARC      0x0210  /* PCI Base Address Register Control [R/W] */
+#define NILE4_BAR0      0x0218  /* PCI Base Address Register 0 [R/W] */
+#define NILE4_BAR1      0x0220  /* PCI Base Address Register 1 [R/W] */
+#define NILE4_CIS       0x0228  /* PCI Cardbus CIS Pointer [R] */
+                                /* (unimplemented) */
+#define NILE4_SSVID     0x022C  /* PCI Sub-System Vendor ID [R/W] */
+#define NILE4_SSID      0x022E  /* PCI Sub-System ID [R/W] */
+#define NILE4_ROM       0x0230  /* Expansion ROM Base Address [R] */
+                                /* (unimplemented) */
+#define NILE4_INTLIN    0x023C  /* PCI Interrupt Line [R/W] */
+#define NILE4_INTPIN    0x023D  /* PCI Interrupt Pin [R] */
+#define NILE4_MINGNT    0x023E  /* PCI Min_Gnt [R] (unimplemented) */
+#define NILE4_MAXLAT    0x023F  /* PCI Max_Lat [R] (unimplemented) */
+#define NILE4_BAR2      0x0240  /* PCI Base Address Register 2 [R/W] */
+#define NILE4_BAR3      0x0248  /* PCI Base Address Register 3 [R/W] */
+#define NILE4_BAR4      0x0250  /* PCI Base Address Register 4 [R/W] */
+#define NILE4_BAR5      0x0258  /* PCI Base Address Register 5 [R/W] */
+#define NILE4_BAR6      0x0260  /* PCI Base Address Register 6 [R/W] */
+#define NILE4_BAR7      0x0268  /* PCI Base Address Register 7 [R/W] */
+#define NILE4_BAR8      0x0270  /* PCI Base Address Register 8 [R/W] */
+#define NILE4_BARB      0x0278  /* PCI Base Address Register BOOT [R/W] */
+
+
+    /*
+     *  Serial-Port Registers
+     */
+
+#define NILE4_UART_BASE 0x0300
+
+#define NILE4_UARTRBR   0x0300  /* UART Receiver Data Buffer [R] */
+#define NILE4_UARTTHR   0x0300  /* UART Transmitter Data Holding [W] */
+#define NILE4_UARTIER   0x0308  /* UART Interrupt Enable [R/W] */
+#define NILE4_UARTDLL   0x0300  /* UART Divisor Latch LSB [R/W] */
+#define NILE4_UARTDLM   0x0308  /* UART Divisor Latch MSB [R/W] */
+#define NILE4_UARTIIR   0x0310  /* UART Interrupt ID [R] */
+#define NILE4_UARTFCR   0x0310  /* UART FIFO Control [W] */
+#define NILE4_UARTLCR   0x0318  /* UART Line Control [R/W] */
+#define NILE4_UARTMCR   0x0320  /* UART Modem Control [R/W] */
+#define NILE4_UARTLSR   0x0328  /* UART Line Status [R/W] */
+#define NILE4_UARTMSR   0x0330  /* UART Modem Status [R/W] */
+#define NILE4_UARTSCR   0x0338  /* UART Scratch [R/W] */
+
+#define NILE4_UART_BASE_BAUD    520833  /* 100 MHz / 12 / 16 */
+
+
+    /*
+     *  Interrupt Lines
+     */
+
+#define NILE4_INT_CPCE  0       /* CPU-Interface Parity-Error Interrupt */
+#define NILE4_INT_CNTD  1       /* CPU No-Target Decode Interrupt */
+#define NILE4_INT_MCE   2       /* Memory-Check Error Interrupt */
+#define NILE4_INT_DMA   3       /* DMA Controller Interrupt */
+#define NILE4_INT_UART  4       /* UART Interrupt */
+#define NILE4_INT_WDOG  5       /* Watchdog Timer Interrupt */
+#define NILE4_INT_GPT   6       /* General-Purpose Timer Interrupt */
+#define NILE4_INT_LBRTD 7       /* Local-Bus Ready Timer Interrupt */
+#define NILE4_INT_INTA  8       /* PCI Interrupt Signal INTA# */
+#define NILE4_INT_INTB  9       /* PCI Interrupt Signal INTB# */
+#define NILE4_INT_INTC  10      /* PCI Interrupt Signal INTC# */
+#define NILE4_INT_INTD  11      /* PCI Interrupt Signal INTD# */
+#define NILE4_INT_INTE  12      /* PCI Interrupt Signal INTE# (ISA cascade) */
+#define NILE4_INT_RESV  13      /* Reserved */
+#define NILE4_INT_PCIS  14      /* PCI SERR# Interrupt */
+#define NILE4_INT_PCIE  15      /* PCI Internal Error Interrupt */
+
+
+    /*
+     *  Nile 4 Register Access
+     */
+
+static inline void nile4_sync(void)
+{
+    volatile u32 *p = (volatile u32 *)0xbfc00000;
+    (void)(*p);
+}
+
+static inline void nile4_out32(u32 offset, u32 val)
+{
+    *(volatile u32 *)(NILE4_BASE+offset) = val;
+    nile4_sync();
+}
+
+static inline u32 nile4_in32(u32 offset)
+{
+    u32 val = *(volatile u32 *)(NILE4_BASE+offset);
+    nile4_sync();
+    return val;
+}
+
+static inline void nile4_out16(u32 offset, u16 val)
+{
+    *(volatile u16 *)(NILE4_BASE+offset) = val;
+    nile4_sync();
+}
+
+static inline u16 nile4_in16(u32 offset)
+{
+    u16 val = *(volatile u16 *)(NILE4_BASE+offset);
+    nile4_sync();
+    return val;
+}
+
+static inline void nile4_out8(u32 offset, u8 val)
+{
+    *(volatile u8 *)(NILE4_BASE+offset) = val;
+    nile4_sync();
+}
+
+static inline u8 nile4_in8(u32 offset)
+{
+    u8 val = *(volatile u8 *)(NILE4_BASE+offset);
+    nile4_sync();
+    return val;
+}
+
+
+    /*
+     *  Physical Device Address Registers
+     */
+
+extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
+                           int on_memory_bus, int visible);
+
+
+    /*
+     *  PCI Master Registers
+     */
+
+#define NILE4_PCICMD_IACK       0       /* PCI Interrupt Acknowledge */
+#define NILE4_PCICMD_IO         1       /* PCI I/O Space */
+#define NILE4_PCICMD_MEM        3       /* PCI Memory Space */
+#define NILE4_PCICMD_CFG        5       /* PCI Configuration Space */
+
+
+    /*
+     *  PCI Address Spaces
+     *
+     *  Note that these are multiplexed using PCIINIT[01]!
+     */
+
+#define NILE4_PCI_IO_BASE       0xa6000000
+#define NILE4_PCI_MEM_BASE      0xa8000000
+#define NILE4_PCI_CFG_BASE      NILE4_PCI_MEM_BASE
+#define NILE4_PCI_IACK_BASE     NILE4_PCI_IO_BASE
+
+
+extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
+
+
+    /*
+     *  Interrupt Programming
+     */
+
+#define NUM_I8259_INTERRUPTS    16
+#define NUM_NILE4_INTERRUPTS    16
+
+#define IRQ_I8259_CASCADE       NILE4_INT_INTE
+#define is_i8259_irq(irq)       ((irq) < NUM_I8259_INTERRUPTS)
+#define nile4_to_irq(n)         ((n)+NUM_I8259_INTERRUPTS)
+#define irq_to_nile4(n)         ((n)-NUM_I8259_INTERRUPTS)
+
+extern void nile4_map_irq(int nile4_irq, int cpu_irq);
+extern void nile4_map_irq_all(int cpu_irq);
+extern void nile4_enable_irq(unsigned int nile4_irq);
+extern void nile4_disable_irq(unsigned int nile4_irq);
+extern void nile4_disable_irq_all(void);
+extern u16 nile4_get_irq_stat(int cpu_irq);
+extern void nile4_enable_irq_output(int cpu_irq);
+extern void nile4_disable_irq_output(int cpu_irq);
+extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
+extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
+extern void nile4_clear_irq(int nile4_irq);
+extern void nile4_clear_irq_mask(u32 mask);
+extern u8 nile4_i8259_iack(void);
+extern void nile4_dump_irq_status(void);        /* Debug */
+
+#endif
+
diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h
new file mode 100644
index 000000000000..c2394f8b0fe1
--- /dev/null
+++ b/arch/mips/include/asm/paccess.h
@@ -0,0 +1,112 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * Protected memory access.  Used for everything that might take revenge
+ * by sending a DBE error like accessing possibly non-existant memory or
+ * devices.
+ */
+#ifndef _ASM_PACCESS_H
+#define _ASM_PACCESS_H
+
+#include <linux/errno.h>
+
+#ifdef CONFIG_32BIT
+#define __PA_ADDR       ".word"
+#endif
+#ifdef CONFIG_64BIT
+#define __PA_ADDR       ".dword"
+#endif
+
+extern asmlinkage void handle_ibe(void);
+extern asmlinkage void handle_dbe(void);
+
+#define put_dbe(x, ptr) __put_dbe((x), (ptr), sizeof(*(ptr)))
+#define get_dbe(x, ptr) __get_dbe((x), (ptr), sizeof(*(ptr)))
+
+struct __large_pstruct { unsigned long buf[100]; };
+#define __mp(x) (*(struct __large_pstruct *)(x))
+
+#define __get_dbe(x, ptr, size)                                         \
+({                                                                      \
+        long __gu_err;                                                  \
+        __typeof__(*(ptr)) __gu_val;                                    \
+        unsigned long __gu_addr;                                        \
+        __asm__("":"=r" (__gu_val));                                    \
+        __gu_addr = (unsigned long) (ptr);                              \
+        __asm__("":"=r" (__gu_err));                                    \
+        switch (size) {                                                 \
+        case 1: __get_dbe_asm("lb"); break;                             \
+        case 2: __get_dbe_asm("lh"); break;                             \
+        case 4: __get_dbe_asm("lw"); break;                             \
+        case 8:  __get_dbe_asm("ld"); break;                            \
+        default: __get_dbe_unknown(); break;                            \
+        }                                                               \
+        x = (__typeof__(*(ptr))) __gu_val;                              \
+        __gu_err;                                                       \
+})
+
+#define __get_dbe_asm(insn)                                             \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:\t" insn "\t%1,%2\n\t"                                       \
+        "move\t%0,$0\n"                                                 \
+        "2:\n\t"                                                        \
+        ".section\t.fixup,\"ax\"\n"                                     \
+        "3:\tli\t%0,%3\n\t"                                             \
+        "move\t%1,$0\n\t"                                               \
+        "j\t2b\n\t"                                                     \
+        ".previous\n\t"                                                 \
+        ".section\t__dbe_table,\"a\"\n\t"                               \
+        __PA_ADDR "\t1b, 3b\n\t"                                        \
+        ".previous"                                                     \
+        :"=r" (__gu_err), "=r" (__gu_val)                               \
+        :"o" (__mp(__gu_addr)), "i" (-EFAULT));                         \
+}
+
+extern void __get_dbe_unknown(void);
+
+#define __put_dbe(x, ptr, size)                                         \
+({                                                                      \
+        long __pu_err;                                                  \
+        __typeof__(*(ptr)) __pu_val;                                    \
+        long __pu_addr;                                                 \
+        __pu_val = (x);                                                 \
+        __pu_addr = (long) (ptr);                                       \
+        __asm__("":"=r" (__pu_err));                                    \
+        switch (size) {                                                 \
+        case 1: __put_dbe_asm("sb"); break;                             \
+        case 2: __put_dbe_asm("sh"); break;                             \
+        case 4: __put_dbe_asm("sw"); break;                             \
+        case 8: __put_dbe_asm("sd"); break;                             \
+        default: __put_dbe_unknown(); break;                            \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_dbe_asm(insn)                                             \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:\t" insn "\t%1,%2\n\t"                                       \
+        "move\t%0,$0\n"                                                 \
+        "2:\n\t"                                                        \
+        ".section\t.fixup,\"ax\"\n"                                     \
+        "3:\tli\t%0,%3\n\t"                                             \
+        "j\t2b\n\t"                                                     \
+        ".previous\n\t"                                                 \
+        ".section\t__dbe_table,\"a\"\n\t"                               \
+        __PA_ADDR "\t1b, 3b\n\t"                                        \
+        ".previous"                                                     \
+        : "=r" (__pu_err)                                               \
+        : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT));        \
+}
+
+extern void __put_dbe_unknown(void);
+
+extern unsigned long search_dbe_table(unsigned long addr);
+
+#endif /* _ASM_PACCESS_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
new file mode 100644
index 000000000000..fe7a88ea066e
--- /dev/null
+++ b/arch/mips/include/asm/page.h
@@ -0,0 +1,191 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PAGE_H
+#define _ASM_PAGE_H
+
+#include <spaces.h>
+
+/*
+ * PAGE_SHIFT determines the page size
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PAGE_SHIFT      12
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define PAGE_SHIFT      13
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define PAGE_SHIFT      14
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define PAGE_SHIFT      16
+#endif
+#define PAGE_SIZE       (1UL << PAGE_SHIFT)
+#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
+
+#ifndef __ASSEMBLY__
+
+#include <linux/pfn.h>
+#include <asm/io.h>
+
+extern void build_clear_page(void);
+extern void build_copy_page(void);
+
+/*
+ * It's normally defined only for FLATMEM config but it's
+ * used in our early mem init code for all memory models.
+ * So always define it.
+ */
+#define ARCH_PFN_OFFSET         PFN_UP(PHYS_OFFSET)
+
+extern void clear_page(void * page);
+extern void copy_page(void * to, void * from);
+
+extern unsigned long shm_align_mask;
+
+static inline unsigned long pages_do_alias(unsigned long addr1,
+        unsigned long addr2)
+{
+        return (addr1 ^ addr2) & shm_align_mask;
+}
+
+struct page;
+
+static inline void clear_user_page(void *addr, unsigned long vaddr,
+        struct page *page)
+{
+        extern void (*flush_data_cache_page)(unsigned long addr);
+
+        clear_page(addr);
+        if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
+                flush_data_cache_page((unsigned long)addr);
+}
+
+extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+        struct page *to);
+struct vm_area_struct;
+extern void copy_user_highpage(struct page *to, struct page *from,
+        unsigned long vaddr, struct vm_area_struct *vma);
+
+#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+
+/*
+ * These are used to make use of C type-checking..
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+  #ifdef CONFIG_CPU_MIPS32
+    typedef struct { unsigned long pte_low, pte_high; } pte_t;
+    #define pte_val(x)    ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+    #define __pte(x)      ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
+  #else
+     typedef struct { unsigned long long pte; } pte_t;
+     #define pte_val(x) ((x).pte)
+     #define __pte(x)   ((pte_t) { (x) } )
+  #endif
+#else
+typedef struct { unsigned long pte; } pte_t;
+#define pte_val(x)      ((x).pte)
+#define __pte(x)        ((pte_t) { (x) } )
+#endif
+typedef struct page *pgtable_t;
+
+/*
+ * For 3-level pagetables we defines these ourselves, for 2-level the
+ * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
+ */
+#ifdef CONFIG_64BIT
+
+typedef struct { unsigned long pmd; } pmd_t;
+#define pmd_val(x)      ((x).pmd)
+#define __pmd(x)        ((pmd_t) { (x) } )
+
+#endif
+
+/*
+ * Right now we don't support 4-level pagetables, so all pud-related
+ * definitions come from <asm-generic/pgtable-nopud.h>.
+ */
+
+/*
+ * Finall the top of the hierarchy, the pgd
+ */
+typedef struct { unsigned long pgd; } pgd_t;
+#define pgd_val(x)      ((x).pgd)
+#define __pgd(x)        ((pgd_t) { (x) } )
+
+/*
+ * Manipulate page protection bits
+ */
+typedef struct { unsigned long pgprot; } pgprot_t;
+#define pgprot_val(x)   ((x).pgprot)
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+/*
+ * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
+ * pair of pages we only have a single global bit per pair of pages.  When
+ * writing to the TLB make sure we always have the bit set for both pages
+ * or none.  This macro is used to access the `buddy' of the pte we're just
+ * working on.
+ */
+#define ptep_buddy(x)   ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * __pa()/__va() should be used only during mem init.
+ */
+#ifdef CONFIG_64BIT
+#define __pa(x)                                                         \
+({                                                                      \
+    unsigned long __x = (unsigned long)(x);                             \
+    __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x);                     \
+})
+#else
+#define __pa(x)                                                         \
+    ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
+#endif
+#define __va(x)         ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
+#define __pa_symbol(x)  __pa(RELOC_HIDE((unsigned long)(x), 0))
+
+#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
+
+#ifdef CONFIG_FLATMEM
+
+#define pfn_valid(pfn)          ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr)
+
+#elif defined(CONFIG_SPARSEMEM)
+
+/* pfn_valid is defined in linux/mmzone.h */
+
+#elif defined(CONFIG_NEED_MULTIPLE_NODES)
+
+#define pfn_valid(pfn)                                                  \
+({                                                                      \
+        unsigned long __pfn = (pfn);                                    \
+        int __n = pfn_to_nid(__pfn);                                    \
+        ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn +         \
+                               NODE_DATA(__n)->node_spanned_pages)      \
+                    : 0);                                               \
+})
+
+#endif
+
+#define virt_to_page(kaddr)     pfn_to_page(PFN_DOWN(virt_to_phys(kaddr)))
+#define virt_addr_valid(kaddr)  pfn_valid(PFN_DOWN(virt_to_phys(kaddr)))
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#define UNCAC_ADDR(addr)        ((addr) - PAGE_OFFSET + UNCAC_BASE)
+#define CAC_ADDR(addr)          ((addr) - UNCAC_BASE + PAGE_OFFSET)
+
+#include <asm-generic/memory_model.h>
+#include <asm-generic/page.h>
+
+#endif /* _ASM_PAGE_H */
diff --git a/arch/mips/include/asm/param.h b/arch/mips/include/asm/param.h
new file mode 100644
index 000000000000..1d9bb8c5ab24
--- /dev/null
+++ b/arch/mips/include/asm/param.h
@@ -0,0 +1,31 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1994 - 2000, 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PARAM_H
+#define _ASM_PARAM_H
+
+#ifdef __KERNEL__
+
+# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
+# define USER_HZ        100             /* .. some user interfaces are in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE   65536
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif /* _ASM_PARAM_H */
diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h
new file mode 100644
index 000000000000..f52656826cce
--- /dev/null
+++ b/arch/mips/include/asm/parport.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ */
+#ifndef _ASM_PARPORT_H
+#define _ASM_PARPORT_H
+
+static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
+static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
+{
+        return parport_pc_find_isa_ports(autoirq, autodma);
+}
+
+#endif /* _ASM_PARPORT_H */
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
new file mode 100644
index 000000000000..5510c53b7feb
--- /dev/null
+++ b/arch/mips/include/asm/pci.h
@@ -0,0 +1,179 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_PCI_H
+#define _ASM_PCI_H
+
+#include <linux/mm.h>
+
+#ifdef __KERNEL__
+
+/*
+ * This file essentially defines the interface between board
+ * specific PCI code and MIPS common PCI code.  Should potentially put
+ * into include/asm/pci.h file.
+ */
+
+#include <linux/ioport.h>
+
+/*
+ * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
+ * multiple PCI channels may have multiple PCI host controllers or a
+ * single controller supporting multiple channels.
+ */
+struct pci_controller {
+        struct pci_controller *next;
+        struct pci_bus *bus;
+
+        struct pci_ops *pci_ops;
+        struct resource *mem_resource;
+        unsigned long mem_offset;
+        struct resource *io_resource;
+        unsigned long io_offset;
+        unsigned long io_map_base;
+
+        unsigned int index;
+        /* For compatibility with current (as of July 2003) pciutils
+           and XFree86. Eventually will be removed. */
+        unsigned int need_domain_info;
+
+        int iommu;
+
+        /* Optional access methods for reading/writing the bus number
+           of the PCI controller */
+        int (*get_busno)(void);
+        void (*set_busno)(int busno);
+};
+
+/*
+ * Used by boards to register their PCI busses before the actual scanning.
+ */
+extern struct pci_controller * alloc_pci_controller(void);
+extern void register_pci_controller(struct pci_controller *hose);
+
+/*
+ * board supplied pci irq fixup routine
+ */
+extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+   already-configured bus numbers - to be used for buggy BIOSes
+   or architectures with incomplete PCI setup by the loader */
+
+extern unsigned int pcibios_assign_all_busses(void);
+
+#define pcibios_scan_all_fns(a, b)      0
+
+extern unsigned long PCIBIOS_MIN_IO;
+extern unsigned long PCIBIOS_MIN_MEM;
+
+#define PCIBIOS_MIN_CARDBUS_IO  0x4000
+
+extern void pcibios_set_master(struct pci_dev *dev);
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+/*
+ * Dynamic DMA mapping stuff.
+ * MIPS has everything mapped statically.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/scatterlist.h>
+#include <linux/string.h>
+#include <asm/io.h>
+
+struct pci_dev;
+
+/*
+ * The PCI address space does equal the physical memory address space.  The
+ * networking and block device layers use this boolean for bounce buffer
+ * decisions.  This is set if any hose does not have an IOMMU.
+ */
+extern unsigned int PCI_DMA_BUS_IS_PHYS;
+
+#ifdef CONFIG_DMA_NEED_PCI_MAP_STATE
+
+/* pci_unmap_{single,page} is not a nop, thus... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)          ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)            ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   (((PTR)->LEN_NAME) = (VAL))
+
+#else /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
+
+/* pci_unmap_{page,single} is a nop so... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
+#define pci_unmap_len(PTR, LEN_NAME)            (0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
+
+#endif /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+                                        enum pci_dma_burst_strategy *strat,
+                                        unsigned long *strategy_parameter)
+{
+        *strat = PCI_DMA_BURST_INFINITY;
+        *strategy_parameter = ~0UL;
+}
+#endif
+
+extern void pcibios_resource_to_bus(struct pci_dev *dev,
+        struct pci_bus_region *region, struct resource *res);
+
+extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                                    struct pci_bus_region *region);
+
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+
+        return root;
+}
+
+#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
+
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        struct pci_controller *hose = bus->sysdata;
+        return hose->need_domain_info;
+}
+
+#endif /* __KERNEL__ */
+
+/* implement the pci_ DMA API in terms of the generic device dma_ one */
+#include <asm-generic/pci-dma-compat.h>
+
+/* Do platform specific device initialization at pci_enable_device() time */
+extern int pcibios_plat_dev_init(struct pci_dev *dev);
+
+/* Chances are this interrupt is wired PC-style ...  */
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+        return channel ? 15 : 14;
+}
+
+extern int pci_probe_only;
+
+extern char * (*pcibios_plat_setup)(char *str);
+
+#endif /* _ASM_PCI_H */
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
new file mode 100644
index 000000000000..5f4b9d4e4114
--- /dev/null
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -0,0 +1,854 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
+ * revision 1.76.
+ *
+ * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_PCI_BRIDGE_H
+#define _ASM_PCI_BRIDGE_H
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <asm/xtalk/xwidget.h>          /* generic widget header */
+#include <asm/sn/types.h>
+
+/* I/O page size */
+
+#define IOPFNSHIFT              12      /* 4K per mapped page */
+
+#define IOPGSIZE                (1 << IOPFNSHIFT)
+#define IOPG(x)                 ((x) >> IOPFNSHIFT)
+#define IOPGOFF(x)              ((x) & (IOPGSIZE-1))
+
+/* Bridge RAM sizes */
+
+#define BRIDGE_ATE_RAM_SIZE     0x00000400      /* 1kB ATE RAM */
+
+#define BRIDGE_CONFIG_BASE      0x20000
+#define BRIDGE_CONFIG1_BASE     0x28000
+#define BRIDGE_CONFIG_END       0x30000
+#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
+
+#define BRIDGE_SSRAM_512K       0x00080000      /* 512kB */
+#define BRIDGE_SSRAM_128K       0x00020000      /* 128kB */
+#define BRIDGE_SSRAM_64K        0x00010000      /* 64kB */
+#define BRIDGE_SSRAM_0K         0x00000000      /* 0kB */
+
+/* ========================================================================
+ *    Bridge address map
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * All accesses to bridge hardware registers must be done
+ * using 32-bit loads and stores.
+ */
+typedef u32     bridgereg_t;
+
+typedef u64     bridge_ate_t;
+
+/* pointers to bridge ATEs
+ * are always "pointer to volatile"
+ */
+typedef volatile bridge_ate_t  *bridge_ate_p;
+
+/*
+ * It is generally preferred that hardware registers on the bridge
+ * are located from C code via this structure.
+ *
+ * Generated from Bridge spec dated 04oct95
+ */
+
+typedef volatile struct bridge_s {
+        /* Local Registers                             0x000000-0x00FFFF */
+
+        /* standard widget configuration               0x000000-0x000057 */
+        widget_cfg_t        b_widget;                   /* 0x000000 */
+
+        /* helper fieldnames for accessing bridge widget */
+
+#define b_wid_id                        b_widget.w_id
+#define b_wid_stat                      b_widget.w_status
+#define b_wid_err_upper                 b_widget.w_err_upper_addr
+#define b_wid_err_lower                 b_widget.w_err_lower_addr
+#define b_wid_control                   b_widget.w_control
+#define b_wid_req_timeout               b_widget.w_req_timeout
+#define b_wid_int_upper                 b_widget.w_intdest_upper_addr
+#define b_wid_int_lower                 b_widget.w_intdest_lower_addr
+#define b_wid_err_cmdword               b_widget.w_err_cmd_word
+#define b_wid_llp                       b_widget.w_llp_cfg
+#define b_wid_tflush                    b_widget.w_tflush
+
+        /* bridge-specific widget configuration 0x000058-0x00007F */
+        bridgereg_t         _pad_000058;
+        bridgereg_t         b_wid_aux_err;              /* 0x00005C */
+        bridgereg_t         _pad_000060;
+        bridgereg_t         b_wid_resp_upper;           /* 0x000064 */
+        bridgereg_t         _pad_000068;
+        bridgereg_t         b_wid_resp_lower;           /* 0x00006C */
+        bridgereg_t         _pad_000070;
+        bridgereg_t         b_wid_tst_pin_ctrl;         /* 0x000074 */
+        bridgereg_t     _pad_000078[2];
+
+        /* PMU & Map 0x000080-0x00008F */
+        bridgereg_t     _pad_000080;
+        bridgereg_t     b_dir_map;                      /* 0x000084 */
+        bridgereg_t     _pad_000088[2];
+
+        /* SSRAM 0x000090-0x00009F */
+        bridgereg_t     _pad_000090;
+        bridgereg_t     b_ram_perr;                     /* 0x000094 */
+        bridgereg_t     _pad_000098[2];
+
+        /* Arbitration 0x0000A0-0x0000AF */
+        bridgereg_t     _pad_0000A0;
+        bridgereg_t     b_arb;                          /* 0x0000A4 */
+        bridgereg_t     _pad_0000A8[2];
+
+        /* Number In A Can 0x0000B0-0x0000BF */
+        bridgereg_t     _pad_0000B0;
+        bridgereg_t     b_nic;                          /* 0x0000B4 */
+        bridgereg_t     _pad_0000B8[2];
+
+        /* PCI/GIO 0x0000C0-0x0000FF */
+        bridgereg_t     _pad_0000C0;
+        bridgereg_t     b_bus_timeout;                  /* 0x0000C4 */
+#define b_pci_bus_timeout b_bus_timeout
+
+        bridgereg_t     _pad_0000C8;
+        bridgereg_t     b_pci_cfg;                      /* 0x0000CC */
+        bridgereg_t     _pad_0000D0;
+        bridgereg_t     b_pci_err_upper;                /* 0x0000D4 */
+        bridgereg_t     _pad_0000D8;
+        bridgereg_t     b_pci_err_lower;                /* 0x0000DC */
+        bridgereg_t     _pad_0000E0[8];
+#define b_gio_err_lower b_pci_err_lower
+#define b_gio_err_upper b_pci_err_upper
+
+        /* Interrupt 0x000100-0x0001FF */
+        bridgereg_t     _pad_000100;
+        bridgereg_t     b_int_status;                   /* 0x000104 */
+        bridgereg_t     _pad_000108;
+        bridgereg_t     b_int_enable;                   /* 0x00010C */
+        bridgereg_t     _pad_000110;
+        bridgereg_t     b_int_rst_stat;                 /* 0x000114 */
+        bridgereg_t     _pad_000118;
+        bridgereg_t     b_int_mode;                     /* 0x00011C */
+        bridgereg_t     _pad_000120;
+        bridgereg_t     b_int_device;                   /* 0x000124 */
+        bridgereg_t     _pad_000128;
+        bridgereg_t     b_int_host_err;                 /* 0x00012C */
+
+        struct {
+                bridgereg_t     __pad;                  /* 0x0001{30,,,68} */
+                bridgereg_t     addr;                   /* 0x0001{34,,,6C} */
+        } b_int_addr[8];                                /* 0x000130 */
+
+        bridgereg_t     _pad_000170[36];
+
+        /* Device 0x000200-0x0003FF */
+        struct {
+                bridgereg_t     __pad;                  /* 0x0002{00,,,38} */
+                bridgereg_t     reg;                    /* 0x0002{04,,,3C} */
+        } b_device[8];                                  /* 0x000200 */
+
+        struct {
+                bridgereg_t     __pad;                  /* 0x0002{40,,,78} */
+                bridgereg_t     reg;                    /* 0x0002{44,,,7C} */
+        } b_wr_req_buf[8];                              /* 0x000240 */
+
+        struct {
+                bridgereg_t     __pad;                  /* 0x0002{80,,,88} */
+                bridgereg_t     reg;                    /* 0x0002{84,,,8C} */
+        } b_rrb_map[2];                                 /* 0x000280 */
+#define b_even_resp     b_rrb_map[0].reg                /* 0x000284 */
+#define b_odd_resp      b_rrb_map[1].reg                /* 0x00028C */
+
+        bridgereg_t     _pad_000290;
+        bridgereg_t     b_resp_status;                  /* 0x000294 */
+        bridgereg_t     _pad_000298;
+        bridgereg_t     b_resp_clear;                   /* 0x00029C */
+
+        bridgereg_t     _pad_0002A0[24];
+
+        char            _pad_000300[0x10000 - 0x000300];
+
+        /* Internal Address Translation Entry RAM 0x010000-0x0103FF */
+        union {
+                bridge_ate_t    wr;                     /* write-only */
+                struct {
+                        bridgereg_t     _p_pad;
+                        bridgereg_t     rd;             /* read-only */
+                }                       hi;
+        }                           b_int_ate_ram[128];
+
+        char    _pad_010400[0x11000 - 0x010400];
+
+        /* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
+        struct {
+                bridgereg_t     _p_pad;
+                bridgereg_t     rd;             /* read-only */
+        } b_int_ate_ram_lo[128];
+
+        char    _pad_011400[0x20000 - 0x011400];
+
+        /* PCI Device Configuration Spaces 0x020000-0x027FFF */
+        union {                         /* make all access sizes available. */
+                u8      c[0x1000 / 1];
+                u16     s[0x1000 / 2];
+                u32     l[0x1000 / 4];
+                u64     d[0x1000 / 8];
+                union {
+                        u8      c[0x100 / 1];
+                        u16     s[0x100 / 2];
+                        u32     l[0x100 / 4];
+                        u64     d[0x100 / 8];
+                } f[8];
+        } b_type0_cfg_dev[8];                                   /* 0x020000 */
+
+    /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
+        union {                         /* make all access sizes available. */
+                u8      c[0x1000 / 1];
+                u16     s[0x1000 / 2];
+                u32     l[0x1000 / 4];
+                u64     d[0x1000 / 8];
+        } b_type1_cfg;                                  /* 0x028000-0x029000 */
+
+        char    _pad_029000[0x007000];                  /* 0x029000-0x030000 */
+
+        /* PCI Interrupt Acknowledge Cycle 0x030000 */
+        union {
+                u8      c[8 / 1];
+                u16     s[8 / 2];
+                u32     l[8 / 4];
+                u64     d[8 / 8];
+        } b_pci_iack;                                           /* 0x030000 */
+
+        u8      _pad_030007[0x04fff8];                  /* 0x030008-0x07FFFF */
+
+        /* External Address Translation Entry RAM 0x080000-0x0FFFFF */
+        bridge_ate_t    b_ext_ate_ram[0x10000];
+
+        /* Reserved 0x100000-0x1FFFFF */
+        char    _pad_100000[0x200000-0x100000];
+
+        /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
+        union {                         /* make all access sizes available. */
+                u8      c[0x100000 / 1];
+                u16     s[0x100000 / 2];
+                u32     l[0x100000 / 4];
+                u64     d[0x100000 / 8];
+        } b_devio_raw[10];                              /* 0x200000 */
+
+        /* b_devio macro is a bit strange; it reflects the
+         * fact that the Bridge ASIC provides 2M for the
+         * first two DevIO windows and 1M for the other six.
+         */
+#define b_devio(n)      b_devio_raw[((n)<2)?(n*2):(n+2)]
+
+        /* External Flash Proms 1,0 0xC00000-0xFFFFFF */
+        union {         /* make all access sizes available. */
+                u8      c[0x400000 / 1];        /* read-only */
+                u16     s[0x400000 / 2];        /* read-write */
+                u32     l[0x400000 / 4];        /* read-only */
+                u64     d[0x400000 / 8];        /* read-only */
+        } b_external_flash;                     /* 0xC00000 */
+} bridge_t;
+
+/*
+ * Field formats for Error Command Word and Auxillary Error Command Word
+ * of bridge.
+ */
+typedef struct bridge_err_cmdword_s {
+        union {
+                u32             cmd_word;
+                struct {
+                        u32     didn:4,         /* Destination ID */
+                                sidn:4,         /* Source ID      */
+                                pactyp:4,       /* Packet type    */
+                                tnum:5,         /* Trans Number   */
+                                coh:1,          /* Coh Transacti  */
+                                ds:2,           /* Data size      */
+                                gbr:1,          /* GBR enable     */
+                                vbpm:1,         /* VBPM message   */
+                                error:1,        /* Error occurred  */
+                                barr:1,         /* Barrier op     */
+                                rsvd:8;
+                } berr_st;
+        } berr_un;
+} bridge_err_cmdword_t;
+
+#define berr_field      berr_un.berr_st
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * The values of these macros can and should be crosschecked
+ * regularly against the offsets of the like-named fields
+ * within the "bridge_t" structure above.
+ */
+
+/* Byte offset macros for Bridge internal registers */
+
+#define BRIDGE_WID_ID           WIDGET_ID
+#define BRIDGE_WID_STAT         WIDGET_STATUS
+#define BRIDGE_WID_ERR_UPPER    WIDGET_ERR_UPPER_ADDR
+#define BRIDGE_WID_ERR_LOWER    WIDGET_ERR_LOWER_ADDR
+#define BRIDGE_WID_CONTROL      WIDGET_CONTROL
+#define BRIDGE_WID_REQ_TIMEOUT  WIDGET_REQ_TIMEOUT
+#define BRIDGE_WID_INT_UPPER    WIDGET_INTDEST_UPPER_ADDR
+#define BRIDGE_WID_INT_LOWER    WIDGET_INTDEST_LOWER_ADDR
+#define BRIDGE_WID_ERR_CMDWORD  WIDGET_ERR_CMD_WORD
+#define BRIDGE_WID_LLP          WIDGET_LLP_CFG
+#define BRIDGE_WID_TFLUSH       WIDGET_TFLUSH
+
+#define BRIDGE_WID_AUX_ERR      0x00005C        /* Aux Error Command Word */
+#define BRIDGE_WID_RESP_UPPER   0x000064        /* Response Buf Upper Addr */
+#define BRIDGE_WID_RESP_LOWER   0x00006C        /* Response Buf Lower Addr */
+#define BRIDGE_WID_TST_PIN_CTRL 0x000074        /* Test pin control */
+
+#define BRIDGE_DIR_MAP          0x000084        /* Direct Map reg */
+
+#define BRIDGE_RAM_PERR         0x000094        /* SSRAM Parity Error */
+
+#define BRIDGE_ARB              0x0000A4        /* Arbitration Priority reg */
+
+#define BRIDGE_NIC              0x0000B4        /* Number In A Can */
+
+#define BRIDGE_BUS_TIMEOUT      0x0000C4        /* Bus Timeout Register */
+#define BRIDGE_PCI_BUS_TIMEOUT  BRIDGE_BUS_TIMEOUT
+#define BRIDGE_PCI_CFG          0x0000CC        /* PCI Type 1 Config reg */
+#define BRIDGE_PCI_ERR_UPPER    0x0000D4        /* PCI error Upper Addr */
+#define BRIDGE_PCI_ERR_LOWER    0x0000DC        /* PCI error Lower Addr */
+
+#define BRIDGE_INT_STATUS       0x000104        /* Interrupt Status */
+#define BRIDGE_INT_ENABLE       0x00010C        /* Interrupt Enables */
+#define BRIDGE_INT_RST_STAT     0x000114        /* Reset Intr Status */
+#define BRIDGE_INT_MODE         0x00011C        /* Interrupt Mode */
+#define BRIDGE_INT_DEVICE       0x000124        /* Interrupt Device */
+#define BRIDGE_INT_HOST_ERR     0x00012C        /* Host Error Field */
+
+#define BRIDGE_INT_ADDR0        0x000134        /* Host Address Reg */
+#define BRIDGE_INT_ADDR_OFF     0x000008        /* Host Addr offset (1..7) */
+#define BRIDGE_INT_ADDR(x)      (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
+
+#define BRIDGE_DEVICE0          0x000204        /* Device 0 */
+#define BRIDGE_DEVICE_OFF       0x000008        /* Device offset (1..7) */
+#define BRIDGE_DEVICE(x)        (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
+
+#define BRIDGE_WR_REQ_BUF0      0x000244        /* Write Request Buffer 0 */
+#define BRIDGE_WR_REQ_BUF_OFF   0x000008        /* Buffer Offset (1..7) */
+#define BRIDGE_WR_REQ_BUF(x)    (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
+
+#define BRIDGE_EVEN_RESP        0x000284        /* Even Device Response Buf */
+#define BRIDGE_ODD_RESP         0x00028C        /* Odd Device Response Buf */
+
+#define BRIDGE_RESP_STATUS      0x000294        /* Read Response Status reg */
+#define BRIDGE_RESP_CLEAR       0x00029C        /* Read Response Clear reg */
+
+/* Byte offset macros for Bridge I/O space */
+
+#define BRIDGE_ATE_RAM          0x00010000      /* Internal Addr Xlat Ram */
+
+#define BRIDGE_TYPE0_CFG_DEV0   0x00020000      /* Type 0 Cfg, Device 0 */
+#define BRIDGE_TYPE0_CFG_SLOT_OFF       0x00001000      /* Type 0 Cfg Slot Offset (1..7) */
+#define BRIDGE_TYPE0_CFG_FUNC_OFF       0x00000100      /* Type 0 Cfg Func Offset (1..7) */
+#define BRIDGE_TYPE0_CFG_DEV(s)         (BRIDGE_TYPE0_CFG_DEV0+\
+                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
+#define BRIDGE_TYPE0_CFG_DEVF(s, f)     (BRIDGE_TYPE0_CFG_DEV0+\
+                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
+                                         (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
+
+#define BRIDGE_TYPE1_CFG        0x00028000      /* Type 1 Cfg space */
+
+#define BRIDGE_PCI_IACK         0x00030000      /* PCI Interrupt Ack */
+#define BRIDGE_EXT_SSRAM        0x00080000      /* Extern SSRAM (ATE) */
+
+/* Byte offset macros for Bridge device IO spaces */
+
+#define BRIDGE_DEV_CNT          8       /* Up to 8 devices per bridge */
+#define BRIDGE_DEVIO0           0x00200000      /* Device IO 0 Addr */
+#define BRIDGE_DEVIO1           0x00400000      /* Device IO 1 Addr */
+#define BRIDGE_DEVIO2           0x00600000      /* Device IO 2 Addr */
+#define BRIDGE_DEVIO_OFF        0x00100000      /* Device IO Offset (3..7) */
+
+#define BRIDGE_DEVIO_2MB        0x00200000      /* Device IO Offset (0..1) */
+#define BRIDGE_DEVIO_1MB        0x00100000      /* Device IO Offset (2..7) */
+
+#define BRIDGE_DEVIO(x)         ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
+
+#define BRIDGE_EXTERNAL_FLASH   0x00C00000      /* External Flash PROMS */
+
+/* ========================================================================
+ *    Bridge register bit field definitions
+ */
+
+/* Widget part number of bridge */
+#define BRIDGE_WIDGET_PART_NUM          0xc002
+#define XBRIDGE_WIDGET_PART_NUM         0xd002
+
+/* Manufacturer of bridge */
+#define BRIDGE_WIDGET_MFGR_NUM          0x036
+#define XBRIDGE_WIDGET_MFGR_NUM         0x024
+
+/* Revision numbers for known Bridge revisions */
+#define BRIDGE_REV_A                    0x1
+#define BRIDGE_REV_B                    0x2
+#define BRIDGE_REV_C                    0x3
+#define BRIDGE_REV_D                    0x4
+
+/* Bridge widget status register bits definition */
+
+#define BRIDGE_STAT_LLP_REC_CNT         (0xFFu << 24)
+#define BRIDGE_STAT_LLP_TX_CNT          (0xFF << 16)
+#define BRIDGE_STAT_FLASH_SELECT        (0x1 << 6)
+#define BRIDGE_STAT_PCI_GIO_N           (0x1 << 5)
+#define BRIDGE_STAT_PENDING             (0x1F << 0)
+
+/* Bridge widget control register bits definition */
+#define BRIDGE_CTRL_FLASH_WR_EN         (0x1ul << 31)
+#define BRIDGE_CTRL_EN_CLK50            (0x1 << 30)
+#define BRIDGE_CTRL_EN_CLK40            (0x1 << 29)
+#define BRIDGE_CTRL_EN_CLK33            (0x1 << 28)
+#define BRIDGE_CTRL_RST(n)              ((n) << 24)
+#define BRIDGE_CTRL_RST_MASK            (BRIDGE_CTRL_RST(0xF))
+#define BRIDGE_CTRL_RST_PIN(x)          (BRIDGE_CTRL_RST(0x1 << (x)))
+#define BRIDGE_CTRL_IO_SWAP             (0x1 << 23)
+#define BRIDGE_CTRL_MEM_SWAP            (0x1 << 22)
+#define BRIDGE_CTRL_PAGE_SIZE           (0x1 << 21)
+#define BRIDGE_CTRL_SS_PAR_BAD          (0x1 << 20)
+#define BRIDGE_CTRL_SS_PAR_EN           (0x1 << 19)
+#define BRIDGE_CTRL_SSRAM_SIZE(n)       ((n) << 17)
+#define BRIDGE_CTRL_SSRAM_SIZE_MASK     (BRIDGE_CTRL_SSRAM_SIZE(0x3))
+#define BRIDGE_CTRL_SSRAM_512K          (BRIDGE_CTRL_SSRAM_SIZE(0x3))
+#define BRIDGE_CTRL_SSRAM_128K          (BRIDGE_CTRL_SSRAM_SIZE(0x2))
+#define BRIDGE_CTRL_SSRAM_64K           (BRIDGE_CTRL_SSRAM_SIZE(0x1))
+#define BRIDGE_CTRL_SSRAM_1K            (BRIDGE_CTRL_SSRAM_SIZE(0x0))
+#define BRIDGE_CTRL_F_BAD_PKT           (0x1 << 16)
+#define BRIDGE_CTRL_LLP_XBAR_CRD(n)     ((n) << 12)
+#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK   (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
+#define BRIDGE_CTRL_CLR_RLLP_CNT        (0x1 << 11)
+#define BRIDGE_CTRL_CLR_TLLP_CNT        (0x1 << 10)
+#define BRIDGE_CTRL_SYS_END             (0x1 << 9)
+#define BRIDGE_CTRL_MAX_TRANS(n)        ((n) << 4)
+#define BRIDGE_CTRL_MAX_TRANS_MASK      (BRIDGE_CTRL_MAX_TRANS(0x1f))
+#define BRIDGE_CTRL_WIDGET_ID(n)        ((n) << 0)
+#define BRIDGE_CTRL_WIDGET_ID_MASK      (BRIDGE_CTRL_WIDGET_ID(0xf))
+
+/* Bridge Response buffer Error Upper Register bit fields definition */
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+#define BRIDGE_RESP_ERRRUPPR_BUFMASK    (0xFFFF)
+
+#define BRIDGE_RESP_ERRUPPR_BUFNUM(x)   \
+                        (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
+                                BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+
+#define BRIDGE_RESP_ERRUPPR_DEVICE(x)   \
+                        (((x) &  BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
+                                 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+
+/* Bridge direct mapping register bits definition */
+#define BRIDGE_DIRMAP_W_ID_SHFT         20
+#define BRIDGE_DIRMAP_W_ID              (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
+#define BRIDGE_DIRMAP_RMF_64            (0x1 << 18)
+#define BRIDGE_DIRMAP_ADD512            (0x1 << 17)
+#define BRIDGE_DIRMAP_OFF               (0x1ffff << 0)
+#define BRIDGE_DIRMAP_OFF_ADDRSHFT      (31)    /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
+
+/* Bridge Arbitration register bits definition */
+#define BRIDGE_ARB_REQ_WAIT_TICK(x)     ((x) << 16)
+#define BRIDGE_ARB_REQ_WAIT_TICK_MASK   BRIDGE_ARB_REQ_WAIT_TICK(0x3)
+#define BRIDGE_ARB_REQ_WAIT_EN(x)       ((x) << 8)
+#define BRIDGE_ARB_REQ_WAIT_EN_MASK     BRIDGE_ARB_REQ_WAIT_EN(0xff)
+#define BRIDGE_ARB_FREEZE_GNT           (1 << 6)
+#define BRIDGE_ARB_HPRI_RING_B2         (1 << 5)
+#define BRIDGE_ARB_HPRI_RING_B1         (1 << 4)
+#define BRIDGE_ARB_HPRI_RING_B0         (1 << 3)
+#define BRIDGE_ARB_LPRI_RING_B2         (1 << 2)
+#define BRIDGE_ARB_LPRI_RING_B1         (1 << 1)
+#define BRIDGE_ARB_LPRI_RING_B0         (1 << 0)
+
+/* Bridge Bus time-out register bits definition */
+#define BRIDGE_BUS_PCI_RETRY_HLD(x)     ((x) << 16)
+#define BRIDGE_BUS_PCI_RETRY_HLD_MASK   BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
+#define BRIDGE_BUS_GIO_TIMEOUT          (1 << 12)
+#define BRIDGE_BUS_PCI_RETRY_CNT(x)     ((x) << 0)
+#define BRIDGE_BUS_PCI_RETRY_MASK       BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
+
+/* Bridge interrupt status register bits definition */
+#define BRIDGE_ISR_MULTI_ERR            (0x1u << 31)
+#define BRIDGE_ISR_PMU_ESIZE_FAULT      (0x1 << 30)
+#define BRIDGE_ISR_UNEXP_RESP           (0x1 << 29)
+#define BRIDGE_ISR_BAD_XRESP_PKT        (0x1 << 28)
+#define BRIDGE_ISR_BAD_XREQ_PKT         (0x1 << 27)
+#define BRIDGE_ISR_RESP_XTLK_ERR        (0x1 << 26)
+#define BRIDGE_ISR_REQ_XTLK_ERR         (0x1 << 25)
+#define BRIDGE_ISR_INVLD_ADDR           (0x1 << 24)
+#define BRIDGE_ISR_UNSUPPORTED_XOP      (0x1 << 23)
+#define BRIDGE_ISR_XREQ_FIFO_OFLOW      (0x1 << 22)
+#define BRIDGE_ISR_LLP_REC_SNERR        (0x1 << 21)
+#define BRIDGE_ISR_LLP_REC_CBERR        (0x1 << 20)
+#define BRIDGE_ISR_LLP_RCTY             (0x1 << 19)
+#define BRIDGE_ISR_LLP_TX_RETRY         (0x1 << 18)
+#define BRIDGE_ISR_LLP_TCTY             (0x1 << 17)
+#define BRIDGE_ISR_SSRAM_PERR           (0x1 << 16)
+#define BRIDGE_ISR_PCI_ABORT            (0x1 << 15)
+#define BRIDGE_ISR_PCI_PARITY           (0x1 << 14)
+#define BRIDGE_ISR_PCI_SERR             (0x1 << 13)
+#define BRIDGE_ISR_PCI_PERR             (0x1 << 12)
+#define BRIDGE_ISR_PCI_MST_TIMEOUT      (0x1 << 11)
+#define BRIDGE_ISR_GIO_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
+#define BRIDGE_ISR_PCI_RETRY_CNT        (0x1 << 10)
+#define BRIDGE_ISR_XREAD_REQ_TIMEOUT    (0x1 << 9)
+#define BRIDGE_ISR_GIO_B_ENBL_ERR       (0x1 << 8)
+#define BRIDGE_ISR_INT_MSK              (0xff << 0)
+#define BRIDGE_ISR_INT(x)               (0x1 << (x))
+
+#define BRIDGE_ISR_LINK_ERROR           \
+                (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|     \
+                 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|           \
+                 BRIDGE_ISR_LLP_TCTY)
+
+#define BRIDGE_ISR_PCIBUS_PIOERR        \
+                (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
+
+#define BRIDGE_ISR_PCIBUS_ERROR         \
+                (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|          \
+                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|          \
+                 BRIDGE_ISR_PCI_PARITY)
+
+#define BRIDGE_ISR_XTALK_ERROR          \
+                (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
+                 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|      \
+                 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|      \
+                 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|      \
+                 BRIDGE_ISR_UNEXP_RESP)
+
+#define BRIDGE_ISR_ERRORS               \
+                (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|         \
+                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|          \
+                 BRIDGE_ISR_PMU_ESIZE_FAULT)
+
+/*
+ * List of Errors which are fatal and kill the system
+ */
+#define BRIDGE_ISR_ERROR_FATAL          \
+                ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
+                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
+
+#define BRIDGE_ISR_ERROR_DUMP           \
+                (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|    \
+                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
+
+/* Bridge interrupt enable register bits definition */
+#define BRIDGE_IMR_UNEXP_RESP           BRIDGE_ISR_UNEXP_RESP
+#define BRIDGE_IMR_PMU_ESIZE_FAULT      BRIDGE_ISR_PMU_ESIZE_FAULT
+#define BRIDGE_IMR_BAD_XRESP_PKT        BRIDGE_ISR_BAD_XRESP_PKT
+#define BRIDGE_IMR_BAD_XREQ_PKT         BRIDGE_ISR_BAD_XREQ_PKT
+#define BRIDGE_IMR_RESP_XTLK_ERR        BRIDGE_ISR_RESP_XTLK_ERR
+#define BRIDGE_IMR_REQ_XTLK_ERR         BRIDGE_ISR_REQ_XTLK_ERR
+#define BRIDGE_IMR_INVLD_ADDR           BRIDGE_ISR_INVLD_ADDR
+#define BRIDGE_IMR_UNSUPPORTED_XOP      BRIDGE_ISR_UNSUPPORTED_XOP
+#define BRIDGE_IMR_XREQ_FIFO_OFLOW      BRIDGE_ISR_XREQ_FIFO_OFLOW
+#define BRIDGE_IMR_LLP_REC_SNERR        BRIDGE_ISR_LLP_REC_SNERR
+#define BRIDGE_IMR_LLP_REC_CBERR        BRIDGE_ISR_LLP_REC_CBERR
+#define BRIDGE_IMR_LLP_RCTY             BRIDGE_ISR_LLP_RCTY
+#define BRIDGE_IMR_LLP_TX_RETRY         BRIDGE_ISR_LLP_TX_RETRY
+#define BRIDGE_IMR_LLP_TCTY             BRIDGE_ISR_LLP_TCTY
+#define BRIDGE_IMR_SSRAM_PERR           BRIDGE_ISR_SSRAM_PERR
+#define BRIDGE_IMR_PCI_ABORT            BRIDGE_ISR_PCI_ABORT
+#define BRIDGE_IMR_PCI_PARITY           BRIDGE_ISR_PCI_PARITY
+#define BRIDGE_IMR_PCI_SERR             BRIDGE_ISR_PCI_SERR
+#define BRIDGE_IMR_PCI_PERR             BRIDGE_ISR_PCI_PERR
+#define BRIDGE_IMR_PCI_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
+#define BRIDGE_IMR_GIO_MST_TIMEOUT      BRIDGE_ISR_GIO_MST_TIMEOUT
+#define BRIDGE_IMR_PCI_RETRY_CNT        BRIDGE_ISR_PCI_RETRY_CNT
+#define BRIDGE_IMR_XREAD_REQ_TIMEOUT    BRIDGE_ISR_XREAD_REQ_TIMEOUT
+#define BRIDGE_IMR_GIO_B_ENBL_ERR       BRIDGE_ISR_GIO_B_ENBL_ERR
+#define BRIDGE_IMR_INT_MSK              BRIDGE_ISR_INT_MSK
+#define BRIDGE_IMR_INT(x)               BRIDGE_ISR_INT(x)
+
+/* Bridge interrupt reset register bits definition */
+#define BRIDGE_IRR_MULTI_CLR            (0x1 << 6)
+#define BRIDGE_IRR_CRP_GRP_CLR          (0x1 << 5)
+#define BRIDGE_IRR_RESP_BUF_GRP_CLR     (0x1 << 4)
+#define BRIDGE_IRR_REQ_DSP_GRP_CLR      (0x1 << 3)
+#define BRIDGE_IRR_LLP_GRP_CLR          (0x1 << 2)
+#define BRIDGE_IRR_SSRAM_GRP_CLR        (0x1 << 1)
+#define BRIDGE_IRR_PCI_GRP_CLR          (0x1 << 0)
+#define BRIDGE_IRR_GIO_GRP_CLR          (0x1 << 0)
+#define BRIDGE_IRR_ALL_CLR              0x7f
+
+#define BRIDGE_IRR_CRP_GRP              (BRIDGE_ISR_UNEXP_RESP | \
+                                         BRIDGE_ISR_XREQ_FIFO_OFLOW)
+#define BRIDGE_IRR_RESP_BUF_GRP         (BRIDGE_ISR_BAD_XRESP_PKT | \
+                                         BRIDGE_ISR_RESP_XTLK_ERR | \
+                                         BRIDGE_ISR_XREAD_REQ_TIMEOUT)
+#define BRIDGE_IRR_REQ_DSP_GRP          (BRIDGE_ISR_UNSUPPORTED_XOP | \
+                                         BRIDGE_ISR_BAD_XREQ_PKT | \
+                                         BRIDGE_ISR_REQ_XTLK_ERR | \
+                                         BRIDGE_ISR_INVLD_ADDR)
+#define BRIDGE_IRR_LLP_GRP              (BRIDGE_ISR_LLP_REC_SNERR | \
+                                         BRIDGE_ISR_LLP_REC_CBERR | \
+                                         BRIDGE_ISR_LLP_RCTY | \
+                                         BRIDGE_ISR_LLP_TX_RETRY | \
+                                         BRIDGE_ISR_LLP_TCTY)
+#define BRIDGE_IRR_SSRAM_GRP            (BRIDGE_ISR_SSRAM_PERR | \
+                                         BRIDGE_ISR_PMU_ESIZE_FAULT)
+#define BRIDGE_IRR_PCI_GRP              (BRIDGE_ISR_PCI_ABORT | \
+                                         BRIDGE_ISR_PCI_PARITY | \
+                                         BRIDGE_ISR_PCI_SERR | \
+                                         BRIDGE_ISR_PCI_PERR | \
+                                         BRIDGE_ISR_PCI_MST_TIMEOUT | \
+                                         BRIDGE_ISR_PCI_RETRY_CNT)
+
+#define BRIDGE_IRR_GIO_GRP              (BRIDGE_ISR_GIO_B_ENBL_ERR | \
+                                         BRIDGE_ISR_GIO_MST_TIMEOUT)
+
+/* Bridge INT_DEV register bits definition */
+#define BRIDGE_INT_DEV_SHFT(n)          ((n)*3)
+#define BRIDGE_INT_DEV_MASK(n)          (0x7 << BRIDGE_INT_DEV_SHFT(n))
+#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
+
+/* Bridge interrupt(x) register bits definition */
+#define BRIDGE_INT_ADDR_HOST            0x0003FF00
+#define BRIDGE_INT_ADDR_FLD             0x000000FF
+
+#define BRIDGE_TMO_PCI_RETRY_HLD_MASK   0x1f0000
+#define BRIDGE_TMO_GIO_TIMEOUT_MASK     0x001000
+#define BRIDGE_TMO_PCI_RETRY_CNT_MASK   0x0003ff
+
+#define BRIDGE_TMO_PCI_RETRY_CNT_MAX    0x3ff
+
+/*
+ * The NASID should be shifted by this amount and stored into the
+ * interrupt(x) register.
+ */
+#define BRIDGE_INT_ADDR_NASID_SHFT      8
+
+/*
+ * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
+ * memory.
+ */
+#define BRIDGE_INT_ADDR_DEST_IO         (1 << 17)
+#define BRIDGE_INT_ADDR_DEST_MEM        0
+#define BRIDGE_INT_ADDR_MASK            (1 << 17)
+
+/* Bridge device(x) register bits definition */
+#define BRIDGE_DEV_ERR_LOCK_EN          0x10000000
+#define BRIDGE_DEV_PAGE_CHK_DIS         0x08000000
+#define BRIDGE_DEV_FORCE_PCI_PAR        0x04000000
+#define BRIDGE_DEV_VIRTUAL_EN           0x02000000
+#define BRIDGE_DEV_PMU_WRGA_EN          0x01000000
+#define BRIDGE_DEV_DIR_WRGA_EN          0x00800000
+#define BRIDGE_DEV_DEV_SIZE             0x00400000
+#define BRIDGE_DEV_RT                   0x00200000
+#define BRIDGE_DEV_SWAP_PMU             0x00100000
+#define BRIDGE_DEV_SWAP_DIR             0x00080000
+#define BRIDGE_DEV_PREF                 0x00040000
+#define BRIDGE_DEV_PRECISE              0x00020000
+#define BRIDGE_DEV_COH                  0x00010000
+#define BRIDGE_DEV_BARRIER              0x00008000
+#define BRIDGE_DEV_GBR                  0x00004000
+#define BRIDGE_DEV_DEV_SWAP             0x00002000
+#define BRIDGE_DEV_DEV_IO_MEM           0x00001000
+#define BRIDGE_DEV_OFF_MASK             0x00000fff
+#define BRIDGE_DEV_OFF_ADDR_SHFT        20
+
+#define BRIDGE_DEV_PMU_BITS             (BRIDGE_DEV_PMU_WRGA_EN         | \
+                                         BRIDGE_DEV_SWAP_PMU)
+#define BRIDGE_DEV_D32_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
+                                         BRIDGE_DEV_SWAP_DIR            | \
+                                         BRIDGE_DEV_PREF                | \
+                                         BRIDGE_DEV_PRECISE             | \
+                                         BRIDGE_DEV_COH                 | \
+                                         BRIDGE_DEV_BARRIER)
+#define BRIDGE_DEV_D64_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
+                                         BRIDGE_DEV_SWAP_DIR            | \
+                                         BRIDGE_DEV_COH                 | \
+                                         BRIDGE_DEV_BARRIER)
+
+/* Bridge Error Upper register bit field definition */
+#define BRIDGE_ERRUPPR_DEVMASTER        (0x1 << 20)     /* Device was master */
+#define BRIDGE_ERRUPPR_PCIVDEV          (0x1 << 19)     /* Virtual Req value */
+#define BRIDGE_ERRUPPR_DEVNUM_SHFT      (16)
+#define BRIDGE_ERRUPPR_DEVNUM_MASK      (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_ERRUPPR_DEVICE(err)      (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
+#define BRIDGE_ERRUPPR_ADDRMASK         (0xFFFF)
+
+/* Bridge interrupt mode register bits definition */
+#define BRIDGE_INTMODE_CLR_PKT_EN(x)    (0x1 << (x))
+
+/* this should be written to the xbow's link_control(x) register */
+#define BRIDGE_CREDIT   3
+
+/* RRB assignment register */
+#define BRIDGE_RRB_EN   0x8     /* after shifting down */
+#define BRIDGE_RRB_DEV  0x7     /* after shifting down */
+#define BRIDGE_RRB_VDEV 0x4     /* after shifting down */
+#define BRIDGE_RRB_PDEV 0x3     /* after shifting down */
+
+/* RRB status register */
+#define BRIDGE_RRB_VALID(r)     (0x00010000<<(r))
+#define BRIDGE_RRB_INUSE(r)     (0x00000001<<(r))
+
+/* RRB clear register */
+#define BRIDGE_RRB_CLEAR(r)     (0x00000001<<(r))
+
+/* xbox system controller declarations */
+#define XBOX_BRIDGE_WID         8
+#define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
+#define XBOX_RPS_EXISTS         1 << 6   /* RPS bit in status register */
+#define XBOX_RPS_FAIL           1 << 4   /* RPS status bit in register */
+
+/* ========================================================================
+ */
+/*
+ * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
+ * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
+ */
+/* XTALK addresses that map into Bridge Bus addr space */
+#define BRIDGE_PIO32_XTALK_ALIAS_BASE   0x000040000000L
+#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT  0x00007FFFFFFFL
+#define BRIDGE_PIO64_XTALK_ALIAS_BASE   0x000080000000L
+#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT  0x0000BFFFFFFFL
+#define BRIDGE_PCIIO_XTALK_ALIAS_BASE   0x000100000000L
+#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT  0x0001FFFFFFFFL
+
+/* Ranges of PCI bus space that can be accessed via PIO from xtalk */
+#define BRIDGE_MIN_PIO_ADDR_MEM         0x00000000      /* 1G PCI memory space */
+#define BRIDGE_MAX_PIO_ADDR_MEM         0x3fffffff
+#define BRIDGE_MIN_PIO_ADDR_IO          0x00000000      /* 4G PCI IO space */
+#define BRIDGE_MAX_PIO_ADDR_IO          0xffffffff
+
+/* XTALK addresses that map into PCI addresses */
+#define BRIDGE_PCI_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
+#define BRIDGE_PCI_MEM64_BASE           BRIDGE_PIO64_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_MEM64_LIMIT          BRIDGE_PIO64_XTALK_ALIAS_LIMIT
+#define BRIDGE_PCI_IO_BASE              BRIDGE_PCIIO_XTALK_ALIAS_BASE
+#define BRIDGE_PCI_IO_LIMIT             BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
+
+/*
+ * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
+ */
+/* Bridge Bus DMA addresses */
+#define BRIDGE_LOCAL_BASE               0
+#define BRIDGE_DMA_MAPPED_BASE          0x40000000
+#define BRIDGE_DMA_MAPPED_SIZE          0x40000000      /* 1G Bytes */
+#define BRIDGE_DMA_DIRECT_BASE          0x80000000
+#define BRIDGE_DMA_DIRECT_SIZE          0x80000000      /* 2G Bytes */
+
+#define PCI32_LOCAL_BASE                BRIDGE_LOCAL_BASE
+
+/* PCI addresses of regions decoded by Bridge for DMA */
+#define PCI32_MAPPED_BASE               BRIDGE_DMA_MAPPED_BASE
+#define PCI32_DIRECT_BASE               BRIDGE_DMA_DIRECT_BASE
+
+#define IS_PCI32_LOCAL(x)       ((ulong_t)(x) < PCI32_MAPPED_BASE)
+#define IS_PCI32_MAPPED(x)      ((ulong_t)(x) < PCI32_DIRECT_BASE && \
+                                        (ulong_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x)      ((ulong_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI64(x)             ((ulong_t)(x) >= PCI64_BASE)
+
+/*
+ * The GIO address space.
+ */
+/* Xtalk to GIO PIO */
+#define BRIDGE_GIO_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
+#define BRIDGE_GIO_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
+
+#define GIO_LOCAL_BASE                  BRIDGE_LOCAL_BASE
+
+/* GIO addresses of regions decoded by Bridge for DMA */
+#define GIO_MAPPED_BASE                 BRIDGE_DMA_MAPPED_BASE
+#define GIO_DIRECT_BASE                 BRIDGE_DMA_DIRECT_BASE
+
+#define IS_GIO_LOCAL(x)         ((ulong_t)(x) < GIO_MAPPED_BASE)
+#define IS_GIO_MAPPED(x)        ((ulong_t)(x) < GIO_DIRECT_BASE && \
+                                        (ulong_t)(x) >= GIO_MAPPED_BASE)
+#define IS_GIO_DIRECT(x)        ((ulong_t)(x) >= GIO_MAPPED_BASE)
+
+/* PCI to xtalk mapping */
+
+/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
+ * which xtalk address is accessed
+ */
+#define BRIDGE_DIRECT_32_SEG_SIZE       BRIDGE_DMA_DIRECT_SIZE
+#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)          \
+        ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +        \
+                ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
+
+/* 64-bit address attribute masks */
+#define PCI64_ATTR_TARG_MASK    0xf000000000000000
+#define PCI64_ATTR_TARG_SHFT    60
+#define PCI64_ATTR_PREF         0x0800000000000000
+#define PCI64_ATTR_PREC         0x0400000000000000
+#define PCI64_ATTR_VIRTUAL      0x0200000000000000
+#define PCI64_ATTR_BAR          0x0100000000000000
+#define PCI64_ATTR_RMF_MASK     0x00ff000000000000
+#define PCI64_ATTR_RMF_SHFT     48
+
+#ifndef __ASSEMBLY__
+/* Address translation entry for mapped pci32 accesses */
+typedef union ate_u {
+        u64     ent;
+        struct ate_s {
+                u64     rmf:16;
+                u64     addr:36;
+                u64     targ:4;
+                u64     reserved:3;
+                u64     barrier:1;
+                u64     prefetch:1;
+                u64     precise:1;
+                u64     coherent:1;
+                u64     valid:1;
+        } field;
+} ate_t;
+#endif /* !__ASSEMBLY__ */
+
+#define ATE_V           0x01
+#define ATE_CO          0x02
+#define ATE_PREC        0x04
+#define ATE_PREF        0x08
+#define ATE_BAR         0x10
+
+#define ATE_PFNSHIFT            12
+#define ATE_TIDSHIFT            8
+#define ATE_RMFSHIFT            48
+
+#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
+                                ((xid)<<ATE_TIDSHIFT) | \
+                                (attr)
+
+#define BRIDGE_INTERNAL_ATES    128
+
+struct bridge_controller {
+        struct pci_controller   pc;
+        struct resource         mem;
+        struct resource         io;
+        bridge_t                *base;
+        nasid_t                 nasid;
+        unsigned int            widget_id;
+        unsigned int            irq_cpu;
+        dma64_addr_t            baddr;
+        unsigned int            pci_int[8];
+};
+
+#define BRIDGE_CONTROLLER(bus) \
+        ((struct bridge_controller *)((bus)->sysdata))
+
+extern void register_bridge_irq(unsigned int irq);
+extern int request_bridge_irq(struct bridge_controller *bc);
+
+extern struct pci_ops bridge_pci_ops;
+
+#endif /* _ASM_PCI_BRIDGE_H */
diff --git a/arch/mips/include/asm/percpu.h b/arch/mips/include/asm/percpu.h
new file mode 100644
index 000000000000..844e763e9332
--- /dev/null
+++ b/arch/mips/include/asm/percpu.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_PERCPU_H
+#define __ASM_PERCPU_H
+
+#include <asm-generic/percpu.h>
+
+#endif /* __ASM_PERCPU_H */
diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h
new file mode 100644
index 000000000000..1275831dda29
--- /dev/null
+++ b/arch/mips/include/asm/pgalloc.h
@@ -0,0 +1,143 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 2001, 2003 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGALLOC_H
+#define _ASM_PGALLOC_H
+
+#include <linux/highmem.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
+        pte_t *pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)pte));
+}
+
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+        pgtable_t pte)
+{
+        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+/*
+ * Initialize a new pmd table with invalid pointers.
+ */
+extern void pmd_init(unsigned long page, unsigned long pagetable);
+
+#ifdef CONFIG_64BIT
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+        set_pud(pud, __pud((unsigned long)pmd));
+}
+#endif
+
+/*
+ * Initialize a new pgd / pmd table with invalid pointers.
+ */
+extern void pgd_init(unsigned long page);
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        pgd_t *ret, *init;
+
+        ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
+        if (ret) {
+                init = pgd_offset(&init_mm, 0UL);
+                pgd_init((unsigned long)ret);
+                memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
+                       (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+        }
+
+        return ret;
+}
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+        free_pages((unsigned long)pgd, PGD_ORDER);
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+        unsigned long address)
+{
+        pte_t *pte;
+
+        pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, PTE_ORDER);
+
+        return pte;
+}
+
+static inline struct page *pte_alloc_one(struct mm_struct *mm,
+        unsigned long address)
+{
+        struct page *pte;
+
+        pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER);
+        if (pte) {
+                clear_highpage(pte);
+                pgtable_page_ctor(pte);
+        }
+        return pte;
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        free_pages((unsigned long)pte, PTE_ORDER);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
+{
+        pgtable_page_dtor(pte);
+        __free_pages(pte, PTE_ORDER);
+}
+
+#define __pte_free_tlb(tlb,pte)                         \
+do {                                                    \
+        pgtable_page_dtor(pte);                         \
+        tlb_remove_page((tlb), pte);                    \
+} while (0)
+
+#ifdef CONFIG_32BIT
+
+/*
+ * allocating and freeing a pmd is trivial: the 1-entry pmd is
+ * inside the pgd, so has no extra memory associated with it.
+ */
+#define pmd_free(mm, x)                 do { } while (0)
+#define __pmd_free_tlb(tlb, x)          do { } while (0)
+
+#endif
+
+#ifdef CONFIG_64BIT
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+        pmd_t *pmd;
+
+        pmd = (pmd_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, PMD_ORDER);
+        if (pmd)
+                pmd_init((unsigned long)pmd, (unsigned long)invalid_pte_table);
+        return pmd;
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+        free_pages((unsigned long)pmd, PMD_ORDER);
+}
+
+#define __pmd_free_tlb(tlb, x)  pmd_free((tlb)->mm, x)
+
+#endif
+
+#define check_pgt_cache()       do { } while (0)
+
+extern void pagetable_init(void);
+
+#endif /* _ASM_PGALLOC_H */
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
new file mode 100644
index 000000000000..55813d6150c7
--- /dev/null
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -0,0 +1,234 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGTABLE_32_H
+#define _ASM_PGTABLE_32_H
+
+#include <asm/addrspace.h>
+#include <asm/page.h>
+
+#include <linux/linkage.h>
+#include <asm/cachectl.h>
+#include <asm/fixmap.h>
+
+#include <asm-generic/pgtable-nopmd.h>
+
+/*
+ * - add_wired_entry() add a fixed TLB entry, and move wired register
+ */
+extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
+                               unsigned long entryhi, unsigned long pagemask);
+
+/*
+ * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
+ *      starting at the top and working down. This is for populating the
+ *      TLB before trap_init() puts the TLB miss handler in place. It
+ *      should be used only for entries matching the actual page tables,
+ *      to prevent inconsistencies.
+ */
+extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
+                               unsigned long entryhi, unsigned long pagemask);
+
+
+/* Basically we have the same two-level (which is the logical three level
+ * Linux page table layout folded) page tables as the i386.  Some day
+ * when we have proper page coloring support we can have a 1% quicker
+ * tlb refill handling mechanism, but for now it is a bit slower but
+ * works even with the cache aliasing problem the R4k and above have.
+ */
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT     (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * Entries per page directory level: we use two-level, so
+ * we don't really have any PUD/PMD directory physically.
+ */
+#define __PGD_ORDER     (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
+#define PGD_ORDER       (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
+#define PUD_ORDER       aieeee_attempt_to_allocate_pud
+#define PMD_ORDER       1
+#define PTE_ORDER       0
+
+#define PTRS_PER_PGD    (USER_PTRS_PER_PGD * 2)
+#define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+
+#define USER_PTRS_PER_PGD       (0x80000000UL/PGDIR_SIZE)
+#define FIRST_USER_ADDRESS      0
+
+#define VMALLOC_START     MAP_BASE
+
+#define PKMAP_BASE              (0xfe000000UL)
+
+#ifdef CONFIG_HIGHMEM
+# define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
+#else
+# define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
+#endif
+
+#ifdef CONFIG_64BIT_PHYS_ADDR
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
+#else
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#endif
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+extern void load_pgd(unsigned long pg_dir);
+
+extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
+
+/*
+ * Empty pgd/pmd entries point to the invalid_pte_table.
+ */
+static inline int pmd_none(pmd_t pmd)
+{
+        return pmd_val(pmd) == (unsigned long) invalid_pte_table;
+}
+
+#define pmd_bad(pmd)            (pmd_val(pmd) & ~PAGE_MASK)
+
+static inline int pmd_present(pmd_t pmd)
+{
+        return pmd_val(pmd) != (unsigned long) invalid_pte_table;
+}
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
+}
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+#define pte_pfn(x)              ((unsigned long)((x).pte_high >> 6))
+static inline pte_t
+pfn_pte(unsigned long pfn, pgprot_t prot)
+{
+        pte_t pte;
+        pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
+        pte.pte_low = pgprot_val(prot);
+        return pte;
+}
+
+#else
+
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#ifdef CONFIG_CPU_VR41XX
+#define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
+#else
+#define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
+#define pfn_pte(pfn, prot)      __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#endif
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
+
+#define __pgd_offset(address)   pgd_index(address)
+#define __pud_offset(address)   (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+#define __pmd_offset(address)   (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+
+/* to find an entry in a page-table-directory */
+#define pgd_offset(mm, addr)    ((mm)->pgd + pgd_index(addr))
+
+/* Find an entry in the third-level page table.. */
+#define __pte_offset(address)                                           \
+        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset(dir, address)                                        \
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
+#define pte_offset_kernel(dir, address)                                 \
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
+
+#define pte_offset_map(dir, address)                                    \
+        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
+#define pte_offset_map_nested(dir, address)                             \
+        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
+#define pte_unmap(pte) ((void)(pte))
+#define pte_unmap_nested(pte) ((void)(pte))
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+/* Swap entries must have VALID bit cleared. */
+#define __swp_type(x)           (((x).val >> 10) & 0x1f)
+#define __swp_offset(x)         ((x).val >> 15)
+#define __swp_entry(type,offset)        \
+        ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
+
+/*
+ * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
+ */
+#define PTE_FILE_MAX_BITS       28
+
+#define pte_to_pgoff(_pte)      ((((_pte).pte >> 1 ) & 0x07) | \
+                                 (((_pte).pte >> 2 ) & 0x38) | \
+                                 (((_pte).pte >> 10) <<  6 ))
+
+#define pgoff_to_pte(off)       ((pte_t) { (((off) & 0x07) << 1 ) | \
+                                           (((off) & 0x38) << 2 ) | \
+                                           (((off) >>  6 ) << 10) | \
+                                           _PAGE_FILE })
+
+#else
+
+/* Swap entries must have VALID and GLOBAL bits cleared. */
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define __swp_type(x)           (((x).val >> 2) & 0x1f)
+#define __swp_offset(x)          ((x).val >> 7)
+#define __swp_entry(type,offset)        \
+                ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
+#else
+#define __swp_type(x)           (((x).val >> 8) & 0x1f)
+#define __swp_offset(x)          ((x).val >> 13)
+#define __swp_entry(type,offset)        \
+                ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+/*
+ * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
+ */
+#define PTE_FILE_MAX_BITS       30
+
+#define pte_to_pgoff(_pte)      ((_pte).pte_high >> 2)
+#define pgoff_to_pte(off)       ((pte_t) { _PAGE_FILE, (off) << 2 })
+
+#else
+/*
+ * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
+ */
+#define PTE_FILE_MAX_BITS       28
+
+#define pte_to_pgoff(_pte)      ((((_pte).pte >> 1) & 0x7) | \
+                                 (((_pte).pte >> 2) & 0x8) | \
+                                 (((_pte).pte >> 8) <<  4))
+
+#define pgoff_to_pte(off)       ((pte_t) { (((off) & 0x7) << 1) | \
+                                           (((off) & 0x8) << 2) | \
+                                           (((off) >>  4) << 8) | \
+                                           _PAGE_FILE })
+#endif
+
+#endif
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
+#define __swp_entry_to_pte(x)   ((pte_t) { 0, (x).val })
+#else
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
+#endif
+
+#endif /* _ASM_PGTABLE_32_H */
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
new file mode 100644
index 000000000000..943515f0ef87
--- /dev/null
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -0,0 +1,253 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PGTABLE_64_H
+#define _ASM_PGTABLE_64_H
+
+#include <linux/linkage.h>
+
+#include <asm/addrspace.h>
+#include <asm/page.h>
+#include <asm/cachectl.h>
+#include <asm/fixmap.h>
+
+#include <asm-generic/pgtable-nopud.h>
+
+/*
+ * Each address space has 2 4K pages as its page directory, giving 1024
+ * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
+ * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
+ * tables. Each page table is also a single 4K page, giving 512 (==
+ * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
+ * invalid_pmd_table, each pmd entry is initialized to point to
+ * invalid_pte_table, each pte is initialized to 0. When memory is low,
+ * and a pmd table or a page table allocation fails, empty_bad_pmd_table
+ * and empty_bad_page_table is returned back to higher layer code, so
+ * that the failure is recognized later on. Linux does not seem to
+ * handle these failures very well though. The empty_bad_page_table has
+ * invalid pte entries in it, to force page faults.
+ *
+ * Kernel mappings: kernel mappings are held in the swapper_pg_table.
+ * The layout is identical to userspace except it's indexed with the
+ * fault address - VMALLOC_START.
+ */
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT     (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * For 4kB page size we use a 3 level page tree and an 8kB pud, which
+ * permits us mapping 40 bits of virtual address space.
+ *
+ * We used to implement 41 bits by having an order 1 pmd level but that seemed
+ * rather pointless.
+ *
+ * For 8kB page size we use a 3 level page tree which permits a total of
+ * 8TB of address space.  Alternatively a 33-bit / 8GB organization using
+ * two levels would be easy to implement.
+ *
+ * For 16kB page size we use a 2 level page tree which permits a total of
+ * 36 bits of virtual address space.  We could add a third level but it seems
+ * like at the moment there's no need for this.
+ *
+ * For 64kB page size we use a 2 level page table tree for a total of 42 bits
+ * of virtual address space.
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PGD_ORDER               1
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define PGD_ORDER               0
+#define PUD_ORDER               aieeee_attempt_to_allocate_pud
+#define PMD_ORDER               0
+#define PTE_ORDER               0
+#endif
+
+#define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
+#define PTRS_PER_PMD    ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
+#define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+
+#if PGDIR_SIZE >= TASK_SIZE
+#define USER_PTRS_PER_PGD       (1)
+#else
+#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
+#endif
+#define FIRST_USER_ADDRESS      0UL
+
+#define VMALLOC_START           MAP_BASE
+#define VMALLOC_END     \
+        (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
+#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
+        VMALLOC_START != CKSSEG
+/* Load modules into 32bit-compatible segment. */
+#define MODULE_START    CKSSEG
+#define MODULE_END      (FIXADDR_START-2*PAGE_SIZE)
+extern pgd_t module_pg_dir[PTRS_PER_PGD];
+#endif
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+        printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+extern pte_t invalid_pte_table[PTRS_PER_PTE];
+extern pte_t empty_bad_page_table[PTRS_PER_PTE];
+extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
+extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
+
+/*
+ * Empty pgd/pmd entries point to the invalid_pte_table.
+ */
+static inline int pmd_none(pmd_t pmd)
+{
+        return pmd_val(pmd) == (unsigned long) invalid_pte_table;
+}
+
+#define pmd_bad(pmd)            (pmd_val(pmd) & ~PAGE_MASK)
+
+static inline int pmd_present(pmd_t pmd)
+{
+        return pmd_val(pmd) != (unsigned long) invalid_pte_table;
+}
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
+}
+
+/*
+ * Empty pud entries point to the invalid_pmd_table.
+ */
+static inline int pud_none(pud_t pud)
+{
+        return pud_val(pud) == (unsigned long) invalid_pmd_table;
+}
+
+static inline int pud_bad(pud_t pud)
+{
+        return pud_val(pud) & ~PAGE_MASK;
+}
+
+static inline int pud_present(pud_t pud)
+{
+        return pud_val(pud) != (unsigned long) invalid_pmd_table;
+}
+
+static inline void pud_clear(pud_t *pudp)
+{
+        pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
+}
+
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#ifdef CONFIG_CPU_VR41XX
+#define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
+#else
+#define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#endif
+
+#define __pgd_offset(address)   pgd_index(address)
+#define __pud_offset(address)   (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+#define __pmd_offset(address)   pmd_index(address)
+
+/* to find an entry in a kernel page-table-directory */
+#ifdef MODULE_START
+#define pgd_offset_k(address) \
+        ((address) >= MODULE_START ? module_pg_dir : pgd_offset(&init_mm, 0UL))
+#else
+#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL)
+#endif
+
+#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pmd_index(address)      (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
+
+/* to find an entry in a page-table-directory */
+#define pgd_offset(mm, addr)    ((mm)->pgd + pgd_index(addr))
+
+static inline unsigned long pud_page_vaddr(pud_t pud)
+{
+        return pud_val(pud);
+}
+#define pud_phys(pud)           virt_to_phys((void *)pud_val(pud))
+#define pud_page(pud)           (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))
+
+/* Find an entry in the second-level page table.. */
+static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
+{
+        return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address);
+}
+
+/* Find an entry in the third-level page table.. */
+#define __pte_offset(address)                                           \
+        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset(dir, address)                                        \
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
+#define pte_offset_kernel(dir, address)                                 \
+        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
+#define pte_offset_map(dir, address)                                    \
+        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
+#define pte_offset_map_nested(dir, address)                             \
+        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
+#define pte_unmap(pte) ((void)(pte))
+#define pte_unmap_nested(pte) ((void)(pte))
+
+/*
+ * Initialize a new pgd / pmd table with invalid pointers.
+ */
+extern void pgd_init(unsigned long page);
+extern void pmd_init(unsigned long page, unsigned long pagetable);
+
+/*
+ * Non-present pages:  high 24 bits are offset, next 8 bits type,
+ * low 32 bits zero.
+ */
+static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
+{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
+
+#define __swp_type(x)           (((x).val >> 32) & 0xff)
+#define __swp_offset(x)         ((x).val >> 40)
+#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
+
+/*
+ * Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
+ * make things easier, and only use the upper 56 bits for the page offset...
+ */
+#define PTE_FILE_MAX_BITS       56
+
+#define pte_to_pgoff(_pte)      ((_pte).pte >> 8)
+#define pgoff_to_pte(off)       ((pte_t) { ((off) << 8) | _PAGE_FILE })
+
+#endif /* _ASM_PGTABLE_64_H */
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
new file mode 100644
index 000000000000..51b34a48c84a
--- /dev/null
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -0,0 +1,137 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 2002 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+#ifndef _ASM_PGTABLE_BITS_H
+#define _ASM_PGTABLE_BITS_H
+
+
+/*
+ * Note that we shift the lower 32bits of each EntryLo[01] entry
+ * 6 bits to the left. That way we can convert the PFN into the
+ * physical address by a single 'and' operation and gain 6 additional
+ * bits for storing information which isn't present in a normal
+ * MIPS page table.
+ *
+ * Similar to the Alpha port, we need to keep track of the ref
+ * and mod bits in software.  We have a software "yeah you can read
+ * from this page" bit, and a hardware one which actually lets the
+ * process read from the page.  On the same token we have a software
+ * writable bit and the real hardware one which actually lets the
+ * process write to the page, this keeps a mod bit via the hardware
+ * dirty bit.
+ *
+ * Certain revisions of the R4000 and R5000 have a bug where if a
+ * certain sequence occurs in the last 3 instructions of an executable
+ * page, and the following page is not mapped, the cpu can do
+ * unpredictable things.  The code (when it is written) to deal with
+ * this problem will be in the update_mmu_cache() code for the r4k.
+ */
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+
+#define _PAGE_PRESENT               (1<<6)  /* implemented in software */
+#define _PAGE_READ                  (1<<7)  /* implemented in software */
+#define _PAGE_WRITE                 (1<<8)  /* implemented in software */
+#define _PAGE_ACCESSED              (1<<9)  /* implemented in software */
+#define _PAGE_MODIFIED              (1<<10) /* implemented in software */
+#define _PAGE_FILE                  (1<<10) /* set:pagecache unset:swap */
+
+#define _PAGE_R4KBUG                (1<<0)  /* workaround for r4k bug  */
+#define _PAGE_GLOBAL                (1<<0)
+#define _PAGE_VALID                 (1<<1)
+#define _PAGE_SILENT_READ           (1<<1)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<2)  /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<2)
+#define _CACHE_SHIFT                3
+#define _CACHE_MASK                 (7<<3)
+
+#else
+
+#define _PAGE_PRESENT               (1<<0)  /* implemented in software */
+#define _PAGE_READ                  (1<<1)  /* implemented in software */
+#define _PAGE_WRITE                 (1<<2)  /* implemented in software */
+#define _PAGE_ACCESSED              (1<<3)  /* implemented in software */
+#define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
+#define _PAGE_FILE                  (1<<4)  /* set:pagecache unset:swap */
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+#define _PAGE_GLOBAL                (1<<8)
+#define _PAGE_VALID                 (1<<9)
+#define _PAGE_SILENT_READ           (1<<9)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<10) /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<10)
+#define _CACHE_UNCACHED             (1<<11)
+#define _CACHE_MASK                 (1<<11)
+
+#else
+
+#define _PAGE_R4KBUG                (1<<5)  /* workaround for r4k bug  */
+#define _PAGE_GLOBAL                (1<<6)
+#define _PAGE_VALID                 (1<<7)
+#define _PAGE_SILENT_READ           (1<<7)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<8)  /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<8)
+#define _CACHE_SHIFT                9
+#define _CACHE_MASK                 (7<<9)
+
+#endif
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
+
+
+/*
+ * Cache attributes
+ */
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+#define _CACHE_CACHABLE_NONCOHERENT 0
+
+#elif defined(CONFIG_CPU_SB1)
+
+/* No penalty for being coherent on the SB1, so just
+   use it for "noncoherent" spaces, too.  Shouldn't hurt. */
+
+#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)
+#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)
+#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
+
+#elif defined(CONFIG_CPU_RM9000)
+
+#define _CACHE_WT                   (0<<_CACHE_SHIFT)
+#define _CACHE_WTWA                 (1<<_CACHE_SHIFT)
+#define _CACHE_UC_B                 (2<<_CACHE_SHIFT)
+#define _CACHE_WB                   (3<<_CACHE_SHIFT)
+#define _CACHE_CWBEA                (4<<_CACHE_SHIFT)
+#define _CACHE_CWB                  (5<<_CACHE_SHIFT)
+#define _CACHE_UCNB                 (6<<_CACHE_SHIFT)
+#define _CACHE_FPC                  (7<<_CACHE_SHIFT)
+
+#define _CACHE_UNCACHED             _CACHE_UC_B
+#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
+
+#else
+
+#define _CACHE_CACHABLE_NO_WA       (0<<_CACHE_SHIFT)  /* R4600 only      */
+#define _CACHE_CACHABLE_WA          (1<<_CACHE_SHIFT)  /* R4600 only      */
+#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)  /* R4[0246]00      */
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* R4[0246]00      */
+#define _CACHE_CACHABLE_CE          (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
+#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
+#define _CACHE_CACHABLE_COHERENT    (5<<_CACHE_SHIFT)  /* MIPS32R2 CMP    */
+#define _CACHE_CACHABLE_CUW         (6<<_CACHE_SHIFT)  /* R4[04]00MC only */
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* R10000 only     */
+
+#endif
+
+#define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
+#define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
+
+#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
new file mode 100644
index 000000000000..6a0edf72ffbc
--- /dev/null
+++ b/arch/mips/include/asm/pgtable.h
@@ -0,0 +1,383 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef _ASM_PGTABLE_H
+#define _ASM_PGTABLE_H
+
+#ifdef CONFIG_32BIT
+#include <asm/pgtable-32.h>
+#endif
+#ifdef CONFIG_64BIT
+#include <asm/pgtable-64.h>
+#endif
+
+#include <asm/io.h>
+#include <asm/pgtable-bits.h>
+
+struct mm_struct;
+struct vm_area_struct;
+
+#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+                                 _page_cachable_default)
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_READ | \
+                                 _page_cachable_default)
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_READ | \
+                                 _page_cachable_default)
+#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
+                                 _PAGE_GLOBAL | _page_cachable_default)
+#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+                                 _page_cachable_default)
+#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
+                        __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
+
+/*
+ * MIPS can't do page protection for execute, and considers that the same like
+ * read. Also, write permissions imply read permissions. This is the closest
+ * we can get by reasonable means..
+ */
+
+/*
+ * Dummy values to fill the table in mmap.c
+ * The real values will be generated at runtime
+ */
+#define __P000 __pgprot(0)
+#define __P001 __pgprot(0)
+#define __P010 __pgprot(0)
+#define __P011 __pgprot(0)
+#define __P100 __pgprot(0)
+#define __P101 __pgprot(0)
+#define __P110 __pgprot(0)
+#define __P111 __pgprot(0)
+
+#define __S000 __pgprot(0)
+#define __S001 __pgprot(0)
+#define __S010 __pgprot(0)
+#define __S011 __pgprot(0)
+#define __S100 __pgprot(0)
+#define __S101 __pgprot(0)
+#define __S110 __pgprot(0)
+#define __S111 __pgprot(0)
+
+extern unsigned long _page_cachable_default;
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero; used
+ * for zero-mapped memory areas etc..
+ */
+
+extern unsigned long empty_zero_page;
+extern unsigned long zero_page_mask;
+
+#define ZERO_PAGE(vaddr) \
+        (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
+
+extern void paging_init(void);
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define pmd_phys(pmd)           virt_to_phys((void *)pmd_val(pmd))
+#define pmd_page(pmd)           (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
+#define pmd_page_vaddr(pmd)     pmd_val(pmd)
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+
+#define pte_none(pte)           (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
+#define pte_present(pte)        ((pte).pte_low & _PAGE_PRESENT)
+
+static inline void set_pte(pte_t *ptep, pte_t pte)
+{
+        ptep->pte_high = pte.pte_high;
+        smp_wmb();
+        ptep->pte_low = pte.pte_low;
+        //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
+
+        if (pte.pte_low & _PAGE_GLOBAL) {
+                pte_t *buddy = ptep_buddy(ptep);
+                /*
+                 * Make sure the buddy is global too (if it's !none,
+                 * it better already be global)
+                 */
+                if (pte_none(*buddy)) {
+                        buddy->pte_low  |= _PAGE_GLOBAL;
+                        buddy->pte_high |= _PAGE_GLOBAL;
+                }
+        }
+}
+#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+        pte_t null = __pte(0);
+
+        /* Preserve global status for the pair */
+        if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
+                null.pte_low = null.pte_high = _PAGE_GLOBAL;
+
+        set_pte_at(mm, addr, ptep, null);
+}
+#else
+
+#define pte_none(pte)           (!(pte_val(pte) & ~_PAGE_GLOBAL))
+#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
+
+/*
+ * Certain architectures need to do special things when pte's
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+static inline void set_pte(pte_t *ptep, pte_t pteval)
+{
+        *ptep = pteval;
+#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+        if (pte_val(pteval) & _PAGE_GLOBAL) {
+                pte_t *buddy = ptep_buddy(ptep);
+                /*
+                 * Make sure the buddy is global too (if it's !none,
+                 * it better already be global)
+                 */
+                if (pte_none(*buddy))
+                        pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL;
+        }
+#endif
+}
+#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+        /* Preserve global status for the pair */
+        if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
+                set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
+        else
+#endif
+                set_pte_at(mm, addr, ptep, __pte(0));
+}
+#endif
+
+/*
+ * (pmds are folded into puds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
+
+#ifdef CONFIG_64BIT
+/*
+ * (puds are folded into pgds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
+#endif
+
+#define PGD_T_LOG2      (__builtin_ffs(sizeof(pgd_t)) - 1)
+#define PMD_T_LOG2      (__builtin_ffs(sizeof(pmd_t)) - 1)
+#define PTE_T_LOG2      (__builtin_ffs(sizeof(pte_t)) - 1)
+
+/*
+ * We used to declare this array with size but gcc 3.3 and older are not able
+ * to find that this expression is a constant, so the size is dropped.
+ */
+extern pgd_t swapper_pg_dir[];
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+static inline int pte_write(pte_t pte)  { return pte.pte_low & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte)  { return pte.pte_low & _PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte)  { return pte.pte_low & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)   { return pte.pte_low & _PAGE_FILE; }
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        pte.pte_low  &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+        pte.pte_high &= ~_PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        pte.pte_low  &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
+        pte.pte_high &= ~_PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+        pte.pte_low  &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
+        pte.pte_high &= ~_PAGE_SILENT_READ;
+        return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        pte.pte_low |= _PAGE_WRITE;
+        if (pte.pte_low & _PAGE_MODIFIED) {
+                pte.pte_low  |= _PAGE_SILENT_WRITE;
+                pte.pte_high |= _PAGE_SILENT_WRITE;
+        }
+        return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        pte.pte_low |= _PAGE_MODIFIED;
+        if (pte.pte_low & _PAGE_WRITE) {
+                pte.pte_low  |= _PAGE_SILENT_WRITE;
+                pte.pte_high |= _PAGE_SILENT_WRITE;
+        }
+        return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        pte.pte_low |= _PAGE_ACCESSED;
+        if (pte.pte_low & _PAGE_READ) {
+                pte.pte_low  |= _PAGE_SILENT_READ;
+                pte.pte_high |= _PAGE_SILENT_READ;
+        }
+        return pte;
+}
+#else
+static inline int pte_write(pte_t pte)  { return pte_val(pte) & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte)  { return pte_val(pte) & _PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte)  { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)   { return pte_val(pte) & _PAGE_FILE; }
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+        return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
+        return pte;
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+        pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
+        return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_WRITE;
+        if (pte_val(pte) & _PAGE_MODIFIED)
+                pte_val(pte) |= _PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_MODIFIED;
+        if (pte_val(pte) & _PAGE_WRITE)
+                pte_val(pte) |= _PAGE_SILENT_WRITE;
+        return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_ACCESSED;
+        if (pte_val(pte) & _PAGE_READ)
+                pte_val(pte) |= _PAGE_SILENT_READ;
+        return pte;
+}
+#endif
+static inline int pte_special(pte_t pte)        { return 0; }
+static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
+
+/*
+ * Macro to make mark a page protection value as "uncacheable".  Note
+ * that "protection" is really a misnomer here as the protection value
+ * contains the memory attribute bits, dirty bits, and various other
+ * bits as well.
+ */
+#define pgprot_noncached pgprot_noncached
+
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+        unsigned long prot = pgprot_val(_prot);
+
+        prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
+
+        return __pgprot(prot);
+}
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
+
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte.pte_low  &= _PAGE_CHG_MASK;
+        pte.pte_high &= ~0x3f;
+        pte.pte_low  |= pgprot_val(newprot);
+        pte.pte_high |= pgprot_val(newprot) & 0x3f;
+        return pte;
+}
+#else
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
+}
+#endif
+
+
+extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
+        pte_t pte);
+extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
+        pte_t pte);
+
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+        unsigned long address, pte_t pte)
+{
+        __update_tlb(vma, address, pte);
+        __update_cache(vma, address, pte);
+}
+
+#define kern_addr_valid(addr)   (1)
+
+#ifdef CONFIG_64BIT_PHYS_ADDR
+extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
+
+static inline int io_remap_pfn_range(struct vm_area_struct *vma,
+                unsigned long vaddr,
+                unsigned long pfn,
+                unsigned long size,
+                pgprot_t prot)
+{
+        phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
+        return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
+}
+#else
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+#endif
+
+#include <asm-generic/pgtable.h>
+
+/*
+ * We provide our own get_unmapped area to cope with the virtual aliasing
+ * constraints placed on us by the cache architecture.
+ */
+#define HAVE_ARCH_UNMAPPED_AREA
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+#endif /* _ASM_PGTABLE_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h b/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h
new file mode 100644
index 000000000000..ebdbab973e41
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h
@@ -0,0 +1,46 @@
+/*
+ * include/asm-mips/pmc-sierra/msp71xx/gpio.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * @author Patrick Glass <patrickglass@gmail.com>
+ */
+
+#ifndef __PMC_MSP71XX_GPIO_H
+#define __PMC_MSP71XX_GPIO_H
+
+/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */
+#define ARCH_NR_GPIOS (28 + (3 * 8))
+
+/* new generic GPIO API - see Documentation/gpio.txt */
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+
+/* Setup calls for the gpio and gpio extended */
+extern void msp71xx_init_gpio(void);
+extern void msp71xx_init_gpio_extended(void);
+extern int msp71xx_set_output_drive(unsigned gpio, int value);
+
+/* Custom output drive functionss */
+static inline int gpio_set_output_drive(unsigned gpio, int value)
+{
+        return msp71xx_set_output_drive(gpio, value);
+}
+
+/* IRQ's are not supported for gpio lines */
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+        return -EINVAL;
+}
+
+#endif /* __PMC_MSP71XX_GPIO_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h
new file mode 100644
index 000000000000..c84bcf9570b1
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h
@@ -0,0 +1,151 @@
+/*
+ * Defines for the MSP interrupt controller.
+ *
+ * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ * Author: Carsten Langgaard, carstenl@mips.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+
+#ifndef _MSP_CIC_INT_H
+#define _MSP_CIC_INT_H
+
+/*
+ * The PMC-Sierra CIC interrupts are all centrally managed by the
+ * CIC sub-system.
+ * We attempt to keep the interrupt numbers as consistent as possible
+ * across all of the MSP devices, but some differences will creep in ...
+ * The interrupts which are directly forwarded to the MIPS core interrupts
+ * are assigned interrupts in the range 0-7, interrupts cascaded through
+ * the CIC are assigned interrupts 8-39.  The cascade occurs on C_IRQ4
+ * (MSP_INT_CIC).  Currently we don't really distinguish between VPE1
+ * and VPE0 (or thread contexts for that matter).  Will have to fix.
+ * The PER interrupts are assigned interrupts in the range 40-71.
+*/
+
+
+/*
+ * IRQs directly forwarded to the CPU
+ */
+#define MSP_MIPS_INTBASE        0
+#define MSP_INT_SW0             0       /* IRQ for swint0,       C_SW0  */
+#define MSP_INT_SW1             1       /* IRQ for swint1,       C_SW1  */
+#define MSP_INT_MAC0            2       /* IRQ for MAC 0,        C_IRQ0 */
+#define MSP_INT_MAC1            3       /* IRQ for MAC 1,        C_IRQ1 */
+#define MSP_INT_USB             4       /* IRQ for USB,          C_IRQ2 */
+#define MSP_INT_SAR             5       /* IRQ for ADSL2+ SAR,   C_IRQ3 */
+#define MSP_INT_CIC             6       /* IRQ for CIC block,    C_IRQ4 */
+#define MSP_INT_SEC             7       /* IRQ for Sec engine,   C_IRQ5 */
+
+/*
+ * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
+ * These defines should be tied to the register definitions for the CIC
+ * interrupt routine.  For now, just use hard-coded values.
+ */
+#define MSP_CIC_INTBASE         (MSP_MIPS_INTBASE + 8)
+#define MSP_INT_EXT0            (MSP_CIC_INTBASE + 0)
+                                        /* External interrupt 0         */
+#define MSP_INT_EXT1            (MSP_CIC_INTBASE + 1)
+                                        /* External interrupt 1         */
+#define MSP_INT_EXT2            (MSP_CIC_INTBASE + 2)
+                                        /* External interrupt 2         */
+#define MSP_INT_EXT3            (MSP_CIC_INTBASE + 3)
+                                        /* External interrupt 3         */
+#define MSP_INT_CPUIF           (MSP_CIC_INTBASE + 4)
+                                        /* CPU interface interrupt      */
+#define MSP_INT_EXT4            (MSP_CIC_INTBASE + 5)
+                                        /* External interrupt 4         */
+#define MSP_INT_CIC_USB         (MSP_CIC_INTBASE + 6)
+                                        /* Cascaded IRQ for USB         */
+#define MSP_INT_MBOX            (MSP_CIC_INTBASE + 7)
+                                        /* Sec engine mailbox IRQ       */
+#define MSP_INT_EXT5            (MSP_CIC_INTBASE + 8)
+                                        /* External interrupt 5         */
+#define MSP_INT_TDM             (MSP_CIC_INTBASE + 9)
+                                        /* TDM interrupt                */
+#define MSP_INT_CIC_MAC0        (MSP_CIC_INTBASE + 10)
+                                        /* Cascaded IRQ for MAC 0       */
+#define MSP_INT_CIC_MAC1        (MSP_CIC_INTBASE + 11)
+                                        /* Cascaded IRQ for MAC 1       */
+#define MSP_INT_CIC_SEC         (MSP_CIC_INTBASE + 12)
+                                        /* Cascaded IRQ for sec engine  */
+#define MSP_INT_PER             (MSP_CIC_INTBASE + 13)
+                                        /* Peripheral interrupt         */
+#define MSP_INT_TIMER0          (MSP_CIC_INTBASE + 14)
+                                        /* SLP timer 0                  */
+#define MSP_INT_TIMER1          (MSP_CIC_INTBASE + 15)
+                                        /* SLP timer 1                  */
+#define MSP_INT_TIMER2          (MSP_CIC_INTBASE + 16)
+                                        /* SLP timer 2                  */
+#define MSP_INT_VPE0_TIMER      (MSP_CIC_INTBASE + 17)
+                                        /* VPE0 MIPS timer              */
+#define MSP_INT_BLKCP           (MSP_CIC_INTBASE + 18)
+                                        /* Block Copy                   */
+#define MSP_INT_UART0           (MSP_CIC_INTBASE + 19)
+                                        /* UART 0                       */
+#define MSP_INT_PCI             (MSP_CIC_INTBASE + 20)
+                                        /* PCI subsystem                */
+#define MSP_INT_EXT6            (MSP_CIC_INTBASE + 21)
+                                        /* External interrupt 5         */
+#define MSP_INT_PCI_MSI         (MSP_CIC_INTBASE + 22)
+                                        /* PCI Message Signal           */
+#define MSP_INT_CIC_SAR         (MSP_CIC_INTBASE + 23)
+                                        /* Cascaded ADSL2+ SAR IRQ      */
+#define MSP_INT_DSL             (MSP_CIC_INTBASE + 24)
+                                        /* ADSL2+ IRQ                   */
+#define MSP_INT_CIC_ERR         (MSP_CIC_INTBASE + 25)
+                                        /* SLP error condition          */
+#define MSP_INT_VPE1_TIMER      (MSP_CIC_INTBASE + 26)
+                                        /* VPE1 MIPS timer              */
+#define MSP_INT_VPE0_PC         (MSP_CIC_INTBASE + 27)
+                                        /* VPE0 Performance counter     */
+#define MSP_INT_VPE1_PC         (MSP_CIC_INTBASE + 28)
+                                        /* VPE1 Performance counter     */
+#define MSP_INT_EXT7            (MSP_CIC_INTBASE + 29)
+                                        /* External interrupt 5         */
+#define MSP_INT_VPE0_SW         (MSP_CIC_INTBASE + 30)
+                                        /* VPE0 Software interrupt      */
+#define MSP_INT_VPE1_SW         (MSP_CIC_INTBASE + 31)
+                                        /* VPE0 Software interrupt      */
+
+/*
+ * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
+ */
+#define MSP_PER_INTBASE         (MSP_CIC_INTBASE + 32)
+/* Reserved                                        0-1                  */
+#define MSP_INT_UART1           (MSP_PER_INTBASE + 2)
+                                        /* UART 1                       */
+/* Reserved                                        3-5                  */
+#define MSP_INT_2WIRE           (MSP_PER_INTBASE + 6)
+                                        /* 2-wire                       */
+#define MSP_INT_TM0             (MSP_PER_INTBASE + 7)
+                                        /* Peripheral timer block out 0 */
+#define MSP_INT_TM1             (MSP_PER_INTBASE + 8)
+                                        /* Peripheral timer block out 1 */
+/* Reserved                                        9                    */
+#define MSP_INT_SPRX            (MSP_PER_INTBASE + 10)
+                                        /* SPI RX complete              */
+#define MSP_INT_SPTX            (MSP_PER_INTBASE + 11)
+                                        /* SPI TX complete              */
+#define MSP_INT_GPIO            (MSP_PER_INTBASE + 12)
+                                        /* GPIO                         */
+#define MSP_INT_PER_ERR         (MSP_PER_INTBASE + 13)
+                                        /* Peripheral error             */
+/* Reserved                                        14-31                */
+
+#endif /* !_MSP_CIC_INT_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h
new file mode 100644
index 000000000000..1d9f05474820
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h
@@ -0,0 +1,43 @@
+/*
+ * Defines for the MSP interrupt handlers.
+ *
+ * Copyright (C) 2005, PMC-Sierra, Inc.  All rights reserved.
+ * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+
+#ifndef _MSP_INT_H
+#define _MSP_INT_H
+
+/*
+ * The PMC-Sierra MSP product line has at least two different interrupt
+ * controllers, the SLP register based scheme and the CIC interrupt
+ * controller block mechanism.  This file distinguishes between them
+ * so that devices see a uniform interface.
+ */
+
+#if defined(CONFIG_IRQ_MSP_SLP)
+        #include "msp_slp_int.h"
+#elif defined(CONFIG_IRQ_MSP_CIC)
+        #include "msp_cic_int.h"
+#else
+        #error "What sort of interrupt controller does *your* MSP have?"
+#endif
+
+#endif /* !_MSP_INT_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h
new file mode 100644
index 000000000000..415606903617
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2000-2006 PMC-Sierra INC.
+ *
+ *     This program is free software; you can redistribute it
+ *     and/or modify it under the terms of the GNU General
+ *     Public License as published by the Free Software
+ *     Foundation; either version 2 of the License, or (at your
+ *     option) any later version.
+ *
+ *     This program is distributed in the hope that it will be
+ *     useful, but WITHOUT ANY WARRANTY; without even the implied
+ *     warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ *     PURPOSE.  See the GNU General Public License for more
+ *     details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this program; if not, write to the Free
+ *     Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ *     02139, USA.
+ *
+ * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
+ * SOFTWARE.
+ */
+
+#ifndef _MSP_PCI_H_
+#define _MSP_PCI_H_
+
+#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
+
+/*
+ * It is convenient to program the OATRAN register so that
+ * Athena virtual address space and PCI address space are
+ * the same. This is not a requirement, just a convenience.
+ *
+ * The only hard restrictions on the value of OATRAN is that
+ * OATRAN must not be programmed to allow translated memory
+ * addresses to fall within the lowest 512MB of
+ * PCI address space. This region is hardcoded
+ * for use as Athena PCI Host Controller target
+ * access memory space to the Athena's SDRAM.
+ *
+ * Note that OATRAN applies only to memory accesses, not
+ * to I/O accesses.
+ *
+ * To program OATRAN to make Athena virtual address space
+ * and PCI address space have the same values, OATRAN
+ * is to be programmed to 0xB8000000. The top seven
+ * bits of the value mimic the seven bits clipped off
+ * by the PCI Host controller.
+ *
+ * With OATRAN at the said value, when the CPU does
+ * an access to its virtual address at, say 0xB900_5000,
+ * the address appearing on the PCI bus will be
+ * 0xB900_5000.
+ *    - Michael Penner
+ */
+#define MSP_PCI_OATRAN          0xB8000000UL
+
+#define MSP_PCI_SPACE_BASE      (MSP_PCI_OATRAN + 0x1002000UL)
+#define MSP_PCI_SPACE_SIZE      (0x3000000UL - 0x2000)
+#define MSP_PCI_SPACE_END \
+                (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
+#define MSP_PCI_IOSPACE_BASE    (MSP_PCI_OATRAN + 0x1001000UL)
+#define MSP_PCI_IOSPACE_SIZE    0x1000
+#define MSP_PCI_IOSPACE_END  \
+                (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
+
+/* IRQ for PCI status interrupts */
+#define PCI_STAT_IRQ    20
+
+#define QFLUSH_REG_1    0xB7F40000
+
+typedef volatile unsigned int pcireg;
+typedef void * volatile ppcireg;
+
+struct pci_block_copy
+{
+    pcireg   unused1; /* +0x00 */
+    pcireg   unused2; /* +0x04 */
+    ppcireg  unused3; /* +0x08 */
+    ppcireg  unused4; /* +0x0C */
+    pcireg   unused5; /* +0x10 */
+    pcireg   unused6; /* +0x14 */
+    pcireg   unused7; /* +0x18 */
+    ppcireg  unused8; /* +0x1C */
+    ppcireg  unused9; /* +0x20 */
+    pcireg   unusedA; /* +0x24 */
+    ppcireg  unusedB; /* +0x28 */
+    ppcireg  unusedC; /* +0x2C */
+};
+
+enum
+{
+    config_device_vendor,  /* 0 */
+    config_status_command, /* 1 */
+    config_class_revision, /* 2 */
+    config_BIST_header_latency_cache, /* 3 */
+    config_BAR0,           /* 4 */
+    config_BAR1,           /* 5 */
+    config_BAR2,           /* 6 */
+    config_not_used7,      /* 7 */
+    config_not_used8,      /* 8 */
+    config_not_used9,      /* 9 */
+    config_CIS,            /* 10 */
+    config_subsystem,      /* 11 */
+    config_not_used12,     /* 12 */
+    config_capabilities,   /* 13 */
+    config_not_used14,     /* 14 */
+    config_lat_grant_irq,  /* 15 */
+    config_message_control,/* 16 */
+    config_message_addr,   /* 17 */
+    config_message_data,   /* 18 */
+    config_VPD_addr,       /* 19 */
+    config_VPD_data,       /* 20 */
+    config_maxregs         /* 21 - number of registers */
+};
+
+struct msp_pci_regs
+{
+    pcireg hop_unused_00; /* +0x00 */
+    pcireg hop_unused_04; /* +0x04 */
+    pcireg hop_unused_08; /* +0x08 */
+    pcireg hop_unused_0C; /* +0x0C */
+    pcireg hop_unused_10; /* +0x10 */
+    pcireg hop_unused_14; /* +0x14 */
+    pcireg hop_unused_18; /* +0x18 */
+    pcireg hop_unused_1C; /* +0x1C */
+    pcireg hop_unused_20; /* +0x20 */
+    pcireg hop_unused_24; /* +0x24 */
+    pcireg hop_unused_28; /* +0x28 */
+    pcireg hop_unused_2C; /* +0x2C */
+    pcireg hop_unused_30; /* +0x30 */
+    pcireg hop_unused_34; /* +0x34 */
+    pcireg if_control;    /* +0x38 */
+    pcireg oatran;        /* +0x3C */
+    pcireg reset_ctl;     /* +0x40 */
+    pcireg config_addr;   /* +0x44 */
+    pcireg hop_unused_48; /* +0x48 */
+    pcireg msg_signaled_int_status; /* +0x4C */
+    pcireg msg_signaled_int_mask;   /* +0x50 */
+    pcireg if_status;     /* +0x54 */
+    pcireg if_mask;       /* +0x58 */
+    pcireg hop_unused_5C; /* +0x5C */
+    pcireg hop_unused_60; /* +0x60 */
+    pcireg hop_unused_64; /* +0x64 */
+    pcireg hop_unused_68; /* +0x68 */
+    pcireg hop_unused_6C; /* +0x6C */
+    pcireg hop_unused_70; /* +0x70 */
+
+    struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
+
+    pcireg error_hdr1; /* +0xE0 */
+    pcireg error_hdr2; /* +0xE4 */
+
+    pcireg config[config_maxregs] __attribute__((aligned(256)));
+
+};
+
+#define BPCI_CFGADDR_BUSNUM_SHF 16
+#define BPCI_CFGADDR_FUNCTNUM_SHF 8
+#define BPCI_CFGADDR_REGNUM_SHF 2
+#define BPCI_CFGADDR_ENABLE (1<<31)
+
+#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
+#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
+#define BPCI_IFCONTROL_CTO_SHF 12  /* Shift count for CTO bits */
+#define BPCI_IFCONTROL_SE  (1<<5)  /* Enable exceptions on errors */
+#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
+#define BPCI_IFCONTROL_CAP (1<<3)  /* Enable capabilities */
+#define BPCI_IFCONTROL_MMC_SHF 0   /* Shift count for MMC bits */
+
+#define BPCI_IFSTATUS_MGT  (1<<8)  /* Master Grant timeout */
+#define BPCI_IFSTATUS_MTT  (1<<9)  /* Master TRDY timeout */
+#define BPCI_IFSTATUS_MRT  (1<<10) /* Master retry timeout */
+#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
+#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
+#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
+#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
+#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
+#define BPCI_IFSTATUS_RTO  (1<<18) /* Retry time out */
+#define BPCI_IFSTATUS_SER  (1<<19) /* System error */
+#define BPCI_IFSTATUS_PER  (1<<20) /* Parity error */
+#define BPCI_IFSTATUS_LCA  (1<<21) /* Local CPU abort */
+#define BPCI_IFSTATUS_MEM  (1<<22) /* Memory prot. violation */
+#define BPCI_IFSTATUS_ARB  (1<<23) /* Arbiter timed out */
+#define BPCI_IFSTATUS_STA  (1<<27) /* Signaled target abort */
+#define BPCI_IFSTATUS_TA   (1<<28) /* Target abort */
+#define BPCI_IFSTATUS_MA   (1<<29) /* Master abort */
+#define BPCI_IFSTATUS_PEI  (1<<30) /* Parity error as initiator */
+#define BPCI_IFSTATUS_PET  (1<<31) /* Parity error as target */
+
+#define BPCI_RESETCTL_PR (1<<0)    /* True if reset asserted */
+#define BPCI_RESETCTL_RT (1<<4)    /* Release time */
+#define BPCI_RESETCTL_CT (1<<8)    /* Config time */
+#define BPCI_RESETCTL_PE (1<<12)   /* PCI enabled */
+#define BPCI_RESETCTL_HM (1<<13)   /* PCI host mode */
+#define BPCI_RESETCTL_RI (1<<14)   /* PCI reset in */
+
+extern struct msp_pci_regs msp_pci_regs
+                        __attribute__((section(".register")));
+extern unsigned long msp_pci_config_space
+                        __attribute__((section(".register")));
+
+#endif /* !_MSP_PCI_H_ */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
new file mode 100644
index 000000000000..14ca7dc382a8
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -0,0 +1,176 @@
+/*
+ * MIPS boards bootprom interface for the Linux kernel.
+ *
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Author: Carsten Langgaard, carstenl@mips.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+
+#ifndef _ASM_MSP_PROM_H
+#define _ASM_MSP_PROM_H
+
+#include <linux/types.h>
+
+#define DEVICEID                        "deviceid"
+#define FEATURES                        "features"
+#define PROM_ENV                        "prom_env"
+#define PROM_ENV_FILE                   "/proc/"PROM_ENV
+#define PROM_ENV_SIZE                   256
+
+#define CPU_DEVID_FAMILY                0x0000ff00
+#define CPU_DEVID_REVISION              0x000000ff
+
+#define FPGA_IS_POLO(revision) \
+                (((revision >= 0xb0) && (revision < 0xd0)))
+#define FPGA_IS_5000(revision) \
+                ((revision >= 0x80) && (revision <= 0x90))
+#define FPGA_IS_ZEUS(revision)          ((revision < 0x7f))
+#define FPGA_IS_DUET(revision) \
+                (((revision >= 0xa0) && (revision < 0xb0)))
+#define FPGA_IS_MSP4200(revision)       ((revision >= 0xd0))
+#define FPGA_IS_MSP7100(revision)       ((revision >= 0xd0))
+
+#define MACHINE_TYPE_POLO               "POLO"
+#define MACHINE_TYPE_DUET               "DUET"
+#define MACHINE_TYPE_ZEUS               "ZEUS"
+#define MACHINE_TYPE_MSP2000REVB        "MSP2000REVB"
+#define MACHINE_TYPE_MSP5000            "MSP5000"
+#define MACHINE_TYPE_MSP4200            "MSP4200"
+#define MACHINE_TYPE_MSP7120            "MSP7120"
+#define MACHINE_TYPE_MSP7130            "MSP7130"
+#define MACHINE_TYPE_OTHER              "OTHER"
+
+#define MACHINE_TYPE_POLO_FPGA          "POLO-FPGA"
+#define MACHINE_TYPE_DUET_FPGA          "DUET-FPGA"
+#define MACHINE_TYPE_ZEUS_FPGA          "ZEUS_FPGA"
+#define MACHINE_TYPE_MSP2000REVB_FPGA   "MSP2000REVB-FPGA"
+#define MACHINE_TYPE_MSP5000_FPGA       "MSP5000-FPGA"
+#define MACHINE_TYPE_MSP4200_FPGA       "MSP4200-FPGA"
+#define MACHINE_TYPE_MSP7100_FPGA       "MSP7100-FPGA"
+#define MACHINE_TYPE_OTHER_FPGA         "OTHER-FPGA"
+
+/* Device Family definitions */
+#define FAMILY_FPGA                     0x0000
+#define FAMILY_ZEUS                     0x1000
+#define FAMILY_POLO                     0x2000
+#define FAMILY_DUET                     0x4000
+#define FAMILY_TRIAD                    0x5000
+#define FAMILY_MSP4200                  0x4200
+#define FAMILY_MSP4200_FPGA             0x4f00
+#define FAMILY_MSP7100                  0x7100
+#define FAMILY_MSP7100_FPGA             0x7f00
+
+/* Device Type definitions */
+#define TYPE_MSP7120                    0x7120
+#define TYPE_MSP7130                    0x7130
+
+#define ENET_KEY                'E'
+#define ENETTXD_KEY             'e'
+#define PCI_KEY                 'P'
+#define PCIMUX_KEY              'p'
+#define SEC_KEY                 'S'
+#define SPAD_KEY                'D'
+#define TDM_KEY                 'T'
+#define ZSP_KEY                 'Z'
+
+#define FEATURE_NOEXIST         '-'
+#define FEATURE_EXIST           '+'
+
+#define ENET_MII                'M'
+#define ENET_RMII               'R'
+
+#define ENETTXD_FALLING         'F'
+#define ENETTXD_RISING          'R'
+
+#define PCI_HOST                'H'
+#define PCI_PERIPHERAL          'P'
+
+#define PCIMUX_FULL             'F'
+#define PCIMUX_SINGLE           'S'
+
+#define SEC_DUET                'D'
+#define SEC_POLO                'P'
+#define SEC_SLOW                'S'
+#define SEC_TRIAD               'T'
+
+#define SPAD_POLO               'P'
+
+#define TDM_DUET                'D'     /* DUET TDMs might exist */
+#define TDM_POLO                'P'     /* POLO TDMs might exist */
+#define TDM_TRIAD               'T'     /* TRIAD TDMs might exist */
+
+#define ZSP_DUET                'D'     /* one DUET zsp engine */
+#define ZSP_TRIAD               'T'     /* two TRIAD zsp engines */
+
+extern char *prom_getcmdline(void);
+extern char *prom_getenv(char *name);
+extern void prom_init_cmdline(void);
+extern void prom_meminit(void);
+extern void prom_fixup_mem_map(unsigned long start_mem,
+                               unsigned long end_mem);
+
+#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
+extern bool get_ramroot(void **start, unsigned long *size);
+#endif
+
+extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
+extern unsigned long get_deviceid(void);
+extern char identify_enet(unsigned long interface_num);
+extern char identify_enetTxD(unsigned long interface_num);
+extern char identify_pci(void);
+extern char identify_sec(void);
+extern char identify_spad(void);
+extern char identify_sec(void);
+extern char identify_tdm(void);
+extern char identify_zsp(void);
+extern unsigned long identify_family(void);
+extern unsigned long identify_revision(void);
+
+/*
+ * The following macro calls prom_printf and puts the format string
+ * into an init section so it can be reclaimed.
+ */
+#define ppfinit(f, x...) \
+        do { \
+                static char _f[] __initdata = KERN_INFO f; \
+                printk(_f, ## x); \
+        } while (0)
+
+/* Memory descriptor management. */
+#define PROM_MAX_PMEMBLOCKS    7        /* 6 used */
+
+enum yamon_memtypes {
+        yamon_dontuse,
+        yamon_prom,
+        yamon_free,
+};
+
+struct prom_pmemblock {
+        unsigned long base; /* Within KSEG0. */
+        unsigned int size;  /* In bytes. */
+        unsigned int type;  /* free or prom memory */
+};
+
+extern int prom_argc;
+extern char **prom_argv;
+extern char **prom_envp;
+extern int *prom_vec;
+extern struct prom_pmemblock *prom_getmdesc(void);
+
+#endif /* !_ASM_MSP_PROM_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
new file mode 100644
index 000000000000..60a5a38dd5b2
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
@@ -0,0 +1,236 @@
+/*
+ * SMP/VPE-safe functions to access "registers" (see note).
+ *
+ * NOTES:
+* - These macros use ll/sc instructions, so it is your responsibility to
+ * ensure these are available on your platform before including this file.
+ * - The MIPS32 spec states that ll/sc results are undefined for uncached
+ * accesses. This means they can't be used on HW registers accessed
+ * through kseg1. Code which requires these macros for this purpose must
+ * front-end the registers with cached memory "registers" and have a single
+ * thread update the actual HW registers.
+ * - A maximum of 2k of code can be inserted between ll and sc. Every
+ * memory accesses between the instructions will increase the chance of
+ * sc failing and having to loop.
+ * - When using custom_read_reg32/custom_write_reg32 only perform the
+ * necessary logical operations on the register value in between these
+ * two calls. All other logic should be performed before the first call.
+  * - There is a bug on the R10000 chips which has a workaround. If you
+ * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
+ * to be non-zero.  If you are using this header from within linux, you may
+ * include <asm/war.h> before including this file to have this defined
+ * appropriately for you.
+ *
+ * Copyright 2005-2007 PMC-Sierra, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
+ *  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF USE,
+ *  DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc., 675
+ *  Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_REGOPS_H__
+#define __ASM_REGOPS_H__
+
+#include <linux/types.h>
+
+#include <asm/war.h>
+
+#ifndef R10000_LLSC_WAR
+#define R10000_LLSC_WAR 0
+#endif
+
+#if R10000_LLSC_WAR == 1
+#define __beqz  "beqzl  "
+#else
+#define __beqz  "beqz   "
+#endif
+
+#ifndef _LINUX_TYPES_H
+typedef unsigned int u32;
+#endif
+
+/*
+ * Sets all the masked bits to the corresponding value bits
+ */
+static inline void set_value_reg32(volatile u32 *const addr,
+                                        u32 const mask,
+                                        u32 const value)
+{
+        u32 temp;
+
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1  # set_value_reg32       \n"
+        "       and     %0, %2                          \n"
+        "       or      %0, %3                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (~mask), "ir" (value), "m" (*addr));
+}
+
+/*
+ * Sets all the masked bits to '1'
+ */
+static inline void set_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1          # set_reg32     \n"
+        "       or      %0, %2                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (mask), "m" (*addr));
+}
+
+/*
+ * Sets all the masked bits to '0'
+ */
+static inline void clear_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1          # clear_reg32   \n"
+        "       and     %0, %2                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (~mask), "m" (*addr));
+}
+
+/*
+ * Toggles all masked bits from '0' to '1' and '1' to '0'
+ */
+static inline void toggle_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1          # toggle_reg32  \n"
+        "       xor     %0, %2                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (mask), "m" (*addr));
+}
+
+/*
+ * Read all masked bits others are returned as '0'
+ */
+static inline u32 read_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    noreorder                       \n"
+        "       lw      %0, %1          # read          \n"
+        "       and     %0, %2          # mask          \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp)
+        : "m" (*addr), "ir" (mask));
+
+        return temp;
+}
+
+/*
+ * blocking_read_reg32 - Read address with blocking load
+ *
+ * Uncached writes need to be read back to ensure they reach RAM.
+ * The returned value must be 'used' to prevent from becoming a
+ * non-blocking load.
+ */
+static inline u32 blocking_read_reg32(volatile u32 *const addr)
+{
+        u32 temp;
+
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    noreorder                       \n"
+        "       lw      %0, %1          # read          \n"
+        "       move    %0, %0          # block         \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp)
+        : "m" (*addr));
+
+        return temp;
+}
+
+/*
+ * For special strange cases only:
+ *
+ * If you need custom processing within a ll/sc loop, use the following macros
+ * VERY CAREFULLY:
+ *
+ *   u32 tmp;                           <-- Define a variable to hold the data
+ *
+ *   custom_read_reg32(address, tmp);   <-- Reads the address and put the value
+ *                                              in the 'tmp' variable given
+ *
+ *      From here on out, you are (basicly) atomic, so don't do anything too
+ *      fancy!
+ *      Also, this code may loop if the end of this block fails to write
+ *      everything back safely due do the other CPU, so do NOT do anything
+ *      with side-effects!
+ *
+ *   custom_write_reg32(address, tmp);  <-- Writes back 'tmp' safely.
+ */
+#define custom_read_reg32(address, tmp)                         \
+        __asm__ __volatile__(                                   \
+        "       .set    push                            \n"     \
+        "       .set    mips3                           \n"     \
+        "1:     ll      %0, %1  #custom_read_reg32      \n"     \
+        "       .set    pop                             \n"     \
+        : "=r" (tmp), "=m" (*address)                           \
+        : "m" (*address))
+
+#define custom_write_reg32(address, tmp)                        \
+        __asm__ __volatile__(                                   \
+        "       .set    push                            \n"     \
+        "       .set    mips3                           \n"     \
+        "       sc      %0, %1  #custom_write_reg32     \n"     \
+        "       "__beqz"%0, 1b                          \n"     \
+        "       nop                                     \n"     \
+        "       .set    pop                             \n"     \
+        : "=&r" (tmp), "=m" (*address)                          \
+        : "0" (tmp), "m" (*address))
+
+#endif  /* __ASM_REGOPS_H__ */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
new file mode 100644
index 000000000000..603eb737b4a8
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
@@ -0,0 +1,663 @@
+/*
+ * Defines for the address space, registers and register configuration
+ * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
+ * This file contains addess maps for all the devices in the line of
+ * products but only has register definitions and configuration masks for
+ * registers which aren't definitely associated with any device.  Things
+ * like clock settings, reset access, the ELB etc.  Individual device
+ * drivers will reference the appropriate XXX_BASE value defined here
+ * and have individual registers offset from that.
+ *
+ * Copyright (C) 2005-2007 PMC-Sierra, Inc.  All rights reserved.
+ * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+
+#include <asm/addrspace.h>
+#include <linux/types.h>
+
+#ifndef _ASM_MSP_REGS_H
+#define _ASM_MSP_REGS_H
+
+/*
+ ########################################################################
+ #  Address space and device base definitions                           #
+ ########################################################################
+ */
+
+/*
+ ***************************************************************************
+ * System Logic and Peripherals (ELB, UART0, etc) device address space     *
+ ***************************************************************************
+ */
+#define MSP_SLP_BASE            0x1c000000
+                                        /* System Logic and Peripherals */
+#define MSP_RST_BASE            (MSP_SLP_BASE + 0x10)
+                                        /* System reset register base   */
+#define MSP_RST_SIZE            0x0C    /* System reset register space  */
+
+#define MSP_WTIMER_BASE         (MSP_SLP_BASE + 0x04C)
+                                        /* watchdog timer base          */
+#define MSP_ITIMER_BASE         (MSP_SLP_BASE + 0x054)
+                                        /* internal timer base          */
+#define MSP_UART0_BASE          (MSP_SLP_BASE + 0x100)
+                                        /* UART0 controller base        */
+#define MSP_BCPY_CTRL_BASE      (MSP_SLP_BASE + 0x120)
+                                        /* Block Copy controller base   */
+#define MSP_BCPY_DESC_BASE      (MSP_SLP_BASE + 0x160)
+                                        /* Block Copy descriptor base   */
+
+/*
+ ***************************************************************************
+ * PCI address space                                                       *
+ ***************************************************************************
+ */
+#define MSP_PCI_BASE            0x19000000
+
+/*
+ ***************************************************************************
+ * MSbus device address space                                              *
+ ***************************************************************************
+ */
+#define MSP_MSB_BASE            0x18000000
+                                        /* MSbus address start          */
+#define MSP_PER_BASE            (MSP_MSB_BASE + 0x400000)
+                                        /* Peripheral device registers  */
+#define MSP_MAC0_BASE           (MSP_MSB_BASE + 0x600000)
+                                        /* MAC A device registers       */
+#define MSP_MAC1_BASE           (MSP_MSB_BASE + 0x700000)
+                                        /* MAC B device registers       */
+#define MSP_MAC_SIZE            0xE0    /* MAC register space           */
+
+#define MSP_SEC_BASE            (MSP_MSB_BASE + 0x800000)
+                                        /* Security Engine registers    */
+#define MSP_MAC2_BASE           (MSP_MSB_BASE + 0x900000)
+                                        /* MAC C device registers       */
+#define MSP_ADSL2_BASE          (MSP_MSB_BASE + 0xA80000)
+                                        /* ADSL2 device registers       */
+#define MSP_USB_BASE            (MSP_MSB_BASE + 0xB40000)
+                                        /* USB device registers         */
+#define MSP_USB_BASE_START      (MSP_MSB_BASE + 0xB40100)
+                                        /* USB device registers         */
+#define MSP_USB_BASE_END        (MSP_MSB_BASE + 0xB401FF)
+                                        /* USB device registers         */
+#define MSP_CPUIF_BASE          (MSP_MSB_BASE + 0xC00000)
+                                        /* CPU interface registers      */
+
+/* Devices within the MSbus peripheral block */
+#define MSP_UART1_BASE          (MSP_PER_BASE + 0x030)
+                                        /* UART1 controller base        */
+#define MSP_SPI_BASE            (MSP_PER_BASE + 0x058)
+                                        /* SPI/MPI control registers    */
+#define MSP_TWI_BASE            (MSP_PER_BASE + 0x090)
+                                        /* Two-wire control registers   */
+#define MSP_PTIMER_BASE         (MSP_PER_BASE + 0x0F0)
+                                        /* Programmable timer control   */
+
+/*
+ ***************************************************************************
+ * Physical Memory configuration address space                             *
+ ***************************************************************************
+ */
+#define MSP_MEM_CFG_BASE        0x17f00000
+
+#define MSP_MEM_INDIRECT_CTL_10 0x10
+
+/*
+ * Notes:
+ *  1) The SPI registers are split into two blocks, one offset from the
+ *     MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
+ *     0x68.  The SPI driver definitions for the register must be aware
+ *     of this.
+ *  2) The block copy engine register are divided into two regions, one
+ *     for the control/configuration of the engine proper and one for the
+ *     values of the descriptors used in the copy process.  These have
+ *     different base defines (CTRL_BASE vs DESC_BASE)
+ *  3) These constants are for physical addresses which means that they
+ *     work correctly with "ioremap" and friends.  This means that device
+ *     drivers will need to remap these addresses using ioremap and perhaps
+ *     the readw/writew macros.  Or they could use the regptr() macro
+ *     defined below, but the readw/writew calls are the correct thing.
+ *  4) The UARTs have an additional status register offset from the base
+ *     address.  This register isn't used in the standard 8250 driver but
+ *     may be used in other software.  Consult the hardware datasheet for
+ *     offset details.
+ *  5) For some unknown reason the security engine (MSP_SEC_BASE) registers
+ *     start at an offset of 0x84 from the base address but the block of
+ *     registers before this is reserved for the security engine.  The
+ *     driver will have to be aware of this but it makes the register
+ *     definitions line up better with the documentation.
+ */
+
+/*
+ ########################################################################
+ #  System register definitions.  Not associated with a specific device #
+ ########################################################################
+ */
+
+/*
+ * This macro maps the physical register number into uncached space
+ * and (for C code) casts it into a u32 pointer so it can be dereferenced
+ * Normally these would be accessed with ioremap and readX/writeX, but
+ * these are convenient for a lot of internal kernel code.
+ */
+#ifdef __ASSEMBLER__
+        #define regptr(addr) (KSEG1ADDR(addr))
+#else
+        #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
+#endif
+
+/*
+ ***************************************************************************
+ * System Logic and Peripherals (RESET, ELB, etc) registers                *
+ ***************************************************************************
+ */
+
+/* System Control register definitions */
+#define DEV_ID_REG      regptr(MSP_SLP_BASE + 0x00)
+                                        /* Device-ID                 RO */
+#define FWR_ID_REG      regptr(MSP_SLP_BASE + 0x04)
+                                        /* Firmware-ID Register      RW */
+#define SYS_ID_REG0     regptr(MSP_SLP_BASE + 0x08)
+                                        /* System-ID Register-0      RW */
+#define SYS_ID_REG1     regptr(MSP_SLP_BASE + 0x0C)
+                                        /* System-ID Register-1      RW */
+
+/* System Reset register definitions */
+#define RST_STS_REG     regptr(MSP_SLP_BASE + 0x10)
+                                        /* System Reset Status       RO */
+#define RST_SET_REG     regptr(MSP_SLP_BASE + 0x14)
+                                        /* System Set Reset          WO */
+#define RST_CLR_REG     regptr(MSP_SLP_BASE + 0x18)
+                                        /* System Clear Reset        WO */
+
+/* System Clock Registers */
+#define PCI_SLP_REG     regptr(MSP_SLP_BASE + 0x1C)
+                                        /* PCI clock generator       RW */
+#define URT_SLP_REG     regptr(MSP_SLP_BASE + 0x20)
+                                        /* UART clock generator      RW */
+/* reserved                   (MSP_SLP_BASE + 0x24)                     */
+/* reserved                   (MSP_SLP_BASE + 0x28)                     */
+#define PLL1_SLP_REG    regptr(MSP_SLP_BASE + 0x2C)
+                                        /* PLL1 clock generator      RW */
+#define PLL0_SLP_REG    regptr(MSP_SLP_BASE + 0x30)
+                                        /* PLL0 clock generator      RW */
+#define MIPS_SLP_REG    regptr(MSP_SLP_BASE + 0x34)
+                                        /* MIPS clock generator      RW */
+#define VE_SLP_REG      regptr(MSP_SLP_BASE + 0x38)
+                                        /* Voice Eng clock generator RW */
+/* reserved                   (MSP_SLP_BASE + 0x3C)                     */
+#define MSB_SLP_REG     regptr(MSP_SLP_BASE + 0x40)
+                                        /* MS-Bus clock generator    RW */
+#define SMAC_SLP_REG    regptr(MSP_SLP_BASE + 0x44)
+                                        /* Sec & MAC clock generator RW */
+#define PERF_SLP_REG    regptr(MSP_SLP_BASE + 0x48)
+                                        /* Per & TDM clock generator RW */
+
+/* Interrupt Controller Registers */
+#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
+                                        /* Interrupt status register RW */
+#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
+                                        /* Interrupt enable/mask     RW */
+#define SE_MBOX_REG     regptr(MSP_SLP_BASE + 0x78)
+                                        /* Security Engine mailbox   RW */
+#define VE_MBOX_REG     regptr(MSP_SLP_BASE + 0x7C)
+                                        /* Voice Engine mailbox      RW */
+
+/* ELB Controller Registers */
+#define CS0_CNFG_REG    regptr(MSP_SLP_BASE + 0x80)
+                                        /* ELB CS0 Configuration Reg    */
+#define CS0_ADDR_REG    regptr(MSP_SLP_BASE + 0x84)
+                                        /* ELB CS0 Base Address Reg     */
+#define CS0_MASK_REG    regptr(MSP_SLP_BASE + 0x88)
+                                        /* ELB CS0 Mask Register        */
+#define CS0_ACCESS_REG  regptr(MSP_SLP_BASE + 0x8C)
+                                        /* ELB CS0 access register      */
+
+#define CS1_CNFG_REG    regptr(MSP_SLP_BASE + 0x90)
+                                        /* ELB CS1 Configuration Reg    */
+#define CS1_ADDR_REG    regptr(MSP_SLP_BASE + 0x94)
+                                        /* ELB CS1 Base Address Reg     */
+#define CS1_MASK_REG    regptr(MSP_SLP_BASE + 0x98)
+                                        /* ELB CS1 Mask Register        */
+#define CS1_ACCESS_REG  regptr(MSP_SLP_BASE + 0x9C)
+                                        /* ELB CS1 access register      */
+
+#define CS2_CNFG_REG    regptr(MSP_SLP_BASE + 0xA0)
+                                        /* ELB CS2 Configuration Reg    */
+#define CS2_ADDR_REG    regptr(MSP_SLP_BASE + 0xA4)
+                                        /* ELB CS2 Base Address Reg     */
+#define CS2_MASK_REG    regptr(MSP_SLP_BASE + 0xA8)
+                                        /* ELB CS2 Mask Register        */
+#define CS2_ACCESS_REG  regptr(MSP_SLP_BASE + 0xAC)
+                                        /* ELB CS2 access register      */
+
+#define CS3_CNFG_REG    regptr(MSP_SLP_BASE + 0xB0)
+                                        /* ELB CS3 Configuration Reg    */
+#define CS3_ADDR_REG    regptr(MSP_SLP_BASE + 0xB4)
+                                        /* ELB CS3 Base Address Reg     */
+#define CS3_MASK_REG    regptr(MSP_SLP_BASE + 0xB8)
+                                        /* ELB CS3 Mask Register        */
+#define CS3_ACCESS_REG  regptr(MSP_SLP_BASE + 0xBC)
+                                        /* ELB CS3 access register      */
+
+#define CS4_CNFG_REG    regptr(MSP_SLP_BASE + 0xC0)
+                                        /* ELB CS4 Configuration Reg    */
+#define CS4_ADDR_REG    regptr(MSP_SLP_BASE + 0xC4)
+                                        /* ELB CS4 Base Address Reg     */
+#define CS4_MASK_REG    regptr(MSP_SLP_BASE + 0xC8)
+                                        /* ELB CS4 Mask Register        */
+#define CS4_ACCESS_REG  regptr(MSP_SLP_BASE + 0xCC)
+                                        /* ELB CS4 access register      */
+
+#define CS5_CNFG_REG    regptr(MSP_SLP_BASE + 0xD0)
+                                        /* ELB CS5 Configuration Reg    */
+#define CS5_ADDR_REG    regptr(MSP_SLP_BASE + 0xD4)
+                                        /* ELB CS5 Base Address Reg     */
+#define CS5_MASK_REG    regptr(MSP_SLP_BASE + 0xD8)
+                                        /* ELB CS5 Mask Register        */
+#define CS5_ACCESS_REG  regptr(MSP_SLP_BASE + 0xDC)
+                                        /* ELB CS5 access register      */
+
+/* reserved                            0xE0 - 0xE8                      */
+#define ELB_1PC_EN_REG  regptr(MSP_SLP_BASE + 0xEC)
+                                        /* ELB single PC card detect    */
+
+/* reserved                            0xF0 - 0xF8                      */
+#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
+                                        /* SDRAM read/ELB timing Reg    */
+
+/* Extended UART status registers */
+#define UART0_STATUS_REG        regptr(MSP_UART0_BASE + 0x0c0)
+                                        /* UART Status Register 0       */
+#define UART1_STATUS_REG        regptr(MSP_UART1_BASE + 0x170)
+                                        /* UART Status Register 1       */
+
+/* Performance monitoring registers */
+#define PERF_MON_CTRL_REG       regptr(MSP_SLP_BASE + 0x140)
+                                        /* Performance monitor control  */
+#define PERF_MON_CLR_REG        regptr(MSP_SLP_BASE + 0x144)
+                                        /* Performance monitor clear    */
+#define PERF_MON_CNTH_REG       regptr(MSP_SLP_BASE + 0x148)
+                                        /* Perf monitor counter high    */
+#define PERF_MON_CNTL_REG       regptr(MSP_SLP_BASE + 0x14C)
+                                        /* Perf monitor counter low     */
+
+/* System control registers */
+#define SYS_CTRL_REG            regptr(MSP_SLP_BASE + 0x150)
+                                        /* System control register      */
+#define SYS_ERR1_REG            regptr(MSP_SLP_BASE + 0x154)
+                                        /* System Error status 1        */
+#define SYS_ERR2_REG            regptr(MSP_SLP_BASE + 0x158)
+                                        /* System Error status 2        */
+#define SYS_INT_CFG_REG         regptr(MSP_SLP_BASE + 0x15C)
+                                        /* System Interrupt config      */
+
+/* Voice Engine Memory configuration */
+#define VE_MEM_REG              regptr(MSP_SLP_BASE + 0x17C)
+                                        /* Voice engine memory config   */
+
+/* CPU/SLP Error Status registers */
+#define CPU_ERR1_REG            regptr(MSP_SLP_BASE + 0x180)
+                                        /* CPU/SLP Error status 1       */
+#define CPU_ERR2_REG            regptr(MSP_SLP_BASE + 0x184)
+                                        /* CPU/SLP Error status 1       */
+
+#define EXTENDED_GPIO_REG       regptr(MSP_SLP_BASE + 0x188)
+                                        /* Extended GPIO register       */
+
+/* System Error registers */
+#define SLP_ERR_STS_REG         regptr(MSP_SLP_BASE + 0x190)
+                                        /* Int status for SLP errors    */
+#define SLP_ERR_MSK_REG         regptr(MSP_SLP_BASE + 0x194)
+                                        /* Int mask for SLP errors      */
+#define SLP_ELB_ERST_REG        regptr(MSP_SLP_BASE + 0x198)
+                                        /* External ELB reset           */
+#define SLP_BOOT_STS_REG        regptr(MSP_SLP_BASE + 0x19C)
+                                        /* Boot Status                  */
+
+/* Extended ELB addressing */
+#define CS0_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A0)
+                                        /* CS0 Extended address         */
+#define CS1_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A4)
+                                        /* CS1 Extended address         */
+#define CS2_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A8)
+                                        /* CS2 Extended address         */
+#define CS3_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1AC)
+                                        /* CS3 Extended address         */
+/* reserved                                           0x1B0             */
+#define CS5_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1B4)
+                                        /* CS5 Extended address         */
+
+/* PLL Adjustment registers */
+#define PLL_LOCK_REG            regptr(MSP_SLP_BASE + 0x200)
+                                        /* PLL0 lock status             */
+#define PLL_ARST_REG            regptr(MSP_SLP_BASE + 0x204)
+                                        /* PLL Analog reset status      */
+#define PLL0_ADJ_REG            regptr(MSP_SLP_BASE + 0x208)
+                                        /* PLL0 Adjustment value        */
+#define PLL1_ADJ_REG            regptr(MSP_SLP_BASE + 0x20C)
+                                        /* PLL1 Adjustment value        */
+
+/*
+ ***************************************************************************
+ * Peripheral Register definitions                                         *
+ ***************************************************************************
+ */
+
+/* Peripheral status */
+#define PER_CTRL_REG            regptr(MSP_PER_BASE + 0x50)
+                                        /* Peripheral control register  */
+#define PER_STS_REG             regptr(MSP_PER_BASE + 0x54)
+                                        /* Peripheral status register   */
+
+/* SPI/MPI Registers */
+#define SMPI_TX_SZ_REG          regptr(MSP_PER_BASE + 0x58)
+                                        /* SPI/MPI Tx Size register     */
+#define SMPI_RX_SZ_REG          regptr(MSP_PER_BASE + 0x5C)
+                                        /* SPI/MPI Rx Size register     */
+#define SMPI_CTL_REG            regptr(MSP_PER_BASE + 0x60)
+                                        /* SPI/MPI Control register     */
+#define SMPI_MS_REG             regptr(MSP_PER_BASE + 0x64)
+                                        /* SPI/MPI Chip Select reg      */
+#define SMPI_CORE_DATA_REG      regptr(MSP_PER_BASE + 0xC0)
+                                        /* SPI/MPI Core Data reg        */
+#define SMPI_CORE_CTRL_REG      regptr(MSP_PER_BASE + 0xC4)
+                                        /* SPI/MPI Core Control reg     */
+#define SMPI_CORE_STAT_REG      regptr(MSP_PER_BASE + 0xC8)
+                                        /* SPI/MPI Core Status reg      */
+#define SMPI_CORE_SSEL_REG      regptr(MSP_PER_BASE + 0xCC)
+                                        /* SPI/MPI Core Ssel reg        */
+#define SMPI_FIFO_REG           regptr(MSP_PER_BASE + 0xD0)
+                                        /* SPI/MPI Data FIFO reg        */
+
+/* Peripheral Block Error Registers           */
+#define PER_ERR_STS_REG         regptr(MSP_PER_BASE + 0x70)
+                                        /* Error Bit Status Register    */
+#define PER_ERR_MSK_REG         regptr(MSP_PER_BASE + 0x74)
+                                        /* Error Bit Mask Register      */
+#define PER_HDR1_REG            regptr(MSP_PER_BASE + 0x78)
+                                        /* Error Header 1 Register      */
+#define PER_HDR2_REG            regptr(MSP_PER_BASE + 0x7C)
+                                        /* Error Header 2 Register      */
+
+/* Peripheral Block Interrupt Registers       */
+#define PER_INT_STS_REG         regptr(MSP_PER_BASE + 0x80)
+                                        /* Interrupt status register    */
+#define PER_INT_MSK_REG         regptr(MSP_PER_BASE + 0x84)
+                                        /* Interrupt Mask Register      */
+#define GPIO_INT_STS_REG        regptr(MSP_PER_BASE + 0x88)
+                                        /* GPIO interrupt status reg    */
+#define GPIO_INT_MSK_REG        regptr(MSP_PER_BASE + 0x8C)
+                                        /* GPIO interrupt MASK Reg      */
+
+/* POLO GPIO registers                        */
+#define POLO_GPIO_DAT1_REG      regptr(MSP_PER_BASE + 0x0E0)
+                                        /* Polo GPIO[8:0]  data reg     */
+#define POLO_GPIO_CFG1_REG      regptr(MSP_PER_BASE + 0x0E4)
+                                        /* Polo GPIO[7:0]  config reg   */
+#define POLO_GPIO_CFG2_REG      regptr(MSP_PER_BASE + 0x0E8)
+                                        /* Polo GPIO[15:8] config reg   */
+#define POLO_GPIO_OD1_REG       regptr(MSP_PER_BASE + 0x0EC)
+                                        /* Polo GPIO[31:0] output drive */
+#define POLO_GPIO_CFG3_REG      regptr(MSP_PER_BASE + 0x170)
+                                        /* Polo GPIO[23:16] config reg  */
+#define POLO_GPIO_DAT2_REG      regptr(MSP_PER_BASE + 0x174)
+                                        /* Polo GPIO[15:9]  data reg    */
+#define POLO_GPIO_DAT3_REG      regptr(MSP_PER_BASE + 0x178)
+                                        /* Polo GPIO[23:16]  data reg   */
+#define POLO_GPIO_DAT4_REG      regptr(MSP_PER_BASE + 0x17C)
+                                        /* Polo GPIO[31:24]  data reg   */
+#define POLO_GPIO_DAT5_REG      regptr(MSP_PER_BASE + 0x180)
+                                        /* Polo GPIO[39:32]  data reg   */
+#define POLO_GPIO_DAT6_REG      regptr(MSP_PER_BASE + 0x184)
+                                        /* Polo GPIO[47:40]  data reg   */
+#define POLO_GPIO_DAT7_REG      regptr(MSP_PER_BASE + 0x188)
+                                        /* Polo GPIO[54:48]  data reg   */
+#define POLO_GPIO_CFG4_REG      regptr(MSP_PER_BASE + 0x18C)
+                                        /* Polo GPIO[31:24] config reg  */
+#define POLO_GPIO_CFG5_REG      regptr(MSP_PER_BASE + 0x190)
+                                        /* Polo GPIO[39:32] config reg  */
+#define POLO_GPIO_CFG6_REG      regptr(MSP_PER_BASE + 0x194)
+                                        /* Polo GPIO[47:40] config reg  */
+#define POLO_GPIO_CFG7_REG      regptr(MSP_PER_BASE + 0x198)
+                                        /* Polo GPIO[54:48] config reg  */
+#define POLO_GPIO_OD2_REG       regptr(MSP_PER_BASE + 0x19C)
+                                        /* Polo GPIO[54:32] output drive */
+
+/* Generic GPIO registers                     */
+#define GPIO_DATA1_REG          regptr(MSP_PER_BASE + 0x170)
+                                        /* GPIO[1:0] data register      */
+#define GPIO_DATA2_REG          regptr(MSP_PER_BASE + 0x174)
+                                        /* GPIO[5:2] data register      */
+#define GPIO_DATA3_REG          regptr(MSP_PER_BASE + 0x178)
+                                        /* GPIO[9:6] data register      */
+#define GPIO_DATA4_REG          regptr(MSP_PER_BASE + 0x17C)
+                                        /* GPIO[15:10] data register    */
+#define GPIO_CFG1_REG           regptr(MSP_PER_BASE + 0x180)
+                                        /* GPIO[1:0] config register    */
+#define GPIO_CFG2_REG           regptr(MSP_PER_BASE + 0x184)
+                                        /* GPIO[5:2] config register    */
+#define GPIO_CFG3_REG           regptr(MSP_PER_BASE + 0x188)
+                                        /* GPIO[9:6] config register    */
+#define GPIO_CFG4_REG           regptr(MSP_PER_BASE + 0x18C)
+                                        /* GPIO[15:10] config register  */
+#define GPIO_OD_REG             regptr(MSP_PER_BASE + 0x190)
+                                        /* GPIO[15:0] output drive      */
+
+/*
+ ***************************************************************************
+ * CPU Interface register definitions                                      *
+ ***************************************************************************
+ */
+#define PCI_FLUSH_REG           regptr(MSP_CPUIF_BASE + 0x00)
+                                        /* PCI-SDRAM queue flush trigger */
+#define OCP_ERR1_REG            regptr(MSP_CPUIF_BASE + 0x04)
+                                        /* OCP Error Attribute 1        */
+#define OCP_ERR2_REG            regptr(MSP_CPUIF_BASE + 0x08)
+                                        /* OCP Error Attribute 2        */
+#define OCP_STS_REG             regptr(MSP_CPUIF_BASE + 0x0C)
+                                        /* OCP Error Status             */
+#define CPUIF_PM_REG            regptr(MSP_CPUIF_BASE + 0x10)
+                                        /* CPU policy configuration     */
+#define CPUIF_CFG_REG           regptr(MSP_CPUIF_BASE + 0x10)
+                                        /* Misc configuration options   */
+
+/* Central Interrupt Controller Registers */
+#define MSP_CIC_BASE            (MSP_CPUIF_BASE + 0x8000)
+                                        /* Central Interrupt registers  */
+#define CIC_EXT_CFG_REG         regptr(MSP_CIC_BASE + 0x00)
+                                        /* External interrupt config    */
+#define CIC_STS_REG             regptr(MSP_CIC_BASE + 0x04)
+                                        /* CIC Interrupt Status         */
+#define CIC_VPE0_MSK_REG        regptr(MSP_CIC_BASE + 0x08)
+                                        /* VPE0 Interrupt Mask          */
+#define CIC_VPE1_MSK_REG        regptr(MSP_CIC_BASE + 0x0C)
+                                        /* VPE1 Interrupt Mask          */
+#define CIC_TC0_MSK_REG         regptr(MSP_CIC_BASE + 0x10)
+                                        /* Thread Context 0 Int Mask    */
+#define CIC_TC1_MSK_REG         regptr(MSP_CIC_BASE + 0x14)
+                                        /* Thread Context 1 Int Mask    */
+#define CIC_TC2_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
+                                        /* Thread Context 2 Int Mask    */
+#define CIC_TC3_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
+                                        /* Thread Context 3 Int Mask    */
+#define CIC_TC4_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
+                                        /* Thread Context 4 Int Mask    */
+#define CIC_PCIMSI_STS_REG      regptr(MSP_CIC_BASE + 0x18)
+#define CIC_PCIMSI_MSK_REG      regptr(MSP_CIC_BASE + 0x18)
+#define CIC_PCIFLSH_REG         regptr(MSP_CIC_BASE + 0x18)
+#define CIC_VPE0_SWINT_REG      regptr(MSP_CIC_BASE + 0x08)
+
+
+/*
+ ***************************************************************************
+ * Memory controller registers                                             *
+ ***************************************************************************
+ */
+#define MEM_CFG1_REG            regptr(MSP_MEM_CFG_BASE + 0x00)
+#define MEM_SS_ADDR             regptr(MSP_MEM_CFG_BASE + 0x00)
+#define MEM_SS_DATA             regptr(MSP_MEM_CFG_BASE + 0x04)
+#define MEM_SS_WRITE            regptr(MSP_MEM_CFG_BASE + 0x08)
+
+/*
+ ***************************************************************************
+ * PCI controller registers                                                *
+ ***************************************************************************
+ */
+#define PCI_BASE_REG            regptr(MSP_PCI_BASE + 0x00)
+#define PCI_CONFIG_SPACE_REG    regptr(MSP_PCI_BASE + 0x800)
+#define PCI_JTAG_DEVID_REG      regptr(MSP_SLP_BASE + 0x13c)
+
+/*
+ ########################################################################
+ #  Register content & macro definitions                                #
+ ########################################################################
+ */
+
+/*
+ ***************************************************************************
+ * DEV_ID defines                                                          *
+ ***************************************************************************
+ */
+#define DEV_ID_PCI_DIS          (1 << 26)       /* Set if PCI disabled */
+#define DEV_ID_PCI_HOST         (1 << 20)       /* Set if PCI host */
+#define DEV_ID_SINGLE_PC        (1 << 19)       /* Set if single PC Card */
+#define DEV_ID_FAMILY           (0xff << 8)     /* family ID code */
+#define POLO_ZEUS_SUB_FAMILY    (0x7  << 16)    /* sub family for Polo/Zeus */
+
+#define MSPFPGA_ID              (0x00  << 8)    /* you are on your own here */
+#define MSP5000_ID              (0x50  << 8)
+#define MSP4F00_ID              (0x4f  << 8)    /* FPGA version of MSP4200 */
+#define MSP4E00_ID              (0x4f  << 8)    /* FPGA version of MSP7120 */
+#define MSP4200_ID              (0x42  << 8)
+#define MSP4000_ID              (0x40  << 8)
+#define MSP2XXX_ID              (0x20  << 8)
+#define MSPZEUS_ID              (0x10  << 8)
+
+#define MSP2004_SUB_ID          (0x0   << 16)
+#define MSP2005_SUB_ID          (0x1   << 16)
+#define MSP2006_SUB_ID          (0x1   << 16)
+#define MSP2007_SUB_ID          (0x2   << 16)
+#define MSP2010_SUB_ID          (0x3   << 16)
+#define MSP2015_SUB_ID          (0x4   << 16)
+#define MSP2020_SUB_ID          (0x5   << 16)
+#define MSP2100_SUB_ID          (0x6   << 16)
+
+/*
+ ***************************************************************************
+ * RESET defines                                                           *
+ ***************************************************************************
+ */
+#define MSP_GR_RST              (0x01 << 0)     /* Global reset bit     */
+#define MSP_MR_RST              (0x01 << 1)     /* MIPS reset bit       */
+#define MSP_PD_RST              (0x01 << 2)     /* PVC DMA reset bit    */
+#define MSP_PP_RST              (0x01 << 3)     /* PVC reset bit        */
+/* reserved                                                             */
+#define MSP_EA_RST              (0x01 << 6)     /* Mac A reset bit      */
+#define MSP_EB_RST              (0x01 << 7)     /* Mac B reset bit      */
+#define MSP_SE_RST              (0x01 << 8)     /* Security Eng reset bit */
+#define MSP_PB_RST              (0x01 << 9)     /* Per block reset bit  */
+#define MSP_EC_RST              (0x01 << 10)    /* Mac C reset bit      */
+#define MSP_TW_RST              (0x01 << 11)    /* TWI reset bit        */
+#define MSP_SPI_RST             (0x01 << 12)    /* SPI/MPI reset bit    */
+#define MSP_U1_RST              (0x01 << 13)    /* UART1 reset bit      */
+#define MSP_U0_RST              (0x01 << 14)    /* UART0 reset bit      */
+
+/*
+ ***************************************************************************
+ * UART defines                                                            *
+ ***************************************************************************
+ */
+#define MSP_BASE_BAUD           25000000
+#define MSP_UART_REG_LEN        0x20
+
+/*
+ ***************************************************************************
+ * ELB defines                                                             *
+ ***************************************************************************
+ */
+#define PCCARD_32               0x02    /* Set if is PCCARD 32 (Cardbus) */
+#define SINGLE_PCCARD           0x01    /* Set to enable single PC card */
+
+/*
+ ***************************************************************************
+ * CIC defines                                                             *
+ ***************************************************************************
+ */
+
+/* CIC_EXT_CFG_REG */
+#define EXT_INT_POL(eirq)                       (1 << (eirq + 8))
+#define EXT_INT_EDGE(eirq)                      (1 << eirq)
+
+#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq)    (reg &= ~EXT_INT_EDGE(eirq))
+#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq)     (reg |= EXT_INT_EDGE(eirq))
+#define CIC_EXT_SET_ACTIVE_HI(reg, eirq)        (reg |= EXT_INT_POL(eirq))
+#define CIC_EXT_SET_ACTIVE_LO(reg, eirq)        (reg &= ~EXT_INT_POL(eirq))
+#define CIC_EXT_SET_ACTIVE_RISING               CIC_EXT_SET_ACTIVE_HI
+#define CIC_EXT_SET_ACTIVE_FALLING              CIC_EXT_SET_ACTIVE_LO
+
+#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
+                                ((reg & EXT_INT_EDGE(eirq)) == 0)
+#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq)      (reg & EXT_INT_EDGE(eirq))
+#define CIC_EXT_IS_ACTIVE_HI(reg, eirq)         (reg & EXT_INT_POL(eirq))
+#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
+                                ((reg & EXT_INT_POL(eirq)) == 0)
+#define CIC_EXT_IS_ACTIVE_RISING                CIC_EXT_IS_ACTIVE_HI
+#define CIC_EXT_IS_ACTIVE_FALLING               CIC_EXT_IS_ACTIVE_LO
+
+/*
+ ***************************************************************************
+ * Memory Controller defines                                               *
+ ***************************************************************************
+ */
+
+/* Indirect memory controller registers */
+#define DDRC_CFG(n)             (n)
+#define DDRC_DEBUG(n)           (0x04 + n)
+#define DDRC_CTL(n)             (0x40 + n)
+
+/* Macro to perform DDRC indirect write */
+#define DDRC_INDIRECT_WRITE(reg, mask, value) \
+({ \
+        *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
+        *MEM_SS_DATA = (value); \
+        *MEM_SS_WRITE = 1; \
+})
+
+/*
+ ***************************************************************************
+ * SPI/MPI Mode                                                            *
+ ***************************************************************************
+ */
+#define SPI_MPI_RX_BUSY         0x00008000      /* SPI/MPI Receive Busy */
+#define SPI_MPI_FIFO_EMPTY      0x00004000      /* SPI/MPI Fifo Empty   */
+#define SPI_MPI_TX_BUSY         0x00002000      /* SPI/MPI Transmit Busy */
+#define SPI_MPI_FIFO_FULL       0x00001000      /* SPI/MPU FIFO full    */
+
+/*
+ ***************************************************************************
+ * SPI/MPI Control Register                                                *
+ ***************************************************************************
+ */
+#define SPI_MPI_RX_START        0x00000004      /* Start receive command */
+#define SPI_MPI_FLUSH_Q         0x00000002      /* Flush SPI/MPI Queue */
+#define SPI_MPI_TX_START        0x00000001      /* Start Transmit Command */
+
+#endif /* !_ASM_MSP_REGS_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h
new file mode 100644
index 000000000000..96d4c8ce8c83
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h
@@ -0,0 +1,141 @@
+/*
+ * Defines for the MSP interrupt controller.
+ *
+ * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ * Author: Carsten Langgaard, carstenl@mips.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+
+#ifndef _MSP_SLP_INT_H
+#define _MSP_SLP_INT_H
+
+/*
+ * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
+ * hierarchical system.  The first level are the direct MIPS interrupts
+ * and are assigned the interrupt range 0-7.  The second level is the SLM
+ * interrupt controller and is assigned the range 8-39.  The third level
+ * comprises the Peripherial block, the PCI block, the PCI MSI block and
+ * the SLP.  The PCI interrupts and the SLP errors are handled by the
+ * relevant subsystems so the core interrupt code needs only concern
+ * itself with the Peripheral block.  These are assigned interrupts in
+ * the range 40-71.
+ */
+
+/*
+ * IRQs directly connected to CPU
+ */
+#define MSP_MIPS_INTBASE        0
+#define MSP_INT_SW0             0  /* IRQ for swint0,         C_SW0  */
+#define MSP_INT_SW1             1  /* IRQ for swint1,         C_SW1  */
+#define MSP_INT_MAC0            2  /* IRQ for MAC 0,          C_IRQ0 */
+#define MSP_INT_MAC1            3  /* IRQ for MAC 1,          C_IRQ1 */
+#define MSP_INT_C_IRQ2          4  /* Wired off,              C_IRQ2 */
+#define MSP_INT_VE              5  /* IRQ for Voice Engine,   C_IRQ3 */
+#define MSP_INT_SLP             6  /* IRQ for SLM block,      C_IRQ4 */
+#define MSP_INT_TIMER           7  /* IRQ for the MIPS timer, C_IRQ5 */
+
+/*
+ * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
+ * These defines should be tied to the register definition for the SLM
+ * interrupt routine.  For now, just use hard-coded values.
+ */
+#define MSP_SLP_INTBASE         (MSP_MIPS_INTBASE + 8)
+#define MSP_INT_EXT0            (MSP_SLP_INTBASE + 0)
+                                        /* External interrupt 0         */
+#define MSP_INT_EXT1            (MSP_SLP_INTBASE + 1)
+                                        /* External interrupt 1         */
+#define MSP_INT_EXT2            (MSP_SLP_INTBASE + 2)
+                                        /* External interrupt 2         */
+#define MSP_INT_EXT3            (MSP_SLP_INTBASE + 3)
+                                        /* External interrupt 3         */
+/* Reserved                                        4-7                  */
+
+/*
+ *************************************************************************
+ * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
+ * Some MSP produces have this interrupt labelled as Voice and some are  *
+ * SEC mbox ...                                                          *
+ *************************************************************************
+ */
+#define MSP_INT_SLP_VE          (MSP_SLP_INTBASE + 8)
+                                        /* Cascaded IRQ for Voice Engine*/
+#define MSP_INT_SLP_TDM         (MSP_SLP_INTBASE + 9)
+                                        /* TDM interrupt                */
+#define MSP_INT_SLP_MAC0        (MSP_SLP_INTBASE + 10)
+                                        /* Cascaded IRQ for MAC 0       */
+#define MSP_INT_SLP_MAC1        (MSP_SLP_INTBASE + 11)
+                                        /* Cascaded IRQ for MAC 1       */
+#define MSP_INT_SEC             (MSP_SLP_INTBASE + 12)
+                                        /* IRQ for security engine      */
+#define MSP_INT_PER             (MSP_SLP_INTBASE + 13)
+                                        /* Peripheral interrupt         */
+#define MSP_INT_TIMER0          (MSP_SLP_INTBASE + 14)
+                                        /* SLP timer 0                  */
+#define MSP_INT_TIMER1          (MSP_SLP_INTBASE + 15)
+                                        /* SLP timer 1                  */
+#define MSP_INT_TIMER2          (MSP_SLP_INTBASE + 16)
+                                        /* SLP timer 2                  */
+#define MSP_INT_SLP_TIMER       (MSP_SLP_INTBASE + 17)
+                                        /* Cascaded MIPS timer          */
+#define MSP_INT_BLKCP           (MSP_SLP_INTBASE + 18)
+                                        /* Block Copy                   */
+#define MSP_INT_UART0           (MSP_SLP_INTBASE + 19)
+                                        /* UART 0                       */
+#define MSP_INT_PCI             (MSP_SLP_INTBASE + 20)
+                                        /* PCI subsystem                */
+#define MSP_INT_PCI_DBELL       (MSP_SLP_INTBASE + 21)
+                                        /* PCI doorbell                 */
+#define MSP_INT_PCI_MSI         (MSP_SLP_INTBASE + 22)
+                                        /* PCI Message Signal           */
+#define MSP_INT_PCI_BC0         (MSP_SLP_INTBASE + 23)
+                                        /* PCI Block Copy 0             */
+#define MSP_INT_PCI_BC1         (MSP_SLP_INTBASE + 24)
+                                        /* PCI Block Copy 1             */
+#define MSP_INT_SLP_ERR         (MSP_SLP_INTBASE + 25)
+                                        /* SLP error condition          */
+#define MSP_INT_MAC2            (MSP_SLP_INTBASE + 26)
+                                        /* IRQ for MAC2                 */
+/* Reserved                                        26-31                */
+
+/*
+ * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
+ */
+#define MSP_PER_INTBASE         (MSP_SLP_INTBASE + 32)
+/* Reserved                                        0-1                  */
+#define MSP_INT_UART1           (MSP_PER_INTBASE + 2)
+                                        /* UART 1                       */
+/* Reserved                                        3-5                  */
+#define MSP_INT_2WIRE           (MSP_PER_INTBASE + 6)
+                                        /* 2-wire                       */
+#define MSP_INT_TM0             (MSP_PER_INTBASE + 7)
+                                        /* Peripheral timer block out 0 */
+#define MSP_INT_TM1             (MSP_PER_INTBASE + 8)
+                                        /* Peripheral timer block out 1 */
+/* Reserved                                        9                    */
+#define MSP_INT_SPRX            (MSP_PER_INTBASE + 10)
+                                        /* SPI RX complete              */
+#define MSP_INT_SPTX            (MSP_PER_INTBASE + 11)
+                                        /* SPI TX complete              */
+#define MSP_INT_GPIO            (MSP_PER_INTBASE + 12)
+                                        /* GPIO                         */
+#define MSP_INT_PER_ERR         (MSP_PER_INTBASE + 13)
+                                        /* Peripheral error             */
+/* Reserved                                        14-31                */
+
+#endif /* !_MSP_SLP_INT_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
new file mode 100644
index 000000000000..0bf48fc1892b
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
+#define __ASM_MIPS_PMC_SIERRA_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
+        defined(CONFIG_PMC_MSP7120_FPGA)
+#define MIPS34K_MISSED_ITLB_WAR         1
+#endif
+
+#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
diff --git a/arch/mips/include/asm/pmon.h b/arch/mips/include/asm/pmon.h
new file mode 100644
index 000000000000..6ad519189ce2
--- /dev/null
+++ b/arch/mips/include/asm/pmon.h
@@ -0,0 +1,46 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 by Ralf Baechle
+ *
+ * The cpustart method is a PMC-Sierra's function to start the secondary CPU.
+ * Stock PMON 2000 has the smpfork, semlock and semunlock methods instead.
+ */
+#ifndef _ASM_PMON_H
+#define _ASM_PMON_H
+
+struct callvectors {
+        int     (*open) (char*, int, int);
+        int     (*close) (int);
+        int     (*read) (int, void*, int);
+        int     (*write) (int, void*, int);
+        off_t   (*lseek) (int, off_t, int);
+        int     (*printf) (const char*, ...);
+        void    (*cacheflush) (void);
+        char*   (*gets) (char*);
+        union {
+                int     (*smpfork) (unsigned long cp, char *sp);
+                int     (*cpustart) (long, void (*)(void), void *, long);
+        } _s;
+        int     (*semlock) (int sem);
+        void    (*semunlock) (int sem);
+};
+
+extern struct callvectors *debug_vectors;
+
+#define pmon_open(name, flags, mode)    debug_vectors->open(name, flage, mode)
+#define pmon_close(fd)                  debug_vectors->close(fd)
+#define pmon_read(fd, buf, count)       debug_vectors->read(fd, buf, count)
+#define pmon_write(fd, buf, count)      debug_vectors->write(fd, buf, count)
+#define pmon_lseek(fd, off, whence)     debug_vectors->lseek(fd, off, whence)
+#define pmon_printf(fmt...)             debug_vectors->printf(fmt)
+#define pmon_cacheflush()               debug_vectors->cacheflush()
+#define pmon_gets(s)                    debug_vectors->gets(s)
+#define pmon_cpustart(n, f, sp, gp)     debug_vectors->_s.cpustart(n, f, sp, gp)
+#define pmon_smpfork(cp, sp)            debug_vectors->_s.smpfork(cp, sp)
+#define pmon_semlock(sem)               debug_vectors->semlock(sem)
+#define pmon_semunlock(sem)             debug_vectors->semunlock(sem)
+
+#endif /* _ASM_PMON_H */
diff --git a/arch/mips/include/asm/poll.h b/arch/mips/include/asm/poll.h
new file mode 100644
index 000000000000..47b952080431
--- /dev/null
+++ b/arch/mips/include/asm/poll.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_POLL_H
+#define __ASM_POLL_H
+
+#define POLLWRNORM      POLLOUT
+#define POLLWRBAND      0x0100
+
+#include <asm-generic/poll.h>
+
+#endif /* __ASM_POLL_H */
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
new file mode 100644
index 000000000000..c200102c8586
--- /dev/null
+++ b/arch/mips/include/asm/posix_types.h
@@ -0,0 +1,144 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_POSIX_TYPES_H
+#define _ASM_POSIX_TYPES_H
+
+#include <asm/sgidefs.h>
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned int    __kernel_mode_t;
+#if (_MIPS_SZLONG == 32)
+typedef unsigned long   __kernel_nlink_t;
+#endif
+#if (_MIPS_SZLONG == 64)
+typedef unsigned int    __kernel_nlink_t;
+#endif
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef int             __kernel_ipc_pid_t;
+typedef unsigned int    __kernel_uid_t;
+typedef unsigned int    __kernel_gid_t;
+#if (_MIPS_SZLONG == 32)
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef int             __kernel_ptrdiff_t;
+#endif
+#if (_MIPS_SZLONG == 64)
+typedef unsigned long   __kernel_size_t;
+typedef long            __kernel_ssize_t;
+typedef long            __kernel_ptrdiff_t;
+#endif
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef long            __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+typedef __kernel_uid_t  __kernel_old_uid_t;
+typedef __kernel_gid_t  __kernel_old_gid_t;
+typedef unsigned int    __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long      __kernel_loff_t;
+#endif
+
+typedef struct {
+#if (_MIPS_SZLONG == 32)
+        long    val[2];
+#endif
+#if (_MIPS_SZLONG == 64)
+        int     val[2];
+#endif
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+        unsigned long *__tmp = __p->fds_bits;
+        int __i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                case 16:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        __tmp[ 8] = 0; __tmp[ 9] = 0;
+                        __tmp[10] = 0; __tmp[11] = 0;
+                        __tmp[12] = 0; __tmp[13] = 0;
+                        __tmp[14] = 0; __tmp[15] = 0;
+                        return;
+
+                case 8:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        return;
+
+                case 4:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        return;
+                }
+        }
+        __i = __FDSET_LONGS;
+        while (__i) {
+                __i--;
+                *__tmp = 0;
+                __tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* _ASM_POSIX_TYPES_H */
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h
new file mode 100644
index 000000000000..17850834ccb0
--- /dev/null
+++ b/arch/mips/include/asm/prefetch.h
@@ -0,0 +1,87 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_PREFETCH_H
+#define __ASM_PREFETCH_H
+
+
+/*
+ * R5000 and RM5200 implements pref and prefx instructions but they're nops, so
+ * rather than wasting time we pretend these processors don't support
+ * prefetching at all.
+ *
+ * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
+ * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
+ *
+ * Hell (and the book on my shelf I can't open ...) know what the R8000 does.
+ *
+ * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
+ * Pref_PrepareForStore also.
+ *
+ * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
+ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
+ * current versions due to erratum G105.
+ *
+ * VR7701 only implements the Load prefetch.
+ *
+ * Finally MIPS32 and MIPS64 implement all of the following hints.
+ */
+
+#define Pref_Load                       0
+#define Pref_Store                      1
+                                                /* 2 and 3 are reserved */
+#define Pref_LoadStreamed               4
+#define Pref_StoreStreamed              5
+#define Pref_LoadRetained               6
+#define Pref_StoreRetained              7
+                                                /* 8 ... 24 are reserved */
+#define Pref_WriteBackInvalidate        25
+#define Pref_PrepareForStore            30
+
+#ifdef __ASSEMBLY__
+
+        .macro  __pref hint addr
+#ifdef CONFIG_CPU_HAS_PREFETCH
+        pref    \hint, \addr
+#endif
+        .endm
+
+        .macro  pref_load addr
+        __pref  Pref_Load, \addr
+        .endm
+
+        .macro  pref_store addr
+        __pref  Pref_Store, \addr
+        .endm
+
+        .macro  pref_load_streamed addr
+        __pref  Pref_LoadStreamed, \addr
+        .endm
+
+        .macro  pref_store_streamed addr
+        __pref  Pref_StoreStreamed, \addr
+        .endm
+
+        .macro  pref_load_retained addr
+        __pref  Pref_LoadRetained, \addr
+        .endm
+
+        .macro  pref_store_retained addr
+        __pref  Pref_StoreRetained, \addr
+        .endm
+
+        .macro  pref_wback_inv addr
+        __pref  Pref_WriteBackInvalidate, \addr
+        .endm
+
+        .macro  pref_prepare_for_store addr
+        __pref  Pref_PrepareForStore, \addr
+        .endm
+
+#endif
+
+#endif /* __ASM_PREFETCH_H */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
new file mode 100644
index 000000000000..18ee58e39445
--- /dev/null
+++ b/arch/mips/include/asm/processor.h
@@ -0,0 +1,283 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PROCESSOR_H
+#define _ASM_PROCESSOR_H
+
+#include <linux/cpumask.h>
+#include <linux/threads.h>
+
+#include <asm/cachectl.h>
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+#include <asm/mipsregs.h>
+#include <asm/prefetch.h>
+#include <asm/system.h>
+
+/*
+ * Return current * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+/*
+ * System setup and hardware flags..
+ */
+extern void (*cpu_wait)(void);
+
+extern unsigned int vced_count, vcei_count;
+
+#ifdef CONFIG_32BIT
+/*
+ * User space process size: 2GB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.
+ */
+#define TASK_SIZE       0x7fff8000UL
+#define STACK_TOP       TASK_SIZE
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE      ((TASK_SIZE / 3) & ~(PAGE_SIZE))
+#endif
+
+#ifdef CONFIG_64BIT
+/*
+ * User space process size: 1TB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.  TASK_SIZE
+ * is limited to 1TB by the R4000 architecture; R10000 and better can
+ * support 16TB; the architectural reserve for future expansion is
+ * 8192EB ...
+ */
+#define TASK_SIZE32     0x7fff8000UL
+#define TASK_SIZE       0x10000000000UL
+#define STACK_TOP       \
+      (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE                                              \
+        (test_thread_flag(TIF_32BIT_ADDR) ?                             \
+                PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
+#define TASK_SIZE_OF(tsk)                                               \
+        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
+#endif
+
+#ifdef __KERNEL__
+#define STACK_TOP_MAX   TASK_SIZE
+#endif
+
+#define NUM_FPU_REGS    32
+
+typedef __u64 fpureg_t;
+
+/*
+ * It would be nice to add some more fields for emulator statistics, but there
+ * are a number of fixed offsets in offset.h and elsewhere that would have to
+ * be recalculated by hand.  So the additional information will be private to
+ * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
+ */
+
+struct mips_fpu_struct {
+        fpureg_t        fpr[NUM_FPU_REGS];
+        unsigned int    fcr31;
+};
+
+#define NUM_DSP_REGS   6
+
+typedef __u32 dspreg_t;
+
+struct mips_dsp_state {
+        dspreg_t        dspr[NUM_DSP_REGS];
+        unsigned int    dspcontrol;
+};
+
+#define INIT_CPUMASK { \
+        {0,} \
+}
+
+struct mips3264_watch_reg_state {
+        /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
+           64 bit kernel.  We use unsigned long as it has the same
+           property. */
+        unsigned long watchlo[NUM_WATCH_REGS];
+        /* Only the mask and IRW bits from watchhi. */
+        u16 watchhi[NUM_WATCH_REGS];
+};
+
+union mips_watch_reg_state {
+        struct mips3264_watch_reg_state mips3264;
+};
+
+typedef struct {
+        unsigned long seg;
+} mm_segment_t;
+
+#define ARCH_MIN_TASKALIGN      8
+
+struct mips_abi;
+
+/*
+ * If you change thread_struct remember to change the #defines below too!
+ */
+struct thread_struct {
+        /* Saved main processor registers. */
+        unsigned long reg16;
+        unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
+        unsigned long reg29, reg30, reg31;
+
+        /* Saved cp0 stuff. */
+        unsigned long cp0_status;
+
+        /* Saved fpu/fpu emulator stuff. */
+        struct mips_fpu_struct fpu;
+#ifdef CONFIG_MIPS_MT_FPAFF
+        /* Emulated instruction count */
+        unsigned long emulated_fp;
+        /* Saved per-thread scheduler affinity mask */
+        cpumask_t user_cpus_allowed;
+#endif /* CONFIG_MIPS_MT_FPAFF */
+
+        /* Saved state of the DSP ASE, if available. */
+        struct mips_dsp_state dsp;
+
+        /* Saved watch register state, if available. */
+        union mips_watch_reg_state watch;
+
+        /* Other stuff associated with the thread. */
+        unsigned long cp0_badvaddr;     /* Last user fault */
+        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
+        unsigned long error_code;
+        unsigned long trap_no;
+        unsigned long irix_trampoline;  /* Wheee... */
+        unsigned long irix_oldctx;
+        struct mips_abi *abi;
+};
+
+#ifdef CONFIG_MIPS_MT_FPAFF
+#define FPAFF_INIT                                              \
+        .emulated_fp                    = 0,                    \
+        .user_cpus_allowed              = INIT_CPUMASK,
+#else
+#define FPAFF_INIT
+#endif /* CONFIG_MIPS_MT_FPAFF */
+
+#define INIT_THREAD  {                                          \
+        /*                                                      \
+         * Saved main processor registers                       \
+         */                                                     \
+        .reg16                  = 0,                            \
+        .reg17                  = 0,                            \
+        .reg18                  = 0,                            \
+        .reg19                  = 0,                            \
+        .reg20                  = 0,                            \
+        .reg21                  = 0,                            \
+        .reg22                  = 0,                            \
+        .reg23                  = 0,                            \
+        .reg29                  = 0,                            \
+        .reg30                  = 0,                            \
+        .reg31                  = 0,                            \
+        /*                                                      \
+         * Saved cp0 stuff                                      \
+         */                                                     \
+        .cp0_status             = 0,                            \
+        /*                                                      \
+         * Saved FPU/FPU emulator stuff                         \
+         */                                                     \
+        .fpu                    = {                             \
+                .fpr            = {0,},                         \
+                .fcr31          = 0,                            \
+        },                                                      \
+        /*                                                      \
+         * FPU affinity state (null if not FPAFF)               \
+         */                                                     \
+        FPAFF_INIT                                              \
+        /*                                                      \
+         * Saved DSP stuff                                      \
+         */                                                     \
+        .dsp                    = {                             \
+                .dspr           = {0, },                        \
+                .dspcontrol     = 0,                            \
+        },                                                      \
+        /*                                                      \
+         * saved watch register stuff                           \
+         */                                                     \
+        .watch = {{{0,},},},                                    \
+        /*                                                      \
+         * Other stuff associated with the process              \
+         */                                                     \
+        .cp0_badvaddr           = 0,                            \
+        .cp0_baduaddr           = 0,                            \
+        .error_code             = 0,                            \
+        .trap_no                = 0,                            \
+        .irix_trampoline        = 0,                            \
+        .irix_oldctx            = 0,                            \
+}
+
+struct task_struct;
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+extern unsigned long thread_saved_pc(struct task_struct *tsk);
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32)
+#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk) - 1)
+#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
+#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
+#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
+
+#define cpu_relax()     barrier()
+
+/*
+ * Return_address is a replacement for __builtin_return_address(count)
+ * which on certain architectures cannot reasonably be implemented in GCC
+ * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
+ * Note that __builtin_return_address(x>=1) is forbidden because GCC
+ * aborts compilation on some CPUs.  It's simply not possible to unwind
+ * some CPU's stackframes.
+ *
+ * __builtin_return_address works only for non-leaf functions.  We avoid the
+ * overhead of a function call by forcing the compiler to save the return
+ * address register on the stack.
+ */
+#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
+
+#ifdef CONFIG_CPU_HAS_PREFETCH
+
+#define ARCH_HAS_PREFETCH
+
+static inline void prefetch(const void *addr)
+{
+        __asm__ __volatile__(
+        "       .set    mips4           \n"
+        "       pref    %0, (%1)        \n"
+        "       .set    mips0           \n"
+        :
+        : "i" (Pref_Load), "r" (addr));
+}
+
+#endif
+
+#endif /* _ASM_PROCESSOR_H */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
new file mode 100644
index 000000000000..9c22571b160d
--- /dev/null
+++ b/arch/mips/include/asm/ptrace.h
@@ -0,0 +1,154 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PTRACE_H
+#define _ASM_PTRACE_H
+
+#ifdef CONFIG_64BIT
+#define __ARCH_WANT_COMPAT_SYS_PTRACE
+#endif
+
+/* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
+#define FPR_BASE        32
+#define PC              64
+#define CAUSE           65
+#define BADVADDR        66
+#define MMHI            67
+#define MMLO            68
+#define FPC_CSR         69
+#define FPC_EIR         70
+#define DSP_BASE        71              /* 3 more hi / lo register pairs */
+#define DSP_CONTROL     77
+#define ACX             78
+
+/*
+ * This struct defines the way the registers are stored on the stack during a
+ * system call/exception. As usual the registers k0/k1 aren't being saved.
+ */
+struct pt_regs {
+#ifdef CONFIG_32BIT
+        /* Pad bytes for argument save space on the stack. */
+        unsigned long pad0[6];
+#endif
+
+        /* Saved main processor registers. */
+        unsigned long regs[32];
+
+        /* Saved special registers. */
+        unsigned long cp0_status;
+        unsigned long hi;
+        unsigned long lo;
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+        unsigned long acx;
+#endif
+        unsigned long cp0_badvaddr;
+        unsigned long cp0_cause;
+        unsigned long cp0_epc;
+#ifdef CONFIG_MIPS_MT_SMTC
+        unsigned long cp0_tcstatus;
+#endif /* CONFIG_MIPS_MT_SMTC */
+} __attribute__ ((aligned (8)));
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS          12
+#define PTRACE_SETREGS          13
+#define PTRACE_GETFPREGS                14
+#define PTRACE_SETFPREGS                15
+/* #define PTRACE_GETFPXREGS            18 */
+/* #define PTRACE_SETFPXREGS            19 */
+
+#define PTRACE_OLDSETOPTIONS    21
+
+#define PTRACE_GET_THREAD_AREA  25
+#define PTRACE_SET_THREAD_AREA  26
+
+/* Calls to trace a 64bit program from a 32bit program.  */
+#define PTRACE_PEEKTEXT_3264    0xc0
+#define PTRACE_PEEKDATA_3264    0xc1
+#define PTRACE_POKETEXT_3264    0xc2
+#define PTRACE_POKEDATA_3264    0xc3
+#define PTRACE_GET_THREAD_AREA_3264     0xc4
+
+/* Read and write watchpoint registers.  */
+enum pt_watch_style {
+        pt_watch_style_mips32,
+        pt_watch_style_mips64
+};
+struct mips32_watch_regs {
+        uint32_t watchlo[8];
+        /* Lower 16 bits of watchhi. */
+        uint16_t watchhi[8];
+        /* Valid mask and I R W bits.
+         * bit 0 -- 1 if W bit is usable.
+         * bit 1 -- 1 if R bit is usable.
+         * bit 2 -- 1 if I bit is usable.
+         * bits 3 - 11 -- Valid watchhi mask bits.
+         */
+        uint16_t watch_masks[8];
+        /* The number of valid watch register pairs.  */
+        uint32_t num_valid;
+} __attribute__((aligned(8)));
+
+struct mips64_watch_regs {
+        uint64_t watchlo[8];
+        uint16_t watchhi[8];
+        uint16_t watch_masks[8];
+        uint32_t num_valid;
+} __attribute__((aligned(8)));
+
+struct pt_watch_regs {
+        enum pt_watch_style style;
+        union {
+                struct mips32_watch_regs mips32;
+                struct mips32_watch_regs mips64;
+        };
+};
+
+#define PTRACE_GET_WATCH_REGS   0xd0
+#define PTRACE_SET_WATCH_REGS   0xd1
+
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <asm/isadep.h>
+
+struct task_struct;
+
+extern int ptrace_getregs(struct task_struct *child, __s64 __user *data);
+extern int ptrace_setregs(struct task_struct *child, __s64 __user *data);
+
+extern int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
+extern int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
+
+extern int ptrace_get_watch_regs(struct task_struct *child,
+        struct pt_watch_regs __user *addr);
+extern int ptrace_set_watch_regs(struct task_struct *child,
+        struct pt_watch_regs __user *addr);
+
+/*
+ * Does the process account for user or for system time?
+ */
+#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
+
+#define instruction_pointer(regs) ((regs)->cp0_epc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
+
+extern NORET_TYPE void die(const char *, const struct pt_regs *) ATTRIB_NORET;
+
+static inline void die_if_kernel(const char *str, const struct pt_regs *regs)
+{
+        if (unlikely(!user_mode(regs)))
+                die(str, regs);
+}
+
+#endif
+
+#endif /* _ASM_PTRACE_H */
diff --git a/arch/mips/include/asm/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h
new file mode 100644
index 000000000000..a37d12b3b61c
--- /dev/null
+++ b/arch/mips/include/asm/r4k-timer.h
@@ -0,0 +1,30 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_R4K_TYPES_H
+#define __ASM_R4K_TYPES_H
+
+#include <linux/compiler.h>
+
+#ifdef CONFIG_SYNC_R4K
+
+extern void synchronise_count_master(void);
+extern void synchronise_count_slave(void);
+
+#else
+
+static inline void synchronise_count_master(void)
+{
+}
+
+static inline void synchronise_count_slave(void)
+{
+}
+
+#endif
+
+#endif /* __ASM_R4K_TYPES_H */
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
new file mode 100644
index 000000000000..4c140db36786
--- /dev/null
+++ b/arch/mips/include/asm/r4kcache.h
@@ -0,0 +1,443 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Inline assembly cache operations.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_R4KCACHE_H
+#define _ASM_R4KCACHE_H
+
+#include <asm/asm.h>
+#include <asm/cacheops.h>
+#include <asm/cpu-features.h>
+#include <asm/mipsmtregs.h>
+
+/*
+ * This macro return a properly sign-extended address suitable as base address
+ * for indexed cache operations.  Two issues here:
+ *
+ *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive
+ *    the index bits from the virtual address.  This breaks with tradition
+ *    set by the R4000.  To keep unpleasant surprises from happening we pick
+ *    an address in KSEG0 / CKSEG0.
+ *  - We need a properly sign extended address for 64-bit code.  To get away
+ *    without ifdefs we let the compiler do it by a type cast.
+ */
+#define INDEX_BASE      CKSEG0
+
+#define cache_op(op,addr)                                               \
+        __asm__ __volatile__(                                           \
+        "       .set    push                                    \n"     \
+        "       .set    noreorder                               \n"     \
+        "       .set    mips3\n\t                               \n"     \
+        "       cache   %0, %1                                  \n"     \
+        "       .set    pop                                     \n"     \
+        :                                                               \
+        : "i" (op), "R" (*(unsigned char *)(addr)))
+
+#ifdef CONFIG_MIPS_MT
+/*
+ * Temporary hacks for SMTC debug. Optionally force single-threaded
+ * execution during I-cache flushes.
+ */
+
+#define PROTECT_CACHE_FLUSHES 1
+
+#ifdef PROTECT_CACHE_FLUSHES
+
+extern int mt_protiflush;
+extern int mt_protdflush;
+extern void mt_cflush_lockdown(void);
+extern void mt_cflush_release(void);
+
+#define BEGIN_MT_IPROT \
+        unsigned long flags = 0;                        \
+        unsigned long mtflags = 0;                      \
+        if(mt_protiflush) {                             \
+                local_irq_save(flags);                  \
+                ehb();                                  \
+                mtflags = dvpe();                       \
+                mt_cflush_lockdown();                   \
+        }
+
+#define END_MT_IPROT \
+        if(mt_protiflush) {                             \
+                mt_cflush_release();                    \
+                evpe(mtflags);                          \
+                local_irq_restore(flags);               \
+        }
+
+#define BEGIN_MT_DPROT \
+        unsigned long flags = 0;                        \
+        unsigned long mtflags = 0;                      \
+        if(mt_protdflush) {                             \
+                local_irq_save(flags);                  \
+                ehb();                                  \
+                mtflags = dvpe();                       \
+                mt_cflush_lockdown();                   \
+        }
+
+#define END_MT_DPROT \
+        if(mt_protdflush) {                             \
+                mt_cflush_release();                    \
+                evpe(mtflags);                          \
+                local_irq_restore(flags);               \
+        }
+
+#else
+
+#define BEGIN_MT_IPROT
+#define BEGIN_MT_DPROT
+#define END_MT_IPROT
+#define END_MT_DPROT
+
+#endif /* PROTECT_CACHE_FLUSHES */
+
+#define __iflush_prologue                                               \
+        unsigned long redundance;                                       \
+        extern int mt_n_iflushes;                                       \
+        BEGIN_MT_IPROT                                                  \
+        for (redundance = 0; redundance < mt_n_iflushes; redundance++) {
+
+#define __iflush_epilogue                                               \
+        END_MT_IPROT                                                    \
+        }
+
+#define __dflush_prologue                                               \
+        unsigned long redundance;                                       \
+        extern int mt_n_dflushes;                                       \
+        BEGIN_MT_DPROT                                                  \
+        for (redundance = 0; redundance < mt_n_dflushes; redundance++) {
+
+#define __dflush_epilogue \
+        END_MT_DPROT     \
+        }
+
+#define __inv_dflush_prologue __dflush_prologue
+#define __inv_dflush_epilogue __dflush_epilogue
+#define __sflush_prologue {
+#define __sflush_epilogue }
+#define __inv_sflush_prologue __sflush_prologue
+#define __inv_sflush_epilogue __sflush_epilogue
+
+#else /* CONFIG_MIPS_MT */
+
+#define __iflush_prologue {
+#define __iflush_epilogue }
+#define __dflush_prologue {
+#define __dflush_epilogue }
+#define __inv_dflush_prologue {
+#define __inv_dflush_epilogue }
+#define __sflush_prologue {
+#define __sflush_epilogue }
+#define __inv_sflush_prologue {
+#define __inv_sflush_epilogue }
+
+#endif /* CONFIG_MIPS_MT */
+
+static inline void flush_icache_line_indexed(unsigned long addr)
+{
+        __iflush_prologue
+        cache_op(Index_Invalidate_I, addr);
+        __iflush_epilogue
+}
+
+static inline void flush_dcache_line_indexed(unsigned long addr)
+{
+        __dflush_prologue
+        cache_op(Index_Writeback_Inv_D, addr);
+        __dflush_epilogue
+}
+
+static inline void flush_scache_line_indexed(unsigned long addr)
+{
+        cache_op(Index_Writeback_Inv_SD, addr);
+}
+
+static inline void flush_icache_line(unsigned long addr)
+{
+        __iflush_prologue
+        cache_op(Hit_Invalidate_I, addr);
+        __iflush_epilogue
+}
+
+static inline void flush_dcache_line(unsigned long addr)
+{
+        __dflush_prologue
+        cache_op(Hit_Writeback_Inv_D, addr);
+        __dflush_epilogue
+}
+
+static inline void invalidate_dcache_line(unsigned long addr)
+{
+        __dflush_prologue
+        cache_op(Hit_Invalidate_D, addr);
+        __dflush_epilogue
+}
+
+static inline void invalidate_scache_line(unsigned long addr)
+{
+        cache_op(Hit_Invalidate_SD, addr);
+}
+
+static inline void flush_scache_line(unsigned long addr)
+{
+        cache_op(Hit_Writeback_Inv_SD, addr);
+}
+
+#define protected_cache_op(op,addr)                             \
+        __asm__ __volatile__(                                   \
+        "       .set    push                    \n"             \
+        "       .set    noreorder               \n"             \
+        "       .set    mips3                   \n"             \
+        "1:     cache   %0, (%1)                \n"             \
+        "2:     .set    pop                     \n"             \
+        "       .section __ex_table,\"a\"       \n"             \
+        "       "STR(PTR)" 1b, 2b               \n"             \
+        "       .previous"                                      \
+        :                                                       \
+        : "i" (op), "r" (addr))
+
+/*
+ * The next two are for badland addresses like signal trampolines.
+ */
+static inline void protected_flush_icache_line(unsigned long addr)
+{
+        protected_cache_op(Hit_Invalidate_I, addr);
+}
+
+/*
+ * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
+ * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
+ * caches.  We're talking about one cacheline unnecessarily getting invalidated
+ * here so the penalty isn't overly hard.
+ */
+static inline void protected_writeback_dcache_line(unsigned long addr)
+{
+        protected_cache_op(Hit_Writeback_Inv_D, addr);
+}
+
+static inline void protected_writeback_scache_line(unsigned long addr)
+{
+        protected_cache_op(Hit_Writeback_Inv_SD, addr);
+}
+
+/*
+ * This one is RM7000-specific
+ */
+static inline void invalidate_tcache_page(unsigned long addr)
+{
+        cache_op(Page_Invalidate_T, addr);
+}
+
+#define cache16_unroll32(base,op)                                       \
+        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set noreorder                                  \n"     \
+        "       .set mips3                                      \n"     \
+        "       cache %1, 0x000(%0); cache %1, 0x010(%0)        \n"     \
+        "       cache %1, 0x020(%0); cache %1, 0x030(%0)        \n"     \
+        "       cache %1, 0x040(%0); cache %1, 0x050(%0)        \n"     \
+        "       cache %1, 0x060(%0); cache %1, 0x070(%0)        \n"     \
+        "       cache %1, 0x080(%0); cache %1, 0x090(%0)        \n"     \
+        "       cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)        \n"     \
+        "       cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)        \n"     \
+        "       cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)        \n"     \
+        "       cache %1, 0x100(%0); cache %1, 0x110(%0)        \n"     \
+        "       cache %1, 0x120(%0); cache %1, 0x130(%0)        \n"     \
+        "       cache %1, 0x140(%0); cache %1, 0x150(%0)        \n"     \
+        "       cache %1, 0x160(%0); cache %1, 0x170(%0)        \n"     \
+        "       cache %1, 0x180(%0); cache %1, 0x190(%0)        \n"     \
+        "       cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)        \n"     \
+        "       cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)        \n"     \
+        "       cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)        \n"     \
+        "       .set pop                                        \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+
+#define cache32_unroll32(base,op)                                       \
+        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set noreorder                                  \n"     \
+        "       .set mips3                                      \n"     \
+        "       cache %1, 0x000(%0); cache %1, 0x020(%0)        \n"     \
+        "       cache %1, 0x040(%0); cache %1, 0x060(%0)        \n"     \
+        "       cache %1, 0x080(%0); cache %1, 0x0a0(%0)        \n"     \
+        "       cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)        \n"     \
+        "       cache %1, 0x100(%0); cache %1, 0x120(%0)        \n"     \
+        "       cache %1, 0x140(%0); cache %1, 0x160(%0)        \n"     \
+        "       cache %1, 0x180(%0); cache %1, 0x1a0(%0)        \n"     \
+        "       cache %1, 0x1c0(%0); cache %1, 0x1e0(%0)        \n"     \
+        "       cache %1, 0x200(%0); cache %1, 0x220(%0)        \n"     \
+        "       cache %1, 0x240(%0); cache %1, 0x260(%0)        \n"     \
+        "       cache %1, 0x280(%0); cache %1, 0x2a0(%0)        \n"     \
+        "       cache %1, 0x2c0(%0); cache %1, 0x2e0(%0)        \n"     \
+        "       cache %1, 0x300(%0); cache %1, 0x320(%0)        \n"     \
+        "       cache %1, 0x340(%0); cache %1, 0x360(%0)        \n"     \
+        "       cache %1, 0x380(%0); cache %1, 0x3a0(%0)        \n"     \
+        "       cache %1, 0x3c0(%0); cache %1, 0x3e0(%0)        \n"     \
+        "       .set pop                                        \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+
+#define cache64_unroll32(base,op)                                       \
+        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set noreorder                                  \n"     \
+        "       .set mips3                                      \n"     \
+        "       cache %1, 0x000(%0); cache %1, 0x040(%0)        \n"     \
+        "       cache %1, 0x080(%0); cache %1, 0x0c0(%0)        \n"     \
+        "       cache %1, 0x100(%0); cache %1, 0x140(%0)        \n"     \
+        "       cache %1, 0x180(%0); cache %1, 0x1c0(%0)        \n"     \
+        "       cache %1, 0x200(%0); cache %1, 0x240(%0)        \n"     \
+        "       cache %1, 0x280(%0); cache %1, 0x2c0(%0)        \n"     \
+        "       cache %1, 0x300(%0); cache %1, 0x340(%0)        \n"     \
+        "       cache %1, 0x380(%0); cache %1, 0x3c0(%0)        \n"     \
+        "       cache %1, 0x400(%0); cache %1, 0x440(%0)        \n"     \
+        "       cache %1, 0x480(%0); cache %1, 0x4c0(%0)        \n"     \
+        "       cache %1, 0x500(%0); cache %1, 0x540(%0)        \n"     \
+        "       cache %1, 0x580(%0); cache %1, 0x5c0(%0)        \n"     \
+        "       cache %1, 0x600(%0); cache %1, 0x640(%0)        \n"     \
+        "       cache %1, 0x680(%0); cache %1, 0x6c0(%0)        \n"     \
+        "       cache %1, 0x700(%0); cache %1, 0x740(%0)        \n"     \
+        "       cache %1, 0x780(%0); cache %1, 0x7c0(%0)        \n"     \
+        "       .set pop                                        \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+
+#define cache128_unroll32(base,op)                                      \
+        __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set noreorder                                  \n"     \
+        "       .set mips3                                      \n"     \
+        "       cache %1, 0x000(%0); cache %1, 0x080(%0)        \n"     \
+        "       cache %1, 0x100(%0); cache %1, 0x180(%0)        \n"     \
+        "       cache %1, 0x200(%0); cache %1, 0x280(%0)        \n"     \
+        "       cache %1, 0x300(%0); cache %1, 0x380(%0)        \n"     \
+        "       cache %1, 0x400(%0); cache %1, 0x480(%0)        \n"     \
+        "       cache %1, 0x500(%0); cache %1, 0x580(%0)        \n"     \
+        "       cache %1, 0x600(%0); cache %1, 0x680(%0)        \n"     \
+        "       cache %1, 0x700(%0); cache %1, 0x780(%0)        \n"     \
+        "       cache %1, 0x800(%0); cache %1, 0x880(%0)        \n"     \
+        "       cache %1, 0x900(%0); cache %1, 0x980(%0)        \n"     \
+        "       cache %1, 0xa00(%0); cache %1, 0xa80(%0)        \n"     \
+        "       cache %1, 0xb00(%0); cache %1, 0xb80(%0)        \n"     \
+        "       cache %1, 0xc00(%0); cache %1, 0xc80(%0)        \n"     \
+        "       cache %1, 0xd00(%0); cache %1, 0xd80(%0)        \n"     \
+        "       cache %1, 0xe00(%0); cache %1, 0xe80(%0)        \n"     \
+        "       cache %1, 0xf00(%0); cache %1, 0xf80(%0)        \n"     \
+        "       .set pop                                        \n"     \
+                :                                                       \
+                : "r" (base),                                           \
+                  "i" (op));
+
+/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
+static inline void blast_##pfx##cache##lsize(void)                      \
+{                                                                       \
+        unsigned long start = INDEX_BASE;                               \
+        unsigned long end = start + current_cpu_data.desc.waysize;      \
+        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
+        unsigned long ws_end = current_cpu_data.desc.ways <<            \
+                               current_cpu_data.desc.waybit;            \
+        unsigned long ws, addr;                                         \
+                                                                        \
+        __##pfx##flush_prologue                                         \
+                                                                        \
+        for (ws = 0; ws < ws_end; ws += ws_inc)                         \
+                for (addr = start; addr < end; addr += lsize * 32)      \
+                        cache##lsize##_unroll32(addr|ws, indexop);      \
+                                                                        \
+        __##pfx##flush_epilogue                                         \
+}                                                                       \
+                                                                        \
+static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
+{                                                                       \
+        unsigned long start = page;                                     \
+        unsigned long end = page + PAGE_SIZE;                           \
+                                                                        \
+        __##pfx##flush_prologue                                         \
+                                                                        \
+        do {                                                            \
+                cache##lsize##_unroll32(start, hitop);                  \
+                start += lsize * 32;                                    \
+        } while (start < end);                                          \
+                                                                        \
+        __##pfx##flush_epilogue                                         \
+}                                                                       \
+                                                                        \
+static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
+{                                                                       \
+        unsigned long indexmask = current_cpu_data.desc.waysize - 1;    \
+        unsigned long start = INDEX_BASE + (page & indexmask);          \
+        unsigned long end = start + PAGE_SIZE;                          \
+        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
+        unsigned long ws_end = current_cpu_data.desc.ways <<            \
+                               current_cpu_data.desc.waybit;            \
+        unsigned long ws, addr;                                         \
+                                                                        \
+        __##pfx##flush_prologue                                         \
+                                                                        \
+        for (ws = 0; ws < ws_end; ws += ws_inc)                         \
+                for (addr = start; addr < end; addr += lsize * 32)      \
+                        cache##lsize##_unroll32(addr|ws, indexop);      \
+                                                                        \
+        __##pfx##flush_epilogue                                         \
+}
+
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
+
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
+
+/* build blast_xxx_range, protected_blast_xxx_range */
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
+static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
+                                                    unsigned long end)  \
+{                                                                       \
+        unsigned long lsize = cpu_##desc##_line_size();                 \
+        unsigned long addr = start & ~(lsize - 1);                      \
+        unsigned long aend = (end - 1) & ~(lsize - 1);                  \
+                                                                        \
+        __##pfx##flush_prologue                                         \
+                                                                        \
+        while (1) {                                                     \
+                prot##cache_op(hitop, addr);                            \
+                if (addr == aend)                                       \
+                        break;                                          \
+                addr += lsize;                                          \
+        }                                                               \
+                                                                        \
+        __##pfx##flush_epilogue                                         \
+}
+
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
+/* blast_inv_dcache_range */
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
+
+#endif /* _ASM_R4KCACHE_H */
diff --git a/arch/mips/include/asm/reboot.h b/arch/mips/include/asm/reboot.h
new file mode 100644
index 000000000000..e48c0bfab257
--- /dev/null
+++ b/arch/mips/include/asm/reboot.h
@@ -0,0 +1,15 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_REBOOT_H
+#define _ASM_REBOOT_H
+
+extern void (*_machine_restart)(char *command);
+extern void (*_machine_halt)(void);
+
+#endif /* _ASM_REBOOT_H */
diff --git a/arch/mips/include/asm/reg.h b/arch/mips/include/asm/reg.h
new file mode 100644
index 000000000000..634b55d7e7f6
--- /dev/null
+++ b/arch/mips/include/asm/reg.h
@@ -0,0 +1,128 @@
+/*
+ * Various register offset definitions for debuggers, core file
+ * examiners and whatnot.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 Ralf Baechle
+ * Copyright (C) 1995, 1999 Silicon Graphics
+ */
+#ifndef __ASM_MIPS_REG_H
+#define __ASM_MIPS_REG_H
+
+
+#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
+
+#define EF_R0                   6
+#define EF_R1                   7
+#define EF_R2                   8
+#define EF_R3                   9
+#define EF_R4                   10
+#define EF_R5                   11
+#define EF_R6                   12
+#define EF_R7                   13
+#define EF_R8                   14
+#define EF_R9                   15
+#define EF_R10                  16
+#define EF_R11                  17
+#define EF_R12                  18
+#define EF_R13                  19
+#define EF_R14                  20
+#define EF_R15                  21
+#define EF_R16                  22
+#define EF_R17                  23
+#define EF_R18                  24
+#define EF_R19                  25
+#define EF_R20                  26
+#define EF_R21                  27
+#define EF_R22                  28
+#define EF_R23                  29
+#define EF_R24                  30
+#define EF_R25                  31
+
+/*
+ * k0/k1 unsaved
+ */
+#define EF_R26                  32
+#define EF_R27                  33
+
+#define EF_R28                  34
+#define EF_R29                  35
+#define EF_R30                  36
+#define EF_R31                  37
+
+/*
+ * Saved special registers
+ */
+#define EF_LO                   38
+#define EF_HI                   39
+
+#define EF_CP0_EPC              40
+#define EF_CP0_BADVADDR         41
+#define EF_CP0_STATUS           42
+#define EF_CP0_CAUSE            43
+#define EF_UNUSED0              44
+
+#define EF_SIZE                 180
+
+#endif
+
+#ifdef CONFIG_64BIT
+
+#define EF_R0                    0
+#define EF_R1                    1
+#define EF_R2                    2
+#define EF_R3                    3
+#define EF_R4                    4
+#define EF_R5                    5
+#define EF_R6                    6
+#define EF_R7                    7
+#define EF_R8                    8
+#define EF_R9                    9
+#define EF_R10                  10
+#define EF_R11                  11
+#define EF_R12                  12
+#define EF_R13                  13
+#define EF_R14                  14
+#define EF_R15                  15
+#define EF_R16                  16
+#define EF_R17                  17
+#define EF_R18                  18
+#define EF_R19                  19
+#define EF_R20                  20
+#define EF_R21                  21
+#define EF_R22                  22
+#define EF_R23                  23
+#define EF_R24                  24
+#define EF_R25                  25
+
+/*
+ * k0/k1 unsaved
+ */
+#define EF_R26                  26
+#define EF_R27                  27
+
+
+#define EF_R28                  28
+#define EF_R29                  29
+#define EF_R30                  30
+#define EF_R31                  31
+
+/*
+ * Saved special registers
+ */
+#define EF_LO                   32
+#define EF_HI                   33
+
+#define EF_CP0_EPC              34
+#define EF_CP0_BADVADDR         35
+#define EF_CP0_STATUS           36
+#define EF_CP0_CAUSE            37
+
+#define EF_SIZE                 304     /* size in bytes */
+
+#endif /* CONFIG_64BIT */
+
+#endif /* __ASM_MIPS_REG_H */
diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
new file mode 100644
index 000000000000..7c8ecb6b9c40
--- /dev/null
+++ b/arch/mips/include/asm/regdef.h
@@ -0,0 +1,100 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1985 MIPS Computer Systems, Inc.
+ * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_REGDEF_H
+#define _ASM_REGDEF_H
+
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Symbolic register names for 32 bit ABI
+ */
+#define zero    $0      /* wired zero */
+#define AT      $1      /* assembler temp  - uppercase because of ".set at" */
+#define v0      $2      /* return value */
+#define v1      $3
+#define a0      $4      /* argument registers */
+#define a1      $5
+#define a2      $6
+#define a3      $7
+#define t0      $8      /* caller saved */
+#define t1      $9
+#define t2      $10
+#define t3      $11
+#define t4      $12
+#define t5      $13
+#define t6      $14
+#define t7      $15
+#define s0      $16     /* callee saved */
+#define s1      $17
+#define s2      $18
+#define s3      $19
+#define s4      $20
+#define s5      $21
+#define s6      $22
+#define s7      $23
+#define t8      $24     /* caller saved */
+#define t9      $25
+#define jp      $25     /* PIC jump register */
+#define k0      $26     /* kernel scratch */
+#define k1      $27
+#define gp      $28     /* global pointer */
+#define sp      $29     /* stack pointer */
+#define fp      $30     /* frame pointer */
+#define s8      $30     /* same like fp! */
+#define ra      $31     /* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define zero    $0      /* wired zero */
+#define AT      $at     /* assembler temp - uppercase because of ".set at" */
+#define v0      $2      /* return value - caller saved */
+#define v1      $3
+#define a0      $4      /* argument registers */
+#define a1      $5
+#define a2      $6
+#define a3      $7
+#define a4      $8      /* arg reg 64 bit; caller saved in 32 bit */
+#define ta0     $8
+#define a5      $9
+#define ta1     $9
+#define a6      $10
+#define ta2     $10
+#define a7      $11
+#define ta3     $11
+#define t0      $12     /* caller saved */
+#define t1      $13
+#define t2      $14
+#define t3      $15
+#define s0      $16     /* callee saved */
+#define s1      $17
+#define s2      $18
+#define s3      $19
+#define s4      $20
+#define s5      $21
+#define s6      $22
+#define s7      $23
+#define t8      $24     /* caller saved */
+#define t9      $25     /* callee address for PIC/temp */
+#define jp      $25     /* PIC jump register */
+#define k0      $26     /* kernel temporary */
+#define k1      $27
+#define gp      $28     /* global pointer - caller saved for PIC */
+#define sp      $29     /* stack pointer */
+#define fp      $30     /* frame pointer */
+#define s8      $30     /* callee saved */
+#define ra      $31     /* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _ASM_REGDEF_H */
diff --git a/arch/mips/include/asm/resource.h b/arch/mips/include/asm/resource.h
new file mode 100644
index 000000000000..87cb3085269c
--- /dev/null
+++ b/arch/mips/include/asm/resource.h
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_RESOURCE_H
+#define _ASM_RESOURCE_H
+
+
+/*
+ * These five resource limit IDs have a MIPS/Linux-specific ordering,
+ * the rest comes from the generic header:
+ */
+#define RLIMIT_NOFILE           5       /* max number of open files */
+#define RLIMIT_AS               6       /* address space limit */
+#define RLIMIT_RSS              7       /* max resident set size */
+#define RLIMIT_NPROC            8       /* max number of processes */
+#define RLIMIT_MEMLOCK          9       /* max locked-in-memory address space */
+
+/*
+ * SuS says limits have to be unsigned.
+ * Which makes a ton more sense anyway,
+ * but we keep the old value on MIPS32,
+ * for compatibility:
+ */
+#ifdef CONFIG_32BIT
+# define RLIM_INFINITY          0x7fffffffUL
+#endif
+
+#include <asm-generic/resource.h>
+
+#endif /* _ASM_RESOURCE_H */
diff --git a/arch/mips/include/asm/rm9k-ocd.h b/arch/mips/include/asm/rm9k-ocd.h
new file mode 100644
index 000000000000..b0b80d9ecf96
--- /dev/null
+++ b/arch/mips/include/asm/rm9k-ocd.h
@@ -0,0 +1,56 @@
+/*
+ *  Copyright (C) 2004 by Basler Vision Technologies AG
+ *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#if !defined(_ASM_RM9K_OCD_H)
+#define _ASM_RM9K_OCD_H
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+
+extern volatile void __iomem * const ocd_base;
+extern volatile void __iomem * const titan_base;
+
+#define ocd_addr(__x__)         (ocd_base + (__x__))
+#define titan_addr(__x__)       (titan_base + (__x__))
+#define scram_addr(__x__)       (scram_base + (__x__))
+
+/* OCD register access */
+#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
+#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
+#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
+#define ocd_writel(__val__, __offs__) \
+        __raw_writel((__val__), ocd_addr(__offs__))
+#define ocd_writew(__val__, __offs__) \
+        __raw_writew((__val__), ocd_addr(__offs__))
+#define ocd_writeb(__val__, __offs__) \
+        __raw_writeb((__val__), ocd_addr(__offs__))
+
+/* TITAN register access - 32 bit-wide only */
+#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
+#define titan_writel(__val__, __offs__) \
+        __raw_writel((__val__), titan_addr(__offs__))
+
+/* Protect access to shared TITAN registers */
+extern spinlock_t titan_lock;
+extern int titan_irqflags;
+#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
+#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
+
+#endif  /* !defined(_ASM_RM9K_OCD_H) */
diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h
new file mode 100644
index 000000000000..4ca3063ed2ce
--- /dev/null
+++ b/arch/mips/include/asm/rtlx.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ */
+
+#ifndef __ASM_RTLX_H_
+#define __ASM_RTLX_H_
+
+#include <irq.h>
+
+#define LX_NODE_BASE 10
+
+#define MIPS_CPU_RTLX_IRQ 0
+
+#define RTLX_VERSION 2
+#define RTLX_xID 0x12345600
+#define RTLX_ID (RTLX_xID | RTLX_VERSION)
+#define RTLX_CHANNELS 8
+
+#define RTLX_CHANNEL_STDIO      0
+#define RTLX_CHANNEL_DBG        1
+#define RTLX_CHANNEL_SYSIO      2
+
+extern int rtlx_open(int index, int can_sleep);
+extern int rtlx_release(int index);
+extern ssize_t rtlx_read(int index, void __user *buff, size_t count);
+extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count);
+extern unsigned int rtlx_read_poll(int index, int can_sleep);
+extern unsigned int rtlx_write_poll(int index);
+
+enum rtlx_state {
+        RTLX_STATE_UNUSED = 0,
+        RTLX_STATE_INITIALISED,
+        RTLX_STATE_REMOTE_READY,
+        RTLX_STATE_OPENED
+};
+
+#define RTLX_BUFFER_SIZE 2048
+
+/* each channel supports read and write.
+   linux (vpe0) reads lx_buffer  and writes rt_buffer
+   SP (vpe1) reads rt_buffer and writes lx_buffer
+*/
+struct rtlx_channel {
+        enum rtlx_state rt_state;
+        enum rtlx_state lx_state;
+
+        int buffer_size;
+
+        /* read and write indexes per buffer */
+        int rt_write, rt_read;
+        char *rt_buffer;
+
+        int lx_write, lx_read;
+        char *lx_buffer;
+};
+
+struct rtlx_info {
+        unsigned long id;
+        enum rtlx_state state;
+
+        struct rtlx_channel channel[RTLX_CHANNELS];
+};
+
+#endif /* __ASM_RTLX_H_ */
diff --git a/arch/mips/include/asm/scatterlist.h b/arch/mips/include/asm/scatterlist.h
new file mode 100644
index 000000000000..83d69fe17c9f
--- /dev/null
+++ b/arch/mips/include/asm/scatterlist.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_SCATTERLIST_H
+#define __ASM_SCATTERLIST_H
+
+#include <asm/types.h>
+
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+        unsigned long   sg_magic;
+#endif
+        unsigned long   page_link;
+        unsigned int    offset;
+        dma_addr_t      dma_address;
+        unsigned int    length;
+};
+
+/*
+ * These macros should be used after a pci_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)          ((sg)->length)
+
+#define ISA_DMA_THRESHOLD (0x00ffffffUL)
+
+#endif /* __ASM_SCATTERLIST_H */
diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h
new file mode 100644
index 000000000000..36ed44070256
--- /dev/null
+++ b/arch/mips/include/asm/seccomp.h
@@ -0,0 +1,37 @@
+#ifndef __ASM_SECCOMP_H
+
+#include <linux/thread_info.h>
+#include <linux/unistd.h>
+
+#define __NR_seccomp_read __NR_read
+#define __NR_seccomp_write __NR_write
+#define __NR_seccomp_exit __NR_exit
+#define __NR_seccomp_sigreturn __NR_rt_sigreturn
+
+/*
+ * Kludge alert:
+ *
+ * The generic seccomp code currently allows only a single compat ABI.  Until
+ * this is fixed we priorize O32 as the compat ABI over N32.
+ */
+#ifdef CONFIG_MIPS32_O32
+
+#define TIF_32BIT TIF_32BIT_REGS
+
+#define __NR_seccomp_read_32            4003
+#define __NR_seccomp_write_32           4004
+#define __NR_seccomp_exit_32            4001
+#define __NR_seccomp_sigreturn_32       4193    /* rt_sigreturn */
+
+#elif defined(CONFIG_MIPS32_N32)
+
+#define TIF_32BIT _TIF_32BIT_ADDR
+
+#define __NR_seccomp_read_32            6000
+#define __NR_seccomp_write_32           6001
+#define __NR_seccomp_exit_32            6058
+#define __NR_seccomp_sigreturn_32       6211    /* rt_sigreturn */
+
+#endif /* CONFIG_MIPS32_O32 */
+
+#endif /* __ASM_SECCOMP_H */
diff --git a/arch/mips/include/asm/sections.h b/arch/mips/include/asm/sections.h
new file mode 100644
index 000000000000..b7e37262c246
--- /dev/null
+++ b/arch/mips/include/asm/sections.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_SECTIONS_H
+#define _ASM_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif /* _ASM_SECTIONS_H */
diff --git a/arch/mips/include/asm/segment.h b/arch/mips/include/asm/segment.h
new file mode 100644
index 000000000000..92ac001fc483
--- /dev/null
+++ b/arch/mips/include/asm/segment.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_SEGMENT_H
+#define _ASM_SEGMENT_H
+
+/* Only here because we have some old header files that expect it.. */
+
+#endif /* _ASM_SEGMENT_H */
diff --git a/arch/mips/include/asm/sembuf.h b/arch/mips/include/asm/sembuf.h
new file mode 100644
index 000000000000..7281a4decaa0
--- /dev/null
+++ b/arch/mips/include/asm/sembuf.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_SEMBUF_H
+#define _ASM_SEMBUF_H
+
+/*
+ * The semid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;              /* last semop time */
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+
+#endif /* _ASM_SEMBUF_H */
diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h
new file mode 100644
index 000000000000..c07ebd8eb9e7
--- /dev/null
+++ b/arch/mips/include/asm/serial.h
@@ -0,0 +1,22 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SERIAL_H
+#define _ASM_SERIAL_H
+
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD (1843200 / 16)
+
+#endif /* _ASM_SERIAL_H */
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h
new file mode 100644
index 000000000000..e600cedda976
--- /dev/null
+++ b/arch/mips/include/asm/setup.h
@@ -0,0 +1,10 @@
+#ifndef _MIPS_SETUP_H
+#define _MIPS_SETUP_H
+
+#define COMMAND_LINE_SIZE       256
+
+#ifdef  __KERNEL__
+extern void setup_early_printk(void);
+#endif /* __KERNEL__ */
+
+#endif /* __SETUP_H */
diff --git a/arch/mips/include/asm/sgi/gio.h b/arch/mips/include/asm/sgi/gio.h
new file mode 100644
index 000000000000..889cf028c95d
--- /dev/null
+++ b/arch/mips/include/asm/sgi/gio.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * gio.h: Definitions for SGI GIO bus
+ *
+ * Copyright (C) 2002 Ladislav Michl
+ */
+
+#ifndef _SGI_GIO_H
+#define _SGI_GIO_H
+
+/*
+ * GIO bus addresses
+ *
+ * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
+ * three physical connectors, but only two slots, GFX and EXP0.
+ *
+ * There is 10MB of GIO address space for GIO64 slot devices
+ * slot#   slot type address range            size
+ * -----   --------- ----------------------- -----
+ *   0     GFX       0x1f000000 - 0x1f3fffff   4MB
+ *   1     EXP0      0x1f400000 - 0x1f5fffff   2MB
+ *   2     EXP1      0x1f600000 - 0x1f9fffff   4MB
+ *
+ * There are un-slotted devices, HPC, I/O and misc devices, which are grouped
+ * into the HPC address space.
+ *   -     MISC      0x1fb00000 - 0x1fbfffff   1MB
+ *
+ * Following space is reserved and unused
+ *   -     RESERVED  0x18000000 - 0x1effffff 112MB
+ *
+ * GIO bus IDs
+ *
+ * Each GIO bus device identifies itself to the system by answering a
+ * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
+ * than 128 are 8 bits long, with the most significant 24 bits read from
+ * the slot undefined.
+ *
+ * 32-bit IDs are divided into
+ *      bits 0:6        the product ID; ranges from 0x00 to 0x7F.
+ *      bit 7           0=GIO Product ID is 8 bits wide
+ *                      1=GIO Product ID is 32 bits wide.
+ *      bits 8:15       manufacturer version for the product.
+ *      bit 16          0=GIO32 and GIO32-bis, 1=GIO64.
+ *      bit 17          0=no ROM present
+ *                      1=ROM present on this board AND next three words
+ *                      space define the ROM.
+ *      bits 18:31      up to manufacturer.
+ *
+ * IDs above 0x50/0xd0 are of 3rd party boards.
+ *
+ * 8-bit IDs
+ *      0x01            XPI low cost FDDI
+ *      0x02            GTR TokenRing
+ *      0x04            Synchronous ISDN
+ *      0x05            ATM board [*]
+ *      0x06            Canon Interface
+ *      0x07            16 bit SCSI Card [*]
+ *      0x08            JPEG (Double Wide)
+ *      0x09            JPEG (Single Wide)
+ *      0x0a            XPI mez. FDDI device 0
+ *      0x0b            XPI mez. FDDI device 1
+ *      0x0c            SMPTE 259M Video [*]
+ *      0x0d            Babblefish Compression [*]
+ *      0x0e            E-Plex 8-port Ethernet
+ *      0x30            Lyon Lamb IVAS
+ *      0xb8            GIO 100BaseTX Fast Ethernet (gfe)
+ *
+ * [*] Device provide 32-bit ID.
+ *
+ */
+
+#define GIO_ID(x)               (x & 0x7f)
+#define GIO_32BIT_ID            0x80
+#define GIO_REV(x)              ((x >> 8) & 0xff)
+#define GIO_64BIT_IFACE         0x10000
+#define GIO_ROM_PRESENT         0x20000
+#define GIO_VENDOR_CODE(x)      ((x >> 18) & 0x3fff)
+
+#define GIO_SLOT_GFX_BASE       0x1f000000
+#define GIO_SLOT_EXP0_BASE      0x1f400000
+#define GIO_SLOT_EXP1_BASE      0x1f600000
+
+#endif /* _SGI_GIO_H */
diff --git a/arch/mips/include/asm/sgi/hpc3.h b/arch/mips/include/asm/sgi/hpc3.h
new file mode 100644
index 000000000000..c4729f531919
--- /dev/null
+++ b/arch/mips/include/asm/sgi/hpc3.h
@@ -0,0 +1,317 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * hpc3.h: Definitions for SGI HPC3 controller
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1998 Ralf Baechle
+ */
+
+#ifndef _SGI_HPC3_H
+#define _SGI_HPC3_H
+
+#include <linux/types.h>
+#include <asm/page.h>
+
+/* An HPC DMA descriptor. */
+struct hpc_dma_desc {
+        u32 pbuf;       /* physical address of data buffer */
+        u32 cntinfo;    /* counter and info bits */
+#define HPCDMA_EOX      0x80000000 /* last desc in chain for tx */
+#define HPCDMA_EOR      0x80000000 /* last desc in chain for rx */
+#define HPCDMA_EOXP     0x40000000 /* end of packet for tx */
+#define HPCDMA_EORP     0x40000000 /* end of packet for rx */
+#define HPCDMA_XIE      0x20000000 /* irq generated when at end of this desc */
+#define HPCDMA_XIU      0x01000000 /* Tx buffer in use by CPU. */
+#define HPCDMA_EIPC     0x00ff0000 /* SEEQ ethernet special xternal bytecount */
+#define HPCDMA_ETXD     0x00008000 /* set to one by HPC when packet tx'd */
+#define HPCDMA_OWN      0x00004000 /* Denotes ring buffer ownership on rx */
+#define HPCDMA_BCNT     0x00003fff /* size in bytes of this dma buffer */
+
+        u32 pnext;      /* paddr of next hpc_dma_desc if any */
+};
+
+/* The set of regs for each HPC3 PBUS DMA channel. */
+struct hpc3_pbus_dmacregs {
+        volatile u32 pbdma_bptr;        /* pbus dma channel buffer ptr */
+        volatile u32 pbdma_dptr;        /* pbus dma channel desc ptr */
+        u32 _unused0[0x1000/4 - 2];     /* padding */
+        volatile u32 pbdma_ctrl;        /* pbus dma channel control register has
+                                         * copletely different meaning for read
+                                         * compared with write */
+        /* read */
+#define HPC3_PDMACTRL_INT       0x00000001 /* interrupt (cleared after read) */
+#define HPC3_PDMACTRL_ISACT     0x00000002 /* channel active */
+        /* write */
+#define HPC3_PDMACTRL_SEL       0x00000002 /* little endian transfer */
+#define HPC3_PDMACTRL_RCV       0x00000004 /* direction is receive */
+#define HPC3_PDMACTRL_FLSH      0x00000008 /* enable flush for receive DMA */
+#define HPC3_PDMACTRL_ACT       0x00000010 /* start dma transfer */
+#define HPC3_PDMACTRL_LD        0x00000020 /* load enable for ACT */
+#define HPC3_PDMACTRL_RT        0x00000040 /* Use realtime GIO bus servicing */
+#define HPC3_PDMACTRL_HW        0x0000ff00 /* DMA High-water mark */
+#define HPC3_PDMACTRL_FB        0x003f0000 /* Ptr to beginning of fifo */
+#define HPC3_PDMACTRL_FE        0x3f000000 /* Ptr to end of fifo */
+
+        u32 _unused1[0x1000/4 - 1];     /* padding */
+};
+
+/* The HPC3 SCSI registers, this does not include external ones. */
+struct hpc3_scsiregs {
+        volatile u32 cbptr;     /* current dma buffer ptr, diagnostic use only */
+        volatile u32 ndptr;     /* next dma descriptor ptr */
+        u32 _unused0[0x1000/4 - 2];     /* padding */
+        volatile u32 bcd;       /* byte count info */
+#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
+#define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
+#define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */
+
+        volatile u32 ctrl;    /* control register */
+#define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
+#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
+#define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
+#define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
+#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
+#define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
+#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
+#define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
+
+        volatile u32 gfptr;     /* current GIO fifo ptr */
+        volatile u32 dfptr;     /* current device fifo ptr */
+        volatile u32 dconfig;   /* DMA configuration register */
+#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
+#define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
+#define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
+#define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
+#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
+#define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
+#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
+#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
+#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
+#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
+
+        volatile u32 pconfig;   /* PIO configuration register */
+#define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
+#define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
+#define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
+#define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
+#define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
+#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
+#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
+#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
+
+        u32 _unused1[0x1000/4 - 6];     /* padding */
+};
+
+/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
+struct hpc3_ethregs {
+        /* Receiver registers. */
+        volatile u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
+        volatile u32 rx_ndptr;   /* next dma descriptor ptr */
+        u32 _unused0[0x1000/4 - 2];     /* padding */
+        volatile u32 rx_bcd;    /* byte count info */
+#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
+#define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
+#define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */
+
+        volatile u32 rx_ctrl;   /* control register */
+#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
+#define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */
+#define HPC3_ERXCTRL_STAT7  0x00000080 /* Rdonlt old/new status bit from Seeq */
+#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
+#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
+#define HPC3_ERXCTRL_AMASK  0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
+#define HPC3_ERXCTRL_RBO    0x00000800 /* Receive buffer overflow if set to 1 */
+
+        volatile u32 rx_gfptr;  /* current GIO fifo ptr */
+        volatile u32 rx_dfptr;  /* current device fifo ptr */
+        u32 _unused1;           /* padding */
+        volatile u32 reset;     /* reset register */
+#define HPC3_ERST_CRESET 0x1    /* Reset dma channel and external controller */
+#define HPC3_ERST_CLRIRQ 0x2    /* Clear channel interrupt */
+#define HPC3_ERST_LBACK  0x4    /* Enable diagnostic loopback mode of Seeq8003 */
+
+        volatile u32 dconfig;    /* DMA configuration register */
+#define HPC3_EDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
+#define HPC3_EDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
+#define HPC3_EDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
+#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
+#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
+#define HPC3_EDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
+#define HPC3_EDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
+#define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */
+
+        volatile u32 pconfig;   /* PIO configuration register */
+#define HPC3_EPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
+#define HPC3_EPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
+#define HPC3_EPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
+#define HPC3_EPCFG_TST   0x1000 /* Diagnistic ram test feature bit */
+
+        u32 _unused2[0x1000/4 - 8];     /* padding */
+
+        /* Transmitter registers. */
+        volatile u32 tx_cbptr;  /* current dma buffer ptr, diagnostic use only */
+        volatile u32 tx_ndptr;  /* next dma descriptor ptr */
+        u32 _unused3[0x1000/4 - 2];     /* padding */
+        volatile u32 tx_bcd;            /* byte count info */
+#define HPC3_ETXBCD_BCNTMSK 0x00003fff  /* bytes to be read from memory */
+#define HPC3_ETXBCD_ESAMP   0x10000000  /* if set, too late to add descriptor */
+#define HPC3_ETXBCD_XIE     0x20000000  /* Interrupt cpu at end of cur desc */
+#define HPC3_ETXBCD_EOP     0x40000000  /* Last byte of cur buf is end of packet */
+#define HPC3_ETXBCD_EOX     0x80000000  /* This buf is the end of desc chain */
+
+        volatile u32 tx_ctrl;           /* control register */
+#define HPC3_ETXCTRL_STAT30 0x0000000f  /* Rdonly copy of seeq tx stat reg */
+#define HPC3_ETXCTRL_STAT4  0x00000010  /* Indicate late collision occurred */
+#define HPC3_ETXCTRL_STAT75 0x000000e0  /* Rdonly irq status from seeq */
+#define HPC3_ETXCTRL_ENDIAN 0x00000100  /* DMA channel endian mode, 1=little 0=big */
+#define HPC3_ETXCTRL_ACTIVE 0x00000200  /* DMA tx channel is active */
+#define HPC3_ETXCTRL_AMASK  0x00000400  /* Indicates ACTIVE inhibits PIO's */
+
+        volatile u32 tx_gfptr;          /* current GIO fifo ptr */
+        volatile u32 tx_dfptr;          /* current device fifo ptr */
+        u32 _unused4[0x1000/4 - 4];     /* padding */
+};
+
+struct hpc3_regs {
+        /* First regs for the PBUS 8 dma channels. */
+        struct hpc3_pbus_dmacregs pbdma[8];
+
+        /* Now the HPC scsi registers, we get two scsi reg sets. */
+        struct hpc3_scsiregs scsi_chan0, scsi_chan1;
+
+        /* The SEEQ hpc3 ethernet dma/control registers. */
+        struct hpc3_ethregs ethregs;
+
+        /* Here are where the hpc3 fifo's can be directly accessed
+         * via PIO accesses.  Under normal operation we never stick
+         * our grubby paws in here so it's just padding. */
+        u32 _unused0[0x18000/4];
+
+        /* HPC3 irq status regs.  Due to a peculiar bug you need to
+         * look at two different register addresses to get at all of
+         * the status bits.  The first reg can only reliably report
+         * bits 4:0 of the status, and the second reg can only
+         * reliably report bits 9:5 of the hpc3 irq status.  I told
+         * you it was a peculiar bug. ;-)
+         */
+        volatile u32 istat0;            /* Irq status, only bits <4:0> reliable. */
+#define HPC3_ISTAT_PBIMASK      0x0ff   /* irq bits for pbus devs 0 --> 7 */
+#define HPC3_ISTAT_SC0MASK      0x100   /* irq bit for scsi channel 0 */
+#define HPC3_ISTAT_SC1MASK      0x200   /* irq bit for scsi channel 1 */
+
+        volatile u32 gio_misc;          /* GIO misc control bits. */
+#define HPC3_GIOMISC_ERTIME     0x1     /* Enable external timer real time. */
+#define HPC3_GIOMISC_DENDIAN    0x2     /* dma descriptor endian, 1=lit 0=big */
+
+        u32 eeprom;                     /* EEPROM data reg. */
+#define HPC3_EEPROM_EPROT       0x01    /* Protect register enable */
+#define HPC3_EEPROM_CSEL        0x02    /* Chip select */
+#define HPC3_EEPROM_ECLK        0x04    /* EEPROM clock */
+#define HPC3_EEPROM_DATO        0x08    /* Data out */
+#define HPC3_EEPROM_DATI        0x10    /* Data in */
+
+        volatile u32 istat1;            /* Irq status, only bits <9:5> reliable. */
+        volatile u32 bestat;            /* Bus error interrupt status reg. */
+#define HPC3_BESTAT_BLMASK      0x000ff /* Bus lane where bad parity occurred */
+#define HPC3_BESTAT_CTYPE       0x00100 /* Bus cycle type, 0=PIO 1=DMA */
+#define HPC3_BESTAT_PIDSHIFT    9
+#define HPC3_BESTAT_PIDMASK     0x3f700 /* DMA channel parity identifier */
+
+        u32 _unused1[0x14000/4 - 5];    /* padding */
+
+        /* Now direct PIO per-HPC3 peripheral access to external regs. */
+        volatile u32 scsi0_ext[256];    /* SCSI channel 0 external regs */
+        u32 _unused2[0x7c00/4];
+        volatile u32 scsi1_ext[256];    /* SCSI channel 1 external regs */
+        u32 _unused3[0x7c00/4];
+        volatile u32 eth_ext[320];      /* Ethernet external registers */
+        u32 _unused4[0x3b00/4];
+
+        /* Per-peripheral device external registers and DMA/PIO control. */
+        volatile u32 pbus_extregs[16][256];
+        volatile u32 pbus_dmacfg[8][128];
+        /* Cycles to spend in D3 for reads */
+#define HPC3_DMACFG_D3R_MASK            0x00000001
+#define HPC3_DMACFG_D3R_SHIFT           0
+        /* Cycles to spend in D4 for reads */
+#define HPC3_DMACFG_D4R_MASK            0x0000001e
+#define HPC3_DMACFG_D4R_SHIFT           1
+        /* Cycles to spend in D5 for reads */
+#define HPC3_DMACFG_D5R_MASK            0x000001e0
+#define HPC3_DMACFG_D5R_SHIFT           5
+        /* Cycles to spend in D3 for writes */
+#define HPC3_DMACFG_D3W_MASK            0x00000200
+#define HPC3_DMACFG_D3W_SHIFT           9
+        /* Cycles to spend in D4 for writes */
+#define HPC3_DMACFG_D4W_MASK            0x00003c00
+#define HPC3_DMACFG_D4W_SHIFT           10
+        /* Cycles to spend in D5 for writes */
+#define HPC3_DMACFG_D5W_MASK            0x0003c000
+#define HPC3_DMACFG_D5W_SHIFT           14
+        /* Enable 16-bit DMA access mode */
+#define HPC3_DMACFG_DS16                0x00040000
+        /* Places halfwords on high 16 bits of bus */
+#define HPC3_DMACFG_EVENHI              0x00080000
+        /* Make this device real time */
+#define HPC3_DMACFG_RTIME               0x00200000
+        /* 5 bit burst count for DMA device */
+#define HPC3_DMACFG_BURST_MASK          0x07c00000
+#define HPC3_DMACFG_BURST_SHIFT 22
+        /* Use live pbus_dreq unsynchronized signal */
+#define HPC3_DMACFG_DRQLIVE             0x08000000
+        volatile u32 pbus_piocfg[16][64];
+        /* Cycles to spend in P2 state for reads */
+#define HPC3_PIOCFG_P2R_MASK            0x00001
+#define HPC3_PIOCFG_P2R_SHIFT           0
+        /* Cycles to spend in P3 state for reads */
+#define HPC3_PIOCFG_P3R_MASK            0x0001e
+#define HPC3_PIOCFG_P3R_SHIFT           1
+        /* Cycles to spend in P4 state for reads */
+#define HPC3_PIOCFG_P4R_MASK            0x001e0
+#define HPC3_PIOCFG_P4R_SHIFT           5
+        /* Cycles to spend in P2 state for writes */
+#define HPC3_PIOCFG_P2W_MASK            0x00200
+#define HPC3_PIOCFG_P2W_SHIFT           9
+        /* Cycles to spend in P3 state for writes */
+#define HPC3_PIOCFG_P3W_MASK            0x03c00
+#define HPC3_PIOCFG_P3W_SHIFT           10
+        /* Cycles to spend in P4 state for writes */
+#define HPC3_PIOCFG_P4W_MASK            0x3c000
+#define HPC3_PIOCFG_P4W_SHIFT           14
+        /* Enable 16-bit PIO accesses */
+#define HPC3_PIOCFG_DS16                0x40000
+        /* Place even address bits in bits <15:8> */
+#define HPC3_PIOCFG_EVENHI              0x80000
+
+        /* PBUS PROM control regs. */
+        volatile u32 pbus_promwe;       /* PROM write enable register */
+#define HPC3_PROM_WENAB 0x1     /* Enable writes to the PROM */
+
+        u32 _unused5[0x0800/4 - 1];
+        volatile u32 pbus_promswap;     /* Chip select swap reg */
+#define HPC3_PROM_SWAP  0x1     /* invert GIO addr bit to select prom0 or prom1 */
+
+        u32 _unused6[0x0800/4 - 1];
+        volatile u32 pbus_gout; /* PROM general purpose output reg */
+#define HPC3_PROM_STAT  0x1     /* General purpose status bit in gout */
+
+        u32 _unused7[0x1000/4 - 1];
+        volatile u32 rtcregs[14];       /* Dallas clock registers */
+        u32 _unused8[50];
+        volatile u32 bbram[8192-50-14]; /* Battery backed ram */
+};
+
+/*
+ * It is possible to have two HPC3's within the address space on
+ * one machine, though only having one is more likely on an Indy.
+ */
+extern struct hpc3_regs *hpc3c0, *hpc3c1;
+#define HPC3_CHIP0_BASE         0x1fb80000      /* physical */
+#define HPC3_CHIP1_BASE         0x1fb00000      /* physical */
+
+extern void sgihpc_init(void);
+
+#endif /* _SGI_HPC3_H */
diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
new file mode 100644
index 000000000000..343ed15f8dc4
--- /dev/null
+++ b/arch/mips/include/asm/sgi/ioc.h
@@ -0,0 +1,200 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * ioc.h: Definitions for SGI I/O Controller
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
+ * Copyright (C) 2001, 2003 Ladislav Michl
+ */
+
+#ifndef _SGI_IOC_H
+#define _SGI_IOC_H
+
+#include <linux/types.h>
+#include <asm/sgi/pi1.h>
+
+/*
+ * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
+ * happen if you try word access them. You have been warned.
+ */
+
+struct sgioc_uart_regs {
+        u8 _ctrl1[3];
+        volatile u8 ctrl1;
+        u8 _data1[3];
+        volatile u8 data1;
+        u8 _ctrl2[3];
+        volatile u8 ctrl2;
+        u8 _data2[3];
+        volatile u8 data2;
+};
+
+struct sgioc_keyb_regs {
+        u8 _data[3];
+        volatile u8 data;
+        u8 _command[3];
+        volatile u8 command;
+};
+
+struct sgint_regs {
+        u8 _istat0[3];
+        volatile u8 istat0;             /* Interrupt status zero */
+#define SGINT_ISTAT0_FFULL      0x01
+#define SGINT_ISTAT0_SCSI0      0x02
+#define SGINT_ISTAT0_SCSI1      0x04
+#define SGINT_ISTAT0_ENET       0x08
+#define SGINT_ISTAT0_GFXDMA     0x10
+#define SGINT_ISTAT0_PPORT      0x20
+#define SGINT_ISTAT0_HPC2       0x40
+#define SGINT_ISTAT0_LIO2       0x80
+        u8 _imask0[3];
+        volatile u8 imask0;             /* Interrupt mask zero */
+        u8 _istat1[3];
+        volatile u8 istat1;             /* Interrupt status one */
+#define SGINT_ISTAT1_ISDNI      0x01
+#define SGINT_ISTAT1_PWR        0x02
+#define SGINT_ISTAT1_ISDNH      0x04
+#define SGINT_ISTAT1_LIO3       0x08
+#define SGINT_ISTAT1_HPC3       0x10
+#define SGINT_ISTAT1_AFAIL      0x20
+#define SGINT_ISTAT1_VIDEO      0x40
+#define SGINT_ISTAT1_GIO2       0x80
+        u8 _imask1[3];
+        volatile u8 imask1;             /* Interrupt mask one */
+        u8 _vmeistat[3];
+        volatile u8 vmeistat;           /* VME interrupt status */
+        u8 _cmeimask0[3];
+        volatile u8 cmeimask0;          /* VME interrupt mask zero */
+        u8 _cmeimask1[3];
+        volatile u8 cmeimask1;          /* VME interrupt mask one */
+        u8 _cmepol[3];
+        volatile u8 cmepol;             /* VME polarity */
+        u8 _tclear[3];
+        volatile u8 tclear;
+        u8 _errstat[3];
+        volatile u8 errstat;    /* Error status reg, reserved on INT2 */
+        u32 _unused0[2];
+        u8 _tcnt0[3];
+        volatile u8 tcnt0;              /* counter 0 */
+        u8 _tcnt1[3];
+        volatile u8 tcnt1;              /* counter 1 */
+        u8 _tcnt2[3];
+        volatile u8 tcnt2;              /* counter 2 */
+        u8 _tcword[3];
+        volatile u8 tcword;             /* control word */
+#define SGINT_TCWORD_BCD        0x01    /* Use BCD mode for counters */
+#define SGINT_TCWORD_MMASK      0x0e    /* Mode bitmask. */
+#define SGINT_TCWORD_MITC       0x00    /* IRQ on terminal count (doesn't work) */
+#define SGINT_TCWORD_MOS        0x02    /* One-shot IRQ mode. */
+#define SGINT_TCWORD_MRGEN      0x04    /* Normal rate generation */
+#define SGINT_TCWORD_MSWGEN     0x06    /* Square wave generator mode */
+#define SGINT_TCWORD_MSWST      0x08    /* Software strobe */
+#define SGINT_TCWORD_MHWST      0x0a    /* Hardware strobe */
+#define SGINT_TCWORD_CMASK      0x30    /* Command mask */
+#define SGINT_TCWORD_CLAT       0x00    /* Latch command */
+#define SGINT_TCWORD_CLSB       0x10    /* LSB read/write */
+#define SGINT_TCWORD_CMSB       0x20    /* MSB read/write */
+#define SGINT_TCWORD_CALL       0x30    /* Full counter read/write */
+#define SGINT_TCWORD_CNT0       0x00    /* Select counter zero */
+#define SGINT_TCWORD_CNT1       0x40    /* Select counter one */
+#define SGINT_TCWORD_CNT2       0x80    /* Select counter two */
+#define SGINT_TCWORD_CRBCK      0xc0    /* Readback command */
+};
+
+/*
+ * The timer is the good old 8254.  Unlike in PCs it's clocked at exactly 1MHz
+ */
+#define SGINT_TIMER_CLOCK       1000000
+
+/*
+ * This is the constant we're using for calibrating the counter.
+ */
+#define SGINT_TCSAMP_COUNTER    ((SGINT_TIMER_CLOCK / HZ) + 255)
+
+/* We need software copies of these because they are write only. */
+extern u8 sgi_ioc_reset, sgi_ioc_write;
+
+struct sgioc_regs {
+        struct pi1_regs pport;
+        u32 _unused0[2];
+        struct sgioc_uart_regs uart;
+        struct sgioc_keyb_regs kbdmouse;
+        u8 _gcsel[3];
+        volatile u8 gcsel;
+        u8 _genctrl[3];
+        volatile u8 genctrl;
+        u8 _panel[3];
+        volatile u8 panel;
+#define SGIOC_PANEL_POWERON     0x01
+#define SGIOC_PANEL_POWERINTR   0x02
+#define SGIOC_PANEL_VOLDNINTR   0x10
+#define SGIOC_PANEL_VOLDNHOLD   0x20
+#define SGIOC_PANEL_VOLUPINTR   0x40
+#define SGIOC_PANEL_VOLUPHOLD   0x80
+        u32 _unused1;
+        u8 _sysid[3];
+        volatile u8 sysid;
+#define SGIOC_SYSID_FULLHOUSE   0x01
+#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1)
+#define SGIOC_SYSID_CHIPREV(x)  (((x) & 0xe0) >> 5)
+        u32 _unused2;
+        u8 _read[3];
+        volatile u8 read;
+        u32 _unused3;
+        u8 _dmasel[3];
+        volatile u8 dmasel;
+#define SGIOC_DMASEL_SCLK10MHZ  0x00    /* use 10MHZ serial clock */
+#define SGIOC_DMASEL_ISDNB      0x01    /* enable isdn B */
+#define SGIOC_DMASEL_ISDNA      0x02    /* enable isdn A */
+#define SGIOC_DMASEL_PPORT      0x04    /* use parallel DMA */
+#define SGIOC_DMASEL_SCLK667MHZ 0x10    /* use 6.67MHZ serial clock */
+#define SGIOC_DMASEL_SCLKEXT    0x20    /* use external serial clock */
+        u32 _unused4;
+        u8 _reset[3];
+        volatile u8 reset;
+#define SGIOC_RESET_PPORT       0x01    /* 0=parport reset, 1=nornal */
+#define SGIOC_RESET_KBDMOUSE    0x02    /* 0=kbdmouse reset, 1=normal */
+#define SGIOC_RESET_EISA        0x04    /* 0=eisa reset, 1=normal */
+#define SGIOC_RESET_ISDN        0x08    /* 0=isdn reset, 1=normal */
+#define SGIOC_RESET_LC0OFF      0x10    /* guiness: turn led off (red, else green) */
+#define SGIOC_RESET_LC1OFF      0x20    /* guiness: turn led off (green, else amber) */
+        u32 _unused5;
+        u8 _write[3];
+        volatile u8 write;
+#define SGIOC_WRITE_NTHRESH     0x01    /* use 4.5db threshhold */
+#define SGIOC_WRITE_TPSPEED     0x02    /* use 100ohm TP speed */
+#define SGIOC_WRITE_EPSEL       0x04    /* force cable mode: 1=AUI 0=TP */
+#define SGIOC_WRITE_EASEL       0x08    /* 1=autoselect 0=manual cable selection */
+#define SGIOC_WRITE_U1AMODE     0x10    /* 1=PC 0=MAC UART mode */
+#define SGIOC_WRITE_U0AMODE     0x20    /* 1=PC 0=MAC UART mode */
+#define SGIOC_WRITE_MLO         0x40    /* 1=4.75V 0=+5V */
+#define SGIOC_WRITE_MHI         0x80    /* 1=5.25V 0=+5V */
+        u32 _unused6;
+        struct sgint_regs int3;
+        u32 _unused7[16];
+        volatile u32 extio;             /* FullHouse only */
+#define EXTIO_S0_IRQ_3          0x8000  /* S0: vid.vsync */
+#define EXTIO_S0_IRQ_2          0x4000  /* S0: gfx.fifofull */
+#define EXTIO_S0_IRQ_1          0x2000  /* S0: gfx.int */
+#define EXTIO_S0_RETRACE        0x1000
+#define EXTIO_SG_IRQ_3          0x0800  /* SG: vid.vsync */
+#define EXTIO_SG_IRQ_2          0x0400  /* SG: gfx.fifofull */
+#define EXTIO_SG_IRQ_1          0x0200  /* SG: gfx.int */
+#define EXTIO_SG_RETRACE        0x0100
+#define EXTIO_GIO_33MHZ         0x0080
+#define EXTIO_EISA_BUSERR       0x0040
+#define EXTIO_MC_BUSERR         0x0020
+#define EXTIO_HPC3_BUSERR       0x0010
+#define EXTIO_S0_STAT_1         0x0008
+#define EXTIO_S0_STAT_0         0x0004
+#define EXTIO_SG_STAT_1         0x0002
+#define EXTIO_SG_STAT_0         0x0001
+};
+
+extern struct sgioc_regs *sgioc;
+extern struct sgint_regs *sgint;
+
+#endif
diff --git a/arch/mips/include/asm/sgi/ip22.h b/arch/mips/include/asm/sgi/ip22.h
new file mode 100644
index 000000000000..c0501f91719b
--- /dev/null
+++ b/arch/mips/include/asm/sgi/ip22.h
@@ -0,0 +1,78 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * ip22.h: Definitions for SGI IP22 machines
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
+ */
+
+#ifndef _SGI_IP22_H
+#define _SGI_IP22_H
+
+/*
+ * These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts
+ * are not supported this way. Driver is supposed to allocate HPC/MC
+ * interrupt as shareable and then look to proper status bit (see
+ * HAL2 driver). This will prevent many complications, trust me ;-)
+ */
+
+#include <irq.h>
+#include <asm/sgi/ioc.h>
+
+#define SGINT_EISA      0       /* 16 EISA irq levels (Indigo2) */
+#define SGINT_CPU       MIPS_CPU_IRQ_BASE       /* MIPS CPU define 8 interrupt sources */
+#define SGINT_LOCAL0    (SGINT_CPU+8)   /* 8 local0 irq levels */
+#define SGINT_LOCAL1    (SGINT_CPU+16)  /* 8 local1 irq levels */
+#define SGINT_LOCAL2    (SGINT_CPU+24)  /* 8 local2 vectored irq levels */
+#define SGINT_LOCAL3    (SGINT_CPU+32)  /* 8 local3 vectored irq levels */
+#define SGINT_END       (SGINT_CPU+40)  /* End of 'spaces' */
+
+/*
+ * Individual interrupt definitions for the Indy and Indigo2
+ */
+
+#define SGI_SOFT_0_IRQ  SGINT_CPU + 0
+#define SGI_SOFT_1_IRQ  SGINT_CPU + 1
+#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
+#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
+#define SGI_8254_0_IRQ  SGINT_CPU + 4
+#define SGI_8254_1_IRQ  SGINT_CPU + 5
+#define SGI_BUSERR_IRQ  SGINT_CPU + 6
+#define SGI_TIMER_IRQ   SGINT_CPU + 7
+
+#define SGI_FIFO_IRQ    SGINT_LOCAL0 + 0        /* FIFO full */
+#define SGI_GIO_0_IRQ   SGI_FIFO_IRQ            /* GIO-0 */
+#define SGI_WD93_0_IRQ  SGINT_LOCAL0 + 1        /* 1st onboard WD93 */
+#define SGI_WD93_1_IRQ  SGINT_LOCAL0 + 2        /* 2nd onboard WD93 */
+#define SGI_ENET_IRQ    SGINT_LOCAL0 + 3        /* onboard ethernet */
+#define SGI_MCDMA_IRQ   SGINT_LOCAL0 + 4        /* MC DMA done */
+#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5        /* Parallel port */
+#define SGI_GIO_1_IRQ   SGINT_LOCAL0 + 6        /* GE / GIO-1 / 2nd-HPC */
+#define SGI_MAP_0_IRQ   SGINT_LOCAL0 + 7        /* Mappable interrupt 0 */
+
+#define SGI_GPL0_IRQ    SGINT_LOCAL1 + 0        /* General Purpose LOCAL1_N<0> */
+#define SGI_PANEL_IRQ   SGINT_LOCAL1 + 1        /* front panel */
+#define SGI_GPL2_IRQ    SGINT_LOCAL1 + 2        /* General Purpose LOCAL1_N<2> */
+#define SGI_MAP_1_IRQ   SGINT_LOCAL1 + 3        /* Mappable interrupt 1 */
+#define SGI_HPCDMA_IRQ  SGINT_LOCAL1 + 4        /* HPC DMA done */
+#define SGI_ACFAIL_IRQ  SGINT_LOCAL1 + 5        /* AC fail */
+#define SGI_VINO_IRQ    SGINT_LOCAL1 + 6        /* Indy VINO */
+#define SGI_GIO_2_IRQ   SGINT_LOCAL1 + 7        /* Vert retrace / GIO-2 */
+
+/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
+#define SGI_VERT_IRQ    SGINT_LOCAL2 + 0        /* INT3: newport vertical status */
+#define SGI_EISA_IRQ    SGINT_LOCAL2 + 3        /* EISA interrupts */
+#define SGI_KEYBD_IRQ   SGINT_LOCAL2 + 4        /* keyboard */
+#define SGI_SERIAL_IRQ  SGINT_LOCAL2 + 5        /* onboard serial */
+
+#define ip22_is_fullhouse()     (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
+
+extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
+extern unsigned short ip22_nvram_read(int reg);
+
+#endif
diff --git a/arch/mips/include/asm/sgi/mc.h b/arch/mips/include/asm/sgi/mc.h
new file mode 100644
index 000000000000..1576c2394de8
--- /dev/null
+++ b/arch/mips/include/asm/sgi/mc.h
@@ -0,0 +1,231 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * mc.h: Definitions for SGI Memory Controller
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1999 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+
+#ifndef _SGI_MC_H
+#define _SGI_MC_H
+
+struct sgimc_regs {
+        u32 _unused0;
+        volatile u32 cpuctrl0;  /* CPU control register 0, readwrite */
+#define SGIMC_CCTRL0_REFS       0x0000000f /* REFS mask */
+#define SGIMC_CCTRL0_EREFRESH   0x00000010 /* Memory refresh enable */
+#define SGIMC_CCTRL0_EPERRGIO   0x00000020 /* GIO parity error enable */
+#define SGIMC_CCTRL0_EPERRMEM   0x00000040 /* Main mem parity error enable */
+#define SGIMC_CCTRL0_EPERRCPU   0x00000080 /* CPU bus parity error enable */
+#define SGIMC_CCTRL0_WDOG       0x00000100 /* Watchdog timer enable */
+#define SGIMC_CCTRL0_SYSINIT    0x00000200 /* System init bit */
+#define SGIMC_CCTRL0_GFXRESET   0x00000400 /* Graphics interface reset */
+#define SGIMC_CCTRL0_EISALOCK   0x00000800 /* Lock CPU from memory for EISA */
+#define SGIMC_CCTRL0_EPERRSCMD  0x00001000 /* SysCMD bus parity error enable */
+#define SGIMC_CCTRL0_IENAB      0x00002000 /* Allow interrupts from MC */
+#define SGIMC_CCTRL0_ESNOOP     0x00004000 /* Snooping I/O enable */
+#define SGIMC_CCTRL0_EPROMWR    0x00008000 /* Prom writes from cpu enable */
+#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
+#define SGIMC_CCTRL0_LENDIAN    0x00020000 /* Put MC in little-endian mode */
+#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
+#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
+#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
+#define SGIMC_CCTRL0_GIOBTOB    0x08000000 /* Allow GIO back to back writes */
+        u32 _unused1;
+        volatile u32 cpuctrl1;  /* CPU control register 1, readwrite */
+#define SGIMC_CCTRL1_EGIOTIMEO  0x00000010 /* GIO bus timeout enable */
+#define SGIMC_CCTRL1_FIXEDEHPC  0x00001000 /* Fixed HPC endianness */
+#define SGIMC_CCTRL1_LITTLEHPC  0x00002000 /* Little endian HPC */
+#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
+#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
+#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
+#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
+
+        u32 _unused2;
+        volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
+
+        u32 _unused3;
+        volatile u32 systemid;  /* MC system ID register, readonly */
+#define SGIMC_SYSID_MASKREV     0x0000000f /* Revision of MC controller */
+#define SGIMC_SYSID_EPRESENT    0x00000010 /* Indicates presence of EISA bus */
+
+        u32 _unused4[3];
+        volatile u32 divider;   /* Divider reg for RPSS */
+
+        u32 _unused5;
+        u32 eeprom;             /* EEPROM byte reg for r4k */
+#define SGIMC_EEPROM_PRE        0x00000001 /* eeprom chip PRE pin assertion */
+#define SGIMC_EEPROM_CSEL       0x00000002 /* Active high, eeprom chip select */
+#define SGIMC_EEPROM_SECLOCK    0x00000004 /* EEPROM serial clock */
+#define SGIMC_EEPROM_SDATAO     0x00000008 /* Serial EEPROM data-out */
+#define SGIMC_EEPROM_SDATAI     0x00000010 /* Serial EEPROM data-in */
+
+        u32 _unused6[3];
+        volatile u32 rcntpre;   /* Preload refresh counter */
+
+        u32 _unused7;
+        volatile u32 rcounter;  /* Readonly refresh counter */
+
+        u32 _unused8[13];
+        volatile u32 giopar;    /* Parameter word for GIO64 */
+#define SGIMC_GIOPAR_HPC64      0x00000001 /* HPC talks to GIO using 64-bits */
+#define SGIMC_GIOPAR_GFX64      0x00000002 /* GFX talks to GIO using 64-bits */
+#define SGIMC_GIOPAR_EXP064     0x00000004 /* EXP(slot0) talks using 64-bits */
+#define SGIMC_GIOPAR_EXP164     0x00000008 /* EXP(slot1) talks using 64-bits */
+#define SGIMC_GIOPAR_EISA64     0x00000010 /* EISA bus talks 64-bits to GIO */
+#define SGIMC_GIOPAR_HPC264     0x00000020 /* 2nd HPX talks 64-bits to GIO */
+#define SGIMC_GIOPAR_RTIMEGFX   0x00000040 /* GFX device has realtime attr */
+#define SGIMC_GIOPAR_RTIMEEXP0  0x00000080 /* EXP(slot0) has realtime attr */
+#define SGIMC_GIOPAR_RTIMEEXP1  0x00000100 /* EXP(slot1) has realtime attr */
+#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
+#define SGIMC_GIOPAR_ONEBUS     0x00000400 /* Exists one GIO64 pipelined bus */
+#define SGIMC_GIOPAR_MASTERGFX  0x00000800 /* GFX can act as a bus master */
+#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
+#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
+#define SGIMC_GIOPAR_PLINEEXP0  0x00004000 /* EXP(slot0) has pipeline attr */
+#define SGIMC_GIOPAR_PLINEEXP1  0x00008000 /* EXP(slot1) has pipeline attr */
+
+        u32 _unused9;
+        volatile u32 cputp;     /* CPU bus arb time period */
+
+        u32 _unused10[3];
+        volatile u32 lbursttp;  /* Time period for long bursts */
+
+        /* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
+         * be the same size. The size encoding for supported SIMMs is bellow */
+        u32 _unused11[9];
+        volatile u32 mconfig0;  /* Memory config register zero */
+        u32 _unused12;
+        volatile u32 mconfig1;  /* Memory config register one */
+#define SGIMC_MCONFIG_BASEADDR  0x000000ff /* Base address of bank*/
+#define SGIMC_MCONFIG_RMASK     0x00001f00 /* Ram config bitmask */
+#define SGIMC_MCONFIG_BVALID    0x00002000 /* Bank is valid */
+#define SGIMC_MCONFIG_SBANKS    0x00004000 /* Number of subbanks */
+
+        u32 _unused13;
+        volatile u32 cmacc;        /* Mem access config for CPU */
+        u32 _unused14;
+        volatile u32 gmacc;        /* Mem access config for GIO */
+
+        /* This define applies to both cmacc and gmacc registers above. */
+#define SGIMC_MACC_ALIASBIG     0x20000000 /* 512MB home for alias */
+
+        /* Error address/status regs from GIO and CPU perspectives. */
+        u32 _unused15;
+        volatile u32 cerr;      /* Error address reg for CPU */
+        u32 _unused16;
+        volatile u32 cstat;     /* Status reg for CPU */
+#define SGIMC_CSTAT_RD          0x00000100 /* read parity error */
+#define SGIMC_CSTAT_PAR         0x00000200 /* CPU parity error */
+#define SGIMC_CSTAT_ADDR        0x00000400 /* memory bus error bad addr */
+#define SGIMC_CSTAT_SYSAD_PAR   0x00000800 /* sysad parity error */
+#define SGIMC_CSTAT_SYSCMD_PAR  0x00001000 /* syscmd parity error */
+#define SGIMC_CSTAT_BAD_DATA    0x00002000 /* bad data identifier */
+#define SGIMC_CSTAT_PAR_MASK    0x00001f00 /* parity error mask */
+#define SGIMC_CSTAT_RD_PAR      (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
+
+        u32 _unused17;
+        volatile u32 gerr;      /* Error address reg for GIO */
+        u32 _unused18;
+        volatile u32 gstat;     /* Status reg for GIO */
+#define SGIMC_GSTAT_RD          0x00000100 /* read parity error */
+#define SGIMC_GSTAT_WR          0x00000200 /* write parity error */
+#define SGIMC_GSTAT_TIME        0x00000400 /* GIO bus timed out */
+#define SGIMC_GSTAT_PROM        0x00000800 /* write to PROM when PROM_EN not set */
+#define SGIMC_GSTAT_ADDR        0x00001000 /* parity error on addr cycle */
+#define SGIMC_GSTAT_BC          0x00002000 /* parity error on byte count cycle */
+#define SGIMC_GSTAT_PIO_RD      0x00004000 /* read data parity on pio */
+#define SGIMC_GSTAT_PIO_WR      0x00008000 /* write data parity on pio */
+
+        /* Special hard bus locking registers. */
+        u32 _unused19;
+        volatile u32 syssembit;         /* Uni-bit system semaphore */
+        u32 _unused20;
+        volatile u32 mlock;             /* Global GIO memory access lock */
+        u32 _unused21;
+        volatile u32 elock;             /* Locks EISA from GIO accesses */
+
+        /* GIO dma control registers. */
+        u32 _unused22[15];
+        volatile u32 gio_dma_trans;     /* DMA mask to translation GIO addrs */
+        u32 _unused23;
+        volatile u32 gio_dma_sbits;     /* DMA GIO addr substitution bits */
+        u32 _unused24;
+        volatile u32 dma_intr_cause;    /* DMA IRQ cause indicator bits */
+        u32 _unused25;
+        volatile u32 dma_ctrl;          /* Main DMA control reg */
+
+        /* DMA TLB entry 0 */
+        u32 _unused26[5];
+        volatile u32 dtlb_hi0;
+        u32 _unused27;
+        volatile u32 dtlb_lo0;
+
+        /* DMA TLB entry 1 */
+        u32 _unused28;
+        volatile u32 dtlb_hi1;
+        u32 _unused29;
+        volatile u32 dtlb_lo1;
+
+        /* DMA TLB entry 2 */
+        u32 _unused30;
+        volatile u32 dtlb_hi2;
+        u32 _unused31;
+        volatile u32 dtlb_lo2;
+
+        /* DMA TLB entry 3 */
+        u32 _unused32;
+        volatile u32 dtlb_hi3;
+        u32 _unused33;
+        volatile u32 dtlb_lo3;
+
+        u32 _unused34[0x0392];
+
+        u32 _unused35;
+        volatile u32 rpsscounter;       /* Chirps at 100ns */
+
+        u32 _unused36[0x1000/4-2*4];
+
+        u32 _unused37;
+        volatile u32 maddronly;         /* Address DMA goes at */
+        u32 _unused38;
+        volatile u32 maddrpdeflts;      /* Same as above, plus set defaults */
+        u32 _unused39;
+        volatile u32 dmasz;             /* DMA count */
+        u32 _unused40;
+        volatile u32 ssize;             /* DMA stride size */
+        u32 _unused41;
+        volatile u32 gmaddronly;        /* Set GIO DMA but don't start trans */
+        u32 _unused42;
+        volatile u32 dmaddnpgo;         /* Set GIO DMA addr + start transfer */
+        u32 _unused43;
+        volatile u32 dmamode;           /* DMA mode config bit settings */
+        u32 _unused44;
+        volatile u32 dmaccount;         /* Zoom and byte count for DMA */
+        u32 _unused45;
+        volatile u32 dmastart;          /* Pedal to the metal. */
+        u32 _unused46;
+        volatile u32 dmarunning;        /* DMA op is in progress */
+        u32 _unused47;
+        volatile u32 maddrdefstart;     /* Set dma addr, defaults, and kick it */
+};
+
+extern struct sgimc_regs *sgimc;
+#define SGIMC_BASE              0x1fa00000      /* physical */
+
+/* Base location of the two ram banks found in IP2[0268] machines. */
+#define SGIMC_SEG0_BADDR        0x08000000
+#define SGIMC_SEG1_BADDR        0x20000000
+
+/* Maximum size of the above banks are per machine. */
+#define SGIMC_SEG0_SIZE_ALL             0x10000000 /* 256MB */
+#define SGIMC_SEG1_SIZE_IP20_IP22       0x08000000 /* 128MB */
+#define SGIMC_SEG1_SIZE_IP26_IP28       0x20000000 /* 512MB */
+
+extern void sgimc_init(void);
+
+#endif /* _SGI_MC_H */
diff --git a/arch/mips/include/asm/sgi/pi1.h b/arch/mips/include/asm/sgi/pi1.h
new file mode 100644
index 000000000000..c9506915dc5c
--- /dev/null
+++ b/arch/mips/include/asm/sgi/pi1.h
@@ -0,0 +1,71 @@
+/*
+ * pi1.h: Definitions for SGI PI1 parallel port
+ */
+
+#ifndef _SGI_PI1_H
+#define _SGI_PI1_H
+
+struct pi1_regs {
+        u8 _data[3];
+        volatile u8 data;
+        u8 _ctrl[3];
+        volatile u8 ctrl;
+#define PI1_CTRL_STROBE_N       0x01
+#define PI1_CTRL_AFD_N          0x02
+#define PI1_CTRL_INIT_N         0x04
+#define PI1_CTRL_SLIN_N         0x08
+#define PI1_CTRL_IRQ_ENA        0x10
+#define PI1_CTRL_DIR            0x20
+#define PI1_CTRL_SEL            0x40
+        u8 _status[3];
+        volatile u8 status;
+#define PI1_STAT_DEVID          0x03    /* bits 0-1 */
+#define PI1_STAT_NOINK          0x04    /* SGI MODE only */
+#define PI1_STAT_ERROR          0x08
+#define PI1_STAT_ONLINE         0x10
+#define PI1_STAT_PE             0x20
+#define PI1_STAT_ACK            0x40
+#define PI1_STAT_BUSY           0x80
+        u8 _dmactrl[3];
+        volatile u8 dmactrl;
+#define PI1_DMACTRL_FIFO_EMPTY  0x01    /* fifo empty R/O */
+#define PI1_DMACTRL_ABORT       0x02    /* reset DMA and internal fifo W/O */
+#define PI1_DMACTRL_STDMODE     0x00    /* bits 2-3 */
+#define PI1_DMACTRL_SGIMODE     0x04    /* bits 2-3 */
+#define PI1_DMACTRL_RICOHMODE   0x08    /* bits 2-3 */
+#define PI1_DMACTRL_HPMODE      0x0c    /* bits 2-3 */
+#define PI1_DMACTRL_BLKMODE     0x10    /* block mode */
+#define PI1_DMACTRL_FIFO_CLEAR  0x20    /* clear fifo W/O */
+#define PI1_DMACTRL_READ        0x40    /* read */
+#define PI1_DMACTRL_RUN         0x80    /* pedal to the metal */
+        u8 _intstat[3];
+        volatile u8 intstat;
+#define PI1_INTSTAT_ACK         0x04
+#define PI1_INTSTAT_FEMPTY      0x08
+#define PI1_INTSTAT_NOINK       0x10
+#define PI1_INTSTAT_ONLINE      0x20
+#define PI1_INTSTAT_ERR         0x40
+#define PI1_INTSTAT_PE          0x80
+        u8 _intmask[3];
+        volatile u8 intmask;            /* enabled low, reset high*/
+#define PI1_INTMASK_ACK         0x04
+#define PI1_INTMASK_FIFO_EMPTY  0x08
+#define PI1_INTMASK_NOINK       0x10
+#define PI1_INTMASK_ONLINE      0x20
+#define PI1_INTMASK_ERR         0x40
+#define PI1_INTMASK_PE          0x80
+        u8 _timer1[3];
+        volatile u8 timer1;
+#define PI1_TIME1               0x27
+        u8 _timer2[3];
+        volatile u8 timer2;
+#define PI1_TIME2               0x13
+        u8 _timer3[3];
+        volatile u8 timer3;
+#define PI1_TIME3               0x10
+        u8 _timer4[3];
+        volatile u8 timer4;
+#define PI1_TIME4               0x00
+};
+
+#endif
diff --git a/arch/mips/include/asm/sgi/seeq.h b/arch/mips/include/asm/sgi/seeq.h
new file mode 100644
index 000000000000..af0ffd76899d
--- /dev/null
+++ b/arch/mips/include/asm/sgi/seeq.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle
+ */
+#ifndef __ASM_SGI_SEEQ_H
+#define __ASM_SGI_SEEQ_H
+
+#include <linux/if_ether.h>
+
+#include <asm/sgi/hpc3.h>
+
+struct sgiseeq_platform_data {
+        struct hpc3_regs *hpc;
+        unsigned int irq;
+        unsigned char mac[ETH_ALEN];
+};
+
+#endif /* __ASM_SGI_SEEQ_H */
diff --git a/arch/mips/include/asm/sgi/sgi.h b/arch/mips/include/asm/sgi/sgi.h
new file mode 100644
index 000000000000..645cea7c0f8e
--- /dev/null
+++ b/arch/mips/include/asm/sgi/sgi.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * sgi.h: Definitions specific to SGI machines.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@sgi.com)
+ */
+#ifndef _ASM_SGI_SGI_H
+#define _ASM_SGI_SGI_H
+
+/* UP=UniProcessor MP=MultiProcessor(capable) */
+enum sgi_mach {
+        ip4,    /* R2k UP */
+        ip5,    /* R2k MP */
+        ip6,    /* R3k UP */
+        ip7,    /* R3k MP */
+        ip9,    /* R3k UP */
+        ip12,   /* R3kA UP, Indigo */
+        ip15,   /* R3kA MP */
+        ip17,   /* R4K UP */
+        ip19,   /* R4K MP */
+        ip20,   /* R4K UP, Indigo */
+        ip21,   /* TFP MP */
+        ip22,   /* R4x00 UP, Indigo2 */
+        ip25,   /* R10k MP */
+        ip26,   /* TFP UP, Indigo2 */
+        ip27,   /* R10k MP, R12k MP, Origin */
+        ip28,   /* R10k UP, Indigo2 */
+        ip30,   /* Octane */
+        ip32,   /* O2 */
+};
+
+extern enum sgi_mach sgimach;
+extern void sgi_sysinit(void);
+
+/* Many I/O space registers are byte sized and are contained within
+ * one byte per word, specifically the MSB, this macro helps out.
+ */
+#ifdef __MIPSEL__
+#define SGI_MSB(regaddr)   (regaddr)
+#else
+#define SGI_MSB(regaddr)   ((regaddr) | 0x3)
+#endif
+
+#endif /* _ASM_SGI_SGI_H */
diff --git a/arch/mips/include/asm/sgi/wd.h b/arch/mips/include/asm/sgi/wd.h
new file mode 100644
index 000000000000..0d6c3a4da891
--- /dev/null
+++ b/arch/mips/include/asm/sgi/wd.h
@@ -0,0 +1,20 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle
+ */
+#ifndef __ASM_SGI_WD_H
+#define __ASM_SGI_WD_H
+
+#include <asm/sgi/hpc3.h>
+
+struct sgiwd93_platform_data {
+        unsigned int unit;
+        unsigned int irq;
+        struct hpc3_scsiregs *hregs;
+        unsigned char *wdregs;
+};
+
+#endif /* __ASM_SGI_WD_H */
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
new file mode 100644
index 000000000000..bfce5c786f1c
--- /dev/null
+++ b/arch/mips/include/asm/sgialib.h
@@ -0,0 +1,124 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI ARCS firmware interface library for the Linux kernel.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 2001, 2002 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SGIALIB_H
+#define _ASM_SGIALIB_H
+
+#include <asm/sgiarcs.h>
+
+extern struct linux_romvec *romvec;
+extern int prom_argc;
+
+extern LONG *_prom_argv, *_prom_envp;
+
+/* A 32-bit ARC PROM pass arguments and environment as 32-bit pointer.
+   These macros take care of sign extension.  */
+#define prom_argv(index) ((char *) (long) _prom_argv[(index)])
+#define prom_argc(index) ((char *) (long) _prom_argc[(index)])
+
+extern int prom_flags;
+
+#define PROM_FLAG_ARCS                  1
+#define PROM_FLAG_USE_AS_CONSOLE        2
+#define PROM_FLAG_DONT_FREE_TEMP        4
+
+/* Simple char-by-char console I/O. */
+extern void prom_putchar(char c);
+extern char prom_getchar(void);
+
+/* Memory descriptor management. */
+#define PROM_MAX_PMEMBLOCKS    32
+struct prom_pmemblock {
+        LONG    base;           /* Within KSEG0 or XKPHYS. */
+        ULONG   size;           /* In bytes. */
+        ULONG   type;           /* free or prom memory */
+};
+
+/* Get next memory descriptor after CURR, returns first descriptor
+ * in chain is CURR is NULL.
+ */
+extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr);
+#define PROM_NULL_MDESC   ((struct linux_mdesc *) 0)
+
+/* Called by prom_init to setup the physical memory pmemblock
+ * array.
+ */
+extern void prom_meminit(void);
+extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
+
+/* PROM device tree library routines. */
+#define PROM_NULL_COMPONENT ((pcomponent *) 0)
+
+/* Get sibling component of THIS. */
+extern pcomponent *ArcGetPeer(pcomponent *this);
+
+/* Get child component of THIS. */
+extern pcomponent *ArcGetChild(pcomponent *this);
+
+/* Get parent component of CHILD. */
+extern pcomponent *prom_getparent(pcomponent *child);
+
+/* Copy component opaque data of component THIS into BUFFER
+ * if component THIS has opaque data.  Returns success or
+ * failure status.
+ */
+extern long prom_getcdata(void *buffer, pcomponent *this);
+
+/* Other misc. component routines. */
+extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data);
+extern long prom_delcomponent(pcomponent *this);
+extern pcomponent *prom_componentbypath(char *path);
+
+/* This is called at prom_init time to identify the
+ * ARC architecture we are running on
+ */
+extern void prom_identify_arch(void);
+
+/* Environment variable routines. */
+extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
+extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
+
+/* ARCS command line acquisition and parsing. */
+extern char *prom_getcmdline(void);
+extern void prom_init_cmdline(void);
+
+/* Acquiring info about the current time, etc. */
+extern struct linux_tinfo *prom_gettinfo(void);
+extern unsigned long prom_getrtime(void);
+
+/* File operations. */
+extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt);
+extern long prom_open(char *name, enum linux_omode md, unsigned long *fd);
+extern long prom_close(unsigned long fd);
+extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
+extern long prom_getrstatus(unsigned long fd);
+extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
+extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm);
+extern long prom_mount(char *name, enum linux_mountops op);
+extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf);
+extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk);
+
+/* Running stand-along programs. */
+extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr);
+extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp);
+extern long prom_exec(char *name, long argc, char **argv, char **envp);
+
+/* Misc. routines. */
+extern VOID prom_halt(VOID) __attribute__((noreturn));
+extern VOID prom_powerdown(VOID) __attribute__((noreturn));
+extern VOID prom_restart(VOID) __attribute__((noreturn));
+extern VOID ArcReboot(VOID) __attribute__((noreturn));
+extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn));
+extern long prom_cfgsave(VOID);
+extern struct linux_sysid *prom_getsysid(VOID);
+extern VOID ArcFlushAllCaches(VOID);
+extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID);
+
+#endif /* _ASM_SGIALIB_H */
diff --git a/arch/mips/include/asm/sgiarcs.h b/arch/mips/include/asm/sgiarcs.h
new file mode 100644
index 000000000000..721327f88601
--- /dev/null
+++ b/arch/mips/include/asm/sgiarcs.h
@@ -0,0 +1,548 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * ARC firmware interface defines.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 1999, 2001 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SGIARCS_H
+#define _ASM_SGIARCS_H
+
+#include <asm/types.h>
+#include <asm/fw/arc/types.h>
+
+/* Various ARCS error codes. */
+#define PROM_ESUCCESS                   0x00
+#define PROM_E2BIG                      0x01
+#define PROM_EACCESS                    0x02
+#define PROM_EAGAIN                     0x03
+#define PROM_EBADF                      0x04
+#define PROM_EBUSY                      0x05
+#define PROM_EFAULT                     0x06
+#define PROM_EINVAL                     0x07
+#define PROM_EIO                        0x08
+#define PROM_EISDIR                     0x09
+#define PROM_EMFILE                     0x0a
+#define PROM_EMLINK                     0x0b
+#define PROM_ENAMETOOLONG               0x0c
+#define PROM_ENODEV                     0x0d
+#define PROM_ENOENT                     0x0e
+#define PROM_ENOEXEC                    0x0f
+#define PROM_ENOMEM                     0x10
+#define PROM_ENOSPC                     0x11
+#define PROM_ENOTDIR                    0x12
+#define PROM_ENOTTY                     0x13
+#define PROM_ENXIO                      0x14
+#define PROM_EROFS                      0x15
+/* SGI ARCS specific errno's. */
+#define PROM_EADDRNOTAVAIL              0x1f
+#define PROM_ETIMEDOUT                  0x20
+#define PROM_ECONNABORTED               0x21
+#define PROM_ENOCONNECT                 0x22
+
+/* Device classes, types, and identifiers for prom
+ * device inventory queries.
+ */
+enum linux_devclass {
+        system, processor, cache, adapter, controller, peripheral, memory
+};
+
+enum linux_devtypes {
+        /* Generic stuff. */
+        Arc, Cpu, Fpu,
+
+        /* Primary insn and data caches. */
+        picache, pdcache,
+
+        /* Secondary insn, data, and combined caches. */
+        sicache, sdcache, sccache,
+
+        memdev, eisa_adapter, tc_adapter, scsi_adapter, dti_adapter,
+        multifunc_adapter, dsk_controller, tp_controller, cdrom_controller,
+        worm_controller, serial_controller, net_controller, disp_controller,
+        parallel_controller, ptr_controller, kbd_controller, audio_controller,
+        misc_controller, disk_peripheral, flpy_peripheral, tp_peripheral,
+        modem_peripheral, monitor_peripheral, printer_peripheral,
+        ptr_peripheral, kbd_peripheral, term_peripheral, line_peripheral,
+        net_peripheral, misc_peripheral, anon
+};
+
+enum linux_identifier {
+        bogus, ronly, removable, consin, consout, input, output
+};
+
+/* A prom device tree component. */
+struct linux_component {
+        enum linux_devclass     class;  /* node class */
+        enum linux_devtypes     type;   /* node type */
+        enum linux_identifier   iflags; /* node flags */
+        USHORT                  vers;   /* node version */
+        USHORT                  rev;    /* node revision */
+        ULONG                   key;    /* completely magic */
+        ULONG                   amask;  /* XXX affinity mask??? */
+        ULONG                   cdsize; /* size of configuration data */
+        ULONG                   ilen;   /* length of string identifier */
+        _PULONG                 iname;  /* string identifier */
+};
+typedef struct linux_component pcomponent;
+
+struct linux_sysid {
+        char vend[8], prod[8];
+};
+
+/* ARCS prom memory descriptors. */
+enum arcs_memtypes {
+        arcs_eblock,  /* exception block */
+        arcs_rvpage,  /* ARCS romvec page */
+        arcs_fcontig, /* Contiguous and free */
+        arcs_free,    /* Generic free memory */
+        arcs_bmem,    /* Borken memory, don't use */
+        arcs_prog,    /* A loaded program resides here */
+        arcs_atmp,    /* ARCS temporary storage area, wish Sparc OpenBoot told this */
+        arcs_aperm,   /* ARCS permanent storage... */
+};
+
+/* ARC has slightly different types than ARCS */
+enum arc_memtypes {
+        arc_eblock,  /* exception block */
+        arc_rvpage,  /* romvec page */
+        arc_free,    /* Generic free memory */
+        arc_bmem,    /* Borken memory, don't use */
+        arc_prog,    /* A loaded program resides here */
+        arc_atmp,    /* temporary storage area */
+        arc_aperm,   /* permanent storage */
+        arc_fcontig, /* Contiguous and free */
+};
+
+union linux_memtypes {
+    enum arcs_memtypes arcs;
+    enum arc_memtypes arc;
+};
+
+struct linux_mdesc {
+        union linux_memtypes type;
+        ULONG base;
+        ULONG pages;
+};
+
+/* Time of day descriptor. */
+struct linux_tinfo {
+        unsigned short yr;
+        unsigned short mnth;
+        unsigned short day;
+        unsigned short hr;
+        unsigned short min;
+        unsigned short sec;
+        unsigned short msec;
+};
+
+/* ARCS virtual dirents. */
+struct linux_vdirent {
+        ULONG namelen;
+        unsigned char attr;
+        char fname[32]; /* XXX imperical, should be a define */
+};
+
+/* Other stuff for files. */
+enum linux_omode {
+        rdonly, wronly, rdwr, wronly_creat, rdwr_creat,
+        wronly_ssede, rdwr_ssede, dirent, dirent_creat
+};
+
+enum linux_seekmode {
+        absolute, relative
+};
+
+enum linux_mountops {
+        media_load, media_unload
+};
+
+/* This prom has a bolixed design. */
+struct linux_bigint {
+#ifdef __MIPSEL__
+        u32 lo;
+        s32 hi;
+#else /* !(__MIPSEL__) */
+        s32 hi;
+        u32 lo;
+#endif
+};
+
+struct linux_finfo {
+        struct linux_bigint   begin;
+        struct linux_bigint   end;
+        struct linux_bigint   cur;
+        enum linux_devtypes   dtype;
+        unsigned long         namelen;
+        unsigned char         attr;
+        char                  name[32]; /* XXX imperical, should be define */
+};
+
+/* This describes the vector containing function pointers to the ARC
+   firmware functions.  */
+struct linux_romvec {
+        LONG    load;                   /* Load an executable image. */
+        LONG    invoke;                 /* Invoke a standalong image. */
+        LONG    exec;                   /* Load and begin execution of a
+                                           standalone image. */
+        LONG    halt;                   /* Halt the machine. */
+        LONG    pdown;                  /* Power down the machine. */
+        LONG    restart;                /* XXX soft reset??? */
+        LONG    reboot;                 /* Reboot the machine. */
+        LONG    imode;                  /* Enter PROM interactive mode. */
+        LONG    _unused1;               /* Was ReturnFromMain(). */
+
+        /* PROM device tree interface. */
+        LONG    next_component;
+        LONG    child_component;
+        LONG    parent_component;
+        LONG    component_data;
+        LONG    child_add;
+        LONG    comp_del;
+        LONG    component_by_path;
+
+        /* Misc. stuff. */
+        LONG    cfg_save;
+        LONG    get_sysid;
+
+        /* Probing for memory. */
+        LONG    get_mdesc;
+        LONG    _unused2;               /* was Signal() */
+
+        LONG    get_tinfo;
+        LONG    get_rtime;
+
+        /* File type operations. */
+        LONG    get_vdirent;
+        LONG    open;
+        LONG    close;
+        LONG    read;
+        LONG    get_rstatus;
+        LONG    write;
+        LONG    seek;
+        LONG    mount;
+
+        /* Dealing with firmware environment variables. */
+        LONG    get_evar;
+        LONG    set_evar;
+
+        LONG    get_finfo;
+        LONG    set_finfo;
+
+        /* Miscellaneous. */
+        LONG    cache_flush;
+        LONG    TestUnicodeCharacter;           /* ARC; not sure if ARCS too */
+        LONG    GetDisplayStatus;
+};
+
+/* The SGI ARCS parameter block is in a fixed location for standalone
+ * programs to access PROM facilities easily.
+ */
+typedef struct _SYSTEM_PARAMETER_BLOCK {
+        ULONG                   magic;          /* magic cookie */
+#define PROMBLOCK_MAGIC      0x53435241
+
+        ULONG                   len;            /* length of parm block */
+        USHORT                  ver;            /* ARCS firmware version */
+        USHORT                  rev;            /* ARCS firmware revision */
+        _PLONG                  rs_block;       /* Restart block. */
+        _PLONG                  dbg_block;      /* Debug block. */
+        _PLONG                  gevect;         /* XXX General vector??? */
+        _PLONG                  utlbvect;       /* XXX UTLB vector??? */
+        ULONG                   rveclen;        /* Size of romvec struct. */
+        _PVOID                  romvec;         /* Function interface. */
+        ULONG                   pveclen;        /* Length of private vector. */
+        _PVOID                  pvector;        /* Private vector. */
+        ULONG                   adap_cnt;       /* Adapter count. */
+        ULONG                   adap_typ0;      /* First adapter type. */
+        ULONG                   adap_vcnt0;     /* Adapter 0 vector count. */
+        _PVOID                  adap_vector;    /* Adapter 0 vector ptr. */
+        ULONG                   adap_typ1;      /* Second adapter type. */
+        ULONG                   adap_vcnt1;     /* Adapter 1 vector count. */
+        _PVOID                  adap_vector1;   /* Adapter 1 vector ptr. */
+        /* More adapter vectors go here... */
+} SYSTEM_PARAMETER_BLOCK, *PSYSTEM_PARAMETER_BLOCK;
+
+#define PROMBLOCK ((PSYSTEM_PARAMETER_BLOCK) (int)0xA0001000)
+#define ROMVECTOR ((struct linux_romvec *) (long)(PROMBLOCK)->romvec)
+
+/* Cache layout parameter block. */
+union linux_cache_key {
+        struct param {
+#ifdef __MIPSEL__
+                unsigned short size;
+                unsigned char lsize;
+                unsigned char bsize;
+#else /* !(__MIPSEL__) */
+                unsigned char bsize;
+                unsigned char lsize;
+                unsigned short size;
+#endif
+        } info;
+        unsigned long allinfo;
+};
+
+/* Configuration data. */
+struct linux_cdata {
+        char *name;
+        int mlen;
+        enum linux_devtypes type;
+};
+
+/* Common SGI ARCS firmware file descriptors. */
+#define SGIPROM_STDIN     0
+#define SGIPROM_STDOUT    1
+
+/* Common SGI ARCS firmware file types. */
+#define SGIPROM_ROFILE    0x01  /* read-only file */
+#define SGIPROM_HFILE     0x02  /* hidden file */
+#define SGIPROM_SFILE     0x04  /* System file */
+#define SGIPROM_AFILE     0x08  /* Archive file */
+#define SGIPROM_DFILE     0x10  /* Directory file */
+#define SGIPROM_DELFILE   0x20  /* Deleted file */
+
+/* SGI ARCS boot record information. */
+struct sgi_partition {
+        unsigned char flag;
+#define SGIPART_UNUSED 0x00
+#define SGIPART_ACTIVE 0x80
+
+        unsigned char shead, ssect, scyl; /* unused */
+        unsigned char systype; /* OS type, Irix or NT */
+        unsigned char ehead, esect, ecyl; /* unused */
+        unsigned char rsect0, rsect1, rsect2, rsect3;
+        unsigned char tsect0, tsect1, tsect2, tsect3;
+};
+
+#define SGIBBLOCK_MAGIC   0xaa55
+#define SGIBBLOCK_MAXPART 0x0004
+
+struct sgi_bootblock {
+        unsigned char _unused[446];
+        struct sgi_partition partitions[SGIBBLOCK_MAXPART];
+        unsigned short magic;
+};
+
+/* BIOS parameter block. */
+struct sgi_bparm_block {
+        unsigned short bytes_sect;    /* bytes per sector */
+        unsigned char  sect_clust;    /* sectors per cluster */
+        unsigned short sect_resv;     /* reserved sectors */
+        unsigned char  nfats;         /* # of allocation tables */
+        unsigned short nroot_dirents; /* # of root directory entries */
+        unsigned short sect_volume;   /* sectors in volume */
+        unsigned char  media_type;    /* media descriptor */
+        unsigned short sect_fat;      /* sectors per allocation table */
+        unsigned short sect_track;    /* sectors per track */
+        unsigned short nheads;        /* # of heads */
+        unsigned short nhsects;       /* # of hidden sectors */
+};
+
+struct sgi_bsector {
+        unsigned char   jmpinfo[3];
+        unsigned char   manuf_name[8];
+        struct sgi_bparm_block info;
+};
+
+/* Debugging block used with SGI symmon symbolic debugger. */
+#define SMB_DEBUG_MAGIC   0xfeeddead
+struct linux_smonblock {
+        unsigned long   magic;
+        void            (*handler)(void);  /* Breakpoint routine. */
+        unsigned long   dtable_base;       /* Base addr of dbg table. */
+        int             (*printf)(const char *fmt, ...);
+        unsigned long   btable_base;       /* Breakpoint table. */
+        unsigned long   mpflushreqs;       /* SMP cache flush request list. */
+        unsigned long   ntab;              /* Name table. */
+        unsigned long   stab;              /* Symbol table. */
+        int             smax;              /* Max # of symbols. */
+};
+
+/*
+ * Macros for calling a 32-bit ARC implementation from 64-bit code
+ */
+
+#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32)
+
+#define __arc_clobbers                                                  \
+        "$2", "$3" /* ... */, "$8", "$9", "$10", "$11",                         \
+        "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31"
+
+#define ARC_CALL0(dest)                                                 \
+({      long __res;                                                     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec)                                                   \
+        : __arc_clobbers, "$4", "$5", "$6", "$7");                      \
+        (unsigned long) __res;                                          \
+})
+
+#define ARC_CALL1(dest, a1)                                             \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec), "r" (__a1)                                       \
+        : __arc_clobbers, "$5", "$6", "$7");                            \
+        (unsigned long) __res;                                          \
+})
+
+#define ARC_CALL2(dest, a1, a2)                                         \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec), "r" (__a1), "r" (__a2)                           \
+        : __arc_clobbers, "$6", "$7");                                  \
+        __res;                                                          \
+})
+
+#define ARC_CALL3(dest, a1, a2, a3)                                     \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
+        register signed int __a3 __asm__("$6") = (int) (long) (a3);     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3)               \
+        : __arc_clobbers, "$7");                                        \
+        __res;                                                          \
+})
+
+#define ARC_CALL4(dest, a1, a2, a3, a4)                                 \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
+        register signed int __a3 __asm__("$6") = (int) (long) (a3);     \
+        register signed int __a4 __asm__("$7") = (int) (long) (a4);     \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3),              \
+          "r" (__a4)                                                    \
+        : __arc_clobbers);                                              \
+        __res;                                                          \
+})
+
+#define ARC_CALL5(dest, a1, a2, a3, a4, a5)                                     \
+({      long __res;                                                     \
+        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
+        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
+        register signed int __a3 __asm__("$6") = (int) (long) (a3);     \
+        register signed int __a4 __asm__("$7") = (int) (long) (a4);     \
+        register signed int __a5 = (int) (long) (a5);                   \
+        long __vec = (long) romvec->dest;                               \
+        __asm__ __volatile__(                                           \
+        "dsubu\t$29, 32\n\t"                                            \
+        "sw\t%7, 16($29)\n\t"                                           \
+        "jalr\t%1\n\t"                                                  \
+        "daddu\t$29, 32\n\t"                                            \
+        "move\t%0, $2"                                                  \
+        : "=r" (__res), "=r" (__vec)                                    \
+        : "1" (__vec),                                                  \
+          "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4),               \
+          "r" (__a5)                                                    \
+        : __arc_clobbers);                                              \
+        __res;                                                          \
+})
+
+#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */
+
+#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) ||         \
+    (defined(CONFIG_64BIT) && defined(CONFIG_ARC64))
+
+#define ARC_CALL0(dest)                                                 \
+({      long __res;                                                     \
+        long (*__vec)(void) = (void *) romvec->dest;                    \
+                                                                        \
+        __res = __vec();                                                \
+        __res;                                                          \
+})
+
+#define ARC_CALL1(dest, a1)                                             \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long (*__vec)(long) = (void *) romvec->dest;                    \
+                                                                        \
+        __res = __vec(__a1);                                            \
+        __res;                                                          \
+})
+
+#define ARC_CALL2(dest, a1, a2)                                         \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long (*__vec)(long, long) = (void *) romvec->dest;              \
+                                                                        \
+        __res = __vec(__a1, __a2);                                      \
+        __res;                                                          \
+})
+
+#define ARC_CALL3(dest, a1, a2, a3)                                     \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long __a3 = (long) (a3);                                        \
+        long (*__vec)(long, long, long) = (void *) romvec->dest;        \
+                                                                        \
+        __res = __vec(__a1, __a2, __a3);                                \
+        __res;                                                          \
+})
+
+#define ARC_CALL4(dest, a1, a2, a3, a4)                                 \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long __a3 = (long) (a3);                                        \
+        long __a4 = (long) (a4);                                        \
+        long (*__vec)(long, long, long, long) = (void *) romvec->dest;  \
+                                                                        \
+        __res = __vec(__a1, __a2, __a3, __a4);                          \
+        __res;                                                          \
+})
+
+#define ARC_CALL5(dest, a1, a2, a3, a4, a5)                             \
+({      long __res;                                                     \
+        long __a1 = (long) (a1);                                        \
+        long __a2 = (long) (a2);                                        \
+        long __a3 = (long) (a3);                                        \
+        long __a4 = (long) (a4);                                        \
+        long __a5 = (long) (a5);                                        \
+        long (*__vec)(long, long, long, long, long);                    \
+        __vec = (void *) romvec->dest;                                  \
+                                                                        \
+        __res = __vec(__a1, __a2, __a3, __a4, __a5);                    \
+        __res;                                                          \
+})
+#endif /* both kernel and ARC either 32-bit or 64-bit */
+
+#endif /* _ASM_SGIARCS_H */
diff --git a/arch/mips/include/asm/sgidefs.h b/arch/mips/include/asm/sgidefs.h
new file mode 100644
index 000000000000..876442fcfb32
--- /dev/null
+++ b/arch/mips/include/asm/sgidefs.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1999, 2001 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_SGIDEFS_H
+#define __ASM_SGIDEFS_H
+
+/*
+ * Using a Linux compiler for building Linux seems logic but not to
+ * everybody.
+ */
+#ifndef __linux__
+#error Use a Linux compiler or give up.
+#endif
+
+/*
+ * Definitions for the ISA levels
+ *
+ * With the introduction of MIPS32 / MIPS64 instruction sets definitions
+ * MIPS ISAs are no longer subsets of each other.  Therefore comparisons
+ * on these symbols except with == may result in unexpected results and
+ * are forbidden!
+ */
+#define _MIPS_ISA_MIPS1         1
+#define _MIPS_ISA_MIPS2         2
+#define _MIPS_ISA_MIPS3         3
+#define _MIPS_ISA_MIPS4         4
+#define _MIPS_ISA_MIPS5         5
+#define _MIPS_ISA_MIPS32        6
+#define _MIPS_ISA_MIPS64        7
+
+/*
+ * Subprogram calling convention
+ */
+#define _MIPS_SIM_ABI32         1
+#define _MIPS_SIM_NABI32        2
+#define _MIPS_SIM_ABI64         3
+
+#endif /* __ASM_SGIDEFS_H */
diff --git a/arch/mips/include/asm/shmbuf.h b/arch/mips/include/asm/shmbuf.h
new file mode 100644
index 000000000000..f994438277bf
--- /dev/null
+++ b/arch/mips/include/asm/shmbuf.h
@@ -0,0 +1,38 @@
+#ifndef _ASM_SHMBUF_H
+#define _ASM_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous 32-bit rsp. 64-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        __kernel_time_t         shm_ctime;      /* last change time */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _ASM_SHMBUF_H */
diff --git a/arch/mips/include/asm/shmparam.h b/arch/mips/include/asm/shmparam.h
new file mode 100644
index 000000000000..09290720751c
--- /dev/null
+++ b/arch/mips/include/asm/shmparam.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_SHMPARAM_H
+#define _ASM_SHMPARAM_H
+
+#define __ARCH_FORCE_SHMLBA     1
+
+#define SHMLBA 0x40000                  /* attach addr a multiple of this */
+
+#endif /* _ASM_SHMPARAM_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_int.h b/arch/mips/include/asm/sibyte/bcm1480_int.h
new file mode 100644
index 000000000000..6109557c14e9
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_int.h
@@ -0,0 +1,312 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  Interrupt Mapper definitions             File: bcm1480_int.h
+    *
+    *  This module contains constants for manipulating the
+    *  BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
+    *  definitions for the interrupt sources.
+    *
+    *  BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _BCM1480_INT_H
+#define _BCM1480_INT_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Interrupt Mapper Constants
+    ********************************************************************* */
+
+/*
+ * The interrupt mapper deals with 128-bit logical registers that are
+ * implemented as pairs of 64-bit registers, with the "low" 64 bits in
+ * a register that has an address 0x1000 higher(!) than the
+ * corresponding "high" register.
+ *
+ * For appropriate registers, bit 0 of the "high" register is a
+ * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
+ * register.
+ */
+
+/*
+ * This entire file uses _BCM1480_ in all the symbols because it is
+ * entirely BCM1480 specific.
+ */
+
+/*
+ * Interrupt sources (Table 22)
+ */
+
+#define K_BCM1480_INT_SOURCES               128
+
+#define _BCM1480_INT_HIGH(k)   (k)
+#define _BCM1480_INT_LOW(k)    ((k)+64)
+
+#define K_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_HIGH(1)
+#define K_BCM1480_INT_GPIO_0                _BCM1480_INT_HIGH(4)
+#define K_BCM1480_INT_GPIO_1                _BCM1480_INT_HIGH(5)
+#define K_BCM1480_INT_GPIO_2                _BCM1480_INT_HIGH(6)
+#define K_BCM1480_INT_GPIO_3                _BCM1480_INT_HIGH(7)
+#define K_BCM1480_INT_PCI_INTA              _BCM1480_INT_HIGH(8)
+#define K_BCM1480_INT_PCI_INTB              _BCM1480_INT_HIGH(9)
+#define K_BCM1480_INT_PCI_INTC              _BCM1480_INT_HIGH(10)
+#define K_BCM1480_INT_PCI_INTD              _BCM1480_INT_HIGH(11)
+#define K_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_HIGH(12)
+#define K_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_HIGH(13)
+#define K_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_HIGH(14)
+#define K_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_HIGH(15)
+#define K_BCM1480_INT_TIMER_0               _BCM1480_INT_HIGH(20)
+#define K_BCM1480_INT_TIMER_1               _BCM1480_INT_HIGH(21)
+#define K_BCM1480_INT_TIMER_2               _BCM1480_INT_HIGH(22)
+#define K_BCM1480_INT_TIMER_3               _BCM1480_INT_HIGH(23)
+#define K_BCM1480_INT_DM_CH_0               _BCM1480_INT_HIGH(28)
+#define K_BCM1480_INT_DM_CH_1               _BCM1480_INT_HIGH(29)
+#define K_BCM1480_INT_DM_CH_2               _BCM1480_INT_HIGH(30)
+#define K_BCM1480_INT_DM_CH_3               _BCM1480_INT_HIGH(31)
+#define K_BCM1480_INT_MAC_0                 _BCM1480_INT_HIGH(36)
+#define K_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_HIGH(37)
+#define K_BCM1480_INT_MAC_1                 _BCM1480_INT_HIGH(38)
+#define K_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_HIGH(39)
+#define K_BCM1480_INT_MAC_2                 _BCM1480_INT_HIGH(40)
+#define K_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_HIGH(41)
+#define K_BCM1480_INT_MAC_3                 _BCM1480_INT_HIGH(42)
+#define K_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_HIGH(43)
+#define K_BCM1480_INT_PMI_LOW               _BCM1480_INT_HIGH(52)
+#define K_BCM1480_INT_PMI_HIGH              _BCM1480_INT_HIGH(53)
+#define K_BCM1480_INT_PMO_LOW               _BCM1480_INT_HIGH(54)
+#define K_BCM1480_INT_PMO_HIGH              _BCM1480_INT_HIGH(55)
+#define K_BCM1480_INT_MBOX_0_0              _BCM1480_INT_HIGH(56)
+#define K_BCM1480_INT_MBOX_0_1              _BCM1480_INT_HIGH(57)
+#define K_BCM1480_INT_MBOX_0_2              _BCM1480_INT_HIGH(58)
+#define K_BCM1480_INT_MBOX_0_3              _BCM1480_INT_HIGH(59)
+#define K_BCM1480_INT_MBOX_1_0              _BCM1480_INT_HIGH(60)
+#define K_BCM1480_INT_MBOX_1_1              _BCM1480_INT_HIGH(61)
+#define K_BCM1480_INT_MBOX_1_2              _BCM1480_INT_HIGH(62)
+#define K_BCM1480_INT_MBOX_1_3              _BCM1480_INT_HIGH(63)
+
+#define K_BCM1480_INT_BAD_ECC               _BCM1480_INT_LOW(1)
+#define K_BCM1480_INT_COR_ECC               _BCM1480_INT_LOW(2)
+#define K_BCM1480_INT_IO_BUS                _BCM1480_INT_LOW(3)
+#define K_BCM1480_INT_PERF_CNT              _BCM1480_INT_LOW(4)
+#define K_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_LOW(5)
+#define K_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_LOW(6)
+#define K_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_LOW(7)
+#define K_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_LOW(8)
+#define K_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_LOW(9)
+#define K_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_LOW(10)
+#define K_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_LOW(11)
+#define K_BCM1480_INT_PCI_ERROR             _BCM1480_INT_LOW(16)
+#define K_BCM1480_INT_PCI_RESET             _BCM1480_INT_LOW(17)
+#define K_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_LOW(18)
+#define K_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_LOW(19)
+#define K_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_LOW(20)
+#define K_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_LOW(21)
+#define K_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_LOW(22)
+#define K_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_LOW(23)
+#define K_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_LOW(24)
+#define K_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_LOW(25)
+#define K_BCM1480_INT_LDT_SMI               _BCM1480_INT_LOW(32)
+#define K_BCM1480_INT_LDT_NMI               _BCM1480_INT_LOW(33)
+#define K_BCM1480_INT_LDT_INIT              _BCM1480_INT_LOW(34)
+#define K_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_LOW(35)
+#define K_BCM1480_INT_LDT_EXT               _BCM1480_INT_LOW(36)
+#define K_BCM1480_INT_SMB_0                 _BCM1480_INT_LOW(40)
+#define K_BCM1480_INT_SMB_1                 _BCM1480_INT_LOW(41)
+#define K_BCM1480_INT_PCMCIA                _BCM1480_INT_LOW(42)
+#define K_BCM1480_INT_UART_0                _BCM1480_INT_LOW(44)
+#define K_BCM1480_INT_UART_1                _BCM1480_INT_LOW(45)
+#define K_BCM1480_INT_UART_2                _BCM1480_INT_LOW(46)
+#define K_BCM1480_INT_UART_3                _BCM1480_INT_LOW(47)
+#define K_BCM1480_INT_GPIO_4                _BCM1480_INT_LOW(52)
+#define K_BCM1480_INT_GPIO_5                _BCM1480_INT_LOW(53)
+#define K_BCM1480_INT_GPIO_6                _BCM1480_INT_LOW(54)
+#define K_BCM1480_INT_GPIO_7                _BCM1480_INT_LOW(55)
+#define K_BCM1480_INT_GPIO_8                _BCM1480_INT_LOW(56)
+#define K_BCM1480_INT_GPIO_9                _BCM1480_INT_LOW(57)
+#define K_BCM1480_INT_GPIO_10               _BCM1480_INT_LOW(58)
+#define K_BCM1480_INT_GPIO_11               _BCM1480_INT_LOW(59)
+#define K_BCM1480_INT_GPIO_12               _BCM1480_INT_LOW(60)
+#define K_BCM1480_INT_GPIO_13               _BCM1480_INT_LOW(61)
+#define K_BCM1480_INT_GPIO_14               _BCM1480_INT_LOW(62)
+#define K_BCM1480_INT_GPIO_15               _BCM1480_INT_LOW(63)
+
+/*
+ * Mask values for each interrupt
+ */
+
+#define _BCM1480_INT_MASK(w, n)              _SB_MAKEMASK(w, ((n) & 0x3F))
+#define _BCM1480_INT_MASK1(n)               _SB_MAKEMASK1(((n) & 0x3F))
+#define _BCM1480_INT_OFFSET(n)              (((n) & 0x40) << 6)
+
+#define M_BCM1480_INT_CASCADE               _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
+
+#define M_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
+#define M_BCM1480_INT_GPIO_0                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
+#define M_BCM1480_INT_GPIO_1                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
+#define M_BCM1480_INT_GPIO_2                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
+#define M_BCM1480_INT_GPIO_3                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
+#define M_BCM1480_INT_PCI_INTA              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
+#define M_BCM1480_INT_PCI_INTB              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
+#define M_BCM1480_INT_PCI_INTC              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
+#define M_BCM1480_INT_PCI_INTD              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
+#define M_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
+#define M_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
+#define M_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
+#define M_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
+#define M_BCM1480_INT_TIMER_0               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
+#define M_BCM1480_INT_TIMER_1               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
+#define M_BCM1480_INT_TIMER_2               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
+#define M_BCM1480_INT_TIMER_3               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
+#define M_BCM1480_INT_DM_CH_0               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
+#define M_BCM1480_INT_DM_CH_1               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
+#define M_BCM1480_INT_DM_CH_2               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
+#define M_BCM1480_INT_DM_CH_3               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
+#define M_BCM1480_INT_MAC_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
+#define M_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
+#define M_BCM1480_INT_MAC_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
+#define M_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
+#define M_BCM1480_INT_MAC_2                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
+#define M_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
+#define M_BCM1480_INT_MAC_3                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
+#define M_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
+#define M_BCM1480_INT_PMI_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
+#define M_BCM1480_INT_PMI_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
+#define M_BCM1480_INT_PMO_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
+#define M_BCM1480_INT_PMO_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
+#define M_BCM1480_INT_MBOX_ALL              _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
+#define M_BCM1480_INT_MBOX_0_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
+#define M_BCM1480_INT_MBOX_0_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
+#define M_BCM1480_INT_MBOX_0_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
+#define M_BCM1480_INT_MBOX_0_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
+#define M_BCM1480_INT_MBOX_1_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
+#define M_BCM1480_INT_MBOX_1_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
+#define M_BCM1480_INT_MBOX_1_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
+#define M_BCM1480_INT_MBOX_1_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
+#define M_BCM1480_INT_BAD_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
+#define M_BCM1480_INT_COR_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
+#define M_BCM1480_INT_IO_BUS                _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
+#define M_BCM1480_INT_PERF_CNT              _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
+#define M_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
+#define M_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
+#define M_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
+#define M_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
+#define M_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
+#define M_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
+#define M_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
+#define M_BCM1480_INT_PCI_ERROR             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
+#define M_BCM1480_INT_PCI_RESET             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
+#define M_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
+#define M_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
+#define M_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
+#define M_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
+#define M_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
+#define M_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
+#define M_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
+#define M_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
+#define M_BCM1480_INT_LDT_SMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
+#define M_BCM1480_INT_LDT_NMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
+#define M_BCM1480_INT_LDT_INIT              _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
+#define M_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
+#define M_BCM1480_INT_LDT_EXT               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
+#define M_BCM1480_INT_SMB_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
+#define M_BCM1480_INT_SMB_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
+#define M_BCM1480_INT_PCMCIA                _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
+#define M_BCM1480_INT_UART_0                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
+#define M_BCM1480_INT_UART_1                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
+#define M_BCM1480_INT_UART_2                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
+#define M_BCM1480_INT_UART_3                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
+#define M_BCM1480_INT_GPIO_4                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
+#define M_BCM1480_INT_GPIO_5                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
+#define M_BCM1480_INT_GPIO_6                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
+#define M_BCM1480_INT_GPIO_7                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
+#define M_BCM1480_INT_GPIO_8                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
+#define M_BCM1480_INT_GPIO_9                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
+#define M_BCM1480_INT_GPIO_10               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
+#define M_BCM1480_INT_GPIO_11               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
+#define M_BCM1480_INT_GPIO_12               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
+#define M_BCM1480_INT_GPIO_13               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
+#define M_BCM1480_INT_GPIO_14               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
+#define M_BCM1480_INT_GPIO_15               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
+
+/*
+ * Interrupt mappings (Table 18)
+ */
+
+#define K_BCM1480_INT_MAP_I0    0               /* interrupt pins on processor */
+#define K_BCM1480_INT_MAP_I1    1
+#define K_BCM1480_INT_MAP_I2    2
+#define K_BCM1480_INT_MAP_I3    3
+#define K_BCM1480_INT_MAP_I4    4
+#define K_BCM1480_INT_MAP_I5    5
+#define K_BCM1480_INT_MAP_NMI   6               /* nonmaskable */
+#define K_BCM1480_INT_MAP_DINT  7               /* debug interrupt */
+
+/*
+ * Interrupt LDT Set Register (Table 19)
+ */
+
+#define S_BCM1480_INT_HT_INTMSG             0
+#define M_BCM1480_INT_HT_INTMSG             _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
+#define V_BCM1480_INT_HT_INTMSG(x)          _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
+#define G_BCM1480_INT_HT_INTMSG(x)          _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
+
+#define K_BCM1480_INT_HT_INTMSG_FIXED       0
+#define K_BCM1480_INT_HT_INTMSG_ARBITRATED  1
+#define K_BCM1480_INT_HT_INTMSG_SMI         2
+#define K_BCM1480_INT_HT_INTMSG_NMI         3
+#define K_BCM1480_INT_HT_INTMSG_INIT        4
+#define K_BCM1480_INT_HT_INTMSG_STARTUP     5
+#define K_BCM1480_INT_HT_INTMSG_EXTINT      6
+#define K_BCM1480_INT_HT_INTMSG_RESERVED    7
+
+#define M_BCM1480_INT_HT_TRIGGERMODE        _SB_MAKEMASK1(3)
+#define V_BCM1480_INT_HT_EDGETRIGGER        0
+#define V_BCM1480_INT_HT_LEVELTRIGGER       M_BCM1480_INT_HT_TRIGGERMODE
+
+#define M_BCM1480_INT_HT_DESTMODE           _SB_MAKEMASK1(4)
+#define V_BCM1480_INT_HT_PHYSICALDEST       0
+#define V_BCM1480_INT_HT_LOGICALDEST        M_BCM1480_INT_HT_DESTMODE
+
+#define S_BCM1480_INT_HT_INTDEST            5
+#define M_BCM1480_INT_HT_INTDEST            _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
+#define V_BCM1480_INT_HT_INTDEST(x)         _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
+#define G_BCM1480_INT_HT_INTDEST(x)         _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
+
+#define S_BCM1480_INT_HT_VECTOR             13
+#define M_BCM1480_INT_HT_VECTOR             _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
+#define V_BCM1480_INT_HT_VECTOR(x)          _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
+#define G_BCM1480_INT_HT_VECTOR(x)          _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
+
+/*
+ * Vector prefix (Table 4-7)
+ */
+
+#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH  0x00
+#define M_BCM1480_HTVECT_RAISE_MBOX_0       0x40
+#define M_BCM1480_HTVECT_RAISE_INTLDT_LO    0x80
+#define M_BCM1480_HTVECT_RAISE_MBOX_1       0xC0
+
+#endif /* _BCM1480_INT_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_l2c.h b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
new file mode 100644
index 000000000000..fd75817f7ac4
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
@@ -0,0 +1,176 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  L2 Cache constants and macros            File: bcm1480_l2c.h
+    *
+    *  This module contains constants useful for manipulating the
+    *  level 2 cache.
+    *
+    *  BCM1400 specification level:  1280-UM100-D2 (11/14/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _BCM1480_L2C_H
+#define _BCM1480_L2C_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Format of level 2 cache management address (Table 55)
+ */
+
+#define S_BCM1480_L2C_MGMT_INDEX            5
+#define M_BCM1480_L2C_MGMT_INDEX            _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX)
+#define V_BCM1480_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX)
+#define G_BCM1480_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX)
+
+#define S_BCM1480_L2C_MGMT_WAY              17
+#define M_BCM1480_L2C_MGMT_WAY              _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY)
+#define V_BCM1480_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY)
+#define G_BCM1480_L2C_MGMT_WAY(x)           _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY)
+
+#define M_BCM1480_L2C_MGMT_DIRTY            _SB_MAKEMASK1(20)
+#define M_BCM1480_L2C_MGMT_VALID            _SB_MAKEMASK1(21)
+
+#define S_BCM1480_L2C_MGMT_ECC_DIAG         22
+#define M_BCM1480_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define V_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define G_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG)
+
+#define A_BCM1480_L2C_MGMT_TAG_BASE         0x00D0000000
+
+#define BCM1480_L2C_ENTRIES_PER_WAY         4096
+#define BCM1480_L2C_NUM_WAYS                8
+
+
+/*
+ * Level 2 Cache Tag register (Table 59)
+ */
+
+#define S_BCM1480_L2C_TAG_MBZ               0
+#define M_BCM1480_L2C_TAG_MBZ               _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ)
+
+#define S_BCM1480_L2C_TAG_INDEX             5
+#define M_BCM1480_L2C_TAG_INDEX             _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX)
+#define V_BCM1480_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX)
+#define G_BCM1480_L2C_TAG_INDEX(x)          _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX)
+
+/* Note that index bit 16 is also tag bit 40 */
+#define S_BCM1480_L2C_TAG_TAG               17
+#define M_BCM1480_L2C_TAG_TAG               _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG)
+#define V_BCM1480_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG)
+#define G_BCM1480_L2C_TAG_TAG(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG)
+
+#define S_BCM1480_L2C_TAG_ECC               40
+#define M_BCM1480_L2C_TAG_ECC               _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC)
+#define V_BCM1480_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC)
+#define G_BCM1480_L2C_TAG_ECC(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC)
+
+#define S_BCM1480_L2C_TAG_WAY               46
+#define M_BCM1480_L2C_TAG_WAY               _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY)
+#define V_BCM1480_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY)
+#define G_BCM1480_L2C_TAG_WAY(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY)
+
+#define M_BCM1480_L2C_TAG_DIRTY             _SB_MAKEMASK1(49)
+#define M_BCM1480_L2C_TAG_VALID             _SB_MAKEMASK1(50)
+
+#define S_BCM1480_L2C_DATA_ECC              51
+#define M_BCM1480_L2C_DATA_ECC              _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC)
+#define V_BCM1480_L2C_DATA_ECC(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC)
+#define G_BCM1480_L2C_DATA_ECC(x)           _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC)
+
+
+/*
+ * L2 Misc0 Value Register (Table 60)
+ */
+
+#define S_BCM1480_L2C_MISC0_WAY_REMOTE      0
+#define M_BCM1480_L2C_MISC0_WAY_REMOTE      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE)
+#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE)
+
+#define S_BCM1480_L2C_MISC0_WAY_LOCAL       8
+#define M_BCM1480_L2C_MISC0_WAY_LOCAL       _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL)
+#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x)    _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL)
+
+#define S_BCM1480_L2C_MISC0_WAY_ENABLE      16
+#define M_BCM1480_L2C_MISC0_WAY_ENABLE      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE)
+#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE)
+
+#define S_BCM1480_L2C_MISC0_CACHE_DISABLE   24
+#define M_BCM1480_L2C_MISC0_CACHE_DISABLE   _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE)
+#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE)
+
+#define S_BCM1480_L2C_MISC0_CACHE_QUAD      26
+#define M_BCM1480_L2C_MISC0_CACHE_QUAD      _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD)
+#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD)
+
+#define S_BCM1480_L2C_MISC0_MC_PRIORITY      30
+#define M_BCM1480_L2C_MISC0_MC_PRIORITY      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
+
+#define S_BCM1480_L2C_MISC0_ECC_CLEANUP      31
+#define M_BCM1480_L2C_MISC0_ECC_CLEANUP      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
+
+
+/*
+ * L2 Misc1 Value Register (Table 60)
+ */
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_0      0
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_0      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_1      8
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_1      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_2      16
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_2      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_3      24
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_3      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3)
+
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_4      32
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_4      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4)
+#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4)
+
+
+/*
+ * L2 Misc2 Value Register (Table 60)
+ */
+
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_8      0
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_8      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8)
+
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_9      8
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_9      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9)
+
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_A      16
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_A      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A)
+#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A)
+
+
+#endif /* _BCM1480_L2C_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_mc.h b/arch/mips/include/asm/sibyte/bcm1480_mc.h
new file mode 100644
index 000000000000..f26a41a82b59
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_mc.h
@@ -0,0 +1,984 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1480 Board Support Package
+    *
+    *  Memory Controller constants              File: bcm1480_mc.h
+    *
+    *  This module contains constants and macros useful for
+    *  programming the memory controller.
+    *
+    *  BCM1400 specification level:  1280-UM100-D1 (11/14/03 Review Copy)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _BCM1480_MC_H
+#define _BCM1480_MC_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Memory Channel Configuration Register (Table 81)
+ */
+
+#define S_BCM1480_MC_INTLV0                 0
+#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0_DEFAULT         V_BCM1480_MC_INTLV0(0)
+
+#define S_BCM1480_MC_INTLV1                 8
+#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1_DEFAULT         V_BCM1480_MC_INTLV1(0)
+
+#define S_BCM1480_MC_INTLV2                 16
+#define M_BCM1480_MC_INTLV2                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2)
+#define G_BCM1480_MC_INTLV2(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2_DEFAULT         V_BCM1480_MC_INTLV2(0)
+
+#define S_BCM1480_MC_CS_MODE                32
+#define M_BCM1480_MC_CS_MODE                _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE)
+#define G_BCM1480_MC_CS_MODE(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE_DEFAULT        V_BCM1480_MC_CS_MODE(0)
+
+#define V_BCM1480_MC_CONFIG_DEFAULT         (V_BCM1480_MC_INTLV0_DEFAULT  | \
+                                     V_BCM1480_MC_INTLV1_DEFAULT  | \
+                                     V_BCM1480_MC_INTLV2_DEFAULT  | \
+                                     V_BCM1480_MC_CS_MODE_DEFAULT)
+
+#define K_BCM1480_MC_CS01_MODE              0x03
+#define K_BCM1480_MC_CS02_MODE              0x05
+#define K_BCM1480_MC_CS0123_MODE            0x0F
+#define K_BCM1480_MC_CS0246_MODE            0x55
+#define K_BCM1480_MC_CS0145_MODE            0x33
+#define K_BCM1480_MC_CS0167_MODE            0xC3
+#define K_BCM1480_MC_CSFULL_MODE            0xFF
+
+/*
+ * Chip Select Start Address Register (Table 82)
+ */
+
+#define S_BCM1480_MC_CS0_START              0
+#define M_BCM1480_MC_CS0_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START)
+#define V_BCM1480_MC_CS0_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START)
+#define G_BCM1480_MC_CS0_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START)
+
+#define S_BCM1480_MC_CS1_START              16
+#define M_BCM1480_MC_CS1_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START)
+#define V_BCM1480_MC_CS1_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START)
+#define G_BCM1480_MC_CS1_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START)
+
+#define S_BCM1480_MC_CS2_START              32
+#define M_BCM1480_MC_CS2_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START)
+#define V_BCM1480_MC_CS2_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START)
+#define G_BCM1480_MC_CS2_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START)
+
+#define S_BCM1480_MC_CS3_START              48
+#define M_BCM1480_MC_CS3_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START)
+#define V_BCM1480_MC_CS3_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START)
+#define G_BCM1480_MC_CS3_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START)
+
+/*
+ * Chip Select End Address Register (Table 83)
+ */
+
+#define S_BCM1480_MC_CS0_END                0
+#define M_BCM1480_MC_CS0_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END)
+#define V_BCM1480_MC_CS0_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END)
+#define G_BCM1480_MC_CS0_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END)
+
+#define S_BCM1480_MC_CS1_END                16
+#define M_BCM1480_MC_CS1_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END)
+#define V_BCM1480_MC_CS1_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END)
+#define G_BCM1480_MC_CS1_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END)
+
+#define S_BCM1480_MC_CS2_END                32
+#define M_BCM1480_MC_CS2_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END)
+#define V_BCM1480_MC_CS2_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END)
+#define G_BCM1480_MC_CS2_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END)
+
+#define S_BCM1480_MC_CS3_END                48
+#define M_BCM1480_MC_CS3_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END)
+#define V_BCM1480_MC_CS3_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END)
+#define G_BCM1480_MC_CS3_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END)
+
+/*
+ * Row Address Bit Select Register 0 (Table 84)
+ */
+
+#define S_BCM1480_MC_ROW00                  0
+#define M_BCM1480_MC_ROW00                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW00)
+#define V_BCM1480_MC_ROW00(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00)
+#define G_BCM1480_MC_ROW00(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00)
+
+#define S_BCM1480_MC_ROW01                  8
+#define M_BCM1480_MC_ROW01                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW01)
+#define V_BCM1480_MC_ROW01(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01)
+#define G_BCM1480_MC_ROW01(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01)
+
+#define S_BCM1480_MC_ROW02                  16
+#define M_BCM1480_MC_ROW02                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW02)
+#define V_BCM1480_MC_ROW02(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02)
+#define G_BCM1480_MC_ROW02(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02)
+
+#define S_BCM1480_MC_ROW03                  24
+#define M_BCM1480_MC_ROW03                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW03)
+#define V_BCM1480_MC_ROW03(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03)
+#define G_BCM1480_MC_ROW03(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03)
+
+#define S_BCM1480_MC_ROW04                  32
+#define M_BCM1480_MC_ROW04                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW04)
+#define V_BCM1480_MC_ROW04(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04)
+#define G_BCM1480_MC_ROW04(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04)
+
+#define S_BCM1480_MC_ROW05                  40
+#define M_BCM1480_MC_ROW05                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW05)
+#define V_BCM1480_MC_ROW05(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05)
+#define G_BCM1480_MC_ROW05(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05)
+
+#define S_BCM1480_MC_ROW06                  48
+#define M_BCM1480_MC_ROW06                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW06)
+#define V_BCM1480_MC_ROW06(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06)
+#define G_BCM1480_MC_ROW06(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06)
+
+#define S_BCM1480_MC_ROW07                  56
+#define M_BCM1480_MC_ROW07                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW07)
+#define V_BCM1480_MC_ROW07(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07)
+#define G_BCM1480_MC_ROW07(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07)
+
+/*
+ * Row Address Bit Select Register 1 (Table 85)
+ */
+
+#define S_BCM1480_MC_ROW08                  0
+#define M_BCM1480_MC_ROW08                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW08)
+#define V_BCM1480_MC_ROW08(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08)
+#define G_BCM1480_MC_ROW08(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08)
+
+#define S_BCM1480_MC_ROW09                  8
+#define M_BCM1480_MC_ROW09                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW09)
+#define V_BCM1480_MC_ROW09(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09)
+#define G_BCM1480_MC_ROW09(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09)
+
+#define S_BCM1480_MC_ROW10                  16
+#define M_BCM1480_MC_ROW10                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW10)
+#define V_BCM1480_MC_ROW10(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10)
+#define G_BCM1480_MC_ROW10(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10)
+
+#define S_BCM1480_MC_ROW11                  24
+#define M_BCM1480_MC_ROW11                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW11)
+#define V_BCM1480_MC_ROW11(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11)
+#define G_BCM1480_MC_ROW11(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11)
+
+#define S_BCM1480_MC_ROW12                  32
+#define M_BCM1480_MC_ROW12                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW12)
+#define V_BCM1480_MC_ROW12(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12)
+#define G_BCM1480_MC_ROW12(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12)
+
+#define S_BCM1480_MC_ROW13                  40
+#define M_BCM1480_MC_ROW13                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW13)
+#define V_BCM1480_MC_ROW13(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13)
+#define G_BCM1480_MC_ROW13(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13)
+
+#define S_BCM1480_MC_ROW14                  48
+#define M_BCM1480_MC_ROW14                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW14)
+#define V_BCM1480_MC_ROW14(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14)
+#define G_BCM1480_MC_ROW14(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14)
+
+#define K_BCM1480_MC_ROWX_BIT_SPACING       8
+
+/*
+ * Column Address Bit Select Register 0 (Table 86)
+ */
+
+#define S_BCM1480_MC_COL00                  0
+#define M_BCM1480_MC_COL00                  _SB_MAKEMASK(6, S_BCM1480_MC_COL00)
+#define V_BCM1480_MC_COL00(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL00)
+#define G_BCM1480_MC_COL00(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00)
+
+#define S_BCM1480_MC_COL01                  8
+#define M_BCM1480_MC_COL01                  _SB_MAKEMASK(6, S_BCM1480_MC_COL01)
+#define V_BCM1480_MC_COL01(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL01)
+#define G_BCM1480_MC_COL01(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01)
+
+#define S_BCM1480_MC_COL02                  16
+#define M_BCM1480_MC_COL02                  _SB_MAKEMASK(6, S_BCM1480_MC_COL02)
+#define V_BCM1480_MC_COL02(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL02)
+#define G_BCM1480_MC_COL02(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02)
+
+#define S_BCM1480_MC_COL03                  24
+#define M_BCM1480_MC_COL03                  _SB_MAKEMASK(6, S_BCM1480_MC_COL03)
+#define V_BCM1480_MC_COL03(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL03)
+#define G_BCM1480_MC_COL03(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03)
+
+#define S_BCM1480_MC_COL04                  32
+#define M_BCM1480_MC_COL04                  _SB_MAKEMASK(6, S_BCM1480_MC_COL04)
+#define V_BCM1480_MC_COL04(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL04)
+#define G_BCM1480_MC_COL04(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04)
+
+#define S_BCM1480_MC_COL05                  40
+#define M_BCM1480_MC_COL05                  _SB_MAKEMASK(6, S_BCM1480_MC_COL05)
+#define V_BCM1480_MC_COL05(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL05)
+#define G_BCM1480_MC_COL05(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05)
+
+#define S_BCM1480_MC_COL06                  48
+#define M_BCM1480_MC_COL06                  _SB_MAKEMASK(6, S_BCM1480_MC_COL06)
+#define V_BCM1480_MC_COL06(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL06)
+#define G_BCM1480_MC_COL06(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06)
+
+#define S_BCM1480_MC_COL07                  56
+#define M_BCM1480_MC_COL07                  _SB_MAKEMASK(6, S_BCM1480_MC_COL07)
+#define V_BCM1480_MC_COL07(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL07)
+#define G_BCM1480_MC_COL07(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07)
+
+/*
+ * Column Address Bit Select Register 1 (Table 87)
+ */
+
+#define S_BCM1480_MC_COL08                  0
+#define M_BCM1480_MC_COL08                  _SB_MAKEMASK(6, S_BCM1480_MC_COL08)
+#define V_BCM1480_MC_COL08(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL08)
+#define G_BCM1480_MC_COL08(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08)
+
+#define S_BCM1480_MC_COL09                  8
+#define M_BCM1480_MC_COL09                  _SB_MAKEMASK(6, S_BCM1480_MC_COL09)
+#define V_BCM1480_MC_COL09(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL09)
+#define G_BCM1480_MC_COL09(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09)
+
+#define S_BCM1480_MC_COL10                  16   /* not a valid position, must be prog as 0 */
+
+#define S_BCM1480_MC_COL11                  24
+#define M_BCM1480_MC_COL11                  _SB_MAKEMASK(6, S_BCM1480_MC_COL11)
+#define V_BCM1480_MC_COL11(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL11)
+#define G_BCM1480_MC_COL11(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11)
+
+#define S_BCM1480_MC_COL12                  32
+#define M_BCM1480_MC_COL12                  _SB_MAKEMASK(6, S_BCM1480_MC_COL12)
+#define V_BCM1480_MC_COL12(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL12)
+#define G_BCM1480_MC_COL12(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12)
+
+#define S_BCM1480_MC_COL13                  40
+#define M_BCM1480_MC_COL13                  _SB_MAKEMASK(6, S_BCM1480_MC_COL13)
+#define V_BCM1480_MC_COL13(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL13)
+#define G_BCM1480_MC_COL13(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13)
+
+#define S_BCM1480_MC_COL14                  48
+#define M_BCM1480_MC_COL14                  _SB_MAKEMASK(6, S_BCM1480_MC_COL14)
+#define V_BCM1480_MC_COL14(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL14)
+#define G_BCM1480_MC_COL14(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14)
+
+#define K_BCM1480_MC_COLX_BIT_SPACING       8
+
+/*
+ * CS0 and CS1 Bank Address Bit Select Register (Table 88)
+ */
+
+#define S_BCM1480_MC_CS01_BANK0             0
+#define M_BCM1480_MC_CS01_BANK0             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0)
+#define V_BCM1480_MC_CS01_BANK0(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0)
+#define G_BCM1480_MC_CS01_BANK0(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0)
+
+#define S_BCM1480_MC_CS01_BANK1             8
+#define M_BCM1480_MC_CS01_BANK1             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1)
+#define V_BCM1480_MC_CS01_BANK1(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1)
+#define G_BCM1480_MC_CS01_BANK1(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1)
+
+#define S_BCM1480_MC_CS01_BANK2             16
+#define M_BCM1480_MC_CS01_BANK2             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2)
+#define V_BCM1480_MC_CS01_BANK2(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2)
+#define G_BCM1480_MC_CS01_BANK2(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2)
+
+/*
+ * CS2 and CS3 Bank Address Bit Select Register (Table 89)
+ */
+
+#define S_BCM1480_MC_CS23_BANK0             0
+#define M_BCM1480_MC_CS23_BANK0             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0)
+#define V_BCM1480_MC_CS23_BANK0(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0)
+#define G_BCM1480_MC_CS23_BANK0(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0)
+
+#define S_BCM1480_MC_CS23_BANK1             8
+#define M_BCM1480_MC_CS23_BANK1             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1)
+#define V_BCM1480_MC_CS23_BANK1(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1)
+#define G_BCM1480_MC_CS23_BANK1(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1)
+
+#define S_BCM1480_MC_CS23_BANK2             16
+#define M_BCM1480_MC_CS23_BANK2             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2)
+#define V_BCM1480_MC_CS23_BANK2(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2)
+#define G_BCM1480_MC_CS23_BANK2(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2)
+
+#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING  8
+
+/*
+ * DRAM Command Register (Table 90)
+ */
+
+#define S_BCM1480_MC_COMMAND                0
+#define M_BCM1480_MC_COMMAND                _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND)
+#define V_BCM1480_MC_COMMAND(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND)
+#define G_BCM1480_MC_COMMAND(x)             _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND)
+
+#define K_BCM1480_MC_COMMAND_EMRS           0
+#define K_BCM1480_MC_COMMAND_MRS            1
+#define K_BCM1480_MC_COMMAND_PRE            2
+#define K_BCM1480_MC_COMMAND_AR             3
+#define K_BCM1480_MC_COMMAND_SETRFSH        4
+#define K_BCM1480_MC_COMMAND_CLRRFSH        5
+#define K_BCM1480_MC_COMMAND_SETPWRDN       6
+#define K_BCM1480_MC_COMMAND_CLRPWRDN       7
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define K_BCM1480_MC_COMMAND_EMRS2          8
+#define K_BCM1480_MC_COMMAND_EMRS3          9
+#define K_BCM1480_MC_COMMAND_ENABLE_MCLK    10
+#define K_BCM1480_MC_COMMAND_DISABLE_MCLK   11
+#endif
+
+#define V_BCM1480_MC_COMMAND_EMRS           V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)
+#define V_BCM1480_MC_COMMAND_MRS            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)
+#define V_BCM1480_MC_COMMAND_PRE            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)
+#define V_BCM1480_MC_COMMAND_AR             V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)
+#define V_BCM1480_MC_COMMAND_SETRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)
+#define V_BCM1480_MC_COMMAND_CLRRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)
+#define V_BCM1480_MC_COMMAND_SETPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)
+#define V_BCM1480_MC_COMMAND_CLRPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define V_BCM1480_MC_COMMAND_EMRS2          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)
+#define V_BCM1480_MC_COMMAND_EMRS3          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)
+#define V_BCM1480_MC_COMMAND_ENABLE_MCLK    V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)
+#define V_BCM1480_MC_COMMAND_DISABLE_MCLK   V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)
+#endif
+
+#define S_BCM1480_MC_CS0                    4
+#define M_BCM1480_MC_CS0                    _SB_MAKEMASK1(4)
+#define M_BCM1480_MC_CS1                    _SB_MAKEMASK1(5)
+#define M_BCM1480_MC_CS2                    _SB_MAKEMASK1(6)
+#define M_BCM1480_MC_CS3                    _SB_MAKEMASK1(7)
+#define M_BCM1480_MC_CS4                    _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_CS5                    _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_CS6                    _SB_MAKEMASK1(10)
+#define M_BCM1480_MC_CS7                    _SB_MAKEMASK1(11)
+
+#define M_BCM1480_MC_CS                  _SB_MAKEMASK(8, S_BCM1480_MC_CS0)
+#define V_BCM1480_MC_CS(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_CS0)
+#define G_BCM1480_MC_CS(x)               _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0)
+
+#define M_BCM1480_MC_CMD_ACTIVE             _SB_MAKEMASK1(16)
+
+/*
+ * DRAM Mode Register (Table 91)
+ */
+
+#define S_BCM1480_MC_EMODE                  0
+#define M_BCM1480_MC_EMODE                  _SB_MAKEMASK(15, S_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE)
+#define G_BCM1480_MC_EMODE(x)               _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE_DEFAULT          V_BCM1480_MC_EMODE(0)
+
+#define S_BCM1480_MC_MODE                   16
+#define M_BCM1480_MC_MODE                   _SB_MAKEMASK(15, S_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_MODE)
+#define G_BCM1480_MC_MODE(x)                _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE_DEFAULT           V_BCM1480_MC_MODE(0)
+
+#define S_BCM1480_MC_DRAM_TYPE              32
+#define M_BCM1480_MC_DRAM_TYPE              _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE)
+#define V_BCM1480_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE)
+#define G_BCM1480_MC_DRAM_TYPE(x)           _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE)
+
+#define K_BCM1480_MC_DRAM_TYPE_JEDEC        0
+#define K_BCM1480_MC_DRAM_TYPE_FCRAM        1
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define K_BCM1480_MC_DRAM_TYPE_DDR2         2
+#endif
+
+#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1   0
+
+#define V_BCM1480_MC_DRAM_TYPE_JEDEC        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
+#define V_BCM1480_MC_DRAM_TYPE_FCRAM        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define V_BCM1480_MC_DRAM_TYPE_DDR2         V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)
+#endif
+
+#define M_BCM1480_MC_GANGED                 _SB_MAKEMASK1(36)
+#define M_BCM1480_MC_BY9_INTF               _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_FORCE_ECC64            _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_ECC_DISABLE            _SB_MAKEMASK1(39)
+
+#define S_BCM1480_MC_PG_POLICY              40
+#define M_BCM1480_MC_PG_POLICY              _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY)
+#define V_BCM1480_MC_PG_POLICY(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY)
+#define G_BCM1480_MC_PG_POLICY(x)           _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY)
+
+#define K_BCM1480_MC_PG_POLICY_CLOSED       0
+#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
+
+#define V_BCM1480_MC_PG_POLICY_CLOSED       V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)
+#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_2T_CMD                 _SB_MAKEMASK1(42)
+#define M_BCM1480_MC_ECC_COR_DIS            _SB_MAKEMASK1(43)
+#endif
+
+#define V_BCM1480_MC_DRAMMODE_DEFAULT   V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \
+                                V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
+
+/*
+ * Memory Clock Configuration Register (Table 92)
+ */
+
+#define S_BCM1480_MC_CLK_RATIO              0
+#define M_BCM1480_MC_CLK_RATIO              _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO)
+#define V_BCM1480_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO)
+#define G_BCM1480_MC_CLK_RATIO(x)           _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO)
+
+#define V_BCM1480_MC_CLK_RATIO_DEFAULT      V_BCM1480_MC_CLK_RATIO(10)
+
+#define S_BCM1480_MC_REF_RATE               8
+#define M_BCM1480_MC_REF_RATE               _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE)
+#define V_BCM1480_MC_REF_RATE(x)            _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE)
+#define G_BCM1480_MC_REF_RATE(x)            _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE)
+
+#define K_BCM1480_MC_REF_RATE_100MHz        0x31
+#define K_BCM1480_MC_REF_RATE_200MHz        0x62
+#define K_BCM1480_MC_REF_RATE_400MHz        0xC4
+
+#define V_BCM1480_MC_REF_RATE_100MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)
+#define V_BCM1480_MC_REF_RATE_200MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)
+#define V_BCM1480_MC_REF_RATE_400MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)
+#define V_BCM1480_MC_REF_RATE_DEFAULT       V_BCM1480_MC_REF_RATE_400MHz
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_AUTO_REF_DIS           _SB_MAKEMASK1(16)
+#endif
+
+/*
+ * ODT Register (Table 99)
+ */
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_RD_ODT0_CS0            _SB_MAKEMASK1(0)
+#define M_BCM1480_MC_RD_ODT0_CS2            _SB_MAKEMASK1(1)
+#define M_BCM1480_MC_RD_ODT0_CS4            _SB_MAKEMASK1(2)
+#define M_BCM1480_MC_RD_ODT0_CS6            _SB_MAKEMASK1(3)
+#define M_BCM1480_MC_WR_ODT0_CS0            _SB_MAKEMASK1(4)
+#define M_BCM1480_MC_WR_ODT0_CS2            _SB_MAKEMASK1(5)
+#define M_BCM1480_MC_WR_ODT0_CS4            _SB_MAKEMASK1(6)
+#define M_BCM1480_MC_WR_ODT0_CS6            _SB_MAKEMASK1(7)
+#define M_BCM1480_MC_RD_ODT2_CS0            _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_RD_ODT2_CS2            _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_RD_ODT2_CS4            _SB_MAKEMASK1(10)
+#define M_BCM1480_MC_RD_ODT2_CS6            _SB_MAKEMASK1(11)
+#define M_BCM1480_MC_WR_ODT2_CS0            _SB_MAKEMASK1(12)
+#define M_BCM1480_MC_WR_ODT2_CS2            _SB_MAKEMASK1(13)
+#define M_BCM1480_MC_WR_ODT2_CS4            _SB_MAKEMASK1(14)
+#define M_BCM1480_MC_WR_ODT2_CS6            _SB_MAKEMASK1(15)
+#define M_BCM1480_MC_RD_ODT4_CS0            _SB_MAKEMASK1(16)
+#define M_BCM1480_MC_RD_ODT4_CS2            _SB_MAKEMASK1(17)
+#define M_BCM1480_MC_RD_ODT4_CS4            _SB_MAKEMASK1(18)
+#define M_BCM1480_MC_RD_ODT4_CS6            _SB_MAKEMASK1(19)
+#define M_BCM1480_MC_WR_ODT4_CS0            _SB_MAKEMASK1(20)
+#define M_BCM1480_MC_WR_ODT4_CS2            _SB_MAKEMASK1(21)
+#define M_BCM1480_MC_WR_ODT4_CS4            _SB_MAKEMASK1(22)
+#define M_BCM1480_MC_WR_ODT4_CS6            _SB_MAKEMASK1(23)
+#define M_BCM1480_MC_RD_ODT6_CS0            _SB_MAKEMASK1(24)
+#define M_BCM1480_MC_RD_ODT6_CS2            _SB_MAKEMASK1(25)
+#define M_BCM1480_MC_RD_ODT6_CS4            _SB_MAKEMASK1(26)
+#define M_BCM1480_MC_RD_ODT6_CS6            _SB_MAKEMASK1(27)
+#define M_BCM1480_MC_WR_ODT6_CS0            _SB_MAKEMASK1(28)
+#define M_BCM1480_MC_WR_ODT6_CS2            _SB_MAKEMASK1(29)
+#define M_BCM1480_MC_WR_ODT6_CS4            _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_WR_ODT6_CS6            _SB_MAKEMASK1(31)
+
+#define M_BCM1480_MC_CS_ODD_ODT_EN          _SB_MAKEMASK1(32)
+
+#define S_BCM1480_MC_ODT0                   0
+#define M_BCM1480_MC_ODT0                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT0)
+#define V_BCM1480_MC_ODT0(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0)
+
+#define S_BCM1480_MC_ODT2                   8
+#define M_BCM1480_MC_ODT2                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT2)
+#define V_BCM1480_MC_ODT2(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2)
+
+#define S_BCM1480_MC_ODT4                   16
+#define M_BCM1480_MC_ODT4                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT4)
+#define V_BCM1480_MC_ODT4(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4)
+
+#define S_BCM1480_MC_ODT6                   24
+#define M_BCM1480_MC_ODT6                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT6)
+#define V_BCM1480_MC_ODT6(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6)
+#endif
+
+/*
+ * Memory DLL Configuration Register (Table 93)
+ */
+
+#define S_BCM1480_MC_ADDR_COARSE_ADJ         0
+#define M_BCM1480_MC_ADDR_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define V_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define G_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ)
+#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_ADDR_FREQ_RANGE            8
+#define M_BCM1480_MC_ADDR_FREQ_RANGE            _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define G_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT    V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_ADDR_FINE_ADJ          8
+#define M_BCM1480_MC_ADDR_FINE_ADJ          _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ)
+#define V_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ)
+#define G_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ)
+#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT  V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
+
+#define S_BCM1480_MC_DQI_COARSE_ADJ         16
+#define M_BCM1480_MC_DQI_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ)
+#define V_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ)
+#define G_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ)
+#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DQI_FREQ_RANGE             24
+#define M_BCM1480_MC_DQI_FREQ_RANGE             _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE)
+#define G_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_DQI_FINE_ADJ           24
+#define M_BCM1480_MC_DQI_FINE_ADJ           _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ)
+#define V_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ)
+#define G_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ)
+#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQI_FINE_ADJ(0x8)
+
+#define S_BCM1480_MC_DQO_COARSE_ADJ         32
+#define M_BCM1480_MC_DQO_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ)
+#define V_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ)
+#define G_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ)
+#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DQO_FREQ_RANGE             40
+#define M_BCM1480_MC_DQO_FREQ_RANGE             _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE)
+#define G_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_DQO_FINE_ADJ           40
+#define M_BCM1480_MC_DQO_FINE_ADJ           _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ)
+#define V_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ)
+#define G_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ)
+#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQO_FINE_ADJ(0x8)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_PDSEL            44
+#define M_BCM1480_MC_DLL_PDSEL            _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_PDSEL(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL)
+#define G_BCM1480_MC_DLL_PDSEL(x)         _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_DEFAULT_PDSEL    V_BCM1480_MC_DLL_PDSEL(0x0)
+
+#define M_BCM1480_MC_DLL_REGBYPASS        _SB_MAKEMASK1(46)
+#define M_BCM1480_MC_DQO_SHIFT            _SB_MAKEMASK1(47)
+#endif
+
+#define S_BCM1480_MC_DLL_DEFAULT           48
+#define M_BCM1480_MC_DLL_DEFAULT           _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT)
+#define V_BCM1480_MC_DLL_DEFAULT(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT)
+#define G_BCM1480_MC_DLL_DEFAULT(x)        _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT)
+#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT   V_BCM1480_MC_DLL_DEFAULT(0x10)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_REGCTRL          54
+#define M_BCM1480_MC_DLL_REGCTRL          _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL)
+#define V_BCM1480_MC_DLL_REGCTRL(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL)
+#define G_BCM1480_MC_DLL_REGCTRL(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL)
+#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL  V_BCM1480_MC_DLL_REGCTRL(0x0)
+#endif
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_FREQ_RANGE             56
+#define M_BCM1480_MC_DLL_FREQ_RANGE             _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE)
+#define G_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
+#endif
+
+#define S_BCM1480_MC_DLL_STEP_SIZE          56
+#define M_BCM1480_MC_DLL_STEP_SIZE          _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE)
+#define V_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE)
+#define G_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE)
+#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT  V_BCM1480_MC_DLL_STEP_SIZE(0x8)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_DLL_BGCTRL   60
+#define M_BCM1480_MC_DLL_BGCTRL           _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_BGCTRL(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL)
+#define G_BCM1480_MC_DLL_BGCTRL(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL  V_BCM1480_MC_DLL_BGCTRL(0x0)
+#endif
+
+#define M_BCM1480_MC_DLL_BYPASS             _SB_MAKEMASK1(63)
+
+/*
+ * Memory Drive Configuration Register (Table 94)
+ */
+
+#define S_BCM1480_MC_RTT_BYP_PULLDOWN       0
+#define M_BCM1480_MC_RTT_BYP_PULLDOWN       _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN)
+
+#define S_BCM1480_MC_RTT_BYP_PULLUP         6
+#define M_BCM1480_MC_RTT_BYP_PULLUP         _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP)
+#define V_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP)
+#define G_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP)
+
+#define M_BCM1480_MC_RTT_BYPASS             _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_RTT_COMP_MOV_AVG       _SB_MAKEMASK1(9)
+
+#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN    10
+#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN    _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
+
+#define S_BCM1480_MC_PVT_BYP_C1_PULLUP      15
+#define M_BCM1480_MC_PVT_BYP_C1_PULLUP      _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP)
+
+#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN    20
+#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN    _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
+
+#define S_BCM1480_MC_PVT_BYP_C2_PULLUP      25
+#define M_BCM1480_MC_PVT_BYP_C2_PULLUP      _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP)
+
+#define M_BCM1480_MC_PVT_BYPASS             _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_PVT_COMP_MOV_AVG       _SB_MAKEMASK1(31)
+
+#define M_BCM1480_MC_CLK_CLASS              _SB_MAKEMASK1(34)
+#define M_BCM1480_MC_DATA_CLASS             _SB_MAKEMASK1(35)
+#define M_BCM1480_MC_ADDR_CLASS             _SB_MAKEMASK1(36)
+
+#define M_BCM1480_MC_DQ_ODT_75              _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_DQ_ODT_150             _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_DQS_ODT_75             _SB_MAKEMASK1(39)
+#define M_BCM1480_MC_DQS_ODT_150            _SB_MAKEMASK1(40)
+#define M_BCM1480_MC_DQS_DIFF               _SB_MAKEMASK1(41)
+
+/*
+ * ECC Test Data Register (Table 95)
+ */
+
+#define S_BCM1480_MC_DATA_INVERT            0
+#define M_DATA_ECC_INVERT           _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT)
+
+/*
+ * ECC Test ECC Register (Table 96)
+ */
+
+#define S_BCM1480_MC_ECC_INVERT             0
+#define M_BCM1480_MC_ECC_INVERT             _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT)
+
+/*
+ * SDRAM Timing Register  (Table 97)
+ */
+
+#define S_BCM1480_MC_tRCD                   0
+#define M_BCM1480_MC_tRCD                   _SB_MAKEMASK(4, S_BCM1480_MC_tRCD)
+#define V_BCM1480_MC_tRCD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD)
+#define G_BCM1480_MC_tRCD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD)
+#define K_BCM1480_MC_tRCD_DEFAULT           3
+#define V_BCM1480_MC_tRCD_DEFAULT           V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
+
+#define S_BCM1480_MC_tCL                    4
+#define M_BCM1480_MC_tCL                    _SB_MAKEMASK(4, S_BCM1480_MC_tCL)
+#define V_BCM1480_MC_tCL(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tCL)
+#define G_BCM1480_MC_tCL(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL)
+#define K_BCM1480_MC_tCL_DEFAULT            2
+#define V_BCM1480_MC_tCL_DEFAULT            V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
+
+#define M_BCM1480_MC_tCrDh                  _SB_MAKEMASK1(8)
+
+#define S_BCM1480_MC_tWR                    9
+#define M_BCM1480_MC_tWR                    _SB_MAKEMASK(3, S_BCM1480_MC_tWR)
+#define V_BCM1480_MC_tWR(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tWR)
+#define G_BCM1480_MC_tWR(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR)
+#define K_BCM1480_MC_tWR_DEFAULT            2
+#define V_BCM1480_MC_tWR_DEFAULT            V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
+
+#define S_BCM1480_MC_tCwD                   12
+#define M_BCM1480_MC_tCwD                   _SB_MAKEMASK(4, S_BCM1480_MC_tCwD)
+#define V_BCM1480_MC_tCwD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD)
+#define G_BCM1480_MC_tCwD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD)
+#define K_BCM1480_MC_tCwD_DEFAULT           1
+#define V_BCM1480_MC_tCwD_DEFAULT           V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
+
+#define S_BCM1480_MC_tRP                    16
+#define M_BCM1480_MC_tRP                    _SB_MAKEMASK(4, S_BCM1480_MC_tRP)
+#define V_BCM1480_MC_tRP(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tRP)
+#define G_BCM1480_MC_tRP(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP)
+#define K_BCM1480_MC_tRP_DEFAULT            4
+#define V_BCM1480_MC_tRP_DEFAULT            V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
+
+#define S_BCM1480_MC_tRRD                   20
+#define M_BCM1480_MC_tRRD                   _SB_MAKEMASK(4, S_BCM1480_MC_tRRD)
+#define V_BCM1480_MC_tRRD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD)
+#define G_BCM1480_MC_tRRD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD)
+#define K_BCM1480_MC_tRRD_DEFAULT           2
+#define V_BCM1480_MC_tRRD_DEFAULT           V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
+
+#define S_BCM1480_MC_tRCw                   24
+#define M_BCM1480_MC_tRCw                   _SB_MAKEMASK(5, S_BCM1480_MC_tRCw)
+#define V_BCM1480_MC_tRCw(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw)
+#define G_BCM1480_MC_tRCw(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw)
+#define K_BCM1480_MC_tRCw_DEFAULT           10
+#define V_BCM1480_MC_tRCw_DEFAULT           V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
+
+#define S_BCM1480_MC_tRCr                   32
+#define M_BCM1480_MC_tRCr                   _SB_MAKEMASK(5, S_BCM1480_MC_tRCr)
+#define V_BCM1480_MC_tRCr(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr)
+#define G_BCM1480_MC_tRCr(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr)
+#define K_BCM1480_MC_tRCr_DEFAULT           9
+#define V_BCM1480_MC_tRCr_DEFAULT           V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define S_BCM1480_MC_tFAW                   40
+#define M_BCM1480_MC_tFAW                   _SB_MAKEMASK(6, S_BCM1480_MC_tFAW)
+#define V_BCM1480_MC_tFAW(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW)
+#define G_BCM1480_MC_tFAW(x)                _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW)
+#define K_BCM1480_MC_tFAW_DEFAULT           0
+#define V_BCM1480_MC_tFAW_DEFAULT           V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
+#endif
+
+#define S_BCM1480_MC_tRFC                   48
+#define M_BCM1480_MC_tRFC                   _SB_MAKEMASK(7, S_BCM1480_MC_tRFC)
+#define V_BCM1480_MC_tRFC(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC)
+#define G_BCM1480_MC_tRFC(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC)
+#define K_BCM1480_MC_tRFC_DEFAULT           12
+#define V_BCM1480_MC_tRFC_DEFAULT           V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
+
+#define S_BCM1480_MC_tFIFO                  56
+#define M_BCM1480_MC_tFIFO                  _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO)
+#define V_BCM1480_MC_tFIFO(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO)
+#define G_BCM1480_MC_tFIFO(x)               _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO)
+#define K_BCM1480_MC_tFIFO_DEFAULT          0
+#define V_BCM1480_MC_tFIFO_DEFAULT          V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
+
+#define S_BCM1480_MC_tW2R                  58
+#define M_BCM1480_MC_tW2R                  _SB_MAKEMASK(2, S_BCM1480_MC_tW2R)
+#define V_BCM1480_MC_tW2R(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R)
+#define G_BCM1480_MC_tW2R(x)               _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R)
+#define K_BCM1480_MC_tW2R_DEFAULT          1
+#define V_BCM1480_MC_tW2R_DEFAULT          V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
+
+#define S_BCM1480_MC_tR2W                  60
+#define M_BCM1480_MC_tR2W                  _SB_MAKEMASK(2, S_BCM1480_MC_tR2W)
+#define V_BCM1480_MC_tR2W(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W)
+#define G_BCM1480_MC_tR2W(x)               _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W)
+#define K_BCM1480_MC_tR2W_DEFAULT          0
+#define V_BCM1480_MC_tR2W_DEFAULT          V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
+
+#define M_BCM1480_MC_tR2R                   _SB_MAKEMASK1(62)
+
+#define V_BCM1480_MC_TIMING_DEFAULT         (M_BCM1480_MC_tR2R | \
+                                     V_BCM1480_MC_tFIFO_DEFAULT | \
+                                     V_BCM1480_MC_tR2W_DEFAULT | \
+                                     V_BCM1480_MC_tW2R_DEFAULT | \
+                                     V_BCM1480_MC_tRFC_DEFAULT | \
+                                     V_BCM1480_MC_tRCr_DEFAULT | \
+                                     V_BCM1480_MC_tRCw_DEFAULT | \
+                                     V_BCM1480_MC_tRRD_DEFAULT | \
+                                     V_BCM1480_MC_tRP_DEFAULT | \
+                                     V_BCM1480_MC_tCwD_DEFAULT | \
+                                     V_BCM1480_MC_tWR_DEFAULT | \
+                                     M_BCM1480_MC_tCrDh | \
+                                     V_BCM1480_MC_tCL_DEFAULT | \
+                                     V_BCM1480_MC_tRCD_DEFAULT)
+
+/*
+ * SDRAM Timing Register 2
+ */
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+
+#define S_BCM1480_MC_tAL                   0
+#define M_BCM1480_MC_tAL                   _SB_MAKEMASK(4, S_BCM1480_MC_tAL)
+#define V_BCM1480_MC_tAL(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tAL)
+#define G_BCM1480_MC_tAL(x)                _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL)
+#define K_BCM1480_MC_tAL_DEFAULT           0
+#define V_BCM1480_MC_tAL_DEFAULT           V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
+
+#define S_BCM1480_MC_tRTP                   4
+#define M_BCM1480_MC_tRTP                   _SB_MAKEMASK(3, S_BCM1480_MC_tRTP)
+#define V_BCM1480_MC_tRTP(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP)
+#define G_BCM1480_MC_tRTP(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP)
+#define K_BCM1480_MC_tRTP_DEFAULT           2
+#define V_BCM1480_MC_tRTP_DEFAULT           V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
+
+#define S_BCM1480_MC_tW2W                   8
+#define M_BCM1480_MC_tW2W                   _SB_MAKEMASK(2, S_BCM1480_MC_tW2W)
+#define V_BCM1480_MC_tW2W(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W)
+#define G_BCM1480_MC_tW2W(x)                _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W)
+#define K_BCM1480_MC_tW2W_DEFAULT           0
+#define V_BCM1480_MC_tW2W_DEFAULT           V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
+
+#define S_BCM1480_MC_tRAP                   12
+#define M_BCM1480_MC_tRAP                  _SB_MAKEMASK(4, S_BCM1480_MC_tRAP)
+#define V_BCM1480_MC_tRAP(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP)
+#define G_BCM1480_MC_tRAP(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP)
+#define K_BCM1480_MC_tRAP_DEFAULT           0
+#define V_BCM1480_MC_tRAP_DEFAULT           V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
+
+#endif
+
+
+
+/*
+ * Global Registers: single instances per BCM1480
+ */
+
+/*
+ * Global Configuration Register (Table 99)
+ */
+
+#define S_BCM1480_MC_BLK_SET_MARK           8
+#define M_BCM1480_MC_BLK_SET_MARK           _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK)
+#define V_BCM1480_MC_BLK_SET_MARK(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK)
+#define G_BCM1480_MC_BLK_SET_MARK(x)        _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK)
+
+#define S_BCM1480_MC_BLK_CLR_MARK           12
+#define M_BCM1480_MC_BLK_CLR_MARK           _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK)
+#define V_BCM1480_MC_BLK_CLR_MARK(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK)
+#define G_BCM1480_MC_BLK_CLR_MARK(x)        _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK)
+
+#define M_BCM1480_MC_PKT_PRIORITY           _SB_MAKEMASK1(16)
+
+#define S_BCM1480_MC_MAX_AGE                20
+#define M_BCM1480_MC_MAX_AGE                _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE)
+#define V_BCM1480_MC_MAX_AGE(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE)
+#define G_BCM1480_MC_MAX_AGE(x)             _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE)
+
+#define M_BCM1480_MC_BERR_DISABLE           _SB_MAKEMASK1(29)
+#define M_BCM1480_MC_FORCE_SEQ              _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_VGEN                   _SB_MAKEMASK1(32)
+
+#define S_BCM1480_MC_SLEW                   33
+#define M_BCM1480_MC_SLEW                   _SB_MAKEMASK(2, S_BCM1480_MC_SLEW)
+#define V_BCM1480_MC_SLEW(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW)
+#define G_BCM1480_MC_SLEW(x)                _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW)
+
+#define M_BCM1480_MC_SSTL_VOLTAGE           _SB_MAKEMASK1(35)
+
+/*
+ * Global Channel Interleave Register (Table 100)
+ */
+
+#define S_BCM1480_MC_INTLV0                 0
+#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
+
+#define S_BCM1480_MC_INTLV1                 8
+#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
+
+#define S_BCM1480_MC_INTLV_MODE             16
+#define M_BCM1480_MC_INTLV_MODE             _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE)
+#define V_BCM1480_MC_INTLV_MODE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE)
+#define G_BCM1480_MC_INTLV_MODE(x)          _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE)
+
+#define K_BCM1480_MC_INTLV_MODE_NONE        0x0
+#define K_BCM1480_MC_INTLV_MODE_01          0x1
+#define K_BCM1480_MC_INTLV_MODE_23          0x2
+#define K_BCM1480_MC_INTLV_MODE_01_23       0x3
+#define K_BCM1480_MC_INTLV_MODE_0123        0x4
+
+#define V_BCM1480_MC_INTLV_MODE_NONE        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE)
+#define V_BCM1480_MC_INTLV_MODE_01          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01)
+#define V_BCM1480_MC_INTLV_MODE_23          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23)
+#define V_BCM1480_MC_INTLV_MODE_01_23       V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23)
+#define V_BCM1480_MC_INTLV_MODE_0123        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123)
+
+/*
+ * ECC Status Register
+ */
+
+#define S_BCM1480_MC_ECC_ERR_ADDR           0
+#define M_BCM1480_MC_ECC_ERR_ADDR           _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR)
+#define V_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR)
+#define G_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR)
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define M_BCM1480_MC_ECC_ERR_RMW            _SB_MAKEMASK1(60)
+#endif
+
+#define M_BCM1480_MC_ECC_MULT_ERR_DET       _SB_MAKEMASK1(61)
+#define M_BCM1480_MC_ECC_UERR_DET           _SB_MAKEMASK1(62)
+#define M_BCM1480_MC_ECC_CERR_DET           _SB_MAKEMASK1(63)
+
+/*
+ * Global ECC Address Register (Table 102)
+ */
+
+#define S_BCM1480_MC_ECC_CORR_ADDR          0
+#define M_BCM1480_MC_ECC_CORR_ADDR          _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR)
+#define V_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR)
+#define G_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR)
+
+/*
+ * Global ECC Correction Register (Table 103)
+ */
+
+#define S_BCM1480_MC_ECC_CORRECT            0
+#define M_BCM1480_MC_ECC_CORRECT            _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT)
+#define V_BCM1480_MC_ECC_CORRECT(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT)
+#define G_BCM1480_MC_ECC_CORRECT(x)         _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT)
+
+/*
+ * Global ECC Performance Counters Control Register (Table 104)
+ */
+
+#define S_BCM1480_MC_CHANNEL_SELECT         0
+#define M_BCM1480_MC_CHANNEL_SELECT         _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT)
+#define V_BCM1480_MC_CHANNEL_SELECT(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT)
+#define G_BCM1480_MC_CHANNEL_SELECT(x)      _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT)
+#define K_BCM1480_MC_CHANNEL_SELECT_0       0x1
+#define K_BCM1480_MC_CHANNEL_SELECT_1       0x2
+#define K_BCM1480_MC_CHANNEL_SELECT_2       0x4
+#define K_BCM1480_MC_CHANNEL_SELECT_3       0x8
+
+#endif /* _BCM1480_MC_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_regs.h b/arch/mips/include/asm/sibyte/bcm1480_regs.h
new file mode 100644
index 000000000000..b4077bb72611
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_regs.h
@@ -0,0 +1,902 @@
+/*  *********************************************************************
+    *  BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
+    *
+    *  Register Definitions                     File: bcm1480_regs.h
+    *
+    *  This module contains the addresses of the on-chip peripherals
+    *  on the BCM1280 and BCM1480.
+    *
+    *  BCM1480 specification level:  1X55_1X80-UM100-D4 (11/24/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+#ifndef _BCM1480_REGS_H
+#define _BCM1480_REGS_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Pull in the BCM1250's registers since a great deal of the 1480's
+    *  functions are the same as the BCM1250.
+    ********************************************************************* */
+
+#include "sb1250_regs.h"
+
+
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  Register addresses are grouped by function and follow the order
+    *  of the User Manual.
+    *
+    *  For the most part, when there is more than one peripheral
+    *  of the same type on the SOC, the constants below will be
+    *  offsets from the base of each peripheral.  For example,
+    *  the MAC registers are described as offsets from the first
+    *  MAC register, and there will be a MAC_REGISTER() macro
+    *  to calculate the base address of a given MAC.
+    *
+    *  The information in this file is based on the BCM1X55/BCM1X80
+    *  User Manual, Document 1X55_1X80-UM100-R, 22/12/03.
+    *
+    *  This file is basically a "what's new" header file.  Since the
+    *  BCM1250 and the new BCM1480 (and derivatives) share many common
+    *  features, this file contains only what's new or changed from
+    *  the 1250.  (above, you can see that we include the 1250 symbols
+    *  to get the base functionality).
+    *
+    *  In software, be sure to use the correct symbols, particularly
+    *  for blocks that are different between the two chip families.
+    *  All BCM1480-specific symbols have _BCM1480_ in their names,
+    *  and all BCM1250-specific and "base" functions that are common in
+    *  both chips have no special names (this is for compatibility with
+    *  older include files).  Therefore, if you're working with the
+    *  SCD, which is very different on each chip, A_SCD_xxx implies
+    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
+    *  version.
+    ********************************************************************* */
+
+
+/*  *********************************************************************
+    * Memory Controller Registers (Section 6)
+    ********************************************************************* */
+
+#define A_BCM1480_MC_BASE_0                 0x0010050000
+#define A_BCM1480_MC_BASE_1                 0x0010051000
+#define A_BCM1480_MC_BASE_2                 0x0010052000
+#define A_BCM1480_MC_BASE_3                 0x0010053000
+#define BCM1480_MC_REGISTER_SPACING         0x1000
+
+#define A_BCM1480_MC_BASE(ctlid)            (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
+#define A_BCM1480_MC_REGISTER(ctlid, reg)    (A_BCM1480_MC_BASE(ctlid)+(reg))
+
+#define R_BCM1480_MC_CONFIG                 0x0000000100
+#define R_BCM1480_MC_CS_START               0x0000000120
+#define R_BCM1480_MC_CS_END                 0x0000000140
+#define S_BCM1480_MC_CS_STARTEND            24
+
+#define R_BCM1480_MC_CS01_ROW0              0x0000000180
+#define R_BCM1480_MC_CS01_ROW1              0x00000001A0
+#define R_BCM1480_MC_CS23_ROW0              0x0000000200
+#define R_BCM1480_MC_CS23_ROW1              0x0000000220
+#define R_BCM1480_MC_CS01_COL0              0x0000000280
+#define R_BCM1480_MC_CS01_COL1              0x00000002A0
+#define R_BCM1480_MC_CS23_COL0              0x0000000300
+#define R_BCM1480_MC_CS23_COL1              0x0000000320
+
+#define R_BCM1480_MC_CSX_BASE               0x0000000180
+#define R_BCM1480_MC_CSX_ROW0               0x0000000000   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_ROW1               0x0000000020   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL0               0x0000000100   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL1               0x0000000120   /* relative to CSX_BASE */
+#define BCM1480_MC_CSX_SPACING              0x0000000080   /* CS23 relative to CS01 */
+
+#define R_BCM1480_MC_CS01_BA                0x0000000380
+#define R_BCM1480_MC_CS23_BA                0x00000003A0
+#define R_BCM1480_MC_DRAMCMD                0x0000000400
+#define R_BCM1480_MC_DRAMMODE               0x0000000420
+#define R_BCM1480_MC_CLOCK_CFG              0x0000000440
+#define R_BCM1480_MC_MCLK_CFG               R_BCM1480_MC_CLOCK_CFG
+#define R_BCM1480_MC_TEST_DATA              0x0000000480
+#define R_BCM1480_MC_TEST_ECC               0x00000004A0
+#define R_BCM1480_MC_TIMING1                0x00000004C0
+#define R_BCM1480_MC_TIMING2                0x00000004E0
+#define R_BCM1480_MC_DLL_CFG                0x0000000500
+#define R_BCM1480_MC_DRIVE_CFG              0x0000000520
+
+#if SIBYTE_HDR_FEATURE(1480, PASS2)
+#define R_BCM1480_MC_ODT                    0x0000000460
+#define R_BCM1480_MC_ECC_STATUS             0x0000000540
+#endif
+
+/* Global registers (single instance) */
+#define A_BCM1480_MC_GLB_CONFIG             0x0010054100
+#define A_BCM1480_MC_GLB_INTLV              0x0010054120
+#define A_BCM1480_MC_GLB_ECC_STATUS         0x0010054140
+#define A_BCM1480_MC_GLB_ECC_ADDR           0x0010054160
+#define A_BCM1480_MC_GLB_ECC_CORRECT        0x0010054180
+#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL   0x00100541A0
+
+/*  *********************************************************************
+    * L2 Cache Control Registers (Section 5)
+    ********************************************************************* */
+
+#define A_BCM1480_L2_BASE                   0x0010040000
+
+#define A_BCM1480_L2_READ_TAG               0x0010040018
+#define A_BCM1480_L2_ECC_TAG                0x0010040038
+#define A_BCM1480_L2_MISC0_VALUE            0x0010040058
+#define A_BCM1480_L2_MISC1_VALUE            0x0010040078
+#define A_BCM1480_L2_MISC2_VALUE            0x0010040098
+#define A_BCM1480_L2_MISC_CONFIG            0x0010040040        /* x040 */
+#define A_BCM1480_L2_CACHE_DISABLE          0x0010040060        /* x060 */
+#define A_BCM1480_L2_MAKECACHEDISABLE(x)    (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
+#define A_BCM1480_L2_WAY_ENABLE_3_0         0x0010040080        /* x080 */
+#define A_BCM1480_L2_WAY_ENABLE_7_4         0x00100400A0        /* x0A0 */
+#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
+#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
+#define A_BCM1480_L2_WAY_LOCAL_3_0          0x0010040100        /* x100 */
+#define A_BCM1480_L2_WAY_LOCAL_7_4          0x0010040120        /* x120 */
+#define A_BCM1480_L2_WAY_REMOTE_3_0         0x0010040140        /* x140 */
+#define A_BCM1480_L2_WAY_REMOTE_7_4         0x0010040160        /* x160 */
+#define A_BCM1480_L2_WAY_AGENT_3_0          0x00100400C0        /* xxC0 */
+#define A_BCM1480_L2_WAY_AGENT_7_4          0x00100400E0        /* xxE0 */
+#define A_BCM1480_L2_WAY_ENABLE(A, banks)   (A | (((~(banks))&0x0F) << 8))
+#define A_BCM1480_L2_BANK_BASE              0x00D0300000
+#define A_BCM1480_L2_BANK_ADDRESS(b)        (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
+#define A_BCM1480_L2_MGMT_TAG_BASE          0x00D0000000
+
+
+/*  *********************************************************************
+    * PCI-X Interface Registers (Section 7)
+    ********************************************************************* */
+
+#define A_BCM1480_PCI_BASE                  0x0010061400
+
+#define A_BCM1480_PCI_RESET                 0x0010061400
+#define A_BCM1480_PCI_DLL                   0x0010061500
+
+#define A_BCM1480_PCI_TYPE00_HEADER         0x002E000000
+
+/*  *********************************************************************
+    * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
+    ********************************************************************* */
+
+/* No register changes with Rev.C BCM1250, but one additional MAC */
+
+#define A_BCM1480_MAC_BASE_2        0x0010066000
+
+#ifndef A_MAC_BASE_2
+#define A_MAC_BASE_2                A_BCM1480_MAC_BASE_2
+#endif
+
+#define A_BCM1480_MAC_BASE_3        0x0010067000
+#define A_MAC_BASE_3                A_BCM1480_MAC_BASE_3
+
+#define R_BCM1480_MAC_DMA_OODPKTLOST        0x00000038
+
+#ifndef R_MAC_DMA_OODPKTLOST
+#define R_MAC_DMA_OODPKTLOST        R_BCM1480_MAC_DMA_OODPKTLOST
+#endif
+
+
+/*  *********************************************************************
+    * DUART Registers (Section 14)
+    ********************************************************************* */
+
+/* No significant differences from BCM1250, two DUARTs */
+
+/*  Conventions, per user manual:
+ *     DUART    generic, channels A,B,C,D
+ *     DUART0   implementing channels A,B
+ *     DUART1   inplementing channels C,D
+ */
+
+#define BCM1480_DUART_NUM_PORTS           4
+
+#define A_BCM1480_DUART0                    0x0010060000
+#define A_BCM1480_DUART1                    0x0010060400
+#define A_BCM1480_DUART(chan)               ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)
+
+#define BCM1480_DUART_CHANREG_SPACING       0x100
+#define A_BCM1480_DUART_CHANREG(chan, reg)                              \
+        (A_BCM1480_DUART(chan) +                                        \
+         BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg))
+#define A_BCM1480_DUART_CTRLREG(chan, reg)                              \
+        (A_BCM1480_DUART(chan) +                                        \
+         BCM1480_DUART_CHANREG_SPACING * 3 + (reg))
+
+#define DUART_IMRISR_SPACING        0x20
+#define DUART_INCHNG_SPACING        0x10
+
+#define R_BCM1480_DUART_IMRREG(chan)                                    \
+        (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
+#define R_BCM1480_DUART_ISRREG(chan)                                    \
+        (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
+#define R_BCM1480_DUART_INCHREG(chan)                                   \
+        (R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING)
+
+#define A_BCM1480_DUART_IMRREG(chan)                                    \
+        (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan)))
+#define A_BCM1480_DUART_ISRREG(chan)                                    \
+        (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_ISRREG(chan)))
+
+#define A_BCM1480_DUART_IN_PORT(chan)                                   \
+        (A_BCM1480_DUART_CTRLREG((chan), R_DUART_IN_PORT))
+
+/*
+ * These constants are the absolute addresses.
+ */
+
+#define A_BCM1480_DUART_MODE_REG_1_C        0x0010060400
+#define A_BCM1480_DUART_MODE_REG_2_C        0x0010060410
+#define A_BCM1480_DUART_STATUS_C            0x0010060420
+#define A_BCM1480_DUART_CLK_SEL_C           0x0010060430
+#define A_BCM1480_DUART_FULL_CTL_C          0x0010060440
+#define A_BCM1480_DUART_CMD_C               0x0010060450
+#define A_BCM1480_DUART_RX_HOLD_C           0x0010060460
+#define A_BCM1480_DUART_TX_HOLD_C           0x0010060470
+#define A_BCM1480_DUART_OPCR_C              0x0010060480
+#define A_BCM1480_DUART_AUX_CTRL_C          0x0010060490
+
+#define A_BCM1480_DUART_MODE_REG_1_D        0x0010060500
+#define A_BCM1480_DUART_MODE_REG_2_D        0x0010060510
+#define A_BCM1480_DUART_STATUS_D            0x0010060520
+#define A_BCM1480_DUART_CLK_SEL_D           0x0010060530
+#define A_BCM1480_DUART_FULL_CTL_D          0x0010060540
+#define A_BCM1480_DUART_CMD_D               0x0010060550
+#define A_BCM1480_DUART_RX_HOLD_D           0x0010060560
+#define A_BCM1480_DUART_TX_HOLD_D           0x0010060570
+#define A_BCM1480_DUART_OPCR_D              0x0010060580
+#define A_BCM1480_DUART_AUX_CTRL_D          0x0010060590
+
+#define A_BCM1480_DUART_INPORT_CHNG_CD      0x0010060600
+#define A_BCM1480_DUART_AUX_CTRL_CD         0x0010060610
+#define A_BCM1480_DUART_ISR_C               0x0010060620
+#define A_BCM1480_DUART_IMR_C               0x0010060630
+#define A_BCM1480_DUART_ISR_D               0x0010060640
+#define A_BCM1480_DUART_IMR_D               0x0010060650
+#define A_BCM1480_DUART_OUT_PORT_CD         0x0010060660
+#define A_BCM1480_DUART_OPCR_CD             0x0010060670
+#define A_BCM1480_DUART_IN_PORT_CD          0x0010060680
+#define A_BCM1480_DUART_ISR_CD              0x0010060690
+#define A_BCM1480_DUART_IMR_CD              0x00100606A0
+#define A_BCM1480_DUART_SET_OPR_CD          0x00100606B0
+#define A_BCM1480_DUART_CLEAR_OPR_CD        0x00100606C0
+#define A_BCM1480_DUART_INPORT_CHNG_C       0x00100606D0
+#define A_BCM1480_DUART_INPORT_CHNG_D       0x00100606E0
+
+
+/*  *********************************************************************
+    * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16)
+    ********************************************************************* */
+
+#define A_BCM1480_IO_PCMCIA_CFG_B       0x0010061A58
+#define A_BCM1480_IO_PCMCIA_STATUS_B    0x0010061A68
+
+/*  *********************************************************************
+    * GPIO Registers (Section 17)
+    ********************************************************************* */
+
+/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
+
+#define A_BCM1480_GPIO_INT_ADD_TYPE         0x0010061A78
+#define R_BCM1480_GPIO_INT_ADD_TYPE         (-8)
+
+#define A_GPIO_INT_ADD_TYPE     A_BCM1480_GPIO_INT_ADD_TYPE
+#define R_GPIO_INT_ADD_TYPE     R_BCM1480_GPIO_INT_ADD_TYPE
+
+/*  *********************************************************************
+    * SMBus Registers (Section 18)
+    ********************************************************************* */
+
+/* No changes from BCM1250 */
+
+/*  *********************************************************************
+    * Timer Registers (Sections 4.6)
+    ********************************************************************* */
+
+/* BCM1480 has two additional watchdogs */
+
+/* Watchdog timers */
+
+#define A_BCM1480_SCD_WDOG_2                0x0010022050
+#define A_BCM1480_SCD_WDOG_3                0x0010022150
+
+#define BCM1480_SCD_NUM_WDOGS               4
+
+#define A_BCM1480_SCD_WDOG_BASE(w)       (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
+#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
+
+#define A_BCM1480_SCD_WDOG_INIT_2       0x0010022050
+#define A_BCM1480_SCD_WDOG_CNT_2        0x0010022058
+#define A_BCM1480_SCD_WDOG_CFG_2        0x0010022060
+
+#define A_BCM1480_SCD_WDOG_INIT_3       0x0010022150
+#define A_BCM1480_SCD_WDOG_CNT_3        0x0010022158
+#define A_BCM1480_SCD_WDOG_CFG_3        0x0010022160
+
+/* BCM1480 has two additional compare registers */
+
+#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT         A_SCD_ZBBUS_CYCLE_COUNT
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE       0x0010020C00
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0           A_SCD_ZBBUS_CYCLE_CP0
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1           A_SCD_ZBBUS_CYCLE_CP1
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2           0x0010020C10
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3           0x0010020C18
+
+/*  *********************************************************************
+    * System Control Registers (Section 4.2)
+    ********************************************************************* */
+
+/* Scratch register in different place */
+
+#define A_BCM1480_SCD_SCRATCH           0x100200A0
+
+/*  *********************************************************************
+    * System Address Trap Registers (Section 4.9)
+    ********************************************************************* */
+
+/* No changes from BCM1250 */
+
+/*  *********************************************************************
+    * System Interrupt Mapper Registers (Sections 4.3-4.5)
+    ********************************************************************* */
+
+#define A_BCM1480_IMR_CPU0_BASE             0x0010020000
+#define A_BCM1480_IMR_CPU1_BASE             0x0010022000
+#define A_BCM1480_IMR_CPU2_BASE             0x0010024000
+#define A_BCM1480_IMR_CPU3_BASE             0x0010026000
+#define BCM1480_IMR_REGISTER_SPACING        0x2000
+#define BCM1480_IMR_REGISTER_SPACING_SHIFT  13
+
+#define A_BCM1480_IMR_MAPPER(cpu)       (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
+#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
+
+/* Most IMR registers are 128 bits, implemented as non-contiguous
+   64-bit registers high (_H) and low (_L) */
+#define BCM1480_IMR_HL_SPACING                  0x1000
+
+#define R_BCM1480_IMR_INTERRUPT_DIAG_H          0x0010
+#define R_BCM1480_IMR_LDT_INTERRUPT_H           0x0018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H       0x0020
+#define R_BCM1480_IMR_INTERRUPT_MASK_H          0x0028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_H         0x0038
+#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
+#define R_BCM1480_IMR_LDT_INTERRUPT_SET         0x0048
+#define R_BCM1480_IMR_MAILBOX_0_CPU             0x00C0
+#define R_BCM1480_IMR_MAILBOX_0_SET_CPU         0x00C8
+#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU         0x00D0
+#define R_BCM1480_IMR_MAILBOX_1_CPU             0x00E0
+#define R_BCM1480_IMR_MAILBOX_1_SET_CPU         0x00E8
+#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU         0x00F0
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H   0x0100
+#define BCM1480_IMR_INTERRUPT_STATUS_COUNT      8
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H      0x0200
+#define BCM1480_IMR_INTERRUPT_MAP_COUNT         64
+
+#define R_BCM1480_IMR_INTERRUPT_DIAG_L          0x1010
+#define R_BCM1480_IMR_LDT_INTERRUPT_L           0x1018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L       0x1020
+#define R_BCM1480_IMR_INTERRUPT_MASK_L          0x1028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_L         0x1038
+#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L   0x1100
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L      0x1200
+
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE   0x0010028000
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE   0x0010028100
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE   0x0010028200
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE   0x0010028300
+#define BCM1480_IMR_ALIAS_MAILBOX_SPACING       0100
+
+#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu)     (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
+                                        (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
+#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
+
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0           0x0000          /* 0x0x0 */
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET       0x0008          /* 0x0x8 */
+
+/*
+ * these macros work together to build the address of a mailbox
+ * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
+ * for mbox_0_set_cpu2 returns 0x00100240C8
+ */
+#define R_BCM1480_IMR_MAILBOX_CPU         0x00
+#define R_BCM1480_IMR_MAILBOX_SET         0x08
+#define R_BCM1480_IMR_MAILBOX_CLR         0x10
+#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
+#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \
+    (A_BCM1480_IMR_CPU0_BASE + \
+     (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
+     (cpu * BCM1480_IMR_REGISTER_SPACING) + \
+     (R_BCM1480_IMR_MAILBOX_0_CPU + reg))
+
+/*  *********************************************************************
+    * System Performance Counter Registers (Section 4.7)
+    ********************************************************************* */
+
+/* BCM1480 has four more performance counter registers, and two control
+   registers. */
+
+#define A_BCM1480_SCD_PERF_CNT_BASE         0x00100204C0
+
+#define A_BCM1480_SCD_PERF_CNT_CFG0         0x00100204C0
+#define A_BCM1480_SCD_PERF_CNT_CFG_0        A_BCM1480_SCD_PERF_CNT_CFG0
+#define A_BCM1480_SCD_PERF_CNT_CFG1         0x00100204C8
+#define A_BCM1480_SCD_PERF_CNT_CFG_1        A_BCM1480_SCD_PERF_CNT_CFG1
+
+#define A_BCM1480_SCD_PERF_CNT_0            A_SCD_PERF_CNT_0
+#define A_BCM1480_SCD_PERF_CNT_1            A_SCD_PERF_CNT_1
+#define A_BCM1480_SCD_PERF_CNT_2            A_SCD_PERF_CNT_2
+#define A_BCM1480_SCD_PERF_CNT_3            A_SCD_PERF_CNT_3
+
+#define A_BCM1480_SCD_PERF_CNT_4            0x00100204F0
+#define A_BCM1480_SCD_PERF_CNT_5            0x00100204F8
+#define A_BCM1480_SCD_PERF_CNT_6            0x0010020500
+#define A_BCM1480_SCD_PERF_CNT_7            0x0010020508
+
+#define BCM1480_SCD_NUM_PERF_CNT 8
+#define BCM1480_SCD_PERF_CNT_SPACING 8
+#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING))
+
+/*  *********************************************************************
+    * System Bus Watcher Registers (Section 4.8)
+    ********************************************************************* */
+
+
+/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
+
+#define A_BCM1480_BUS_ERR_STATUS_DEBUG      0x00100208D8
+
+/*  *********************************************************************
+    * System Debug Controller Registers (Section 19)
+    ********************************************************************* */
+
+/* Same as 1250 */
+
+/*  *********************************************************************
+    * System Trace Unit Registers (Sections 4.10)
+    ********************************************************************* */
+
+/* Same as 1250 */
+
+/*  *********************************************************************
+    * Data Mover DMA Registers (Section 10.7)
+    ********************************************************************* */
+
+/* Same as 1250 */
+
+
+/*  *********************************************************************
+    * HyperTransport Interface Registers (Section 8)
+    ********************************************************************* */
+
+#define BCM1480_HT_NUM_PORTS               3
+#define BCM1480_HT_PORT_SPACING            0x800
+#define A_BCM1480_HT_PORT_HEADER(x)        (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
+
+#define A_BCM1480_HT_PORT0_HEADER          0x00FE000000
+#define A_BCM1480_HT_PORT1_HEADER          0x00FE000800
+#define A_BCM1480_HT_PORT2_HEADER          0x00FE001000
+#define A_BCM1480_HT_TYPE00_HEADER         0x00FE002000
+
+
+/*  *********************************************************************
+    * Node Controller Registers (Section 9)
+    ********************************************************************* */
+
+#define A_BCM1480_NC_BASE                   0x00DFBD0000
+
+#define A_BCM1480_NC_RLD_FIELD              0x00DFBD0000
+#define A_BCM1480_NC_RLD_TRIGGER            0x00DFBD0020
+#define A_BCM1480_NC_RLD_BAD_ERROR          0x00DFBD0040
+#define A_BCM1480_NC_RLD_COR_ERROR          0x00DFBD0060
+#define A_BCM1480_NC_RLD_ECC_STATUS         0x00DFBD0080
+#define A_BCM1480_NC_RLD_WAY_ENABLE         0x00DFBD00A0
+#define A_BCM1480_NC_RLD_RANDOM_LFSR        0x00DFBD00C0
+
+#define A_BCM1480_NC_INTERRUPT_STATUS       0x00DFBD00E0
+#define A_BCM1480_NC_INTERRUPT_ENABLE       0x00DFBD0100
+#define A_BCM1480_NC_TIMEOUT_COUNTER        0x00DFBD0120
+#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL    0x00DFBD0140
+
+#define A_BCM1480_NC_CREDIT_STATUS_REG0     0x00DFBD0200
+#define A_BCM1480_NC_CREDIT_STATUS_REG1     0x00DFBD0220
+#define A_BCM1480_NC_CREDIT_STATUS_REG2     0x00DFBD0240
+#define A_BCM1480_NC_CREDIT_STATUS_REG3     0x00DFBD0260
+#define A_BCM1480_NC_CREDIT_STATUS_REG4     0x00DFBD0280
+#define A_BCM1480_NC_CREDIT_STATUS_REG5     0x00DFBD02A0
+#define A_BCM1480_NC_CREDIT_STATUS_REG6     0x00DFBD02C0
+#define A_BCM1480_NC_CREDIT_STATUS_REG7     0x00DFBD02E0
+#define A_BCM1480_NC_CREDIT_STATUS_REG8     0x00DFBD0300
+#define A_BCM1480_NC_CREDIT_STATUS_REG9     0x00DFBD0320
+#define A_BCM1480_NC_CREDIT_STATUS_REG10    0x00DFBE0000
+#define A_BCM1480_NC_CREDIT_STATUS_REG11    0x00DFBE0020
+#define A_BCM1480_NC_CREDIT_STATUS_REG12    0x00DFBE0040
+
+#define A_BCM1480_NC_SR_TIMEOUT_COUNTER     0x00DFBE0060
+#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
+
+
+/*  *********************************************************************
+    * H&R Block Configuration Registers (Section 12.4)
+    ********************************************************************* */
+
+#define A_BCM1480_HR_BASE_0                 0x00DF820000
+#define A_BCM1480_HR_BASE_1                 0x00DF8A0000
+#define A_BCM1480_HR_BASE_2                 0x00DF920000
+#define BCM1480_HR_REGISTER_SPACING         0x80000
+
+#define A_BCM1480_HR_BASE(idx)              (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
+#define A_BCM1480_HR_REGISTER(idx, reg)      (A_BCM1480_HR_BASE(idx) + (reg))
+
+#define R_BCM1480_HR_CFG                    0x0000000000
+
+#define R_BCM1480_HR_MAPPING                0x0000010010
+
+#define BCM1480_HR_RULE_SPACING             0x0000000010
+#define BCM1480_HR_NUM_RULES                16
+#define BCM1480_HR_OP_OFFSET                0x0000000100
+#define BCM1480_HR_TYPE_OFFSET              0x0000000108
+#define R_BCM1480_HR_RULE_OP(idx)           (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+#define R_BCM1480_HR_RULE_TYPE(idx)         (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+
+#define BCM1480_HR_LEAF_SPACING             0x0000000010
+#define BCM1480_HR_NUM_LEAVES               10
+#define BCM1480_HR_LEAF_OFFSET              0x0000000300
+#define R_BCM1480_HR_HA_LEAF0(idx)          (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))
+
+#define R_BCM1480_HR_EX_LEAF0               0x00000003A0
+
+#define BCM1480_HR_PATH_SPACING             0x0000000010
+#define BCM1480_HR_NUM_PATHS                16
+#define BCM1480_HR_PATH_OFFSET              0x0000000600
+#define R_BCM1480_HR_PATH(idx)              (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))
+
+#define R_BCM1480_HR_PATH_DEFAULT           0x0000000700
+
+#define BCM1480_HR_ROUTE_SPACING            8
+#define BCM1480_HR_NUM_ROUTES               512
+#define BCM1480_HR_ROUTE_OFFSET             0x0000001000
+#define R_BCM1480_HR_RT_WORD(idx)           (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))
+
+
+/* checked to here - ehs */
+/*  *********************************************************************
+    * Packet Manager DMA Registers (Section 12.5)
+    ********************************************************************* */
+
+#define A_BCM1480_PM_BASE                   0x0010056000
+
+#define A_BCM1480_PMI_LCL_0                 0x0010058000
+#define A_BCM1480_PMO_LCL_0                 0x001005C000
+#define A_BCM1480_PMI_OFFSET_0              (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_OFFSET_0              (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)
+
+#define BCM1480_PM_LCL_REGISTER_SPACING     0x100
+#define BCM1480_PM_NUM_CHANNELS             32
+
+#define A_BCM1480_PMI_LCL_BASE(idx)             (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMI_LCL_REGISTER(idx, reg)     (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
+#define A_BCM1480_PMO_LCL_BASE(idx)             (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMO_LCL_REGISTER(idx, reg)     (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
+
+#define BCM1480_PM_INT_PACKING              8
+#define BCM1480_PM_INT_FUNCTION_SPACING     0x40
+#define BCM1480_PM_INT_NUM_FUNCTIONS        3
+
+/*
+ * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
+ */
+
+#define R_BCM1480_PM_BASE_SIZE              0x0000000000
+#define R_BCM1480_PM_CNT                    0x0000000008
+#define R_BCM1480_PM_PFCNT                  0x0000000010
+#define R_BCM1480_PM_LAST                   0x0000000018
+#define R_BCM1480_PM_PFINDX                 0x0000000020
+#define R_BCM1480_PM_INT_WMK                0x0000000028
+#define R_BCM1480_PM_CONFIG0                0x0000000030
+#define R_BCM1480_PM_LOCALDEBUG             0x0000000078
+#define R_BCM1480_PM_CACHEABILITY           0x0000000080   /* PMI only */
+#define R_BCM1480_PM_INT_CNFG               0x0000000088
+#define R_BCM1480_PM_DESC_MERGE_TIMER       0x0000000090
+#define R_BCM1480_PM_LOCALDEBUG_PIB         0x00000000F8   /* PMI only */
+#define R_BCM1480_PM_LOCALDEBUG_POB         0x00000000F8   /* PMO only */
+
+/*
+ * Global Registers (Not Channelized)
+ */
+
+#define A_BCM1480_PMI_GLB_0                 0x0010056000
+#define A_BCM1480_PMO_GLB_0                 0x0010057000
+
+/*
+ * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
+ */
+
+#define R_BCM1480_PM_PMO_MAPPING            0x00000008C8   /* PMO only */
+
+#define A_BCM1480_PM_PMO_MAPPING        (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
+
+/*
+ * Interrupt mapping registers
+ */
+
+
+#define A_BCM1480_PMI_INT_0                 0x0010056800
+#define A_BCM1480_PMI_INT(q)                (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMI_INT_OFFSET_0          (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_INT_0                 0x0010057800
+#define A_BCM1480_PMO_INT(q)                (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMO_INT_OFFSET_0          (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)
+
+/*
+ * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
+ */
+
+#define R_BCM1480_PM_INT_ST                 0x0000000000
+#define R_BCM1480_PM_INT_MSK                0x0000000040
+#define R_BCM1480_PM_INT_CLR                0x0000000080
+#define R_BCM1480_PM_MRGD_INT               0x00000000C0
+
+/*
+ * Debug registers (global)
+ */
+
+#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI    0x0010056000
+#define A_BCM1480_PM_GLOBALDEBUG_PID        0x00100567F8
+#define A_BCM1480_PM_GLOBALDEBUG_PIB        0x0010056FF8
+#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO    0x0010057000
+#define A_BCM1480_PM_GLOBALDEBUG_POD        0x00100577F8
+#define A_BCM1480_PM_GLOBALDEBUG_POB        0x0010057FF8
+
+/*  *********************************************************************
+    *  Switch performance counters
+    ********************************************************************* */
+
+#define A_BCM1480_SWPERF_CFG    0xdfb91800
+#define A_BCM1480_SWPERF_CNT0   0xdfb91880
+#define A_BCM1480_SWPERF_CNT1   0xdfb91888
+#define A_BCM1480_SWPERF_CNT2   0xdfb91890
+#define A_BCM1480_SWPERF_CNT3   0xdfb91898
+
+
+/*  *********************************************************************
+    *  Switch Trace Unit
+    ********************************************************************* */
+
+#define A_BCM1480_SWTRC_MATCH_CONTROL_0         0xDFB91000
+#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0      0xDFB91100
+#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0       0xDFB91108
+#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0       0xDFB91200
+#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0        0xDFB91208
+#define A_BCM1480_SWTRC_EVENT_0                 0xDFB91300
+#define A_BCM1480_SWTRC_SEQUENCE_0              0xDFB91400
+
+#define A_BCM1480_SWTRC_CFG                     0xDFB91500
+#define A_BCM1480_SWTRC_READ                    0xDFB91508
+
+#define A_BCM1480_SWDEBUG_SCHEDSTOP             0xDFB92000
+
+#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8))
+#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8))
+#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8))
+
+#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16))
+#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16))
+
+
+
+/*  *********************************************************************
+    *  High-Speed Port Registers (Section 13)
+    ********************************************************************* */
+
+#define A_BCM1480_HSP_BASE_0                0x00DF810000
+#define A_BCM1480_HSP_BASE_1                0x00DF890000
+#define A_BCM1480_HSP_BASE_2                0x00DF910000
+#define BCM1480_HSP_REGISTER_SPACING        0x80000
+
+#define A_BCM1480_HSP_BASE(idx)             (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
+#define A_BCM1480_HSP_REGISTER(idx, reg)     (A_BCM1480_HSP_BASE(idx) + (reg))
+
+#define R_BCM1480_HSP_RX_SPI4_CFG_0           0x0000000000
+#define R_BCM1480_HSP_RX_SPI4_CFG_1           0x0000000008
+#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
+#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
+#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN     0x0000000020
+#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028
+
+#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0      0x0000000200
+#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1      0x0000000208
+
+#define R_BCM1480_HSP_RX_PLL_CNFG             0x0000000800
+#define R_BCM1480_HSP_RX_CALIBRATION          0x0000000808
+#define R_BCM1480_HSP_RX_TEST                 0x0000000810
+#define R_BCM1480_HSP_RX_DIAG_DETAILS         0x0000000818
+#define R_BCM1480_HSP_RX_DIAG_CRC_0           0x0000000820
+#define R_BCM1480_HSP_RX_DIAG_CRC_1           0x0000000828
+#define R_BCM1480_HSP_RX_DIAG_HTCMD           0x0000000830
+#define R_BCM1480_HSP_RX_DIAG_PKTCTL          0x0000000838
+
+#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER   0x0000000870
+
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0       0x0000020020
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1       0x0000020028
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2       0x0000020030
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3       0x0000020038
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4       0x0000020040
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5       0x0000020048
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6       0x0000020050
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7       0x0000020058
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
+
+/* XXX Following registers were shuffled.  Renamed/renumbered per errata. */
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_0      0x0000020078
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_1      0x0000020080
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_2      0x0000020088
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_3      0x0000020090
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_4      0x0000020098
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_5      0x00000200A0
+
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_0      0x00000200B0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_1      0x00000200B8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_2      0x00000200C0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_3      0x00000200C8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_4      0x00000200D0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_5      0x00000200D8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_6      0x00000200E0
+#define R_BCM1480_HSP_RX_SPI_WATERMARK_7      0x00000200E8
+#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx)   (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
+
+#define R_BCM1480_HSP_RX_VIS_CMDQ_0           0x00000200F0
+#define R_BCM1480_HSP_RX_VIS_CMDQ_1           0x00000200F8
+#define R_BCM1480_HSP_RX_VIS_CMDQ_2           0x0000020100
+#define R_BCM1480_HSP_RX_RAM_READCTL          0x0000020108
+#define R_BCM1480_HSP_RX_RAM_READWINDOW       0x0000020110
+#define R_BCM1480_HSP_RX_RF_READCTL           0x0000020118
+#define R_BCM1480_HSP_RX_RF_READWINDOW        0x0000020120
+
+#define R_BCM1480_HSP_TX_SPI4_CFG_0           0x0000040000
+#define R_BCM1480_HSP_TX_SPI4_CFG_1           0x0000040008
+#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT    0x0000040010
+
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0       0x0000040020
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1       0x0000040028
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2       0x0000040030
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3       0x0000040038
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4       0x0000040040
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5       0x0000040048
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6       0x0000040050
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7       0x0000040058
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_NPC_RAMALLOC         0x0000040078
+#define R_BCM1480_HSP_TX_RSP_RAMALLOC         0x0000040080
+#define R_BCM1480_HSP_TX_PC_RAMALLOC          0x0000040088
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0      0x0000040090
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1      0x0000040098
+#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2      0x00000400A0
+
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0      0x00000400B0
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1      0x00000400B8
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2      0x00000400C0
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3      0x00000400C8
+#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT       0x00000400D0
+#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT       0x00000400D8
+
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0      0x00000400E0
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1      0x00000400E8
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2      0x00000400F0
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3      0x00000400F8
+#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
+#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT       0x0000040100
+#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT       0x0000040108
+
+#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0      0x0000040200
+#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1      0x0000040208
+
+#define R_BCM1480_HSP_TX_PLL_CNFG             0x0000040800
+#define R_BCM1480_HSP_TX_CALIBRATION          0x0000040808
+#define R_BCM1480_HSP_TX_TEST                 0x0000040810
+
+#define R_BCM1480_HSP_TX_VIS_CMDQ_0           0x0000040840
+#define R_BCM1480_HSP_TX_VIS_CMDQ_1           0x0000040848
+#define R_BCM1480_HSP_TX_VIS_CMDQ_2           0x0000040850
+#define R_BCM1480_HSP_TX_RAM_READCTL          0x0000040860
+#define R_BCM1480_HSP_TX_RAM_READWINDOW       0x0000040868
+#define R_BCM1480_HSP_TX_RF_READCTL           0x0000040870
+#define R_BCM1480_HSP_TX_RF_READWINDOW        0x0000040878
+
+#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
+#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN     0x0000040888
+
+#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
+#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x)  (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))
+
+
+
+/*  *********************************************************************
+    *  Physical Address Map (Table 10 and Figure 7)
+    ********************************************************************* */
+
+#define A_BCM1480_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
+#define A_BCM1480_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
+#define A_BCM1480_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
+#define A_BCM1480_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
+#define A_BCM1480_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
+#define A_BCM1480_PHYS_GENBUS_END               _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES     _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES     _SB_MAKE64(0x0029000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES       _SB_MAKE64(0x002C000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES      _SB_MAKE64(0x002E000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES     _SB_MAKE64(0x002F000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES      _SB_MAKE64(0x0030000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES       _SB_MAKE64(0x0040000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS        _SB_MAKE64(0x0060000000)
+#define A_BCM1480_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
+#define A_BCM1480_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS      _SB_MAKE64(0x00A8000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS      _SB_MAKE64(0x00A9000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS        _SB_MAKE64(0x00AC000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS       _SB_MAKE64(0x00AE000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS      _SB_MAKE64(0x00AF000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS       _SB_MAKE64(0x00B0000000)
+#define A_BCM1480_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
+#define A_BCM1480_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES   _SB_MAKE64(0x00D8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES        _SB_MAKE64(0x00DC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES       _SB_MAKE64(0x00DE000000)
+#define A_BCM1480_PHYS_HS_SUBSYS                _SB_MAKE64(0x00DF000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS    _SB_MAKE64(0x00F8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BITS         _SB_MAKE64(0x00FC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS        _SB_MAKE64(0x00FE000000)
+#define A_BCM1480_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
+#define A_BCM1480_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
+#define A_BCM1480_PHYS_PCI_UPPER                _SB_MAKE64(0x1000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES     _SB_MAKE64(0x2000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS      _SB_MAKE64(0x3000000000)
+#define A_BCM1480_PHYS_HT_NODE_ALIAS            _SB_MAKE64(0x4000000000)
+#define A_BCM1480_PHYS_HT_FULLACCESS            _SB_MAKE64(0xF000000000)
+
+
+/*  *********************************************************************
+    *  L2 Cache as RAM (Table 54)
+    ********************************************************************* */
+
+#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
+#define BCM1480_PHYS_L2CACHE_NUM_WAYS           8
+#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000100000)
+#define A_BCM1480_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0300000)
+#define A_BCM1480_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D0320000)
+#define A_BCM1480_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D0340000)
+#define A_BCM1480_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D0360000)
+#define A_BCM1480_PHYS_L2CACHE_WAY4             _SB_MAKE64(0x00D0380000)
+#define A_BCM1480_PHYS_L2CACHE_WAY5             _SB_MAKE64(0x00D03A0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY6             _SB_MAKE64(0x00D03C0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY7             _SB_MAKE64(0x00D03E0000)
+
+#endif /* _BCM1480_REGS_H */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h
new file mode 100644
index 000000000000..25ef24cbb92a
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h
@@ -0,0 +1,406 @@
+/*  *********************************************************************
+    *  BCM1280/BCM1400 Board Support Package
+    *
+    *  SCD Constants and Macros                     File: bcm1480_scd.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the System Control and Debug module.
+    *
+    *  BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003,2004,2005
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+#ifndef _BCM1480_SCD_H
+#define _BCM1480_SCD_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Pull in the BCM1250's SCD since lots of stuff is the same.
+    ********************************************************************* */
+
+#include "sb1250_scd.h"
+
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  This file is basically a "what's new" header file.  Since the
+    *  BCM1250 and the new BCM1480 (and derivatives) share many common
+    *  features, this file contains only what's new or changed from
+    *  the 1250.  (above, you can see that we include the 1250 symbols
+    *  to get the base functionality).
+    *
+    *  In software, be sure to use the correct symbols, particularly
+    *  for blocks that are different between the two chip families.
+    *  All BCM1480-specific symbols have _BCM1480_ in their names,
+    *  and all BCM1250-specific and "base" functions that are common in
+    *  both chips have no special names (this is for compatibility with
+    *  older include files).  Therefore, if you're working with the
+    *  SCD, which is very different on each chip, A_SCD_xxx implies
+    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
+    *  version.
+    ********************************************************************* */
+
+/*  *********************************************************************
+    *  System control/debug registers
+    ********************************************************************* */
+
+/*
+ * System Identification and Revision Register (Table 12)
+ * Register: SCD_SYSTEM_REVISION
+ * This register is field compatible with the 1250.
+ */
+
+/*
+ * New part definitions
+ */
+
+#define K_SYS_PART_BCM1480          0x1406
+#define K_SYS_PART_BCM1280          0x1206
+#define K_SYS_PART_BCM1455          0x1407
+#define K_SYS_PART_BCM1255          0x1257
+#define K_SYS_PART_BCM1158          0x1156
+
+/*
+ * Manufacturing Information Register (Table 14)
+ * Register: SCD_SYSTEM_MANUF
+ */
+
+/*
+ * System Configuration Register (Table 15)
+ * Register: SCD_SYSTEM_CFG
+ * Entire register is different from 1250, all new constants below
+ */
+
+#define M_BCM1480_SYS_RESERVED0             _SB_MAKEMASK1(0)
+#define M_BCM1480_SYS_HT_MINRSTCNT          _SB_MAKEMASK1(1)
+#define M_BCM1480_SYS_RESERVED2             _SB_MAKEMASK1(2)
+#define M_BCM1480_SYS_RESERVED3             _SB_MAKEMASK1(3)
+#define M_BCM1480_SYS_RESERVED4             _SB_MAKEMASK1(4)
+#define M_BCM1480_SYS_IOB_DIV               _SB_MAKEMASK1(5)
+
+#define S_BCM1480_SYS_PLL_DIV               _SB_MAKE64(6)
+#define M_BCM1480_SYS_PLL_DIV               _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
+#define V_BCM1480_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
+#define G_BCM1480_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
+
+#define S_BCM1480_SYS_SW_DIV                _SB_MAKE64(11)
+#define M_BCM1480_SYS_SW_DIV                _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
+#define V_BCM1480_SYS_SW_DIV(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
+#define G_BCM1480_SYS_SW_DIV(x)             _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
+
+#define M_BCM1480_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
+#define M_BCM1480_SYS_DUART1_ENABLE         _SB_MAKEMASK1(17)
+
+#define S_BCM1480_SYS_BOOT_MODE             _SB_MAKE64(18)
+#define M_BCM1480_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
+#define V_BCM1480_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
+#define G_BCM1480_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
+#define K_BCM1480_SYS_BOOT_MODE_ROM32       0
+#define K_BCM1480_SYS_BOOT_MODE_ROM8        1
+#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
+#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG   3
+#define M_BCM1480_SYS_BOOT_MODE_SMBUS       _SB_MAKEMASK1(19)
+
+#define M_BCM1480_SYS_PCI_HOST              _SB_MAKEMASK1(20)
+#define M_BCM1480_SYS_PCI_ARBITER           _SB_MAKEMASK1(21)
+#define M_BCM1480_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
+#define M_BCM1480_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
+#define M_BCM1480_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(24)
+#define M_BCM1480_SYS_RESERVED25            _SB_MAKEMASK1(25)
+
+#define S_BCM1480_SYS_CONFIG                26
+#define M_BCM1480_SYS_CONFIG                _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
+#define V_BCM1480_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
+#define G_BCM1480_SYS_CONFIG(x)             _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
+
+#define M_BCM1480_SYS_RESERVED32            _SB_MAKEMASK(32, 15)
+
+#define S_BCM1480_SYS_NODEID                47
+#define M_BCM1480_SYS_NODEID                _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
+#define V_BCM1480_SYS_NODEID(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
+#define G_BCM1480_SYS_NODEID(x)             _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
+
+#define M_BCM1480_SYS_CCNUMA_EN             _SB_MAKEMASK1(51)
+#define M_BCM1480_SYS_CPU_RESET_0           _SB_MAKEMASK1(52)
+#define M_BCM1480_SYS_CPU_RESET_1           _SB_MAKEMASK1(53)
+#define M_BCM1480_SYS_CPU_RESET_2           _SB_MAKEMASK1(54)
+#define M_BCM1480_SYS_CPU_RESET_3           _SB_MAKEMASK1(55)
+#define S_BCM1480_SYS_DISABLECPU0           56
+#define M_BCM1480_SYS_DISABLECPU0           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
+#define S_BCM1480_SYS_DISABLECPU1           57
+#define M_BCM1480_SYS_DISABLECPU1           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
+#define S_BCM1480_SYS_DISABLECPU2           58
+#define M_BCM1480_SYS_DISABLECPU2           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
+#define S_BCM1480_SYS_DISABLECPU3           59
+#define M_BCM1480_SYS_DISABLECPU3           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
+
+#define M_BCM1480_SYS_SB_SOFTRES            _SB_MAKEMASK1(60)
+#define M_BCM1480_SYS_EXT_RESET             _SB_MAKEMASK1(61)
+#define M_BCM1480_SYS_SYSTEM_RESET          _SB_MAKEMASK1(62)
+#define M_BCM1480_SYS_SW_FLAG               _SB_MAKEMASK1(63)
+
+/*
+ * Scratch Register (Table 16)
+ * Register: SCD_SYSTEM_SCRATCH
+ * Same as BCM1250
+ */
+
+
+/*
+ * Mailbox Registers (Table 17)
+ * Registers: SCD_MBOX_{0,1}_CPU_x
+ * Same as BCM1250
+ */
+
+
+/*
+ * See bcm1480_int.h for interrupt mapper registers.
+ */
+
+
+/*
+ * Watchdog Timer Initial Count Registers (Table 23)
+ * Registers: SCD_WDOG_INIT_CNT_x
+ *
+ * The watchdogs are almost the same as the 1250, except
+ * the configuration register has more bits to control the
+ * other CPUs.
+ */
+
+
+/*
+ * Watchdog Timer Configuration Registers (Table 25)
+ * Registers: SCD_WDOG_CFG_x
+ */
+
+#define M_BCM1480_SCD_WDOG_ENABLE           _SB_MAKEMASK1(0)
+
+#define S_BCM1480_SCD_WDOG_RESET_TYPE       2
+#define M_BCM1480_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
+#define V_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
+#define G_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
+
+#define K_BCM1480_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
+#define K_BCM1480_SCD_WDOG_RESET_SOFT       1
+#define K_BCM1480_SCD_WDOG_RESET_CPU0       3
+#define K_BCM1480_SCD_WDOG_RESET_CPU1       5
+#define K_BCM1480_SCD_WDOG_RESET_CPU2       9
+#define K_BCM1480_SCD_WDOG_RESET_CPU3       17
+#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS   31
+
+
+#define M_BCM1480_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(8)
+
+/*
+ * General Timer Initial Count Registers (Table 26)
+ * Registers: SCD_TIMER_INIT_x
+ *
+ * The timer registers are the same as the BCM1250
+ */
+
+
+/*
+ * ZBbus Count Register (Table 29)
+ * Register: ZBBUS_CYCLE_COUNT
+ *
+ * Same as BCM1250
+ */
+
+/*
+ * ZBbus Compare Registers (Table 30)
+ * Registers: ZBBUS_CYCLE_CPx
+ *
+ * Same as BCM1250
+ */
+
+
+/*
+ * System Performance Counter Configuration Register (Table 31)
+ * Register: PERF_CNT_CFG_0
+ *
+ * SPC_CFG_SRC[0-3] is the same as the 1250.
+ * SPC_CFG_SRC[4-7] only exist on the 1480
+ * The clear/enable bits are in different locations on the 1250 and 1480.
+ */
+
+#define S_SPC_CFG_SRC4              32
+#define M_SPC_CFG_SRC4              _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
+#define V_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
+#define G_SPC_CFG_SRC4(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)
+
+#define S_SPC_CFG_SRC5              40
+#define M_SPC_CFG_SRC5              _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
+#define V_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
+#define G_SPC_CFG_SRC5(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)
+
+#define S_SPC_CFG_SRC6              48
+#define M_SPC_CFG_SRC6              _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
+#define V_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
+#define G_SPC_CFG_SRC6(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)
+
+#define S_SPC_CFG_SRC7              56
+#define M_SPC_CFG_SRC7              _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
+#define V_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
+#define G_SPC_CFG_SRC7(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)
+
+/*
+ * System Performance Counter Control Register (Table 32)
+ * Register: PERF_CNT_CFG_1
+ * BCM1480 specific
+ */
+#define M_BCM1480_SPC_CFG_CLEAR     _SB_MAKEMASK1(0)
+#define M_BCM1480_SPC_CFG_ENABLE    _SB_MAKEMASK1(1)
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_SPC_CFG_CLEAR                 M_BCM1480_SPC_CFG_CLEAR
+#define M_SPC_CFG_ENABLE                M_BCM1480_SPC_CFG_ENABLE
+#endif
+
+/*
+ * System Performance Counters (Table 33)
+ * Registers: PERF_CNT_x
+ */
+
+#define S_BCM1480_SPC_CNT_COUNT             0
+#define M_BCM1480_SPC_CNT_COUNT             _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
+#define V_BCM1480_SPC_CNT_COUNT(x)          _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
+#define G_BCM1480_SPC_CNT_COUNT(x)          _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)
+
+#define M_BCM1480_SPC_CNT_OFLOW             _SB_MAKEMASK1(40)
+
+
+/*
+ * Bus Watcher Error Status Register (Tables 36, 37)
+ * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
+ * Same as BCM1250.
+ */
+
+/*
+ * Bus Watcher Error Data Registers (Table 38)
+ * Registers: BUS_ERR_DATA_x
+ * Same as BCM1250.
+ */
+
+/*
+ * Bus Watcher L2 ECC Counter Register (Table 39)
+ * Register: BUS_L2_ERRORS
+ * Same as BCM1250.
+ */
+
+
+/*
+ * Bus Watcher Memory and I/O Error Counter Register (Table 40)
+ * Register: BUS_MEM_IO_ERRORS
+ * Same as BCM1250.
+ */
+
+
+/*
+ * Address Trap Registers
+ *
+ * Register layout same as BCM1250, almost.  The bus agents
+ * are different, and the address trap configuration bits are
+ * slightly different.
+ */
+
+#define M_BCM1480_ATRAP_INDEX             _SB_MAKEMASK(4, 0)
+#define M_BCM1480_ATRAP_ADDRESS           _SB_MAKEMASK(40, 0)
+
+#define S_BCM1480_ATRAP_CFG_CNT            0
+#define M_BCM1480_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
+#define V_BCM1480_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
+#define G_BCM1480_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)
+
+#define M_BCM1480_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
+#define M_BCM1480_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
+#define M_BCM1480_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
+#define M_BCM1480_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
+#define M_BCM1480_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
+
+#define S_BCM1480_ATRAP_CFG_AGENTID     8
+#define M_BCM1480_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
+#define V_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
+#define G_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)
+
+
+#define K_BCM1480_BUS_AGENT_CPU0            0
+#define K_BCM1480_BUS_AGENT_CPU1            1
+#define K_BCM1480_BUS_AGENT_NC              2
+#define K_BCM1480_BUS_AGENT_IOB             3
+#define K_BCM1480_BUS_AGENT_SCD             4
+#define K_BCM1480_BUS_AGENT_L2C             6
+#define K_BCM1480_BUS_AGENT_MC              7
+#define K_BCM1480_BUS_AGENT_CPU2            8
+#define K_BCM1480_BUS_AGENT_CPU3            9
+#define K_BCM1480_BUS_AGENT_PM              10
+
+#define S_BCM1480_ATRAP_CFG_CATTR           12
+#define M_BCM1480_ATRAP_CFG_CATTR           _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
+#define V_BCM1480_ATRAP_CFG_CATTR(x)        _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
+#define G_BCM1480_ATRAP_CFG_CATTR(x)        _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)
+
+#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE    0
+#define K_BCM1480_ATRAP_CFG_CATTR_UNC       1
+#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH    2
+#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT  3
+
+#define M_BCM1480_ATRAP_CFG_CATTRINV        _SB_MAKEMASK1(14)
+
+
+/*
+ * Trace Event Registers (Table 47)
+ * Same as BCM1250.
+ */
+
+/*
+ * Trace Sequence Control Registers (Table 48)
+ * Registers: TRACE_SEQUENCE_x
+ *
+ * Same as BCM1250 except for two new fields.
+ */
+
+
+#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN    _SB_MAKEMASK1(25)
+
+#define S_BCM1480_SCD_TRSEQ_SWFUNC          26
+#define M_BCM1480_SCD_TRSEQ_SWFUNC          _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define V_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define G_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)
+
+/*
+ * Trace Control Register (Table 49)
+ * Register: TRACE_CFG
+ *
+ * BCM1480 changes to this register (other than location of the CUR_ADDR field)
+ * are defined below.
+ */
+
+#define S_BCM1480_SCD_TRACE_CFG_MODE        16
+#define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
+#define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
+#define G_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)
+
+#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS   0
+#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
+#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID    2
+
+#endif /* _BCM1480_SCD_H */
diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h
new file mode 100644
index 000000000000..ebefe797fc1d
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/bigsur.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ASM_SIBYTE_BIGSUR_H
+#define __ASM_SIBYTE_BIGSUR_H
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/bcm1480_int.h>
+
+#ifdef CONFIG_SIBYTE_BIGSUR
+#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
+#define SIBYTE_HAVE_PCMCIA 1
+#define SIBYTE_HAVE_IDE    1
+#endif
+
+/* Generic bus chip selects */
+#define LEDS_CS         3
+#define LEDS_PHYS       0x100a0000
+
+#ifdef SIBYTE_HAVE_IDE
+#define IDE_CS          4
+#define IDE_PHYS        0x100b0000
+#define K_GPIO_GB_IDE   4
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+
+#ifdef SIBYTE_HAVE_PCMCIA
+#define PCMCIA_CS       6
+#define PCMCIA_PHYS     0x11000000
+#define K_GPIO_PC_READY 9
+#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
+#endif
+
+#endif /* __ASM_SIBYTE_BIGSUR_H */
+
diff --git a/arch/mips/include/asm/sibyte/board.h b/arch/mips/include/asm/sibyte/board.h
new file mode 100644
index 000000000000..25372ae0e814
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/board.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef _SIBYTE_BOARD_H
+#define _SIBYTE_BOARD_H
+
+#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \
+    defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR)
+#include <asm/sibyte/swarm.h>
+#endif
+
+#if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE)
+#include <asm/sibyte/sentosa.h>
+#endif
+
+#ifdef CONFIG_SIBYTE_CARMEL
+#include <asm/sibyte/carmel.h>
+#endif
+
+#ifdef CONFIG_SIBYTE_BIGSUR
+#include <asm/sibyte/bigsur.h>
+#endif
+
+#ifdef __ASSEMBLY__
+
+#ifdef LEDS_PHYS
+#define setleds(t0, t1, c0, c1, c2, c3) \
+        li      t0, (LEDS_PHYS|0xa0000000); \
+        li      t1, c0; \
+        sb      t1, 0x18(t0); \
+        li      t1, c1; \
+        sb      t1, 0x10(t0); \
+        li      t1, c2; \
+        sb      t1, 0x08(t0); \
+        li      t1, c3; \
+        sb      t1, 0x00(t0)
+#else
+#define setleds(t0, t1, c0, c1, c2, c3)
+#endif /* LEDS_PHYS */
+
+#else
+
+void swarm_setup(void);
+
+#ifdef LEDS_PHYS
+extern void setleds(char *str);
+#else
+#define setleds(s) do { } while (0)
+#endif /* LEDS_PHYS */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SIBYTE_BOARD_H */
diff --git a/arch/mips/include/asm/sibyte/carmel.h b/arch/mips/include/asm/sibyte/carmel.h
new file mode 100644
index 000000000000..11cad71323e8
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/carmel.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2002 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ASM_SIBYTE_CARMEL_H
+#define __ASM_SIBYTE_CARMEL_H
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_int.h>
+
+#define SIBYTE_BOARD_NAME "Carmel"
+
+#define GPIO_PHY_INTERRUPT      2
+#define GPIO_NONMASKABLE_INT    3
+#define GPIO_CF_INSERTED        6
+#define GPIO_MONTEREY_RESET     7
+#define GPIO_QUADUART_INT       8
+#define GPIO_CF_INT             9
+#define GPIO_FPGA_CCLK          10
+#define GPIO_FPGA_DOUT          11
+#define GPIO_FPGA_DIN           12
+#define GPIO_FPGA_PGM           13
+#define GPIO_FPGA_DONE          14
+#define GPIO_FPGA_INIT          15
+
+#define LEDS_CS                 2
+#define LEDS_PHYS               0x100C0000
+#define MLEDS_CS                3
+#define MLEDS_PHYS              0x100A0000
+#define UART_CS                 4
+#define UART_PHYS               0x100D0000
+#define ARAVALI_CS              5
+#define ARAVALI_PHYS            0x11000000
+#define IDE_CS                  6
+#define IDE_PHYS                0x100B0000
+#define ARAVALI2_CS             7
+#define ARAVALI2_PHYS           0x100E0000
+
+#if defined(CONFIG_SIBYTE_CARMEL)
+#define K_GPIO_GB_IDE   9
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+
+
+#endif /* __ASM_SIBYTE_CARMEL_H */
diff --git a/arch/mips/include/asm/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h
new file mode 100644
index 000000000000..80c1a052662a
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef _ASM_SIBYTE_SB1250_H
+#define _ASM_SIBYTE_SB1250_H
+
+/*
+ * yymmddpp: year, month, day, patch.
+ * should sync with Makefile EXTRAVERSION
+ */
+#define SIBYTE_RELEASE 0x02111403
+
+#define SB1250_NR_IRQS 64
+
+#define BCM1480_NR_IRQS                 128
+#define BCM1480_NR_IRQS_HALF            64
+
+#define SB1250_DUART_MINOR_BASE         64
+
+#ifndef __ASSEMBLY__
+
+#include <asm/addrspace.h>
+
+/* For revision/pass information */
+#include <asm/sibyte/sb1250_scd.h>
+#include <asm/sibyte/bcm1480_scd.h>
+extern unsigned int sb1_pass;
+extern unsigned int soc_pass;
+extern unsigned int soc_type;
+extern unsigned int periph_rev;
+extern unsigned int zbbus_mhz;
+
+extern void sb1250_time_init(void);
+extern void sb1250_mask_irq(int cpu, int irq);
+extern void sb1250_unmask_irq(int cpu, int irq);
+
+extern void bcm1480_time_init(void);
+extern void bcm1480_mask_irq(int cpu, int irq);
+extern void bcm1480_unmask_irq(int cpu, int irq);
+
+#define AT_spin \
+        __asm__ __volatile__ (          \
+                ".set noat\n"           \
+                "li $at, 0\n"           \
+                "1: beqz $at, 1b\n"     \
+                ".set at\n"             \
+                )
+
+#endif
+
+#define IOADDR(a) ((void __iomem *)(IO_BASE + (a)))
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_defs.h b/arch/mips/include/asm/sibyte/sb1250_defs.h
new file mode 100644
index 000000000000..09365f9111fa
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_defs.h
@@ -0,0 +1,259 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Global constants and macros              File: sb1250_defs.h
+    *
+    *  This file contains macros and definitions used by the other
+    *  include files.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+#ifndef _SB1250_DEFS_H
+#define _SB1250_DEFS_H
+
+/*
+ * These headers require ANSI C89 string concatenation, and GCC or other
+ * 'long long' (64-bit integer) support.
+ */
+#if !defined(__STDC__) && !defined(_MSC_VER)
+#error SiByte headers require ANSI C89 support
+#endif
+
+
+/*  *********************************************************************
+    *  Macros for feature tests, used to enable include file features
+    *  for chip features only present in certain chip revisions.
+    *
+    *  SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
+    *  which is to be exposed by the headers.  If undefined, it defaults to
+    *  "all features."
+    *
+    *  Use like:
+    *
+    *    #define SIBYTE_HDR_FEATURES    SIBYTE_HDR_FMASK_112x_PASS1
+    *
+    *           Generate defines only for that revision of chip.
+    *
+    *    #if SIBYTE_HDR_FEATURE(chip,pass)
+    *
+    *           True if header features for that revision or later of
+    *           that particular chip type are enabled in SIBYTE_HDR_FEATURES.
+    *           (Use this to bracket #defines for features present in a given
+    *           revision and later.)
+    *
+    *           Note that there is no implied ordering between chip types.
+    *
+    *           Note also that 'chip' and 'pass' must textually exactly
+    *           match the defines below.  So, for example,
+    *           SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
+    *           SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
+    *
+    *    #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
+    *
+    *           Same as SIBYTE_HDR_FEATURE, but true for the named revision
+    *           and earlier revisions of the named chip type.
+    *
+    *    #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
+    *
+    *           Same as SIBYTE_HDR_FEATURE, but only true for the named
+    *           revision of the named chip type.  (Note that this CANNOT
+    *           be used to verify that you're compiling only for that
+    *           particular chip/revision.  It will be true any time this
+    *           chip/revision is included in SIBYTE_HDR_FEATURES.)
+    *
+    *    #if SIBYTE_HDR_FEATURE_CHIP(chip)
+    *
+    *           True if header features for (any revision of) that chip type
+    *           are enabled in SIBYTE_HDR_FEATURES.  (Use this to bracket
+    *           #defines for features specific to a given chip type.)
+    *
+    *  Mask values currently include room for additional revisions of each
+    *  chip type, but can be renumbered at will.  Note that they MUST fit
+    *  into 31 bits and may not include C type constructs, for safe use in
+    *  CPP conditionals.  Bit positions within chip types DO indicate
+    *  ordering, so be careful when adding support for new minor revs.
+    ********************************************************************* */
+
+#define SIBYTE_HDR_FMASK_1250_ALL               0x000000ff
+#define SIBYTE_HDR_FMASK_1250_PASS1             0x00000001
+#define SIBYTE_HDR_FMASK_1250_PASS2             0x00000002
+#define SIBYTE_HDR_FMASK_1250_PASS3             0x00000004
+
+#define SIBYTE_HDR_FMASK_112x_ALL               0x00000f00
+#define SIBYTE_HDR_FMASK_112x_PASS1             0x00000100
+
+#define SIBYTE_HDR_FMASK_1480_ALL               0x0000f000
+#define SIBYTE_HDR_FMASK_1480_PASS1             0x00001000
+#define SIBYTE_HDR_FMASK_1480_PASS2             0x00002000
+
+/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
+#define SIBYTE_HDR_FMASK(chip, pass)                                    \
+    (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
+#define SIBYTE_HDR_FMASK_ALLREVS(chip)                                  \
+    (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
+
+/* Default constant value for all chips, all revisions */
+#define SIBYTE_HDR_FMASK_ALL                                            \
+    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL              \
+     | SIBYTE_HDR_FMASK_1480_ALL)
+
+/* This one is used for the "original" BCM1250/BCM112x chips.  We use this
+   to weed out constants and macros that do not exist on later chips like
+   the BCM1480  */
+#define SIBYTE_HDR_FMASK_1250_112x_ALL                                  \
+    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
+#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
+
+#ifndef SIBYTE_HDR_FEATURES
+#define SIBYTE_HDR_FEATURES                     SIBYTE_HDR_FMASK_ALL
+#endif
+
+
+/* Bit mask for revisions of chip exclusively before the named revision.  */
+#define SIBYTE_HDR_FMASK_BEFORE(chip, pass)                             \
+    ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
+
+/* Bit mask for revisions of chip exclusively after the named revision.  */
+#define SIBYTE_HDR_FMASK_AFTER(chip, pass)                              \
+    (~(SIBYTE_HDR_FMASK(chip, pass)                                     \
+     | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
+
+
+/* True if header features enabled for (any revision of) that chip type.  */
+#define SIBYTE_HDR_FEATURE_CHIP(chip)                                   \
+    (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
+
+/* True for all versions of the BCM1250 and BCM1125, but not true for
+   anything else */
+#define SIBYTE_HDR_FEATURE_1250_112x \
+      (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
+/*    (!!  (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */
+
+/* True if header features enabled for that rev or later, inclusive.  */
+#define SIBYTE_HDR_FEATURE(chip, pass)                                  \
+    (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
+          | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
+
+/* True if header features enabled for exactly that rev.  */
+#define SIBYTE_HDR_FEATURE_EXACT(chip, pass)                            \
+    (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
+
+/* True if header features enabled for that rev or before, inclusive.  */
+#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass)                            \
+    (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
+         | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
+
+
+/*  *********************************************************************
+    *  Naming schemes for constants in these files:
+    *
+    *  M_xxx           MASK constant (identifies bits in a register).
+    *                  For multi-bit fields, all bits in the field will
+    *                  be set.
+    *
+    *  K_xxx           "Code" constant (value for data in a multi-bit
+    *                  field).  The value is right justified.
+    *
+    *  V_xxx           "Value" constant.  This is the same as the
+    *                  corresponding "K_xxx" constant, except it is
+    *                  shifted to the correct position in the register.
+    *
+    *  S_xxx           SHIFT constant.  This is the number of bits that
+    *                  a field value (code) needs to be shifted
+    *                  (towards the left) to put the value in the right
+    *                  position for the register.
+    *
+    *  A_xxx           ADDRESS constant.  This will be a physical
+    *                  address.  Use the PHYS_TO_K1 macro to generate
+    *                  a K1SEG address.
+    *
+    *  R_xxx           RELATIVE offset constant.  This is an offset from
+    *                  an A_xxx constant (usually the first register in
+    *                  a group).
+    *
+    *  G_xxx(X)        GET value.  This macro obtains a multi-bit field
+    *                  from a register, masks it, and shifts it to
+    *                  the bottom of the register (retrieving a K_xxx
+    *                  value, for example).
+    *
+    *  V_xxx(X)        VALUE.  This macro computes the value of a
+    *                  K_xxx constant shifted to the correct position
+    *                  in the register.
+    ********************************************************************* */
+
+
+
+
+/*
+ * Cast to 64-bit number.  Presumably the syntax is different in
+ * assembly language.
+ *
+ * Note: you'll need to define uint32_t and uint64_t in your headers.
+ */
+
+#if !defined(__ASSEMBLY__)
+#define _SB_MAKE64(x) ((uint64_t)(x))
+#define _SB_MAKE32(x) ((uint32_t)(x))
+#else
+#define _SB_MAKE64(x) (x)
+#define _SB_MAKE32(x) (x)
+#endif
+
+
+/*
+ * Make a mask for 1 bit at position 'n'
+ */
+
+#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
+#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
+
+/*
+ * Make a mask for 'v' bits at position 'n'
+ */
+
+#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
+#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
+
+/*
+ * Make a value at 'v' at bit position 'n'
+ */
+
+#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n))
+#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n))
+
+#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
+#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
+
+/*
+ * Macros to read/write on-chip registers
+ * XXX should we do the PHYS_TO_K1 here?
+ */
+
+
+#if defined(__mips64) && !defined(__ASSEMBLY__)
+#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
+#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_dma.h b/arch/mips/include/asm/sibyte/sb1250_dma.h
new file mode 100644
index 000000000000..bad56171d747
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_dma.h
@@ -0,0 +1,594 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  DMA definitions                          File: sb1250_dma.h
+    *
+    *  This module contains constants and macros useful for
+    *  programming the SB1250's DMA controllers, both the data mover
+    *  and the Ethernet DMA.
+    *
+    *  SB1250 specification level:  User's manual 10/21/02
+    *  BCM1280 specification level: User's manual 11/24/03
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_DMA_H
+#define _SB1250_DMA_H
+
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  DMA Registers
+    ********************************************************************* */
+
+/*
+ * Ethernet and Serial DMA Configuration Register 0  (Table 7-4)
+ * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
+ * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
+ * Registers: DMA_CONFIG0_SER_x_RX
+ * Registers: DMA_CONFIG0_SER_x_TX
+ */
+
+
+#define M_DMA_DROP                  _SB_MAKEMASK1(0)
+
+#define M_DMA_CHAIN_SEL             _SB_MAKEMASK1(1)
+#define M_DMA_RESERVED1             _SB_MAKEMASK1(2)
+
+#define S_DMA_DESC_TYPE             _SB_MAKE64(1)
+#define M_DMA_DESC_TYPE             _SB_MAKEMASK(2, S_DMA_DESC_TYPE)
+#define V_DMA_DESC_TYPE(x)          _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
+#define G_DMA_DESC_TYPE(x)          _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)
+
+#define K_DMA_DESC_TYPE_RING_AL         0
+#define K_DMA_DESC_TYPE_CHAIN_AL        1
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define K_DMA_DESC_TYPE_RING_UAL_WI     2
+#define K_DMA_DESC_TYPE_RING_UAL_RMW    3
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
+#define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
+#define M_DMA_LWM_INT_EN            _SB_MAKEMASK1(5)
+#define M_DMA_TBX_EN                _SB_MAKEMASK1(6)
+#define M_DMA_TDX_EN                _SB_MAKEMASK1(7)
+
+#define S_DMA_INT_PKTCNT            _SB_MAKE64(8)
+#define M_DMA_INT_PKTCNT            _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
+#define V_DMA_INT_PKTCNT(x)         _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
+#define G_DMA_INT_PKTCNT(x)         _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)
+
+#define S_DMA_RINGSZ                _SB_MAKE64(16)
+#define M_DMA_RINGSZ                _SB_MAKEMASK(16, S_DMA_RINGSZ)
+#define V_DMA_RINGSZ(x)             _SB_MAKEVALUE(x, S_DMA_RINGSZ)
+#define G_DMA_RINGSZ(x)             _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)
+
+#define S_DMA_HIGH_WATERMARK        _SB_MAKE64(32)
+#define M_DMA_HIGH_WATERMARK        _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
+#define V_DMA_HIGH_WATERMARK(x)     _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
+#define G_DMA_HIGH_WATERMARK(x)     _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)
+
+#define S_DMA_LOW_WATERMARK         _SB_MAKE64(48)
+#define M_DMA_LOW_WATERMARK         _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
+#define V_DMA_LOW_WATERMARK(x)      _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
+#define G_DMA_LOW_WATERMARK(x)      _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)
+
+/*
+ * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
+ * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
+ * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
+ * Registers: DMA_CONFIG1_SER_x_RX
+ * Registers: DMA_CONFIG1_SER_x_TX
+ */
+
+#define M_DMA_HDR_CF_EN             _SB_MAKEMASK1(0)
+#define M_DMA_ASIC_XFR_EN           _SB_MAKEMASK1(1)
+#define M_DMA_PRE_ADDR_EN           _SB_MAKEMASK1(2)
+#define M_DMA_FLOW_CTL_EN           _SB_MAKEMASK1(3)
+#define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
+#define M_DMA_L2CA                  _SB_MAKEMASK1(5)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_DMA_RX_XTRA_STATUS        _SB_MAKEMASK1(6)
+#define M_DMA_TX_CPU_PAUSE          _SB_MAKEMASK1(6)
+#define M_DMA_TX_FC_PAUSE_EN        _SB_MAKEMASK1(7)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define M_DMA_MBZ1                  _SB_MAKEMASK(6, 15)
+
+#define S_DMA_HDR_SIZE              _SB_MAKE64(21)
+#define M_DMA_HDR_SIZE              _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
+#define V_DMA_HDR_SIZE(x)           _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
+#define G_DMA_HDR_SIZE(x)           _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)
+
+#define M_DMA_MBZ2                  _SB_MAKEMASK(5, 32)
+
+#define S_DMA_ASICXFR_SIZE          _SB_MAKE64(37)
+#define M_DMA_ASICXFR_SIZE          _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
+#define V_DMA_ASICXFR_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
+#define G_DMA_ASICXFR_SIZE(x)       _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)
+
+#define S_DMA_INT_TIMEOUT           _SB_MAKE64(48)
+#define M_DMA_INT_TIMEOUT           _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
+#define V_DMA_INT_TIMEOUT(x)        _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
+#define G_DMA_INT_TIMEOUT(x)        _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)
+
+/*
+ * Ethernet and Serial DMA Descriptor base address (Table 7-6)
+ */
+
+#define M_DMA_DSCRBASE_MBZ          _SB_MAKEMASK(4, 0)
+
+
+/*
+ * ASIC Mode Base Address (Table 7-7)
+ */
+
+#define M_DMA_ASIC_BASE_MBZ         _SB_MAKEMASK(20, 0)
+
+/*
+ * DMA Descriptor Count Registers (Table 7-8)
+ */
+
+/* No bitfields */
+
+
+/*
+ * Current Descriptor Address Register (Table 7-11)
+ */
+
+#define S_DMA_CURDSCR_ADDR          _SB_MAKE64(0)
+#define M_DMA_CURDSCR_ADDR          _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
+#define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
+#define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_DMA_TX_CH_PAUSE_ON        _SB_MAKEMASK1(56)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+/*
+ * Receive Packet Drop Registers
+ */
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_OODLOST_RX           _SB_MAKE64(0)
+#define M_DMA_OODLOST_RX           _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
+#define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)
+
+#define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
+#define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
+#define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+/*  *********************************************************************
+    *  DMA Descriptors
+    ********************************************************************* */
+
+/*
+ * Descriptor doubleword "A"  (Table 7-12)
+ */
+
+#define S_DMA_DSCRA_OFFSET          _SB_MAKE64(0)
+#define M_DMA_DSCRA_OFFSET          _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
+#define V_DMA_DSCRA_OFFSET(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
+#define G_DMA_DSCRA_OFFSET(x)       _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)
+
+/* Note: Don't shift the address over, just mask it with the mask below */
+#define S_DMA_DSCRA_A_ADDR          _SB_MAKE64(5)
+#define M_DMA_DSCRA_A_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)
+
+#define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
+#define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
+#define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
+#define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
+#define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_DSCRA_DSCR_CNT        _SB_MAKE64(40)
+#define M_DMA_DSCRA_DSCR_CNT        _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT)
+#define G_DMA_DSCRA_DSCR_CNT(x)     _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
+#define M_DMA_DSCRA_OFFSETB         _SB_MAKEMASK1(50)
+
+#define S_DMA_DSCRA_STATUS          _SB_MAKE64(51)
+#define M_DMA_DSCRA_STATUS          _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
+#define V_DMA_DSCRA_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
+#define G_DMA_DSCRA_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)
+
+/*
+ * Descriptor doubleword "B"  (Table 7-13)
+ */
+
+
+#define S_DMA_DSCRB_OPTIONS         _SB_MAKE64(0)
+#define M_DMA_DSCRB_OPTIONS         _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
+#define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
+#define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
+#define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
+#define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
+#define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
+
+/* Note: Don't shift the address over, just mask it with the mask below */
+#define S_DMA_DSCRB_B_ADDR          _SB_MAKE64(5)
+#define M_DMA_DSCRB_B_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)
+
+#define S_DMA_DSCRB_B_SIZE          _SB_MAKE64(40)
+#define M_DMA_DSCRB_B_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
+#define V_DMA_DSCRB_B_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
+#define G_DMA_DSCRB_B_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)
+
+#define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
+#define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB)
+#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB)
+#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
+#define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
+#define V_DMA_DSCRB_PKT_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
+#define G_DMA_DSCRB_PKT_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)
+
+/*
+ * from pass2 some bits in dscr_b are also used for rx status
+ */
+#define S_DMA_DSCRB_STATUS          _SB_MAKE64(0)
+#define M_DMA_DSCRB_STATUS          _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
+#define V_DMA_DSCRB_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
+#define G_DMA_DSCRB_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)
+
+/*
+ * Ethernet Descriptor Status Bits (Table 7-15)
+ */
+
+#define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
+#define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/* Note: This bit is in the DSCR_B options field */
+#define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/* Note: These bits are in the DSCR_B options field */
+#define M_DMA_ETH_VLAN_FLAG     _SB_MAKEMASK1(1)
+#define M_DMA_ETH_CRC_FLAG      _SB_MAKEMASK1(2)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_DMA_ETHRX_RXCH            53
+#define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
+#define V_DMA_ETHRX_RXCH(x)         _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
+#define G_DMA_ETHRX_RXCH(x)         _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)
+
+#define S_DMA_ETHRX_PKTTYPE         55
+#define M_DMA_ETHRX_PKTTYPE         _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
+#define V_DMA_ETHRX_PKTTYPE(x)      _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
+#define G_DMA_ETHRX_PKTTYPE(x)      _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)
+
+#define K_DMA_ETHRX_PKTTYPE_IPV4    0
+#define K_DMA_ETHRX_PKTTYPE_ARPV4   1
+#define K_DMA_ETHRX_PKTTYPE_802     2
+#define K_DMA_ETHRX_PKTTYPE_OTHER   3
+#define K_DMA_ETHRX_PKTTYPE_USER0   4
+#define K_DMA_ETHRX_PKTTYPE_USER1   5
+#define K_DMA_ETHRX_PKTTYPE_USER2   6
+#define K_DMA_ETHRX_PKTTYPE_USER3   7
+
+#define M_DMA_ETHRX_MATCH_HASH      _SB_MAKEMASK1(58)
+#define M_DMA_ETHRX_MATCH_EXACT     _SB_MAKEMASK1(59)
+#define M_DMA_ETHRX_BCAST           _SB_MAKEMASK1(60)
+#define M_DMA_ETHRX_MCAST           _SB_MAKEMASK1(61)
+#define M_DMA_ETHRX_BAD             _SB_MAKEMASK1(62)
+#define M_DMA_ETHRX_SOP             _SB_MAKEMASK1(63)
+
+/*
+ * Ethernet Transmit Status Bits (Table 7-16)
+ */
+
+#define M_DMA_ETHTX_SOP             _SB_MAKEMASK1(63)
+
+/*
+ * Ethernet Transmit Options (Table 7-17)
+ */
+
+#define K_DMA_ETHTX_NOTSOP          _SB_MAKE64(0x00)
+#define K_DMA_ETHTX_APPENDCRC       _SB_MAKE64(0x01)
+#define K_DMA_ETHTX_REPLACECRC      _SB_MAKE64(0x02)
+#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
+#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
+#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
+#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
+#define K_DMA_ETHTX_NOMODS          _SB_MAKE64(0x07)
+#define K_DMA_ETHTX_RESERVED1       _SB_MAKE64(0x08)
+#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
+#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
+#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
+#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
+#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
+#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
+#define K_DMA_ETHTX_RESERVED2       _SB_MAKE64(0x0F)
+
+/*
+ * Serial Receive Options (Table 7-18)
+ */
+#define M_DMA_SERRX_CRC_ERROR       _SB_MAKEMASK1(56)
+#define M_DMA_SERRX_ABORT           _SB_MAKEMASK1(57)
+#define M_DMA_SERRX_OCTET_ERROR     _SB_MAKEMASK1(58)
+#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
+#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
+#define M_DMA_SERRX_OVERRUN_ERROR   _SB_MAKEMASK1(61)
+#define M_DMA_SERRX_GOOD            _SB_MAKEMASK1(62)
+#define M_DMA_SERRX_SOP             _SB_MAKEMASK1(63)
+
+/*
+ * Serial Transmit Status Bits (Table 7-20)
+ */
+
+#define M_DMA_SERTX_FLAG            _SB_MAKEMASK1(63)
+
+/*
+ * Serial Transmit Options (Table 7-21)
+ */
+
+#define K_DMA_SERTX_RESERVED        _SB_MAKEMASK1(0)
+#define K_DMA_SERTX_APPENDCRC       _SB_MAKEMASK1(1)
+#define K_DMA_SERTX_APPENDPAD       _SB_MAKEMASK1(2)
+#define K_DMA_SERTX_ABORT           _SB_MAKEMASK1(3)
+
+
+/*  *********************************************************************
+    *  Data Mover Registers
+    ********************************************************************* */
+
+/*
+ * Data Mover Descriptor Base Address Register (Table 7-22)
+ * Register: DM_DSCR_BASE_0
+ * Register: DM_DSCR_BASE_1
+ * Register: DM_DSCR_BASE_2
+ * Register: DM_DSCR_BASE_3
+ */
+
+#define M_DM_DSCR_BASE_MBZ          _SB_MAKEMASK(4, 0)
+
+/*  Note: Just mask the base address and then OR it in. */
+#define S_DM_DSCR_BASE_ADDR         _SB_MAKE64(4)
+#define M_DM_DSCR_BASE_ADDR         _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)
+
+#define S_DM_DSCR_BASE_RINGSZ       _SB_MAKE64(40)
+#define M_DM_DSCR_BASE_RINGSZ       _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)
+#define V_DM_DSCR_BASE_RINGSZ(x)    _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
+#define G_DM_DSCR_BASE_RINGSZ(x)    _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
+
+#define S_DM_DSCR_BASE_PRIORITY     _SB_MAKE64(56)
+#define M_DM_DSCR_BASE_PRIORITY     _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)
+#define V_DM_DSCR_BASE_PRIORITY(x)  _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
+#define G_DM_DSCR_BASE_PRIORITY(x)  _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
+
+#define K_DM_DSCR_BASE_PRIORITY_1   0
+#define K_DM_DSCR_BASE_PRIORITY_2   1
+#define K_DM_DSCR_BASE_PRIORITY_4   2
+#define K_DM_DSCR_BASE_PRIORITY_8   3
+#define K_DM_DSCR_BASE_PRIORITY_16  4
+
+#define M_DM_DSCR_BASE_ACTIVE       _SB_MAKEMASK1(59)
+#define M_DM_DSCR_BASE_INTERRUPT    _SB_MAKEMASK1(60)
+#define M_DM_DSCR_BASE_RESET        _SB_MAKEMASK1(61)   /* write register */
+#define M_DM_DSCR_BASE_ERROR        _SB_MAKEMASK1(61)   /* read register */
+#define M_DM_DSCR_BASE_ABORT        _SB_MAKEMASK1(62)
+#define M_DM_DSCR_BASE_ENABL        _SB_MAKEMASK1(63)
+
+/*
+ * Data Mover Descriptor Count Register (Table 7-25)
+ */
+
+/* no bitfields */
+
+/*
+ * Data Mover Current Descriptor Address (Table 7-24)
+ * Register: DM_CUR_DSCR_ADDR_0
+ * Register: DM_CUR_DSCR_ADDR_1
+ * Register: DM_CUR_DSCR_ADDR_2
+ * Register: DM_CUR_DSCR_ADDR_3
+ */
+
+#define S_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKE64(0)
+#define M_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)
+
+#define S_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKE64(48)
+#define M_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
+#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
+#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\
+                                     M_DM_CUR_DSCR_DSCR_COUNT)
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/*
+ * Data Mover Channel Partial Result Registers
+ * Register: DM_PARTIAL_0
+ * Register: DM_PARTIAL_1
+ * Register: DM_PARTIAL_2
+ * Register: DM_PARTIAL_3
+ */
+#define S_DM_PARTIAL_CRC_PARTIAL      _SB_MAKE64(0)
+#define M_DM_PARTIAL_CRC_PARTIAL      _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
+#define V_DM_PARTIAL_CRC_PARTIAL(r)   _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
+#define G_DM_PARTIAL_CRC_PARTIAL(r)   _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\
+                                       M_DM_PARTIAL_CRC_PARTIAL)
+
+#define S_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKE64(32)
+#define M_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
+#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
+#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\
+                                       M_DM_PARTIAL_TCPCS_PARTIAL)
+
+#define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/*
+ * Data Mover CRC Definition Registers
+ * Register: CRC_DEF_0
+ * Register: CRC_DEF_1
+ */
+#define S_CRC_DEF_CRC_INIT            _SB_MAKE64(0)
+#define M_CRC_DEF_CRC_INIT            _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
+#define V_CRC_DEF_CRC_INIT(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
+#define G_CRC_DEF_CRC_INIT(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
+                                       M_CRC_DEF_CRC_INIT)
+
+#define S_CRC_DEF_CRC_POLY            _SB_MAKE64(32)
+#define M_CRC_DEF_CRC_POLY            _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
+#define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
+#define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
+                                       M_CRC_DEF_CRC_POLY)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/*
+ * Data Mover CRC/Checksum Definition Registers
+ * Register: CTCP_DEF_0
+ * Register: CTCP_DEF_1
+ */
+#define S_CTCP_DEF_CRC_TXOR           _SB_MAKE64(0)
+#define M_CTCP_DEF_CRC_TXOR           _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
+#define V_CTCP_DEF_CRC_TXOR(r)        _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
+#define G_CTCP_DEF_CRC_TXOR(r)        _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
+                                       M_CTCP_DEF_CRC_TXOR)
+
+#define S_CTCP_DEF_TCPCS_INIT         _SB_MAKE64(32)
+#define M_CTCP_DEF_TCPCS_INIT         _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)
+#define V_CTCP_DEF_TCPCS_INIT(r)      _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
+#define G_CTCP_DEF_TCPCS_INIT(r)      _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\
+                                       M_CTCP_DEF_TCPCS_INIT)
+
+#define S_CTCP_DEF_CRC_WIDTH          _SB_MAKE64(48)
+#define M_CTCP_DEF_CRC_WIDTH          _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
+#define V_CTCP_DEF_CRC_WIDTH(r)       _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
+#define G_CTCP_DEF_CRC_WIDTH(r)       _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
+                                       M_CTCP_DEF_CRC_WIDTH)
+
+#define K_CTCP_DEF_CRC_WIDTH_4        0
+#define K_CTCP_DEF_CRC_WIDTH_2        1
+#define K_CTCP_DEF_CRC_WIDTH_1        2
+
+#define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+
+/*
+ * Data Mover Descriptor Doubleword "A"  (Table 7-26)
+ */
+
+#define S_DM_DSCRA_DST_ADDR         _SB_MAKE64(0)
+#define M_DM_DSCRA_DST_ADDR         _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)
+
+#define M_DM_DSCRA_UN_DEST          _SB_MAKEMASK1(40)
+#define M_DM_DSCRA_UN_SRC           _SB_MAKEMASK1(41)
+#define M_DM_DSCRA_INTERRUPT        _SB_MAKEMASK1(42)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+#define M_DM_DSCRA_THROTTLE         _SB_MAKEMASK1(43)
+#endif /* up to 1250 PASS1 */
+
+#define S_DM_DSCRA_DIR_DEST         _SB_MAKE64(44)
+#define M_DM_DSCRA_DIR_DEST         _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST(x)      _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
+#define G_DM_DSCRA_DIR_DEST(x)      _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)
+
+#define K_DM_DSCRA_DIR_DEST_INCR    0
+#define K_DM_DSCRA_DIR_DEST_DECR    1
+#define K_DM_DSCRA_DIR_DEST_CONST   2
+
+#define V_DM_DSCRA_DIR_DEST_INCR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST_DECR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST_CONST   _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
+
+#define S_DM_DSCRA_DIR_SRC          _SB_MAKE64(46)
+#define M_DM_DSCRA_DIR_SRC          _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC(x)       _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
+#define G_DM_DSCRA_DIR_SRC(x)       _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)
+
+#define K_DM_DSCRA_DIR_SRC_INCR     0
+#define K_DM_DSCRA_DIR_SRC_DECR     1
+#define K_DM_DSCRA_DIR_SRC_CONST    2
+
+#define V_DM_DSCRA_DIR_SRC_INCR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC_DECR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC_CONST    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
+
+
+#define M_DM_DSCRA_ZERO_MEM         _SB_MAKEMASK1(48)
+#define M_DM_DSCRA_PREFETCH         _SB_MAKEMASK1(49)
+#define M_DM_DSCRA_L2C_DEST         _SB_MAKEMASK1(50)
+#define M_DM_DSCRA_L2C_SRC          _SB_MAKEMASK1(51)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_DM_DSCRA_RD_BKOFF         _SB_MAKEMASK1(52)
+#define M_DM_DSCRA_WR_BKOFF         _SB_MAKEMASK1(53)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
+#define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
+#define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
+#define M_DM_DSCRA_CRC_EN           _SB_MAKEMASK1(57)
+#define M_DM_DSCRA_CRC_RES          _SB_MAKEMASK1(58)
+#define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
+#define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
+#define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3, 61)
+
+/*
+ * Data Mover Descriptor Doubleword "B"  (Table 7-25)
+ */
+
+#define S_DM_DSCRB_SRC_ADDR         _SB_MAKE64(0)
+#define M_DM_DSCRB_SRC_ADDR         _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)
+
+#define S_DM_DSCRB_SRC_LENGTH       _SB_MAKE64(40)
+#define M_DM_DSCRB_SRC_LENGTH       _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)
+#define V_DM_DSCRB_SRC_LENGTH(x)    _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
+#define G_DM_DSCRB_SRC_LENGTH(x)    _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_genbus.h b/arch/mips/include/asm/sibyte/sb1250_genbus.h
new file mode 100644
index 000000000000..94e9c7c8e783
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_genbus.h
@@ -0,0 +1,474 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Generic Bus Constants                     File: sb1250_genbus.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the SB1250's Generic Bus interface
+    *
+    *  SB1250 specification level:  User's manual 10/21/02
+    *  BCM1280 specification level: User's Manual 11/14/03
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000, 2001, 2002, 2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_GENBUS_H
+#define _SB1250_GENBUS_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Generic Bus Region Configuration Registers (Table 11-4)
+ */
+
+#define S_IO_RDY_ACTIVE         0
+#define M_IO_RDY_ACTIVE         _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
+
+#define S_IO_ENA_RDY            1
+#define M_IO_ENA_RDY            _SB_MAKEMASK1(S_IO_ENA_RDY)
+
+#define S_IO_WIDTH_SEL          2
+#define M_IO_WIDTH_SEL          _SB_MAKEMASK(2, S_IO_WIDTH_SEL)
+#define K_IO_WIDTH_SEL_1        0
+#define K_IO_WIDTH_SEL_2        1
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define K_IO_WIDTH_SEL_1L       2
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define K_IO_WIDTH_SEL_4        3
+#define V_IO_WIDTH_SEL(x)       _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)
+#define G_IO_WIDTH_SEL(x)       _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL)
+
+#define S_IO_PARITY_ENA         4
+#define M_IO_PARITY_ENA         _SB_MAKEMASK1(S_IO_PARITY_ENA)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_IO_BURST_EN           5
+#define M_IO_BURST_EN           _SB_MAKEMASK1(S_IO_BURST_EN)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define S_IO_PARITY_ODD         6
+#define M_IO_PARITY_ODD         _SB_MAKEMASK1(S_IO_PARITY_ODD)
+#define S_IO_NONMUX             7
+#define M_IO_NONMUX             _SB_MAKEMASK1(S_IO_NONMUX)
+
+#define S_IO_TIMEOUT            8
+#define M_IO_TIMEOUT            _SB_MAKEMASK(8, S_IO_TIMEOUT)
+#define V_IO_TIMEOUT(x)         _SB_MAKEVALUE(x, S_IO_TIMEOUT)
+#define G_IO_TIMEOUT(x)         _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT)
+
+/*
+ * Generic Bus Region Size register (Table 11-5)
+ */
+
+#define S_IO_MULT_SIZE          0
+#define M_IO_MULT_SIZE          _SB_MAKEMASK(12, S_IO_MULT_SIZE)
+#define V_IO_MULT_SIZE(x)       _SB_MAKEVALUE(x, S_IO_MULT_SIZE)
+#define G_IO_MULT_SIZE(x)       _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE)
+
+#define S_IO_REGSIZE            16       /* # bits to shift size for this reg */
+
+/*
+ * Generic Bus Region Address (Table 11-6)
+ */
+
+#define S_IO_START_ADDR         0
+#define M_IO_START_ADDR         _SB_MAKEMASK(14, S_IO_START_ADDR)
+#define V_IO_START_ADDR(x)      _SB_MAKEVALUE(x, S_IO_START_ADDR)
+#define G_IO_START_ADDR(x)      _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR)
+
+#define S_IO_ADDRBASE           16       /* # bits to shift addr for this reg */
+
+#define M_IO_BLK_CACHE          _SB_MAKEMASK1(15)
+
+
+/*
+ * Generic Bus Timing 0 Registers (Table 11-7)
+ */
+
+#define S_IO_ALE_WIDTH          0
+#define M_IO_ALE_WIDTH          _SB_MAKEMASK(3, S_IO_ALE_WIDTH)
+#define V_IO_ALE_WIDTH(x)       _SB_MAKEVALUE(x, S_IO_ALE_WIDTH)
+#define G_IO_ALE_WIDTH(x)       _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_IO_EARLY_CS           _SB_MAKEMASK1(3)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_IO_ALE_TO_CS          4
+#define M_IO_ALE_TO_CS          _SB_MAKEMASK(2, S_IO_ALE_TO_CS)
+#define V_IO_ALE_TO_CS(x)       _SB_MAKEVALUE(x, S_IO_ALE_TO_CS)
+#define G_IO_ALE_TO_CS(x)       _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_IO_BURST_WIDTH           _SB_MAKE64(6)
+#define M_IO_BURST_WIDTH           _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
+#define V_IO_BURST_WIDTH(x)        _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
+#define G_IO_BURST_WIDTH(x)        _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_IO_CS_WIDTH           8
+#define M_IO_CS_WIDTH           _SB_MAKEMASK(5, S_IO_CS_WIDTH)
+#define V_IO_CS_WIDTH(x)        _SB_MAKEVALUE(x, S_IO_CS_WIDTH)
+#define G_IO_CS_WIDTH(x)        _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH)
+
+#define S_IO_RDY_SMPLE          13
+#define M_IO_RDY_SMPLE          _SB_MAKEMASK(3, S_IO_RDY_SMPLE)
+#define V_IO_RDY_SMPLE(x)       _SB_MAKEVALUE(x, S_IO_RDY_SMPLE)
+#define G_IO_RDY_SMPLE(x)       _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE)
+
+
+/*
+ * Generic Bus Timing 1 Registers (Table 11-8)
+ */
+
+#define S_IO_ALE_TO_WRITE       0
+#define M_IO_ALE_TO_WRITE       _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE)
+#define V_IO_ALE_TO_WRITE(x)    _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE)
+#define G_IO_ALE_TO_WRITE(x)    _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
+    || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_IO_RDY_SYNC           _SB_MAKEMASK1(3)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_IO_WRITE_WIDTH        4
+#define M_IO_WRITE_WIDTH        _SB_MAKEMASK(4, S_IO_WRITE_WIDTH)
+#define V_IO_WRITE_WIDTH(x)     _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH)
+#define G_IO_WRITE_WIDTH(x)     _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH)
+
+#define S_IO_IDLE_CYCLE         8
+#define M_IO_IDLE_CYCLE         _SB_MAKEMASK(4, S_IO_IDLE_CYCLE)
+#define V_IO_IDLE_CYCLE(x)      _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE)
+#define G_IO_IDLE_CYCLE(x)      _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE)
+
+#define S_IO_OE_TO_CS           12
+#define M_IO_OE_TO_CS           _SB_MAKEMASK(2, S_IO_OE_TO_CS)
+#define V_IO_OE_TO_CS(x)        _SB_MAKEVALUE(x, S_IO_OE_TO_CS)
+#define G_IO_OE_TO_CS(x)        _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS)
+
+#define S_IO_CS_TO_OE           14
+#define M_IO_CS_TO_OE           _SB_MAKEMASK(2, S_IO_CS_TO_OE)
+#define V_IO_CS_TO_OE(x)        _SB_MAKEVALUE(x, S_IO_CS_TO_OE)
+#define G_IO_CS_TO_OE(x)        _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE)
+
+/*
+ * Generic Bus Interrupt Status Register (Table 11-9)
+ */
+
+#define M_IO_CS_ERR_INT         _SB_MAKEMASK(0, 8)
+#define M_IO_CS0_ERR_INT        _SB_MAKEMASK1(0)
+#define M_IO_CS1_ERR_INT        _SB_MAKEMASK1(1)
+#define M_IO_CS2_ERR_INT        _SB_MAKEMASK1(2)
+#define M_IO_CS3_ERR_INT        _SB_MAKEMASK1(3)
+#define M_IO_CS4_ERR_INT        _SB_MAKEMASK1(4)
+#define M_IO_CS5_ERR_INT        _SB_MAKEMASK1(5)
+#define M_IO_CS6_ERR_INT        _SB_MAKEMASK1(6)
+#define M_IO_CS7_ERR_INT        _SB_MAKEMASK1(7)
+
+#define M_IO_RD_PAR_INT         _SB_MAKEMASK1(9)
+#define M_IO_TIMEOUT_INT        _SB_MAKEMASK1(10)
+#define M_IO_ILL_ADDR_INT       _SB_MAKEMASK1(11)
+#define M_IO_MULT_CS_INT        _SB_MAKEMASK1(12)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_IO_COH_ERR            _SB_MAKEMASK1(14)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+
+/*
+ * Generic Bus Output Drive Control Register 0 (Table 14-18)
+ */
+
+#define S_IO_SLEW0              0
+#define M_IO_SLEW0              _SB_MAKEMASK(2, S_IO_SLEW0)
+#define V_IO_SLEW0(x)           _SB_MAKEVALUE(x, S_IO_SLEW0)
+#define G_IO_SLEW0(x)           _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0)
+
+#define S_IO_DRV_A              2
+#define M_IO_DRV_A              _SB_MAKEMASK(2, S_IO_DRV_A)
+#define V_IO_DRV_A(x)           _SB_MAKEVALUE(x, S_IO_DRV_A)
+#define G_IO_DRV_A(x)           _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A)
+
+#define S_IO_DRV_B              6
+#define M_IO_DRV_B              _SB_MAKEMASK(2, S_IO_DRV_B)
+#define V_IO_DRV_B(x)           _SB_MAKEVALUE(x, S_IO_DRV_B)
+#define G_IO_DRV_B(x)           _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B)
+
+#define S_IO_DRV_C              10
+#define M_IO_DRV_C              _SB_MAKEMASK(2, S_IO_DRV_C)
+#define V_IO_DRV_C(x)           _SB_MAKEVALUE(x, S_IO_DRV_C)
+#define G_IO_DRV_C(x)           _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C)
+
+#define S_IO_DRV_D              14
+#define M_IO_DRV_D              _SB_MAKEMASK(2, S_IO_DRV_D)
+#define V_IO_DRV_D(x)           _SB_MAKEVALUE(x, S_IO_DRV_D)
+#define G_IO_DRV_D(x)           _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D)
+
+/*
+ * Generic Bus Output Drive Control Register 1 (Table 14-19)
+ */
+
+#define S_IO_DRV_E              2
+#define M_IO_DRV_E              _SB_MAKEMASK(2, S_IO_DRV_E)
+#define V_IO_DRV_E(x)           _SB_MAKEVALUE(x, S_IO_DRV_E)
+#define G_IO_DRV_E(x)           _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E)
+
+#define S_IO_DRV_F              6
+#define M_IO_DRV_F              _SB_MAKEMASK(2, S_IO_DRV_F)
+#define V_IO_DRV_F(x)           _SB_MAKEVALUE(x, S_IO_DRV_F)
+#define G_IO_DRV_F(x)           _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F)
+
+#define S_IO_SLEW1              8
+#define M_IO_SLEW1              _SB_MAKEMASK(2, S_IO_SLEW1)
+#define V_IO_SLEW1(x)           _SB_MAKEVALUE(x, S_IO_SLEW1)
+#define G_IO_SLEW1(x)           _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1)
+
+#define S_IO_DRV_G              10
+#define M_IO_DRV_G              _SB_MAKEMASK(2, S_IO_DRV_G)
+#define V_IO_DRV_G(x)           _SB_MAKEVALUE(x, S_IO_DRV_G)
+#define G_IO_DRV_G(x)           _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G)
+
+#define S_IO_SLEW2              12
+#define M_IO_SLEW2              _SB_MAKEMASK(2, S_IO_SLEW2)
+#define V_IO_SLEW2(x)           _SB_MAKEVALUE(x, S_IO_SLEW2)
+#define G_IO_SLEW2(x)           _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2)
+
+#define S_IO_DRV_H              14
+#define M_IO_DRV_H              _SB_MAKEMASK(2, S_IO_DRV_H)
+#define V_IO_DRV_H(x)           _SB_MAKEVALUE(x, S_IO_DRV_H)
+#define G_IO_DRV_H(x)           _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H)
+
+/*
+ * Generic Bus Output Drive Control Register 2 (Table 14-20)
+ */
+
+#define S_IO_DRV_J              2
+#define M_IO_DRV_J              _SB_MAKEMASK(2, S_IO_DRV_J)
+#define V_IO_DRV_J(x)           _SB_MAKEVALUE(x, S_IO_DRV_J)
+#define G_IO_DRV_J(x)           _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J)
+
+#define S_IO_DRV_K              6
+#define M_IO_DRV_K              _SB_MAKEMASK(2, S_IO_DRV_K)
+#define V_IO_DRV_K(x)           _SB_MAKEVALUE(x, S_IO_DRV_K)
+#define G_IO_DRV_K(x)           _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K)
+
+#define S_IO_DRV_L              10
+#define M_IO_DRV_L              _SB_MAKEMASK(2, S_IO_DRV_L)
+#define V_IO_DRV_L(x)           _SB_MAKEVALUE(x, S_IO_DRV_L)
+#define G_IO_DRV_L(x)           _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L)
+
+#define S_IO_DRV_M              14
+#define M_IO_DRV_M              _SB_MAKEMASK(2, S_IO_DRV_M)
+#define V_IO_DRV_M(x)           _SB_MAKEVALUE(x, S_IO_DRV_M)
+#define G_IO_DRV_M(x)           _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M)
+
+/*
+ * Generic Bus Output Drive Control Register 3 (Table 14-21)
+ */
+
+#define S_IO_SLEW3              0
+#define M_IO_SLEW3              _SB_MAKEMASK(2, S_IO_SLEW3)
+#define V_IO_SLEW3(x)           _SB_MAKEVALUE(x, S_IO_SLEW3)
+#define G_IO_SLEW3(x)           _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3)
+
+#define S_IO_DRV_N              2
+#define M_IO_DRV_N              _SB_MAKEMASK(2, S_IO_DRV_N)
+#define V_IO_DRV_N(x)           _SB_MAKEVALUE(x, S_IO_DRV_N)
+#define G_IO_DRV_N(x)           _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N)
+
+#define S_IO_DRV_P              6
+#define M_IO_DRV_P              _SB_MAKEMASK(2, S_IO_DRV_P)
+#define V_IO_DRV_P(x)           _SB_MAKEVALUE(x, S_IO_DRV_P)
+#define G_IO_DRV_P(x)           _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P)
+
+#define S_IO_DRV_Q              10
+#define M_IO_DRV_Q              _SB_MAKEMASK(2, S_IO_DRV_Q)
+#define V_IO_DRV_Q(x)           _SB_MAKEVALUE(x, S_IO_DRV_Q)
+#define G_IO_DRV_Q(x)           _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q)
+
+#define S_IO_DRV_R              14
+#define M_IO_DRV_R              _SB_MAKEMASK(2, S_IO_DRV_R)
+#define V_IO_DRV_R(x)           _SB_MAKEVALUE(x, S_IO_DRV_R)
+#define G_IO_DRV_R(x)           _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R)
+
+
+/*
+ * PCMCIA configuration register (Table 12-6)
+ */
+
+#define M_PCMCIA_CFG_ATTRMEM    _SB_MAKEMASK1(0)
+#define M_PCMCIA_CFG_3VEN       _SB_MAKEMASK1(1)
+#define M_PCMCIA_CFG_5VEN       _SB_MAKEMASK1(2)
+#define M_PCMCIA_CFG_VPPEN      _SB_MAKEMASK1(3)
+#define M_PCMCIA_CFG_RESET      _SB_MAKEMASK1(4)
+#define M_PCMCIA_CFG_APWRONEN   _SB_MAKEMASK1(5)
+#define M_PCMCIA_CFG_CDMASK     _SB_MAKEMASK1(6)
+#define M_PCMCIA_CFG_WPMASK     _SB_MAKEMASK1(7)
+#define M_PCMCIA_CFG_RDYMASK    _SB_MAKEMASK1(8)
+#define M_PCMCIA_CFG_PWRCTL     _SB_MAKEMASK1(9)
+
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_PCMCIA_MODE           16
+#define M_PCMCIA_MODE           _SB_MAKEMASK(3, S_PCMCIA_MODE)
+#define V_PCMCIA_MODE(x)        _SB_MAKEVALUE(x, S_PCMCIA_MODE)
+#define G_PCMCIA_MODE(x)        _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE)
+
+#define K_PCMCIA_MODE_PCMA_NOB  0       /* standard PCMCIA "A", no "B" */
+#define K_PCMCIA_MODE_IDEA_NOB  1       /* IDE "A", no "B" */
+#define K_PCMCIA_MODE_PCMIOA_NOB 2      /* PCMCIA with I/O "A", no "B" */
+#define K_PCMCIA_MODE_PCMA_PCMB 4       /* standard PCMCIA "A", standard PCMCIA "B" */
+#define K_PCMCIA_MODE_IDEA_PCMB 5       /* IDE "A", standard PCMCIA "B" */
+#define K_PCMCIA_MODE_PCMA_IDEB 6       /* standard PCMCIA "A", IDE "B" */
+#define K_PCMCIA_MODE_IDEA_IDEB 7       /* IDE "A", IDE "B" */
+#endif
+
+
+/*
+ * PCMCIA status register (Table 12-7)
+ */
+
+#define M_PCMCIA_STATUS_CD1     _SB_MAKEMASK1(0)
+#define M_PCMCIA_STATUS_CD2     _SB_MAKEMASK1(1)
+#define M_PCMCIA_STATUS_VS1     _SB_MAKEMASK1(2)
+#define M_PCMCIA_STATUS_VS2     _SB_MAKEMASK1(3)
+#define M_PCMCIA_STATUS_WP      _SB_MAKEMASK1(4)
+#define M_PCMCIA_STATUS_RDY     _SB_MAKEMASK1(5)
+#define M_PCMCIA_STATUS_3VEN    _SB_MAKEMASK1(6)
+#define M_PCMCIA_STATUS_5VEN    _SB_MAKEMASK1(7)
+#define M_PCMCIA_STATUS_CDCHG   _SB_MAKEMASK1(8)
+#define M_PCMCIA_STATUS_WPCHG   _SB_MAKEMASK1(9)
+#define M_PCMCIA_STATUS_RDYCHG  _SB_MAKEMASK1(10)
+
+/*
+ * GPIO Interrupt Type Register (table 13-3)
+ */
+
+#define K_GPIO_INTR_DISABLE     0
+#define K_GPIO_INTR_EDGE        1
+#define K_GPIO_INTR_LEVEL       2
+#define K_GPIO_INTR_SPLIT       3
+
+#define S_GPIO_INTR_TYPEX(n)    (((n)/2)*2)
+#define M_GPIO_INTR_TYPEX(n)    _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))
+#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
+#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))
+
+#define S_GPIO_INTR_TYPE0       0
+#define M_GPIO_INTR_TYPE0       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)
+#define V_GPIO_INTR_TYPE0(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0)
+#define G_GPIO_INTR_TYPE0(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0)
+
+#define S_GPIO_INTR_TYPE2       2
+#define M_GPIO_INTR_TYPE2       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2)
+#define V_GPIO_INTR_TYPE2(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2)
+#define G_GPIO_INTR_TYPE2(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2)
+
+#define S_GPIO_INTR_TYPE4       4
+#define M_GPIO_INTR_TYPE4       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4)
+#define V_GPIO_INTR_TYPE4(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4)
+#define G_GPIO_INTR_TYPE4(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4)
+
+#define S_GPIO_INTR_TYPE6       6
+#define M_GPIO_INTR_TYPE6       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6)
+#define V_GPIO_INTR_TYPE6(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6)
+#define G_GPIO_INTR_TYPE6(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6)
+
+#define S_GPIO_INTR_TYPE8       8
+#define M_GPIO_INTR_TYPE8       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8)
+#define V_GPIO_INTR_TYPE8(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8)
+#define G_GPIO_INTR_TYPE8(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8)
+
+#define S_GPIO_INTR_TYPE10      10
+#define M_GPIO_INTR_TYPE10      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10)
+#define V_GPIO_INTR_TYPE10(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10)
+#define G_GPIO_INTR_TYPE10(x)   _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10)
+
+#define S_GPIO_INTR_TYPE12      12
+#define M_GPIO_INTR_TYPE12      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12)
+#define V_GPIO_INTR_TYPE12(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12)
+#define G_GPIO_INTR_TYPE12(x)   _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12)
+
+#define S_GPIO_INTR_TYPE14      14
+#define M_GPIO_INTR_TYPE14      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14)
+#define V_GPIO_INTR_TYPE14(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14)
+#define G_GPIO_INTR_TYPE14(x)   _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14)
+
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+
+/*
+ * GPIO Interrupt Additional Type Register
+ */
+
+#define K_GPIO_INTR_BOTHEDGE    0
+#define K_GPIO_INTR_RISEEDGE    1
+#define K_GPIO_INTR_UNPRED1     2
+#define K_GPIO_INTR_UNPRED2     3
+
+#define S_GPIO_INTR_ATYPEX(n)   (((n)/2)*2)
+#define M_GPIO_INTR_ATYPEX(n)   _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n))
+#define V_GPIO_INTR_ATYPEX(n, x)        _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n))
+#define G_GPIO_INTR_ATYPEX(n, x)        _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n))
+
+#define S_GPIO_INTR_ATYPE0      0
+#define M_GPIO_INTR_ATYPE0      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0)
+#define V_GPIO_INTR_ATYPE0(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0)
+#define G_GPIO_INTR_ATYPE0(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0)
+
+#define S_GPIO_INTR_ATYPE2      2
+#define M_GPIO_INTR_ATYPE2      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2)
+#define V_GPIO_INTR_ATYPE2(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2)
+#define G_GPIO_INTR_ATYPE2(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2)
+
+#define S_GPIO_INTR_ATYPE4      4
+#define M_GPIO_INTR_ATYPE4      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4)
+#define V_GPIO_INTR_ATYPE4(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4)
+#define G_GPIO_INTR_ATYPE4(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4)
+
+#define S_GPIO_INTR_ATYPE6      6
+#define M_GPIO_INTR_ATYPE6      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6)
+#define V_GPIO_INTR_ATYPE6(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6)
+#define G_GPIO_INTR_ATYPE6(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6)
+
+#define S_GPIO_INTR_ATYPE8      8
+#define M_GPIO_INTR_ATYPE8      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8)
+#define V_GPIO_INTR_ATYPE8(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8)
+#define G_GPIO_INTR_ATYPE8(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8)
+
+#define S_GPIO_INTR_ATYPE10     10
+#define M_GPIO_INTR_ATYPE10     _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10)
+#define V_GPIO_INTR_ATYPE10(x)  _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10)
+#define G_GPIO_INTR_ATYPE10(x)  _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10)
+
+#define S_GPIO_INTR_ATYPE12     12
+#define M_GPIO_INTR_ATYPE12     _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12)
+#define V_GPIO_INTR_ATYPE12(x)  _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12)
+#define G_GPIO_INTR_ATYPE12(x)  _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12)
+
+#define S_GPIO_INTR_ATYPE14     14
+#define M_GPIO_INTR_ATYPE14     _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14)
+#define V_GPIO_INTR_ATYPE14(x)  _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14)
+#define G_GPIO_INTR_ATYPE14(x)  _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14)
+#endif
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_int.h b/arch/mips/include/asm/sibyte/sb1250_int.h
new file mode 100644
index 000000000000..f2850b4bcfd4
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_int.h
@@ -0,0 +1,248 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Interrupt Mapper definitions             File: sb1250_int.h
+    *
+    *  This module contains constants for manipulating the SB1250's
+    *  interrupt mapper and definitions for the interrupt sources.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000, 2001, 2002, 2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_INT_H
+#define _SB1250_INT_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Interrupt Mapper Constants
+    ********************************************************************* */
+
+/*
+ * Interrupt sources (Table 4-8, UM 0.2)
+ *
+ * First, the interrupt numbers.
+ */
+
+#define K_INT_SOURCES               64
+
+#define K_INT_WATCHDOG_TIMER_0      0
+#define K_INT_WATCHDOG_TIMER_1      1
+#define K_INT_TIMER_0               2
+#define K_INT_TIMER_1               3
+#define K_INT_TIMER_2               4
+#define K_INT_TIMER_3               5
+#define K_INT_SMB_0                 6
+#define K_INT_SMB_1                 7
+#define K_INT_UART_0                8
+#define K_INT_UART_1                9
+#define K_INT_SER_0                 10
+#define K_INT_SER_1                 11
+#define K_INT_PCMCIA                12
+#define K_INT_ADDR_TRAP             13
+#define K_INT_PERF_CNT              14
+#define K_INT_TRACE_FREEZE          15
+#define K_INT_BAD_ECC               16
+#define K_INT_COR_ECC               17
+#define K_INT_IO_BUS                18
+#define K_INT_MAC_0                 19
+#define K_INT_MAC_1                 20
+#define K_INT_MAC_2                 21
+#define K_INT_DM_CH_0               22
+#define K_INT_DM_CH_1               23
+#define K_INT_DM_CH_2               24
+#define K_INT_DM_CH_3               25
+#define K_INT_MBOX_0                26
+#define K_INT_MBOX_1                27
+#define K_INT_MBOX_2                28
+#define K_INT_MBOX_3                29
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define K_INT_CYCLE_CP0_INT         30
+#define K_INT_CYCLE_CP1_INT         31
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define K_INT_GPIO_0                32
+#define K_INT_GPIO_1                33
+#define K_INT_GPIO_2                34
+#define K_INT_GPIO_3                35
+#define K_INT_GPIO_4                36
+#define K_INT_GPIO_5                37
+#define K_INT_GPIO_6                38
+#define K_INT_GPIO_7                39
+#define K_INT_GPIO_8                40
+#define K_INT_GPIO_9                41
+#define K_INT_GPIO_10               42
+#define K_INT_GPIO_11               43
+#define K_INT_GPIO_12               44
+#define K_INT_GPIO_13               45
+#define K_INT_GPIO_14               46
+#define K_INT_GPIO_15               47
+#define K_INT_LDT_FATAL             48
+#define K_INT_LDT_NONFATAL          49
+#define K_INT_LDT_SMI               50
+#define K_INT_LDT_NMI               51
+#define K_INT_LDT_INIT              52
+#define K_INT_LDT_STARTUP           53
+#define K_INT_LDT_EXT               54
+#define K_INT_PCI_ERROR             55
+#define K_INT_PCI_INTA              56
+#define K_INT_PCI_INTB              57
+#define K_INT_PCI_INTC              58
+#define K_INT_PCI_INTD              59
+#define K_INT_SPARE_2               60
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define K_INT_MAC_0_CH1             61
+#define K_INT_MAC_1_CH1             62
+#define K_INT_MAC_2_CH1             63
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/*
+ * Mask values for each interrupt
+ */
+
+#define M_INT_WATCHDOG_TIMER_0      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
+#define M_INT_WATCHDOG_TIMER_1      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
+#define M_INT_TIMER_0               _SB_MAKEMASK1(K_INT_TIMER_0)
+#define M_INT_TIMER_1               _SB_MAKEMASK1(K_INT_TIMER_1)
+#define M_INT_TIMER_2               _SB_MAKEMASK1(K_INT_TIMER_2)
+#define M_INT_TIMER_3               _SB_MAKEMASK1(K_INT_TIMER_3)
+#define M_INT_SMB_0                 _SB_MAKEMASK1(K_INT_SMB_0)
+#define M_INT_SMB_1                 _SB_MAKEMASK1(K_INT_SMB_1)
+#define M_INT_UART_0                _SB_MAKEMASK1(K_INT_UART_0)
+#define M_INT_UART_1                _SB_MAKEMASK1(K_INT_UART_1)
+#define M_INT_SER_0                 _SB_MAKEMASK1(K_INT_SER_0)
+#define M_INT_SER_1                 _SB_MAKEMASK1(K_INT_SER_1)
+#define M_INT_PCMCIA                _SB_MAKEMASK1(K_INT_PCMCIA)
+#define M_INT_ADDR_TRAP             _SB_MAKEMASK1(K_INT_ADDR_TRAP)
+#define M_INT_PERF_CNT              _SB_MAKEMASK1(K_INT_PERF_CNT)
+#define M_INT_TRACE_FREEZE          _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
+#define M_INT_BAD_ECC               _SB_MAKEMASK1(K_INT_BAD_ECC)
+#define M_INT_COR_ECC               _SB_MAKEMASK1(K_INT_COR_ECC)
+#define M_INT_IO_BUS                _SB_MAKEMASK1(K_INT_IO_BUS)
+#define M_INT_MAC_0                 _SB_MAKEMASK1(K_INT_MAC_0)
+#define M_INT_MAC_1                 _SB_MAKEMASK1(K_INT_MAC_1)
+#define M_INT_MAC_2                 _SB_MAKEMASK1(K_INT_MAC_2)
+#define M_INT_DM_CH_0               _SB_MAKEMASK1(K_INT_DM_CH_0)
+#define M_INT_DM_CH_1               _SB_MAKEMASK1(K_INT_DM_CH_1)
+#define M_INT_DM_CH_2               _SB_MAKEMASK1(K_INT_DM_CH_2)
+#define M_INT_DM_CH_3               _SB_MAKEMASK1(K_INT_DM_CH_3)
+#define M_INT_MBOX_0                _SB_MAKEMASK1(K_INT_MBOX_0)
+#define M_INT_MBOX_1                _SB_MAKEMASK1(K_INT_MBOX_1)
+#define M_INT_MBOX_2                _SB_MAKEMASK1(K_INT_MBOX_2)
+#define M_INT_MBOX_3                _SB_MAKEMASK1(K_INT_MBOX_3)
+#define M_INT_MBOX_ALL              _SB_MAKEMASK(4, K_INT_MBOX_0)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_INT_CYCLE_CP0_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
+#define M_INT_CYCLE_CP1_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define M_INT_GPIO_0                _SB_MAKEMASK1(K_INT_GPIO_0)
+#define M_INT_GPIO_1                _SB_MAKEMASK1(K_INT_GPIO_1)
+#define M_INT_GPIO_2                _SB_MAKEMASK1(K_INT_GPIO_2)
+#define M_INT_GPIO_3                _SB_MAKEMASK1(K_INT_GPIO_3)
+#define M_INT_GPIO_4                _SB_MAKEMASK1(K_INT_GPIO_4)
+#define M_INT_GPIO_5                _SB_MAKEMASK1(K_INT_GPIO_5)
+#define M_INT_GPIO_6                _SB_MAKEMASK1(K_INT_GPIO_6)
+#define M_INT_GPIO_7                _SB_MAKEMASK1(K_INT_GPIO_7)
+#define M_INT_GPIO_8                _SB_MAKEMASK1(K_INT_GPIO_8)
+#define M_INT_GPIO_9                _SB_MAKEMASK1(K_INT_GPIO_9)
+#define M_INT_GPIO_10               _SB_MAKEMASK1(K_INT_GPIO_10)
+#define M_INT_GPIO_11               _SB_MAKEMASK1(K_INT_GPIO_11)
+#define M_INT_GPIO_12               _SB_MAKEMASK1(K_INT_GPIO_12)
+#define M_INT_GPIO_13               _SB_MAKEMASK1(K_INT_GPIO_13)
+#define M_INT_GPIO_14               _SB_MAKEMASK1(K_INT_GPIO_14)
+#define M_INT_GPIO_15               _SB_MAKEMASK1(K_INT_GPIO_15)
+#define M_INT_LDT_FATAL             _SB_MAKEMASK1(K_INT_LDT_FATAL)
+#define M_INT_LDT_NONFATAL          _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
+#define M_INT_LDT_SMI               _SB_MAKEMASK1(K_INT_LDT_SMI)
+#define M_INT_LDT_NMI               _SB_MAKEMASK1(K_INT_LDT_NMI)
+#define M_INT_LDT_INIT              _SB_MAKEMASK1(K_INT_LDT_INIT)
+#define M_INT_LDT_STARTUP           _SB_MAKEMASK1(K_INT_LDT_STARTUP)
+#define M_INT_LDT_EXT               _SB_MAKEMASK1(K_INT_LDT_EXT)
+#define M_INT_PCI_ERROR             _SB_MAKEMASK1(K_INT_PCI_ERROR)
+#define M_INT_PCI_INTA              _SB_MAKEMASK1(K_INT_PCI_INTA)
+#define M_INT_PCI_INTB              _SB_MAKEMASK1(K_INT_PCI_INTB)
+#define M_INT_PCI_INTC              _SB_MAKEMASK1(K_INT_PCI_INTC)
+#define M_INT_PCI_INTD              _SB_MAKEMASK1(K_INT_PCI_INTD)
+#define M_INT_SPARE_2               _SB_MAKEMASK1(K_INT_SPARE_2)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_INT_MAC_0_CH1             _SB_MAKEMASK1(K_INT_MAC_0_CH1)
+#define M_INT_MAC_1_CH1             _SB_MAKEMASK1(K_INT_MAC_1_CH1)
+#define M_INT_MAC_2_CH1             _SB_MAKEMASK1(K_INT_MAC_2_CH1)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/*
+ * Interrupt mappings
+ */
+
+#define K_INT_MAP_I0    0               /* interrupt pins on processor */
+#define K_INT_MAP_I1    1
+#define K_INT_MAP_I2    2
+#define K_INT_MAP_I3    3
+#define K_INT_MAP_I4    4
+#define K_INT_MAP_I5    5
+#define K_INT_MAP_NMI   6               /* nonmaskable */
+#define K_INT_MAP_DINT  7               /* debug interrupt */
+
+/*
+ * LDT Interrupt Set Register (table 4-5)
+ */
+
+#define S_INT_LDT_INTMSG              0
+#define M_INT_LDT_INTMSG              _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
+#define V_INT_LDT_INTMSG(x)           _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
+#define G_INT_LDT_INTMSG(x)           _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)
+
+#define K_INT_LDT_INTMSG_FIXED        0
+#define K_INT_LDT_INTMSG_ARBITRATED   1
+#define K_INT_LDT_INTMSG_SMI          2
+#define K_INT_LDT_INTMSG_NMI          3
+#define K_INT_LDT_INTMSG_INIT         4
+#define K_INT_LDT_INTMSG_STARTUP      5
+#define K_INT_LDT_INTMSG_EXTINT       6
+#define K_INT_LDT_INTMSG_RESERVED     7
+
+#define M_INT_LDT_EDGETRIGGER         0
+#define M_INT_LDT_LEVELTRIGGER        _SB_MAKEMASK1(3)
+
+#define M_INT_LDT_PHYSICALDEST        0
+#define M_INT_LDT_LOGICALDEST         _SB_MAKEMASK1(4)
+
+#define S_INT_LDT_INTDEST             5
+#define M_INT_LDT_INTDEST             _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
+#define V_INT_LDT_INTDEST(x)          _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
+#define G_INT_LDT_INTDEST(x)          _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)
+
+#define S_INT_LDT_VECTOR              13
+#define M_INT_LDT_VECTOR              _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
+#define V_INT_LDT_VECTOR(x)           _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
+#define G_INT_LDT_VECTOR(x)           _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)
+
+/*
+ * Vector format (Table 4-6)
+ */
+
+#define M_LDTVECT_RAISEINT              0x00
+#define M_LDTVECT_RAISEMBOX             0x40
+
+
+#endif  /* 1250/112x */
diff --git a/arch/mips/include/asm/sibyte/sb1250_l2c.h b/arch/mips/include/asm/sibyte/sb1250_l2c.h
new file mode 100644
index 000000000000..6554dcf05cfe
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_l2c.h
@@ -0,0 +1,131 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  L2 Cache constants and macros            File: sb1250_l2c.h
+    *
+    *  This module contains constants useful for manipulating the
+    *  level 2 cache.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_L2C_H
+#define _SB1250_L2C_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Level 2 Cache Tag register (Table 5-3)
+ */
+
+#define S_L2C_TAG_MBZ               0
+#define M_L2C_TAG_MBZ               _SB_MAKEMASK(5, S_L2C_TAG_MBZ)
+
+#define S_L2C_TAG_INDEX             5
+#define M_L2C_TAG_INDEX             _SB_MAKEMASK(12, S_L2C_TAG_INDEX)
+#define V_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x, S_L2C_TAG_INDEX)
+#define G_L2C_TAG_INDEX(x)          _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX)
+
+#define S_L2C_TAG_TAG               17
+#define M_L2C_TAG_TAG               _SB_MAKEMASK(23, S_L2C_TAG_TAG)
+#define V_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x, S_L2C_TAG_TAG)
+#define G_L2C_TAG_TAG(x)            _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG)
+
+#define S_L2C_TAG_ECC               40
+#define M_L2C_TAG_ECC               _SB_MAKEMASK(6, S_L2C_TAG_ECC)
+#define V_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x, S_L2C_TAG_ECC)
+#define G_L2C_TAG_ECC(x)            _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC)
+
+#define S_L2C_TAG_WAY               46
+#define M_L2C_TAG_WAY               _SB_MAKEMASK(2, S_L2C_TAG_WAY)
+#define V_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x, S_L2C_TAG_WAY)
+#define G_L2C_TAG_WAY(x)            _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY)
+
+#define M_L2C_TAG_DIRTY             _SB_MAKEMASK1(48)
+#define M_L2C_TAG_VALID             _SB_MAKEMASK1(49)
+
+/*
+ * Format of level 2 cache management address (table 5-2)
+ */
+
+#define S_L2C_MGMT_INDEX            5
+#define M_L2C_MGMT_INDEX            _SB_MAKEMASK(12, S_L2C_MGMT_INDEX)
+#define V_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX)
+#define G_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX)
+
+#define S_L2C_MGMT_QUADRANT         15
+#define M_L2C_MGMT_QUADRANT         _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT)
+#define V_L2C_MGMT_QUADRANT(x)      _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT)
+#define G_L2C_MGMT_QUADRANT(x)      _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT)
+
+#define S_L2C_MGMT_HALF             16
+#define M_L2C_MGMT_HALF             _SB_MAKEMASK(1, S_L2C_MGMT_HALF)
+
+#define S_L2C_MGMT_WAY              17
+#define M_L2C_MGMT_WAY              _SB_MAKEMASK(2, S_L2C_MGMT_WAY)
+#define V_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x, S_L2C_MGMT_WAY)
+#define G_L2C_MGMT_WAY(x)           _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY)
+
+#define S_L2C_MGMT_ECC_DIAG         21
+#define M_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG)
+#define V_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG)
+#define G_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG)
+
+#define S_L2C_MGMT_TAG              23
+#define M_L2C_MGMT_TAG              _SB_MAKEMASK(4, S_L2C_MGMT_TAG)
+#define V_L2C_MGMT_TAG(x)           _SB_MAKEVALUE(x, S_L2C_MGMT_TAG)
+#define G_L2C_MGMT_TAG(x)           _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG)
+
+#define M_L2C_MGMT_DIRTY            _SB_MAKEMASK1(19)
+#define M_L2C_MGMT_VALID            _SB_MAKEMASK1(20)
+
+#define A_L2C_MGMT_TAG_BASE         0x00D0000000
+
+#define L2C_ENTRIES_PER_WAY       4096
+#define L2C_NUM_WAYS              4
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/*
+ * L2 Read Misc. register (A_L2_READ_MISC)
+ */
+#define S_L2C_MISC_NO_WAY               10
+#define M_L2C_MISC_NO_WAY               _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY)
+#define V_L2C_MISC_NO_WAY(x)            _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY)
+#define G_L2C_MISC_NO_WAY(x)            _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY)
+
+#define M_L2C_MISC_ECC_CLEANUP_DIS      _SB_MAKEMASK1(9)
+#define M_L2C_MISC_MC_PRIO_LOW          _SB_MAKEMASK1(8)
+#define M_L2C_MISC_SOFT_DISABLE_T       _SB_MAKEMASK1(7)
+#define M_L2C_MISC_SOFT_DISABLE_B       _SB_MAKEMASK1(6)
+#define M_L2C_MISC_SOFT_DISABLE_R       _SB_MAKEMASK1(5)
+#define M_L2C_MISC_SOFT_DISABLE_L       _SB_MAKEMASK1(4)
+#define M_L2C_MISC_SCACHE_DISABLE_T     _SB_MAKEMASK1(3)
+#define M_L2C_MISC_SCACHE_DISABLE_B     _SB_MAKEMASK1(2)
+#define M_L2C_MISC_SCACHE_DISABLE_R     _SB_MAKEMASK1(1)
+#define M_L2C_MISC_SCACHE_DISABLE_L     _SB_MAKEMASK1(0)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h
new file mode 100644
index 000000000000..081e8b1c4ad0
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h
@@ -0,0 +1,423 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  LDT constants                            File: sb1250_ldt.h
+    *
+    *  This module contains constants and macros to describe
+    *  the LDT interface on the SB1250.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000, 2001, 2002, 2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_LDT_H
+#define _SB1250_LDT_H
+
+#include "sb1250_defs.h"
+
+#define K_LDT_VENDOR_SIBYTE     0x166D
+#define K_LDT_DEVICE_SB1250     0x0002
+
+/*
+ * LDT Interface Type 1 (bridge) configuration header
+ */
+
+#define R_LDT_TYPE1_DEVICEID    0x0000
+#define R_LDT_TYPE1_CMDSTATUS   0x0004
+#define R_LDT_TYPE1_CLASSREV    0x0008
+#define R_LDT_TYPE1_DEVHDR      0x000C
+#define R_LDT_TYPE1_BAR0        0x0010  /* not used */
+#define R_LDT_TYPE1_BAR1        0x0014  /* not used */
+
+#define R_LDT_TYPE1_BUSID       0x0018  /* bus ID register */
+#define R_LDT_TYPE1_SECSTATUS   0x001C  /* secondary status / I/O base/limit */
+#define R_LDT_TYPE1_MEMLIMIT    0x0020
+#define R_LDT_TYPE1_PREFETCH    0x0024
+#define R_LDT_TYPE1_PREF_BASE   0x0028
+#define R_LDT_TYPE1_PREF_LIMIT  0x002C
+#define R_LDT_TYPE1_IOLIMIT     0x0030
+#define R_LDT_TYPE1_CAPPTR      0x0034
+#define R_LDT_TYPE1_ROMADDR     0x0038
+#define R_LDT_TYPE1_BRCTL       0x003C
+#define R_LDT_TYPE1_CMD         0x0040
+#define R_LDT_TYPE1_LINKCTRL    0x0044
+#define R_LDT_TYPE1_LINKFREQ    0x0048
+#define R_LDT_TYPE1_RESERVED1   0x004C
+#define R_LDT_TYPE1_SRICMD      0x0050
+#define R_LDT_TYPE1_SRITXNUM    0x0054
+#define R_LDT_TYPE1_SRIRXNUM    0x0058
+#define R_LDT_TYPE1_ERRSTATUS   0x0068
+#define R_LDT_TYPE1_SRICTRL     0x006C
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define R_LDT_TYPE1_ADDSTATUS   0x0070
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define R_LDT_TYPE1_TXBUFCNT    0x00C8
+#define R_LDT_TYPE1_EXPCRC      0x00DC
+#define R_LDT_TYPE1_RXCRC       0x00F0
+
+
+/*
+ * LDT Device ID register
+ */
+
+#define S_LDT_DEVICEID_VENDOR           0
+#define M_LDT_DEVICEID_VENDOR           _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR)
+#define V_LDT_DEVICEID_VENDOR(x)        _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR)
+#define G_LDT_DEVICEID_VENDOR(x)        _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR)
+
+#define S_LDT_DEVICEID_DEVICEID         16
+#define M_LDT_DEVICEID_DEVICEID         _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID)
+#define V_LDT_DEVICEID_DEVICEID(x)      _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID)
+#define G_LDT_DEVICEID_DEVICEID(x)      _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID)
+
+
+/*
+ * LDT Command Register (Table 8-13)
+ */
+
+#define M_LDT_CMD_IOSPACE_EN            _SB_MAKEMASK1_32(0)
+#define M_LDT_CMD_MEMSPACE_EN           _SB_MAKEMASK1_32(1)
+#define M_LDT_CMD_MASTER_EN             _SB_MAKEMASK1_32(2)
+#define M_LDT_CMD_SPECCYC_EN            _SB_MAKEMASK1_32(3)
+#define M_LDT_CMD_MEMWRINV_EN           _SB_MAKEMASK1_32(4)
+#define M_LDT_CMD_VGAPALSNP_EN          _SB_MAKEMASK1_32(5)
+#define M_LDT_CMD_PARERRRESP            _SB_MAKEMASK1_32(6)
+#define M_LDT_CMD_WAITCYCCTRL           _SB_MAKEMASK1_32(7)
+#define M_LDT_CMD_SERR_EN               _SB_MAKEMASK1_32(8)
+#define M_LDT_CMD_FASTB2B_EN            _SB_MAKEMASK1_32(9)
+
+/*
+ * LDT class and revision registers
+ */
+
+#define S_LDT_CLASSREV_REV              0
+#define M_LDT_CLASSREV_REV              _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV)
+#define V_LDT_CLASSREV_REV(x)           _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV)
+#define G_LDT_CLASSREV_REV(x)           _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV)
+
+#define S_LDT_CLASSREV_CLASS            8
+#define M_LDT_CLASSREV_CLASS            _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS)
+#define V_LDT_CLASSREV_CLASS(x)         _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS)
+#define G_LDT_CLASSREV_CLASS(x)         _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS)
+
+#define K_LDT_REV                       0x01
+#define K_LDT_CLASS                     0x060000
+
+/*
+ * Device Header (offset 0x0C)
+ */
+
+#define S_LDT_DEVHDR_CLINESZ            0
+#define M_LDT_DEVHDR_CLINESZ            _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ)
+#define V_LDT_DEVHDR_CLINESZ(x)         _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ)
+#define G_LDT_DEVHDR_CLINESZ(x)         _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ)
+
+#define S_LDT_DEVHDR_LATTMR             8
+#define M_LDT_DEVHDR_LATTMR             _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR)
+#define V_LDT_DEVHDR_LATTMR(x)          _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR)
+#define G_LDT_DEVHDR_LATTMR(x)          _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR)
+
+#define S_LDT_DEVHDR_HDRTYPE            16
+#define M_LDT_DEVHDR_HDRTYPE            _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE)
+#define V_LDT_DEVHDR_HDRTYPE(x)         _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE)
+#define G_LDT_DEVHDR_HDRTYPE(x)         _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE)
+
+#define K_LDT_DEVHDR_HDRTYPE_TYPE1      1
+
+#define S_LDT_DEVHDR_BIST               24
+#define M_LDT_DEVHDR_BIST               _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST)
+#define V_LDT_DEVHDR_BIST(x)            _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST)
+#define G_LDT_DEVHDR_BIST(x)            _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST)
+
+
+
+/*
+ * LDT Status Register (Table 8-14).  Note that these constants
+ * assume you've read the command and status register
+ * together (32-bit read at offset 0x04)
+ *
+ * These bits also apply to the secondary status
+ * register (Table 8-15), offset 0x1C
+ */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_LDT_STATUS_VGAEN              _SB_MAKEMASK1_32(3)
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define M_LDT_STATUS_CAPLIST            _SB_MAKEMASK1_32(20)
+#define M_LDT_STATUS_66MHZCAP           _SB_MAKEMASK1_32(21)
+#define M_LDT_STATUS_RESERVED2          _SB_MAKEMASK1_32(22)
+#define M_LDT_STATUS_FASTB2BCAP         _SB_MAKEMASK1_32(23)
+#define M_LDT_STATUS_MSTRDPARERR        _SB_MAKEMASK1_32(24)
+
+#define S_LDT_STATUS_DEVSELTIMING       25
+#define M_LDT_STATUS_DEVSELTIMING       _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING)
+#define V_LDT_STATUS_DEVSELTIMING(x)    _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING)
+#define G_LDT_STATUS_DEVSELTIMING(x)    _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING)
+
+#define M_LDT_STATUS_SIGDTGTABORT       _SB_MAKEMASK1_32(27)
+#define M_LDT_STATUS_RCVDTGTABORT       _SB_MAKEMASK1_32(28)
+#define M_LDT_STATUS_RCVDMSTRABORT      _SB_MAKEMASK1_32(29)
+#define M_LDT_STATUS_SIGDSERR           _SB_MAKEMASK1_32(30)
+#define M_LDT_STATUS_DETPARERR          _SB_MAKEMASK1_32(31)
+
+/*
+ * Bridge Control Register (Table 8-16).  Note that these
+ * constants assume you've read the register as a 32-bit
+ * read (offset 0x3C)
+ */
+
+#define M_LDT_BRCTL_PARERRRESP_EN       _SB_MAKEMASK1_32(16)
+#define M_LDT_BRCTL_SERR_EN             _SB_MAKEMASK1_32(17)
+#define M_LDT_BRCTL_ISA_EN              _SB_MAKEMASK1_32(18)
+#define M_LDT_BRCTL_VGA_EN              _SB_MAKEMASK1_32(19)
+#define M_LDT_BRCTL_MSTRABORTMODE       _SB_MAKEMASK1_32(21)
+#define M_LDT_BRCTL_SECBUSRESET         _SB_MAKEMASK1_32(22)
+#define M_LDT_BRCTL_FASTB2B_EN          _SB_MAKEMASK1_32(23)
+#define M_LDT_BRCTL_PRIDISCARD          _SB_MAKEMASK1_32(24)
+#define M_LDT_BRCTL_SECDISCARD          _SB_MAKEMASK1_32(25)
+#define M_LDT_BRCTL_DISCARDSTAT         _SB_MAKEMASK1_32(26)
+#define M_LDT_BRCTL_DISCARDSERR_EN      _SB_MAKEMASK1_32(27)
+
+/*
+ * LDT Command Register (Table 8-17).  Note that these constants
+ * assume you've read the command and status register together
+ * 32-bit read at offset 0x40
+ */
+
+#define M_LDT_CMD_WARMRESET             _SB_MAKEMASK1_32(16)
+#define M_LDT_CMD_DOUBLEENDED           _SB_MAKEMASK1_32(17)
+
+#define S_LDT_CMD_CAPTYPE               29
+#define M_LDT_CMD_CAPTYPE               _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE)
+#define V_LDT_CMD_CAPTYPE(x)            _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE)
+#define G_LDT_CMD_CAPTYPE(x)            _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE)
+
+/*
+ * LDT link control register (Table 8-18), and (Table 8-19)
+ */
+
+#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN  _SB_MAKEMASK1_32(1)
+#define M_LDT_LINKCTRL_CRCSTARTTEST     _SB_MAKEMASK1_32(2)
+#define M_LDT_LINKCTRL_CRCFORCEERR      _SB_MAKEMASK1_32(3)
+#define M_LDT_LINKCTRL_LINKFAIL         _SB_MAKEMASK1_32(4)
+#define M_LDT_LINKCTRL_INITDONE         _SB_MAKEMASK1_32(5)
+#define M_LDT_LINKCTRL_EOC              _SB_MAKEMASK1_32(6)
+#define M_LDT_LINKCTRL_XMITOFF          _SB_MAKEMASK1_32(7)
+
+#define S_LDT_LINKCTRL_CRCERR           8
+#define M_LDT_LINKCTRL_CRCERR           _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR)
+#define V_LDT_LINKCTRL_CRCERR(x)        _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR)
+#define G_LDT_LINKCTRL_CRCERR(x)        _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR)
+
+#define S_LDT_LINKCTRL_MAXIN            16
+#define M_LDT_LINKCTRL_MAXIN            _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN)
+#define V_LDT_LINKCTRL_MAXIN(x)         _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN)
+#define G_LDT_LINKCTRL_MAXIN(x)         _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN)
+
+#define M_LDT_LINKCTRL_DWFCLN           _SB_MAKEMASK1_32(19)
+
+#define S_LDT_LINKCTRL_MAXOUT           20
+#define M_LDT_LINKCTRL_MAXOUT           _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT)
+#define V_LDT_LINKCTRL_MAXOUT(x)        _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT)
+#define G_LDT_LINKCTRL_MAXOUT(x)        _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT)
+
+#define M_LDT_LINKCTRL_DWFCOUT          _SB_MAKEMASK1_32(23)
+
+#define S_LDT_LINKCTRL_WIDTHIN          24
+#define M_LDT_LINKCTRL_WIDTHIN          _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN)
+#define V_LDT_LINKCTRL_WIDTHIN(x)       _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN)
+#define G_LDT_LINKCTRL_WIDTHIN(x)       _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN)
+
+#define M_LDT_LINKCTRL_DWFCLIN_EN       _SB_MAKEMASK1_32(27)
+
+#define S_LDT_LINKCTRL_WIDTHOUT         28
+#define M_LDT_LINKCTRL_WIDTHOUT         _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT)
+#define V_LDT_LINKCTRL_WIDTHOUT(x)      _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT)
+#define G_LDT_LINKCTRL_WIDTHOUT(x)      _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT)
+
+#define M_LDT_LINKCTRL_DWFCOUT_EN       _SB_MAKEMASK1_32(31)
+
+/*
+ * LDT Link frequency register  (Table 8-20) offset 0x48
+ */
+
+#define S_LDT_LINKFREQ_FREQ             8
+#define M_LDT_LINKFREQ_FREQ             _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ)
+#define V_LDT_LINKFREQ_FREQ(x)          _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ)
+#define G_LDT_LINKFREQ_FREQ(x)          _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ)
+
+#define K_LDT_LINKFREQ_200MHZ           0
+#define K_LDT_LINKFREQ_300MHZ           1
+#define K_LDT_LINKFREQ_400MHZ           2
+#define K_LDT_LINKFREQ_500MHZ           3
+#define K_LDT_LINKFREQ_600MHZ           4
+#define K_LDT_LINKFREQ_800MHZ           5
+#define K_LDT_LINKFREQ_1000MHZ          6
+
+/*
+ * LDT SRI Command Register (Table 8-21).  Note that these constants
+ * assume you've read the command and status register together
+ * 32-bit read at offset 0x50
+ */
+
+#define M_LDT_SRICMD_SIPREADY           _SB_MAKEMASK1_32(16)
+#define M_LDT_SRICMD_SYNCPTRCTL         _SB_MAKEMASK1_32(17)
+#define M_LDT_SRICMD_REDUCESYNCZERO     _SB_MAKEMASK1_32(18)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+#define M_LDT_SRICMD_DISSTARVATIONCNT   _SB_MAKEMASK1_32(19)    /* PASS1 */
+#endif /* up to 1250 PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_LDT_SRICMD_DISMULTTXVLD       _SB_MAKEMASK1_32(19)
+#define M_LDT_SRICMD_EXPENDIAN          _SB_MAKEMASK1_32(26)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+#define S_LDT_SRICMD_RXMARGIN           20
+#define M_LDT_SRICMD_RXMARGIN           _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN)
+#define V_LDT_SRICMD_RXMARGIN(x)        _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN)
+#define G_LDT_SRICMD_RXMARGIN(x)        _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN)
+
+#define M_LDT_SRICMD_LDTPLLCOMPAT       _SB_MAKEMASK1_32(25)
+
+#define S_LDT_SRICMD_TXINITIALOFFSET    28
+#define M_LDT_SRICMD_TXINITIALOFFSET    _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)
+#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
+#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)
+
+#define M_LDT_SRICMD_LINKFREQDIRECT     _SB_MAKEMASK1_32(31)
+
+/*
+ * LDT Error control and status register (Table 8-22) (Table 8-23)
+ */
+
+#define M_LDT_ERRCTL_PROTFATAL_EN       _SB_MAKEMASK1_32(0)
+#define M_LDT_ERRCTL_PROTNONFATAL_EN    _SB_MAKEMASK1_32(1)
+#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN   _SB_MAKEMASK1_32(2)
+#define M_LDT_ERRCTL_OVFFATAL_EN        _SB_MAKEMASK1_32(3)
+#define M_LDT_ERRCTL_OVFNONFATAL_EN     _SB_MAKEMASK1_32(4)
+#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN    _SB_MAKEMASK1_32(5)
+#define M_LDT_ERRCTL_EOCNXAFATAL_EN     _SB_MAKEMASK1_32(6)
+#define M_LDT_ERRCTL_EOCNXANONFATAL_EN  _SB_MAKEMASK1_32(7)
+#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
+#define M_LDT_ERRCTL_CRCFATAL_EN        _SB_MAKEMASK1_32(9)
+#define M_LDT_ERRCTL_CRCNONFATAL_EN     _SB_MAKEMASK1_32(10)
+#define M_LDT_ERRCTL_SERRFATAL_EN       _SB_MAKEMASK1_32(11)
+#define M_LDT_ERRCTL_SRCTAGFATAL_EN     _SB_MAKEMASK1_32(12)
+#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN  _SB_MAKEMASK1_32(13)
+#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
+#define M_LDT_ERRCTL_MAPNXAFATAL_EN     _SB_MAKEMASK1_32(15)
+#define M_LDT_ERRCTL_MAPNXANONFATAL_EN  _SB_MAKEMASK1_32(16)
+#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
+
+#define M_LDT_ERRCTL_PROTOERR           _SB_MAKEMASK1_32(24)
+#define M_LDT_ERRCTL_OVFERR             _SB_MAKEMASK1_32(25)
+#define M_LDT_ERRCTL_EOCNXAERR          _SB_MAKEMASK1_32(26)
+#define M_LDT_ERRCTL_SRCTAGERR          _SB_MAKEMASK1_32(27)
+#define M_LDT_ERRCTL_MAPNXAERR          _SB_MAKEMASK1_32(28)
+
+/*
+ * SRI Control register (Table 8-24, 8-25)  Offset 0x6C
+ */
+
+#define S_LDT_SRICTRL_NEEDRESP          0
+#define M_LDT_SRICTRL_NEEDRESP          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP)
+#define V_LDT_SRICTRL_NEEDRESP(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP)
+#define G_LDT_SRICTRL_NEEDRESP(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP)
+
+#define S_LDT_SRICTRL_NEEDNPREQ         2
+#define M_LDT_SRICTRL_NEEDNPREQ         _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ)
+#define V_LDT_SRICTRL_NEEDNPREQ(x)      _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ)
+#define G_LDT_SRICTRL_NEEDNPREQ(x)      _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ)
+
+#define S_LDT_SRICTRL_NEEDPREQ          4
+#define M_LDT_SRICTRL_NEEDPREQ          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ)
+#define V_LDT_SRICTRL_NEEDPREQ(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ)
+#define G_LDT_SRICTRL_NEEDPREQ(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ)
+
+#define S_LDT_SRICTRL_WANTRESP          8
+#define M_LDT_SRICTRL_WANTRESP          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP)
+#define V_LDT_SRICTRL_WANTRESP(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP)
+#define G_LDT_SRICTRL_WANTRESP(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP)
+
+#define S_LDT_SRICTRL_WANTNPREQ         10
+#define M_LDT_SRICTRL_WANTNPREQ         _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ)
+#define V_LDT_SRICTRL_WANTNPREQ(x)      _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ)
+#define G_LDT_SRICTRL_WANTNPREQ(x)      _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ)
+
+#define S_LDT_SRICTRL_WANTPREQ          12
+#define M_LDT_SRICTRL_WANTPREQ          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ)
+#define V_LDT_SRICTRL_WANTPREQ(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ)
+#define G_LDT_SRICTRL_WANTPREQ(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ)
+
+#define S_LDT_SRICTRL_BUFRELSPACE       16
+#define M_LDT_SRICTRL_BUFRELSPACE       _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE)
+#define V_LDT_SRICTRL_BUFRELSPACE(x)    _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE)
+#define G_LDT_SRICTRL_BUFRELSPACE(x)    _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE)
+
+/*
+ * LDT SRI Transmit Buffer Count register (Table 8-26)
+ */
+
+#define S_LDT_TXBUFCNT_PCMD             0
+#define M_LDT_TXBUFCNT_PCMD             _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD)
+#define V_LDT_TXBUFCNT_PCMD(x)          _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD)
+#define G_LDT_TXBUFCNT_PCMD(x)          _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD)
+
+#define S_LDT_TXBUFCNT_PDATA            4
+#define M_LDT_TXBUFCNT_PDATA            _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA)
+#define V_LDT_TXBUFCNT_PDATA(x)         _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA)
+#define G_LDT_TXBUFCNT_PDATA(x)         _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA)
+
+#define S_LDT_TXBUFCNT_NPCMD            8
+#define M_LDT_TXBUFCNT_NPCMD            _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD)
+#define V_LDT_TXBUFCNT_NPCMD(x)         _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD)
+#define G_LDT_TXBUFCNT_NPCMD(x)         _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD)
+
+#define S_LDT_TXBUFCNT_NPDATA           12
+#define M_LDT_TXBUFCNT_NPDATA           _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA)
+#define V_LDT_TXBUFCNT_NPDATA(x)        _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA)
+#define G_LDT_TXBUFCNT_NPDATA(x)        _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA)
+
+#define S_LDT_TXBUFCNT_RCMD             16
+#define M_LDT_TXBUFCNT_RCMD             _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD)
+#define V_LDT_TXBUFCNT_RCMD(x)          _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD)
+#define G_LDT_TXBUFCNT_RCMD(x)          _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD)
+
+#define S_LDT_TXBUFCNT_RDATA            20
+#define M_LDT_TXBUFCNT_RDATA            _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA)
+#define V_LDT_TXBUFCNT_RDATA(x)         _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA)
+#define G_LDT_TXBUFCNT_RDATA(x)         _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+/*
+ * Additional Status Register
+ */
+
+#define S_LDT_ADDSTATUS_TGTDONE         0
+#define M_LDT_ADDSTATUS_TGTDONE         _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE)
+#define V_LDT_ADDSTATUS_TGTDONE(x)      _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE)
+#define G_LDT_ADDSTATUS_TGTDONE(x)      _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#endif
+
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
new file mode 100644
index 000000000000..b6faf08ca81d
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -0,0 +1,656 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  MAC constants and macros                 File: sb1250_mac.h
+    *
+    *  This module contains constants and macros for the SB1250's
+    *  ethernet controllers.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_MAC_H
+#define _SB1250_MAC_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  Ethernet MAC Registers
+    ********************************************************************* */
+
+/*
+ * MAC Configuration Register (Table 9-13)
+ * Register: MAC_CFG_0
+ * Register: MAC_CFG_1
+ * Register: MAC_CFG_2
+ */
+
+
+#define M_MAC_RESERVED0             _SB_MAKEMASK1(0)
+#define M_MAC_TX_HOLD_SOP_EN        _SB_MAKEMASK1(1)
+#define M_MAC_RETRY_EN              _SB_MAKEMASK1(2)
+#define M_MAC_RET_DRPREQ_EN         _SB_MAKEMASK1(3)
+#define M_MAC_RET_UFL_EN            _SB_MAKEMASK1(4)
+#define M_MAC_BURST_EN              _SB_MAKEMASK1(5)
+
+#define S_MAC_TX_PAUSE              _SB_MAKE64(6)
+#define M_MAC_TX_PAUSE_CNT          _SB_MAKEMASK(3, S_MAC_TX_PAUSE)
+#define V_MAC_TX_PAUSE_CNT(x)       _SB_MAKEVALUE(x, S_MAC_TX_PAUSE)
+
+#define K_MAC_TX_PAUSE_CNT_512      0
+#define K_MAC_TX_PAUSE_CNT_1K       1
+#define K_MAC_TX_PAUSE_CNT_2K       2
+#define K_MAC_TX_PAUSE_CNT_4K       3
+#define K_MAC_TX_PAUSE_CNT_8K       4
+#define K_MAC_TX_PAUSE_CNT_16K      5
+#define K_MAC_TX_PAUSE_CNT_32K      6
+#define K_MAC_TX_PAUSE_CNT_64K      7
+
+#define V_MAC_TX_PAUSE_CNT_512      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512)
+#define V_MAC_TX_PAUSE_CNT_1K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K)
+#define V_MAC_TX_PAUSE_CNT_2K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K)
+#define V_MAC_TX_PAUSE_CNT_4K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K)
+#define V_MAC_TX_PAUSE_CNT_8K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K)
+#define V_MAC_TX_PAUSE_CNT_16K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K)
+#define V_MAC_TX_PAUSE_CNT_32K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
+#define V_MAC_TX_PAUSE_CNT_64K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
+
+#define M_MAC_RESERVED1             _SB_MAKEMASK(8, 9)
+
+#define M_MAC_AP_STAT_EN            _SB_MAKEMASK1(17)
+
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TIMESTAMP             _SB_MAKEMASK1(18)
+#endif
+#define M_MAC_DRP_ERRPKT_EN         _SB_MAKEMASK1(19)
+#define M_MAC_DRP_FCSERRPKT_EN      _SB_MAKEMASK1(20)
+#define M_MAC_DRP_CODEERRPKT_EN     _SB_MAKEMASK1(21)
+#define M_MAC_DRP_DRBLERRPKT_EN     _SB_MAKEMASK1(22)
+#define M_MAC_DRP_RNTPKT_EN         _SB_MAKEMASK1(23)
+#define M_MAC_DRP_OSZPKT_EN         _SB_MAKEMASK1(24)
+#define M_MAC_DRP_LENERRPKT_EN      _SB_MAKEMASK1(25)
+
+#define M_MAC_RESERVED3             _SB_MAKEMASK(6, 26)
+
+#define M_MAC_BYPASS_SEL            _SB_MAKEMASK1(32)
+#define M_MAC_HDX_EN                _SB_MAKEMASK1(33)
+
+#define S_MAC_SPEED_SEL             _SB_MAKE64(34)
+#define M_MAC_SPEED_SEL             _SB_MAKEMASK(2, S_MAC_SPEED_SEL)
+#define V_MAC_SPEED_SEL(x)          _SB_MAKEVALUE(x, S_MAC_SPEED_SEL)
+#define G_MAC_SPEED_SEL(x)          _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL)
+
+#define K_MAC_SPEED_SEL_10MBPS      0
+#define K_MAC_SPEED_SEL_100MBPS     1
+#define K_MAC_SPEED_SEL_1000MBPS    2
+#define K_MAC_SPEED_SEL_RESERVED    3
+
+#define V_MAC_SPEED_SEL_10MBPS      V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS)
+#define V_MAC_SPEED_SEL_100MBPS     V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS)
+#define V_MAC_SPEED_SEL_1000MBPS    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS)
+#define V_MAC_SPEED_SEL_RESERVED    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED)
+
+#define M_MAC_TX_CLK_EDGE_SEL       _SB_MAKEMASK1(36)
+#define M_MAC_LOOPBACK_SEL          _SB_MAKEMASK1(37)
+#define M_MAC_FAST_SYNC             _SB_MAKEMASK1(38)
+#define M_MAC_SS_EN                 _SB_MAKEMASK1(39)
+
+#define S_MAC_BYPASS_CFG            _SB_MAKE64(40)
+#define M_MAC_BYPASS_CFG            _SB_MAKEMASK(2, S_MAC_BYPASS_CFG)
+#define V_MAC_BYPASS_CFG(x)         _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG)
+#define G_MAC_BYPASS_CFG(x)         _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG)
+
+#define K_MAC_BYPASS_GMII           0
+#define K_MAC_BYPASS_ENCODED        1
+#define K_MAC_BYPASS_SOP            2
+#define K_MAC_BYPASS_EOP            3
+
+#define M_MAC_BYPASS_16             _SB_MAKEMASK1(42)
+#define M_MAC_BYPASS_FCS_CHK        _SB_MAKEMASK1(43)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_RX_CH_SEL_MSB         _SB_MAKEMASK1(44)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_SPLIT_CH_SEL          _SB_MAKEMASK1(45)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_MAC_BYPASS_IFG            _SB_MAKE64(46)
+#define M_MAC_BYPASS_IFG            _SB_MAKEMASK(8, S_MAC_BYPASS_IFG)
+#define V_MAC_BYPASS_IFG(x)         _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG)
+#define G_MAC_BYPASS_IFG(x)         _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG)
+
+#define K_MAC_FC_CMD_DISABLED       0
+#define K_MAC_FC_CMD_ENABLED        1
+#define K_MAC_FC_CMD_ENAB_FALSECARR 2
+
+#define V_MAC_FC_CMD_DISABLED       V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED)
+#define V_MAC_FC_CMD_ENABLED        V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED)
+#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR)
+
+#define M_MAC_FC_SEL                _SB_MAKEMASK1(54)
+
+#define S_MAC_FC_CMD                _SB_MAKE64(55)
+#define M_MAC_FC_CMD                _SB_MAKEMASK(2, S_MAC_FC_CMD)
+#define V_MAC_FC_CMD(x)             _SB_MAKEVALUE(x, S_MAC_FC_CMD)
+#define G_MAC_FC_CMD(x)             _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD)
+
+#define S_MAC_RX_CH_SEL             _SB_MAKE64(57)
+#define M_MAC_RX_CH_SEL             _SB_MAKEMASK(7, S_MAC_RX_CH_SEL)
+#define V_MAC_RX_CH_SEL(x)          _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL)
+#define G_MAC_RX_CH_SEL(x)          _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL)
+
+
+/*
+ * MAC Enable Registers
+ * Register: MAC_ENABLE_0
+ * Register: MAC_ENABLE_1
+ * Register: MAC_ENABLE_2
+ */
+
+#define M_MAC_RXDMA_EN0             _SB_MAKEMASK1(0)
+#define M_MAC_RXDMA_EN1             _SB_MAKEMASK1(1)
+#define M_MAC_TXDMA_EN0             _SB_MAKEMASK1(4)
+#define M_MAC_TXDMA_EN1             _SB_MAKEMASK1(5)
+
+#define M_MAC_PORT_RESET            _SB_MAKEMASK1(8)
+
+#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
+#define M_MAC_RX_ENABLE             _SB_MAKEMASK1(10)
+#define M_MAC_TX_ENABLE             _SB_MAKEMASK1(11)
+#define M_MAC_BYP_RX_ENABLE         _SB_MAKEMASK1(12)
+#define M_MAC_BYP_TX_ENABLE         _SB_MAKEMASK1(13)
+#endif
+
+/*
+ * MAC reset information register (1280/1255)
+ */
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_RX_CH0_PAUSE_ON   _SB_MAKEMASK1(8)
+#define M_MAC_RX_CH1_PAUSE_ON   _SB_MAKEMASK1(16)
+#define M_MAC_TX_CH0_PAUSE_ON   _SB_MAKEMASK1(24)
+#define M_MAC_TX_CH1_PAUSE_ON   _SB_MAKEMASK1(32)
+#endif
+
+/*
+ * MAC DMA Control Register
+ * Register: MAC_TXD_CTL_0
+ * Register: MAC_TXD_CTL_1
+ * Register: MAC_TXD_CTL_2
+ */
+
+#define S_MAC_TXD_WEIGHT0           _SB_MAKE64(0)
+#define M_MAC_TXD_WEIGHT0           _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0)
+#define V_MAC_TXD_WEIGHT0(x)        _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0)
+#define G_MAC_TXD_WEIGHT0(x)        _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0)
+
+#define S_MAC_TXD_WEIGHT1           _SB_MAKE64(4)
+#define M_MAC_TXD_WEIGHT1           _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1)
+#define V_MAC_TXD_WEIGHT1(x)        _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1)
+#define G_MAC_TXD_WEIGHT1(x)        _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
+
+/*
+ * MAC Fifo Threshhold registers (Table 9-14)
+ * Register: MAC_THRSH_CFG_0
+ * Register: MAC_THRSH_CFG_1
+ * Register: MAC_THRSH_CFG_2
+ */
+
+#define S_MAC_TX_WR_THRSH           _SB_MAKE64(0)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
+/* #define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */
+#endif /* up to 1250 PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define V_MAC_TX_WR_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH)
+#define G_MAC_TX_WR_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH)
+
+#define S_MAC_TX_RD_THRSH           _SB_MAKE64(8)
+#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
+/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
+/* #define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */
+#endif /* up to 1250 PASS1 */
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define V_MAC_TX_RD_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH)
+#define G_MAC_TX_RD_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH)
+
+#define S_MAC_TX_RL_THRSH           _SB_MAKE64(16)
+#define M_MAC_TX_RL_THRSH           _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH)
+#define V_MAC_TX_RL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH)
+#define G_MAC_TX_RL_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH)
+
+#define S_MAC_RX_PL_THRSH           _SB_MAKE64(24)
+#define M_MAC_RX_PL_THRSH           _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH)
+#define V_MAC_RX_PL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH)
+#define G_MAC_RX_PL_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH)
+
+#define S_MAC_RX_RD_THRSH           _SB_MAKE64(32)
+#define M_MAC_RX_RD_THRSH           _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH)
+#define V_MAC_RX_RD_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH)
+#define G_MAC_RX_RD_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH)
+
+#define S_MAC_RX_RL_THRSH           _SB_MAKE64(40)
+#define M_MAC_RX_RL_THRSH           _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH)
+#define V_MAC_RX_RL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH)
+#define G_MAC_RX_RL_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_MAC_ENC_FC_THRSH           _SB_MAKE64(56)
+#define M_MAC_ENC_FC_THRSH           _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH)
+#define V_MAC_ENC_FC_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH)
+#define G_MAC_ENC_FC_THRSH(x)        _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+/*
+ * MAC Frame Configuration Registers (Table 9-15)
+ * Register: MAC_FRAME_CFG_0
+ * Register: MAC_FRAME_CFG_1
+ * Register: MAC_FRAME_CFG_2
+ */
+
+/* XXXCGD: ??? Unused in pass2? */
+#define S_MAC_IFG_RX                _SB_MAKE64(0)
+#define M_MAC_IFG_RX                _SB_MAKEMASK(6, S_MAC_IFG_RX)
+#define V_MAC_IFG_RX(x)             _SB_MAKEVALUE(x, S_MAC_IFG_RX)
+#define G_MAC_IFG_RX(x)             _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_MAC_PRE_LEN               _SB_MAKE64(0)
+#define M_MAC_PRE_LEN               _SB_MAKEMASK(6, S_MAC_PRE_LEN)
+#define V_MAC_PRE_LEN(x)            _SB_MAKEVALUE(x, S_MAC_PRE_LEN)
+#define G_MAC_PRE_LEN(x)            _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_MAC_IFG_TX                _SB_MAKE64(6)
+#define M_MAC_IFG_TX                _SB_MAKEMASK(6, S_MAC_IFG_TX)
+#define V_MAC_IFG_TX(x)             _SB_MAKEVALUE(x, S_MAC_IFG_TX)
+#define G_MAC_IFG_TX(x)             _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX)
+
+#define S_MAC_IFG_THRSH             _SB_MAKE64(12)
+#define M_MAC_IFG_THRSH             _SB_MAKEMASK(6, S_MAC_IFG_THRSH)
+#define V_MAC_IFG_THRSH(x)          _SB_MAKEVALUE(x, S_MAC_IFG_THRSH)
+#define G_MAC_IFG_THRSH(x)          _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH)
+
+#define S_MAC_BACKOFF_SEL           _SB_MAKE64(18)
+#define M_MAC_BACKOFF_SEL           _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL)
+#define V_MAC_BACKOFF_SEL(x)        _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL)
+#define G_MAC_BACKOFF_SEL(x)        _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL)
+
+#define S_MAC_LFSR_SEED             _SB_MAKE64(22)
+#define M_MAC_LFSR_SEED             _SB_MAKEMASK(8, S_MAC_LFSR_SEED)
+#define V_MAC_LFSR_SEED(x)          _SB_MAKEVALUE(x, S_MAC_LFSR_SEED)
+#define G_MAC_LFSR_SEED(x)          _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED)
+
+#define S_MAC_SLOT_SIZE             _SB_MAKE64(30)
+#define M_MAC_SLOT_SIZE             _SB_MAKEMASK(10, S_MAC_SLOT_SIZE)
+#define V_MAC_SLOT_SIZE(x)          _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE)
+#define G_MAC_SLOT_SIZE(x)          _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE)
+
+#define S_MAC_MIN_FRAMESZ           _SB_MAKE64(40)
+#define M_MAC_MIN_FRAMESZ           _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ)
+#define V_MAC_MIN_FRAMESZ(x)        _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ)
+#define G_MAC_MIN_FRAMESZ(x)        _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ)
+
+#define S_MAC_MAX_FRAMESZ           _SB_MAKE64(48)
+#define M_MAC_MAX_FRAMESZ           _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ)
+#define V_MAC_MAX_FRAMESZ(x)        _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ)
+#define G_MAC_MAX_FRAMESZ(x)        _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ)
+
+/*
+ * These constants are used to configure the fields within the Frame
+ * Configuration Register.
+ */
+
+#define K_MAC_IFG_RX_10             _SB_MAKE64(0)       /* See table 176, not used */
+#define K_MAC_IFG_RX_100            _SB_MAKE64(0)
+#define K_MAC_IFG_RX_1000           _SB_MAKE64(0)
+
+#define K_MAC_IFG_TX_10             _SB_MAKE64(20)
+#define K_MAC_IFG_TX_100            _SB_MAKE64(20)
+#define K_MAC_IFG_TX_1000           _SB_MAKE64(8)
+
+#define K_MAC_IFG_THRSH_10          _SB_MAKE64(4)
+#define K_MAC_IFG_THRSH_100         _SB_MAKE64(4)
+#define K_MAC_IFG_THRSH_1000        _SB_MAKE64(0)
+
+#define K_MAC_SLOT_SIZE_10          _SB_MAKE64(0)
+#define K_MAC_SLOT_SIZE_100         _SB_MAKE64(0)
+#define K_MAC_SLOT_SIZE_1000        _SB_MAKE64(0)
+
+#define V_MAC_IFG_RX_10        V_MAC_IFG_RX(K_MAC_IFG_RX_10)
+#define V_MAC_IFG_RX_100       V_MAC_IFG_RX(K_MAC_IFG_RX_100)
+#define V_MAC_IFG_RX_1000      V_MAC_IFG_RX(K_MAC_IFG_RX_1000)
+
+#define V_MAC_IFG_TX_10        V_MAC_IFG_TX(K_MAC_IFG_TX_10)
+#define V_MAC_IFG_TX_100       V_MAC_IFG_TX(K_MAC_IFG_TX_100)
+#define V_MAC_IFG_TX_1000      V_MAC_IFG_TX(K_MAC_IFG_TX_1000)
+
+#define V_MAC_IFG_THRSH_10     V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10)
+#define V_MAC_IFG_THRSH_100    V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100)
+#define V_MAC_IFG_THRSH_1000   V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000)
+
+#define V_MAC_SLOT_SIZE_10     V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10)
+#define V_MAC_SLOT_SIZE_100    V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
+#define V_MAC_SLOT_SIZE_1000   V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
+
+#define K_MAC_MIN_FRAMESZ_FIFO      _SB_MAKE64(9)
+#define K_MAC_MIN_FRAMESZ_DEFAULT   _SB_MAKE64(64)
+#define K_MAC_MAX_FRAMESZ_DEFAULT   _SB_MAKE64(1518)
+#define K_MAC_MAX_FRAMESZ_JUMBO     _SB_MAKE64(9216)
+
+#define V_MAC_MIN_FRAMESZ_FIFO      V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)
+#define V_MAC_MIN_FRAMESZ_DEFAULT   V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
+#define V_MAC_MAX_FRAMESZ_DEFAULT   V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)
+#define V_MAC_MAX_FRAMESZ_JUMBO     V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)
+
+/*
+ * MAC VLAN Tag Registers (Table 9-16)
+ * Register: MAC_VLANTAG_0
+ * Register: MAC_VLANTAG_1
+ * Register: MAC_VLANTAG_2
+ */
+
+#define S_MAC_VLAN_TAG           _SB_MAKE64(0)
+#define M_MAC_VLAN_TAG           _SB_MAKEMASK(32, S_MAC_VLAN_TAG)
+#define V_MAC_VLAN_TAG(x)        _SB_MAKEVALUE(x, S_MAC_VLAN_TAG)
+#define G_MAC_VLAN_TAG(x)        _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define S_MAC_TX_PKT_OFFSET      _SB_MAKE64(32)
+#define M_MAC_TX_PKT_OFFSET      _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET)
+#define V_MAC_TX_PKT_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET)
+#define G_MAC_TX_PKT_OFFSET(x)   _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET)
+
+#define S_MAC_TX_CRC_OFFSET      _SB_MAKE64(40)
+#define M_MAC_TX_CRC_OFFSET      _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET)
+#define V_MAC_TX_CRC_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET)
+#define G_MAC_TX_CRC_OFFSET(x)   _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET)
+
+#define M_MAC_CH_BASE_FC_EN      _SB_MAKEMASK1(48)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*
+ * MAC Status Registers (Table 9-17)
+ * Also used for the MAC Interrupt Mask Register (Table 9-18)
+ * Register: MAC_STATUS_0
+ * Register: MAC_STATUS_1
+ * Register: MAC_STATUS_2
+ * Register: MAC_INT_MASK_0
+ * Register: MAC_INT_MASK_1
+ * Register: MAC_INT_MASK_2
+ */
+
+/*
+ * Use these constants to shift the appropriate channel
+ * into the CH0 position so the same tests can be used
+ * on each channel.
+ */
+
+#define S_MAC_RX_CH0                _SB_MAKE64(0)
+#define S_MAC_RX_CH1                _SB_MAKE64(8)
+#define S_MAC_TX_CH0                _SB_MAKE64(16)
+#define S_MAC_TX_CH1                _SB_MAKE64(24)
+
+#define S_MAC_TXCHANNELS            _SB_MAKE64(16)      /* this is 1st TX chan */
+#define S_MAC_CHANWIDTH             _SB_MAKE64(8)       /* bits between channels */
+
+/*
+ *  These are the same as RX channel 0.  The idea here
+ *  is that you'll use one of the "S_" things above
+ *  and pass just the six bits to a DMA-channel-specific ISR
+ */
+#define M_MAC_INT_CHANNEL           _SB_MAKEMASK(8, 0)
+#define M_MAC_INT_EOP_COUNT         _SB_MAKEMASK1(0)
+#define M_MAC_INT_EOP_TIMER         _SB_MAKEMASK1(1)
+#define M_MAC_INT_EOP_SEEN          _SB_MAKEMASK1(2)
+#define M_MAC_INT_HWM               _SB_MAKEMASK1(3)
+#define M_MAC_INT_LWM               _SB_MAKEMASK1(4)
+#define M_MAC_INT_DSCR              _SB_MAKEMASK1(5)
+#define M_MAC_INT_ERR               _SB_MAKEMASK1(6)
+#define M_MAC_INT_DZERO             _SB_MAKEMASK1(7)    /* only for TX channels */
+#define M_MAC_INT_DROP              _SB_MAKEMASK1(7)    /* only for RX channels */
+
+/*
+ * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
+ * also DMA_TX/DMA_RX in sb_regs.h).
+ */
+#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
+
+#define M_MAC_STATUS_CHANNEL(ch, txrx)   _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_EOP_SEEN(ch, txrx)  _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_HWM(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_LWM(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_DSCR(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_ERR(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_DZERO(ch, txrx)     _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_DROP(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_OTHER_ERR           _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40)
+
+
+#define M_MAC_RX_UNDRFL             _SB_MAKEMASK1(40)
+#define M_MAC_RX_OVRFL              _SB_MAKEMASK1(41)
+#define M_MAC_TX_UNDRFL             _SB_MAKEMASK1(42)
+#define M_MAC_TX_OVRFL              _SB_MAKEMASK1(43)
+#define M_MAC_LTCOL_ERR             _SB_MAKEMASK1(44)
+#define M_MAC_EXCOL_ERR             _SB_MAKEMASK1(45)
+#define M_MAC_CNTR_OVRFL_ERR        _SB_MAKEMASK1(46)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_SPLIT_EN              _SB_MAKEMASK1(47)   /* interrupt mask only */
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_MAC_COUNTER_ADDR          _SB_MAKE64(47)
+#define M_MAC_COUNTER_ADDR          _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR)
+#define V_MAC_COUNTER_ADDR(x)       _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR)
+#define G_MAC_COUNTER_ADDR(x)       _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_TX_PAUSE_ON           _SB_MAKEMASK1(52)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+/*
+ * MAC Fifo Pointer Registers (Table 9-19)    [Debug register]
+ * Register: MAC_FIFO_PTRS_0
+ * Register: MAC_FIFO_PTRS_1
+ * Register: MAC_FIFO_PTRS_2
+ */
+
+#define S_MAC_TX_WRPTR              _SB_MAKE64(0)
+#define M_MAC_TX_WRPTR              _SB_MAKEMASK(6, S_MAC_TX_WRPTR)
+#define V_MAC_TX_WRPTR(x)           _SB_MAKEVALUE(x, S_MAC_TX_WRPTR)
+#define G_MAC_TX_WRPTR(x)           _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR)
+
+#define S_MAC_TX_RDPTR              _SB_MAKE64(8)
+#define M_MAC_TX_RDPTR              _SB_MAKEMASK(6, S_MAC_TX_RDPTR)
+#define V_MAC_TX_RDPTR(x)           _SB_MAKEVALUE(x, S_MAC_TX_RDPTR)
+#define G_MAC_TX_RDPTR(x)           _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR)
+
+#define S_MAC_RX_WRPTR              _SB_MAKE64(16)
+#define M_MAC_RX_WRPTR              _SB_MAKEMASK(6, S_MAC_RX_WRPTR)
+#define V_MAC_RX_WRPTR(x)           _SB_MAKEVALUE(x, S_MAC_RX_WRPTR)
+#define G_MAC_RX_WRPTR(x)           _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR)
+
+#define S_MAC_RX_RDPTR              _SB_MAKE64(24)
+#define M_MAC_RX_RDPTR              _SB_MAKEMASK(6, S_MAC_RX_RDPTR)
+#define V_MAC_RX_RDPTR(x)           _SB_MAKEVALUE(x, S_MAC_RX_RDPTR)
+#define G_MAC_RX_RDPTR(x)           _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR)
+
+/*
+ * MAC Fifo End Of Packet Count Registers (Table 9-20)  [Debug register]
+ * Register: MAC_EOPCNT_0
+ * Register: MAC_EOPCNT_1
+ * Register: MAC_EOPCNT_2
+ */
+
+#define S_MAC_TX_EOP_COUNTER        _SB_MAKE64(0)
+#define M_MAC_TX_EOP_COUNTER        _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER)
+#define V_MAC_TX_EOP_COUNTER(x)     _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER)
+#define G_MAC_TX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER)
+
+#define S_MAC_RX_EOP_COUNTER        _SB_MAKE64(8)
+#define M_MAC_RX_EOP_COUNTER        _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER)
+#define V_MAC_RX_EOP_COUNTER(x)     _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER)
+#define G_MAC_RX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
+
+/*
+ * MAC Recieve Address Filter Exact Match Registers (Table 9-21)
+ * Registers: MAC_ADDR0_0 through MAC_ADDR7_0
+ * Registers: MAC_ADDR0_1 through MAC_ADDR7_1
+ * Registers: MAC_ADDR0_2 through MAC_ADDR7_2
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Receive Address Filter Mask Registers
+ * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1
+ * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1
+ * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Recieve Address Filter Hash Match Registers (Table 9-22)
+ * Registers: MAC_HASH0_0 through MAC_HASH7_0
+ * Registers: MAC_HASH0_1 through MAC_HASH7_1
+ * Registers: MAC_HASH0_2 through MAC_HASH7_2
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Transmit Source Address Registers (Table 9-23)
+ * Register: MAC_ETHERNET_ADDR_0
+ * Register: MAC_ETHERNET_ADDR_1
+ * Register: MAC_ETHERNET_ADDR_2
+ */
+
+/* No bitfields */
+
+/*
+ * MAC Packet Type Configuration Register
+ * Register: MAC_TYPE_CFG_0
+ * Register: MAC_TYPE_CFG_1
+ * Register: MAC_TYPE_CFG_2
+ */
+
+#define S_TYPECFG_TYPESIZE      _SB_MAKE64(16)
+
+#define S_TYPECFG_TYPE0         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE0         _SB_MAKEMASK(16, S_TYPECFG_TYPE0)
+#define V_TYPECFG_TYPE0(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE0)
+#define G_TYPECFG_TYPE0(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0)
+
+#define S_TYPECFG_TYPE1         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE1         _SB_MAKEMASK(16, S_TYPECFG_TYPE1)
+#define V_TYPECFG_TYPE1(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE1)
+#define G_TYPECFG_TYPE1(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1)
+
+#define S_TYPECFG_TYPE2         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE2         _SB_MAKEMASK(16, S_TYPECFG_TYPE2)
+#define V_TYPECFG_TYPE2(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE2)
+#define G_TYPECFG_TYPE2(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2)
+
+#define S_TYPECFG_TYPE3         _SB_MAKE64(0)
+#define M_TYPECFG_TYPE3         _SB_MAKEMASK(16, S_TYPECFG_TYPE3)
+#define V_TYPECFG_TYPE3(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE3)
+#define G_TYPECFG_TYPE3(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3)
+
+/*
+ * MAC Receive Address Filter Control Registers (Table 9-24)
+ * Register: MAC_ADFILTER_CFG_0
+ * Register: MAC_ADFILTER_CFG_1
+ * Register: MAC_ADFILTER_CFG_2
+ */
+
+#define M_MAC_ALLPKT_EN         _SB_MAKEMASK1(0)
+#define M_MAC_UCAST_EN          _SB_MAKEMASK1(1)
+#define M_MAC_UCAST_INV         _SB_MAKEMASK1(2)
+#define M_MAC_MCAST_EN          _SB_MAKEMASK1(3)
+#define M_MAC_MCAST_INV         _SB_MAKEMASK1(4)
+#define M_MAC_BCAST_EN          _SB_MAKEMASK1(5)
+#define M_MAC_DIRECT_INV        _SB_MAKEMASK1(6)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_MAC_ALLMCAST_EN       _SB_MAKEMASK1(7)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define S_MAC_IPHDR_OFFSET      _SB_MAKE64(8)
+#define M_MAC_IPHDR_OFFSET      _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET)
+#define V_MAC_IPHDR_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET)
+#define G_MAC_IPHDR_OFFSET(x)   _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_MAC_RX_CRC_OFFSET     _SB_MAKE64(16)
+#define M_MAC_RX_CRC_OFFSET     _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET)
+#define V_MAC_RX_CRC_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET)
+#define G_MAC_RX_CRC_OFFSET(x)  _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET)
+
+#define S_MAC_RX_PKT_OFFSET     _SB_MAKE64(24)
+#define M_MAC_RX_PKT_OFFSET     _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET)
+#define V_MAC_RX_PKT_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET)
+#define G_MAC_RX_PKT_OFFSET(x)  _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET)
+
+#define M_MAC_FWDPAUSE_EN       _SB_MAKEMASK1(32)
+#define M_MAC_VLAN_DET_EN       _SB_MAKEMASK1(33)
+
+#define S_MAC_RX_CH_MSN_SEL     _SB_MAKE64(34)
+#define M_MAC_RX_CH_MSN_SEL     _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL)
+#define V_MAC_RX_CH_MSN_SEL(x)  _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL)
+#define G_MAC_RX_CH_MSN_SEL(x)  _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+/*
+ * MAC Receive Channel Select Registers (Table 9-25)
+ */
+
+/* no bitfields */
+
+/*
+ * MAC MII Management Interface Registers (Table 9-26)
+ * Register: MAC_MDIO_0
+ * Register: MAC_MDIO_1
+ * Register: MAC_MDIO_2
+ */
+
+#define S_MAC_MDC               0
+#define S_MAC_MDIO_DIR          1
+#define S_MAC_MDIO_OUT          2
+#define S_MAC_GENC              3
+#define S_MAC_MDIO_IN           4
+
+#define M_MAC_MDC               _SB_MAKEMASK1(S_MAC_MDC)
+#define M_MAC_MDIO_DIR          _SB_MAKEMASK1(S_MAC_MDIO_DIR)
+#define M_MAC_MDIO_DIR_INPUT    _SB_MAKEMASK1(S_MAC_MDIO_DIR)
+#define M_MAC_MDIO_OUT          _SB_MAKEMASK1(S_MAC_MDIO_OUT)
+#define M_MAC_GENC              _SB_MAKEMASK1(S_MAC_GENC)
+#define M_MAC_MDIO_IN           _SB_MAKEMASK1(S_MAC_MDIO_IN)
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h
new file mode 100644
index 000000000000..1eb1b5a88736
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_mc.h
@@ -0,0 +1,550 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Memory Controller constants              File: sb1250_mc.h
+    *
+    *  This module contains constants and macros useful for
+    *  programming the memory controller.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000, 2001, 2002, 2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_MC_H
+#define _SB1250_MC_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Memory Channel Config Register (table 6-14)
+ */
+
+#define S_MC_RESERVED0              0
+#define M_MC_RESERVED0              _SB_MAKEMASK(8, S_MC_RESERVED0)
+
+#define S_MC_CHANNEL_SEL            8
+#define M_MC_CHANNEL_SEL            _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
+#define V_MC_CHANNEL_SEL(x)         _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
+#define G_MC_CHANNEL_SEL(x)         _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
+
+#define S_MC_BANK0_MAP              16
+#define M_MC_BANK0_MAP              _SB_MAKEMASK(4, S_MC_BANK0_MAP)
+#define V_MC_BANK0_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
+#define G_MC_BANK0_MAP(x)           _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
+
+#define K_MC_BANK0_MAP_DEFAULT      0x00
+#define V_MC_BANK0_MAP_DEFAULT      V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
+
+#define S_MC_BANK1_MAP              20
+#define M_MC_BANK1_MAP              _SB_MAKEMASK(4, S_MC_BANK1_MAP)
+#define V_MC_BANK1_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
+#define G_MC_BANK1_MAP(x)           _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
+
+#define K_MC_BANK1_MAP_DEFAULT      0x08
+#define V_MC_BANK1_MAP_DEFAULT      V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
+
+#define S_MC_BANK2_MAP              24
+#define M_MC_BANK2_MAP              _SB_MAKEMASK(4, S_MC_BANK2_MAP)
+#define V_MC_BANK2_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
+#define G_MC_BANK2_MAP(x)           _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
+
+#define K_MC_BANK2_MAP_DEFAULT      0x09
+#define V_MC_BANK2_MAP_DEFAULT      V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
+
+#define S_MC_BANK3_MAP              28
+#define M_MC_BANK3_MAP              _SB_MAKEMASK(4, S_MC_BANK3_MAP)
+#define V_MC_BANK3_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
+#define G_MC_BANK3_MAP(x)           _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
+
+#define K_MC_BANK3_MAP_DEFAULT      0x0C
+#define V_MC_BANK3_MAP_DEFAULT      V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
+
+#define M_MC_RESERVED1              _SB_MAKEMASK(8, 32)
+
+#define S_MC_QUEUE_SIZE             40
+#define M_MC_QUEUE_SIZE             _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
+#define V_MC_QUEUE_SIZE(x)          _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
+#define G_MC_QUEUE_SIZE(x)          _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
+#define V_MC_QUEUE_SIZE_DEFAULT     V_MC_QUEUE_SIZE(0x0A)
+
+#define S_MC_AGE_LIMIT              44
+#define M_MC_AGE_LIMIT              _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
+#define V_MC_AGE_LIMIT(x)           _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
+#define G_MC_AGE_LIMIT(x)           _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
+#define V_MC_AGE_LIMIT_DEFAULT      V_MC_AGE_LIMIT(8)
+
+#define S_MC_WR_LIMIT               48
+#define M_MC_WR_LIMIT               _SB_MAKEMASK(4, S_MC_WR_LIMIT)
+#define V_MC_WR_LIMIT(x)            _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
+#define G_MC_WR_LIMIT(x)            _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
+#define V_MC_WR_LIMIT_DEFAULT       V_MC_WR_LIMIT(5)
+
+#define M_MC_IOB1HIGHPRIORITY       _SB_MAKEMASK1(52)
+
+#define M_MC_RESERVED2              _SB_MAKEMASK(3, 53)
+
+#define S_MC_CS_MODE                56
+#define M_MC_CS_MODE                _SB_MAKEMASK(4, S_MC_CS_MODE)
+#define V_MC_CS_MODE(x)             _SB_MAKEVALUE(x, S_MC_CS_MODE)
+#define G_MC_CS_MODE(x)             _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
+
+#define K_MC_CS_MODE_MSB_CS         0
+#define K_MC_CS_MODE_INTLV_CS       15
+#define K_MC_CS_MODE_MIXED_CS_10    12
+#define K_MC_CS_MODE_MIXED_CS_30    6
+#define K_MC_CS_MODE_MIXED_CS_32    3
+
+#define V_MC_CS_MODE_MSB_CS         V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
+#define V_MC_CS_MODE_INTLV_CS       V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
+#define V_MC_CS_MODE_MIXED_CS_10    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
+#define V_MC_CS_MODE_MIXED_CS_30    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
+#define V_MC_CS_MODE_MIXED_CS_32    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
+
+#define M_MC_ECC_DISABLE            _SB_MAKEMASK1(60)
+#define M_MC_BERR_DISABLE           _SB_MAKEMASK1(61)
+#define M_MC_FORCE_SEQ              _SB_MAKEMASK1(62)
+#define M_MC_DEBUG                  _SB_MAKEMASK1(63)
+
+#define V_MC_CONFIG_DEFAULT     V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
+                                V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
+                                V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
+                                M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
+
+
+/*
+ * Memory clock config register (Table 6-15)
+ *
+ * Note: this field has been updated to be consistent with the errata to 0.2
+ */
+
+#define S_MC_CLK_RATIO              0
+#define M_MC_CLK_RATIO              _SB_MAKEMASK(4, S_MC_CLK_RATIO)
+#define V_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
+#define G_MC_CLK_RATIO(x)           _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
+
+#define K_MC_CLK_RATIO_2X           4
+#define K_MC_CLK_RATIO_25X          5
+#define K_MC_CLK_RATIO_3X           6
+#define K_MC_CLK_RATIO_35X          7
+#define K_MC_CLK_RATIO_4X           8
+#define K_MC_CLK_RATIO_45X          9
+
+#define V_MC_CLK_RATIO_2X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
+#define V_MC_CLK_RATIO_25X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
+#define V_MC_CLK_RATIO_3X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
+#define V_MC_CLK_RATIO_35X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
+#define V_MC_CLK_RATIO_4X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
+#define V_MC_CLK_RATIO_45X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
+#define V_MC_CLK_RATIO_DEFAULT      V_MC_CLK_RATIO_25X
+
+#define S_MC_REF_RATE                8
+#define M_MC_REF_RATE                _SB_MAKEMASK(8, S_MC_REF_RATE)
+#define V_MC_REF_RATE(x)             _SB_MAKEVALUE(x, S_MC_REF_RATE)
+#define G_MC_REF_RATE(x)             _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
+
+#define K_MC_REF_RATE_100MHz         0x62
+#define K_MC_REF_RATE_133MHz         0x81
+#define K_MC_REF_RATE_200MHz         0xC4
+
+#define V_MC_REF_RATE_100MHz         V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
+#define V_MC_REF_RATE_133MHz         V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
+#define V_MC_REF_RATE_200MHz         V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
+#define V_MC_REF_RATE_DEFAULT        V_MC_REF_RATE_100MHz
+
+#define S_MC_CLOCK_DRIVE             16
+#define M_MC_CLOCK_DRIVE             _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
+#define V_MC_CLOCK_DRIVE(x)          _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
+#define G_MC_CLOCK_DRIVE(x)          _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
+#define V_MC_CLOCK_DRIVE_DEFAULT     V_MC_CLOCK_DRIVE(0xF)
+
+#define S_MC_DATA_DRIVE              20
+#define M_MC_DATA_DRIVE              _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
+#define V_MC_DATA_DRIVE(x)           _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
+#define G_MC_DATA_DRIVE(x)           _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
+#define V_MC_DATA_DRIVE_DEFAULT      V_MC_DATA_DRIVE(0x0)
+
+#define S_MC_ADDR_DRIVE              24
+#define M_MC_ADDR_DRIVE              _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
+#define V_MC_ADDR_DRIVE(x)           _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
+#define G_MC_ADDR_DRIVE(x)           _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
+#define V_MC_ADDR_DRIVE_DEFAULT      V_MC_ADDR_DRIVE(0x0)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MC_REF_DISABLE             _SB_MAKEMASK1(30)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#define M_MC_DLL_BYPASS              _SB_MAKEMASK1(31)
+
+#define S_MC_DQI_SKEW               32
+#define M_MC_DQI_SKEW               _SB_MAKEMASK(8, S_MC_DQI_SKEW)
+#define V_MC_DQI_SKEW(x)            _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
+#define G_MC_DQI_SKEW(x)            _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
+#define V_MC_DQI_SKEW_DEFAULT       V_MC_DQI_SKEW(0)
+
+#define S_MC_DQO_SKEW               40
+#define M_MC_DQO_SKEW               _SB_MAKEMASK(8, S_MC_DQO_SKEW)
+#define V_MC_DQO_SKEW(x)            _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
+#define G_MC_DQO_SKEW(x)            _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
+#define V_MC_DQO_SKEW_DEFAULT       V_MC_DQO_SKEW(0)
+
+#define S_MC_ADDR_SKEW               48
+#define M_MC_ADDR_SKEW               _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
+#define V_MC_ADDR_SKEW(x)            _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
+#define G_MC_ADDR_SKEW(x)            _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
+#define V_MC_ADDR_SKEW_DEFAULT       V_MC_ADDR_SKEW(0x0F)
+
+#define S_MC_DLL_DEFAULT             56
+#define M_MC_DLL_DEFAULT             _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
+#define V_MC_DLL_DEFAULT(x)          _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
+#define G_MC_DLL_DEFAULT(x)          _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
+#define V_MC_DLL_DEFAULT_DEFAULT     V_MC_DLL_DEFAULT(0x10)
+
+#define V_MC_CLKCONFIG_DEFAULT       V_MC_DLL_DEFAULT_DEFAULT |  \
+                                     V_MC_ADDR_SKEW_DEFAULT | \
+                                     V_MC_DQO_SKEW_DEFAULT | \
+                                     V_MC_DQI_SKEW_DEFAULT | \
+                                     V_MC_ADDR_DRIVE_DEFAULT | \
+                                     V_MC_DATA_DRIVE_DEFAULT | \
+                                     V_MC_CLOCK_DRIVE_DEFAULT | \
+                                     V_MC_REF_RATE_DEFAULT
+
+
+
+/*
+ * DRAM Command Register (Table 6-13)
+ */
+
+#define S_MC_COMMAND                0
+#define M_MC_COMMAND                _SB_MAKEMASK(4, S_MC_COMMAND)
+#define V_MC_COMMAND(x)             _SB_MAKEVALUE(x, S_MC_COMMAND)
+#define G_MC_COMMAND(x)             _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
+
+#define K_MC_COMMAND_EMRS           0
+#define K_MC_COMMAND_MRS            1
+#define K_MC_COMMAND_PRE            2
+#define K_MC_COMMAND_AR             3
+#define K_MC_COMMAND_SETRFSH        4
+#define K_MC_COMMAND_CLRRFSH        5
+#define K_MC_COMMAND_SETPWRDN       6
+#define K_MC_COMMAND_CLRPWRDN       7
+
+#define V_MC_COMMAND_EMRS           V_MC_COMMAND(K_MC_COMMAND_EMRS)
+#define V_MC_COMMAND_MRS            V_MC_COMMAND(K_MC_COMMAND_MRS)
+#define V_MC_COMMAND_PRE            V_MC_COMMAND(K_MC_COMMAND_PRE)
+#define V_MC_COMMAND_AR             V_MC_COMMAND(K_MC_COMMAND_AR)
+#define V_MC_COMMAND_SETRFSH        V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
+#define V_MC_COMMAND_CLRRFSH        V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
+#define V_MC_COMMAND_SETPWRDN       V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
+#define V_MC_COMMAND_CLRPWRDN       V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
+
+#define M_MC_CS0                    _SB_MAKEMASK1(4)
+#define M_MC_CS1                    _SB_MAKEMASK1(5)
+#define M_MC_CS2                    _SB_MAKEMASK1(6)
+#define M_MC_CS3                    _SB_MAKEMASK1(7)
+
+/*
+ * DRAM Mode Register (Table 6-14)
+ */
+
+#define S_MC_EMODE                  0
+#define M_MC_EMODE                  _SB_MAKEMASK(15, S_MC_EMODE)
+#define V_MC_EMODE(x)               _SB_MAKEVALUE(x, S_MC_EMODE)
+#define G_MC_EMODE(x)               _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
+#define V_MC_EMODE_DEFAULT          V_MC_EMODE(0)
+
+#define S_MC_MODE                   16
+#define M_MC_MODE                   _SB_MAKEMASK(15, S_MC_MODE)
+#define V_MC_MODE(x)                _SB_MAKEVALUE(x, S_MC_MODE)
+#define G_MC_MODE(x)                _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
+#define V_MC_MODE_DEFAULT           V_MC_MODE(0x22)
+
+#define S_MC_DRAM_TYPE              32
+#define M_MC_DRAM_TYPE              _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
+#define V_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
+#define G_MC_DRAM_TYPE(x)           _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
+
+#define K_MC_DRAM_TYPE_JEDEC        0
+#define K_MC_DRAM_TYPE_FCRAM        1
+#define K_MC_DRAM_TYPE_SGRAM        2
+
+#define V_MC_DRAM_TYPE_JEDEC        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
+#define V_MC_DRAM_TYPE_FCRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
+#define V_MC_DRAM_TYPE_SGRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
+
+#define M_MC_EXTERNALDECODE         _SB_MAKEMASK1(35)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_MC_PRE_ON_A8              _SB_MAKEMASK1(36)
+#define M_MC_RAM_WITH_A13           _SB_MAKEMASK1(37)
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+
+
+/*
+ * SDRAM Timing Register  (Table 6-15)
+ */
+
+#define M_MC_w2rIDLE_TWOCYCLES    _SB_MAKEMASK1(60)
+#define M_MC_r2wIDLE_TWOCYCLES    _SB_MAKEMASK1(61)
+#define M_MC_r2rIDLE_TWOCYCLES    _SB_MAKEMASK1(62)
+
+#define S_MC_tFIFO                56
+#define M_MC_tFIFO                _SB_MAKEMASK(4, S_MC_tFIFO)
+#define V_MC_tFIFO(x)             _SB_MAKEVALUE(x, S_MC_tFIFO)
+#define G_MC_tFIFO(x)             _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
+#define K_MC_tFIFO_DEFAULT        1
+#define V_MC_tFIFO_DEFAULT        V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
+
+#define S_MC_tRFC                 52
+#define M_MC_tRFC                 _SB_MAKEMASK(4, S_MC_tRFC)
+#define V_MC_tRFC(x)              _SB_MAKEVALUE(x, S_MC_tRFC)
+#define G_MC_tRFC(x)              _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
+#define K_MC_tRFC_DEFAULT         12
+#define V_MC_tRFC_DEFAULT         V_MC_tRFC(K_MC_tRFC_DEFAULT)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3)
+#define M_MC_tRFC_PLUS16          _SB_MAKEMASK1(51)     /* 1250C3 and later.  */
+#endif
+
+#define S_MC_tCwCr                40
+#define M_MC_tCwCr                _SB_MAKEMASK(4, S_MC_tCwCr)
+#define V_MC_tCwCr(x)             _SB_MAKEVALUE(x, S_MC_tCwCr)
+#define G_MC_tCwCr(x)             _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
+#define K_MC_tCwCr_DEFAULT        4
+#define V_MC_tCwCr_DEFAULT        V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
+
+#define S_MC_tRCr                 28
+#define M_MC_tRCr                 _SB_MAKEMASK(4, S_MC_tRCr)
+#define V_MC_tRCr(x)              _SB_MAKEVALUE(x, S_MC_tRCr)
+#define G_MC_tRCr(x)              _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
+#define K_MC_tRCr_DEFAULT         9
+#define V_MC_tRCr_DEFAULT         V_MC_tRCr(K_MC_tRCr_DEFAULT)
+
+#define S_MC_tRCw                 24
+#define M_MC_tRCw                 _SB_MAKEMASK(4, S_MC_tRCw)
+#define V_MC_tRCw(x)              _SB_MAKEVALUE(x, S_MC_tRCw)
+#define G_MC_tRCw(x)              _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
+#define K_MC_tRCw_DEFAULT         10
+#define V_MC_tRCw_DEFAULT         V_MC_tRCw(K_MC_tRCw_DEFAULT)
+
+#define S_MC_tRRD                 20
+#define M_MC_tRRD                 _SB_MAKEMASK(4, S_MC_tRRD)
+#define V_MC_tRRD(x)              _SB_MAKEVALUE(x, S_MC_tRRD)
+#define G_MC_tRRD(x)              _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
+#define K_MC_tRRD_DEFAULT         2
+#define V_MC_tRRD_DEFAULT         V_MC_tRRD(K_MC_tRRD_DEFAULT)
+
+#define S_MC_tRP                  16
+#define M_MC_tRP                  _SB_MAKEMASK(4, S_MC_tRP)
+#define V_MC_tRP(x)               _SB_MAKEVALUE(x, S_MC_tRP)
+#define G_MC_tRP(x)               _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
+#define K_MC_tRP_DEFAULT          4
+#define V_MC_tRP_DEFAULT          V_MC_tRP(K_MC_tRP_DEFAULT)
+
+#define S_MC_tCwD                 8
+#define M_MC_tCwD                 _SB_MAKEMASK(4, S_MC_tCwD)
+#define V_MC_tCwD(x)              _SB_MAKEVALUE(x, S_MC_tCwD)
+#define G_MC_tCwD(x)              _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
+#define K_MC_tCwD_DEFAULT         1
+#define V_MC_tCwD_DEFAULT         V_MC_tCwD(K_MC_tCwD_DEFAULT)
+
+#define M_tCrDh                   _SB_MAKEMASK1(7)
+#define M_MC_tCrDh                M_tCrDh
+
+#define S_MC_tCrD                 4
+#define M_MC_tCrD                 _SB_MAKEMASK(3, S_MC_tCrD)
+#define V_MC_tCrD(x)              _SB_MAKEVALUE(x, S_MC_tCrD)
+#define G_MC_tCrD(x)              _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
+#define K_MC_tCrD_DEFAULT         2
+#define V_MC_tCrD_DEFAULT         V_MC_tCrD(K_MC_tCrD_DEFAULT)
+
+#define S_MC_tRCD                 0
+#define M_MC_tRCD                 _SB_MAKEMASK(4, S_MC_tRCD)
+#define V_MC_tRCD(x)              _SB_MAKEVALUE(x, S_MC_tRCD)
+#define G_MC_tRCD(x)              _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
+#define K_MC_tRCD_DEFAULT         3
+#define V_MC_tRCD_DEFAULT         V_MC_tRCD(K_MC_tRCD_DEFAULT)
+
+#define V_MC_TIMING_DEFAULT     V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
+                                V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
+                                V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
+                                V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
+                                V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
+                                V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
+                                V_MC_tRP(K_MC_tRP_DEFAULT) | \
+                                V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
+                                V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
+                                V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
+                                M_MC_r2rIDLE_TWOCYCLES
+
+/*
+ * Errata says these are not the default
+ *                               M_MC_w2rIDLE_TWOCYCLES | \
+ *                               M_MC_r2wIDLE_TWOCYCLES | \
+ */
+
+
+/*
+ * Chip Select Start Address Register (Table 6-17)
+ */
+
+#define S_MC_CS0_START              0
+#define M_MC_CS0_START              _SB_MAKEMASK(16, S_MC_CS0_START)
+#define V_MC_CS0_START(x)           _SB_MAKEVALUE(x, S_MC_CS0_START)
+#define G_MC_CS0_START(x)           _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
+
+#define S_MC_CS1_START              16
+#define M_MC_CS1_START              _SB_MAKEMASK(16, S_MC_CS1_START)
+#define V_MC_CS1_START(x)           _SB_MAKEVALUE(x, S_MC_CS1_START)
+#define G_MC_CS1_START(x)           _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
+
+#define S_MC_CS2_START              32
+#define M_MC_CS2_START              _SB_MAKEMASK(16, S_MC_CS2_START)
+#define V_MC_CS2_START(x)           _SB_MAKEVALUE(x, S_MC_CS2_START)
+#define G_MC_CS2_START(x)           _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
+
+#define S_MC_CS3_START              48
+#define M_MC_CS3_START              _SB_MAKEMASK(16, S_MC_CS3_START)
+#define V_MC_CS3_START(x)           _SB_MAKEVALUE(x, S_MC_CS3_START)
+#define G_MC_CS3_START(x)           _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
+
+/*
+ * Chip Select End Address Register (Table 6-18)
+ */
+
+#define S_MC_CS0_END                0
+#define M_MC_CS0_END                _SB_MAKEMASK(16, S_MC_CS0_END)
+#define V_MC_CS0_END(x)             _SB_MAKEVALUE(x, S_MC_CS0_END)
+#define G_MC_CS0_END(x)             _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
+
+#define S_MC_CS1_END                16
+#define M_MC_CS1_END                _SB_MAKEMASK(16, S_MC_CS1_END)
+#define V_MC_CS1_END(x)             _SB_MAKEVALUE(x, S_MC_CS1_END)
+#define G_MC_CS1_END(x)             _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
+
+#define S_MC_CS2_END                32
+#define M_MC_CS2_END                _SB_MAKEMASK(16, S_MC_CS2_END)
+#define V_MC_CS2_END(x)             _SB_MAKEVALUE(x, S_MC_CS2_END)
+#define G_MC_CS2_END(x)             _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
+
+#define S_MC_CS3_END                48
+#define M_MC_CS3_END                _SB_MAKEMASK(16, S_MC_CS3_END)
+#define V_MC_CS3_END(x)             _SB_MAKEVALUE(x, S_MC_CS3_END)
+#define G_MC_CS3_END(x)             _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
+
+/*
+ * Chip Select Interleave Register (Table 6-19)
+ */
+
+#define S_MC_INTLV_RESERVED         0
+#define M_MC_INTLV_RESERVED         _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
+
+#define S_MC_INTERLEAVE             7
+#define M_MC_INTERLEAVE             _SB_MAKEMASK(18, S_MC_INTERLEAVE)
+#define V_MC_INTERLEAVE(x)          _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
+
+#define S_MC_INTLV_MBZ              25
+#define M_MC_INTLV_MBZ              _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
+
+/*
+ * Row Address Bits Register (Table 6-20)
+ */
+
+#define S_MC_RAS_RESERVED           0
+#define M_MC_RAS_RESERVED           _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
+
+#define S_MC_RAS_SELECT             12
+#define M_MC_RAS_SELECT             _SB_MAKEMASK(25, S_MC_RAS_SELECT)
+#define V_MC_RAS_SELECT(x)          _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
+
+#define S_MC_RAS_MBZ                37
+#define M_MC_RAS_MBZ                _SB_MAKEMASK(27, S_MC_RAS_MBZ)
+
+
+/*
+ * Column Address Bits Register (Table 6-21)
+ */
+
+#define S_MC_CAS_RESERVED           0
+#define M_MC_CAS_RESERVED           _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
+
+#define S_MC_CAS_SELECT             5
+#define M_MC_CAS_SELECT             _SB_MAKEMASK(18, S_MC_CAS_SELECT)
+#define V_MC_CAS_SELECT(x)          _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
+
+#define S_MC_CAS_MBZ                23
+#define M_MC_CAS_MBZ                _SB_MAKEMASK(41, S_MC_CAS_MBZ)
+
+
+/*
+ * Bank Address Address Bits Register (Table 6-22)
+ */
+
+#define S_MC_BA_RESERVED            0
+#define M_MC_BA_RESERVED            _SB_MAKEMASK(5, S_MC_BA_RESERVED)
+
+#define S_MC_BA_SELECT              5
+#define M_MC_BA_SELECT              _SB_MAKEMASK(20, S_MC_BA_SELECT)
+#define V_MC_BA_SELECT(x)           _SB_MAKEVALUE(x, S_MC_BA_SELECT)
+
+#define S_MC_BA_MBZ                 25
+#define M_MC_BA_MBZ                 _SB_MAKEMASK(39, S_MC_BA_MBZ)
+
+/*
+ * Chip Select Attribute Register (Table 6-23)
+ */
+
+#define K_MC_CS_ATTR_CLOSED         0
+#define K_MC_CS_ATTR_CASCHECK       1
+#define K_MC_CS_ATTR_HINT           2
+#define K_MC_CS_ATTR_OPEN           3
+
+#define S_MC_CS0_PAGE               0
+#define M_MC_CS0_PAGE               _SB_MAKEMASK(2, S_MC_CS0_PAGE)
+#define V_MC_CS0_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
+#define G_MC_CS0_PAGE(x)            _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
+
+#define S_MC_CS1_PAGE               16
+#define M_MC_CS1_PAGE               _SB_MAKEMASK(2, S_MC_CS1_PAGE)
+#define V_MC_CS1_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
+#define G_MC_CS1_PAGE(x)            _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
+
+#define S_MC_CS2_PAGE               32
+#define M_MC_CS2_PAGE               _SB_MAKEMASK(2, S_MC_CS2_PAGE)
+#define V_MC_CS2_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
+#define G_MC_CS2_PAGE(x)            _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
+
+#define S_MC_CS3_PAGE               48
+#define M_MC_CS3_PAGE               _SB_MAKEMASK(2, S_MC_CS3_PAGE)
+#define V_MC_CS3_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
+#define G_MC_CS3_PAGE(x)            _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
+
+/*
+ * ECC Test ECC Register (Table 6-25)
+ */
+
+#define S_MC_ECC_INVERT             0
+#define M_MC_ECC_INVERT             _SB_MAKEMASK(8, S_MC_ECC_INVERT)
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_regs.h b/arch/mips/include/asm/sibyte/sb1250_regs.h
new file mode 100644
index 000000000000..8f53ec817a5e
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_regs.h
@@ -0,0 +1,893 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Register Definitions                     File: sb1250_regs.h
+    *
+    *  This module contains the addresses of the on-chip peripherals
+    *  on the SB1250.
+    *
+    *  SB1250 specification level:  01/02/2002
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_REGS_H
+#define _SB1250_REGS_H
+
+#include "sb1250_defs.h"
+
+
+/*  *********************************************************************
+    *  Some general notes:
+    *
+    *  For the most part, when there is more than one peripheral
+    *  of the same type on the SOC, the constants below will be
+    *  offsets from the base of each peripheral.  For example,
+    *  the MAC registers are described as offsets from the first
+    *  MAC register, and there will be a MAC_REGISTER() macro
+    *  to calculate the base address of a given MAC.
+    *
+    *  The information in this file is based on the SB1250 SOC
+    *  manual version 0.2, July 2000.
+    ********************************************************************* */
+
+
+/*  *********************************************************************
+    * Memory Controller Registers
+    ********************************************************************* */
+
+/*
+ * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
+ * since there is one reg there (but it could get its addr/offset constant).
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
+#define A_MC_BASE_0                 0x0010051000
+#define A_MC_BASE_1                 0x0010052000
+#define MC_REGISTER_SPACING         0x1000
+
+#define A_MC_BASE(ctlid)            ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
+#define A_MC_REGISTER(ctlid, reg)    (A_MC_BASE(ctlid)+(reg))
+
+#define R_MC_CONFIG                 0x0000000100
+#define R_MC_DRAMCMD                0x0000000120
+#define R_MC_DRAMMODE               0x0000000140
+#define R_MC_TIMING1                0x0000000160
+#define R_MC_TIMING2                0x0000000180
+#define R_MC_CS_START               0x00000001A0
+#define R_MC_CS_END                 0x00000001C0
+#define R_MC_CS_INTERLEAVE          0x00000001E0
+#define S_MC_CS_STARTEND            16
+
+#define R_MC_CSX_BASE               0x0000000200
+#define R_MC_CSX_ROW                0x0000000000        /* relative to CSX_BASE, above */
+#define R_MC_CSX_COL                0x0000000020        /* relative to CSX_BASE, above */
+#define R_MC_CSX_BA                 0x0000000040        /* relative to CSX_BASE, above */
+#define MC_CSX_SPACING              0x0000000060        /* relative to CSX_BASE, above */
+
+#define R_MC_CS0_ROW                0x0000000200
+#define R_MC_CS0_COL                0x0000000220
+#define R_MC_CS0_BA                 0x0000000240
+#define R_MC_CS1_ROW                0x0000000260
+#define R_MC_CS1_COL                0x0000000280
+#define R_MC_CS1_BA                 0x00000002A0
+#define R_MC_CS2_ROW                0x00000002C0
+#define R_MC_CS2_COL                0x00000002E0
+#define R_MC_CS2_BA                 0x0000000300
+#define R_MC_CS3_ROW                0x0000000320
+#define R_MC_CS3_COL                0x0000000340
+#define R_MC_CS3_BA                 0x0000000360
+#define R_MC_CS_ATTR                0x0000000380
+#define R_MC_TEST_DATA              0x0000000400
+#define R_MC_TEST_ECC               0x0000000420
+#define R_MC_MCLK_CFG               0x0000000500
+
+#endif  /* 1250 & 112x */
+
+/*  *********************************************************************
+    * L2 Cache Control Registers
+    ********************************************************************* */
+
+#if SIBYTE_HDR_FEATURE_1250_112x        /* This L2C only on 1250/112x */
+
+#define A_L2_READ_TAG               0x0010040018
+#define A_L2_ECC_TAG                0x0010040038
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_L2_READ_MISC              0x0010040058
+#endif /* 1250 PASS3 || 112x PASS1 */
+#define A_L2_WAY_DISABLE            0x0010041000
+#define A_L2_MAKEDISABLE(x)         (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
+#define A_L2_MGMT_TAG_BASE          0x00D0000000
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_L2_CACHE_DISABLE         0x0010042000
+#define A_L2_MAKECACHEDISABLE(x)   (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
+#define A_L2_MISC_CONFIG           0x0010043000
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+/* Backward-compatibility definitions.  */
+/* XXX: discourage people from using these constants.  */
+#define A_L2_READ_ADDRESS           A_L2_READ_TAG
+#define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
+
+#endif
+
+
+/*  *********************************************************************
+    * PCI Interface Registers
+    ********************************************************************* */
+
+#if SIBYTE_HDR_FEATURE_1250_112x        /* This PCI/HT only on 1250/112x */
+#define A_PCI_TYPE00_HEADER         0x00DE000000
+#define A_PCI_TYPE01_HEADER         0x00DE000800
+#endif
+
+
+/*  *********************************************************************
+    * Ethernet DMA and MACs
+    ********************************************************************* */
+
+#define A_MAC_BASE_0                0x0010064000
+#define A_MAC_BASE_1                0x0010065000
+#if SIBYTE_HDR_FEATURE_CHIP(1250)
+#define A_MAC_BASE_2                0x0010066000
+#endif /* 1250 */
+
+#define MAC_SPACING                 0x1000
+#define MAC_DMA_TXRX_SPACING        0x0400
+#define MAC_DMA_CHANNEL_SPACING     0x0100
+#define DMA_RX                      0
+#define DMA_TX                      1
+#define MAC_NUM_DMACHAN             2               /* channels per direction */
+
+/* XXX: not correct; depends on SOC type.  */
+#define MAC_NUM_PORTS               3
+
+#define A_MAC_CHANNEL_BASE(macnum)                  \
+            (A_MAC_BASE_0 +                         \
+             MAC_SPACING*(macnum))
+
+#define A_MAC_REGISTER(macnum,reg)                  \
+            (A_MAC_BASE_0 +                         \
+             MAC_SPACING*(macnum) + (reg))
+
+
+#define R_MAC_DMA_CHANNELS              0x800 /* Relative to A_MAC_CHANNEL_BASE */
+
+#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan)  \
+             ((A_MAC_CHANNEL_BASE(macnum)) +        \
+             R_MAC_DMA_CHANNELS +                   \
+             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
+             (MAC_DMA_CHANNEL_SPACING*(chan)))
+
+#define R_MAC_DMA_CHANNEL_BASE(txrx, chan)              \
+             (R_MAC_DMA_CHANNELS +                   \
+             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
+             (MAC_DMA_CHANNEL_SPACING*(chan)))
+
+#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg)           \
+            (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) +    \
+            (reg))
+
+#define R_MAC_DMA_REGISTER(txrx, chan, reg)           \
+            (R_MAC_DMA_CHANNEL_BASE(txrx, chan) +    \
+            (reg))
+
+/*
+ * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
+ */
+
+#define R_MAC_DMA_CONFIG0               0x00000000
+#define R_MAC_DMA_CONFIG1               0x00000008
+#define R_MAC_DMA_DSCR_BASE             0x00000010
+#define R_MAC_DMA_DSCR_CNT              0x00000018
+#define R_MAC_DMA_CUR_DSCRA             0x00000020
+#define R_MAC_DMA_CUR_DSCRB             0x00000028
+#define R_MAC_DMA_CUR_DSCRADDR          0x00000030
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define R_MAC_DMA_OODPKTLOST_RX         0x00000038      /* rx only */
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*
+ * RMON Counters
+ */
+
+#define R_MAC_RMON_TX_BYTES             0x00000000
+#define R_MAC_RMON_COLLISIONS           0x00000008
+#define R_MAC_RMON_LATE_COL             0x00000010
+#define R_MAC_RMON_EX_COL               0x00000018
+#define R_MAC_RMON_FCS_ERROR            0x00000020
+#define R_MAC_RMON_TX_ABORT             0x00000028
+/* Counter #6 (0x30) now reserved */
+#define R_MAC_RMON_TX_BAD               0x00000038
+#define R_MAC_RMON_TX_GOOD              0x00000040
+#define R_MAC_RMON_TX_RUNT              0x00000048
+#define R_MAC_RMON_TX_OVERSIZE          0x00000050
+#define R_MAC_RMON_RX_BYTES             0x00000080
+#define R_MAC_RMON_RX_MCAST             0x00000088
+#define R_MAC_RMON_RX_BCAST             0x00000090
+#define R_MAC_RMON_RX_BAD               0x00000098
+#define R_MAC_RMON_RX_GOOD              0x000000A0
+#define R_MAC_RMON_RX_RUNT              0x000000A8
+#define R_MAC_RMON_RX_OVERSIZE          0x000000B0
+#define R_MAC_RMON_RX_FCS_ERROR         0x000000B8
+#define R_MAC_RMON_RX_LENGTH_ERROR      0x000000C0
+#define R_MAC_RMON_RX_CODE_ERROR        0x000000C8
+#define R_MAC_RMON_RX_ALIGN_ERROR       0x000000D0
+
+/* Updated to spec 0.2 */
+#define R_MAC_CFG                       0x00000100
+#define R_MAC_THRSH_CFG                 0x00000108
+#define R_MAC_VLANTAG                   0x00000110
+#define R_MAC_FRAMECFG                  0x00000118
+#define R_MAC_EOPCNT                    0x00000120
+#define R_MAC_FIFO_PTRS                 0x00000128
+#define R_MAC_ADFILTER_CFG              0x00000200
+#define R_MAC_ETHERNET_ADDR             0x00000208
+#define R_MAC_PKT_TYPE                  0x00000210
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define R_MAC_ADMASK0                   0x00000218
+#define R_MAC_ADMASK1                   0x00000220
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+#define R_MAC_HASH_BASE                 0x00000240
+#define R_MAC_ADDR_BASE                 0x00000280
+#define R_MAC_CHLO0_BASE                0x00000300
+#define R_MAC_CHUP0_BASE                0x00000320
+#define R_MAC_ENABLE                    0x00000400
+#define R_MAC_STATUS                    0x00000408
+#define R_MAC_INT_MASK                  0x00000410
+#define R_MAC_TXD_CTL                   0x00000420
+#define R_MAC_MDIO                      0x00000428
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define R_MAC_STATUS1                   0x00000430
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+#define R_MAC_DEBUG_STATUS              0x00000448
+
+#define MAC_HASH_COUNT                  8
+#define MAC_ADDR_COUNT                  8
+#define MAC_CHMAP_COUNT                 4
+
+
+/*  *********************************************************************
+    * DUART Registers
+    ********************************************************************* */
+
+
+#if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */
+#define R_DUART_NUM_PORTS           2
+
+#define A_DUART                     0x0010060000
+
+#define DUART_CHANREG_SPACING       0x100
+
+#define A_DUART_CHANREG(chan, reg)                                      \
+        (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg))
+#endif  /* 1250 & 112x */
+
+#define R_DUART_MODE_REG_1          0x000
+#define R_DUART_MODE_REG_2          0x010
+#define R_DUART_STATUS              0x020
+#define R_DUART_CLK_SEL             0x030
+#define R_DUART_CMD                 0x050
+#define R_DUART_RX_HOLD             0x060
+#define R_DUART_TX_HOLD             0x070
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define R_DUART_FULL_CTL            0x040
+#define R_DUART_OPCR_X              0x080
+#define R_DUART_AUXCTL_X            0x090
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+
+/*
+ * The IMR and ISR can't be addressed with A_DUART_CHANREG,
+ * so use these macros instead.
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */
+#define DUART_IMRISR_SPACING        0x20
+#define DUART_INCHNG_SPACING        0x10
+
+#define A_DUART_CTRLREG(reg)                                            \
+        (A_DUART + DUART_CHANREG_SPACING * 3 + (reg))
+
+#define R_DUART_IMRREG(chan)                                            \
+        (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING)
+#define R_DUART_ISRREG(chan)                                            \
+        (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING)
+#define R_DUART_INCHREG(chan)                                           \
+        (R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING)
+
+#define A_DUART_IMRREG(chan)        A_DUART_CTRLREG(R_DUART_IMRREG(chan))
+#define A_DUART_ISRREG(chan)        A_DUART_CTRLREG(R_DUART_ISRREG(chan))
+#define A_DUART_INCHREG(chan)       A_DUART_CTRLREG(R_DUART_INCHREG(chan))
+#endif  /* 1250 & 112x */
+
+#define R_DUART_AUX_CTRL            0x010
+#define R_DUART_ISR_A               0x020
+#define R_DUART_IMR_A               0x030
+#define R_DUART_ISR_B               0x040
+#define R_DUART_IMR_B               0x050
+#define R_DUART_OUT_PORT            0x060
+#define R_DUART_OPCR                0x070
+#define R_DUART_IN_PORT             0x080
+
+#define R_DUART_SET_OPR             0x0B0
+#define R_DUART_CLEAR_OPR           0x0C0
+#define R_DUART_IN_CHNG_A           0x0D0
+#define R_DUART_IN_CHNG_B           0x0E0
+
+
+/*
+ * These constants are the absolute addresses.
+ */
+
+#define A_DUART_MODE_REG_1_A        0x0010060100
+#define A_DUART_MODE_REG_2_A        0x0010060110
+#define A_DUART_STATUS_A            0x0010060120
+#define A_DUART_CLK_SEL_A           0x0010060130
+#define A_DUART_CMD_A               0x0010060150
+#define A_DUART_RX_HOLD_A           0x0010060160
+#define A_DUART_TX_HOLD_A           0x0010060170
+
+#define A_DUART_MODE_REG_1_B        0x0010060200
+#define A_DUART_MODE_REG_2_B        0x0010060210
+#define A_DUART_STATUS_B            0x0010060220
+#define A_DUART_CLK_SEL_B           0x0010060230
+#define A_DUART_CMD_B               0x0010060250
+#define A_DUART_RX_HOLD_B           0x0010060260
+#define A_DUART_TX_HOLD_B           0x0010060270
+
+#define A_DUART_INPORT_CHNG         0x0010060300
+#define A_DUART_AUX_CTRL            0x0010060310
+#define A_DUART_ISR_A               0x0010060320
+#define A_DUART_IMR_A               0x0010060330
+#define A_DUART_ISR_B               0x0010060340
+#define A_DUART_IMR_B               0x0010060350
+#define A_DUART_OUT_PORT            0x0010060360
+#define A_DUART_OPCR                0x0010060370
+#define A_DUART_IN_PORT             0x0010060380
+#define A_DUART_ISR                 0x0010060390
+#define A_DUART_IMR                 0x00100603A0
+#define A_DUART_SET_OPR             0x00100603B0
+#define A_DUART_CLEAR_OPR           0x00100603C0
+#define A_DUART_INPORT_CHNG_A       0x00100603D0
+#define A_DUART_INPORT_CHNG_B       0x00100603E0
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_DUART_FULL_CTL_A          0x0010060140
+#define A_DUART_FULL_CTL_B          0x0010060240
+
+#define A_DUART_OPCR_A              0x0010060180
+#define A_DUART_OPCR_B              0x0010060280
+
+#define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+
+/*  *********************************************************************
+    * Synchronous Serial Registers
+    ********************************************************************* */
+
+
+#if SIBYTE_HDR_FEATURE_1250_112x        /* sync serial only on 1250/112x */
+
+#define A_SER_BASE_0                0x0010060400
+#define A_SER_BASE_1                0x0010060800
+#define SER_SPACING                 0x400
+
+#define SER_DMA_TXRX_SPACING        0x80
+
+#define SER_NUM_PORTS               2
+
+#define A_SER_CHANNEL_BASE(sernum)                  \
+            (A_SER_BASE_0 +                         \
+             SER_SPACING*(sernum))
+
+#define A_SER_REGISTER(sernum,reg)                  \
+            (A_SER_BASE_0 +                         \
+             SER_SPACING*(sernum) + (reg))
+
+
+#define R_SER_DMA_CHANNELS              0   /* Relative to A_SER_BASE_x */
+
+#define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \
+             ((A_SER_CHANNEL_BASE(sernum)) +        \
+             R_SER_DMA_CHANNELS +                   \
+             (SER_DMA_TXRX_SPACING*(txrx)))
+
+#define A_SER_DMA_REGISTER(sernum, txrx, reg)           \
+            (A_SER_DMA_CHANNEL_BASE(sernum, txrx) +    \
+            (reg))
+
+
+/*
+ * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
+ */
+
+#define R_SER_DMA_CONFIG0           0x00000000
+#define R_SER_DMA_CONFIG1           0x00000008
+#define R_SER_DMA_DSCR_BASE         0x00000010
+#define R_SER_DMA_DSCR_CNT          0x00000018
+#define R_SER_DMA_CUR_DSCRA         0x00000020
+#define R_SER_DMA_CUR_DSCRB         0x00000028
+#define R_SER_DMA_CUR_DSCRADDR      0x00000030
+
+#define R_SER_DMA_CONFIG0_RX        0x00000000
+#define R_SER_DMA_CONFIG1_RX        0x00000008
+#define R_SER_DMA_DSCR_BASE_RX      0x00000010
+#define R_SER_DMA_DSCR_COUNT_RX     0x00000018
+#define R_SER_DMA_CUR_DSCR_A_RX     0x00000020
+#define R_SER_DMA_CUR_DSCR_B_RX     0x00000028
+#define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030
+
+#define R_SER_DMA_CONFIG0_TX        0x00000080
+#define R_SER_DMA_CONFIG1_TX        0x00000088
+#define R_SER_DMA_DSCR_BASE_TX      0x00000090
+#define R_SER_DMA_DSCR_COUNT_TX     0x00000098
+#define R_SER_DMA_CUR_DSCR_A_TX     0x000000A0
+#define R_SER_DMA_CUR_DSCR_B_TX     0x000000A8
+#define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0
+
+#define R_SER_MODE                  0x00000100
+#define R_SER_MINFRM_SZ             0x00000108
+#define R_SER_MAXFRM_SZ             0x00000110
+#define R_SER_ADDR                  0x00000118
+#define R_SER_USR0_ADDR             0x00000120
+#define R_SER_USR1_ADDR             0x00000128
+#define R_SER_USR2_ADDR             0x00000130
+#define R_SER_USR3_ADDR             0x00000138
+#define R_SER_CMD                   0x00000140
+#define R_SER_TX_RD_THRSH           0x00000160
+#define R_SER_TX_WR_THRSH           0x00000168
+#define R_SER_RX_RD_THRSH           0x00000170
+#define R_SER_LINE_MODE             0x00000178
+#define R_SER_DMA_ENABLE            0x00000180
+#define R_SER_INT_MASK              0x00000190
+#define R_SER_STATUS                0x00000188
+#define R_SER_STATUS_DEBUG          0x000001A8
+#define R_SER_RX_TABLE_BASE         0x00000200
+#define SER_RX_TABLE_COUNT          16
+#define R_SER_TX_TABLE_BASE         0x00000300
+#define SER_TX_TABLE_COUNT          16
+
+/* RMON Counters */
+#define R_SER_RMON_TX_BYTE_LO       0x000001C0
+#define R_SER_RMON_TX_BYTE_HI       0x000001C8
+#define R_SER_RMON_RX_BYTE_LO       0x000001D0
+#define R_SER_RMON_RX_BYTE_HI       0x000001D8
+#define R_SER_RMON_TX_UNDERRUN      0x000001E0
+#define R_SER_RMON_RX_OVERFLOW      0x000001E8
+#define R_SER_RMON_RX_ERRORS        0x000001F0
+#define R_SER_RMON_RX_BADADDR       0x000001F8
+
+#endif  /* 1250/112x */
+
+/*  *********************************************************************
+    * Generic Bus Registers
+    ********************************************************************* */
+
+#define IO_EXT_CFG_COUNT            8
+
+#define A_IO_EXT_BASE               0x0010061000
+#define A_IO_EXT_REG(r)             (A_IO_EXT_BASE + (r))
+
+#define A_IO_EXT_CFG_BASE           0x0010061000
+#define A_IO_EXT_MULT_SIZE_BASE     0x0010061100
+#define A_IO_EXT_START_ADDR_BASE    0x0010061200
+#define A_IO_EXT_TIME_CFG0_BASE     0x0010061600
+#define A_IO_EXT_TIME_CFG1_BASE     0x0010061700
+
+#define IO_EXT_REGISTER_SPACING     8
+#define A_IO_EXT_CS_BASE(cs)        (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
+#define R_IO_EXT_REG(reg, cs)       ((cs)*IO_EXT_REGISTER_SPACING + (reg))
+
+#define R_IO_EXT_CFG                0x0000
+#define R_IO_EXT_MULT_SIZE          0x0100
+#define R_IO_EXT_START_ADDR         0x0200
+#define R_IO_EXT_TIME_CFG0          0x0600
+#define R_IO_EXT_TIME_CFG1          0x0700
+
+
+#define A_IO_INTERRUPT_STATUS       0x0010061A00
+#define A_IO_INTERRUPT_DATA0        0x0010061A10
+#define A_IO_INTERRUPT_DATA1        0x0010061A18
+#define A_IO_INTERRUPT_DATA2        0x0010061A20
+#define A_IO_INTERRUPT_DATA3        0x0010061A28
+#define A_IO_INTERRUPT_ADDR0        0x0010061A30
+#define A_IO_INTERRUPT_ADDR1        0x0010061A40
+#define A_IO_INTERRUPT_PARITY       0x0010061A50
+#define A_IO_PCMCIA_CFG             0x0010061A60
+#define A_IO_PCMCIA_STATUS          0x0010061A70
+#define A_IO_DRIVE_0                0x0010061300
+#define A_IO_DRIVE_1                0x0010061308
+#define A_IO_DRIVE_2                0x0010061310
+#define A_IO_DRIVE_3                0x0010061318
+#define A_IO_DRIVE_BASE             A_IO_DRIVE_0
+#define IO_DRIVE_REGISTER_SPACING   8
+#define R_IO_DRIVE(x)               ((x)*IO_DRIVE_REGISTER_SPACING)
+#define A_IO_DRIVE(x)               (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
+
+#define R_IO_INTERRUPT_STATUS       0x0A00
+#define R_IO_INTERRUPT_DATA0        0x0A10
+#define R_IO_INTERRUPT_DATA1        0x0A18
+#define R_IO_INTERRUPT_DATA2        0x0A20
+#define R_IO_INTERRUPT_DATA3        0x0A28
+#define R_IO_INTERRUPT_ADDR0        0x0A30
+#define R_IO_INTERRUPT_ADDR1        0x0A40
+#define R_IO_INTERRUPT_PARITY       0x0A50
+#define R_IO_PCMCIA_CFG             0x0A60
+#define R_IO_PCMCIA_STATUS          0x0A70
+
+/*  *********************************************************************
+    * GPIO Registers
+    ********************************************************************* */
+
+#define A_GPIO_CLR_EDGE             0x0010061A80
+#define A_GPIO_INT_TYPE             0x0010061A88
+#define A_GPIO_INPUT_INVERT         0x0010061A90
+#define A_GPIO_GLITCH               0x0010061A98
+#define A_GPIO_READ                 0x0010061AA0
+#define A_GPIO_DIRECTION            0x0010061AA8
+#define A_GPIO_PIN_CLR              0x0010061AB0
+#define A_GPIO_PIN_SET              0x0010061AB8
+
+#define A_GPIO_BASE                 0x0010061A80
+
+#define R_GPIO_CLR_EDGE             0x00
+#define R_GPIO_INT_TYPE             0x08
+#define R_GPIO_INPUT_INVERT         0x10
+#define R_GPIO_GLITCH               0x18
+#define R_GPIO_READ                 0x20
+#define R_GPIO_DIRECTION            0x28
+#define R_GPIO_PIN_CLR              0x30
+#define R_GPIO_PIN_SET              0x38
+
+/*  *********************************************************************
+    * SMBus Registers
+    ********************************************************************* */
+
+#define A_SMB_XTRA_0                0x0010060000
+#define A_SMB_XTRA_1                0x0010060008
+#define A_SMB_FREQ_0                0x0010060010
+#define A_SMB_FREQ_1                0x0010060018
+#define A_SMB_STATUS_0              0x0010060020
+#define A_SMB_STATUS_1              0x0010060028
+#define A_SMB_CMD_0                 0x0010060030
+#define A_SMB_CMD_1                 0x0010060038
+#define A_SMB_START_0               0x0010060040
+#define A_SMB_START_1               0x0010060048
+#define A_SMB_DATA_0                0x0010060050
+#define A_SMB_DATA_1                0x0010060058
+#define A_SMB_CONTROL_0             0x0010060060
+#define A_SMB_CONTROL_1             0x0010060068
+#define A_SMB_PEC_0                 0x0010060070
+#define A_SMB_PEC_1                 0x0010060078
+
+#define A_SMB_0                     0x0010060000
+#define A_SMB_1                     0x0010060008
+#define SMB_REGISTER_SPACING        0x8
+#define A_SMB_BASE(idx)             (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
+#define A_SMB_REGISTER(idx, reg)    (A_SMB_BASE(idx)+(reg))
+
+#define R_SMB_XTRA                  0x0000000000
+#define R_SMB_FREQ                  0x0000000010
+#define R_SMB_STATUS                0x0000000020
+#define R_SMB_CMD                   0x0000000030
+#define R_SMB_START                 0x0000000040
+#define R_SMB_DATA                  0x0000000050
+#define R_SMB_CONTROL               0x0000000060
+#define R_SMB_PEC                   0x0000000070
+
+/*  *********************************************************************
+    * Timer Registers
+    ********************************************************************* */
+
+/*
+ * Watchdog timers
+ */
+
+#define A_SCD_WDOG_0                0x0010020050
+#define A_SCD_WDOG_1                0x0010020150
+#define SCD_WDOG_SPACING            0x100
+#define SCD_NUM_WDOGS               2
+#define A_SCD_WDOG_BASE(w)          (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
+#define A_SCD_WDOG_REGISTER(w, r)   (A_SCD_WDOG_BASE(w) + (r))
+
+#define R_SCD_WDOG_INIT             0x0000000000
+#define R_SCD_WDOG_CNT              0x0000000008
+#define R_SCD_WDOG_CFG              0x0000000010
+
+#define A_SCD_WDOG_INIT_0           0x0010020050
+#define A_SCD_WDOG_CNT_0            0x0010020058
+#define A_SCD_WDOG_CFG_0            0x0010020060
+
+#define A_SCD_WDOG_INIT_1           0x0010020150
+#define A_SCD_WDOG_CNT_1            0x0010020158
+#define A_SCD_WDOG_CFG_1            0x0010020160
+
+/*
+ * Generic timers
+ */
+
+#define A_SCD_TIMER_0               0x0010020070
+#define A_SCD_TIMER_1               0x0010020078
+#define A_SCD_TIMER_2               0x0010020170
+#define A_SCD_TIMER_3               0x0010020178
+#define SCD_NUM_TIMERS              4
+#define A_SCD_TIMER_BASE(w)         (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
+#define A_SCD_TIMER_REGISTER(w, r)  (A_SCD_TIMER_BASE(w) + (r))
+
+#define R_SCD_TIMER_INIT            0x0000000000
+#define R_SCD_TIMER_CNT             0x0000000010
+#define R_SCD_TIMER_CFG             0x0000000020
+
+#define A_SCD_TIMER_INIT_0          0x0010020070
+#define A_SCD_TIMER_CNT_0           0x0010020080
+#define A_SCD_TIMER_CFG_0           0x0010020090
+
+#define A_SCD_TIMER_INIT_1          0x0010020078
+#define A_SCD_TIMER_CNT_1           0x0010020088
+#define A_SCD_TIMER_CFG_1           0x0010020098
+
+#define A_SCD_TIMER_INIT_2          0x0010020170
+#define A_SCD_TIMER_CNT_2           0x0010020180
+#define A_SCD_TIMER_CFG_2           0x0010020190
+
+#define A_SCD_TIMER_INIT_3          0x0010020178
+#define A_SCD_TIMER_CNT_3           0x0010020188
+#define A_SCD_TIMER_CFG_3           0x0010020198
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_SCD_SCRATCH              0x0010020C10
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define A_SCD_ZBBUS_CYCLE_COUNT    0x0010030000
+#define A_SCD_ZBBUS_CYCLE_CP0      0x0010020C00
+#define A_SCD_ZBBUS_CYCLE_CP1      0x0010020C08
+#endif
+
+/*  *********************************************************************
+    * System Control Registers
+    ********************************************************************* */
+
+#define A_SCD_SYSTEM_REVISION       0x0010020000
+#define A_SCD_SYSTEM_CFG            0x0010020008
+#define A_SCD_SYSTEM_MANUF          0x0010038000
+
+/*  *********************************************************************
+    * System Address Trap Registers
+    ********************************************************************* */
+
+#define A_ADDR_TRAP_INDEX           0x00100200B0
+#define A_ADDR_TRAP_REG             0x00100200B8
+#define A_ADDR_TRAP_UP_0            0x0010020400
+#define A_ADDR_TRAP_UP_1            0x0010020408
+#define A_ADDR_TRAP_UP_2            0x0010020410
+#define A_ADDR_TRAP_UP_3            0x0010020418
+#define A_ADDR_TRAP_DOWN_0          0x0010020420
+#define A_ADDR_TRAP_DOWN_1          0x0010020428
+#define A_ADDR_TRAP_DOWN_2          0x0010020430
+#define A_ADDR_TRAP_DOWN_3          0x0010020438
+#define A_ADDR_TRAP_CFG_0           0x0010020440
+#define A_ADDR_TRAP_CFG_1           0x0010020448
+#define A_ADDR_TRAP_CFG_2           0x0010020450
+#define A_ADDR_TRAP_CFG_3           0x0010020458
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define A_ADDR_TRAP_REG_DEBUG       0x0010020460
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#define ADDR_TRAP_SPACING 8
+#define NUM_ADDR_TRAP 4
+#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING))
+#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING))
+#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING))
+
+
+/*  *********************************************************************
+    * System Interrupt Mapper Registers
+    ********************************************************************* */
+
+#define A_IMR_CPU0_BASE                 0x0010020000
+#define A_IMR_CPU1_BASE                 0x0010022000
+#define IMR_REGISTER_SPACING            0x2000
+#define IMR_REGISTER_SPACING_SHIFT      13
+
+#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
+#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg))
+
+#define R_IMR_INTERRUPT_DIAG            0x0010
+#define R_IMR_INTERRUPT_LDT             0x0018
+#define R_IMR_INTERRUPT_MASK            0x0028
+#define R_IMR_INTERRUPT_TRACE           0x0038
+#define R_IMR_INTERRUPT_SOURCE_STATUS   0x0040
+#define R_IMR_LDT_INTERRUPT_SET         0x0048
+#define R_IMR_LDT_INTERRUPT             0x0018
+#define R_IMR_LDT_INTERRUPT_CLR         0x0020
+#define R_IMR_MAILBOX_CPU               0x00c0
+#define R_IMR_ALIAS_MAILBOX_CPU         0x1000
+#define R_IMR_MAILBOX_SET_CPU           0x00C8
+#define R_IMR_ALIAS_MAILBOX_SET_CPU     0x1008
+#define R_IMR_MAILBOX_CLR_CPU           0x00D0
+#define R_IMR_INTERRUPT_STATUS_BASE     0x0100
+#define R_IMR_INTERRUPT_STATUS_COUNT    7
+#define R_IMR_INTERRUPT_MAP_BASE        0x0200
+#define R_IMR_INTERRUPT_MAP_COUNT       64
+
+/*
+ * these macros work together to build the address of a mailbox
+ * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1)
+ * for mbox_0_set_cpu2 returns 0x00100240C8
+ */
+#define A_MAILBOX_REGISTER(reg,cpu) \
+    (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
+
+/*  *********************************************************************
+    * System Performance Counter Registers
+    ********************************************************************* */
+
+#define A_SCD_PERF_CNT_CFG          0x00100204C0
+#define A_SCD_PERF_CNT_0            0x00100204D0
+#define A_SCD_PERF_CNT_1            0x00100204D8
+#define A_SCD_PERF_CNT_2            0x00100204E0
+#define A_SCD_PERF_CNT_3            0x00100204E8
+
+#define SCD_NUM_PERF_CNT 4
+#define SCD_PERF_CNT_SPACING 8
+#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING))
+
+/*  *********************************************************************
+    * System Bus Watcher Registers
+    ********************************************************************* */
+
+#define A_SCD_BUS_ERR_STATUS        0x0010020880
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0
+#define A_BUS_ERR_STATUS_DEBUG  0x00100208D0
+#endif /* 1250 PASS2 || 112x PASS1 */
+#define A_BUS_ERR_DATA_0            0x00100208A0
+#define A_BUS_ERR_DATA_1            0x00100208A8
+#define A_BUS_ERR_DATA_2            0x00100208B0
+#define A_BUS_ERR_DATA_3            0x00100208B8
+#define A_BUS_L2_ERRORS             0x00100208C0
+#define A_BUS_MEM_IO_ERRORS         0x00100208C8
+
+/*  *********************************************************************
+    * System Debug Controller Registers
+    ********************************************************************* */
+
+#define A_SCD_JTAG_BASE             0x0010000000
+
+/*  *********************************************************************
+    * System Trace Buffer Registers
+    ********************************************************************* */
+
+#define A_SCD_TRACE_CFG             0x0010020A00
+#define A_SCD_TRACE_READ            0x0010020A08
+#define A_SCD_TRACE_EVENT_0         0x0010020A20
+#define A_SCD_TRACE_EVENT_1         0x0010020A28
+#define A_SCD_TRACE_EVENT_2         0x0010020A30
+#define A_SCD_TRACE_EVENT_3         0x0010020A38
+#define A_SCD_TRACE_SEQUENCE_0      0x0010020A40
+#define A_SCD_TRACE_SEQUENCE_1      0x0010020A48
+#define A_SCD_TRACE_SEQUENCE_2      0x0010020A50
+#define A_SCD_TRACE_SEQUENCE_3      0x0010020A58
+#define A_SCD_TRACE_EVENT_4         0x0010020A60
+#define A_SCD_TRACE_EVENT_5         0x0010020A68
+#define A_SCD_TRACE_EVENT_6         0x0010020A70
+#define A_SCD_TRACE_EVENT_7         0x0010020A78
+#define A_SCD_TRACE_SEQUENCE_4      0x0010020A80
+#define A_SCD_TRACE_SEQUENCE_5      0x0010020A88
+#define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
+#define A_SCD_TRACE_SEQUENCE_7      0x0010020A98
+
+#define TRACE_REGISTER_SPACING 8
+#define TRACE_NUM_REGISTERS    8
+#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \
+   (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
+   (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING)))
+#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \
+   (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
+   (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING)))
+
+/*  *********************************************************************
+    * System Generic DMA Registers
+    ********************************************************************* */
+
+#define A_DM_0                      0x0010020B00
+#define A_DM_1                      0x0010020B20
+#define A_DM_2                      0x0010020B40
+#define A_DM_3                      0x0010020B60
+#define DM_REGISTER_SPACING         0x20
+#define DM_NUM_CHANNELS             4
+#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
+#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg))
+
+#define R_DM_DSCR_BASE              0x0000000000
+#define R_DM_DSCR_COUNT             0x0000000008
+#define R_DM_CUR_DSCR_ADDR          0x0000000010
+#define R_DM_DSCR_BASE_DEBUG        0x0000000018
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_DM_PARTIAL_0              0x0010020ba0
+#define A_DM_PARTIAL_1              0x0010020ba8
+#define A_DM_PARTIAL_2              0x0010020bb0
+#define A_DM_PARTIAL_3              0x0010020bb8
+#define DM_PARTIAL_REGISTER_SPACING 0x8
+#define A_DM_PARTIAL(idx)           (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define A_DM_CRC_0                  0x0010020b80
+#define A_DM_CRC_1                  0x0010020b90
+#define DM_CRC_REGISTER_SPACING     0x10
+#define DM_CRC_NUM_CHANNELS         2
+#define A_DM_CRC_BASE(idx)          (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
+#define A_DM_CRC_REGISTER(idx, reg)  (A_DM_CRC_BASE(idx) + (reg))
+
+#define R_CRC_DEF_0                 0x00
+#define R_CTCP_DEF_0                0x08
+#endif /* 1250 PASS3 || 112x PASS1 */
+
+/*  *********************************************************************
+    *  Physical Address Map
+    ********************************************************************* */
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
+#define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
+#define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
+#define A_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
+#define A_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
+#define A_PHYS_GENBUS_END               _SB_MAKE64(0x0040000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BITS_32  _SB_MAKE64(0x0060000000)
+#define A_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
+#define A_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
+#define A_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
+#define A_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
+#define A_PHYS_LDT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BYTES    _SB_MAKE64(0x00DC000000)
+#define A_PHYS_LDTPCI_CFG_MATCH_BYTES   _SB_MAKE64(0x00DE000000)
+#define A_PHYS_LDT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BITS     _SB_MAKE64(0x00FC000000)
+#define A_PHYS_LDTPCI_CFG_MATCH_BITS    _SB_MAKE64(0x00FE000000)
+#define A_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
+#define A_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
+#define A_PHYS_LDT_EXP                  _SB_MAKE64(0x8000000000)
+#define A_PHYS_PCI_FULLACCESS_BYTES     _SB_MAKE64(0xF000000000)
+#define A_PHYS_PCI_FULLACCESS_BITS      _SB_MAKE64(0xF100000000)
+#define A_PHYS_RESERVED                 _SB_MAKE64(0xF200000000)
+#define A_PHYS_RESERVED_SPECIAL_LDT     _SB_MAKE64(0xFD00000000)
+
+#define A_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
+#define PHYS_L2CACHE_NUM_WAYS           4
+#define A_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000080000)
+#define A_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0180000)
+#define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
+#define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
+#define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)
+#endif
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_scd.h b/arch/mips/include/asm/sibyte/sb1250_scd.h
new file mode 100644
index 000000000000..e49c3e89b5ee
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_scd.h
@@ -0,0 +1,654 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  SCD Constants and Macros                 File: sb1250_scd.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the System Control and Debug module on the 1250.
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003,2004,2005
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+#ifndef _SB1250_SCD_H
+#define _SB1250_SCD_H
+
+#include "sb1250_defs.h"
+
+/*  *********************************************************************
+    *  System control/debug registers
+    ********************************************************************* */
+
+/*
+ * System Revision Register (Table 4-1)
+ */
+
+#define M_SYS_RESERVED              _SB_MAKEMASK(8, 0)
+
+#define S_SYS_REVISION              _SB_MAKE64(8)
+#define M_SYS_REVISION              _SB_MAKEMASK(8, S_SYS_REVISION)
+#define V_SYS_REVISION(x)           _SB_MAKEVALUE(x, S_SYS_REVISION)
+#define G_SYS_REVISION(x)           _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)
+
+#define K_SYS_REVISION_BCM1250_PASS1    0x01
+
+#define K_SYS_REVISION_BCM1250_PASS2    0x03
+#define K_SYS_REVISION_BCM1250_A1       0x03    /* Pass 2.0 WB */
+#define K_SYS_REVISION_BCM1250_A2       0x04    /* Pass 2.0 FC */
+#define K_SYS_REVISION_BCM1250_A3       0x05    /* Pass 2.1 FC */
+#define K_SYS_REVISION_BCM1250_A4       0x06    /* Pass 2.1 WB */
+#define K_SYS_REVISION_BCM1250_A6       0x07    /* OR 0x04 (A2) w/WID != 0 */
+#define K_SYS_REVISION_BCM1250_A8       0x0b    /* A8/A10 */
+#define K_SYS_REVISION_BCM1250_A9       0x08
+#define K_SYS_REVISION_BCM1250_A10      K_SYS_REVISION_BCM1250_A8
+
+#define K_SYS_REVISION_BCM1250_PASS2_2  0x10
+#define K_SYS_REVISION_BCM1250_B0       K_SYS_REVISION_BCM1250_B1
+#define K_SYS_REVISION_BCM1250_B1       0x10
+#define K_SYS_REVISION_BCM1250_B2       0x11
+
+#define K_SYS_REVISION_BCM1250_C0       0x20
+#define K_SYS_REVISION_BCM1250_C1       0x21
+#define K_SYS_REVISION_BCM1250_C2       0x22
+#define K_SYS_REVISION_BCM1250_C3       0x23
+
+#if SIBYTE_HDR_FEATURE_CHIP(1250)
+/* XXX: discourage people from using these constants.  */
+#define K_SYS_REVISION_PASS1        K_SYS_REVISION_BCM1250_PASS1
+#define K_SYS_REVISION_PASS2        K_SYS_REVISION_BCM1250_PASS2
+#define K_SYS_REVISION_PASS2_2      K_SYS_REVISION_BCM1250_PASS2_2
+#define K_SYS_REVISION_PASS3        K_SYS_REVISION_BCM1250_PASS3
+#define K_SYS_REVISION_BCM1250_PASS3    K_SYS_REVISION_BCM1250_C0
+#endif /* 1250 */
+
+#define K_SYS_REVISION_BCM112x_A1       0x20
+#define K_SYS_REVISION_BCM112x_A2       0x21
+#define K_SYS_REVISION_BCM112x_A3       0x22
+#define K_SYS_REVISION_BCM112x_A4       0x23
+#define K_SYS_REVISION_BCM112x_B0       0x30
+
+#define K_SYS_REVISION_BCM1480_S0       0x01
+#define K_SYS_REVISION_BCM1480_A1       0x02
+#define K_SYS_REVISION_BCM1480_A2       0x03
+#define K_SYS_REVISION_BCM1480_A3       0x04
+#define K_SYS_REVISION_BCM1480_B0       0x11
+
+/*Cache size - 23:20  of revision register*/
+#define S_SYS_L2C_SIZE            _SB_MAKE64(20)
+#define M_SYS_L2C_SIZE            _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
+#define V_SYS_L2C_SIZE(x)         _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
+#define G_SYS_L2C_SIZE(x)         _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)
+
+#define K_SYS_L2C_SIZE_1MB      0
+#define K_SYS_L2C_SIZE_512KB    5
+#define K_SYS_L2C_SIZE_256KB    2
+#define K_SYS_L2C_SIZE_128KB    1
+
+#define K_SYS_L2C_SIZE_BCM1250  K_SYS_L2C_SIZE_512KB
+#define K_SYS_L2C_SIZE_BCM1125  K_SYS_L2C_SIZE_256KB
+#define K_SYS_L2C_SIZE_BCM1122  K_SYS_L2C_SIZE_128KB
+
+
+/* Number of CPU cores, bits 27:24  of revision register*/
+#define S_SYS_NUM_CPUS            _SB_MAKE64(24)
+#define M_SYS_NUM_CPUS            _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
+#define V_SYS_NUM_CPUS(x)         _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
+#define G_SYS_NUM_CPUS(x)         _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)
+
+
+/* XXX: discourage people from using these constants.  */
+#define S_SYS_PART                  _SB_MAKE64(16)
+#define M_SYS_PART                  _SB_MAKEMASK(16, S_SYS_PART)
+#define V_SYS_PART(x)               _SB_MAKEVALUE(x, S_SYS_PART)
+#define G_SYS_PART(x)               _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)
+
+/* XXX: discourage people from using these constants.  */
+#define K_SYS_PART_SB1250           0x1250
+#define K_SYS_PART_BCM1120          0x1121
+#define K_SYS_PART_BCM1125          0x1123
+#define K_SYS_PART_BCM1125H         0x1124
+#define K_SYS_PART_BCM1122          0x1113
+
+
+/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */
+#define S_SYS_SOC_TYPE              _SB_MAKE64(16)
+#define M_SYS_SOC_TYPE              _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
+#define V_SYS_SOC_TYPE(x)           _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
+#define G_SYS_SOC_TYPE(x)           _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
+
+#define K_SYS_SOC_TYPE_BCM1250      0x0
+#define K_SYS_SOC_TYPE_BCM1120      0x1
+#define K_SYS_SOC_TYPE_BCM1250_ALT  0x2         /* 1250pass2 w/ 1/4 L2.  */
+#define K_SYS_SOC_TYPE_BCM1125      0x3
+#define K_SYS_SOC_TYPE_BCM1125H     0x4
+#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5         /* 1250pass2 w/ 1/2 L2.  */
+#define K_SYS_SOC_TYPE_BCM1x80      0x6
+#define K_SYS_SOC_TYPE_BCM1x55      0x7
+
+/*
+ * Calculate correct SOC type given a copy of system revision register.
+ *
+ * (For the assembler version, sysrev and dest may be the same register.
+ * Also, it clobbers AT.)
+ */
+#ifdef __ASSEMBLER__
+#define SYS_SOC_TYPE(dest, sysrev)                                      \
+        .set push ;                                                     \
+        .set reorder ;                                                  \
+        dsrl    dest, sysrev, S_SYS_SOC_TYPE ;                          \
+        andi    dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE);         \
+        beq     dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ;                \
+        beq     dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f  ;              \
+        b       992f ;                                                  \
+991:    li      dest, K_SYS_SOC_TYPE_BCM1250 ;                          \
+992:                                                                    \
+        .set pop
+#else
+#define SYS_SOC_TYPE(sysrev)                                            \
+        ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT          \
+          || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2)     \
+         ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
+#endif
+
+#define S_SYS_WID                   _SB_MAKE64(32)
+#define M_SYS_WID                   _SB_MAKEMASK(32, S_SYS_WID)
+#define V_SYS_WID(x)                _SB_MAKEVALUE(x, S_SYS_WID)
+#define G_SYS_WID(x)                _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)
+
+/*
+ * System Manufacturing Register
+ * Register: SCD_SYSTEM_MANUF
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+/* Wafer ID: bits 31:0 */
+#define S_SYS_WAFERID1_200        _SB_MAKE64(0)
+#define M_SYS_WAFERID1_200        _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
+#define V_SYS_WAFERID1_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
+#define G_SYS_WAFERID1_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)
+
+#define S_SYS_BIN                 _SB_MAKE64(32)
+#define M_SYS_BIN                 _SB_MAKEMASK(4, S_SYS_BIN)
+#define V_SYS_BIN(x)              _SB_MAKEVALUE(x, S_SYS_BIN)
+#define G_SYS_BIN(x)              _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)
+
+/* Wafer ID: bits 39:36 */
+#define S_SYS_WAFERID2_200        _SB_MAKE64(36)
+#define M_SYS_WAFERID2_200        _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
+#define V_SYS_WAFERID2_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
+#define G_SYS_WAFERID2_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)
+
+/* Wafer ID: bits 39:0 */
+#define S_SYS_WAFERID_300         _SB_MAKE64(0)
+#define M_SYS_WAFERID_300         _SB_MAKEMASK(40, S_SYS_WAFERID_300)
+#define V_SYS_WAFERID_300(x)      _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
+#define G_SYS_WAFERID_300(x)      _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
+
+#define S_SYS_XPOS                _SB_MAKE64(40)
+#define M_SYS_XPOS                _SB_MAKEMASK(6, S_SYS_XPOS)
+#define V_SYS_XPOS(x)             _SB_MAKEVALUE(x, S_SYS_XPOS)
+#define G_SYS_XPOS(x)             _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
+
+#define S_SYS_YPOS                _SB_MAKE64(46)
+#define M_SYS_YPOS                _SB_MAKEMASK(6, S_SYS_YPOS)
+#define V_SYS_YPOS(x)             _SB_MAKEVALUE(x, S_SYS_YPOS)
+#define G_SYS_YPOS(x)             _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)
+#endif
+
+
+/*
+ * System Config Register (Table 4-2)
+ * Register: SCD_SYSTEM_CFG
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
+#define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
+#define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
+#define M_SYS_IOB1_DIV              _SB_MAKEMASK1(6)
+
+#define S_SYS_PLL_DIV               _SB_MAKE64(7)
+#define M_SYS_PLL_DIV               _SB_MAKEMASK(5, S_SYS_PLL_DIV)
+#define V_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
+#define G_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
+
+#define M_SYS_SER0_ENABLE           _SB_MAKEMASK1(12)
+#define M_SYS_SER0_RSTB_EN          _SB_MAKEMASK1(13)
+#define M_SYS_SER1_ENABLE           _SB_MAKEMASK1(14)
+#define M_SYS_SER1_RSTB_EN          _SB_MAKEMASK1(15)
+#define M_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
+
+#define S_SYS_BOOT_MODE             _SB_MAKE64(17)
+#define M_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
+#define V_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
+#define G_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
+#define K_SYS_BOOT_MODE_ROM32       0
+#define K_SYS_BOOT_MODE_ROM8        1
+#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
+#define K_SYS_BOOT_MODE_SMBUS_BIG   3
+
+#define M_SYS_PCI_HOST              _SB_MAKEMASK1(19)
+#define M_SYS_PCI_ARBITER           _SB_MAKEMASK1(20)
+#define M_SYS_SOUTH_ON_LDT          _SB_MAKEMASK1(21)
+#define M_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
+#define M_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
+#define M_SYS_LDT_TEST_EN           _SB_MAKEMASK1(24)
+#define M_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(25)
+
+#define S_SYS_CONFIG                26
+#define M_SYS_CONFIG                _SB_MAKEMASK(6, S_SYS_CONFIG)
+#define V_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_SYS_CONFIG)
+#define G_SYS_CONFIG(x)             _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)
+
+/* The following bits are writeable by JTAG only. */
+
+#define M_SYS_CLKSTOP               _SB_MAKEMASK1(32)
+#define M_SYS_CLKSTEP               _SB_MAKEMASK1(33)
+
+#define S_SYS_CLKCOUNT              34
+#define M_SYS_CLKCOUNT              _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
+#define V_SYS_CLKCOUNT(x)           _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
+#define G_SYS_CLKCOUNT(x)           _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)
+
+#define M_SYS_PLL_BYPASS            _SB_MAKEMASK1(42)
+
+#define S_SYS_PLL_IREF              43
+#define M_SYS_PLL_IREF              _SB_MAKEMASK(2, S_SYS_PLL_IREF)
+
+#define S_SYS_PLL_VCO               45
+#define M_SYS_PLL_VCO               _SB_MAKEMASK(2, S_SYS_PLL_VCO)
+
+#define S_SYS_PLL_VREG              47
+#define M_SYS_PLL_VREG              _SB_MAKEMASK(2, S_SYS_PLL_VREG)
+
+#define M_SYS_MEM_RESET             _SB_MAKEMASK1(49)
+#define M_SYS_L2C_RESET             _SB_MAKEMASK1(50)
+#define M_SYS_IO_RESET_0            _SB_MAKEMASK1(51)
+#define M_SYS_IO_RESET_1            _SB_MAKEMASK1(52)
+#define M_SYS_SCD_RESET             _SB_MAKEMASK1(53)
+
+/* End of bits writable by JTAG only. */
+
+#define M_SYS_CPU_RESET_0           _SB_MAKEMASK1(54)
+#define M_SYS_CPU_RESET_1           _SB_MAKEMASK1(55)
+
+#define M_SYS_UNICPU0               _SB_MAKEMASK1(56)
+#define M_SYS_UNICPU1               _SB_MAKEMASK1(57)
+
+#define M_SYS_SB_SOFTRES            _SB_MAKEMASK1(58)
+#define M_SYS_EXT_RESET             _SB_MAKEMASK1(59)
+#define M_SYS_SYSTEM_RESET          _SB_MAKEMASK1(60)
+
+#define M_SYS_MISR_MODE             _SB_MAKEMASK1(61)
+#define M_SYS_MISR_RESET            _SB_MAKEMASK1(62)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
+#define M_SYS_SW_FLAG               _SB_MAKEMASK1(63)
+#endif /* 1250 PASS2 || 112x PASS1 */
+
+#endif
+
+
+/*
+ * Mailbox Registers (Table 4-3)
+ * Registers: SCD_MBOX_CPU_x
+ */
+
+#define S_MBOX_INT_3                0
+#define M_MBOX_INT_3                _SB_MAKEMASK(16, S_MBOX_INT_3)
+#define S_MBOX_INT_2                16
+#define M_MBOX_INT_2                _SB_MAKEMASK(16, S_MBOX_INT_2)
+#define S_MBOX_INT_1                32
+#define M_MBOX_INT_1                _SB_MAKEMASK(16, S_MBOX_INT_1)
+#define S_MBOX_INT_0                48
+#define M_MBOX_INT_0                _SB_MAKEMASK(16, S_MBOX_INT_0)
+
+/*
+ * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
+ * Registers: SCD_WDOG_INIT_CNT_x
+ */
+
+#define V_SCD_WDOG_FREQ             1000000
+
+#define S_SCD_WDOG_INIT             0
+#define M_SCD_WDOG_INIT             _SB_MAKEMASK(23, S_SCD_WDOG_INIT)
+
+#define S_SCD_WDOG_CNT              0
+#define M_SCD_WDOG_CNT              _SB_MAKEMASK(23, S_SCD_WDOG_CNT)
+
+#define S_SCD_WDOG_ENABLE           0
+#define M_SCD_WDOG_ENABLE           _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
+
+#define S_SCD_WDOG_RESET_TYPE       2
+#define M_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)
+#define V_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
+#define G_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
+
+#define K_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
+#define K_SCD_WDOG_RESET_SOFT       1
+#define K_SCD_WDOG_RESET_CPU0       3
+#define K_SCD_WDOG_RESET_CPU1       5
+#define K_SCD_WDOG_RESET_BOTH_CPUS  7
+
+/* This feature is present in 1250 C0 and later, but *not* in 112x A revs.  */
+#if SIBYTE_HDR_FEATURE(1250, PASS3)
+#define S_SCD_WDOG_HAS_RESET        8
+#define M_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
+#endif
+
+
+/*
+ * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
+ */
+
+#define V_SCD_TIMER_FREQ            1000000
+
+#define S_SCD_TIMER_INIT            0
+#define M_SCD_TIMER_INIT            _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
+#define V_SCD_TIMER_INIT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
+#define G_SCD_TIMER_INIT(x)         _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)
+
+#define V_SCD_TIMER_WIDTH           23
+#define S_SCD_TIMER_CNT             0
+#define M_SCD_TIMER_CNT             _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
+#define V_SCD_TIMER_CNT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
+#define G_SCD_TIMER_CNT(x)         _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)
+
+#define M_SCD_TIMER_ENABLE          _SB_MAKEMASK1(0)
+#define M_SCD_TIMER_MODE            _SB_MAKEMASK1(1)
+#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
+
+/*
+ * System Performance Counters
+ */
+
+#define S_SPC_CFG_SRC0            0
+#define M_SPC_CFG_SRC0            _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
+#define V_SPC_CFG_SRC0(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
+#define G_SPC_CFG_SRC0(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)
+
+#define S_SPC_CFG_SRC1            8
+#define M_SPC_CFG_SRC1            _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
+#define V_SPC_CFG_SRC1(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
+#define G_SPC_CFG_SRC1(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)
+
+#define S_SPC_CFG_SRC2            16
+#define M_SPC_CFG_SRC2            _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
+#define V_SPC_CFG_SRC2(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
+#define G_SPC_CFG_SRC2(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)
+
+#define S_SPC_CFG_SRC3            24
+#define M_SPC_CFG_SRC3            _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
+#define V_SPC_CFG_SRC3(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
+#define G_SPC_CFG_SRC3(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define M_SPC_CFG_CLEAR         _SB_MAKEMASK1(32)
+#define M_SPC_CFG_ENABLE        _SB_MAKEMASK1(33)
+#endif
+
+
+/*
+ * Bus Watcher
+ */
+
+#define S_SCD_BERR_TID            8
+#define M_SCD_BERR_TID            _SB_MAKEMASK(10, S_SCD_BERR_TID)
+#define V_SCD_BERR_TID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_TID)
+#define G_SCD_BERR_TID(x)         _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)
+
+#define S_SCD_BERR_RID            18
+#define M_SCD_BERR_RID            _SB_MAKEMASK(4, S_SCD_BERR_RID)
+#define V_SCD_BERR_RID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_RID)
+#define G_SCD_BERR_RID(x)         _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)
+
+#define S_SCD_BERR_DCODE          22
+#define M_SCD_BERR_DCODE          _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
+#define V_SCD_BERR_DCODE(x)       _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
+#define G_SCD_BERR_DCODE(x)       _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)
+
+#define M_SCD_BERR_MULTERRS       _SB_MAKEMASK1(30)
+
+
+#define S_SCD_L2ECC_CORR_D        0
+#define M_SCD_L2ECC_CORR_D        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
+#define V_SCD_L2ECC_CORR_D(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
+#define G_SCD_L2ECC_CORR_D(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)
+
+#define S_SCD_L2ECC_BAD_D         8
+#define M_SCD_L2ECC_BAD_D         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
+#define V_SCD_L2ECC_BAD_D(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
+#define G_SCD_L2ECC_BAD_D(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)
+
+#define S_SCD_L2ECC_CORR_T        16
+#define M_SCD_L2ECC_CORR_T        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
+#define V_SCD_L2ECC_CORR_T(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
+#define G_SCD_L2ECC_CORR_T(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)
+
+#define S_SCD_L2ECC_BAD_T         24
+#define M_SCD_L2ECC_BAD_T         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
+#define V_SCD_L2ECC_BAD_T(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
+#define G_SCD_L2ECC_BAD_T(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)
+
+#define S_SCD_MEM_ECC_CORR        0
+#define M_SCD_MEM_ECC_CORR        _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
+#define V_SCD_MEM_ECC_CORR(x)     _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
+#define G_SCD_MEM_ECC_CORR(x)     _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)
+
+#define S_SCD_MEM_ECC_BAD         8
+#define M_SCD_MEM_ECC_BAD         _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
+#define V_SCD_MEM_ECC_BAD(x)      _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
+#define G_SCD_MEM_ECC_BAD(x)      _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)
+
+#define S_SCD_MEM_BUSERR          16
+#define M_SCD_MEM_BUSERR          _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
+#define V_SCD_MEM_BUSERR(x)       _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
+#define G_SCD_MEM_BUSERR(x)       _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)
+
+
+/*
+ * Address Trap Registers
+ */
+
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define M_ATRAP_INDEX             _SB_MAKEMASK(4, 0)
+#define M_ATRAP_ADDRESS           _SB_MAKEMASK(40, 0)
+
+#define S_ATRAP_CFG_CNT            0
+#define M_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
+#define V_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
+#define G_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)
+
+#define M_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
+#define M_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
+#define M_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
+#define M_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
+#define M_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
+
+#define S_ATRAP_CFG_AGENTID     8
+#define M_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
+#define V_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
+#define G_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)
+
+#define K_BUS_AGENT_CPU0        0
+#define K_BUS_AGENT_CPU1        1
+#define K_BUS_AGENT_IOB0        2
+#define K_BUS_AGENT_IOB1        3
+#define K_BUS_AGENT_SCD 4
+#define K_BUS_AGENT_L2C 6
+#define K_BUS_AGENT_MC  7
+
+#define S_ATRAP_CFG_CATTR     12
+#define M_ATRAP_CFG_CATTR     _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR)
+#define V_ATRAP_CFG_CATTR(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR)
+#define G_ATRAP_CFG_CATTR(x)  _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
+
+#define K_ATRAP_CFG_CATTR_IGNORE        0
+#define K_ATRAP_CFG_CATTR_UNC           1
+#define K_ATRAP_CFG_CATTR_CACHEABLE     2
+#define K_ATRAP_CFG_CATTR_NONCOH        3
+#define K_ATRAP_CFG_CATTR_COHERENT      4
+#define K_ATRAP_CFG_CATTR_NOTUNC        5
+#define K_ATRAP_CFG_CATTR_NOTNONCOH     6
+#define K_ATRAP_CFG_CATTR_NOTCOHERENT   7
+
+#endif  /* 1250/112x */
+
+/*
+ * Trace Buffer Config register
+ */
+
+#define M_SCD_TRACE_CFG_RESET           _SB_MAKEMASK1(0)
+#define M_SCD_TRACE_CFG_START_READ      _SB_MAKEMASK1(1)
+#define M_SCD_TRACE_CFG_START           _SB_MAKEMASK1(2)
+#define M_SCD_TRACE_CFG_STOP            _SB_MAKEMASK1(3)
+#define M_SCD_TRACE_CFG_FREEZE          _SB_MAKEMASK1(4)
+#define M_SCD_TRACE_CFG_FREEZE_FULL     _SB_MAKEMASK1(5)
+#define M_SCD_TRACE_CFG_DEBUG_FULL      _SB_MAKEMASK1(6)
+#define M_SCD_TRACE_CFG_FULL            _SB_MAKEMASK1(7)
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define M_SCD_TRACE_CFG_FORCECNT        _SB_MAKEMASK1(8)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+/*
+ * This field is the same on the 1250/112x and 1480, just located in
+ * a slightly different place in the register.
+ */
+#if SIBYTE_HDR_FEATURE_1250_112x
+#define S_SCD_TRACE_CFG_CUR_ADDR        10
+#else
+#if SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_SCD_TRACE_CFG_CUR_ADDR        24
+#endif  /* 1480 */
+#endif  /* 1250/112x */
+
+#define M_SCD_TRACE_CFG_CUR_ADDR        _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
+#define V_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
+#define G_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)
+
+/*
+ * Trace Event registers
+ */
+
+#define S_SCD_TREVT_ADDR_MATCH          0
+#define M_SCD_TREVT_ADDR_MATCH          _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
+#define V_SCD_TREVT_ADDR_MATCH(x)       _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
+#define G_SCD_TREVT_ADDR_MATCH(x)       _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
+
+#define M_SCD_TREVT_REQID_MATCH         _SB_MAKEMASK1(4)
+#define M_SCD_TREVT_DATAID_MATCH        _SB_MAKEMASK1(5)
+#define M_SCD_TREVT_RESPID_MATCH        _SB_MAKEMASK1(6)
+#define M_SCD_TREVT_INTERRUPT           _SB_MAKEMASK1(7)
+#define M_SCD_TREVT_DEBUG_PIN           _SB_MAKEMASK1(9)
+#define M_SCD_TREVT_WRITE               _SB_MAKEMASK1(10)
+#define M_SCD_TREVT_READ                _SB_MAKEMASK1(11)
+
+#define S_SCD_TREVT_REQID               12
+#define M_SCD_TREVT_REQID               _SB_MAKEMASK(4, S_SCD_TREVT_REQID)
+#define V_SCD_TREVT_REQID(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
+#define G_SCD_TREVT_REQID(x)            _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
+
+#define S_SCD_TREVT_RESPID              16
+#define M_SCD_TREVT_RESPID              _SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
+#define V_SCD_TREVT_RESPID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
+#define G_SCD_TREVT_RESPID(x)           _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
+
+#define S_SCD_TREVT_DATAID              20
+#define M_SCD_TREVT_DATAID              _SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
+#define V_SCD_TREVT_DATAID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
+#define G_SCD_TREVT_DATAID(x)           _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
+
+#define S_SCD_TREVT_COUNT               24
+#define M_SCD_TREVT_COUNT               _SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
+#define V_SCD_TREVT_COUNT(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
+#define G_SCD_TREVT_COUNT(x)            _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)
+
+/*
+ * Trace Sequence registers
+ */
+
+#define S_SCD_TRSEQ_EVENT4              0
+#define M_SCD_TRSEQ_EVENT4              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
+#define V_SCD_TRSEQ_EVENT4(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
+#define G_SCD_TRSEQ_EVENT4(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
+
+#define S_SCD_TRSEQ_EVENT3              4
+#define M_SCD_TRSEQ_EVENT3              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
+#define V_SCD_TRSEQ_EVENT3(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
+#define G_SCD_TRSEQ_EVENT3(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
+
+#define S_SCD_TRSEQ_EVENT2              8
+#define M_SCD_TRSEQ_EVENT2              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
+#define V_SCD_TRSEQ_EVENT2(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
+#define G_SCD_TRSEQ_EVENT2(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
+
+#define S_SCD_TRSEQ_EVENT1              12
+#define M_SCD_TRSEQ_EVENT1              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
+#define V_SCD_TRSEQ_EVENT1(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
+#define G_SCD_TRSEQ_EVENT1(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
+
+#define K_SCD_TRSEQ_E0                  0
+#define K_SCD_TRSEQ_E1                  1
+#define K_SCD_TRSEQ_E2                  2
+#define K_SCD_TRSEQ_E3                  3
+#define K_SCD_TRSEQ_E0_E1               4
+#define K_SCD_TRSEQ_E1_E2               5
+#define K_SCD_TRSEQ_E2_E3               6
+#define K_SCD_TRSEQ_E0_E1_E2            7
+#define K_SCD_TRSEQ_E0_E1_E2_E3         8
+#define K_SCD_TRSEQ_E0E1                9
+#define K_SCD_TRSEQ_E0E1E2              10
+#define K_SCD_TRSEQ_E0E1E2E3            11
+#define K_SCD_TRSEQ_E0E1_E2             12
+#define K_SCD_TRSEQ_E0E1_E2E3           13
+#define K_SCD_TRSEQ_E0E1_E2_E3          14
+#define K_SCD_TRSEQ_IGNORED             15
+
+#define K_SCD_TRSEQ_TRIGGER_ALL         (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
+                                         V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
+                                         V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
+                                         V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
+
+#define S_SCD_TRSEQ_FUNCTION            16
+#define M_SCD_TRSEQ_FUNCTION            _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
+#define V_SCD_TRSEQ_FUNCTION(x)         _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
+#define G_SCD_TRSEQ_FUNCTION(x)         _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
+
+#define K_SCD_TRSEQ_FUNC_NOP            0
+#define K_SCD_TRSEQ_FUNC_START          1
+#define K_SCD_TRSEQ_FUNC_STOP           2
+#define K_SCD_TRSEQ_FUNC_FREEZE         3
+
+#define V_SCD_TRSEQ_FUNC_NOP            V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
+#define V_SCD_TRSEQ_FUNC_START          V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
+#define V_SCD_TRSEQ_FUNC_STOP           V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
+#define V_SCD_TRSEQ_FUNC_FREEZE         V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
+
+#define M_SCD_TRSEQ_ASAMPLE             _SB_MAKEMASK1(18)
+#define M_SCD_TRSEQ_DSAMPLE             _SB_MAKEMASK1(19)
+#define M_SCD_TRSEQ_DEBUGPIN            _SB_MAKEMASK1(20)
+#define M_SCD_TRSEQ_DEBUGCPU            _SB_MAKEMASK1(21)
+#define M_SCD_TRSEQ_CLEARUSE            _SB_MAKEMASK1(22)
+#define M_SCD_TRSEQ_ALLD_A              _SB_MAKEMASK1(23)
+#define M_SCD_TRSEQ_ALL_A               _SB_MAKEMASK1(24)
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_smbus.h b/arch/mips/include/asm/sibyte/sb1250_smbus.h
new file mode 100644
index 000000000000..04769923cf1e
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_smbus.h
@@ -0,0 +1,204 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  SMBUS Constants                          File: sb1250_smbus.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the SB1250's SMbus devices.
+    *
+    *  SB1250 specification level:  10/21/02
+    *  BCM1280 specification level:  11/24/03
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_SMBUS_H
+#define _SB1250_SMBUS_H
+
+#include "sb1250_defs.h"
+
+/*
+ * SMBus Clock Frequency Register (Table 14-2)
+ */
+
+#define S_SMB_FREQ_DIV              0
+#define M_SMB_FREQ_DIV              _SB_MAKEMASK(13, S_SMB_FREQ_DIV)
+#define V_SMB_FREQ_DIV(x)           _SB_MAKEVALUE(x, S_SMB_FREQ_DIV)
+
+#define K_SMB_FREQ_400KHZ           0x1F
+#define K_SMB_FREQ_100KHZ           0x7D
+#define K_SMB_FREQ_10KHZ            1250
+
+#define S_SMB_CMD                   0
+#define M_SMB_CMD                   _SB_MAKEMASK(8, S_SMB_CMD)
+#define V_SMB_CMD(x)                _SB_MAKEVALUE(x, S_SMB_CMD)
+
+/*
+ * SMBus control register (Table 14-4)
+ */
+
+#define M_SMB_ERR_INTR              _SB_MAKEMASK1(0)
+#define M_SMB_FINISH_INTR           _SB_MAKEMASK1(1)
+
+#define S_SMB_DATA_OUT              4
+#define M_SMB_DATA_OUT              _SB_MAKEMASK1(S_SMB_DATA_OUT)
+#define V_SMB_DATA_OUT(x)           _SB_MAKEVALUE(x, S_SMB_DATA_OUT)
+
+#define M_SMB_DATA_DIR              _SB_MAKEMASK1(5)
+#define M_SMB_DATA_DIR_OUTPUT       M_SMB_DATA_DIR
+#define M_SMB_CLK_OUT               _SB_MAKEMASK1(6)
+#define M_SMB_DIRECT_ENABLE         _SB_MAKEMASK1(7)
+
+/*
+ * SMBus status registers (Table 14-5)
+ */
+
+#define M_SMB_BUSY                  _SB_MAKEMASK1(0)
+#define M_SMB_ERROR                 _SB_MAKEMASK1(1)
+#define M_SMB_ERROR_TYPE            _SB_MAKEMASK1(2)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+#define S_SMB_SCL_IN                5
+#define M_SMB_SCL_IN                _SB_MAKEMASK1(S_SMB_SCL_IN)
+#define V_SMB_SCL_IN(x)             _SB_MAKEVALUE(x, S_SMB_SCL_IN)
+#define G_SMB_SCL_IN(x)             _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN)
+#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
+
+#define S_SMB_REF                   6
+#define M_SMB_REF                   _SB_MAKEMASK1(S_SMB_REF)
+#define V_SMB_REF(x)                _SB_MAKEVALUE(x, S_SMB_REF)
+#define G_SMB_REF(x)                _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF)
+
+#define S_SMB_DATA_IN               7
+#define M_SMB_DATA_IN               _SB_MAKEMASK1(S_SMB_DATA_IN)
+#define V_SMB_DATA_IN(x)            _SB_MAKEVALUE(x, S_SMB_DATA_IN)
+#define G_SMB_DATA_IN(x)            _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN)
+
+/*
+ * SMBus Start/Command registers (Table 14-9)
+ */
+
+#define S_SMB_ADDR                  0
+#define M_SMB_ADDR                  _SB_MAKEMASK(7, S_SMB_ADDR)
+#define V_SMB_ADDR(x)               _SB_MAKEVALUE(x, S_SMB_ADDR)
+#define G_SMB_ADDR(x)               _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR)
+
+#define M_SMB_QDATA                 _SB_MAKEMASK1(7)
+
+#define S_SMB_TT                    8
+#define M_SMB_TT                    _SB_MAKEMASK(3, S_SMB_TT)
+#define V_SMB_TT(x)                 _SB_MAKEVALUE(x, S_SMB_TT)
+#define G_SMB_TT(x)                 _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT)
+
+#define K_SMB_TT_WR1BYTE            0
+#define K_SMB_TT_WR2BYTE            1
+#define K_SMB_TT_WR3BYTE            2
+#define K_SMB_TT_CMD_RD1BYTE        3
+#define K_SMB_TT_CMD_RD2BYTE        4
+#define K_SMB_TT_RD1BYTE            5
+#define K_SMB_TT_QUICKCMD           6
+#define K_SMB_TT_EEPROMREAD         7
+
+#define V_SMB_TT_WR1BYTE            V_SMB_TT(K_SMB_TT_WR1BYTE)
+#define V_SMB_TT_WR2BYTE            V_SMB_TT(K_SMB_TT_WR2BYTE)
+#define V_SMB_TT_WR3BYTE            V_SMB_TT(K_SMB_TT_WR3BYTE)
+#define V_SMB_TT_CMD_RD1BYTE        V_SMB_TT(K_SMB_TT_CMD_RD1BYTE)
+#define V_SMB_TT_CMD_RD2BYTE        V_SMB_TT(K_SMB_TT_CMD_RD2BYTE)
+#define V_SMB_TT_RD1BYTE            V_SMB_TT(K_SMB_TT_RD1BYTE)
+#define V_SMB_TT_QUICKCMD           V_SMB_TT(K_SMB_TT_QUICKCMD)
+#define V_SMB_TT_EEPROMREAD         V_SMB_TT(K_SMB_TT_EEPROMREAD)
+
+#define M_SMB_PEC                   _SB_MAKEMASK1(15)
+
+/*
+ * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7)
+ */
+
+#define S_SMB_LB                    0
+#define M_SMB_LB                    _SB_MAKEMASK(8, S_SMB_LB)
+#define V_SMB_LB(x)                 _SB_MAKEVALUE(x, S_SMB_LB)
+
+#define S_SMB_MB                    8
+#define M_SMB_MB                    _SB_MAKEMASK(8, S_SMB_MB)
+#define V_SMB_MB(x)                 _SB_MAKEVALUE(x, S_SMB_MB)
+
+
+/*
+ * SMBus Packet Error Check register (Table 14-8)
+ */
+
+#define S_SPEC_PEC                  0
+#define M_SPEC_PEC                  _SB_MAKEMASK(8, S_SPEC_PEC)
+#define V_SPEC_MB(x)                _SB_MAKEVALUE(x, S_SPEC_PEC)
+
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+
+#define S_SMB_CMDH                  8
+#define M_SMB_CMDH                  _SB_MAKEMASK(8, S_SMB_CMDH)
+#define V_SMB_CMDH(x)               _SB_MAKEVALUE(x, S_SMB_CMDH)
+
+#define M_SMB_EXTEND                _SB_MAKEMASK1(14)
+
+#define S_SMB_DFMT                  8
+#define M_SMB_DFMT                  _SB_MAKEMASK(3, S_SMB_DFMT)
+#define V_SMB_DFMT(x)               _SB_MAKEVALUE(x, S_SMB_DFMT)
+#define G_SMB_DFMT(x)               _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT)
+
+#define K_SMB_DFMT_1BYTE            0
+#define K_SMB_DFMT_2BYTE            1
+#define K_SMB_DFMT_3BYTE            2
+#define K_SMB_DFMT_4BYTE            3
+#define K_SMB_DFMT_NODATA           4
+#define K_SMB_DFMT_CMD4BYTE         5
+#define K_SMB_DFMT_CMD5BYTE         6
+#define K_SMB_DFMT_RESERVED         7
+
+#define V_SMB_DFMT_1BYTE            V_SMB_DFMT(K_SMB_DFMT_1BYTE)
+#define V_SMB_DFMT_2BYTE            V_SMB_DFMT(K_SMB_DFMT_2BYTE)
+#define V_SMB_DFMT_3BYTE            V_SMB_DFMT(K_SMB_DFMT_3BYTE)
+#define V_SMB_DFMT_4BYTE            V_SMB_DFMT(K_SMB_DFMT_4BYTE)
+#define V_SMB_DFMT_NODATA           V_SMB_DFMT(K_SMB_DFMT_NODATA)
+#define V_SMB_DFMT_CMD4BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE)
+#define V_SMB_DFMT_CMD5BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
+#define V_SMB_DFMT_RESERVED         V_SMB_DFMT(K_SMB_DFMT_RESERVED)
+
+#define S_SMB_AFMT                  11
+#define M_SMB_AFMT                  _SB_MAKEMASK(2, S_SMB_AFMT)
+#define V_SMB_AFMT(x)               _SB_MAKEVALUE(x, S_SMB_AFMT)
+#define G_SMB_AFMT(x)               _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT)
+
+#define K_SMB_AFMT_NONE             0
+#define K_SMB_AFMT_ADDR             1
+#define K_SMB_AFMT_ADDR_CMD1BYTE    2
+#define K_SMB_AFMT_ADDR_CMD2BYTE    3
+
+#define V_SMB_AFMT_NONE             V_SMB_AFMT(K_SMB_AFMT_NONE)
+#define V_SMB_AFMT_ADDR             V_SMB_AFMT(K_SMB_AFMT_ADDR)
+#define V_SMB_AFMT_ADDR_CMD1BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE)
+#define V_SMB_AFMT_ADDR_CMD2BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE)
+
+#define M_SMB_DIR                   _SB_MAKEMASK1(13)
+
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_syncser.h b/arch/mips/include/asm/sibyte/sb1250_syncser.h
new file mode 100644
index 000000000000..d4b8558e0bf1
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_syncser.h
@@ -0,0 +1,146 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  Synchronous Serial Constants              File: sb1250_syncser.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the SB1250's Synchronous Serial
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_SYNCSER_H
+#define _SB1250_SYNCSER_H
+
+#include "sb1250_defs.h"
+
+/*
+ * Serial Mode Configuration Register
+ */
+
+#define M_SYNCSER_CRC_MODE                 _SB_MAKEMASK1(0)
+#define M_SYNCSER_MSB_FIRST                _SB_MAKEMASK1(1)
+
+#define S_SYNCSER_FLAG_NUM                 2
+#define M_SYNCSER_FLAG_NUM                 _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
+#define V_SYNCSER_FLAG_NUM                 _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)
+
+#define M_SYNCSER_FLAG_EN                  _SB_MAKEMASK1(6)
+#define M_SYNCSER_HDLC_EN                  _SB_MAKEMASK1(7)
+#define M_SYNCSER_LOOP_MODE                _SB_MAKEMASK1(8)
+#define M_SYNCSER_LOOPBACK                 _SB_MAKEMASK1(9)
+
+/*
+ * Serial Clock Source and Line Interface Mode Register
+ */
+
+#define M_SYNCSER_RXCLK_INV                _SB_MAKEMASK1(0)
+#define M_SYNCSER_RXCLK_EXT                _SB_MAKEMASK1(1)
+
+#define S_SYNCSER_RXSYNC_DLY               2
+#define M_SYNCSER_RXSYNC_DLY               _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
+#define V_SYNCSER_RXSYNC_DLY(x)            _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)
+
+#define M_SYNCSER_RXSYNC_LOW               _SB_MAKEMASK1(4)
+#define M_SYNCSER_RXSTRB_LOW               _SB_MAKEMASK1(5)
+
+#define M_SYNCSER_RXSYNC_EDGE              _SB_MAKEMASK1(6)
+#define M_SYNCSER_RXSYNC_INT               _SB_MAKEMASK1(7)
+
+#define M_SYNCSER_TXCLK_INV                _SB_MAKEMASK1(8)
+#define M_SYNCSER_TXCLK_EXT                _SB_MAKEMASK1(9)
+
+#define S_SYNCSER_TXSYNC_DLY               10
+#define M_SYNCSER_TXSYNC_DLY               _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
+#define V_SYNCSER_TXSYNC_DLY(x)            _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)
+
+#define M_SYNCSER_TXSYNC_LOW               _SB_MAKEMASK1(12)
+#define M_SYNCSER_TXSTRB_LOW               _SB_MAKEMASK1(13)
+
+#define M_SYNCSER_TXSYNC_EDGE              _SB_MAKEMASK1(14)
+#define M_SYNCSER_TXSYNC_INT               _SB_MAKEMASK1(15)
+
+/*
+ * Serial Command Register
+ */
+
+#define M_SYNCSER_CMD_RX_EN                _SB_MAKEMASK1(0)
+#define M_SYNCSER_CMD_TX_EN                _SB_MAKEMASK1(1)
+#define M_SYNCSER_CMD_RX_RESET             _SB_MAKEMASK1(2)
+#define M_SYNCSER_CMD_TX_RESET             _SB_MAKEMASK1(3)
+#define M_SYNCSER_CMD_TX_PAUSE             _SB_MAKEMASK1(5)
+
+/*
+ * Serial DMA Enable Register
+ */
+
+#define M_SYNCSER_DMA_RX_EN                _SB_MAKEMASK1(0)
+#define M_SYNCSER_DMA_TX_EN                _SB_MAKEMASK1(4)
+
+/*
+ * Serial Status Register
+ */
+
+#define M_SYNCSER_RX_CRCERR                _SB_MAKEMASK1(0)
+#define M_SYNCSER_RX_ABORT                 _SB_MAKEMASK1(1)
+#define M_SYNCSER_RX_OCTET                 _SB_MAKEMASK1(2)
+#define M_SYNCSER_RX_LONGFRM               _SB_MAKEMASK1(3)
+#define M_SYNCSER_RX_SHORTFRM              _SB_MAKEMASK1(4)
+#define M_SYNCSER_RX_OVERRUN               _SB_MAKEMASK1(5)
+#define M_SYNCSER_RX_SYNC_ERR              _SB_MAKEMASK1(6)
+#define M_SYNCSER_TX_CRCERR                _SB_MAKEMASK1(8)
+#define M_SYNCSER_TX_UNDERRUN              _SB_MAKEMASK1(9)
+#define M_SYNCSER_TX_SYNC_ERR              _SB_MAKEMASK1(10)
+#define M_SYNCSER_TX_PAUSE_COMPLETE        _SB_MAKEMASK1(11)
+#define M_SYNCSER_RX_EOP_COUNT             _SB_MAKEMASK1(16)
+#define M_SYNCSER_RX_EOP_TIMER             _SB_MAKEMASK1(17)
+#define M_SYNCSER_RX_EOP_SEEN              _SB_MAKEMASK1(18)
+#define M_SYNCSER_RX_HWM                   _SB_MAKEMASK1(19)
+#define M_SYNCSER_RX_LWM                   _SB_MAKEMASK1(20)
+#define M_SYNCSER_RX_DSCR                  _SB_MAKEMASK1(21)
+#define M_SYNCSER_RX_DERR                  _SB_MAKEMASK1(22)
+#define M_SYNCSER_TX_EOP_COUNT             _SB_MAKEMASK1(24)
+#define M_SYNCSER_TX_EOP_TIMER             _SB_MAKEMASK1(25)
+#define M_SYNCSER_TX_EOP_SEEN              _SB_MAKEMASK1(26)
+#define M_SYNCSER_TX_HWM                   _SB_MAKEMASK1(27)
+#define M_SYNCSER_TX_LWM                   _SB_MAKEMASK1(28)
+#define M_SYNCSER_TX_DSCR                  _SB_MAKEMASK1(29)
+#define M_SYNCSER_TX_DERR                  _SB_MAKEMASK1(30)
+#define M_SYNCSER_TX_DZERO                 _SB_MAKEMASK1(31)
+
+/*
+ * Sequencer Table Entry format
+ */
+
+#define M_SYNCSER_SEQ_LAST                 _SB_MAKEMASK1(0)
+#define M_SYNCSER_SEQ_BYTE                 _SB_MAKEMASK1(1)
+
+#define S_SYNCSER_SEQ_COUNT                2
+#define M_SYNCSER_SEQ_COUNT                _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
+#define V_SYNCSER_SEQ_COUNT(x)             _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)
+
+#define M_SYNCSER_SEQ_ENABLE               _SB_MAKEMASK1(6)
+#define M_SYNCSER_SEQ_STROBE               _SB_MAKEMASK1(7)
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sb1250_uart.h b/arch/mips/include/asm/sibyte/sb1250_uart.h
new file mode 100644
index 000000000000..d835bf280140
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sb1250_uart.h
@@ -0,0 +1,362 @@
+/*  *********************************************************************
+    *  SB1250 Board Support Package
+    *
+    *  UART Constants                           File: sb1250_uart.h
+    *
+    *  This module contains constants and macros useful for
+    *  manipulating the SB1250's UARTs
+    *
+    *  SB1250 specification level:  User's manual 1/02/02
+    *
+    *********************************************************************
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
+    *  the License, or (at your option) any later version.
+    *
+    *  This program is distributed in the hope that it will be useful,
+    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    *  GNU General Public License for more details.
+    *
+    *  You should have received a copy of the GNU General Public License
+    *  along with this program; if not, write to the Free Software
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+    *  MA 02111-1307 USA
+    ********************************************************************* */
+
+
+#ifndef _SB1250_UART_H
+#define _SB1250_UART_H
+
+#include "sb1250_defs.h"
+
+/* **********************************************************************
+   * DUART Registers
+   ********************************************************************** */
+
+/*
+ * DUART Mode Register #1 (Table 10-3)
+ * Register: DUART_MODE_REG_1_A
+ * Register: DUART_MODE_REG_1_B
+ */
+
+#define S_DUART_BITS_PER_CHAR       0
+#define M_DUART_BITS_PER_CHAR       _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
+#define V_DUART_BITS_PER_CHAR(x)    _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
+
+#define K_DUART_BITS_PER_CHAR_RSV0  0
+#define K_DUART_BITS_PER_CHAR_RSV1  1
+#define K_DUART_BITS_PER_CHAR_7     2
+#define K_DUART_BITS_PER_CHAR_8     3
+
+#define V_DUART_BITS_PER_CHAR_RSV0  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
+#define V_DUART_BITS_PER_CHAR_RSV1  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
+#define V_DUART_BITS_PER_CHAR_7     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
+#define V_DUART_BITS_PER_CHAR_8     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
+
+
+#define M_DUART_PARITY_TYPE_EVEN    0x00
+#define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(2)
+
+#define S_DUART_PARITY_MODE          3
+#define M_DUART_PARITY_MODE         _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
+#define V_DUART_PARITY_MODE(x)      _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
+
+#define K_DUART_PARITY_MODE_ADD       0
+#define K_DUART_PARITY_MODE_ADD_FIXED 1
+#define K_DUART_PARITY_MODE_NONE      2
+
+#define V_DUART_PARITY_MODE_ADD       V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
+#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
+#define V_DUART_PARITY_MODE_NONE      V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
+
+#define M_DUART_TX_IRQ_SEL_TXRDY    0
+#define M_DUART_TX_IRQ_SEL_TXEMPT   _SB_MAKEMASK1(5)
+
+#define M_DUART_RX_IRQ_SEL_RXRDY    0
+#define M_DUART_RX_IRQ_SEL_RXFULL   _SB_MAKEMASK1(6)
+
+#define M_DUART_RX_RTS_ENA          _SB_MAKEMASK1(7)
+
+/*
+ * DUART Mode Register #2 (Table 10-4)
+ * Register: DUART_MODE_REG_2_A
+ * Register: DUART_MODE_REG_2_B
+ */
+
+#define M_DUART_MODE_RESERVED1      _SB_MAKEMASK(3, 0)   /* ignored */
+
+#define M_DUART_STOP_BIT_LEN_2      _SB_MAKEMASK1(3)
+#define M_DUART_STOP_BIT_LEN_1      0
+
+#define M_DUART_TX_CTS_ENA          _SB_MAKEMASK1(4)
+
+
+#define M_DUART_MODE_RESERVED2      _SB_MAKEMASK1(5)    /* must be zero */
+
+#define S_DUART_CHAN_MODE           6
+#define M_DUART_CHAN_MODE           _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
+#define V_DUART_CHAN_MODE(x)        _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
+
+#define K_DUART_CHAN_MODE_NORMAL    0
+#define K_DUART_CHAN_MODE_LCL_LOOP  2
+#define K_DUART_CHAN_MODE_REM_LOOP  3
+
+#define V_DUART_CHAN_MODE_NORMAL    V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
+#define V_DUART_CHAN_MODE_LCL_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
+#define V_DUART_CHAN_MODE_REM_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
+
+/*
+ * DUART Command Register (Table 10-5)
+ * Register: DUART_CMD_A
+ * Register: DUART_CMD_B
+ */
+
+#define M_DUART_RX_EN               _SB_MAKEMASK1(0)
+#define M_DUART_RX_DIS              _SB_MAKEMASK1(1)
+#define M_DUART_TX_EN               _SB_MAKEMASK1(2)
+#define M_DUART_TX_DIS              _SB_MAKEMASK1(3)
+
+#define S_DUART_MISC_CMD            4
+#define M_DUART_MISC_CMD            _SB_MAKEMASK(3, S_DUART_MISC_CMD)
+#define V_DUART_MISC_CMD(x)         _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
+
+#define K_DUART_MISC_CMD_NOACTION0       0
+#define K_DUART_MISC_CMD_NOACTION1       1
+#define K_DUART_MISC_CMD_RESET_RX        2
+#define K_DUART_MISC_CMD_RESET_TX        3
+#define K_DUART_MISC_CMD_NOACTION4       4
+#define K_DUART_MISC_CMD_RESET_BREAK_INT 5
+#define K_DUART_MISC_CMD_START_BREAK     6
+#define K_DUART_MISC_CMD_STOP_BREAK      7
+
+#define V_DUART_MISC_CMD_NOACTION0       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
+#define V_DUART_MISC_CMD_NOACTION1       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
+#define V_DUART_MISC_CMD_RESET_RX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
+#define V_DUART_MISC_CMD_RESET_TX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
+#define V_DUART_MISC_CMD_NOACTION4       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
+#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
+#define V_DUART_MISC_CMD_START_BREAK     V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
+#define V_DUART_MISC_CMD_STOP_BREAK      V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
+
+#define M_DUART_CMD_RESERVED             _SB_MAKEMASK1(7)
+
+/*
+ * DUART Status Register (Table 10-6)
+ * Register: DUART_STATUS_A
+ * Register: DUART_STATUS_B
+ * READ-ONLY
+ */
+
+#define M_DUART_RX_RDY              _SB_MAKEMASK1(0)
+#define M_DUART_RX_FFUL             _SB_MAKEMASK1(1)
+#define M_DUART_TX_RDY              _SB_MAKEMASK1(2)
+#define M_DUART_TX_EMT              _SB_MAKEMASK1(3)
+#define M_DUART_OVRUN_ERR           _SB_MAKEMASK1(4)
+#define M_DUART_PARITY_ERR          _SB_MAKEMASK1(5)
+#define M_DUART_FRM_ERR             _SB_MAKEMASK1(6)
+#define M_DUART_RCVD_BRK            _SB_MAKEMASK1(7)
+
+/*
+ * DUART Baud Rate Register (Table 10-7)
+ * Register: DUART_CLK_SEL_A
+ * Register: DUART_CLK_SEL_B
+ */
+
+#define M_DUART_CLK_COUNTER         _SB_MAKEMASK(12, 0)
+#define V_DUART_BAUD_RATE(x)        (100000000/((x)*20)-1)
+
+/*
+ * DUART Data Registers (Table 10-8 and 10-9)
+ * Register: DUART_RX_HOLD_A
+ * Register: DUART_RX_HOLD_B
+ * Register: DUART_TX_HOLD_A
+ * Register: DUART_TX_HOLD_B
+ */
+
+#define M_DUART_RX_DATA             _SB_MAKEMASK(8, 0)
+#define M_DUART_TX_DATA             _SB_MAKEMASK(8, 0)
+
+/*
+ * DUART Input Port Register (Table 10-10)
+ * Register: DUART_IN_PORT
+ */
+
+#define M_DUART_IN_PIN0_VAL         _SB_MAKEMASK1(0)
+#define M_DUART_IN_PIN1_VAL         _SB_MAKEMASK1(1)
+#define M_DUART_IN_PIN2_VAL         _SB_MAKEMASK1(2)
+#define M_DUART_IN_PIN3_VAL         _SB_MAKEMASK1(3)
+#define M_DUART_IN_PIN4_VAL         _SB_MAKEMASK1(4)
+#define M_DUART_IN_PIN5_VAL         _SB_MAKEMASK1(5)
+#define M_DUART_RIN0_PIN            _SB_MAKEMASK1(6)
+#define M_DUART_RIN1_PIN            _SB_MAKEMASK1(7)
+
+/*
+ * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
+ * Register: DUART_INPORT_CHNG
+ */
+
+#define S_DUART_IN_PIN_VAL          0
+#define M_DUART_IN_PIN_VAL          _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
+
+#define S_DUART_IN_PIN_CHNG         4
+#define M_DUART_IN_PIN_CHNG         _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
+
+
+/*
+ * DUART Output port control register (Table 10-14)
+ * Register: DUART_OPCR
+ */
+
+#define M_DUART_OPCR_RESERVED0      _SB_MAKEMASK1(0)   /* must be zero */
+#define M_DUART_OPC2_SEL            _SB_MAKEMASK1(1)
+#define M_DUART_OPCR_RESERVED1      _SB_MAKEMASK1(2)   /* must be zero */
+#define M_DUART_OPC3_SEL            _SB_MAKEMASK1(3)
+#define M_DUART_OPCR_RESERVED2      _SB_MAKEMASK(4, 4)  /* must be zero */
+
+/*
+ * DUART Aux Control Register (Table 10-15)
+ * Register: DUART_AUX_CTRL
+ */
+
+#define M_DUART_IP0_CHNG_ENA        _SB_MAKEMASK1(0)
+#define M_DUART_IP1_CHNG_ENA        _SB_MAKEMASK1(1)
+#define M_DUART_IP2_CHNG_ENA        _SB_MAKEMASK1(2)
+#define M_DUART_IP3_CHNG_ENA        _SB_MAKEMASK1(3)
+#define M_DUART_ACR_RESERVED        _SB_MAKEMASK(4, 4)
+
+#define M_DUART_CTS_CHNG_ENA        _SB_MAKEMASK1(0)
+#define M_DUART_CIN_CHNG_ENA        _SB_MAKEMASK1(2)
+
+/*
+ * DUART Interrupt Status Register (Table 10-16)
+ * Register: DUART_ISR
+ */
+
+#define M_DUART_ISR_TX_A            _SB_MAKEMASK1(0)
+
+#define S_DUART_ISR_RX_A            1
+#define M_DUART_ISR_RX_A            _SB_MAKEMASK1(S_DUART_ISR_RX_A)
+#define V_DUART_ISR_RX_A(x)         _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
+#define G_DUART_ISR_RX_A(x)         _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
+
+#define M_DUART_ISR_BRK_A           _SB_MAKEMASK1(2)
+#define M_DUART_ISR_IN_A            _SB_MAKEMASK1(3)
+#define M_DUART_ISR_ALL_A           _SB_MAKEMASK(4, 0)
+
+#define M_DUART_ISR_TX_B            _SB_MAKEMASK1(4)
+#define M_DUART_ISR_RX_B            _SB_MAKEMASK1(5)
+#define M_DUART_ISR_BRK_B           _SB_MAKEMASK1(6)
+#define M_DUART_ISR_IN_B            _SB_MAKEMASK1(7)
+#define M_DUART_ISR_ALL_B           _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Channel A Interrupt Status Register (Table 10-17)
+ * DUART Channel B Interrupt Status Register (Table 10-18)
+ * Register: DUART_ISR_A
+ * Register: DUART_ISR_B
+ */
+
+#define M_DUART_ISR_TX              _SB_MAKEMASK1(0)
+#define M_DUART_ISR_RX              _SB_MAKEMASK1(1)
+#define M_DUART_ISR_BRK             _SB_MAKEMASK1(2)
+#define M_DUART_ISR_IN              _SB_MAKEMASK1(3)
+#define M_DUART_ISR_ALL             _SB_MAKEMASK(4, 0)
+#define M_DUART_ISR_RESERVED        _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Interrupt Mask Register (Table 10-19)
+ * Register: DUART_IMR
+ */
+
+#define M_DUART_IMR_TX_A            _SB_MAKEMASK1(0)
+#define M_DUART_IMR_RX_A            _SB_MAKEMASK1(1)
+#define M_DUART_IMR_BRK_A           _SB_MAKEMASK1(2)
+#define M_DUART_IMR_IN_A            _SB_MAKEMASK1(3)
+#define M_DUART_IMR_ALL_A           _SB_MAKEMASK(4, 0)
+
+#define M_DUART_IMR_TX_B            _SB_MAKEMASK1(4)
+#define M_DUART_IMR_RX_B            _SB_MAKEMASK1(5)
+#define M_DUART_IMR_BRK_B           _SB_MAKEMASK1(6)
+#define M_DUART_IMR_IN_B            _SB_MAKEMASK1(7)
+#define M_DUART_IMR_ALL_B           _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Channel A Interrupt Mask Register (Table 10-20)
+ * DUART Channel B Interrupt Mask Register (Table 10-21)
+ * Register: DUART_IMR_A
+ * Register: DUART_IMR_B
+ */
+
+#define M_DUART_IMR_TX              _SB_MAKEMASK1(0)
+#define M_DUART_IMR_RX              _SB_MAKEMASK1(1)
+#define M_DUART_IMR_BRK             _SB_MAKEMASK1(2)
+#define M_DUART_IMR_IN              _SB_MAKEMASK1(3)
+#define M_DUART_IMR_ALL             _SB_MAKEMASK(4, 0)
+#define M_DUART_IMR_RESERVED        _SB_MAKEMASK(4, 4)
+
+
+/*
+ * DUART Output Port Set Register (Table 10-22)
+ * Register: DUART_SET_OPR
+ */
+
+#define M_DUART_SET_OPR0            _SB_MAKEMASK1(0)
+#define M_DUART_SET_OPR1            _SB_MAKEMASK1(1)
+#define M_DUART_SET_OPR2            _SB_MAKEMASK1(2)
+#define M_DUART_SET_OPR3            _SB_MAKEMASK1(3)
+#define M_DUART_OPSR_RESERVED       _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Output Port Clear Register (Table 10-23)
+ * Register: DUART_CLEAR_OPR
+ */
+
+#define M_DUART_CLR_OPR0            _SB_MAKEMASK1(0)
+#define M_DUART_CLR_OPR1            _SB_MAKEMASK1(1)
+#define M_DUART_CLR_OPR2            _SB_MAKEMASK1(2)
+#define M_DUART_CLR_OPR3            _SB_MAKEMASK1(3)
+#define M_DUART_OPCR_RESERVED       _SB_MAKEMASK(4, 4)
+
+/*
+ * DUART Output Port RTS Register (Table 10-24)
+ * Register: DUART_OUT_PORT
+ */
+
+#define M_DUART_OUT_PIN_SET0        _SB_MAKEMASK1(0)
+#define M_DUART_OUT_PIN_SET1        _SB_MAKEMASK1(1)
+#define M_DUART_OUT_PIN_CLR0        _SB_MAKEMASK1(2)
+#define M_DUART_OUT_PIN_CLR1        _SB_MAKEMASK1(3)
+#define M_DUART_OPRR_RESERVED       _SB_MAKEMASK(4, 4)
+
+#define M_DUART_OUT_PIN_SET(chan) \
+    (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
+#define M_DUART_OUT_PIN_CLR(chan) \
+    (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
+
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
+/*
+ * Full Interrupt Control Register
+ */
+
+#define S_DUART_SIG_FULL           _SB_MAKE64(0)
+#define M_DUART_SIG_FULL           _SB_MAKEMASK(4, S_DUART_SIG_FULL)
+#define V_DUART_SIG_FULL(x)        _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
+#define G_DUART_SIG_FULL(x)        _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
+
+#define S_DUART_INT_TIME           _SB_MAKE64(4)
+#define M_DUART_INT_TIME           _SB_MAKEMASK(4, S_DUART_INT_TIME)
+#define V_DUART_INT_TIME(x)        _SB_MAKEVALUE(x, S_DUART_INT_TIME)
+#define G_DUART_INT_TIME(x)        _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
+#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
+
+
+/* ********************************************************************** */
+
+
+#endif
diff --git a/arch/mips/include/asm/sibyte/sentosa.h b/arch/mips/include/asm/sibyte/sentosa.h
new file mode 100644
index 000000000000..64c47874f32d
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/sentosa.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ASM_SIBYTE_SENTOSA_H
+#define __ASM_SIBYTE_SENTOSA_H
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_int.h>
+
+#ifdef CONFIG_SIBYTE_SENTOSA
+#define SIBYTE_BOARD_NAME "BCM91250E (Sentosa)"
+#endif
+#ifdef CONFIG_SIBYTE_RHONE
+#define SIBYTE_BOARD_NAME "BCM91125E (Rhone)"
+#endif
+
+/* Generic bus chip selects */
+#ifdef CONFIG_SIBYTE_RHONE
+#define LEDS_CS         6
+#define LEDS_PHYS       0x1d0a0000
+#endif
+
+/* GPIOs */
+#define K_GPIO_DBG_LED  0
+
+#endif /* __ASM_SIBYTE_SENTOSA_H */
diff --git a/arch/mips/include/asm/sibyte/swarm.h b/arch/mips/include/asm/sibyte/swarm.h
new file mode 100644
index 000000000000..114d9d29ca9d
--- /dev/null
+++ b/arch/mips/include/asm/sibyte/swarm.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ASM_SIBYTE_SWARM_H
+#define __ASM_SIBYTE_SWARM_H
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_int.h>
+
+#ifdef CONFIG_SIBYTE_SWARM
+#define SIBYTE_BOARD_NAME "BCM91250A (SWARM)"
+#define SIBYTE_HAVE_PCMCIA 1
+#define SIBYTE_HAVE_IDE    1
+#endif
+#ifdef CONFIG_SIBYTE_LITTLESUR
+#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
+#define SIBYTE_HAVE_PCMCIA 0
+#define SIBYTE_HAVE_IDE    1
+#define SIBYTE_DEFAULT_CONSOLE "cfe0"
+#endif
+#ifdef CONFIG_SIBYTE_CRHONE
+#define SIBYTE_BOARD_NAME "BCM91125C (CRhone)"
+#define SIBYTE_HAVE_PCMCIA 0
+#define SIBYTE_HAVE_IDE    0
+#endif
+#ifdef CONFIG_SIBYTE_CRHINE
+#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)"
+#define SIBYTE_HAVE_PCMCIA 0
+#define SIBYTE_HAVE_IDE    0
+#endif
+
+/* Generic bus chip selects */
+#define LEDS_CS         3
+#define LEDS_PHYS       0x100a0000
+
+#ifdef SIBYTE_HAVE_IDE
+#define IDE_CS          4
+#define IDE_PHYS        0x100b0000
+#define K_GPIO_GB_IDE   4
+#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#endif
+
+#ifdef SIBYTE_HAVE_PCMCIA
+#define PCMCIA_CS       6
+#define PCMCIA_PHYS     0x11000000
+#define K_GPIO_PC_READY 9
+#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
+#endif
+
+#endif /* __ASM_SIBYTE_SWARM_H */
diff --git a/arch/mips/include/asm/sigcontext.h b/arch/mips/include/asm/sigcontext.h
new file mode 100644
index 000000000000..9ce0607d7a4e
--- /dev/null
+++ b/arch/mips/include/asm/sigcontext.h
@@ -0,0 +1,100 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIGCONTEXT_H
+#define _ASM_SIGCONTEXT_H
+
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Keep this struct definition in sync with the sigcontext fragment
+ * in arch/mips/tools/offset.c
+ */
+struct sigcontext {
+        unsigned int            sc_regmask;     /* Unused */
+        unsigned int            sc_status;      /* Unused */
+        unsigned long long      sc_pc;
+        unsigned long long      sc_regs[32];
+        unsigned long long      sc_fpregs[32];
+        unsigned int            sc_acx;         /* Was sc_ownedfp */
+        unsigned int            sc_fpc_csr;
+        unsigned int            sc_fpc_eir;     /* Unused */
+        unsigned int            sc_used_math;
+        unsigned int            sc_dsp;         /* dsp status, was sc_ssflags */
+        unsigned long long      sc_mdhi;
+        unsigned long long      sc_mdlo;
+        unsigned long           sc_hi1;         /* Was sc_cause */
+        unsigned long           sc_lo1;         /* Was sc_badvaddr */
+        unsigned long           sc_hi2;         /* Was sc_sigset[4] */
+        unsigned long           sc_lo2;
+        unsigned long           sc_hi3;
+        unsigned long           sc_lo3;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#include <linux/posix_types.h>
+/*
+ * Keep this struct definition in sync with the sigcontext fragment
+ * in arch/mips/tools/offset.c
+ *
+ * Warning: this structure illdefined with sc_badvaddr being just an unsigned
+ * int so it was changed to unsigned long in 2.6.0-test1.  This may break
+ * binary compatibility - no prisoners.
+ * DSP ASE in 2.6.12-rc4.  Turn sc_mdhi and sc_mdlo into an array of four
+ * entries, add sc_dsp and sc_reserved for padding.  No prisoners.
+ */
+struct sigcontext {
+        __u64   sc_regs[32];
+        __u64   sc_fpregs[32];
+        __u64   sc_mdhi;
+        __u64   sc_hi1;
+        __u64   sc_hi2;
+        __u64   sc_hi3;
+        __u64   sc_mdlo;
+        __u64   sc_lo1;
+        __u64   sc_lo2;
+        __u64   sc_lo3;
+        __u64   sc_pc;
+        __u32   sc_fpc_csr;
+        __u32   sc_used_math;
+        __u32   sc_dsp;
+        __u32   sc_reserved;
+};
+
+#ifdef __KERNEL__
+
+struct sigcontext32 {
+        __u32           sc_regmask;     /* Unused */
+        __u32           sc_status;      /* Unused */
+        __u64           sc_pc;
+        __u64           sc_regs[32];
+        __u64           sc_fpregs[32];
+        __u32           sc_acx;         /* Only MIPS32; was sc_ownedfp */
+        __u32           sc_fpc_csr;
+        __u32           sc_fpc_eir;     /* Unused */
+        __u32           sc_used_math;
+        __u32           sc_dsp;         /* dsp status, was sc_ssflags */
+        __u64           sc_mdhi;
+        __u64           sc_mdlo;
+        __u32           sc_hi1;         /* Was sc_cause */
+        __u32           sc_lo1;         /* Was sc_badvaddr */
+        __u32           sc_hi2;         /* Was sc_sigset[4] */
+        __u32           sc_lo2;
+        __u32           sc_hi3;
+        __u32           sc_lo3;
+};
+#endif /* __KERNEL__ */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _ASM_SIGCONTEXT_H */
diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h
new file mode 100644
index 000000000000..96e28f18dad1
--- /dev/null
+++ b/arch/mips/include/asm/siginfo.h
@@ -0,0 +1,130 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 1999, 2001, 2003 Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIGINFO_H
+#define _ASM_SIGINFO_H
+
+
+#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
+#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ...  */
+
+#define HAVE_ARCH_SIGINFO_T
+
+/*
+ * We duplicate the generic versions - <asm-generic/siginfo.h> is just borked
+ * by design ...
+ */
+#define HAVE_ARCH_COPY_SIGINFO
+struct siginfo;
+
+/*
+ * Careful to keep union _sifields from shifting ...
+ */
+#ifdef CONFIG_32BIT
+#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
+#endif
+#ifdef CONFIG_64BIT
+#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
+#endif
+
+#include <asm-generic/siginfo.h>
+
+typedef struct siginfo {
+        int si_signo;
+        int si_code;
+        int si_errno;
+        int __pad0[SI_MAX_SIZE / sizeof(int) - SI_PAD_SIZE - 3];
+
+        union {
+                int _pad[SI_PAD_SIZE];
+
+                /* kill() */
+                struct {
+                        pid_t _pid;             /* sender's pid */
+                        __ARCH_SI_UID_T _uid;   /* sender's uid */
+                } _kill;
+
+                /* POSIX.1b timers */
+                struct {
+                        timer_t _tid;           /* timer id */
+                        int _overrun;           /* overrun count */
+                        char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
+                        sigval_t _sigval;       /* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        pid_t _pid;             /* sender's pid */
+                        __ARCH_SI_UID_T _uid;   /* sender's uid */
+                        sigval_t _sigval;
+                } _rt;
+
+                /* SIGCHLD */
+                struct {
+                        pid_t _pid;             /* which child */
+                        __ARCH_SI_UID_T _uid;   /* sender's uid */
+                        int _status;            /* exit code */
+                        clock_t _utime;
+                        clock_t _stime;
+                } _sigchld;
+
+                /* IRIX SIGCHLD */
+                struct {
+                        pid_t _pid;             /* which child */
+                        clock_t _utime;
+                        int _status;            /* exit code */
+                        clock_t _stime;
+                } _irix_sigchld;
+
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        void __user *_addr; /* faulting insn/memory ref. */
+#ifdef __ARCH_SI_TRAPNO
+                        int _trapno;    /* TRAP # which caused the signal */
+#endif
+                } _sigfault;
+
+                /* SIGPOLL, SIGXFSZ (To do ...)  */
+                struct {
+                        __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+        } _sifields;
+} siginfo_t;
+
+/*
+ * si_code values
+ * Again these have been choosen to be IRIX compatible.
+ */
+#undef SI_ASYNCIO
+#undef SI_TIMER
+#undef SI_MESGQ
+#define SI_ASYNCIO      -2      /* sent by AIO completion */
+#define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */
+#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */
+
+#ifdef __KERNEL__
+
+/*
+ * Duplicated here because of <asm-generic/siginfo.h> braindamage ...
+ */
+#include <linux/string.h>
+
+static inline void copy_siginfo(struct siginfo *to, struct siginfo *from)
+{
+        if (from->si_code < 0)
+                memcpy(to, from, sizeof(*to));
+        else
+                /* _sigchld is currently the largest know union member */
+                memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld));
+}
+
+#endif
+
+#endif /* _ASM_SIGINFO_H */
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
new file mode 100644
index 000000000000..bee5153aca48
--- /dev/null
+++ b/arch/mips/include/asm/signal.h
@@ -0,0 +1,139 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIGNAL_H
+#define _ASM_SIGNAL_H
+
+#include <linux/types.h>
+
+#define _NSIG           128
+#define _NSIG_BPW       (sizeof(unsigned long) * 8)
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+#define SIGHUP           1      /* Hangup (POSIX).  */
+#define SIGINT           2      /* Interrupt (ANSI).  */
+#define SIGQUIT          3      /* Quit (POSIX).  */
+#define SIGILL           4      /* Illegal instruction (ANSI).  */
+#define SIGTRAP          5      /* Trace trap (POSIX).  */
+#define SIGIOT           6      /* IOT trap (4.2 BSD).  */
+#define SIGABRT          SIGIOT /* Abort (ANSI).  */
+#define SIGEMT           7
+#define SIGFPE           8      /* Floating-point exception (ANSI).  */
+#define SIGKILL          9      /* Kill, unblockable (POSIX).  */
+#define SIGBUS          10      /* BUS error (4.2 BSD).  */
+#define SIGSEGV         11      /* Segmentation violation (ANSI).  */
+#define SIGSYS          12
+#define SIGPIPE         13      /* Broken pipe (POSIX).  */
+#define SIGALRM         14      /* Alarm clock (POSIX).  */
+#define SIGTERM         15      /* Termination (ANSI).  */
+#define SIGUSR1         16      /* User-defined signal 1 (POSIX).  */
+#define SIGUSR2         17      /* User-defined signal 2 (POSIX).  */
+#define SIGCHLD         18      /* Child status has changed (POSIX).  */
+#define SIGCLD          SIGCHLD /* Same as SIGCHLD (System V).  */
+#define SIGPWR          19      /* Power failure restart (System V).  */
+#define SIGWINCH        20      /* Window size change (4.3 BSD, Sun).  */
+#define SIGURG          21      /* Urgent condition on socket (4.2 BSD).  */
+#define SIGIO           22      /* I/O now possible (4.2 BSD).  */
+#define SIGPOLL         SIGIO   /* Pollable event occurred (System V).  */
+#define SIGSTOP         23      /* Stop, unblockable (POSIX).  */
+#define SIGTSTP         24      /* Keyboard stop (POSIX).  */
+#define SIGCONT         25      /* Continue (POSIX).  */
+#define SIGTTIN         26      /* Background read from tty (POSIX).  */
+#define SIGTTOU         27      /* Background write to tty (POSIX).  */
+#define SIGVTALRM       28      /* Virtual alarm clock (4.2 BSD).  */
+#define SIGPROF         29      /* Profiling alarm clock (4.2 BSD).  */
+#define SIGXCPU         30      /* CPU limit exceeded (4.2 BSD).  */
+#define SIGXFSZ         31      /* File size limit exceeded (4.2 BSD).  */
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_ONSTACK      0x08000000
+#define SA_RESETHAND    0x80000000
+#define SA_RESTART      0x10000000
+#define SA_SIGINFO      0x00000008
+#define SA_NODEFER      0x40000000
+#define SA_NOCLDWAIT    0x00010000
+#define SA_NOCLDSTOP    0x00000001
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+#define SA_RESTORER     0x04000000      /* Only for o32 */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK     1
+#define SS_DISABLE     2
+
+#define MINSIGSTKSZ    2048
+#define SIGSTKSZ       8192
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_TRAD_SIGNALS
+#define sig_uses_siginfo(ka)    ((ka)->sa.sa_flags & SA_SIGINFO)
+#else
+#define sig_uses_siginfo(ka)    (1)
+#endif
+
+#endif /* __KERNEL__ */
+
+#define SIG_BLOCK       1       /* for blocking signals */
+#define SIG_UNBLOCK     2       /* for unblocking signals */
+#define SIG_SETMASK     3       /* for setting the signal mask */
+
+#include <asm-generic/signal.h>
+
+struct sigaction {
+        unsigned int    sa_flags;
+        __sighandler_t  sa_handler;
+        sigset_t        sa_mask;
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+
+/* IRIX compatible stack_t  */
+typedef struct sigaltstack {
+        void __user *ss_sp;
+        size_t ss_size;
+        int ss_flags;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+#include <asm/siginfo.h>
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_SIGNAL_H */
diff --git a/arch/mips/include/asm/sim.h b/arch/mips/include/asm/sim.h
new file mode 100644
index 000000000000..0cd719fabb51
--- /dev/null
+++ b/arch/mips/include/asm/sim.h
@@ -0,0 +1,82 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SIM_H
+#define _ASM_SIM_H
+
+
+#include <asm/asm-offsets.h>
+
+#define __str2(x) #x
+#define __str(x) __str2(x)
+
+#ifdef CONFIG_32BIT
+
+#define save_static_function(symbol)                                    \
+__asm__(                                                                \
+        ".text\n\t"                                                     \
+        ".globl\t" #symbol "\n\t"                                       \
+        ".align\t2\n\t"                                                 \
+        ".type\t" #symbol ", @function\n\t"                             \
+        ".ent\t" #symbol ", 0\n"                                        \
+        #symbol":\n\t"                                                  \
+        ".frame\t$29, 0, $31\n\t"                                       \
+        "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t"  \
+        "sw\t$17,"__str(PT_R17)"($29)\n\t"                              \
+        "sw\t$18,"__str(PT_R18)"($29)\n\t"                              \
+        "sw\t$19,"__str(PT_R19)"($29)\n\t"                              \
+        "sw\t$20,"__str(PT_R20)"($29)\n\t"                              \
+        "sw\t$21,"__str(PT_R21)"($29)\n\t"                              \
+        "sw\t$22,"__str(PT_R22)"($29)\n\t"                              \
+        "sw\t$23,"__str(PT_R23)"($29)\n\t"                              \
+        "sw\t$30,"__str(PT_R30)"($29)\n\t"                              \
+        "j\t_" #symbol "\n\t"                                           \
+        ".end\t" #symbol "\n\t"                                         \
+        ".size\t" #symbol",. - " #symbol)
+
+#define nabi_no_regargs
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#define save_static_function(symbol)                                    \
+__asm__(                                                                \
+        ".text\n\t"                                                     \
+        ".globl\t" #symbol "\n\t"                                       \
+        ".align\t2\n\t"                                                 \
+        ".type\t" #symbol ", @function\n\t"                             \
+        ".ent\t" #symbol ", 0\n"                                        \
+        #symbol":\n\t"                                                  \
+        ".frame\t$29, 0, $31\n\t"                                       \
+        "sd\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t"  \
+        "sd\t$17,"__str(PT_R17)"($29)\n\t"                              \
+        "sd\t$18,"__str(PT_R18)"($29)\n\t"                              \
+        "sd\t$19,"__str(PT_R19)"($29)\n\t"                              \
+        "sd\t$20,"__str(PT_R20)"($29)\n\t"                              \
+        "sd\t$21,"__str(PT_R21)"($29)\n\t"                              \
+        "sd\t$22,"__str(PT_R22)"($29)\n\t"                              \
+        "sd\t$23,"__str(PT_R23)"($29)\n\t"                              \
+        "sd\t$30,"__str(PT_R30)"($29)\n\t"                              \
+        "j\t_" #symbol "\n\t"                                           \
+        ".end\t" #symbol "\n\t"                                         \
+        ".size\t" #symbol",. - " #symbol)
+
+#define nabi_no_regargs                                                 \
+        unsigned long __dummy0,                                         \
+        unsigned long __dummy1,                                         \
+        unsigned long __dummy2,                                         \
+        unsigned long __dummy3,                                         \
+        unsigned long __dummy4,                                         \
+        unsigned long __dummy5,                                         \
+        unsigned long __dummy6,                                         \
+        unsigned long __dummy7,
+
+#endif /* CONFIG_64BIT */
+
+#endif /* _ASM_SIM_H */
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
new file mode 100644
index 000000000000..43c207e72a63
--- /dev/null
+++ b/arch/mips/include/asm/smp-ops.h
@@ -0,0 +1,57 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
+ * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
+ * Copyright (C) 2000, 2001, 2002 Ralf Baechle
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ */
+#ifndef __ASM_SMP_OPS_H
+#define __ASM_SMP_OPS_H
+
+#ifdef CONFIG_SMP
+
+#include <linux/cpumask.h>
+
+struct plat_smp_ops {
+        void (*send_ipi_single)(int cpu, unsigned int action);
+        void (*send_ipi_mask)(cpumask_t mask, unsigned int action);
+        void (*init_secondary)(void);
+        void (*smp_finish)(void);
+        void (*cpus_done)(void);
+        void (*boot_secondary)(int cpu, struct task_struct *idle);
+        void (*smp_setup)(void);
+        void (*prepare_cpus)(unsigned int max_cpus);
+};
+
+extern void register_smp_ops(struct plat_smp_ops *ops);
+
+static inline void plat_smp_setup(void)
+{
+        extern struct plat_smp_ops *mp_ops;     /* private */
+
+        mp_ops->smp_setup();
+}
+
+#else /* !CONFIG_SMP */
+
+struct plat_smp_ops;
+
+static inline void plat_smp_setup(void)
+{
+        /* UP, nothing to do ...  */
+}
+
+static inline void register_smp_ops(struct plat_smp_ops *ops)
+{
+}
+
+#endif /* !CONFIG_SMP */
+
+extern struct plat_smp_ops up_smp_ops;
+extern struct plat_smp_ops cmp_smp_ops;
+extern struct plat_smp_ops vsmp_smp_ops;
+
+#endif /* __ASM_SMP_OPS_H */
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
new file mode 100644
index 000000000000..0ff5b523ea77
--- /dev/null
+++ b/arch/mips/include/asm/smp.h
@@ -0,0 +1,63 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of this
+ * archive for more details.
+ *
+ * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
+ * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
+ * Copyright (C) 2000, 2001, 2002 Ralf Baechle
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ */
+#ifndef __ASM_SMP_H
+#define __ASM_SMP_H
+
+#include <linux/bitops.h>
+#include <linux/linkage.h>
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+
+#include <asm/atomic.h>
+#include <asm/smp-ops.h>
+
+extern int smp_num_siblings;
+extern cpumask_t cpu_sibling_map[];
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+/* Map from cpu id to sequential logical cpu number.  This will only
+   not be idempotent when cpus failed to come on-line.  */
+extern int __cpu_number_map[NR_CPUS];
+#define cpu_number_map(cpu)  __cpu_number_map[cpu]
+
+/* The reverse map from sequential logical cpu number to cpu id.  */
+extern int __cpu_logical_map[NR_CPUS];
+#define cpu_logical_map(cpu)  __cpu_logical_map[cpu]
+
+#define NO_PROC_ID      (-1)
+
+#define SMP_RESCHEDULE_YOURSELF 0x1     /* XXX braindead */
+#define SMP_CALL_FUNCTION       0x2
+
+extern cpumask_t phys_cpu_present_map;
+#define cpu_possible_map        phys_cpu_present_map
+
+extern void asmlinkage smp_bootstrap(void);
+
+/*
+ * this function sends a 'reschedule' IPI to another CPU.
+ * it goes straight through and wastes no time serializing
+ * anything. Worst case is that we lose a reschedule ...
+ */
+static inline void smp_send_reschedule(int cpu)
+{
+        extern struct plat_smp_ops *mp_ops;     /* private */
+
+        mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF);
+}
+
+extern asmlinkage void smp_call_function_interrupt(void);
+
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi(cpumask_t mask);
+
+#endif /* __ASM_SMP_H */
diff --git a/arch/mips/include/asm/smtc.h b/arch/mips/include/asm/smtc.h
new file mode 100644
index 000000000000..ea60bf08dcb0
--- /dev/null
+++ b/arch/mips/include/asm/smtc.h
@@ -0,0 +1,71 @@
+#ifndef _ASM_SMTC_MT_H
+#define _ASM_SMTC_MT_H
+
+/*
+ * Definitions for SMTC multitasking on MIPS MT cores
+ */
+
+#include <asm/mips_mt.h>
+#include <asm/smtc_ipi.h>
+
+/*
+ * System-wide SMTC status information
+ */
+
+extern unsigned int smtc_status;
+
+#define SMTC_TLB_SHARED 0x00000001
+#define SMTC_MTC_ACTIVE 0x00000002
+
+/*
+ * TLB/ASID Management information
+ */
+
+#define MAX_SMTC_TLBS 2
+#define MAX_SMTC_ASIDS 256
+#if NR_CPUS <= 8
+typedef char asiduse;
+#else
+#if NR_CPUS <= 16
+typedef short asiduse;
+#else
+typedef long asiduse;
+#endif
+#endif
+
+extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
+
+struct mm_struct;
+struct task_struct;
+
+void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
+void self_ipi(struct smtc_ipi *);
+void smtc_flush_tlb_asid(unsigned long asid);
+extern int smtc_build_cpu_map(int startslot);
+extern void smtc_prepare_cpus(int cpus);
+extern void smtc_smp_finish(void);
+extern void smtc_boot_secondary(int cpu, struct task_struct *t);
+extern void smtc_cpus_done(void);
+
+
+/*
+ * Sharing the TLB between multiple VPEs means that the
+ * "random" index selection function is not allowed to
+ * select the current value of the Index register. To
+ * avoid additional TLB pressure, the Index registers
+ * are "parked" with an non-Valid value.
+ */
+
+#define PARKED_INDEX    ((unsigned int)0x80000000)
+
+/*
+ * Define low-level interrupt mask for IPIs, if necessary.
+ * By default, use SW interrupt 1, which requires no external
+ * hardware support, but which works only for single-core
+ * MIPS MT systems.
+ */
+#ifndef MIPS_CPU_IPI_IRQ
+#define MIPS_CPU_IPI_IRQ 1
+#endif
+
+#endif /*  _ASM_SMTC_MT_H */
diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h
new file mode 100644
index 000000000000..8ce517574340
--- /dev/null
+++ b/arch/mips/include/asm/smtc_ipi.h
@@ -0,0 +1,128 @@
+/*
+ * Definitions used in MIPS MT SMTC "Interprocessor Interrupt" code.
+ */
+#ifndef __ASM_SMTC_IPI_H
+#define __ASM_SMTC_IPI_H
+
+#include <linux/spinlock.h>
+
+//#define SMTC_IPI_DEBUG
+
+#ifdef SMTC_IPI_DEBUG
+#include <asm/mipsregs.h>
+#include <asm/mipsmtregs.h>
+#endif /* SMTC_IPI_DEBUG */
+
+/*
+ * An IPI "message"
+ */
+
+struct smtc_ipi {
+        struct smtc_ipi *flink;
+        int type;
+        void *arg;
+        int dest;
+#ifdef  SMTC_IPI_DEBUG
+        int sender;
+        long stamp;
+#endif /* SMTC_IPI_DEBUG */
+};
+
+/*
+ * Defined IPI Types
+ */
+
+#define LINUX_SMP_IPI 1
+#define SMTC_CLOCK_TICK 2
+#define IRQ_AFFINITY_IPI 3
+
+/*
+ * A queue of IPI messages
+ */
+
+struct smtc_ipi_q {
+        struct smtc_ipi *head;
+        spinlock_t lock;
+        struct smtc_ipi *tail;
+        int depth;
+};
+
+static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&q->lock, flags);
+        if (q->head == NULL)
+                q->head = q->tail = p;
+        else
+                q->tail->flink = p;
+        p->flink = NULL;
+        q->tail = p;
+        q->depth++;
+#ifdef  SMTC_IPI_DEBUG
+        p->sender = read_c0_tcbind();
+        p->stamp = read_c0_count();
+#endif /* SMTC_IPI_DEBUG */
+        spin_unlock_irqrestore(&q->lock, flags);
+}
+
+static inline struct smtc_ipi *__smtc_ipi_dq(struct smtc_ipi_q *q)
+{
+        struct smtc_ipi *p;
+
+        if (q->head == NULL)
+                p = NULL;
+        else {
+                p = q->head;
+                q->head = q->head->flink;
+                q->depth--;
+                /* Arguably unnecessary, but leaves queue cleaner */
+                if (q->head == NULL)
+                        q->tail = NULL;
+        }
+
+        return p;
+}
+
+static inline struct smtc_ipi *smtc_ipi_dq(struct smtc_ipi_q *q)
+{
+        unsigned long flags;
+        struct smtc_ipi *p;
+
+        spin_lock_irqsave(&q->lock, flags);
+        p = __smtc_ipi_dq(q);
+        spin_unlock_irqrestore(&q->lock, flags);
+
+        return p;
+}
+
+static inline void smtc_ipi_req(struct smtc_ipi_q *q, struct smtc_ipi *p)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&q->lock, flags);
+        if (q->head == NULL) {
+                q->head = q->tail = p;
+                p->flink = NULL;
+        } else {
+                p->flink = q->head;
+                q->head = p;
+        }
+        q->depth++;
+        spin_unlock_irqrestore(&q->lock, flags);
+}
+
+static inline int smtc_ipi_qdepth(struct smtc_ipi_q *q)
+{
+        unsigned long flags;
+        int retval;
+
+        spin_lock_irqsave(&q->lock, flags);
+        retval = q->depth;
+        spin_unlock_irqrestore(&q->lock, flags);
+        return retval;
+}
+
+extern void smtc_send_ipi(int cpu, int type, unsigned int action);
+
+#endif /* __ASM_SMTC_IPI_H */
diff --git a/arch/mips/include/asm/smtc_proc.h b/arch/mips/include/asm/smtc_proc.h
new file mode 100644
index 000000000000..25da651f1f5f
--- /dev/null
+++ b/arch/mips/include/asm/smtc_proc.h
@@ -0,0 +1,23 @@
+/*
+ * Definitions for SMTC /proc entries
+ * Copyright(C) 2005 MIPS Technologies Inc.
+ */
+#ifndef __ASM_SMTC_PROC_H
+#define __ASM_SMTC_PROC_H
+
+/*
+ * per-"CPU" statistics
+ */
+
+struct smtc_cpu_proc {
+        unsigned long timerints;
+        unsigned long selfipis;
+};
+
+extern struct smtc_cpu_proc smtc_cpu_stats[NR_CPUS];
+
+/* Count of number of recoveries of "stolen" FPU access rights on 34K */
+
+extern atomic_t smtc_fpu_recoveries;
+
+#endif /* __ASM_SMTC_PROC_H */
diff --git a/arch/mips/include/asm/smvp.h b/arch/mips/include/asm/smvp.h
new file mode 100644
index 000000000000..0d0e80a39e8a
--- /dev/null
+++ b/arch/mips/include/asm/smvp.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_SMVP_H
+#define _ASM_SMVP_H
+
+/*
+ * Definitions for SMVP multitasking on MIPS MT cores
+ */
+struct task_struct;
+
+extern void smvp_smp_setup(void);
+extern void smvp_smp_finish(void);
+extern void smvp_boot_secondary(int cpu, struct task_struct *t);
+extern void smvp_init_secondary(void);
+extern void smvp_smp_finish(void);
+extern void smvp_cpus_done(void);
+extern void smvp_prepare_cpus(unsigned int max_cpus);
+
+/* This is platform specific */
+extern void smvp_send_ipi(int cpu, unsigned int action);
+#endif /*  _ASM_SMVP_H */
diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
new file mode 100644
index 000000000000..fec9bdd34913
--- /dev/null
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -0,0 +1,430 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_SN_ADDRS_H
+#define _ASM_SN_ADDRS_H
+
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif /* !__ASSEMBLY__ */
+
+#include <asm/addrspace.h>
+#include <asm/sn/kldir.h>
+
+#if defined(CONFIG_SGI_IP27)
+#include <asm/sn/sn0/addrs.h>
+#elif defined(CONFIG_SGI_IP35)
+#include <asm/sn/sn1/addrs.h>
+#endif
+
+
+#ifndef __ASSEMBLY__
+
+#define PS_UINT_CAST            (unsigned long)
+#define UINT64_CAST             (unsigned long)
+
+#define HUBREG_CAST             (volatile hubreg_t *)
+
+#else /* __ASSEMBLY__ */
+
+#define PS_UINT_CAST
+#define UINT64_CAST
+#define HUBREG_CAST
+
+#endif /* __ASSEMBLY__ */
+
+
+#define NASID_GET_META(_n)      ((_n) >> NASID_LOCAL_BITS)
+#ifdef CONFIG_SGI_IP27
+#define NASID_GET_LOCAL(_n)     ((_n) & 0xf)
+#endif
+#define NASID_MAKE(_m, _l)      (((_m) << NASID_LOCAL_BITS) | (_l))
+
+#define NODE_ADDRSPACE_MASK     (NODE_ADDRSPACE_SIZE - 1)
+#define TO_NODE_ADDRSPACE(_pa)  (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
+
+#define CHANGE_ADDR_NASID(_pa, _nasid)  \
+                ((UINT64_CAST(_pa) & ~NASID_MASK) | \
+                 (UINT64_CAST(_nasid) <<  NASID_SHFT))
+
+
+/*
+ * The following macros are used to index to the beginning of a specific
+ * node's address space.
+ */
+
+#define NODE_OFFSET(_n)         (UINT64_CAST (_n) << NODE_SIZE_BITS)
+
+#define NODE_CAC_BASE(_n)       (CAC_BASE   + NODE_OFFSET(_n))
+#define NODE_HSPEC_BASE(_n)     (HSPEC_BASE + NODE_OFFSET(_n))
+#define NODE_IO_BASE(_n)        (IO_BASE    + NODE_OFFSET(_n))
+#define NODE_MSPEC_BASE(_n)     (MSPEC_BASE + NODE_OFFSET(_n))
+#define NODE_UNCAC_BASE(_n)     (UNCAC_BASE + NODE_OFFSET(_n))
+
+#define TO_NODE(_n, _x)         (NODE_OFFSET(_n)     | ((_x)               ))
+#define TO_NODE_CAC(_n, _x)     (NODE_CAC_BASE(_n)   | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_UNCAC(_n, _x)   (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_MSPEC(_n, _x)   (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+#define TO_NODE_HSPEC(_n, _x)   (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
+
+
+#define RAW_NODE_SWIN_BASE(nasid, widget)                               \
+        (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
+
+#define WIDGETID_GET(addr)      ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define SWIN_SIZE_BITS          24
+#define SWIN_SIZE               (UINT64_CAST 1 << 24)
+#define SWIN_SIZEMASK           (SWIN_SIZE - 1)
+#define SWIN_WIDGET_MASK        0xF
+
+/*
+ * Convert smallwindow address to xtalk address.
+ *
+ * 'addr' can be physical or virtual address, but will be converted
+ * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
+ */
+#define SWIN_WIDGETADDR(addr)   ((addr) & SWIN_SIZEMASK)
+#define SWIN_WIDGETNUM(addr)    (((addr)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
+/*
+ * Verify if addr belongs to small window address on node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+#define NODE_SWIN_ADDR(nasid, addr)     \
+                (((addr) >= NODE_SWIN_BASE(nasid, 0))  && \
+                 ((addr) <  (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
+                 ))
+
+/*
+ * The following define the major position-independent aliases used
+ * in SN.
+ *      UALIAS -- 256MB in size, reads in the UALIAS result in
+ *                      uncached references to the memory of the reader's node.
+ *      CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
+ *                      depending on which CPU does the access to provide
+ *                      all CPUs with unique uncached memory at low addresses.
+ *      LBOOT  -- 256MB in size, reads in the LBOOT area result in
+ *                      uncached references to the local hub's boot prom and
+ *                      other directory-bus connected devices.
+ *      IALIAS -- 8MB in size, reads in the IALIAS result in uncached
+ *                      references to the local hub's registers.
+ */
+
+#define UALIAS_BASE             HSPEC_BASE
+#define UALIAS_SIZE             0x10000000      /* 256 Megabytes */
+#define UALIAS_LIMIT            (UALIAS_BASE + UALIAS_SIZE)
+
+/*
+ * The bottom of ualias space is flipped depending on whether you're
+ * processor 0 or 1 within a node.
+ */
+#ifdef CONFIG_SGI_IP27
+#define UALIAS_FLIP_BASE        UALIAS_BASE
+#define UALIAS_FLIP_SIZE        0x20000
+#define UALIAS_FLIP_BIT         0x10000
+#define UALIAS_FLIP_ADDR(_x)    (cputoslice(smp_processor_id()) ? \
+                                 (_x) ^ UALIAS_FLIP_BIT : (_x))
+
+#define LBOOT_BASE              (HSPEC_BASE + 0x10000000)
+#define LBOOT_SIZE              0x10000000
+#define LBOOT_LIMIT             (LBOOT_BASE + LBOOT_SIZE)
+#define LBOOT_STRIDE            0               /* IP27 has only one CPU PROM */
+
+#endif
+
+#define HUB_REGISTER_WIDGET     1
+#define IALIAS_BASE             NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
+#define IALIAS_SIZE             0x800000        /* 8 Megabytes */
+#define IS_IALIAS(_a)           (((_a) >= IALIAS_BASE) &&               \
+                                 ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
+
+/*
+ * Macro for referring to Hub's RBOOT space
+ */
+
+#ifdef CONFIG_SGI_IP27
+#define RBOOT_SIZE              0x10000000      /* 256 Megabytes */
+#define NODE_RBOOT_BASE(_n)     (NODE_HSPEC_BASE(_n) + 0x30000000)
+#define NODE_RBOOT_LIMIT(_n)    (NODE_RBOOT_BASE(_n) + RBOOT_SIZE)
+
+#endif
+
+/*
+ * Macros for referring the Hub's back door space
+ *
+ *   These macros correctly process addresses in any node's space.
+ *   WARNING: They won't work in assembler.
+ *
+ *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir
+ *                  entry corresponding to a physical (Cac or Uncac) address.
+ *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
+ *   BDPRT_ENTRY    returns the address of the double-word protection entry
+ *                  corresponding to the page containing the physical address.
+ *   BDPRT_ENTRY_S  Stores the value into the protection entry.
+ *   BDPRT_ENTRY_L  Load the value from the protection entry.
+ *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a
+ *                  double-word at a specified physical address.
+ *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a
+ *                  quad-word at a specified physical address.
+ */
+#define NODE_BDOOR_BASE(_n)     (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
+
+#define NODE_BDECC_BASE(_n)     (NODE_BDOOR_BASE(_n))
+#define NODE_BDDIR_BASE(_n)     (NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
+#ifdef CONFIG_SGI_IP27
+#define BDDIR_ENTRY_LO(_pa)     ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE * 3 / 4 +               \
+                                  0x200)                                    | \
+                                 UINT64_CAST(_pa)        & NASID_MASK       | \
+                                 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK  | \
+                                 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
+
+#define BDDIR_ENTRY_HI(_pa)     ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE * 3 / 4 +               \
+                                  0x208)                                    | \
+                                 UINT64_CAST(_pa)        & NASID_MASK       | \
+                                 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK  | \
+                                 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
+
+#define BDPRT_ENTRY(_pa, _rgn)  ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE * 3 / 4)              | \
+                                 UINT64_CAST(_pa)        & NASID_MASK       | \
+                                 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK  | \
+                                 (_rgn) << 3)
+#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn)))
+#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val))
+#define BDPRT_ENTRY_L(_pa, _rgn)        (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn)))
+
+#define BDECC_ENTRY(_pa)        ((HSPEC_BASE +                                \
+                                  NODE_ADDRSPACE_SIZE / 2)                  | \
+                                 UINT64_CAST(_pa)        & NASID_MASK       | \
+                                 UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK  | \
+                                 UINT64_CAST(_pa) >> 3 & 3)
+
+/*
+ * Macro to convert a back door directory or protection address into the
+ *   raw physical address of the associated cache line or protection page.
+ */
+#define BDADDR_IS_DIR(_ba)      ((UINT64_CAST  (_ba) & 0x200) != 0)
+#define BDADDR_IS_PRT(_ba)      ((UINT64_CAST  (_ba) & 0x200) == 0)
+
+#define BDDIR_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK            | \
+                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2  | \
+                                 (UINT64_CAST(_ba) & 0x1f << 4) << 3)
+
+#define BDPRT_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK     | \
+                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
+
+#define BDECC_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK     | \
+                                 (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2  | \
+                                 (UINT64_CAST(_ba) & 3) << 3)
+#endif /* CONFIG_SGI_IP27 */
+
+
+/*
+ * The following macros produce the correct base virtual address for
+ * the hub registers.  The LOCAL_HUB_* macros produce the appropriate
+ * address for the local registers.  The REMOTE_HUB_* macro produce
+ * the address for the specified hub's registers.  The intent is
+ * that the appropriate PI, MD, NI, or II register would be substituted
+ * for _x.
+ */
+
+/*
+ * WARNING:
+ *      When certain Hub chip workaround are defined, it's not sufficient
+ *      to dereference the *_HUB_ADDR() macros.  You should instead use
+ *      HUB_L() and HUB_S() if you must deal with pointers to hub registers.
+ *      Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
+ *      They're always safe.
+ */
+#define LOCAL_HUB_ADDR(_x)      (HUBREG_CAST (IALIAS_BASE + (_x)))
+#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
+                                              0x800000 + (_x)))
+#ifdef CONFIG_SGI_IP27
+#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
+                                              0x800000 + (_x)))
+#endif /* CONFIG_SGI_IP27 */
+
+#ifndef __ASSEMBLY__
+
+#define HUB_L(_a)                       *(_a)
+#define HUB_S(_a, _d)                   *(_a) = (_d)
+
+#define LOCAL_HUB_L(_r)                 HUB_L(LOCAL_HUB_ADDR(_r))
+#define LOCAL_HUB_S(_r, _d)             HUB_S(LOCAL_HUB_ADDR(_r), (_d))
+#define REMOTE_HUB_L(_n, _r)            HUB_L(REMOTE_HUB_ADDR((_n), (_r)))
+#define REMOTE_HUB_S(_n, _r, _d)        HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d))
+#define REMOTE_HUB_PI_L(_n, _sn, _r)    HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
+#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * The following macros are used to get to a hub/bridge register, given
+ * the base of the register space.
+ */
+#define HUB_REG_PTR(_base, _off)        \
+        (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
+
+#define HUB_REG_PTR_L(_base, _off)      \
+        HUB_L(HUB_REG_PTR((_base), (_off)))
+
+#define HUB_REG_PTR_S(_base, _off, _data)       \
+        HUB_S(HUB_REG_PTR((_base), (_off)), (_data))
+
+/*
+ * Software structure locations -- permanently fixed
+ *    See diagram in kldir.h
+ */
+
+#define PHYS_RAMBASE            0x0
+#define K0_RAMBASE              PHYS_TO_K0(PHYS_RAMBASE)
+
+#define EX_HANDLER_OFFSET(slice) ((slice) << 16)
+#define EX_HANDLER_ADDR(nasid, slice)                                   \
+        PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
+#define EX_HANDLER_SIZE         0x0400
+
+#define EX_FRAME_OFFSET(slice)  ((slice) << 16 | 0x400)
+#define EX_FRAME_ADDR(nasid, slice)                                     \
+        PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
+#define EX_FRAME_SIZE           0x0c00
+
+#define ARCS_SPB_OFFSET         0x1000
+#define ARCS_SPB_ADDR(nasid)                                            \
+        PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
+#define ARCS_SPB_SIZE           0x0400
+
+#define KLDIR_OFFSET            0x2000
+#define KLDIR_ADDR(nasid)                                               \
+        TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
+#define KLDIR_SIZE              0x0400
+
+
+/*
+ * Software structure locations -- indirected through KLDIR
+ *    See diagram in kldir.h
+ *
+ * Important:   All low memory structures must only be accessed
+ *              uncached, except for the symmon stacks.
+ */
+
+#define KLI_LAUNCH              0               /* Dir. entries */
+#define KLI_KLCONFIG            1
+#define KLI_NMI                 2
+#define KLI_GDA                 3
+#define KLI_FREEMEM             4
+#define KLI_SYMMON_STK          5
+#define KLI_PI_ERROR            6
+#define KLI_KERN_VARS           7
+#define KLI_KERN_XP             8
+#define KLI_KERN_PARTID         9
+
+#ifndef __ASSEMBLY__
+
+#define KLD_BASE(nasid)         ((kldir_ent_t *) KLDIR_ADDR(nasid))
+#define KLD_LAUNCH(nasid)       (KLD_BASE(nasid) + KLI_LAUNCH)
+#define KLD_NMI(nasid)          (KLD_BASE(nasid) + KLI_NMI)
+#define KLD_KLCONFIG(nasid)     (KLD_BASE(nasid) + KLI_KLCONFIG)
+#define KLD_PI_ERROR(nasid)     (KLD_BASE(nasid) + KLI_PI_ERROR)
+#define KLD_GDA(nasid)          (KLD_BASE(nasid) + KLI_GDA)
+#define KLD_SYMMON_STK(nasid)   (KLD_BASE(nasid) + KLI_SYMMON_STK)
+#define KLD_FREEMEM(nasid)      (KLD_BASE(nasid) + KLI_FREEMEM)
+#define KLD_KERN_VARS(nasid)    (KLD_BASE(nasid) + KLI_KERN_VARS)
+#define KLD_KERN_XP(nasid)      (KLD_BASE(nasid) + KLI_KERN_XP)
+#define KLD_KERN_PARTID(nasid)  (KLD_BASE(nasid) + KLI_KERN_PARTID)
+
+#define LAUNCH_OFFSET(nasid, slice)                                     \
+        (KLD_LAUNCH(nasid)->offset +                                    \
+         KLD_LAUNCH(nasid)->stride * (slice))
+#define LAUNCH_ADDR(nasid, slice)                                       \
+        TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
+#define LAUNCH_SIZE(nasid)      KLD_LAUNCH(nasid)->size
+
+#define NMI_OFFSET(nasid, slice)                                        \
+        (KLD_NMI(nasid)->offset +                                       \
+         KLD_NMI(nasid)->stride * (slice))
+#define NMI_ADDR(nasid, slice)                                          \
+        TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice))
+#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
+
+#define KLCONFIG_OFFSET(nasid)  KLD_KLCONFIG(nasid)->offset
+#define KLCONFIG_ADDR(nasid)                                            \
+        TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
+#define KLCONFIG_SIZE(nasid)    KLD_KLCONFIG(nasid)->size
+
+#define GDA_ADDR(nasid)         KLD_GDA(nasid)->pointer
+#define GDA_SIZE(nasid)         KLD_GDA(nasid)->size
+
+#define SYMMON_STK_OFFSET(nasid, slice)                                 \
+        (KLD_SYMMON_STK(nasid)->offset +                                \
+         KLD_SYMMON_STK(nasid)->stride * (slice))
+#define SYMMON_STK_STRIDE(nasid)        KLD_SYMMON_STK(nasid)->stride
+
+#define SYMMON_STK_ADDR(nasid, slice)                                   \
+        TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
+
+#define SYMMON_STK_SIZE(nasid)  KLD_SYMMON_STK(nasid)->stride
+
+#define SYMMON_STK_END(nasid)   (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
+
+/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
+ * relocatable program
+ */
+#define UNIX_DEBUG_LOADADDR     0x300000
+#define SYMMON_LOADADDR(nasid)                                          \
+        TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
+
+#define FREEMEM_OFFSET(nasid)   KLD_FREEMEM(nasid)->offset
+#define FREEMEM_ADDR(nasid)     SYMMON_STK_END(nasid)
+/*
+ * XXX
+ * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
+ * Also, it should take into account what prom thinks to be a safe
+ * address
+        PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
+ */
+#define FREEMEM_SIZE(nasid)     KLD_FREEMEM(nasid)->size
+
+#define PI_ERROR_OFFSET(nasid)  KLD_PI_ERROR(nasid)->offset
+#define PI_ERROR_ADDR(nasid)                                            \
+        TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
+#define PI_ERROR_SIZE(nasid)    KLD_PI_ERROR(nasid)->size
+
+#define NODE_OFFSET_TO_K0(_nasid, _off)                                 \
+        PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE)
+#define NODE_OFFSET_TO_K1(_nasid, _off)                                 \
+        TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE)
+#define K0_TO_NODE_OFFSET(_k0addr)                                      \
+        ((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
+
+#define KERN_VARS_ADDR(nasid)   KLD_KERN_VARS(nasid)->pointer
+#define KERN_VARS_SIZE(nasid)   KLD_KERN_VARS(nasid)->size
+
+#define KERN_XP_ADDR(nasid)     KLD_KERN_XP(nasid)->pointer
+#define KERN_XP_SIZE(nasid)     KLD_KERN_XP(nasid)->size
+
+#define GPDA_ADDR(nasid)        TO_NODE_CAC(nasid, GPDA_OFFSET)
+
+#endif /* !__ASSEMBLY__ */
+
+
+#endif /* _ASM_SN_ADDRS_H */
diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h
new file mode 100644
index 000000000000..ac4ea85c3a5c
--- /dev/null
+++ b/arch/mips/include/asm/sn/agent.h
@@ -0,0 +1,46 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * This file has definitions for the hub and snac interfaces.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silcon Graphics, Inc.
+ * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SGI_SN_AGENT_H
+#define _ASM_SGI_SN_AGENT_H
+
+#include <linux/topology.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+
+#if defined(CONFIG_SGI_IP27)
+#include <asm/sn/sn0/hub.h>
+#elif defined(CONFIG_SGI_IP35)
+#include <asm/sn/sn1/hub.h>
+#endif  /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
+
+/*
+ * NIC register macros
+ */
+
+#if defined(CONFIG_SGI_IP27)
+#define HUB_NIC_ADDR(_cpuid)                                               \
+        REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)),       \
+                MD_MLAN_CTL)
+#endif
+
+#define SET_HUB_NIC(_my_cpuid, _val)                                       \
+        (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
+
+#define SET_MY_HUB_NIC(_v)                                                 \
+        SET_HUB_NIC(cpuid(), (_v))
+
+#define GET_HUB_NIC(_my_cpuid)                                             \
+        (HUB_L(HUB_NIC_ADDR(_my_cpuid)))
+
+#define GET_MY_HUB_NIC()                                                   \
+        GET_HUB_NIC(cpuid())
+
+#endif /* _ASM_SGI_SN_AGENT_H */
diff --git a/arch/mips/include/asm/sn/arch.h b/arch/mips/include/asm/sn/arch.h
new file mode 100644
index 000000000000..bd75945e10ff
--- /dev/null
+++ b/arch/mips/include/asm/sn/arch.h
@@ -0,0 +1,64 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI specific setup.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_ARCH_H
+#define _ASM_SN_ARCH_H
+
+#include <linux/types.h>
+#include <asm/sn/types.h>
+#ifdef CONFIG_SGI_IP27
+#include <asm/sn/sn0/arch.h>
+#endif
+
+typedef u64     hubreg_t;
+
+#define cputonasid(cpu)         (sn_cpu_info[(cpu)].p_nasid)
+#define cputoslice(cpu)         (sn_cpu_info[(cpu)].p_slice)
+#define makespnum(_nasid, _slice)                                       \
+                (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
+
+#define INVALID_NASID           (nasid_t)-1
+#define INVALID_CNODEID         (cnodeid_t)-1
+#define INVALID_PNODEID         (pnodeid_t)-1
+#define INVALID_MODULE          (moduleid_t)-1
+#define INVALID_PARTID          (partid_t)-1
+
+extern nasid_t get_nasid(void);
+extern cnodeid_t get_cpu_cnode(cpuid_t);
+extern int get_cpu_slice(cpuid_t);
+
+/*
+ * NO ONE should access these arrays directly.  The only reason we refer to
+ * them here is to avoid the procedure call that would be required in the
+ * macros below.  (Really want private data members here :-)
+ */
+extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
+extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
+
+/*
+ * These macros are used by various parts of the kernel to convert
+ * between the three different kinds of node numbering.   At least some
+ * of them may change to procedure calls in the future, but the macros
+ * will continue to work.  Don't use the arrays above directly.
+ */
+
+#define NASID_TO_REGION(nnode)          \
+    ((nnode) >> \
+     (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
+
+extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
+extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
+extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
+
+#define NASID_TO_COMPACT_NODEID(nnode)  (nasid_to_compact_node[nnode])
+#define COMPACT_TO_NASID_NODEID(cnode)  (compact_to_nasid_node[cnode])
+#define CPUID_TO_COMPACT_NODEID(cpu)    (cpuid_to_compact_node[(cpu)])
+
+#endif /* _ASM_SN_ARCH_H */
diff --git a/arch/mips/include/asm/sn/fru.h b/arch/mips/include/asm/sn/fru.h
new file mode 100644
index 000000000000..b3e3606723b7
--- /dev/null
+++ b/arch/mips/include/asm/sn/fru.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
+ */
+#ifndef __ASM_SN_FRU_H
+#define __ASM_SN_FRU_H
+
+#define MAX_DIMMS                       8        /* max # of dimm banks */
+#define MAX_PCIDEV                      8        /* max # of pci devices on a pci bus */
+
+typedef unsigned char confidence_t;
+
+typedef struct kf_mem_s {
+        confidence_t km_confidence; /* confidence level that the memory is bad
+                                     * is this necessary ?
+                                     */
+        confidence_t km_dimm[MAX_DIMMS];
+                                    /* confidence level that dimm[i] is bad
+                                     *I think this is the right number
+                                     */
+
+} kf_mem_t;
+
+typedef struct kf_cpu_s {
+        confidence_t    kc_confidence; /* confidence level that cpu is bad */
+        confidence_t    kc_icache; /* confidence level that instr. cache is bad */
+        confidence_t    kc_dcache; /* confidence level that data   cache is bad */
+        confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
+        confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
+} kf_cpu_t;
+
+typedef struct kf_pci_bus_s {
+        confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
+        confidence_t    kpb_pcidev_belief[MAX_PCIDEV];
+                                        /* confidence level that the pci dev is bad */
+} kf_pci_bus_t;
+
+#endif /* __ASM_SN_FRU_H */
diff --git a/arch/mips/include/asm/sn/gda.h b/arch/mips/include/asm/sn/gda.h
new file mode 100644
index 000000000000..9cb6ff770915
--- /dev/null
+++ b/arch/mips/include/asm/sn/gda.h
@@ -0,0 +1,107 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/gda.h>.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ *
+ * gda.h -- Contains the data structure for the global data area,
+ *      The GDA contains information communicated between the
+ *      PROM, SYMMON, and the kernel.
+ */
+#ifndef _ASM_SN_GDA_H
+#define _ASM_SN_GDA_H
+
+#include <asm/sn/addrs.h>
+
+#define GDA_MAGIC       0x58464552
+
+/*
+ * GDA Version History
+ *
+ * Version #    | Change
+ * -------------+-------------------------------------------------------
+ *      1       | Initial SN0 version
+ *      2       | Prom sets g_partid field to the partition number. 0 IS
+ *              | a valid partition #.
+ */
+
+#define GDA_VERSION     2       /* Current GDA version # */
+
+#define G_MAGICOFF      0
+#define G_VERSIONOFF    4
+#define G_PROMOPOFF     6
+#define G_MASTEROFF     8
+#define G_VDSOFF        12
+#define G_HKDNORMOFF    16
+#define G_HKDUTLBOFF    24
+#define G_HKDXUTLBOFF   32
+#define G_PARTIDOFF     40
+#define G_TABLEOFF      128
+
+#ifndef __ASSEMBLY__
+
+typedef struct gda {
+        u32     g_magic;        /* GDA magic number */
+        u16     g_version;      /* Version of this structure */
+        u16     g_masterid;     /* The NASID:CPUNUM of the master cpu */
+        u32     g_promop;       /* Passes requests from the kernel to prom */
+        u32     g_vds;          /* Store the virtual dipswitches here */
+        void    **g_hooked_norm;/* ptr to pda loc for norm hndlr */
+        void    **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */
+        void    **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */
+        int     g_partid;       /* partition id */
+        int     g_symmax;       /* Max symbols in name table. */
+        void    *g_dbstab;      /* Address of idbg symbol table */
+        char    *g_nametab;     /* Address of idbg name table */
+        void    *g_ktext_repmask;
+                                /* Pointer to a mask of nodes with copies
+                                 * of the kernel. */
+        char    g_padding[56];  /* pad out to 128 bytes */
+        nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
+                                                  * indexed by cnodeid.
+                                                  */
+} gda_t;
+
+#define GDA ((gda_t*) GDA_ADDR(get_nasid()))
+
+#endif /* !__ASSEMBLY__ */
+/*
+ * Define:      PART_GDA_VERSION
+ * Purpose:     Define the minimum version of the GDA required, lower
+ *              revisions assume GDA is NOT set up, and read partition
+ *              information from the board info.
+ */
+#define PART_GDA_VERSION        2
+
+/*
+ * The following requests can be sent to the PROM during startup.
+ */
+
+#define PROMOP_MAGIC            0x0ead0000
+#define PROMOP_MAGIC_MASK       0x0fff0000
+
+#define PROMOP_BIST_SHIFT       11
+#define PROMOP_BIST_MASK        (0x3 << 11)
+
+#define PROMOP_REG              PI_ERR_STACK_ADDR_A
+
+#define PROMOP_INVALID          (PROMOP_MAGIC | 0x00)
+#define PROMOP_HALT             (PROMOP_MAGIC | 0x10)
+#define PROMOP_POWERDOWN        (PROMOP_MAGIC | 0x20)
+#define PROMOP_RESTART          (PROMOP_MAGIC | 0x30)
+#define PROMOP_REBOOT           (PROMOP_MAGIC | 0x40)
+#define PROMOP_IMODE            (PROMOP_MAGIC | 0x50)
+
+#define PROMOP_CMD_MASK         0x00f0
+#define PROMOP_OPTIONS_MASK     0xfff0
+
+#define PROMOP_SKIP_DIAGS       0x0100          /* don't bother running diags */
+#define PROMOP_SKIP_MEMINIT     0x0200          /* don't bother initing memory */
+#define PROMOP_SKIP_DEVINIT     0x0400          /* don't bother initing devices */
+#define PROMOP_BIST1            0x0800          /* keep track of which BIST ran */
+#define PROMOP_BIST2            0x1000          /* keep track of which BIST ran */
+
+#endif /* _ASM_SN_GDA_H */
diff --git a/arch/mips/include/asm/sn/hub.h b/arch/mips/include/asm/sn/hub.h
new file mode 100644
index 000000000000..1992d9254a08
--- /dev/null
+++ b/arch/mips/include/asm/sn/hub.h
@@ -0,0 +1,16 @@
+#ifndef __ASM_SN_HUB_H
+#define __ASM_SN_HUB_H
+
+#include <linux/types.h>
+#include <linux/cpumask.h>
+#include <asm/sn/types.h>
+#include <asm/sn/io.h>
+#include <asm/sn/klkernvars.h>
+#include <asm/xtalk/xtalk.h>
+
+/* ip27-hubio.c */
+extern unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
+                          unsigned long xtalk_addr, size_t size);
+extern void hub_pio_init(cnodeid_t cnode);
+
+#endif /* __ASM_SN_HUB_H */
diff --git a/arch/mips/include/asm/sn/intr.h b/arch/mips/include/asm/sn/intr.h
new file mode 100644
index 000000000000..6718b644b970
--- /dev/null
+++ b/arch/mips/include/asm/sn/intr.h
@@ -0,0 +1,129 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_INTR_H
+#define __ASM_SN_INTR_H
+
+/* Number of interrupt levels associated with each interrupt register. */
+#define N_INTPEND_BITS          64
+
+#define INT_PEND0_BASELVL       0
+#define INT_PEND1_BASELVL       64
+
+#define N_INTPENDJUNK_BITS      8
+#define INTPENDJUNK_CLRBIT      0x80
+
+/*
+ * Macros to manipulate the interrupt register on the calling hub chip.
+ */
+
+#define LOCAL_HUB_SEND_INTR(level)                              \
+        LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
+#define REMOTE_HUB_SEND_INTR(hub, level)                        \
+        REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
+
+/*
+ * When clearing the interrupt, make sure this clear does make it
+ * to the hub. Otherwise we could end up losing interrupts.
+ * We do an uncached load of the int_pend0 register to ensure this.
+ */
+
+#define LOCAL_HUB_CLR_INTR(level)                               \
+do {                                                            \
+        LOCAL_HUB_S(PI_INT_PEND_MOD, (level));                  \
+        LOCAL_HUB_L(PI_INT_PEND0);                              \
+} while (0);
+
+#define REMOTE_HUB_CLR_INTR(hub, level)                         \
+do {                                                            \
+        nasid_t  __hub = (hub);                                 \
+                                                                \
+        REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));          \
+        REMOTE_HUB_L(__hub, PI_INT_PEND0);                      \
+} while (0);
+
+/*
+ * Hard-coded interrupt levels:
+ */
+
+/*
+ *      L0 = SW1
+ *      L1 = SW2
+ *      L2 = INT_PEND0
+ *      L3 = INT_PEND1
+ *      L4 = RTC
+ *      L5 = Profiling Timer
+ *      L6 = Hub Errors
+ *      L7 = Count/Compare (T5 counters)
+ */
+
+
+/*
+ * INT_PEND0 hard-coded bits.
+ */
+
+/*
+ * INT_PEND0 bits determined by hardware:
+ */
+#define RESERVED_INTR            0      /* What is this bit? */
+#define GFX_INTR_A               1
+#define GFX_INTR_B               2
+#define PG_MIG_INTR              3
+#define UART_INTR                4
+#define CC_PEND_A                5
+#define CC_PEND_B                6
+
+/*
+ * INT_PEND0 used by the kernel for itself ...
+ */
+#define CPU_RESCHED_A_IRQ        7
+#define CPU_RESCHED_B_IRQ        8
+#define CPU_CALL_A_IRQ           9
+#define CPU_CALL_B_IRQ          10
+#define MSC_MESG_INTR           11
+#define BASE_PCI_IRQ            12
+
+/*
+ * INT_PEND0 again, bits determined by hardware / hardcoded:
+ */
+#define SDISK_INTR              63      /* SABLE name */
+#define IP_PEND0_6_63           63      /* What is this bit? */
+
+/*
+ * INT_PEND1 hard-coded bits:
+ */
+#define NI_BRDCAST_ERR_A        39
+#define NI_BRDCAST_ERR_B        40
+
+#define LLP_PFAIL_INTR_A        41      /* see ml/SN/SN0/sysctlr.c */
+#define LLP_PFAIL_INTR_B        42
+
+#define TLB_INTR_A              43      /* used for tlb flush random */
+#define TLB_INTR_B              44
+
+#define IP27_INTR_0             45      /* Reserved for PROM use */
+#define IP27_INTR_1             46      /* do not use in Kernel */
+#define IP27_INTR_2             47
+#define IP27_INTR_3             48
+#define IP27_INTR_4             49
+#define IP27_INTR_5             50
+#define IP27_INTR_6             51
+#define IP27_INTR_7             52
+
+#define BRIDGE_ERROR_INTR       53      /* Setup by PROM to catch       */
+                                        /* Bridge Errors */
+#define DEBUG_INTR_A            54
+#define DEBUG_INTR_B            55      /* Used by symmon to stop all cpus */
+#define IO_ERROR_INTR           57      /* Setup by PROM */
+#define CLK_ERR_INTR            58
+#define COR_ERR_INTR_A          59
+#define COR_ERR_INTR_B          60
+#define MD_COR_ERR_INTR         61
+#define NI_ERROR_INTR           62
+#define MSC_PANIC_INTR          63
+
+#endif /* __ASM_SN_INTR_H */
diff --git a/arch/mips/include/asm/sn/io.h b/arch/mips/include/asm/sn/io.h
new file mode 100644
index 000000000000..24c6775fbb0f
--- /dev/null
+++ b/arch/mips/include/asm/sn/io.h
@@ -0,0 +1,59 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000, 2003 Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SN_IO_H
+#define _ASM_SN_IO_H
+
+#if defined(CONFIG_SGI_IP27)
+#include <asm/sn/sn0/hubio.h>
+#endif
+
+
+#define IIO_ITTE_BASE           0x400160 /* base of translation table entries */
+#define IIO_ITTE(bigwin)        (IIO_ITTE_BASE + 8*(bigwin))
+
+#define IIO_ITTE_OFFSET_BITS    5       /* size of offset field */
+#define IIO_ITTE_OFFSET_MASK    ((1<<IIO_ITTE_OFFSET_BITS)-1)
+#define IIO_ITTE_OFFSET_SHIFT   0
+
+#define IIO_ITTE_WIDGET_BITS    4       /* size of widget field */
+#define IIO_ITTE_WIDGET_MASK    ((1<<IIO_ITTE_WIDGET_BITS)-1)
+#define IIO_ITTE_WIDGET_SHIFT   8
+
+#define IIO_ITTE_IOSP           1       /* I/O Space bit */
+#define IIO_ITTE_IOSP_MASK      1
+#define IIO_ITTE_IOSP_SHIFT     12
+#define HUB_PIO_MAP_TO_MEM      0
+#define HUB_PIO_MAP_TO_IO       1
+
+#define IIO_ITTE_INVALID_WIDGET 3       /* an invalid widget  */
+
+#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
+        REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
+                (((((addr) >> BWIN_SIZE_BITS) & \
+                   IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \
+                (io_or_mem << IIO_ITTE_IOSP_SHIFT) | \
+                (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
+
+#define IIO_ITTE_DISABLE(nasid, bigwin) \
+        IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \
+                     (bigwin), IIO_ITTE_INVALID_WIDGET, 0)
+
+#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
+
+/*
+ * Macro which takes the widget number, and returns the
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range
+ * 0, 8 - 0xF
+ */
+#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+                        (_x) : \
+                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
+
+#endif /* _ASM_SN_IO_H */
diff --git a/arch/mips/include/asm/sn/ioc3.h b/arch/mips/include/asm/sn/ioc3.h
new file mode 100644
index 000000000000..099677774d71
--- /dev/null
+++ b/arch/mips/include/asm/sn/ioc3.h
@@ -0,0 +1,663 @@
+/*
+ * Copyright (C) 1999, 2000 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _IOC3_H
+#define _IOC3_H
+
+#include <linux/types.h>
+
+/* SUPERIO uart register map */
+typedef volatile struct ioc3_uartregs {
+        union {
+                volatile u8     rbr;    /* read only, DLAB == 0 */
+                volatile u8     thr;    /* write only, DLAB == 0 */
+                volatile u8     dll;    /* DLAB == 1 */
+        } u1;
+        union {
+                volatile u8     ier;    /* DLAB == 0 */
+                volatile u8     dlm;    /* DLAB == 1 */
+        } u2;
+        union {
+                volatile u8     iir;    /* read only */
+                volatile u8     fcr;    /* write only */
+        } u3;
+        volatile u8         iu_lcr;
+        volatile u8         iu_mcr;
+        volatile u8         iu_lsr;
+        volatile u8         iu_msr;
+        volatile u8         iu_scr;
+} ioc3_uregs_t;
+
+#define iu_rbr u1.rbr
+#define iu_thr u1.thr
+#define iu_dll u1.dll
+#define iu_ier u2.ier
+#define iu_dlm u2.dlm
+#define iu_iir u3.iir
+#define iu_fcr u3.fcr
+
+struct ioc3_sioregs {
+        volatile u8             fill[0x141];    /* starts at 0x141 */
+
+        volatile u8             uartc;
+        volatile u8             kbdcg;
+
+        volatile u8             fill0[0x150 - 0x142 - 1];
+
+        volatile u8             pp_data;
+        volatile u8             pp_dsr;
+        volatile u8             pp_dcr;
+
+        volatile u8             fill1[0x158 - 0x152 - 1];
+
+        volatile u8             pp_fifa;
+        volatile u8             pp_cfgb;
+        volatile u8             pp_ecr;
+
+        volatile u8             fill2[0x168 - 0x15a - 1];
+
+        volatile u8             rtcad;
+        volatile u8             rtcdat;
+
+        volatile u8             fill3[0x170 - 0x169 - 1];
+
+        struct ioc3_uartregs    uartb;  /* 0x20170  */
+        struct ioc3_uartregs    uarta;  /* 0x20178  */
+};
+
+/* Register layout of IOC3 in configuration space.  */
+struct ioc3 {
+        volatile u32    pad0[7];        /* 0x00000  */
+        volatile u32    sio_ir;         /* 0x0001c  */
+        volatile u32    sio_ies;        /* 0x00020  */
+        volatile u32    sio_iec;        /* 0x00024  */
+        volatile u32    sio_cr;         /* 0x00028  */
+        volatile u32    int_out;        /* 0x0002c  */
+        volatile u32    mcr;            /* 0x00030  */
+
+        /* General Purpose I/O registers  */
+        volatile u32    gpcr_s;         /* 0x00034  */
+        volatile u32    gpcr_c;         /* 0x00038  */
+        volatile u32    gpdr;           /* 0x0003c  */
+        volatile u32    gppr_0;         /* 0x00040  */
+        volatile u32    gppr_1;         /* 0x00044  */
+        volatile u32    gppr_2;         /* 0x00048  */
+        volatile u32    gppr_3;         /* 0x0004c  */
+        volatile u32    gppr_4;         /* 0x00050  */
+        volatile u32    gppr_5;         /* 0x00054  */
+        volatile u32    gppr_6;         /* 0x00058  */
+        volatile u32    gppr_7;         /* 0x0005c  */
+        volatile u32    gppr_8;         /* 0x00060  */
+        volatile u32    gppr_9;         /* 0x00064  */
+        volatile u32    gppr_10;        /* 0x00068  */
+        volatile u32    gppr_11;        /* 0x0006c  */
+        volatile u32    gppr_12;        /* 0x00070  */
+        volatile u32    gppr_13;        /* 0x00074  */
+        volatile u32    gppr_14;        /* 0x00078  */
+        volatile u32    gppr_15;        /* 0x0007c  */
+
+        /* Parallel Port Registers  */
+        volatile u32    ppbr_h_a;       /* 0x00080  */
+        volatile u32    ppbr_l_a;       /* 0x00084  */
+        volatile u32    ppcr_a;         /* 0x00088  */
+        volatile u32    ppcr;           /* 0x0008c  */
+        volatile u32    ppbr_h_b;       /* 0x00090  */
+        volatile u32    ppbr_l_b;       /* 0x00094  */
+        volatile u32    ppcr_b;         /* 0x00098  */
+
+        /* Keyboard and Mouse Registers  */
+        volatile u32    km_csr;         /* 0x0009c  */
+        volatile u32    k_rd;           /* 0x000a0  */
+        volatile u32    m_rd;           /* 0x000a4  */
+        volatile u32    k_wd;           /* 0x000a8  */
+        volatile u32    m_wd;           /* 0x000ac  */
+
+        /* Serial Port Registers  */
+        volatile u32    sbbr_h;         /* 0x000b0  */
+        volatile u32    sbbr_l;         /* 0x000b4  */
+        volatile u32    sscr_a;         /* 0x000b8  */
+        volatile u32    stpir_a;        /* 0x000bc  */
+        volatile u32    stcir_a;        /* 0x000c0  */
+        volatile u32    srpir_a;        /* 0x000c4  */
+        volatile u32    srcir_a;        /* 0x000c8  */
+        volatile u32    srtr_a;         /* 0x000cc  */
+        volatile u32    shadow_a;       /* 0x000d0  */
+        volatile u32    sscr_b;         /* 0x000d4  */
+        volatile u32    stpir_b;        /* 0x000d8  */
+        volatile u32    stcir_b;        /* 0x000dc  */
+        volatile u32    srpir_b;        /* 0x000e0  */
+        volatile u32    srcir_b;        /* 0x000e4  */
+        volatile u32    srtr_b;         /* 0x000e8  */
+        volatile u32    shadow_b;       /* 0x000ec  */
+
+        /* Ethernet Registers  */
+        volatile u32    emcr;           /* 0x000f0  */
+        volatile u32    eisr;           /* 0x000f4  */
+        volatile u32    eier;           /* 0x000f8  */
+        volatile u32    ercsr;          /* 0x000fc  */
+        volatile u32    erbr_h;         /* 0x00100  */
+        volatile u32    erbr_l;         /* 0x00104  */
+        volatile u32    erbar;          /* 0x00108  */
+        volatile u32    ercir;          /* 0x0010c  */
+        volatile u32    erpir;          /* 0x00110  */
+        volatile u32    ertr;           /* 0x00114  */
+        volatile u32    etcsr;          /* 0x00118  */
+        volatile u32    ersr;           /* 0x0011c  */
+        volatile u32    etcdc;          /* 0x00120  */
+        volatile u32    ebir;           /* 0x00124  */
+        volatile u32    etbr_h;         /* 0x00128  */
+        volatile u32    etbr_l;         /* 0x0012c  */
+        volatile u32    etcir;          /* 0x00130  */
+        volatile u32    etpir;          /* 0x00134  */
+        volatile u32    emar_h;         /* 0x00138  */
+        volatile u32    emar_l;         /* 0x0013c  */
+        volatile u32    ehar_h;         /* 0x00140  */
+        volatile u32    ehar_l;         /* 0x00144  */
+        volatile u32    micr;           /* 0x00148  */
+        volatile u32    midr_r;         /* 0x0014c  */
+        volatile u32    midr_w;         /* 0x00150  */
+        volatile u32    pad1[(0x20000 - 0x00154) / 4];
+
+        /* SuperIO Registers  XXX */
+        struct ioc3_sioregs     sregs;  /* 0x20000 */
+        volatile u32    pad2[(0x40000 - 0x20180) / 4];
+
+        /* SSRAM Diagnostic Access */
+        volatile u32    ssram[(0x80000 - 0x40000) / 4];
+
+        /* Bytebus device offsets
+           0x80000 -   Access to the generic devices selected with   DEV0
+           0x9FFFF     bytebus DEV_SEL_0
+           0xA0000 -   Access to the generic devices selected with   DEV1
+           0xBFFFF     bytebus DEV_SEL_1
+           0xC0000 -   Access to the generic devices selected with   DEV2
+           0xDFFFF     bytebus DEV_SEL_2
+           0xE0000 -   Access to the generic devices selected with   DEV3
+           0xFFFFF     bytebus DEV_SEL_3  */
+};
+
+/*
+ * Ethernet RX Buffer
+ */
+struct ioc3_erxbuf {
+        u32     w0;                     /* first word (valid,bcnt,cksum) */
+        u32     err;                    /* second word various errors */
+        /* next comes n bytes of padding */
+        /* then the received ethernet frame itself */
+};
+
+#define ERXBUF_IPCKSUM_MASK     0x0000ffff
+#define ERXBUF_BYTECNT_MASK     0x07ff0000
+#define ERXBUF_BYTECNT_SHIFT    16
+#define ERXBUF_V                0x80000000
+
+#define ERXBUF_CRCERR           0x00000001      /* aka RSV15 */
+#define ERXBUF_FRAMERR          0x00000002      /* aka RSV14 */
+#define ERXBUF_CODERR           0x00000004      /* aka RSV13 */
+#define ERXBUF_INVPREAMB        0x00000008      /* aka RSV18 */
+#define ERXBUF_LOLEN            0x00007000      /* aka RSV2_0 */
+#define ERXBUF_HILEN            0x03ff0000      /* aka RSV12_3 */
+#define ERXBUF_MULTICAST        0x04000000      /* aka RSV16 */
+#define ERXBUF_BROADCAST        0x08000000      /* aka RSV17 */
+#define ERXBUF_LONGEVENT        0x10000000      /* aka RSV19 */
+#define ERXBUF_BADPKT           0x20000000      /* aka RSV20 */
+#define ERXBUF_GOODPKT          0x40000000      /* aka RSV21 */
+#define ERXBUF_CARRIER          0x80000000      /* aka RSV22 */
+
+/*
+ * Ethernet TX Descriptor
+ */
+#define ETXD_DATALEN    104
+struct ioc3_etxd {
+        u32     cmd;                            /* command field */
+        u32     bufcnt;                         /* buffer counts field */
+        u64     p1;                             /* buffer pointer 1 */
+        u64     p2;                             /* buffer pointer 2 */
+        u8      data[ETXD_DATALEN];             /* opt. tx data */
+};
+
+#define ETXD_BYTECNT_MASK       0x000007ff      /* total byte count */
+#define ETXD_INTWHENDONE        0x00001000      /* intr when done */
+#define ETXD_D0V                0x00010000      /* data 0 valid */
+#define ETXD_B1V                0x00020000      /* buf 1 valid */
+#define ETXD_B2V                0x00040000      /* buf 2 valid */
+#define ETXD_DOCHECKSUM         0x00080000      /* insert ip cksum */
+#define ETXD_CHKOFF_MASK        0x07f00000      /* cksum byte offset */
+#define ETXD_CHKOFF_SHIFT       20
+
+#define ETXD_D0CNT_MASK         0x0000007f
+#define ETXD_B1CNT_MASK         0x0007ff00
+#define ETXD_B1CNT_SHIFT        8
+#define ETXD_B2CNT_MASK         0x7ff00000
+#define ETXD_B2CNT_SHIFT        20
+
+/*
+ * Bytebus device space
+ */
+#define IOC3_BYTEBUS_DEV0       0x80000L
+#define IOC3_BYTEBUS_DEV1       0xa0000L
+#define IOC3_BYTEBUS_DEV2       0xc0000L
+#define IOC3_BYTEBUS_DEV3       0xe0000L
+
+/* ------------------------------------------------------------------------- */
+
+/* Superio Registers (PIO Access) */
+#define IOC3_SIO_BASE           0x20000
+#define IOC3_SIO_UARTC          (IOC3_SIO_BASE+0x141)   /* UART Config */
+#define IOC3_SIO_KBDCG          (IOC3_SIO_BASE+0x142)   /* KBD Config */
+#define IOC3_SIO_PP_BASE        (IOC3_SIO_BASE+PP_BASE)         /* Parallel Port */
+#define IOC3_SIO_RTC_BASE       (IOC3_SIO_BASE+0x168)   /* Real Time Clock */
+#define IOC3_SIO_UB_BASE        (IOC3_SIO_BASE+UARTB_BASE)      /* UART B */
+#define IOC3_SIO_UA_BASE        (IOC3_SIO_BASE+UARTA_BASE)      /* UART A */
+
+/* SSRAM Diagnostic Access */
+#define IOC3_SSRAM      IOC3_RAM_OFF    /* base of SSRAM diagnostic access */
+#define IOC3_SSRAM_LEN  0x40000 /* 256kb (address space size, may not be fully populated) */
+#define IOC3_SSRAM_DM   0x0000ffff      /* data mask */
+#define IOC3_SSRAM_PM   0x00010000      /* parity mask */
+
+/* bitmasks for PCI_SCR */
+#define PCI_SCR_PAR_RESP_EN     0x00000040      /* enb PCI parity checking */
+#define PCI_SCR_SERR_EN         0x00000100      /* enable the SERR# driver */
+#define PCI_SCR_DROP_MODE_EN    0x00008000      /* drop pios on parity err */
+#define PCI_SCR_RX_SERR         (0x1 << 16)
+#define PCI_SCR_DROP_MODE       (0x1 << 17)
+#define PCI_SCR_SIG_PAR_ERR     (0x1 << 24)
+#define PCI_SCR_SIG_TAR_ABRT    (0x1 << 27)
+#define PCI_SCR_RX_TAR_ABRT     (0x1 << 28)
+#define PCI_SCR_SIG_MST_ABRT    (0x1 << 29)
+#define PCI_SCR_SIG_SERR        (0x1 << 30)
+#define PCI_SCR_PAR_ERR         (0x1 << 31)
+
+/* bitmasks for IOC3_KM_CSR */
+#define KM_CSR_K_WRT_PEND 0x00000001    /* kbd port xmitting or resetting */
+#define KM_CSR_M_WRT_PEND 0x00000002    /* mouse port xmitting or resetting */
+#define KM_CSR_K_LCB      0x00000004    /* Line Cntrl Bit for last KBD write */
+#define KM_CSR_M_LCB      0x00000008    /* same for mouse */
+#define KM_CSR_K_DATA     0x00000010    /* state of kbd data line */
+#define KM_CSR_K_CLK      0x00000020    /* state of kbd clock line */
+#define KM_CSR_K_PULL_DATA 0x00000040   /* pull kbd data line low */
+#define KM_CSR_K_PULL_CLK 0x00000080    /* pull kbd clock line low */
+#define KM_CSR_M_DATA     0x00000100    /* state of ms data line */
+#define KM_CSR_M_CLK      0x00000200    /* state of ms clock line */
+#define KM_CSR_M_PULL_DATA 0x00000400   /* pull ms data line low */
+#define KM_CSR_M_PULL_CLK 0x00000800    /* pull ms clock line low */
+#define KM_CSR_EMM_MODE   0x00001000    /* emulation mode */
+#define KM_CSR_SIM_MODE   0x00002000    /* clock X8 */
+#define KM_CSR_K_SM_IDLE  0x00004000    /* Keyboard is idle */
+#define KM_CSR_M_SM_IDLE  0x00008000    /* Mouse is idle */
+#define KM_CSR_K_TO       0x00010000    /* Keyboard trying to send/receive */
+#define KM_CSR_M_TO       0x00020000    /* Mouse trying to send/receive */
+#define KM_CSR_K_TO_EN    0x00040000    /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
+                                           SIO_IR to assert */
+#define KM_CSR_M_TO_EN    0x00080000    /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
+                                           SIO_IR to assert */
+#define KM_CSR_K_CLAMP_ONE      0x00100000      /* Pull K_CLK low after rec. one char */
+#define KM_CSR_M_CLAMP_ONE      0x00200000      /* Pull M_CLK low after rec. one char */
+#define KM_CSR_K_CLAMP_THREE    0x00400000      /* Pull K_CLK low after rec. three chars */
+#define KM_CSR_M_CLAMP_THREE    0x00800000      /* Pull M_CLK low after rec. three char */
+
+/* bitmasks for IOC3_K_RD and IOC3_M_RD */
+#define KM_RD_DATA_2    0x000000ff      /* 3rd char recvd since last read */
+#define KM_RD_DATA_2_SHIFT 0
+#define KM_RD_DATA_1    0x0000ff00      /* 2nd char recvd since last read */
+#define KM_RD_DATA_1_SHIFT 8
+#define KM_RD_DATA_0    0x00ff0000      /* 1st char recvd since last read */
+#define KM_RD_DATA_0_SHIFT 16
+#define KM_RD_FRAME_ERR_2 0x01000000    /*  framing or parity error in byte 2 */
+#define KM_RD_FRAME_ERR_1 0x02000000    /* same for byte 1 */
+#define KM_RD_FRAME_ERR_0 0x04000000    /* same for byte 0 */
+
+#define KM_RD_KBD_MSE   0x08000000      /* 0 if from kbd, 1 if from mouse */
+#define KM_RD_OFLO      0x10000000      /* 4th char recvd before this read */
+#define KM_RD_VALID_2   0x20000000      /* DATA_2 valid */
+#define KM_RD_VALID_1   0x40000000      /* DATA_1 valid */
+#define KM_RD_VALID_0   0x80000000      /* DATA_0 valid */
+#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
+
+/* bitmasks for IOC3_K_WD & IOC3_M_WD */
+#define KM_WD_WRT_DATA  0x000000ff      /* write to keyboard/mouse port */
+#define KM_WD_WRT_DATA_SHIFT 0
+
+/* bitmasks for serial RX status byte */
+#define RXSB_OVERRUN    0x01    /* char(s) lost */
+#define RXSB_PAR_ERR    0x02    /* parity error */
+#define RXSB_FRAME_ERR  0x04    /* framing error */
+#define RXSB_BREAK      0x08    /* break character */
+#define RXSB_CTS        0x10    /* state of CTS */
+#define RXSB_DCD        0x20    /* state of DCD */
+#define RXSB_MODEM_VALID 0x40   /* DCD, CTS and OVERRUN are valid */
+#define RXSB_DATA_VALID 0x80    /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
+
+/* bitmasks for serial TX control byte */
+#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
+#define TXCB_INVALID    0x00    /* byte is invalid */
+#define TXCB_VALID      0x40    /* byte is valid */
+#define TXCB_MCR        0x80    /* data<7:0> to modem control register */
+#define TXCB_DELAY      0xc0    /* delay data<7:0> mSec */
+
+/* bitmasks for IOC3_SBBR_L */
+#define SBBR_L_SIZE     0x00000001      /* 0 == 1KB rings, 1 == 4KB rings */
+#define SBBR_L_BASE     0xfffff000      /* lower serial ring base addr */
+
+/* bitmasks for IOC3_SSCR_<A:B> */
+#define SSCR_RX_THRESHOLD 0x000001ff    /* hiwater mark */
+#define SSCR_TX_TIMER_BUSY 0x00010000   /* TX timer in progress */
+#define SSCR_HFC_EN     0x00020000      /* hardware flow control enabled */
+#define SSCR_RX_RING_DCD 0x00040000     /* post RX record on delta-DCD */
+#define SSCR_RX_RING_CTS 0x00080000     /* post RX record on delta-CTS */
+#define SSCR_HIGH_SPD   0x00100000      /* 4X speed */
+#define SSCR_DIAG       0x00200000      /* bypass clock divider for sim */
+#define SSCR_RX_DRAIN   0x08000000      /* drain RX buffer to memory */
+#define SSCR_DMA_EN     0x10000000      /* enable ring buffer DMA */
+#define SSCR_DMA_PAUSE  0x20000000      /* pause DMA */
+#define SSCR_PAUSE_STATE 0x40000000     /* sets when PAUSE takes effect */
+#define SSCR_RESET      0x80000000      /* reset DMA channels */
+
+/* all producer/comsumer pointers are the same bitfield */
+#define PROD_CONS_PTR_4K 0x00000ff8     /* for 4K buffers */
+#define PROD_CONS_PTR_1K 0x000003f8     /* for 1K buffers */
+#define PROD_CONS_PTR_OFF 3
+
+/* bitmasks for IOC3_SRCIR_<A:B> */
+#define SRCIR_ARM       0x80000000      /* arm RX timer */
+
+/* bitmasks for IOC3_SRPIR_<A:B> */
+#define SRPIR_BYTE_CNT  0x07000000      /* bytes in packer */
+#define SRPIR_BYTE_CNT_SHIFT 24
+
+/* bitmasks for IOC3_STCIR_<A:B> */
+#define STCIR_BYTE_CNT  0x0f000000      /* bytes in unpacker */
+#define STCIR_BYTE_CNT_SHIFT 24
+
+/* bitmasks for IOC3_SHADOW_<A:B> */
+#define SHADOW_DR       0x00000001      /* data ready */
+#define SHADOW_OE       0x00000002      /* overrun error */
+#define SHADOW_PE       0x00000004      /* parity error */
+#define SHADOW_FE       0x00000008      /* framing error */
+#define SHADOW_BI       0x00000010      /* break interrupt */
+#define SHADOW_THRE     0x00000020      /* transmit holding register empty */
+#define SHADOW_TEMT     0x00000040      /* transmit shift register empty */
+#define SHADOW_RFCE     0x00000080      /* char in RX fifo has an error */
+#define SHADOW_DCTS     0x00010000      /* delta clear to send */
+#define SHADOW_DDCD     0x00080000      /* delta data carrier detect */
+#define SHADOW_CTS      0x00100000      /* clear to send */
+#define SHADOW_DCD      0x00800000      /* data carrier detect */
+#define SHADOW_DTR      0x01000000      /* data terminal ready */
+#define SHADOW_RTS      0x02000000      /* request to send */
+#define SHADOW_OUT1     0x04000000      /* 16550 OUT1 bit */
+#define SHADOW_OUT2     0x08000000      /* 16550 OUT2 bit */
+#define SHADOW_LOOP     0x10000000      /* loopback enabled */
+
+/* bitmasks for IOC3_SRTR_<A:B> */
+#define SRTR_CNT        0x00000fff      /* reload value for RX timer */
+#define SRTR_CNT_VAL    0x0fff0000      /* current value of RX timer */
+#define SRTR_CNT_VAL_SHIFT 16
+#define SRTR_HZ         16000   /* SRTR clock frequency */
+
+/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES  */
+#define SIO_IR_SA_TX_MT         0x00000001      /* Serial port A TX empty */
+#define SIO_IR_SA_RX_FULL       0x00000002      /* port A RX buf full */
+#define SIO_IR_SA_RX_HIGH       0x00000004      /* port A RX hiwat */
+#define SIO_IR_SA_RX_TIMER      0x00000008      /* port A RX timeout */
+#define SIO_IR_SA_DELTA_DCD     0x00000010      /* port A delta DCD */
+#define SIO_IR_SA_DELTA_CTS     0x00000020      /* port A delta CTS */
+#define SIO_IR_SA_INT           0x00000040      /* port A pass-thru intr */
+#define SIO_IR_SA_TX_EXPLICIT   0x00000080      /* port A explicit TX thru */
+#define SIO_IR_SA_MEMERR        0x00000100      /* port A PCI error */
+#define SIO_IR_SB_TX_MT         0x00000200      /* */
+#define SIO_IR_SB_RX_FULL       0x00000400      /* */
+#define SIO_IR_SB_RX_HIGH       0x00000800      /* */
+#define SIO_IR_SB_RX_TIMER      0x00001000      /* */
+#define SIO_IR_SB_DELTA_DCD     0x00002000      /* */
+#define SIO_IR_SB_DELTA_CTS     0x00004000      /* */
+#define SIO_IR_SB_INT           0x00008000      /* */
+#define SIO_IR_SB_TX_EXPLICIT   0x00010000      /* */
+#define SIO_IR_SB_MEMERR        0x00020000      /* */
+#define SIO_IR_PP_INT           0x00040000      /* P port pass-thru intr */
+#define SIO_IR_PP_INTA          0x00080000      /* PP context A thru */
+#define SIO_IR_PP_INTB          0x00100000      /* PP context B thru */
+#define SIO_IR_PP_MEMERR        0x00200000      /* PP PCI error */
+#define SIO_IR_KBD_INT          0x00400000      /* kbd/mouse intr */
+#define SIO_IR_RT_INT           0x08000000      /* RT output pulse */
+#define SIO_IR_GEN_INT1         0x10000000      /* RT input pulse */
+#define SIO_IR_GEN_INT_SHIFT    28
+
+/* per device interrupt masks */
+#define SIO_IR_SA               (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
+                                 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
+                                 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
+                                 SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
+                                 SIO_IR_SA_MEMERR)
+#define SIO_IR_SB               (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
+                                 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
+                                 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
+                                 SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
+                                 SIO_IR_SB_MEMERR)
+#define SIO_IR_PP               (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
+                                 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
+#define SIO_IR_RT               (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
+
+/* macro to load pending interrupts */
+#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
+                                 PCI_INW(&((mem)->sio_ies_ro)))
+
+/* bitmasks for SIO_CR */
+#define SIO_CR_SIO_RESET        0x00000001      /* reset the SIO */
+#define SIO_CR_SER_A_BASE       0x000000fe      /* DMA poll addr port A */
+#define SIO_CR_SER_A_BASE_SHIFT 1
+#define SIO_CR_SER_B_BASE       0x00007f00      /* DMA poll addr port B */
+#define SIO_CR_SER_B_BASE_SHIFT 8
+#define SIO_SR_CMD_PULSE        0x00078000      /* byte bus strobe length */
+#define SIO_CR_CMD_PULSE_SHIFT  15
+#define SIO_CR_ARB_DIAG         0x00380000      /* cur !enet PCI requet (ro) */
+#define SIO_CR_ARB_DIAG_TXA     0x00000000
+#define SIO_CR_ARB_DIAG_RXA     0x00080000
+#define SIO_CR_ARB_DIAG_TXB     0x00100000
+#define SIO_CR_ARB_DIAG_RXB     0x00180000
+#define SIO_CR_ARB_DIAG_PP      0x00200000
+#define SIO_CR_ARB_DIAG_IDLE    0x00400000      /* 0 -> active request (ro) */
+
+/* bitmasks for INT_OUT */
+#define INT_OUT_COUNT   0x0000ffff      /* pulse interval timer */
+#define INT_OUT_MODE    0x00070000      /* mode mask */
+#define INT_OUT_MODE_0  0x00000000      /* set output to 0 */
+#define INT_OUT_MODE_1  0x00040000      /* set output to 1 */
+#define INT_OUT_MODE_1PULSE 0x00050000  /* send 1 pulse */
+#define INT_OUT_MODE_PULSES 0x00060000  /* send 1 pulse every interval */
+#define INT_OUT_MODE_SQW 0x00070000     /* toggle output every interval */
+#define INT_OUT_DIAG    0x40000000      /* diag mode */
+#define INT_OUT_INT_OUT 0x80000000      /* current state of INT_OUT */
+
+/* time constants for INT_OUT */
+#define INT_OUT_NS_PER_TICK (30 * 260)  /* 30 ns PCI clock, divisor=260 */
+#define INT_OUT_TICKS_PER_PULSE 3       /* outgoing pulse lasts 3 ticks */
+#define INT_OUT_US_TO_COUNT(x)          /* convert uS to a count value */ \
+        (((x) * 10 + INT_OUT_NS_PER_TICK / 200) *       \
+         100 / INT_OUT_NS_PER_TICK - 1)
+#define INT_OUT_COUNT_TO_US(x)          /* convert count value to uS */ \
+        (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
+#define INT_OUT_MIN_TICKS 3     /* min period is width of pulse in "ticks" */
+#define INT_OUT_MAX_TICKS INT_OUT_COUNT         /* largest possible count */
+
+/* bitmasks for GPCR */
+#define GPCR_DIR        0x000000ff      /* tristate pin input or output */
+#define GPCR_DIR_PIN(x) (1<<(x))        /* access one of the DIR bits */
+#define GPCR_EDGE       0x000f0000      /* extint edge or level sensitive */
+#define GPCR_EDGE_PIN(x) (1<<((x)+15))  /* access one of the EDGE bits */
+
+/* values for GPCR */
+#define GPCR_INT_OUT_EN 0x00100000      /* enable INT_OUT to pin 0 */
+#define GPCR_MLAN_EN    0x00200000      /* enable MCR to pin 8 */
+#define GPCR_DIR_SERA_XCVR 0x00000080   /* Port A Transceiver select enable */
+#define GPCR_DIR_SERB_XCVR 0x00000040   /* Port B Transceiver select enable */
+#define GPCR_DIR_PHY_RST   0x00000020   /* ethernet PHY reset enable */
+
+/* defs for some of the generic I/O pins */
+#define GPCR_PHY_RESET          0x20    /* pin is output to PHY reset */
+#define GPCR_UARTB_MODESEL      0x40    /* pin is output to port B mode sel */
+#define GPCR_UARTA_MODESEL      0x80    /* pin is output to port A mode sel */
+
+#define GPPR_PHY_RESET_PIN      5       /* GIO pin controlling phy reset */
+#define GPPR_UARTB_MODESEL_PIN  6       /* GIO pin controlling uart b mode select */
+#define GPPR_UARTA_MODESEL_PIN  7       /* GIO pin controlling uart a mode select */
+
+#define EMCR_DUPLEX             0x00000001
+#define EMCR_PROMISC            0x00000002
+#define EMCR_PADEN              0x00000004
+#define EMCR_RXOFF_MASK         0x000001f8
+#define EMCR_RXOFF_SHIFT        3
+#define EMCR_RAMPAR             0x00000200
+#define EMCR_BADPAR             0x00000800
+#define EMCR_BUFSIZ             0x00001000
+#define EMCR_TXDMAEN            0x00002000
+#define EMCR_TXEN               0x00004000
+#define EMCR_RXDMAEN            0x00008000
+#define EMCR_RXEN               0x00010000
+#define EMCR_LOOPBACK           0x00020000
+#define EMCR_ARB_DIAG           0x001c0000
+#define EMCR_ARB_DIAG_IDLE      0x00200000
+#define EMCR_RST                0x80000000
+
+#define EISR_RXTIMERINT         0x00000001
+#define EISR_RXTHRESHINT        0x00000002
+#define EISR_RXOFLO             0x00000004
+#define EISR_RXBUFOFLO          0x00000008
+#define EISR_RXMEMERR           0x00000010
+#define EISR_RXPARERR           0x00000020
+#define EISR_TXEMPTY            0x00010000
+#define EISR_TXRTRY             0x00020000
+#define EISR_TXEXDEF            0x00040000
+#define EISR_TXLCOL             0x00080000
+#define EISR_TXGIANT            0x00100000
+#define EISR_TXBUFUFLO          0x00200000
+#define EISR_TXEXPLICIT         0x00400000
+#define EISR_TXCOLLWRAP         0x00800000
+#define EISR_TXDEFERWRAP        0x01000000
+#define EISR_TXMEMERR           0x02000000
+#define EISR_TXPARERR           0x04000000
+
+#define ERCSR_THRESH_MASK       0x000001ff      /* enet RX threshold */
+#define ERCSR_RX_TMR            0x40000000      /* simulation only */
+#define ERCSR_DIAG_OFLO         0x80000000      /* simulation only */
+
+#define ERBR_ALIGNMENT          4096
+#define ERBR_L_RXRINGBASE_MASK  0xfffff000
+
+#define ERBAR_BARRIER_BIT       0x0100
+#define ERBAR_RXBARR_MASK       0xffff0000
+#define ERBAR_RXBARR_SHIFT      16
+
+#define ERCIR_RXCONSUME_MASK    0x00000fff
+
+#define ERPIR_RXPRODUCE_MASK    0x00000fff
+#define ERPIR_ARM               0x80000000
+
+#define ERTR_CNT_MASK           0x000007ff
+
+#define ETCSR_IPGT_MASK         0x0000007f
+#define ETCSR_IPGR1_MASK        0x00007f00
+#define ETCSR_IPGR1_SHIFT       8
+#define ETCSR_IPGR2_MASK        0x007f0000
+#define ETCSR_IPGR2_SHIFT       16
+#define ETCSR_NOTXCLK           0x80000000
+
+#define ETCDC_COLLCNT_MASK      0x0000ffff
+#define ETCDC_DEFERCNT_MASK     0xffff0000
+#define ETCDC_DEFERCNT_SHIFT    16
+
+#define ETBR_ALIGNMENT          (64*1024)
+#define ETBR_L_RINGSZ_MASK      0x00000001
+#define ETBR_L_RINGSZ128        0
+#define ETBR_L_RINGSZ512        1
+#define ETBR_L_TXRINGBASE_MASK  0xffffc000
+
+#define ETCIR_TXCONSUME_MASK    0x0000ffff
+#define ETCIR_IDLE              0x80000000
+
+#define ETPIR_TXPRODUCE_MASK    0x0000ffff
+
+#define EBIR_TXBUFPROD_MASK     0x0000001f
+#define EBIR_TXBUFCONS_MASK     0x00001f00
+#define EBIR_TXBUFCONS_SHIFT    8
+#define EBIR_RXBUFPROD_MASK     0x007fc000
+#define EBIR_RXBUFPROD_SHIFT    14
+#define EBIR_RXBUFCONS_MASK     0xff800000
+#define EBIR_RXBUFCONS_SHIFT    23
+
+#define MICR_REGADDR_MASK       0x0000001f
+#define MICR_PHYADDR_MASK       0x000003e0
+#define MICR_PHYADDR_SHIFT      5
+#define MICR_READTRIG           0x00000400
+#define MICR_BUSY               0x00000800
+
+#define MIDR_DATA_MASK          0x0000ffff
+
+#define ERXBUF_IPCKSUM_MASK     0x0000ffff
+#define ERXBUF_BYTECNT_MASK     0x07ff0000
+#define ERXBUF_BYTECNT_SHIFT    16
+#define ERXBUF_V                0x80000000
+
+#define ERXBUF_CRCERR           0x00000001      /* aka RSV15 */
+#define ERXBUF_FRAMERR          0x00000002      /* aka RSV14 */
+#define ERXBUF_CODERR           0x00000004      /* aka RSV13 */
+#define ERXBUF_INVPREAMB        0x00000008      /* aka RSV18 */
+#define ERXBUF_LOLEN            0x00007000      /* aka RSV2_0 */
+#define ERXBUF_HILEN            0x03ff0000      /* aka RSV12_3 */
+#define ERXBUF_MULTICAST        0x04000000      /* aka RSV16 */
+#define ERXBUF_BROADCAST        0x08000000      /* aka RSV17 */
+#define ERXBUF_LONGEVENT        0x10000000      /* aka RSV19 */
+#define ERXBUF_BADPKT           0x20000000      /* aka RSV20 */
+#define ERXBUF_GOODPKT          0x40000000      /* aka RSV21 */
+#define ERXBUF_CARRIER          0x80000000      /* aka RSV22 */
+
+#define ETXD_BYTECNT_MASK       0x000007ff      /* total byte count */
+#define ETXD_INTWHENDONE        0x00001000      /* intr when done */
+#define ETXD_D0V                0x00010000      /* data 0 valid */
+#define ETXD_B1V                0x00020000      /* buf 1 valid */
+#define ETXD_B2V                0x00040000      /* buf 2 valid */
+#define ETXD_DOCHECKSUM         0x00080000      /* insert ip cksum */
+#define ETXD_CHKOFF_MASK        0x07f00000      /* cksum byte offset */
+#define ETXD_CHKOFF_SHIFT       20
+
+#define ETXD_D0CNT_MASK         0x0000007f
+#define ETXD_B1CNT_MASK         0x0007ff00
+#define ETXD_B1CNT_SHIFT        8
+#define ETXD_B2CNT_MASK         0x7ff00000
+#define ETXD_B2CNT_SHIFT        20
+
+typedef enum ioc3_subdevs_e {
+    ioc3_subdev_ether,
+    ioc3_subdev_generic,
+    ioc3_subdev_nic,
+    ioc3_subdev_kbms,
+    ioc3_subdev_ttya,
+    ioc3_subdev_ttyb,
+    ioc3_subdev_ecpp,
+    ioc3_subdev_rt,
+    ioc3_nsubdevs
+} ioc3_subdev_t;
+
+/* subdevice disable bits,
+ * from the standard INFO_LBL_SUBDEVS
+ */
+#define IOC3_SDB_ETHER          (1<<ioc3_subdev_ether)
+#define IOC3_SDB_GENERIC        (1<<ioc3_subdev_generic)
+#define IOC3_SDB_NIC            (1<<ioc3_subdev_nic)
+#define IOC3_SDB_KBMS           (1<<ioc3_subdev_kbms)
+#define IOC3_SDB_TTYA           (1<<ioc3_subdev_ttya)
+#define IOC3_SDB_TTYB           (1<<ioc3_subdev_ttyb)
+#define IOC3_SDB_ECPP           (1<<ioc3_subdev_ecpp)
+#define IOC3_SDB_RT             (1<<ioc3_subdev_rt)
+
+#define IOC3_ALL_SUBDEVS        ((1<<ioc3_nsubdevs)-1)
+
+#define IOC3_SDB_SERIAL         (IOC3_SDB_TTYA|IOC3_SDB_TTYB)
+
+#define IOC3_STD_SUBDEVS        IOC3_ALL_SUBDEVS
+
+#define IOC3_INTA_SUBDEVS       IOC3_SDB_ETHER
+#define IOC3_INTB_SUBDEVS       (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
+
+#endif /* _IOC3_H */
diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
new file mode 100644
index 000000000000..09e590daca17
--- /dev/null
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -0,0 +1,898 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/klconfig.h>.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_SN_KLCONFIG_H
+#define _ASM_SN_KLCONFIG_H
+
+/*
+ * The KLCONFIG structures store info about the various BOARDs found
+ * during Hardware Discovery. In addition, it stores info about the
+ * components found on the BOARDs.
+ */
+
+/*
+ * WARNING:
+ *      Certain assembly language routines (notably xxxxx.s) in the IP27PROM
+ *      will depend on the format of the data structures in this file.  In
+ *      most cases, rearranging the fields can seriously break things.
+ *      Adding fields in the beginning or middle can also break things.
+ *      Add fields if necessary, to the end of a struct in such a way
+ *      that offsets of existing fields do not change.
+ */
+
+#include <linux/types.h>
+#include <asm/sn/types.h>
+
+#if defined(CONFIG_SGI_IP27)
+
+#include <asm/sn/sn0/addrs.h>
+//#include <sys/SN/router.h>
+// XXX Stolen from <sys/SN/router.h>:
+#define MAX_ROUTER_PORTS (6)    /* Max. number of ports on a router */
+#include <asm/sn/fru.h>
+//#include <sys/graph.h>
+//#include <sys/xtalk/xbow.h>
+
+#elif defined(CONFIG_SGI_IP35)
+
+#include <asm/sn/sn1/addrs.h>
+#include <sys/sn/router.h>
+#include <sys/graph.h>
+#include <asm/xtalk/xbow.h>
+
+#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
+
+#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35)
+#include <asm/sn/agent.h>
+#include <asm/fw/arc/types.h>
+#include <asm/fw/arc/hinv.h>
+#if defined(CONFIG_SGI_IP35)
+// The hack file has to be before vector and after sn0_fru....
+#include <asm/hack.h>
+#include <asm/sn/vector.h>
+#include <asm/xtalk/xtalk.h>
+#endif /* CONFIG_SGI_IP35 */
+#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
+
+typedef u64  nic_t;
+
+#define KLCFGINFO_MAGIC 0xbeedbabe
+
+typedef s32 klconf_off_t;
+
+/*
+ * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
+ */
+#define MAX_MODULE_ID           255
+#define SIZE_PAD                4096 /* 4k padding for structures */
+/*
+ * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets,
+ * 2 Midplanes assuming no pci card cages
+ */
+#define MAX_SLOTS_PER_NODE      (1 + 2 + 6 + 2)
+
+/* XXX if each node is guranteed to have some memory */
+
+#define MAX_PCI_DEVS            8
+
+/* lboard_t->brd_flags fields */
+/* All bits in this field are currently used. Try the pad fields if
+   you need more flag bits */
+
+#define ENABLE_BOARD            0x01
+#define FAILED_BOARD            0x02
+#define DUPLICATE_BOARD         0x04    /* Boards like midplanes/routers which
+                                           are discovered twice. Use one of them */
+#define VISITED_BOARD           0x08    /* Used for compact hub numbering. */
+#define LOCAL_MASTER_IO6        0x10    /* master io6 for that node */
+#define GLOBAL_MASTER_IO6       0x20
+#define THIRD_NIC_PRESENT       0x40    /* for future use */
+#define SECOND_NIC_PRESENT      0x80    /* addons like MIO are present */
+
+/* klinfo->flags fields */
+
+#define KLINFO_ENABLE           0x01    /* This component is enabled */
+#define KLINFO_FAILED           0x02    /* This component failed */
+#define KLINFO_DEVICE           0x04    /* This component is a device */
+#define KLINFO_VISITED          0x08    /* This component has been visited */
+#define KLINFO_CONTROLLER       0x10    /* This component is a device controller */
+#define KLINFO_INSTALL          0x20    /* Install a driver */
+#define KLINFO_HEADLESS         0x40    /* Headless (or hubless) component */
+#define IS_CONSOLE_IOC3(i)      ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
+
+#define GB2             0x80000000
+
+#define MAX_RSV_PTRS    32
+
+/* Structures to manage various data storage areas */
+/* The numbers must be contiguous since the array index i
+   is used in the code to allocate various areas.
+*/
+
+#define BOARD_STRUCT            0
+#define COMPONENT_STRUCT        1
+#define ERRINFO_STRUCT          2
+#define KLMALLOC_TYPE_MAX       (ERRINFO_STRUCT + 1)
+#define DEVICE_STRUCT           3
+
+
+typedef struct console_s {
+        unsigned long   uart_base;
+        unsigned long   config_base;
+        unsigned long   memory_base;
+        short           baud;
+        short           flag;
+        int             type;
+        nasid_t         nasid;
+        char            wid;
+        char            npci;
+        nic_t           baseio_nic;
+} console_t;
+
+typedef struct klc_malloc_hdr {
+        klconf_off_t km_base;
+        klconf_off_t km_limit;
+        klconf_off_t km_current;
+} klc_malloc_hdr_t;
+
+/* Functions/macros needed to use this structure */
+
+typedef struct kl_config_hdr {
+        u64             ch_magic;       /* set this to KLCFGINFO_MAGIC */
+        u32             ch_version;    /* structure version number */
+        klconf_off_t    ch_malloc_hdr_off; /* offset of ch_malloc_hdr */
+        klconf_off_t    ch_cons_off;       /* offset of ch_cons */
+        klconf_off_t    ch_board_info;  /* the link list of boards */
+        console_t       ch_cons_info;   /* address info of the console */
+        klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];
+        confidence_t    ch_sw_belief;   /* confidence that software is bad*/
+        confidence_t    ch_sn0net_belief; /* confidence that sn0net is bad */
+} kl_config_hdr_t;
+
+
+#define KL_CONFIG_HDR(_nasid)   ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
+#define KL_CONFIG_INFO_OFFSET(_nasid)                                   \
+        (KL_CONFIG_HDR(_nasid)->ch_board_info)
+#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)                         \
+        (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
+
+#define KL_CONFIG_INFO(_nasid)                                          \
+        (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ?           \
+         NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
+         0)
+#define KL_CONFIG_MAGIC(_nasid)         (KL_CONFIG_HDR(_nasid)->ch_magic)
+
+#define KL_CONFIG_CHECK_MAGIC(_nasid)                                   \
+        (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
+
+#define KL_CONFIG_HDR_INIT_MAGIC(_nasid)        \
+                  (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
+
+/* --- New Macros for the changed kl_config_hdr_t structure --- */
+
+#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+                        ((unsigned long)_k + (_k->ch_malloc_hdr_off)))
+
+#define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
+
+#define PTR_CH_CONS_INFO(_k)    ((console_t *)\
+                        ((unsigned long)_k + (_k->ch_cons_off)))
+
+#define KL_CONFIG_CH_CONS_INFO(_n)   PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
+
+/* ------------------------------------------------------------- */
+
+#define KL_CONFIG_INFO_START(_nasid)    \
+        (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
+
+#define KL_CONFIG_BOARD_NASID(_brd)     ((_brd)->brd_nasid)
+#define KL_CONFIG_BOARD_SET_NEXT(_brd, _off)    ((_brd)->brd_next = (_off))
+
+#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD)
+
+#define XBOW_PORT_TYPE_HUB(_xbowp, _link)       \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
+#define XBOW_PORT_TYPE_IO(_xbowp, _link)        \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
+
+#define XBOW_PORT_IS_ENABLED(_xbowp, _link)     \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
+#define XBOW_PORT_NASID(_xbowp, _link)  \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
+
+#define XBOW_PORT_IO     0x1
+#define XBOW_PORT_HUB    0x2
+#define XBOW_PORT_ENABLE 0x4
+
+#define SN0_PORT_FENCE_SHFT     0
+#define SN0_PORT_FENCE_MASK     (1 << SN0_PORT_FENCE_SHFT)
+
+/*
+ * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
+ * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
+ * the LOCAL/current NODE. REMOTE means it is attached to a different
+ * node.(TBD - Need a way to treat ROUTER boards.)
+ *
+ * There are 2 different structures to represent these boards -
+ * lboard - Local board, rboard - remote board. These 2 structures
+ * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
+ * Figure below). The first byte of the rboard or lboard structure
+ * is used to find out its type - no unions are used.
+ * If it is a lboard, then the config info of this board will be found
+ * on the local node. (LOCAL NODE BASE + offset value gives pointer to
+ * the structure.
+ * If it is a rboard, the local structure contains the node number
+ * and the offset of the beginning of the LINKED LIST on the remote node.
+ * The details of the hardware on a remote node can be built locally,
+ * if required, by reading the LINKED LIST on the remote node and
+ * ignoring all the rboards on that node.
+ *
+ * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
+ * First board info on the remote node. The remote node list is
+ * traversed as the local list, using the REMOTE BASE ADDRESS and not
+ * the local base address and ignoring all rboard values.
+ *
+ *
+ KLCONFIG
+
+ +------------+      +------------+      +------------+      +------------+
+ |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
+ +------------+      +------------+      +------------+      +------------+
+
+
+ +------------+
+ | board info |
+ +------------+       +--------------------------------+
+ | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
+ +------------+       +--------------------------------+
+ | compt 2    |--+
+ +------------+  |    +--------------------------------+
+ |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
+ +------------+       +--------------------------------+
+ | errinfo    |--+
+ +------------+  |    +--------------------------------+
+                 +--->|r/l brd errinfo,compt err flags |
+                      +--------------------------------+
+
+ *
+ * Each BOARD consists of COMPONENTs and the BOARD structure has
+ * pointers (offsets) to its COMPONENT structure.
+ * The COMPONENT structure has version info, size and speed info, revision,
+ * error info and the NIC info. This structure can accommodate any
+ * BOARD with arbitrary COMPONENT composition.
+ *
+ * The ERRORINFO part of each BOARD has error information
+ * that describes errors about the BOARD itself. It also has flags to
+ * indicate the COMPONENT(s) on the board that have errors. The error
+ * information specific to the COMPONENT is present in the respective
+ * COMPONENT structure.
+ *
+ * The ERRORINFO structure is also treated like a COMPONENT, ie. the
+ * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
+ * structure also has a pointer to the ERRORINFO structure. This is
+ * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
+ * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
+ * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
+ * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
+ * which is present on the REMOTE NODE.(TBD)
+ * REMOTE ERRINFO can be stored on any of the nearest nodes
+ * or on all the nearest nodes.(TBD)
+ * Like BOARD structures, REMOTE ERRINFO structures can be built locally
+ * using the rboard errinfo pointer.
+ *
+ * In order to get useful information from this Data organization, a set of
+ * interface routines are provided (TBD). The important thing to remember while
+ * manipulating the structures, is that, the NODE number information should
+ * be used. If the NODE is non-zero (remote) then each offset should
+ * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
+ * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
+ *
+ * Note that these structures do not provide much info about connectivity.
+ * That info will be part of HWGRAPH, which is an extension of the cfg_t
+ * data structure. (ref IP27prom/cfg.h) It has to be extended to include
+ * the IO part of the Network(TBD).
+ *
+ * The data structures below define the above concepts.
+ */
+
+/*
+ * Values for CPU types
+ */
+#define KL_CPU_R4000            0x1     /* Standard R4000 */
+#define KL_CPU_TFP              0x2     /* TFP processor */
+#define KL_CPU_R10000           0x3     /* R10000 (T5) */
+#define KL_CPU_NONE             (-1)    /* no cpu present in slot */
+
+/*
+ * IP27 BOARD classes
+ */
+
+#define KLCLASS_MASK    0xf0
+#define KLCLASS_NONE    0x00
+#define KLCLASS_NODE    0x10             /* CPU, Memory and HUB board */
+#define KLCLASS_CPU     KLCLASS_NODE
+#define KLCLASS_IO      0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI
+                                            and the non-graphics widget boards */
+#define KLCLASS_ROUTER  0x30             /* Router board */
+#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
+                                            so that we can record error info */
+#define KLCLASS_GFX     0x50            /* graphics boards */
+
+#define KLCLASS_PSEUDO_GFX      0x60    /* HDTV type cards that use a gfx
+                                         * hw ifc to xtalk and are not gfx
+                                         * class for sw purposes */
+
+#define KLCLASS_MAX     7               /* Bump this if a new CLASS is added */
+#define KLTYPE_MAX      10              /* Bump this if a new CLASS is added */
+
+#define KLCLASS_UNKNOWN 0xf0
+
+#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
+
+/*
+ * IP27 board types
+ */
+
+#define KLTYPE_MASK     0x0f
+#define KLTYPE_NONE     0x00
+#define KLTYPE_EMPTY    0x00
+
+#define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0)
+#define KLTYPE_IP27     (KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */
+
+#define KLTYPE_WEIRDIO  (KLCLASS_IO  | 0x0)
+#define KLTYPE_BASEIO   (KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
+#define KLTYPE_IO6      KLTYPE_BASEIO       /* Additional name */
+#define KLTYPE_4CHSCSI  (KLCLASS_IO  | 0x2)
+#define KLTYPE_MSCSI    KLTYPE_4CHSCSI      /* Additional name */
+#define KLTYPE_ETHERNET (KLCLASS_IO  | 0x3)
+#define KLTYPE_MENET    KLTYPE_ETHERNET     /* Additional name */
+#define KLTYPE_FDDI     (KLCLASS_IO  | 0x4)
+#define KLTYPE_UNUSED   (KLCLASS_IO  | 0x5) /* XXX UNUSED */
+#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
+#define KLTYPE_PCI      KLTYPE_HAROLD
+#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
+#define KLTYPE_MIO      (KLCLASS_IO  | 0x8)
+#define KLTYPE_FC       (KLCLASS_IO  | 0x9)
+#define KLTYPE_LINC     (KLCLASS_IO  | 0xA)
+#define KLTYPE_TPU      (KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
+#define KLTYPE_GSN_A    (KLCLASS_IO  | 0xC) /* Main GSN board */
+#define KLTYPE_GSN_B    (KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
+
+#define KLTYPE_GFX      (KLCLASS_GFX | 0x0) /* unknown graphics type */
+#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
+#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
+
+#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
+#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
+#define KLTYPE_ROUTER2    KLTYPE_ROUTER         /* Obsolete! */
+#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
+#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
+
+#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
+#define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
+#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
+#define KLTYPE_PBRICK_XBOW      (KLCLASS_MIDPLANE | 0x2)
+
+#define KLTYPE_IOBRICK          (KLCLASS_IOBRICK | 0x0)
+#define KLTYPE_IBRICK           (KLCLASS_IOBRICK | 0x1)
+#define KLTYPE_PBRICK           (KLCLASS_IOBRICK | 0x2)
+#define KLTYPE_XBRICK           (KLCLASS_IOBRICK | 0x3)
+
+#define KLTYPE_PBRICK_BRIDGE    KLTYPE_PBRICK
+
+/* The value of type should be more than 8 so that hinv prints
+ * out the board name from the NIC string. For values less than
+ * 8 the name of the board needs to be hard coded in a few places.
+ * When bringup started nic names had not standardized and so we
+ * had to hard code. (For people interested in history.)
+ */
+#define KLTYPE_XTHD     (KLCLASS_PSEUDO_GFX | 0x9)
+
+#define KLTYPE_UNKNOWN  (KLCLASS_UNKNOWN | 0xf)
+
+#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
+#define IS_MIO_PRESENT(l)       ((l->brd_type == KLTYPE_BASEIO) && \
+                                 (l->brd_flags & SECOND_NIC_PRESENT))
+#define IS_MIO_IOC3(l, n)       (IS_MIO_PRESENT(l) && (n > 2))
+
+/*
+ * board structures
+ */
+
+#define MAX_COMPTS_PER_BRD 24
+
+#define LOCAL_BOARD 1
+#define REMOTE_BOARD 2
+
+#define LBOARD_STRUCT_VERSION   2
+
+typedef struct lboard_s {
+        klconf_off_t    brd_next;         /* Next BOARD */
+        unsigned char   struct_type;      /* type of structure, local or remote */
+        unsigned char   brd_type;         /* type+class */
+        unsigned char   brd_sversion;     /* version of this structure */
+        unsigned char   brd_brevision;    /* board revision */
+        unsigned char   brd_promver;      /* board prom version, if any */
+        unsigned char   brd_flags;        /* Enabled, Disabled etc */
+        unsigned char   brd_slot;         /* slot number */
+        unsigned short  brd_debugsw;      /* Debug switches */
+        moduleid_t      brd_module;       /* module to which it belongs */
+        partid_t        brd_partition;    /* Partition number */
+        unsigned short  brd_diagval;      /* diagnostic value */
+        unsigned short  brd_diagparm;     /* diagnostic parameter */
+        unsigned char   brd_inventory;    /* inventory history */
+        unsigned char   brd_numcompts;    /* Number of components */
+        nic_t           brd_nic;          /* Number in CAN */
+        nasid_t         brd_nasid;        /* passed parameter */
+        klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
+        klconf_off_t    brd_errinfo;      /* Board's error information */
+        struct lboard_s *brd_parent;      /* Logical parent for this brd */
+        vertex_hdl_t    brd_graph_link;   /* vertex hdl to connect extern compts */
+        confidence_t    brd_confidence;   /* confidence that the board is bad */
+        nasid_t         brd_owner;        /* who owns this board */
+        unsigned char   brd_nic_flags;    /* To handle 8 more NICs */
+        char            brd_name[32];
+} lboard_t;
+
+
+/*
+ *      Make sure we pass back the calias space address for local boards.
+ *      klconfig board traversal and error structure extraction defines.
+ */
+
+#define BOARD_SLOT(_brd)        ((_brd)->brd_slot)
+
+#define KLCF_CLASS(_brd)        KLCLASS((_brd)->brd_type)
+#define KLCF_TYPE(_brd)         KLTYPE((_brd)->brd_type)
+#define KLCF_REMOTE(_brd)       (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
+#define KLCF_NUM_COMPS(_brd)    ((_brd)->brd_numcompts)
+#define KLCF_MODULE_ID(_brd)    ((_brd)->brd_module)
+
+#define KLCF_NEXT(_brd)         \
+        ((_brd)->brd_next ?     \
+         (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
+         NULL)
+#define KLCF_COMP(_brd, _ndx)   \
+                (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \
+                                               (_brd)->brd_compts[(_ndx)]))
+
+#define KLCF_COMP_ERROR(_brd, _comp)    \
+               (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
+
+#define KLCF_COMP_TYPE(_comp)   ((_comp)->struct_type)
+#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid)       /* Widget ID */
+
+
+
+/*
+ * Generic info structure. This stores common info about a
+ * component.
+ */
+
+typedef struct klinfo_s {                  /* Generic info */
+        unsigned char   struct_type;       /* type of this structure */
+        unsigned char   struct_version;    /* version of this structure */
+        unsigned char   flags;            /* Enabled, disabled etc */
+        unsigned char   revision;         /* component revision */
+        unsigned short  diagval;          /* result of diagnostics */
+        unsigned short  diagparm;         /* diagnostic parameter */
+        unsigned char   inventory;        /* previous inventory status */
+        nic_t           nic;              /* MUst be aligned properly */
+        unsigned char   physid;           /* physical id of component */
+        unsigned int    virtid;           /* virtual id as seen by system */
+        unsigned char   widid;            /* Widget id - if applicable */
+        nasid_t         nasid;            /* node number - from parent */
+        char            pad1;             /* pad out structure. */
+        char            pad2;             /* pad out structure. */
+        COMPONENT       *arcs_compt;      /* ptr to the arcs struct for ease*/
+        klconf_off_t    errinfo;          /* component specific errors */
+        unsigned short  pad3;             /* pci fields have moved over to */
+        unsigned short  pad4;             /* klbri_t */
+} klinfo_t ;
+
+#define KLCONFIG_INFO_ENABLED(_i)       ((_i)->flags & KLINFO_ENABLE)
+/*
+ * Component structures.
+ * Following are the currently identified components:
+ *      CPU, HUB, MEM_BANK,
+ *      XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
+ *      BRIDGE, IOC3, SuperIO, SCSI, FDDI
+ *      ROUTER
+ *      GRAPHICS
+ */
+#define KLSTRUCT_UNKNOWN        0
+#define KLSTRUCT_CPU            1
+#define KLSTRUCT_HUB            2
+#define KLSTRUCT_MEMBNK         3
+#define KLSTRUCT_XBOW           4
+#define KLSTRUCT_BRI            5
+#define KLSTRUCT_IOC3           6
+#define KLSTRUCT_PCI            7
+#define KLSTRUCT_VME            8
+#define KLSTRUCT_ROU            9
+#define KLSTRUCT_GFX            10
+#define KLSTRUCT_SCSI           11
+#define KLSTRUCT_FDDI           12
+#define KLSTRUCT_MIO            13
+#define KLSTRUCT_DISK           14
+#define KLSTRUCT_TAPE           15
+#define KLSTRUCT_CDROM          16
+#define KLSTRUCT_HUB_UART       17
+#define KLSTRUCT_IOC3ENET       18
+#define KLSTRUCT_IOC3UART       19
+#define KLSTRUCT_UNUSED         20 /* XXX UNUSED */
+#define KLSTRUCT_IOC3PCKM       21
+#define KLSTRUCT_RAD            22
+#define KLSTRUCT_HUB_TTY        23
+#define KLSTRUCT_IOC3_TTY       24
+
+/* Early Access IO proms are compatible
+   only with KLSTRUCT values upto 24. */
+
+#define KLSTRUCT_FIBERCHANNEL   25
+#define KLSTRUCT_MOD_SERIAL_NUM 26
+#define KLSTRUCT_IOC3MS         27
+#define KLSTRUCT_TPU            28
+#define KLSTRUCT_GSN_A          29
+#define KLSTRUCT_GSN_B          30
+#define KLSTRUCT_XTHD           31
+
+/*
+ * These are the indices of various components within a lboard structure.
+ */
+
+#define IP27_CPU0_INDEX 0
+#define IP27_CPU1_INDEX 1
+#define IP27_HUB_INDEX 2
+#define IP27_MEM_INDEX 3
+
+#define BASEIO_BRIDGE_INDEX 0
+#define BASEIO_IOC3_INDEX 1
+#define BASEIO_SCSI1_INDEX 2
+#define BASEIO_SCSI2_INDEX 3
+
+#define MIDPLANE_XBOW_INDEX 0
+#define ROUTER_COMPONENT_INDEX 0
+
+#define CH4SCSI_BRIDGE_INDEX 0
+
+/* Info holders for various hardware components */
+
+typedef u64 *pci_t;
+typedef u64 *vmeb_t;
+typedef u64 *vmed_t;
+typedef u64 *fddi_t;
+typedef u64 *scsi_t;
+typedef u64 *mio_t;
+typedef u64 *graphics_t;
+typedef u64 *router_t;
+
+/*
+ * The port info in ip27_cfg area translates to a lboart_t in the
+ * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
+ * is stored in terms of a nasid and a offset from start of KLCONFIG
+ * area  on that nasid.
+ */
+typedef struct klport_s {
+        nasid_t         port_nasid;
+        unsigned char   port_flag;
+        klconf_off_t    port_offset;
+} klport_t;
+
+typedef struct klcpu_s {                          /* CPU */
+        klinfo_t        cpu_info;
+        unsigned short  cpu_prid;       /* Processor PRID value */
+        unsigned short  cpu_fpirr;      /* FPU IRR value */
+        unsigned short  cpu_speed;      /* Speed in MHZ */
+        unsigned short  cpu_scachesz;   /* secondary cache size in MB */
+        unsigned short  cpu_scachespeed;/* secondary cache speed in MHz */
+} klcpu_t ;
+
+#define CPU_STRUCT_VERSION   2
+
+typedef struct klhub_s {                        /* HUB */
+        klinfo_t        hub_info;
+        unsigned int            hub_flags;              /* PCFG_HUB_xxx flags */
+        klport_t        hub_port;               /* hub is connected to this */
+        nic_t           hub_box_nic;            /* nic of containing box */
+        klconf_off_t    hub_mfg_nic;            /* MFG NIC string */
+        u64             hub_speed;              /* Speed of hub in HZ */
+} klhub_t ;
+
+typedef struct klhub_uart_s {                   /* HUB */
+        klinfo_t        hubuart_info;
+        unsigned int            hubuart_flags;          /* PCFG_HUB_xxx flags */
+        nic_t           hubuart_box_nic;        /* nic of containing box */
+} klhub_uart_t ;
+
+#define MEMORY_STRUCT_VERSION   2
+
+typedef struct klmembnk_s {                     /* MEMORY BANK */
+        klinfo_t        membnk_info;
+        short           membnk_memsz;           /* Total memory in megabytes */
+        short           membnk_dimm_select; /* bank to physical addr mapping*/
+        short           membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
+        short           membnk_attr;
+} klmembnk_t ;
+
+#define KLCONFIG_MEMBNK_SIZE(_info, _bank)      \
+                            ((_info)->membnk_bnksz[(_bank)])
+
+
+#define MEMBNK_PREMIUM 1
+#define KLCONFIG_MEMBNK_PREMIUM(_info, _bank)   \
+                            ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
+
+#define MAX_SERIAL_NUM_SIZE 10
+
+typedef struct klmod_serial_num_s {
+      klinfo_t        snum_info;
+      union {
+              char snum_str[MAX_SERIAL_NUM_SIZE];
+              unsigned long long       snum_int;
+      } snum;
+} klmod_serial_num_t;
+
+/* Macros needed to access serial number structure in lboard_t.
+   Hard coded values are necessary since we cannot treat
+   serial number struct as a component without losing compatibility
+   between prom versions. */
+
+#define GET_SNUM_COMP(_l)       ((klmod_serial_num_t *)\
+                                KLCF_COMP(_l, _l->brd_numcompts))
+
+#define MAX_XBOW_LINKS 16
+
+typedef struct klxbow_s {                          /* XBOW */
+        klinfo_t        xbow_info ;
+        klport_t        xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
+        int             xbow_master_hub_link;
+        /* type of brd connected+component struct ptr+flags */
+} klxbow_t ;
+
+#define MAX_PCI_SLOTS 8
+
+typedef struct klpci_device_s {
+        s32     pci_device_id;  /* 32 bits of vendor/device ID. */
+        s32     pci_device_pad; /* 32 bits of padding. */
+} klpci_device_t;
+
+#define BRIDGE_STRUCT_VERSION   2
+
+typedef struct klbri_s {                          /* BRIDGE */
+        klinfo_t        bri_info ;
+        unsigned char   bri_eprominfo ;    /* IO6prom connected to bridge */
+        unsigned char   bri_bustype ;      /* PCI/VME BUS bridge/GIO */
+        pci_t           pci_specific  ;    /* PCI Board config info */
+        klpci_device_t  bri_devices[MAX_PCI_DEVS] ;     /* PCI IDs */
+        klconf_off_t    bri_mfg_nic ;
+} klbri_t ;
+
+#define MAX_IOC3_TTY    2
+
+typedef struct klioc3_s {                          /* IOC3 */
+        klinfo_t        ioc3_info ;
+        unsigned char   ioc3_ssram ;        /* Info about ssram */
+        unsigned char   ioc3_nvram ;        /* Info about nvram */
+        klinfo_t        ioc3_superio ;      /* Info about superio */
+        klconf_off_t    ioc3_tty_off ;
+        klinfo_t        ioc3_enet ;
+        klconf_off_t    ioc3_enet_off ;
+        klconf_off_t    ioc3_kbd_off ;
+} klioc3_t ;
+
+#define MAX_VME_SLOTS 8
+
+typedef struct klvmeb_s {                          /* VME BRIDGE - PCI CTLR */
+        klinfo_t        vmeb_info ;
+        vmeb_t          vmeb_specific ;
+        klconf_off_t    vmeb_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+} klvmeb_t ;
+
+typedef struct klvmed_s {                          /* VME DEVICE - VME BOARD */
+        klinfo_t        vmed_info ;
+        vmed_t          vmed_specific ;
+        klconf_off_t    vmed_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+} klvmed_t ;
+
+#define ROUTER_VECTOR_VERS      2
+
+/* XXX - Don't we need the number of ports here?!? */
+typedef struct klrou_s {                          /* ROUTER */
+        klinfo_t        rou_info ;
+        unsigned int            rou_flags ;           /* PCFG_ROUTER_xxx flags */
+        nic_t           rou_box_nic ;         /* nic of the containing module */
+        klport_t        rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
+        klconf_off_t    rou_mfg_nic ;     /* MFG NIC string */
+        u64     rou_vector;       /* vector from master node */
+} klrou_t ;
+
+/*
+ *  Graphics Controller/Device
+ *
+ *  (IP27/IO6) Prom versions 6.13 (and 6.5.1 kernels) and earlier
+ *  used a couple different structures to store graphics information.
+ *  For compatibility reasons, the newer data structure preserves some
+ *  of the layout so that fields that are used in the old versions remain
+ *  in the same place (with the same info).  Determination of what version
+ *  of this structure we have is done by checking the cookie field.
+ */
+#define KLGFX_COOKIE    0x0c0de000
+
+typedef struct klgfx_s {                /* GRAPHICS Device */
+        klinfo_t        gfx_info;
+        klconf_off_t    old_gndevs;     /* for compatibility with older proms */
+        klconf_off_t    old_gdoff0;     /* for compatibility with older proms */
+        unsigned int            cookie;         /* for compatibility with older proms */
+        unsigned int            moduleslot;
+        struct klgfx_s  *gfx_next_pipe;
+        graphics_t      gfx_specific;
+        klconf_off_t    pad0;           /* for compatibility with older proms */
+        klconf_off_t    gfx_mfg_nic;
+} klgfx_t;
+
+typedef struct klxthd_s {
+        klinfo_t        xthd_info ;
+        klconf_off_t    xthd_mfg_nic ;        /* MFG NIC string */
+} klxthd_t ;
+
+typedef struct kltpu_s {                     /* TPU board */
+        klinfo_t        tpu_info ;
+        klconf_off_t    tpu_mfg_nic ;        /* MFG NIC string */
+} kltpu_t ;
+
+typedef struct klgsn_s {                     /* GSN board */
+        klinfo_t        gsn_info ;
+        klconf_off_t    gsn_mfg_nic ;        /* MFG NIC string */
+} klgsn_t ;
+
+#define MAX_SCSI_DEVS 16
+
+/*
+ * NOTE: THis is the max sized kl* structure and is used in klmalloc.c
+ * to allocate space of type COMPONENT. Make sure that if the size of
+ * any other component struct becomes more than this, then redefine
+ * that as the size to be klmalloced.
+ */
+
+typedef struct klscsi_s {                          /* SCSI Controller */
+        klinfo_t        scsi_info ;
+        scsi_t          scsi_specific   ;
+        unsigned char   scsi_numdevs ;
+        klconf_off_t    scsi_devinfo[MAX_SCSI_DEVS] ;
+} klscsi_t ;
+
+typedef struct klscdev_s {                          /* SCSI device */
+        klinfo_t        scdev_info ;
+        struct scsidisk_data *scdev_cfg ; /* driver fills up this */
+} klscdev_t ;
+
+typedef struct klttydev_s {                          /* TTY device */
+        klinfo_t        ttydev_info ;
+        struct terminal_data *ttydev_cfg ; /* driver fills up this */
+} klttydev_t ;
+
+typedef struct klenetdev_s {                          /* ENET device */
+        klinfo_t        enetdev_info ;
+        struct net_data *enetdev_cfg ; /* driver fills up this */
+} klenetdev_t ;
+
+typedef struct klkbddev_s {                          /* KBD device */
+        klinfo_t        kbddev_info ;
+        struct keyboard_data *kbddev_cfg ; /* driver fills up this */
+} klkbddev_t ;
+
+typedef struct klmsdev_s {                          /* mouse device */
+        klinfo_t        msdev_info ;
+        void            *msdev_cfg ;
+} klmsdev_t ;
+
+#define MAX_FDDI_DEVS 10 /* XXX Is this true */
+
+typedef struct klfddi_s {                          /* FDDI */
+        klinfo_t        fddi_info ;
+        fddi_t          fddi_specific ;
+        klconf_off_t    fddi_devinfo[MAX_FDDI_DEVS] ;
+} klfddi_t ;
+
+typedef struct klmio_s {                          /* MIO */
+        klinfo_t        mio_info ;
+        mio_t           mio_specific   ;
+} klmio_t ;
+
+
+typedef union klcomp_s {
+        klcpu_t         kc_cpu;
+        klhub_t         kc_hub;
+        klmembnk_t      kc_mem;
+        klxbow_t        kc_xbow;
+        klbri_t         kc_bri;
+        klioc3_t        kc_ioc3;
+        klvmeb_t        kc_vmeb;
+        klvmed_t        kc_vmed;
+        klrou_t         kc_rou;
+        klgfx_t         kc_gfx;
+        klscsi_t        kc_scsi;
+        klscdev_t       kc_scsi_dev;
+        klfddi_t        kc_fddi;
+        klmio_t         kc_mio;
+        klmod_serial_num_t kc_snum ;
+} klcomp_t;
+
+typedef union kldev_s {      /* for device structure allocation */
+        klscdev_t       kc_scsi_dev ;
+        klttydev_t      kc_tty_dev ;
+        klenetdev_t     kc_enet_dev ;
+        klkbddev_t      kc_kbd_dev ;
+} kldev_t ;
+
+/* Data structure interface routines. TBD */
+
+/* Include launch info in this file itself? TBD */
+
+/*
+ * TBD - Can the ARCS and device driver related info also be included in the
+ * KLCONFIG area. On the IO4PROM, prom device driver info is part of cfgnode_t
+ * structure, viz private to the IO4prom.
+ */
+
+/*
+ * TBD - Allocation issues.
+ *
+ * Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component,
+ * errinfo and allocate from them, or have a single heap and allocate all
+ * structures from it. Debug is easier in the former method since we can
+ * dump all similar structs in one command, but there will be lots of holes,
+ * in memory and max limits are needed for number of structures.
+ * Another way to make it organized, is to have a union of all components
+ * and allocate a aligned chunk of memory greater than the biggest
+ * component.
+ */
+
+typedef union {
+        lboard_t *lbinfo ;
+} biptr_t ;
+
+
+#define BRI_PER_XBOW 6
+#define PCI_PER_BRI  8
+#define DEV_PER_PCI  16
+
+
+/* Virtual dipswitch values (starting from switch "7"): */
+
+#define VDS_NOGFX               0x8000  /* Don't enable gfx and autoboot */
+#define VDS_NOMP                0x100   /* Don't start slave processors */
+#define VDS_MANUMODE            0x80    /* Manufacturing mode */
+#define VDS_NOARB               0x40    /* No bootmaster arbitration */
+#define VDS_PODMODE             0x20    /* Go straight to POD mode */
+#define VDS_NO_DIAGS            0x10    /* Don't run any diags after BM arb */
+#define VDS_DEFAULTS            0x08    /* Use default environment values */
+#define VDS_NOMEMCLEAR          0x04    /* Don't run mem cfg code */
+#define VDS_2ND_IO4             0x02    /* Boot from the second IO4 */
+#define VDS_DEBUG_PROM          0x01    /* Print PROM debugging messages */
+
+/* external declarations of Linux kernel functions. */
+
+extern lboard_t *find_lboard(lboard_t *start, unsigned char type);
+extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
+extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
+extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int);
+extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
+
+
+extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
+
+#endif /* _ASM_SN_KLCONFIG_H */
diff --git a/arch/mips/include/asm/sn/kldir.h b/arch/mips/include/asm/sn/kldir.h
new file mode 100644
index 000000000000..1327e12e9645
--- /dev/null
+++ b/arch/mips/include/asm/sn/kldir.h
@@ -0,0 +1,217 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
+ *
+ * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_SN_KLDIR_H
+#define _ASM_SN_KLDIR_H
+
+
+/*
+ * The kldir memory area resides at a fixed place in each node's memory and
+ * provides pointers to most other IP27 memory areas.  This allows us to
+ * resize and/or relocate memory areas at a later time without breaking all
+ * firmware and kernels that use them.  Indices in the array are
+ * permanently dedicated to areas listed below.  Some memory areas (marked
+ * below) reside at a permanently fixed location, but are included in the
+ * directory for completeness.
+ */
+
+#define KLDIR_MAGIC             0x434d5f53505f5357
+
+/*
+ * The upper portion of the memory map applies during boot
+ * only and is overwritten by IRIX/SYMMON.
+ *
+ *                                    MEMORY MAP PER NODE
+ *
+ * 0x2000000 (32M)         +-----------------------------------------+
+ *                         |      IO6 BUFFERS FOR FLASH ENET IOC3    |
+ * 0x1F80000 (31.5M)       +-----------------------------------------+
+ *                         |      IO6 TEXT/DATA/BSS/stack            |
+ * 0x1C00000 (30M)         +-----------------------------------------+
+ *                         |      IO6 PROM DEBUG TEXT/DATA/BSS/stack |
+ * 0x0800000 (28M)         +-----------------------------------------+
+ *                         |      IP27 PROM TEXT/DATA/BSS/stack      |
+ * 0x1B00000 (27M)         +-----------------------------------------+
+ *                         |      IP27 CFG                           |
+ * 0x1A00000 (26M)         +-----------------------------------------+
+ *                         |      Graphics PROM                      |
+ * 0x1800000 (24M)         +-----------------------------------------+
+ *                         |      3rd Party PROM drivers             |
+ * 0x1600000 (22M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Free                               |
+ *                         |                                         |
+ *                         +-----------------------------------------+
+ *                         |      UNIX DEBUG Version                 |
+ * 0x190000 (2M--)         +-----------------------------------------+
+ *                         |      SYMMON                             |
+ *                         |      (For UNIX Debug only)              |
+ * 0x34000 (208K)          +-----------------------------------------+
+ *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
+ *                         |      (For UNIX Debug only)              |
+ * 0x25000 (148K)          +-----------------------------------------+
+ *                         |      KLCONFIG - II (temp)               |
+ *                         |                                         |
+ *                         |    ----------------------------         |
+ *                         |                                         |
+ *                         |      UNIX NON-DEBUG Version             |
+ * 0x19000 (100K)          +-----------------------------------------+
+ *
+ *
+ * The lower portion of the memory map contains information that is
+ * permanent and is used by the IP27PROM, IO6PROM and IRIX.
+ *
+ * 0x19000 (100K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      PI Error Spools (32K)              |
+ *                         |                                         |
+ * 0x12000 (72K)           +-----------------------------------------+
+ *                         |      Unused                             |
+ * 0x11c00 (71K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Eframe area              |
+ * 0x11a00 (70.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Eframe area              |
+ * 0x11800 (70K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Register save area       |
+ * 0x11600 (69.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Register save area       |
+ * 0x11400 (69K)           +-----------------------------------------+
+ *                         |      GDA (1k)                           |
+ * 0x11000 (68K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *                         |      kernel/io6prom nmi registers       |
+ * 0x10800  (66k)          +-----------------------------------------+
+ *                         |      cache error eframe                 |
+ * 0x10400 (65K)           +-----------------------------------------+
+ *                         |      Exception Handlers (UALIAS copy)   |
+ * 0x10000 (64K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      KLCONFIG - I (permanent) (48K)     |
+ *                         |                                         |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x4000 (16K)            +-----------------------------------------+
+ *                         |      NMI Handler (Protected Page)       |
+ * 0x3000 (12K)            +-----------------------------------------+
+ *                         |      ARCS PVECTORS (master node only)   |
+ * 0x2c00 (11K)            +-----------------------------------------+
+ *                         |      ARCS TVECTORS (master node only)   |
+ * 0x2800 (10K)            +-----------------------------------------+
+ *                         |      LAUNCH [NUM_CPU]                   |
+ * 0x2400 (9K)             +-----------------------------------------+
+ *                         |      Low memory directory (KLDIR)       |
+ * 0x2000 (8K)             +-----------------------------------------+
+ *                         |      ARCS SPB (1K)                      |
+ * 0x1000 (4K)             +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *                         |      kernel/io6prom nmi registers       |
+ * 0x800  (2k)             +-----------------------------------------+
+ *                         |      cache error eframe                 |
+ * 0x400 (1K)              +-----------------------------------------+
+ *                         |      Exception Handlers                 |
+ * 0x0   (0K)              +-----------------------------------------+
+ */
+
+#ifdef __ASSEMBLY__
+#define KLDIR_OFF_MAGIC                 0x00
+#define KLDIR_OFF_OFFSET                0x08
+#define KLDIR_OFF_POINTER               0x10
+#define KLDIR_OFF_SIZE                  0x18
+#define KLDIR_OFF_COUNT                 0x20
+#define KLDIR_OFF_STRIDE                0x28
+#endif /* __ASSEMBLY__ */
+
+/*
+ * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
+ * we define here.  Since it's set up in the prom.  We can't redefine it later
+ * and expect more space to be allocated.  The way to find out the true size
+ * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
+ * for a particular node.
+ */
+#define SYMMON_STACK_SIZE               0x8000
+
+#if defined(PROM)
+
+/*
+ * These defines are prom version dependent.  No code other than the IP27
+ * prom should attempt to use these values.
+ */
+#define IP27_LAUNCH_OFFSET              0x2400
+#define IP27_LAUNCH_SIZE                0x400
+#define IP27_LAUNCH_COUNT               2
+#define IP27_LAUNCH_STRIDE              0x200
+
+#define IP27_KLCONFIG_OFFSET            0x4000
+#define IP27_KLCONFIG_SIZE              0xc000
+#define IP27_KLCONFIG_COUNT             1
+#define IP27_KLCONFIG_STRIDE            0
+
+#define IP27_NMI_OFFSET                 0x3000
+#define IP27_NMI_SIZE                   0x40
+#define IP27_NMI_COUNT                  2
+#define IP27_NMI_STRIDE                 0x40
+
+#define IP27_PI_ERROR_OFFSET            0x12000
+#define IP27_PI_ERROR_SIZE              0x4000
+#define IP27_PI_ERROR_COUNT             1
+#define IP27_PI_ERROR_STRIDE            0
+
+#define IP27_SYMMON_STK_OFFSET          0x25000
+#define IP27_SYMMON_STK_SIZE            0xe000
+#define IP27_SYMMON_STK_COUNT           2
+/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
+#define IP27_SYMMON_STK_STRIDE          0x7000
+
+#define IP27_FREEMEM_OFFSET             0x19000
+#define IP27_FREEMEM_SIZE               -1
+#define IP27_FREEMEM_COUNT              1
+#define IP27_FREEMEM_STRIDE             0
+
+#endif /* PROM */
+/*
+ * There will be only one of these in a partition so the IO6 must set it up.
+ */
+#define IO6_GDA_OFFSET                  0x11000
+#define IO6_GDA_SIZE                    0x400
+#define IO6_GDA_COUNT                   1
+#define IO6_GDA_STRIDE                  0
+
+/*
+ * save area of kernel nmi regs in the prom format
+ */
+#define IP27_NMI_KREGS_OFFSET           0x11400
+#define IP27_NMI_KREGS_CPU_SIZE         0x200
+/*
+ * save area of kernel nmi regs in eframe format
+ */
+#define IP27_NMI_EFRAME_OFFSET          0x11800
+#define IP27_NMI_EFRAME_SIZE            0x200
+
+#define KLDIR_ENT_SIZE                  0x40
+#define KLDIR_MAX_ENTRIES               (0x400 / 0x40)
+
+#ifndef __ASSEMBLY__
+typedef struct kldir_ent_s {
+        u64             magic;          /* Indicates validity of entry      */
+        off_t           offset;         /* Offset from start of node space  */
+        unsigned long   pointer;        /* Pointer to area in some cases    */
+        size_t          size;           /* Size in bytes                    */
+        u64             count;          /* Repeat count if array, 1 if not  */
+        size_t          stride;         /* Stride if array, 0 if not        */
+        char            rsvd[16];       /* Pad entry to 0x40 bytes          */
+        /* NOTE: These 16 bytes are used in the Partition KLDIR
+           entry to store partition info. Refer to klpart.h for this. */
+} kldir_ent_t;
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_SN_KLDIR_H */
diff --git a/arch/mips/include/asm/sn/klkernvars.h b/arch/mips/include/asm/sn/klkernvars.h
new file mode 100644
index 000000000000..5de4c5e8ab30
--- /dev/null
+++ b/arch/mips/include/asm/sn/klkernvars.h
@@ -0,0 +1,29 @@
+/*
+ * File ported from IRIX to Linux by Kanoj Sarcar, 06/08/00.
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_KLKERNVARS_H
+#define __ASM_SN_KLKERNVARS_H
+
+#define KV_MAGIC_OFFSET         0x0
+#define KV_RO_NASID_OFFSET      0x4
+#define KV_RW_NASID_OFFSET      0x6
+
+#define KV_MAGIC                0x5f4b565f
+
+#ifndef __ASSEMBLY__
+
+#include <asm/sn/types.h>
+
+typedef struct kern_vars_s {
+        int             kv_magic;
+        nasid_t         kv_ro_nasid;
+        nasid_t         kv_rw_nasid;
+        unsigned long   kv_ro_baseaddr;
+        unsigned long   kv_rw_baseaddr;
+} kern_vars_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_SN_KLKERNVARS_H */
+
diff --git a/arch/mips/include/asm/sn/launch.h b/arch/mips/include/asm/sn/launch.h
new file mode 100644
index 000000000000..b7c2226312c6
--- /dev/null
+++ b/arch/mips/include/asm/sn/launch.h
@@ -0,0 +1,106 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 by Colin Ngam
+ */
+#ifndef _ASM_SN_LAUNCH_H
+#define _ASM_SN_LAUNCH_H
+
+#include <asm/sn/types.h>
+#include <asm/sn/addrs.h>
+
+/*
+ * The launch data structure resides at a fixed place in each node's memory
+ * and is used to communicate between the master processor and the slave
+ * processors.
+ *
+ * The master stores launch parameters in the launch structure
+ * corresponding to a target processor that is in a slave loop, then sends
+ * an interrupt to the slave processor.  The slave calls the desired
+ * function, then returns to the slave loop.  The master may poll or wait
+ * for the slaves to finish.
+ *
+ * There is an array of launch structures, one per CPU on the node.  One
+ * interrupt level is used per local CPU.
+ */
+
+#define LAUNCH_MAGIC            0xaddbead2addbead3
+#ifdef CONFIG_SGI_IP27
+#define LAUNCH_SIZEOF           0x100
+#define LAUNCH_PADSZ            0xa0
+#endif
+
+#define LAUNCH_OFF_MAGIC        0x00    /* Struct offsets for assembly      */
+#define LAUNCH_OFF_BUSY         0x08
+#define LAUNCH_OFF_CALL         0x10
+#define LAUNCH_OFF_CALLC        0x18
+#define LAUNCH_OFF_CALLPARM     0x20
+#define LAUNCH_OFF_STACK        0x28
+#define LAUNCH_OFF_GP           0x30
+#define LAUNCH_OFF_BEVUTLB      0x38
+#define LAUNCH_OFF_BEVNORMAL    0x40
+#define LAUNCH_OFF_BEVECC       0x48
+
+#define LAUNCH_STATE_DONE       0       /* Return value of LAUNCH_POLL      */
+#define LAUNCH_STATE_SENT       1
+#define LAUNCH_STATE_RECD       2
+
+/*
+ * The launch routine is called only if the complement address is correct.
+ *
+ * Before control is transferred to a routine, the complement address
+ * is zeroed (invalidated) to prevent an accidental call from a spurious
+ * interrupt.
+ *
+ * The slave_launch routine turns on the BUSY flag, and the slave loop
+ * clears the BUSY flag after control is returned to it.
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef int launch_state_t;
+typedef void (*launch_proc_t)(u64 call_parm);
+
+typedef struct launch_s {
+        volatile u64            magic;  /* Magic number                     */
+        volatile u64            busy;   /* Slave currently active           */
+        volatile launch_proc_t  call_addr;      /* Func. for slave to call  */
+        volatile u64            call_addr_c;    /* 1's complement of call_addr*/
+        volatile u64            call_parm;      /* Single parm passed to call*/
+        volatile void *stack_addr;      /* Stack pointer for slave function */
+        volatile void *gp_addr;         /* Global pointer for slave func.   */
+        volatile char           *bevutlb;/* Address of bev utlb ex handler   */
+        volatile char           *bevnormal;/*Address of bev normal ex handler */
+        volatile char           *bevecc;/* Address of bev cache err handler */
+        volatile char           pad[160];       /* Pad to LAUNCH_SIZEOF     */
+} launch_t;
+
+/*
+ * PROM entry points for launch routines are determined by IPxxprom/start.s
+ */
+
+#define LAUNCH_SLAVE    (*(void (*)(int nasid, int cpu, \
+                                    launch_proc_t call_addr, \
+                                    u64 call_parm, \
+                                    void *stack_addr, \
+                                    void *gp_addr)) \
+                         IP27PROM_LAUNCHSLAVE)
+
+#define LAUNCH_WAIT     (*(void (*)(int nasid, int cpu, int timeout_msec)) \
+                         IP27PROM_WAITSLAVE)
+
+#define LAUNCH_POLL     (*(launch_state_t (*)(int nasid, int cpu)) \
+                         IP27PROM_POLLSLAVE)
+
+#define LAUNCH_LOOP     (*(void (*)(void)) \
+                         IP27PROM_SLAVELOOP)
+
+#define LAUNCH_FLASH    (*(void (*)(void)) \
+                         IP27PROM_FLASHLEDS)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_SN_LAUNCH_H */
diff --git a/arch/mips/include/asm/sn/mapped_kernel.h b/arch/mips/include/asm/sn/mapped_kernel.h
new file mode 100644
index 000000000000..721496a0bb92
--- /dev/null
+++ b/arch/mips/include/asm/sn/mapped_kernel.h
@@ -0,0 +1,54 @@
+/*
+ * File created by Kanoj Sarcar 06/06/00.
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_MAPPED_KERNEL_H
+#define __ASM_SN_MAPPED_KERNEL_H
+
+#include <linux/mmzone.h>
+
+/*
+ * Note on how mapped kernels work: the text and data section is
+ * compiled at cksseg segment (LOADADDR = 0xc001c000), and the
+ * init/setup/data section gets a 16M virtual address bump in the
+ * ld.script file (so that tlblo0 and tlblo1 maps the sections).
+ * The vmlinux.64 section addresses are put in the xkseg range
+ * using the change-addresses makefile option. Use elfdump -of
+ * on IRIX to see where the sections go. The Origin loader loads
+ * the two sections contiguously in physical memory. The loader
+ * sets the entry point into kernel_entry using a xkphys address,
+ * but instead of using 0xa800000001160000, it uses the address
+ * 0xa800000000160000, which is where it physically loaded that
+ * code. So no jumps can be done before we have switched to using
+ * cksseg addresses.
+ */
+#include <asm/addrspace.h>
+
+#define REP_BASE        CAC_BASE
+
+#ifdef CONFIG_MAPPED_KERNEL
+
+#define MAPPED_ADDR_RO_TO_PHYS(x)       (x - REP_BASE)
+#define MAPPED_ADDR_RW_TO_PHYS(x)       (x - REP_BASE - 16777216)
+
+#define MAPPED_KERN_RO_PHYSBASE(n) (hub_data(n)->kern_vars.kv_ro_baseaddr)
+#define MAPPED_KERN_RW_PHYSBASE(n) (hub_data(n)->kern_vars.kv_rw_baseaddr)
+
+#define MAPPED_KERN_RO_TO_PHYS(x) \
+                                ((unsigned long)MAPPED_ADDR_RO_TO_PHYS(x) | \
+                                MAPPED_KERN_RO_PHYSBASE(get_compact_nodeid()))
+#define MAPPED_KERN_RW_TO_PHYS(x) \
+                                ((unsigned long)MAPPED_ADDR_RW_TO_PHYS(x) | \
+                                MAPPED_KERN_RW_PHYSBASE(get_compact_nodeid()))
+
+#else /* CONFIG_MAPPED_KERNEL */
+
+#define MAPPED_KERN_RO_TO_PHYS(x)       (x - REP_BASE)
+#define MAPPED_KERN_RW_TO_PHYS(x)       (x - REP_BASE)
+
+#endif /* CONFIG_MAPPED_KERNEL */
+
+#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
+#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
+
+#endif /* __ASM_SN_MAPPED_KERNEL_H  */
diff --git a/arch/mips/include/asm/sn/nmi.h b/arch/mips/include/asm/sn/nmi.h
new file mode 100644
index 000000000000..6b7b0b5f3729
--- /dev/null
+++ b/arch/mips/include/asm/sn/nmi.h
@@ -0,0 +1,125 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_SN_NMI_H
+#define __ASM_SN_NMI_H
+
+#ident "$Revision: 1.5 $"
+
+#include <asm/sn/addrs.h>
+
+/*
+ * The launch data structure resides at a fixed place in each node's memory
+ * and is used to communicate between the master processor and the slave
+ * processors.
+ *
+ * The master stores launch parameters in the launch structure
+ * corresponding to a target processor that is in a slave loop, then sends
+ * an interrupt to the slave processor.  The slave calls the desired
+ * function, followed by an optional rendezvous function, then returns to
+ * the slave loop.  The master does not wait for the slaves before
+ * returning.
+ *
+ * There is an array of launch structures, one per CPU on the node.  One
+ * interrupt level is used per CPU.
+ */
+
+#define NMI_MAGIC               0x48414d4d455201
+#define NMI_SIZEOF              0x40
+
+#define NMI_OFF_MAGIC           0x00    /* Struct offsets for assembly      */
+#define NMI_OFF_FLAGS           0x08
+#define NMI_OFF_CALL            0x10
+#define NMI_OFF_CALLC           0x18
+#define NMI_OFF_CALLPARM        0x20
+#define NMI_OFF_GMASTER         0x28
+
+/*
+ * The NMI routine is called only if the complement address is
+ * correct.
+ *
+ * Before control is transferred to a routine, the complement address
+ * is zeroed (invalidated) to prevent an accidental call from a spurious
+ * interrupt.
+ *
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef struct nmi_s {
+        volatile unsigned long   magic;         /* Magic number */
+        volatile unsigned long   flags;         /* Combination of flags above */
+        volatile void *call_addr;       /* Routine for slave to call        */
+        volatile void *call_addr_c;     /* 1's complement of address        */
+        volatile void *call_parm;       /* Single parm passed to call       */
+        volatile unsigned long   gmaster;       /* Flag true only on global master*/
+} nmi_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/* Following definitions are needed both in the prom & the kernel
+ * to identify the format of the nmi cpu register save area in the
+ * low memory on each node.
+ */
+#ifndef __ASSEMBLY__
+
+struct reg_struct {
+        unsigned long   gpr[32];
+        unsigned long   sr;
+        unsigned long   cause;
+        unsigned long   epc;
+        unsigned long   badva;
+        unsigned long   error_epc;
+        unsigned long   cache_err;
+        unsigned long   nmi_sr;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+/* These are the assembly language offsets into the reg_struct structure */
+
+#define R0_OFF          0x0
+#define R1_OFF          0x8
+#define R2_OFF          0x10
+#define R3_OFF          0x18
+#define R4_OFF          0x20
+#define R5_OFF          0x28
+#define R6_OFF          0x30
+#define R7_OFF          0x38
+#define R8_OFF          0x40
+#define R9_OFF          0x48
+#define R10_OFF         0x50
+#define R11_OFF         0x58
+#define R12_OFF         0x60
+#define R13_OFF         0x68
+#define R14_OFF         0x70
+#define R15_OFF         0x78
+#define R16_OFF         0x80
+#define R17_OFF         0x88
+#define R18_OFF         0x90
+#define R19_OFF         0x98
+#define R20_OFF         0xa0
+#define R21_OFF         0xa8
+#define R22_OFF         0xb0
+#define R23_OFF         0xb8
+#define R24_OFF         0xc0
+#define R25_OFF         0xc8
+#define R26_OFF         0xd0
+#define R27_OFF         0xd8
+#define R28_OFF         0xe0
+#define R29_OFF         0xe8
+#define R30_OFF         0xf0
+#define R31_OFF         0xf8
+#define SR_OFF          0x100
+#define CAUSE_OFF       0x108
+#define EPC_OFF         0x110
+#define BADVA_OFF       0x118
+#define ERROR_EPC_OFF   0x120
+#define CACHE_ERR_OFF   0x128
+#define NMISR_OFF       0x130
+
+#endif /* __ASM_SN_NMI_H */
diff --git a/arch/mips/include/asm/sn/sn0/addrs.h b/arch/mips/include/asm/sn/sn0/addrs.h
new file mode 100644
index 000000000000..b06190093bbc
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/addrs.h
@@ -0,0 +1,288 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_ADDRS_H
+#define _ASM_SN_SN0_ADDRS_H
+
+
+/*
+ * SN0 (on a T5) Address map
+ *
+ * This file contains a set of definitions and macros which are used
+ * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
+ * and UNCAC) used by the SN0 architecture.  It also contains addresses
+ * for "major" statically locatable PROM/Kernel data structures, such as
+ * the partition table, the configuration data structure, etc.
+ * We make an implicit assumption that the processor using this file
+ * follows the R10K's provisions for specifying uncached attributes;
+ * should this change, the base registers may very well become processor-
+ * dependent.
+ *
+ * For more information on the address spaces, see the "Local Resources"
+ * chapter of the Hub specification.
+ *
+ * NOTE: This header file is included both by C and by assembler source
+ *       files.  Please bracket any language-dependent definitions
+ *       appropriately.
+ */
+
+/*
+ * Some of the macros here need to be casted to appropriate types when used
+ * from C.  They definitely must not be casted from assembly language so we
+ * use some new ANSI preprocessor stuff to paste these on where needed.
+ */
+
+/*
+ * The following couple of definitions will eventually need to be variables,
+ * since the amount of address space assigned to each node depends on
+ * whether the system is running in N-mode (more nodes with less memory)
+ * or M-mode (fewer nodes with more memory).  We expect that it will
+ * be a while before we need to make this decision dynamically, though,
+ * so for now we just use defines bracketed by an ifdef.
+ */
+
+#ifdef CONFIG_SGI_SN_N_MODE
+
+#define NODE_SIZE_BITS          31
+#define BWIN_SIZE_BITS          28
+
+#define NASID_BITS              9
+#define NASID_BITMASK           (0x1ffLL)
+#define NASID_SHFT              31
+#define NASID_META_BITS         5
+#define NASID_LOCAL_BITS        4
+
+#define BDDIR_UPPER_MASK        (UINT64_CAST 0x7ffff << 10)
+#define BDECC_UPPER_MASK        (UINT64_CAST 0x3ffffff << 3)
+
+#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
+
+#define NODE_SIZE_BITS          32
+#define BWIN_SIZE_BITS          29
+
+#define NASID_BITMASK           (0xffLL)
+#define NASID_BITS              8
+#define NASID_SHFT              32
+#define NASID_META_BITS         4
+#define NASID_LOCAL_BITS        4
+
+#define BDDIR_UPPER_MASK        (UINT64_CAST 0xfffff << 10)
+#define BDECC_UPPER_MASK        (UINT64_CAST 0x7ffffff << 3)
+
+#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
+
+#define NODE_ADDRSPACE_SIZE     (UINT64_CAST 1 << NODE_SIZE_BITS)
+
+#define NASID_MASK              (UINT64_CAST NASID_BITMASK << NASID_SHFT)
+#define NASID_GET(_pa)          (int) ((UINT64_CAST (_pa) >>            \
+                                        NASID_SHFT) & NASID_BITMASK)
+
+#if !defined(__ASSEMBLY__)
+
+#define NODE_SWIN_BASE(nasid, widget)                                   \
+        ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)          \
+        : RAW_NODE_SWIN_BASE(nasid, widget))
+#else /* __ASSEMBLY__ */
+#define NODE_SWIN_BASE(nasid, widget) \
+     (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define BWIN_INDEX_BITS         3
+#define BWIN_SIZE               (UINT64_CAST 1 << BWIN_SIZE_BITS)
+#define BWIN_SIZEMASK           (BWIN_SIZE - 1)
+#define BWIN_WIDGET_MASK        0x7
+#define NODE_BWIN_BASE0(nasid)  (NODE_IO_BASE(nasid) + BWIN_SIZE)
+#define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
+                        (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
+
+#define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
+#define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+/*
+ * Verify if addr belongs to large window address of node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+
+#define NODE_BWIN_ADDR(nasid, addr)     \
+                (((addr) >= NODE_BWIN_BASE0(nasid)) && \
+                 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
+                                BWIN_SIZE)))
+
+/*
+ * The following define the major position-independent aliases used
+ * in SN0.
+ *      CALIAS -- Varies in size, points to the first n bytes of memory
+ *                      on the reader's node.
+ */
+
+#define CALIAS_BASE             CAC_BASE
+
+
+
+#define BRIDGE_REG_PTR(_base, _off)     ((volatile bridgereg_t *) \
+        ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
+
+#define SN0_WIDGET_BASE(_nasid, _wid)   (NODE_SWIN_BASE((_nasid), (_wid)))
+
+/* Turn on sable logging for the processors whose bits are set. */
+#define SABLE_LOG_TRIGGER(_map)
+
+#ifndef __ASSEMBLY__
+#define KERN_NMI_ADDR(nasid, slice)                                     \
+                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +      \
+                                  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
+#endif /* !__ASSEMBLY__ */
+
+#ifdef PROM
+
+#define MISC_PROM_BASE          PHYS_TO_K0(0x01300000)
+#define MISC_PROM_SIZE          0x200000
+
+#define DIAG_BASE               PHYS_TO_K0(0x01500000)
+#define DIAG_SIZE               0x300000
+
+#define ROUTE_BASE              PHYS_TO_K0(0x01800000)
+#define ROUTE_SIZE              0x200000
+
+#define IP27PROM_FLASH_HDR      PHYS_TO_K0(0x01300000)
+#define IP27PROM_FLASH_DATA     PHYS_TO_K0(0x01301000)
+#define IP27PROM_CORP_MAX       32
+#define IP27PROM_CORP           PHYS_TO_K0(0x01800000)
+#define IP27PROM_CORP_SIZE      0x10000
+#define IP27PROM_CORP_STK       PHYS_TO_K0(0x01810000)
+#define IP27PROM_CORP_STKSIZE   0x2000
+#define IP27PROM_DECOMP_BUF     PHYS_TO_K0(0x01900000)
+#define IP27PROM_DECOMP_SIZE    0xfff00
+
+#define IP27PROM_BASE           PHYS_TO_K0(0x01a00000)
+#define IP27PROM_BASE_MAPPED    (UNCAC_BASE | 0x1fc00000)
+#define IP27PROM_SIZE_MAX       0x100000
+
+#define IP27PROM_PCFG           PHYS_TO_K0(0x01b00000)
+#define IP27PROM_PCFG_SIZE      0xd0000
+#define IP27PROM_ERRDMP         PHYS_TO_K1(0x01bd0000)
+#define IP27PROM_ERRDMP_SIZE    0xf000
+
+#define IP27PROM_INIT_START     PHYS_TO_K1(0x01bd0000)
+#define IP27PROM_CONSOLE        PHYS_TO_K1(0x01bdf000)
+#define IP27PROM_CONSOLE_SIZE   0x200
+#define IP27PROM_NETUART        PHYS_TO_K1(0x01bdf200)
+#define IP27PROM_NETUART_SIZE   0x100
+#define IP27PROM_UNUSED1        PHYS_TO_K1(0x01bdf300)
+#define IP27PROM_UNUSED1_SIZE   0x500
+#define IP27PROM_ELSC_BASE_A    PHYS_TO_K0(0x01bdf800)
+#define IP27PROM_ELSC_BASE_B    PHYS_TO_K0(0x01bdfc00)
+#define IP27PROM_STACK_A        PHYS_TO_K0(0x01be0000)
+#define IP27PROM_STACK_B        PHYS_TO_K0(0x01bf0000)
+#define IP27PROM_STACK_SHFT     16
+#define IP27PROM_STACK_SIZE     (1 << IP27PROM_STACK_SHFT)
+#define IP27PROM_INIT_END       PHYS_TO_K0(0x01c00000)
+
+#define SLAVESTACK_BASE         PHYS_TO_K0(0x01580000)
+#define SLAVESTACK_SIZE         0x40000
+
+#define ENETBUFS_BASE           PHYS_TO_K0(0x01f80000)
+#define ENETBUFS_SIZE           0x20000
+
+#define IO6PROM_BASE            PHYS_TO_K0(0x01c00000)
+#define IO6PROM_SIZE            0x400000
+#define IO6PROM_BASE_MAPPED     (UNCAC_BASE | 0x11c00000)
+#define IO6DPROM_BASE           PHYS_TO_K0(0x01c00000)
+#define IO6DPROM_SIZE           0x200000
+
+#define NODEBUGUNIX_ADDR        PHYS_TO_K0(0x00019000)
+#define DEBUGUNIX_ADDR          PHYS_TO_K0(0x00100000)
+
+#define IP27PROM_INT_LAUNCH     10      /* and 11 */
+#define IP27PROM_INT_NETUART    12      /* through 17 */
+
+#endif /* PROM */
+
+/*
+ * needed by symmon so it needs to be outside #if PROM
+ */
+#define IP27PROM_ELSC_SHFT      10
+#define IP27PROM_ELSC_SIZE      (1 << IP27PROM_ELSC_SHFT)
+
+/*
+ * This address is used by IO6PROM to build MemoryDescriptors of
+ * free memory. This address is important since unix gets loaded
+ * at this address, and this memory has to be FREE if unix is to
+ * be loaded.
+ */
+
+#define FREEMEM_BASE            PHYS_TO_K0(0x2000000)
+
+#define IO6PROM_STACK_SHFT      14      /* stack per cpu */
+#define IO6PROM_STACK_SIZE      (1 << IO6PROM_STACK_SHFT)
+
+/*
+ * IP27 PROM vectors
+ */
+
+#define IP27PROM_ENTRY          PHYS_TO_COMPATK1(0x1fc00000)
+#define IP27PROM_RESTART        PHYS_TO_COMPATK1(0x1fc00008)
+#define IP27PROM_SLAVELOOP      PHYS_TO_COMPATK1(0x1fc00010)
+#define IP27PROM_PODMODE        PHYS_TO_COMPATK1(0x1fc00018)
+#define IP27PROM_IOC3UARTPOD    PHYS_TO_COMPATK1(0x1fc00020)
+#define IP27PROM_FLASHLEDS      PHYS_TO_COMPATK1(0x1fc00028)
+#define IP27PROM_REPOD          PHYS_TO_COMPATK1(0x1fc00030)
+#define IP27PROM_LAUNCHSLAVE    PHYS_TO_COMPATK1(0x1fc00038)
+#define IP27PROM_WAITSLAVE      PHYS_TO_COMPATK1(0x1fc00040)
+#define IP27PROM_POLLSLAVE      PHYS_TO_COMPATK1(0x1fc00048)
+
+#define KL_UART_BASE    LOCAL_HUB_ADDR(MD_UREG0_0)      /* base of UART regs */
+#define KL_UART_CMD     LOCAL_HUB_ADDR(MD_UREG0_0)      /* UART command reg */
+#define KL_UART_DATA    LOCAL_HUB_ADDR(MD_UREG0_1)      /* UART data reg */
+#define KL_I2C_REG      MD_UREG0_0                      /* I2C reg */
+
+#ifndef __ASSEMBLY__
+
+/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
+ * CACHE_ERR_SP_PTR could either contain an address to the stack, or
+ * the stack could start at CACHE_ERR_SP_PTR
+ */
+#if defined(HUB_ERR_STS_WAR)
+#define CACHE_ERR_EFRAME        0x480
+#else /* HUB_ERR_STS_WAR */
+#define CACHE_ERR_EFRAME        0x400
+#endif /* HUB_ERR_STS_WAR */
+
+#define CACHE_ERR_ECCFRAME      (CACHE_ERR_EFRAME + EF_SIZE)
+#define CACHE_ERR_SP_PTR        (0x1000 - 32)   /* why -32? TBD */
+#define CACHE_ERR_IBASE_PTR     (0x1000 - 40)
+#define CACHE_ERR_SP            (CACHE_ERR_SP_PTR - 16)
+#define CACHE_ERR_AREA_SIZE     (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
+
+#endif  /* !__ASSEMBLY__ */
+
+#define _ARCSPROM
+
+#if defined(HUB_ERR_STS_WAR)
+
+#define ERR_STS_WAR_REGISTER    IIO_IIBUSERR
+#define ERR_STS_WAR_ADDR        LOCAL_HUB_ADDR(IIO_IIBUSERR)
+#define ERR_STS_WAR_PHYSADDR    TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
+                                /* Used to match addr in error reg. */
+#define OLD_ERR_STS_WAR_OFFSET  ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
+
+#endif /* HUB_ERR_STS_WAR */
+
+#endif /* _ASM_SN_SN0_ADDRS_H */
diff --git a/arch/mips/include/asm/sn/sn0/arch.h b/arch/mips/include/asm/sn/sn0/arch.h
new file mode 100644
index 000000000000..f734f2007f24
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/arch.h
@@ -0,0 +1,72 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI IP27 specific setup.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_SN0_ARCH_H
+#define _ASM_SN_SN0_ARCH_H
+
+
+#ifndef SN0XXL  /* 128 cpu SMP max */
+/*
+ * This is the maximum number of nodes that can be part of a kernel.
+ * Effectively, it's the maximum number of compact node ids (cnodeid_t).
+ */
+#define MAX_COMPACT_NODES       64
+
+/*
+ * MAXCPUS refers to the maximum number of CPUs in a single kernel.
+ * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
+ */
+#define MAXCPUS                 128
+
+#else /* SN0XXL system */
+
+#define MAX_COMPACT_NODES       128
+#define MAXCPUS                 256
+
+#endif /* SN0XXL */
+
+/*
+ * This is the maximum number of NASIDS that can be present in a system.
+ * (Highest NASID plus one.)
+ */
+#define MAX_NASIDS              256
+
+/*
+ * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
+ */
+#define MAX_REGIONS             64
+#define MAX_NONPREMIUM_REGIONS  16
+#define MAX_PREMIUM_REGIONS     MAX_REGIONS
+
+/*
+ * MAX_PARITIONS refers to the maximum number of logically defined
+ * partitions the system can support.
+ */
+#define MAX_PARTITIONS          MAX_REGIONS
+
+#define NASID_MASK_BYTES        ((MAX_NASIDS + 7) / 8)
+
+/*
+ * Slot constants for SN0
+ */
+#ifdef CONFIG_SGI_SN_N_MODE
+#define MAX_MEM_SLOTS   16                      /* max slots per node */
+#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
+#define MAX_MEM_SLOTS   32                      /* max slots per node */
+#endif /* CONFIG_SGI_SN_M_MODE */
+
+#define SLOT_SHIFT              (27)
+#define SLOT_MIN_MEM_SIZE       (32*1024*1024)
+
+#define CPUS_PER_NODE           2       /* CPUs on a single hub */
+#define CPUS_PER_NODE_SHFT      1       /* Bits to shift in the node number */
+#define CPUS_PER_SUBNODE        2       /* CPUs on a single hub PI */
+
+#endif /* _ASM_SN_SN0_ARCH_H */
diff --git a/arch/mips/include/asm/sn/sn0/hub.h b/arch/mips/include/asm/sn/sn0/hub.h
new file mode 100644
index 000000000000..3e228f8e7969
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hub.h
@@ -0,0 +1,40 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUB_H
+#define _ASM_SN_SN0_HUB_H
+
+/* The secret password; used to release protection */
+#define HUB_PASSWORD            0x53474972756c6573ull
+
+#define CHIPID_HUB              0
+#define CHIPID_ROUTER           1
+
+#define HUB_REV_1_0             1
+#define HUB_REV_2_0             2
+#define HUB_REV_2_1             3
+#define HUB_REV_2_2             4
+#define HUB_REV_2_3             5
+#define HUB_REV_2_4             6
+
+#define MAX_HUB_PATH            80
+
+#include <asm/sn/sn0/addrs.h>
+#include <asm/sn/sn0/hubpi.h>
+#include <asm/sn/sn0/hubmd.h>
+#include <asm/sn/sn0/hubio.h>
+#include <asm/sn/sn0/hubni.h>
+//#include <asm/sn/sn0/hubcore.h>
+
+/* Translation of uncached attributes */
+#define UATTR_HSPEC     0
+#define UATTR_IO        1
+#define UATTR_MSPEC     2
+#define UATTR_UNCAC     3
+
+#endif /* _ASM_SN_SN0_HUB_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
new file mode 100644
index 000000000000..d0c29d4de084
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -0,0 +1,972 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SGI_SN_SN0_HUBIO_H
+#define _ASM_SGI_SN_SN0_HUBIO_H
+
+/*
+ * Hub I/O interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ * In general, the longer software name should be used when available.
+ */
+
+/*
+ * Slightly friendlier names for some common registers.
+ * The hardware definitions follow.
+ */
+#define IIO_WIDGET              IIO_WID      /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
+#define IIO_WIDGET_TOUT         IIO_WRTO     /* Widget request timeout */
+#define IIO_WIDGET_FLUSH        IIO_WTFR     /* Widget target flush */
+#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
+#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_BTE_CRB_CNT         IIO_IBCN     /* IO BTE CRB count */
+
+#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1   IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT             0
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+
+/*
+ * The following definitions use the names defined in the IO interface
+ * document for ease of reference.  When possible, software should
+ * generally use the longer but clearer names defined above.
+ */
+
+#define IIO_BASE        0x400000
+#define IIO_BASE_BTE0   0x410000
+#define IIO_BASE_BTE1   0x420000
+#define IIO_BASE_PERF   0x430000
+#define IIO_PERF_CNT    0x430008
+
+#define IO_PERF_SETS    32
+
+#define IIO_WID         0x400000        /* Widget identification */
+#define IIO_WSTAT       0x400008        /* Widget status */
+#define IIO_WCR         0x400020        /* Widget control */
+
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  (0x7F)
+#define IIO_WSTAT_TXRETRY_SHFT  (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                          IIO_WSTAT_TXRETRY_MASK)
+
+#define IIO_ILAPR       0x400100        /* Local Access Protection */
+#define IIO_ILAPO       0x400108        /* Protection override */
+#define IIO_IOWA        0x400110        /* outbound widget access */
+#define IIO_IIWA        0x400118        /* inbound widget access */
+#define IIO_IIDEM       0x400120        /* Inbound Device Error Mask */
+#define IIO_ILCSR       0x400128        /* LLP control and status */
+#define IIO_ILLR        0x400130        /* LLP Log */
+#define IIO_IIDSR       0x400138        /* Interrupt destination */
+
+#define IIO_IIBUSERR    0x1400208       /* Reads here cause a bus error. */
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT    28
+#define IIO_IIDSR_SENT_MASK     0x10000000
+#define IIO_IIDSR_ENB_SHIFT     24
+#define IIO_IIDSR_ENB_MASK      0x01000000
+#define IIO_IIDSR_NODE_SHIFT    8
+#define IIO_IIDSR_NODE_MASK     0x0000ff00
+#define IIO_IIDSR_LVL_SHIFT     0
+#define IIO_IIDSR_LVL_MASK      0x0000003f
+
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_0      0x400140        /* gfx node/widget register 0 */
+#define IIO_IGFX_1      0x400148        /* gfx node/widget register 1 */
+#define IIO_IGFX_W_NUM_BITS     4       /* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK     ((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT    0
+#define IIO_IGFX_N_NUM_BITS     9       /* size of node num field */
+#define IIO_IGFX_N_NUM_MASK     ((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT    4
+#define IIO_IGFX_P_NUM_BITS     1       /* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK     ((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT    16
+#define IIO_IGFX_VLD_BITS       1       /* size of valid field */
+#define IIO_IGFX_VLD_MASK       ((1<<IIO_IGFX_VLD_BITS)-1)
+#define IIO_IGFX_VLD_SHIFT      20
+#define IIO_IGFX_INIT(widget, node, cpu, valid)                         (\
+        (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
+        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
+        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
+        (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)         )
+
+/* Scratch registers (not all bits available) */
+#define IIO_SCRATCH_REG0        0x400150
+#define IIO_SCRATCH_REG1        0x400158
+#define IIO_SCRATCH_MASK        0x0000000f00f11fff
+
+#define IIO_SCRATCH_BIT0_0      0x0000000800000000
+#define IIO_SCRATCH_BIT0_1      0x0000000400000000
+#define IIO_SCRATCH_BIT0_2      0x0000000200000000
+#define IIO_SCRATCH_BIT0_3      0x0000000100000000
+#define IIO_SCRATCH_BIT0_4      0x0000000000800000
+#define IIO_SCRATCH_BIT0_5      0x0000000000400000
+#define IIO_SCRATCH_BIT0_6      0x0000000000200000
+#define IIO_SCRATCH_BIT0_7      0x0000000000100000
+#define IIO_SCRATCH_BIT0_8      0x0000000000010000
+#define IIO_SCRATCH_BIT0_9      0x0000000000001000
+#define IIO_SCRATCH_BIT0_R      0x0000000000000fff
+
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the hub, we've
+ * redefined big window 7 as small window 0.
+ */
+#define HUB_NUM_BIG_WINDOW      IIO_NUM_ITTES - 1
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+
+#define ILCSR_WARM_RESET        0x100
+/*
+ * The IO LLP control status register and widget control register
+ */
+#ifndef __ASSEMBLY__
+
+typedef union hubii_wid_u {
+        u64     wid_reg_value;
+        struct {
+                u64     wid_rsvd:       32,     /* unused */
+                        wid_rev_num:     4,     /* revision number */
+                        wid_part_num:   16,     /* the widget type: hub=c101 */
+                        wid_mfg_num:    11,     /* Manufacturer id (IBM) */
+                        wid_rsvd1:       1;     /* Reserved */
+        } wid_fields_s;
+} hubii_wid_t;
+
+
+typedef union hubii_wcr_u {
+        u64     wcr_reg_value;
+        struct {
+                u64     wcr_rsvd:       41,     /* unused */
+                        wcr_e_thresh:    5,     /* elasticity threshold */
+                        wcr_dir_con:     1,     /* widget direct connect */
+                        wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
+                        wcr_xbar_crd:    3,     /* LLP crossbar credit */
+                        wcr_rsvd1:       8,     /* Reserved */
+                        wcr_tag_mode:    1,     /* Tag mode */
+                        wcr_widget_id:   4;     /* LLP crossbar credit */
+        } wcr_fields_s;
+} hubii_wcr_t;
+
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+
+typedef union hubii_wstat_u {
+        u64      reg_value;
+        struct {
+                u64     rsvd1:          31,
+                        crazy:           1,     /* Crazy bit            */
+                        rsvd2:           8,
+                        llp_tx_cnt:      8,     /* LLP Xmit retry counter */
+                        rsvd3:           6,
+                        tx_max_rtry:     1,     /* LLP Retry Timeout Signal */
+                        rsvd4:           2,
+                        xt_tail_to:      1,     /* Xtalk Tail Timeout   */
+                        xt_crd_to:       1,     /* Xtalk Credit Timeout */
+                        pending:         4;     /* Pending Requests     */
+        } wstat_fields_s;
+} hubii_wstat_t;
+
+
+typedef union hubii_ilcsr_u {
+        u64     icsr_reg_value;
+        struct {
+                u64     icsr_rsvd:      22,     /* unused */
+                        icsr_max_burst: 10,     /* max burst */
+                        icsr_rsvd4:      6,     /* reserved */
+                        icsr_max_retry: 10,     /* max retry */
+                        icsr_rsvd3:      2,     /* reserved */
+                        icsr_lnk_stat:   2,     /* link status */
+                        icsr_bm8:        1,     /* Bit mode 8 */
+                        icsr_llp_en:     1,     /* LLP enable bit */
+                        icsr_rsvd2:      1,     /* reserver */
+                        icsr_wrm_reset:  1,     /* Warm reset bit */
+                        icsr_rsvd1:      2,     /* Data ready offset */
+                        icsr_null_to:    6;     /* Null timeout   */
+
+        } icsr_fields_s;
+} hubii_ilcsr_t;
+
+
+typedef union hubii_iowa_u {
+        u64     iowa_reg_value;
+        struct {
+                u64     iowa_rsvd:      48,     /* unused */
+                        iowa_wxoac:      8,     /* xtalk widget access bits */
+                        iowa_rsvd1:      7,     /* xtalk widget access bits */
+                        iowa_w0oac:      1;     /* xtalk widget access bits */
+        } iowa_fields_s;
+} hubii_iowa_t;
+
+typedef union hubii_iiwa_u {
+        u64     iiwa_reg_value;
+        struct {
+                u64     iiwa_rsvd:      48,     /* unused */
+                        iiwa_wxiac:      8,     /* hub wid access bits */
+                        iiwa_rsvd1:      7,     /* reserved */
+                        iiwa_w0iac:      1;     /* hub wid0 access */
+        } iiwa_fields_s;
+} hubii_iiwa_t;
+
+typedef union   hubii_illr_u {
+        u64     illr_reg_value;
+        struct {
+                u64     illr_rsvd:      32,     /* unused */
+                        illr_cb_cnt:    16,     /* checkbit error count */
+                        illr_sn_cnt:    16;     /* sequence number count */
+        } illr_fields_s;
+} hubii_illr_t;
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+   performed */
+typedef union io_perf_sel {
+        u64 perf_sel_reg;
+        struct {
+                u64     perf_rsvd  : 48,
+                        perf_icct  :  8,
+                        perf_ippr1 :  4,
+                        perf_ippr0 :  4;
+        } perf_sel_bits;
+} io_perf_sel_t;
+
+/* io_perf_cnt is to extract the count from the hub registers. Due to
+   hardware problems there is only one counter, not two. */
+
+typedef union io_perf_cnt {
+        u64     perf_cnt;
+        struct {
+                u64     perf_rsvd1 : 32,
+                        perf_rsvd2 : 12,
+                        perf_cnt   : 20;
+        } perf_cnt_bits;
+} io_perf_cnt_t;
+
+#endif /* !__ASSEMBLY__ */
+
+
+#define LNK_STAT_WORKING        0x2
+
+#define IIO_LLP_CB_MAX  0xffff
+#define IIO_LLP_SN_MAX  0xffff
+
+/* IO PRB Entries */
+#define IIO_NUM_IPRBS   (9)
+#define IIO_IOPRB_0     0x400198        /* PRB entry 0 */
+#define IIO_IOPRB_8     0x4001a0        /* PRB entry 8 */
+#define IIO_IOPRB_9     0x4001a8        /* PRB entry 9 */
+#define IIO_IOPRB_A     0x4001b0        /* PRB entry a */
+#define IIO_IOPRB_B     0x4001b8        /* PRB entry b */
+#define IIO_IOPRB_C     0x4001c0        /* PRB entry c */
+#define IIO_IOPRB_D     0x4001c8        /* PRB entry d */
+#define IIO_IOPRB_E     0x4001d0        /* PRB entry e */
+#define IIO_IOPRB_F     0x4001d8        /* PRB entry f */
+
+
+#define IIO_IXCC        0x4001e0        /* Crosstalk credit count timeout */
+#define IIO_IXTCC       IIO_IXCC
+#define IIO_IMEM        0x4001e8        /* Miscellaneous Enable Mask */
+#define IIO_IXTT        0x4001f0        /* Crosstalk tail timeout */
+#define IIO_IECLR       0x4001f8        /* IO error clear */
+#define IIO_IBCN        0x400200        /* IO BTE CRB count */
+
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
+
+/* PIO Read address Table Entries */
+#define IIO_IPCA        0x400300        /* PRB Counter adjust */
+#define IIO_NUM_PRTES   8               /* Total number of PRB table entries */
+#define IIO_PRTE_0      0x400308        /* PIO Read address table entry 0 */
+#define IIO_PRTE(_x)    (IIO_PRTE_0 + (8 * (_x)))
+#define IIO_WIDPRTE(x)  IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_IPDR        0x400388        /* PIO table entry deallocation */
+#define IIO_ICDR        0x400390        /* CRB Entry Deallocation */
+#define IIO_IFDR        0x400398        /* IOQ FIFO Depth */
+#define IIO_IIAP        0x4003a0        /* IIQ Arbitration Parameters */
+#define IIO_IMMR        IIO_IIAP
+#define IIO_ICMR        0x4003a8        /* CRB Management Register */
+#define IIO_ICCR        0x4003b0        /* CRB Control Register */
+#define IIO_ICTO        0x4003b8        /* CRB Time Out Register */
+#define IIO_ICTP        0x4003c0        /* CRB Time Out Prescalar */
+
+
+/*
+ * ICMR register fields
+ */
+#define IIO_ICMR_PC_VLD_SHFT    36
+#define IIO_ICMR_PC_VLD_MASK    (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
+
+#define IIO_ICMR_CRB_VLD_SHFT   20
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT    16
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT     4
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_P_CNT_SHFT     0
+#define IIO_ICMR_P_CNT_MASK     (0xf << IIO_ICMR_P_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ */
+#define IIO_IPDR_PND    (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND    (1 << 4)
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR
+ */
+#define IIO_ICCR_PENDING        (0x10000)
+#define IIO_ICCR_CMD_MASK       (0xFF)
+#define IIO_ICCR_CMD_SHFT       (7)
+#define IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
+#define IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory
+                                         * via a WB
+                                         */
+#define IIO_ICCR_CMD_FLUSH      (0x800)
+
+/*
+ * CRB manipulation macros
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_NORMAL_CRBS     12      /* Number of regular CRB entries */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET         8
+#define IIO_ICRB_0              0x400400
+/* XXX - This is now tuneable:
+        #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
+#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
+#define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
+#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
+
+/* XXX - IBUE register coming for Hub 2 */
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to hub IIO's status.
+ * Quiescing implies  no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+/*
+ * Fields in CRB Register A
+ */
+#ifndef __ASSEMBLY__
+typedef union icrba_u {
+        u64     reg_value;
+        struct {
+                u64     resvd:  6,
+                        stall_bte0: 1,  /* Stall BTE 0 */
+                        stall_bte1: 1,  /* Stall BTE 1 */
+                        error:  1,      /* CRB has an error     */
+                        ecode:  3,      /* Error Code           */
+                        lnetuce: 1,     /* SN0net Uncorrectable error */
+                        mark:   1,      /* CRB Has been marked  */
+                        xerr:   1,      /* Error bit set in xtalk header */
+                        sidn:   4,      /* SIDN field from xtalk        */
+                        tnum:   5,      /* TNUM field in xtalk          */
+                        addr:   38,     /* Address of request   */
+                        valid:  1,      /* Valid status         */
+                        iow:    1;      /* IO Write operation   */
+        } icrba_fields_s;
+} icrba_t;
+
+/* This is an alternate typedef for the HUB1 CRB A in order to allow
+   runtime selection of the format based on the REV_ID field of the
+   NI_STATUS_REV_ID register. */
+typedef union h1_icrba_u {
+        u64     reg_value;
+
+        struct {
+                u64     resvd:  6,
+                        unused: 1,      /* Unused but RW!!      */
+                        error:  1,      /* CRB has an error     */
+                        ecode:  4,      /* Error Code           */
+                        lnetuce: 1,     /* SN0net Uncorrectable error */
+                        mark:   1,      /* CRB Has been marked  */
+                        xerr:   1,      /* Error bit set in xtalk header */
+                        sidn:   4,      /* SIDN field from xtalk        */
+                        tnum:   5,      /* TNUM field in xtalk          */
+                        addr:   38,     /* Address of request   */
+                        valid:  1,      /* Valid status         */
+                        iow:    1;      /* IO Write operation   */
+        } h1_icrba_fields_s;
+} h1_icrba_t;
+
+/* XXX - Is this still right?  Check the spec. */
+#define ICRBN_A_CERR_SHFT       54
+#define ICRBN_A_ERR_MASK        0x3ff
+
+#endif /* !__ASSEMBLY__ */
+
+#define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line.
+                                         */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+
+
+
+/*
+ * Fields in CRB Register B
+ */
+#ifndef __ASSEMBLY__
+typedef union icrbb_u {
+        u64     reg_value;
+        struct {
+            u64 rsvd1:  5,
+                btenum: 1,      /* BTE to which entry belongs to */
+                cohtrans: 1,    /* Coherent transaction */
+                xtsize: 2,      /* Xtalk operation size
+                                 * 0: Double Word
+                                 * 1: 32 Bytes.
+                                 * 2: 128 Bytes,
+                                 * 3: Reserved.
+                                 */
+                srcnode: 9,     /* Source Node ID               */
+                srcinit: 2,     /* Source Initiator:
+                                 * See below for field values.
+                                 */
+                useold: 1,      /* Use OLD command for processing */
+                imsgtype: 2,    /* Incoming message type
+                                 * see below for field values
+                                 */
+                imsg:   8,      /* Incoming message     */
+                initator: 3,    /* Initiator of original request
+                                 * See below for field values.
+                                 */
+                reqtype: 5,     /* Identifies type of request
+                                 * See below for field values.
+                                 */
+                rsvd2:  7,
+                ackcnt: 11,     /* Invalidate ack count */
+                resp:   1,      /* data response  given to processor */
+                ack:    1,      /* indicates data ack received  */
+                hold:   1,      /* entry is gathering inval acks */
+                wb_pend:1,      /* waiting for writeback to complete */
+                intvn:  1,      /* Intervention */
+                stall_ib: 1,    /* Stall Ibuf (from crosstalk) */
+                stall_intr: 1;  /* Stall internal interrupts */
+        } icrbb_field_s;
+} icrbb_t;
+
+/* This is an alternate typedef for the HUB1 CRB B in order to allow
+   runtime selection of the format based on the REV_ID field of the
+   NI_STATUS_REV_ID register. */
+typedef union h1_icrbb_u {
+        u64     reg_value;
+        struct {
+                u64     rsvd1:  5,
+                        btenum: 1,      /* BTE to which entry belongs to */
+                        cohtrans: 1,    /* Coherent transaction */
+                        xtsize: 2,      /* Xtalk operation size
+                                         * 0: Double Word
+                                         * 1: 32 Bytes.
+                                         * 2: 128 Bytes,
+                                         * 3: Reserved.
+                                         */
+                        srcnode: 9,     /* Source Node ID               */
+                        srcinit: 2,     /* Source Initiator:
+                                         * See below for field values.
+                                         */
+                        useold: 1,      /* Use OLD command for processing */
+                        imsgtype: 2,    /* Incoming message type
+                                         * see below for field values
+                                         */
+                        imsg:   8,      /* Incoming message     */
+                        initator: 3,    /* Initiator of original request
+                                         * See below for field values.
+                                         */
+                        rsvd2:  1,
+                        pcache: 1,      /* entry belongs to partial cache */
+                        reqtype: 5,     /* Identifies type of request
+                                         * See below for field values.
+                                         */
+                        stl_ib: 1,      /* stall Ibus coming from xtalk */
+                        stl_intr: 1,    /* Stall internal interrupts */
+                        stl_bte0: 1,    /* Stall BTE 0  */
+                        stl_bte1: 1,    /* Stall BTE 1  */
+                        intrvn: 1,      /* Req was target of intervention */
+                        ackcnt: 11,     /* Invalidate ack count */
+                        resp:   1,      /* data response  given to processor */
+                        ack:    1,      /* indicates data ack received  */
+                        hold:   1,      /* entry is gathering inval acks */
+                        wb_pend:1,      /* waiting for writeback to complete */
+                        sleep:  1,      /* xtalk req sleeping till IO-sync */
+                        pnd_reply: 1,   /* replies not issed due to IOQ full */
+                        pnd_req: 1;     /* reqs not issued due to IOQ full */
+        } h1_icrbb_field_s;
+} h1_icrbb_t;
+
+
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_btenum        icrbb_field_s.btenum
+#define b_cohtrans      icrbb_field_s.cohtrans
+#define b_xtsize        icrbb_field_s.xtsize
+#define b_srcnode       icrbb_field_s.srcnode
+#define b_srcinit       icrbb_field_s.srcinit
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_imsg          icrbb_field_s.imsg
+#define b_initiator     icrbb_field_s.initiator
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * values for field xtsize
+ */
+#define IIO_ICRB_XTSIZE_DW      0       /* Xtalk operation size is 8 bytes  */
+#define IIO_ICRB_XTSIZE_32      1       /* Xtalk operation size is 32 bytes */
+#define IIO_ICRB_XTSIZE_128     2       /* Xtalk operation size is 128 bytes */
+
+/*
+ * values for field srcinit
+ */
+#define IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
+#define IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
+#define IIO_ICRB_GB_REQ         2       /* Source is Guranteed BW request */
+#define IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
+
+/*
+ * Values for field imsgtype
+ */
+#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN0NET   2       /* Incoming message from SN0 net */
+#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+
+/*
+ * values for field initiator.
+ */
+#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN0NET    0x2     /* Message originated in SN0net */
+#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+
+/*
+ * Values for field reqtype.
+ */
+/* XXX - Need to fix this for Hub 2 */
+#define IIO_ICRB_REQ_DWRD       0       /* Request type double word     */
+#define IIO_ICRB_REQ_QCLRD      1       /* Request is Qrtr Caceh line Rd */
+#define IIO_ICRB_REQ_BLKRD      2       /* Request is block read        */
+#define IIO_ICRB_REQ_RSHU       6       /* Request is BTE block read    */
+#define IIO_ICRB_REQ_REXU       7       /* request is BTE Excl Read     */
+#define IIO_ICRB_REQ_RDEX       8       /* Request is Read Exclusive    */
+#define IIO_ICRB_REQ_WINC       9       /* Request is Write Invalidate  */
+#define IIO_ICRB_REQ_BWINV      10      /* Request is BTE Winv          */
+#define IIO_ICRB_REQ_PIORD      11      /* Request is PIO read          */
+#define IIO_ICRB_REQ_PIOWR      12      /* Request is PIO Write         */
+#define IIO_ICRB_REQ_PRDM       13      /* Request is Fetch&Op          */
+#define IIO_ICRB_REQ_PWRM       14      /* Request is Store &Op         */
+#define IIO_ICRB_REQ_PTPWR      15      /* Request is Peer to peer      */
+#define IIO_ICRB_REQ_WB         16      /* Request is Write back        */
+#define IIO_ICRB_REQ_DEX        17      /* Retained DEX Cache line      */
+
+/*
+ * Fields in CRB Register C
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef union icrbc_s {
+        u64     reg_value;
+        struct {
+                u64     rsvd:   6,
+                        sleep:  1,
+                        pricnt: 4,      /* Priority count sent with Read req */
+                        pripsc: 4,      /* Priority Pre scalar  */
+                        bteop:  1,      /* BTE Operation        */
+                        push_be: 34,    /* Push address Byte enable
+                                         * Holds push addr, if CRB is for BTE
+                                         * If CRB belongs to Partial cache,
+                                         * this contains byte enables bits
+                                         * ([47:46] = 0)
+                                         */
+                        suppl:  11,     /* Supplemental field   */
+                        barrop: 1,      /* Barrier Op bit set in xtalk req */
+                        doresp: 1,      /* Xtalk req needs a response   */
+                        gbr:    1;      /* GBR bit set in xtalk packet  */
+        } icrbc_field_s;
+} icrbc_t;
+
+#define c_pricnt        icrbc_field_s.pricnt
+#define c_pripsc        icrbc_field_s.pripsc
+#define c_bteop         icrbc_field_s.bteop
+#define c_bteaddr       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_benable       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_suppl         icrbc_field_s.suppl
+#define c_barrop        icrbc_field_s.barrop
+#define c_doresp        icrbc_field_s.doresp
+#define c_gbr   icrbc_field_s.gbr
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Fields in CRB Register D
+ */
+
+#ifndef __ASSEMBLY__
+typedef union icrbd_s {
+        u64     reg_value;
+        struct {
+            u64 rsvd:   38,
+                toutvld: 1,     /* Timeout in progress for this CRB */
+                ctxtvld: 1,     /* Context field below is valid */
+                rsvd2:  1,
+                context: 15,    /* Bit vector:
+                                 * Has a bit set for each CRB entry
+                                 * which needs to be deallocated
+                                 * before this CRB entry is processed.
+                                 * Set only for barrier operations.
+                                 */
+                timeout: 8;     /* Timeout Upper 8 bits */
+        } icrbd_field_s;
+} icrbd_t;
+
+#define icrbd_toutvld   icrbd_field_s.toutvld
+#define icrbd_ctxtvld   icrbd_field_s.ctxtvld
+#define icrbd_context   icrbd_field_s.context
+
+
+typedef union hubii_ifdr_u {
+        u64     hi_ifdr_value;
+        struct {
+                u64     ifdr_rsvd:      49,
+                        ifdr_maxrp:      7,
+                        ifdr_rsvd1:      1,
+                        ifdr_maxrq:      7;
+        } hi_ifdr_fields;
+} hubii_ifdr_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Hardware designed names for the BTE control registers.
+ */
+#define IIO_IBLS_0      0x410000        /* BTE length/status 0 */
+#define IIO_IBSA_0      0x410008        /* BTE source address 0 */
+#define IIO_IBDA_0      0x410010        /* BTE destination address 0 */
+#define IIO_IBCT_0      0x410018        /* BTE control/terminate 0 */
+#define IIO_IBNA_0      0x410020        /* BTE notification address 0 */
+#define IIO_IBNR_0      IIO_IBNA_0
+#define IIO_IBIA_0      0x410028        /* BTE interrupt address 0 */
+
+#define IIO_IBLS_1      0x420000        /* BTE length/status 1 */
+#define IIO_IBSA_1      0x420008        /* BTE source address 1 */
+#define IIO_IBDA_1      0x420010        /* BTE destination address 1 */
+#define IIO_IBCT_1      0x420018        /* BTE control/terminate 1 */
+#define IIO_IBNA_1      0x420020        /* BTE notification address 1 */
+#define IIO_IBNR_1      IIO_IBNA_1
+#define IIO_IBIA_1      0x420028        /* BTE interrupt address 1 */
+
+/*
+ * More miscellaneous registers
+ */
+#define IIO_IPCR        0x430000        /* Performance Control */
+#define IIO_IPPR        0x430008        /* Performance Profiling */
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_BTE1              (1 << 18)  /* clear bte error 1 ??? */
+#define IECLR_BTE0              (1 << 17)  /* clear bte error 0 ??? */
+#define IECLR_CRAZY             (1 << 16)  /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F             (1 << 15)  /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E             (1 << 14)  /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D             (1 << 13)  /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C             (1 << 12)  /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B             (1 << 11)  /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A             (1 << 10)  /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9             (1 << 9)   /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8             (1 << 8)   /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0             (1 << 0)   /* clear err bit in PRB_0 reg */
+
+/*
+ * IO PIO Read Table Entry format
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef union iprte_a {
+        u64     entry;
+        struct {
+            u64 rsvd1     : 7,  /* Reserved field               */
+                valid     : 1,  /* Maps to a timeout entry      */
+                rsvd2     : 1,
+                srcnode   : 9,  /* Node which did this PIO      */
+                initiator : 2,  /* If T5A or T5B or IO          */
+                rsvd3     : 3,
+                addr      : 38, /* Physical address of PIO      */
+                rsvd4     : 3;
+        } iprte_fields;
+} iprte_a_t;
+
+#define iprte_valid     iprte_fields.valid
+#define iprte_timeout   iprte_fields.timeout
+#define iprte_srcnode   iprte_fields.srcnode
+#define iprte_init      iprte_fields.initiator
+#define iprte_addr      iprte_fields.addr
+
+#endif /* !__ASSEMBLY__ */
+
+#define IPRTE_ADDRSHFT  3
+
+/*
+ * Hub IIO PRB Register format.
+ */
+
+#ifndef __ASSEMBLY__
+/*
+ * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
+ * "Status" fields, and should only be used in case of clean up after errors.
+ */
+
+typedef union iprb_u {
+        u64     reg_value;
+        struct {
+            u64 rsvd1:  15,
+                error:  1,      /* Widget rcvd wr resp pkt w/ error */
+                ovflow: 5,      /* Over flow count. perf measurement */
+                fire_and_forget: 1, /* Launch Write without response */
+                mode:   2,      /* Widget operation Mode        */
+                rsvd2:  2,
+                bnakctr: 14,
+                rsvd3:  2,
+                anakctr: 14,
+                xtalkctr: 8;
+        } iprb_fields_s;
+} iprb_t;
+
+#define iprb_regval     reg_value
+
+#define iprb_error      iprb_fields_s.error
+#define iprb_ovflow     iprb_fields_s.ovflow
+#define iprb_ff         iprb_fields_s.fire_and_forget
+#define iprb_mode       iprb_fields_s.mode
+#define iprb_bnakctr    iprb_fields_s.bnakctr
+#define iprb_anakctr    iprb_fields_s.anakctr
+#define iprb_xtalkctr   iprb_fields_s.xtalkctr
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * values for mode field in iprb_t.
+ * For details of the meanings of NAK and Accept, refer the PIO flow
+ * document
+ */
+#define IPRB_MODE_NORMAL        (0)
+#define IPRB_MODE_COLLECT_A     (1)     /* PRB in collect A mode */
+#define IPRB_MODE_SERVICE_A     (2)     /* NAK B and Accept A */
+#define IPRB_MODE_SERVICE_B     (3)     /* NAK A and Accept B */
+
+/*
+ * IO CRB entry C_A to E_A : Partial (cache) CRBS
+ */
+#ifndef __ASSEMBLY__
+typedef union icrbp_a {
+        u64   ip_reg;       /* the entire register value        */
+        struct {
+             u64 error: 1,  /*    63, error occurred            */
+                ln_uce: 1,  /*    62: uncorrectable memory      */
+                ln_ae:  1,  /*    61: protection violation      */
+                ln_werr:1,  /*    60: write access error        */
+                ln_aerr:1,  /*    59: sn0net: Address error     */
+                ln_perr:1,  /*    58: sn0net: poison error      */
+                timeout:1,  /*    57: CRB timed out             */
+                l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
+                c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
+                c_err:  1,  /*    54: incoming xtalk req, err set*/
+                rsvd1: 12,  /* 53-42: reserved                  */
+                valid:  1,  /*    41: Valid status              */
+                sidn:   4,  /* 40-37: SIDN field of xtalk rqst  */
+                tnum:   5,  /* 36-32: TNUM of xtalk request     */
+                bo:     1,  /*    31: barrier op set in xtalk rqst*/
+                resprqd:1,  /*    30: xtalk rqst requires response*/
+                gbr:    1,  /*    29: gbr bit set in xtalk rqst */
+                size:   2,  /* 28-27: size of xtalk request     */
+                excl:   4,  /* 26-23: exclusive bit(s)          */
+                stall:  3,  /* 22-20: stall (xtalk, bte 0/1)    */
+                intvn:  1,  /*    19: rqst target of intervention*/
+                resp:   1,  /*    18: Data response given to t5 */
+                ack:    1,  /*    17: Data ack received.        */
+                hold:   1,  /*    16: crb gathering invalidate acks*/
+                wb:     1,  /*    15: writeback pending.        */
+                ack_cnt:11, /* 14-04: counter of invalidate acks*/
+                tscaler:4;  /* 03-00: Timeout prescaler         */
+        } ip_fmt;
+} icrbp_a_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * A couple of defines to go with the above structure.
+ */
+#define ICRBP_A_CERR_SHFT       54
+#define ICRBP_A_ERR_MASK        0x3ff
+
+#ifndef __ASSEMBLY__
+typedef union hubii_idsr {
+        u64 iin_reg;
+        struct {
+                u64 rsvd1 : 35,
+                    isent : 1,
+                    rsvd2 : 3,
+                    ienable: 1,
+                    rsvd  : 7,
+                    node  : 9,
+                    rsvd4 : 1,
+                    level : 7;
+        } iin_fmt;
+} hubii_idsr_t;
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY               (0x1 << 20)
+#define IBLS_ERROR_SHFT         16
+#define IBLS_ERROR              (0x1 << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK        0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON             (0x1 << 8)
+#define IBCT_NOTIFY             (0x1 << 4)
+#define IBCT_ZFIL_MODE          (0x1 << 0)
+
+/*
+ * IO BTE Interrupt Address Register (IBIA) register bit field definitions
+ */
+#define IBIA_LEVEL_SHFT         16
+#define IBIA_LEVEL_MASK         (0x7f << IBIA_LEVEL_SHFT)
+#define IBIA_NODE_ID_SHFT       0
+#define IBIA_NODE_ID_MASK       (0x1ff)
+
+/*
+ * Miscellaneous hub constants
+ */
+
+/* Number of widgets supported by hub */
+#define HUB_NUM_WIDGET          9
+#define HUB_WIDGET_ID_MIN       0x8
+#define HUB_WIDGET_ID_MAX       0xf
+
+#define HUB_WIDGET_PART_NUM     0xc101
+#define MAX_HUBS_PER_XBOW       2
+
+/*
+ * Get a hub's widget id from widget control register
+ */
+#define IIO_WCR_WID_GET(nasid)  (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
+#define IIO_WST_ERROR_MASK      (UINT64_CAST 1 << 32) /* Widget status error */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define       HUBII_XBOW_CREDIT       3
+#define       HUBII_XBOW_REV2_CREDIT  4
+
+#endif /* _ASM_SGI_SN_SN0_HUBIO_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubmd.h b/arch/mips/include/asm/sn/sn0/hubmd.h
new file mode 100644
index 000000000000..14c225d80664
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubmd.h
@@ -0,0 +1,789 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUBMD_H
+#define _ASM_SN_SN0_HUBMD_H
+
+
+/*
+ * Hub Memory/Directory interface registers
+ */
+#define CACHE_SLINE_SIZE        128     /* Secondary cache line size on SN0 */
+
+#define MAX_REGIONS             64
+
+/* Hardware page size and shift */
+
+#define MD_PAGE_SIZE            4096     /* Page size in bytes              */
+#define MD_PAGE_NUM_SHFT        12       /* Address to page number shift    */
+
+/* Register offsets from LOCAL_HUB or REMOTE_HUB */
+
+#define MD_BASE                 0x200000
+#define MD_BASE_PERF            0x210000
+#define MD_BASE_JUNK            0x220000
+
+#define MD_IO_PROTECT           0x200000 /* MD and core register protection */
+#define MD_IO_PROT_OVRRD        0x200008 /* Clear my bit in MD_IO_PROTECT   */
+#define MD_HSPEC_PROTECT        0x200010 /* BDDIR, LBOOT, RBOOT protection  */
+#define MD_MEMORY_CONFIG        0x200018 /* Memory/Directory DIMM control   */
+#define MD_REFRESH_CONTROL      0x200020 /* Memory/Directory refresh ctrl   */
+#define MD_FANDOP_CAC_STAT      0x200028 /* Fetch-and-op cache status       */
+#define MD_MIG_DIFF_THRESH      0x200030 /* Page migr. count diff thresh.   */
+#define MD_MIG_VALUE_THRESH     0x200038 /* Page migr. count abs. thresh.   */
+#define MD_MIG_CANDIDATE        0x200040 /* Latest page migration candidate */
+#define MD_MIG_CANDIDATE_CLR    0x200048 /* Clear page migration candidate  */
+#define MD_DIR_ERROR            0x200050 /* Directory DIMM error            */
+#define MD_DIR_ERROR_CLR        0x200058 /* Directory DIMM error clear      */
+#define MD_PROTOCOL_ERROR       0x200060 /* Directory protocol error        */
+#define MD_PROTOCOL_ERROR_CLR   0x200068 /* Directory protocol error clear  */
+#define MD_MEM_ERROR            0x200070 /* Memory DIMM error               */
+#define MD_MEM_ERROR_CLR        0x200078 /* Memory DIMM error clear         */
+#define MD_MISC_ERROR           0x200080 /* Miscellaneous MD error          */
+#define MD_MISC_ERROR_CLR       0x200088 /* Miscellaneous MD error clear    */
+#define MD_MEM_DIMM_INIT        0x200090 /* Memory DIMM mode initization.   */
+#define MD_DIR_DIMM_INIT        0x200098 /* Directory DIMM mode init.       */
+#define MD_MOQ_SIZE             0x2000a0 /* MD outgoing queue size          */
+#define MD_MLAN_CTL             0x2000a8 /* NIC (Microlan) control register */
+
+#define MD_PERF_SEL             0x210000 /* Select perf monitor events      */
+#define MD_PERF_CNT0            0x210010 /* Performance counter 0           */
+#define MD_PERF_CNT1            0x210018 /* Performance counter 1           */
+#define MD_PERF_CNT2            0x210020 /* Performance counter 2           */
+#define MD_PERF_CNT3            0x210028 /* Performance counter 3           */
+#define MD_PERF_CNT4            0x210030 /* Performance counter 4           */
+#define MD_PERF_CNT5            0x210038 /* Performance counter 5           */
+
+#define MD_UREG0_0              0x220000 /* uController/UART 0 register     */
+#define MD_UREG0_1              0x220008 /* uController/UART 0 register     */
+#define MD_UREG0_2              0x220010 /* uController/UART 0 register     */
+#define MD_UREG0_3              0x220018 /* uController/UART 0 register     */
+#define MD_UREG0_4              0x220020 /* uController/UART 0 register     */
+#define MD_UREG0_5              0x220028 /* uController/UART 0 register     */
+#define MD_UREG0_6              0x220030 /* uController/UART 0 register     */
+#define MD_UREG0_7              0x220038 /* uController/UART 0 register     */
+
+#define MD_SLOTID_USTAT         0x220048 /* Hub slot ID & UART/uCtlr status */
+#define MD_LED0                 0x220050 /* Eight-bit LED for CPU A         */
+#define MD_LED1                 0x220058 /* Eight-bit LED for CPU B         */
+
+#define MD_UREG1_0              0x220080 /* uController/UART 1 register     */
+#define MD_UREG1_1              0x220088 /* uController/UART 1 register     */
+#define MD_UREG1_2              0x220090 /* uController/UART 1 register     */
+#define MD_UREG1_3              0x220098 /* uController/UART 1 register     */
+#define MD_UREG1_4              0x2200a0 /* uController/UART 1 register     */
+#define MD_UREG1_5              0x2200a8 /* uController/UART 1 register     */
+#define MD_UREG1_6              0x2200b0 /* uController/UART 1 register     */
+#define MD_UREG1_7              0x2200b8 /* uController/UART 1 register     */
+#define MD_UREG1_8              0x2200c0 /* uController/UART 1 register     */
+#define MD_UREG1_9              0x2200c8 /* uController/UART 1 register     */
+#define MD_UREG1_10             0x2200d0 /* uController/UART 1 register     */
+#define MD_UREG1_11             0x2200d8 /* uController/UART 1 register     */
+#define MD_UREG1_12             0x2200e0 /* uController/UART 1 register     */
+#define MD_UREG1_13             0x2200e8 /* uController/UART 1 register     */
+#define MD_UREG1_14             0x2200f0 /* uController/UART 1 register     */
+#define MD_UREG1_15             0x2200f8 /* uController/UART 1 register     */
+
+#ifdef CONFIG_SGI_SN_N_MODE
+#define MD_MEM_BANKS            4        /* 4 banks of memory max in N mode */
+#else
+#define MD_MEM_BANKS            8        /* 8 banks of memory max in M mode */
+#endif
+
+/*
+ * MD_MEMORY_CONFIG fields
+ *
+ *   MD_SIZE_xxx are useful for representing the size of a SIMM or bank
+ *   (SIMM pair).  They correspond to the values needed for the bit
+ *   triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
+ *   Bits not used by the MD are used by software.
+ */
+
+#define MD_SIZE_EMPTY           0       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_8MB             1
+#define MD_SIZE_16MB            2
+#define MD_SIZE_32MB            3       /* Broken in Hub 1                  */
+#define MD_SIZE_64MB            4       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_128MB           5       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_256MB           6
+#define MD_SIZE_512MB           7       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_1GB             8
+#define MD_SIZE_2GB             9
+#define MD_SIZE_4GB             10
+
+#define MD_SIZE_BYTES(size)     ((size) == 0 ? 0 : 0x400000L << (size))
+#define MD_SIZE_MBYTES(size)    ((size) == 0 ? 0 :   4       << (size))
+
+#define MMC_FPROM_CYC_SHFT      49      /* Have to use UINT64_CAST, instead */
+#define MMC_FPROM_CYC_MASK      (UINT64_CAST 31 << 49)  /* of 'L' suffix,   */
+#define MMC_FPROM_WR_SHFT       44                      /* for assembler    */
+#define MMC_FPROM_WR_MASK       (UINT64_CAST 31 << 44)
+#define MMC_UCTLR_CYC_SHFT      39
+#define MMC_UCTLR_CYC_MASK      (UINT64_CAST 31 << 39)
+#define MMC_UCTLR_WR_SHFT       34
+#define MMC_UCTLR_WR_MASK       (UINT64_CAST 31 << 34)
+#define MMC_DIMM0_SEL_SHFT      32
+#define MMC_DIMM0_SEL_MASK      (UINT64_CAST 3 << 32)
+#define MMC_IO_PROT_EN_SHFT     31
+#define MMC_IO_PROT_EN_MASK     (UINT64_CAST 1 << 31)
+#define MMC_IO_PROT             (UINT64_CAST 1 << 31)
+#define MMC_ARB_MLSS_SHFT       30
+#define MMC_ARB_MLSS_MASK       (UINT64_CAST 1 << 30)
+#define MMC_ARB_MLSS            (UINT64_CAST 1 << 30)
+#define MMC_IGNORE_ECC_SHFT     29
+#define MMC_IGNORE_ECC_MASK     (UINT64_CAST 1 << 29)
+#define MMC_IGNORE_ECC          (UINT64_CAST 1 << 29)
+#define MMC_DIR_PREMIUM_SHFT    28
+#define MMC_DIR_PREMIUM_MASK    (UINT64_CAST 1 << 28)
+#define MMC_DIR_PREMIUM         (UINT64_CAST 1 << 28)
+#define MMC_REPLY_GUAR_SHFT     24
+#define MMC_REPLY_GUAR_MASK     (UINT64_CAST 15 << 24)
+#define MMC_BANK_SHFT(_b)       ((_b) * 3)
+#define MMC_BANK_MASK(_b)       (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
+#define MMC_BANK_ALL_MASK       0xffffff
+#define MMC_RESET_DEFAULTS      (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
+                                 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
+                                 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
+                                 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
+                                 MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
+                                 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
+                                 MMC_BANK_ALL_MASK)
+
+/* MD_REFRESH_CONTROL fields */
+
+#define MRC_ENABLE_SHFT         63
+#define MRC_ENABLE_MASK         (UINT64_CAST 1 << 63)
+#define MRC_ENABLE              (UINT64_CAST 1 << 63)
+#define MRC_COUNTER_SHFT        12
+#define MRC_COUNTER_MASK        (UINT64_CAST 0xfff << 12)
+#define MRC_CNT_THRESH_MASK     0xfff
+#define MRC_RESET_DEFAULTS      (UINT64_CAST 0x400)
+
+/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
+
+#define MDI_SELECT_SHFT         32
+#define MDI_SELECT_MASK         (UINT64_CAST 0x0f << 32)
+#define MDI_DIMM_MODE_MASK      (UINT64_CAST 0xfff)
+
+/* MD_MOQ_SIZE fields */
+
+#define MMS_RP_SIZE_SHFT        8
+#define MMS_RP_SIZE_MASK        (UINT64_CAST 0x3f << 8)
+#define MMS_RQ_SIZE_SHFT        0
+#define MMS_RQ_SIZE_MASK        (UINT64_CAST 0x1f)
+#define MMS_RESET_DEFAULTS      (0x32 << 8 | 0x12)
+
+/* MD_FANDOP_CAC_STAT fields */
+
+#define MFC_VALID_SHFT          63
+#define MFC_VALID_MASK          (UINT64_CAST 1 << 63)
+#define MFC_VALID               (UINT64_CAST 1 << 63)
+#define MFC_ADDR_SHFT           6
+#define MFC_ADDR_MASK           (UINT64_CAST 0x3ffffff)
+
+/* MD_MLAN_CTL fields */
+
+#define MLAN_PHI1_SHFT          27
+#define MLAN_PHI1_MASK          (UINT64_CAST 0x7f << 27)
+#define MLAN_PHI0_SHFT          20
+#define MLAN_PHI0_MASK          (UINT64_CAST 0x7f << 27)
+#define MLAN_PULSE_SHFT         10
+#define MLAN_PULSE_MASK         (UINT64_CAST 0x3ff << 10)
+#define MLAN_SAMPLE_SHFT        2
+#define MLAN_SAMPLE_MASK        (UINT64_CAST 0xff << 2)
+#define MLAN_DONE_SHFT          1
+#define MLAN_DONE_MASK          2
+#define MLAN_DONE               (UINT64_CAST 0x02)
+#define MLAN_RD_DATA            (UINT64_CAST 0x01)
+#define MLAN_RESET_DEFAULTS     (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
+                                 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
+
+/* MD_SLOTID_USTAT bit definitions */
+
+#define MSU_CORECLK_TST_SHFT    7       /* You don't wanna know             */
+#define MSU_CORECLK_TST_MASK    (UINT64_CAST 1 << 7)
+#define MSU_CORECLK_TST         (UINT64_CAST 1 << 7)
+#define MSU_CORECLK_SHFT        6       /* You don't wanna know             */
+#define MSU_CORECLK_MASK        (UINT64_CAST 1 << 6)
+#define MSU_CORECLK             (UINT64_CAST 1 << 6)
+#define MSU_NETSYNC_SHFT        5       /* You don't wanna know             */
+#define MSU_NETSYNC_MASK        (UINT64_CAST 1 << 5)
+#define MSU_NETSYNC             (UINT64_CAST 1 << 5)
+#define MSU_FPROMRDY_SHFT       4       /* Flash PROM ready bit             */
+#define MSU_FPROMRDY_MASK       (UINT64_CAST 1 << 4)
+#define MSU_FPROMRDY            (UINT64_CAST 1 << 4)
+#define MSU_I2CINTR_SHFT                3       /* I2C interrupt bit   */
+#define MSU_I2CINTR_MASK                (UINT64_CAST 1 << 3)
+#define MSU_I2CINTR             (UINT64_CAST 1 << 3)
+#define MSU_SLOTID_MASK         0xff
+#define MSU_SN0_SLOTID_SHFT     0       /* Slot ID                          */
+#define MSU_SN0_SLOTID_MASK     (UINT64_CAST 7)
+#define MSU_SN00_SLOTID_SHFT    7
+#define MSU_SN00_SLOTID_MASK    (UINT64_CAST 0x80)
+
+#define MSU_PIMM_PSC_SHFT       4
+#define MSU_PIMM_PSC_MASK       (0xf << MSU_PIMM_PSC_SHFT)
+
+/* MD_MIG_DIFF_THRESH bit definitions */
+
+#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_DIFF_THRES_VALID_SHFT 63
+#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
+
+/* MD_MIG_VALUE_THRESH bit definitions */
+
+#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_VALUE_THRES_VALID_SHFT 63
+#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
+
+/* MD_MIG_CANDIDATE bit definitions */
+
+#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_CANDIDATE_VALID_SHFT 63
+#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
+#define MD_MIG_CANDIDATE_TYPE_SHFT 30
+#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
+#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
+#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
+#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
+#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
+#define MD_MIG_CANDIDATE_NODEID_SHFT 20
+#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
+#define MD_MIG_CANDIDATE_ADDR_SHFT 14  /* The address starts at bit 14 */
+
+/* Other MD definitions */
+
+#define MD_BANK_SHFT            29                      /* log2(512 MB)     */
+#define MD_BANK_MASK            (UINT64_CAST 7 << 29)
+#define MD_BANK_SIZE            (UINT64_CAST 1 << MD_BANK_SHFT)   /* 512 MB */
+#define MD_BANK_OFFSET(_b)      (UINT64_CAST (_b) << MD_BANK_SHFT)
+
+/*
+ * The following definitions cover the bit field definitions for the
+ * various MD registers.  For multi-bit registers, we define both
+ * a shift amount and a mask value.  By convention, if you want to
+ * isolate a field, you should mask the field and then shift it down,
+ * since this makes the masks useful without a shift.
+ */
+
+/* Directory entry states for both premium and standard SIMMs. */
+
+#define MD_DIR_SHARED           (UINT64_CAST 0x0)       /* 000 */
+#define MD_DIR_POISONED         (UINT64_CAST 0x1)       /* 001 */
+#define MD_DIR_EXCLUSIVE        (UINT64_CAST 0x2)       /* 010 */
+#define MD_DIR_BUSY_SHARED      (UINT64_CAST 0x3)       /* 011 */
+#define MD_DIR_BUSY_EXCL        (UINT64_CAST 0x4)       /* 100 */
+#define MD_DIR_WAIT             (UINT64_CAST 0x5)       /* 101 */
+#define MD_DIR_UNOWNED          (UINT64_CAST 0x7)       /* 111 */
+
+/*
+ * The MD_DIR_FORCE_ECC bit can be added directory entry write data
+ * to forcing the ECC to be written as-is instead of recalculated.
+ */
+
+#define MD_DIR_FORCE_ECC        (UINT64_CAST 1 << 63)
+
+/*
+ * Premium SIMM directory entry shifts and masks.  Each is valid only in the
+ * context(s) indicated, where A, B, and C indicate the directory entry format
+ * as shown, and low and/or high indicates which double-word of the entry.
+ *
+ * Format A:  STATE = shared, FINE = 1
+ * Format B:  STATE = shared, FINE = 0
+ * Format C:  STATE != shared (FINE must be 0)
+ */
+
+#define MD_PDIR_MASK            0xffffffffffff          /* Whole entry      */
+#define MD_PDIR_ECC_SHFT        0                       /* ABC low or high  */
+#define MD_PDIR_ECC_MASK        0x7f
+#define MD_PDIR_PRIO_SHFT       8                       /* ABC low          */
+#define MD_PDIR_PRIO_MASK       (0xf << 8)
+#define MD_PDIR_AX_SHFT         7                       /* ABC low          */
+#define MD_PDIR_AX_MASK         (1 << 7)
+#define MD_PDIR_AX              (1 << 7)
+#define MD_PDIR_FINE_SHFT       12                      /* ABC low          */
+#define MD_PDIR_FINE_MASK       (1 << 12)
+#define MD_PDIR_FINE            (1 << 12)
+#define MD_PDIR_OCT_SHFT        13                      /* A low            */
+#define MD_PDIR_OCT_MASK        (7 << 13)
+#define MD_PDIR_STATE_SHFT      13                      /* BC low           */
+#define MD_PDIR_STATE_MASK      (7 << 13)
+#define MD_PDIR_ONECNT_SHFT     16                      /* BC low           */
+#define MD_PDIR_ONECNT_MASK     (0x3f << 16)
+#define MD_PDIR_PTR_SHFT        22                      /* C low            */
+#define MD_PDIR_PTR_MASK        (UINT64_CAST 0x7ff << 22)
+#define MD_PDIR_VECMSB_SHFT     22                      /* AB low           */
+#define MD_PDIR_VECMSB_BITMASK  0x3ffffff
+#define MD_PDIR_VECMSB_BITSHFT  27
+#define MD_PDIR_VECMSB_MASK     (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
+#define MD_PDIR_CWOFF_SHFT      7                       /* C high           */
+#define MD_PDIR_CWOFF_MASK      (7 << 7)
+#define MD_PDIR_VECLSB_SHFT     10                      /* AB high          */
+#define MD_PDIR_VECLSB_BITMASK  (UINT64_CAST 0x3fffffffff)
+#define MD_PDIR_VECLSB_BITSHFT  0
+#define MD_PDIR_VECLSB_MASK     (MD_PDIR_VECLSB_BITMASK << 10)
+
+/*
+ * Directory initialization values
+ */
+
+#define MD_PDIR_INIT_LO         (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
+                                 MD_PDIR_AX)
+#define MD_PDIR_INIT_HI         0
+#define MD_PDIR_INIT_PROT       (MD_PROT_RW << MD_PPROT_IO_SHFT | \
+                                 MD_PROT_RW << MD_PPROT_SHFT)
+
+/*
+ * Standard SIMM directory entry shifts and masks.  Each is valid only in the
+ * context(s) indicated, where A and C indicate the directory entry format
+ * as shown, and low and/or high indicates which double-word of the entry.
+ *
+ * Format A:  STATE == shared
+ * Format C:  STATE != shared
+ */
+
+#define MD_SDIR_MASK            0xffff                  /* Whole entry      */
+#define MD_SDIR_ECC_SHFT        0                       /* AC low or high   */
+#define MD_SDIR_ECC_MASK        0x1f
+#define MD_SDIR_PRIO_SHFT       6                       /* AC low           */
+#define MD_SDIR_PRIO_MASK       (1 << 6)
+#define MD_SDIR_AX_SHFT         5                       /* AC low           */
+#define MD_SDIR_AX_MASK         (1 << 5)
+#define MD_SDIR_AX              (1 << 5)
+#define MD_SDIR_STATE_SHFT      7                       /* AC low           */
+#define MD_SDIR_STATE_MASK      (7 << 7)
+#define MD_SDIR_PTR_SHFT        10                      /* C low            */
+#define MD_SDIR_PTR_MASK        (0x3f << 10)
+#define MD_SDIR_CWOFF_SHFT      5                       /* C high           */
+#define MD_SDIR_CWOFF_MASK      (7 << 5)
+#define MD_SDIR_VECMSB_SHFT     11                      /* A low            */
+#define MD_SDIR_VECMSB_BITMASK  0x1f
+#define MD_SDIR_VECMSB_BITSHFT  7
+#define MD_SDIR_VECMSB_MASK     (MD_SDIR_VECMSB_BITMASK << 11)
+#define MD_SDIR_VECLSB_SHFT     5                       /* A high           */
+#define MD_SDIR_VECLSB_BITMASK  0x7ff
+#define MD_SDIR_VECLSB_BITSHFT  0
+#define MD_SDIR_VECLSB_MASK     (MD_SDIR_VECLSB_BITMASK << 5)
+
+/*
+ * Directory initialization values
+ */
+
+#define MD_SDIR_INIT_LO         (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
+                                 MD_SDIR_AX)
+#define MD_SDIR_INIT_HI         0
+#define MD_SDIR_INIT_PROT       (MD_PROT_RW << MD_SPROT_SHFT)
+
+/* Protection and migration field values */
+
+#define MD_PROT_RW              (UINT64_CAST 0x6)
+#define MD_PROT_RO              (UINT64_CAST 0x3)
+#define MD_PROT_NO              (UINT64_CAST 0x0)
+#define MD_PROT_BAD             (UINT64_CAST 0x5)
+
+/* Premium SIMM protection entry shifts and masks. */
+
+#define MD_PPROT_SHFT           0                       /* Prot. field      */
+#define MD_PPROT_MASK           7
+#define MD_PPROT_MIGMD_SHFT     3                       /* Migration mode   */
+#define MD_PPROT_MIGMD_MASK     (3 << 3)
+#define MD_PPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_PPROT_REFCNT_WIDTH   0x7ffff
+#define MD_PPROT_REFCNT_MASK    (MD_PPROT_REFCNT_WIDTH << 5)
+
+#define MD_PPROT_IO_SHFT        45                      /* I/O Prot field   */
+#define MD_PPROT_IO_MASK        (UINT64_CAST 7 << 45)
+
+/* Standard SIMM protection entry shifts and masks. */
+
+#define MD_SPROT_SHFT           0                       /* Prot. field      */
+#define MD_SPROT_MASK           7
+#define MD_SPROT_MIGMD_SHFT     3                       /* Migration mode   */
+#define MD_SPROT_MIGMD_MASK     (3 << 3)
+#define MD_SPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_SPROT_REFCNT_WIDTH   0x7ff
+#define MD_SPROT_REFCNT_MASK    (MD_SPROT_REFCNT_WIDTH << 5)
+
+/* Migration modes used in protection entries */
+
+#define MD_PROT_MIGMD_IREL      (UINT64_CAST 0x3 << 3)
+#define MD_PROT_MIGMD_IABS      (UINT64_CAST 0x2 << 3)
+#define MD_PROT_MIGMD_PREL      (UINT64_CAST 0x1 << 3)
+#define MD_PROT_MIGMD_OFF       (UINT64_CAST 0x0 << 3)
+
+
+/*
+ * Operations on page migration threshold register
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * LED register macros
+ */
+
+#define CPU_LED_ADDR(_nasid, _slice)                                       \
+        (private.p_sn00 ?                                                  \
+         REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \
+         REMOTE_HUB_ADDR((_nasid), MD_LED0    + ((_slice) << 3)))
+
+#define SET_CPU_LEDS(_nasid, _slice,  _val)                                \
+        (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
+
+#define SET_MY_LEDS(_v)                                                    \
+        SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
+
+/*
+ * Operations on Memory/Directory DIMM control register
+ */
+
+#define DIRTYPE_PREMIUM 1
+#define DIRTYPE_STANDARD 0
+#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
+        (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
+        MMC_DIR_PREMIUM_SHFT)
+
+
+/*
+ * Operations on page migration count difference and absolute threshold
+ * registers
+ */
+
+#define MD_MIG_DIFF_THRESH_GET(region) ( \
+        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
+        MD_MIG_DIFF_THRES_VALUE_MASK)
+
+#define MD_MIG_DIFF_THRESH_SET(region, value) (                         \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                MD_MIG_DIFF_THRES_VALID_MASK | (value)))
+
+#define MD_MIG_DIFF_THRESH_DISABLE(region) (                    \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
+                             & ~MD_MIG_DIFF_THRES_VALID_MASK))
+
+#define MD_MIG_DIFF_THRESH_ENABLE(region) (                     \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
+                             | MD_MIG_DIFF_THRES_VALID_MASK))
+
+#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) (                         \
+        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) &                    \
+               MD_MIG_DIFF_THRES_VALID_MASK)
+
+#define MD_MIG_VALUE_THRESH_GET(region) (                               \
+        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &  \
+        MD_MIG_VALUE_THRES_VALUE_MASK)
+
+#define MD_MIG_VALUE_THRESH_SET(region, value) (                        \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                MD_MIG_VALUE_THRES_VALID_MASK | (value)))
+
+#define MD_MIG_VALUE_THRESH_DISABLE(region) (                   \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH)               \
+                             & ~MD_MIG_VALUE_THRES_VALID_MASK))
+
+#define MD_MIG_VALUE_THRESH_ENABLE(region) (                    \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH)             \
+                             | MD_MIG_VALUE_THRES_VALID_MASK))
+
+#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) (                        \
+        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &                    \
+               MD_MIG_VALUE_THRES_VALID_MASK)
+
+/*
+ * Operations on page migration candidate register
+ */
+
+#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
+        REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
+
+#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
+
+#define MD_MIG_CANDIDATE_NODEID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
+
+#define MD_MIG_CANDIDATE_TYPE(value) ( \
+        ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
+
+#define MD_MIG_CANDIDATE_VALID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
+
+/*
+ * Macros to retrieve fields in the protection entry
+ */
+
+/* for Premium SIMM */
+#define MD_PPROT_REFCNT_GET(value) ( \
+        ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
+
+#define MD_PPROT_MIGMD_GET(value) ( \
+        ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
+
+/* for Standard SIMM */
+#define MD_SPROT_REFCNT_GET(value) ( \
+        ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
+
+#define MD_SPROT_MIGMD_GET(value) ( \
+        ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
+
+/*
+ * Format of dir_error, mem_error, protocol_error and misc_error registers
+ */
+
+struct dir_error_reg {
+        u64     uce_vld:   1,   /*    63: valid directory uce   */
+                ae_vld:    1,   /*    62: valid dir prot ecc error */
+                ce_vld:    1,   /*    61: valid correctable ECC err*/
+                rsvd1:    19,   /* 60-42: reserved              */
+                bad_prot:  3,   /* 41-39: encoding, bad access rights*/
+                bad_syn:   7,   /* 38-32: bad dir syndrome      */
+                rsvd2:     2,   /* 31-30: reserved              */
+                hspec_addr:27,  /* 29-03: bddir space bad entry */
+                uce_ovr:   1,   /*     2: multiple dir uce's    */
+                ae_ovr:    1,   /*     1: multiple prot ecc errs*/
+                ce_ovr:    1;   /*     0: multiple correctable errs */
+};
+
+typedef union md_dir_error {
+        u64     derr_reg;       /* the entire register          */
+        struct dir_error_reg derr_fmt;  /* the register format          */
+} md_dir_error_t;
+
+
+struct mem_error_reg {
+        u64     uce_vld:   1,   /*    63: valid memory uce      */
+                ce_vld:    1,   /*    62: valid correctable ECC err*/
+                rsvd1:    22,   /* 61-40: reserved              */
+                bad_syn:   8,   /* 39-32: bad mem ecc syndrome  */
+                address:  29,   /* 31-03: bad entry pointer     */
+                rsvd2:     1,   /*     2: reserved              */
+                uce_ovr:   1,   /*     1: multiple mem uce's    */
+                ce_ovr:    1;   /*     0: multiple correctable errs */
+};
+
+
+typedef union md_mem_error {
+        u64     merr_reg;       /* the entire register          */
+        struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */
+} md_mem_error_t;
+
+
+struct proto_error_reg {
+        u64     valid:     1,   /*    63: valid protocol error  */
+                rsvd1:     2,   /* 62-61: reserved              */
+                initiator:11,   /* 60-50: id of request initiator*/
+                backoff:   2,   /* 49-48: backoff control       */
+                msg_type:  8,   /* 47-40: type of request       */
+                access:    2,   /* 39-38: access rights of initiator*/
+                priority:  1,   /*    37: priority level of requestor*/
+                dir_state: 4,   /* 36-33: state of directory    */
+                pointer_me:1,   /*    32: initiator same as dir ptr */
+                address:  29,   /* 31-03: request address       */
+                rsvd2:     2,   /* 02-01: reserved              */
+                overrun:   1;   /*     0: multiple protocol errs */
+};
+
+typedef union md_proto_error {
+        u64     perr_reg;       /* the entire register          */
+        struct proto_error_reg  perr_fmt; /* format of the register     */
+} md_proto_error_t;
+
+
+struct md_sdir_high_fmt {
+        unsigned short sd_hi_bvec : 11,
+                       sd_hi_ecc  : 5;
+};
+
+
+typedef union md_sdir_high {
+        /* The 16 bits of standard directory, upper word */
+        unsigned short sd_hi_val;
+        struct  md_sdir_high_fmt sd_hi_fmt;
+}md_sdir_high_t;
+
+
+struct md_sdir_low_shared_fmt {
+        /* The meaning of lower directory, shared */
+        unsigned short  sds_lo_bvec  : 5,
+                        sds_lo_unused: 1,
+                        sds_lo_state : 3,
+                        sds_lo_prio  : 1,
+                        sds_lo_ax    : 1,
+                        sds_lo_ecc   : 5;
+};
+
+struct md_sdir_low_exclusive_fmt {
+        /* The meaning of lower directory, exclusive */
+        unsigned short  sde_lo_ptr   : 6,
+                        sde_lo_state : 3,
+                        sde_lo_prio  : 1,
+                        sde_lo_ax    : 1,
+                        sde_lo_ecc   : 5;
+};
+
+
+typedef union md_sdir_low {
+        /* The 16 bits of standard directory, lower word */
+        unsigned short  sd_lo_val;
+        struct  md_sdir_low_exclusive_fmt sde_lo_fmt;
+        struct  md_sdir_low_shared_fmt sds_lo_fmt;
+}md_sdir_low_t;
+
+
+
+struct md_pdir_high_fmt {
+        u64     pd_hi_unused   : 16,
+                pd_hi_bvec     : 38,
+                pd_hi_unused1  : 3,
+                pd_hi_ecc      : 7;
+};
+
+
+typedef union md_pdir_high {
+        /* The 48 bits of standard directory, upper word */
+        u64     pd_hi_val;
+        struct md_pdir_high_fmt pd_hi_fmt;
+}md_pdir_high_t;
+
+
+struct md_pdir_low_shared_fmt {
+        /* The meaning of lower directory, shared */
+        u64     pds_lo_unused   : 16,
+                pds_lo_bvec     : 26,
+                pds_lo_cnt      :  6,
+                pds_lo_state    :  3,
+                pds_lo_ste      :  1,
+                pds_lo_prio     :  4,
+                pds_lo_ax       :  1,
+                pds_lo_ecc      :  7;
+};
+
+struct md_pdir_low_exclusive_fmt {
+        /* The meaning of lower directory, exclusive */
+        u64     pde_lo_unused   : 31,
+                pde_lo_ptr      : 11,
+                pde_lo_unused1  :  6,
+                pde_lo_state    :  3,
+                pde_lo_ste      :  1,
+                pde_lo_prio     :  4,
+                pde_lo_ax       :  1,
+                pde_lo_ecc      :  7;
+};
+
+
+typedef union md_pdir_loent {
+        /* The 48 bits of premium directory, lower word */
+        u64     pd_lo_val;
+        struct md_pdir_low_exclusive_fmt pde_lo_fmt;
+        struct md_pdir_low_shared_fmt   pds_lo_fmt;
+}md_pdir_low_t;
+
+
+/*
+ *   the following two "union" definitions and two
+ *   "struct" definitions are used in vmdump.c to
+ *   represent directory memory information.
+ */
+
+typedef union   md_dir_high     {
+        md_sdir_high_t  md_sdir_high;
+        md_pdir_high_t  md_pdir_high;
+} md_dir_high_t;
+
+typedef union   md_dir_low      {
+        md_sdir_low_t   md_sdir_low;
+        md_pdir_low_t   md_pdir_low;
+} md_dir_low_t;
+
+typedef struct  bddir_entry     {
+        md_dir_low_t    md_dir_low;
+        md_dir_high_t   md_dir_high;
+} bddir_entry_t;
+
+typedef struct  dir_mem_entry   {
+        u64             prcpf[MAX_REGIONS];
+        bddir_entry_t   directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
+} dir_mem_entry_t;
+
+
+
+typedef union md_perf_sel {
+        u64     perf_sel_reg;
+        struct  {
+                u64     perf_rsvd : 60,
+                        perf_en   :  1,
+                        perf_sel  :  3;
+        } perf_sel_bits;
+} md_perf_sel_t;
+
+typedef union md_perf_cnt {
+        u64     perf_cnt;
+        struct  {
+                u64     perf_rsvd : 44,
+                        perf_cnt  : 20;
+        } perf_cnt_bits;
+} md_perf_cnt_t;
+
+
+#endif /* !__ASSEMBLY__ */
+
+
+#define DIR_ERROR_VALID_MASK    0xe000000000000000
+#define DIR_ERROR_VALID_SHFT    61
+#define DIR_ERROR_VALID_UCE     0x8000000000000000
+#define DIR_ERROR_VALID_AE      0x4000000000000000
+#define DIR_ERROR_VALID_CE      0x2000000000000000
+
+#define MEM_ERROR_VALID_MASK    0xc000000000000000
+#define MEM_ERROR_VALID_SHFT    62
+#define MEM_ERROR_VALID_UCE     0x8000000000000000
+#define MEM_ERROR_VALID_CE      0x4000000000000000
+
+#define PROTO_ERROR_VALID_MASK  0x8000000000000000
+
+#define MISC_ERROR_VALID_MASK   0x3ff
+
+/*
+ * Mask for hspec address that is stored in the dir error register.
+ * This represents bits 29 through 3.
+ */
+#define DIR_ERR_HSPEC_MASK      0x3ffffff8
+#define ERROR_HSPEC_MASK        0x3ffffff8
+#define ERROR_HSPEC_SHFT        3
+#define ERROR_ADDR_MASK         0xfffffff8
+#define ERROR_ADDR_SHFT         3
+
+/*
+ * MD_MISC_ERROR register defines.
+ */
+
+#define MMCE_VALID_MASK         0x3ff
+#define MMCE_ILL_MSG_SHFT       8
+#define MMCE_ILL_MSG_MASK       (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
+#define MMCE_ILL_REV_SHFT       6
+#define MMCE_ILL_REV_MASK       (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
+#define MMCE_LONG_PACK_SHFT     4
+#define MMCE_LONG_PACK_MASK     (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
+#define MMCE_SHORT_PACK_SHFT    2
+#define MMCE_SHORT_PACK_MASK    (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
+#define MMCE_BAD_DATA_SHFT      0
+#define MMCE_BAD_DATA_MASK      (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
+
+
+#define MD_PERF_COUNTERS        6
+#define MD_PERF_SETS            6
+
+#define MEM_DIMM_MASK                           0xe0000000
+#define MEM_DIMM_SHFT                           29
+
+#endif /* _ASM_SN_SN0_HUBMD_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubni.h b/arch/mips/include/asm/sn/sn0/hubni.h
new file mode 100644
index 000000000000..b40d3ef97a12
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubni.h
@@ -0,0 +1,255 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
+ *
+ * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SGI_SN0_HUBNI_H
+#define _ASM_SGI_SN0_HUBNI_H
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif
+
+/*
+ * Hub Network Interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ */
+
+#define NI_BASE                 0x600000
+#define NI_BASE_TABLES          0x630000
+
+#define NI_STATUS_REV_ID        0x600000 /* Hub network status, rev, and ID */
+#define NI_PORT_RESET           0x600008 /* Reset the network interface     */
+#define NI_PROTECTION           0x600010 /* NI register access permissions  */
+#define NI_GLOBAL_PARMS         0x600018 /* LLP parameters                  */
+#define NI_SCRATCH_REG0         0x600100 /* Scratch register 0 (64 bits)    */
+#define NI_SCRATCH_REG1         0x600108 /* Scratch register 1 (64 bits)    */
+#define NI_DIAG_PARMS           0x600110 /* Parameters for diags            */
+
+#define NI_VECTOR_PARMS         0x600200 /* Vector PIO routing parameters   */
+#define NI_VECTOR               0x600208 /* Vector PIO route                */
+#define NI_VECTOR_DATA          0x600210 /* Vector PIO data                 */
+#define NI_VECTOR_STATUS        0x600300 /* Vector PIO return status        */
+#define NI_RETURN_VECTOR        0x600308 /* Vector PIO return vector        */
+#define NI_VECTOR_READ_DATA     0x600310 /* Vector PIO read data            */
+#define NI_VECTOR_CLEAR         0x600380 /* Vector PIO read & clear status  */
+
+#define NI_IO_PROTECT           0x600400 /* PIO protection bits             */
+#define NI_IO_PROT_OVRRD        0x600408 /* PIO protection bit override     */
+
+#define NI_AGE_CPU0_MEMORY      0x600500 /* CPU 0 memory age control        */
+#define NI_AGE_CPU0_PIO         0x600508 /* CPU 0 PIO age control           */
+#define NI_AGE_CPU1_MEMORY      0x600510 /* CPU 1 memory age control        */
+#define NI_AGE_CPU1_PIO         0x600518 /* CPU 1 PIO age control           */
+#define NI_AGE_GBR_MEMORY       0x600520 /* GBR memory age control          */
+#define NI_AGE_GBR_PIO          0x600528 /* GBR PIO age control             */
+#define NI_AGE_IO_MEMORY        0x600530 /* IO memory age control           */
+#define NI_AGE_IO_PIO           0x600538 /* IO PIO age control              */
+#define NI_AGE_REG_MIN          NI_AGE_CPU0_MEMORY
+#define NI_AGE_REG_MAX          NI_AGE_IO_PIO
+
+#define NI_PORT_PARMS           0x608000 /* LLP Parameters                  */
+#define NI_PORT_ERROR           0x608008 /* LLP Errors                      */
+#define NI_PORT_ERROR_CLEAR     0x608088 /* Clear the error bits            */
+
+#define NI_META_TABLE0          0x638000 /* First meta routing table entry  */
+#define NI_META_TABLE(_x)       (NI_META_TABLE0 + (8 * (_x)))
+#define NI_META_ENTRIES         32
+
+#define NI_LOCAL_TABLE0         0x638100 /* First local routing table entry */
+#define NI_LOCAL_TABLE(_x)      (NI_LOCAL_TABLE0 + (8 * (_x)))
+#define NI_LOCAL_ENTRIES        16
+
+/*
+ * NI_STATUS_REV_ID mask and shift definitions
+ * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
+ */
+
+#define NSRI_8BITMODE_SHFT      30
+#define NSRI_8BITMODE_MASK      (UINT64_CAST 0x1 << 30)
+#define NSRI_LINKUP_SHFT        29
+#define NSRI_LINKUP_MASK        (UINT64_CAST 0x1 << 29)
+#define NSRI_DOWNREASON_SHFT    28              /* 0=failed, 1=never came   */
+#define NSRI_DOWNREASON_MASK    (UINT64_CAST 0x1 << 28) /*    out of reset. */
+#define NSRI_MORENODES_SHFT     18
+#define NSRI_MORENODES_MASK     (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
+#define  MORE_MEMORY            0
+#define  MORE_NODES             1
+#define NSRI_REGIONSIZE_SHFT    17
+#define NSRI_REGIONSIZE_MASK    (UINT64_CAST 1 << 17)   /* Granularity      */
+#define  REGIONSIZE_FINE        1
+#define  REGIONSIZE_COARSE      0
+#define NSRI_NODEID_SHFT        8
+#define NSRI_NODEID_MASK        (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID    */
+#define NSRI_REV_SHFT           4
+#define NSRI_REV_MASK           (UINT64_CAST 0xf << 4)  /* Chip Revision    */
+#define NSRI_CHIPID_SHFT        0
+#define NSRI_CHIPID_MASK        (UINT64_CAST 0xf)       /* Chip type ID     */
+
+/*
+ * In fine mode, each node is a region.  In coarse mode, there are
+ * eight nodes per region.
+ */
+#define NASID_TO_FINEREG_SHFT   0
+#define NASID_TO_COARSEREG_SHFT 3
+
+/* NI_PORT_RESET mask definitions */
+
+#define NPR_PORTRESET           (UINT64_CAST 1 << 7)    /* Send warm reset  */
+#define NPR_LINKRESET           (UINT64_CAST 1 << 1)    /* Send link reset  */
+#define NPR_LOCALRESET          (UINT64_CAST 1)         /* Reset entire hub */
+
+/* NI_PROTECTION mask and shift definitions */
+
+#define NPROT_RESETOK           (UINT64_CAST 1)
+
+/* NI_GLOBAL_PARMS mask and shift definitions */
+
+#define NGP_MAXRETRY_SHFT       48              /* Maximum retries          */
+#define NGP_MAXRETRY_MASK       (UINT64_CAST 0x3ff << 48)
+#define NGP_TAILTOWRAP_SHFT     32              /* Tail timeout wrap        */
+#define NGP_TAILTOWRAP_MASK     (UINT64_CAST 0xffff << 32)
+
+#define NGP_CREDITTOVAL_SHFT    16              /* Tail timeout wrap        */
+#define NGP_CREDITTOVAL_MASK    (UINT64_CAST 0xf << 16)
+#define NGP_TAILTOVAL_SHFT      4               /* Tail timeout value       */
+#define NGP_TAILTOVAL_MASK      (UINT64_CAST 0xf << 4)
+
+/* NI_DIAG_PARMS mask and shift definitions */
+
+#define NDP_PORTTORESET         (UINT64_CAST 1 << 18)   /* Port tmout reset */
+#define NDP_LLP8BITMODE         (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */
+#define NDP_PORTDISABLE         (UINT64_CAST 1 <<  6)   /* Port disable     */
+#define NDP_SENDERROR           (UINT64_CAST 1)         /* Send data error  */
+
+/*
+ * NI_VECTOR_PARMS mask and shift definitions.
+ * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
+ */
+
+#define NVP_PIOID_SHFT          40
+#define NVP_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
+#define NVP_WRITEID_SHFT        32
+#define NVP_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define NVP_ADDRESS_MASK        (UINT64_CAST 0xffff8)   /* Bits 19:3        */
+#define NVP_TYPE_SHFT           0
+#define NVP_TYPE_MASK           (UINT64_CAST 0x3)
+
+/* NI_VECTOR_STATUS mask and shift definitions */
+
+#define NVS_VALID               (UINT64_CAST 1 << 63)
+#define NVS_OVERRUN             (UINT64_CAST 1 << 62)
+#define NVS_TARGET_SHFT         51
+#define NVS_TARGET_MASK         (UINT64_CAST 0x3ff << 51)
+#define NVS_PIOID_SHFT          40
+#define NVS_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
+#define NVS_WRITEID_SHFT        32
+#define NVS_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define NVS_ADDRESS_MASK        (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
+#define NVS_TYPE_SHFT           0
+#define NVS_TYPE_MASK           (UINT64_CAST 0x7)
+#define NVS_ERROR_MASK          (UINT64_CAST 0x4)  /* bit set means error */
+
+
+#define  PIOTYPE_READ           0       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
+#define  PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
+#define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
+#define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
+
+/* NI_AGE_XXX mask and shift definitions */
+
+#define NAGE_VCH_SHFT           10
+#define NAGE_VCH_MASK           (UINT64_CAST 3 << 10)
+#define NAGE_CC_SHFT            8
+#define NAGE_CC_MASK            (UINT64_CAST 3 << 8)
+#define NAGE_AGE_SHFT           0
+#define NAGE_AGE_MASK           (UINT64_CAST 0xff)
+#define NAGE_MASK               (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
+
+#define  VCHANNEL_A             0
+#define  VCHANNEL_B             1
+#define  VCHANNEL_ANY           2
+
+/* NI_PORT_PARMS mask and shift definitions */
+
+#define NPP_NULLTO_SHFT         10
+#define NPP_NULLTO_MASK         (UINT64_CAST 0x3f << 16)
+#define NPP_MAXBURST_SHFT       0
+#define NPP_MAXBURST_MASK       (UINT64_CAST 0x3ff)
+#define NPP_RESET_DFLT_HUB20    ((UINT64_CAST 1     << NPP_NULLTO_SHFT) | \
+                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
+#define NPP_RESET_DEFAULTS      ((UINT64_CAST 6     << NPP_NULLTO_SHFT) | \
+                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
+
+
+/* NI_PORT_ERROR mask and shift definitions */
+
+#define NPE_LINKRESET           (UINT64_CAST 1 << 37)
+#define NPE_INTERNALERROR       (UINT64_CAST 1 << 36)
+#define NPE_BADMESSAGE          (UINT64_CAST 1 << 35)
+#define NPE_BADDEST             (UINT64_CAST 1 << 34)
+#define NPE_FIFOOVERFLOW        (UINT64_CAST 1 << 33)
+#define NPE_CREDITTO_SHFT       28
+#define NPE_CREDITTO_MASK       (UINT64_CAST 0xf << 28)
+#define NPE_TAILTO_SHFT         24
+#define NPE_TAILTO_MASK         (UINT64_CAST 0xf << 24)
+#define NPE_RETRYCOUNT_SHFT     16
+#define NPE_RETRYCOUNT_MASK     (UINT64_CAST 0xff << 16)
+#define NPE_CBERRCOUNT_SHFT     8
+#define NPE_CBERRCOUNT_MASK     (UINT64_CAST 0xff << 8)
+#define NPE_SNERRCOUNT_SHFT     0
+#define NPE_SNERRCOUNT_MASK     (UINT64_CAST 0xff << 0)
+#define NPE_MASK                0x3effffffff
+
+#define NPE_COUNT_MAX           0xff
+
+#define NPE_FATAL_ERRORS        (NPE_LINKRESET | NPE_INTERNALERROR |    \
+                                 NPE_BADMESSAGE | NPE_BADDEST |         \
+                                 NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
+                                 NPE_TAILTO_MASK)
+
+/* NI_META_TABLE mask and shift definitions */
+
+#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
+
+/* NI_LOCAL_TABLE mask and shift definitions */
+
+#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
+
+#ifndef __ASSEMBLY__
+
+typedef union   hubni_port_error_u {
+        u64     nipe_reg_value;
+        struct {
+            u64 nipe_rsvd:      26,     /* unused */
+                nipe_lnk_reset:  1,     /* link reset */
+                nipe_intl_err:   1,     /* internal error */
+                nipe_bad_msg:    1,     /* bad message */
+                nipe_bad_dest:   1,     /* bad dest     */
+                nipe_fifo_ovfl:  1,     /* fifo overflow */
+                nipe_rsvd1:      1,     /* unused */
+                nipe_credit_to:  4,     /* credit timeout */
+                nipe_tail_to:    4,     /* tail timeout */
+                nipe_retry_cnt:  8,     /* retry error count */
+                nipe_cb_cnt:     8,     /* checkbit error count */
+                nipe_sn_cnt:     8;     /* sequence number count */
+        } nipe_fields_s;
+} hubni_port_error_t;
+
+#define NI_LLP_RETRY_MAX        0xff
+#define NI_LLP_CB_MAX           0xff
+#define NI_LLP_SN_MAX           0xff
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_SGI_SN0_HUBNI_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubpi.h b/arch/mips/include/asm/sn/sn0/hubpi.h
new file mode 100644
index 000000000000..e39f5f9da040
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubpi.h
@@ -0,0 +1,409 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUBPI_H
+#define _ASM_SN_SN0_HUBPI_H
+
+#include <linux/types.h>
+
+/*
+ * Hub I/O interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ * All register "addresses" are actually offsets.  Use the LOCAL_HUB
+ * or REMOTE_HUB macros to synthesize an actual address
+ */
+
+#define PI_BASE                 0x000000
+
+/* General protection and control registers */
+
+#define PI_CPU_PROTECT          0x000000 /* CPU Protection                  */
+#define PI_PROT_OVERRD          0x000008 /* Clear CPU Protection bit        */
+#define PI_IO_PROTECT           0x000010 /* Interrupt Pending Protection    */
+#define PI_REGION_PRESENT       0x000018 /* Indicates whether region exists */
+#define PI_CPU_NUM              0x000020 /* CPU Number ID                   */
+#define PI_CALIAS_SIZE          0x000028 /* Cached Alias Size               */
+#define PI_MAX_CRB_TIMEOUT      0x000030 /* Maximum Timeout for CRB         */
+#define PI_CRB_SFACTOR          0x000038 /* Scale factor for CRB timeout    */
+
+/* CALIAS values */
+#define PI_CALIAS_SIZE_0        0
+#define PI_CALIAS_SIZE_4K       1
+#define PI_CALIAS_SIZE_8K       2
+#define PI_CALIAS_SIZE_16K      3
+#define PI_CALIAS_SIZE_32K      4
+#define PI_CALIAS_SIZE_64K      5
+#define PI_CALIAS_SIZE_128K     6
+#define PI_CALIAS_SIZE_256K     7
+#define PI_CALIAS_SIZE_512K     8
+#define PI_CALIAS_SIZE_1M       9
+#define PI_CALIAS_SIZE_2M       10
+#define PI_CALIAS_SIZE_4M       11
+#define PI_CALIAS_SIZE_8M       12
+#define PI_CALIAS_SIZE_16M      13
+#define PI_CALIAS_SIZE_32M      14
+#define PI_CALIAS_SIZE_64M      15
+
+/* Processor control and status checking */
+
+#define PI_CPU_PRESENT_A        0x000040 /* CPU Present A                   */
+#define PI_CPU_PRESENT_B        0x000048 /* CPU Present B                   */
+#define PI_CPU_ENABLE_A         0x000050 /* CPU Enable A                    */
+#define PI_CPU_ENABLE_B         0x000058 /* CPU Enable B                    */
+#define PI_REPLY_LEVEL          0x000060 /* Reply Level                     */
+#define PI_HARDRESET_BIT        0x020068 /* Bit cleared by s/w on SR        */
+#define PI_NMI_A                0x000070 /* NMI to CPU A                    */
+#define PI_NMI_B                0x000078 /* NMI to CPU B                    */
+#define PI_NMI_OFFSET           (PI_NMI_B - PI_NMI_A)
+#define PI_SOFTRESET            0x000080 /* Softreset (to both CPUs)        */
+
+/* Regular Interrupt register checking.  */
+
+#define PI_INT_PEND_MOD         0x000090 /* Write to set pending ints       */
+#define PI_INT_PEND0            0x000098 /* Read to get pending ints        */
+#define PI_INT_PEND1            0x0000a0 /* Read to get pending ints        */
+#define PI_INT_MASK0_A          0x0000a8 /* Interrupt Mask 0 for CPU A      */
+#define PI_INT_MASK1_A          0x0000b0 /* Interrupt Mask 1 for CPU A      */
+#define PI_INT_MASK0_B          0x0000b8 /* Interrupt Mask 0 for CPU B      */
+#define PI_INT_MASK1_B          0x0000c0 /* Interrupt Mask 1 for CPU B      */
+
+#define PI_INT_MASK_OFFSET      0x10     /* Offset from A to B              */
+
+/* Crosscall interrupts */
+
+#define PI_CC_PEND_SET_A        0x0000c8 /* CC Interrupt Pending Set, CPU A */
+#define PI_CC_PEND_SET_B        0x0000d0 /* CC Interrupt Pending Set, CPU B */
+#define PI_CC_PEND_CLR_A        0x0000d8 /* CC Interrupt Pending Clr, CPU A */
+#define PI_CC_PEND_CLR_B        0x0000e0 /* CC Interrupt Pending Clr, CPU B */
+#define PI_CC_MASK              0x0000e8 /* CC Interrupt mask               */
+
+#define PI_INT_SET_OFFSET       0x08     /* Offset from A to B              */
+
+/* Realtime Counter and Profiler control registers */
+
+#define PI_RT_COUNT             0x030100 /* Real Time Counter               */
+#define PI_RT_COMPARE_A         0x000108 /* Real Time Compare A             */
+#define PI_RT_COMPARE_B         0x000110 /* Real Time Compare B             */
+#define PI_PROFILE_COMPARE      0x000118 /* L5 int to both cpus when == RTC */
+#define PI_RT_PEND_A            0x000120 /* Set if RT int for A pending     */
+#define PI_RT_PEND_B            0x000128 /* Set if RT int for B pending     */
+#define PI_PROF_PEND_A          0x000130 /* Set if Prof int for A pending   */
+#define PI_PROF_PEND_B          0x000138 /* Set if Prof int for B pending   */
+#define PI_RT_EN_A              0x000140 /* RT int for CPU A enable         */
+#define PI_RT_EN_B              0x000148 /* RT int for CPU B enable         */
+#define PI_PROF_EN_A            0x000150 /* PROF int for CPU A enable       */
+#define PI_PROF_EN_B            0x000158 /* PROF int for CPU B enable       */
+#define PI_RT_LOCAL_CTRL        0x000160 /* RT control register             */
+#define PI_RT_FILTER_CTRL       0x000168 /* GCLK Filter control register    */
+
+#define PI_COUNT_OFFSET         0x08     /* A to B offset for all counts    */
+
+/* Built-In Self Test support */
+
+#define PI_BIST_WRITE_DATA      0x000200 /* BIST write data                 */
+#define PI_BIST_READ_DATA       0x000208 /* BIST read data                  */
+#define PI_BIST_COUNT_TARG      0x000210 /* BIST Count and Target           */
+#define PI_BIST_READY           0x000218 /* BIST Ready indicator            */
+#define PI_BIST_SHIFT_LOAD      0x000220 /* BIST control                    */
+#define PI_BIST_SHIFT_UNLOAD    0x000228 /* BIST control                    */
+#define PI_BIST_ENTER_RUN       0x000230 /* BIST control                    */
+
+/* Graphics control registers */
+
+#define PI_GFX_PAGE_A           0x000300 /* Graphics page A                 */
+#define PI_GFX_CREDIT_CNTR_A    0x000308 /* Graphics credit counter A       */
+#define PI_GFX_BIAS_A           0x000310 /* Graphics bias A                 */
+#define PI_GFX_INT_CNTR_A       0x000318 /* Graphics interrupt counter A    */
+#define PI_GFX_INT_CMP_A        0x000320 /* Graphics interrupt comparator A */
+#define PI_GFX_PAGE_B           0x000328 /* Graphics page B                 */
+#define PI_GFX_CREDIT_CNTR_B    0x000330 /* Graphics credit counter B       */
+#define PI_GFX_BIAS_B           0x000338 /* Graphics bias B                 */
+#define PI_GFX_INT_CNTR_B       0x000340 /* Graphics interrupt counter B    */
+#define PI_GFX_INT_CMP_B        0x000348 /* Graphics interrupt comparator B */
+
+#define PI_GFX_OFFSET           (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
+#define PI_GFX_PAGE_ENABLE      0x0000010000000000LL
+
+/* Error and timeout registers */
+#define PI_ERR_INT_PEND         0x000400 /* Error Interrupt Pending         */
+#define PI_ERR_INT_MASK_A       0x000408 /* Error Interrupt mask for CPU A  */
+#define PI_ERR_INT_MASK_B       0x000410 /* Error Interrupt mask for CPU B  */
+#define PI_ERR_STACK_ADDR_A     0x000418 /* Error stack address for CPU A   */
+#define PI_ERR_STACK_ADDR_B     0x000420 /* Error stack address for CPU B   */
+#define PI_ERR_STACK_SIZE       0x000428 /* Error Stack Size                */
+#define PI_ERR_STATUS0_A        0x000430 /* Error Status 0A                 */
+#define PI_ERR_STATUS0_A_RCLR   0x000438 /* Error Status 0A clear on read   */
+#define PI_ERR_STATUS1_A        0x000440 /* Error Status 1A                 */
+#define PI_ERR_STATUS1_A_RCLR   0x000448 /* Error Status 1A clear on read   */
+#define PI_ERR_STATUS0_B        0x000450 /* Error Status 0B                 */
+#define PI_ERR_STATUS0_B_RCLR   0x000458 /* Error Status 0B clear on read   */
+#define PI_ERR_STATUS1_B        0x000460 /* Error Status 1B                 */
+#define PI_ERR_STATUS1_B_RCLR   0x000468 /* Error Status 1B clear on read   */
+#define PI_SPOOL_CMP_A          0x000470 /* Spool compare for CPU A         */
+#define PI_SPOOL_CMP_B          0x000478 /* Spool compare for CPU B         */
+#define PI_CRB_TIMEOUT_A        0x000480 /* Timed out CRB entries for A     */
+#define PI_CRB_TIMEOUT_B        0x000488 /* Timed out CRB entries for B     */
+#define PI_SYSAD_ERRCHK_EN      0x000490 /* Enables SYSAD error checking    */
+#define PI_BAD_CHECK_BIT_A      0x000498 /* Force SYSAD check bit error     */
+#define PI_BAD_CHECK_BIT_B      0x0004a0 /* Force SYSAD check bit error     */
+#define PI_NACK_CNT_A           0x0004a8 /* Consecutive NACK counter        */
+#define PI_NACK_CNT_B           0x0004b0 /*     "       " for CPU B         */
+#define PI_NACK_CMP             0x0004b8 /* NACK count compare              */
+#define PI_STACKADDR_OFFSET     (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
+#define PI_ERRSTAT_OFFSET       (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
+#define PI_RDCLR_OFFSET         (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
+
+/* Bits in PI_ERR_INT_PEND */
+#define PI_ERR_SPOOL_CMP_B      0x00000001      /* Spool end hit high water */
+#define PI_ERR_SPOOL_CMP_A      0x00000002
+#define PI_ERR_SPUR_MSG_B       0x00000004      /* Spurious message intr.   */
+#define PI_ERR_SPUR_MSG_A       0x00000008
+#define PI_ERR_WRB_TERR_B       0x00000010      /* WRB TERR                 */
+#define PI_ERR_WRB_TERR_A       0x00000020
+#define PI_ERR_WRB_WERR_B       0x00000040      /* WRB WERR                 */
+#define PI_ERR_WRB_WERR_A       0x00000080
+#define PI_ERR_SYSSTATE_B       0x00000100      /* SysState parity error    */
+#define PI_ERR_SYSSTATE_A       0x00000200
+#define PI_ERR_SYSAD_DATA_B     0x00000400      /* SysAD data parity error  */
+#define PI_ERR_SYSAD_DATA_A     0x00000800
+#define PI_ERR_SYSAD_ADDR_B     0x00001000      /* SysAD addr parity error  */
+#define PI_ERR_SYSAD_ADDR_A     0x00002000
+#define PI_ERR_SYSCMD_DATA_B    0x00004000      /* SysCmd data parity error */
+#define PI_ERR_SYSCMD_DATA_A    0x00008000
+#define PI_ERR_SYSCMD_ADDR_B    0x00010000      /* SysCmd addr parity error */
+#define PI_ERR_SYSCMD_ADDR_A    0x00020000
+#define PI_ERR_BAD_SPOOL_B      0x00040000      /* Error spooling to memory */
+#define PI_ERR_BAD_SPOOL_A      0x00080000
+#define PI_ERR_UNCAC_UNCORR_B   0x00100000      /* Uncached uncorrectable   */
+#define PI_ERR_UNCAC_UNCORR_A   0x00200000
+#define PI_ERR_SYSSTATE_TAG_B   0x00400000      /* SysState tag parity error */
+#define PI_ERR_SYSSTATE_TAG_A   0x00800000
+#define PI_ERR_MD_UNCORR        0x01000000      /* Must be cleared in MD    */
+
+#define PI_ERR_CLEAR_ALL_A      0x00aaaaaa
+#define PI_ERR_CLEAR_ALL_B      0x00555555
+
+
+/*
+ * The following three macros define all possible error int pends.
+ */
+
+#define PI_FATAL_ERR_CPU_A      (PI_ERR_SYSSTATE_TAG_A  | \
+                                 PI_ERR_BAD_SPOOL_A     | \
+                                 PI_ERR_SYSCMD_ADDR_A   | \
+                                 PI_ERR_SYSCMD_DATA_A   | \
+                                 PI_ERR_SYSAD_ADDR_A    | \
+                                 PI_ERR_SYSAD_DATA_A    | \
+                                 PI_ERR_SYSSTATE_A)
+
+#define PI_MISC_ERR_CPU_A       (PI_ERR_UNCAC_UNCORR_A  | \
+                                 PI_ERR_WRB_WERR_A      | \
+                                 PI_ERR_WRB_TERR_A      | \
+                                 PI_ERR_SPUR_MSG_A      | \
+                                 PI_ERR_SPOOL_CMP_A)
+
+#define PI_FATAL_ERR_CPU_B      (PI_ERR_SYSSTATE_TAG_B  | \
+                                 PI_ERR_BAD_SPOOL_B     | \
+                                 PI_ERR_SYSCMD_ADDR_B   | \
+                                 PI_ERR_SYSCMD_DATA_B   | \
+                                 PI_ERR_SYSAD_ADDR_B    | \
+                                 PI_ERR_SYSAD_DATA_B    | \
+                                 PI_ERR_SYSSTATE_B)
+
+#define PI_MISC_ERR_CPU_B       (PI_ERR_UNCAC_UNCORR_B  | \
+                                 PI_ERR_WRB_WERR_B      | \
+                                 PI_ERR_WRB_TERR_B      | \
+                                 PI_ERR_SPUR_MSG_B      | \
+                                 PI_ERR_SPOOL_CMP_B)
+
+#define PI_ERR_GENERIC  (PI_ERR_MD_UNCORR)
+
+/*
+ * Error types for PI_ERR_STATUS0_[AB] and error stack:
+ * Use the write types if WRBRRB is 1 else use the read types
+ */
+
+/* Fields in PI_ERR_STATUS0_[AB] */
+#define PI_ERR_ST0_TYPE_MASK    0x0000000000000007
+#define PI_ERR_ST0_TYPE_SHFT    0
+#define PI_ERR_ST0_REQNUM_MASK  0x0000000000000038
+#define PI_ERR_ST0_REQNUM_SHFT  3
+#define PI_ERR_ST0_SUPPL_MASK   0x000000000001ffc0
+#define PI_ERR_ST0_SUPPL_SHFT   6
+#define PI_ERR_ST0_CMD_MASK     0x0000000001fe0000
+#define PI_ERR_ST0_CMD_SHFT     17
+#define PI_ERR_ST0_ADDR_MASK    0x3ffffffffe000000
+#define PI_ERR_ST0_ADDR_SHFT    25
+#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
+#define PI_ERR_ST0_OVERRUN_SHFT 62
+#define PI_ERR_ST0_VALID_MASK   0x8000000000000000
+#define PI_ERR_ST0_VALID_SHFT   63
+
+/* Fields in PI_ERR_STATUS1_[AB] */
+#define PI_ERR_ST1_SPOOL_MASK   0x00000000001fffff
+#define PI_ERR_ST1_SPOOL_SHFT   0
+#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
+#define PI_ERR_ST1_TOUTCNT_SHFT 21
+#define PI_ERR_ST1_INVCNT_MASK  0x0000007fe0000000
+#define PI_ERR_ST1_INVCNT_SHFT  29
+#define PI_ERR_ST1_CRBNUM_MASK  0x0000038000000000
+#define PI_ERR_ST1_CRBNUM_SHFT  39
+#define PI_ERR_ST1_WRBRRB_MASK  0x0000040000000000
+#define PI_ERR_ST1_WRBRRB_SHFT  42
+#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
+#define PI_ERR_ST1_CRBSTAT_SHFT 43
+#define PI_ERR_ST1_MSGSRC_MASK  0xffe0000000000000
+#define PI_ERR_ST1_MSGSRC_SHFT  53
+
+/* Fields in the error stack */
+#define PI_ERR_STK_TYPE_MASK    0x0000000000000003
+#define PI_ERR_STK_TYPE_SHFT    0
+#define PI_ERR_STK_SUPPL_MASK   0x0000000000000038
+#define PI_ERR_STK_SUPPL_SHFT   3
+#define PI_ERR_STK_REQNUM_MASK  0x00000000000001c0
+#define PI_ERR_STK_REQNUM_SHFT  6
+#define PI_ERR_STK_CRBNUM_MASK  0x0000000000000e00
+#define PI_ERR_STK_CRBNUM_SHFT  9
+#define PI_ERR_STK_WRBRRB_MASK  0x0000000000001000
+#define PI_ERR_STK_WRBRRB_SHFT  12
+#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
+#define PI_ERR_STK_CRBSTAT_SHFT 13
+#define PI_ERR_STK_CMD_MASK     0x000000007f800000
+#define PI_ERR_STK_CMD_SHFT     23
+#define PI_ERR_STK_ADDR_MASK    0xffffffff80000000
+#define PI_ERR_STK_ADDR_SHFT    31
+
+/* Error type in the error status or stack on Read CRBs */
+#define PI_ERR_RD_PRERR         1
+#define PI_ERR_RD_DERR          2
+#define PI_ERR_RD_TERR          3
+
+/* Error type in the error status or stack on Write CRBs */
+#define PI_ERR_WR_WERR          0
+#define PI_ERR_WR_PWERR         1
+#define PI_ERR_WR_TERR          3
+
+/* Read or Write CRB in error status or stack */
+#define PI_ERR_RRB      0
+#define PI_ERR_WRB      1
+#define PI_ERR_ANY_CRB  2
+
+/* Address masks in the error status and error stack are not the same */
+#define ERR_STK_ADDR_SHFT       7
+#define ERR_STAT0_ADDR_SHFT     3
+
+#define PI_MIN_STACK_SIZE 4096  /* For figuring out the size to set */
+#define PI_STACK_SIZE_SHFT      12      /* 4k */
+
+#define ERR_STACK_SIZE_BYTES(_sz) \
+       ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
+
+#ifndef __ASSEMBLY__
+/*
+ * format of error stack and error status registers.
+ */
+
+struct err_stack_format {
+        u64     sk_addr    : 33,   /* address */
+                sk_cmd     :  8,   /* message command */
+                sk_crb_sts : 10,   /* status from RRB or WRB */
+                sk_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                sk_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                sk_t5_req  :  3,   /* RRB T5 request number */
+                sk_suppl   :  3,   /* lowest 3 bit of supplemental */
+                sk_err_type:  3;   /* error type        */
+};
+
+typedef union pi_err_stack {
+        u64     pi_stk_word;
+        struct  err_stack_format pi_stk_fmt;
+} pi_err_stack_t;
+
+struct err_status0_format {
+        u64     s0_valid   :  1,   /* Valid */
+                s0_ovr_run :  1,   /* Overrun, spooled to memory */
+                s0_addr    : 37,   /* address */
+                s0_cmd     :  8,   /* message command */
+                s0_supl    : 11,   /* message supplemental field */
+                s0_t5_req  :  3,   /* RRB T5 request number */
+                s0_err_type:  3;   /* error type */
+};
+
+typedef union pi_err_stat0 {
+        u64     pi_stat0_word;
+        struct err_status0_format pi_stat0_fmt;
+} pi_err_stat0_t;
+
+struct err_status1_format {
+        u64     s1_src     : 11,   /* message source */
+                s1_crb_sts : 10,   /* status from RRB or WRB */
+                s1_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                s1_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                s1_inval_cnt:10,   /* signed invalidate counter RRB */
+                s1_to_cnt  :  8,   /* crb timeout counter */
+                s1_spl_cnt : 21;   /* number spooled to memory */
+};
+
+typedef union pi_err_stat1 {
+        u64     pi_stat1_word;
+        struct err_status1_format pi_stat1_fmt;
+} pi_err_stat1_t;
+
+typedef u64     rtc_time_t;
+
+#endif /* !__ASSEMBLY__ */
+
+
+/* Bits in PI_SYSAD_ERRCHK_EN */
+#define PI_SYSAD_ERRCHK_ECCGEN  0x01    /* Enable ECC generation            */
+#define PI_SYSAD_ERRCHK_QUALGEN 0x02    /* Enable data quality signal gen.  */
+#define PI_SYSAD_ERRCHK_SADP    0x04    /* Enable SysAD parity checking     */
+#define PI_SYSAD_ERRCHK_CMDP    0x08    /* Enable SysCmd parity checking    */
+#define PI_SYSAD_ERRCHK_STATE   0x10    /* Enable SysState parity checking  */
+#define PI_SYSAD_ERRCHK_QUAL    0x20    /* Enable data quality checking     */
+#define PI_SYSAD_CHECK_ALL      0x3f    /* Generate and check all signals.  */
+
+/* Interrupt pending bits on R10000 */
+
+#define HUB_IP_PEND0            0x0400
+#define HUB_IP_PEND1_CC         0x0800
+#define HUB_IP_RT               0x1000
+#define HUB_IP_PROF             0x2000
+#define HUB_IP_ERROR            0x4000
+#define HUB_IP_MASK             0x7c00
+
+/* PI_RT_LOCAL_CTRL mask and shift definitions */
+
+#define PRLC_USE_INT_SHFT       16
+#define PRLC_USE_INT_MASK       (UINT64_CAST 1 << 16)
+#define PRLC_USE_INT            (UINT64_CAST 1 << 16)
+#define PRLC_GCLK_SHFT          15
+#define PRLC_GCLK_MASK          (UINT64_CAST 1 << 15)
+#define PRLC_GCLK               (UINT64_CAST 1 << 15)
+#define PRLC_GCLK_COUNT_SHFT    8
+#define PRLC_GCLK_COUNT_MASK    (UINT64_CAST 0x7f << 8)
+#define PRLC_MAX_COUNT_SHFT     1
+#define PRLC_MAX_COUNT_MASK     (UINT64_CAST 0x7f << 1)
+#define PRLC_GCLK_EN_SHFT       0
+#define PRLC_GCLK_EN_MASK       (UINT64_CAST 1)
+#define PRLC_GCLK_EN            (UINT64_CAST 1)
+
+/* PI_RT_FILTER_CTRL mask and shift definitions */
+
+/*
+ * Bits for NACK_CNT_A/B and NACK_CMP
+ */
+#define PI_NACK_CNT_EN_SHFT     20
+#define PI_NACK_CNT_EN_MASK     0x100000
+#define PI_NACK_CNT_MASK        0x0fffff
+#define PI_NACK_CNT_MAX         0x0fffff
+
+#endif /* _ASM_SN_SN0_HUBPI_H */
diff --git a/arch/mips/include/asm/sn/sn0/ip27.h b/arch/mips/include/asm/sn/sn0/ip27.h
new file mode 100644
index 000000000000..3c97e0855c8d
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/ip27.h
@@ -0,0 +1,85 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/IP27.h>.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2006 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_IP27_H
+#define _ASM_SN_SN0_IP27_H
+
+#include <asm/mipsregs.h>
+
+/*
+ * Simple definitions for the masks which remove SW bits from pte.
+ */
+
+#define TLBLO_HWBITSHIFT        0               /* Shift value, for masking */
+
+#ifndef __ASSEMBLY__
+
+#define CAUSE_BERRINTR          IE_IRQ5
+
+#define ECCF_CACHE_ERR  0
+#define ECCF_TAGLO      1
+#define ECCF_ECC        2
+#define ECCF_ERROREPC   3
+#define ECCF_PADDR      4
+#define ECCF_SIZE       (5 * sizeof(long))
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef __ASSEMBLY__
+
+/*
+ * KL_GET_CPUNUM (similar to EV_GET_SPNUM for EVEREST platform) reads
+ * the processor number of the calling processor.  The proc parameters
+ * must be a register.
+ */
+#define KL_GET_CPUNUM(proc)                             \
+        dli     proc, LOCAL_HUB(0);                     \
+        ld      proc, PI_CPU_NUM(proc)
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * R10000 status register interrupt bit mask usage for IP27.
+ */
+#define SRB_SWTIMO      IE_SW0          /* 0x0100 */
+#define SRB_NET         IE_SW1          /* 0x0200 */
+#define SRB_DEV0        IE_IRQ0         /* 0x0400 */
+#define SRB_DEV1        IE_IRQ1         /* 0x0800 */
+#define SRB_TIMOCLK     IE_IRQ2         /* 0x1000 */
+#define SRB_PROFCLK     IE_IRQ3         /* 0x2000 */
+#define SRB_ERR         IE_IRQ4         /* 0x4000 */
+#define SRB_SCHEDCLK    IE_IRQ5         /* 0x8000 */
+
+#define SR_IBIT_HI      SRB_DEV0
+#define SR_IBIT_PROF    SRB_PROFCLK
+
+#define SRB_SWTIMO_IDX          0
+#define SRB_NET_IDX             1
+#define SRB_DEV0_IDX            2
+#define SRB_DEV1_IDX            3
+#define SRB_TIMOCLK_IDX         4
+#define SRB_PROFCLK_IDX         5
+#define SRB_ERR_IDX             6
+#define SRB_SCHEDCLK_IDX        7
+
+#define NUM_CAUSE_INTRS         8
+
+#define SCACHE_LINESIZE 128
+#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
+
+#include <asm/sn/addrs.h>
+
+#define LED_CYCLE_MASK  0x0f
+#define LED_CYCLE_SHFT  4
+
+#define SEND_NMI(_nasid, _slice)        \
+          REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
+
+#endif /* _ASM_SN_SN0_IP27_H */
diff --git a/arch/mips/include/asm/sn/sn_private.h b/arch/mips/include/asm/sn/sn_private.h
new file mode 100644
index 000000000000..1a2c3025bf28
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn_private.h
@@ -0,0 +1,19 @@
+#ifndef __ASM_SN_SN_PRIVATE_H
+#define __ASM_SN_SN_PRIVATE_H
+
+#include <asm/sn/types.h>
+
+extern nasid_t master_nasid;
+
+extern void cpu_node_probe(void);
+extern cnodeid_t get_compact_nodeid(void);
+extern void hub_rtc_init(cnodeid_t);
+extern void cpu_time_init(void);
+extern void per_cpu_init(void);
+extern void install_cpu_nmi_handler(int slice);
+extern void install_ipi(void);
+extern void setup_replication_mask(void);
+extern void replicate_kernel_text(void);
+extern pfn_t node_getfirstfree(cnodeid_t);
+
+#endif /* __ASM_SN_SN_PRIVATE_H */
diff --git a/arch/mips/include/asm/sn/types.h b/arch/mips/include/asm/sn/types.h
new file mode 100644
index 000000000000..74d0bb260b86
--- /dev/null
+++ b/arch/mips/include/asm/sn/types.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_TYPES_H
+#define _ASM_SN_TYPES_H
+
+#include <linux/types.h>
+
+typedef unsigned long   cpuid_t;
+typedef unsigned long   cnodemask_t;
+typedef signed short    nasid_t;        /* node id in numa-as-id space */
+typedef signed short    cnodeid_t;      /* node id in compact-id space */
+typedef signed char     partid_t;       /* partition ID type */
+typedef signed short    moduleid_t;     /* user-visible module number type */
+typedef signed short    cmoduleid_t;    /* kernel compact module id type */
+typedef unsigned char   clusterid_t;    /* Clusterid of the cell */
+typedef unsigned long   pfn_t;
+
+typedef dev_t           vertex_hdl_t;   /* hardware graph vertex handle */
+
+#endif /* _ASM_SN_TYPES_H */
diff --git a/arch/mips/include/asm/sni.h b/arch/mips/include/asm/sni.h
new file mode 100644
index 000000000000..8c1eb02c6d16
--- /dev/null
+++ b/arch/mips/include/asm/sni.h
@@ -0,0 +1,244 @@
+/*
+ * SNI specific definitions
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1998 by Ralf Baechle
+ * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
+ */
+#ifndef __ASM_SNI_H
+#define __ASM_SNI_H
+
+extern unsigned int sni_brd_type;
+
+#define SNI_BRD_10                 2
+#define SNI_BRD_10NEW              3
+#define SNI_BRD_TOWER_OASIC        4
+#define SNI_BRD_MINITOWER          5
+#define SNI_BRD_PCI_TOWER          6
+#define SNI_BRD_RM200              7
+#define SNI_BRD_PCI_MTOWER         8
+#define SNI_BRD_PCI_DESKTOP        9
+#define SNI_BRD_PCI_TOWER_CPLUS   10
+#define SNI_BRD_PCI_MTOWER_CPLUS  11
+
+/* RM400 cpu types */
+#define SNI_CPU_M8021           0x01
+#define SNI_CPU_M8030           0x04
+#define SNI_CPU_M8031           0x06
+#define SNI_CPU_M8034           0x0f
+#define SNI_CPU_M8037           0x07
+#define SNI_CPU_M8040           0x05
+#define SNI_CPU_M8043           0x09
+#define SNI_CPU_M8050           0x0b
+#define SNI_CPU_M8053           0x0d
+
+#define SNI_PORT_BASE           CKSEG1ADDR(0xb4000000)
+
+#ifndef __MIPSEL__
+/*
+ * ASIC PCI registers for big endian configuration.
+ */
+#define PCIMT_UCONF             CKSEG1ADDR(0xbfff0004)
+#define PCIMT_IOADTIMEOUT2      CKSEG1ADDR(0xbfff000c)
+#define PCIMT_IOMEMCONF         CKSEG1ADDR(0xbfff0014)
+#define PCIMT_IOMMU             CKSEG1ADDR(0xbfff001c)
+#define PCIMT_IOADTIMEOUT1      CKSEG1ADDR(0xbfff0024)
+#define PCIMT_DMAACCESS         CKSEG1ADDR(0xbfff002c)
+#define PCIMT_DMAHIT            CKSEG1ADDR(0xbfff0034)
+#define PCIMT_ERRSTATUS         CKSEG1ADDR(0xbfff003c)
+#define PCIMT_ERRADDR           CKSEG1ADDR(0xbfff0044)
+#define PCIMT_SYNDROME          CKSEG1ADDR(0xbfff004c)
+#define PCIMT_ITPEND            CKSEG1ADDR(0xbfff0054)
+#define  IT_INT2                0x01
+#define  IT_INTD                0x02
+#define  IT_INTC                0x04
+#define  IT_INTB                0x08
+#define  IT_INTA                0x10
+#define  IT_EISA                0x20
+#define  IT_SCSI                0x40
+#define  IT_ETH                 0x80
+#define PCIMT_IRQSEL            CKSEG1ADDR(0xbfff005c)
+#define PCIMT_TESTMEM           CKSEG1ADDR(0xbfff0064)
+#define PCIMT_ECCREG            CKSEG1ADDR(0xbfff006c)
+#define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0074)
+#define PCIMT_ASIC_ID           CKSEG1ADDR(0xbfff007c)  /* read */
+#define PCIMT_SOFT_RESET        CKSEG1ADDR(0xbfff007c)  /* write */
+#define PCIMT_PIA_OE            CKSEG1ADDR(0xbfff0084)
+#define PCIMT_PIA_DATAOUT       CKSEG1ADDR(0xbfff008c)
+#define PCIMT_PIA_DATAIN        CKSEG1ADDR(0xbfff0094)
+#define PCIMT_CACHECONF         CKSEG1ADDR(0xbfff009c)
+#define PCIMT_INVSPACE          CKSEG1ADDR(0xbfff00a4)
+#else
+/*
+ * ASIC PCI registers for little endian configuration.
+ */
+#define PCIMT_UCONF             CKSEG1ADDR(0xbfff0000)
+#define PCIMT_IOADTIMEOUT2      CKSEG1ADDR(0xbfff0008)
+#define PCIMT_IOMEMCONF         CKSEG1ADDR(0xbfff0010)
+#define PCIMT_IOMMU             CKSEG1ADDR(0xbfff0018)
+#define PCIMT_IOADTIMEOUT1      CKSEG1ADDR(0xbfff0020)
+#define PCIMT_DMAACCESS         CKSEG1ADDR(0xbfff0028)
+#define PCIMT_DMAHIT            CKSEG1ADDR(0xbfff0030)
+#define PCIMT_ERRSTATUS         CKSEG1ADDR(0xbfff0038)
+#define PCIMT_ERRADDR           CKSEG1ADDR(0xbfff0040)
+#define PCIMT_SYNDROME          CKSEG1ADDR(0xbfff0048)
+#define PCIMT_ITPEND            CKSEG1ADDR(0xbfff0050)
+#define  IT_INT2                0x01
+#define  IT_INTD                0x02
+#define  IT_INTC                0x04
+#define  IT_INTB                0x08
+#define  IT_INTA                0x10
+#define  IT_EISA                0x20
+#define  IT_SCSI                0x40
+#define  IT_ETH                 0x80
+#define PCIMT_IRQSEL            CKSEG1ADDR(0xbfff0058)
+#define PCIMT_TESTMEM           CKSEG1ADDR(0xbfff0060)
+#define PCIMT_ECCREG            CKSEG1ADDR(0xbfff0068)
+#define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0070)
+#define PCIMT_ASIC_ID           CKSEG1ADDR(0xbfff0078)  /* read */
+#define PCIMT_SOFT_RESET        CKSEG1ADDR(0xbfff0078)  /* write */
+#define PCIMT_PIA_OE            CKSEG1ADDR(0xbfff0080)
+#define PCIMT_PIA_DATAOUT       CKSEG1ADDR(0xbfff0088)
+#define PCIMT_PIA_DATAIN        CKSEG1ADDR(0xbfff0090)
+#define PCIMT_CACHECONF         CKSEG1ADDR(0xbfff0098)
+#define PCIMT_INVSPACE          CKSEG1ADDR(0xbfff00a0)
+#endif
+
+#define PCIMT_PCI_CONF          CKSEG1ADDR(0xbfff0100)
+
+/*
+ * Data port for the PCI bus in IO space
+ */
+#define PCIMT_CONFIG_DATA       0x0cfc
+
+/*
+ * Board specific registers
+ */
+#define PCIMT_CSMSR             CKSEG1ADDR(0xbfd00000)
+#define PCIMT_CSSWITCH          CKSEG1ADDR(0xbfd10000)
+#define PCIMT_CSITPEND          CKSEG1ADDR(0xbfd20000)
+#define PCIMT_AUTO_PO_EN        CKSEG1ADDR(0xbfd30000)
+#define PCIMT_CLR_TEMP          CKSEG1ADDR(0xbfd40000)
+#define PCIMT_AUTO_PO_DIS       CKSEG1ADDR(0xbfd50000)
+#define PCIMT_EXMSR             CKSEG1ADDR(0xbfd60000)
+#define PCIMT_UNUSED1           CKSEG1ADDR(0xbfd70000)
+#define PCIMT_CSWCSM            CKSEG1ADDR(0xbfd80000)
+#define PCIMT_UNUSED2           CKSEG1ADDR(0xbfd90000)
+#define PCIMT_CSLED             CKSEG1ADDR(0xbfda0000)
+#define PCIMT_CSMAPISA          CKSEG1ADDR(0xbfdb0000)
+#define PCIMT_CSRSTBP           CKSEG1ADDR(0xbfdc0000)
+#define PCIMT_CLRPOFF           CKSEG1ADDR(0xbfdd0000)
+#define PCIMT_CSTIMER           CKSEG1ADDR(0xbfde0000)
+#define PCIMT_PWDN              CKSEG1ADDR(0xbfdf0000)
+
+/*
+ * A20R based boards
+ */
+#define A20R_PT_CLOCK_BASE      CKSEG1ADDR(0xbc040000)
+#define A20R_PT_TIM0_ACK        CKSEG1ADDR(0xbc050000)
+#define A20R_PT_TIM1_ACK        CKSEG1ADDR(0xbc060000)
+
+#define SNI_A20R_IRQ_BASE       MIPS_CPU_IRQ_BASE
+#define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)
+
+#define SNI_PCIT_INT_REG        CKSEG1ADDR(0xbfff000c)
+
+#define SNI_PCIT_INT_START      24
+#define SNI_PCIT_INT_END        30
+
+#define PCIT_IRQ_ETHERNET       (MIPS_CPU_IRQ_BASE + 5)
+#define PCIT_IRQ_INTA           (SNI_PCIT_INT_START + 0)
+#define PCIT_IRQ_INTB           (SNI_PCIT_INT_START + 1)
+#define PCIT_IRQ_INTC           (SNI_PCIT_INT_START + 2)
+#define PCIT_IRQ_INTD           (SNI_PCIT_INT_START + 3)
+#define PCIT_IRQ_SCSI0          (SNI_PCIT_INT_START + 4)
+#define PCIT_IRQ_SCSI1          (SNI_PCIT_INT_START + 5)
+
+
+/*
+ * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
+ * to the other interrupts generated by ASIC PCI.
+ *
+ * INT2 is a wired-or of the push button interrupt, high temperature interrupt
+ * ASIC PCI interrupt.
+ */
+#define PCIMT_KEYBOARD_IRQ       1
+#define PCIMT_IRQ_INT2          24
+#define PCIMT_IRQ_INTD          25
+#define PCIMT_IRQ_INTC          26
+#define PCIMT_IRQ_INTB          27
+#define PCIMT_IRQ_INTA          28
+#define PCIMT_IRQ_EISA          29
+#define PCIMT_IRQ_SCSI          30
+
+#define PCIMT_IRQ_ETHERNET      (MIPS_CPU_IRQ_BASE+6)
+
+#if 0
+#define PCIMT_IRQ_TEMPERATURE   24
+#define PCIMT_IRQ_EISA_NMI      25
+#define PCIMT_IRQ_POWER_OFF     26
+#define PCIMT_IRQ_BUTTON        27
+#endif
+
+/*
+ * Base address for the mapped 16mb EISA bus segment.
+ */
+#define PCIMT_EISA_BASE         CKSEG1ADDR(0xb0000000)
+
+/* PCI EISA Interrupt acknowledge  */
+#define PCIMT_INT_ACKNOWLEDGE   CKSEG1ADDR(0xba000000)
+
+/*
+ *  SNI ID PROM
+ *
+ * SNI_IDPROM_MEMSIZE  Memsize in 16MB quantities
+ * SNI_IDPROM_BRDTYPE  Board Type
+ * SNI_IDPROM_CPUTYPE  CPU Type on RM400
+ */
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define __SNI_END 0
+#endif
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define __SNI_END 3
+#endif
+#define SNI_IDPROM_BASE        CKSEG1ADDR(0x1ff00000)
+#define SNI_IDPROM_MEMSIZE     (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
+#define SNI_IDPROM_BRDTYPE     (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
+#define SNI_IDPROM_CPUTYPE     (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
+
+#define SNI_IDPROM_SIZE 0x1000
+
+/* board specific init functions */
+extern void sni_a20r_init(void);
+extern void sni_pcit_init(void);
+extern void sni_rm200_init(void);
+extern void sni_pcimt_init(void);
+
+/* board specific irq init functions */
+extern void sni_a20r_irq_init(void);
+extern void sni_pcit_irq_init(void);
+extern void sni_pcit_cplus_irq_init(void);
+extern void sni_rm200_irq_init(void);
+extern void sni_pcimt_irq_init(void);
+
+/* timer inits */
+extern void sni_cpu_time_init(void);
+
+/* eisa init for RM200/400 */
+#ifdef CONFIG_EISA
+extern int sni_eisa_root_init(void);
+#else
+static inline int sni_eisa_root_init(void)
+{
+        return 0;
+}
+#endif
+
+/* common irq stuff */
+extern void (*sni_hwint)(void);
+extern struct irqaction sni_isa_irq;
+
+#endif /* __ASM_SNI_H */
diff --git a/arch/mips/include/asm/socket.h b/arch/mips/include/asm/socket.h
new file mode 100644
index 000000000000..facc2d7a87ca
--- /dev/null
+++ b/arch/mips/include/asm/socket.h
@@ -0,0 +1,117 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997, 1999, 2000, 2001 Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/*
+ * For setsockopt(2)
+ *
+ * This defines are ABI conformant as far as Linux supports these ...
+ */
+#define SOL_SOCKET      0xffff
+
+#define SO_DEBUG        0x0001  /* Record debugging information.  */
+#define SO_REUSEADDR    0x0004  /* Allow reuse of local addresses.  */
+#define SO_KEEPALIVE    0x0008  /* Keep connections alive and send
+                                   SIGPIPE when they die.  */
+#define SO_DONTROUTE    0x0010  /* Don't do local routing.  */
+#define SO_BROADCAST    0x0020  /* Allow transmission of
+                                   broadcast messages.  */
+#define SO_LINGER       0x0080  /* Block on close of a reliable
+                                   socket to transmit pending data.  */
+#define SO_OOBINLINE 0x0100     /* Receive out-of-band data in-band.  */
+#if 0
+To add: #define SO_REUSEPORT 0x0200     /* Allow local address and port reuse.  */
+#endif
+
+#define SO_TYPE         0x1008  /* Compatible name for SO_STYLE.  */
+#define SO_STYLE        SO_TYPE /* Synonym */
+#define SO_ERROR        0x1007  /* get error status and clear */
+#define SO_SNDBUF       0x1001  /* Send buffer size. */
+#define SO_RCVBUF       0x1002  /* Receive buffer. */
+#define SO_SNDLOWAT     0x1003  /* send low-water mark */
+#define SO_RCVLOWAT     0x1004  /* receive low-water mark */
+#define SO_SNDTIMEO     0x1005  /* send timeout */
+#define SO_RCVTIMEO     0x1006  /* receive timeout */
+#define SO_ACCEPTCONN   0x1009
+
+/* linux-specific, might as well be the same as on i386 */
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_BSDCOMPAT    14
+
+#define SO_PASSCRED     17
+#define SO_PEERCRED     18
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE         25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_PEERSEC              30
+#define SO_SNDBUFFORCE          31
+#define SO_RCVBUFFORCE          33
+#define SO_PASSSEC              34
+#define SO_TIMESTAMPNS          35
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+
+#define SO_MARK                 36
+
+#ifdef __KERNEL__
+
+/** sock_type - Socket types
+ *
+ * Please notice that for binary compat reasons MIPS has to
+ * override the enum sock_type in include/linux/net.h, so
+ * we define ARCH_HAS_SOCKET_TYPES here.
+ *
+ * @SOCK_DGRAM - datagram (conn.less) socket
+ * @SOCK_STREAM - stream (connection) socket
+ * @SOCK_RAW - raw socket
+ * @SOCK_RDM - reliably-delivered message
+ * @SOCK_SEQPACKET - sequential packet socket
+ * @SOCK_PACKET - linux specific way of getting packets at the dev level.
+ *                For writing rarp and other similar things on the user level.
+ */
+enum sock_type {
+        SOCK_DGRAM      = 1,
+        SOCK_STREAM     = 2,
+        SOCK_RAW        = 3,
+        SOCK_RDM        = 4,
+        SOCK_SEQPACKET  = 5,
+        SOCK_DCCP       = 6,
+        SOCK_PACKET     = 10,
+};
+
+#define SOCK_MAX (SOCK_PACKET + 1)
+/* Mask which covers at least up to SOCK_MASK-1.  The
+ *  * remaining bits are used as flags. */
+#define SOCK_TYPE_MASK 0xf
+
+/* Flags for socket, socketpair, paccept */
+#define SOCK_CLOEXEC    O_CLOEXEC
+#define SOCK_NONBLOCK   O_NONBLOCK
+
+#define ARCH_HAS_SOCKET_TYPES 1
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_SOCKET_H */
diff --git a/arch/mips/include/asm/sockios.h b/arch/mips/include/asm/sockios.h
new file mode 100644
index 000000000000..ed1a5f78d22f
--- /dev/null
+++ b/arch/mips/include/asm/sockios.h
@@ -0,0 +1,26 @@
+/*
+ * Socket-level I/O control calls.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ */
+#ifndef _ASM_SOCKIOS_H
+#define _ASM_SOCKIOS_H
+
+#include <asm/ioctl.h>
+
+/* Socket-level I/O control calls. */
+#define FIOGETOWN       _IOR('f', 123, int)
+#define FIOSETOWN       _IOW('f', 124, int)
+
+#define SIOCATMARK      _IOR('s', 7, int)
+#define SIOCSPGRP       _IOW('s', 8, pid_t)
+#define SIOCGPGRP       _IOR('s', 9, pid_t)
+
+#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
+
+#endif /* _ASM_SOCKIOS_H */
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
new file mode 100644
index 000000000000..795ac6c23203
--- /dev/null
+++ b/arch/mips/include/asm/sparsemem.h
@@ -0,0 +1,14 @@
+#ifndef _MIPS_SPARSEMEM_H
+#define _MIPS_SPARSEMEM_H
+#ifdef CONFIG_SPARSEMEM
+
+/*
+ * SECTION_SIZE_BITS            2^N: how big each section will be
+ * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
+ */
+#define SECTION_SIZE_BITS       28
+#define MAX_PHYSMEM_BITS        35
+
+#endif /* CONFIG_SPARSEMEM */
+#endif /* _MIPS_SPARSEMEM_H */
+
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
new file mode 100644
index 000000000000..5d98a3cb85b7
--- /dev/null
+++ b/arch/mips/include/asm/spinlock.h
@@ -0,0 +1,487 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_SPINLOCK_H
+#define _ASM_SPINLOCK_H
+
+#include <linux/compiler.h>
+
+#include <asm/barrier.h>
+#include <asm/war.h>
+
+/*
+ * Your basic SMP spinlocks, allowing only a single CPU anywhere
+ *
+ * Simple spin lock operations.  There are two variants, one clears IRQ's
+ * on the local processor, one does not.
+ *
+ * These are fair FIFO ticket locks
+ *
+ * (the type definitions are in asm/spinlock_types.h)
+ */
+
+
+/*
+ * Ticket locks are conceptually two parts, one indicating the current head of
+ * the queue, and the other indicating the current tail. The lock is acquired
+ * by atomically noting the tail and incrementing it by one (thus adding
+ * ourself to the queue and noting our position), then waiting until the head
+ * becomes equal to the the initial value of the tail.
+ */
+
+static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
+{
+        unsigned int counters = ACCESS_ONCE(lock->lock);
+
+        return ((counters >> 14) ^ counters) & 0x1fff;
+}
+
+#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+#define __raw_spin_unlock_wait(x) \
+        while (__raw_spin_is_locked(x)) { cpu_relax(); }
+
+static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
+{
+        unsigned int counters = ACCESS_ONCE(lock->lock);
+
+        return (((counters >> 14) - counters) & 0x1fff) > 1;
+}
+
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
+{
+        int my_ticket;
+        int tmp;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__ (
+                "       .set push               # __raw_spin_lock       \n"
+                "       .set noreorder                                  \n"
+                "                                                       \n"
+                "1:     ll      %[ticket], %[ticket_ptr]                \n"
+                "       addiu   %[my_ticket], %[ticket], 0x4000         \n"
+                "       sc      %[my_ticket], %[ticket_ptr]             \n"
+                "       beqzl   %[my_ticket], 1b                        \n"
+                "        nop                                            \n"
+                "       srl     %[my_ticket], %[ticket], 14             \n"
+                "       andi    %[my_ticket], %[my_ticket], 0x1fff      \n"
+                "       andi    %[ticket], %[ticket], 0x1fff            \n"
+                "       bne     %[ticket], %[my_ticket], 4f             \n"
+                "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
+                "2:                                                     \n"
+                "       .subsection 2                                   \n"
+                "4:     andi    %[ticket], %[ticket], 0x1fff            \n"
+                "5:     sll     %[ticket], 5                            \n"
+                "                                                       \n"
+                "6:     bnez    %[ticket], 6b                           \n"
+                "        subu   %[ticket], 1                            \n"
+                "                                                       \n"
+                "       lw      %[ticket], %[ticket_ptr]                \n"
+                "       andi    %[ticket], %[ticket], 0x1fff            \n"
+                "       beq     %[ticket], %[my_ticket], 2b             \n"
+                "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
+                "       b       5b                                      \n"
+                "        subu   %[ticket], %[ticket], 1                 \n"
+                "       .previous                                       \n"
+                "       .set pop                                        \n"
+                : [ticket_ptr] "+m" (lock->lock),
+                  [ticket] "=&r" (tmp),
+                  [my_ticket] "=&r" (my_ticket));
+        } else {
+                __asm__ __volatile__ (
+                "       .set push               # __raw_spin_lock       \n"
+                "       .set noreorder                                  \n"
+                "                                                       \n"
+                "       ll      %[ticket], %[ticket_ptr]                \n"
+                "1:     addiu   %[my_ticket], %[ticket], 0x4000         \n"
+                "       sc      %[my_ticket], %[ticket_ptr]             \n"
+                "       beqz    %[my_ticket], 3f                        \n"
+                "        nop                                            \n"
+                "       srl     %[my_ticket], %[ticket], 14             \n"
+                "       andi    %[my_ticket], %[my_ticket], 0x1fff      \n"
+                "       andi    %[ticket], %[ticket], 0x1fff            \n"
+                "       bne     %[ticket], %[my_ticket], 4f             \n"
+                "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
+                "2:                                                     \n"
+                "       .subsection 2                                   \n"
+                "3:     b       1b                                      \n"
+                "        ll     %[ticket], %[ticket_ptr]                \n"
+                "                                                       \n"
+                "4:     andi    %[ticket], %[ticket], 0x1fff            \n"
+                "5:     sll     %[ticket], 5                            \n"
+                "                                                       \n"
+                "6:     bnez    %[ticket], 6b                           \n"
+                "        subu   %[ticket], 1                            \n"
+                "                                                       \n"
+                "       lw      %[ticket], %[ticket_ptr]                \n"
+                "       andi    %[ticket], %[ticket], 0x1fff            \n"
+                "       beq     %[ticket], %[my_ticket], 2b             \n"
+                "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
+                "       b       5b                                      \n"
+                "        subu   %[ticket], %[ticket], 1                 \n"
+                "       .previous                                       \n"
+                "       .set pop                                        \n"
+                : [ticket_ptr] "+m" (lock->lock),
+                  [ticket] "=&r" (tmp),
+                  [my_ticket] "=&r" (my_ticket));
+        }
+
+        smp_llsc_mb();
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+{
+        int tmp;
+
+        smp_llsc_mb();
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__ (
+                "                               # __raw_spin_unlock     \n"
+                "1:     ll      %[ticket], %[ticket_ptr]                \n"
+                "       addiu   %[ticket], %[ticket], 1                 \n"
+                "       ori     %[ticket], %[ticket], 0x2000            \n"
+                "       xori    %[ticket], %[ticket], 0x2000            \n"
+                "       sc      %[ticket], %[ticket_ptr]                \n"
+                "       beqzl   %[ticket], 2f                           \n"
+                : [ticket_ptr] "+m" (lock->lock),
+                  [ticket] "=&r" (tmp));
+        } else {
+                __asm__ __volatile__ (
+                "       .set push               # __raw_spin_unlock     \n"
+                "       .set noreorder                                  \n"
+                "                                                       \n"
+                "       ll      %[ticket], %[ticket_ptr]                \n"
+                "1:     addiu   %[ticket], %[ticket], 1                 \n"
+                "       ori     %[ticket], %[ticket], 0x2000            \n"
+                "       xori    %[ticket], %[ticket], 0x2000            \n"
+                "       sc      %[ticket], %[ticket_ptr]                \n"
+                "       beqz    %[ticket], 2f                           \n"
+                "        nop                                            \n"
+                "                                                       \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "        ll     %[ticket], %[ticket_ptr]                \n"
+                "       .previous                                       \n"
+                "       .set pop                                        \n"
+                : [ticket_ptr] "+m" (lock->lock),
+                  [ticket] "=&r" (tmp));
+        }
+}
+
+static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
+{
+        int tmp, tmp2, tmp3;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__ (
+                "       .set push               # __raw_spin_trylock    \n"
+                "       .set noreorder                                  \n"
+                "                                                       \n"
+                "1:     ll      %[ticket], %[ticket_ptr]                \n"
+                "       srl     %[my_ticket], %[ticket], 14             \n"
+                "       andi    %[my_ticket], %[my_ticket], 0x1fff      \n"
+                "       andi    %[now_serving], %[ticket], 0x1fff       \n"
+                "       bne     %[my_ticket], %[now_serving], 3f        \n"
+                "        addiu  %[ticket], %[ticket], 0x4000            \n"
+                "       sc      %[ticket], %[ticket_ptr]                \n"
+                "       beqzl   %[ticket], 1b                           \n"
+                "        li     %[ticket], 1                            \n"
+                "2:                                                     \n"
+                "       .subsection 2                                   \n"
+                "3:     b       2b                                      \n"
+                "        li     %[ticket], 0                            \n"
+                "       .previous                                       \n"
+                "       .set pop                                        \n"
+                : [ticket_ptr] "+m" (lock->lock),
+                  [ticket] "=&r" (tmp),
+                  [my_ticket] "=&r" (tmp2),
+                  [now_serving] "=&r" (tmp3));
+        } else {
+                __asm__ __volatile__ (
+                "       .set push               # __raw_spin_trylock    \n"
+                "       .set noreorder                                  \n"
+                "                                                       \n"
+                "       ll      %[ticket], %[ticket_ptr]                \n"
+                "1:     srl     %[my_ticket], %[ticket], 14             \n"
+                "       andi    %[my_ticket], %[my_ticket], 0x1fff      \n"
+                "       andi    %[now_serving], %[ticket], 0x1fff       \n"
+                "       bne     %[my_ticket], %[now_serving], 3f        \n"
+                "        addiu  %[ticket], %[ticket], 0x4000            \n"
+                "       sc      %[ticket], %[ticket_ptr]                \n"
+                "       beqz    %[ticket], 4f                           \n"
+                "        li     %[ticket], 1                            \n"
+                "2:                                                     \n"
+                "       .subsection 2                                   \n"
+                "3:     b       2b                                      \n"
+                "        li     %[ticket], 0                            \n"
+                "4:     b       1b                                      \n"
+                "        ll     %[ticket], %[ticket_ptr]                \n"
+                "       .previous                                       \n"
+                "       .set pop                                        \n"
+                : [ticket_ptr] "+m" (lock->lock),
+                  [ticket] "=&r" (tmp),
+                  [my_ticket] "=&r" (tmp2),
+                  [now_serving] "=&r" (tmp3));
+        }
+
+        smp_llsc_mb();
+
+        return tmp;
+}
+
+/*
+ * Read-write spinlocks, allowing multiple readers but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts but no interrupt
+ * writers. For those circumstances we can "mix" irq-safe locks - any writer
+ * needs to get a irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+
+/*
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
+
+/*
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define __raw_write_can_lock(rw)        (!(rw)->lock)
+
+static inline void __raw_read_lock(raw_rwlock_t *rw)
+{
+        unsigned int tmp;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_read_lock       \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bltz    %1, 1b                                  \n"
+                "        addu   %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                "        nop                                            \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_read_lock       \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bltz    %1, 2f                                  \n"
+                "        addu   %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 1b                                  \n"
+                "        nop                                            \n"
+                "       .subsection 2                                   \n"
+                "2:     ll      %1, %2                                  \n"
+                "       bltz    %1, 2b                                  \n"
+                "        addu   %1, 1                                   \n"
+                "       b       1b                                      \n"
+                "        nop                                            \n"
+                "       .previous                                       \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        }
+
+        smp_llsc_mb();
+}
+
+/* Note the use of sub, not subu which will make the kernel die with an
+   overflow exception if we ever try to unlock an rwlock that is already
+   unlocked or is being held by a writer.  */
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
+{
+        unsigned int tmp;
+
+        smp_llsc_mb();
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "1:     ll      %1, %2          # __raw_read_unlock     \n"
+                "       sub     %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_read_unlock     \n"
+                "1:     ll      %1, %2                                  \n"
+                "       sub     %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 2f                                  \n"
+                "        nop                                            \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "        nop                                            \n"
+                "       .previous                                       \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        }
+}
+
+static inline void __raw_write_lock(raw_rwlock_t *rw)
+{
+        unsigned int tmp;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_write_lock      \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bnez    %1, 1b                                  \n"
+                "        lui    %1, 0x8000                              \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                "        nop                                            \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_write_lock      \n"
+                "1:     ll      %1, %2                                  \n"
+                "       bnez    %1, 2f                                  \n"
+                "        lui    %1, 0x8000                              \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 2f                                  \n"
+                "        nop                                            \n"
+                "       .subsection 2                                   \n"
+                "2:     ll      %1, %2                                  \n"
+                "       bnez    %1, 2b                                  \n"
+                "        lui    %1, 0x8000                              \n"
+                "       b       1b                                      \n"
+                "        nop                                            \n"
+                "       .previous                                       \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp)
+                : "m" (rw->lock)
+                : "memory");
+        }
+
+        smp_llsc_mb();
+}
+
+static inline void __raw_write_unlock(raw_rwlock_t *rw)
+{
+        smp_mb();
+
+        __asm__ __volatile__(
+        "                               # __raw_write_unlock    \n"
+        "       sw      $0, %0                                  \n"
+        : "=m" (rw->lock)
+        : "m" (rw->lock)
+        : "memory");
+}
+
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+        unsigned int tmp;
+        int ret;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_read_trylock    \n"
+                "       li      %2, 0                                   \n"
+                "1:     ll      %1, %3                                  \n"
+                "       bltz    %1, 2f                                  \n"
+                "        addu   %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       .set    reorder                                 \n"
+                "       beqzl   %1, 1b                                  \n"
+                "        nop                                            \n"
+                __WEAK_LLSC_MB
+                "       li      %2, 1                                   \n"
+                "2:                                                     \n"
+                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_read_trylock    \n"
+                "       li      %2, 0                                   \n"
+                "1:     ll      %1, %3                                  \n"
+                "       bltz    %1, 2f                                  \n"
+                "        addu   %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 1b                                  \n"
+                "        nop                                            \n"
+                "       .set    reorder                                 \n"
+                __WEAK_LLSC_MB
+                "       li      %2, 1                                   \n"
+                "2:                                                     \n"
+                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+                : "m" (rw->lock)
+                : "memory");
+        }
+
+        return ret;
+}
+
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
+{
+        unsigned int tmp;
+        int ret;
+
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_write_trylock   \n"
+                "       li      %2, 0                                   \n"
+                "1:     ll      %1, %3                                  \n"
+                "       bnez    %1, 2f                                  \n"
+                "        lui    %1, 0x8000                              \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                "        nop                                            \n"
+                __WEAK_LLSC_MB
+                "       li      %2, 1                                   \n"
+                "       .set    reorder                                 \n"
+                "2:                                                     \n"
+                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_write_trylock   \n"
+                "       li      %2, 0                                   \n"
+                "1:     ll      %1, %3                                  \n"
+                "       bnez    %1, 2f                                  \n"
+                "       lui     %1, 0x8000                              \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 3f                                  \n"
+                "        li     %2, 1                                   \n"
+                "2:                                                     \n"
+                __WEAK_LLSC_MB
+                "       .subsection 2                                   \n"
+                "3:     b       1b                                      \n"
+                "        li     %2, 0                                   \n"
+                "       .previous                                       \n"
+                "       .set    reorder                                 \n"
+                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+                : "m" (rw->lock)
+                : "memory");
+        }
+
+        return ret;
+}
+
+
+#define _raw_spin_relax(lock)   cpu_relax()
+#define _raw_read_relax(lock)   cpu_relax()
+#define _raw_write_relax(lock)  cpu_relax()
+
+#endif /* _ASM_SPINLOCK_H */
diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..adeedaa116c1
--- /dev/null
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -0,0 +1,25 @@
+#ifndef _ASM_SPINLOCK_TYPES_H
+#define _ASM_SPINLOCK_TYPES_H
+
+#ifndef __LINUX_SPINLOCK_TYPES_H
+# error "please don't include this file directly"
+#endif
+
+typedef struct {
+        /*
+         * bits  0..13: serving_now
+         * bits 14    : junk data
+         * bits 15..28: ticket
+         */
+        unsigned int lock;
+} raw_spinlock_t;
+
+#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+
+typedef struct {
+        volatile unsigned int lock;
+} raw_rwlock_t;
+
+#define __RAW_RW_LOCK_UNLOCKED          { 0 }
+
+#endif
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
new file mode 100644
index 000000000000..4c37c4e5f72e
--- /dev/null
+++ b/arch/mips/include/asm/stackframe.h
@@ -0,0 +1,574 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2007  Maciej W. Rozycki
+ */
+#ifndef _ASM_STACKFRAME_H
+#define _ASM_STACKFRAME_H
+
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/asmmacro.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+
+/*
+ * For SMTC kernel, global IE should be left set, and interrupts
+ * controlled exclusively via IXMT.
+ */
+#ifdef CONFIG_MIPS_MT_SMTC
+#define STATMASK 0x1e
+#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#define STATMASK 0x3f
+#else
+#define STATMASK 0x1f
+#endif
+
+#ifdef CONFIG_MIPS_MT_SMTC
+#include <asm/mipsmtregs.h>
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+                .macro  SAVE_AT
+                .set    push
+                .set    noat
+                LONG_S  $1, PT_R1(sp)
+                .set    pop
+                .endm
+
+                .macro  SAVE_TEMP
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+                mflhxu  v1
+                LONG_S  v1, PT_LO(sp)
+                mflhxu  v1
+                LONG_S  v1, PT_HI(sp)
+                mflhxu  v1
+                LONG_S  v1, PT_ACX(sp)
+#else
+                mfhi    v1
+                LONG_S  v1, PT_HI(sp)
+                mflo    v1
+                LONG_S  v1, PT_LO(sp)
+#endif
+#ifdef CONFIG_32BIT
+                LONG_S  $8, PT_R8(sp)
+                LONG_S  $9, PT_R9(sp)
+#endif
+                LONG_S  $10, PT_R10(sp)
+                LONG_S  $11, PT_R11(sp)
+                LONG_S  $12, PT_R12(sp)
+                LONG_S  $13, PT_R13(sp)
+                LONG_S  $14, PT_R14(sp)
+                LONG_S  $15, PT_R15(sp)
+                LONG_S  $24, PT_R24(sp)
+                .endm
+
+                .macro  SAVE_STATIC
+                LONG_S  $16, PT_R16(sp)
+                LONG_S  $17, PT_R17(sp)
+                LONG_S  $18, PT_R18(sp)
+                LONG_S  $19, PT_R19(sp)
+                LONG_S  $20, PT_R20(sp)
+                LONG_S  $21, PT_R21(sp)
+                LONG_S  $22, PT_R22(sp)
+                LONG_S  $23, PT_R23(sp)
+                LONG_S  $30, PT_R30(sp)
+                .endm
+
+#ifdef CONFIG_SMP
+#ifdef CONFIG_MIPS_MT_SMTC
+#define PTEBASE_SHIFT   19      /* TCBIND */
+#else
+#define PTEBASE_SHIFT   23      /* CONTEXT */
+#endif
+                .macro  get_saved_sp    /* SMP variation */
+#ifdef CONFIG_MIPS_MT_SMTC
+                mfc0    k0, CP0_TCBIND
+#else
+                MFC0    k0, CP0_CONTEXT
+#endif
+#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
+                lui     k1, %hi(kernelsp)
+#else
+                lui     k1, %highest(kernelsp)
+                daddiu  k1, %higher(kernelsp)
+                dsll    k1, 16
+                daddiu  k1, %hi(kernelsp)
+                dsll    k1, 16
+#endif
+                LONG_SRL        k0, PTEBASE_SHIFT
+                LONG_ADDU       k1, k0
+                LONG_L  k1, %lo(kernelsp)(k1)
+                .endm
+
+                .macro  set_saved_sp stackp temp temp2
+#ifdef CONFIG_MIPS_MT_SMTC
+                mfc0    \temp, CP0_TCBIND
+#else
+                MFC0    \temp, CP0_CONTEXT
+#endif
+                LONG_SRL        \temp, PTEBASE_SHIFT
+                LONG_S  \stackp, kernelsp(\temp)
+                .endm
+#else
+                .macro  get_saved_sp    /* Uniprocessor variation */
+#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
+                lui     k1, %hi(kernelsp)
+#else
+                lui     k1, %highest(kernelsp)
+                daddiu  k1, %higher(kernelsp)
+                dsll    k1, k1, 16
+                daddiu  k1, %hi(kernelsp)
+                dsll    k1, k1, 16
+#endif
+                LONG_L  k1, %lo(kernelsp)(k1)
+                .endm
+
+                .macro  set_saved_sp stackp temp temp2
+                LONG_S  \stackp, kernelsp
+                .endm
+#endif
+
+                .macro  SAVE_SOME
+                .set    push
+                .set    noat
+                .set    reorder
+                mfc0    k0, CP0_STATUS
+                sll     k0, 3           /* extract cu0 bit */
+                .set    noreorder
+                bltz    k0, 8f
+                 move   k1, sp
+                .set    reorder
+                /* Called from user mode, new stack. */
+                get_saved_sp
+#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
+8:              move    k0, sp
+                PTR_SUBU sp, k1, PT_SIZE
+#else
+                .set    at=k0
+8:              PTR_SUBU k1, PT_SIZE
+                .set    noat
+                move    k0, sp
+                move    sp, k1
+#endif
+                LONG_S  k0, PT_R29(sp)
+                LONG_S  $3, PT_R3(sp)
+                /*
+                 * You might think that you don't need to save $0,
+                 * but the FPU emulator and gdb remote debug stub
+                 * need it to operate correctly
+                 */
+                LONG_S  $0, PT_R0(sp)
+                mfc0    v1, CP0_STATUS
+                LONG_S  $2, PT_R2(sp)
+                LONG_S  v1, PT_STATUS(sp)
+#ifdef CONFIG_MIPS_MT_SMTC
+                /*
+                 * Ideally, these instructions would be shuffled in
+                 * to cover the pipeline delay.
+                 */
+                .set    mips32
+                mfc0    v1, CP0_TCSTATUS
+                .set    mips0
+                LONG_S  v1, PT_TCSTATUS(sp)
+#endif /* CONFIG_MIPS_MT_SMTC */
+                LONG_S  $4, PT_R4(sp)
+                mfc0    v1, CP0_CAUSE
+                LONG_S  $5, PT_R5(sp)
+                LONG_S  v1, PT_CAUSE(sp)
+                LONG_S  $6, PT_R6(sp)
+                MFC0    v1, CP0_EPC
+                LONG_S  $7, PT_R7(sp)
+#ifdef CONFIG_64BIT
+                LONG_S  $8, PT_R8(sp)
+                LONG_S  $9, PT_R9(sp)
+#endif
+                LONG_S  v1, PT_EPC(sp)
+                LONG_S  $25, PT_R25(sp)
+                LONG_S  $28, PT_R28(sp)
+                LONG_S  $31, PT_R31(sp)
+                ori     $28, sp, _THREAD_MASK
+                xori    $28, _THREAD_MASK
+                .set    pop
+                .endm
+
+                .macro  SAVE_ALL
+                SAVE_SOME
+                SAVE_AT
+                SAVE_TEMP
+                SAVE_STATIC
+                .endm
+
+                .macro  RESTORE_AT
+                .set    push
+                .set    noat
+                LONG_L  $1,  PT_R1(sp)
+                .set    pop
+                .endm
+
+                .macro  RESTORE_TEMP
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+                LONG_L  $24, PT_ACX(sp)
+                mtlhx   $24
+                LONG_L  $24, PT_HI(sp)
+                mtlhx   $24
+                LONG_L  $24, PT_LO(sp)
+                mtlhx   $24
+#else
+                LONG_L  $24, PT_LO(sp)
+                mtlo    $24
+                LONG_L  $24, PT_HI(sp)
+                mthi    $24
+#endif
+#ifdef CONFIG_32BIT
+                LONG_L  $8, PT_R8(sp)
+                LONG_L  $9, PT_R9(sp)
+#endif
+                LONG_L  $10, PT_R10(sp)
+                LONG_L  $11, PT_R11(sp)
+                LONG_L  $12, PT_R12(sp)
+                LONG_L  $13, PT_R13(sp)
+                LONG_L  $14, PT_R14(sp)
+                LONG_L  $15, PT_R15(sp)
+                LONG_L  $24, PT_R24(sp)
+                .endm
+
+                .macro  RESTORE_STATIC
+                LONG_L  $16, PT_R16(sp)
+                LONG_L  $17, PT_R17(sp)
+                LONG_L  $18, PT_R18(sp)
+                LONG_L  $19, PT_R19(sp)
+                LONG_L  $20, PT_R20(sp)
+                LONG_L  $21, PT_R21(sp)
+                LONG_L  $22, PT_R22(sp)
+                LONG_L  $23, PT_R23(sp)
+                LONG_L  $30, PT_R30(sp)
+                .endm
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+                .macro  RESTORE_SOME
+                .set    push
+                .set    reorder
+                .set    noat
+                mfc0    a0, CP0_STATUS
+                li      v1, 0xff00
+                ori     a0, STATMASK
+                xori    a0, STATMASK
+                mtc0    a0, CP0_STATUS
+                and     a0, v1
+                LONG_L  v0, PT_STATUS(sp)
+                nor     v1, $0, v1
+                and     v0, v1
+                or      v0, a0
+                mtc0    v0, CP0_STATUS
+                LONG_L  $31, PT_R31(sp)
+                LONG_L  $28, PT_R28(sp)
+                LONG_L  $25, PT_R25(sp)
+                LONG_L  $7,  PT_R7(sp)
+                LONG_L  $6,  PT_R6(sp)
+                LONG_L  $5,  PT_R5(sp)
+                LONG_L  $4,  PT_R4(sp)
+                LONG_L  $3,  PT_R3(sp)
+                LONG_L  $2,  PT_R2(sp)
+                .set    pop
+                .endm
+
+                .macro  RESTORE_SP_AND_RET
+                .set    push
+                .set    noreorder
+                LONG_L  k0, PT_EPC(sp)
+                LONG_L  sp, PT_R29(sp)
+                jr      k0
+                 rfe
+                .set    pop
+                .endm
+
+#else
+                .macro  RESTORE_SOME
+                .set    push
+                .set    reorder
+                .set    noat
+#ifdef CONFIG_MIPS_MT_SMTC
+                .set    mips32r2
+                /*
+                 * We need to make sure the read-modify-write
+                 * of Status below isn't perturbed by an interrupt
+                 * or cross-TC access, so we need to do at least a DMT,
+                 * protected by an interrupt-inhibit. But setting IXMT
+                 * also creates a few-cycle window where an IPI could
+                 * be queued and not be detected before potentially
+                 * returning to a WAIT or user-mode loop. It must be
+                 * replayed.
+                 *
+                 * We're in the middle of a context switch, and
+                 * we can't dispatch it directly without trashing
+                 * some registers, so we'll try to detect this unlikely
+                 * case and program a software interrupt in the VPE,
+                 * as would be done for a cross-VPE IPI.  To accomodate
+                 * the handling of that case, we're doing a DVPE instead
+                 * of just a DMT here to protect against other threads.
+                 * This is a lot of cruft to cover a tiny window.
+                 * If you can find a better design, implement it!
+                 *
+                 */
+                mfc0    v0, CP0_TCSTATUS
+                ori     v0, TCSTATUS_IXMT
+                mtc0    v0, CP0_TCSTATUS
+                _ehb
+                DVPE    5                               # dvpe a1
+                jal     mips_ihb
+#endif /* CONFIG_MIPS_MT_SMTC */
+                mfc0    a0, CP0_STATUS
+                ori     a0, STATMASK
+                xori    a0, STATMASK
+                mtc0    a0, CP0_STATUS
+                li      v1, 0xff00
+                and     a0, v1
+                LONG_L  v0, PT_STATUS(sp)
+                nor     v1, $0, v1
+                and     v0, v1
+                or      v0, a0
+                mtc0    v0, CP0_STATUS
+#ifdef CONFIG_MIPS_MT_SMTC
+/*
+ * Only after EXL/ERL have been restored to status can we
+ * restore TCStatus.IXMT.
+ */
+                LONG_L  v1, PT_TCSTATUS(sp)
+                _ehb
+                mfc0    a0, CP0_TCSTATUS
+                andi    v1, TCSTATUS_IXMT
+                bnez    v1, 0f
+
+/*
+ * We'd like to detect any IPIs queued in the tiny window
+ * above and request an software interrupt to service them
+ * when we ERET.
+ *
+ * Computing the offset into the IPIQ array of the executing
+ * TC's IPI queue in-line would be tedious.  We use part of
+ * the TCContext register to hold 16 bits of offset that we
+ * can add in-line to find the queue head.
+ */
+                mfc0    v0, CP0_TCCONTEXT
+                la      a2, IPIQ
+                srl     v0, v0, 16
+                addu    a2, a2, v0
+                LONG_L  v0, 0(a2)
+                beqz    v0, 0f
+/*
+ * If we have a queue, provoke dispatch within the VPE by setting C_SW1
+ */
+                mfc0    v0, CP0_CAUSE
+                ori     v0, v0, C_SW1
+                mtc0    v0, CP0_CAUSE
+0:
+                /*
+                 * This test should really never branch but
+                 * let's be prudent here.  Having atomized
+                 * the shared register modifications, we can
+                 * now EVPE, and must do so before interrupts
+                 * are potentially re-enabled.
+                 */
+                andi    a1, a1, MVPCONTROL_EVP
+                beqz    a1, 1f
+                evpe
+1:
+                /* We know that TCStatua.IXMT should be set from above */
+                xori    a0, a0, TCSTATUS_IXMT
+                or      a0, a0, v1
+                mtc0    a0, CP0_TCSTATUS
+                _ehb
+
+                .set    mips0
+#endif /* CONFIG_MIPS_MT_SMTC */
+                LONG_L  v1, PT_EPC(sp)
+                MTC0    v1, CP0_EPC
+                LONG_L  $31, PT_R31(sp)
+                LONG_L  $28, PT_R28(sp)
+                LONG_L  $25, PT_R25(sp)
+#ifdef CONFIG_64BIT
+                LONG_L  $8, PT_R8(sp)
+                LONG_L  $9, PT_R9(sp)
+#endif
+                LONG_L  $7,  PT_R7(sp)
+                LONG_L  $6,  PT_R6(sp)
+                LONG_L  $5,  PT_R5(sp)
+                LONG_L  $4,  PT_R4(sp)
+                LONG_L  $3,  PT_R3(sp)
+                LONG_L  $2,  PT_R2(sp)
+                .set    pop
+                .endm
+
+                .macro  RESTORE_SP_AND_RET
+                LONG_L  sp, PT_R29(sp)
+                .set    mips3
+                eret
+                .set    mips0
+                .endm
+
+#endif
+
+                .macro  RESTORE_SP
+                LONG_L  sp, PT_R29(sp)
+                .endm
+
+                .macro  RESTORE_ALL
+                RESTORE_TEMP
+                RESTORE_STATIC
+                RESTORE_AT
+                RESTORE_SOME
+                RESTORE_SP
+                .endm
+
+                .macro  RESTORE_ALL_AND_RET
+                RESTORE_TEMP
+                RESTORE_STATIC
+                RESTORE_AT
+                RESTORE_SOME
+                RESTORE_SP_AND_RET
+                .endm
+
+/*
+ * Move to kernel mode and disable interrupts.
+ * Set cp0 enable bit as sign that we're running on the kernel stack
+ */
+                .macro  CLI
+#if !defined(CONFIG_MIPS_MT_SMTC)
+                mfc0    t0, CP0_STATUS
+                li      t1, ST0_CU0 | STATMASK
+                or      t0, t1
+                xori    t0, STATMASK
+                mtc0    t0, CP0_STATUS
+#else /* CONFIG_MIPS_MT_SMTC */
+                /*
+                 * For SMTC, we need to set privilege
+                 * and disable interrupts only for the
+                 * current TC, using the TCStatus register.
+                 */
+                mfc0    t0, CP0_TCSTATUS
+                /* Fortunately CU 0 is in the same place in both registers */
+                /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
+                li      t1, ST0_CU0 | 0x08001c00
+                or      t0, t1
+                /* Clear TKSU, leave IXMT */
+                xori    t0, 0x00001800
+                mtc0    t0, CP0_TCSTATUS
+                _ehb
+                /* We need to leave the global IE bit set, but clear EXL...*/
+                mfc0    t0, CP0_STATUS
+                ori     t0, ST0_EXL | ST0_ERL
+                xori    t0, ST0_EXL | ST0_ERL
+                mtc0    t0, CP0_STATUS
+#endif /* CONFIG_MIPS_MT_SMTC */
+                irq_disable_hazard
+                .endm
+
+/*
+ * Move to kernel mode and enable interrupts.
+ * Set cp0 enable bit as sign that we're running on the kernel stack
+ */
+                .macro  STI
+#if !defined(CONFIG_MIPS_MT_SMTC)
+                mfc0    t0, CP0_STATUS
+                li      t1, ST0_CU0 | STATMASK
+                or      t0, t1
+                xori    t0, STATMASK & ~1
+                mtc0    t0, CP0_STATUS
+#else /* CONFIG_MIPS_MT_SMTC */
+                /*
+                 * For SMTC, we need to set privilege
+                 * and enable interrupts only for the
+                 * current TC, using the TCStatus register.
+                 */
+                _ehb
+                mfc0    t0, CP0_TCSTATUS
+                /* Fortunately CU 0 is in the same place in both registers */
+                /* Set TCU0, TKSU (for later inversion) and IXMT */
+                li      t1, ST0_CU0 | 0x08001c00
+                or      t0, t1
+                /* Clear TKSU *and* IXMT */
+                xori    t0, 0x00001c00
+                mtc0    t0, CP0_TCSTATUS
+                _ehb
+                /* We need to leave the global IE bit set, but clear EXL...*/
+                mfc0    t0, CP0_STATUS
+                ori     t0, ST0_EXL
+                xori    t0, ST0_EXL
+                mtc0    t0, CP0_STATUS
+                /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
+#endif /* CONFIG_MIPS_MT_SMTC */
+                irq_enable_hazard
+                .endm
+
+/*
+ * Just move to kernel mode and leave interrupts as they are.  Note
+ * for the R3000 this means copying the previous enable from IEp.
+ * Set cp0 enable bit as sign that we're running on the kernel stack
+ */
+                .macro  KMODE
+#ifdef CONFIG_MIPS_MT_SMTC
+                /*
+                 * This gets baroque in SMTC.  We want to
+                 * protect the non-atomic clearing of EXL
+                 * with DMT/EMT, but we don't want to take
+                 * an interrupt while DMT is still in effect.
+                 */
+
+                /* KMODE gets invoked from both reorder and noreorder code */
+                .set    push
+                .set    mips32r2
+                .set    noreorder
+                mfc0    v0, CP0_TCSTATUS
+                andi    v1, v0, TCSTATUS_IXMT
+                ori     v0, TCSTATUS_IXMT
+                mtc0    v0, CP0_TCSTATUS
+                _ehb
+                DMT     2                               # dmt   v0
+                /*
+                 * We don't know a priori if ra is "live"
+                 */
+                move    t0, ra
+                jal     mips_ihb
+                nop     /* delay slot */
+                move    ra, t0
+#endif /* CONFIG_MIPS_MT_SMTC */
+                mfc0    t0, CP0_STATUS
+                li      t1, ST0_CU0 | (STATMASK & ~1)
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+                andi    t2, t0, ST0_IEP
+                srl     t2, 2
+                or      t0, t2
+#endif
+                or      t0, t1
+                xori    t0, STATMASK & ~1
+                mtc0    t0, CP0_STATUS
+#ifdef CONFIG_MIPS_MT_SMTC
+                _ehb
+                andi    v0, v0, VPECONTROL_TE
+                beqz    v0, 2f
+                nop     /* delay slot */
+                emt
+2:
+                mfc0    v0, CP0_TCSTATUS
+                /* Clear IXMT, then OR in previous value */
+                ori     v0, TCSTATUS_IXMT
+                xori    v0, TCSTATUS_IXMT
+                or      v0, v1, v0
+                mtc0    v0, CP0_TCSTATUS
+                /*
+                 * irq_disable_hazard below should expand to EHB
+                 * on 24K/34K CPUS
+                 */
+                .set pop
+#endif /* CONFIG_MIPS_MT_SMTC */
+                irq_disable_hazard
+                .endm
+
+#endif /* _ASM_STACKFRAME_H */
diff --git a/arch/mips/include/asm/stacktrace.h b/arch/mips/include/asm/stacktrace.h
new file mode 100644
index 000000000000..0bf82818aa53
--- /dev/null
+++ b/arch/mips/include/asm/stacktrace.h
@@ -0,0 +1,48 @@
+#ifndef _ASM_STACKTRACE_H
+#define _ASM_STACKTRACE_H
+
+#include <asm/ptrace.h>
+
+#ifdef CONFIG_KALLSYMS
+extern int raw_show_trace;
+extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
+                                  unsigned long pc, unsigned long *ra);
+#else
+#define raw_show_trace 1
+static inline unsigned long unwind_stack(struct task_struct *task,
+        unsigned long *sp, unsigned long pc, unsigned long *ra)
+{
+        return 0;
+}
+#endif
+
+static __always_inline void prepare_frametrace(struct pt_regs *regs)
+{
+#ifndef CONFIG_KALLSYMS
+        /*
+         * Remove any garbage that may be in regs (specially func
+         * addresses) to avoid show_raw_backtrace() to report them
+         */
+        memset(regs, 0, sizeof(*regs));
+#endif
+        __asm__ __volatile__(
+                ".set push\n\t"
+                ".set noat\n\t"
+#ifdef CONFIG_64BIT
+                "1: dla $1, 1b\n\t"
+                "sd $1, %0\n\t"
+                "sd $29, %1\n\t"
+                "sd $31, %2\n\t"
+#else
+                "1: la $1, 1b\n\t"
+                "sw $1, %0\n\t"
+                "sw $29, %1\n\t"
+                "sw $31, %2\n\t"
+#endif
+                ".set pop\n\t"
+                : "=m" (regs->cp0_epc),
+                "=m" (regs->regs[29]), "=m" (regs->regs[31])
+                : : "memory");
+}
+
+#endif /* _ASM_STACKTRACE_H */
diff --git a/arch/mips/include/asm/stat.h b/arch/mips/include/asm/stat.h
new file mode 100644
index 000000000000..6e00f751ab6d
--- /dev/null
+++ b/arch/mips/include/asm/stat.h
@@ -0,0 +1,132 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2000 Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_STAT_H
+#define _ASM_STAT_H
+
+#include <linux/types.h>
+
+#include <asm/sgidefs.h>
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+
+struct stat {
+        unsigned        st_dev;
+        long            st_pad1[3];             /* Reserved for network id */
+        ino_t           st_ino;
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+        uid_t           st_uid;
+        gid_t           st_gid;
+        unsigned        st_rdev;
+        long            st_pad2[2];
+        off_t           st_size;
+        long            st_pad3;
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        time_t          st_atime;
+        long            st_atime_nsec;
+        time_t          st_mtime;
+        long            st_mtime_nsec;
+        time_t          st_ctime;
+        long            st_ctime_nsec;
+        long            st_blksize;
+        long            st_blocks;
+        long            st_pad4[14];
+};
+
+/*
+ * This matches struct stat64 in glibc2.1, hence the absolutely insane
+ * amounts of padding around dev_t's.  The memory layout is the same as of
+ * struct stat of the 64-bit kernel.
+ */
+
+struct stat64 {
+        unsigned long   st_dev;
+        unsigned long   st_pad0[3];     /* Reserved for st_dev expansion  */
+
+        unsigned long long      st_ino;
+
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+
+        uid_t           st_uid;
+        gid_t           st_gid;
+
+        unsigned long   st_rdev;
+        unsigned long   st_pad1[3];     /* Reserved for st_rdev expansion  */
+
+        long long       st_size;
+
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        time_t          st_atime;
+        unsigned long   st_atime_nsec;  /* Reserved for st_atime expansion  */
+
+        time_t          st_mtime;
+        unsigned long   st_mtime_nsec;  /* Reserved for st_mtime expansion  */
+
+        time_t          st_ctime;
+        unsigned long   st_ctime_nsec;  /* Reserved for st_ctime expansion  */
+
+        unsigned long   st_blksize;
+        unsigned long   st_pad2;
+
+        long long       st_blocks;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+/* The memory layout is the same as of struct stat64 of the 32-bit kernel.  */
+struct stat {
+        unsigned int            st_dev;
+        unsigned int            st_pad0[3]; /* Reserved for st_dev expansion */
+
+        unsigned long           st_ino;
+
+        mode_t                  st_mode;
+        nlink_t                 st_nlink;
+
+        uid_t                   st_uid;
+        gid_t                   st_gid;
+
+        unsigned int            st_rdev;
+        unsigned int            st_pad1[3]; /* Reserved for st_rdev expansion */
+
+        off_t                   st_size;
+
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        unsigned int            st_atime;
+        unsigned int            st_atime_nsec;
+
+        unsigned int            st_mtime;
+        unsigned int            st_mtime_nsec;
+
+        unsigned int            st_ctime;
+        unsigned int            st_ctime_nsec;
+
+        unsigned int            st_blksize;
+        unsigned int            st_pad2;
+
+        unsigned long           st_blocks;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#define STAT_HAVE_NSEC 1
+
+#endif /* _ASM_STAT_H */
diff --git a/arch/mips/include/asm/statfs.h b/arch/mips/include/asm/statfs.h
new file mode 100644
index 000000000000..c3ddf973c1c0
--- /dev/null
+++ b/arch/mips/include/asm/statfs.h
@@ -0,0 +1,96 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_STATFS_H
+#define _ASM_STATFS_H
+
+#include <linux/posix_types.h>
+#include <asm/sgidefs.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+
+#include <linux/types.h>
+
+typedef __kernel_fsid_t        fsid_t;
+
+#endif
+
+struct statfs {
+        long            f_type;
+#define f_fstyp f_type
+        long            f_bsize;
+        long            f_frsize;       /* Fragment size - unsupported */
+        long            f_blocks;
+        long            f_bfree;
+        long            f_files;
+        long            f_ffree;
+        long            f_bavail;
+
+        /* Linux specials */
+        __kernel_fsid_t f_fsid;
+        long            f_namelen;
+        long            f_spare[6];
+};
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+
+/*
+ * Unlike the traditional version the LFAPI version has none of the ABI junk
+ */
+struct statfs64 {
+        __u32   f_type;
+        __u32   f_bsize;
+        __u32   f_frsize;       /* Fragment size - unsupported */
+        __u32   __pad;
+        __u64   f_blocks;
+        __u64   f_bfree;
+        __u64   f_files;
+        __u64   f_ffree;
+        __u64   f_bavail;
+        __kernel_fsid_t f_fsid;
+        __u32   f_namelen;
+        __u32   f_spare[6];
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+struct statfs64 {                       /* Same as struct statfs */
+        long            f_type;
+        long            f_bsize;
+        long            f_frsize;       /* Fragment size - unsupported */
+        long            f_blocks;
+        long            f_bfree;
+        long            f_files;
+        long            f_ffree;
+        long            f_bavail;
+
+        /* Linux specials */
+        __kernel_fsid_t f_fsid;
+        long            f_namelen;
+        long            f_spare[6];
+};
+
+struct compat_statfs64 {
+        __u32   f_type;
+        __u32   f_bsize;
+        __u32   f_frsize;       /* Fragment size - unsupported */
+        __u32   __pad;
+        __u64   f_blocks;
+        __u64   f_bfree;
+        __u64   f_files;
+        __u64   f_ffree;
+        __u64   f_bavail;
+        __kernel_fsid_t f_fsid;
+        __u32   f_namelen;
+        __u32   f_spare[6];
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#endif /* _ASM_STATFS_H */
diff --git a/arch/mips/include/asm/string.h b/arch/mips/include/asm/string.h
new file mode 100644
index 000000000000..436e3ad352d9
--- /dev/null
+++ b/arch/mips/include/asm/string.h
@@ -0,0 +1,143 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
+ * Copyright (c) 2000 by Silicon Graphics, Inc.
+ * Copyright (c) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_STRING_H
+#define _ASM_STRING_H
+
+
+/*
+ * Most of the inline functions are rather naive implementations so I just
+ * didn't bother updating them for 64-bit ...
+ */
+#ifdef CONFIG_32BIT
+
+#ifndef IN_STRING_C
+
+#define __HAVE_ARCH_STRCPY
+static __inline__ char *strcpy(char *__dest, __const__ char *__src)
+{
+  char *__xdest = __dest;
+
+  __asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n"
+        "1:\tlbu\t$1,(%1)\n\t"
+        "addiu\t%1,1\n\t"
+        "sb\t$1,(%0)\n\t"
+        "bnez\t$1,1b\n\t"
+        "addiu\t%0,1\n\t"
+        ".set\tat\n\t"
+        ".set\treorder"
+        : "=r" (__dest), "=r" (__src)
+        : "0" (__dest), "1" (__src)
+        : "memory");
+
+  return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
+{
+  char *__xdest = __dest;
+
+  if (__n == 0)
+    return __xdest;
+
+  __asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n"
+        "1:\tlbu\t$1,(%1)\n\t"
+        "subu\t%2,1\n\t"
+        "sb\t$1,(%0)\n\t"
+        "beqz\t$1,2f\n\t"
+        "addiu\t%0,1\n\t"
+        "bnez\t%2,1b\n\t"
+        "addiu\t%1,1\n"
+        "2:\n\t"
+        ".set\tat\n\t"
+        ".set\treorder"
+        : "=r" (__dest), "=r" (__src), "=r" (__n)
+        : "0" (__dest), "1" (__src), "2" (__n)
+        : "memory");
+
+  return __xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+static __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
+{
+  int __res;
+
+  __asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n\t"
+        "lbu\t%2,(%0)\n"
+        "1:\tlbu\t$1,(%1)\n\t"
+        "addiu\t%0,1\n\t"
+        "bne\t$1,%2,2f\n\t"
+        "addiu\t%1,1\n\t"
+        "bnez\t%2,1b\n\t"
+        "lbu\t%2,(%0)\n\t"
+#if defined(CONFIG_CPU_R3000)
+        "nop\n\t"
+#endif
+        "move\t%2,$1\n"
+        "2:\tsubu\t%2,$1\n"
+        "3:\t.set\tat\n\t"
+        ".set\treorder"
+        : "=r" (__cs), "=r" (__ct), "=r" (__res)
+        : "0" (__cs), "1" (__ct));
+
+  return __res;
+}
+
+#endif /* !defined(IN_STRING_C) */
+
+#define __HAVE_ARCH_STRNCMP
+static __inline__ int
+strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
+{
+        int __res;
+
+        __asm__ __volatile__(
+        ".set\tnoreorder\n\t"
+        ".set\tnoat\n"
+        "1:\tlbu\t%3,(%0)\n\t"
+        "beqz\t%2,2f\n\t"
+        "lbu\t$1,(%1)\n\t"
+        "subu\t%2,1\n\t"
+        "bne\t$1,%3,3f\n\t"
+        "addiu\t%0,1\n\t"
+        "bnez\t%3,1b\n\t"
+        "addiu\t%1,1\n"
+        "2:\n\t"
+#if defined(CONFIG_CPU_R3000)
+        "nop\n\t"
+#endif
+        "move\t%3,$1\n"
+        "3:\tsubu\t%3,$1\n\t"
+        ".set\tat\n\t"
+        ".set\treorder"
+        : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
+        : "0" (__cs), "1" (__ct), "2" (__count));
+
+        return __res;
+}
+#endif /* CONFIG_32BIT */
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+#endif /* _ASM_STRING_H */
diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h
new file mode 100644
index 000000000000..2562f8f9be0e
--- /dev/null
+++ b/arch/mips/include/asm/suspend.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SUSPEND_H
+#define __ASM_SUSPEND_H
+
+/* Somewhen...  Maybe :-)  */
+
+#endif /* __ASM_SUSPEND_H */
diff --git a/arch/mips/include/asm/sysmips.h b/arch/mips/include/asm/sysmips.h
new file mode 100644
index 000000000000..4f47b7d6a5f7
--- /dev/null
+++ b/arch/mips/include/asm/sysmips.h
@@ -0,0 +1,25 @@
+/*
+ * Definitions for the MIPS sysmips(2) call
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ */
+#ifndef _ASM_SYSMIPS_H
+#define _ASM_SYSMIPS_H
+
+/*
+ * Commands for the sysmips(2) call
+ *
+ * sysmips(2) is deprecated - though some existing software uses it.
+ * We only support the following commands.
+ */
+#define SETNAME                    1    /* set hostname                  */
+#define FLUSH_CACHE                3    /* writeback and invalidate caches */
+#define MIPS_FIXADE                7    /* control address error fixing  */
+#define MIPS_RDNVRAM              10    /* read NVRAM */
+#define MIPS_ATOMIC_SET         2001    /* atomically set variable       */
+
+#endif /* _ASM_SYSMIPS_H */
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
new file mode 100644
index 000000000000..cd30f83235bb
--- /dev/null
+++ b/arch/mips/include/asm/system.h
@@ -0,0 +1,222 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_SYSTEM_H
+#define _ASM_SYSTEM_H
+
+#include <linux/types.h>
+#include <linux/irqflags.h>
+
+#include <asm/addrspace.h>
+#include <asm/barrier.h>
+#include <asm/cmpxchg.h>
+#include <asm/cpu-features.h>
+#include <asm/dsp.h>
+#include <asm/watch.h>
+#include <asm/war.h>
+
+
+/*
+ * switch_to(n) should switch tasks to task nr n, first
+ * checking that n isn't the current task, in which case it does nothing.
+ */
+extern asmlinkage void *resume(void *last, void *next, void *next_ti);
+
+struct task_struct;
+
+#ifdef CONFIG_MIPS_MT_FPAFF
+
+/*
+ * Handle the scheduler resume end of FPU affinity management.  We do this
+ * inline to try to keep the overhead down. If we have been forced to run on
+ * a "CPU" with an FPU because of a previous high level of FP computation,
+ * but did not actually use the FPU during the most recent time-slice (CU1
+ * isn't set), we undo the restriction on cpus_allowed.
+ *
+ * We're not calling set_cpus_allowed() here, because we have no need to
+ * force prompt migration - we're already switching the current CPU to a
+ * different thread.
+ */
+
+#define __mips_mt_fpaff_switch_to(prev)                                 \
+do {                                                                    \
+        struct thread_info *__prev_ti = task_thread_info(prev);         \
+                                                                        \
+        if (cpu_has_fpu &&                                              \
+            test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&             \
+            (!(KSTK_STATUS(prev) & ST0_CU1))) {                         \
+                clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);          \
+                prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
+        }                                                               \
+        next->thread.emulated_fp = 0;                                   \
+} while(0)
+
+#else
+#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
+#endif
+
+#define switch_to(prev, next, last)                                     \
+do {                                                                    \
+        __mips_mt_fpaff_switch_to(prev);                                \
+        if (cpu_has_dsp)                                                \
+                __save_dsp(prev);                                       \
+        (last) = resume(prev, next, task_thread_info(next));            \
+} while (0)
+
+#define finish_arch_switch(prev)                                        \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __restore_dsp(current);                                 \
+        if (cpu_has_userlocal)                                          \
+                write_c0_userlocal(current_thread_info()->tp_value);    \
+        __restore_watch();                                              \
+} while (0)
+
+static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
+{
+        __u32 retval;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %3                  # xchg_u32      \n"
+                "       .set    mips0                                   \n"
+                "       move    %2, %z4                                 \n"
+                "       .set    mips3                                   \n"
+                "       sc      %2, %1                                  \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %3                  # xchg_u32      \n"
+                "       .set    mips0                                   \n"
+                "       move    %2, %z4                                 \n"
+                "       .set    mips3                                   \n"
+                "       sc      %2, %1                                  \n"
+                "       beqz    %2, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                retval = *m;
+                *m = val;
+                raw_local_irq_restore(flags);   /* implies memory barrier  */
+        }
+
+        smp_llsc_mb();
+
+        return retval;
+}
+
+#ifdef CONFIG_64BIT
+static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
+{
+        __u64 retval;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %0, %3                  # xchg_u64      \n"
+                "       move    %2, %z4                                 \n"
+                "       scd     %2, %1                                  \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %0, %3                  # xchg_u64      \n"
+                "       move    %2, %z4                                 \n"
+                "       scd     %2, %1                                  \n"
+                "       beqz    %2, 2f                                  \n"
+                "       .subsection 2                                   \n"
+                "2:     b       1b                                      \n"
+                "       .previous                                       \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                retval = *m;
+                *m = val;
+                raw_local_irq_restore(flags);   /* implies memory barrier  */
+        }
+
+        smp_llsc_mb();
+
+        return retval;
+}
+#else
+extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
+#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
+#endif
+
+/* This function doesn't exist, so you'll get a linker error
+   if something tries to do an invalid xchg().  */
+extern void __xchg_called_with_bad_pointer(void);
+
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+        switch (size) {
+        case 4:
+                return __xchg_u32(ptr, x);
+        case 8:
+                return __xchg_u64(ptr, x);
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
+
+#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
+
+extern void set_handler(unsigned long offset, void *addr, unsigned long len);
+extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
+
+typedef void (*vi_handler_t)(void);
+extern void *set_vi_handler(int n, vi_handler_t addr);
+
+extern void *set_except_vector(int n, void *addr);
+extern unsigned long ebase;
+extern void per_cpu_trap_init(void);
+
+/*
+ * See include/asm-ia64/system.h; prevents deadlock on SMP
+ * systems.
+ */
+#define __ARCH_WANT_UNLOCKED_CTXSW
+
+extern unsigned long arch_align_stack(unsigned long sp);
+
+#endif /* _ASM_SYSTEM_H */
diff --git a/arch/mips/include/asm/termbits.h b/arch/mips/include/asm/termbits.h
new file mode 100644
index 000000000000..c83c68444e86
--- /dev/null
+++ b/arch/mips/include/asm/termbits.h
@@ -0,0 +1,226 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 99, 2001, 06 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_TERMBITS_H
+#define _ASM_TERMBITS_H
+
+#include <linux/posix_types.h>
+
+typedef unsigned char cc_t;
+typedef unsigned int speed_t;
+typedef unsigned int tcflag_t;
+
+/*
+ * The ABI says nothing about NCC but seems to use NCCS as
+ * replacement for it in struct termio
+ */
+#define NCCS    23
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR            0              /* Interrupt character [ISIG].  */
+#define VQUIT            1              /* Quit character [ISIG].  */
+#define VERASE           2              /* Erase character [ICANON].  */
+#define VKILL            3              /* Kill-line character [ICANON].  */
+#define VMIN             4              /* Minimum number of bytes read at once [!ICANON].  */
+#define VTIME            5              /* Time-out value (tenths of a second) [!ICANON].  */
+#define VEOL2            6              /* Second EOL character [ICANON].  */
+#define VSWTC            7              /* ??? */
+#define VSWTCH          VSWTC
+#define VSTART           8              /* Start (X-ON) character [IXON, IXOFF].  */
+#define VSTOP            9              /* Stop (X-OFF) character [IXON, IXOFF].  */
+#define VSUSP           10              /* Suspend character [ISIG].  */
+#if 0
+/*
+ * VDSUSP is not supported
+ */
+#define VDSUSP          11              /* Delayed suspend character [ISIG].  */
+#endif
+#define VREPRINT        12              /* Reprint-line character [ICANON].  */
+#define VDISCARD        13              /* Discard character [IEXTEN].  */
+#define VWERASE         14              /* Word-erase character [ICANON].  */
+#define VLNEXT          15              /* Literal-next character [IEXTEN].  */
+#define VEOF            16              /* End-of-file character [ICANON].  */
+#define VEOL            17              /* End-of-line character [ICANON].  */
+
+/* c_iflag bits */
+#define IGNBRK  0000001         /* Ignore break condition.  */
+#define BRKINT  0000002         /* Signal interrupt on break.  */
+#define IGNPAR  0000004         /* Ignore characters with parity errors.  */
+#define PARMRK  0000010         /* Mark parity and framing errors.  */
+#define INPCK   0000020         /* Enable input parity check.  */
+#define ISTRIP  0000040         /* Strip 8th bit off characters.  */
+#define INLCR   0000100         /* Map NL to CR on input.  */
+#define IGNCR   0000200         /* Ignore CR.  */
+#define ICRNL   0000400         /* Map CR to NL on input.  */
+#define IUCLC   0001000         /* Map upper case to lower case on input.  */
+#define IXON    0002000         /* Enable start/stop output control.  */
+#define IXANY   0004000         /* Any character will restart after stop.  */
+#define IXOFF   0010000         /* Enable start/stop input control.  */
+#define IMAXBEL 0020000         /* Ring bell when input queue is full.  */
+#define IUTF8   0040000         /* Input is UTF-8 */
+
+/* c_oflag bits */
+#define OPOST   0000001         /* Perform output processing.  */
+#define OLCUC   0000002         /* Map lower case to upper case on output.  */
+#define ONLCR   0000004         /* Map NL to CR-NL on output.  */
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+/*
+#define PAGEOUT ???
+#define WRAP    ???
+ */
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060         /* Number of bits per byte (mask).  */
+#define   CS5   0000000         /* 5 bits per byte.  */
+#define   CS6   0000020         /* 6 bits per byte.  */
+#define   CS7   0000040         /* 7 bits per byte.  */
+#define   CS8   0000060         /* 8 bits per byte.  */
+#define CSTOPB  0000100         /* Two stop bits instead of one.  */
+#define CREAD   0000200         /* Enable receiver.  */
+#define PARENB  0000400         /* Parity enable.  */
+#define PARODD  0001000         /* Odd parity instead of even.  */
+#define HUPCL   0002000         /* Hang up on last close.  */
+#define CLOCAL  0004000         /* Ignore modem status lines.  */
+#define CBAUDEX 0010000
+#define    BOTHER 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000  /* input baud rate */
+#define CMSPAR    010000000000  /* mark or space (stick) parity */
+#define CRTSCTS   020000000000  /* flow control */
+
+#define IBSHIFT 16              /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG    0000001         /* Enable signals.  */
+#define ICANON  0000002         /* Do erase and kill processing.  */
+#define XCASE   0000004
+#define ECHO    0000010         /* Enable echo.  */
+#define ECHOE   0000020         /* Visual erase for ERASE.  */
+#define ECHOK   0000040         /* Echo NL after KILL.  */
+#define ECHONL  0000100         /* Echo NL even if ECHO is off.  */
+#define NOFLSH  0000200         /* Disable flush after interrupt.  */
+#define IEXTEN  0000400         /* Enable DISCARD and LNEXT.  */
+#define ECHOCTL 0001000         /* Echo control characters as ^X.  */
+#define ECHOPRT 0002000         /* Hardcopy visual erase.  */
+#define ECHOKE  0004000         /* Visual erase for KILL.  */
+#define FLUSHO  0020000
+#define PENDIN  0040000         /* Retype pending input (state).  */
+#define TOSTOP  0100000         /* Send SIGTTOU for background output.  */
+#define ITOSTOP TOSTOP
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0       /* Suspend output.  */
+#define TCOON           1       /* Restart suspended output.  */
+#define TCIOFF          2       /* Send a STOP character.  */
+#define TCION           3       /* Send a START character.  */
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0       /* Discard data received but not yet read.  */
+#define TCOFLUSH        1       /* Discard data written but not yet sent.  */
+#define TCIOFLUSH       2       /* Discard all pending data.  */
+
+/* tcsetattr uses these */
+#define TCSANOW         TCSETS  /* Change immediately.  */
+#define TCSADRAIN       TCSETSW /* Change when pending output is written.  */
+#define TCSAFLUSH       TCSETSF /* Flush pending input before changing.  */
+
+#endif /* _ASM_TERMBITS_H */
diff --git a/arch/mips/include/asm/termios.h b/arch/mips/include/asm/termios.h
new file mode 100644
index 000000000000..a275661fa7e1
--- /dev/null
+++ b/arch/mips/include/asm/termios.h
@@ -0,0 +1,132 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TERMIOS_H
+#define _ASM_TERMIOS_H
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct sgttyb {
+        char    sg_ispeed;
+        char    sg_ospeed;
+        char    sg_erase;
+        char    sg_kill;
+        int     sg_flags;       /* SGI special - int, not short */
+};
+
+struct tchars {
+        char    t_intrc;
+        char    t_quitc;
+        char    t_startc;
+        char    t_stopc;
+        char    t_eofc;
+        char    t_brkc;
+};
+
+struct ltchars {
+        char    t_suspc;        /* stop process signal */
+        char    t_dsuspc;       /* delayed stop process signal */
+        char    t_rprntc;       /* reprint line */
+        char    t_flushc;       /* flush output (toggles) */
+        char    t_werasc;       /* word erase */
+        char    t_lnextc;       /* literal next character */
+};
+
+/* TIOCGSIZE, TIOCSSIZE not defined yet.  Only needed for SunOS source
+   compatibility anyway ... */
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC     8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        char c_line;                    /* line discipline */
+        unsigned char c_cc[NCCS];       /* control characters */
+};
+
+#ifdef __KERNEL__
+#include <linux/module.h>
+
+/*
+ *      intr=^C         quit=^\         erase=del       kill=^U
+ *      vmin=\1         vtime=\0        eol2=\0         swtc=\0
+ *      start=^Q        stop=^S         susp=^Z         vdsusp=
+ *      reprint=^R      discard=^U      werase=^W       lnext=^V
+ *      eof=^D          eol=\0
+ */
+#define INIT_C_CC "\003\034\177\025\1\0\0\0\021\023\032\0\022\017\027\026\004\0"
+#endif
+
+/* modem lines */
+#define TIOCM_LE        0x001           /* line enable */
+#define TIOCM_DTR       0x002           /* data terminal ready */
+#define TIOCM_RTS       0x004           /* request to send */
+#define TIOCM_ST        0x010           /* secondary transmit */
+#define TIOCM_SR        0x020           /* secondary receive */
+#define TIOCM_CTS       0x040           /* clear to send */
+#define TIOCM_CAR       0x100           /* carrier detect */
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RNG       0x200           /* ring */
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_DSR       0x400           /* data set ready */
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+#ifdef __KERNEL__
+
+#include <linux/string.h>
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        unsigned short tmp; \
+        get_user(tmp, &(termio)->c_iflag); \
+        (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
+        get_user(tmp, &(termio)->c_oflag); \
+        (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
+        get_user(tmp, &(termio)->c_cflag); \
+        (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
+        get_user(tmp, &(termio)->c_lflag); \
+        (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
+        get_user((termios)->c_line, &(termio)->c_line); \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        put_user((termios)->c_line, &(termio)->c_line); \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* _ASM_TERMIOS_H */
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
new file mode 100644
index 000000000000..3f76de73c943
--- /dev/null
+++ b/arch/mips/include/asm/thread_info.h
@@ -0,0 +1,153 @@
+/* thread_info.h: MIPS low-level thread information
+ *
+ * Copyright (C) 2002  David Howells (dhowells@redhat.com)
+ * - Incorporating suggestions made by Linus Torvalds and Dave Miller
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+
+#ifndef __ASSEMBLY__
+
+#include <asm/processor.h>
+
+/*
+ * low level task data that entry.S needs immediate access to
+ * - this struct should fit entirely inside of one cache line
+ * - this struct shares the supervisor stack pages
+ * - if the contents of this structure are changed, the assembly constants
+ *   must also be changed
+ */
+struct thread_info {
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        unsigned long           flags;          /* low level flags */
+        unsigned long           tp_value;       /* thread pointer */
+        __u32                   cpu;            /* current CPU */
+        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
+
+        mm_segment_t            addr_limit;     /* thread address space:
+                                                   0-0xBFFFFFFF for user-thead
+                                                   0-0xFFFFFFFF for kernel-thread
+                                                */
+        struct restart_block    restart_block;
+        struct pt_regs          *regs;
+};
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = _TIF_FIXADE,          \
+        .cpu            = 0,                    \
+        .preempt_count  = 1,                    \
+        .addr_limit     = KERNEL_DS,            \
+        .restart_block  = {                     \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/* How to get the thread information struct from C.  */
+register struct thread_info *__current_thread_info __asm__("$28");
+#define current_thread_info()  __current_thread_info
+
+/* thread information allocation */
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
+#define THREAD_SIZE_ORDER (1)
+#endif
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT)
+#define THREAD_SIZE_ORDER (2)
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define THREAD_SIZE_ORDER (1)
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define THREAD_SIZE_ORDER (0)
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define THREAD_SIZE_ORDER (0)
+#endif
+
+#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define THREAD_MASK (THREAD_SIZE - 1UL)
+
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info(tsk)                                  \
+({                                                              \
+        struct thread_info *ret;                                \
+                                                                \
+        ret = kzalloc(THREAD_SIZE, GFP_KERNEL);                 \
+                                                                \
+        ret;                                                    \
+})
+#else
+#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
+#endif
+
+#define free_thread_info(info) kfree(info)
+
+#endif /* !__ASSEMBLY__ */
+
+#define PREEMPT_ACTIVE          0x10000000
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to
+ *   access
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_SIGPENDING          1       /* signal pending */
+#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
+#define TIF_SYSCALL_AUDIT       3       /* syscall auditing active */
+#define TIF_SECCOMP             4       /* secure computing */
+#define TIF_RESTORE_SIGMASK     9       /* restore signal mask in do_signal() */
+#define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
+#define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
+#define TIF_MEMDIE              18
+#define TIF_FREEZE              19
+#define TIF_FIXADE              20      /* Fix address errors in software */
+#define TIF_LOGADE              21      /* Log address errors to syslog */
+#define TIF_32BIT_REGS          22      /* also implies 16/32 fprs */
+#define TIF_32BIT_ADDR          23      /* 32-bit address space (o32/n32) */
+#define TIF_FPUBOUND            24      /* thread bound to FPU-full CPU set */
+#define TIF_LOAD_WATCH          25      /* If set, load watch registers */
+#define TIF_SYSCALL_TRACE       31      /* syscall trace active */
+
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
+#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_USEDFPU            (1<<TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_FREEZE             (1<<TIF_FREEZE)
+#define _TIF_FIXADE             (1<<TIF_FIXADE)
+#define _TIF_LOGADE             (1<<TIF_LOGADE)
+#define _TIF_32BIT_REGS         (1<<TIF_32BIT_REGS)
+#define _TIF_32BIT_ADDR         (1<<TIF_32BIT_ADDR)
+#define _TIF_FPUBOUND           (1<<TIF_FPUBOUND)
+#define _TIF_LOAD_WATCH         (1<<TIF_LOAD_WATCH)
+
+/* work to do on interrupt/exception return */
+#define _TIF_WORK_MASK          (0x0000ffef & ~_TIF_SECCOMP)
+/* work to do on any return to u-space */
+#define _TIF_ALLWORK_MASK       (0x8000ffff & ~_TIF_SECCOMP)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
new file mode 100644
index 000000000000..d3bd5c5aa2ec
--- /dev/null
+++ b/arch/mips/include/asm/time.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2001, 2002, MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ * Copyright (c) 2003  Maciej W. Rozycki
+ *
+ * include/asm-mips/time.h
+ *     header file for the new style time.c file and time services.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef _ASM_TIME_H
+#define _ASM_TIME_H
+
+#include <linux/rtc.h>
+#include <linux/spinlock.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+
+extern spinlock_t rtc_lock;
+
+/*
+ * RTC ops.  By default, they point to weak no-op RTC functions.
+ *      rtc_mips_set_time - reverse the above translation and set time to RTC.
+ *      rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need
+ *                      to be set.  Used by RTC sync-up.
+ */
+extern int rtc_mips_set_time(unsigned long);
+extern int rtc_mips_set_mmss(unsigned long);
+
+/*
+ * board specific routines required by time_init().
+ */
+extern void plat_time_init(void);
+
+/*
+ * mips_hpt_frequency - must be set if you intend to use an R4k-compatible
+ * counter as a timer interrupt source.
+ */
+extern unsigned int mips_hpt_frequency;
+
+/*
+ * The performance counter IRQ on MIPS is a close relative to the timer IRQ
+ * so it lives here.
+ */
+extern int (*perf_irq)(void);
+
+/*
+ * Initialize the calling CPU's compare interrupt as clockevent device
+ */
+#ifdef CONFIG_CEVT_R4K
+extern int mips_clockevent_init(void);
+extern unsigned int __weak get_c0_compare_int(void);
+#else
+static inline int mips_clockevent_init(void)
+{
+        return -ENXIO;
+}
+#endif
+
+/*
+ * Initialize the count register as a clocksource
+ */
+#ifdef CONFIG_CEVT_R4K
+extern int init_mips_clocksource(void);
+#else
+static inline int init_mips_clocksource(void)
+{
+        return 0;
+}
+#endif
+
+extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock);
+extern void clockevent_set_clock(struct clock_event_device *cd,
+                unsigned int clock);
+
+#endif /* _ASM_TIME_H */
diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h
new file mode 100644
index 000000000000..6529704aa73a
--- /dev/null
+++ b/arch/mips/include/asm/timex.h
@@ -0,0 +1,43 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 1999, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_TIMEX_H
+#define _ASM_TIMEX_H
+
+#ifdef __KERNEL__
+
+#include <asm/mipsregs.h>
+
+/*
+ * This is the clock rate of the i8253 PIT.  A MIPS system may not have
+ * a PIT by the symbol is used all over the kernel including some APIs.
+ * So keeping it defined to the number for the PIT is the only sane thing
+ * for now.
+ */
+#define CLOCK_TICK_RATE 1193182
+
+/*
+ * Standard way to access the cycle counter.
+ * Currently only used on SMP for scheduling.
+ *
+ * Only the low 32 bits are available as a continuously counting entity.
+ * But this only means we'll force a reschedule every 8 seconds or so,
+ * which isn't an evil thing.
+ *
+ * We know that all SMP capable CPUs have cycle counters.
+ */
+
+typedef unsigned int cycles_t;
+
+static inline cycles_t get_cycles(void)
+{
+        return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /*  _ASM_TIMEX_H */
diff --git a/arch/mips/include/asm/titan_dep.h b/arch/mips/include/asm/titan_dep.h
new file mode 100644
index 000000000000..fee1908c65d2
--- /dev/null
+++ b/arch/mips/include/asm/titan_dep.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright 2003 PMC-Sierra
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * Board specific definititions for the PMC-Sierra Yosemite
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __TITAN_DEP_H__
+#define __TITAN_DEP_H__
+
+#include <asm/addrspace.h>              /* for KSEG1ADDR() */
+#include <asm/byteorder.h>              /* for cpu_to_le32() */
+
+#define TITAN_READ(ofs)                                                 \
+        (*(volatile u32 *)(ocd_base+(ofs)))
+#define TITAN_READ_16(ofs)                                              \
+        (*(volatile u16 *)(ocd_base+(ofs)))
+#define TITAN_READ_8(ofs)                                               \
+        (*(volatile u8 *)(ocd_base+(ofs)))
+
+#define TITAN_WRITE(ofs, data)                                          \
+        do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_16(ofs, data)                                       \
+        do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_8(ofs, data)                                        \
+        do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
+
+/*
+ * PCI specific defines
+ */
+#define TITAN_PCI_0_CONFIG_ADDRESS      0x780
+#define TITAN_PCI_0_CONFIG_DATA         0x784
+
+/*
+ * HT specific defines
+ */
+#define RM9000x2_HTLINK_REG             0xbb000644
+#define RM9000x2_BASE_ADDR              0xbb000000
+
+#define OCD_BASE                        0xfb000000UL
+#define OCD_SIZE                        0x3000UL
+
+extern unsigned long ocd_base;
+
+/*
+ * OCD Registers
+ */
+#define RM9000x2_OCD_LKB5               0x0128          /* Ethernet */
+#define RM9000x2_OCD_LKM5               0x012c
+
+#define RM9000x2_OCD_LKB7               0x0138          /* HT Region 0 */
+#define RM9000x2_OCD_LKM7               0x013c
+#define RM9000x2_OCD_LKB8               0x0140          /* HT Region 1 */
+#define RM9000x2_OCD_LKM8               0x0144
+
+#define RM9000x2_OCD_LKB9               0x0148          /* Local Bus */
+#define RM9000x2_OCD_LKM9               0x014c
+#define RM9000x2_OCD_LKB10              0x0150
+#define RM9000x2_OCD_LKM10              0x0154
+#define RM9000x2_OCD_LKB11              0x0158
+#define RM9000x2_OCD_LKM11              0x015c
+#define RM9000x2_OCD_LKB12              0x0160
+#define RM9000x2_OCD_LKM12              0x0164
+
+#define RM9000x2_OCD_LKB13              0x0168          /* Scratch RAM */
+#define RM9000x2_OCD_LKM13              0x016c
+
+#define RM9000x2_OCD_LPD0               0x0200          /* Local Bus */
+#define RM9000x2_OCD_LPD1               0x0210
+#define RM9000x2_OCD_LPD2               0x0220
+#define RM9000x2_OCD_LPD3               0x0230
+
+#define RM9000x2_OCD_HTDVID             0x0600  /* HT Device Header */
+#define RM9000x2_OCD_HTSC               0x0604
+#define RM9000x2_OCD_HTCCR              0x0608
+#define RM9000x2_OCD_HTBHL              0x060c
+#define RM9000x2_OCD_HTBAR0             0x0610
+#define RM9000x2_OCD_HTBAR1             0x0614
+#define RM9000x2_OCD_HTBAR2             0x0618
+#define RM9000x2_OCD_HTBAR3             0x061c
+#define RM9000x2_OCD_HTBAR4             0x0620
+#define RM9000x2_OCD_HTBAR5             0x0624
+#define RM9000x2_OCD_HTCBCPT            0x0628
+#define RM9000x2_OCD_HTSDVID            0x062c
+#define RM9000x2_OCD_HTXRA              0x0630
+#define RM9000x2_OCD_HTCAP1             0x0634
+#define RM9000x2_OCD_HTIL               0x063c
+
+#define RM9000x2_OCD_HTLCC              0x0640  /* HT Capability Block */
+#define RM9000x2_OCD_HTLINK             0x0644
+#define RM9000x2_OCD_HTFQREV            0x0648
+
+#define RM9000x2_OCD_HTERCTL            0x0668  /* HT Controller */
+#define RM9000x2_OCD_HTRXDB             0x066c
+#define RM9000x2_OCD_HTIMPED            0x0670
+#define RM9000x2_OCD_HTSWIMP            0x0674
+#define RM9000x2_OCD_HTCAL              0x0678
+
+#define RM9000x2_OCD_HTBAA30            0x0680
+#define RM9000x2_OCD_HTBAA54            0x0684
+#define RM9000x2_OCD_HTMASK0            0x0688
+#define RM9000x2_OCD_HTMASK1            0x068c
+#define RM9000x2_OCD_HTMASK2            0x0690
+#define RM9000x2_OCD_HTMASK3            0x0694
+#define RM9000x2_OCD_HTMASK4            0x0698
+#define RM9000x2_OCD_HTMASK5            0x069c
+
+#define RM9000x2_OCD_HTIFCTL            0x06a0
+#define RM9000x2_OCD_HTPLL              0x06a4
+
+#define RM9000x2_OCD_HTSRI              0x06b0
+#define RM9000x2_OCD_HTRXNUM            0x06b4
+#define RM9000x2_OCD_HTTXNUM            0x06b8
+
+#define RM9000x2_OCD_HTTXCNT            0x06c8
+
+#define RM9000x2_OCD_HTERROR            0x06d8
+#define RM9000x2_OCD_HTRCRCE            0x06dc
+#define RM9000x2_OCD_HTEOI              0x06e0
+
+#define RM9000x2_OCD_CRCR               0x06f0
+
+#define RM9000x2_OCD_HTCFGA             0x06f8
+#define RM9000x2_OCD_HTCFGD             0x06fc
+
+#define RM9000x2_OCD_INTMSG             0x0a00
+
+#define RM9000x2_OCD_INTPIN0            0x0a40
+#define RM9000x2_OCD_INTPIN1            0x0a44
+#define RM9000x2_OCD_INTPIN2            0x0a48
+#define RM9000x2_OCD_INTPIN3            0x0a4c
+#define RM9000x2_OCD_INTPIN4            0x0a50
+#define RM9000x2_OCD_INTPIN5            0x0a54
+#define RM9000x2_OCD_INTPIN6            0x0a58
+#define RM9000x2_OCD_INTPIN7            0x0a5c
+#define RM9000x2_OCD_SEM                0x0a60
+#define RM9000x2_OCD_SEMSET             0x0a64
+#define RM9000x2_OCD_SEMCLR             0x0a68
+
+#define RM9000x2_OCD_TKT                0x0a70
+#define RM9000x2_OCD_TKTINC             0x0a74
+
+#define RM9000x2_OCD_NMICONFIG          0x0ac0          /* Interrupts */
+#define RM9000x2_OCD_INTP0PRI           0x1a80
+#define RM9000x2_OCD_INTP1PRI           0x1a80
+#define RM9000x2_OCD_INTP0STATUS0       0x1b00
+#define RM9000x2_OCD_INTP0MASK0         0x1b04
+#define RM9000x2_OCD_INTP0SET0          0x1b08
+#define RM9000x2_OCD_INTP0CLEAR0        0x1b0c
+#define RM9000x2_OCD_INTP0STATUS1       0x1b10
+#define RM9000x2_OCD_INTP0MASK1         0x1b14
+#define RM9000x2_OCD_INTP0SET1          0x1b18
+#define RM9000x2_OCD_INTP0CLEAR1        0x1b1c
+#define RM9000x2_OCD_INTP0STATUS2       0x1b20
+#define RM9000x2_OCD_INTP0MASK2         0x1b24
+#define RM9000x2_OCD_INTP0SET2          0x1b28
+#define RM9000x2_OCD_INTP0CLEAR2        0x1b2c
+#define RM9000x2_OCD_INTP0STATUS3       0x1b30
+#define RM9000x2_OCD_INTP0MASK3         0x1b34
+#define RM9000x2_OCD_INTP0SET3          0x1b38
+#define RM9000x2_OCD_INTP0CLEAR3        0x1b3c
+#define RM9000x2_OCD_INTP0STATUS4       0x1b40
+#define RM9000x2_OCD_INTP0MASK4         0x1b44
+#define RM9000x2_OCD_INTP0SET4          0x1b48
+#define RM9000x2_OCD_INTP0CLEAR4        0x1b4c
+#define RM9000x2_OCD_INTP0STATUS5       0x1b50
+#define RM9000x2_OCD_INTP0MASK5         0x1b54
+#define RM9000x2_OCD_INTP0SET5          0x1b58
+#define RM9000x2_OCD_INTP0CLEAR5        0x1b5c
+#define RM9000x2_OCD_INTP0STATUS6       0x1b60
+#define RM9000x2_OCD_INTP0MASK6         0x1b64
+#define RM9000x2_OCD_INTP0SET6          0x1b68
+#define RM9000x2_OCD_INTP0CLEAR6        0x1b6c
+#define RM9000x2_OCD_INTP0STATUS7       0x1b70
+#define RM9000x2_OCD_INTP0MASK7         0x1b74
+#define RM9000x2_OCD_INTP0SET7          0x1b78
+#define RM9000x2_OCD_INTP0CLEAR7        0x1b7c
+#define RM9000x2_OCD_INTP1STATUS0       0x2b00
+#define RM9000x2_OCD_INTP1MASK0         0x2b04
+#define RM9000x2_OCD_INTP1SET0          0x2b08
+#define RM9000x2_OCD_INTP1CLEAR0        0x2b0c
+#define RM9000x2_OCD_INTP1STATUS1       0x2b10
+#define RM9000x2_OCD_INTP1MASK1         0x2b14
+#define RM9000x2_OCD_INTP1SET1          0x2b18
+#define RM9000x2_OCD_INTP1CLEAR1        0x2b1c
+#define RM9000x2_OCD_INTP1STATUS2       0x2b20
+#define RM9000x2_OCD_INTP1MASK2         0x2b24
+#define RM9000x2_OCD_INTP1SET2          0x2b28
+#define RM9000x2_OCD_INTP1CLEAR2        0x2b2c
+#define RM9000x2_OCD_INTP1STATUS3       0x2b30
+#define RM9000x2_OCD_INTP1MASK3         0x2b34
+#define RM9000x2_OCD_INTP1SET3          0x2b38
+#define RM9000x2_OCD_INTP1CLEAR3        0x2b3c
+#define RM9000x2_OCD_INTP1STATUS4       0x2b40
+#define RM9000x2_OCD_INTP1MASK4         0x2b44
+#define RM9000x2_OCD_INTP1SET4          0x2b48
+#define RM9000x2_OCD_INTP1CLEAR4        0x2b4c
+#define RM9000x2_OCD_INTP1STATUS5       0x2b50
+#define RM9000x2_OCD_INTP1MASK5         0x2b54
+#define RM9000x2_OCD_INTP1SET5          0x2b58
+#define RM9000x2_OCD_INTP1CLEAR5        0x2b5c
+#define RM9000x2_OCD_INTP1STATUS6       0x2b60
+#define RM9000x2_OCD_INTP1MASK6         0x2b64
+#define RM9000x2_OCD_INTP1SET6          0x2b68
+#define RM9000x2_OCD_INTP1CLEAR6        0x2b6c
+#define RM9000x2_OCD_INTP1STATUS7       0x2b70
+#define RM9000x2_OCD_INTP1MASK7         0x2b74
+#define RM9000x2_OCD_INTP1SET7          0x2b78
+#define RM9000x2_OCD_INTP1CLEAR7        0x2b7c
+
+#define OCD_READ(reg)           (*(volatile unsigned int *)(ocd_base + (reg)))
+#define OCD_WRITE(reg, val)                                     \
+        do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
+
+/*
+ * Hypertransport specific macros
+ */
+#define RM9K_WRITE(ofs, data)   *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
+#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
+#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
+
+#define RM9K_READ(ofs, val)     *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
+#define RM9K_READ_8(ofs, val)   *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
+#define RM9K_READ_16(ofs, val)  *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
+
+#endif
diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
new file mode 100644
index 000000000000..80d9dfcf1e88
--- /dev/null
+++ b/arch/mips/include/asm/tlb.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_TLB_H
+#define __ASM_TLB_H
+
+/*
+ * MIPS doesn't need any special per-pte or per-vma handling, except
+ * we need to flush cache for area to be unmapped.
+ */
+#define tlb_start_vma(tlb, vma)                                 \
+        do {                                                    \
+                if (!tlb->fullmm)                               \
+                        flush_cache_range(vma, vma->vm_start, vma->vm_end); \
+        }  while (0)
+#define tlb_end_vma(tlb, vma) do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
+
+/*
+ * .. because we flush the whole mm when it fills up.
+ */
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+
+#endif /* __ASM_TLB_H */
diff --git a/arch/mips/include/asm/tlbdebug.h b/arch/mips/include/asm/tlbdebug.h
new file mode 100644
index 000000000000..bb8f5c29c3d9
--- /dev/null
+++ b/arch/mips/include/asm/tlbdebug.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002 by Ralf Baechle
+ */
+#ifndef __ASM_TLBDEBUG_H
+#define __ASM_TLBDEBUG_H
+
+/*
+ * TLB debugging functions:
+ */
+extern void dump_tlb_all(void);
+
+#endif /* __ASM_TLBDEBUG_H */
diff --git a/arch/mips/include/asm/tlbflush.h b/arch/mips/include/asm/tlbflush.h
new file mode 100644
index 000000000000..86b21de12e91
--- /dev/null
+++ b/arch/mips/include/asm/tlbflush.h
@@ -0,0 +1,47 @@
+#ifndef __ASM_TLBFLUSH_H
+#define __ASM_TLBFLUSH_H
+
+#include <linux/mm.h>
+
+/*
+ * TLB flushing:
+ *
+ *  - flush_tlb_all() flushes all processes TLB entries
+ *  - flush_tlb_mm(mm) flushes the specified mm context TLB entries
+ *  - flush_tlb_page(vma, vmaddr) flushes one page
+ *  - flush_tlb_range(vma, start, end) flushes a range of pages
+ *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
+ */
+extern void local_flush_tlb_all(void);
+extern void local_flush_tlb_mm(struct mm_struct *mm);
+extern void local_flush_tlb_range(struct vm_area_struct *vma,
+        unsigned long start, unsigned long end);
+extern void local_flush_tlb_kernel_range(unsigned long start,
+        unsigned long end);
+extern void local_flush_tlb_page(struct vm_area_struct *vma,
+        unsigned long page);
+extern void local_flush_tlb_one(unsigned long vaddr);
+
+#ifdef CONFIG_SMP
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long,
+        unsigned long);
+extern void flush_tlb_kernel_range(unsigned long, unsigned long);
+extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
+extern void flush_tlb_one(unsigned long vaddr);
+
+#else /* CONFIG_SMP */
+
+#define flush_tlb_all()                 local_flush_tlb_all()
+#define flush_tlb_mm(mm)                local_flush_tlb_mm(mm)
+#define flush_tlb_range(vma, vmaddr, end)       local_flush_tlb_range(vma, vmaddr, end)
+#define flush_tlb_kernel_range(vmaddr,end) \
+        local_flush_tlb_kernel_range(vmaddr, end)
+#define flush_tlb_page(vma, page)       local_flush_tlb_page(vma, page)
+#define flush_tlb_one(vaddr)            local_flush_tlb_one(vaddr)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_TLBFLUSH_H */
diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h
new file mode 100644
index 000000000000..259145e07e97
--- /dev/null
+++ b/arch/mips/include/asm/topology.h
@@ -0,0 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle
+ */
+#ifndef __ASM_TOPOLOGY_H
+#define __ASM_TOPOLOGY_H
+
+#include <topology.h>
+
+#ifdef CONFIG_SMP
+#define smt_capable()   (smp_num_siblings > 1)
+#endif
+
+#endif /* __ASM_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
new file mode 100644
index 000000000000..90ff2f497c50
--- /dev/null
+++ b/arch/mips/include/asm/traps.h
@@ -0,0 +1,28 @@
+/*
+ *      Trap handling definitions.
+ *
+ *      Copyright (C) 2002, 2003  Maciej W. Rozycki
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_TRAPS_H
+#define _ASM_TRAPS_H
+
+/*
+ * Possible status responses for a board_be_handler backend.
+ */
+#define MIPS_BE_DISCARD 0               /* return with no action */
+#define MIPS_BE_FIXUP   1               /* return to the fixup code */
+#define MIPS_BE_FATAL   2               /* treat as an unrecoverable error */
+
+extern void (*board_be_init)(void);
+extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
+
+extern void (*board_nmi_handler_setup)(void);
+extern void (*board_ejtag_handler_setup)(void);
+extern void (*board_bind_eic_interrupt)(int irq, int regset);
+
+#endif /* _ASM_TRAPS_H */
diff --git a/arch/mips/include/asm/txx9/boards.h b/arch/mips/include/asm/txx9/boards.h
new file mode 100644
index 000000000000..cbe9476d963e
--- /dev/null
+++ b/arch/mips/include/asm/txx9/boards.h
@@ -0,0 +1,13 @@
+#ifdef CONFIG_TOSHIBA_JMR3927
+BOARD_VEC(jmr3927_vec)
+#endif
+#ifdef CONFIG_TOSHIBA_RBTX4927
+BOARD_VEC(rbtx4927_vec)
+BOARD_VEC(rbtx4937_vec)
+#endif
+#ifdef CONFIG_TOSHIBA_RBTX4938
+BOARD_VEC(rbtx4938_vec)
+#endif
+#ifdef CONFIG_TOSHIBA_RBTX4939
+BOARD_VEC(rbtx4939_vec)
+#endif
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
new file mode 100644
index 000000000000..4316a3e57678
--- /dev/null
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -0,0 +1,89 @@
+/*
+ * linux/include/asm-mips/txx9/generic.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_GENERIC_H
+#define __ASM_TXX9_GENERIC_H
+
+#include <linux/init.h>
+#include <linux/ioport.h>       /* for struct resource */
+
+extern struct resource txx9_ce_res[];
+#define TXX9_CE(n)      (unsigned long)(txx9_ce_res[(n)].start)
+extern unsigned int txx9_pcode;
+extern char txx9_pcode_str[8];
+void txx9_reg_res_init(unsigned int pcode, unsigned long base,
+                       unsigned long size);
+
+extern unsigned int txx9_master_clock;
+extern unsigned int txx9_cpu_clock;
+extern unsigned int txx9_gbus_clock;
+#define TXX9_IMCLK      (txx9_gbus_clock / 2)
+
+extern int txx9_ccfg_toeon;
+struct uart_port;
+int early_serial_txx9_setup(struct uart_port *port);
+
+struct pci_dev;
+struct txx9_board_vec {
+        const char *system;
+        void (*prom_init)(void);
+        void (*mem_setup)(void);
+        void (*irq_setup)(void);
+        void (*time_init)(void);
+        void (*arch_init)(void);
+        void (*device_init)(void);
+#ifdef CONFIG_PCI
+        int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
+#endif
+};
+extern struct txx9_board_vec *txx9_board_vec;
+extern int (*txx9_irq_dispatch)(int pending);
+char *prom_getcmdline(void);
+const char *prom_getenv(const char *name);
+void txx9_wdt_init(unsigned long base);
+void txx9_wdt_now(unsigned long base);
+void txx9_spi_init(int busid, unsigned long base, int irq);
+void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr);
+void txx9_sio_init(unsigned long baseaddr, int irq,
+                   unsigned int line, unsigned int sclk, int nocts);
+void prom_putchar(char c);
+#ifdef CONFIG_EARLY_PRINTK
+extern void (*txx9_prom_putchar)(char c);
+void txx9_sio_putchar_init(unsigned long baseaddr);
+#else
+static inline void txx9_sio_putchar_init(unsigned long baseaddr)
+{
+}
+#endif
+
+struct physmap_flash_data;
+void txx9_physmap_flash_init(int no, unsigned long addr, unsigned long size,
+                             const struct physmap_flash_data *pdata);
+
+/* 8 bit version of __fls(): find first bit set (returns 0..7) */
+static inline unsigned int __fls8(unsigned char x)
+{
+        int r = 7;
+
+        if (!(x & 0xf0)) {
+                r -= 4;
+                x <<= 4;
+        }
+        if (!(x & 0xc0)) {
+                r -= 2;
+                x <<= 2;
+        }
+        if (!(x & 0x80))
+                r -= 1;
+        return r;
+}
+
+void txx9_iocled_init(unsigned long baseaddr,
+                      int basenum, unsigned int num, int lowactive,
+                      const char *color, char **deftriggers);
+
+#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h
new file mode 100644
index 000000000000..a409c446bf18
--- /dev/null
+++ b/arch/mips/include/asm/txx9/jmr3927.h
@@ -0,0 +1,180 @@
+/*
+ * Defines for the TJSYS JMR-TX3927
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ */
+#ifndef __ASM_TXX9_JMR3927_H
+#define __ASM_TXX9_JMR3927_H
+
+#include <asm/txx9/tx3927.h>
+#include <asm/addrspace.h>
+#include <asm/system.h>
+#include <asm/txx9irq.h>
+
+/* CS */
+#define JMR3927_ROMCE0  0x1fc00000      /* 4M */
+#define JMR3927_ROMCE1  0x1e000000      /* 4M */
+#define JMR3927_ROMCE2  0x14000000      /* 16M */
+#define JMR3927_ROMCE3  0x10000000      /* 64M */
+#define JMR3927_ROMCE5  0x1d000000      /* 4M */
+#define JMR3927_SDCS0   0x00000000      /* 32M */
+#define JMR3927_SDCS1   0x02000000      /* 32M */
+/* PCI Direct Mappings */
+
+#define JMR3927_PCIMEM  0x08000000
+#define JMR3927_PCIMEM_SIZE     0x08000000      /* 128M */
+#define JMR3927_PCIIO   0x15000000
+#define JMR3927_PCIIO_SIZE      0x01000000      /* 16M */
+
+#define JMR3927_SDRAM_SIZE      0x02000000      /* 32M */
+#define JMR3927_PORT_BASE       KSEG1
+
+/* Address map (virtual address) */
+#define JMR3927_ROM0_BASE       (KSEG1 + JMR3927_ROMCE0)
+#define JMR3927_ROM1_BASE       (KSEG1 + JMR3927_ROMCE1)
+#define JMR3927_IOC_BASE        (KSEG1 + JMR3927_ROMCE2)
+#define JMR3927_PCIMEM_BASE     (KSEG1 + JMR3927_PCIMEM)
+#define JMR3927_PCIIO_BASE      (KSEG1 + JMR3927_PCIIO)
+
+#define JMR3927_IOC_REV_ADDR    (JMR3927_IOC_BASE + 0x00000000)
+#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
+#define JMR3927_IOC_LED_ADDR    (JMR3927_IOC_BASE + 0x00020000)
+#define JMR3927_IOC_DIPSW_ADDR  (JMR3927_IOC_BASE + 0x00030000)
+#define JMR3927_IOC_BREV_ADDR   (JMR3927_IOC_BASE + 0x00040000)
+#define JMR3927_IOC_DTR_ADDR    (JMR3927_IOC_BASE + 0x00050000)
+#define JMR3927_IOC_INTS1_ADDR  (JMR3927_IOC_BASE + 0x00080000)
+#define JMR3927_IOC_INTS2_ADDR  (JMR3927_IOC_BASE + 0x00090000)
+#define JMR3927_IOC_INTM_ADDR   (JMR3927_IOC_BASE + 0x000a0000)
+#define JMR3927_IOC_INTP_ADDR   (JMR3927_IOC_BASE + 0x000b0000)
+#define JMR3927_IOC_RESET_ADDR  (JMR3927_IOC_BASE + 0x000f0000)
+
+/* Flash ROM */
+#define JMR3927_FLASH_BASE      (JMR3927_ROM0_BASE)
+#define JMR3927_FLASH_SIZE      0x00400000
+
+/* bits for IOC_REV/IOC_BREV (high byte) */
+#define JMR3927_IDT_MASK        0xfc
+#define JMR3927_REV_MASK        0x03
+#define JMR3927_IOC_IDT         0xe0
+
+/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
+#define JMR3927_IOC_INTB_PCIA   0
+#define JMR3927_IOC_INTB_PCIB   1
+#define JMR3927_IOC_INTB_PCIC   2
+#define JMR3927_IOC_INTB_PCID   3
+#define JMR3927_IOC_INTB_MODEM  4
+#define JMR3927_IOC_INTB_INT6   5
+#define JMR3927_IOC_INTB_INT7   6
+#define JMR3927_IOC_INTB_SOFT   7
+#define JMR3927_IOC_INTF_PCIA   (1 << JMR3927_IOC_INTF_PCIA)
+#define JMR3927_IOC_INTF_PCIB   (1 << JMR3927_IOC_INTB_PCIB)
+#define JMR3927_IOC_INTF_PCIC   (1 << JMR3927_IOC_INTB_PCIC)
+#define JMR3927_IOC_INTF_PCID   (1 << JMR3927_IOC_INTB_PCID)
+#define JMR3927_IOC_INTF_MODEM  (1 << JMR3927_IOC_INTB_MODEM)
+#define JMR3927_IOC_INTF_INT6   (1 << JMR3927_IOC_INTB_INT6)
+#define JMR3927_IOC_INTF_INT7   (1 << JMR3927_IOC_INTB_INT7)
+#define JMR3927_IOC_INTF_SOFT   (1 << JMR3927_IOC_INTB_SOFT)
+
+/* bits for IOC_RESET (high byte) */
+#define JMR3927_IOC_RESET_CPU   1
+#define JMR3927_IOC_RESET_PCI   2
+
+#if defined(__BIG_ENDIAN)
+#define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)(a)) = (d))
+#define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)(a))
+#elif defined(__LITTLE_ENDIAN)
+#define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)((a)^1)) = (d))
+#define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)((a)^1))
+#else
+#error "No Endian"
+#endif
+
+/* LED macro */
+#define jmr3927_led_set(n/*0-16*/)      jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
+
+#define jmr3927_led_and_set(n/*0-16*/)  jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
+
+/* DIPSW4 macro */
+#define jmr3927_dipsw1()        (gpio_get_value(11) == 0)
+#define jmr3927_dipsw2()        (gpio_get_value(10) == 0)
+#define jmr3927_dipsw3()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
+#define jmr3927_dipsw4()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
+
+/*
+ * IRQ mappings
+ */
+
+/* These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an JMR machine.  Add new 'spaces' as new
+ * IRQ hardware is supported.
+ */
+#define JMR3927_NR_IRQ_IRC      16      /* On-Chip IRC */
+#define JMR3927_NR_IRQ_IOC      8       /* PCI/MODEM/INT[6:7] */
+
+#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
+#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
+#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
+
+#define JMR3927_IRQ_IRC_INT0    (JMR3927_IRQ_IRC + TX3927_IR_INT0)
+#define JMR3927_IRQ_IRC_INT1    (JMR3927_IRQ_IRC + TX3927_IR_INT1)
+#define JMR3927_IRQ_IRC_INT2    (JMR3927_IRQ_IRC + TX3927_IR_INT2)
+#define JMR3927_IRQ_IRC_INT3    (JMR3927_IRQ_IRC + TX3927_IR_INT3)
+#define JMR3927_IRQ_IRC_INT4    (JMR3927_IRQ_IRC + TX3927_IR_INT4)
+#define JMR3927_IRQ_IRC_INT5    (JMR3927_IRQ_IRC + TX3927_IR_INT5)
+#define JMR3927_IRQ_IRC_SIO0    (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
+#define JMR3927_IRQ_IRC_SIO1    (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
+#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
+#define JMR3927_IRQ_IRC_DMA     (JMR3927_IRQ_IRC + TX3927_IR_DMA)
+#define JMR3927_IRQ_IRC_PIO     (JMR3927_IRQ_IRC + TX3927_IR_PIO)
+#define JMR3927_IRQ_IRC_PCI     (JMR3927_IRQ_IRC + TX3927_IR_PCI)
+#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
+#define JMR3927_IRQ_IOC_PCIA    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
+#define JMR3927_IRQ_IOC_PCIB    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
+#define JMR3927_IRQ_IOC_PCIC    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
+#define JMR3927_IRQ_IOC_PCID    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
+#define JMR3927_IRQ_IOC_MODEM   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
+#define JMR3927_IRQ_IOC_INT6    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
+#define JMR3927_IRQ_IOC_INT7    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
+#define JMR3927_IRQ_IOC_SOFT    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
+
+/* IOC (PCI, MODEM) */
+#define JMR3927_IRQ_IOCINT      JMR3927_IRQ_IRC_INT1
+/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
+#define JMR3927_IRQ_ETHER0      JMR3927_IRQ_IRC_INT3
+
+/* Clocks */
+#define JMR3927_CORECLK 132710400       /* 132.7MHz */
+
+/*
+ * TX3927 Pin Configuration:
+ *
+ *      PCFG bits               Avail                   Dead
+ *      SELSIO[1:0]:11          RXD[1:0], TXD[1:0]      PIO[6:3]
+ *      SELSIOC[0]:1            CTS[0], RTS[0]          INT[5:4]
+ *      SELSIOC[1]:0,SELDSF:0,  GSDAO[0],GPCST[3]       CTS[1], RTS[1],DSF,
+ *        GDBGE*                                          PIO[2:1]
+ *      SELDMA[2]:1             DMAREQ[2],DMAACK[2]     PIO[13:12]
+ *      SELTMR[2:0]:000                                 TIMER[1:0]
+ *      SELCS:0,SELDMA[1]:0     PIO[11;10]              SDCS_CE[7:6],
+ *                                                        DMAREQ[1],DMAACK[1]
+ *      SELDMA[0]:1             DMAREQ[0],DMAACK[0]     PIO[9:8]
+ *      SELDMA[3]:1             DMAREQ[3],DMAACK[3]     PIO[15:14]
+ *      SELDONE:1               DMADONE                 PIO[7]
+ *
+ * Usable pins are:
+ *      RXD[1;0],TXD[1:0],CTS[0],RTS[0],
+ *      DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
+ *      INT[3:0]
+ */
+
+void jmr3927_prom_init(void);
+void jmr3927_irq_setup(void);
+struct pci_dev;
+int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_JMR3927_H */
diff --git a/arch/mips/include/asm/txx9/pci.h b/arch/mips/include/asm/txx9/pci.h
new file mode 100644
index 000000000000..3d32529060aa
--- /dev/null
+++ b/arch/mips/include/asm/txx9/pci.h
@@ -0,0 +1,39 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_PCI_H
+#define __ASM_TXX9_PCI_H
+
+#include <linux/pci.h>
+
+extern struct pci_controller txx9_primary_pcic;
+struct pci_controller *
+txx9_alloc_pci_controller(struct pci_controller *pcic,
+                          unsigned long mem_base, unsigned long mem_size,
+                          unsigned long io_base, unsigned long io_size);
+
+int txx9_pci66_check(struct pci_controller *hose, int top_bus,
+                        int current_bus);
+extern int txx9_pci_mem_high __initdata;
+
+extern int txx9_pci_option;
+#define TXX9_PCI_OPT_PICMG      0x0002
+#define TXX9_PCI_OPT_CLK_33     0x0008
+#define TXX9_PCI_OPT_CLK_66     0x0010
+#define TXX9_PCI_OPT_CLK_MASK   \
+        (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
+#define TXX9_PCI_OPT_CLK_AUTO   TXX9_PCI_OPT_CLK_MASK
+
+enum txx9_pci_err_action {
+        TXX9_PCI_ERR_REPORT,
+        TXX9_PCI_ERR_IGNORE,
+        TXX9_PCI_ERR_PANIC,
+};
+extern enum txx9_pci_err_action txx9_pci_err_action;
+
+extern char * (*txx9_board_pcibios_setup)(char *str);
+char *txx9_pcibios_setup(char *str);
+
+#endif /* __ASM_TXX9_PCI_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4927.h b/arch/mips/include/asm/txx9/rbtx4927.h
new file mode 100644
index 000000000000..b2adab3d1acc
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4927.h
@@ -0,0 +1,92 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TXX9_RBTX4927_H
+#define __ASM_TXX9_RBTX4927_H
+
+#include <asm/txx9/tx4927.h>
+
+#define RBTX4927_PCIMEM         0x08000000
+#define RBTX4927_PCIMEM_SIZE    0x08000000
+#define RBTX4927_PCIIO          0x16000000
+#define RBTX4927_PCIIO_SIZE     0x01000000
+
+#define RBTX4927_LED_ADDR       (IO_BASE + TXX9_CE(2) + 0x00001000)
+#define RBTX4927_IMASK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002000)
+#define RBTX4927_IMSTAT_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002006)
+#define RBTX4927_SOFTINT_ADDR   (IO_BASE + TXX9_CE(2) + 0x00003000)
+#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
+#define RBTX4927_SOFTRESETLOCK_ADDR     (IO_BASE + TXX9_CE(2) + 0x0000f002)
+#define RBTX4927_PCIRESET_ADDR  (IO_BASE + TXX9_CE(2) + 0x0000f006)
+#define RBTX4927_BRAMRTC_BASE   (IO_BASE + TXX9_CE(2) + 0x00010000)
+#define RBTX4927_ETHER_BASE     (IO_BASE + TXX9_CE(2) + 0x00020000)
+
+/* Ethernet port address */
+#define RBTX4927_ETHER_ADDR     (RBTX4927_ETHER_BASE + 0x280)
+
+#define rbtx4927_imask_addr     ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
+#define rbtx4927_imstat_addr    ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
+#define rbtx4927_softint_addr   ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
+#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
+#define rbtx4927_softresetlock_addr     \
+                                ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
+#define rbtx4927_pcireset_addr  ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
+
+/* bits for ISTAT/IMASK/IMSTAT */
+#define RBTX4927_INTB_PCID      0
+#define RBTX4927_INTB_PCIC      1
+#define RBTX4927_INTB_PCIB      2
+#define RBTX4927_INTB_PCIA      3
+#define RBTX4927_INTF_PCID      (1 << RBTX4927_INTB_PCID)
+#define RBTX4927_INTF_PCIC      (1 << RBTX4927_INTB_PCIC)
+#define RBTX4927_INTF_PCIB      (1 << RBTX4927_INTB_PCIB)
+#define RBTX4927_INTF_PCIA      (1 << RBTX4927_INTB_PCIA)
+
+#define RBTX4927_NR_IRQ_IOC     8       /* IOC */
+
+#define RBTX4927_IRQ_IOC        (TXX9_IRQ_BASE + TX4927_NUM_IR)
+#define RBTX4927_IRQ_IOC_PCID   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
+#define RBTX4927_IRQ_IOC_PCIC   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
+#define RBTX4927_IRQ_IOC_PCIB   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
+#define RBTX4927_IRQ_IOC_PCIA   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
+
+#define RBTX4927_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4927_IR_INT(1))
+
+#ifdef CONFIG_PCI
+#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
+#else
+#define RBTX4927_ISA_IO_OFFSET 0
+#endif
+
+#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base)
+#define RBTX4927_RTL_8019_IRQ  (TXX9_IRQ_BASE + TX4927_IR_INT(3))
+
+void rbtx4927_prom_init(void);
+void rbtx4927_irq_setup(void);
+struct pci_dev;
+int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_RBTX4927_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h
new file mode 100644
index 000000000000..9f0441a28126
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4938.h
@@ -0,0 +1,145 @@
+/*
+ * Definitions for TX4937/TX4938
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TXX9_RBTX4938_H
+#define __ASM_TXX9_RBTX4938_H
+
+#include <asm/addrspace.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/tx4938.h>
+
+/* Address map */
+#define RBTX4938_FPGA_REG_ADDR  (IO_BASE + TXX9_CE(2) + 0x00000000)
+#define RBTX4938_FPGA_REV_ADDR  (IO_BASE + TXX9_CE(2) + 0x00000002)
+#define RBTX4938_CONFIG1_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000004)
+#define RBTX4938_CONFIG2_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000006)
+#define RBTX4938_CONFIG3_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000008)
+#define RBTX4938_LED_ADDR       (IO_BASE + TXX9_CE(2) + 0x00001000)
+#define RBTX4938_DIPSW_ADDR     (IO_BASE + TXX9_CE(2) + 0x00001002)
+#define RBTX4938_BDIPSW_ADDR    (IO_BASE + TXX9_CE(2) + 0x00001004)
+#define RBTX4938_IMASK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002000)
+#define RBTX4938_IMASK2_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002002)
+#define RBTX4938_INTPOL_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002004)
+#define RBTX4938_ISTAT_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002006)
+#define RBTX4938_ISTAT2_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002008)
+#define RBTX4938_IMSTAT_ADDR    (IO_BASE + TXX9_CE(2) + 0x0000200a)
+#define RBTX4938_IMSTAT2_ADDR   (IO_BASE + TXX9_CE(2) + 0x0000200c)
+#define RBTX4938_SOFTINT_ADDR   (IO_BASE + TXX9_CE(2) + 0x00003000)
+#define RBTX4938_PIOSEL_ADDR    (IO_BASE + TXX9_CE(2) + 0x00005000)
+#define RBTX4938_SPICS_ADDR     (IO_BASE + TXX9_CE(2) + 0x00005002)
+#define RBTX4938_SFPWR_ADDR     (IO_BASE + TXX9_CE(2) + 0x00005008)
+#define RBTX4938_SFVOL_ADDR     (IO_BASE + TXX9_CE(2) + 0x0000500a)
+#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
+#define RBTX4938_SOFTRESETLOCK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00007002)
+#define RBTX4938_PCIRESET_ADDR  (IO_BASE + TXX9_CE(2) + 0x00007004)
+#define RBTX4938_ETHER_BASE     (IO_BASE + TXX9_CE(2) + 0x00020000)
+
+/* Ethernet port address (Jumperless Mode (W12:Open)) */
+#define RBTX4938_ETHER_ADDR     (RBTX4938_ETHER_BASE + 0x280)
+
+/* bits for ISTAT/IMASK/IMSTAT */
+#define RBTX4938_INTB_PCID      0
+#define RBTX4938_INTB_PCIC      1
+#define RBTX4938_INTB_PCIB      2
+#define RBTX4938_INTB_PCIA      3
+#define RBTX4938_INTB_RTC       4
+#define RBTX4938_INTB_ATA       5
+#define RBTX4938_INTB_MODEM     6
+#define RBTX4938_INTB_SWINT     7
+#define RBTX4938_INTF_PCID      (1 << RBTX4938_INTB_PCID)
+#define RBTX4938_INTF_PCIC      (1 << RBTX4938_INTB_PCIC)
+#define RBTX4938_INTF_PCIB      (1 << RBTX4938_INTB_PCIB)
+#define RBTX4938_INTF_PCIA      (1 << RBTX4938_INTB_PCIA)
+#define RBTX4938_INTF_RTC       (1 << RBTX4938_INTB_RTC)
+#define RBTX4938_INTF_ATA       (1 << RBTX4938_INTB_ATA)
+#define RBTX4938_INTF_MODEM     (1 << RBTX4938_INTB_MODEM)
+#define RBTX4938_INTF_SWINT     (1 << RBTX4938_INTB_SWINT)
+
+#define rbtx4938_fpga_rev_addr  ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
+#define rbtx4938_led_addr       ((__u8 __iomem *)RBTX4938_LED_ADDR)
+#define rbtx4938_dipsw_addr     ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
+#define rbtx4938_bdipsw_addr    ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
+#define rbtx4938_imask_addr     ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
+#define rbtx4938_imask2_addr    ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
+#define rbtx4938_intpol_addr    ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
+#define rbtx4938_istat_addr     ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
+#define rbtx4938_istat2_addr    ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
+#define rbtx4938_imstat_addr    ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
+#define rbtx4938_imstat2_addr   ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
+#define rbtx4938_softint_addr   ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
+#define rbtx4938_piosel_addr    ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
+#define rbtx4938_spics_addr     ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
+#define rbtx4938_sfpwr_addr     ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
+#define rbtx4938_sfvol_addr     ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
+#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
+#define rbtx4938_softresetlock_addr     \
+                                ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
+#define rbtx4938_pcireset_addr  ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
+
+/*
+ * IRQ mappings
+ */
+
+#define RBTX4938_SOFT_INT0      0       /* not used */
+#define RBTX4938_SOFT_INT1      1       /* not used */
+#define RBTX4938_IRC_INT        2
+#define RBTX4938_TIMER_INT      7
+
+/* These are the virtual IRQ numbers, we divide all IRQ's into
+ * 'spaces', the 'space' determines where and how to enable/disable
+ * that particular IRQ on an RBTX4938 machine.  Add new 'spaces' as new
+ * IRQ hardware is supported.
+ */
+#define RBTX4938_NR_IRQ_IOC     8
+
+#define RBTX4938_IRQ_IRC        TXX9_IRQ_BASE
+#define RBTX4938_IRQ_IOC        (TXX9_IRQ_BASE + TX4938_NUM_IR)
+#define RBTX4938_IRQ_END        (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
+
+#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
+#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
+#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
+#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
+#define RBTX4938_IRQ_IRC_DMA(ch, n)     (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
+#define RBTX4938_IRQ_IRC_PIO    (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
+#define RBTX4938_IRQ_IRC_PDMAC  (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
+#define RBTX4938_IRQ_IRC_PCIC   (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
+#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
+#define RBTX4938_IRQ_IRC_NDFMC  (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
+#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
+#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
+#define RBTX4938_IRQ_IRC_ACLC   (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
+#define RBTX4938_IRQ_IRC_ACLCPME        (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
+#define RBTX4938_IRQ_IRC_PCIC1  (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
+#define RBTX4938_IRQ_IRC_SPI    (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
+#define RBTX4938_IRQ_IOC_PCID   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
+#define RBTX4938_IRQ_IOC_PCIC   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
+#define RBTX4938_IRQ_IOC_PCIB   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
+#define RBTX4938_IRQ_IOC_PCIA   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
+#define RBTX4938_IRQ_IOC_RTC    (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
+#define RBTX4938_IRQ_IOC_ATA    (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
+#define RBTX4938_IRQ_IOC_MODEM  (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
+#define RBTX4938_IRQ_IOC_SWINT  (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
+
+
+/* IOC (PCI, etc) */
+#define RBTX4938_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4938_IR_INT(0))
+/* Onboard 10M Ether */
+#define RBTX4938_IRQ_ETHER      (TXX9_IRQ_BASE + TX4938_IR_INT(1))
+
+#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
+#define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
+
+void rbtx4938_prom_init(void);
+void rbtx4938_irq_setup(void);
+struct pci_dev;
+int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h
new file mode 100644
index 000000000000..1acf428c0b4f
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4939.h
@@ -0,0 +1,133 @@
+/*
+ * Definitions for RBTX4939
+ *
+ * (C) Copyright TOSHIBA CORPORATION 2005-2006
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_TXX9_RBTX4939_H
+#define __ASM_TXX9_RBTX4939_H
+
+#include <asm/addrspace.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4939.h>
+
+/* Address map */
+#define RBTX4939_IOC_REG_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000000)
+#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
+#define RBTX4939_IOC_REV_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000002)
+#define RBTX4939_CONFIG1_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000004)
+#define RBTX4939_CONFIG2_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000006)
+#define RBTX4939_CONFIG3_ADDR   (IO_BASE + TXX9_CE(1) + 0x00000008)
+#define RBTX4939_CONFIG4_ADDR   (IO_BASE + TXX9_CE(1) + 0x0000000a)
+#define RBTX4939_USTAT_ADDR     (IO_BASE + TXX9_CE(1) + 0x00001000)
+#define RBTX4939_UDIPSW_ADDR    (IO_BASE + TXX9_CE(1) + 0x00001002)
+#define RBTX4939_BDIPSW_ADDR    (IO_BASE + TXX9_CE(1) + 0x00001004)
+#define RBTX4939_IEN_ADDR       (IO_BASE + TXX9_CE(1) + 0x00002000)
+#define RBTX4939_IPOL_ADDR      (IO_BASE + TXX9_CE(1) + 0x00002002)
+#define RBTX4939_IFAC1_ADDR     (IO_BASE + TXX9_CE(1) + 0x00002004)
+#define RBTX4939_IFAC2_ADDR     (IO_BASE + TXX9_CE(1) + 0x00002006)
+#define RBTX4939_SOFTINT_ADDR   (IO_BASE + TXX9_CE(1) + 0x00003000)
+#define RBTX4939_ISASTAT_ADDR   (IO_BASE + TXX9_CE(1) + 0x00004000)
+#define RBTX4939_PCISTAT_ADDR   (IO_BASE + TXX9_CE(1) + 0x00004002)
+#define RBTX4939_ROME_ADDR      (IO_BASE + TXX9_CE(1) + 0x00004004)
+#define RBTX4939_SPICS_ADDR     (IO_BASE + TXX9_CE(1) + 0x00004006)
+#define RBTX4939_AUDI_ADDR      (IO_BASE + TXX9_CE(1) + 0x00004008)
+#define RBTX4939_ISAGPIO_ADDR   (IO_BASE + TXX9_CE(1) + 0x0000400a)
+#define RBTX4939_PE1_ADDR       (IO_BASE + TXX9_CE(1) + 0x00005000)
+#define RBTX4939_PE2_ADDR       (IO_BASE + TXX9_CE(1) + 0x00005002)
+#define RBTX4939_PE3_ADDR       (IO_BASE + TXX9_CE(1) + 0x00005004)
+#define RBTX4939_VP_ADDR        (IO_BASE + TXX9_CE(1) + 0x00005006)
+#define RBTX4939_VPRESET_ADDR   (IO_BASE + TXX9_CE(1) + 0x00005008)
+#define RBTX4939_VPSOUT_ADDR    (IO_BASE + TXX9_CE(1) + 0x0000500a)
+#define RBTX4939_VPSIN_ADDR     (IO_BASE + TXX9_CE(1) + 0x0000500c)
+#define RBTX4939_7SEG_ADDR(s, ch)       \
+        (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
+#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
+#define RBTX4939_RESETEN_ADDR   (IO_BASE + TXX9_CE(1) + 0x00007002)
+#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
+#define RBTX4939_ETHER_BASE     (IO_BASE + TXX9_CE(1) + 0x00020000)
+
+/* Ethernet port address */
+#define RBTX4939_ETHER_ADDR     (RBTX4939_ETHER_BASE + 0x300)
+
+/* bits for IEN/IPOL/IFAC */
+#define RBTX4938_INTB_ISA0      0
+#define RBTX4938_INTB_ISA11     1
+#define RBTX4938_INTB_ISA12     2
+#define RBTX4938_INTB_ISA15     3
+#define RBTX4938_INTB_I2S       4
+#define RBTX4938_INTB_SW        5
+#define RBTX4938_INTF_ISA0      (1 << RBTX4938_INTB_ISA0)
+#define RBTX4938_INTF_ISA11     (1 << RBTX4938_INTB_ISA11)
+#define RBTX4938_INTF_ISA12     (1 << RBTX4938_INTB_ISA12)
+#define RBTX4938_INTF_ISA15     (1 << RBTX4938_INTB_ISA15)
+#define RBTX4938_INTF_I2S       (1 << RBTX4938_INTB_I2S)
+#define RBTX4938_INTF_SW        (1 << RBTX4938_INTB_SW)
+
+/* bits for PE1,PE2,PE3 */
+#define RBTX4939_PE1_ATA(ch)    (0x01 << (ch))
+#define RBTX4939_PE1_RMII(ch)   (0x04 << (ch))
+#define RBTX4939_PE2_SIO0       0x01
+#define RBTX4939_PE2_SIO2       0x02
+#define RBTX4939_PE2_SIO3       0x04
+#define RBTX4939_PE2_CIR        0x08
+#define RBTX4939_PE2_SPI        0x10
+#define RBTX4939_PE2_GPIO       0x20
+#define RBTX4939_PE3_VP 0x01
+#define RBTX4939_PE3_VP_P       0x02
+#define RBTX4939_PE3_VP_S       0x04
+
+#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
+#define rbtx4939_ioc_rev_addr   ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
+#define rbtx4939_config1_addr   ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
+#define rbtx4939_config2_addr   ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
+#define rbtx4939_config3_addr   ((u8 __iomem *)RBTX4939_CONFIG3_ADDR)
+#define rbtx4939_config4_addr   ((u8 __iomem *)RBTX4939_CONFIG4_ADDR)
+#define rbtx4939_ustat_addr     ((u8 __iomem *)RBTX4939_USTAT_ADDR)
+#define rbtx4939_udipsw_addr    ((u8 __iomem *)RBTX4939_UDIPSW_ADDR)
+#define rbtx4939_bdipsw_addr    ((u8 __iomem *)RBTX4939_BDIPSW_ADDR)
+#define rbtx4939_ien_addr       ((u8 __iomem *)RBTX4939_IEN_ADDR)
+#define rbtx4939_ipol_addr      ((u8 __iomem *)RBTX4939_IPOL_ADDR)
+#define rbtx4939_ifac1_addr     ((u8 __iomem *)RBTX4939_IFAC1_ADDR)
+#define rbtx4939_ifac2_addr     ((u8 __iomem *)RBTX4939_IFAC2_ADDR)
+#define rbtx4939_softint_addr   ((u8 __iomem *)RBTX4939_SOFTINT_ADDR)
+#define rbtx4939_isastat_addr   ((u8 __iomem *)RBTX4939_ISASTAT_ADDR)
+#define rbtx4939_pcistat_addr   ((u8 __iomem *)RBTX4939_PCISTAT_ADDR)
+#define rbtx4939_rome_addr      ((u8 __iomem *)RBTX4939_ROME_ADDR)
+#define rbtx4939_spics_addr     ((u8 __iomem *)RBTX4939_SPICS_ADDR)
+#define rbtx4939_audi_addr      ((u8 __iomem *)RBTX4939_AUDI_ADDR)
+#define rbtx4939_isagpio_addr   ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR)
+#define rbtx4939_pe1_addr       ((u8 __iomem *)RBTX4939_PE1_ADDR)
+#define rbtx4939_pe2_addr       ((u8 __iomem *)RBTX4939_PE2_ADDR)
+#define rbtx4939_pe3_addr       ((u8 __iomem *)RBTX4939_PE3_ADDR)
+#define rbtx4939_vp_addr        ((u8 __iomem *)RBTX4939_VP_ADDR)
+#define rbtx4939_vpreset_addr   ((u8 __iomem *)RBTX4939_VPRESET_ADDR)
+#define rbtx4939_vpsout_addr    ((u8 __iomem *)RBTX4939_VPSOUT_ADDR)
+#define rbtx4939_vpsin_addr     ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
+#define rbtx4939_7seg_addr(s, ch) \
+                                ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
+#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
+#define rbtx4939_reseten_addr   ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
+#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
+
+/*
+ * IRQ mappings
+ */
+#define RBTX4939_NR_IRQ_IOC     8
+
+#define RBTX4939_IRQ_IOC        (TXX9_IRQ_BASE + TX4939_NUM_IR)
+#define RBTX4939_IRQ_END        (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC)
+
+/* IOC (ISA, etc) */
+#define RBTX4939_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4939_IR_INT(0))
+/* Onboard 10M Ether */
+#define RBTX4939_IRQ_ETHER      (TXX9_IRQ_BASE + TX4939_IR_INT(1))
+
+void rbtx4939_prom_init(void);
+void rbtx4939_irq_setup(void);
+
+#endif /* __ASM_TXX9_RBTX4939_H */
diff --git a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
new file mode 100644
index 000000000000..d1d6332b4ca6
--- /dev/null
+++ b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
@@ -0,0 +1,68 @@
+/*
+ * Interface for smsc fdc48m81x Super IO chip
+ *
+ * Author: MontaVista Software, Inc. source@mvista.com
+ *
+ * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright (C) 2004 MontaVista Software Inc.
+ * Manish Lachwani, mlachwani@mvista.com
+ */
+
+#ifndef _SMSC_FDC37M81X_H_
+#define _SMSC_FDC37M81X_H_
+
+/* Common Registers */
+#define SMSC_FDC37M81X_CONFIG_INDEX  0x00
+#define SMSC_FDC37M81X_CONFIG_DATA   0x01
+#define SMSC_FDC37M81X_CONF          0x02
+#define SMSC_FDC37M81X_INDEX         0x03
+#define SMSC_FDC37M81X_DNUM          0x07
+#define SMSC_FDC37M81X_DID           0x20
+#define SMSC_FDC37M81X_DREV          0x21
+#define SMSC_FDC37M81X_PCNT          0x22
+#define SMSC_FDC37M81X_PMGT          0x23
+#define SMSC_FDC37M81X_OSC           0x24
+#define SMSC_FDC37M81X_CONFPA0       0x26
+#define SMSC_FDC37M81X_CONFPA1       0x27
+#define SMSC_FDC37M81X_TEST4         0x2B
+#define SMSC_FDC37M81X_TEST5         0x2C
+#define SMSC_FDC37M81X_TEST1         0x2D
+#define SMSC_FDC37M81X_TEST2         0x2E
+#define SMSC_FDC37M81X_TEST3         0x2F
+
+/* Logical device numbers */
+#define SMSC_FDC37M81X_FDD           0x00
+#define SMSC_FDC37M81X_PARALLEL      0x03
+#define SMSC_FDC37M81X_SERIAL1       0x04
+#define SMSC_FDC37M81X_SERIAL2       0x05
+#define SMSC_FDC37M81X_KBD           0x07
+#define SMSC_FDC37M81X_AUXIO         0x08
+#define SMSC_FDC37M81X_NONE          0xff
+
+/* Logical device Config Registers */
+#define SMSC_FDC37M81X_ACTIVE        0x30
+#define SMSC_FDC37M81X_BASEADDR0     0x60
+#define SMSC_FDC37M81X_BASEADDR1     0x61
+#define SMSC_FDC37M81X_INT           0x70
+#define SMSC_FDC37M81X_INT2          0x72
+#define SMSC_FDC37M81X_LDCR_F0       0xF0
+
+/* Chip Config Values */
+#define SMSC_FDC37M81X_CONFIG_ENTER  0x55
+#define SMSC_FDC37M81X_CONFIG_EXIT   0xaa
+#define SMSC_FDC37M81X_CHIP_ID       0x4d
+
+unsigned long smsc_fdc37m81x_init(unsigned long port);
+
+void smsc_fdc37m81x_config_beg(void);
+
+void smsc_fdc37m81x_config_end(void);
+
+u8 smsc_fdc37m81x_config_get(u8 reg);
+void smsc_fdc37m81x_config_set(u8 reg, u8 val);
+
+#endif
diff --git a/arch/mips/include/asm/txx9/spi.h b/arch/mips/include/asm/txx9/spi.h
new file mode 100644
index 000000000000..0d727f354557
--- /dev/null
+++ b/arch/mips/include/asm/txx9/spi.h
@@ -0,0 +1,34 @@
+/*
+ * Definitions for TX4937/TX4938 SPI
+ *
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TXX9_SPI_H
+#define __ASM_TXX9_SPI_H
+
+#include <linux/errno.h>
+
+#ifdef CONFIG_SPI
+int spi_eeprom_register(int busid, int chipid, int size);
+int spi_eeprom_read(int busid, int chipid,
+                    int address, unsigned char *buf, int len);
+#else
+static inline int spi_eeprom_register(int busid, int chipid, int size)
+{
+        return -ENODEV;
+}
+static inline int spi_eeprom_read(int busid, int chipid,
+                                  int address, unsigned char *buf, int len)
+{
+        return -ENODEV;
+}
+#endif
+
+#endif /* __ASM_TXX9_SPI_H */
diff --git a/arch/mips/include/asm/txx9/tx3927.h b/arch/mips/include/asm/txx9/tx3927.h
new file mode 100644
index 000000000000..dc30c8d42061
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx3927.h
@@ -0,0 +1,341 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 Toshiba Corporation
+ */
+#ifndef __ASM_TXX9_TX3927_H
+#define __ASM_TXX9_TX3927_H
+
+#define TX3927_REG_BASE 0xfffe0000UL
+#define TX3927_REG_SIZE 0x00010000
+#define TX3927_SDRAMC_REG       (TX3927_REG_BASE + 0x8000)
+#define TX3927_ROMC_REG         (TX3927_REG_BASE + 0x9000)
+#define TX3927_DMA_REG          (TX3927_REG_BASE + 0xb000)
+#define TX3927_IRC_REG          (TX3927_REG_BASE + 0xc000)
+#define TX3927_PCIC_REG         (TX3927_REG_BASE + 0xd000)
+#define TX3927_CCFG_REG         (TX3927_REG_BASE + 0xe000)
+#define TX3927_NR_TMR   3
+#define TX3927_TMR_REG(ch)      (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
+#define TX3927_NR_SIO   2
+#define TX3927_SIO_REG(ch)      (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
+#define TX3927_PIO_REG          (TX3927_REG_BASE + 0xf500)
+
+struct tx3927_sdramc_reg {
+        volatile unsigned long cr[8];
+        volatile unsigned long tr[3];
+        volatile unsigned long cmd;
+        volatile unsigned long smrs[2];
+};
+
+struct tx3927_romc_reg {
+        volatile unsigned long cr[8];
+};
+
+struct tx3927_dma_reg {
+        struct tx3927_dma_ch_reg {
+                volatile unsigned long cha;
+                volatile unsigned long sar;
+                volatile unsigned long dar;
+                volatile unsigned long cntr;
+                volatile unsigned long sair;
+                volatile unsigned long dair;
+                volatile unsigned long ccr;
+                volatile unsigned long csr;
+        } ch[4];
+        volatile unsigned long dbr[8];
+        volatile unsigned long tdhr;
+        volatile unsigned long mcr;
+        volatile unsigned long unused0;
+};
+
+#include <asm/byteorder.h>
+
+#ifdef __BIG_ENDIAN
+#define endian_def_s2(e1, e2)   \
+        volatile unsigned short e1, e2
+#define endian_def_sb2(e1, e2, e3)      \
+        volatile unsigned short e1;volatile unsigned char e2, e3
+#define endian_def_b2s(e1, e2, e3)      \
+        volatile unsigned char e1, e2;volatile unsigned short e3
+#define endian_def_b4(e1, e2, e3, e4)   \
+        volatile unsigned char e1, e2, e3, e4
+#else
+#define endian_def_s2(e1, e2)   \
+        volatile unsigned short e2, e1
+#define endian_def_sb2(e1, e2, e3)      \
+        volatile unsigned char e3, e2;volatile unsigned short e1
+#define endian_def_b2s(e1, e2, e3)      \
+        volatile unsigned short e3;volatile unsigned char e2, e1
+#define endian_def_b4(e1, e2, e3, e4)   \
+        volatile unsigned char e4, e3, e2, e1
+#endif
+
+struct tx3927_pcic_reg {
+        endian_def_s2(did, vid);
+        endian_def_s2(pcistat, pcicmd);
+        endian_def_b4(cc, scc, rpli, rid);
+        endian_def_b4(unused0, ht, mlt, cls);
+        volatile unsigned long ioba;            /* +10 */
+        volatile unsigned long mba;
+        volatile unsigned long unused1[5];
+        endian_def_s2(svid, ssvid);
+        volatile unsigned long unused2;         /* +30 */
+        endian_def_sb2(unused3, unused4, capptr);
+        volatile unsigned long unused5;
+        endian_def_b4(ml, mg, ip, il);
+        volatile unsigned long unused6;         /* +40 */
+        volatile unsigned long istat;
+        volatile unsigned long iim;
+        volatile unsigned long rrt;
+        volatile unsigned long unused7[3];              /* +50 */
+        volatile unsigned long ipbmma;
+        volatile unsigned long ipbioma;         /* +60 */
+        volatile unsigned long ilbmma;
+        volatile unsigned long ilbioma;
+        volatile unsigned long unused8[9];
+        volatile unsigned long tc;              /* +90 */
+        volatile unsigned long tstat;
+        volatile unsigned long tim;
+        volatile unsigned long tccmd;
+        volatile unsigned long pcirrt;          /* +a0 */
+        volatile unsigned long pcirrt_cmd;
+        volatile unsigned long pcirrdt;
+        volatile unsigned long unused9[3];
+        volatile unsigned long tlboap;
+        volatile unsigned long tlbiap;
+        volatile unsigned long tlbmma;          /* +c0 */
+        volatile unsigned long tlbioma;
+        volatile unsigned long sc_msg;
+        volatile unsigned long sc_be;
+        volatile unsigned long tbl;             /* +d0 */
+        volatile unsigned long unused10[3];
+        volatile unsigned long pwmng;           /* +e0 */
+        volatile unsigned long pwmngs;
+        volatile unsigned long unused11[6];
+        volatile unsigned long req_trace;               /* +100 */
+        volatile unsigned long pbapmc;
+        volatile unsigned long pbapms;
+        volatile unsigned long pbapmim;
+        volatile unsigned long bm;              /* +110 */
+        volatile unsigned long cpcibrs;
+        volatile unsigned long cpcibgs;
+        volatile unsigned long pbacs;
+        volatile unsigned long iobas;           /* +120 */
+        volatile unsigned long mbas;
+        volatile unsigned long lbc;
+        volatile unsigned long lbstat;
+        volatile unsigned long lbim;            /* +130 */
+        volatile unsigned long pcistatim;
+        volatile unsigned long ica;
+        volatile unsigned long icd;
+        volatile unsigned long iiadp;           /* +140 */
+        volatile unsigned long iscdp;
+        volatile unsigned long mmas;
+        volatile unsigned long iomas;
+        volatile unsigned long ipciaddr;                /* +150 */
+        volatile unsigned long ipcidata;
+        volatile unsigned long ipcibe;
+};
+
+struct tx3927_ccfg_reg {
+        volatile unsigned long ccfg;
+        volatile unsigned long crir;
+        volatile unsigned long pcfg;
+        volatile unsigned long tear;
+        volatile unsigned long pdcr;
+};
+
+/*
+ * SDRAMC
+ */
+
+/*
+ * ROMC
+ */
+
+/*
+ * DMA
+ */
+/* bits for MCR */
+#define TX3927_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
+#define TX3927_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
+#define TX3927_DMA_MCR_RSFIF    0x00000080
+#define TX3927_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
+#define TX3927_DMA_MCR_LE       0x00000004
+#define TX3927_DMA_MCR_RPRT     0x00000002
+#define TX3927_DMA_MCR_MSTEN    0x00000001
+
+/* bits for CCRn */
+#define TX3927_DMA_CCR_DBINH    0x04000000
+#define TX3927_DMA_CCR_SBINH    0x02000000
+#define TX3927_DMA_CCR_CHRST    0x01000000
+#define TX3927_DMA_CCR_RVBYTE   0x00800000
+#define TX3927_DMA_CCR_ACKPOL   0x00400000
+#define TX3927_DMA_CCR_REQPL    0x00200000
+#define TX3927_DMA_CCR_EGREQ    0x00100000
+#define TX3927_DMA_CCR_CHDN     0x00080000
+#define TX3927_DMA_CCR_DNCTL    0x00060000
+#define TX3927_DMA_CCR_EXTRQ    0x00010000
+#define TX3927_DMA_CCR_INTRQD   0x0000e000
+#define TX3927_DMA_CCR_INTENE   0x00001000
+#define TX3927_DMA_CCR_INTENC   0x00000800
+#define TX3927_DMA_CCR_INTENT   0x00000400
+#define TX3927_DMA_CCR_CHNEN    0x00000200
+#define TX3927_DMA_CCR_XFACT    0x00000100
+#define TX3927_DMA_CCR_SNOP     0x00000080
+#define TX3927_DMA_CCR_DSTINC   0x00000040
+#define TX3927_DMA_CCR_SRCINC   0x00000020
+#define TX3927_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
+#define TX3927_DMA_CCR_XFSZ_1W  TX3927_DMA_CCR_XFSZ(2)
+#define TX3927_DMA_CCR_XFSZ_4W  TX3927_DMA_CCR_XFSZ(4)
+#define TX3927_DMA_CCR_XFSZ_8W  TX3927_DMA_CCR_XFSZ(5)
+#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
+#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
+#define TX3927_DMA_CCR_MEMIO    0x00000002
+#define TX3927_DMA_CCR_ONEAD    0x00000001
+
+/* bits for CSRn */
+#define TX3927_DMA_CSR_CHNACT   0x00000100
+#define TX3927_DMA_CSR_ABCHC    0x00000080
+#define TX3927_DMA_CSR_NCHNC    0x00000040
+#define TX3927_DMA_CSR_NTRNFC   0x00000020
+#define TX3927_DMA_CSR_EXTDN    0x00000010
+#define TX3927_DMA_CSR_CFERR    0x00000008
+#define TX3927_DMA_CSR_CHERR    0x00000004
+#define TX3927_DMA_CSR_DESERR   0x00000002
+#define TX3927_DMA_CSR_SORERR   0x00000001
+
+/*
+ * IRC
+ */
+#define TX3927_IR_INT0  0
+#define TX3927_IR_INT1  1
+#define TX3927_IR_INT2  2
+#define TX3927_IR_INT3  3
+#define TX3927_IR_INT4  4
+#define TX3927_IR_INT5  5
+#define TX3927_IR_SIO0  6
+#define TX3927_IR_SIO1  7
+#define TX3927_IR_SIO(ch)       (6 + (ch))
+#define TX3927_IR_DMA   8
+#define TX3927_IR_PIO   9
+#define TX3927_IR_PCI   10
+#define TX3927_IR_TMR(ch)       (13 + (ch))
+#define TX3927_NUM_IR   16
+
+/*
+ * PCIC
+ */
+/* bits for PCICMD */
+/* see PCI_COMMAND_XXX in linux/pci.h */
+
+/* bits for PCISTAT */
+/* see PCI_STATUS_XXX in linux/pci.h */
+#define PCI_STATUS_NEW_CAP      0x0010
+
+/* bits for ISTAT/IIM */
+#define TX3927_PCIC_IIM_ALL     0x00001600
+
+/* bits for TC */
+#define TX3927_PCIC_TC_OF16E    0x00000020
+#define TX3927_PCIC_TC_IF8E     0x00000010
+#define TX3927_PCIC_TC_OF8E     0x00000008
+
+/* bits for TSTAT/TIM */
+#define TX3927_PCIC_TIM_ALL     0x0003ffff
+
+/* bits for IOBA/MBA */
+/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
+
+/* bits for PBAPMC */
+#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
+#define TX3927_PCIC_PBAPMC_PBAEN        0x00000002
+#define TX3927_PCIC_PBAPMC_BMCEN        0x00000001
+
+/* bits for LBSTAT/LBIM */
+#define TX3927_PCIC_LBIM_ALL    0x0000003e
+
+/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
+#define TX3927_PCIC_PCISTATIM_ALL       0x0000f900
+
+/* bits for LBC */
+#define TX3927_PCIC_LBC_IBSE    0x00004000
+#define TX3927_PCIC_LBC_TIBSE   0x00002000
+#define TX3927_PCIC_LBC_TMFBSE  0x00001000
+#define TX3927_PCIC_LBC_HRST    0x00000800
+#define TX3927_PCIC_LBC_SRST    0x00000400
+#define TX3927_PCIC_LBC_EPCAD   0x00000200
+#define TX3927_PCIC_LBC_MSDSE   0x00000100
+#define TX3927_PCIC_LBC_CRR     0x00000080
+#define TX3927_PCIC_LBC_ILMDE   0x00000040
+#define TX3927_PCIC_LBC_ILIDE   0x00000020
+
+#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX3927_PCIC_MAX_DEVNU   TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX3927_CCFG_TLBOFF      0x00020000
+#define TX3927_CCFG_BEOW        0x00010000
+#define TX3927_CCFG_WR  0x00008000
+#define TX3927_CCFG_TOE 0x00004000
+#define TX3927_CCFG_PCIXARB     0x00002000
+#define TX3927_CCFG_PCI3        0x00001000
+#define TX3927_CCFG_PSNP        0x00000800
+#define TX3927_CCFG_PPRI        0x00000400
+#define TX3927_CCFG_PLLM        0x00000030
+#define TX3927_CCFG_ENDIAN      0x00000004
+#define TX3927_CCFG_HALT        0x00000002
+#define TX3927_CCFG_ACEHOLD     0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX3927_PCFG_SYSCLKEN    0x08000000
+#define TX3927_PCFG_SDRCLKEN_ALL        0x07c00000
+#define TX3927_PCFG_SDRCLKEN(ch)        (0x00400000<<(ch))
+#define TX3927_PCFG_PCICLKEN_ALL        0x003c0000
+#define TX3927_PCFG_PCICLKEN(ch)        (0x00040000<<(ch))
+#define TX3927_PCFG_SELALL      0x0003ffff
+#define TX3927_PCFG_SELCS       0x00020000
+#define TX3927_PCFG_SELDSF      0x00010000
+#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
+#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
+#define TX3927_PCFG_SELSIO_ALL  0x00003000
+#define TX3927_PCFG_SELSIO(ch)  (0x00001000<<(ch))
+#define TX3927_PCFG_SELTMR_ALL  0x00000e00
+#define TX3927_PCFG_SELTMR(ch)  (0x00000200<<(ch))
+#define TX3927_PCFG_SELDONE     0x00000100
+#define TX3927_PCFG_INTDMA_ALL  0x000000f0
+#define TX3927_PCFG_INTDMA(ch)  (0x00000010<<(ch))
+#define TX3927_PCFG_SELDMA_ALL  0x0000000f
+#define TX3927_PCFG_SELDMA(ch)  (0x00000001<<(ch))
+
+#define tx3927_sdramcptr        ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
+#define tx3927_romcptr          ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
+#define tx3927_dmaptr           ((struct tx3927_dma_reg *)TX3927_DMA_REG)
+#define tx3927_pcicptr          ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
+#define tx3927_ccfgptr          ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
+#define tx3927_sioptr(ch)       ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
+#define tx3927_pioptr           ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
+
+#define TX3927_REV_PCODE()      (tx3927_ccfgptr->crir >> 16)
+#define TX3927_ROMC_BA(ch)      (tx3927_romcptr->cr[(ch)] & 0xfff00000)
+#define TX3927_ROMC_SIZE(ch)    \
+        (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
+#define TX3927_ROMC_WIDTH(ch)   (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1))
+
+void tx3927_wdt_init(void);
+void tx3927_setup(void);
+void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
+void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
+struct pci_controller;
+void tx3927_pcic_setup(struct pci_controller *channel,
+                       unsigned long sdram_size, int extarb);
+void tx3927_setup_pcierr_irq(void);
+void tx3927_irq_init(void);
+void tx3927_mtd_init(int ch);
+
+#endif /* __ASM_TXX9_TX3927_H */
diff --git a/arch/mips/include/asm/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h
new file mode 100644
index 000000000000..7d813f1cb98d
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4927.h
@@ -0,0 +1,269 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2001-2006 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_TXX9_TX4927_H
+#define __ASM_TXX9_TX4927_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/tx4927pcic.h>
+
+#ifdef CONFIG_64BIT
+#define TX4927_REG_BASE 0xffffffffff1f0000UL
+#else
+#define TX4927_REG_BASE 0xff1f0000UL
+#endif
+#define TX4927_REG_SIZE 0x00010000
+
+#define TX4927_SDRAMC_REG       (TX4927_REG_BASE + 0x8000)
+#define TX4927_EBUSC_REG        (TX4927_REG_BASE + 0x9000)
+#define TX4927_PCIC_REG         (TX4927_REG_BASE + 0xd000)
+#define TX4927_CCFG_REG         (TX4927_REG_BASE + 0xe000)
+#define TX4927_IRC_REG          (TX4927_REG_BASE + 0xf600)
+#define TX4927_NR_TMR   3
+#define TX4927_TMR_REG(ch)      (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
+#define TX4927_NR_SIO   2
+#define TX4927_SIO_REG(ch)      (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
+#define TX4927_PIO_REG          (TX4927_REG_BASE + 0xf500)
+
+#define TX4927_IR_ECCERR        0
+#define TX4927_IR_WTOERR        1
+#define TX4927_NUM_IR_INT       6
+#define TX4927_IR_INT(n)        (2 + (n))
+#define TX4927_NUM_IR_SIO       2
+#define TX4927_IR_SIO(n)        (8 + (n))
+#define TX4927_NUM_IR_DMA       4
+#define TX4927_IR_DMA(n)        (10 + (n))
+#define TX4927_IR_PIO           14
+#define TX4927_IR_PDMAC         15
+#define TX4927_IR_PCIC          16
+#define TX4927_NUM_IR_TMR       3
+#define TX4927_IR_TMR(n)        (17 + (n))
+#define TX4927_IR_PCIERR        22
+#define TX4927_IR_PCIPME        23
+#define TX4927_IR_ACLC          24
+#define TX4927_IR_ACLCPME       25
+#define TX4927_NUM_IR   32
+
+#define TX4927_IRC_INT  2       /* IP[2] in Status register */
+
+#define TX4927_NUM_PIO  16
+
+struct tx4927_sdramc_reg {
+        u64 cr[4];
+        u64 unused0[4];
+        u64 tr;
+        u64 unused1[2];
+        u64 cmd;
+};
+
+struct tx4927_ebusc_reg {
+        u64 cr[8];
+};
+
+struct tx4927_ccfg_reg {
+        u64 ccfg;
+        u64 crir;
+        u64 pcfg;
+        u64 toea;
+        u64 clkctr;
+        u64 unused0;
+        u64 garbc;
+        u64 unused1;
+        u64 unused2;
+        u64 ramp;
+};
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4927_CCFG_WDRST       0x0000020000000000ULL
+#define TX4927_CCFG_WDREXEN     0x0000010000000000ULL
+#define TX4927_CCFG_BCFG_MASK   0x000000ff00000000ULL
+#define TX4927_CCFG_TINTDIS     0x01000000
+#define TX4927_CCFG_PCI66       0x00800000
+#define TX4927_CCFG_PCIMODE     0x00400000
+#define TX4927_CCFG_DIVMODE_MASK        0x000e0000
+#define TX4927_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4927_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4927_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4927_CCFG_DIVMODE_10  (0x3 << 17)
+#define TX4927_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4927_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4927_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
+#define TX4927_CCFG_BEOW        0x00010000
+#define TX4927_CCFG_WR  0x00008000
+#define TX4927_CCFG_TOE 0x00004000
+#define TX4927_CCFG_PCIARB      0x00002000
+#define TX4927_CCFG_PCIDIVMODE_MASK     0x00001800
+#define TX4927_CCFG_PCIDIVMODE_2_5      0x00000000
+#define TX4927_CCFG_PCIDIVMODE_3        0x00000800
+#define TX4927_CCFG_PCIDIVMODE_5        0x00001000
+#define TX4927_CCFG_PCIDIVMODE_6        0x00001800
+#define TX4927_CCFG_SYSSP_MASK  0x000000c0
+#define TX4927_CCFG_ENDIAN      0x00000004
+#define TX4927_CCFG_HALT        0x00000002
+#define TX4927_CCFG_ACEHOLD     0x00000001
+#define TX4927_CCFG_W1CBITS     (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
+
+/* PCFG : Pin Configuration */
+#define TX4927_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4927_PCFG_SYSCLKEN    0x08000000
+#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4927_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4927_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4927_PCFG_SEL2        0x00000200
+#define TX4927_PCFG_SEL1        0x00000100
+#define TX4927_PCFG_DMASEL_ALL  0x000000ff
+#define TX4927_PCFG_DMASEL0_MASK        0x00000003
+#define TX4927_PCFG_DMASEL1_MASK        0x0000000c
+#define TX4927_PCFG_DMASEL2_MASK        0x00000030
+#define TX4927_PCFG_DMASEL3_MASK        0x000000c0
+#define TX4927_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4927_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4927_PCFG_DMASEL0_ACL0        0x00000002
+#define TX4927_PCFG_DMASEL0_ACL2        0x00000003
+#define TX4927_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4927_PCFG_DMASEL1_SIO1        0x00000004
+#define TX4927_PCFG_DMASEL1_ACL1        0x00000008
+#define TX4927_PCFG_DMASEL1_ACL3        0x0000000c
+#define TX4927_PCFG_DMASEL2_DRQ2        0x00000000      /* SEL2=0 */
+#define TX4927_PCFG_DMASEL2_SIO0        0x00000010      /* SEL2=0 */
+#define TX4927_PCFG_DMASEL2_ACL1        0x00000000      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL2_ACL2        0x00000020      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL2_ACL0        0x00000030      /* SEL2=1 */
+#define TX4927_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4927_PCFG_DMASEL3_SIO0        0x00000040
+#define TX4927_PCFG_DMASEL3_ACL3        0x00000080
+#define TX4927_PCFG_DMASEL3_ACL1        0x000000c0
+
+/* CLKCTR : Clock Control */
+#define TX4927_CLKCTR_ACLCKD    0x02000000
+#define TX4927_CLKCTR_PIOCKD    0x01000000
+#define TX4927_CLKCTR_DMACKD    0x00800000
+#define TX4927_CLKCTR_PCICKD    0x00400000
+#define TX4927_CLKCTR_TM0CKD    0x00100000
+#define TX4927_CLKCTR_TM1CKD    0x00080000
+#define TX4927_CLKCTR_TM2CKD    0x00040000
+#define TX4927_CLKCTR_SIO0CKD   0x00020000
+#define TX4927_CLKCTR_SIO1CKD   0x00010000
+#define TX4927_CLKCTR_ACLRST    0x00000200
+#define TX4927_CLKCTR_PIORST    0x00000100
+#define TX4927_CLKCTR_DMARST    0x00000080
+#define TX4927_CLKCTR_PCIRST    0x00000040
+#define TX4927_CLKCTR_TM0RST    0x00000010
+#define TX4927_CLKCTR_TM1RST    0x00000008
+#define TX4927_CLKCTR_TM2RST    0x00000004
+#define TX4927_CLKCTR_SIO0RST   0x00000002
+#define TX4927_CLKCTR_SIO1RST   0x00000001
+
+#define tx4927_sdramcptr \
+                ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
+#define tx4927_pcicptr \
+                ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
+#define tx4927_ccfgptr \
+                ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
+#define tx4927_ebuscptr \
+                ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
+#define tx4927_pioptr           ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
+
+#define TX4927_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
+
+#define TX4927_SDRAMC_CR(ch)    __raw_readq(&tx4927_sdramcptr->cr[(ch)])
+#define TX4927_SDRAMC_BA(ch)    ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
+#define TX4927_SDRAMC_SIZE(ch)  \
+        ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
+
+#define TX4927_EBUSC_CR(ch)     __raw_readq(&tx4927_ebuscptr->cr[(ch)])
+#define TX4927_EBUSC_BA(ch)     ((TX4927_EBUSC_CR(ch) >> 48) << 20)
+#define TX4927_EBUSC_SIZE(ch)   \
+        (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
+#define TX4927_EBUSC_WIDTH(ch)  \
+        (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3))
+
+/* utilities */
+static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
+{
+#ifdef CONFIG_32BIT
+        unsigned long flags;
+        local_irq_save(flags);
+#endif
+        ____raw_writeq(____raw_readq(adr) & ~bits, adr);
+#ifdef CONFIG_32BIT
+        local_irq_restore(flags);
+#endif
+}
+static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
+{
+#ifdef CONFIG_32BIT
+        unsigned long flags;
+        local_irq_save(flags);
+#endif
+        ____raw_writeq(____raw_readq(adr) | bits, adr);
+#ifdef CONFIG_32BIT
+        local_irq_restore(flags);
+#endif
+}
+
+/* These functions are not interrupt safe. */
+static inline void tx4927_ccfg_clear(__u64 bits)
+{
+        ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
+                       & ~(TX4927_CCFG_W1CBITS | bits),
+                       &tx4927_ccfgptr->ccfg);
+}
+static inline void tx4927_ccfg_set(__u64 bits)
+{
+        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
+                        & ~TX4927_CCFG_W1CBITS) | bits,
+                       &tx4927_ccfgptr->ccfg);
+}
+static inline void tx4927_ccfg_change(__u64 change, __u64 new)
+{
+        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
+                        & ~(TX4927_CCFG_W1CBITS | change)) |
+                       new,
+                       &tx4927_ccfgptr->ccfg);
+}
+
+unsigned int tx4927_get_mem_size(void);
+void tx4927_wdt_init(void);
+void tx4927_setup(void);
+void tx4927_time_init(unsigned int tmrnr);
+void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
+int tx4927_report_pciclk(void);
+int tx4927_pciclk66_setup(void);
+void tx4927_setup_pcierr_irq(void);
+void tx4927_irq_init(void);
+void tx4927_mtd_init(int ch);
+
+#endif /* __ASM_TXX9_TX4927_H */
diff --git a/arch/mips/include/asm/txx9/tx4927pcic.h b/arch/mips/include/asm/txx9/tx4927pcic.h
new file mode 100644
index 000000000000..c470b8a5fe57
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4927pcic.h
@@ -0,0 +1,203 @@
+/*
+ * include/asm-mips/txx9/tx4927pcic.h
+ * TX4927 PCI controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9_TX4927PCIC_H
+#define __ASM_TXX9_TX4927PCIC_H
+
+#include <linux/pci.h>
+#include <linux/irqreturn.h>
+
+struct tx4927_pcic_reg {
+        u32 pciid;
+        u32 pcistatus;
+        u32 pciccrev;
+        u32 pcicfg1;
+        u32 p2gm0plbase;                /* +10 */
+        u32 p2gm0pubase;
+        u32 p2gm1plbase;
+        u32 p2gm1pubase;
+        u32 p2gm2pbase;         /* +20 */
+        u32 p2giopbase;
+        u32 unused0;
+        u32 pcisid;
+        u32 unused1;            /* +30 */
+        u32 pcicapptr;
+        u32 unused2;
+        u32 pcicfg2;
+        u32 g2ptocnt;           /* +40 */
+        u32 unused3[15];
+        u32 g2pstatus;          /* +80 */
+        u32 g2pmask;
+        u32 pcisstatus;
+        u32 pcimask;
+        u32 p2gcfg;             /* +90 */
+        u32 p2gstatus;
+        u32 p2gmask;
+        u32 p2gccmd;
+        u32 unused4[24];                /* +a0 */
+        u32 pbareqport;         /* +100 */
+        u32 pbacfg;
+        u32 pbastatus;
+        u32 pbamask;
+        u32 pbabm;              /* +110 */
+        u32 pbacreq;
+        u32 pbacgnt;
+        u32 pbacstate;
+        u64 g2pmgbase[3];               /* +120 */
+        u64 g2piogbase;
+        u32 g2pmmask[3];                /* +140 */
+        u32 g2piomask;
+        u64 g2pmpbase[3];               /* +150 */
+        u64 g2piopbase;
+        u32 pciccfg;            /* +170 */
+        u32 pcicstatus;
+        u32 pcicmask;
+        u32 unused5;
+        u64 p2gmgbase[3];               /* +180 */
+        u64 p2giogbase;
+        u32 g2pcfgadrs;         /* +1a0 */
+        u32 g2pcfgdata;
+        u32 unused6[8];
+        u32 g2pintack;
+        u32 g2pspc;
+        u32 unused7[12];                /* +1d0 */
+        u64 pdmca;              /* +200 */
+        u64 pdmga;
+        u64 pdmpa;
+        u64 pdmctr;
+        u64 pdmcfg;             /* +220 */
+        u64 pdmsts;
+};
+
+/* bits for PCICMD */
+/* see PCI_COMMAND_XXX in linux/pci_regs.h */
+
+/* bits for PCISTAT */
+/* see PCI_STATUS_XXX in linux/pci_regs.h */
+
+/* bits for IOBA/MBA */
+/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
+
+/* bits for G2PSTATUS/G2PMASK */
+#define TX4927_PCIC_G2PSTATUS_ALL       0x00000003
+#define TX4927_PCIC_G2PSTATUS_TTOE      0x00000002
+#define TX4927_PCIC_G2PSTATUS_RTOE      0x00000001
+
+/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
+#define TX4927_PCIC_PCISTATUS_ALL       0x0000f900
+
+/* bits for PBACFG */
+#define TX4927_PCIC_PBACFG_FIXPA        0x00000008
+#define TX4927_PCIC_PBACFG_RPBA 0x00000004
+#define TX4927_PCIC_PBACFG_PBAEN        0x00000002
+#define TX4927_PCIC_PBACFG_BMCEN        0x00000001
+
+/* bits for PBASTATUS/PBAMASK */
+#define TX4927_PCIC_PBASTATUS_ALL       0x00000001
+#define TX4927_PCIC_PBASTATUS_BM        0x00000001
+
+/* bits for G2PMnGBASE */
+#define TX4927_PCIC_G2PMnGBASE_BSDIS    0x0000002000000000ULL
+#define TX4927_PCIC_G2PMnGBASE_ECHG     0x0000001000000000ULL
+
+/* bits for G2PIOGBASE */
+#define TX4927_PCIC_G2PIOGBASE_BSDIS    0x0000002000000000ULL
+#define TX4927_PCIC_G2PIOGBASE_ECHG     0x0000001000000000ULL
+
+/* bits for PCICSTATUS/PCICMASK */
+#define TX4927_PCIC_PCICSTATUS_ALL      0x000007b8
+#define TX4927_PCIC_PCICSTATUS_PME      0x00000400
+#define TX4927_PCIC_PCICSTATUS_TLB      0x00000200
+#define TX4927_PCIC_PCICSTATUS_NIB      0x00000100
+#define TX4927_PCIC_PCICSTATUS_ZIB      0x00000080
+#define TX4927_PCIC_PCICSTATUS_PERR     0x00000020
+#define TX4927_PCIC_PCICSTATUS_SERR     0x00000010
+#define TX4927_PCIC_PCICSTATUS_GBE      0x00000008
+#define TX4927_PCIC_PCICSTATUS_IWB      0x00000002
+#define TX4927_PCIC_PCICSTATUS_E2PDONE  0x00000001
+
+/* bits for PCICCFG */
+#define TX4927_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
+#define TX4927_PCIC_PCICCFG_HRST        0x00000800
+#define TX4927_PCIC_PCICCFG_SRST        0x00000400
+#define TX4927_PCIC_PCICCFG_IRBER       0x00000200
+#define TX4927_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
+#define TX4927_PCIC_PCICCFG_G2PM0EN     0x00000100
+#define TX4927_PCIC_PCICCFG_G2PM1EN     0x00000080
+#define TX4927_PCIC_PCICCFG_G2PM2EN     0x00000040
+#define TX4927_PCIC_PCICCFG_G2PIOEN     0x00000020
+#define TX4927_PCIC_PCICCFG_TCAR        0x00000010
+#define TX4927_PCIC_PCICCFG_ICAEN       0x00000008
+
+/* bits for P2GMnGBASE */
+#define TX4927_PCIC_P2GMnGBASE_TMEMEN   0x0000004000000000ULL
+#define TX4927_PCIC_P2GMnGBASE_TBSDIS   0x0000002000000000ULL
+#define TX4927_PCIC_P2GMnGBASE_TECHG    0x0000001000000000ULL
+
+/* bits for P2GIOGBASE */
+#define TX4927_PCIC_P2GIOGBASE_TIOEN    0x0000004000000000ULL
+#define TX4927_PCIC_P2GIOGBASE_TBSDIS   0x0000002000000000ULL
+#define TX4927_PCIC_P2GIOGBASE_TECHG    0x0000001000000000ULL
+
+#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
+#define TX4927_PCIC_MAX_DEVNU   TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
+
+/* bits for PDMCFG */
+#define TX4927_PCIC_PDMCFG_RSTFIFO      0x00200000
+#define TX4927_PCIC_PDMCFG_EXFER        0x00100000
+#define TX4927_PCIC_PDMCFG_REQDLY_MASK  0x00003800
+#define TX4927_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_16    (1 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_32    (2 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_64    (3 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_128   (4 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_256   (5 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_512   (6 << 11)
+#define TX4927_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
+#define TX4927_PCIC_PDMCFG_ERRIE        0x00000400
+#define TX4927_PCIC_PDMCFG_NCCMPIE      0x00000200
+#define TX4927_PCIC_PDMCFG_NTCMPIE      0x00000100
+#define TX4927_PCIC_PDMCFG_CHNEN        0x00000080
+#define TX4927_PCIC_PDMCFG_XFRACT       0x00000040
+#define TX4927_PCIC_PDMCFG_BSWAP        0x00000020
+#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
+#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
+#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
+#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
+#define TX4927_PCIC_PDMCFG_XFRDIRC      0x00000002
+#define TX4927_PCIC_PDMCFG_CHRST        0x00000001
+
+/* bits for PDMSTS */
+#define TX4927_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
+#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
+#define TX4927_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
+#define TX4927_PCIC_PDMSTS_FIFORP_MASK  0x00030000
+#define TX4927_PCIC_PDMSTS_ERRINT       0x00000800
+#define TX4927_PCIC_PDMSTS_DONEINT      0x00000400
+#define TX4927_PCIC_PDMSTS_CHNEN        0x00000200
+#define TX4927_PCIC_PDMSTS_XFRACT       0x00000100
+#define TX4927_PCIC_PDMSTS_ACCMP        0x00000080
+#define TX4927_PCIC_PDMSTS_NCCMP        0x00000040
+#define TX4927_PCIC_PDMSTS_NTCMP        0x00000020
+#define TX4927_PCIC_PDMSTS_CFGERR       0x00000008
+#define TX4927_PCIC_PDMSTS_PCIERR       0x00000004
+#define TX4927_PCIC_PDMSTS_CHNERR       0x00000002
+#define TX4927_PCIC_PDMSTS_DATAERR      0x00000001
+#define TX4927_PCIC_PDMSTS_ALL_CMP      0x000000e0
+#define TX4927_PCIC_PDMSTS_ALL_ERR      0x0000000f
+
+struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
+        struct pci_controller *channel);
+void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
+                       struct pci_controller *channel, int extarb);
+void tx4927_report_pcic_status(void);
+char *tx4927_pcibios_setup(char *str);
+void tx4927_dump_pcic_settings(void);
+irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id);
+
+#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
new file mode 100644
index 000000000000..989e7751135a
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -0,0 +1,295 @@
+/*
+ * Definitions for TX4937/TX4938
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
+ */
+#ifndef __ASM_TXX9_TX4938_H
+#define __ASM_TXX9_TX4938_H
+
+/* some controllers are compatible with 4927 */
+#include <asm/txx9/tx4927.h>
+
+#ifdef CONFIG_64BIT
+#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
+#else
+#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
+#endif
+#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
+
+/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
+#define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
+#define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
+#define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
+#define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
+#define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
+#define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
+#define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
+#define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
+#define TX4938_NR_TMR   3
+#define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
+#define TX4938_NR_SIO   2
+#define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
+#define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
+#define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
+#define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
+#define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
+
+struct tx4938_sramc_reg {
+        u64 cr;
+};
+
+struct tx4938_ccfg_reg {
+        u64 ccfg;
+        u64 crir;
+        u64 pcfg;
+        u64 toea;
+        u64 clkctr;
+        u64 unused0;
+        u64 garbc;
+        u64 unused1;
+        u64 unused2;
+        u64 ramp;
+        u64 unused3;
+        u64 jmpadr;
+};
+
+/*
+ * IRC
+ */
+
+#define TX4938_IR_ECCERR        0
+#define TX4938_IR_WTOERR        1
+#define TX4938_NUM_IR_INT       6
+#define TX4938_IR_INT(n)        (2 + (n))
+#define TX4938_NUM_IR_SIO       2
+#define TX4938_IR_SIO(n)        (8 + (n))
+#define TX4938_NUM_IR_DMA       4
+#define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
+#define TX4938_IR_PIO   14
+#define TX4938_IR_PDMAC 15
+#define TX4938_IR_PCIC  16
+#define TX4938_NUM_IR_TMR       3
+#define TX4938_IR_TMR(n)        (17 + (n))
+#define TX4938_IR_NDFMC 21
+#define TX4938_IR_PCIERR        22
+#define TX4938_IR_PCIPME        23
+#define TX4938_IR_ACLC  24
+#define TX4938_IR_ACLCPME       25
+#define TX4938_IR_PCIC1 26
+#define TX4938_IR_SPI   31
+#define TX4938_NUM_IR   32
+/* multiplex */
+#define TX4938_IR_ETH0  TX4938_IR_INT(4)
+#define TX4938_IR_ETH1  TX4938_IR_INT(3)
+
+#define TX4938_IRC_INT  2       /* IP[2] in Status register */
+
+#define TX4938_NUM_PIO  16
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4938_CCFG_WDRST       0x0000020000000000ULL
+#define TX4938_CCFG_WDREXEN     0x0000010000000000ULL
+#define TX4938_CCFG_BCFG_MASK   0x000000ff00000000ULL
+#define TX4938_CCFG_TINTDIS     0x01000000
+#define TX4938_CCFG_PCI66       0x00800000
+#define TX4938_CCFG_PCIMODE     0x00400000
+#define TX4938_CCFG_PCI1_66     0x00200000
+#define TX4938_CCFG_DIVMODE_MASK        0x001e0000
+#define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
+#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
+#define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
+#define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
+#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
+#define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
+#define TX4938_CCFG_DIVMODE_10  (0xb << 17)
+#define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
+#define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
+#define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
+#define TX4938_CCFG_BEOW        0x00010000
+#define TX4938_CCFG_WR  0x00008000
+#define TX4938_CCFG_TOE 0x00004000
+#define TX4938_CCFG_PCIARB      0x00002000
+#define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
+#define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
+#define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
+#define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
+#define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
+#define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
+#define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
+#define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
+#define TX4938_CCFG_PCI1DMD     0x00000100
+#define TX4938_CCFG_SYSSP_MASK  0x000000c0
+#define TX4938_CCFG_ENDIAN      0x00000004
+#define TX4938_CCFG_HALT        0x00000002
+#define TX4938_CCFG_ACEHOLD     0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX4938_PCFG_ETH0_SEL    0x8000000000000000ULL
+#define TX4938_PCFG_ETH1_SEL    0x4000000000000000ULL
+#define TX4938_PCFG_ATA_SEL     0x2000000000000000ULL
+#define TX4938_PCFG_ISA_SEL     0x1000000000000000ULL
+#define TX4938_PCFG_SPI_SEL     0x0800000000000000ULL
+#define TX4938_PCFG_NDF_SEL     0x0400000000000000ULL
+#define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
+#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
+#define TX4938_PCFG_SYSCLKEN    0x08000000
+#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
+#define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
+#define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4938_PCFG_SEL2        0x00000200
+#define TX4938_PCFG_SEL1        0x00000100
+#define TX4938_PCFG_DMASEL_ALL  0x0000000f
+#define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
+#define TX4938_PCFG_DMASEL0_SIO1        0x00000001
+#define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4938_PCFG_DMASEL1_SIO1        0x00000002
+#define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
+#define TX4938_PCFG_DMASEL2_SIO0        0x00000004
+#define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
+#define TX4938_PCFG_DMASEL3_SIO0        0x00000008
+
+/* CLKCTR : Clock Control */
+#define TX4938_CLKCTR_NDFCKD    0x0001000000000000ULL
+#define TX4938_CLKCTR_NDFRST    0x0000000100000000ULL
+#define TX4938_CLKCTR_ETH1CKD   0x80000000
+#define TX4938_CLKCTR_ETH0CKD   0x40000000
+#define TX4938_CLKCTR_SPICKD    0x20000000
+#define TX4938_CLKCTR_SRAMCKD   0x10000000
+#define TX4938_CLKCTR_PCIC1CKD  0x08000000
+#define TX4938_CLKCTR_DMA1CKD   0x04000000
+#define TX4938_CLKCTR_ACLCKD    0x02000000
+#define TX4938_CLKCTR_PIOCKD    0x01000000
+#define TX4938_CLKCTR_DMACKD    0x00800000
+#define TX4938_CLKCTR_PCICKD    0x00400000
+#define TX4938_CLKCTR_TM0CKD    0x00100000
+#define TX4938_CLKCTR_TM1CKD    0x00080000
+#define TX4938_CLKCTR_TM2CKD    0x00040000
+#define TX4938_CLKCTR_SIO0CKD   0x00020000
+#define TX4938_CLKCTR_SIO1CKD   0x00010000
+#define TX4938_CLKCTR_ETH1RST   0x00008000
+#define TX4938_CLKCTR_ETH0RST   0x00004000
+#define TX4938_CLKCTR_SPIRST    0x00002000
+#define TX4938_CLKCTR_SRAMRST   0x00001000
+#define TX4938_CLKCTR_PCIC1RST  0x00000800
+#define TX4938_CLKCTR_DMA1RST   0x00000400
+#define TX4938_CLKCTR_ACLRST    0x00000200
+#define TX4938_CLKCTR_PIORST    0x00000100
+#define TX4938_CLKCTR_DMARST    0x00000080
+#define TX4938_CLKCTR_PCIRST    0x00000040
+#define TX4938_CLKCTR_TM0RST    0x00000010
+#define TX4938_CLKCTR_TM1RST    0x00000008
+#define TX4938_CLKCTR_TM2RST    0x00000004
+#define TX4938_CLKCTR_SIO0RST   0x00000002
+#define TX4938_CLKCTR_SIO1RST   0x00000001
+
+/*
+ * DMA
+ */
+/* bits for MCR */
+#define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
+#define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
+#define TX4938_DMA_MCR_RSFIF    0x00000080
+#define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
+#define TX4938_DMA_MCR_RPRT     0x00000002
+#define TX4938_DMA_MCR_MSTEN    0x00000001
+
+/* bits for CCRn */
+#define TX4938_DMA_CCR_IMMCHN   0x20000000
+#define TX4938_DMA_CCR_USEXFSZ  0x10000000
+#define TX4938_DMA_CCR_LE       0x08000000
+#define TX4938_DMA_CCR_DBINH    0x04000000
+#define TX4938_DMA_CCR_SBINH    0x02000000
+#define TX4938_DMA_CCR_CHRST    0x01000000
+#define TX4938_DMA_CCR_RVBYTE   0x00800000
+#define TX4938_DMA_CCR_ACKPOL   0x00400000
+#define TX4938_DMA_CCR_REQPL    0x00200000
+#define TX4938_DMA_CCR_EGREQ    0x00100000
+#define TX4938_DMA_CCR_CHDN     0x00080000
+#define TX4938_DMA_CCR_DNCTL    0x00060000
+#define TX4938_DMA_CCR_EXTRQ    0x00010000
+#define TX4938_DMA_CCR_INTRQD   0x0000e000
+#define TX4938_DMA_CCR_INTENE   0x00001000
+#define TX4938_DMA_CCR_INTENC   0x00000800
+#define TX4938_DMA_CCR_INTENT   0x00000400
+#define TX4938_DMA_CCR_CHNEN    0x00000200
+#define TX4938_DMA_CCR_XFACT    0x00000100
+#define TX4938_DMA_CCR_SMPCHN   0x00000020
+#define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
+#define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
+#define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
+#define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
+#define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
+#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
+#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
+#define TX4938_DMA_CCR_MEMIO    0x00000002
+#define TX4938_DMA_CCR_SNGAD    0x00000001
+
+/* bits for CSRn */
+#define TX4938_DMA_CSR_CHNEN    0x00000400
+#define TX4938_DMA_CSR_STLXFER  0x00000200
+#define TX4938_DMA_CSR_CHNACT   0x00000100
+#define TX4938_DMA_CSR_ABCHC    0x00000080
+#define TX4938_DMA_CSR_NCHNC    0x00000040
+#define TX4938_DMA_CSR_NTRNFC   0x00000020
+#define TX4938_DMA_CSR_EXTDN    0x00000010
+#define TX4938_DMA_CSR_CFERR    0x00000008
+#define TX4938_DMA_CSR_CHERR    0x00000004
+#define TX4938_DMA_CSR_DESERR   0x00000002
+#define TX4938_DMA_CSR_SORERR   0x00000001
+
+#define tx4938_sdramcptr        tx4927_sdramcptr
+#define tx4938_ebuscptr         tx4927_ebuscptr
+#define tx4938_pcicptr          tx4927_pcicptr
+#define tx4938_pcic1ptr \
+                ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
+#define tx4938_ccfgptr \
+                ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
+#define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
+#define tx4938_sramcptr \
+                ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
+
+
+#define TX4938_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
+
+#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
+#define tx4938_ccfg_set(bits)   tx4927_ccfg_set(bits)
+#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
+
+#define TX4938_SDRAMC_CR(ch)    TX4927_SDRAMC_CR(ch)
+#define TX4938_SDRAMC_BA(ch)    TX4927_SDRAMC_BA(ch)
+#define TX4938_SDRAMC_SIZE(ch)  TX4927_SDRAMC_SIZE(ch)
+
+#define TX4938_EBUSC_CR(ch)     TX4927_EBUSC_CR(ch)
+#define TX4938_EBUSC_BA(ch)     TX4927_EBUSC_BA(ch)
+#define TX4938_EBUSC_SIZE(ch)   TX4927_EBUSC_SIZE(ch)
+#define TX4938_EBUSC_WIDTH(ch)  TX4927_EBUSC_WIDTH(ch)
+
+#define tx4938_get_mem_size() tx4927_get_mem_size()
+void tx4938_wdt_init(void);
+void tx4938_setup(void);
+void tx4938_time_init(unsigned int tmrnr);
+void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
+void tx4938_spi_init(int busid);
+void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
+int tx4938_report_pciclk(void);
+void tx4938_report_pci1clk(void);
+int tx4938_pciclk66_setup(void);
+struct pci_dev;
+int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
+void tx4938_setup_pcierr_irq(void);
+void tx4938_irq_init(void);
+void tx4938_mtd_init(int ch);
+
+#endif
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
new file mode 100644
index 000000000000..88badb423010
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -0,0 +1,545 @@
+/*
+ * Definitions for TX4939
+ *
+ * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_TXX9_TX4939_H
+#define __ASM_TXX9_TX4939_H
+
+/* some controllers are compatible with 4927/4938 */
+#include <asm/txx9/tx4938.h>
+
+#ifdef CONFIG_64BIT
+#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
+#else
+#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
+#endif
+#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
+
+#define TX4939_ATA_REG(ch)      (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
+#define TX4939_NDFMC_REG        (TX4939_REG_BASE + 0x5000)
+#define TX4939_SRAMC_REG        (TX4939_REG_BASE + 0x6000)
+#define TX4939_CRYPTO_REG       (TX4939_REG_BASE + 0x6800)
+#define TX4939_PCIC1_REG        (TX4939_REG_BASE + 0x7000)
+#define TX4939_DDRC_REG         (TX4939_REG_BASE + 0x8000)
+#define TX4939_EBUSC_REG        (TX4939_REG_BASE + 0x9000)
+#define TX4939_VPC_REG          (TX4939_REG_BASE + 0xa000)
+#define TX4939_DMA_REG(ch)      (TX4939_REG_BASE + 0xb000 + (ch) * 0x800)
+#define TX4939_PCIC_REG         (TX4939_REG_BASE + 0xd000)
+#define TX4939_CCFG_REG         (TX4939_REG_BASE + 0xe000)
+#define TX4939_IRC_REG          (TX4939_REG_BASE + 0xe800)
+#define TX4939_NR_TMR   6       /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */
+#define TX4939_TMR_REG(ch)      \
+        (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100)
+#define TX4939_NR_SIO   4       /* 0xf300, 0xf400, 0xf380, 0xf480 */
+#define TX4939_SIO_REG(ch)      \
+        (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6))
+#define TX4939_ACLC_REG         (TX4939_REG_BASE + 0xf700)
+#define TX4939_SPI_REG          (TX4939_REG_BASE + 0xf800)
+#define TX4939_I2C_REG          (TX4939_REG_BASE + 0xf900)
+#define TX4939_I2S_REG          (TX4939_REG_BASE + 0xfa00)
+#define TX4939_RTC_REG          (TX4939_REG_BASE + 0xfb00)
+#define TX4939_CIR_REG          (TX4939_REG_BASE + 0xfc00)
+
+struct tx4939_le_reg {
+        __u32 r;
+        __u32 unused;
+};
+
+struct tx4939_ddrc_reg {
+        struct tx4939_le_reg ctl[47];
+        __u64 unused0[17];
+        __u64 winen;
+        __u64 win[4];
+};
+
+struct tx4939_ccfg_reg {
+        __u64 ccfg;
+        __u64 crir;
+        __u64 pcfg;
+        __u64 toea;
+        __u64 clkctr;
+        __u64 unused0;
+        __u64 garbc;
+        __u64 unused1[2];
+        __u64 ramp;
+        __u64 unused2[2];
+        __u64 dskwctrl;
+        __u64 mclkosc;
+        __u64 mclkctl;
+        __u64 unused3[17];
+        struct {
+                __u64 mr;
+                __u64 dr;
+        } gpio[2];
+};
+
+struct tx4939_irc_reg {
+        struct tx4939_le_reg den;
+        struct tx4939_le_reg scipb;
+        struct tx4939_le_reg dm[2];
+        struct tx4939_le_reg lvl[16];
+        struct tx4939_le_reg msk;
+        struct tx4939_le_reg edc;
+        struct tx4939_le_reg pnd0;
+        struct tx4939_le_reg cs;
+        struct tx4939_le_reg pnd1;
+        struct tx4939_le_reg dm2[2];
+        struct tx4939_le_reg dbr[2];
+        struct tx4939_le_reg dben;
+        struct tx4939_le_reg unused0[2];
+        struct tx4939_le_reg flag[2];
+        struct tx4939_le_reg pol;
+        struct tx4939_le_reg cnt;
+        struct tx4939_le_reg maskint;
+        struct tx4939_le_reg maskext;
+};
+
+struct tx4939_rtc_reg {
+        __u32 ctl;
+        __u32 adr;
+        __u32 dat;
+        __u32 tbc;
+};
+
+struct tx4939_crypto_reg {
+        struct tx4939_le_reg csr;
+        struct tx4939_le_reg idesptr;
+        struct tx4939_le_reg cdesptr;
+        struct tx4939_le_reg buserr;
+        struct tx4939_le_reg cip_tout;
+        struct tx4939_le_reg cir;
+        union {
+                struct {
+                        struct tx4939_le_reg data[8];
+                        struct tx4939_le_reg ctrl;
+                } gen;
+                struct {
+                        struct {
+                                struct tx4939_le_reg l;
+                                struct tx4939_le_reg u;
+                        } key[3], ini;
+                        struct tx4939_le_reg ctrl;
+                } des;
+                struct {
+                        struct tx4939_le_reg key[4];
+                        struct tx4939_le_reg ini[4];
+                        struct tx4939_le_reg ctrl;
+                } aes;
+                struct {
+                        struct {
+                                struct tx4939_le_reg l;
+                                struct tx4939_le_reg u;
+                        } cnt;
+                        struct tx4939_le_reg ini[5];
+                        struct tx4939_le_reg unused;
+                        struct tx4939_le_reg ctrl;
+                } hash;
+        } cdr;
+        struct tx4939_le_reg unused0[7];
+        struct tx4939_le_reg rcsr;
+        struct tx4939_le_reg rpr;
+        __u64 rdr;
+        __u64 ror[3];
+        struct tx4939_le_reg unused1[2];
+        struct tx4939_le_reg xorslr;
+        struct tx4939_le_reg xorsur;
+};
+
+struct tx4939_crypto_desc {
+        __u32 src;
+        __u32 dst;
+        __u32 next;
+        __u32 ctrl;
+        __u32 index;
+        __u32 xor;
+};
+
+struct tx4939_vpc_reg {
+        struct tx4939_le_reg csr;
+        struct {
+                struct tx4939_le_reg ctrlA;
+                struct tx4939_le_reg ctrlB;
+                struct tx4939_le_reg idesptr;
+                struct tx4939_le_reg cdesptr;
+        } port[3];
+        struct tx4939_le_reg buserr;
+};
+
+struct tx4939_vpc_desc {
+        __u32 src;
+        __u32 next;
+        __u32 ctrl1;
+        __u32 ctrl2;
+};
+
+/*
+ * IRC
+ */
+#define TX4939_IR_NONE  0
+#define TX4939_IR_DDR   1
+#define TX4939_IR_WTOERR        2
+#define TX4939_NUM_IR_INT       3
+#define TX4939_IR_INT(n)        (3 + (n))
+#define TX4939_NUM_IR_ETH       2
+#define TX4939_IR_ETH(n)        ((n) ? 43 : 6)
+#define TX4939_IR_VIDEO 7
+#define TX4939_IR_CIR   8
+#define TX4939_NUM_IR_SIO       4
+#define TX4939_IR_SIO(n)        ((n) ? 43 + (n) : 9)    /* 9,44-46 */
+#define TX4939_NUM_IR_DMA       4
+#define TX4939_IR_DMA(ch, n)    (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
+#define TX4939_IR_IRC   14
+#define TX4939_IR_PDMAC 15
+#define TX4939_NUM_IR_TMR       6
+#define TX4939_IR_TMR(n)        (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
+#define TX4939_NUM_IR_ATA       2
+#define TX4939_IR_ATA(n)        (19 + (n))
+#define TX4939_IR_ACLC  21
+#define TX4939_IR_CIPHER        26
+#define TX4939_IR_INTA  27
+#define TX4939_IR_INTB  28
+#define TX4939_IR_INTC  29
+#define TX4939_IR_INTD  30
+#define TX4939_IR_I2C   33
+#define TX4939_IR_SPI   34
+#define TX4939_IR_PCIC  35
+#define TX4939_IR_PCIC1 36
+#define TX4939_IR_PCIERR        37
+#define TX4939_IR_PCIPME        38
+#define TX4939_IR_NDFMC 39
+#define TX4939_IR_ACLCPME       40
+#define TX4939_IR_RTC   41
+#define TX4939_IR_RND   42
+#define TX4939_IR_I2S   47
+#define TX4939_NUM_IR   64
+
+#define TX4939_IRC_INT  2       /* IP[2] in Status register */
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4939_CCFG_PCIBOOT     0x0000040000000000ULL
+#define TX4939_CCFG_WDRST       0x0000020000000000ULL
+#define TX4939_CCFG_WDREXEN     0x0000010000000000ULL
+#define TX4939_CCFG_BCFG_MASK   0x000000ff00000000ULL
+#define TX4939_CCFG_GTOT_MASK   0x06000000
+#define TX4939_CCFG_GTOT_4096   0x06000000
+#define TX4939_CCFG_GTOT_2048   0x04000000
+#define TX4939_CCFG_GTOT_1024   0x02000000
+#define TX4939_CCFG_GTOT_512    0x00000000
+#define TX4939_CCFG_TINTDIS     0x01000000
+#define TX4939_CCFG_PCI66       0x00800000
+#define TX4939_CCFG_PCIMODE     0x00400000
+#define TX4939_CCFG_SSCG        0x00100000
+#define TX4939_CCFG_MULCLK_MASK 0x000e0000
+#define TX4939_CCFG_MULCLK_8    (0x7 << 17)
+#define TX4939_CCFG_MULCLK_9    (0x0 << 17)
+#define TX4939_CCFG_MULCLK_10   (0x1 << 17)
+#define TX4939_CCFG_MULCLK_11   (0x2 << 17)
+#define TX4939_CCFG_MULCLK_12   (0x3 << 17)
+#define TX4939_CCFG_MULCLK_13   (0x4 << 17)
+#define TX4939_CCFG_MULCLK_14   (0x5 << 17)
+#define TX4939_CCFG_MULCLK_15   (0x6 << 17)
+#define TX4939_CCFG_BEOW        0x00010000
+#define TX4939_CCFG_WR  0x00008000
+#define TX4939_CCFG_TOE 0x00004000
+#define TX4939_CCFG_PCIARB      0x00002000
+#define TX4939_CCFG_YDIVMODE_MASK       0x00001c00
+#define TX4939_CCFG_YDIVMODE_2  (0x0 << 10)
+#define TX4939_CCFG_YDIVMODE_3  (0x1 << 10)
+#define TX4939_CCFG_YDIVMODE_5  (0x6 << 10)
+#define TX4939_CCFG_YDIVMODE_6  (0x7 << 10)
+#define TX4939_CCFG_PTSEL       0x00000200
+#define TX4939_CCFG_BESEL       0x00000100
+#define TX4939_CCFG_SYSSP_MASK  0x000000c0
+#define TX4939_CCFG_ACKSEL      0x00000020
+#define TX4939_CCFG_ROMW        0x00000010
+#define TX4939_CCFG_ENDIAN      0x00000004
+#define TX4939_CCFG_ARMODE      0x00000002
+#define TX4939_CCFG_ACEHOLD     0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX4939_PCFG_SIO2MODE_MASK       0xc000000000000000ULL
+#define TX4939_PCFG_SIO2MODE_GPIO       0x8000000000000000ULL
+#define TX4939_PCFG_SIO2MODE_SIO2       0x4000000000000000ULL
+#define TX4939_PCFG_SIO2MODE_SIO0       0x0000000000000000ULL
+#define TX4939_PCFG_SPIMODE     0x2000000000000000ULL
+#define TX4939_PCFG_I2CMODE     0x1000000000000000ULL
+#define TX4939_PCFG_I2SMODE_MASK        0x0c00000000000000ULL
+#define TX4939_PCFG_I2SMODE_GPIO        0x0c00000000000000ULL
+#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
+#define TX4939_PCFG_I2SMODE_I2S_ALT     0x0400000000000000ULL
+#define TX4939_PCFG_I2SMODE_ACLC        0x0000000000000000ULL
+#define TX4939_PCFG_SIO3MODE    0x0200000000000000ULL
+#define TX4939_PCFG_DMASEL3     0x0004000000000000ULL
+#define TX4939_PCFG_DMASEL3_SIO0        0x0004000000000000ULL
+#define TX4939_PCFG_DMASEL3_NDFC        0x0000000000000000ULL
+#define TX4939_PCFG_VSSMODE     0x0000200000000000ULL
+#define TX4939_PCFG_VPSMODE     0x0000100000000000ULL
+#define TX4939_PCFG_ET1MODE     0x0000080000000000ULL
+#define TX4939_PCFG_ET0MODE     0x0000040000000000ULL
+#define TX4939_PCFG_ATA1MODE    0x0000020000000000ULL
+#define TX4939_PCFG_ATA0MODE    0x0000010000000000ULL
+#define TX4939_PCFG_BP_PLL      0x0000000100000000ULL
+
+#define TX4939_PCFG_SYSCLKEN    0x08000000
+#define TX4939_PCFG_PCICLKEN_ALL        0x000f0000
+#define TX4939_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
+#define TX4939_PCFG_SPEED1      0x00002000
+#define TX4939_PCFG_SPEED0      0x00001000
+#define TX4939_PCFG_ITMODE      0x00000300
+#define TX4939_PCFG_DMASEL_ALL  (0x00000007 | TX4939_PCFG_DMASEL3)
+#define TX4939_PCFG_DMASEL2     0x00000004
+#define TX4939_PCFG_DMASEL2_DRQ2        0x00000000
+#define TX4939_PCFG_DMASEL2_SIO0        0x00000004
+#define TX4939_PCFG_DMASEL1     0x00000002
+#define TX4939_PCFG_DMASEL1_DRQ1        0x00000000
+#define TX4939_PCFG_DMASEL0     0x00000001
+#define TX4939_PCFG_DMASEL0_DRQ0        0x00000000
+
+/* CLKCTR : Clock Control */
+#define TX4939_CLKCTR_IOSCKD    0x8000000000000000ULL
+#define TX4939_CLKCTR_SYSCKD    0x4000000000000000ULL
+#define TX4939_CLKCTR_TM5CKD    0x2000000000000000ULL
+#define TX4939_CLKCTR_TM4CKD    0x1000000000000000ULL
+#define TX4939_CLKCTR_TM3CKD    0x0800000000000000ULL
+#define TX4939_CLKCTR_CIRCKD    0x0400000000000000ULL
+#define TX4939_CLKCTR_SIO3CKD   0x0200000000000000ULL
+#define TX4939_CLKCTR_SIO2CKD   0x0100000000000000ULL
+#define TX4939_CLKCTR_SIO1CKD   0x0080000000000000ULL
+#define TX4939_CLKCTR_VPCCKD    0x0040000000000000ULL
+#define TX4939_CLKCTR_EPCICKD   0x0020000000000000ULL
+#define TX4939_CLKCTR_ETH1CKD   0x0008000000000000ULL
+#define TX4939_CLKCTR_ATA1CKD   0x0004000000000000ULL
+#define TX4939_CLKCTR_BROMCKD   0x0002000000000000ULL
+#define TX4939_CLKCTR_NDCCKD    0x0001000000000000ULL
+#define TX4939_CLKCTR_I2CCKD    0x0000800000000000ULL
+#define TX4939_CLKCTR_ETH0CKD   0x0000400000000000ULL
+#define TX4939_CLKCTR_SPICKD    0x0000200000000000ULL
+#define TX4939_CLKCTR_SRAMCKD   0x0000100000000000ULL
+#define TX4939_CLKCTR_PCI1CKD   0x0000080000000000ULL
+#define TX4939_CLKCTR_DMA1CKD   0x0000040000000000ULL
+#define TX4939_CLKCTR_ACLCKD    0x0000020000000000ULL
+#define TX4939_CLKCTR_ATA0CKD   0x0000010000000000ULL
+#define TX4939_CLKCTR_DMA0CKD   0x0000008000000000ULL
+#define TX4939_CLKCTR_PCICCKD   0x0000004000000000ULL
+#define TX4939_CLKCTR_I2SCKD    0x0000002000000000ULL
+#define TX4939_CLKCTR_TM0CKD    0x0000001000000000ULL
+#define TX4939_CLKCTR_TM1CKD    0x0000000800000000ULL
+#define TX4939_CLKCTR_TM2CKD    0x0000000400000000ULL
+#define TX4939_CLKCTR_SIO0CKD   0x0000000200000000ULL
+#define TX4939_CLKCTR_CYPCKD    0x0000000100000000ULL
+#define TX4939_CLKCTR_IOSRST    0x80000000
+#define TX4939_CLKCTR_SYSRST    0x40000000
+#define TX4939_CLKCTR_TM5RST    0x20000000
+#define TX4939_CLKCTR_TM4RST    0x10000000
+#define TX4939_CLKCTR_TM3RST    0x08000000
+#define TX4939_CLKCTR_CIRRST    0x04000000
+#define TX4939_CLKCTR_SIO3RST   0x02000000
+#define TX4939_CLKCTR_SIO2RST   0x01000000
+#define TX4939_CLKCTR_SIO1RST   0x00800000
+#define TX4939_CLKCTR_VPCRST    0x00400000
+#define TX4939_CLKCTR_EPCIRST   0x00200000
+#define TX4939_CLKCTR_ETH1RST   0x00080000
+#define TX4939_CLKCTR_ATA1RST   0x00040000
+#define TX4939_CLKCTR_BROMRST   0x00020000
+#define TX4939_CLKCTR_NDCRST    0x00010000
+#define TX4939_CLKCTR_I2CRST    0x00008000
+#define TX4939_CLKCTR_ETH0RST   0x00004000
+#define TX4939_CLKCTR_SPIRST    0x00002000
+#define TX4939_CLKCTR_SRAMRST   0x00001000
+#define TX4939_CLKCTR_PCI1RST   0x00000800
+#define TX4939_CLKCTR_DMA1RST   0x00000400
+#define TX4939_CLKCTR_ACLRST    0x00000200
+#define TX4939_CLKCTR_ATA0RST   0x00000100
+#define TX4939_CLKCTR_DMA0RST   0x00000080
+#define TX4939_CLKCTR_PCICRST   0x00000040
+#define TX4939_CLKCTR_I2SRST    0x00000020
+#define TX4939_CLKCTR_TM0RST    0x00000010
+#define TX4939_CLKCTR_TM1RST    0x00000008
+#define TX4939_CLKCTR_TM2RST    0x00000004
+#define TX4939_CLKCTR_SIO0RST   0x00000002
+#define TX4939_CLKCTR_CYPRST    0x00000001
+
+/*
+ * RTC
+ */
+#define TX4939_RTCCTL_ALME      0x00000080
+#define TX4939_RTCCTL_ALMD      0x00000040
+#define TX4939_RTCCTL_BUSY      0x00000020
+
+#define TX4939_RTCCTL_COMMAND   0x00000007
+#define TX4939_RTCCTL_COMMAND_NOP       0x00000000
+#define TX4939_RTCCTL_COMMAND_GETTIME   0x00000001
+#define TX4939_RTCCTL_COMMAND_SETTIME   0x00000002
+#define TX4939_RTCCTL_COMMAND_GETALARM  0x00000003
+#define TX4939_RTCCTL_COMMAND_SETALARM  0x00000004
+
+#define TX4939_RTCTBC_PM        0x00000080
+#define TX4939_RTCTBC_COMP      0x0000007f
+
+#define TX4939_RTC_REG_RAMSIZE  0x00000100
+#define TX4939_RTC_REG_RWBSIZE  0x00000006
+
+/*
+ * CRYPTO
+ */
+#define TX4939_CRYPTO_CSR_SAESO 0x08000000
+#define TX4939_CRYPTO_CSR_SAESI 0x04000000
+#define TX4939_CRYPTO_CSR_SDESO 0x02000000
+#define TX4939_CRYPTO_CSR_SDESI 0x01000000
+#define TX4939_CRYPTO_CSR_INDXBST_MASK  0x00700000
+#define TX4939_CRYPTO_CSR_INDXBST(n)    ((n) << 20)
+#define TX4939_CRYPTO_CSR_TOINT 0x00080000
+#define TX4939_CRYPTO_CSR_DCINT 0x00040000
+#define TX4939_CRYPTO_CSR_GBINT 0x00010000
+#define TX4939_CRYPTO_CSR_INDXAST_MASK  0x0000e000
+#define TX4939_CRYPTO_CSR_INDXAST(n)    ((n) << 13)
+#define TX4939_CRYPTO_CSR_CSWAP_MASK    0x00001800
+#define TX4939_CRYPTO_CSR_CSWAP_NONE    0x00000000
+#define TX4939_CRYPTO_CSR_CSWAP_IN      0x00000800
+#define TX4939_CRYPTO_CSR_CSWAP_OUT     0x00001000
+#define TX4939_CRYPTO_CSR_CSWAP_BOTH    0x00001800
+#define TX4939_CRYPTO_CSR_CDIV_MASK     0x00000600
+#define TX4939_CRYPTO_CSR_CDIV_DIV2     0x00000000
+#define TX4939_CRYPTO_CSR_CDIV_DIV1     0x00000200
+#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT  0x00000400
+#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT  0x00000600
+#define TX4939_CRYPTO_CSR_PDINT_MASK    0x000000c0
+#define TX4939_CRYPTO_CSR_PDINT_ALL     0x00000000
+#define TX4939_CRYPTO_CSR_PDINT_END     0x00000040
+#define TX4939_CRYPTO_CSR_PDINT_NEXT    0x00000080
+#define TX4939_CRYPTO_CSR_PDINT_NONE    0x000000c0
+#define TX4939_CRYPTO_CSR_GINTE 0x00000008
+#define TX4939_CRYPTO_CSR_RSTD  0x00000004
+#define TX4939_CRYPTO_CSR_RSTC  0x00000002
+#define TX4939_CRYPTO_CSR_ENCR  0x00000001
+
+/* bits for tx4939_crypto_reg.cdr.gen.ctrl */
+#define TX4939_CRYPTO_CTX_ENGINE_MASK   0x00000003
+#define TX4939_CRYPTO_CTX_ENGINE_DES    0x00000000
+#define TX4939_CRYPTO_CTX_ENGINE_AES    0x00000001
+#define TX4939_CRYPTO_CTX_ENGINE_MD5    0x00000002
+#define TX4939_CRYPTO_CTX_ENGINE_SHA1   0x00000003
+#define TX4939_CRYPTO_CTX_TDMS  0x00000010
+#define TX4939_CRYPTO_CTX_CMS   0x00000020
+#define TX4939_CRYPTO_CTX_DMS   0x00000040
+#define TX4939_CRYPTO_CTX_UPDATE        0x00000080
+
+/* bits for tx4939_crypto_desc.ctrl */
+#define TX4939_CRYPTO_DESC_OB_CNT_MASK  0xffe00000
+#define TX4939_CRYPTO_DESC_OB_CNT(cnt)  ((cnt) << 21)
+#define TX4939_CRYPTO_DESC_IB_CNT_MASK  0x001ffc00
+#define TX4939_CRYPTO_DESC_IB_CNT(cnt)  ((cnt) << 10)
+#define TX4939_CRYPTO_DESC_START        0x00000200
+#define TX4939_CRYPTO_DESC_END  0x00000100
+#define TX4939_CRYPTO_DESC_XOR  0x00000010
+#define TX4939_CRYPTO_DESC_LAST 0x00000008
+#define TX4939_CRYPTO_DESC_ERR_MASK     0x00000006
+#define TX4939_CRYPTO_DESC_ERR_NONE     0x00000000
+#define TX4939_CRYPTO_DESC_ERR_TOUT     0x00000002
+#define TX4939_CRYPTO_DESC_ERR_DIGEST   0x00000004
+#define TX4939_CRYPTO_DESC_OWN  0x00000001
+
+/* bits for tx4939_crypto_desc.index */
+#define TX4939_CRYPTO_DESC_HASH_IDX_MASK        0x00000070
+#define TX4939_CRYPTO_DESC_HASH_IDX(idx)        ((idx) << 4)
+#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK     0x00000007
+#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx)     ((idx) << 0)
+
+#define TX4939_CRYPTO_NR_SET    6
+
+#define TX4939_CRYPTO_RCSR_INTE 0x00000008
+#define TX4939_CRYPTO_RCSR_RST  0x00000004
+#define TX4939_CRYPTO_RCSR_FIN  0x00000002
+#define TX4939_CRYPTO_RCSR_ST   0x00000001
+
+/*
+ * VPC
+ */
+#define TX4939_VPC_CSR_GBINT    0x00010000
+#define TX4939_VPC_CSR_SWAPO    0x00000020
+#define TX4939_VPC_CSR_SWAPI    0x00000010
+#define TX4939_VPC_CSR_GINTE    0x00000008
+#define TX4939_VPC_CSR_RSTD     0x00000004
+#define TX4939_VPC_CSR_RSTVPC   0x00000002
+
+#define TX4939_VPC_CTRLA_VDPSN  0x00000200
+#define TX4939_VPC_CTRLA_PBUSY  0x00000100
+#define TX4939_VPC_CTRLA_DCINT  0x00000080
+#define TX4939_VPC_CTRLA_UOINT  0x00000040
+#define TX4939_VPC_CTRLA_PDINT_MASK     0x00000030
+#define TX4939_VPC_CTRLA_PDINT_ALL      0x00000000
+#define TX4939_VPC_CTRLA_PDINT_NEXT     0x00000010
+#define TX4939_VPC_CTRLA_PDINT_NONE     0x00000030
+#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
+#define TX4939_VPC_CTRLA_VDMODE 0x00000004
+#define TX4939_VPC_CTRLA_VDFOR  0x00000002
+#define TX4939_VPC_CTRLA_ENVPC  0x00000001
+
+/* bits for tx4939_vpc_desc.ctrl1 */
+#define TX4939_VPC_DESC_CTRL1_ERR_MASK  0x00000006
+#define TX4939_VPC_DESC_CTRL1_OWN       0x00000001
+
+#define tx4939_ddrcptr  ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG)
+#define tx4939_ebuscptr         tx4938_ebuscptr
+#define tx4939_ircptr \
+                ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG)
+#define tx4939_pcicptr          tx4938_pcicptr
+#define tx4939_pcic1ptr         tx4938_pcic1ptr
+#define tx4939_ccfgptr \
+                ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG)
+#define tx4939_sramcptr         tx4938_sramcptr
+#define tx4939_rtcptr \
+                ((struct tx4939_rtc_reg __iomem *)TX4939_RTC_REG)
+#define tx4939_cryptoptr \
+                ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG)
+#define tx4939_vpcptr   ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG)
+
+#define TX4939_REV_MAJ_MIN()    \
+        ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff)
+#define TX4939_REV_PCODE()      \
+        ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16)
+#define TX4939_CCFG_BCFG()      \
+        ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
+                 >> 32))
+
+#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
+#define tx4939_ccfg_set(bits)   tx4938_ccfg_set(bits)
+#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
+
+#define TX4939_EBUSC_CR(ch)     TX4927_EBUSC_CR(ch)
+#define TX4939_EBUSC_BA(ch)     TX4927_EBUSC_BA(ch)
+#define TX4939_EBUSC_SIZE(ch)   TX4927_EBUSC_SIZE(ch)
+#define TX4939_EBUSC_WIDTH(ch)  \
+        (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
+
+/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2  (14.745MHz for MST 20MHz) */
+#define TX4939_SCLK0(mst)       \
+        ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
+
+void tx4939_wdt_init(void);
+void tx4939_add_memory_regions(void);
+void tx4939_setup(void);
+void tx4939_time_init(unsigned int tmrnr);
+void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
+void tx4939_spi_init(int busid);
+void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
+int tx4939_report_pciclk(void);
+void tx4939_report_pci1clk(void);
+struct pci_dev;
+int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
+int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+void tx4939_setup_pcierr_irq(void);
+void tx4939_irq_init(void);
+int tx4939_irq(void);
+void tx4939_mtd_init(int ch);
+void tx4939_ata_init(void);
+
+#endif /* __ASM_TXX9_TX4939_H */
diff --git a/arch/mips/include/asm/txx9irq.h b/arch/mips/include/asm/txx9irq.h
new file mode 100644
index 000000000000..5620879be37f
--- /dev/null
+++ b/arch/mips/include/asm/txx9irq.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-mips/txx9irq.h
+ * TX39/TX49 interrupt controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9IRQ_H
+#define __ASM_TXX9IRQ_H
+
+#include <irq.h>
+
+#ifdef CONFIG_IRQ_CPU
+#define TXX9_IRQ_BASE   (MIPS_CPU_IRQ_BASE + 8)
+#else
+#ifdef CONFIG_I8259
+#define TXX9_IRQ_BASE   (I8259A_IRQ_BASE + 16)
+#else
+#define TXX9_IRQ_BASE   0
+#endif
+#endif
+
+#ifdef CONFIG_CPU_TX39XX
+#define TXx9_MAX_IR 16
+#else
+#define TXx9_MAX_IR 32
+#endif
+
+void txx9_irq_init(unsigned long baseaddr);
+int txx9_irq(void);
+int txx9_irq_set_pri(int irc_irq, int new_pri);
+
+#endif /* __ASM_TXX9IRQ_H */
diff --git a/arch/mips/include/asm/txx9pio.h b/arch/mips/include/asm/txx9pio.h
new file mode 100644
index 000000000000..3d6fa9f8d513
--- /dev/null
+++ b/arch/mips/include/asm/txx9pio.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-mips/txx9pio.h
+ * TX39/TX49 PIO controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9PIO_H
+#define __ASM_TXX9PIO_H
+
+#include <linux/types.h>
+
+struct txx9_pio_reg {
+        __u32 dout;
+        __u32 din;
+        __u32 dir;
+        __u32 od;
+        __u32 flag[2];
+        __u32 pol;
+        __u32 intc;
+        __u32 maskcpu;
+        __u32 maskext;
+};
+
+int txx9_gpio_init(unsigned long baseaddr,
+                   unsigned int base, unsigned int num);
+
+#endif /* __ASM_TXX9PIO_H */
diff --git a/arch/mips/include/asm/txx9tmr.h b/arch/mips/include/asm/txx9tmr.h
new file mode 100644
index 000000000000..67f70a8f09bd
--- /dev/null
+++ b/arch/mips/include/asm/txx9tmr.h
@@ -0,0 +1,67 @@
+/*
+ * include/asm-mips/txx9tmr.h
+ * TX39/TX49 timer controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9TMR_H
+#define __ASM_TXX9TMR_H
+
+#include <linux/types.h>
+
+struct txx9_tmr_reg {
+        u32 tcr;
+        u32 tisr;
+        u32 cpra;
+        u32 cprb;
+        u32 itmr;
+        u32 unused0[3];
+        u32 ccdr;
+        u32 unused1[3];
+        u32 pgmr;
+        u32 unused2[3];
+        u32 wtmr;
+        u32 unused3[43];
+        u32 trr;
+};
+
+/* TMTCR : Timer Control */
+#define TXx9_TMTCR_TCE          0x00000080
+#define TXx9_TMTCR_CCDE         0x00000040
+#define TXx9_TMTCR_CRE          0x00000020
+#define TXx9_TMTCR_ECES         0x00000008
+#define TXx9_TMTCR_CCS          0x00000004
+#define TXx9_TMTCR_TMODE_MASK   0x00000003
+#define TXx9_TMTCR_TMODE_ITVL   0x00000000
+#define TXx9_TMTCR_TMODE_PGEN   0x00000001
+#define TXx9_TMTCR_TMODE_WDOG   0x00000002
+
+/* TMTISR : Timer Int. Status */
+#define TXx9_TMTISR_TPIBS       0x00000004
+#define TXx9_TMTISR_TPIAS       0x00000002
+#define TXx9_TMTISR_TIIS        0x00000001
+
+/* TMITMR : Interval Timer Mode */
+#define TXx9_TMITMR_TIIE        0x00008000
+#define TXx9_TMITMR_TZCE        0x00000001
+
+/* TMWTMR : Watchdog Timer Mode */
+#define TXx9_TMWTMR_TWIE        0x00008000
+#define TXx9_TMWTMR_WDIS        0x00000080
+#define TXx9_TMWTMR_TWC         0x00000001
+
+void txx9_clocksource_init(unsigned long baseaddr,
+                           unsigned int imbusclk);
+void txx9_clockevent_init(unsigned long baseaddr, int irq,
+                          unsigned int imbusclk);
+void txx9_tmr_init(unsigned long baseaddr);
+
+#ifdef CONFIG_CPU_TX39XX
+#define TXX9_TIMER_BITS 24
+#else
+#define TXX9_TIMER_BITS 32
+#endif
+
+#endif /* __ASM_TXX9TMR_H */
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
new file mode 100644
index 000000000000..bcbb8d675af5
--- /dev/null
+++ b/arch/mips/include/asm/types.h
@@ -0,0 +1,54 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TYPES_H
+#define _ASM_TYPES_H
+
+#if _MIPS_SZLONG == 64
+# include <asm-generic/int-l64.h>
+#else
+# include <asm-generic/int-ll64.h>
+#endif
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG _MIPS_SZLONG
+
+#ifndef __ASSEMBLY__
+
+#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
+    || defined(CONFIG_64BIT)
+typedef u64 dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+typedef u64 dma64_addr_t;
+
+/*
+ * Don't use phys_t.  You've been warned.
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+typedef unsigned long long phys_t;
+#else
+typedef unsigned long phys_t;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_TYPES_H */
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
new file mode 100644
index 000000000000..09ff5bb17445
--- /dev/null
+++ b/arch/mips/include/asm/uaccess.h
@@ -0,0 +1,1114 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2007  Maciej W. Rozycki
+ */
+#ifndef _ASM_UACCESS_H
+#define _ASM_UACCESS_H
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/thread_info.h>
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ */
+#ifdef CONFIG_32BIT
+
+#define __UA_LIMIT      0x80000000UL
+
+#define __UA_ADDR       ".word"
+#define __UA_LA         "la"
+#define __UA_ADDU       "addu"
+#define __UA_t0         "$8"
+#define __UA_t1         "$9"
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#define __UA_LIMIT      (- TASK_SIZE)
+
+#define __UA_ADDR       ".dword"
+#define __UA_LA         "dla"
+#define __UA_ADDU       "daddu"
+#define __UA_t0         "$12"
+#define __UA_t1         "$13"
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * USER_DS is a bitmask that has the bits set that may not be set in a valid
+ * userspace address.  Note that we limit 32-bit userspace to 0x7fff8000 but
+ * the arithmetic we're doing only works if the limit is a power of two, so
+ * we use 0x80000000 here on 32-bit kernels.  If a process passes an invalid
+ * address in this range it's the process's problem, not ours :-)
+ */
+
+#define KERNEL_DS       ((mm_segment_t) { 0UL })
+#define USER_DS         ((mm_segment_t) { __UA_LIMIT })
+
+#define VERIFY_READ    0
+#define VERIFY_WRITE   1
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current_thread_info()->addr_limit)
+#define set_fs(x)       (current_thread_info()->addr_limit = (x))
+
+#define segment_eq(a, b)        ((a).seg == (b).seg)
+
+
+/*
+ * Is a address valid? This does a straighforward calculation rather
+ * than tests.
+ *
+ * Address valid if:
+ *  - "addr" doesn't have any high-bits set
+ *  - AND "size" doesn't have any high-bits set
+ *  - AND "addr+size" doesn't have any high-bits set
+ *  - OR we are in kernel mode.
+ *
+ * __ua_size() is a trick to avoid runtime checking of positive constant
+ * sizes; for those we already know at compile time that the size is ok.
+ */
+#define __ua_size(size)                                                 \
+        ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size))
+
+/*
+ * access_ok: - Checks if a user space pointer is valid
+ * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE.  Note that
+ *        %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
+ *        to write to a block, it is always safe to read from it.
+ * @addr: User space pointer to start of block to check
+ * @size: Size of block to check
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Checks if a pointer to a block of memory in user space is valid.
+ *
+ * Returns true (nonzero) if the memory block may be valid, false (zero)
+ * if it is definitely invalid.
+ *
+ * Note that, depending on architecture, this function probably just
+ * checks that the pointer is in the user space range - after calling
+ * this function, memory access functions may still return -EFAULT.
+ */
+
+#define __access_mask get_fs().seg
+
+#define __access_ok(addr, size, mask)                                   \
+        (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0)
+
+#define access_ok(type, addr, size)                                     \
+        likely(__access_ok((unsigned long)(addr), (size), __access_mask))
+
+/*
+ * put_user: - Write a simple value into user space.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define put_user(x,ptr) \
+        __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * get_user: - Get a simple variable from user space.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define get_user(x,ptr) \
+        __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * __put_user: - Write a simple value into user space, with less checking.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define __put_user(x,ptr) \
+        __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * __get_user: - Get a simple variable from user space, with less checking.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define __get_user(x,ptr) \
+        __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct __user *)(x))
+
+/*
+ * Yuck.  We need two variants, one for 64bit operation and one
+ * for 32 bit mode and old iron.
+ */
+#ifdef CONFIG_32BIT
+#define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr)
+#endif
+#ifdef CONFIG_64BIT
+#define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr)
+#endif
+
+extern void __get_user_unknown(void);
+
+#define __get_user_common(val, size, ptr)                               \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __get_user_asm(val, "lb", ptr); break;                  \
+        case 2: __get_user_asm(val, "lh", ptr); break;                  \
+        case 4: __get_user_asm(val, "lw", ptr); break;                  \
+        case 8: __GET_USER_DW(val, ptr); break;                         \
+        default: __get_user_unknown(); break;                           \
+        }                                                               \
+} while (0)
+
+#define __get_user_nocheck(x, ptr, size)                                \
+({                                                                      \
+        int __gu_err;                                                   \
+                                                                        \
+        __get_user_common((x), size, ptr);                              \
+        __gu_err;                                                       \
+})
+
+#define __get_user_check(x, ptr, size)                                  \
+({                                                                      \
+        int __gu_err = -EFAULT;                                         \
+        const __typeof__(*(ptr)) __user * __gu_ptr = (ptr);             \
+                                                                        \
+        if (likely(access_ok(VERIFY_READ,  __gu_ptr, size)))            \
+                __get_user_common((x), size, __gu_ptr);                 \
+                                                                        \
+        __gu_err;                                                       \
+})
+
+#define __get_user_asm(val, insn, addr)                                 \
+{                                                                       \
+        long __gu_tmp;                                                  \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "1:     " insn "        %1, %3                          \n"     \
+        "2:                                                     \n"     \
+        "       .section .fixup,\"ax\"                          \n"     \
+        "3:     li      %0, %4                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section __ex_table,\"a\"                       \n"     \
+        "       "__UA_ADDR "\t1b, 3b                            \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__gu_err), "=r" (__gu_tmp)                              \
+        : "0" (0), "o" (__m(addr)), "i" (-EFAULT));                     \
+                                                                        \
+        (val) = (__typeof__(*(addr))) __gu_tmp;                         \
+}
+
+/*
+ * Get a long long 64 using 32 bit registers.
+ */
+#define __get_user_asm_ll32(val, addr)                                  \
+{                                                                       \
+        union {                                                         \
+                unsigned long long      l;                              \
+                __typeof__(*(addr))     t;                              \
+        } __gu_tmp;                                                     \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "1:     lw      %1, (%3)                                \n"     \
+        "2:     lw      %D1, 4(%3)                              \n"     \
+        "3:     .section        .fixup,\"ax\"                   \n"     \
+        "4:     li      %0, %4                                  \n"     \
+        "       move    %1, $0                                  \n"     \
+        "       move    %D1, $0                                 \n"     \
+        "       j       3b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 4b                          \n"     \
+        "       " __UA_ADDR "   2b, 4b                          \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__gu_err), "=&r" (__gu_tmp.l)                           \
+        : "0" (0), "r" (addr), "i" (-EFAULT));                          \
+                                                                        \
+        (val) = __gu_tmp.t;                                             \
+}
+
+/*
+ * Yuck.  We need two variants, one for 64bit operation and one
+ * for 32 bit mode and old iron.
+ */
+#ifdef CONFIG_32BIT
+#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr)
+#endif
+#ifdef CONFIG_64BIT
+#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
+#endif
+
+#define __put_user_nocheck(x, ptr, size)                                \
+({                                                                      \
+        __typeof__(*(ptr)) __pu_val;                                    \
+        int __pu_err = 0;                                               \
+                                                                        \
+        __pu_val = (x);                                                 \
+        switch (size) {                                                 \
+        case 1: __put_user_asm("sb", ptr); break;                       \
+        case 2: __put_user_asm("sh", ptr); break;                       \
+        case 4: __put_user_asm("sw", ptr); break;                       \
+        case 8: __PUT_USER_DW(ptr); break;                              \
+        default: __put_user_unknown(); break;                           \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_user_check(x, ptr, size)                                  \
+({                                                                      \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
+        __typeof__(*(ptr)) __pu_val = (x);                              \
+        int __pu_err = -EFAULT;                                         \
+                                                                        \
+        if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {        \
+                switch (size) {                                         \
+                case 1: __put_user_asm("sb", __pu_addr); break;         \
+                case 2: __put_user_asm("sh", __pu_addr); break;         \
+                case 4: __put_user_asm("sw", __pu_addr); break;         \
+                case 8: __PUT_USER_DW(__pu_addr); break;                \
+                default: __put_user_unknown(); break;                   \
+                }                                                       \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_user_asm(insn, ptr)                                       \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:     " insn "        %z2, %3         # __put_user_asm\n"     \
+        "2:                                                     \n"     \
+        "       .section        .fixup,\"ax\"                   \n"     \
+        "3:     li      %0, %4                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 3b                          \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__pu_err)                                               \
+        : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)),                     \
+          "i" (-EFAULT));                                               \
+}
+
+#define __put_user_asm_ll32(ptr)                                        \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:     sw      %2, (%3)        # __put_user_asm_ll32   \n"     \
+        "2:     sw      %D2, 4(%3)                              \n"     \
+        "3:                                                     \n"     \
+        "       .section        .fixup,\"ax\"                   \n"     \
+        "4:     li      %0, %4                                  \n"     \
+        "       j       3b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 4b                          \n"     \
+        "       " __UA_ADDR "   2b, 4b                          \n"     \
+        "       .previous"                                              \
+        : "=r" (__pu_err)                                               \
+        : "0" (0), "r" (__pu_val), "r" (ptr),                           \
+          "i" (-EFAULT));                                               \
+}
+
+extern void __put_user_unknown(void);
+
+/*
+ * put_user_unaligned: - Write a simple value into user space.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define put_user_unaligned(x,ptr)       \
+        __put_user_unaligned_check((x),(ptr),sizeof(*(ptr)))
+
+/*
+ * get_user_unaligned: - Get a simple variable from user space.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define get_user_unaligned(x,ptr) \
+        __get_user_unaligned_check((x),(ptr),sizeof(*(ptr)))
+
+/*
+ * __put_user_unaligned: - Write a simple value into user space, with less checking.
+ * @x:   Value to copy to user space.
+ * @ptr: Destination address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple value from kernel space to user
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and @x must be assignable
+ * to the result of dereferencing @ptr.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ */
+#define __put_user_unaligned(x,ptr) \
+        __put_user_unaligned_nocheck((x),(ptr),sizeof(*(ptr)))
+
+/*
+ * __get_user_unaligned: - Get a simple variable from user space, with less checking.
+ * @x:   Variable to store result.
+ * @ptr: Source address, in user space.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * This macro copies a single simple variable from user space to kernel
+ * space.  It supports simple types like char and int, but not larger
+ * data types like structures or arrays.
+ *
+ * @ptr must have pointer-to-simple-variable type, and the result of
+ * dereferencing @ptr must be assignable to @x without a cast.
+ *
+ * Caller must check the pointer with access_ok() before calling this
+ * function.
+ *
+ * Returns zero on success, or -EFAULT on error.
+ * On error, the variable @x is set to zero.
+ */
+#define __get_user_unaligned(x,ptr) \
+        __get_user__unalignednocheck((x),(ptr),sizeof(*(ptr)))
+
+/*
+ * Yuck.  We need two variants, one for 64bit operation and one
+ * for 32 bit mode and old iron.
+ */
+#ifdef CONFIG_32BIT
+#define __GET_USER_UNALIGNED_DW(val, ptr)                               \
+        __get_user_unaligned_asm_ll32(val, ptr)
+#endif
+#ifdef CONFIG_64BIT
+#define __GET_USER_UNALIGNED_DW(val, ptr)                               \
+        __get_user_unaligned_asm(val, "uld", ptr)
+#endif
+
+extern void __get_user_unaligned_unknown(void);
+
+#define __get_user_unaligned_common(val, size, ptr)                     \
+do {                                                                    \
+        switch (size) {                                                 \
+        case 1: __get_user_asm(val, "lb", ptr); break;                  \
+        case 2: __get_user_unaligned_asm(val, "ulh", ptr); break;       \
+        case 4: __get_user_unaligned_asm(val, "ulw", ptr); break;       \
+        case 8: __GET_USER_UNALIGNED_DW(val, ptr); break;               \
+        default: __get_user_unaligned_unknown(); break;                 \
+        }                                                               \
+} while (0)
+
+#define __get_user_unaligned_nocheck(x,ptr,size)                        \
+({                                                                      \
+        int __gu_err;                                                   \
+                                                                        \
+        __get_user_unaligned_common((x), size, ptr);                    \
+        __gu_err;                                                       \
+})
+
+#define __get_user_unaligned_check(x,ptr,size)                          \
+({                                                                      \
+        int __gu_err = -EFAULT;                                         \
+        const __typeof__(*(ptr)) __user * __gu_ptr = (ptr);             \
+                                                                        \
+        if (likely(access_ok(VERIFY_READ,  __gu_ptr, size)))            \
+                __get_user_unaligned_common((x), size, __gu_ptr);       \
+                                                                        \
+        __gu_err;                                                       \
+})
+
+#define __get_user_unaligned_asm(val, insn, addr)                       \
+{                                                                       \
+        long __gu_tmp;                                                  \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "1:     " insn "        %1, %3                          \n"     \
+        "2:                                                     \n"     \
+        "       .section .fixup,\"ax\"                          \n"     \
+        "3:     li      %0, %4                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section __ex_table,\"a\"                       \n"     \
+        "       "__UA_ADDR "\t1b, 3b                            \n"     \
+        "       "__UA_ADDR "\t1b + 4, 3b                        \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__gu_err), "=r" (__gu_tmp)                              \
+        : "0" (0), "o" (__m(addr)), "i" (-EFAULT));                     \
+                                                                        \
+        (val) = (__typeof__(*(addr))) __gu_tmp;                         \
+}
+
+/*
+ * Get a long long 64 using 32 bit registers.
+ */
+#define __get_user_unaligned_asm_ll32(val, addr)                        \
+{                                                                       \
+        unsigned long long __gu_tmp;                                    \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "1:     ulw     %1, (%3)                                \n"     \
+        "2:     ulw     %D1, 4(%3)                              \n"     \
+        "       move    %0, $0                                  \n"     \
+        "3:     .section        .fixup,\"ax\"                   \n"     \
+        "4:     li      %0, %4                                  \n"     \
+        "       move    %1, $0                                  \n"     \
+        "       move    %D1, $0                                 \n"     \
+        "       j       3b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 4b                          \n"     \
+        "       " __UA_ADDR "   1b + 4, 4b                      \n"     \
+        "       " __UA_ADDR "   2b, 4b                          \n"     \
+        "       " __UA_ADDR "   2b + 4, 4b                      \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__gu_err), "=&r" (__gu_tmp)                             \
+        : "0" (0), "r" (addr), "i" (-EFAULT));                          \
+        (val) = (__typeof__(*(addr))) __gu_tmp;                         \
+}
+
+/*
+ * Yuck.  We need two variants, one for 64bit operation and one
+ * for 32 bit mode and old iron.
+ */
+#ifdef CONFIG_32BIT
+#define __PUT_USER_UNALIGNED_DW(ptr) __put_user_unaligned_asm_ll32(ptr)
+#endif
+#ifdef CONFIG_64BIT
+#define __PUT_USER_UNALIGNED_DW(ptr) __put_user_unaligned_asm("usd", ptr)
+#endif
+
+#define __put_user_unaligned_nocheck(x,ptr,size)                        \
+({                                                                      \
+        __typeof__(*(ptr)) __pu_val;                                    \
+        int __pu_err = 0;                                               \
+                                                                        \
+        __pu_val = (x);                                                 \
+        switch (size) {                                                 \
+        case 1: __put_user_asm("sb", ptr); break;                       \
+        case 2: __put_user_unaligned_asm("ush", ptr); break;            \
+        case 4: __put_user_unaligned_asm("usw", ptr); break;            \
+        case 8: __PUT_USER_UNALIGNED_DW(ptr); break;                    \
+        default: __put_user_unaligned_unknown(); break;                 \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_user_unaligned_check(x,ptr,size)                          \
+({                                                                      \
+        __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
+        __typeof__(*(ptr)) __pu_val = (x);                              \
+        int __pu_err = -EFAULT;                                         \
+                                                                        \
+        if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {        \
+                switch (size) {                                         \
+                case 1: __put_user_asm("sb", __pu_addr); break;         \
+                case 2: __put_user_unaligned_asm("ush", __pu_addr); break; \
+                case 4: __put_user_unaligned_asm("usw", __pu_addr); break; \
+                case 8: __PUT_USER_UNALGINED_DW(__pu_addr); break;      \
+                default: __put_user_unaligned_unknown(); break;         \
+                }                                                       \
+        }                                                               \
+        __pu_err;                                                       \
+})
+
+#define __put_user_unaligned_asm(insn, ptr)                             \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:     " insn "        %z2, %3         # __put_user_unaligned_asm\n" \
+        "2:                                                     \n"     \
+        "       .section        .fixup,\"ax\"                   \n"     \
+        "3:     li      %0, %4                                  \n"     \
+        "       j       2b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 3b                          \n"     \
+        "       .previous                                       \n"     \
+        : "=r" (__pu_err)                                               \
+        : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)),                     \
+          "i" (-EFAULT));                                               \
+}
+
+#define __put_user_unaligned_asm_ll32(ptr)                              \
+{                                                                       \
+        __asm__ __volatile__(                                           \
+        "1:     sw      %2, (%3)        # __put_user_unaligned_asm_ll32 \n" \
+        "2:     sw      %D2, 4(%3)                              \n"     \
+        "3:                                                     \n"     \
+        "       .section        .fixup,\"ax\"                   \n"     \
+        "4:     li      %0, %4                                  \n"     \
+        "       j       3b                                      \n"     \
+        "       .previous                                       \n"     \
+        "       .section        __ex_table,\"a\"                \n"     \
+        "       " __UA_ADDR "   1b, 4b                          \n"     \
+        "       " __UA_ADDR "   1b + 4, 4b                      \n"     \
+        "       " __UA_ADDR "   2b, 4b                          \n"     \
+        "       " __UA_ADDR "   2b + 4, 4b                      \n"     \
+        "       .previous"                                              \
+        : "=r" (__pu_err)                                               \
+        : "0" (0), "r" (__pu_val), "r" (ptr),                           \
+          "i" (-EFAULT));                                               \
+}
+
+extern void __put_user_unaligned_unknown(void);
+
+/*
+ * We're generating jump to subroutines which will be outside the range of
+ * jump instructions
+ */
+#ifdef MODULE
+#define __MODULE_JAL(destination)                                       \
+        ".set\tnoat\n\t"                                                \
+        __UA_LA "\t$1, " #destination "\n\t"                            \
+        "jalr\t$1\n\t"                                                  \
+        ".set\tat\n\t"
+#else
+#define __MODULE_JAL(destination)                                       \
+        "jal\t" #destination "\n\t"
+#endif
+
+#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
+#define DADDI_SCRATCH "$0"
+#else
+#define DADDI_SCRATCH "$3"
+#endif
+
+extern size_t __copy_user(void *__to, const void *__from, size_t __n);
+
+#define __invoke_copy_to_user(to, from, n)                              \
+({                                                                      \
+        register void __user *__cu_to_r __asm__("$4");                  \
+        register const void *__cu_from_r __asm__("$5");                 \
+        register long __cu_len_r __asm__("$6");                         \
+                                                                        \
+        __cu_to_r = (to);                                               \
+        __cu_from_r = (from);                                           \
+        __cu_len_r = (n);                                               \
+        __asm__ __volatile__(                                           \
+        __MODULE_JAL(__copy_user)                                       \
+        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
+        :                                                               \
+        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
+          DADDI_SCRATCH, "memory");                                     \
+        __cu_len_r;                                                     \
+})
+
+/*
+ * __copy_to_user: - Copy a block of data into user space, with less checking.
+ * @to:   Destination address, in user space.
+ * @from: Source address, in kernel space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from kernel space to user space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ */
+#define __copy_to_user(to, from, n)                                     \
+({                                                                      \
+        void __user *__cu_to;                                           \
+        const void *__cu_from;                                          \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
+        __cu_len;                                                       \
+})
+
+extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
+
+#define __copy_to_user_inatomic(to, from, n)                            \
+({                                                                      \
+        void __user *__cu_to;                                           \
+        const void *__cu_from;                                          \
+        long __cu_len;                                                  \
+                                                                        \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
+        __cu_len;                                                       \
+})
+
+#define __copy_from_user_inatomic(to, from, n)                          \
+({                                                                      \
+        void *__cu_to;                                                  \
+        const void __user *__cu_from;                                   \
+        long __cu_len;                                                  \
+                                                                        \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        __cu_len = __invoke_copy_from_user_inatomic(__cu_to, __cu_from, \
+                                                    __cu_len);          \
+        __cu_len;                                                       \
+})
+
+/*
+ * copy_to_user: - Copy a block of data into user space.
+ * @to:   Destination address, in user space.
+ * @from: Source address, in kernel space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from kernel space to user space.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ */
+#define copy_to_user(to, from, n)                                       \
+({                                                                      \
+        void __user *__cu_to;                                           \
+        const void *__cu_from;                                          \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        if (access_ok(VERIFY_WRITE, __cu_to, __cu_len))                 \
+                __cu_len = __invoke_copy_to_user(__cu_to, __cu_from,    \
+                                                 __cu_len);             \
+        __cu_len;                                                       \
+})
+
+#define __invoke_copy_from_user(to, from, n)                            \
+({                                                                      \
+        register void *__cu_to_r __asm__("$4");                         \
+        register const void __user *__cu_from_r __asm__("$5");          \
+        register long __cu_len_r __asm__("$6");                         \
+                                                                        \
+        __cu_to_r = (to);                                               \
+        __cu_from_r = (from);                                           \
+        __cu_len_r = (n);                                               \
+        __asm__ __volatile__(                                           \
+        ".set\tnoreorder\n\t"                                           \
+        __MODULE_JAL(__copy_user)                                       \
+        ".set\tnoat\n\t"                                                \
+        __UA_ADDU "\t$1, %1, %2\n\t"                                    \
+        ".set\tat\n\t"                                                  \
+        ".set\treorder"                                                 \
+        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
+        :                                                               \
+        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
+          DADDI_SCRATCH, "memory");                                     \
+        __cu_len_r;                                                     \
+})
+
+#define __invoke_copy_from_user_inatomic(to, from, n)                   \
+({                                                                      \
+        register void *__cu_to_r __asm__("$4");                         \
+        register const void __user *__cu_from_r __asm__("$5");          \
+        register long __cu_len_r __asm__("$6");                         \
+                                                                        \
+        __cu_to_r = (to);                                               \
+        __cu_from_r = (from);                                           \
+        __cu_len_r = (n);                                               \
+        __asm__ __volatile__(                                           \
+        ".set\tnoreorder\n\t"                                           \
+        __MODULE_JAL(__copy_user_inatomic)                              \
+        ".set\tnoat\n\t"                                                \
+        __UA_ADDU "\t$1, %1, %2\n\t"                                    \
+        ".set\tat\n\t"                                                  \
+        ".set\treorder"                                                 \
+        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
+        :                                                               \
+        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
+          DADDI_SCRATCH, "memory");                                     \
+        __cu_len_r;                                                     \
+})
+
+/*
+ * __copy_from_user: - Copy a block of data from user space, with less checking.
+ * @to:   Destination address, in kernel space.
+ * @from: Source address, in user space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from user space to kernel space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ *
+ * If some data could not be copied, this function will pad the copied
+ * data to the requested size using zero bytes.
+ */
+#define __copy_from_user(to, from, n)                                   \
+({                                                                      \
+        void *__cu_to;                                                  \
+        const void __user *__cu_from;                                   \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,          \
+                                           __cu_len);                   \
+        __cu_len;                                                       \
+})
+
+/*
+ * copy_from_user: - Copy a block of data from user space.
+ * @to:   Destination address, in kernel space.
+ * @from: Source address, in user space.
+ * @n:    Number of bytes to copy.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Copy data from user space to kernel space.
+ *
+ * Returns number of bytes that could not be copied.
+ * On success, this will be zero.
+ *
+ * If some data could not be copied, this function will pad the copied
+ * data to the requested size using zero bytes.
+ */
+#define copy_from_user(to, from, n)                                     \
+({                                                                      \
+        void *__cu_to;                                                  \
+        const void __user *__cu_from;                                   \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        if (access_ok(VERIFY_READ, __cu_from, __cu_len))                \
+                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
+                                                   __cu_len);           \
+        __cu_len;                                                       \
+})
+
+#define __copy_in_user(to, from, n)     __copy_from_user(to, from, n)
+
+#define copy_in_user(to, from, n)                                       \
+({                                                                      \
+        void __user *__cu_to;                                           \
+        const void __user *__cu_from;                                   \
+        long __cu_len;                                                  \
+                                                                        \
+        might_sleep();                                                  \
+        __cu_to = (to);                                                 \
+        __cu_from = (from);                                             \
+        __cu_len = (n);                                                 \
+        if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&       \
+                   access_ok(VERIFY_WRITE, __cu_to, __cu_len)))         \
+                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
+                                                   __cu_len);           \
+        __cu_len;                                                       \
+})
+
+/*
+ * __clear_user: - Zero a block of memory in user space, with less checking.
+ * @to:   Destination address, in user space.
+ * @n:    Number of bytes to zero.
+ *
+ * Zero a block of memory in user space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be cleared.
+ * On success, this will be zero.
+ */
+static inline __kernel_size_t
+__clear_user(void __user *addr, __kernel_size_t size)
+{
+        __kernel_size_t res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, $0\n\t"
+                "move\t$6, %2\n\t"
+                __MODULE_JAL(__bzero)
+                "move\t%0, $6"
+                : "=r" (res)
+                : "r" (addr), "r" (size)
+                : "$4", "$5", "$6", __UA_t0, __UA_t1, "$31");
+
+        return res;
+}
+
+#define clear_user(addr,n)                                              \
+({                                                                      \
+        void __user * __cl_addr = (addr);                               \
+        unsigned long __cl_size = (n);                                  \
+        if (__cl_size && access_ok(VERIFY_WRITE,                        \
+                ((unsigned long)(__cl_addr)), __cl_size))               \
+                __cl_size = __clear_user(__cl_addr, __cl_size);         \
+        __cl_size;                                                      \
+})
+
+/*
+ * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking.
+ * @dst:   Destination address, in kernel space.  This buffer must be at
+ *         least @count bytes long.
+ * @src:   Source address, in user space.
+ * @count: Maximum number of bytes to copy, including the trailing NUL.
+ *
+ * Copies a NUL-terminated string from userspace to kernel space.
+ * Caller must check the specified block with access_ok() before calling
+ * this function.
+ *
+ * On success, returns the length of the string (not including the trailing
+ * NUL).
+ *
+ * If access to userspace fails, returns -EFAULT (some data may have been
+ * copied).
+ *
+ * If @count is smaller than the length of the string, copies @count bytes
+ * and returns @count.
+ */
+static inline long
+__strncpy_from_user(char *__to, const char __user *__from, long __len)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, %2\n\t"
+                "move\t$6, %3\n\t"
+                __MODULE_JAL(__strncpy_from_user_nocheck_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (__to), "r" (__from), "r" (__len)
+                : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+
+        return res;
+}
+
+/*
+ * strncpy_from_user: - Copy a NUL terminated string from userspace.
+ * @dst:   Destination address, in kernel space.  This buffer must be at
+ *         least @count bytes long.
+ * @src:   Source address, in user space.
+ * @count: Maximum number of bytes to copy, including the trailing NUL.
+ *
+ * Copies a NUL-terminated string from userspace to kernel space.
+ *
+ * On success, returns the length of the string (not including the trailing
+ * NUL).
+ *
+ * If access to userspace fails, returns -EFAULT (some data may have been
+ * copied).
+ *
+ * If @count is smaller than the length of the string, copies @count bytes
+ * and returns @count.
+ */
+static inline long
+strncpy_from_user(char *__to, const char __user *__from, long __len)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, %2\n\t"
+                "move\t$6, %3\n\t"
+                __MODULE_JAL(__strncpy_from_user_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (__to), "r" (__from), "r" (__len)
+                : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
+
+        return res;
+}
+
+/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
+static inline long __strlen_user(const char __user *s)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                __MODULE_JAL(__strlen_user_nocheck_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (s)
+                : "$2", "$4", __UA_t0, "$31");
+
+        return res;
+}
+
+/*
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ *
+ * If there is a limit on the length of a valid string, you may wish to
+ * consider using strnlen_user() instead.
+ */
+static inline long strlen_user(const char __user *s)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                __MODULE_JAL(__strlen_user_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (s)
+                : "$2", "$4", __UA_t0, "$31");
+
+        return res;
+}
+
+/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
+static inline long __strnlen_user(const char __user *s, long n)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, %2\n\t"
+                __MODULE_JAL(__strnlen_user_nocheck_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (s), "r" (n)
+                : "$2", "$4", "$5", __UA_t0, "$31");
+
+        return res;
+}
+
+/*
+ * strlen_user: - Get the size of a string in user space.
+ * @str: The string to measure.
+ *
+ * Context: User context only.  This function may sleep.
+ *
+ * Get the size of a NUL-terminated string in user space.
+ *
+ * Returns the size of the string INCLUDING the terminating NUL.
+ * On exception, returns 0.
+ *
+ * If there is a limit on the length of a valid string, you may wish to
+ * consider using strnlen_user() instead.
+ */
+static inline long strnlen_user(const char __user *s, long n)
+{
+        long res;
+
+        might_sleep();
+        __asm__ __volatile__(
+                "move\t$4, %1\n\t"
+                "move\t$5, %2\n\t"
+                __MODULE_JAL(__strnlen_user_asm)
+                "move\t%0, $2"
+                : "=r" (res)
+                : "r" (s), "r" (n)
+                : "$2", "$4", "$5", __UA_t0, "$31");
+
+        return res;
+}
+
+struct exception_table_entry
+{
+        unsigned long insn;
+        unsigned long nextinsn;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+#endif /* _ASM_UACCESS_H */
diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h
new file mode 100644
index 000000000000..8a4b20e88b81
--- /dev/null
+++ b/arch/mips/include/asm/ucontext.h
@@ -0,0 +1,21 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Low level exception handling
+ *
+ * Copyright (C) 1998, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_UCONTEXT_H
+#define _ASM_UCONTEXT_H
+
+struct ucontext {
+        unsigned long     uc_flags;
+        struct ucontext  *uc_link;
+        stack_t           uc_stack;
+        struct sigcontext uc_mcontext;
+        sigset_t          uc_sigmask;   /* mask last for extensibility */
+};
+
+#endif /* _ASM_UCONTEXT_H */
diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h
new file mode 100644
index 000000000000..792404948571
--- /dev/null
+++ b/arch/mips/include/asm/unaligned.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_MIPS_UNALIGNED_H
+#define _ASM_MIPS_UNALIGNED_H
+
+#include <linux/compiler.h>
+#if defined(__MIPSEB__)
+# include <linux/unaligned/be_struct.h>
+# include <linux/unaligned/le_byteshift.h>
+# include <linux/unaligned/generic.h>
+# define get_unaligned  __get_unaligned_be
+# define put_unaligned  __put_unaligned_be
+#elif defined(__MIPSEL__)
+# include <linux/unaligned/le_struct.h>
+# include <linux/unaligned/be_byteshift.h>
+# include <linux/unaligned/generic.h>
+# define get_unaligned  __get_unaligned_le
+# define put_unaligned  __put_unaligned_le
+#else
+#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#endif /* _ASM_MIPS_UNALIGNED_H */
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
new file mode 100644
index 000000000000..a73e1531e151
--- /dev/null
+++ b/arch/mips/include/asm/unistd.h
@@ -0,0 +1,1037 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
+ * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
+ */
+#ifndef _ASM_UNISTD_H
+#define _ASM_UNISTD_H
+
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Linux o32 style syscalls are in the range from 4000 to 4999.
+ */
+#define __NR_Linux                      4000
+#define __NR_syscall                    (__NR_Linux +   0)
+#define __NR_exit                       (__NR_Linux +   1)
+#define __NR_fork                       (__NR_Linux +   2)
+#define __NR_read                       (__NR_Linux +   3)
+#define __NR_write                      (__NR_Linux +   4)
+#define __NR_open                       (__NR_Linux +   5)
+#define __NR_close                      (__NR_Linux +   6)
+#define __NR_waitpid                    (__NR_Linux +   7)
+#define __NR_creat                      (__NR_Linux +   8)
+#define __NR_link                       (__NR_Linux +   9)
+#define __NR_unlink                     (__NR_Linux +  10)
+#define __NR_execve                     (__NR_Linux +  11)
+#define __NR_chdir                      (__NR_Linux +  12)
+#define __NR_time                       (__NR_Linux +  13)
+#define __NR_mknod                      (__NR_Linux +  14)
+#define __NR_chmod                      (__NR_Linux +  15)
+#define __NR_lchown                     (__NR_Linux +  16)
+#define __NR_break                      (__NR_Linux +  17)
+#define __NR_unused18                   (__NR_Linux +  18)
+#define __NR_lseek                      (__NR_Linux +  19)
+#define __NR_getpid                     (__NR_Linux +  20)
+#define __NR_mount                      (__NR_Linux +  21)
+#define __NR_umount                     (__NR_Linux +  22)
+#define __NR_setuid                     (__NR_Linux +  23)
+#define __NR_getuid                     (__NR_Linux +  24)
+#define __NR_stime                      (__NR_Linux +  25)
+#define __NR_ptrace                     (__NR_Linux +  26)
+#define __NR_alarm                      (__NR_Linux +  27)
+#define __NR_unused28                   (__NR_Linux +  28)
+#define __NR_pause                      (__NR_Linux +  29)
+#define __NR_utime                      (__NR_Linux +  30)
+#define __NR_stty                       (__NR_Linux +  31)
+#define __NR_gtty                       (__NR_Linux +  32)
+#define __NR_access                     (__NR_Linux +  33)
+#define __NR_nice                       (__NR_Linux +  34)
+#define __NR_ftime                      (__NR_Linux +  35)
+#define __NR_sync                       (__NR_Linux +  36)
+#define __NR_kill                       (__NR_Linux +  37)
+#define __NR_rename                     (__NR_Linux +  38)
+#define __NR_mkdir                      (__NR_Linux +  39)
+#define __NR_rmdir                      (__NR_Linux +  40)
+#define __NR_dup                        (__NR_Linux +  41)
+#define __NR_pipe                       (__NR_Linux +  42)
+#define __NR_times                      (__NR_Linux +  43)
+#define __NR_prof                       (__NR_Linux +  44)
+#define __NR_brk                        (__NR_Linux +  45)
+#define __NR_setgid                     (__NR_Linux +  46)
+#define __NR_getgid                     (__NR_Linux +  47)
+#define __NR_signal                     (__NR_Linux +  48)
+#define __NR_geteuid                    (__NR_Linux +  49)
+#define __NR_getegid                    (__NR_Linux +  50)
+#define __NR_acct                       (__NR_Linux +  51)
+#define __NR_umount2                    (__NR_Linux +  52)
+#define __NR_lock                       (__NR_Linux +  53)
+#define __NR_ioctl                      (__NR_Linux +  54)
+#define __NR_fcntl                      (__NR_Linux +  55)
+#define __NR_mpx                        (__NR_Linux +  56)
+#define __NR_setpgid                    (__NR_Linux +  57)
+#define __NR_ulimit                     (__NR_Linux +  58)
+#define __NR_unused59                   (__NR_Linux +  59)
+#define __NR_umask                      (__NR_Linux +  60)
+#define __NR_chroot                     (__NR_Linux +  61)
+#define __NR_ustat                      (__NR_Linux +  62)
+#define __NR_dup2                       (__NR_Linux +  63)
+#define __NR_getppid                    (__NR_Linux +  64)
+#define __NR_getpgrp                    (__NR_Linux +  65)
+#define __NR_setsid                     (__NR_Linux +  66)
+#define __NR_sigaction                  (__NR_Linux +  67)
+#define __NR_sgetmask                   (__NR_Linux +  68)
+#define __NR_ssetmask                   (__NR_Linux +  69)
+#define __NR_setreuid                   (__NR_Linux +  70)
+#define __NR_setregid                   (__NR_Linux +  71)
+#define __NR_sigsuspend                 (__NR_Linux +  72)
+#define __NR_sigpending                 (__NR_Linux +  73)
+#define __NR_sethostname                (__NR_Linux +  74)
+#define __NR_setrlimit                  (__NR_Linux +  75)
+#define __NR_getrlimit                  (__NR_Linux +  76)
+#define __NR_getrusage                  (__NR_Linux +  77)
+#define __NR_gettimeofday               (__NR_Linux +  78)
+#define __NR_settimeofday               (__NR_Linux +  79)
+#define __NR_getgroups                  (__NR_Linux +  80)
+#define __NR_setgroups                  (__NR_Linux +  81)
+#define __NR_reserved82                 (__NR_Linux +  82)
+#define __NR_symlink                    (__NR_Linux +  83)
+#define __NR_unused84                   (__NR_Linux +  84)
+#define __NR_readlink                   (__NR_Linux +  85)
+#define __NR_uselib                     (__NR_Linux +  86)
+#define __NR_swapon                     (__NR_Linux +  87)
+#define __NR_reboot                     (__NR_Linux +  88)
+#define __NR_readdir                    (__NR_Linux +  89)
+#define __NR_mmap                       (__NR_Linux +  90)
+#define __NR_munmap                     (__NR_Linux +  91)
+#define __NR_truncate                   (__NR_Linux +  92)
+#define __NR_ftruncate                  (__NR_Linux +  93)
+#define __NR_fchmod                     (__NR_Linux +  94)
+#define __NR_fchown                     (__NR_Linux +  95)
+#define __NR_getpriority                (__NR_Linux +  96)
+#define __NR_setpriority                (__NR_Linux +  97)
+#define __NR_profil                     (__NR_Linux +  98)
+#define __NR_statfs                     (__NR_Linux +  99)
+#define __NR_fstatfs                    (__NR_Linux + 100)
+#define __NR_ioperm                     (__NR_Linux + 101)
+#define __NR_socketcall                 (__NR_Linux + 102)
+#define __NR_syslog                     (__NR_Linux + 103)
+#define __NR_setitimer                  (__NR_Linux + 104)
+#define __NR_getitimer                  (__NR_Linux + 105)
+#define __NR_stat                       (__NR_Linux + 106)
+#define __NR_lstat                      (__NR_Linux + 107)
+#define __NR_fstat                      (__NR_Linux + 108)
+#define __NR_unused109                  (__NR_Linux + 109)
+#define __NR_iopl                       (__NR_Linux + 110)
+#define __NR_vhangup                    (__NR_Linux + 111)
+#define __NR_idle                       (__NR_Linux + 112)
+#define __NR_vm86                       (__NR_Linux + 113)
+#define __NR_wait4                      (__NR_Linux + 114)
+#define __NR_swapoff                    (__NR_Linux + 115)
+#define __NR_sysinfo                    (__NR_Linux + 116)
+#define __NR_ipc                        (__NR_Linux + 117)
+#define __NR_fsync                      (__NR_Linux + 118)
+#define __NR_sigreturn                  (__NR_Linux + 119)
+#define __NR_clone                      (__NR_Linux + 120)
+#define __NR_setdomainname              (__NR_Linux + 121)
+#define __NR_uname                      (__NR_Linux + 122)
+#define __NR_modify_ldt                 (__NR_Linux + 123)
+#define __NR_adjtimex                   (__NR_Linux + 124)
+#define __NR_mprotect                   (__NR_Linux + 125)
+#define __NR_sigprocmask                (__NR_Linux + 126)
+#define __NR_create_module              (__NR_Linux + 127)
+#define __NR_init_module                (__NR_Linux + 128)
+#define __NR_delete_module              (__NR_Linux + 129)
+#define __NR_get_kernel_syms            (__NR_Linux + 130)
+#define __NR_quotactl                   (__NR_Linux + 131)
+#define __NR_getpgid                    (__NR_Linux + 132)
+#define __NR_fchdir                     (__NR_Linux + 133)
+#define __NR_bdflush                    (__NR_Linux + 134)
+#define __NR_sysfs                      (__NR_Linux + 135)
+#define __NR_personality                (__NR_Linux + 136)
+#define __NR_afs_syscall                (__NR_Linux + 137) /* Syscall for Andrew File System */
+#define __NR_setfsuid                   (__NR_Linux + 138)
+#define __NR_setfsgid                   (__NR_Linux + 139)
+#define __NR__llseek                    (__NR_Linux + 140)
+#define __NR_getdents                   (__NR_Linux + 141)
+#define __NR__newselect                 (__NR_Linux + 142)
+#define __NR_flock                      (__NR_Linux + 143)
+#define __NR_msync                      (__NR_Linux + 144)
+#define __NR_readv                      (__NR_Linux + 145)
+#define __NR_writev                     (__NR_Linux + 146)
+#define __NR_cacheflush                 (__NR_Linux + 147)
+#define __NR_cachectl                   (__NR_Linux + 148)
+#define __NR_sysmips                    (__NR_Linux + 149)
+#define __NR_unused150                  (__NR_Linux + 150)
+#define __NR_getsid                     (__NR_Linux + 151)
+#define __NR_fdatasync                  (__NR_Linux + 152)
+#define __NR__sysctl                    (__NR_Linux + 153)
+#define __NR_mlock                      (__NR_Linux + 154)
+#define __NR_munlock                    (__NR_Linux + 155)
+#define __NR_mlockall                   (__NR_Linux + 156)
+#define __NR_munlockall                 (__NR_Linux + 157)
+#define __NR_sched_setparam             (__NR_Linux + 158)
+#define __NR_sched_getparam             (__NR_Linux + 159)
+#define __NR_sched_setscheduler         (__NR_Linux + 160)
+#define __NR_sched_getscheduler         (__NR_Linux + 161)
+#define __NR_sched_yield                (__NR_Linux + 162)
+#define __NR_sched_get_priority_max     (__NR_Linux + 163)
+#define __NR_sched_get_priority_min     (__NR_Linux + 164)
+#define __NR_sched_rr_get_interval      (__NR_Linux + 165)
+#define __NR_nanosleep                  (__NR_Linux + 166)
+#define __NR_mremap                     (__NR_Linux + 167)
+#define __NR_accept                     (__NR_Linux + 168)
+#define __NR_bind                       (__NR_Linux + 169)
+#define __NR_connect                    (__NR_Linux + 170)
+#define __NR_getpeername                (__NR_Linux + 171)
+#define __NR_getsockname                (__NR_Linux + 172)
+#define __NR_getsockopt                 (__NR_Linux + 173)
+#define __NR_listen                     (__NR_Linux + 174)
+#define __NR_recv                       (__NR_Linux + 175)
+#define __NR_recvfrom                   (__NR_Linux + 176)
+#define __NR_recvmsg                    (__NR_Linux + 177)
+#define __NR_send                       (__NR_Linux + 178)
+#define __NR_sendmsg                    (__NR_Linux + 179)
+#define __NR_sendto                     (__NR_Linux + 180)
+#define __NR_setsockopt                 (__NR_Linux + 181)
+#define __NR_shutdown                   (__NR_Linux + 182)
+#define __NR_socket                     (__NR_Linux + 183)
+#define __NR_socketpair                 (__NR_Linux + 184)
+#define __NR_setresuid                  (__NR_Linux + 185)
+#define __NR_getresuid                  (__NR_Linux + 186)
+#define __NR_query_module               (__NR_Linux + 187)
+#define __NR_poll                       (__NR_Linux + 188)
+#define __NR_nfsservctl                 (__NR_Linux + 189)
+#define __NR_setresgid                  (__NR_Linux + 190)
+#define __NR_getresgid                  (__NR_Linux + 191)
+#define __NR_prctl                      (__NR_Linux + 192)
+#define __NR_rt_sigreturn               (__NR_Linux + 193)
+#define __NR_rt_sigaction               (__NR_Linux + 194)
+#define __NR_rt_sigprocmask             (__NR_Linux + 195)
+#define __NR_rt_sigpending              (__NR_Linux + 196)
+#define __NR_rt_sigtimedwait            (__NR_Linux + 197)
+#define __NR_rt_sigqueueinfo            (__NR_Linux + 198)
+#define __NR_rt_sigsuspend              (__NR_Linux + 199)
+#define __NR_pread64                    (__NR_Linux + 200)
+#define __NR_pwrite64                   (__NR_Linux + 201)
+#define __NR_chown                      (__NR_Linux + 202)
+#define __NR_getcwd                     (__NR_Linux + 203)
+#define __NR_capget                     (__NR_Linux + 204)
+#define __NR_capset                     (__NR_Linux + 205)
+#define __NR_sigaltstack                (__NR_Linux + 206)
+#define __NR_sendfile                   (__NR_Linux + 207)
+#define __NR_getpmsg                    (__NR_Linux + 208)
+#define __NR_putpmsg                    (__NR_Linux + 209)
+#define __NR_mmap2                      (__NR_Linux + 210)
+#define __NR_truncate64                 (__NR_Linux + 211)
+#define __NR_ftruncate64                (__NR_Linux + 212)
+#define __NR_stat64                     (__NR_Linux + 213)
+#define __NR_lstat64                    (__NR_Linux + 214)
+#define __NR_fstat64                    (__NR_Linux + 215)
+#define __NR_pivot_root                 (__NR_Linux + 216)
+#define __NR_mincore                    (__NR_Linux + 217)
+#define __NR_madvise                    (__NR_Linux + 218)
+#define __NR_getdents64                 (__NR_Linux + 219)
+#define __NR_fcntl64                    (__NR_Linux + 220)
+#define __NR_reserved221                (__NR_Linux + 221)
+#define __NR_gettid                     (__NR_Linux + 222)
+#define __NR_readahead                  (__NR_Linux + 223)
+#define __NR_setxattr                   (__NR_Linux + 224)
+#define __NR_lsetxattr                  (__NR_Linux + 225)
+#define __NR_fsetxattr                  (__NR_Linux + 226)
+#define __NR_getxattr                   (__NR_Linux + 227)
+#define __NR_lgetxattr                  (__NR_Linux + 228)
+#define __NR_fgetxattr                  (__NR_Linux + 229)
+#define __NR_listxattr                  (__NR_Linux + 230)
+#define __NR_llistxattr                 (__NR_Linux + 231)
+#define __NR_flistxattr                 (__NR_Linux + 232)
+#define __NR_removexattr                (__NR_Linux + 233)
+#define __NR_lremovexattr               (__NR_Linux + 234)
+#define __NR_fremovexattr               (__NR_Linux + 235)
+#define __NR_tkill                      (__NR_Linux + 236)
+#define __NR_sendfile64                 (__NR_Linux + 237)
+#define __NR_futex                      (__NR_Linux + 238)
+#define __NR_sched_setaffinity          (__NR_Linux + 239)
+#define __NR_sched_getaffinity          (__NR_Linux + 240)
+#define __NR_io_setup                   (__NR_Linux + 241)
+#define __NR_io_destroy                 (__NR_Linux + 242)
+#define __NR_io_getevents               (__NR_Linux + 243)
+#define __NR_io_submit                  (__NR_Linux + 244)
+#define __NR_io_cancel                  (__NR_Linux + 245)
+#define __NR_exit_group                 (__NR_Linux + 246)
+#define __NR_lookup_dcookie             (__NR_Linux + 247)
+#define __NR_epoll_create               (__NR_Linux + 248)
+#define __NR_epoll_ctl                  (__NR_Linux + 249)
+#define __NR_epoll_wait                 (__NR_Linux + 250)
+#define __NR_remap_file_pages           (__NR_Linux + 251)
+#define __NR_set_tid_address            (__NR_Linux + 252)
+#define __NR_restart_syscall            (__NR_Linux + 253)
+#define __NR_fadvise64                  (__NR_Linux + 254)
+#define __NR_statfs64                   (__NR_Linux + 255)
+#define __NR_fstatfs64                  (__NR_Linux + 256)
+#define __NR_timer_create               (__NR_Linux + 257)
+#define __NR_timer_settime              (__NR_Linux + 258)
+#define __NR_timer_gettime              (__NR_Linux + 259)
+#define __NR_timer_getoverrun           (__NR_Linux + 260)
+#define __NR_timer_delete               (__NR_Linux + 261)
+#define __NR_clock_settime              (__NR_Linux + 262)
+#define __NR_clock_gettime              (__NR_Linux + 263)
+#define __NR_clock_getres               (__NR_Linux + 264)
+#define __NR_clock_nanosleep            (__NR_Linux + 265)
+#define __NR_tgkill                     (__NR_Linux + 266)
+#define __NR_utimes                     (__NR_Linux + 267)
+#define __NR_mbind                      (__NR_Linux + 268)
+#define __NR_get_mempolicy              (__NR_Linux + 269)
+#define __NR_set_mempolicy              (__NR_Linux + 270)
+#define __NR_mq_open                    (__NR_Linux + 271)
+#define __NR_mq_unlink                  (__NR_Linux + 272)
+#define __NR_mq_timedsend               (__NR_Linux + 273)
+#define __NR_mq_timedreceive            (__NR_Linux + 274)
+#define __NR_mq_notify                  (__NR_Linux + 275)
+#define __NR_mq_getsetattr              (__NR_Linux + 276)
+#define __NR_vserver                    (__NR_Linux + 277)
+#define __NR_waitid                     (__NR_Linux + 278)
+/* #define __NR_sys_setaltroot          (__NR_Linux + 279) */
+#define __NR_add_key                    (__NR_Linux + 280)
+#define __NR_request_key                (__NR_Linux + 281)
+#define __NR_keyctl                     (__NR_Linux + 282)
+#define __NR_set_thread_area            (__NR_Linux + 283)
+#define __NR_inotify_init               (__NR_Linux + 284)
+#define __NR_inotify_add_watch          (__NR_Linux + 285)
+#define __NR_inotify_rm_watch           (__NR_Linux + 286)
+#define __NR_migrate_pages              (__NR_Linux + 287)
+#define __NR_openat                     (__NR_Linux + 288)
+#define __NR_mkdirat                    (__NR_Linux + 289)
+#define __NR_mknodat                    (__NR_Linux + 290)
+#define __NR_fchownat                   (__NR_Linux + 291)
+#define __NR_futimesat                  (__NR_Linux + 292)
+#define __NR_fstatat64                  (__NR_Linux + 293)
+#define __NR_unlinkat                   (__NR_Linux + 294)
+#define __NR_renameat                   (__NR_Linux + 295)
+#define __NR_linkat                     (__NR_Linux + 296)
+#define __NR_symlinkat                  (__NR_Linux + 297)
+#define __NR_readlinkat                 (__NR_Linux + 298)
+#define __NR_fchmodat                   (__NR_Linux + 299)
+#define __NR_faccessat                  (__NR_Linux + 300)
+#define __NR_pselect6                   (__NR_Linux + 301)
+#define __NR_ppoll                      (__NR_Linux + 302)
+#define __NR_unshare                    (__NR_Linux + 303)
+#define __NR_splice                     (__NR_Linux + 304)
+#define __NR_sync_file_range            (__NR_Linux + 305)
+#define __NR_tee                        (__NR_Linux + 306)
+#define __NR_vmsplice                   (__NR_Linux + 307)
+#define __NR_move_pages                 (__NR_Linux + 308)
+#define __NR_set_robust_list            (__NR_Linux + 309)
+#define __NR_get_robust_list            (__NR_Linux + 310)
+#define __NR_kexec_load                 (__NR_Linux + 311)
+#define __NR_getcpu                     (__NR_Linux + 312)
+#define __NR_epoll_pwait                (__NR_Linux + 313)
+#define __NR_ioprio_set                 (__NR_Linux + 314)
+#define __NR_ioprio_get                 (__NR_Linux + 315)
+#define __NR_utimensat                  (__NR_Linux + 316)
+#define __NR_signalfd                   (__NR_Linux + 317)
+#define __NR_timerfd                    (__NR_Linux + 318)
+#define __NR_eventfd                    (__NR_Linux + 319)
+#define __NR_fallocate                  (__NR_Linux + 320)
+#define __NR_timerfd_create             (__NR_Linux + 321)
+#define __NR_timerfd_gettime            (__NR_Linux + 322)
+#define __NR_timerfd_settime            (__NR_Linux + 323)
+#define __NR_signalfd4                  (__NR_Linux + 324)
+#define __NR_eventfd2                   (__NR_Linux + 325)
+#define __NR_epoll_create1              (__NR_Linux + 326)
+#define __NR_dup3                       (__NR_Linux + 327)
+#define __NR_pipe2                      (__NR_Linux + 328)
+#define __NR_inotify_init1              (__NR_Linux + 329)
+
+/*
+ * Offset of the last Linux o32 flavoured syscall
+ */
+#define __NR_Linux_syscalls             329
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#define __NR_O32_Linux                  4000
+#define __NR_O32_Linux_syscalls         329
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+/*
+ * Linux 64-bit syscalls are in the range from 5000 to 5999.
+ */
+#define __NR_Linux                      5000
+#define __NR_read                       (__NR_Linux +   0)
+#define __NR_write                      (__NR_Linux +   1)
+#define __NR_open                       (__NR_Linux +   2)
+#define __NR_close                      (__NR_Linux +   3)
+#define __NR_stat                       (__NR_Linux +   4)
+#define __NR_fstat                      (__NR_Linux +   5)
+#define __NR_lstat                      (__NR_Linux +   6)
+#define __NR_poll                       (__NR_Linux +   7)
+#define __NR_lseek                      (__NR_Linux +   8)
+#define __NR_mmap                       (__NR_Linux +   9)
+#define __NR_mprotect                   (__NR_Linux +  10)
+#define __NR_munmap                     (__NR_Linux +  11)
+#define __NR_brk                        (__NR_Linux +  12)
+#define __NR_rt_sigaction               (__NR_Linux +  13)
+#define __NR_rt_sigprocmask             (__NR_Linux +  14)
+#define __NR_ioctl                      (__NR_Linux +  15)
+#define __NR_pread64                    (__NR_Linux +  16)
+#define __NR_pwrite64                   (__NR_Linux +  17)
+#define __NR_readv                      (__NR_Linux +  18)
+#define __NR_writev                     (__NR_Linux +  19)
+#define __NR_access                     (__NR_Linux +  20)
+#define __NR_pipe                       (__NR_Linux +  21)
+#define __NR__newselect                 (__NR_Linux +  22)
+#define __NR_sched_yield                (__NR_Linux +  23)
+#define __NR_mremap                     (__NR_Linux +  24)
+#define __NR_msync                      (__NR_Linux +  25)
+#define __NR_mincore                    (__NR_Linux +  26)
+#define __NR_madvise                    (__NR_Linux +  27)
+#define __NR_shmget                     (__NR_Linux +  28)
+#define __NR_shmat                      (__NR_Linux +  29)
+#define __NR_shmctl                     (__NR_Linux +  30)
+#define __NR_dup                        (__NR_Linux +  31)
+#define __NR_dup2                       (__NR_Linux +  32)
+#define __NR_pause                      (__NR_Linux +  33)
+#define __NR_nanosleep                  (__NR_Linux +  34)
+#define __NR_getitimer                  (__NR_Linux +  35)
+#define __NR_setitimer                  (__NR_Linux +  36)
+#define __NR_alarm                      (__NR_Linux +  37)
+#define __NR_getpid                     (__NR_Linux +  38)
+#define __NR_sendfile                   (__NR_Linux +  39)
+#define __NR_socket                     (__NR_Linux +  40)
+#define __NR_connect                    (__NR_Linux +  41)
+#define __NR_accept                     (__NR_Linux +  42)
+#define __NR_sendto                     (__NR_Linux +  43)
+#define __NR_recvfrom                   (__NR_Linux +  44)
+#define __NR_sendmsg                    (__NR_Linux +  45)
+#define __NR_recvmsg                    (__NR_Linux +  46)
+#define __NR_shutdown                   (__NR_Linux +  47)
+#define __NR_bind                       (__NR_Linux +  48)
+#define __NR_listen                     (__NR_Linux +  49)
+#define __NR_getsockname                (__NR_Linux +  50)
+#define __NR_getpeername                (__NR_Linux +  51)
+#define __NR_socketpair                 (__NR_Linux +  52)
+#define __NR_setsockopt                 (__NR_Linux +  53)
+#define __NR_getsockopt                 (__NR_Linux +  54)
+#define __NR_clone                      (__NR_Linux +  55)
+#define __NR_fork                       (__NR_Linux +  56)
+#define __NR_execve                     (__NR_Linux +  57)
+#define __NR_exit                       (__NR_Linux +  58)
+#define __NR_wait4                      (__NR_Linux +  59)
+#define __NR_kill                       (__NR_Linux +  60)
+#define __NR_uname                      (__NR_Linux +  61)
+#define __NR_semget                     (__NR_Linux +  62)
+#define __NR_semop                      (__NR_Linux +  63)
+#define __NR_semctl                     (__NR_Linux +  64)
+#define __NR_shmdt                      (__NR_Linux +  65)
+#define __NR_msgget                     (__NR_Linux +  66)
+#define __NR_msgsnd                     (__NR_Linux +  67)
+#define __NR_msgrcv                     (__NR_Linux +  68)
+#define __NR_msgctl                     (__NR_Linux +  69)
+#define __NR_fcntl                      (__NR_Linux +  70)
+#define __NR_flock                      (__NR_Linux +  71)
+#define __NR_fsync                      (__NR_Linux +  72)
+#define __NR_fdatasync                  (__NR_Linux +  73)
+#define __NR_truncate                   (__NR_Linux +  74)
+#define __NR_ftruncate                  (__NR_Linux +  75)
+#define __NR_getdents                   (__NR_Linux +  76)
+#define __NR_getcwd                     (__NR_Linux +  77)
+#define __NR_chdir                      (__NR_Linux +  78)
+#define __NR_fchdir                     (__NR_Linux +  79)
+#define __NR_rename                     (__NR_Linux +  80)
+#define __NR_mkdir                      (__NR_Linux +  81)
+#define __NR_rmdir                      (__NR_Linux +  82)
+#define __NR_creat                      (__NR_Linux +  83)
+#define __NR_link                       (__NR_Linux +  84)
+#define __NR_unlink                     (__NR_Linux +  85)
+#define __NR_symlink                    (__NR_Linux +  86)
+#define __NR_readlink                   (__NR_Linux +  87)
+#define __NR_chmod                      (__NR_Linux +  88)
+#define __NR_fchmod                     (__NR_Linux +  89)
+#define __NR_chown                      (__NR_Linux +  90)
+#define __NR_fchown                     (__NR_Linux +  91)
+#define __NR_lchown                     (__NR_Linux +  92)
+#define __NR_umask                      (__NR_Linux +  93)
+#define __NR_gettimeofday               (__NR_Linux +  94)
+#define __NR_getrlimit                  (__NR_Linux +  95)
+#define __NR_getrusage                  (__NR_Linux +  96)
+#define __NR_sysinfo                    (__NR_Linux +  97)
+#define __NR_times                      (__NR_Linux +  98)
+#define __NR_ptrace                     (__NR_Linux +  99)
+#define __NR_getuid                     (__NR_Linux + 100)
+#define __NR_syslog                     (__NR_Linux + 101)
+#define __NR_getgid                     (__NR_Linux + 102)
+#define __NR_setuid                     (__NR_Linux + 103)
+#define __NR_setgid                     (__NR_Linux + 104)
+#define __NR_geteuid                    (__NR_Linux + 105)
+#define __NR_getegid                    (__NR_Linux + 106)
+#define __NR_setpgid                    (__NR_Linux + 107)
+#define __NR_getppid                    (__NR_Linux + 108)
+#define __NR_getpgrp                    (__NR_Linux + 109)
+#define __NR_setsid                     (__NR_Linux + 110)
+#define __NR_setreuid                   (__NR_Linux + 111)
+#define __NR_setregid                   (__NR_Linux + 112)
+#define __NR_getgroups                  (__NR_Linux + 113)
+#define __NR_setgroups                  (__NR_Linux + 114)
+#define __NR_setresuid                  (__NR_Linux + 115)
+#define __NR_getresuid                  (__NR_Linux + 116)
+#define __NR_setresgid                  (__NR_Linux + 117)
+#define __NR_getresgid                  (__NR_Linux + 118)
+#define __NR_getpgid                    (__NR_Linux + 119)
+#define __NR_setfsuid                   (__NR_Linux + 120)
+#define __NR_setfsgid                   (__NR_Linux + 121)
+#define __NR_getsid                     (__NR_Linux + 122)
+#define __NR_capget                     (__NR_Linux + 123)
+#define __NR_capset                     (__NR_Linux + 124)
+#define __NR_rt_sigpending              (__NR_Linux + 125)
+#define __NR_rt_sigtimedwait            (__NR_Linux + 126)
+#define __NR_rt_sigqueueinfo            (__NR_Linux + 127)
+#define __NR_rt_sigsuspend              (__NR_Linux + 128)
+#define __NR_sigaltstack                (__NR_Linux + 129)
+#define __NR_utime                      (__NR_Linux + 130)
+#define __NR_mknod                      (__NR_Linux + 131)
+#define __NR_personality                (__NR_Linux + 132)
+#define __NR_ustat                      (__NR_Linux + 133)
+#define __NR_statfs                     (__NR_Linux + 134)
+#define __NR_fstatfs                    (__NR_Linux + 135)
+#define __NR_sysfs                      (__NR_Linux + 136)
+#define __NR_getpriority                (__NR_Linux + 137)
+#define __NR_setpriority                (__NR_Linux + 138)
+#define __NR_sched_setparam             (__NR_Linux + 139)
+#define __NR_sched_getparam             (__NR_Linux + 140)
+#define __NR_sched_setscheduler         (__NR_Linux + 141)
+#define __NR_sched_getscheduler         (__NR_Linux + 142)
+#define __NR_sched_get_priority_max     (__NR_Linux + 143)
+#define __NR_sched_get_priority_min     (__NR_Linux + 144)
+#define __NR_sched_rr_get_interval      (__NR_Linux + 145)
+#define __NR_mlock                      (__NR_Linux + 146)
+#define __NR_munlock                    (__NR_Linux + 147)
+#define __NR_mlockall                   (__NR_Linux + 148)
+#define __NR_munlockall                 (__NR_Linux + 149)
+#define __NR_vhangup                    (__NR_Linux + 150)
+#define __NR_pivot_root                 (__NR_Linux + 151)
+#define __NR__sysctl                    (__NR_Linux + 152)
+#define __NR_prctl                      (__NR_Linux + 153)
+#define __NR_adjtimex                   (__NR_Linux + 154)
+#define __NR_setrlimit                  (__NR_Linux + 155)
+#define __NR_chroot                     (__NR_Linux + 156)
+#define __NR_sync                       (__NR_Linux + 157)
+#define __NR_acct                       (__NR_Linux + 158)
+#define __NR_settimeofday               (__NR_Linux + 159)
+#define __NR_mount                      (__NR_Linux + 160)
+#define __NR_umount2                    (__NR_Linux + 161)
+#define __NR_swapon                     (__NR_Linux + 162)
+#define __NR_swapoff                    (__NR_Linux + 163)
+#define __NR_reboot                     (__NR_Linux + 164)
+#define __NR_sethostname                (__NR_Linux + 165)
+#define __NR_setdomainname              (__NR_Linux + 166)
+#define __NR_create_module              (__NR_Linux + 167)
+#define __NR_init_module                (__NR_Linux + 168)
+#define __NR_delete_module              (__NR_Linux + 169)
+#define __NR_get_kernel_syms            (__NR_Linux + 170)
+#define __NR_query_module               (__NR_Linux + 171)
+#define __NR_quotactl                   (__NR_Linux + 172)
+#define __NR_nfsservctl                 (__NR_Linux + 173)
+#define __NR_getpmsg                    (__NR_Linux + 174)
+#define __NR_putpmsg                    (__NR_Linux + 175)
+#define __NR_afs_syscall                (__NR_Linux + 176)
+#define __NR_reserved177                (__NR_Linux + 177)
+#define __NR_gettid                     (__NR_Linux + 178)
+#define __NR_readahead                  (__NR_Linux + 179)
+#define __NR_setxattr                   (__NR_Linux + 180)
+#define __NR_lsetxattr                  (__NR_Linux + 181)
+#define __NR_fsetxattr                  (__NR_Linux + 182)
+#define __NR_getxattr                   (__NR_Linux + 183)
+#define __NR_lgetxattr                  (__NR_Linux + 184)
+#define __NR_fgetxattr                  (__NR_Linux + 185)
+#define __NR_listxattr                  (__NR_Linux + 186)
+#define __NR_llistxattr                 (__NR_Linux + 187)
+#define __NR_flistxattr                 (__NR_Linux + 188)
+#define __NR_removexattr                (__NR_Linux + 189)
+#define __NR_lremovexattr               (__NR_Linux + 190)
+#define __NR_fremovexattr               (__NR_Linux + 191)
+#define __NR_tkill                      (__NR_Linux + 192)
+#define __NR_reserved193                (__NR_Linux + 193)
+#define __NR_futex                      (__NR_Linux + 194)
+#define __NR_sched_setaffinity          (__NR_Linux + 195)
+#define __NR_sched_getaffinity          (__NR_Linux + 196)
+#define __NR_cacheflush                 (__NR_Linux + 197)
+#define __NR_cachectl                   (__NR_Linux + 198)
+#define __NR_sysmips                    (__NR_Linux + 199)
+#define __NR_io_setup                   (__NR_Linux + 200)
+#define __NR_io_destroy                 (__NR_Linux + 201)
+#define __NR_io_getevents               (__NR_Linux + 202)
+#define __NR_io_submit                  (__NR_Linux + 203)
+#define __NR_io_cancel                  (__NR_Linux + 204)
+#define __NR_exit_group                 (__NR_Linux + 205)
+#define __NR_lookup_dcookie             (__NR_Linux + 206)
+#define __NR_epoll_create               (__NR_Linux + 207)
+#define __NR_epoll_ctl                  (__NR_Linux + 208)
+#define __NR_epoll_wait                 (__NR_Linux + 209)
+#define __NR_remap_file_pages           (__NR_Linux + 210)
+#define __NR_rt_sigreturn               (__NR_Linux + 211)
+#define __NR_set_tid_address            (__NR_Linux + 212)
+#define __NR_restart_syscall            (__NR_Linux + 213)
+#define __NR_semtimedop                 (__NR_Linux + 214)
+#define __NR_fadvise64                  (__NR_Linux + 215)
+#define __NR_timer_create               (__NR_Linux + 216)
+#define __NR_timer_settime              (__NR_Linux + 217)
+#define __NR_timer_gettime              (__NR_Linux + 218)
+#define __NR_timer_getoverrun           (__NR_Linux + 219)
+#define __NR_timer_delete               (__NR_Linux + 220)
+#define __NR_clock_settime              (__NR_Linux + 221)
+#define __NR_clock_gettime              (__NR_Linux + 222)
+#define __NR_clock_getres               (__NR_Linux + 223)
+#define __NR_clock_nanosleep            (__NR_Linux + 224)
+#define __NR_tgkill                     (__NR_Linux + 225)
+#define __NR_utimes                     (__NR_Linux + 226)
+#define __NR_mbind                      (__NR_Linux + 227)
+#define __NR_get_mempolicy              (__NR_Linux + 228)
+#define __NR_set_mempolicy              (__NR_Linux + 229)
+#define __NR_mq_open                    (__NR_Linux + 230)
+#define __NR_mq_unlink                  (__NR_Linux + 231)
+#define __NR_mq_timedsend               (__NR_Linux + 232)
+#define __NR_mq_timedreceive            (__NR_Linux + 233)
+#define __NR_mq_notify                  (__NR_Linux + 234)
+#define __NR_mq_getsetattr              (__NR_Linux + 235)
+#define __NR_vserver                    (__NR_Linux + 236)
+#define __NR_waitid                     (__NR_Linux + 237)
+/* #define __NR_sys_setaltroot          (__NR_Linux + 238) */
+#define __NR_add_key                    (__NR_Linux + 239)
+#define __NR_request_key                (__NR_Linux + 240)
+#define __NR_keyctl                     (__NR_Linux + 241)
+#define __NR_set_thread_area            (__NR_Linux + 242)
+#define __NR_inotify_init               (__NR_Linux + 243)
+#define __NR_inotify_add_watch          (__NR_Linux + 244)
+#define __NR_inotify_rm_watch           (__NR_Linux + 245)
+#define __NR_migrate_pages              (__NR_Linux + 246)
+#define __NR_openat                     (__NR_Linux + 247)
+#define __NR_mkdirat                    (__NR_Linux + 248)
+#define __NR_mknodat                    (__NR_Linux + 249)
+#define __NR_fchownat                   (__NR_Linux + 250)
+#define __NR_futimesat                  (__NR_Linux + 251)
+#define __NR_newfstatat                 (__NR_Linux + 252)
+#define __NR_unlinkat                   (__NR_Linux + 253)
+#define __NR_renameat                   (__NR_Linux + 254)
+#define __NR_linkat                     (__NR_Linux + 255)
+#define __NR_symlinkat                  (__NR_Linux + 256)
+#define __NR_readlinkat                 (__NR_Linux + 257)
+#define __NR_fchmodat                   (__NR_Linux + 258)
+#define __NR_faccessat                  (__NR_Linux + 259)
+#define __NR_pselect6                   (__NR_Linux + 260)
+#define __NR_ppoll                      (__NR_Linux + 261)
+#define __NR_unshare                    (__NR_Linux + 262)
+#define __NR_splice                     (__NR_Linux + 263)
+#define __NR_sync_file_range            (__NR_Linux + 264)
+#define __NR_tee                        (__NR_Linux + 265)
+#define __NR_vmsplice                   (__NR_Linux + 266)
+#define __NR_move_pages                 (__NR_Linux + 267)
+#define __NR_set_robust_list            (__NR_Linux + 268)
+#define __NR_get_robust_list            (__NR_Linux + 269)
+#define __NR_kexec_load                 (__NR_Linux + 270)
+#define __NR_getcpu                     (__NR_Linux + 271)
+#define __NR_epoll_pwait                (__NR_Linux + 272)
+#define __NR_ioprio_set                 (__NR_Linux + 273)
+#define __NR_ioprio_get                 (__NR_Linux + 274)
+#define __NR_utimensat                  (__NR_Linux + 275)
+#define __NR_signalfd                   (__NR_Linux + 276)
+#define __NR_timerfd                    (__NR_Linux + 277)
+#define __NR_eventfd                    (__NR_Linux + 278)
+#define __NR_fallocate                  (__NR_Linux + 279)
+#define __NR_timerfd_create             (__NR_Linux + 280)
+#define __NR_timerfd_gettime            (__NR_Linux + 281)
+#define __NR_timerfd_settime            (__NR_Linux + 282)
+#define __NR_signalfd4                  (__NR_Linux + 283)
+#define __NR_eventfd2                   (__NR_Linux + 284)
+#define __NR_epoll_create1              (__NR_Linux + 285)
+#define __NR_dup3                       (__NR_Linux + 286)
+#define __NR_pipe2                      (__NR_Linux + 287)
+#define __NR_inotify_init1              (__NR_Linux + 288)
+
+/*
+ * Offset of the last Linux 64-bit flavoured syscall
+ */
+#define __NR_Linux_syscalls             288
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#define __NR_64_Linux                   5000
+#define __NR_64_Linux_syscalls          288
+
+#if _MIPS_SIM == _MIPS_SIM_NABI32
+
+/*
+ * Linux N32 syscalls are in the range from 6000 to 6999.
+ */
+#define __NR_Linux                      6000
+#define __NR_read                       (__NR_Linux +   0)
+#define __NR_write                      (__NR_Linux +   1)
+#define __NR_open                       (__NR_Linux +   2)
+#define __NR_close                      (__NR_Linux +   3)
+#define __NR_stat                       (__NR_Linux +   4)
+#define __NR_fstat                      (__NR_Linux +   5)
+#define __NR_lstat                      (__NR_Linux +   6)
+#define __NR_poll                       (__NR_Linux +   7)
+#define __NR_lseek                      (__NR_Linux +   8)
+#define __NR_mmap                       (__NR_Linux +   9)
+#define __NR_mprotect                   (__NR_Linux +  10)
+#define __NR_munmap                     (__NR_Linux +  11)
+#define __NR_brk                        (__NR_Linux +  12)
+#define __NR_rt_sigaction               (__NR_Linux +  13)
+#define __NR_rt_sigprocmask             (__NR_Linux +  14)
+#define __NR_ioctl                      (__NR_Linux +  15)
+#define __NR_pread64                    (__NR_Linux +  16)
+#define __NR_pwrite64                   (__NR_Linux +  17)
+#define __NR_readv                      (__NR_Linux +  18)
+#define __NR_writev                     (__NR_Linux +  19)
+#define __NR_access                     (__NR_Linux +  20)
+#define __NR_pipe                       (__NR_Linux +  21)
+#define __NR__newselect                 (__NR_Linux +  22)
+#define __NR_sched_yield                (__NR_Linux +  23)
+#define __NR_mremap                     (__NR_Linux +  24)
+#define __NR_msync                      (__NR_Linux +  25)
+#define __NR_mincore                    (__NR_Linux +  26)
+#define __NR_madvise                    (__NR_Linux +  27)
+#define __NR_shmget                     (__NR_Linux +  28)
+#define __NR_shmat                      (__NR_Linux +  29)
+#define __NR_shmctl                     (__NR_Linux +  30)
+#define __NR_dup                        (__NR_Linux +  31)
+#define __NR_dup2                       (__NR_Linux +  32)
+#define __NR_pause                      (__NR_Linux +  33)
+#define __NR_nanosleep                  (__NR_Linux +  34)
+#define __NR_getitimer                  (__NR_Linux +  35)
+#define __NR_setitimer                  (__NR_Linux +  36)
+#define __NR_alarm                      (__NR_Linux +  37)
+#define __NR_getpid                     (__NR_Linux +  38)
+#define __NR_sendfile                   (__NR_Linux +  39)
+#define __NR_socket                     (__NR_Linux +  40)
+#define __NR_connect                    (__NR_Linux +  41)
+#define __NR_accept                     (__NR_Linux +  42)
+#define __NR_sendto                     (__NR_Linux +  43)
+#define __NR_recvfrom                   (__NR_Linux +  44)
+#define __NR_sendmsg                    (__NR_Linux +  45)
+#define __NR_recvmsg                    (__NR_Linux +  46)
+#define __NR_shutdown                   (__NR_Linux +  47)
+#define __NR_bind                       (__NR_Linux +  48)
+#define __NR_listen                     (__NR_Linux +  49)
+#define __NR_getsockname                (__NR_Linux +  50)
+#define __NR_getpeername                (__NR_Linux +  51)
+#define __NR_socketpair                 (__NR_Linux +  52)
+#define __NR_setsockopt                 (__NR_Linux +  53)
+#define __NR_getsockopt                 (__NR_Linux +  54)
+#define __NR_clone                      (__NR_Linux +  55)
+#define __NR_fork                       (__NR_Linux +  56)
+#define __NR_execve                     (__NR_Linux +  57)
+#define __NR_exit                       (__NR_Linux +  58)
+#define __NR_wait4                      (__NR_Linux +  59)
+#define __NR_kill                       (__NR_Linux +  60)
+#define __NR_uname                      (__NR_Linux +  61)
+#define __NR_semget                     (__NR_Linux +  62)
+#define __NR_semop                      (__NR_Linux +  63)
+#define __NR_semctl                     (__NR_Linux +  64)
+#define __NR_shmdt                      (__NR_Linux +  65)
+#define __NR_msgget                     (__NR_Linux +  66)
+#define __NR_msgsnd                     (__NR_Linux +  67)
+#define __NR_msgrcv                     (__NR_Linux +  68)
+#define __NR_msgctl                     (__NR_Linux +  69)
+#define __NR_fcntl                      (__NR_Linux +  70)
+#define __NR_flock                      (__NR_Linux +  71)
+#define __NR_fsync                      (__NR_Linux +  72)
+#define __NR_fdatasync                  (__NR_Linux +  73)
+#define __NR_truncate                   (__NR_Linux +  74)
+#define __NR_ftruncate                  (__NR_Linux +  75)
+#define __NR_getdents                   (__NR_Linux +  76)
+#define __NR_getcwd                     (__NR_Linux +  77)
+#define __NR_chdir                      (__NR_Linux +  78)
+#define __NR_fchdir                     (__NR_Linux +  79)
+#define __NR_rename                     (__NR_Linux +  80)
+#define __NR_mkdir                      (__NR_Linux +  81)
+#define __NR_rmdir                      (__NR_Linux +  82)
+#define __NR_creat                      (__NR_Linux +  83)
+#define __NR_link                       (__NR_Linux +  84)
+#define __NR_unlink                     (__NR_Linux +  85)
+#define __NR_symlink                    (__NR_Linux +  86)
+#define __NR_readlink                   (__NR_Linux +  87)
+#define __NR_chmod                      (__NR_Linux +  88)
+#define __NR_fchmod                     (__NR_Linux +  89)
+#define __NR_chown                      (__NR_Linux +  90)
+#define __NR_fchown                     (__NR_Linux +  91)
+#define __NR_lchown                     (__NR_Linux +  92)
+#define __NR_umask                      (__NR_Linux +  93)
+#define __NR_gettimeofday               (__NR_Linux +  94)
+#define __NR_getrlimit                  (__NR_Linux +  95)
+#define __NR_getrusage                  (__NR_Linux +  96)
+#define __NR_sysinfo                    (__NR_Linux +  97)
+#define __NR_times                      (__NR_Linux +  98)
+#define __NR_ptrace                     (__NR_Linux +  99)
+#define __NR_getuid                     (__NR_Linux + 100)
+#define __NR_syslog                     (__NR_Linux + 101)
+#define __NR_getgid                     (__NR_Linux + 102)
+#define __NR_setuid                     (__NR_Linux + 103)
+#define __NR_setgid                     (__NR_Linux + 104)
+#define __NR_geteuid                    (__NR_Linux + 105)
+#define __NR_getegid                    (__NR_Linux + 106)
+#define __NR_setpgid                    (__NR_Linux + 107)
+#define __NR_getppid                    (__NR_Linux + 108)
+#define __NR_getpgrp                    (__NR_Linux + 109)
+#define __NR_setsid                     (__NR_Linux + 110)
+#define __NR_setreuid                   (__NR_Linux + 111)
+#define __NR_setregid                   (__NR_Linux + 112)
+#define __NR_getgroups                  (__NR_Linux + 113)
+#define __NR_setgroups                  (__NR_Linux + 114)
+#define __NR_setresuid                  (__NR_Linux + 115)
+#define __NR_getresuid                  (__NR_Linux + 116)
+#define __NR_setresgid                  (__NR_Linux + 117)
+#define __NR_getresgid                  (__NR_Linux + 118)
+#define __NR_getpgid                    (__NR_Linux + 119)
+#define __NR_setfsuid                   (__NR_Linux + 120)
+#define __NR_setfsgid                   (__NR_Linux + 121)
+#define __NR_getsid                     (__NR_Linux + 122)
+#define __NR_capget                     (__NR_Linux + 123)
+#define __NR_capset                     (__NR_Linux + 124)
+#define __NR_rt_sigpending              (__NR_Linux + 125)
+#define __NR_rt_sigtimedwait            (__NR_Linux + 126)
+#define __NR_rt_sigqueueinfo            (__NR_Linux + 127)
+#define __NR_rt_sigsuspend              (__NR_Linux + 128)
+#define __NR_sigaltstack                (__NR_Linux + 129)
+#define __NR_utime                      (__NR_Linux + 130)
+#define __NR_mknod                      (__NR_Linux + 131)
+#define __NR_personality                (__NR_Linux + 132)
+#define __NR_ustat                      (__NR_Linux + 133)
+#define __NR_statfs                     (__NR_Linux + 134)
+#define __NR_fstatfs                    (__NR_Linux + 135)
+#define __NR_sysfs                      (__NR_Linux + 136)
+#define __NR_getpriority                (__NR_Linux + 137)
+#define __NR_setpriority                (__NR_Linux + 138)
+#define __NR_sched_setparam             (__NR_Linux + 139)
+#define __NR_sched_getparam             (__NR_Linux + 140)
+#define __NR_sched_setscheduler         (__NR_Linux + 141)
+#define __NR_sched_getscheduler         (__NR_Linux + 142)
+#define __NR_sched_get_priority_max     (__NR_Linux + 143)
+#define __NR_sched_get_priority_min     (__NR_Linux + 144)
+#define __NR_sched_rr_get_interval      (__NR_Linux + 145)
+#define __NR_mlock                      (__NR_Linux + 146)
+#define __NR_munlock                    (__NR_Linux + 147)
+#define __NR_mlockall                   (__NR_Linux + 148)
+#define __NR_munlockall                 (__NR_Linux + 149)
+#define __NR_vhangup                    (__NR_Linux + 150)
+#define __NR_pivot_root                 (__NR_Linux + 151)
+#define __NR__sysctl                    (__NR_Linux + 152)
+#define __NR_prctl                      (__NR_Linux + 153)
+#define __NR_adjtimex                   (__NR_Linux + 154)
+#define __NR_setrlimit                  (__NR_Linux + 155)
+#define __NR_chroot                     (__NR_Linux + 156)
+#define __NR_sync                       (__NR_Linux + 157)
+#define __NR_acct                       (__NR_Linux + 158)
+#define __NR_settimeofday               (__NR_Linux + 159)
+#define __NR_mount                      (__NR_Linux + 160)
+#define __NR_umount2                    (__NR_Linux + 161)
+#define __NR_swapon                     (__NR_Linux + 162)
+#define __NR_swapoff                    (__NR_Linux + 163)
+#define __NR_reboot                     (__NR_Linux + 164)
+#define __NR_sethostname                (__NR_Linux + 165)
+#define __NR_setdomainname              (__NR_Linux + 166)
+#define __NR_create_module              (__NR_Linux + 167)
+#define __NR_init_module                (__NR_Linux + 168)
+#define __NR_delete_module              (__NR_Linux + 169)
+#define __NR_get_kernel_syms            (__NR_Linux + 170)
+#define __NR_query_module               (__NR_Linux + 171)
+#define __NR_quotactl                   (__NR_Linux + 172)
+#define __NR_nfsservctl                 (__NR_Linux + 173)
+#define __NR_getpmsg                    (__NR_Linux + 174)
+#define __NR_putpmsg                    (__NR_Linux + 175)
+#define __NR_afs_syscall                (__NR_Linux + 176)
+#define __NR_reserved177                (__NR_Linux + 177)
+#define __NR_gettid                     (__NR_Linux + 178)
+#define __NR_readahead                  (__NR_Linux + 179)
+#define __NR_setxattr                   (__NR_Linux + 180)
+#define __NR_lsetxattr                  (__NR_Linux + 181)
+#define __NR_fsetxattr                  (__NR_Linux + 182)
+#define __NR_getxattr                   (__NR_Linux + 183)
+#define __NR_lgetxattr                  (__NR_Linux + 184)
+#define __NR_fgetxattr                  (__NR_Linux + 185)
+#define __NR_listxattr                  (__NR_Linux + 186)
+#define __NR_llistxattr                 (__NR_Linux + 187)
+#define __NR_flistxattr                 (__NR_Linux + 188)
+#define __NR_removexattr                (__NR_Linux + 189)
+#define __NR_lremovexattr               (__NR_Linux + 190)
+#define __NR_fremovexattr               (__NR_Linux + 191)
+#define __NR_tkill                      (__NR_Linux + 192)
+#define __NR_reserved193                (__NR_Linux + 193)
+#define __NR_futex                      (__NR_Linux + 194)
+#define __NR_sched_setaffinity          (__NR_Linux + 195)
+#define __NR_sched_getaffinity          (__NR_Linux + 196)
+#define __NR_cacheflush                 (__NR_Linux + 197)
+#define __NR_cachectl                   (__NR_Linux + 198)
+#define __NR_sysmips                    (__NR_Linux + 199)
+#define __NR_io_setup                   (__NR_Linux + 200)
+#define __NR_io_destroy                 (__NR_Linux + 201)
+#define __NR_io_getevents               (__NR_Linux + 202)
+#define __NR_io_submit                  (__NR_Linux + 203)
+#define __NR_io_cancel                  (__NR_Linux + 204)
+#define __NR_exit_group                 (__NR_Linux + 205)
+#define __NR_lookup_dcookie             (__NR_Linux + 206)
+#define __NR_epoll_create               (__NR_Linux + 207)
+#define __NR_epoll_ctl                  (__NR_Linux + 208)
+#define __NR_epoll_wait                 (__NR_Linux + 209)
+#define __NR_remap_file_pages           (__NR_Linux + 210)
+#define __NR_rt_sigreturn               (__NR_Linux + 211)
+#define __NR_fcntl64                    (__NR_Linux + 212)
+#define __NR_set_tid_address            (__NR_Linux + 213)
+#define __NR_restart_syscall            (__NR_Linux + 214)
+#define __NR_semtimedop                 (__NR_Linux + 215)
+#define __NR_fadvise64                  (__NR_Linux + 216)
+#define __NR_statfs64                   (__NR_Linux + 217)
+#define __NR_fstatfs64                  (__NR_Linux + 218)
+#define __NR_sendfile64                 (__NR_Linux + 219)
+#define __NR_timer_create               (__NR_Linux + 220)
+#define __NR_timer_settime              (__NR_Linux + 221)
+#define __NR_timer_gettime              (__NR_Linux + 222)
+#define __NR_timer_getoverrun           (__NR_Linux + 223)
+#define __NR_timer_delete               (__NR_Linux + 224)
+#define __NR_clock_settime              (__NR_Linux + 225)
+#define __NR_clock_gettime              (__NR_Linux + 226)
+#define __NR_clock_getres               (__NR_Linux + 227)
+#define __NR_clock_nanosleep            (__NR_Linux + 228)
+#define __NR_tgkill                     (__NR_Linux + 229)
+#define __NR_utimes                     (__NR_Linux + 230)
+#define __NR_mbind                      (__NR_Linux + 231)
+#define __NR_get_mempolicy              (__NR_Linux + 232)
+#define __NR_set_mempolicy              (__NR_Linux + 233)
+#define __NR_mq_open                    (__NR_Linux + 234)
+#define __NR_mq_unlink                  (__NR_Linux + 235)
+#define __NR_mq_timedsend               (__NR_Linux + 236)
+#define __NR_mq_timedreceive            (__NR_Linux + 237)
+#define __NR_mq_notify                  (__NR_Linux + 238)
+#define __NR_mq_getsetattr              (__NR_Linux + 239)
+#define __NR_vserver                    (__NR_Linux + 240)
+#define __NR_waitid                     (__NR_Linux + 241)
+/* #define __NR_sys_setaltroot          (__NR_Linux + 242) */
+#define __NR_add_key                    (__NR_Linux + 243)
+#define __NR_request_key                (__NR_Linux + 244)
+#define __NR_keyctl                     (__NR_Linux + 245)
+#define __NR_set_thread_area            (__NR_Linux + 246)
+#define __NR_inotify_init               (__NR_Linux + 247)
+#define __NR_inotify_add_watch          (__NR_Linux + 248)
+#define __NR_inotify_rm_watch           (__NR_Linux + 249)
+#define __NR_migrate_pages              (__NR_Linux + 250)
+#define __NR_openat                     (__NR_Linux + 251)
+#define __NR_mkdirat                    (__NR_Linux + 252)
+#define __NR_mknodat                    (__NR_Linux + 253)
+#define __NR_fchownat                   (__NR_Linux + 254)
+#define __NR_futimesat                  (__NR_Linux + 255)
+#define __NR_newfstatat                 (__NR_Linux + 256)
+#define __NR_unlinkat                   (__NR_Linux + 257)
+#define __NR_renameat                   (__NR_Linux + 258)
+#define __NR_linkat                     (__NR_Linux + 259)
+#define __NR_symlinkat                  (__NR_Linux + 260)
+#define __NR_readlinkat                 (__NR_Linux + 261)
+#define __NR_fchmodat                   (__NR_Linux + 262)
+#define __NR_faccessat                  (__NR_Linux + 263)
+#define __NR_pselect6                   (__NR_Linux + 264)
+#define __NR_ppoll                      (__NR_Linux + 265)
+#define __NR_unshare                    (__NR_Linux + 266)
+#define __NR_splice                     (__NR_Linux + 267)
+#define __NR_sync_file_range            (__NR_Linux + 268)
+#define __NR_tee                        (__NR_Linux + 269)
+#define __NR_vmsplice                   (__NR_Linux + 270)
+#define __NR_move_pages                 (__NR_Linux + 271)
+#define __NR_set_robust_list            (__NR_Linux + 272)
+#define __NR_get_robust_list            (__NR_Linux + 273)
+#define __NR_kexec_load                 (__NR_Linux + 274)
+#define __NR_getcpu                     (__NR_Linux + 275)
+#define __NR_epoll_pwait                (__NR_Linux + 276)
+#define __NR_ioprio_set                 (__NR_Linux + 277)
+#define __NR_ioprio_get                 (__NR_Linux + 278)
+#define __NR_utimensat                  (__NR_Linux + 279)
+#define __NR_signalfd                   (__NR_Linux + 280)
+#define __NR_timerfd                    (__NR_Linux + 281)
+#define __NR_eventfd                    (__NR_Linux + 282)
+#define __NR_fallocate                  (__NR_Linux + 283)
+#define __NR_timerfd_create             (__NR_Linux + 284)
+#define __NR_timerfd_gettime            (__NR_Linux + 285)
+#define __NR_timerfd_settime            (__NR_Linux + 286)
+#define __NR_signalfd4                  (__NR_Linux + 287)
+#define __NR_eventfd2                   (__NR_Linux + 288)
+#define __NR_epoll_create1              (__NR_Linux + 289)
+#define __NR_dup3                       (__NR_Linux + 290)
+#define __NR_pipe2                      (__NR_Linux + 291)
+#define __NR_inotify_init1              (__NR_Linux + 292)
+
+/*
+ * Offset of the last N32 flavoured syscall
+ */
+#define __NR_Linux_syscalls             292
+
+#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#define __NR_N32_Linux                  6000
+#define __NR_N32_Linux_syscalls         292
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+#define __ARCH_OMIT_COMPAT_SYS_GETDENTS64
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+# ifdef CONFIG_32BIT
+#  define __ARCH_WANT_STAT64
+#  define __ARCH_WANT_SYS_TIME
+# endif
+# ifdef CONFIG_MIPS32_O32
+#  define __ARCH_WANT_COMPAT_SYS_TIME
+# endif
+
+/* whitelists for checksyscalls */
+#define __IGNORE_select
+#define __IGNORE_vfork
+#define __IGNORE_time
+#define __IGNORE_uselib
+#define __IGNORE_fadvise64_64
+#define __IGNORE_getdents64
+#if _MIPS_SIM == _MIPS_SIM_NABI32
+#define __IGNORE_truncate64
+#define __IGNORE_ftruncate64
+#define __IGNORE_stat64
+#define __IGNORE_lstat64
+#define __IGNORE_fstat64
+#define __IGNORE_fstatat64
+#endif
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall")
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_UNISTD_H */
diff --git a/arch/mips/include/asm/user.h b/arch/mips/include/asm/user.h
new file mode 100644
index 000000000000..afa83a4c1888
--- /dev/null
+++ b/arch/mips/include/asm/user.h
@@ -0,0 +1,58 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_USER_H
+#define _ASM_USER_H
+
+#include <asm/page.h>
+#include <asm/reg.h>
+
+/*
+ * Core file format: The core file is written in such a way that gdb
+ * can understand it and provide useful information to the user (under
+ * linux we use the `trad-core' bfd, NOT the irix-core).  The file
+ * contents are as follows:
+ *
+ *  upage: 1 page consisting of a user struct that tells gdb
+ *      what is present in the file.  Directly after this is a
+ *      copy of the task_struct, which is currently not used by gdb,
+ *      but it may come in handy at some point.  All of the registers
+ *      are stored as part of the upage.  The upage should always be
+ *      only one page long.
+ *  data: The data segment follows next.  We use current->end_text to
+ *      current->brk to pick up all of the user variables, plus any memory
+ *      that may have been sbrk'ed.  No attempt is made to determine if a
+ *      page is demand-zero or if a page is totally unused, we just cover
+ *      the entire range.  All of the addresses are rounded in such a way
+ *      that an integral number of pages is written.
+ *  stack: We need the stack information in order to get a meaningful
+ *      backtrace.  We need to write the data from usp to
+ *      current->start_stack, so we round each of these in order to be able
+ *      to write an integer number of pages.
+ */
+struct user {
+        unsigned long   regs[EF_SIZE /          /* integer and fp regs */
+                        sizeof(unsigned long) + 64];
+        size_t          u_tsize;                /* text size (pages) */
+        size_t          u_dsize;                /* data size (pages) */
+        size_t          u_ssize;                /* stack size (pages) */
+        unsigned long   start_code;             /* text starting address */
+        unsigned long   start_data;             /* data starting address */
+        unsigned long   start_stack;            /* stack starting address */
+        long int        signal;                 /* signal causing core dump */
+        unsigned long   u_ar0;                  /* help gdb find registers */
+        unsigned long   magic;                  /* identifies a core file */
+        char            u_comm[32];             /* user command name */
+};
+
+#define NBPG                    PAGE_SIZE
+#define UPAGES                  1
+#define HOST_TEXT_START_ADDR    (u.start_code)
+#define HOST_DATA_START_ADDR    (u.start_data)
+#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
+
+#endif /* _ASM_USER_H */
diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h
new file mode 100644
index 000000000000..f4cff7e4fa8a
--- /dev/null
+++ b/arch/mips/include/asm/vga.h
@@ -0,0 +1,47 @@
+/*
+ *      Access to VGA videoram
+ *
+ *      (c) 1998 Martin Mares <mj@ucw.cz>
+ */
+#ifndef _ASM_VGA_H
+#define _ASM_VGA_H
+
+#include <asm/byteorder.h>
+
+/*
+ *      On the PC, we can just recalculate addresses and then
+ *      access the videoram directly without any black magic.
+ */
+
+#define VGA_MAP_MEM(x, s)       (0xb0000000L + (unsigned long)(x))
+
+#define vga_readb(x)    (*(x))
+#define vga_writeb(x, y)        (*(y) = (x))
+
+#define VT_BUF_HAVE_RW
+/*
+ *  These are only needed for supporting VGA or MDA text mode, which use little
+ *  endian byte ordering.
+ *  In other cases, we can optimize by using native byte ordering and
+ *  <linux/vt_buffer.h> has already done the right job for us.
+ */
+
+#undef scr_writew
+#undef scr_readw
+
+static inline void scr_writew(u16 val, volatile u16 *addr)
+{
+        *addr = cpu_to_le16(val);
+}
+
+static inline u16 scr_readw(volatile const u16 *addr)
+{
+        return le16_to_cpu(*addr);
+}
+
+#define scr_memcpyw(d, s, c) memcpy(d, s, c)
+#define scr_memmovew(d, s, c) memmove(d, s, c)
+#define VT_BUF_HAVE_MEMCPYW
+#define VT_BUF_HAVE_MEMMOVEW
+
+#endif /* _ASM_VGA_H */
diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h
new file mode 100644
index 000000000000..c6e1b961537d
--- /dev/null
+++ b/arch/mips/include/asm/vpe.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#ifndef _ASM_VPE_H
+#define _ASM_VPE_H
+
+struct vpe_notifications {
+        void (*start)(int vpe);
+        void (*stop)(int vpe);
+
+        struct list_head list;
+};
+
+
+extern int vpe_notify(int index, struct vpe_notifications *notify);
+
+extern void *vpe_get_shared(int index);
+extern int vpe_getuid(int index);
+extern int vpe_getgid(int index);
+extern char *vpe_getcwd(int index);
+
+#endif /* _ASM_VPE_H */
diff --git a/arch/mips/include/asm/vr41xx/capcella.h b/arch/mips/include/asm/vr41xx/capcella.h
new file mode 100644
index 000000000000..e0ee05a3dfcc
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/capcella.h
@@ -0,0 +1,43 @@
+/*
+ *  capcella.h, Include file for ZAO Networks Capcella.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ZAO_CAPCELLA_H
+#define __ZAO_CAPCELLA_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define PC104PLUS_INTA_PIN              2
+#define PC104PLUS_INTB_PIN              3
+#define PC104PLUS_INTC_PIN              4
+#define PC104PLUS_INTD_PIN              5
+
+/*
+ * Interrupt Number
+ */
+#define RTL8139_1_IRQ                   GIU_IRQ(PC104PLUS_INTC_PIN)
+#define RTL8139_2_IRQ                   GIU_IRQ(PC104PLUS_INTD_PIN)
+#define PC104PLUS_INTA_IRQ              GIU_IRQ(PC104PLUS_INTA_PIN)
+#define PC104PLUS_INTB_IRQ              GIU_IRQ(PC104PLUS_INTB_PIN)
+#define PC104PLUS_INTC_IRQ              GIU_IRQ(PC104PLUS_INTC_PIN)
+#define PC104PLUS_INTD_IRQ              GIU_IRQ(PC104PLUS_INTD_PIN)
+
+#endif /* __ZAO_CAPCELLA_H */
diff --git a/arch/mips/include/asm/vr41xx/giu.h b/arch/mips/include/asm/vr41xx/giu.h
new file mode 100644
index 000000000000..0bcdd3a5c256
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/giu.h
@@ -0,0 +1,78 @@
+/*
+ *  Include file for NEC VR4100 series General-purpose I/O Unit.
+ *
+ *  Copyright (C) 2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __NEC_VR41XX_GIU_H
+#define __NEC_VR41XX_GIU_H
+
+/*
+ * NEC VR4100 series GIU platform device IDs.
+ */
+enum {
+        GPIO_50PINS_PULLUPDOWN,
+        GPIO_36PINS,
+        GPIO_48PINS_EDGE_SELECT,
+};
+
+typedef enum {
+        IRQ_TRIGGER_LEVEL,
+        IRQ_TRIGGER_EDGE,
+        IRQ_TRIGGER_EDGE_FALLING,
+        IRQ_TRIGGER_EDGE_RISING,
+} irq_trigger_t;
+
+typedef enum {
+        IRQ_SIGNAL_THROUGH,
+        IRQ_SIGNAL_HOLD,
+} irq_signal_t;
+
+extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal);
+
+typedef enum {
+        IRQ_LEVEL_LOW,
+        IRQ_LEVEL_HIGH,
+} irq_level_t;
+
+extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
+
+typedef enum {
+        GPIO_DATA_LOW,
+        GPIO_DATA_HIGH,
+        GPIO_DATA_INVAL,
+} gpio_data_t;
+
+extern gpio_data_t vr41xx_gpio_get_pin(unsigned int pin);
+extern int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data);
+
+typedef enum {
+        GPIO_INPUT,
+        GPIO_OUTPUT,
+        GPIO_OUTPUT_DISABLE,
+} gpio_direction_t;
+
+extern int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir);
+
+typedef enum {
+        GPIO_PULL_DOWN,
+        GPIO_PULL_UP,
+        GPIO_PULL_DISABLE,
+} gpio_pull_t;
+
+extern int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull);
+
+#endif /* __NEC_VR41XX_GIU_H */
diff --git a/arch/mips/include/asm/vr41xx/irq.h b/arch/mips/include/asm/vr41xx/irq.h
new file mode 100644
index 000000000000..d315dfbc08f2
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/irq.h
@@ -0,0 +1,101 @@
+/*
+ * include/asm-mips/vr41xx/irq.h
+ *
+ * Interrupt numbers for NEC VR4100 series.
+ *
+ * Copyright (C) 1999 Michael Klar
+ * Copyright (C) 2001, 2002 Paul Mundt
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ * Copyright (C) 2002 TimeSys Corp.
+ * Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __NEC_VR41XX_IRQ_H
+#define __NEC_VR41XX_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE       0
+#define MIPS_CPU_IRQ(x)         (MIPS_CPU_IRQ_BASE + (x))
+#define MIPS_SOFTINT0_IRQ       MIPS_CPU_IRQ(0)
+#define MIPS_SOFTINT1_IRQ       MIPS_CPU_IRQ(1)
+#define INT0_IRQ                MIPS_CPU_IRQ(2)
+#define INT1_IRQ                MIPS_CPU_IRQ(3)
+#define INT2_IRQ                MIPS_CPU_IRQ(4)
+#define INT3_IRQ                MIPS_CPU_IRQ(5)
+#define INT4_IRQ                MIPS_CPU_IRQ(6)
+#define TIMER_IRQ               MIPS_CPU_IRQ(7)
+
+/*
+ * SYINT1 Interrupt Numbers
+ */
+#define SYSINT1_IRQ_BASE        8
+#define SYSINT1_IRQ(x)          (SYSINT1_IRQ_BASE + (x))
+#define BATTRY_IRQ              SYSINT1_IRQ(0)
+#define POWER_IRQ               SYSINT1_IRQ(1)
+#define RTCLONG1_IRQ            SYSINT1_IRQ(2)
+#define ELAPSEDTIME_IRQ         SYSINT1_IRQ(3)
+/* RFU */
+#define PIU_IRQ                 SYSINT1_IRQ(5)
+#define AIU_IRQ                 SYSINT1_IRQ(6)
+#define KIU_IRQ                 SYSINT1_IRQ(7)
+#define GIUINT_IRQ              SYSINT1_IRQ(8)
+#define SIU_IRQ                 SYSINT1_IRQ(9)
+#define BUSERR_IRQ              SYSINT1_IRQ(10)
+#define SOFTINT_IRQ             SYSINT1_IRQ(11)
+#define CLKRUN_IRQ              SYSINT1_IRQ(12)
+#define DOZEPIU_IRQ             SYSINT1_IRQ(13)
+#define SYSINT1_IRQ_LAST        DOZEPIU_IRQ
+
+/*
+ * SYSINT2 Interrupt Numbers
+ */
+#define SYSINT2_IRQ_BASE        24
+#define SYSINT2_IRQ(x)          (SYSINT2_IRQ_BASE + (x))
+#define RTCLONG2_IRQ            SYSINT2_IRQ(0)
+#define LED_IRQ                 SYSINT2_IRQ(1)
+#define HSP_IRQ                 SYSINT2_IRQ(2)
+#define TCLOCK_IRQ              SYSINT2_IRQ(3)
+#define FIR_IRQ                 SYSINT2_IRQ(4)
+#define CEU_IRQ                 SYSINT2_IRQ(4)  /* same number as FIR_IRQ */
+#define DSIU_IRQ                SYSINT2_IRQ(5)
+#define PCI_IRQ                 SYSINT2_IRQ(6)
+#define SCU_IRQ                 SYSINT2_IRQ(7)
+#define CSI_IRQ                 SYSINT2_IRQ(8)
+#define BCU_IRQ                 SYSINT2_IRQ(9)
+#define ETHERNET_IRQ            SYSINT2_IRQ(10)
+#define SYSINT2_IRQ_LAST        ETHERNET_IRQ
+
+/*
+ * GIU Interrupt Numbers
+ */
+#define GIU_IRQ_BASE            40
+#define GIU_IRQ(x)              (GIU_IRQ_BASE + (x))    /* IRQ 40-71 */
+#define GIU_IRQ_LAST            GIU_IRQ(31)
+
+/*
+ * VRC4173 Interrupt Numbers
+ */
+#define VRC4173_IRQ_BASE        72
+#define VRC4173_IRQ(x)          (VRC4173_IRQ_BASE + (x))
+#define VRC4173_USB_IRQ         VRC4173_IRQ(0)
+#define VRC4173_PCMCIA2_IRQ     VRC4173_IRQ(1)
+#define VRC4173_PCMCIA1_IRQ     VRC4173_IRQ(2)
+#define VRC4173_PS2CH2_IRQ      VRC4173_IRQ(3)
+#define VRC4173_PS2CH1_IRQ      VRC4173_IRQ(4)
+#define VRC4173_PIU_IRQ         VRC4173_IRQ(5)
+#define VRC4173_AIU_IRQ         VRC4173_IRQ(6)
+#define VRC4173_KIU_IRQ         VRC4173_IRQ(7)
+#define VRC4173_GIU_IRQ         VRC4173_IRQ(8)
+#define VRC4173_AC97_IRQ        VRC4173_IRQ(9)
+#define VRC4173_AC97INT1_IRQ    VRC4173_IRQ(10)
+/* RFU */
+#define VRC4173_DOZEPIU_IRQ     VRC4173_IRQ(13)
+#define VRC4173_IRQ_LAST        VRC4173_DOZEPIU_IRQ
+
+#endif /* __NEC_VR41XX_IRQ_H */
diff --git a/arch/mips/include/asm/vr41xx/mpc30x.h b/arch/mips/include/asm/vr41xx/mpc30x.h
new file mode 100644
index 000000000000..1d67df843dc3
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/mpc30x.h
@@ -0,0 +1,37 @@
+/*
+ *  mpc30x.h, Include file for Victor MP-C303/304.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __VICTOR_MPC30X_H
+#define __VICTOR_MPC30X_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define VRC4173_PIN                     1
+#define MQ200_PIN                       4
+
+/*
+ * Interrupt Number
+ */
+#define VRC4173_CASCADE_IRQ             GIU_IRQ(VRC4173_PIN)
+#define MQ200_IRQ                       GIU_IRQ(MQ200_PIN)
+
+#endif /* __VICTOR_MPC30X_H */
diff --git a/arch/mips/include/asm/vr41xx/pci.h b/arch/mips/include/asm/vr41xx/pci.h
new file mode 100644
index 000000000000..6fc01ce19777
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/pci.h
@@ -0,0 +1,90 @@
+/*
+ *  Include file for NEC VR4100 series PCI Control Unit.
+ *
+ *  Copyright (C) 2004-2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __NEC_VR41XX_PCI_H
+#define __NEC_VR41XX_PCI_H
+
+#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
+
+struct pci_master_address_conversion {
+        uint32_t bus_base_address;
+        uint32_t address_mask;
+        uint32_t pci_base_address;
+};
+
+struct pci_target_address_conversion {
+        uint32_t address_mask;
+        uint32_t bus_base_address;
+};
+
+typedef enum {
+        CANNOT_LOCK_FROM_DEVICE,
+        CAN_LOCK_FROM_DEVICE,
+} pci_exclusive_access_t;
+
+struct pci_mailbox_address {
+        uint32_t base_address;
+};
+
+struct pci_target_address_window {
+        uint32_t base_address;
+};
+
+typedef enum {
+        PCI_ARBITRATION_MODE_FAIR,
+        PCI_ARBITRATION_MODE_ALTERNATE_0,
+        PCI_ARBITRATION_MODE_ALTERNATE_B,
+} pci_arbiter_priority_control_t;
+
+typedef enum {
+        PCI_TAKE_AWAY_GNT_DISABLE,
+        PCI_TAKE_AWAY_GNT_ENABLE,
+} pci_take_away_gnt_mode_t;
+
+struct pci_controller_unit_setup {
+        struct pci_master_address_conversion *master_memory1;
+        struct pci_master_address_conversion *master_memory2;
+
+        struct pci_target_address_conversion *target_memory1;
+        struct pci_target_address_conversion *target_memory2;
+
+        struct pci_master_address_conversion *master_io;
+
+        pci_exclusive_access_t exclusive_access;
+
+        uint32_t pci_clock_max;
+        uint8_t wait_time_limit_from_irdy_to_trdy;      /* Only VR4122 is supported */
+
+        struct pci_mailbox_address *mailbox;
+        struct pci_target_address_window *target_window1;
+        struct pci_target_address_window *target_window2;
+
+        uint8_t master_latency_timer;
+        uint8_t retry_limit;
+
+        pci_arbiter_priority_control_t arbiter_priority_control;
+        pci_take_away_gnt_mode_t take_away_gnt_mode;
+
+        struct resource *mem_resource;
+        struct resource *io_resource;
+};
+
+extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
+
+#endif /* __NEC_VR41XX_PCI_H */
diff --git a/arch/mips/include/asm/vr41xx/siu.h b/arch/mips/include/asm/vr41xx/siu.h
new file mode 100644
index 000000000000..da9f6e373409
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/siu.h
@@ -0,0 +1,58 @@
+/*
+ *  Include file for NEC VR4100 series Serial Interface Unit.
+ *
+ *  Copyright (C) 2005-2008  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __NEC_VR41XX_SIU_H
+#define __NEC_VR41XX_SIU_H
+
+#define SIU_PORTS_MAX 2
+
+typedef enum {
+        SIU_INTERFACE_RS232C,
+        SIU_INTERFACE_IRDA,
+} siu_interface_t;
+
+extern void vr41xx_select_siu_interface(siu_interface_t interface);
+
+typedef enum {
+        SIU_USE_IRDA,
+        FIR_USE_IRDA,
+} irda_use_t;
+
+extern void vr41xx_use_irda(irda_use_t use);
+
+typedef enum {
+        SHARP_IRDA,
+        TEMIC_IRDA,
+        HP_IRDA,
+} irda_module_t;
+
+typedef enum {
+        IRDA_TX_1_5MBPS,
+        IRDA_TX_4MBPS,
+} irda_speed_t;
+
+extern void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed);
+
+#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
+extern void vr41xx_siu_early_setup(struct uart_port *port);
+#else
+static inline void vr41xx_siu_early_setup(struct uart_port *port) {}
+#endif
+
+#endif /* __NEC_VR41XX_SIU_H */
diff --git a/arch/mips/include/asm/vr41xx/tb0219.h b/arch/mips/include/asm/vr41xx/tb0219.h
new file mode 100644
index 000000000000..dc981b4be0a4
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/tb0219.h
@@ -0,0 +1,42 @@
+/*
+ *  tb0219.h, Include file for TANBAC TB0219.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  Modified for TANBAC TB0219:
+ *  Copyright (C) 2003 Megasolution Inc.  <matsu@megasolution.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __TANBAC_TB0219_H
+#define __TANBAC_TB0219_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define TB0219_PCI_SLOT1_PIN            2
+#define TB0219_PCI_SLOT2_PIN            3
+#define TB0219_PCI_SLOT3_PIN            4
+
+/*
+ * Interrupt Number
+ */
+#define TB0219_PCI_SLOT1_IRQ            GIU_IRQ(TB0219_PCI_SLOT1_PIN)
+#define TB0219_PCI_SLOT2_IRQ            GIU_IRQ(TB0219_PCI_SLOT2_PIN)
+#define TB0219_PCI_SLOT3_IRQ            GIU_IRQ(TB0219_PCI_SLOT3_PIN)
+
+#endif /* __TANBAC_TB0219_H */
diff --git a/arch/mips/include/asm/vr41xx/tb0226.h b/arch/mips/include/asm/vr41xx/tb0226.h
new file mode 100644
index 000000000000..de527dcfa5f3
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/tb0226.h
@@ -0,0 +1,43 @@
+/*
+ *  tb0226.h, Include file for TANBAC TB0226.
+ *
+ *  Copyright (C) 2002-2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __TANBAC_TB0226_H
+#define __TANBAC_TB0226_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define GD82559_1_PIN                   2
+#define GD82559_2_PIN                   3
+#define UPD720100_INTA_PIN              4
+#define UPD720100_INTB_PIN              8
+#define UPD720100_INTC_PIN              13
+
+/*
+ * Interrupt Number
+ */
+#define GD82559_1_IRQ                   GIU_IRQ(GD82559_1_PIN)
+#define GD82559_2_IRQ                   GIU_IRQ(GD82559_2_PIN)
+#define UPD720100_INTA_IRQ              GIU_IRQ(UPD720100_INTA_PIN)
+#define UPD720100_INTB_IRQ              GIU_IRQ(UPD720100_INTB_PIN)
+#define UPD720100_INTC_IRQ              GIU_IRQ(UPD720100_INTC_PIN)
+
+#endif /* __TANBAC_TB0226_H */
diff --git a/arch/mips/include/asm/vr41xx/tb0287.h b/arch/mips/include/asm/vr41xx/tb0287.h
new file mode 100644
index 000000000000..61bead68abf0
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/tb0287.h
@@ -0,0 +1,43 @@
+/*
+ *  tb0287.h, Include file for TANBAC TB0287 mini-ITX board.
+ *
+ *  Copyright (C) 2005  Media Lab Inc. <ito@mlb.co.jp>
+ *
+ *  This code is largely based on tb0219.h.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __TANBAC_TB0287_H
+#define __TANBAC_TB0287_H
+
+#include <asm/vr41xx/irq.h>
+
+/*
+ * General-Purpose I/O Pin Number
+ */
+#define TB0287_PCI_SLOT_PIN             2
+#define TB0287_SM501_PIN                3
+#define TB0287_SIL680A_PIN              8
+#define TB0287_RTL8110_PIN              13
+
+/*
+ * Interrupt Number
+ */
+#define TB0287_PCI_SLOT_IRQ             GIU_IRQ(TB0287_PCI_SLOT_PIN)
+#define TB0287_SM501_IRQ                GIU_IRQ(TB0287_SM501_PIN)
+#define TB0287_SIL680A_IRQ              GIU_IRQ(TB0287_SIL680A_PIN)
+#define TB0287_RTL8110_IRQ              GIU_IRQ(TB0287_RTL8110_PIN)
+
+#endif /* __TANBAC_TB0287_H */
diff --git a/arch/mips/include/asm/vr41xx/vr41xx.h b/arch/mips/include/asm/vr41xx/vr41xx.h
new file mode 100644
index 000000000000..22be64971cc6
--- /dev/null
+++ b/arch/mips/include/asm/vr41xx/vr41xx.h
@@ -0,0 +1,152 @@
+/*
+ * include/asm-mips/vr41xx/vr41xx.h
+ *
+ * Include file for NEC VR4100 series.
+ *
+ * Copyright (C) 1999 Michael Klar
+ * Copyright (C) 2001, 2002 Paul Mundt
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ * Copyright (C) 2002 TimeSys Corp.
+ * Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __NEC_VR41XX_H
+#define __NEC_VR41XX_H
+
+#include <linux/interrupt.h>
+
+/*
+ * CPU Revision
+ */
+/* VR4122 0x00000c70-0x00000c72 */
+#define PRID_VR4122_REV1_0      0x00000c70
+#define PRID_VR4122_REV2_0      0x00000c70
+#define PRID_VR4122_REV2_1      0x00000c70
+#define PRID_VR4122_REV3_0      0x00000c71
+#define PRID_VR4122_REV3_1      0x00000c72
+
+/* VR4181A 0x00000c73-0x00000c7f */
+#define PRID_VR4181A_REV1_0     0x00000c73
+#define PRID_VR4181A_REV1_1     0x00000c74
+
+/* VR4131 0x00000c80-0x00000c83 */
+#define PRID_VR4131_REV1_2      0x00000c80
+#define PRID_VR4131_REV2_0      0x00000c81
+#define PRID_VR4131_REV2_1      0x00000c82
+#define PRID_VR4131_REV2_2      0x00000c83
+
+/* VR4133 0x00000c84- */
+#define PRID_VR4133             0x00000c84
+
+/*
+ * Bus Control Uint
+ */
+extern unsigned long vr41xx_calculate_clock_frequency(void);
+extern unsigned long vr41xx_get_vtclock_frequency(void);
+extern unsigned long vr41xx_get_tclock_frequency(void);
+
+/*
+ * Clock Mask Unit
+ */
+typedef enum {
+        PIU_CLOCK,
+        SIU_CLOCK,
+        AIU_CLOCK,
+        KIU_CLOCK,
+        FIR_CLOCK,
+        DSIU_CLOCK,
+        CSI_CLOCK,
+        PCIU_CLOCK,
+        HSP_CLOCK,
+        PCI_CLOCK,
+        CEU_CLOCK,
+        ETHER0_CLOCK,
+        ETHER1_CLOCK
+} vr41xx_clock_t;
+
+extern void vr41xx_supply_clock(vr41xx_clock_t clock);
+extern void vr41xx_mask_clock(vr41xx_clock_t clock);
+
+/*
+ * Interrupt Control Unit
+ */
+extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
+extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int));
+
+#define PIUINT_COMMAND          0x0040
+#define PIUINT_DATA             0x0020
+#define PIUINT_PAGE1            0x0010
+#define PIUINT_PAGE0            0x0008
+#define PIUINT_DATALOST         0x0004
+#define PIUINT_STATUSCHANGE     0x0001
+
+extern void vr41xx_enable_piuint(uint16_t mask);
+extern void vr41xx_disable_piuint(uint16_t mask);
+
+#define AIUINT_INPUT_DMAEND     0x0800
+#define AIUINT_INPUT_DMAHALT    0x0400
+#define AIUINT_INPUT_DATALOST   0x0200
+#define AIUINT_INPUT_DATA       0x0100
+#define AIUINT_OUTPUT_DMAEND    0x0008
+#define AIUINT_OUTPUT_DMAHALT   0x0004
+#define AIUINT_OUTPUT_NODATA    0x0002
+
+extern void vr41xx_enable_aiuint(uint16_t mask);
+extern void vr41xx_disable_aiuint(uint16_t mask);
+
+#define KIUINT_DATALOST         0x0004
+#define KIUINT_DATAREADY        0x0002
+#define KIUINT_SCAN             0x0001
+
+extern void vr41xx_enable_kiuint(uint16_t mask);
+extern void vr41xx_disable_kiuint(uint16_t mask);
+
+#define DSIUINT_CTS             0x0800
+#define DSIUINT_RXERR           0x0400
+#define DSIUINT_RX              0x0200
+#define DSIUINT_TX              0x0100
+#define DSIUINT_ALL             0x0f00
+
+extern void vr41xx_enable_dsiuint(uint16_t mask);
+extern void vr41xx_disable_dsiuint(uint16_t mask);
+
+#define FIRINT_UNIT             0x0010
+#define FIRINT_RX_DMAEND        0x0008
+#define FIRINT_RX_DMAHALT       0x0004
+#define FIRINT_TX_DMAEND        0x0002
+#define FIRINT_TX_DMAHALT       0x0001
+
+extern void vr41xx_enable_firint(uint16_t mask);
+extern void vr41xx_disable_firint(uint16_t mask);
+
+extern void vr41xx_enable_pciint(void);
+extern void vr41xx_disable_pciint(void);
+
+extern void vr41xx_enable_scuint(void);
+extern void vr41xx_disable_scuint(void);
+
+#define CSIINT_TX_DMAEND        0x0040
+#define CSIINT_TX_DMAHALT       0x0020
+#define CSIINT_TX_DATA          0x0010
+#define CSIINT_TX_FIFOEMPTY     0x0008
+#define CSIINT_RX_DMAEND        0x0004
+#define CSIINT_RX_DMAHALT       0x0002
+#define CSIINT_RX_FIFOEMPTY     0x0001
+
+extern void vr41xx_enable_csiint(uint16_t mask);
+extern void vr41xx_disable_csiint(uint16_t mask);
+
+extern void vr41xx_enable_bcuint(void);
+extern void vr41xx_disable_bcuint(void);
+
+#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
+extern void vr41xx_siu_setup(void);
+#else
+static inline void vr41xx_siu_setup(void) {}
+#endif
+
+#endif /* __NEC_VR41XX_H */
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
new file mode 100644
index 000000000000..22361d5e3bf0
--- /dev/null
+++ b/arch/mips/include/asm/war.h
@@ -0,0 +1,244 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
+ * Copyright (C) 2007  Maciej W. Rozycki
+ */
+#ifndef _ASM_WAR_H
+#define _ASM_WAR_H
+
+#include <war.h>
+
+/*
+ * Work around certain R4000 CPU errata (as implemented by GCC):
+ *
+ * - A double-word or a variable shift may give an incorrect result
+ *   if executed immediately after starting an integer division:
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #28
+ *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
+ *   #19
+ *
+ * - A double-word or a variable shift may give an incorrect result
+ *   if executed while an integer multiplication is in progress:
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   errata #16 & #28
+ *
+ * - An integer division may give an incorrect result if started in
+ *   a delay slot of a taken branch or a jump:
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #52
+ */
+#ifdef CONFIG_CPU_R4000_WORKAROUNDS
+#define R4000_WAR 1
+#else
+#define R4000_WAR 0
+#endif
+
+/*
+ * Work around certain R4400 CPU errata (as implemented by GCC):
+ *
+ * - A double-word or a variable shift may give an incorrect result
+ *   if executed immediately after starting an integer division:
+ *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
+ *   "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
+ */
+#ifdef CONFIG_CPU_R4400_WORKAROUNDS
+#define R4400_WAR 1
+#else
+#define R4400_WAR 0
+#endif
+
+/*
+ * Work around the "daddi" and "daddiu" CPU errata:
+ *
+ * - The `daddi' instruction fails to trap on overflow.
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #23
+ *
+ * - The `daddiu' instruction can produce an incorrect result.
+ *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
+ *   erratum #41
+ *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
+ *   #15
+ *   "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
+ *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
+ */
+#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
+#define DADDI_WAR 1
+#else
+#define DADDI_WAR 0
+#endif
+
+/*
+ * Another R4600 erratum.  Due to the lack of errata information the exact
+ * technical details aren't known.  I've experimentally found that disabling
+ * interrupts during indexed I-cache flushes seems to be sufficient to deal
+ * with the issue.
+ */
+#ifndef R4600_V1_INDEX_ICACHEOP_WAR
+#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
+#endif
+
+/*
+ * Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
+ *
+ *  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
+ *      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
+ *      executed if there is no other dcache activity. If the dcache is
+ *      accessed for another instruction immeidately preceding when these
+ *      cache instructions are executing, it is possible that the dcache
+ *      tag match outputs used by these cache instructions will be
+ *      incorrect. These cache instructions should be preceded by at least
+ *      four instructions that are not any kind of load or store
+ *      instruction.
+ *
+ *      This is not allowed:    lw
+ *                              nop
+ *                              nop
+ *                              nop
+ *                              cache       Hit_Writeback_Invalidate_D
+ *
+ *      This is allowed:        lw
+ *                              nop
+ *                              nop
+ *                              nop
+ *                              nop
+ *                              cache       Hit_Writeback_Invalidate_D
+ */
+#ifndef R4600_V1_HIT_CACHEOP_WAR
+#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
+#endif
+
+
+/*
+ * Writeback and invalidate the primary cache dcache before DMA.
+ *
+ * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
+ * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
+ * operate correctly if the internal data cache refill buffer is empty.  These
+ * CACHE instructions should be separated from any potential data cache miss
+ * by a load instruction to an uncached address to empty the response buffer."
+ * (Revision 2.0 device errata from IDT available on http://www.idt.com/
+ * in .pdf format.)
+ */
+#ifndef R4600_V2_HIT_CACHEOP_WAR
+#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
+#endif
+
+/*
+ * When an interrupt happens on a CP0 register read instruction, CPU may
+ * lock up or read corrupted values of CP0 registers after it enters
+ * the exception handler.
+ *
+ * This workaround makes sure that we read a "safe" CP0 register as the
+ * first thing in the exception handler, which breaks one of the
+ * pre-conditions for this problem.
+ */
+#ifndef R5432_CP0_INTERRUPT_WAR
+#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
+#endif
+
+/*
+ * Workaround for the Sibyte M3 errata the text of which can be found at
+ *
+ *   http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
+ *
+ * This will enable the use of a special TLB refill handler which does a
+ * consistency check on the information in c0_badvaddr and c0_entryhi and
+ * will just return and take the exception again if the information was
+ * found to be inconsistent.
+ */
+#ifndef BCM1250_M3_WAR
+#error Check setting of BCM1250_M3_WAR for your platform
+#endif
+
+/*
+ * This is a DUART workaround related to glitches around register accesses
+ */
+#ifndef SIBYTE_1956_WAR
+#error Check setting of SIBYTE_1956_WAR for your platform
+#endif
+
+/*
+ * Fill buffers not flushed on CACHE instructions
+ *
+ * Hit_Invalidate_I cacheops invalidate an icache line but the refill
+ * for that line can get stale data from the fill buffer instead of
+ * accessing memory if the previous icache miss was also to that line.
+ *
+ * Workaround: generate an icache refill from a different line
+ *
+ * Affects:
+ *  MIPS 4K             RTL revision <3.0, PRID revision <4
+ */
+#ifndef MIPS4K_ICACHE_REFILL_WAR
+#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
+#endif
+
+/*
+ * Missing implicit forced flush of evictions caused by CACHE
+ * instruction
+ *
+ * Evictions caused by a CACHE instructions are not forced on to the
+ * bus. The BIU gives higher priority to fetches than to the data from
+ * the eviction buffer and no collision detection is performed between
+ * fetches and pending data from the eviction buffer.
+ *
+ * Workaround: Execute a SYNC instruction after the cache instruction
+ *
+ * Affects:
+ *   MIPS 5Kc,5Kf       RTL revision <2.3, PRID revision <8
+ *   MIPS 20Kc          RTL revision <4.0, PRID revision <?
+ */
+#ifndef MIPS_CACHE_SYNC_WAR
+#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
+#endif
+
+/*
+ * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
+ * the line which this instruction itself exists, the following
+ * operation is not guaranteed."
+ *
+ * Workaround: do two phase flushing for Index_Invalidate_I
+ */
+#ifndef TX49XX_ICACHE_INDEX_INV_WAR
+#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
+#endif
+
+/*
+ * On the RM9000 there is a problem which makes the CreateDirtyExclusive
+ * eache operation unusable on SMP systems.
+ */
+#ifndef RM9000_CDEX_SMP_WAR
+#error Check setting of RM9000_CDEX_SMP_WAR for your platform
+#endif
+
+/*
+ * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
+ * opposes it being called that) where invalid instructions in the same
+ * I-cache line worth of instructions being fetched may case spurious
+ * exceptions.
+ */
+#ifndef ICACHE_REFILLS_WORKAROUND_WAR
+#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
+#endif
+
+/*
+ * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
+ * may cause ll / sc and lld / scd sequences to execute non-atomically.
+ */
+#ifndef R10000_LLSC_WAR
+#error Check setting of R10000_LLSC_WAR for your platform
+#endif
+
+/*
+ * 34K core erratum: "Problems Executing the TLBR Instruction"
+ */
+#ifndef MIPS34K_MISSED_ITLB_WAR
+#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
+#endif
+
+#endif /* _ASM_WAR_H */
diff --git a/arch/mips/include/asm/watch.h b/arch/mips/include/asm/watch.h
new file mode 100644
index 000000000000..20126ec79359
--- /dev/null
+++ b/arch/mips/include/asm/watch.h
@@ -0,0 +1,32 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 David Daney
+ */
+#ifndef _ASM_WATCH_H
+#define _ASM_WATCH_H
+
+#include <linux/bitops.h>
+
+#include <asm/mipsregs.h>
+
+void mips_install_watch_registers(void);
+void mips_read_watch_registers(void);
+void mips_clear_watch_registers(void);
+void mips_probe_watch_registers(struct cpuinfo_mips *c);
+
+#ifdef CONFIG_HARDWARE_WATCHPOINTS
+#define __restore_watch() do {                                          \
+        if (unlikely(test_bit(TIF_LOAD_WATCH,                           \
+                              &current_thread_info()->flags))) {        \
+                mips_install_watch_registers();                         \
+        }                                                               \
+} while (0)
+
+#else
+#define __restore_watch() do {} while (0)
+#endif
+
+#endif /* _ASM_WATCH_H */
diff --git a/arch/mips/include/asm/wbflush.h b/arch/mips/include/asm/wbflush.h
new file mode 100644
index 000000000000..eadc0ac47e24
--- /dev/null
+++ b/arch/mips/include/asm/wbflush.h
@@ -0,0 +1,34 @@
+/*
+ * Header file for using the wbflush routine
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ * Copyright (C) 2002 Maciej W. Rozycki
+ */
+#ifndef _ASM_WBFLUSH_H
+#define _ASM_WBFLUSH_H
+
+
+#ifdef CONFIG_CPU_HAS_WB
+
+extern void (*__wbflush)(void);
+extern void wbflush_setup(void);
+
+#define wbflush()                       \
+        do {                            \
+                __sync();               \
+                __wbflush();            \
+        } while (0)
+
+#else /* !CONFIG_CPU_HAS_WB */
+
+#define wbflush_setup() do { } while (0)
+
+#define wbflush() fast_iob()
+
+#endif /* !CONFIG_CPU_HAS_WB */
+
+#endif /* _ASM_WBFLUSH_H */
diff --git a/arch/mips/include/asm/xor.h b/arch/mips/include/asm/xor.h
new file mode 100644
index 000000000000..c82eb12a5b18
--- /dev/null
+++ b/arch/mips/include/asm/xor.h
@@ -0,0 +1 @@
+#include <asm-generic/xor.h>
diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
new file mode 100644
index 000000000000..79bac882a739
--- /dev/null
+++ b/arch/mips/include/asm/xtalk/xtalk.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * xtalk.h -- platform-independent crosstalk interface, derived from
+ * IRIX <sys/PCI/bridge.h>, revision 1.38.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_XTALK_XTALK_H
+#define _ASM_XTALK_XTALK_H
+
+#ifndef __ASSEMBLY__
+/*
+ * User-level device driver visible types
+ */
+typedef char            xwidgetnum_t;   /* xtalk widget number  (0..15) */
+
+#define XWIDGET_NONE            -1
+
+typedef int xwidget_part_num_t; /* xtalk widget part number */
+
+#define XWIDGET_PART_NUM_NONE   -1
+
+typedef int             xwidget_rev_num_t;      /* xtalk widget revision number */
+
+#define XWIDGET_REV_NUM_NONE    -1
+
+typedef int xwidget_mfg_num_t;  /* xtalk widget manufacturing ID */
+
+#define XWIDGET_MFG_NUM_NONE    -1
+
+typedef struct xtalk_piomap_s *xtalk_piomap_t;
+
+/* It is often convenient to fold the XIO target port
+ * number into the XIO address.
+ */
+#define XIO_NOWHERE     (0xFFFFFFFFFFFFFFFFull)
+#define XIO_ADDR_BITS   (0x0000FFFFFFFFFFFFull)
+#define XIO_PORT_BITS   (0xF000000000000000ull)
+#define XIO_PORT_SHIFT  (60)
+
+#define XIO_PACKED(x)   (((x)&XIO_PORT_BITS) != 0)
+#define XIO_ADDR(x)     ((x)&XIO_ADDR_BITS)
+#define XIO_PORT(x)     ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
+#define XIO_PACK(p, o)  ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_XTALK_XTALK_H */
diff --git a/arch/mips/include/asm/xtalk/xwidget.h b/arch/mips/include/asm/xtalk/xwidget.h
new file mode 100644
index 000000000000..b4a13d7405ee
--- /dev/null
+++ b/arch/mips/include/asm/xtalk/xwidget.h
@@ -0,0 +1,167 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * xwidget.h - generic crosstalk widget header file, derived from IRIX
+ * <sys/xtalk/xtalkwidget.h>, revision 1.32.
+ *
+ * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_XTALK_XWIDGET_H
+#define _ASM_XTALK_XWIDGET_H
+
+#include <linux/types.h>
+#include <asm/xtalk/xtalk.h>
+
+#define WIDGET_ID                       0x04
+#define WIDGET_STATUS                   0x0c
+#define WIDGET_ERR_UPPER_ADDR           0x14
+#define WIDGET_ERR_LOWER_ADDR           0x1c
+#define WIDGET_CONTROL                  0x24
+#define WIDGET_REQ_TIMEOUT              0x2c
+#define WIDGET_INTDEST_UPPER_ADDR       0x34
+#define WIDGET_INTDEST_LOWER_ADDR       0x3c
+#define WIDGET_ERR_CMD_WORD             0x44
+#define WIDGET_LLP_CFG                  0x4c
+#define WIDGET_TFLUSH                   0x54
+
+/* WIDGET_ID */
+#define WIDGET_REV_NUM                  0xf0000000
+#define WIDGET_PART_NUM                 0x0ffff000
+#define WIDGET_MFG_NUM                  0x00000ffe
+#define WIDGET_REV_NUM_SHFT             28
+#define WIDGET_PART_NUM_SHFT            12
+#define WIDGET_MFG_NUM_SHFT             1
+
+#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT)
+#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT)
+#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT)
+
+/* WIDGET_STATUS */
+#define WIDGET_LLP_REC_CNT              0xff000000
+#define WIDGET_LLP_TX_CNT               0x00ff0000
+#define WIDGET_PENDING                  0x0000001f
+
+/* WIDGET_ERR_UPPER_ADDR */
+#define WIDGET_ERR_UPPER_ADDR_ONLY      0x0000ffff
+
+/* WIDGET_CONTROL */
+#define WIDGET_F_BAD_PKT                0x00010000
+#define WIDGET_LLP_XBAR_CRD             0x0000f000
+#define WIDGET_LLP_XBAR_CRD_SHFT        12
+#define WIDGET_CLR_RLLP_CNT             0x00000800
+#define WIDGET_CLR_TLLP_CNT             0x00000400
+#define WIDGET_SYS_END                  0x00000200
+#define WIDGET_MAX_TRANS                0x000001f0
+#define WIDGET_WIDGET_ID                0x0000000f
+
+/* WIDGET_INTDEST_UPPER_ADDR */
+#define WIDGET_INT_VECTOR               0xff000000
+#define WIDGET_INT_VECTOR_SHFT          24
+#define WIDGET_TARGET_ID                0x000f0000
+#define WIDGET_TARGET_ID_SHFT           16
+#define WIDGET_UPP_ADDR                 0x0000ffff
+
+/* WIDGET_ERR_CMD_WORD */
+#define WIDGET_DIDN                     0xf0000000
+#define WIDGET_SIDN                     0x0f000000
+#define WIDGET_PACTYP                   0x00f00000
+#define WIDGET_TNUM                     0x000f8000
+#define WIDGET_COHERENT                 0x00004000
+#define WIDGET_DS                       0x00003000
+#define WIDGET_GBR                      0x00000800
+#define WIDGET_VBPM                     0x00000400
+#define WIDGET_ERROR                    0x00000200
+#define WIDGET_BARRIER                  0x00000100
+
+/* WIDGET_LLP_CFG */
+#define WIDGET_LLP_MAXRETRY             0x03ff0000
+#define WIDGET_LLP_MAXRETRY_SHFT        16
+#define WIDGET_LLP_NULLTIMEOUT          0x0000fc00
+#define WIDGET_LLP_NULLTIMEOUT_SHFT     10
+#define WIDGET_LLP_MAXBURST             0x000003ff
+#define WIDGET_LLP_MAXBURST_SHFT        0
+
+/*
+ * according to the crosstalk spec, only 32-bits access to the widget
+ * configuration registers is allowed.  some widgets may allow 64-bits
+ * access but software should not depend on it.  registers beyond the
+ * widget target flush register are widget dependent thus will not be
+ * defined here
+ */
+#ifndef __ASSEMBLY__
+typedef u32 widgetreg_t;
+
+/* widget configuration registers */
+typedef volatile struct widget_cfg {
+        widgetreg_t             w_pad_0;                /* 0x00 */
+        widgetreg_t             w_id;                   /* 0x04 */
+        widgetreg_t             w_pad_1;                /* 0x08 */
+        widgetreg_t             w_status;               /* 0x0c */
+        widgetreg_t             w_pad_2;                /* 0x10 */
+        widgetreg_t             w_err_upper_addr;       /* 0x14 */
+        widgetreg_t             w_pad_3;                /* 0x18 */
+        widgetreg_t             w_err_lower_addr;       /* 0x1c */
+        widgetreg_t             w_pad_4;                /* 0x20 */
+        widgetreg_t             w_control;              /* 0x24 */
+        widgetreg_t             w_pad_5;                /* 0x28 */
+        widgetreg_t             w_req_timeout;          /* 0x2c */
+        widgetreg_t             w_pad_6;                /* 0x30 */
+        widgetreg_t             w_intdest_upper_addr;   /* 0x34 */
+        widgetreg_t             w_pad_7;                /* 0x38 */
+        widgetreg_t             w_intdest_lower_addr;   /* 0x3c */
+        widgetreg_t             w_pad_8;                /* 0x40 */
+        widgetreg_t             w_err_cmd_word;         /* 0x44 */
+        widgetreg_t             w_pad_9;                /* 0x48 */
+        widgetreg_t             w_llp_cfg;              /* 0x4c */
+        widgetreg_t             w_pad_10;               /* 0x50 */
+        widgetreg_t             w_tflush;               /* 0x54 */
+} widget_cfg_t;
+
+typedef struct {
+        unsigned        didn:4;
+        unsigned        sidn:4;
+        unsigned        pactyp:4;
+        unsigned        tnum:5;
+        unsigned        ct:1;
+        unsigned        ds:2;
+        unsigned        gbr:1;
+        unsigned        vbpm:1;
+        unsigned        error:1;
+        unsigned        bo:1;
+        unsigned        other:8;
+} w_err_cmd_word_f;
+
+typedef union {
+        widgetreg_t             r;
+        w_err_cmd_word_f        f;
+} w_err_cmd_word_u;
+
+typedef struct xwidget_info_s *xwidget_info_t;
+
+/*
+ * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
+ */
+typedef struct xwidget_hwid_s {
+        xwidget_part_num_t      part_num;
+        xwidget_rev_num_t       rev_num;
+        xwidget_mfg_num_t       mfg_num;
+} *xwidget_hwid_t;
+
+
+/*
+ * Returns 1 if a driver that handles devices described by hwid1 is able
+ * to manage a device with hardwareid hwid2.  NOTE: We don't check rev
+ * numbers at all.
+ */
+#define XWIDGET_HARDWARE_ID_MATCH(hwid1, hwid2) \
+        (((hwid1)->part_num == (hwid2)->part_num) && \
+        (((hwid1)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
+        ((hwid2)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
+        ((hwid1)->mfg_num == (hwid2)->mfg_num)))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_XTALK_XWIDGET_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 706f93974797..d9da7112aaf8 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -6,10 +6,11 @@ extra-y		:= head.o init_task.o vmlinux.lds
 
 obj-y           += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
                    ptrace.o reset.o setup.o signal.o syscall.o \
-                   time.o topology.o traps.o unaligned.o
+                   time.o topology.o traps.o unaligned.o watch.o
 
 obj-$(CONFIG_CEVT_BCM1480)      += cevt-bcm1480.o
 obj-$(CONFIG_CEVT_R4K)          += cevt-r4k.o
+obj-$(CONFIG_MIPS_MT_SMTC)      += cevt-smtc.o
 obj-$(CONFIG_CEVT_DS1287)       += cevt-ds1287.o
 obj-$(CONFIG_CEVT_GT641XX)      += cevt-gt641xx.o
 obj-$(CONFIG_CEVT_SB1250)       += cevt-sb1250.o
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 24a2d907aa0d..4a4c59f2737a 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -12,6 +12,14 @@
 
 #include <asm/smtc_ipi.h>
 #include <asm/time.h>
+#include <asm/cevt-r4k.h>
+
+/*
+ * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
+ * of these routines with SMTC-specific variants.
+ */
+
+#ifndef CONFIG_MIPS_MT_SMTC
 
 static int mips_next_event(unsigned long delta,
                            struct clock_event_device *evt)
@@ -19,60 +27,27 @@ static int mips_next_event(unsigned long delta,
         unsigned int cnt;
         int res;
 
-#ifdef CONFIG_MIPS_MT_SMTC
-        {
-        unsigned long flags, vpflags;
-        local_irq_save(flags);
-        vpflags = dvpe();
-#endif
         cnt = read_c0_count();
         cnt += delta;
         write_c0_compare(cnt);
         res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
-#ifdef CONFIG_MIPS_MT_SMTC
-        evpe(vpflags);
-        local_irq_restore(flags);
-        }
-#endif
         return res;
 }
 
-static void mips_set_mode(enum clock_event_mode mode,
-                          struct clock_event_device *evt)
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+void mips_set_clock_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
 {
         /* Nothing to do ...  */
 }
 
-static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
-static int cp0_timer_irq_installed;
+DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
+int cp0_timer_irq_installed;
 
-/*
- * Timer ack for an R4k-compatible timer of a known frequency.
- */
-static void c0_timer_ack(void)
-{
-        write_c0_compare(read_c0_compare());
-}
+#ifndef CONFIG_MIPS_MT_SMTC
 
-/*
- * Possibly handle a performance counter interrupt.
- * Return true if the timer interrupt should not be checked
- */
-static inline int handle_perf_irq(int r2)
-{
-        /*
-         * The performance counter overflow interrupt may be shared with the
-         * timer interrupt (cp0_perfcount_irq < 0). If it is and a
-         * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
-         * and we can't reliably determine if a counter interrupt has also
-         * happened (!r2) then don't check for a timer interrupt.
-         */
-        return (cp0_perfcount_irq < 0) &&
-                perf_irq() == IRQ_HANDLED &&
-                !r2;
-}
-
-static irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
+irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
 {
         const int r2 = cpu_has_mips_r2;
         struct clock_event_device *cd;
@@ -93,12 +68,8 @@ static irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
          * interrupt.  Being the paranoiacs we are we check anyway.
          */
         if (!r2 || (read_c0_cause() & (1 << 30))) {
-                c0_timer_ack();
-#ifdef CONFIG_MIPS_MT_SMTC
-                if (cpu_data[cpu].vpe_id)
-                        goto out;
-                cpu = 0;
-#endif
+                /* Clear Count/Compare Interrupt */
+                write_c0_compare(read_c0_compare());
                 cd = &per_cpu(mips_clockevent_device, cpu);
                 cd->event_handler(cd);
         }
@@ -107,65 +78,16 @@ out:
         return IRQ_HANDLED;
 }
 
-static struct irqaction c0_compare_irqaction = {
+#endif /* Not CONFIG_MIPS_MT_SMTC */
+
+struct irqaction c0_compare_irqaction = {
         .handler = c0_compare_interrupt,
-#ifdef CONFIG_MIPS_MT_SMTC
-        .flags = IRQF_DISABLED,
-#else
         .flags = IRQF_DISABLED | IRQF_PERCPU,
-#endif
         .name = "timer",
 };
 
-#ifdef CONFIG_MIPS_MT_SMTC
-DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
-
-static void smtc_set_mode(enum clock_event_mode mode,
-                          struct clock_event_device *evt)
-{
-}
-
-static void mips_broadcast(cpumask_t mask)
-{
-        unsigned int cpu;
-
-        for_each_cpu_mask(cpu, mask)
-                smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
-}
-
-static void setup_smtc_dummy_clockevent_device(void)
-{
-        //uint64_t mips_freq = mips_hpt_^frequency;
-        unsigned int cpu = smp_processor_id();
-        struct clock_event_device *cd;
 
-        cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
-
-        cd->name                = "SMTC";
-        cd->features            = CLOCK_EVT_FEAT_DUMMY;
-
-        /* Calculate the min / max delta */
-        cd->mult        = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
-        cd->shift               = 0; //32;
-        cd->max_delta_ns        = 0; //clockevent_delta2ns(0x7fffffff, cd);
-        cd->min_delta_ns        = 0; //clockevent_delta2ns(0x30, cd);
-
-        cd->rating              = 200;
-        cd->irq                 = 17; //-1;
-//      if (cpu)
-//              cd->cpumask     = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
-//      else
-                cd->cpumask     = cpumask_of_cpu(cpu);
-
-        cd->set_mode            = smtc_set_mode;
-
-        cd->broadcast           = mips_broadcast;
-
-        clockevents_register_device(cd);
-}
-#endif
-
-static void mips_event_handler(struct clock_event_device *dev)
+void mips_event_handler(struct clock_event_device *dev)
 {
 }
 
@@ -177,7 +99,23 @@ static int c0_compare_int_pending(void)
         return (read_c0_cause() >> cp0_compare_irq) & 0x100;
 }
 
-static int c0_compare_int_usable(void)
+/*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register.  4 time the
+ * pipeline depth seems reasonably conservative, and empirically
+ * works better in configurations with high CPU/bus clock ratios.
+ */
+
+#define compare_change_hazard() \
+        do { \
+                irq_disable_hazard(); \
+                irq_disable_hazard(); \
+                irq_disable_hazard(); \
+                irq_disable_hazard(); \
+        } while (0)
+
+int c0_compare_int_usable(void)
 {
         unsigned int delta;
         unsigned int cnt;
@@ -187,7 +125,7 @@ static int c0_compare_int_usable(void)
          */
         if (c0_compare_int_pending()) {
                 write_c0_compare(read_c0_count());
-                irq_disable_hazard();
+                compare_change_hazard();
                 if (c0_compare_int_pending())
                         return 0;
         }
@@ -196,7 +134,7 @@ static int c0_compare_int_usable(void)
                 cnt = read_c0_count();
                 cnt += delta;
                 write_c0_compare(cnt);
-                irq_disable_hazard();
+                compare_change_hazard();
                 if ((int)(read_c0_count() - cnt) < 0)
                     break;
                 /* increase delta if the timer was already expired */
@@ -205,11 +143,12 @@ static int c0_compare_int_usable(void)
         while ((int)(read_c0_count() - cnt) <= 0)
                 ;       /* Wait for expiry  */
 
+        compare_change_hazard();
         if (!c0_compare_int_pending())
                 return 0;
 
         write_c0_compare(read_c0_count());
-        irq_disable_hazard();
+        compare_change_hazard();
         if (c0_compare_int_pending())
                 return 0;
 
@@ -219,6 +158,8 @@ static int c0_compare_int_usable(void)
         return 1;
 }
 
+#ifndef CONFIG_MIPS_MT_SMTC
+
 int __cpuinit mips_clockevent_init(void)
 {
         uint64_t mips_freq = mips_hpt_frequency;
@@ -229,17 +170,6 @@ int __cpuinit mips_clockevent_init(void)
         if (!cpu_has_counter || !mips_hpt_frequency)
                 return -ENXIO;
 
-#ifdef CONFIG_MIPS_MT_SMTC
-        setup_smtc_dummy_clockevent_device();
-
-        /*
-         * On SMTC we only register VPE0's compare interrupt as clockevent
-         * device.
-         */
-        if (cpu)
-                return 0;
-#endif
-
         if (!c0_compare_int_usable())
                 return -ENXIO;
 
@@ -265,13 +195,9 @@ int __cpuinit mips_clockevent_init(void)
 
         cd->rating              = 300;
         cd->irq                 = irq;
-#ifdef CONFIG_MIPS_MT_SMTC
-        cd->cpumask             = CPU_MASK_ALL;
-#else
         cd->cpumask             = cpumask_of_cpu(cpu);
-#endif
         cd->set_next_event      = mips_next_event;
-        cd->set_mode            = mips_set_mode;
+        cd->set_mode            = mips_set_clock_mode;
         cd->event_handler       = mips_event_handler;
 
         clockevents_register_device(cd);
@@ -281,12 +207,9 @@ int __cpuinit mips_clockevent_init(void)
 
         cp0_timer_irq_installed = 1;
 
-#ifdef CONFIG_MIPS_MT_SMTC
-#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
-        setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT);
-#else
         setup_irq(irq, &c0_compare_irqaction);
-#endif
 
         return 0;
 }
+
+#endif /* Not CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c
new file mode 100644
index 000000000000..5162fe4b5952
--- /dev/null
+++ b/arch/mips/kernel/cevt-smtc.c
@@ -0,0 +1,321 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 MIPS Technologies, Inc.
+ * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2008 Kevin D. Kissell, Paralogos sarl
+ */
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/percpu.h>
+
+#include <asm/smtc_ipi.h>
+#include <asm/time.h>
+#include <asm/cevt-r4k.h>
+
+/*
+ * Variant clock event timer support for SMTC on MIPS 34K, 1004K
+ * or other MIPS MT cores.
+ *
+ * Notes on SMTC Support:
+ *
+ * SMTC has multiple microthread TCs pretending to be Linux CPUs.
+ * But there's only one Count/Compare pair per VPE, and Compare
+ * interrupts are taken opportunisitically by available TCs
+ * bound to the VPE with the Count register.  The new timer
+ * framework provides for global broadcasts, but we really
+ * want VPE-level multicasts for best behavior. So instead
+ * of invoking the high-level clock-event broadcast code,
+ * this version of SMTC support uses the historical SMTC
+ * multicast mechanisms "under the hood", appearing to the
+ * generic clock layer as if the interrupts are per-CPU.
+ *
+ * The approach taken here is to maintain a set of NR_CPUS
+ * virtual timers, and track which "CPU" needs to be alerted
+ * at each event.
+ *
+ * It's unlikely that we'll see a MIPS MT core with more than
+ * 2 VPEs, but we *know* that we won't need to handle more
+ * VPEs than we have "CPUs".  So NCPUs arrays of NCPUs elements
+ * is always going to be overkill, but always going to be enough.
+ */
+
+unsigned long smtc_nexttime[NR_CPUS][NR_CPUS];
+static int smtc_nextinvpe[NR_CPUS];
+
+/*
+ * Timestamps stored are absolute values to be programmed
+ * into Count register.  Valid timestamps will never be zero.
+ * If a Zero Count value is actually calculated, it is converted
+ * to be a 1, which will introduce 1 or two CPU cycles of error
+ * roughly once every four billion events, which at 1000 HZ means
+ * about once every 50 days.  If that's actually a problem, one
+ * could alternate squashing 0 to 1 and to -1.
+ */
+
+#define MAKEVALID(x) (((x) == 0L) ? 1L : (x))
+#define ISVALID(x) ((x) != 0L)
+
+/*
+ * Time comparison is subtle, as it's really truncated
+ * modular arithmetic.
+ */
+
+#define IS_SOONER(a, b, reference) \
+    (((a) - (unsigned long)(reference)) < ((b) - (unsigned long)(reference)))
+
+/*
+ * CATCHUP_INCREMENT, used when the function falls behind the counter.
+ * Could be an increasing function instead of a constant;
+ */
+
+#define CATCHUP_INCREMENT 64
+
+static int mips_next_event(unsigned long delta,
+                                struct clock_event_device *evt)
+{
+        unsigned long flags;
+        unsigned int mtflags;
+        unsigned long timestamp, reference, previous;
+        unsigned long nextcomp = 0L;
+        int vpe = current_cpu_data.vpe_id;
+        int cpu = smp_processor_id();
+        local_irq_save(flags);
+        mtflags = dmt();
+
+        /*
+         * Maintain the per-TC virtual timer
+         * and program the per-VPE shared Count register
+         * as appropriate here...
+         */
+        reference = (unsigned long)read_c0_count();
+        timestamp = MAKEVALID(reference + delta);
+        /*
+         * To really model the clock, we have to catch the case
+         * where the current next-in-VPE timestamp is the old
+         * timestamp for the calling CPE, but the new value is
+         * in fact later.  In that case, we have to do a full
+         * scan and discover the new next-in-VPE CPU id and
+         * timestamp.
+         */
+        previous = smtc_nexttime[vpe][cpu];
+        if (cpu == smtc_nextinvpe[vpe] && ISVALID(previous)
+            && IS_SOONER(previous, timestamp, reference)) {
+                int i;
+                int soonest = cpu;
+
+                /*
+                 * Update timestamp array here, so that new
+                 * value gets considered along with those of
+                 * other virtual CPUs on the VPE.
+                 */
+                smtc_nexttime[vpe][cpu] = timestamp;
+                for_each_online_cpu(i) {
+                        if (ISVALID(smtc_nexttime[vpe][i])
+                            && IS_SOONER(smtc_nexttime[vpe][i],
+                                smtc_nexttime[vpe][soonest], reference)) {
+                                    soonest = i;
+                        }
+                }
+                smtc_nextinvpe[vpe] = soonest;
+                nextcomp = smtc_nexttime[vpe][soonest];
+        /*
+         * Otherwise, we don't have to process the whole array rank,
+         * we just have to see if the event horizon has gotten closer.
+         */
+        } else {
+                if (!ISVALID(smtc_nexttime[vpe][smtc_nextinvpe[vpe]]) ||
+                    IS_SOONER(timestamp,
+                        smtc_nexttime[vpe][smtc_nextinvpe[vpe]], reference)) {
+                            smtc_nextinvpe[vpe] = cpu;
+                            nextcomp = timestamp;
+                }
+                /*
+                 * Since next-in-VPE may me the same as the executing
+                 * virtual CPU, we update the array *after* checking
+                 * its value.
+                 */
+                smtc_nexttime[vpe][cpu] = timestamp;
+        }
+
+        /*
+         * It may be that, in fact, we don't need to update Compare,
+         * but if we do, we want to make sure we didn't fall into
+         * a crack just behind Count.
+         */
+        if (ISVALID(nextcomp)) {
+                write_c0_compare(nextcomp);
+                ehb();
+                /*
+                 * We never return an error, we just make sure
+                 * that we trigger the handlers as quickly as
+                 * we can if we fell behind.
+                 */
+                while ((nextcomp - (unsigned long)read_c0_count())
+                        > (unsigned long)LONG_MAX) {
+                        nextcomp += CATCHUP_INCREMENT;
+                        write_c0_compare(nextcomp);
+                        ehb();
+                }
+        }
+        emt(mtflags);
+        local_irq_restore(flags);
+        return 0;
+}
+
+
+void smtc_distribute_timer(int vpe)
+{
+        unsigned long flags;
+        unsigned int mtflags;
+        int cpu;
+        struct clock_event_device *cd;
+        unsigned long nextstamp = 0L;
+        unsigned long reference;
+
+
+repeat:
+        for_each_online_cpu(cpu) {
+            /*
+             * Find virtual CPUs within the current VPE who have
+             * unserviced timer requests whose time is now past.
+             */
+            local_irq_save(flags);
+            mtflags = dmt();
+            if (cpu_data[cpu].vpe_id == vpe &&
+                ISVALID(smtc_nexttime[vpe][cpu])) {
+                reference = (unsigned long)read_c0_count();
+                if ((smtc_nexttime[vpe][cpu] - reference)
+                         > (unsigned long)LONG_MAX) {
+                            smtc_nexttime[vpe][cpu] = 0L;
+                            emt(mtflags);
+                            local_irq_restore(flags);
+                            /*
+                             * We don't send IPIs to ourself.
+                             */
+                            if (cpu != smp_processor_id()) {
+                                smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
+                            } else {
+                                cd = &per_cpu(mips_clockevent_device, cpu);
+                                cd->event_handler(cd);
+                            }
+                } else {
+                        /* Local to VPE but Valid Time not yet reached. */
+                        if (!ISVALID(nextstamp) ||
+                            IS_SOONER(smtc_nexttime[vpe][cpu], nextstamp,
+                            reference)) {
+                                smtc_nextinvpe[vpe] = cpu;
+                                nextstamp = smtc_nexttime[vpe][cpu];
+                        }
+                        emt(mtflags);
+                        local_irq_restore(flags);
+                }
+            } else {
+                emt(mtflags);
+                local_irq_restore(flags);
+
+            }
+        }
+        /* Reprogram for interrupt at next soonest timestamp for VPE */
+        if (ISVALID(nextstamp)) {
+                write_c0_compare(nextstamp);
+                ehb();
+                if ((nextstamp - (unsigned long)read_c0_count())
+                        > (unsigned long)LONG_MAX)
+                                goto repeat;
+        }
+}
+
+
+irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
+{
+        int cpu = smp_processor_id();
+
+        /* If we're running SMTC, we've got MIPS MT and therefore MIPS32R2 */
+        handle_perf_irq(1);
+
+        if (read_c0_cause() & (1 << 30)) {
+                /* Clear Count/Compare Interrupt */
+                write_c0_compare(read_c0_compare());
+                smtc_distribute_timer(cpu_data[cpu].vpe_id);
+        }
+        return IRQ_HANDLED;
+}
+
+
+int __cpuinit mips_clockevent_init(void)
+{
+        uint64_t mips_freq = mips_hpt_frequency;
+        unsigned int cpu = smp_processor_id();
+        struct clock_event_device *cd;
+        unsigned int irq;
+        int i;
+        int j;
+
+        if (!cpu_has_counter || !mips_hpt_frequency)
+                return -ENXIO;
+        if (cpu == 0) {
+                for (i = 0; i < num_possible_cpus(); i++) {
+                        smtc_nextinvpe[i] = 0;
+                        for (j = 0; j < num_possible_cpus(); j++)
+                                smtc_nexttime[i][j] = 0L;
+                }
+                /*
+                 * SMTC also can't have the usablility test
+                 * run by secondary TCs once Compare is in use.
+                 */
+                if (!c0_compare_int_usable())
+                        return -ENXIO;
+        }
+
+        /*
+         * With vectored interrupts things are getting platform specific.
+         * get_c0_compare_int is a hook to allow a platform to return the
+         * interrupt number of it's liking.
+         */
+        irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
+        if (get_c0_compare_int)
+                irq = get_c0_compare_int();
+
+        cd = &per_cpu(mips_clockevent_device, cpu);
+
+        cd->name                = "MIPS";
+        cd->features            = CLOCK_EVT_FEAT_ONESHOT;
+
+        /* Calculate the min / max delta */
+        cd->mult        = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
+        cd->shift               = 32;
+        cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
+        cd->min_delta_ns        = clockevent_delta2ns(0x300, cd);
+
+        cd->rating              = 300;
+        cd->irq                 = irq;
+        cd->cpumask             = cpumask_of_cpu(cpu);
+        cd->set_next_event      = mips_next_event;
+        cd->set_mode            = mips_set_clock_mode;
+        cd->event_handler       = mips_event_handler;
+
+        clockevents_register_device(cd);
+
+        /*
+         * On SMTC we only want to do the data structure
+         * initialization and IRQ setup once.
+         */
+        if (cpu)
+                return 0;
+        /*
+         * And we need the hwmask associated with the c0_compare
+         * vector to be initialized.
+         */
+        irq_hwmask[irq] = (0x100 << cp0_compare_irq);
+        if (cp0_timer_irq_installed)
+                return 0;
+
+        cp0_timer_irq_installed = 1;
+
+        setup_irq(irq, &c0_compare_irqaction);
+
+        return 0;
+}
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 335a6ae3d594..0cf15457ecac 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -21,6 +21,7 @@
 #include <asm/fpu.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
+#include <asm/watch.h>
 
 /*
  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
@@ -45,18 +46,7 @@ static void r39xx_wait(void)
         local_irq_enable();
 }
 
-/*
- * There is a race when WAIT instruction executed with interrupt
- * enabled.
- * But it is implementation-dependent wheter the pipelie restarts when
- * a non-enabled interrupt is requested.
- */
-static void r4k_wait(void)
-{
-        __asm__("       .set    mips3                   \n"
-                "       wait                            \n"
-                "       .set    mips0                   \n");
-}
+extern void r4k_wait(void);
 
 /*
  * This variant is preferable as it allows testing need_resched and going to
@@ -65,14 +55,18 @@ static void r4k_wait(void)
  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  * using this version a gamble.
  */
-static void r4k_wait_irqoff(void)
+void r4k_wait_irqoff(void)
 {
         local_irq_disable();
         if (!need_resched())
-                __asm__("       .set    mips3           \n"
+                __asm__("       .set    push            \n"
+                        "       .set    mips3           \n"
                         "       wait                    \n"
-                        "       .set    mips0           \n");
+                        "       .set    pop             \n");
         local_irq_enable();
+        __asm__("       .globl __pastwait       \n"
+                "__pastwait:                    \n");
+        return;
 }
 
 /*
@@ -128,7 +122,7 @@ static int __init wait_disable(char *s)
 
 __setup("nowait", wait_disable);
 
-static inline void check_wait(void)
+void __init check_wait(void)
 {
         struct cpuinfo_mips *c = &current_cpu_data;
 
@@ -242,7 +236,6 @@ static inline void check_errata(void)
 
 void __init check_bugs32(void)
 {
-        check_wait();
         check_errata();
 }
 
@@ -685,6 +678,7 @@ static inline void spram_config(void) {}
 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 {
         decode_configs(c);
+        mips_probe_watch_registers(c);
         switch (c->processor_id & 0xff00) {
         case PRID_IMP_4KC:
                 c->cputype = CPU_4KC;
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index e29598ae939d..ffa331029e08 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -79,11 +79,6 @@ FEXPORT(syscall_exit)
 
 FEXPORT(restore_all)                    # restore full frame
 #ifdef CONFIG_MIPS_MT_SMTC
-/* Detect and execute deferred IPI "interrupts" */
-        LONG_L  s0, TI_REGS($28)
-        LONG_S  sp, TI_REGS($28)
-        jal     deferred_smtc_ipi
-        LONG_S  s0, TI_REGS($28)
 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
 /* Re-arm any temporarily masked interrupts not explicitly "acked" */
         mfc0    v0, CP0_TCSTATUS
@@ -112,6 +107,11 @@ FEXPORT(restore_all)			# restore full frame
         xor     t0, t0, t3
         mtc0    t0, CP0_TCCONTEXT
 #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
+/* Detect and execute deferred IPI "interrupts" */
+        LONG_L  s0, TI_REGS($28)
+        LONG_S  sp, TI_REGS($28)
+        jal     deferred_smtc_ipi
+        LONG_S  s0, TI_REGS($28)
 #endif /* CONFIG_MIPS_MT_SMTC */
         .set    noat
         RESTORE_TEMP
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index c6ada98ee042..757d48f0d80f 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -20,6 +20,7 @@
 #include <asm/stackframe.h>
 #include <asm/war.h>
 #include <asm/page.h>
+#include <asm/thread_info.h>
 
 #define PANIC_PIC(msg)                                  \
                 .set push;                              \
@@ -126,7 +127,42 @@ handle_vcei:
 
         __FINIT
 
+        .align  5       /* 32 byte rollback region */
+LEAF(r4k_wait)
+        .set    push
+        .set    noreorder
+        /* start of rollback region */
+        LONG_L  t0, TI_FLAGS($28)
+        nop
+        andi    t0, _TIF_NEED_RESCHED
+        bnez    t0, 1f
+         nop
+        nop
+        nop
+        .set    mips3
+        wait
+        /* end of rollback region (the region size must be power of two) */
+        .set    pop
+1:
+        jr      ra
+        END(r4k_wait)
+
+        .macro  BUILD_ROLLBACK_PROLOGUE handler
+        FEXPORT(rollback_\handler)
+        .set    push
+        .set    noat
+        MFC0    k0, CP0_EPC
+        PTR_LA  k1, r4k_wait
+        ori     k0, 0x1f        /* 32 byte rollback region */
+        xori    k0, 0x1f
+        bne     k0, k1, 9f
+        MTC0    k0, CP0_EPC
+9:
+        .set pop
+        .endm
+
         .align  5
+BUILD_ROLLBACK_PROLOGUE handle_int
 NESTED(handle_int, PT_SIZE, sp)
 #ifdef CONFIG_TRACE_IRQFLAGS
         /*
@@ -201,6 +237,7 @@ NESTED(except_vec_ejtag_debug, 0, sp)
  * This prototype is copied to ebase + n*IntCtl.VS and patched
  * to invoke the handler
  */
+BUILD_ROLLBACK_PROLOGUE except_vec_vi
 NESTED(except_vec_vi, 0, sp)
         SAVE_SOME
         SAVE_AT
@@ -245,8 +282,8 @@ NESTED(except_vec_vi_handler, 0, sp)
         and     t0, a0, t1
 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
         mfc0    t2, CP0_TCCONTEXT
-        or      t0, t0, t2
-        mtc0    t0, CP0_TCCONTEXT
+        or      t2, t0, t2
+        mtc0    t2, CP0_TCCONTEXT
 #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
         xor     t1, t1, t0
         mtc0    t1, CP0_STATUS
@@ -416,7 +453,11 @@ NESTED(nmi_handler, PT_SIZE, sp)
         BUILD_HANDLER tr tr sti silent                  /* #13 */
         BUILD_HANDLER fpe fpe fpe silent                /* #15 */
         BUILD_HANDLER mdmx mdmx sti silent              /* #22 */
+#ifdef  CONFIG_HARDWARE_WATCHPOINTS
+        BUILD_HANDLER watch watch sti silent            /* #23 */
+#else
         BUILD_HANDLER watch watch sti verbose           /* #23 */
+#endif
         BUILD_HANDLER mcheck mcheck cli verbose         /* #24 */
         BUILD_HANDLER mt mt sti silent                  /* #25 */
         BUILD_HANDLER dsp dsp sti silent                /* #26 */
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 361364501d34..492a0a8d70fb 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -22,6 +22,7 @@
 #include <asm/irqflags.h>
 #include <asm/regdef.h>
 #include <asm/page.h>
+#include <asm/pgtable-bits.h>
 #include <asm/mipsregs.h>
 #include <asm/stackframe.h>
 
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index 8f6d58ede33c..6e152c80cd4a 100644
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -236,8 +236,7 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code,
 
                 atomic_set(&kgdb_cpu_doing_single_step, -1);
                 if (remcom_in_buffer[0] == 's')
-                        if (kgdb_contthread)
-                                atomic_set(&kgdb_cpu_doing_single_step, cpu);
+                        atomic_set(&kgdb_cpu_doing_single_step, cpu);
 
                 return 0;
         }
diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
index df4d3f2f740c..dc9eb72ed9de 100644
--- a/arch/mips/kernel/mips-mt-fpaff.c
+++ b/arch/mips/kernel/mips-mt-fpaff.c
@@ -159,7 +159,7 @@ __setup("fpaff=", fpaff_thresh);
 /*
  * FPU Use Factor empirically derived from experiments on 34K
  */
-#define FPUSEFACTOR 333
+#define FPUSEFACTOR 2000
 
 static __init int mt_fp_affinity_init(void)
 {
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 36f065398243..75bb1300dd7a 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -23,6 +23,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         unsigned int version = cpu_data[n].processor_id;
         unsigned int fp_vers = cpu_data[n].fpu_id;
         char fmt [64];
+        int i;
 
 #ifdef CONFIG_SMP
         if (!cpu_isset(n, cpu_online_map))
@@ -50,8 +51,16 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
         seq_printf(m, "extra interrupt vector\t: %s\n",
                       cpu_has_divec ? "yes" : "no");
-        seq_printf(m, "hardware watchpoint\t: %s\n",
-                      cpu_has_watch ? "yes" : "no");
+        seq_printf(m, "hardware watchpoint\t: %s",
+                   cpu_has_watch ? "yes, " : "no\n");
+        if (cpu_has_watch) {
+                seq_printf(m, "count: %d, address/irw mask: [",
+                           cpu_data[n].watch_reg_count);
+                for (i = 0; i < cpu_data[n].watch_reg_count; i++)
+                        seq_printf(m, "%s0x%04x", i ? ", " : "" ,
+                                   cpu_data[n].watch_reg_masks[i]);
+                seq_printf(m, "]\n");
+        }
         seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
                       cpu_has_mips16 ? " mips16" : "",
                       cpu_has_mdmx ? " mdmx" : "",
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index b16facd9ea8e..22fc19bbe87f 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -55,7 +55,7 @@ void __noreturn cpu_idle(void)
         while (1) {
                 tick_nohz_stop_sched_tick(1);
                 while (!need_resched()) {
-#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
+#ifdef CONFIG_MIPS_MT_SMTC
                         extern void smtc_idle_loop_hook(void);
 
                         smtc_idle_loop_hook();
@@ -145,17 +145,18 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
          */
         p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1);
         childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
-        clear_tsk_thread_flag(p, TIF_USEDFPU);
 
-#ifdef CONFIG_MIPS_MT_FPAFF
+#ifdef CONFIG_MIPS_MT_SMTC
         /*
-         * FPU affinity support is cleaner if we track the
-         * user-visible CPU affinity from the very beginning.
-         * The generic cpus_allowed mask will already have
-         * been copied from the parent before copy_thread
-         * is invoked.
+         * SMTC restores TCStatus after Status, and the CU bits
+         * are aliased there.
          */
-        p->thread.user_cpus_allowed = p->cpus_allowed;
+        childregs->cp0_tcstatus &= ~(ST0_CU2|ST0_CU1);
+#endif
+        clear_tsk_thread_flag(p, TIF_USEDFPU);
+
+#ifdef CONFIG_MIPS_MT_FPAFF
+        clear_tsk_thread_flag(p, TIF_FPUBOUND);
 #endif /* CONFIG_MIPS_MT_FPAFF */
 
         if (clone_flags & CLONE_SETTLS)
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 35234b92b9a5..054861ccb4dd 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -46,7 +46,8 @@
  */
 void ptrace_disable(struct task_struct *child)
 {
-        /* Nothing to do.. */
+        /* Don't load the watchpoint registers for the ex-child. */
+        clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
 }
 
 /*
@@ -167,6 +168,93 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
         return 0;
 }
 
+int ptrace_get_watch_regs(struct task_struct *child,
+                          struct pt_watch_regs __user *addr)
+{
+        enum pt_watch_style style;
+        int i;
+
+        if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
+                return -EIO;
+        if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
+                return -EIO;
+
+#ifdef CONFIG_32BIT
+        style = pt_watch_style_mips32;
+#define WATCH_STYLE mips32
+#else
+        style = pt_watch_style_mips64;
+#define WATCH_STYLE mips64
+#endif
+
+        __put_user(style, &addr->style);
+        __put_user(current_cpu_data.watch_reg_use_cnt,
+                   &addr->WATCH_STYLE.num_valid);
+        for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
+                __put_user(child->thread.watch.mips3264.watchlo[i],
+                           &addr->WATCH_STYLE.watchlo[i]);
+                __put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
+                           &addr->WATCH_STYLE.watchhi[i]);
+                __put_user(current_cpu_data.watch_reg_masks[i],
+                           &addr->WATCH_STYLE.watch_masks[i]);
+        }
+        for (; i < 8; i++) {
+                __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
+                __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
+                __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
+        }
+
+        return 0;
+}
+
+int ptrace_set_watch_regs(struct task_struct *child,
+                          struct pt_watch_regs __user *addr)
+{
+        int i;
+        int watch_active = 0;
+        unsigned long lt[NUM_WATCH_REGS];
+        u16 ht[NUM_WATCH_REGS];
+
+        if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
+                return -EIO;
+        if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
+                return -EIO;
+        /* Check the values. */
+        for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
+                __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
+#ifdef CONFIG_32BIT
+                if (lt[i] & __UA_LIMIT)
+                        return -EINVAL;
+#else
+                if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
+                        if (lt[i] & 0xffffffff80000000UL)
+                                return -EINVAL;
+                } else {
+                        if (lt[i] & __UA_LIMIT)
+                                return -EINVAL;
+                }
+#endif
+                __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
+                if (ht[i] & ~0xff8)
+                        return -EINVAL;
+        }
+        /* Install them. */
+        for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
+                if (lt[i] & 7)
+                        watch_active = 1;
+                child->thread.watch.mips3264.watchlo[i] = lt[i];
+                /* Set the G bit. */
+                child->thread.watch.mips3264.watchhi[i] = ht[i];
+        }
+
+        if (watch_active)
+                set_tsk_thread_flag(child, TIF_LOAD_WATCH);
+        else
+                clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
+
+        return 0;
+}
+
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
         int ret;
@@ -238,7 +326,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 case FPC_EIR: { /* implementation / version register */
                         unsigned int flags;
 #ifdef CONFIG_MIPS_MT_SMTC
-                        unsigned int irqflags;
+                        unsigned long irqflags;
                         unsigned int mtflags;
 #endif /* CONFIG_MIPS_MT_SMTC */
 
@@ -440,6 +528,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                                 (unsigned long __user *) data);
                 break;
 
+        case PTRACE_GET_WATCH_REGS:
+                ret = ptrace_get_watch_regs(child,
+                                        (struct pt_watch_regs __user *) addr);
+                break;
+
+        case PTRACE_SET_WATCH_REGS:
+                ret = ptrace_set_watch_regs(child,
+                                        (struct pt_watch_regs __user *) addr);
+                break;
+
         default:
                 ret = ptrace_request(child, request, addr, data);
                 break;
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 76818be6ba7c..1ca34104e593 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -15,6 +15,7 @@
  * binaries.
  */
 #include <linux/compiler.h>
+#include <linux/compat.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/mm.h>
@@ -36,47 +37,17 @@
 #include <asm/uaccess.h>
 #include <asm/bootinfo.h>
 
-int ptrace_getregs(struct task_struct *child, __s64 __user *data);
-int ptrace_setregs(struct task_struct *child, __s64 __user *data);
-
-int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
-int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
-
 /*
  * Tracing a 32-bit process with a 64-bit strace and vice versa will not
  * work.  I don't know how to fix this.
  */
-asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
+long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
+                        compat_ulong_t caddr, compat_ulong_t cdata)
 {
-        struct task_struct *child;
+        int addr = caddr;
+        int data = cdata;
         int ret;
 
-#if 0
-        printk("ptrace(r=%d,pid=%d,addr=%08lx,data=%08lx)\n",
-               (int) request, (int) pid, (unsigned long) addr,
-               (unsigned long) data);
-#endif
-        lock_kernel();
-        if (request == PTRACE_TRACEME) {
-                ret = ptrace_traceme();
-                goto out;
-        }
-
-        child = ptrace_get_task_struct(pid);
-        if (IS_ERR(child)) {
-                ret = PTR_ERR(child);
-                goto out;
-        }
-
-        if (request == PTRACE_ATTACH) {
-                ret = ptrace_attach(child);
-                goto out_tsk;
-        }
-
-        ret = ptrace_check_attach(child, request == PTRACE_KILL);
-        if (ret < 0)
-                goto out_tsk;
-
         switch (request) {
         /* when I and D space are separate, these will need to be fixed. */
         case PTRACE_PEEKTEXT: /* read word at location addr. */
@@ -214,7 +185,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
                         if (!cpu_has_dsp) {
                                 tmp = 0;
                                 ret = -EIO;
-                                goto out_tsk;
+                                goto out;
                         }
                         dregs = __get_dsp_regs(child);
                         tmp = (unsigned long) (dregs[addr - DSP_BASE]);
@@ -224,14 +195,14 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
                         if (!cpu_has_dsp) {
                                 tmp = 0;
                                 ret = -EIO;
-                                goto out_tsk;
+                                goto out;
                         }
                         tmp = child->thread.dsp.dspcontrol;
                         break;
                 default:
                         tmp = 0;
                         ret = -EIO;
-                        goto out_tsk;
+                        goto out;
                 }
                 ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
                 break;
@@ -410,14 +381,20 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
                                 (unsigned long __user *) (unsigned long) data);
                 break;
 
+        case PTRACE_GET_WATCH_REGS:
+                ret = ptrace_get_watch_regs(child,
+                        (struct pt_watch_regs __user *) (unsigned long) addr);
+                break;
+
+        case PTRACE_SET_WATCH_REGS:
+                ret = ptrace_set_watch_regs(child,
+                        (struct pt_watch_regs __user *) (unsigned long) addr);
+                break;
+
         default:
                 ret = ptrace_request(child, request, addr, data);
                 break;
         }
-
-out_tsk:
-        put_task_struct(child);
 out:
-        unlock_kernel();
         return ret;
 }
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index da7f1b6ea0fb..324c5499dec2 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -219,7 +219,7 @@ EXPORT(sysn32_call_table)
         PTR     compat_sys_getrusage
         PTR     compat_sys_sysinfo
         PTR     compat_sys_times
-        PTR     sys32_ptrace
+        PTR     compat_sys_ptrace
         PTR     sys_getuid                      /* 6100 */
         PTR     sys_syslog
         PTR     sys_getgid
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index d7cd1aac9ada..85fedac99a57 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -231,7 +231,7 @@ sys_call_table:
         PTR     sys_setuid
         PTR     sys_getuid
         PTR     compat_sys_stime                /* 4025 */
-        PTR     sys32_ptrace
+        PTR     compat_sys_ptrace
         PTR     sys_alarm
         PTR     sys_ni_syscall                  /* was sys_fstat */
         PTR     sys_pause
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 572c610db1b1..652709b353ad 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -482,6 +482,18 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
         return err;
 }
 
+int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
+{
+        memset(to, 0, sizeof *to);
+
+        if (copy_from_user(to, from, 3*sizeof(int)) ||
+            copy_from_user(to->_sifields._pad,
+                           from->_sifields._pad, SI_PAD_SIZE32))
+                return -EFAULT;
+
+        return 0;
+}
+
 asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
 {
         struct sigframe32 __user *frame;
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 4410f172b8ab..7b59cfb7e602 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -121,6 +121,8 @@ asmlinkage __cpuinit void start_secondary(void)
         cpu = smp_processor_id();
         cpu_data[cpu].udelay_val = loops_per_jiffy;
 
+        notify_cpu_starting(cpu);
+
         mp_ops->smp_finish();
         set_cpu_sibling_map(cpu);
 
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index a516286532ab..897fb2b4751c 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1,4 +1,21 @@
-/* Copyright (C) 2004 Mips Technologies, Inc */
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * Copyright (C) 2004 Mips Technologies, Inc
+ * Copyright (C) 2008 Kevin D. Kissell
+ */
 
 #include <linux/clockchips.h>
 #include <linux/kernel.h>
@@ -21,7 +38,6 @@
 #include <asm/time.h>
 #include <asm/addrspace.h>
 #include <asm/smtc.h>
-#include <asm/smtc_ipi.h>
 #include <asm/smtc_proc.h>
 
 /*
@@ -58,11 +74,6 @@ unsigned long irq_hwmask[NR_IRQS];
 
 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
 
-/*
- * Clock interrupt "latch" buffers, per "CPU"
- */
-
-static atomic_t ipi_timer_latch[NR_CPUS];
 
 /*
  * Number of InterProcessor Interrupt (IPI) message buffers to allocate
@@ -70,7 +81,7 @@ static atomic_t ipi_timer_latch[NR_CPUS];
 
 #define IPIBUF_PER_CPU 4
 
-static struct smtc_ipi_q IPIQ[NR_CPUS];
+struct smtc_ipi_q IPIQ[NR_CPUS];
 static struct smtc_ipi_q freeIPIq;
 
 
@@ -282,7 +293,7 @@ static void smtc_configure_tlb(void)
  * phys_cpu_present_map and the logical/physical mappings.
  */
 
-int __init mipsmt_build_cpu_map(int start_cpu_slot)
+int __init smtc_build_cpu_map(int start_cpu_slot)
 {
         int i, ntcs;
 
@@ -325,7 +336,12 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
         write_tc_c0_tcstatus((read_tc_c0_tcstatus()
                         & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
                         | TCSTATUS_A);
-        write_tc_c0_tccontext(0);
+        /*
+         * TCContext gets an offset from the base of the IPIQ array
+         * to be used in low-level code to detect the presence of
+         * an active IPI queue
+         */
+        write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
         /* Bind tc to vpe */
         write_tc_c0_tcbind(vpe);
         /* In general, all TCs should have the same cpu_data indications */
@@ -336,10 +352,18 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
                 cpu_data[cpu].options &= ~MIPS_CPU_FPU;
         cpu_data[cpu].vpe_id = vpe;
         cpu_data[cpu].tc_id = tc;
+        /* Multi-core SMTC hasn't been tested, but be prepared */
+        cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff;
 }
 
+/*
+ * Tweak to get Count registes in as close a sync as possible.
+ * Value seems good for 34K-class cores.
+ */
+
+#define CP0_SKEW 8
 
-void mipsmt_prepare_cpus(void)
+void smtc_prepare_cpus(int cpus)
 {
         int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu;
         unsigned long flags;
@@ -363,13 +387,13 @@ void mipsmt_prepare_cpus(void)
                 IPIQ[i].head = IPIQ[i].tail = NULL;
                 spin_lock_init(&IPIQ[i].lock);
                 IPIQ[i].depth = 0;
-                atomic_set(&ipi_timer_latch[i], 0);
         }
 
         /* cpu_data index starts at zero */
         cpu = 0;
         cpu_data[cpu].vpe_id = 0;
         cpu_data[cpu].tc_id = 0;
+        cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff;
         cpu++;
 
         /* Report on boot-time options */
@@ -484,7 +508,8 @@ void mipsmt_prepare_cpus(void)
                         write_vpe_c0_compare(0);
                         /* Propagate Config7 */
                         write_vpe_c0_config7(read_c0_config7());
-                        write_vpe_c0_count(read_c0_count());
+                        write_vpe_c0_count(read_c0_count() + CP0_SKEW);
+                        ehb();
                 }
                 /* enable multi-threading within VPE */
                 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
@@ -556,7 +581,7 @@ void mipsmt_prepare_cpus(void)
 void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
 {
         extern u32 kernelsp[NR_CPUS];
-        long flags;
+        unsigned long flags;
         int mtflags;
 
         LOCK_MT_PRA();
@@ -585,24 +610,22 @@ void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
 
 void smtc_init_secondary(void)
 {
-        /*
-         * Start timer on secondary VPEs if necessary.
-         * plat_timer_setup has already have been invoked by init/main
-         * on "boot" TC.  Like per_cpu_trap_init() hack, this assumes that
-         * SMTC init code assigns TCs consdecutively and in ascending order
-         * to across available VPEs.
-         */
-        if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
-            ((read_c0_tcbind() & TCBIND_CURVPE)
-            != cpu_data[smp_processor_id() - 1].vpe_id)){
-                write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
-        }
-
         local_irq_enable();
 }
 
 void smtc_smp_finish(void)
 {
+        int cpu = smp_processor_id();
+
+        /*
+         * Lowest-numbered CPU per VPE starts a clock tick.
+         * Like per_cpu_trap_init() hack, this assumes that
+         * SMTC init code assigns TCs consdecutively and
+         * in ascending order across available VPEs.
+         */
+        if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
+                write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
+
         printk("TC %d going on-line as CPU %d\n",
                 cpu_data[smp_processor_id()].tc_id, smp_processor_id());
 }
@@ -753,8 +776,10 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
 {
         int tcstatus;
         struct smtc_ipi *pipi;
-        long flags;
+        unsigned long flags;
         int mtflags;
+        unsigned long tcrestart;
+        extern void r4k_wait_irqoff(void), __pastwait(void);
 
         if (cpu == smp_processor_id()) {
                 printk("Cannot Send IPI to self!\n");
@@ -771,8 +796,6 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
         pipi->arg = (void *)action;
         pipi->dest = cpu;
         if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
-                if (type == SMTC_CLOCK_TICK)
-                        atomic_inc(&ipi_timer_latch[cpu]);
                 /* If not on same VPE, enqueue and send cross-VPE interrupt */
                 smtc_ipi_nq(&IPIQ[cpu], pipi);
                 LOCK_CORE_PRA();
@@ -800,22 +823,29 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
 
                 if ((tcstatus & TCSTATUS_IXMT) != 0) {
                         /*
-                         * Spin-waiting here can deadlock,
-                         * so we queue the message for the target TC.
+                         * If we're in the the irq-off version of the wait
+                         * loop, we need to force exit from the wait and
+                         * do a direct post of the IPI.
+                         */
+                        if (cpu_wait == r4k_wait_irqoff) {
+                                tcrestart = read_tc_c0_tcrestart();
+                                if (tcrestart >= (unsigned long)r4k_wait_irqoff
+                                    && tcrestart < (unsigned long)__pastwait) {
+                                        write_tc_c0_tcrestart(__pastwait);
+                                        tcstatus &= ~TCSTATUS_IXMT;
+                                        write_tc_c0_tcstatus(tcstatus);
+                                        goto postdirect;
+                                }
+                        }
+                        /*
+                         * Otherwise we queue the message for the target TC
+                         * to pick up when he does a local_irq_restore()
                          */
                         write_tc_c0_tchalt(0);
                         UNLOCK_CORE_PRA();
-                        /* Try to reduce redundant timer interrupt messages */
-                        if (type == SMTC_CLOCK_TICK) {
-                            if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){
-                                smtc_ipi_nq(&freeIPIq, pipi);
-                                return;
-                            }
-                        }
                         smtc_ipi_nq(&IPIQ[cpu], pipi);
                 } else {
-                        if (type == SMTC_CLOCK_TICK)
-                                atomic_inc(&ipi_timer_latch[cpu]);
+postdirect:
                         post_direct_ipi(cpu, pipi);
                         write_tc_c0_tchalt(0);
                         UNLOCK_CORE_PRA();
@@ -883,7 +913,7 @@ static void ipi_call_interrupt(void)
         smp_call_function_interrupt();
 }
 
-DECLARE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
+DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
 
 void ipi_decode(struct smtc_ipi *pipi)
 {
@@ -891,20 +921,13 @@ void ipi_decode(struct smtc_ipi *pipi)
         struct clock_event_device *cd;
         void *arg_copy = pipi->arg;
         int type_copy = pipi->type;
-        int ticks;
-
         smtc_ipi_nq(&freeIPIq, pipi);
         switch (type_copy) {
         case SMTC_CLOCK_TICK:
                 irq_enter();
                 kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++;
-                cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
-                ticks = atomic_read(&ipi_timer_latch[cpu]);
-                atomic_sub(ticks, &ipi_timer_latch[cpu]);
-                while (ticks) {
-                        cd->event_handler(cd);
-                        ticks--;
-                }
+                cd = &per_cpu(mips_clockevent_device, cpu);
+                cd->event_handler(cd);
                 irq_exit();
                 break;
 
@@ -937,24 +960,48 @@ void ipi_decode(struct smtc_ipi *pipi)
         }
 }
 
+/*
+ * Similar to smtc_ipi_replay(), but invoked from context restore,
+ * so it reuses the current exception frame rather than set up a
+ * new one with self_ipi.
+ */
+
 void deferred_smtc_ipi(void)
 {
-        struct smtc_ipi *pipi;
-        unsigned long flags;
-/* DEBUG */
-        int q = smp_processor_id();
+        int cpu = smp_processor_id();
 
         /*
          * Test is not atomic, but much faster than a dequeue,
          * and the vast majority of invocations will have a null queue.
+         * If irq_disabled when this was called, then any IPIs queued
+         * after we test last will be taken on the next irq_enable/restore.
+         * If interrupts were enabled, then any IPIs added after the
+         * last test will be taken directly.
          */
-        if (IPIQ[q].head != NULL) {
-                while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) {
-                        /* ipi_decode() should be called with interrupts off */
-                        local_irq_save(flags);
+
+        while (IPIQ[cpu].head != NULL) {
+                struct smtc_ipi_q *q = &IPIQ[cpu];
+                struct smtc_ipi *pipi;
+                unsigned long flags;
+
+                /*
+                 * It may be possible we'll come in with interrupts
+                 * already enabled.
+                 */
+                local_irq_save(flags);
+
+                spin_lock(&q->lock);
+                pipi = __smtc_ipi_dq(q);
+                spin_unlock(&q->lock);
+                if (pipi != NULL)
                         ipi_decode(pipi);
-                        local_irq_restore(flags);
-                }
+                /*
+                 * The use of the __raw_local restore isn't
+                 * as obviously necessary here as in smtc_ipi_replay(),
+                 * but it's more efficient, given that we're already
+                 * running down the IPI queue.
+                 */
+                __raw_local_irq_restore(flags);
         }
 }
 
@@ -975,7 +1022,7 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
         struct smtc_ipi *pipi;
         unsigned long tcstatus;
         int sent;
-        long flags;
+        unsigned long flags;
         unsigned int mtflags;
         unsigned int vpflags;
 
@@ -1066,55 +1113,53 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe)
 
 /*
  * SMTC-specific hacks invoked from elsewhere in the kernel.
- *
- * smtc_ipi_replay is called from raw_local_irq_restore which is only ever
- * called with interrupts disabled.  We do rely on interrupts being disabled
- * here because using spin_lock_irqsave()/spin_unlock_irqrestore() would
- * result in a recursive call to raw_local_irq_restore().
  */
 
-static void __smtc_ipi_replay(void)
+ /*
+  * smtc_ipi_replay is called from raw_local_irq_restore
+  */
+
+void smtc_ipi_replay(void)
 {
         unsigned int cpu = smp_processor_id();
 
         /*
          * To the extent that we've ever turned interrupts off,
          * we may have accumulated deferred IPIs.  This is subtle.
-         * If we use the smtc_ipi_qdepth() macro, we'll get an
-         * exact number - but we'll also disable interrupts
-         * and create a window of failure where a new IPI gets
-         * queued after we test the depth but before we re-enable
-         * interrupts. So long as IXMT never gets set, however,
          * we should be OK:  If we pick up something and dispatch
          * it here, that's great. If we see nothing, but concurrent
          * with this operation, another TC sends us an IPI, IXMT
          * is clear, and we'll handle it as a real pseudo-interrupt
-         * and not a pseudo-pseudo interrupt.
+         * and not a pseudo-pseudo interrupt.  The important thing
+         * is to do the last check for queued message *after* the
+         * re-enabling of interrupts.
          */
-        if (IPIQ[cpu].depth > 0) {
-                while (1) {
-                        struct smtc_ipi_q *q = &IPIQ[cpu];
-                        struct smtc_ipi *pipi;
-                        extern void self_ipi(struct smtc_ipi *);
-
-                        spin_lock(&q->lock);
-                        pipi = __smtc_ipi_dq(q);
-                        spin_unlock(&q->lock);
-                        if (!pipi)
-                                break;
+        while (IPIQ[cpu].head != NULL) {
+                struct smtc_ipi_q *q = &IPIQ[cpu];
+                struct smtc_ipi *pipi;
+                unsigned long flags;
+
+                /*
+                 * It's just possible we'll come in with interrupts
+                 * already enabled.
+                 */
+                local_irq_save(flags);
+
+                spin_lock(&q->lock);
+                pipi = __smtc_ipi_dq(q);
+                spin_unlock(&q->lock);
+                /*
+                 ** But use a raw restore here to avoid recursion.
+                 */
+                __raw_local_irq_restore(flags);
 
+                if (pipi) {
                         self_ipi(pipi);
                         smtc_cpu_stats[cpu].selfipis++;
                 }
         }
 }
 
-void smtc_ipi_replay(void)
-{
-        raw_local_irq_disable();
-        __smtc_ipi_replay();
-}
-
 EXPORT_SYMBOL(smtc_ipi_replay);
 
 void smtc_idle_loop_hook(void)
@@ -1193,40 +1238,13 @@ void smtc_idle_loop_hook(void)
                 }
         }
 
-        /*
-         * Now that we limit outstanding timer IPIs, check for hung TC
-         */
-        for (tc = 0; tc < NR_CPUS; tc++) {
-                /* Don't check ourself - we'll dequeue IPIs just below */
-                if ((tc != smp_processor_id()) &&
-                    atomic_read(&ipi_timer_latch[tc]) > timerq_limit) {
-                    if (clock_hang_reported[tc] == 0) {
-                        pdb_msg += sprintf(pdb_msg,
-                                "TC %d looks hung with timer latch at %d\n",
-                                tc, atomic_read(&ipi_timer_latch[tc]));
-                        clock_hang_reported[tc]++;
-                        }
-                }
-        }
         emt(mtflags);
         local_irq_restore(flags);
         if (pdb_msg != &id_ho_db_msg[0])
                 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
 
-        /*
-         * Replay any accumulated deferred IPIs. If "Instant Replay"
-         * is in use, there should never be any.
-         */
-#ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
-        {
-                unsigned long flags;
-
-                local_irq_save(flags);
-                __smtc_ipi_replay();
-                local_irq_restore(flags);
-        }
-#endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
+        smtc_ipi_replay();
 }
 
 void smtc_soft_dump(void)
@@ -1242,10 +1260,6 @@ void smtc_soft_dump(void)
                 printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
         }
         smtc_ipi_qdump();
-        printk("Timer IPI Backlogs:\n");
-        for (i=0; i < NR_CPUS; i++) {
-                printk("%d: %d\n", i, atomic_read(&ipi_timer_latch[i]));
-        }
         printk("%d Recoveries of \"stolen\" FPU\n",
                atomic_read(&smtc_fpu_recoveries));
 }
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 6bee29097a56..80b9e070c207 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -42,10 +42,14 @@
 #include <asm/tlbdebug.h>
 #include <asm/traps.h>
 #include <asm/uaccess.h>
+#include <asm/watch.h>
 #include <asm/mmu_context.h>
 #include <asm/types.h>
 #include <asm/stacktrace.h>
 
+extern void check_wait(void);
+extern asmlinkage void r4k_wait(void);
+extern asmlinkage void rollback_handle_int(void);
 extern asmlinkage void handle_int(void);
 extern asmlinkage void handle_tlbm(void);
 extern asmlinkage void handle_tlbl(void);
@@ -822,8 +826,10 @@ static void mt_ase_fp_affinity(void)
                 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
                         cpumask_t tmask;
 
-                        cpus_and(tmask, current->thread.user_cpus_allowed,
-                                 mt_fpu_cpumask);
+                        current->thread.user_cpus_allowed
+                                = current->cpus_allowed;
+                        cpus_and(tmask, current->cpus_allowed,
+                                mt_fpu_cpumask);
                         set_cpus_allowed(current, tmask);
                         set_thread_flag(TIF_FPUBOUND);
                 }
@@ -907,13 +913,26 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
 
 asmlinkage void do_watch(struct pt_regs *regs)
 {
+        u32 cause;
+
         /*
-         * We use the watch exception where available to detect stack
-         * overflows.
+         * Clear WP (bit 22) bit of cause register so we don't loop
+         * forever.
          */
-        dump_tlb_all();
-        show_regs(regs);
-        panic("Caught WATCH exception - probably caused by stack overflow.");
+        cause = read_c0_cause();
+        cause &= ~(1 << 22);
+        write_c0_cause(cause);
+
+        /*
+         * If the current thread has the watch registers loaded, save
+         * their values and send SIGTRAP.  Otherwise another thread
+         * left the registers set, clear them and continue.
+         */
+        if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
+                mips_read_watch_registers();
+                force_sig(SIGTRAP, current);
+        } else
+                mips_clear_watch_registers();
 }
 
 asmlinkage void do_mcheck(struct pt_regs *regs)
@@ -1251,6 +1270,9 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 
                 extern char except_vec_vi, except_vec_vi_lui;
                 extern char except_vec_vi_ori, except_vec_vi_end;
+                extern char rollback_except_vec_vi;
+                char *vec_start = (cpu_wait == r4k_wait) ?
+                        &rollback_except_vec_vi : &except_vec_vi;
 #ifdef CONFIG_MIPS_MT_SMTC
                 /*
                  * We need to provide the SMTC vectored interrupt handler
@@ -1258,11 +1280,11 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                  * Status.IM bit to be masked before going there.
                  */
                 extern char except_vec_vi_mori;
-                const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
+                const int mori_offset = &except_vec_vi_mori - vec_start;
 #endif /* CONFIG_MIPS_MT_SMTC */
-                const int handler_len = &except_vec_vi_end - &except_vec_vi;
-                const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
-                const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
+                const int handler_len = &except_vec_vi_end - vec_start;
+                const int lui_offset = &except_vec_vi_lui - vec_start;
+                const int ori_offset = &except_vec_vi_ori - vec_start;
 
                 if (handler_len > VECTORSPACING) {
                         /*
@@ -1272,7 +1294,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                         panic("VECTORSPACING too small");
                 }
 
-                memcpy(b, &except_vec_vi, handler_len);
+                memcpy(b, vec_start, handler_len);
 #ifdef CONFIG_MIPS_MT_SMTC
                 BUG_ON(n > 7);  /* Vector index %d exceeds SMTC maximum. */
 
@@ -1554,6 +1576,10 @@ void __init trap_init(void)
         extern char except_vec3_generic, except_vec3_r4000;
         extern char except_vec4;
         unsigned long i;
+        int rollback;
+
+        check_wait();
+        rollback = (cpu_wait == r4k_wait);
 
 #if defined(CONFIG_KGDB)
         if (kgdb_early_setup)
@@ -1618,7 +1644,7 @@ void __init trap_init(void)
         if (board_be_init)
                 board_be_init();
 
-        set_except_vector(0, handle_int);
+        set_except_vector(0, rollback ? rollback_handle_int : handle_int);
         set_except_vector(1, handle_tlbm);
         set_except_vector(2, handle_tlbl);
         set_except_vector(3, handle_tlbs);
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index b5470ceb418b..afb119f35682 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -36,6 +36,7 @@ SECTIONS
                 SCHED_TEXT
                 LOCK_TEXT
                 KPROBES_TEXT
+                *(.text.*)
                 *(.fixup)
                 *(.gnu.warning)
         } :text = 0
diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
new file mode 100644
index 000000000000..c15406968030
--- /dev/null
+++ b/arch/mips/kernel/watch.c
@@ -0,0 +1,188 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 David Daney
+ */
+
+#include <linux/sched.h>
+
+#include <asm/processor.h>
+#include <asm/watch.h>
+
+/*
+ * Install the watch registers for the current thread.  A maximum of
+ * four registers are installed although the machine may have more.
+ */
+void mips_install_watch_registers(void)
+{
+        struct mips3264_watch_reg_state *watches =
+                &current->thread.watch.mips3264;
+        switch (current_cpu_data.watch_reg_use_cnt) {
+        default:
+                BUG();
+        case 4:
+                write_c0_watchlo3(watches->watchlo[3]);
+                /* Write 1 to the I, R, and W bits to clear them, and
+                   1 to G so all ASIDs are trapped. */
+                write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
+        case 3:
+                write_c0_watchlo2(watches->watchlo[2]);
+                write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
+        case 2:
+                write_c0_watchlo1(watches->watchlo[1]);
+                write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
+        case 1:
+                write_c0_watchlo0(watches->watchlo[0]);
+                write_c0_watchhi0(0x40000007 | watches->watchhi[0]);
+        }
+}
+
+/*
+ * Read back the watchhi registers so the user space debugger has
+ * access to the I, R, and W bits.  A maximum of four registers are
+ * read although the machine may have more.
+ */
+void mips_read_watch_registers(void)
+{
+        struct mips3264_watch_reg_state *watches =
+                &current->thread.watch.mips3264;
+        switch (current_cpu_data.watch_reg_use_cnt) {
+        default:
+                BUG();
+        case 4:
+                watches->watchhi[3] = (read_c0_watchhi3() & 0x0fff);
+        case 3:
+                watches->watchhi[2] = (read_c0_watchhi2() & 0x0fff);
+        case 2:
+                watches->watchhi[1] = (read_c0_watchhi1() & 0x0fff);
+        case 1:
+                watches->watchhi[0] = (read_c0_watchhi0() & 0x0fff);
+        }
+        if (current_cpu_data.watch_reg_use_cnt == 1 &&
+            (watches->watchhi[0] & 7) == 0) {
+                /* Pathological case of release 1 architecture that
+                 * doesn't set the condition bits.  We assume that
+                 * since we got here, the watch condition was met and
+                 * signal that the conditions requested in watchlo
+                 * were met.  */
+                watches->watchhi[0] |= (watches->watchlo[0] & 7);
+        }
+ }
+
+/*
+ * Disable all watch registers.  Although only four registers are
+ * installed, all are cleared to eliminate the possibility of endless
+ * looping in the watch handler.
+ */
+void mips_clear_watch_registers(void)
+{
+        switch (current_cpu_data.watch_reg_count) {
+        default:
+                BUG();
+        case 8:
+                write_c0_watchlo7(0);
+        case 7:
+                write_c0_watchlo6(0);
+        case 6:
+                write_c0_watchlo5(0);
+        case 5:
+                write_c0_watchlo4(0);
+        case 4:
+                write_c0_watchlo3(0);
+        case 3:
+                write_c0_watchlo2(0);
+        case 2:
+                write_c0_watchlo1(0);
+        case 1:
+                write_c0_watchlo0(0);
+        }
+}
+
+__cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
+{
+        unsigned int t;
+
+        if ((c->options & MIPS_CPU_WATCH) == 0)
+                return;
+        /*
+         * Check which of the I,R and W bits are supported, then
+         * disable the register.
+         */
+        write_c0_watchlo0(7);
+        t = read_c0_watchlo0();
+        write_c0_watchlo0(0);
+        c->watch_reg_masks[0] = t & 7;
+
+        /* Write the mask bits and read them back to determine which
+         * can be used. */
+        c->watch_reg_count = 1;
+        c->watch_reg_use_cnt = 1;
+        t = read_c0_watchhi0();
+        write_c0_watchhi0(t | 0xff8);
+        t = read_c0_watchhi0();
+        c->watch_reg_masks[0] |= (t & 0xff8);
+        if ((t & 0x80000000) == 0)
+                return;
+
+        write_c0_watchlo1(7);
+        t = read_c0_watchlo1();
+        write_c0_watchlo1(0);
+        c->watch_reg_masks[1] = t & 7;
+
+        c->watch_reg_count = 2;
+        c->watch_reg_use_cnt = 2;
+        t = read_c0_watchhi1();
+        write_c0_watchhi1(t | 0xff8);
+        t = read_c0_watchhi1();
+        c->watch_reg_masks[1] |= (t & 0xff8);
+        if ((t & 0x80000000) == 0)
+                return;
+
+        write_c0_watchlo2(7);
+        t = read_c0_watchlo2();
+        write_c0_watchlo2(0);
+        c->watch_reg_masks[2] = t & 7;
+
+        c->watch_reg_count = 3;
+        c->watch_reg_use_cnt = 3;
+        t = read_c0_watchhi2();
+        write_c0_watchhi2(t | 0xff8);
+        t = read_c0_watchhi2();
+        c->watch_reg_masks[2] |= (t & 0xff8);
+        if ((t & 0x80000000) == 0)
+                return;
+
+        write_c0_watchlo3(7);
+        t = read_c0_watchlo3();
+        write_c0_watchlo3(0);
+        c->watch_reg_masks[3] = t & 7;
+
+        c->watch_reg_count = 4;
+        c->watch_reg_use_cnt = 4;
+        t = read_c0_watchhi3();
+        write_c0_watchhi3(t | 0xff8);
+        t = read_c0_watchhi3();
+        c->watch_reg_masks[3] |= (t & 0xff8);
+        if ((t & 0x80000000) == 0)
+                return;
+
+        /* We use at most 4, but probe and report up to 8. */
+        c->watch_reg_count = 5;
+        t = read_c0_watchhi4();
+        if ((t & 0x80000000) == 0)
+                return;
+
+        c->watch_reg_count = 6;
+        t = read_c0_watchhi5();
+        if ((t & 0x80000000) == 0)
+                return;
+
+        c->watch_reg_count = 7;
+        t = read_c0_watchhi6();
+        if ((t & 0x80000000) == 0)
+                return;
+
+        c->watch_reg_count = 8;
+}
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 8d7784122c14..6b876ca299ee 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -39,12 +39,14 @@
 #ifdef USE_DOUBLE
 
 #define LOAD   ld
+#define LOAD32 lwu
 #define ADD    daddu
 #define NBYTES 8
 
 #else
 
 #define LOAD   lw
+#define LOAD32 lw
 #define ADD    addu
 #define NBYTES 4
 
@@ -53,12 +55,14 @@
 #define UNIT(unit)  ((unit)*NBYTES)
 
 #define ADDC(sum,reg)                                           \
-        .set    push;                                           \
-        .set    noat;                                           \
         ADD     sum, reg;                                       \
         sltu    v1, sum, reg;                                   \
         ADD     sum, v1;                                        \
-        .set    pop
+
+#define ADDC32(sum,reg)                                         \
+        addu    sum, reg;                                       \
+        sltu    v1, sum, reg;                                   \
+        addu    sum, v1;                                        \
 
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)    \
         LOAD    _t0, (offset + UNIT(0))(src);                   \
@@ -132,7 +136,7 @@ LEAF(csum_partial)
         beqz    t8, .Lqword_align
          andi   t8, src, 0x8
 
-        lw      t0, 0x00(src)
+        LOAD32  t0, 0x00(src)
         LONG_SUBU       a1, a1, 0x4
         ADDC(sum, t0)
         PTR_ADDU        src, src, 0x4
@@ -211,7 +215,7 @@ LEAF(csum_partial)
         LONG_SRL        t8, t8, 0x2
 
 .Lend_words:
-        lw      t0, (src)
+        LOAD32  t0, (src)
         LONG_SUBU       t8, t8, 0x1
         ADDC(sum, t0)
         .set    reorder                         /* DADDI_WAR */
@@ -230,6 +234,9 @@ LEAF(csum_partial)
         /* Still a full word to go  */
         ulw     t1, (src)
         PTR_ADDIU       src, 4
+#ifdef USE_DOUBLE
+        dsll    t1, t1, 32                      /* clear lower 32bit */
+#endif
         ADDC(sum, t1)
 
 1:      move    t1, zero
@@ -254,8 +261,6 @@ LEAF(csum_partial)
 1:      ADDC(sum, t1)
 
         /* fold checksum */
-        .set    push
-        .set    noat
 #ifdef USE_DOUBLE
         dsll32  v1, sum, 0
         daddu   sum, v1
@@ -263,24 +268,25 @@ LEAF(csum_partial)
         dsra32  sum, sum, 0
         addu    sum, v1
 #endif
-        sll     v1, sum, 16
-        addu    sum, v1
-        sltu    v1, sum, v1
-        srl     sum, sum, 16
-        addu    sum, v1
 
         /* odd buffer alignment? */
-        beqz    t7, 1f
-         nop
-        sll     v1, sum, 8
+#ifdef CPU_MIPSR2
+        wsbh    v1, sum
+        movn    sum, v1, t7
+#else
+        beqz    t7, 1f                  /* odd buffer alignment? */
+         lui    v1, 0x00ff
+        addu    v1, 0x00ff
+        and     t0, sum, v1
+        sll     t0, t0, 8
         srl     sum, sum, 8
-        or      sum, v1
-        andi    sum, 0xffff
-        .set    pop
+        and     sum, sum, v1
+        or      sum, sum, t0
 1:
+#endif
         .set    reorder
         /* Add the passed partial csum.  */
-        ADDC(sum, a2)
+        ADDC32(sum, a2)
         jr      ra
         .set    noreorder
         END(csum_partial)
@@ -656,8 +662,6 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
         ADDC(sum, t2)
 .Ldone:
         /* fold checksum */
-        .set    push
-        .set    noat
 #ifdef USE_DOUBLE
         dsll32  v1, sum, 0
         daddu   sum, v1
@@ -665,23 +669,23 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
         dsra32  sum, sum, 0
         addu    sum, v1
 #endif
-        sll     v1, sum, 16
-        addu    sum, v1
-        sltu    v1, sum, v1
-        srl     sum, sum, 16
-        addu    sum, v1
 
-        /* odd buffer alignment? */
-        beqz    odd, 1f
-         nop
-        sll     v1, sum, 8
+#ifdef CPU_MIPSR2
+        wsbh    v1, sum
+        movn    sum, v1, odd
+#else
+        beqz    odd, 1f                 /* odd buffer alignment? */
+         lui    v1, 0x00ff
+        addu    v1, 0x00ff
+        and     t0, sum, v1
+        sll     t0, t0, 8
         srl     sum, sum, 8
-        or      sum, v1
-        andi    sum, 0xffff
-        .set    pop
+        and     sum, sum, v1
+        or      sum, sum, t0
 1:
+#endif
         .set reorder
-        ADDC(sum, psum)
+        ADDC32(sum, psum)
         jr      ra
         .set noreorder
 
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 3b7dd722c32a..cef2db8d2225 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -15,6 +15,6 @@ obj-$(CONFIG_EARLY_PRINTK)	+= malta-console.o
 obj-$(CONFIG_PCI)               += malta-pci.o
 
 # FIXME FIXME FIXME
-obj-$(CONFIG_MIPS_MT_SMTC)      += malta_smtc.o
+obj-$(CONFIG_MIPS_MT_SMTC)      += malta-smtc.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c
index 5ea705e49454..f84a46a8ae6e 100644
--- a/arch/mips/mti-malta/malta-smtc.c
+++ b/arch/mips/mti-malta/malta-smtc.c
@@ -84,12 +84,17 @@ static void msmtc_cpus_done(void)
 
 static void __init msmtc_smp_setup(void)
 {
-        mipsmt_build_cpu_map(0);
+        /*
+         * we won't get the definitive value until
+         * we've run smtc_prepare_cpus later, but
+         * we would appear to need an upper bound now.
+         */
+        smp_num_siblings = smtc_build_cpu_map(0);
 }
 
 static void __init msmtc_prepare_cpus(unsigned int max_cpus)
 {
-        mipsmt_prepare_cpus();
+        smtc_prepare_cpus(max_cpus);
 }
 
 struct plat_smp_ops msmtc_smp_ops = {
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 15e01aec37fd..b1886244cedf 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SOC_TX3927)	+= ops-tx3927.o
 obj-$(CONFIG_PCI_VR41XX)        += ops-vr41xx.o pci-vr41xx.o
 obj-$(CONFIG_MARKEINS)          += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
 obj-$(CONFIG_PCI_TX4927)        += ops-tx4927.o
+obj-$(CONFIG_BCM47XX)           += pci-bcm47xx.o
 
 #
 # These are still pretty much in the old state, watch, go blind.
@@ -44,6 +45,7 @@ obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
 obj-$(CONFIG_TOSHIBA_JMR3927)   += fixup-jmr3927.o
 obj-$(CONFIG_SOC_TX4927)        += pci-tx4927.o
 obj-$(CONFIG_SOC_TX4938)        += pci-tx4938.o
+obj-$(CONFIG_SOC_TX4939)        += pci-tx4939.o
 obj-$(CONFIG_TOSHIBA_RBTX4927)  += fixup-rbtx4927.o
 obj-$(CONFIG_TOSHIBA_RBTX4938)  += fixup-rbtx4938.o
 obj-$(CONFIG_VICTOR_MPC30X)     += fixup-mpc30x.o
diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c
new file mode 100644
index 000000000000..bea9b6cdfdbf
--- /dev/null
+++ b/arch/mips/pci/pci-bcm47xx.c
@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2008 Aurelien Jarno <aurelien@aurel32.net>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/ssb/ssb.h>
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return 0;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        int res;
+        u8 slot, pin;
+
+        res = ssb_pcibios_plat_dev_init(dev);
+        if (res < 0) {
+                printk(KERN_ALERT "PCI: Failed to init device %s\n",
+                       pci_name(dev));
+                return res;
+        }
+
+        pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+        slot = PCI_SLOT(dev->devfn);
+        res = ssb_pcibios_map_irq(dev, slot, pin);
+
+        /* IRQ-0 and IRQ-1 are software interrupts. */
+        if (res < 2) {
+                printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
+                       pci_name(dev));
+                return res;
+        }
+
+        dev->irq = res;
+        return 0;
+}
+
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index bd78368c82bf..f97ab1461012 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -143,25 +143,47 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
  */
 int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
+        return 0;
+}
+
+/* Most MIPS systems have straight-forward swizzling needs.  */
+static inline u8 bridge_swizzle(u8 pin, u8 slot)
+{
+        return (((pin - 1) + slot) % 4) + 1;
+}
+
+static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev)
+{
+        while (dev->bus->parent) {
+                /* Move up the chain of bridges. */
+                dev = dev->bus->self;
+        }
+
+        return dev;
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
-        int irq = bc->pci_int[slot];
+        struct pci_dev *rdev = bridge_root_dev(dev);
+        int slot = PCI_SLOT(rdev->devfn);
+        int irq;
 
+        irq = bc->pci_int[slot];
         if (irq == -1) {
-                irq = bc->pci_int[slot] = request_bridge_irq(bc);
+                irq = request_bridge_irq(bc);
                 if (irq < 0)
-                        panic("Can't allocate interrupt for PCI device %s\n",
-                              pci_name(dev));
+                        return irq;
+
+                bc->pci_int[slot] = irq;
         }
 
         irq_to_bridge[irq] = bc;
         irq_to_slot[irq] = slot;
 
-        return irq;
-}
+        dev->irq = irq;
 
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
         return 0;
 }
 
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
index 60e2c52c2c5e..1ea257bc3b8f 100644
--- a/arch/mips/pci/pci-tx4938.c
+++ b/arch/mips/pci/pci-tx4938.c
@@ -114,7 +114,7 @@ int __init tx4938_pciclk66_setup(void)
         return pciclk;
 }
 
-int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
+int __init tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
 {
         if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) {
                 switch (slot) {
diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c
new file mode 100644
index 000000000000..5fecf1cdc325
--- /dev/null
+++ b/arch/mips/pci/pci-tx4939.c
@@ -0,0 +1,109 @@
+/*
+ * linux/arch/mips/pci/pci-tx4939.c
+ *
+ * Based on linux/arch/mips/txx9/rbtx4939/setup.c,
+ *          and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright 2001, 2003-2005 MontaVista Software Inc.
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4939.h>
+
+int __init tx4939_report_pciclk(void)
+{
+        int pciclk = 0;
+
+        pr_info("PCIC --%s PCICLK:",
+                (__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66) ?
+                " PCI66" : "");
+        if (__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_PCICLKEN_ALL) {
+                pciclk = txx9_master_clock * 20 / 6;
+                if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
+                        pciclk /= 2;
+                printk(KERN_CONT "Internal(%u.%uMHz)",
+                       (pciclk + 50000) / 1000000,
+                       ((pciclk + 50000) / 100000) % 10);
+        } else {
+                printk(KERN_CONT "External");
+                pciclk = -1;
+        }
+        printk(KERN_CONT "\n");
+        return pciclk;
+}
+
+void __init tx4939_report_pci1clk(void)
+{
+        unsigned int pciclk = txx9_master_clock * 20 / 6;
+
+        pr_info("PCIC1 -- PCICLK:%u.%uMHz\n",
+                (pciclk + 50000) / 1000000,
+                ((pciclk + 50000) / 100000) % 10);
+}
+
+int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
+{
+        if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {
+                switch (slot) {
+                case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
+                        if (__raw_readq(&tx4939_ccfgptr->pcfg) &
+                            TX4939_PCFG_ET0MODE)
+                                return TXX9_IRQ_BASE + TX4939_IR_ETH(0);
+                        break;
+                case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
+                        if (__raw_readq(&tx4939_ccfgptr->pcfg) &
+                            TX4939_PCFG_ET1MODE)
+                                return TXX9_IRQ_BASE + TX4939_IR_ETH(1);
+                        break;
+                }
+                return 0;
+        }
+        return -1;
+}
+
+int __init tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq = tx4939_pcic1_map_irq(dev, slot);
+
+        if (irq >= 0)
+                return irq;
+        irq = pin;
+        /* IRQ rotation */
+        irq--;  /* 0-3 */
+        irq = (irq + 33 - slot) % 4;
+        irq++;  /* 1-4 */
+
+        switch (irq) {
+        case 1:
+                irq = TXX9_IRQ_BASE + TX4939_IR_INTA;
+                break;
+        case 2:
+                irq = TXX9_IRQ_BASE + TX4939_IR_INTB;
+                break;
+        case 3:
+                irq = TXX9_IRQ_BASE + TX4939_IR_INTC;
+                break;
+        case 4:
+                irq = TXX9_IRQ_BASE + TX4939_IR_INTD;
+                break;
+        }
+        return irq;
+}
+
+void __init tx4939_setup_pcierr_irq(void)
+{
+        if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
+                        tx4927_pcierr_interrupt,
+                        IRQF_DISABLED, "PCI error",
+                        (void *)TX4939_PCIC_REG))
+                pr_warning("Failed to request irq for PCIERR\n");
+}
diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile
index 4bba79c1cc79..e107f79b1491 100644
--- a/arch/mips/pmc-sierra/msp71xx/Makefile
+++ b/arch/mips/pmc-sierra/msp71xx/Makefile
@@ -3,6 +3,7 @@
 #
 obj-y += msp_prom.o msp_setup.o msp_irq.o \
          msp_time.o msp_serial.o msp_elb.o
+obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o
 obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
 obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
 obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o
diff --git a/arch/mips/pmc-sierra/msp71xx/gpio.c b/arch/mips/pmc-sierra/msp71xx/gpio.c
new file mode 100644
index 000000000000..69848c5813e2
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/gpio.c
@@ -0,0 +1,218 @@
+/*
+ * @file /arch/mips/pmc-sierra/msp71xx/gpio.c
+ *
+ * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two
+ * types of registers. The data register sets the output level when in output
+ * mode and when in input mode will contain the value at the input. The config
+ * register sets the various modes for each gpio.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * @author Patrick Glass <patrickglass@gmail.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+
+#define MSP71XX_CFG_OFFSET(gpio)        (4 * (gpio))
+#define CONF_MASK                       0x0F
+#define MSP71XX_GPIO_INPUT              0x01
+#define MSP71XX_GPIO_OUTPUT             0x08
+
+#define MSP71XX_GPIO_BASE               0x0B8400000L
+
+#define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip)
+
+static spinlock_t gpio_lock;
+
+/*
+ * struct msp71xx_gpio_chip - container for gpio chip and registers
+ * @chip: chip structure for the specified gpio bank
+ * @data_reg: register for reading and writing the gpio pin value
+ * @config_reg: register to set the mode for the gpio pin bank
+ * @out_drive_reg: register to set the output drive mode for the gpio pin bank
+ */
+struct msp71xx_gpio_chip {
+        struct gpio_chip chip;
+        void __iomem *data_reg;
+        void __iomem *config_reg;
+        void __iomem *out_drive_reg;
+};
+
+/*
+ * msp71xx_gpio_get() - return the chip's gpio value
+ * @chip: chip structure which controls the specified gpio
+ * @offset: gpio whose value will be returned
+ *
+ * It will return 0 if gpio value is low and other if high.
+ */
+static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
+
+        return __raw_readl(msp_chip->data_reg) & (1 << offset);
+}
+
+/*
+ * msp71xx_gpio_set() - set the output value for the gpio
+ * @chip: chip structure who controls the specified gpio
+ * @offset: gpio whose value will be assigned
+ * @value: logic level to assign to the gpio initially
+ *
+ * This will set the gpio bit specified to the desired value. It will set the
+ * gpio pin low if value is 0 otherwise it will be high.
+ */
+static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
+        unsigned long flags;
+        u32 data;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        data = __raw_readl(msp_chip->data_reg);
+        if (value)
+                data |= (1 << offset);
+        else
+                data &= ~(1 << offset);
+        __raw_writel(data, msp_chip->data_reg);
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+}
+
+/*
+ * msp71xx_set_gpio_mode() - declare the mode for a gpio
+ * @chip: chip structure which controls the specified gpio
+ * @offset: gpio whose value will be assigned
+ * @mode: desired configuration for the gpio (see datasheet)
+ *
+ * It will set the gpio pin config to the @mode value passed in.
+ */
+static int msp71xx_set_gpio_mode(struct gpio_chip *chip,
+                                 unsigned offset, int mode)
+{
+        struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
+        const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset);
+        unsigned long flags;
+        u32 cfg;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        cfg = __raw_readl(msp_chip->config_reg);
+        cfg &= ~(CONF_MASK << bit_offset);
+        cfg |= (mode << bit_offset);
+        __raw_writel(cfg, msp_chip->config_reg);
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+
+        return 0;
+}
+
+/*
+ * msp71xx_direction_output() - declare the direction mode for a gpio
+ * @chip: chip structure which controls the specified gpio
+ * @offset: gpio whose value will be assigned
+ * @value: logic level to assign to the gpio initially
+ *
+ * This call will set the mode for the @gpio to output. It will set the
+ * gpio pin low if value is 0 otherwise it will be high.
+ */
+static int msp71xx_direction_output(struct gpio_chip *chip,
+                                    unsigned offset, int value)
+{
+        msp71xx_gpio_set(chip, offset, value);
+
+        return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT);
+}
+
+/*
+ * msp71xx_direction_input() - declare the direction mode for a gpio
+ * @chip: chip structure which controls the specified gpio
+ * @offset: gpio whose to which the value will be assigned
+ *
+ * This call will set the mode for the @gpio to input.
+ */
+static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT);
+}
+
+/*
+ * msp71xx_set_output_drive() - declare the output drive for the gpio line
+ * @gpio: gpio pin whose output drive you wish to modify
+ * @value: zero for active drain 1 for open drain drive
+ *
+ * This call will set the output drive mode for the @gpio to output.
+ */
+int msp71xx_set_output_drive(unsigned gpio, int value)
+{
+        unsigned long flags;
+        u32 data;
+
+        if (gpio > 15 || gpio < 0)
+                return -EINVAL;
+
+        spin_lock_irqsave(&gpio_lock, flags);
+
+        data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
+        if (value)
+                data |= (1 << gpio);
+        else
+                data &= ~(1 << gpio);
+        __raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
+
+        spin_unlock_irqrestore(&gpio_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(msp71xx_set_output_drive);
+
+#define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \
+{ \
+        .chip = { \
+                .label            = name, \
+                .direction_input  = msp71xx_direction_input, \
+                .direction_output = msp71xx_direction_output, \
+                .get              = msp71xx_gpio_get, \
+                .set              = msp71xx_gpio_set, \
+                .base             = base_gpio, \
+                .ngpio            = num_gpio \
+        }, \
+        .data_reg       = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \
+        .config_reg     = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \
+        .out_drive_reg  = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \
+}
+
+/*
+ * struct msp71xx_gpio_banks[] - container array of gpio banks
+ * @chip: chip structure for the specified gpio bank
+ * @data_reg: register for reading and writing the gpio pin value
+ * @config_reg: register to set the mode for the gpio pin bank
+ *
+ * This array structure defines the gpio banks for the PMC MIPS Processor.
+ * We specify the bank name, the data register, the config register, base
+ * starting gpio number, and the number of gpios exposed by the bank.
+ */
+static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = {
+
+        MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2),
+        MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4),
+        MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4),
+        MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6),
+};
+
+void __init msp71xx_init_gpio(void)
+{
+        int i;
+
+        spin_lock_init(&gpio_lock);
+
+        for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++)
+                gpiochip_add(&msp71xx_gpio_banks[i].chip);
+}
diff --git a/arch/mips/pmc-sierra/msp71xx/gpio_extended.c b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c
new file mode 100644
index 000000000000..fc6dbc6cf1c0
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c
@@ -0,0 +1,148 @@
+/*
+ * @file /arch/mips/pmc-sierra/msp71xx/gpio_extended.c
+ *
+ * Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is
+ * a set of hardware registers that have no need for explicit locking as
+ * it is handled by unique method of writing individual set/clr bits.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * @author Patrick Glass <patrickglass@gmail.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#define MSP71XX_DATA_OFFSET(gpio)       (2 * (gpio))
+#define MSP71XX_READ_OFFSET(gpio)       (MSP71XX_DATA_OFFSET(gpio) + 1)
+#define MSP71XX_CFG_OUT_OFFSET(gpio)    (MSP71XX_DATA_OFFSET(gpio) + 16)
+#define MSP71XX_CFG_IN_OFFSET(gpio)     (MSP71XX_CFG_OUT_OFFSET(gpio) + 1)
+
+#define MSP71XX_EXD_GPIO_BASE   0x0BC000000L
+
+#define to_msp71xx_exd_gpio_chip(c) \
+                        container_of(c, struct msp71xx_exd_gpio_chip, chip)
+
+/*
+ * struct msp71xx_exd_gpio_chip - container for gpio chip and registers
+ * @chip: chip structure for the specified gpio bank
+ * @reg: register for control and data of gpio pin
+ */
+struct msp71xx_exd_gpio_chip {
+        struct gpio_chip chip;
+        void __iomem *reg;
+};
+
+/*
+ * msp71xx_exd_gpio_get() - return the chip's gpio value
+ * @chip: chip structure which controls the specified gpio
+ * @offset: gpio whose value will be returned
+ *
+ * It will return 0 if gpio value is low and other if high.
+ */
+static int msp71xx_exd_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct msp71xx_exd_gpio_chip *msp71xx_chip =
+            to_msp71xx_exd_gpio_chip(chip);
+        const unsigned bit = MSP71XX_READ_OFFSET(offset);
+
+        return __raw_readl(msp71xx_chip->reg) & (1 << bit);
+}
+
+/*
+ * msp71xx_exd_gpio_set() - set the output value for the gpio
+ * @chip: chip structure who controls the specified gpio
+ * @offset: gpio whose value will be assigned
+ * @value: logic level to assign to the gpio initially
+ *
+ * This will set the gpio bit specified to the desired value. It will set the
+ * gpio pin low if value is 0 otherwise it will be high.
+ */
+static void msp71xx_exd_gpio_set(struct gpio_chip *chip,
+                                 unsigned offset, int value)
+{
+        struct msp71xx_exd_gpio_chip *msp71xx_chip =
+            to_msp71xx_exd_gpio_chip(chip);
+        const unsigned bit = MSP71XX_DATA_OFFSET(offset);
+
+        __raw_writel(1 << (bit + (value ? 1 : 0)), msp71xx_chip->reg);
+}
+
+/*
+ * msp71xx_exd_direction_output() - declare the direction mode for a gpio
+ * @chip: chip structure which controls the specified gpio
+ * @offset: gpio whose value will be assigned
+ * @value: logic level to assign to the gpio initially
+ *
+ * This call will set the mode for the @gpio to output. It will set the
+ * gpio pin low if value is 0 otherwise it will be high.
+ */
+static int msp71xx_exd_direction_output(struct gpio_chip *chip,
+                                        unsigned offset, int value)
+{
+        struct msp71xx_exd_gpio_chip *msp71xx_chip =
+            to_msp71xx_exd_gpio_chip(chip);
+
+        msp71xx_exd_gpio_set(chip, offset, value);
+        __raw_writel(1 << MSP71XX_CFG_OUT_OFFSET(offset), msp71xx_chip->reg);
+        return 0;
+}
+
+/*
+ * msp71xx_exd_direction_input() - declare the direction mode for a gpio
+ * @chip: chip structure which controls the specified gpio
+ * @offset: gpio whose to which the value will be assigned
+ *
+ * This call will set the mode for the @gpio to input.
+ */
+static int msp71xx_exd_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct msp71xx_exd_gpio_chip *msp71xx_chip =
+            to_msp71xx_exd_gpio_chip(chip);
+
+        __raw_writel(1 << MSP71XX_CFG_IN_OFFSET(offset), msp71xx_chip->reg);
+        return 0;
+}
+
+#define MSP71XX_EXD_GPIO_BANK(name, exd_reg, base_gpio, num_gpio) \
+{ \
+        .chip = { \
+                .label            = name, \
+                .direction_input  = msp71xx_exd_direction_input, \
+                .direction_output = msp71xx_exd_direction_output, \
+                .get              = msp71xx_exd_gpio_get, \
+                .set              = msp71xx_exd_gpio_set, \
+                .base             = base_gpio, \
+                .ngpio            = num_gpio, \
+        }, \
+        .reg    = (void __iomem *)(MSP71XX_EXD_GPIO_BASE + exd_reg), \
+}
+
+/*
+ * struct msp71xx_exd_gpio_banks[] - container array of gpio banks
+ * @chip: chip structure for the specified gpio bank
+ * @reg: register for reading and writing the gpio pin value
+ *
+ * This array structure defines the extended gpio banks for the
+ * PMC MIPS Processor. We specify the bank name, the data/config
+ * register,the base starting gpio number, and the number of
+ * gpios exposed by the bank of gpios.
+ */
+static struct msp71xx_exd_gpio_chip msp71xx_exd_gpio_banks[] = {
+
+        MSP71XX_EXD_GPIO_BANK("GPIO_23_16", 0x188, 16, 8),
+        MSP71XX_EXD_GPIO_BANK("GPIO_27_24", 0x18C, 24, 4),
+};
+
+void __init msp71xx_init_gpio_extended(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(msp71xx_exd_gpio_banks); i++)
+                gpiochip_add(&msp71xx_exd_gpio_banks[i].chip);
+}
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 82ab395efa33..31619c601b11 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -34,21 +34,11 @@
 #include <asm/mach-rc32434/rb.h>
 #include <asm/mach-rc32434/integ.h>
 #include <asm/mach-rc32434/gpio.h>
-
-#define ETH0_DMA_RX_IRQ         (GROUP1_IRQ_BASE + 0)
-#define ETH0_DMA_TX_IRQ         (GROUP1_IRQ_BASE + 1)
-#define ETH0_RX_OVR_IRQ         (GROUP3_IRQ_BASE + 9)
-#define ETH0_TX_UND_IRQ         (GROUP3_IRQ_BASE + 10)
+#include <asm/mach-rc32434/irq.h>
 
 #define ETH0_RX_DMA_ADDR  (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
 #define ETH0_TX_DMA_ADDR  (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
 
-/* NAND definitions */
-#define GPIO_RDY (1 << 0x08)
-#define GPIO_WPX (1 << 0x09)
-#define GPIO_ALE (1 << 0x0a)
-#define GPIO_CLE (1 << 0x0b)
-
 static struct resource korina_dev0_res[] = {
         {
                 .name = "korina_regs",
@@ -94,15 +84,13 @@ static struct korina_device korina_dev0_data = {
 };
 
 static struct platform_device korina_dev0 = {
-        .id = 0,
+        .id = -1,
         .name = "korina",
         .dev.platform_data = &korina_dev0_data,
         .resource = korina_dev0_res,
         .num_resources = ARRAY_SIZE(korina_dev0_res),
 };
 
-#define CF_GPIO_NUM 13
-
 static struct resource cf_slot0_res[] = {
         {
                 .name = "cf_membase",
@@ -116,11 +104,11 @@ static struct resource cf_slot0_res[] = {
 };
 
 static struct cf_device cf_slot0_data = {
-        .gpio_pin = 13
+        .gpio_pin = CF_GPIO_NUM
 };
 
 static struct platform_device cf_slot0 = {
-        .id = 0,
+        .id = -1,
         .name = "pata-rb532-cf",
         .dev.platform_data = &cf_slot0_data,
         .resource = cf_slot0_res,
@@ -185,7 +173,7 @@ static struct mtd_partition rb532_partition_info[] = {
 
 static struct platform_device rb532_led = {
         .name = "rb532-led",
-        .id = 0,
+        .id = -1,
 };
 
 static struct gpio_keys_button rb532_gpio_btn[] = {
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 00a1c7877bf4..76a7fd96d564 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -27,28 +27,31 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/types.h>
-#include <linux/pci.h>
 #include <linux/spinlock.h>
-#include <linux/io.h>
 #include <linux/platform_device.h>
-
-#include <asm/addrspace.h>
+#include <linux/gpio.h>
 
 #include <asm/mach-rc32434/rb.h>
-
-struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
-EXPORT_SYMBOL(rb532_gpio_reg0);
+#include <asm/mach-rc32434/gpio.h>
+
+struct rb532_gpio_chip {
+        struct gpio_chip chip;
+        void __iomem     *regbase;
+        void            (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value);
+        int             (*get_int_level)(struct gpio_chip *chip, unsigned offset);
+        void            (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value);
+        int             (*get_int_status)(struct gpio_chip *chip, unsigned offset);
+};
 
 struct mpmc_device dev3;
 
 static struct resource rb532_gpio_reg0_res[] = {
         {
                 .name   = "gpio_reg0",
-                .start  = (u32)(IDT434_REG_BASE + GPIOBASE),
-                .end    = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)),
+                .start  = REGBASE + GPIOBASE,
+                .end    = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -56,8 +59,8 @@ static struct resource rb532_gpio_reg0_res[] = {
 static struct resource rb532_dev3_ctl_res[] = {
         {
                 .name   = "dev3_ctl",
-                .start  = (u32)(IDT434_REG_BASE + DEV3BASE),
-                .end    = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)),
+                .start  = REGBASE + DEV3BASE,
+                .end    = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
                 .flags  = IORESOURCE_MEM,
         }
 };
@@ -70,7 +73,7 @@ void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
 
         spin_lock_irqsave(&dev3.lock, flags);
 
-        data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs);
+        data = readl(IDT434_REG_BASE + reg_offs);
         for (i = 0; i != len; ++i) {
                 if (val & (1 << i))
                         data |= (1 << (i + bit));
@@ -108,108 +111,199 @@ unsigned char get_latch_u5(void)
 }
 EXPORT_SYMBOL(get_latch_u5);
 
-int rb532_gpio_get_value(unsigned gpio)
+/*
+ * Return GPIO level */
+static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
+        u32                     mask = 1 << offset;
+        struct rb532_gpio_chip  *gpch;
+
+        gpch = container_of(chip, struct rb532_gpio_chip, chip);
+        return readl(gpch->regbase + GPIOD) & mask;
 }
-EXPORT_SYMBOL(rb532_gpio_get_value);
 
-void rb532_gpio_set_value(unsigned gpio, int value)
+/*
+ * Set output GPIO level
+ */
+static void rb532_gpio_set(struct gpio_chip *chip,
+                                unsigned offset, int value)
 {
-        unsigned tmp;
+        unsigned long           flags;
+        u32                     mask = 1 << offset;
+        u32                     tmp;
+        struct rb532_gpio_chip  *gpch;
+        void __iomem            *gpvr;
 
-        tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
-        if (value)
-                tmp |= 1 << gpio;
+        gpch = container_of(chip, struct rb532_gpio_chip, chip);
+        gpvr = gpch->regbase + GPIOD;
 
-        writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
+        local_irq_save(flags);
+        tmp = readl(gpvr);
+        if (value)
+                tmp |= mask;
+        else
+                tmp &= ~mask;
+        writel(tmp, gpvr);
+        local_irq_restore(flags);
 }
-EXPORT_SYMBOL(rb532_gpio_set_value);
 
-int rb532_gpio_direction_input(unsigned gpio)
+/*
+ * Set GPIO direction to input
+ */
+static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
-        writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
-               (void *)&rb532_gpio_reg0->gpiocfg);
+        unsigned long           flags;
+        u32                     mask = 1 << offset;
+        u32                     value;
+        struct rb532_gpio_chip  *gpch;
+        void __iomem            *gpdr;
 
-        return 0;
-}
-EXPORT_SYMBOL(rb532_gpio_direction_input);
+        gpch = container_of(chip, struct rb532_gpio_chip, chip);
+        gpdr = gpch->regbase + GPIOCFG;
 
-int rb532_gpio_direction_output(unsigned gpio, int value)
-{
-        gpio_set_value(gpio, value);
-        writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
-               (void *)&rb532_gpio_reg0->gpiocfg);
+        local_irq_save(flags);
+        value = readl(gpdr);
+        value &= ~mask;
+        writel(value, gpdr);
+        local_irq_restore(flags);
 
         return 0;
 }
-EXPORT_SYMBOL(rb532_gpio_direction_output);
 
-void rb532_gpio_set_int_level(unsigned gpio, int value)
+/*
+ * Set GPIO direction to output
+ */
+static int rb532_gpio_direction_output(struct gpio_chip *chip,
+                                        unsigned offset, int value)
 {
-        unsigned tmp;
+        unsigned long           flags;
+        u32                     mask = 1 << offset;
+        u32                     tmp;
+        struct rb532_gpio_chip  *gpch;
+        void __iomem            *gpdr;
+
+        gpch = container_of(chip, struct rb532_gpio_chip, chip);
+        writel(mask, gpch->regbase + GPIOD);
+        gpdr = gpch->regbase + GPIOCFG;
+
+        local_irq_save(flags);
+        tmp = readl(gpdr);
+        tmp |= mask;
+        writel(tmp, gpdr);
+        local_irq_restore(flags);
 
-        tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
-        if (value)
-                tmp |= 1 << gpio;
-        writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
+        return 0;
 }
-EXPORT_SYMBOL(rb532_gpio_set_int_level);
 
-int rb532_gpio_get_int_level(unsigned gpio)
+/*
+ * Set the GPIO interrupt level
+ */
+static void rb532_gpio_set_int_level(struct gpio_chip *chip,
+                                        unsigned offset, int value)
 {
-        return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
-}
-EXPORT_SYMBOL(rb532_gpio_get_int_level);
+        unsigned long           flags;
+        u32                     mask = 1 << offset;
+        u32                     tmp;
+        struct rb532_gpio_chip  *gpch;
+        void __iomem            *gpil;
 
-void rb532_gpio_set_int_status(unsigned gpio, int value)
-{
-        unsigned tmp;
+        gpch = container_of(chip, struct rb532_gpio_chip, chip);
+        gpil = gpch->regbase + GPIOILEVEL;
 
-        tmp = readl(&rb532_gpio_reg0->gpioistat);
+        local_irq_save(flags);
+        tmp = readl(gpil);
         if (value)
-                tmp |= 1 << gpio;
-        writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
+                tmp |= mask;
+        else
+                tmp &= ~mask;
+        writel(tmp, gpil);
+        local_irq_restore(flags);
 }
-EXPORT_SYMBOL(rb532_gpio_set_int_status);
 
-int rb532_gpio_get_int_status(unsigned gpio)
+/*
+ * Get the GPIO interrupt level
+ */
+static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset)
 {
-        return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
+        u32                     mask = 1 << offset;
+        struct rb532_gpio_chip  *gpch;
+
+        gpch = container_of(chip, struct rb532_gpio_chip, chip);
+        return readl(gpch->regbase + GPIOILEVEL) & mask;
 }
-EXPORT_SYMBOL(rb532_gpio_get_int_status);
 
-void rb532_gpio_set_func(unsigned gpio, int value)
+/*
+ * Set the GPIO interrupt status
+ */
+static void rb532_gpio_set_int_status(struct gpio_chip *chip,
+                                unsigned offset, int value)
 {
-        unsigned tmp;
+        unsigned long           flags;
+        u32                     mask = 1 << offset;
+        u32                     tmp;
+        struct rb532_gpio_chip  *gpch;
+        void __iomem            *gpis;
+
+        gpch = container_of(chip, struct rb532_gpio_chip, chip);
+        gpis = gpch->regbase + GPIOISTAT;
 
-        tmp = readl(&rb532_gpio_reg0->gpiofunc);
+        local_irq_save(flags);
+        tmp = readl(gpis);
         if (value)
-                tmp |= 1 << gpio;
-        writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
+                tmp |= mask;
+        else
+                tmp &= ~mask;
+        writel(tmp, gpis);
+        local_irq_restore(flags);
 }
-EXPORT_SYMBOL(rb532_gpio_set_func);
 
-int rb532_gpio_get_func(unsigned gpio)
+/*
+ * Get the GPIO interrupt status
+ */
+static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset)
 {
-        return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
+        u32                     mask = 1 << offset;
+        struct rb532_gpio_chip  *gpch;
+
+        gpch = container_of(chip, struct rb532_gpio_chip, chip);
+        return readl(gpch->regbase + GPIOISTAT) & mask;
 }
-EXPORT_SYMBOL(rb532_gpio_get_func);
+
+static struct rb532_gpio_chip rb532_gpio_chip[] = {
+        [0] = {
+                .chip = {
+                        .label                  = "gpio0",
+                        .direction_input        = rb532_gpio_direction_input,
+                        .direction_output       = rb532_gpio_direction_output,
+                        .get                    = rb532_gpio_get,
+                        .set                    = rb532_gpio_set,
+                        .base                   = 0,
+                        .ngpio                  = 32,
+                },
+                .get_int_level          = rb532_gpio_get_int_level,
+                .set_int_level          = rb532_gpio_set_int_level,
+                .get_int_status         = rb532_gpio_get_int_status,
+                .set_int_status         = rb532_gpio_set_int_status,
+        },
+};
 
 int __init rb532_gpio_init(void)
 {
-        rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
-                                rb532_gpio_reg0_res[0].end -
-                                rb532_gpio_reg0_res[0].start);
+        struct resource *r;
 
-        if (!rb532_gpio_reg0) {
+        r = rb532_gpio_reg0_res;
+        rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);
+
+        if (!rb532_gpio_chip->regbase) {
                 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
                 return -ENXIO;
         }
 
-        dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
-                                rb532_dev3_ctl_res[0].end -
-                                rb532_dev3_ctl_res[0].start);
+        /* Register our GPIO chip */
+        gpiochip_add(&rb532_gpio_chip->chip);
+
+        r = rb532_dev3_ctl_res;
+        dev3.base = ioremap_nocache(r->start, r->end - r->start);
 
         if (!dev3.base) {
                 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index c0d0f950caf2..549b46d2fcee 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -45,7 +45,7 @@
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 
-#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/irq.h>
 
 struct intr_group {
         u32 mask;       /* mask of valid bits in pending/mask registers */
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index 1bc0af8febf4..46ca24dbcc2d 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -37,12 +37,8 @@
 #include <asm/mach-rc32434/ddr.h>
 #include <asm/mach-rc32434/prom.h>
 
-extern void __init setup_serial_port(void);
-
 unsigned int idt_cpu_freq = 132000000;
 EXPORT_SYMBOL(idt_cpu_freq);
-unsigned int gpio_bootup_state;
-EXPORT_SYMBOL(gpio_bootup_state);
 
 static struct resource ddr_reg[] = {
         {
@@ -108,9 +104,6 @@ void __init prom_setup_cmdline(void)
                                 mips_machtype = MACH_MIKROTIK_RB532;
                 }
 
-                if (match_tag(prom_argv[i], GPIO_TAG))
-                        gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
-
                 strcpy(cp, prom_argv[i]);
                 cp += strlen(prom_argv[i]);
         }
@@ -122,11 +115,6 @@ void __init prom_setup_cmdline(void)
                 strcpy(cp, arcs_cmdline);
                 cp += strlen(arcs_cmdline);
         }
-        if (gpio_bootup_state & 0x02)
-                strcpy(cp, GPIO_INIT_NOBUTTON);
-        else
-                strcpy(cp, GPIO_INIT_BUTTON);
-
         cmd_line[CL_SIZE-1] = '\0';
 
         strcpy(arcs_cmdline, cmd_line);
diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
index 1a05b5ddee09..3e0d7ec3a579 100644
--- a/arch/mips/rb532/serial.c
+++ b/arch/mips/rb532/serial.c
@@ -31,16 +31,16 @@
 #include <linux/serial_8250.h>
 
 #include <asm/serial.h>
-#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/rb.h>
 
 extern unsigned int idt_cpu_freq;
 
 static struct uart_port rb532_uart = {
         .type = PORT_16550A,
         .line = 0,
-        .irq = RC32434_UART0_IRQ,
+        .irq = UART0_IRQ,
         .iotype = UPIO_MEM,
-        .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE),
+        .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
         .regshift = 2
 };
 
diff --git a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c
index 7aafa95ac20b..50f530f5b602 100644
--- a/arch/mips/rb532/setup.c
+++ b/arch/mips/rb532/setup.c
@@ -9,7 +9,7 @@
 #include <asm/time.h>
 #include <linux/ioport.h>
 
-#include <asm/mach-rc32434/rc32434.h>
+#include <asm/mach-rc32434/rb.h>
 #include <asm/mach-rc32434/pci.h>
 
 struct pci_reg __iomem *pci_reg;
@@ -27,7 +27,7 @@ static struct resource pci0_res[] = {
 static void rb_machine_restart(char *command)
 {
         /* just jump to the reset vector */
-        writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST));
+        writel(0x80000001, IDT434_REG_BASE + RST);
         ((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
 }
 
diff --git a/arch/mips/sibyte/swarm/Makefile b/arch/mips/sibyte/swarm/Makefile
index f18ba9201bbc..7b45f199d92a 100644
--- a/arch/mips/sibyte/swarm/Makefile
+++ b/arch/mips/sibyte/swarm/Makefile
@@ -1,3 +1,4 @@
-obj-y                           := setup.o rtc_xicor1241.o rtc_m41t81.o
+obj-y                           := platform.o setup.o rtc_xicor1241.o \
+                                   rtc_m41t81.o
 
 obj-$(CONFIG_I2C_BOARDINFO)     += swarm-i2c.o
diff --git a/arch/mips/sibyte/swarm/platform.c b/arch/mips/sibyte/swarm/platform.c
new file mode 100644
index 000000000000..54847fe1e564
--- /dev/null
+++ b/arch/mips/sibyte/swarm/platform.c
@@ -0,0 +1,85 @@
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+
+#include <asm/sibyte/board.h>
+#include <asm/sibyte/sb1250_genbus.h>
+#include <asm/sibyte/sb1250_regs.h>
+
+#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_LITTLESUR)
+
+#define DRV_NAME        "pata-swarm"
+
+#define SWARM_IDE_SHIFT 5
+#define SWARM_IDE_BASE  0x1f0
+#define SWARM_IDE_CTRL  0x3f6
+
+static struct resource swarm_pata_resource[] = {
+        {
+                .name   = "Swarm GenBus IDE",
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "Swarm GenBus IDE",
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "Swarm GenBus IDE",
+                .flags  = IORESOURCE_IRQ,
+                .start  = K_INT_GB_IDE,
+                .end    = K_INT_GB_IDE,
+        },
+};
+
+static struct pata_platform_info pata_platform_data = {
+        .ioport_shift   = SWARM_IDE_SHIFT,
+};
+
+static struct platform_device swarm_pata_device = {
+        .name           = "pata_platform",
+        .id             = -1,
+        .resource       = swarm_pata_resource,
+        .num_resources  = ARRAY_SIZE(swarm_pata_resource),
+        .dev  = {
+                .platform_data          = &pata_platform_data,
+                .coherent_dma_mask      = ~0,   /* grumble */
+        },
+};
+
+static int __init swarm_pata_init(void)
+{
+        u8 __iomem *base;
+        phys_t offset, size;
+        struct resource *r;
+
+        if (!SIBYTE_HAVE_IDE)
+                return -ENODEV;
+
+        base = ioremap(A_IO_EXT_BASE, 0x800);
+        offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS));
+        size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS));
+        iounmap(base);
+
+        offset = G_IO_START_ADDR(offset) << S_IO_ADDRBASE;
+        size = (G_IO_MULT_SIZE(size) + 1) << S_IO_REGSIZE;
+        if (offset < A_PHYS_GENBUS || offset >= A_PHYS_GENBUS_END) {
+                pr_info(DRV_NAME ": PATA interface at GenBus disabled\n");
+
+                return -EBUSY;
+        }
+
+        pr_info(DRV_NAME ": PATA interface at GenBus slot %i\n", IDE_CS);
+
+        r = swarm_pata_resource;
+        r[0].start = offset + (SWARM_IDE_BASE << SWARM_IDE_SHIFT);
+        r[0].end   = offset + ((SWARM_IDE_BASE + 8) << SWARM_IDE_SHIFT) - 1;
+        r[1].start = offset + (SWARM_IDE_CTRL << SWARM_IDE_SHIFT);
+        r[1].end   = offset + ((SWARM_IDE_CTRL + 1) << SWARM_IDE_SHIFT) - 1;
+
+        return platform_device_register(&swarm_pata_device);
+}
+
+device_initcall(swarm_pata_init);
+
+#endif /* defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_LITTLESUR) */
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 840fe757c48d..17052db4161d 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -45,6 +45,14 @@ config TOSHIBA_RBTX4938
           This Toshiba board is based on the TX4938 processor. Say Y here to
           support this machine type
 
+config TOSHIBA_RBTX4939
+        bool "Toshiba RBTX4939 bobard"
+        depends on MACH_TX49XX
+        select SOC_TX4939
+        help
+          This Toshiba board is based on the TX4939 processor. Say Y here to
+          support this machine type
+
 config SOC_TX3927
         bool
         select CEVT_TXX9
@@ -71,6 +79,13 @@ config SOC_TX4938
         select PCI_TX4927
         select GPIO_TXX9
 
+config SOC_TX4939
+        bool
+        select CEVT_TXX9
+        select HAS_TXX9_SERIAL
+        select HW_HAS_PCI
+        select PCI_TX4927
+
 config TOSHIBA_FPCIB0
         bool "FPCIB0 Backplane Support"
         depends on PCI && MACH_TXX9
@@ -94,16 +109,11 @@ config TOSHIBA_RBTX4938_MPLEX_NAND
         bool "NAND"
 config TOSHIBA_RBTX4938_MPLEX_ATA
         bool "ATA"
+config TOSHIBA_RBTX4938_MPLEX_KEEP
+        bool "Keep firmware settings"
 
 endchoice
 
-config TX4938_NAND_BOOT
-        depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND
-        bool "NAND Boot Support (EXPERIMENTAL)"
-        help
-          This is only for Toshiba RBTX4938 reference board, which has NAND IPL.
-          Select this option if you need to use NAND boot.
-
 endif
 
 config PCI_TX4927
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 9bb34af26b73..0030d23bef5b 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -7,6 +7,8 @@ obj-$(CONFIG_PCI)	+= pci.o
 obj-$(CONFIG_SOC_TX3927)        += setup_tx3927.o irq_tx3927.o
 obj-$(CONFIG_SOC_TX4927)        += mem_tx4927.o setup_tx4927.o irq_tx4927.o
 obj-$(CONFIG_SOC_TX4938)        += mem_tx4927.o setup_tx4938.o irq_tx4938.o
+obj-$(CONFIG_SOC_TX4939)        += setup_tx4939.o irq_tx4939.o
 obj-$(CONFIG_TOSHIBA_FPCIB0)    += smsc_fdc37m81x.o
+obj-$(CONFIG_SPI)               += spi_eeprom.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index cbea1fdde82b..ad2870def8f1 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -30,8 +30,19 @@
 
 void __init tx4927_irq_init(void)
 {
+        int i;
+
         mips_cpu_irq_init();
         txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
         set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
                                 handle_simple_irq);
+        /* raise priority for errors, timers, SIO */
+        txx9_irq_set_pri(TX4927_IR_ECCERR, 7);
+        txx9_irq_set_pri(TX4927_IR_WTOERR, 7);
+        txx9_irq_set_pri(TX4927_IR_PCIERR, 7);
+        txx9_irq_set_pri(TX4927_IR_PCIPME, 7);
+        for (i = 0; i < TX4927_NUM_IR_TMR; i++)
+                txx9_irq_set_pri(TX4927_IR_TMR(i), 6);
+        for (i = 0; i < TX4927_NUM_IR_SIO; i++)
+                txx9_irq_set_pri(TX4927_IR_SIO(i), 5);
 }
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index 6eac684bf190..025ae11359a8 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -18,8 +18,19 @@
 
 void __init tx4938_irq_init(void)
 {
+        int i;
+
         mips_cpu_irq_init();
         txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
         set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
                                 handle_simple_irq);
+        /* raise priority for errors, timers, SIO */
+        txx9_irq_set_pri(TX4938_IR_ECCERR, 7);
+        txx9_irq_set_pri(TX4938_IR_WTOERR, 7);
+        txx9_irq_set_pri(TX4938_IR_PCIERR, 7);
+        txx9_irq_set_pri(TX4938_IR_PCIPME, 7);
+        for (i = 0; i < TX4938_NUM_IR_TMR; i++)
+                txx9_irq_set_pri(TX4938_IR_TMR(i), 6);
+        for (i = 0; i < TX4938_NUM_IR_SIO; i++)
+                txx9_irq_set_pri(TX4938_IR_SIO(i), 5);
 }
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
new file mode 100644
index 000000000000..013213a8706b
--- /dev/null
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -0,0 +1,215 @@
+/*
+ * TX4939 irq routines
+ * Based on linux/arch/mips/kernel/irq_txx9.c,
+ *          and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright 2001, 2003-2005 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         ahennessy@mvista.com
+ *         source@mvista.com
+ * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+/*
+ * TX4939 defines 64 IRQs.
+ * Similer to irq_txx9.c but different register layouts.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <asm/irq_cpu.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/tx4939.h>
+
+/* IRCER : Int. Control Enable */
+#define TXx9_IRCER_ICE  0x00000001
+
+/* IRCR : Int. Control */
+#define TXx9_IRCR_LOW   0x00000000
+#define TXx9_IRCR_HIGH  0x00000001
+#define TXx9_IRCR_DOWN  0x00000002
+#define TXx9_IRCR_UP    0x00000003
+#define TXx9_IRCR_EDGE(cr)      ((cr) & 0x00000002)
+
+/* IRSCR : Int. Status Control */
+#define TXx9_IRSCR_EIClrE       0x00000100
+#define TXx9_IRSCR_EIClr_MASK   0x0000000f
+
+/* IRCSR : Int. Current Status */
+#define TXx9_IRCSR_IF   0x00010000
+
+#define irc_dlevel      0
+#define irc_elevel      1
+
+static struct {
+        unsigned char level;
+        unsigned char mode;
+} tx4939irq[TX4939_NUM_IR] __read_mostly;
+
+static void tx4939_irq_unmask(unsigned int irq)
+{
+        unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+        u32 __iomem *lvlp;
+        int ofs;
+        if (irq_nr < 32) {
+                irq_nr--;
+                lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
+        } else {
+                irq_nr -= 32;
+                lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
+        }
+        ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
+        __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
+                     | (tx4939irq[irq_nr].level << ofs),
+                     lvlp);
+}
+
+static inline void tx4939_irq_mask(unsigned int irq)
+{
+        unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+        u32 __iomem *lvlp;
+        int ofs;
+        if (irq_nr < 32) {
+                irq_nr--;
+                lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
+        } else {
+                irq_nr -= 32;
+                lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
+        }
+        ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
+        __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
+                     | (irc_dlevel << ofs),
+                     lvlp);
+        mmiowb();
+}
+
+static void tx4939_irq_mask_ack(unsigned int irq)
+{
+        unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+
+        tx4939_irq_mask(irq);
+        if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
+                irq_nr--;
+                /* clear edge detection */
+                __raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf))
+                             << (irq_nr & 0x10),
+                             &tx4939_ircptr->edc.r);
+        }
+}
+
+static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+        unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+        u32 cr;
+        u32 __iomem *crp;
+        int ofs;
+        int mode;
+
+        if (flow_type & IRQF_TRIGGER_PROBE)
+                return 0;
+        switch (flow_type & IRQF_TRIGGER_MASK) {
+        case IRQF_TRIGGER_RISING:
+                mode = TXx9_IRCR_UP;
+                break;
+        case IRQF_TRIGGER_FALLING:
+                mode = TXx9_IRCR_DOWN;
+                break;
+        case IRQF_TRIGGER_HIGH:
+                mode = TXx9_IRCR_HIGH;
+                break;
+        case IRQF_TRIGGER_LOW:
+                mode = TXx9_IRCR_LOW;
+                break;
+        default:
+                return -EINVAL;
+        }
+        if (irq_nr < 32) {
+                irq_nr--;
+                crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r;
+        } else {
+                irq_nr -= 32;
+                crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r;
+        }
+        ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2;
+        cr = __raw_readl(crp);
+        cr &= ~(0x3 << ofs);
+        cr |= (mode & 0x3) << ofs;
+        __raw_writel(cr, crp);
+        tx4939irq[irq_nr].mode = mode;
+        return 0;
+}
+
+static struct irq_chip tx4939_irq_chip = {
+        .name           = "TX4939",
+        .ack            = tx4939_irq_mask_ack,
+        .mask           = tx4939_irq_mask,
+        .mask_ack       = tx4939_irq_mask_ack,
+        .unmask         = tx4939_irq_unmask,
+        .set_type       = tx4939_irq_set_type,
+};
+
+static int tx4939_irq_set_pri(int irc_irq, int new_pri)
+{
+        int old_pri;
+
+        if ((unsigned int)irc_irq >= TX4939_NUM_IR)
+                return 0;
+        old_pri = tx4939irq[irc_irq].level;
+        tx4939irq[irc_irq].level = new_pri;
+        return old_pri;
+}
+
+void __init tx4939_irq_init(void)
+{
+        int i;
+
+        mips_cpu_irq_init();
+        /* disable interrupt control */
+        __raw_writel(0, &tx4939_ircptr->den.r);
+        __raw_writel(0, &tx4939_ircptr->maskint.r);
+        __raw_writel(0, &tx4939_ircptr->maskext.r);
+        /* irq_base + 0 is not used */
+        for (i = 1; i < TX4939_NUM_IR; i++) {
+                tx4939irq[i].level = 4; /* middle level */
+                tx4939irq[i].mode = TXx9_IRCR_LOW;
+                set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
+                                         &tx4939_irq_chip, handle_level_irq);
+        }
+
+        /* mask all IRC interrupts */
+        __raw_writel(0, &tx4939_ircptr->msk.r);
+        for (i = 0; i < 16; i++)
+                __raw_writel(0, &tx4939_ircptr->lvl[i].r);
+        /* setup IRC interrupt mode (Low Active) */
+        for (i = 0; i < 2; i++)
+                __raw_writel(0, &tx4939_ircptr->dm[i].r);
+        for (i = 0; i < 2; i++)
+                __raw_writel(0, &tx4939_ircptr->dm2[i].r);
+        /* enable interrupt control */
+        __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
+        __raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
+
+        set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
+                                handle_simple_irq);
+
+        /* raise priority for errors, timers, sio */
+        tx4939_irq_set_pri(TX4939_IR_WTOERR, 7);
+        tx4939_irq_set_pri(TX4939_IR_PCIERR, 7);
+        tx4939_irq_set_pri(TX4939_IR_PCIPME, 7);
+        for (i = 0; i < TX4939_NUM_IR_TMR; i++)
+                tx4939_irq_set_pri(TX4939_IR_TMR(i), 6);
+        for (i = 0; i < TX4939_NUM_IR_SIO; i++)
+                tx4939_irq_set_pri(TX4939_IR_SIO(i), 5);
+}
+
+int tx4939_irq(void)
+{
+        u32 csr = __raw_readl(&tx4939_ircptr->cs.r);
+
+        if (likely(!(csr & TXx9_IRCSR_IF)))
+                return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1));
+        return -1;
+}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index fe6bee09cece..5526375010f8 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -22,11 +22,16 @@
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/mtd/physmap.h>
+#include <linux/leds.h>
 #include <asm/bootinfo.h>
 #include <asm/time.h>
 #include <asm/reboot.h>
+#include <asm/r4kcache.h>
+#include <asm/sections.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/pci.h>
+#include <asm/txx9tmr.h>
 #ifdef CONFIG_CPU_TX49XX
 #include <asm/txx9/tx4938.h>
 #endif
@@ -67,7 +72,12 @@ unsigned int txx9_master_clock;
 unsigned int txx9_cpu_clock;
 unsigned int txx9_gbus_clock;
 
+#ifdef CONFIG_CPU_TX39XX
+/* don't enable by default - see errata */
+int txx9_ccfg_toeon __initdata;
+#else
 int txx9_ccfg_toeon __initdata = 1;
+#endif
 
 /* Minimum CLK support */
 
@@ -119,39 +129,232 @@ int irq_to_gpio(unsigned irq)
 EXPORT_SYMBOL(irq_to_gpio);
 #endif
 
-extern struct txx9_board_vec jmr3927_vec;
-extern struct txx9_board_vec rbtx4927_vec;
-extern struct txx9_board_vec rbtx4937_vec;
-extern struct txx9_board_vec rbtx4938_vec;
+#define BOARD_VEC(board)        extern struct txx9_board_vec board;
+#include <asm/txx9/boards.h>
+#undef BOARD_VEC
 
 struct txx9_board_vec *txx9_board_vec __initdata;
 static char txx9_system_type[32];
 
-void __init prom_init_cmdline(void)
+static struct txx9_board_vec *board_vecs[] __initdata = {
+#define BOARD_VEC(board)        &board,
+#include <asm/txx9/boards.h>
+#undef BOARD_VEC
+};
+
+static struct txx9_board_vec *__init find_board_byname(const char *name)
+{
+        int i;
+
+        /* search board_vecs table */
+        for (i = 0; i < ARRAY_SIZE(board_vecs); i++) {
+                if (strstr(board_vecs[i]->system, name))
+                        return board_vecs[i];
+        }
+        return NULL;
+}
+
+static void __init prom_init_cmdline(void)
 {
         int argc = (int)fw_arg0;
-        char **argv = (char **)fw_arg1;
+        int *argv32 = (int *)fw_arg1;
         int i;                  /* Always ignore the "-c" at argv[0] */
-#ifdef CONFIG_64BIT
-        char *fixed_argv[32];
-        for (i = 0; i < argc; i++)
-                fixed_argv[i] = (char *)(long)(*((__s32 *)argv + i));
-        argv = fixed_argv;
-#endif
+        char builtin[CL_SIZE];
 
         /* ignore all built-in args if any f/w args given */
-        if (argc > 1)
-                *arcs_cmdline = '\0';
+        /*
+         * But if built-in strings was started with '+', append them
+         * to command line args.  If built-in was started with '-',
+         * ignore all f/w args.
+         */
+        builtin[0] = '\0';
+        if (arcs_cmdline[0] == '+')
+                strcpy(builtin, arcs_cmdline + 1);
+        else if (arcs_cmdline[0] == '-') {
+                strcpy(builtin, arcs_cmdline + 1);
+                argc = 0;
+        } else if (argc <= 1)
+                strcpy(builtin, arcs_cmdline);
+        arcs_cmdline[0] = '\0';
 
         for (i = 1; i < argc; i++) {
+                char *str = (char *)(long)argv32[i];
                 if (i != 1)
                         strcat(arcs_cmdline, " ");
-                strcat(arcs_cmdline, argv[i]);
+                if (strchr(str, ' ')) {
+                        strcat(arcs_cmdline, "\"");
+                        strcat(arcs_cmdline, str);
+                        strcat(arcs_cmdline, "\"");
+                } else
+                        strcat(arcs_cmdline, str);
+        }
+        /* append saved builtin args */
+        if (builtin[0]) {
+                if (arcs_cmdline[0])
+                        strcat(arcs_cmdline, " ");
+                strcat(arcs_cmdline, builtin);
         }
 }
 
-void __init prom_init(void)
+static int txx9_ic_disable __initdata;
+static int txx9_dc_disable __initdata;
+
+#if defined(CONFIG_CPU_TX49XX)
+/* flush all cache on very early stage (before 4k_cache_init) */
+static void __init early_flush_dcache(void)
 {
+        unsigned int conf = read_c0_config();
+        unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6));
+        unsigned int linesz = 32;
+        unsigned long addr, end;
+
+        end = INDEX_BASE + dc_size / 4;
+        /* 4way, waybit=0 */
+        for (addr = INDEX_BASE; addr < end; addr += linesz) {
+                cache_op(Index_Writeback_Inv_D, addr | 0);
+                cache_op(Index_Writeback_Inv_D, addr | 1);
+                cache_op(Index_Writeback_Inv_D, addr | 2);
+                cache_op(Index_Writeback_Inv_D, addr | 3);
+        }
+}
+
+static void __init txx9_cache_fixup(void)
+{
+        unsigned int conf;
+
+        conf = read_c0_config();
+        /* flush and disable */
+        if (txx9_ic_disable) {
+                conf |= TX49_CONF_IC;
+                write_c0_config(conf);
+        }
+        if (txx9_dc_disable) {
+                early_flush_dcache();
+                conf |= TX49_CONF_DC;
+                write_c0_config(conf);
+        }
+
+        /* enable cache */
+        conf = read_c0_config();
+        if (!txx9_ic_disable)
+                conf &= ~TX49_CONF_IC;
+        if (!txx9_dc_disable)
+                conf &= ~TX49_CONF_DC;
+        write_c0_config(conf);
+
+        if (conf & TX49_CONF_IC)
+                pr_info("TX49XX I-Cache disabled.\n");
+        if (conf & TX49_CONF_DC)
+                pr_info("TX49XX D-Cache disabled.\n");
+}
+#elif defined(CONFIG_CPU_TX39XX)
+/* flush all cache on very early stage (before tx39_cache_init) */
+static void __init early_flush_dcache(void)
+{
+        unsigned int conf = read_c0_config();
+        unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >>
+                                           TX39_CONF_DCS_SHIFT));
+        unsigned int linesz = 16;
+        unsigned long addr, end;
+
+        end = INDEX_BASE + dc_size / 2;
+        /* 2way, waybit=0 */
+        for (addr = INDEX_BASE; addr < end; addr += linesz) {
+                cache_op(Index_Writeback_Inv_D, addr | 0);
+                cache_op(Index_Writeback_Inv_D, addr | 1);
+        }
+}
+
+static void __init txx9_cache_fixup(void)
+{
+        unsigned int conf;
+
+        conf = read_c0_config();
+        /* flush and disable */
+        if (txx9_ic_disable) {
+                conf &= ~TX39_CONF_ICE;
+                write_c0_config(conf);
+        }
+        if (txx9_dc_disable) {
+                early_flush_dcache();
+                conf &= ~TX39_CONF_DCE;
+                write_c0_config(conf);
+        }
+
+        /* enable cache */
+        conf = read_c0_config();
+        if (!txx9_ic_disable)
+                conf |= TX39_CONF_ICE;
+        if (!txx9_dc_disable)
+                conf |= TX39_CONF_DCE;
+        write_c0_config(conf);
+
+        if (!(conf & TX39_CONF_ICE))
+                pr_info("TX39XX I-Cache disabled.\n");
+        if (!(conf & TX39_CONF_DCE))
+                pr_info("TX39XX D-Cache disabled.\n");
+}
+#else
+static inline void txx9_cache_fixup(void)
+{
+}
+#endif
+
+static void __init preprocess_cmdline(void)
+{
+        char cmdline[CL_SIZE];
+        char *s;
+
+        strcpy(cmdline, arcs_cmdline);
+        s = cmdline;
+        arcs_cmdline[0] = '\0';
+        while (s && *s) {
+                char *str = strsep(&s, " ");
+                if (strncmp(str, "board=", 6) == 0) {
+                        txx9_board_vec = find_board_byname(str + 6);
+                        continue;
+                } else if (strncmp(str, "masterclk=", 10) == 0) {
+                        unsigned long val;
+                        if (strict_strtoul(str + 10, 10, &val) == 0)
+                                txx9_master_clock = val;
+                        continue;
+                } else if (strcmp(str, "icdisable") == 0) {
+                        txx9_ic_disable = 1;
+                        continue;
+                } else if (strcmp(str, "dcdisable") == 0) {
+                        txx9_dc_disable = 1;
+                        continue;
+                } else if (strcmp(str, "toeoff") == 0) {
+                        txx9_ccfg_toeon = 0;
+                        continue;
+                } else if (strcmp(str, "toeon") == 0) {
+                        txx9_ccfg_toeon = 1;
+                        continue;
+                }
+                if (arcs_cmdline[0])
+                        strcat(arcs_cmdline, " ");
+                strcat(arcs_cmdline, str);
+        }
+
+        txx9_cache_fixup();
+}
+
+static void __init select_board(void)
+{
+        const char *envstr;
+
+        /* first, determine by "board=" argument in preprocess_cmdline() */
+        if (txx9_board_vec)
+                return;
+        /* next, determine by "board" envvar */
+        envstr = prom_getenv("board");
+        if (envstr) {
+                txx9_board_vec = find_board_byname(envstr);
+                if (txx9_board_vec)
+                        return;
+        }
+
+        /* select "default" board */
 #ifdef CONFIG_CPU_TX39XX
         txx9_board_vec = &jmr3927_vec;
 #endif
@@ -170,8 +373,20 @@ void __init prom_init(void)
                 txx9_board_vec = &rbtx4938_vec;
                 break;
 #endif
+#ifdef CONFIG_TOSHIBA_RBTX4939
+        case 0x4939:
+                txx9_board_vec = &rbtx4939_vec;
+                break;
+#endif
         }
 #endif
+}
+
+void __init prom_init(void)
+{
+        prom_init_cmdline();
+        preprocess_cmdline();
+        select_board();
 
         strcpy(txx9_system_type, txx9_board_vec->system);
 
@@ -180,6 +395,11 @@ void __init prom_init(void)
 
 void __init prom_free_prom_memory(void)
 {
+        unsigned long saddr = PAGE_SIZE;
+        unsigned long eaddr = __pa_symbol(&_text);
+
+        if (saddr < eaddr)
+                free_init_pages("prom memory", saddr, eaddr);
 }
 
 const char *get_system_type(void)
@@ -192,6 +412,21 @@ char * __init prom_getcmdline(void)
         return &(arcs_cmdline[0]);
 }
 
+const char *__init prom_getenv(const char *name)
+{
+        const s32 *str = (const s32 *)fw_arg2;
+
+        if (!str)
+                return NULL;
+        /* YAMON style ("name", "value" pairs) */
+        while (str[0] && str[1]) {
+                if (!strcmp((const char *)(unsigned long)str[0], name))
+                        return (const char *)(unsigned long)str[1];
+                str += 2;
+        }
+        return NULL;
+}
+
 static void __noreturn txx9_machine_halt(void)
 {
         local_irq_disable();
@@ -222,6 +457,20 @@ void __init txx9_wdt_init(unsigned long base)
         platform_device_register_simple("txx9wdt", -1, &res, 1);
 }
 
+void txx9_wdt_now(unsigned long base)
+{
+        struct txx9_tmr_reg __iomem *tmrptr =
+                ioremap(base, sizeof(struct txx9_tmr_reg));
+        /* disable watch dog timer */
+        __raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
+        __raw_writel(0, &tmrptr->tcr);
+        /* kick watchdog */
+        __raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
+        __raw_writel(1, &tmrptr->cpra); /* immediate */
+        __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
+                     &tmrptr->tcr);
+}
+
 /* SPI support */
 void __init txx9_spi_init(int busid, unsigned long base, int irq)
 {
@@ -372,3 +621,153 @@ static unsigned long __swizzle_addr_none(unsigned long port)
 unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
 EXPORT_SYMBOL(__swizzle_addr_b);
 #endif
+
+void __init txx9_physmap_flash_init(int no, unsigned long addr,
+                                    unsigned long size,
+                                    const struct physmap_flash_data *pdata)
+{
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+        struct resource res = {
+                .start = addr,
+                .end = addr + size - 1,
+                .flags = IORESOURCE_MEM,
+        };
+        struct platform_device *pdev;
+#ifdef CONFIG_MTD_PARTITIONS
+        static struct mtd_partition parts[2];
+        struct physmap_flash_data pdata_part;
+
+        /* If this area contained boot area, make separate partition */
+        if (pdata->nr_parts == 0 && !pdata->parts &&
+            addr < 0x1fc00000 && addr + size > 0x1fc00000 &&
+            !parts[0].name) {
+                parts[0].name = "boot";
+                parts[0].offset = 0x1fc00000 - addr;
+                parts[0].size = addr + size - 0x1fc00000;
+                parts[1].name = "user";
+                parts[1].offset = 0;
+                parts[1].size = 0x1fc00000 - addr;
+                pdata_part = *pdata;
+                pdata_part.nr_parts = ARRAY_SIZE(parts);
+                pdata_part.parts = parts;
+                pdata = &pdata_part;
+        }
+#endif
+        pdev = platform_device_alloc("physmap-flash", no);
+        if (!pdev ||
+            platform_device_add_resources(pdev, &res, 1) ||
+            platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
+            platform_device_add(pdev))
+                platform_device_put(pdev);
+#endif
+}
+
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static DEFINE_SPINLOCK(txx9_iocled_lock);
+
+#define TXX9_IOCLED_MAXLEDS 8
+
+struct txx9_iocled_data {
+        struct gpio_chip chip;
+        u8 cur_val;
+        void __iomem *mmioaddr;
+        struct gpio_led_platform_data pdata;
+        struct gpio_led leds[TXX9_IOCLED_MAXLEDS];
+        char names[TXX9_IOCLED_MAXLEDS][32];
+};
+
+static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset)
+{
+        struct txx9_iocled_data *data =
+                container_of(chip, struct txx9_iocled_data, chip);
+        return data->cur_val & (1 << offset);
+}
+
+static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
+                            int value)
+{
+        struct txx9_iocled_data *data =
+                container_of(chip, struct txx9_iocled_data, chip);
+        unsigned long flags;
+        spin_lock_irqsave(&txx9_iocled_lock, flags);
+        if (value)
+                data->cur_val |= 1 << offset;
+        else
+                data->cur_val &= ~(1 << offset);
+        writeb(data->cur_val, data->mmioaddr);
+        mmiowb();
+        spin_unlock_irqrestore(&txx9_iocled_lock, flags);
+}
+
+static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
+{
+        return 0;
+}
+
+static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset,
+                               int value)
+{
+        txx9_iocled_set(chip, offset, value);
+        return 0;
+}
+
+void __init txx9_iocled_init(unsigned long baseaddr,
+                             int basenum, unsigned int num, int lowactive,
+                             const char *color, char **deftriggers)
+{
+        struct txx9_iocled_data *iocled;
+        struct platform_device *pdev;
+        int i;
+        static char *default_triggers[] __initdata = {
+                "heartbeat",
+                "ide-disk",
+                "nand-disk",
+                NULL,
+        };
+
+        if (!deftriggers)
+                deftriggers = default_triggers;
+        iocled = kzalloc(sizeof(*iocled), GFP_KERNEL);
+        if (!iocled)
+                return;
+        iocled->mmioaddr = ioremap(baseaddr, 1);
+        if (!iocled->mmioaddr)
+                return;
+        iocled->chip.get = txx9_iocled_get;
+        iocled->chip.set = txx9_iocled_set;
+        iocled->chip.direction_input = txx9_iocled_dir_in;
+        iocled->chip.direction_output = txx9_iocled_dir_out;
+        iocled->chip.label = "iocled";
+        iocled->chip.base = basenum;
+        iocled->chip.ngpio = num;
+        if (gpiochip_add(&iocled->chip))
+                return;
+        if (basenum < 0)
+                basenum = iocled->chip.base;
+
+        pdev = platform_device_alloc("leds-gpio", basenum);
+        if (!pdev)
+                return;
+        iocled->pdata.num_leds = num;
+        iocled->pdata.leds = iocled->leds;
+        for (i = 0; i < num; i++) {
+                struct gpio_led *led = &iocled->leds[i];
+                snprintf(iocled->names[i], sizeof(iocled->names[i]),
+                         "iocled:%s:%u", color, i);
+                led->name = iocled->names[i];
+                led->gpio = basenum + i;
+                led->active_low = lowactive;
+                if (deftriggers && *deftriggers)
+                        led->default_trigger = *deftriggers++;
+        }
+        pdev->dev.platform_data = &iocled->pdata;
+        if (platform_device_add(pdev))
+                platform_device_put(pdev);
+}
+#else /* CONFIG_LEDS_GPIO */
+void __init txx9_iocled_init(unsigned long baseaddr,
+                             int basenum, unsigned int num, int lowactive,
+                             const char *color, char **deftriggers)
+{
+}
+#endif /* CONFIG_LEDS_GPIO */
diff --git a/arch/mips/txx9/generic/setup_tx3927.c b/arch/mips/txx9/generic/setup_tx3927.c
index 7bd963d37fc3..9505d58454c8 100644
--- a/arch/mips/txx9/generic/setup_tx3927.c
+++ b/arch/mips/txx9/generic/setup_tx3927.c
@@ -15,6 +15,7 @@
 #include <linux/delay.h>
 #include <linux/param.h>
 #include <linux/io.h>
+#include <linux/mtd/physmap.h>
 #include <asm/mipsregs.h>
 #include <asm/txx9irq.h>
 #include <asm/txx9tmr.h>
@@ -32,11 +33,6 @@ void __init tx3927_setup(void)
         int i;
         unsigned int conf;
 
-        /* don't enable - see errata */
-        txx9_ccfg_toeon = 0;
-        if (strstr(prom_getcmdline(), "toeon") != NULL)
-                txx9_ccfg_toeon = 1;
-
         txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE,
                           TX3927_REG_SIZE);
 
@@ -99,16 +95,14 @@ void __init tx3927_setup(void)
         txx9_gpio_init(TX3927_PIO_REG, 0, 16);
 
         conf = read_c0_conf();
-        if (!(conf & TX39_CONF_ICE))
-                printk(KERN_INFO "TX3927 I-Cache disabled.\n");
-        if (!(conf & TX39_CONF_DCE))
-                printk(KERN_INFO "TX3927 D-Cache disabled.\n");
-        else if (!(conf & TX39_CONF_WBON))
-                printk(KERN_INFO "TX3927 D-Cache WriteThrough.\n");
-        else if (!(conf & TX39_CONF_CWFON))
-                printk(KERN_INFO "TX3927 D-Cache WriteBack.\n");
-        else
-                printk(KERN_INFO "TX3927 D-Cache WriteBack (CWF) .\n");
+        if (conf & TX39_CONF_DCE) {
+                if (!(conf & TX39_CONF_WBON))
+                        pr_info("TX3927 D-Cache WriteThrough.\n");
+                else if (!(conf & TX39_CONF_CWFON))
+                        pr_info("TX3927 D-Cache WriteBack.\n");
+                else
+                        pr_info("TX3927 D-Cache WriteBack (CWF) .\n");
+        }
 }
 
 void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)
@@ -128,3 +122,16 @@ void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask)
                               TXX9_IRQ_BASE + TX3927_IR_SIO(i),
                               i, sclk, (1 << i) & cts_mask);
 }
+
+void __init tx3927_mtd_init(int ch)
+{
+        struct physmap_flash_data pdata = {
+                .width = TX3927_ROMC_WIDTH(ch) / 8,
+        };
+        unsigned long start = txx9_ce_res[ch].start;
+        unsigned long size = txx9_ce_res[ch].end - start + 1;
+
+        if (!(tx3927_romcptr->cr[ch] & 0x8))
+                return; /* disabled */
+        txx9_physmap_flash_init(ch, start, size, &pdata);
+}
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
index f80d4b7a694d..914e93c62639 100644
--- a/arch/mips/txx9/generic/setup_tx4927.c
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -14,6 +14,10 @@
 #include <linux/ioport.h>
 #include <linux/delay.h>
 #include <linux/param.h>
+#include <linux/ptrace.h>
+#include <linux/mtd/physmap.h>
+#include <asm/reboot.h>
+#include <asm/traps.h>
 #include <asm/txx9irq.h>
 #include <asm/txx9tmr.h>
 #include <asm/txx9pio.h>
@@ -22,6 +26,10 @@
 
 static void __init tx4927_wdr_init(void)
 {
+        /* report watchdog reset status */
+        if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST)
+                pr_warning("Watchdog reset detected at 0x%lx\n",
+                           read_c0_errorepc());
         /* clear WatchDogReset (W1C) */
         tx4927_ccfg_set(TX4927_CCFG_WDRST);
         /* do reset on watchdog */
@@ -33,6 +41,47 @@ void __init tx4927_wdt_init(void)
         txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
 }
 
+static void tx4927_machine_restart(char *command)
+{
+        local_irq_disable();
+        pr_emerg("Rebooting (with %s watchdog reset)...\n",
+                 (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) ?
+                 "external" : "internal");
+        /* clear watchdog status */
+        tx4927_ccfg_set(TX4927_CCFG_WDRST);     /* W1C */
+        txx9_wdt_now(TX4927_TMR_REG(2) & 0xfffffffffULL);
+        while (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST))
+                ;
+        mdelay(10);
+        if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) {
+                pr_emerg("Rebooting (with internal watchdog reset)...\n");
+                /* External WDRST failed.  Do internal watchdog reset */
+                tx4927_ccfg_clear(TX4927_CCFG_WDREXEN);
+        }
+        /* fallback */
+        (*_machine_halt)();
+}
+
+void show_registers(struct pt_regs *regs);
+static int tx4927_be_handler(struct pt_regs *regs, int is_fixup)
+{
+        int data = regs->cp0_cause & 4;
+        console_verbose();
+        pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
+        pr_err("ccfg:%llx, toea:%llx\n",
+               (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
+               (unsigned long long)____raw_readq(&tx4927_ccfgptr->toea));
+#ifdef CONFIG_PCI
+        tx4927_report_pcic_status();
+#endif
+        show_registers(regs);
+        panic("BusError!");
+}
+static void __init tx4927_be_init(void)
+{
+        board_be_handler = tx4927_be_handler;
+}
+
 static struct resource tx4927_sdram_resource[4];
 
 void __init tx4927_setup(void)
@@ -44,6 +93,7 @@ void __init tx4927_setup(void)
 
         txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
                           TX4927_REG_SIZE);
+        set_c0_config(TX49_CONF_CWFON);
 
         /* SDRAMC,EBUSC are configured by PROM */
         for (i = 0; i < 8; i++) {
@@ -167,6 +217,9 @@ void __init tx4927_setup(void)
         txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
         __raw_writel(0, &tx4927_pioptr->maskcpu);
         __raw_writel(0, &tx4927_pioptr->maskext);
+
+        _machine_restart = tx4927_machine_restart;
+        board_be_init = tx4927_be_init;
 }
 
 void __init tx4927_time_init(unsigned int tmrnr)
@@ -186,3 +239,47 @@ void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
                               TXX9_IRQ_BASE + TX4927_IR_SIO(i),
                               i, sclk, (1 << i) & cts_mask);
 }
+
+void __init tx4927_mtd_init(int ch)
+{
+        struct physmap_flash_data pdata = {
+                .width = TX4927_EBUSC_WIDTH(ch) / 8,
+        };
+        unsigned long start = txx9_ce_res[ch].start;
+        unsigned long size = txx9_ce_res[ch].end - start + 1;
+
+        if (!(TX4927_EBUSC_CR(ch) & 0x8))
+                return; /* disabled */
+        txx9_physmap_flash_init(ch, start, size, &pdata);
+}
+
+static void __init tx4927_stop_unused_modules(void)
+{
+        __u64 pcfg, rst = 0, ckd = 0;
+        char buf[128];
+
+        buf[0] = '\0';
+        local_irq_disable();
+        pcfg = ____raw_readq(&tx4927_ccfgptr->pcfg);
+        if (!(pcfg & TX4927_PCFG_SEL2)) {
+                rst |= TX4927_CLKCTR_ACLRST;
+                ckd |= TX4927_CLKCTR_ACLCKD;
+                strcat(buf, " ACLC");
+        }
+        if (rst | ckd) {
+                txx9_set64(&tx4927_ccfgptr->clkctr, rst);
+                txx9_set64(&tx4927_ccfgptr->clkctr, ckd);
+        }
+        local_irq_enable();
+        if (buf[0])
+                pr_info("%s: stop%s\n", txx9_pcode_str, buf);
+}
+
+static int __init tx4927_late_init(void)
+{
+        if (txx9_pcode != 0x4927)
+                return -ENODEV;
+        tx4927_stop_unused_modules();
+        return 0;
+}
+late_initcall(tx4927_late_init);
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index f3040b9ba059..af724e53ef91 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -14,6 +14,10 @@
 #include <linux/ioport.h>
 #include <linux/delay.h>
 #include <linux/param.h>
+#include <linux/ptrace.h>
+#include <linux/mtd/physmap.h>
+#include <asm/reboot.h>
+#include <asm/traps.h>
 #include <asm/txx9irq.h>
 #include <asm/txx9tmr.h>
 #include <asm/txx9pio.h>
@@ -22,6 +26,10 @@
 
 static void __init tx4938_wdr_init(void)
 {
+        /* report watchdog reset status */
+        if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST)
+                pr_warning("Watchdog reset detected at 0x%lx\n",
+                           read_c0_errorepc());
         /* clear WatchDogReset (W1C) */
         tx4938_ccfg_set(TX4938_CCFG_WDRST);
         /* do reset on watchdog */
@@ -33,6 +41,47 @@ void __init tx4938_wdt_init(void)
         txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
 }
 
+static void tx4938_machine_restart(char *command)
+{
+        local_irq_disable();
+        pr_emerg("Rebooting (with %s watchdog reset)...\n",
+                 (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) ?
+                 "external" : "internal");
+        /* clear watchdog status */
+        tx4938_ccfg_set(TX4938_CCFG_WDRST);     /* W1C */
+        txx9_wdt_now(TX4938_TMR_REG(2) & 0xfffffffffULL);
+        while (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST))
+                ;
+        mdelay(10);
+        if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) {
+                pr_emerg("Rebooting (with internal watchdog reset)...\n");
+                /* External WDRST failed.  Do internal watchdog reset */
+                tx4938_ccfg_clear(TX4938_CCFG_WDREXEN);
+        }
+        /* fallback */
+        (*_machine_halt)();
+}
+
+void show_registers(struct pt_regs *regs);
+static int tx4938_be_handler(struct pt_regs *regs, int is_fixup)
+{
+        int data = regs->cp0_cause & 4;
+        console_verbose();
+        pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
+        pr_err("ccfg:%llx, toea:%llx\n",
+               (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
+               (unsigned long long)____raw_readq(&tx4938_ccfgptr->toea));
+#ifdef CONFIG_PCI
+        tx4927_report_pcic_status();
+#endif
+        show_registers(regs);
+        panic("BusError!");
+}
+static void __init tx4938_be_init(void)
+{
+        board_be_handler = tx4938_be_handler;
+}
+
 static struct resource tx4938_sdram_resource[4];
 static struct resource tx4938_sram_resource;
 
@@ -47,6 +96,7 @@ void __init tx4938_setup(void)
 
         txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
                           TX4938_REG_SIZE);
+        set_c0_config(TX49_CONF_CWFON);
 
         /* SDRAMC,EBUSC are configured by PROM */
         for (i = 0; i < 8; i++) {
@@ -227,6 +277,9 @@ void __init tx4938_setup(void)
                                    TX4938_CLKCTR_ETH1CKD);
                 }
         }
+
+        _machine_restart = tx4938_machine_restart;
+        board_be_init = tx4938_be_init;
 }
 
 void __init tx4938_time_init(unsigned int tmrnr)
@@ -268,3 +321,72 @@ void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
         if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
                 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
 }
+
+void __init tx4938_mtd_init(int ch)
+{
+        struct physmap_flash_data pdata = {
+                .width = TX4938_EBUSC_WIDTH(ch) / 8,
+        };
+        unsigned long start = txx9_ce_res[ch].start;
+        unsigned long size = txx9_ce_res[ch].end - start + 1;
+
+        if (!(TX4938_EBUSC_CR(ch) & 0x8))
+                return; /* disabled */
+        txx9_physmap_flash_init(ch, start, size, &pdata);
+}
+
+static void __init tx4938_stop_unused_modules(void)
+{
+        __u64 pcfg, rst = 0, ckd = 0;
+        char buf[128];
+
+        buf[0] = '\0';
+        local_irq_disable();
+        pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
+        switch (txx9_pcode) {
+        case 0x4937:
+                if (!(pcfg & TX4938_PCFG_SEL2)) {
+                        rst |= TX4938_CLKCTR_ACLRST;
+                        ckd |= TX4938_CLKCTR_ACLCKD;
+                        strcat(buf, " ACLC");
+                }
+                break;
+        case 0x4938:
+                if (!(pcfg & TX4938_PCFG_SEL2) ||
+                    (pcfg & TX4938_PCFG_ETH0_SEL)) {
+                        rst |= TX4938_CLKCTR_ACLRST;
+                        ckd |= TX4938_CLKCTR_ACLCKD;
+                        strcat(buf, " ACLC");
+                }
+                if ((pcfg &
+                     (TX4938_PCFG_ATA_SEL | TX4938_PCFG_ISA_SEL |
+                      TX4938_PCFG_NDF_SEL))
+                    != TX4938_PCFG_NDF_SEL) {
+                        rst |= TX4938_CLKCTR_NDFRST;
+                        ckd |= TX4938_CLKCTR_NDFCKD;
+                        strcat(buf, " NDFMC");
+                }
+                if (!(pcfg & TX4938_PCFG_SPI_SEL)) {
+                        rst |= TX4938_CLKCTR_SPIRST;
+                        ckd |= TX4938_CLKCTR_SPICKD;
+                        strcat(buf, " SPI");
+                }
+                break;
+        }
+        if (rst | ckd) {
+                txx9_set64(&tx4938_ccfgptr->clkctr, rst);
+                txx9_set64(&tx4938_ccfgptr->clkctr, ckd);
+        }
+        local_irq_enable();
+        if (buf[0])
+                pr_info("%s: stop%s\n", txx9_pcode_str, buf);
+}
+
+static int __init tx4938_late_init(void)
+{
+        if (txx9_pcode != 0x4937 && txx9_pcode != 0x4938)
+                return -ENODEV;
+        tx4938_stop_unused_modules();
+        return 0;
+}
+late_initcall(tx4938_late_init);
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
new file mode 100644
index 000000000000..6c0049a5bbc1
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -0,0 +1,506 @@
+/*
+ * TX4939 setup routines
+ * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
+ *          and RBTX49xx patch from CELF patch archive.
+ *
+ * 2003-2005 (c) MontaVista Software, Inc.
+ * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/notifier.h>
+#include <linux/sysdev.h>
+#include <linux/ethtool.h>
+#include <linux/param.h>
+#include <linux/ptrace.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
+#include <asm/traps.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9tmr.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4939.h>
+
+static void __init tx4939_wdr_init(void)
+{
+        /* report watchdog reset status */
+        if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
+                pr_warning("Watchdog reset detected at 0x%lx\n",
+                           read_c0_errorepc());
+        /* clear WatchDogReset (W1C) */
+        tx4939_ccfg_set(TX4939_CCFG_WDRST);
+        /* do reset on watchdog */
+        tx4939_ccfg_set(TX4939_CCFG_WR);
+}
+
+void __init tx4939_wdt_init(void)
+{
+        txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
+}
+
+static void tx4939_machine_restart(char *command)
+{
+        local_irq_disable();
+        pr_emerg("Rebooting (with %s watchdog reset)...\n",
+                 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
+                 "external" : "internal");
+        /* clear watchdog status */
+        tx4939_ccfg_set(TX4939_CCFG_WDRST);     /* W1C */
+        txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
+        while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
+                ;
+        mdelay(10);
+        if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
+                pr_emerg("Rebooting (with internal watchdog reset)...\n");
+                /* External WDRST failed.  Do internal watchdog reset */
+                tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
+        }
+        /* fallback */
+        (*_machine_halt)();
+}
+
+void show_registers(struct pt_regs *regs);
+static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
+{
+        int data = regs->cp0_cause & 4;
+        console_verbose();
+        pr_err("%cBE exception at %#lx\n",
+               data ? 'D' : 'I', regs->cp0_epc);
+        pr_err("ccfg:%llx, toea:%llx\n",
+               (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
+               (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
+#ifdef CONFIG_PCI
+        tx4927_report_pcic_status();
+#endif
+        show_registers(regs);
+        panic("BusError!");
+}
+static void __init tx4939_be_init(void)
+{
+        board_be_handler = tx4939_be_handler;
+}
+
+static struct resource tx4939_sdram_resource[4];
+static struct resource tx4939_sram_resource;
+#define TX4939_SRAM_SIZE 0x800
+
+void __init tx4939_add_memory_regions(void)
+{
+        int i;
+        unsigned long start, size;
+        u64 win;
+
+        for (i = 0; i < 4; i++) {
+                if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
+                        continue;
+                win = ____raw_readq(&tx4939_ddrcptr->win[i]);
+                start = (unsigned long)(win >> 48);
+                size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
+                add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
+        }
+}
+
+void __init tx4939_setup(void)
+{
+        int i;
+        __u32 divmode;
+        __u64 pcfg;
+        int cpuclk = 0;
+
+        txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
+                          TX4939_REG_SIZE);
+        set_c0_config(TX49_CONF_CWFON);
+
+        /* SDRAMC,EBUSC are configured by PROM */
+        for (i = 0; i < 4; i++) {
+                if (!(TX4939_EBUSC_CR(i) & 0x8))
+                        continue;       /* disabled */
+                txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
+                txx9_ce_res[i].end =
+                        txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
+                request_resource(&iomem_resource, &txx9_ce_res[i]);
+        }
+
+        /* clocks */
+        if (txx9_master_clock) {
+                /* calculate cpu_clock from master_clock */
+                divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
+                        TX4939_CCFG_MULCLK_MASK;
+                cpuclk = txx9_master_clock * 20 / 2;
+                switch (divmode) {
+                case TX4939_CCFG_MULCLK_8:
+                        cpuclk = cpuclk / 3 * 4 /* / 6 *  8 */; break;
+                case TX4939_CCFG_MULCLK_9:
+                        cpuclk = cpuclk / 2 * 3 /* / 6 *  9 */; break;
+                case TX4939_CCFG_MULCLK_10:
+                        cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
+                case TX4939_CCFG_MULCLK_11:
+                        cpuclk = cpuclk / 6 * 11; break;
+                case TX4939_CCFG_MULCLK_12:
+                        cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
+                case TX4939_CCFG_MULCLK_13:
+                        cpuclk = cpuclk / 6 * 13; break;
+                case TX4939_CCFG_MULCLK_14:
+                        cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
+                case TX4939_CCFG_MULCLK_15:
+                        cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
+                }
+                txx9_cpu_clock = cpuclk;
+        } else {
+                if (txx9_cpu_clock == 0)
+                        txx9_cpu_clock = 400000000;     /* 400MHz */
+                /* calculate master_clock from cpu_clock */
+                cpuclk = txx9_cpu_clock;
+                divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
+                        TX4939_CCFG_MULCLK_MASK;
+                switch (divmode) {
+                case TX4939_CCFG_MULCLK_8:
+                        txx9_master_clock = cpuclk * 6 / 8; break;
+                case TX4939_CCFG_MULCLK_9:
+                        txx9_master_clock = cpuclk * 6 / 9; break;
+                case TX4939_CCFG_MULCLK_10:
+                        txx9_master_clock = cpuclk * 6 / 10; break;
+                case TX4939_CCFG_MULCLK_11:
+                        txx9_master_clock = cpuclk * 6 / 11; break;
+                case TX4939_CCFG_MULCLK_12:
+                        txx9_master_clock = cpuclk * 6 / 12; break;
+                case TX4939_CCFG_MULCLK_13:
+                        txx9_master_clock = cpuclk * 6 / 13; break;
+                case TX4939_CCFG_MULCLK_14:
+                        txx9_master_clock = cpuclk * 6 / 14; break;
+                case TX4939_CCFG_MULCLK_15:
+                        txx9_master_clock = cpuclk * 6 / 15; break;
+                }
+                txx9_master_clock /= 10; /* * 2 / 20 */
+        }
+        /* calculate gbus_clock from cpu_clock */
+        divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
+                TX4939_CCFG_YDIVMODE_MASK;
+        txx9_gbus_clock = txx9_cpu_clock;
+        switch (divmode) {
+        case TX4939_CCFG_YDIVMODE_2:
+                txx9_gbus_clock /= 2; break;
+        case TX4939_CCFG_YDIVMODE_3:
+                txx9_gbus_clock /= 3; break;
+        case TX4939_CCFG_YDIVMODE_5:
+                txx9_gbus_clock /= 5; break;
+        case TX4939_CCFG_YDIVMODE_6:
+                txx9_gbus_clock /= 6; break;
+        }
+        /* change default value to udelay/mdelay take reasonable time */
+        loops_per_jiffy = txx9_cpu_clock / HZ / 2;
+
+        /* CCFG */
+        tx4939_wdr_init();
+        /* clear BusErrorOnWrite flag (W1C) */
+        tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
+        /* enable Timeout BusError */
+        if (txx9_ccfg_toeon)
+                tx4939_ccfg_set(TX4939_CCFG_TOE);
+
+        /* DMA selection */
+        txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
+
+        /* Use external clock for external arbiter */
+        if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
+                txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
+
+        pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
+                txx9_pcode_str,
+                (cpuclk + 500000) / 1000000,
+                (txx9_master_clock + 500000) / 1000000,
+                (txx9_gbus_clock + 500000) / 1000000,
+                (__u32)____raw_readq(&tx4939_ccfgptr->crir),
+                (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
+                (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
+
+        pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
+                (__u32)____raw_readq(&tx4939_ddrcptr->winen));
+        for (i = 0; i < 4; i++) {
+                __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
+                if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
+                        continue;       /* disabled */
+                printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
+                tx4939_sdram_resource[i].name = "DDR SDRAM";
+                tx4939_sdram_resource[i].start =
+                        (unsigned long)(win >> 48) << 20;
+                tx4939_sdram_resource[i].end =
+                        ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
+                         20) - 1;
+                tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
+                request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
+        }
+        printk(KERN_CONT "\n");
+
+        /* SRAM */
+        if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
+                unsigned int size = TX4939_SRAM_SIZE;
+                tx4939_sram_resource.name = "SRAM";
+                tx4939_sram_resource.start =
+                        (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
+                        & ~(size - 1);
+                tx4939_sram_resource.end =
+                        tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
+                tx4939_sram_resource.flags = IORESOURCE_MEM;
+                request_resource(&iomem_resource, &tx4939_sram_resource);
+        }
+
+        /* TMR */
+        /* disable all timers */
+        for (i = 0; i < TX4939_NR_TMR; i++)
+                txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
+
+        /* DMA */
+        for (i = 0; i < 2; i++)
+                ____raw_writeq(TX4938_DMA_MCR_MSTEN,
+                               (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
+
+        /* set PCIC1 reset (required to prevent hangup on BIST) */
+        txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
+        pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
+        if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
+                mdelay(1);      /* at least 128 cpu clock */
+                /* clear PCIC1 reset */
+                txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
+        } else {
+                pr_info("%s: stop PCIC1\n", txx9_pcode_str);
+                /* stop PCIC1 */
+                txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
+        }
+        if (!(pcfg & TX4939_PCFG_ET0MODE)) {
+                pr_info("%s: stop ETH0\n", txx9_pcode_str);
+                txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
+                txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
+        }
+        if (!(pcfg & TX4939_PCFG_ET1MODE)) {
+                pr_info("%s: stop ETH1\n", txx9_pcode_str);
+                txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
+                txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
+        }
+
+        _machine_restart = tx4939_machine_restart;
+        board_be_init = tx4939_be_init;
+}
+
+void __init tx4939_time_init(unsigned int tmrnr)
+{
+        if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
+                txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
+                                     TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
+                                     TXX9_IMCLK);
+}
+
+void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
+{
+        int i;
+        unsigned int ch_mask = 0;
+        __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
+
+        cts_mask |= ~1; /* only SIO0 have RTS/CTS */
+        if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
+                cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
+        if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
+                ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
+        if (pcfg & TX4939_PCFG_SIO3MODE)
+                ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
+        for (i = 0; i < 4; i++) {
+                if ((1 << i) & ch_mask)
+                        continue;
+                txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
+                              TXX9_IRQ_BASE + TX4939_IR_SIO(i),
+                              i, sclk, (1 << i) & cts_mask);
+        }
+}
+
+#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
+static int tx4939_get_eth_speed(struct net_device *dev)
+{
+        struct ethtool_cmd cmd = { ETHTOOL_GSET };
+        int speed = 100;        /* default 100Mbps */
+        int err;
+        if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings)
+                return speed;
+        err = dev->ethtool_ops->get_settings(dev, &cmd);
+        if (err < 0)
+                return speed;
+        speed = cmd.speed == SPEED_100 ? 100 : 10;
+        return speed;
+}
+static int tx4939_netdev_event(struct notifier_block *this,
+                               unsigned long event,
+                               void *ptr)
+{
+        struct net_device *dev = ptr;
+        if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
+                __u64 bit = 0;
+                if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
+                        bit = TX4939_PCFG_SPEED0;
+                else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
+                        bit = TX4939_PCFG_SPEED1;
+                if (bit) {
+                        int speed = tx4939_get_eth_speed(dev);
+                        if (speed == 100)
+                                txx9_set64(&tx4939_ccfgptr->pcfg, bit);
+                        else
+                                txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
+                }
+        }
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block tx4939_netdev_notifier = {
+        .notifier_call = tx4939_netdev_event,
+        .priority = 1,
+};
+
+void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
+{
+        u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
+
+        if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
+                txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
+        if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
+                txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
+        register_netdevice_notifier(&tx4939_netdev_notifier);
+}
+#else
+void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
+{
+}
+#endif
+
+void __init tx4939_mtd_init(int ch)
+{
+        struct physmap_flash_data pdata = {
+                .width = TX4939_EBUSC_WIDTH(ch) / 8,
+        };
+        unsigned long start = txx9_ce_res[ch].start;
+        unsigned long size = txx9_ce_res[ch].end - start + 1;
+
+        if (!(TX4939_EBUSC_CR(ch) & 0x8))
+                return; /* disabled */
+        txx9_physmap_flash_init(ch, start, size, &pdata);
+}
+
+#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
+void __init tx4939_ata_init(void)
+{
+        static struct resource ata0_res[] = {
+                {
+                        .start = TX4939_ATA_REG_PHYS(0),
+                        .end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        static struct resource ata1_res[] = {
+                {
+                        .start = TX4939_ATA_REG_PHYS(1),
+                        .end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        static struct platform_device ata0_dev = {
+                .name = "tx4939ide",
+                .id = 0,
+                .num_resources = ARRAY_SIZE(ata0_res),
+                .resource = ata0_res,
+        };
+        static struct platform_device ata1_dev = {
+                .name = "tx4939ide",
+                .id = 1,
+                .num_resources = ARRAY_SIZE(ata1_res),
+                .resource = ata1_res,
+        };
+        __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
+
+        if (pcfg & TX4939_PCFG_ATA0MODE)
+                platform_device_register(&ata0_dev);
+        if ((pcfg & (TX4939_PCFG_ATA1MODE |
+                     TX4939_PCFG_ET1MODE |
+                     TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
+                platform_device_register(&ata1_dev);
+}
+
+static void __init tx4939_stop_unused_modules(void)
+{
+        __u64 pcfg, rst = 0, ckd = 0;
+        char buf[128];
+
+        buf[0] = '\0';
+        local_irq_disable();
+        pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
+        if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
+            TX4939_PCFG_I2SMODE_ACLC) {
+                rst |= TX4939_CLKCTR_ACLRST;
+                ckd |= TX4939_CLKCTR_ACLCKD;
+                strcat(buf, " ACLC");
+        }
+        if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
+            TX4939_PCFG_I2SMODE_I2S &&
+            (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
+            TX4939_PCFG_I2SMODE_I2S_ALT) {
+                rst |= TX4939_CLKCTR_I2SRST;
+                ckd |= TX4939_CLKCTR_I2SCKD;
+                strcat(buf, " I2S");
+        }
+        if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
+                rst |= TX4939_CLKCTR_ATA0RST;
+                ckd |= TX4939_CLKCTR_ATA0CKD;
+                strcat(buf, " ATA0");
+        }
+        if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
+                rst |= TX4939_CLKCTR_ATA1RST;
+                ckd |= TX4939_CLKCTR_ATA1CKD;
+                strcat(buf, " ATA1");
+        }
+        if (pcfg & TX4939_PCFG_SPIMODE) {
+                rst |= TX4939_CLKCTR_SPIRST;
+                ckd |= TX4939_CLKCTR_SPICKD;
+                strcat(buf, " SPI");
+        }
+        if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
+                rst |= TX4939_CLKCTR_VPCRST;
+                ckd |= TX4939_CLKCTR_VPCCKD;
+                strcat(buf, " VPC");
+        }
+        if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
+                rst |= TX4939_CLKCTR_SIO2RST;
+                ckd |= TX4939_CLKCTR_SIO2CKD;
+                strcat(buf, " SIO2");
+        }
+        if (pcfg & TX4939_PCFG_SIO3MODE) {
+                rst |= TX4939_CLKCTR_SIO3RST;
+                ckd |= TX4939_CLKCTR_SIO3CKD;
+                strcat(buf, " SIO3");
+        }
+        if (rst | ckd) {
+                txx9_set64(&tx4939_ccfgptr->clkctr, rst);
+                txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
+        }
+        local_irq_enable();
+        if (buf[0])
+                pr_info("%s: stop%s\n", txx9_pcode_str, buf);
+}
+
+static int __init tx4939_late_init(void)
+{
+        if (txx9_pcode != 0x4939)
+                return -ENODEV;
+        tx4939_stop_unused_modules();
+        return 0;
+}
+late_initcall(tx4939_late_init);
diff --git a/arch/mips/txx9/rbtx4938/spi_eeprom.c b/arch/mips/txx9/generic/spi_eeprom.c
index a7ea8b041c1d..75c347238f47 100644
--- a/arch/mips/txx9/rbtx4938/spi_eeprom.c
+++ b/arch/mips/txx9/generic/spi_eeprom.c
@@ -18,29 +18,31 @@
 #define AT250X0_PAGE_SIZE       8
 
 /* register board information for at25 driver */
-int __init spi_eeprom_register(int chipid)
+int __init spi_eeprom_register(int busid, int chipid, int size)
 {
-        static struct spi_eeprom eeprom = {
-                .name = "at250x0",
-                .byte_len = 128,
-                .page_size = AT250X0_PAGE_SIZE,
-                .flags = EE_ADDR1,
-        };
         struct spi_board_info info = {
                 .modalias = "at25",
                 .max_speed_hz = 1500000,        /* 1.5Mbps */
-                .bus_num = 0,
+                .bus_num = busid,
                 .chip_select = chipid,
-                .platform_data = &eeprom,
                 /* Mode 0: High-Active, Sample-Then-Shift */
         };
-
+        struct spi_eeprom *eeprom;
+        eeprom = kzalloc(sizeof(*eeprom), GFP_KERNEL);
+        if (!eeprom)
+                return -ENOMEM;
+        strcpy(eeprom->name, "at250x0");
+        eeprom->byte_len = size;
+        eeprom->page_size = AT250X0_PAGE_SIZE;
+        eeprom->flags = EE_ADDR1;
+        info.platform_data = eeprom;
         return spi_register_board_info(&info, 1);
 }
 
 /* simple temporary spi driver to provide early access to seeprom. */
 
 static struct read_param {
+        int busid;
         int chipid;
         int address;
         unsigned char *buf;
@@ -57,7 +59,8 @@ static int __init early_seeprom_probe(struct spi_device *spi)
 
         dev_info(&spi->dev, "spiclk %u KHz.\n",
                  (spi->max_speed_hz + 500) / 1000);
-        if (read_param->chipid != spi->chip_select)
+        if (read_param->busid != spi->master->bus_num ||
+            read_param->chipid != spi->chip_select)
                 return -ENODEV;
         while (len > 0) {
                 /* spi_write_then_read can only work with small chunk */
@@ -80,11 +83,12 @@ static struct spi_driver early_seeprom_driver __initdata = {
         .probe  = early_seeprom_probe,
 };
 
-int __init spi_eeprom_read(int chipid, int address,
+int __init spi_eeprom_read(int busid, int chipid, int address,
                            unsigned char *buf, int len)
 {
         int ret;
         struct read_param param = {
+                .busid = busid,
                 .chipid = chipid,
                 .address = address,
                 .buf = buf,
diff --git a/arch/mips/txx9/jmr3927/prom.c b/arch/mips/txx9/jmr3927/prom.c
index 70c4c8ec3e84..c899c0c087a0 100644
--- a/arch/mips/txx9/jmr3927/prom.c
+++ b/arch/mips/txx9/jmr3927/prom.c
@@ -47,7 +47,6 @@ void __init jmr3927_prom_init(void)
         if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
                 printk(KERN_ERR "TX3927 TLB off\n");
 
-        prom_init_cmdline();
         add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
         txx9_sio_putchar_init(TX3927_SIO_REG(1));
 }
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 87db41be8a56..25e50a7be387 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -62,7 +62,6 @@ static void __init jmr3927_time_init(void)
 }
 
 #define DO_WRITE_THROUGH
-#define DO_ENABLE_CACHE
 
 static void jmr3927_board_init(void);
 
@@ -77,11 +76,6 @@ static void __init jmr3927_mem_setup(void)
         /* cache setup */
         {
                 unsigned int conf;
-#ifdef DO_ENABLE_CACHE
-                int mips_ic_disable = 0, mips_dc_disable = 0;
-#else
-                int mips_ic_disable = 1, mips_dc_disable = 1;
-#endif
 #ifdef DO_WRITE_THROUGH
                 int mips_config_cwfon = 0;
                 int mips_config_wbon = 0;
@@ -91,10 +85,7 @@ static void __init jmr3927_mem_setup(void)
 #endif
 
                 conf = read_c0_conf();
-                conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE |
-                          TX39_CONF_WBON | TX39_CONF_CWFON);
-                conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
-                conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
+                conf &= ~(TX39_CONF_WBON | TX39_CONF_CWFON);
                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 
@@ -199,11 +190,25 @@ static void __init jmr3927_rtc_init(void)
         platform_device_register_simple("rtc-ds1742", -1, &res, 1);
 }
 
+static void __init jmr3927_mtd_init(void)
+{
+        int i;
+
+        for (i = 0; i < 2; i++)
+                tx3927_mtd_init(i);
+}
+
 static void __init jmr3927_device_init(void)
 {
+        unsigned long iocled_base = JMR3927_IOC_LED_ADDR - IO_BASE;
+#ifdef __LITTLE_ENDIAN
+        iocled_base |= 1;
+#endif
         __swizzle_addr_b = jmr3927_swizzle_addr_b;
         jmr3927_rtc_init();
         tx3927_wdt_init();
+        jmr3927_mtd_init();
+        txx9_iocled_init(iocled_base, -1, 8, 1, "green", NULL);
 }
 
 struct txx9_board_vec jmr3927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 00cd5231da30..9c14ebb26cb4 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -133,15 +133,20 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq)
         u8 level3;
 
         level3 = readb(rbtx4927_imstat_addr) & 0x1f;
-        if (level3)
-                sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
-        return sw_irq;
+        if (unlikely(!level3))
+                return -1;
+        return RBTX4927_IRQ_IOC + __fls8(level3);
 }
 
 static void __init toshiba_rbtx4927_irq_ioc_init(void)
 {
         int i;
 
+        /* mask all IOC interrupts */
+        writeb(0, rbtx4927_imask_addr);
+        /* clear SoftInt interrupts */
+        writeb(0, rbtx4927_softint_addr);
+
         for (i = RBTX4927_IRQ_IOC;
              i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
                 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c
index 1dc0a5b1956b..cc97c6a6011b 100644
--- a/arch/mips/txx9/rbtx4927/prom.c
+++ b/arch/mips/txx9/rbtx4927/prom.c
@@ -36,7 +36,6 @@
 
 void __init rbtx4927_prom_init(void)
 {
-        prom_init_cmdline();
         add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM);
         txx9_sio_putchar_init(TX4927_SIO_REG(0) & 0xfffffffffULL);
 }
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 0d39bafea794..4a74423b2ba8 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -48,6 +48,7 @@
 #include <linux/ioport.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <linux/gpio.h>
 #include <asm/io.h>
 #include <asm/reboot.h>
 #include <asm/txx9/generic.h>
@@ -185,14 +186,8 @@ static void __init rbtx4937_clock_init(void);
 
 static void __init rbtx4927_mem_setup(void)
 {
-        u32 cp0_config;
         char *argptr;
 
-        /* enable caches -- HCP5 does this, pmon does not */
-        cp0_config = read_c0_config();
-        cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
-        write_c0_config(cp0_config);
-
         if (TX4927_REV_PCODE() == 0x4927) {
                 rbtx4927_clock_init();
                 tx4927_setup();
@@ -212,6 +207,14 @@ static void __init rbtx4927_mem_setup(void)
         set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
 #endif
 
+        /* TX4927-SIO DTR on (PIO[15]) */
+        gpio_request(15, "sio-dtr");
+        gpio_direction_output(15, 1);
+        gpio_request(0, "led");
+        gpio_direction_output(0, 1);
+        gpio_request(1, "led");
+        gpio_direction_output(1, 1);
+
         tx4927_sio_init(0, 0);
 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
         argptr = prom_getcmdline();
@@ -304,11 +307,21 @@ static void __init rbtx4927_ne_init(void)
         platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
 }
 
+static void __init rbtx4927_mtd_init(void)
+{
+        int i;
+
+        for (i = 0; i < 2; i++)
+                tx4927_mtd_init(i);
+}
+
 static void __init rbtx4927_device_init(void)
 {
         toshiba_rbtx4927_rtc_init();
         rbtx4927_ne_init();
         tx4927_wdt_init();
+        rbtx4927_mtd_init();
+        txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
 }
 
 struct txx9_board_vec rbtx4927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4938/Makefile b/arch/mips/txx9/rbtx4938/Makefile
index 9dcc52ae5b9d..f3e1f597b4f1 100644
--- a/arch/mips/txx9/rbtx4938/Makefile
+++ b/arch/mips/txx9/rbtx4938/Makefile
@@ -1,3 +1,3 @@
-obj-y   += prom.o setup.o irq.o spi_eeprom.o
+obj-y   += prom.o setup.o irq.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index ca2f8306ce93..7d21befb8932 100644
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -85,10 +85,10 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq)
         u8 level3;
 
         level3 = readb(rbtx4938_imstat_addr);
-        if (level3)
-                /* must use fls so onboard ATA has priority */
-                sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1;
-        return sw_irq;
+        if (unlikely(!level3))
+                return -1;
+        /* must use fls so onboard ATA has priority */
+        return RBTX4938_IRQ_IOC + __fls8(level3);
 }
 
 static void __init
diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c
index d73123cd2ab9..bcb469247e8c 100644
--- a/arch/mips/txx9/rbtx4938/prom.c
+++ b/arch/mips/txx9/rbtx4938/prom.c
@@ -18,9 +18,6 @@
 
 void __init rbtx4938_prom_init(void)
 {
-#ifndef CONFIG_TX4938_NAND_BOOT
-        prom_init_cmdline();
-#endif
         add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM);
         txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL);
 }
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index 9ab48dec0fe8..e077cc4d3a59 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -15,6 +15,7 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/mtd/physmap.h>
 
 #include <asm/reboot.h>
 #include <asm/io.h>
@@ -110,6 +111,7 @@ static void __init rbtx4938_pci_setup(void)
 #define SEEPROM2_CS     0       /* IOC */
 #define SEEPROM3_CS     1       /* IOC */
 #define SRTC_CS 2       /* IOC */
+#define SPI_BUSNO       0
 
 static int __init rbtx4938_ethaddr_init(void)
 {
@@ -119,7 +121,7 @@ static int __init rbtx4938_ethaddr_init(void)
         int i;
 
         /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
-        if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
+        if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
                 printk(KERN_ERR "seeprom: read error.\n");
                 return -ENODEV;
         } else {
@@ -173,23 +175,30 @@ static void __init rbtx4938_mem_setup(void)
 #endif
 
 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
-        printk(KERN_INFO "PIOSEL: disabling both ata and nand selection\n");
+        pr_info("PIOSEL: disabling both ATA and NAND selection\n");
         txx9_clear64(&tx4938_ccfgptr->pcfg,
                      TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
 #endif
 
 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
-        printk(KERN_INFO "PIOSEL: enabling nand selection\n");
+        pr_info("PIOSEL: enabling NAND selection\n");
         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
 #endif
 
 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
-        printk(KERN_INFO "PIOSEL: enabling ata selection\n");
+        pr_info("PIOSEL: enabling ATA selection\n");
         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
 #endif
 
+#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
+        pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
+        pr_info("PIOSEL: NAND %s, ATA %s\n",
+                (pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
+                (pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
+#endif
+
         rbtx4938_spi_setup();
         pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);    /* updated */
         /* fixup piosel */
@@ -279,9 +288,9 @@ static int __init rbtx4938_spi_init(void)
                 .mode = SPI_MODE_1 | SPI_CS_HIGH,
         };
         spi_register_board_info(&srtc_info, 1);
-        spi_eeprom_register(SEEPROM1_CS);
-        spi_eeprom_register(16 + SEEPROM2_CS);
-        spi_eeprom_register(16 + SEEPROM3_CS);
+        spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
+        spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
+        spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
         gpio_request(16 + SRTC_CS, "rtc-rs5c348");
         gpio_direction_output(16 + SRTC_CS, 0);
         gpio_request(SEEPROM1_CS, "seeprom1");
@@ -290,10 +299,46 @@ static int __init rbtx4938_spi_init(void)
         gpio_direction_output(16 + SEEPROM2_CS, 1);
         gpio_request(16 + SEEPROM3_CS, "seeprom3");
         gpio_direction_output(16 + SEEPROM3_CS, 1);
-        tx4938_spi_init(0);
+        tx4938_spi_init(SPI_BUSNO);
         return 0;
 }
 
+static void __init rbtx4938_mtd_init(void)
+{
+        struct physmap_flash_data pdata = {
+                .width = 4,
+        };
+
+        switch (readb(rbtx4938_bdipsw_addr) & 7) {
+        case 0:
+                /* Boot */
+                txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
+                /* System */
+                txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
+                break;
+        case 1:
+                /* System */
+                txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
+                /* Boot */
+                txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
+                break;
+        case 2:
+                /* Ext */
+                txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
+                /* System */
+                txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
+                /* Boot */
+                txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
+                break;
+        case 3:
+                /* Boot */
+                txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
+                /* System */
+                txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
+                break;
+        }
+}
+
 static void __init rbtx4938_arch_init(void)
 {
         gpiochip_add(&rbtx4938_spi_gpio_chip);
@@ -306,6 +351,8 @@ static void __init rbtx4938_device_init(void)
         rbtx4938_ethaddr_init();
         rbtx4938_ne_init();
         tx4938_wdt_init();
+        rbtx4938_mtd_init();
+        txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
 }
 
 struct txx9_board_vec rbtx4938_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4939/Makefile b/arch/mips/txx9/rbtx4939/Makefile
new file mode 100644
index 000000000000..3232cd03a7d6
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/Makefile
@@ -0,0 +1,3 @@
+obj-y    += irq.o setup.o prom.o
+
+EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c
new file mode 100644
index 000000000000..500cc0a908e6
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/irq.c
@@ -0,0 +1,96 @@
+/*
+ * Toshiba RBTX4939 interrupt routines
+ * Based on linux/arch/mips/txx9/rbtx4938/irq.c,
+ *          and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/mipsregs.h>
+#include <asm/txx9/rbtx4939.h>
+
+/*
+ * RBTX4939 IOC controller definition
+ */
+
+static void rbtx4939_ioc_irq_unmask(unsigned int irq)
+{
+        int ioc_nr = irq - RBTX4939_IRQ_IOC;
+
+        writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr);
+}
+
+static void rbtx4939_ioc_irq_mask(unsigned int irq)
+{
+        int ioc_nr = irq - RBTX4939_IRQ_IOC;
+
+        writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
+        mmiowb();
+}
+
+static struct irq_chip rbtx4939_ioc_irq_chip = {
+        .name           = "IOC",
+        .ack            = rbtx4939_ioc_irq_mask,
+        .mask           = rbtx4939_ioc_irq_mask,
+        .mask_ack       = rbtx4939_ioc_irq_mask,
+        .unmask         = rbtx4939_ioc_irq_unmask,
+};
+
+
+static inline int rbtx4939_ioc_irqroute(void)
+{
+        unsigned char istat = readb(rbtx4939_ifac2_addr);
+
+        if (unlikely(istat == 0))
+                return -1;
+        return RBTX4939_IRQ_IOC + __fls8(istat);
+}
+
+static int rbtx4939_irq_dispatch(int pending)
+{
+        int irq;
+
+        if (pending & CAUSEF_IP7)
+                return MIPS_CPU_IRQ_BASE + 7;
+        irq = tx4939_irq();
+        if (likely(irq >= 0)) {
+                /* redirect IOC interrupts */
+                switch (irq) {
+                case RBTX4939_IRQ_IOCINT:
+                        irq = rbtx4939_ioc_irqroute();
+                        break;
+                }
+        } else if (pending & CAUSEF_IP0)
+                irq = MIPS_CPU_IRQ_BASE + 0;
+        else if (pending & CAUSEF_IP1)
+                irq = MIPS_CPU_IRQ_BASE + 1;
+        else
+                irq = -1;
+        return irq;
+}
+
+void __init rbtx4939_irq_setup(void)
+{
+        int i;
+
+        /* mask all IOC interrupts */
+        writeb(0, rbtx4939_ien_addr);
+
+        /* clear SoftInt interrupts */
+        writeb(0, rbtx4939_softint_addr);
+
+        txx9_irq_dispatch = rbtx4939_irq_dispatch;
+
+        tx4939_irq_init();
+        for (i = RBTX4939_IRQ_IOC;
+             i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
+                set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
+                                         handle_level_irq);
+
+        set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
+}
diff --git a/arch/mips/txx9/rbtx4939/prom.c b/arch/mips/txx9/rbtx4939/prom.c
new file mode 100644
index 000000000000..bd277ecb4ad6
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/prom.c
@@ -0,0 +1,17 @@
+/*
+ * rbtx4939 specific prom routines
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/rbtx4939.h>
+
+void __init rbtx4939_prom_init(void)
+{
+        tx4939_add_memory_regions();
+        txx9_sio_putchar_init(TX4939_SIO_REG(0) & 0xfffffffffULL);
+}
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
new file mode 100644
index 000000000000..9855d7bccc20
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -0,0 +1,307 @@
+/*
+ * Toshiba RBTX4939 setup routines.
+ * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
+ *          and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <asm/reboot.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/pci.h>
+#include <asm/txx9/rbtx4939.h>
+
+static void rbtx4939_machine_restart(char *command)
+{
+        local_irq_disable();
+        writeb(1, rbtx4939_reseten_addr);
+        writeb(1, rbtx4939_softreset_addr);
+        while (1)
+                ;
+}
+
+static void __init rbtx4939_time_init(void)
+{
+        tx4939_time_init(0);
+}
+
+static void __init rbtx4939_pci_setup(void)
+{
+#ifdef CONFIG_PCI
+        int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
+        struct pci_controller *c = &txx9_primary_pcic;
+
+        register_pci_controller(c);
+
+        tx4939_report_pciclk();
+        tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
+        if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
+            (__raw_readq(&tx4939_ccfgptr->pcfg) &
+             (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
+                tx4939_report_pci1clk();
+
+                /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
+                c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
+                register_pci_controller(c);
+                tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
+        }
+
+        tx4939_setup_pcierr_irq();
+#endif /* CONFIG_PCI */
+}
+
+static unsigned long long default_ebccr[] __initdata = {
+        0x01c0000000007608ULL, /* 64M ROM */
+        0x017f000000007049ULL, /* 1M IOC */
+        0x0180000000408608ULL, /* ISA */
+        0,
+};
+
+static void __init rbtx4939_ebusc_setup(void)
+{
+        int i;
+        unsigned int sp;
+
+        /* use user-configured speed */
+        sp = TX4939_EBUSC_CR(0) & 0x30;
+        default_ebccr[0] |= sp;
+        default_ebccr[1] |= sp;
+        default_ebccr[2] |= sp;
+        /* initialise by myself */
+        for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
+                if (default_ebccr[i])
+                        ____raw_writeq(default_ebccr[i],
+                                       &tx4939_ebuscptr->cr[i]);
+                else
+                        ____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
+                                       & ~8,
+                                       &tx4939_ebuscptr->cr[i]);
+        }
+}
+
+static void __init rbtx4939_update_ioc_pen(void)
+{
+        __u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
+        __u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
+        __u8 pe1 = readb(rbtx4939_pe1_addr);
+        __u8 pe2 = readb(rbtx4939_pe2_addr);
+        __u8 pe3 = readb(rbtx4939_pe3_addr);
+        if (pcfg & TX4939_PCFG_ATA0MODE)
+                pe1 |= RBTX4939_PE1_ATA(0);
+        else
+                pe1 &= ~RBTX4939_PE1_ATA(0);
+        if (pcfg & TX4939_PCFG_ATA1MODE) {
+                pe1 |= RBTX4939_PE1_ATA(1);
+                pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1));
+        } else {
+                pe1 &= ~RBTX4939_PE1_ATA(1);
+                if (pcfg & TX4939_PCFG_ET0MODE)
+                        pe1 |= RBTX4939_PE1_RMII(0);
+                else
+                        pe1 &= ~RBTX4939_PE1_RMII(0);
+                if (pcfg & TX4939_PCFG_ET1MODE)
+                        pe1 |= RBTX4939_PE1_RMII(1);
+                else
+                        pe1 &= ~RBTX4939_PE1_RMII(1);
+        }
+        if (ccfg & TX4939_CCFG_PTSEL)
+                pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
+                         RBTX4939_PE3_VP_S);
+        else {
+                __u64 vmode = pcfg &
+                        (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE);
+                if (vmode == 0)
+                        pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
+                                 RBTX4939_PE3_VP_S);
+                else if (vmode == TX4939_PCFG_VPSMODE) {
+                        pe3 |= RBTX4939_PE3_VP_P;
+                        pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S);
+                } else if (vmode == TX4939_PCFG_VSSMODE) {
+                        pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S;
+                        pe3 &= ~RBTX4939_PE3_VP_P;
+                } else {
+                        pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P;
+                        pe3 &= ~RBTX4939_PE3_VP_S;
+                }
+        }
+        if (pcfg & TX4939_PCFG_SPIMODE) {
+                if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
+                        pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0);
+                else {
+                        if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
+                                pe2 |= RBTX4939_PE2_SIO2;
+                                pe2 &= ~RBTX4939_PE2_SIO0;
+                        } else {
+                                pe2 |= RBTX4939_PE2_SIO0;
+                                pe2 &= ~RBTX4939_PE2_SIO2;
+                        }
+                }
+                if (pcfg & TX4939_PCFG_SIO3MODE)
+                        pe2 |= RBTX4939_PE2_SIO3;
+                else
+                        pe2 &= ~RBTX4939_PE2_SIO3;
+                pe2 &= ~RBTX4939_PE2_SPI;
+        } else {
+                pe2 |= RBTX4939_PE2_SPI;
+                pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 |
+                         RBTX4939_PE2_SIO0);
+        }
+        if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
+                pe2 |= RBTX4939_PE2_GPIO;
+        else
+                pe2 &= ~RBTX4939_PE2_GPIO;
+        writeb(pe1, rbtx4939_pe1_addr);
+        writeb(pe2, rbtx4939_pe2_addr);
+        writeb(pe3, rbtx4939_pe3_addr);
+}
+
+#define RBTX4939_MAX_7SEGLEDS   8
+
+#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
+static u8 led_val[RBTX4939_MAX_7SEGLEDS];
+struct rbtx4939_led_data {
+        struct led_classdev cdev;
+        char name[32];
+        unsigned int num;
+};
+
+/* Use "dot" in 7seg LEDs */
+static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
+                                        enum led_brightness value)
+{
+        struct rbtx4939_led_data *led_dat =
+                container_of(led_cdev, struct rbtx4939_led_data, cdev);
+        unsigned int num = led_dat->num;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0);
+        writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
+        local_irq_restore(flags);
+}
+
+static int __init rbtx4939_led_probe(struct platform_device *pdev)
+{
+        struct rbtx4939_led_data *leds_data;
+        int i;
+        static char *default_triggers[] __initdata = {
+                "heartbeat",
+                "ide-disk",
+                "nand-disk",
+        };
+
+        leds_data = kzalloc(sizeof(*leds_data) * RBTX4939_MAX_7SEGLEDS,
+                            GFP_KERNEL);
+        if (!leds_data)
+                return -ENOMEM;
+        for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
+                int rc;
+                struct rbtx4939_led_data *led_dat = &leds_data[i];
+
+                led_dat->num = i;
+                led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
+                sprintf(led_dat->name, "rbtx4939:amber:%u", i);
+                led_dat->cdev.name = led_dat->name;
+                if (i < ARRAY_SIZE(default_triggers))
+                        led_dat->cdev.default_trigger = default_triggers[i];
+                rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
+                if (rc < 0)
+                        return rc;
+                led_dat->cdev.brightness_set(&led_dat->cdev, 0);
+        }
+        return 0;
+
+}
+
+static struct platform_driver rbtx4939_led_driver = {
+        .driver  = {
+                .name = "rbtx4939-led",
+                .owner = THIS_MODULE,
+        },
+};
+
+static void __init rbtx4939_led_setup(void)
+{
+        platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
+        platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
+}
+#else
+static inline void rbtx4939_led_setup(void)
+{
+}
+#endif
+
+static void __init rbtx4939_arch_init(void)
+{
+        rbtx4939_pci_setup();
+}
+
+static void __init rbtx4939_device_init(void)
+{
+#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
+        int i, j;
+        unsigned char ethaddr[2][6];
+        for (i = 0; i < 2; i++) {
+                unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
+                if (readb(rbtx4939_bdipsw_addr) & 8) {
+                        u16 buf[3];
+                        area -= 0x03000000;
+                        for (j = 0; j < 3; j++)
+                                buf[j] = le16_to_cpup((u16 *)(area + j * 2));
+                        memcpy(ethaddr[i], buf, 6);
+                } else
+                        memcpy(ethaddr[i], (void *)area, 6);
+        }
+        tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
+#endif
+        rbtx4939_led_setup();
+        tx4939_wdt_init();
+        tx4939_ata_init();
+}
+
+static void __init rbtx4939_setup(void)
+{
+        rbtx4939_ebusc_setup();
+        /* always enable ATA0 */
+        txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
+        rbtx4939_update_ioc_pen();
+        if (txx9_master_clock == 0)
+                txx9_master_clock = 20000000;
+        tx4939_setup();
+
+        _machine_restart = rbtx4939_machine_restart;
+
+        pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
+                readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
+                readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
+
+#ifdef CONFIG_PCI
+        txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
+        txx9_board_pcibios_setup = tx4927_pcibios_setup;
+#else
+        set_io_port_base(RBTX4939_ETHER_BASE);
+#endif
+
+        tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
+}
+
+struct txx9_board_vec rbtx4939_vec __initdata = {
+        .system = "Tothiba RBTX4939",
+        .prom_init = rbtx4939_prom_init,
+        .mem_setup = rbtx4939_setup,
+        .irq_setup = rbtx4939_irq_setup,
+        .time_init = rbtx4939_time_init,
+        .device_init = rbtx4939_device_init,
+        .arch_init = rbtx4939_arch_init,
+#ifdef CONFIG_PCI
+        .pci_map_irq = tx4939_pci_map_irq,
+#endif
+};
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index cba36a247e32..92dd1a0ca352 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -72,6 +72,7 @@ static void irq_dispatch(unsigned int irq)
         cascade = irq_cascade + irq;
         if (cascade->get_irq != NULL) {
                 unsigned int source_irq = irq;
+                int ret;
                 desc = irq_desc + source_irq;
                 if (desc->chip->mask_ack)
                         desc->chip->mask_ack(source_irq);
@@ -79,8 +80,9 @@ static void irq_dispatch(unsigned int irq)
                         desc->chip->mask(source_irq);
                         desc->chip->ack(source_irq);
                 }
-                irq = cascade->get_irq(irq);
-                if (irq < 0)
+                ret = cascade->get_irq(irq);
+                irq = ret;
+                if (ret < 0)
                         atomic_inc(&irq_err_count);
                 else
                         irq_dispatch(irq);
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c
index 761c434a2488..56c64ccc9c21 100644
--- a/arch/mn10300/kernel/irq.c
+++ b/arch/mn10300/kernel/irq.c
@@ -20,22 +20,8 @@ EXPORT_SYMBOL(__mn10300_irq_enabled_epsw);
 atomic_t irq_err_count;
 
 /*
- * MN10300 INTC controller operations
+ * MN10300 interrupt controller operations
  */
-static void mn10300_cpupic_disable(unsigned int irq)
-{
-        u16 tmp = GxICR(irq);
-        GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
-        tmp = GxICR(irq);
-}
-
-static void mn10300_cpupic_enable(unsigned int irq)
-{
-        u16 tmp = GxICR(irq);
-        GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE;
-        tmp = GxICR(irq);
-}
-
 static void mn10300_cpupic_ack(unsigned int irq)
 {
         u16 tmp;
@@ -60,26 +46,54 @@ static void mn10300_cpupic_mask_ack(unsigned int irq)
 static void mn10300_cpupic_unmask(unsigned int irq)
 {
         u16 tmp = GxICR(irq);
-        GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
+        GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE;
         tmp = GxICR(irq);
 }
 
-static void mn10300_cpupic_end(unsigned int irq)
+static void mn10300_cpupic_unmask_clear(unsigned int irq)
 {
+        /* the MN10300 PIC latches its interrupt request bit, even after the
+         * device has ceased to assert its interrupt line and the interrupt
+         * channel has been disabled in the PIC, so for level-triggered
+         * interrupts we need to clear the request bit when we re-enable */
         u16 tmp = GxICR(irq);
-        GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE;
+        GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
         tmp = GxICR(irq);
 }
 
-static struct irq_chip mn10300_cpu_pic = {
-        .name           = "cpu",
-        .disable        = mn10300_cpupic_disable,
-        .enable         = mn10300_cpupic_enable,
+/*
+ * MN10300 PIC level-triggered IRQ handling.
+ *
+ * The PIC has no 'ACK' function per se.  It is possible to clear individual
+ * channel latches, but each latch relatches whether or not the channel is
+ * masked, so we need to clear the latch when we unmask the channel.
+ *
+ * Also for this reason, we don't supply an ack() op (it's unused anyway if
+ * mask_ack() is provided), and mask_ack() just masks.
+ */
+static struct irq_chip mn10300_cpu_pic_level = {
+        .name           = "cpu_l",
+        .disable        = mn10300_cpupic_mask,
+        .enable         = mn10300_cpupic_unmask_clear,
+        .ack            = NULL,
+        .mask           = mn10300_cpupic_mask,
+        .mask_ack       = mn10300_cpupic_mask,
+        .unmask         = mn10300_cpupic_unmask_clear,
+};
+
+/*
+ * MN10300 PIC edge-triggered IRQ handling.
+ *
+ * We use the latch clearing function of the PIC as the 'ACK' function.
+ */
+static struct irq_chip mn10300_cpu_pic_edge = {
+        .name           = "cpu_e",
+        .disable        = mn10300_cpupic_mask,
+        .enable         = mn10300_cpupic_unmask,
         .ack            = mn10300_cpupic_ack,
         .mask           = mn10300_cpupic_mask,
         .mask_ack       = mn10300_cpupic_mask_ack,
         .unmask         = mn10300_cpupic_unmask,
-        .end            = mn10300_cpupic_end,
 };
 
 /*
@@ -114,7 +128,8 @@ void set_intr_level(int irq, u16 level)
  */
 void set_intr_postackable(int irq)
 {
-        set_irq_handler(irq, handle_level_irq);
+        set_irq_chip_and_handler(irq, &mn10300_cpu_pic_level,
+                                 handle_level_irq);
 }
 
 /*
@@ -126,8 +141,12 @@ void __init init_IRQ(void)
 
         for (irq = 0; irq < NR_IRQS; irq++)
                 if (irq_desc[irq].chip == &no_irq_type)
-                        set_irq_chip_and_handler(irq, &mn10300_cpu_pic,
-                                                 handle_edge_irq);
+                        /* due to the PIC latching interrupt requests, even
+                         * when the IRQ is disabled, IRQ_PENDING is superfluous
+                         * and we can use handle_level_irq() for edge-triggered
+                         * interrupts */
+                        set_irq_chip_and_handler(irq, &mn10300_cpu_pic_edge,
+                                                 handle_level_irq);
         unit_init_IRQ();
 }
 
diff --git a/arch/mn10300/kernel/time.c b/arch/mn10300/kernel/time.c
index babb7c2ac377..e4606586f94c 100644
--- a/arch/mn10300/kernel/time.c
+++ b/arch/mn10300/kernel/time.c
@@ -1,6 +1,6 @@
 /* MN10300 Low level time management
  *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Copyright (C) 2007-2008 Red Hat, Inc. All Rights Reserved.
  * Written by David Howells (dhowells@redhat.com)
  * - Derived from arch/i386/kernel/time.c
  *
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/profile.h>
+#include <linux/cnt32_to_63.h>
 #include <asm/irq.h>
 #include <asm/div64.h>
 #include <asm/processor.h>
@@ -40,27 +41,54 @@ static struct irqaction timer_irq = {
         .name           = "timer",
 };
 
+static unsigned long sched_clock_multiplier;
+
 /*
  * scheduler clock - returns current time in nanosec units.
  */
 unsigned long long sched_clock(void)
 {
         union {
-                unsigned long long l;
-                u32 w[2];
-        } quot;
+                unsigned long long ll;
+                unsigned l[2];
+        } tsc64, result;
+        unsigned long tsc, tmp;
+        unsigned product[3]; /* 96-bit intermediate value */
+
+        /* read the TSC value
+         */
+        tsc = 0 - get_cycles(); /* get_cycles() counts down */
 
-        quot.w[0] = mn10300_last_tsc - get_cycles();
-        quot.w[1] = 1000000000;
+        /* expand to 64-bits.
+         * - sched_clock() must be called once a minute or better or the
+         *   following will go horribly wrong - see cnt32_to_63()
+         */
+        tsc64.ll = cnt32_to_63(tsc) & 0x7fffffffffffffffULL;
 
-        asm("mulu %2,%3,%0,%1"
-            : "=r"(quot.w[1]), "=r"(quot.w[0])
-            : "0"(quot.w[1]), "1"(quot.w[0])
+        /* scale the 64-bit TSC value to a nanosecond value via a 96-bit
+         * intermediate
+         */
+        asm("mulu       %2,%0,%3,%0     \n"     /* LSW * mult ->  0:%3:%0 */
+            "mulu       %2,%1,%2,%1     \n"     /* MSW * mult -> %2:%1:0 */
+            "add        %3,%1           \n"
+            "addc       0,%2            \n"     /* result in %2:%1:%0 */
+            : "=r"(product[0]), "=r"(product[1]), "=r"(product[2]), "=r"(tmp)
+            :  "0"(tsc64.l[0]),  "1"(tsc64.l[1]),  "2"(sched_clock_multiplier)
             : "cc");
 
-        do_div(quot.l, MN10300_TSCCLK);
+        result.l[0] = product[1] << 16 | product[0] >> 16;
+        result.l[1] = product[2] << 16 | product[1] >> 16;
 
-        return quot.l;
+        return result.ll;
+}
+
+/*
+ * initialise the scheduler clock
+ */
+static void __init mn10300_sched_clock_init(void)
+{
+        sched_clock_multiplier =
+                __muldiv64u(NSEC_PER_SEC, 1 << 16, MN10300_TSCCLK);
 }
 
 /*
@@ -128,4 +156,6 @@ void __init time_init(void)
         /* start the watchdog timer */
         watchdog_go();
 #endif
+
+        mn10300_sched_clock_init();
 }
diff --git a/arch/mn10300/mm/fault.c b/arch/mn10300/mm/fault.c
index 78f092ca0316..33cf25025dac 100644
--- a/arch/mn10300/mm/fault.c
+++ b/arch/mn10300/mm/fault.c
@@ -174,7 +174,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long fault_code,
          * If we're in an interrupt or have no user
          * context, we must not take the fault..
          */
-        if (in_interrupt() || !mm)
+        if (in_atomic() || !mm)
                 goto no_context;
 
         down_read(&mm->mmap_sem);
diff --git a/arch/mn10300/unit-asb2303/unit-init.c b/arch/mn10300/unit-asb2303/unit-init.c
index 14b2c817cff8..70e8cb4ea266 100644
--- a/arch/mn10300/unit-asb2303/unit-init.c
+++ b/arch/mn10300/unit-asb2303/unit-init.c
@@ -51,7 +51,7 @@ void __init unit_init_IRQ(void)
                 switch (GET_XIRQ_TRIGGER(extnum)) {
                 case XIRQ_TRIGGER_HILEVEL:
                 case XIRQ_TRIGGER_LOWLEVEL:
-                        set_irq_handler(XIRQ2IRQ(extnum), handle_level_irq);
+                        set_intr_postackable(XIRQ2IRQ(extnum));
                         break;
                 default:
                         break;
diff --git a/arch/mn10300/unit-asb2305/unit-init.c b/arch/mn10300/unit-asb2305/unit-init.c
index 6a352414a358..72812a9439ac 100644
--- a/arch/mn10300/unit-asb2305/unit-init.c
+++ b/arch/mn10300/unit-asb2305/unit-init.c
@@ -52,7 +52,7 @@ void __init unit_init_IRQ(void)
                 switch (GET_XIRQ_TRIGGER(extnum)) {
                 case XIRQ_TRIGGER_HILEVEL:
                 case XIRQ_TRIGGER_LOWLEVEL:
-                        set_irq_handler(XIRQ2IRQ(extnum), handle_level_irq);
+                        set_intr_postackable(XIRQ2IRQ(extnum));
                         break;
                 default:
                         break;
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 717a3bc1352e..65d1a8454d2c 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -195,7 +195,7 @@ image-$(CONFIG_PPC_CELLEB)		+= zImage.pseries
 image-$(CONFIG_PPC_CHRP)                += zImage.chrp
 image-$(CONFIG_PPC_EFIKA)               += zImage.chrp
 image-$(CONFIG_PPC_PMAC)                += zImage.pmac
-image-$(CONFIG_PPC_HOLLY)               += zImage.holly
+image-$(CONFIG_PPC_HOLLY)               += dtbImage.holly
 image-$(CONFIG_PPC_PRPMC2800)           += dtbImage.prpmc2800
 image-$(CONFIG_PPC_ISERIES)             += zImage.iseries
 image-$(CONFIG_DEFAULT_UIMAGE)          += uImage
diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts
index f87fe7b9ced9..c6e11ebecebb 100644
--- a/arch/powerpc/boot/dts/holly.dts
+++ b/arch/powerpc/boot/dts/holly.dts
@@ -133,61 +133,61 @@
                         reg = <0x00007400 0x00000400>;
                         big-endian;
                 };
+        };
 
-                pci@1000 {
-                        device_type = "pci";
-                        compatible = "tsi109-pci", "tsi108-pci";
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        reg = <0x00001000 0x00001000>;
-                        bus-range = <0x0 0x0>;
-                        /*----------------------------------------------------+
-                        | PCI memory range.
-                        | 01 denotes I/O space
-                        | 02 denotes 32-bit memory space
-                        +----------------------------------------------------*/
-                        ranges = <0x02000000 0x00000000 0x40000000 0x40000000 0x00000000 0x10000000
-                                  0x01000000 0x00000000 0x00000000 0x7e000000 0x00000000 0x00010000>;
-                        clock-frequency = <133333332>;
-                        interrupt-parent = <&MPIC>;
+        pci@c0001000 {
+                device_type = "pci";
+                compatible = "tsi109-pci", "tsi108-pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xc0001000 0x00001000>;
+                bus-range = <0x0 0x0>;
+                /*----------------------------------------------------+
+                | PCI memory range.
+                | 01 denotes I/O space
+                | 02 denotes 32-bit memory space
+                +----------------------------------------------------*/
+                ranges = <0x02000000 0x00000000 0x40000000 0x40000000 0x00000000 0x10000000
+                          0x01000000 0x00000000 0x00000000 0x7e000000 0x00000000 0x00010000>;
+                clock-frequency = <133333332>;
+                interrupt-parent = <&MPIC>;
+                interrupts = <0x17 0x2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                /*----------------------------------------------------+
+                | The INTA, INTB, INTC, INTD are shared.
+                +----------------------------------------------------*/
+                interrupt-map = <
+                        0x800 0x0 0x0 0x1 &RT0 0x24 0x0
+                        0x800 0x0 0x0 0x2 &RT0 0x25 0x0
+                        0x800 0x0 0x0 0x3 &RT0 0x26 0x0
+                        0x800 0x0 0x0 0x4 &RT0 0x27 0x0
+
+                        0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
+                        0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
+                        0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
+                        0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
+
+                        0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
+                        0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
+                        0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
+                        0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
+
+                        0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
+                        0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
+                        0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
+                        0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
+                        >;
+
+                RT0: router@1180 {
+                        device_type = "pic-router";
+                        interrupt-controller;
+                        big-endian;
+                        clock-frequency = <0>;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
                         interrupts = <0x17 0x2>;
-                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                        /*----------------------------------------------------+
-                        | The INTA, INTB, INTC, INTD are shared.
-                        +----------------------------------------------------*/
-                        interrupt-map = <
-                                0x800 0x0 0x0 0x1 &RT0 0x24 0x0
-                                0x800 0x0 0x0 0x2 &RT0 0x25 0x0
-                                0x800 0x0 0x0 0x3 &RT0 0x26 0x0
-                                0x800 0x0 0x0 0x4 &RT0 0x27 0x0
-
-                                0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
-                                0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
-                                0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
-                                0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
-
-                                0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
-                                0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
-                                0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
-                                0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
-
-                                0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
-                                0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
-                                0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
-                                0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
-                                >;
-
-                        RT0: router@1180 {
-                                device_type = "pic-router";
-                                interrupt-controller;
-                                big-endian;
-                                clock-frequency = <0>;
-                                #address-cells = <0>;
-                                #interrupt-cells = <2>;
-                                interrupts = <0x17 0x2>;
-                                interrupt-parent = <&MPIC>;
-                        };
+                        interrupt-parent = <&MPIC>;
                 };
         };
 
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 3b3a1062cb25..584a4f184eb2 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -281,7 +281,7 @@
                                 cell-index = <0>;
                                 reg = <0x0 0x80>;
                                 interrupt-parent = <&mpic>;
-                                interrupts = <60 2>;
+                                interrupts = <76 2>;
                         };
                         dma-channel@1 {
                                 compatible = "fsl,mpc8610-dma-channel",
@@ -289,7 +289,7 @@
                                 cell-index = <1>;
                                 reg = <0x80 0x80>;
                                 interrupt-parent = <&mpic>;
-                                interrupts = <61 2>;
+                                interrupts = <77 2>;
                         };
                         dma-channel@2 {
                                 compatible = "fsl,mpc8610-dma-channel",
@@ -297,7 +297,7 @@
                                 cell-index = <2>;
                                 reg = <0x100 0x80>;
                                 interrupt-parent = <&mpic>;
-                                interrupts = <62 2>;
+                                interrupts = <78 2>;
                         };
                         dma-channel@3 {
                                 compatible = "fsl,mpc8610-dma-channel",
@@ -305,7 +305,7 @@
                                 cell-index = <3>;
                                 reg = <0x180 0x80>;
                                 interrupt-parent = <&mpic>;
-                                interrupts = <63 2>;
+                                interrupts = <79 2>;
                         };
                 };
 
diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h
index 29b0ecef980a..f15296cf3598 100644
--- a/arch/powerpc/include/asm/dcr-regs.h
+++ b/arch/powerpc/include/asm/dcr-regs.h
@@ -68,6 +68,10 @@
 #define SDR0_UART3              0x0123
 #define SDR0_CUST0              0x4000
 
+/* SDRs (460EX/460GT) */
+#define SDR0_ETH_CFG            0x4103
+#define SDR0_ETH_CFG_ECS        0x00000100      /* EMAC int clk source */
+
 /*
  * All those DCR register addresses are offsets from the base address
  * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
index 80d1f399ee51..64c6ee22eefd 100644
--- a/arch/powerpc/include/asm/elf.h
+++ b/arch/powerpc/include/asm/elf.h
@@ -409,6 +409,13 @@ do {									\
 /* Keep this the last entry.  */
 #define R_PPC64_NUM             107
 
+/* There's actually a third entry here, but it's unused */
+struct ppc64_opd_entry
+{
+        unsigned long funcaddr;
+        unsigned long r2;
+};
+
 #ifdef  __KERNEL__
 
 #ifdef CONFIG_SPU_BASE
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
index 7710e9e6660f..07956f3e7844 100644
--- a/arch/powerpc/include/asm/sections.h
+++ b/arch/powerpc/include/asm/sections.h
@@ -2,6 +2,8 @@
 #define _ASM_POWERPC_SECTIONS_H
 #ifdef __KERNEL__
 
+#include <linux/elf.h>
+#include <linux/uaccess.h>
 #include <asm-generic/sections.h>
 
 #ifdef __powerpc64__
@@ -17,7 +19,15 @@ static inline int in_kernel_text(unsigned long addr)
 }
 
 #undef dereference_function_descriptor
-void *dereference_function_descriptor(void *);
+static inline void *dereference_function_descriptor(void *ptr)
+{
+        struct ppc64_opd_entry *desc = ptr;
+        void *p;
+
+        if (!probe_kernel_address(&desc->funcaddr, p))
+                ptr = p;
+        return ptr;
+}
 
 #endif
 
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index d308a9f70f1b..31982d05d81a 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -34,11 +34,7 @@
 #include <asm/smp.h>
 
 #ifdef CONFIG_HOTPLUG_CPU
-/* this is used for software suspend, and that shuts down
- * CPUs even while the system is still booting... */
-#define cpu_should_die()        (cpu_is_offline(smp_processor_id()) && \
-                                   (system_state == SYSTEM_RUNNING     \
-                                 || system_state == SYSTEM_BOOTING))
+#define cpu_should_die()        cpu_is_offline(smp_processor_id())
 #else
 #define cpu_should_die()        0
 #endif
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index b4fdf2f2743c..fe8f71dd0b3f 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -347,9 +347,8 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code,
                         linux_regs->msr |= MSR_SE;
 #endif
                         kgdb_single_step = 1;
-                        if (kgdb_contthread)
-                                atomic_set(&kgdb_cpu_doing_single_step,
-                                           raw_smp_processor_id());
+                        atomic_set(&kgdb_cpu_doing_single_step,
+                                   raw_smp_processor_id());
                 }
                 return 0;
         }
diff --git a/arch/powerpc/kernel/module_64.c b/arch/powerpc/kernel/module_64.c
index ad79de272ff3..1af2377e4992 100644
--- a/arch/powerpc/kernel/module_64.c
+++ b/arch/powerpc/kernel/module_64.c
@@ -21,9 +21,7 @@
 #include <linux/err.h>
 #include <linux/vmalloc.h>
 #include <linux/bug.h>
-#include <linux/uaccess.h>
 #include <asm/module.h>
-#include <asm/sections.h>
 #include <asm/firmware.h>
 #include <asm/code-patching.h>
 #include <linux/sort.h>
@@ -43,13 +41,6 @@
 #define DEBUGP(fmt , ...)
 #endif
 
-/* There's actually a third entry here, but it's unused */
-struct ppc64_opd_entry
-{
-        unsigned long funcaddr;
-        unsigned long r2;
-};
-
 /* Like PPC32, we need little trampolines to do > 24-bit jumps (into
    the kernel itself).  But on PPC64, these need to be used for every
    jump, actually, to reset r2 (TOC+0x8000). */
@@ -452,13 +443,3 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
 
         return 0;
 }
-
-void *dereference_function_descriptor(void *ptr)
-{
-        struct ppc64_opd_entry *desc = ptr;
-        void *p;
-
-        if (!probe_kernel_address(&desc->funcaddr, p))
-                ptr = p;
-        return ptr;
-}
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 5337ca7bb649..c27b10a1bd79 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -453,6 +453,7 @@ int __devinit start_secondary(void *unused)
         secondary_cpu_time_init();
 
         ipi_call_lock();
+        notify_cpu_starting(cpu);
         cpu_set(cpu, cpu_online_map);
         /* Update sibling maps */
         base = cpu_first_thread_in_core(cpu);
diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
index d5770fdf7f09..0eb6d7f62241 100644
--- a/arch/powerpc/platforms/82xx/ep8248e.c
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -137,7 +137,7 @@ static int __devinit ep8248e_mdio_probe(struct of_device *ofdev,
                 bus->irq[i] = -1;
 
         bus->name = "ep8248e-mdio-bitbang";
-        bus->dev = &ofdev->dev;
+        bus->parent = &ofdev->dev;
         snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
 
         return mdiobus_register(bus);
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c
index ef74a0763ec1..8c619963becc 100644
--- a/arch/powerpc/platforms/fsl_uli1575.c
+++ b/arch/powerpc/platforms/fsl_uli1575.c
@@ -219,11 +219,21 @@ static void __devinit quirk_final_uli5249(struct pci_dev *dev)
         int i;
         u8 *dummy;
         struct pci_bus *bus = dev->bus;
+        resource_size_t end = 0;
+
+        for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCES+3; i++) {
+                unsigned long flags = pci_resource_flags(dev, i);
+                if ((flags & (IORESOURCE_MEM|IORESOURCE_PREFETCH)) == IORESOURCE_MEM)
+                        end = pci_resource_end(dev, i);
+        }
 
         for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
                 if ((bus->resource[i]) &&
                         (bus->resource[i]->flags & IORESOURCE_MEM)) {
-                        dummy = ioremap(bus->resource[i]->end - 3, 0x4);
+                        if (bus->resource[i]->end == end)
+                                dummy = ioremap(bus->resource[i]->start, 0x4);
+                        else
+                                dummy = ioremap(bus->resource[i]->end - 3, 0x4);
                         if (dummy) {
                                 in_8(dummy);
                                 iounmap(dummy);
diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c
index ab6955412ba4..75cc165d5bee 100644
--- a/arch/powerpc/platforms/pasemi/gpio_mdio.c
+++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c
@@ -230,7 +230,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
         if (!priv)
                 goto out;
 
-        new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
+        new_bus = mdiobus_alloc();
 
         if (!new_bus)
                 goto out_free_priv;
@@ -272,7 +272,7 @@ static int __devinit gpio_mdio_probe(struct of_device *ofdev,
         prop = of_get_property(np, "mdio-pin", NULL);
         priv->mdio_pin = *prop;
 
-        new_bus->dev = dev;
+        new_bus->parent = dev;
         dev_set_drvdata(dev, new_bus);
 
         err = mdiobus_register(new_bus);
@@ -306,7 +306,7 @@ static int gpio_mdio_remove(struct of_device *dev)
 
         kfree(bus->priv);
         bus->priv = NULL;
-        kfree(bus);
+        mdiobus_free(bus);
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index 32e0ad0ebea8..b6bd775d2e22 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -293,10 +293,8 @@ static int __init mv64x60_eth_device_setup(struct device_node *np, int id,
                 return -ENODEV;
 
         prop = of_get_property(phy, "reg", NULL);
-        if (prop) {
-                pdata.force_phy_addr = 1;
-                pdata.phy_addr = *prop;
-        }
+        if (prop)
+                pdata.phy_addr = MV643XX_ETH_PHY_ADDR(*prop);
 
         of_node_put(phy);
 
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 8d41908e2513..4c03049e7db9 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -74,6 +74,7 @@ config S390
         select HAVE_KPROBES
         select HAVE_KRETPROBES
         select HAVE_KVM if 64BIT
+        select HAVE_ARCH_TRACEHOOK
 
 source "init/Kconfig"
 
diff --git a/arch/s390/include/asm/dasd.h b/arch/s390/include/asm/dasd.h
index 3f002e13d024..55b2b80cdf6e 100644
--- a/arch/s390/include/asm/dasd.h
+++ b/arch/s390/include/asm/dasd.h
@@ -3,6 +3,8 @@
  * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
  * Bugreports.to..: <Linux390@de.ibm.com>
  * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000
+ * EMC Symmetrix ioctl Copyright EMC Corporation, 2008
+ * Author.........: Nigel Hislop <hislop_nigel@emc.com>
  *
  * This file is the interface of the DASD device driver, which is exported to user space
  * any future changes wrt the API will result in a change of the APIVERSION reported
@@ -202,6 +204,16 @@ typedef struct attrib_data_t {
 #define DASD_SEQ_PRESTAGE  0x4
 #define DASD_REC_ACCESS    0x5
 
+/*
+ * Perform EMC Symmetrix I/O
+ */
+typedef struct dasd_symmio_parms {
+        unsigned char reserved[8];      /* compat with older releases */
+        unsigned long long psf_data;    /* char * cast to u64 */
+        unsigned long long rssd_result; /* char * cast to u64 */
+        int psf_data_len;
+        int rssd_result_len;
+} __attribute__ ((packed)) dasd_symmio_parms_t;
 
 /********************************************************************************
  * SECTION: Definition of IOCTLs
@@ -247,6 +259,7 @@ typedef struct attrib_data_t {
 /* Set Attributes (cache operations) */
 #define BIODASDSATTR   _IOW(DASD_IOCTL_LETTER,2,attrib_data_t) 
 
+#define BIODASDSYMMIO  _IOWR(DASD_IOCTL_LETTER, 240, dasd_symmio_parms_t)
 
 #endif                          /* DASD_H */
 
diff --git a/arch/s390/include/asm/delay.h b/arch/s390/include/asm/delay.h
index 78357314c450..a356c958e260 100644
--- a/arch/s390/include/asm/delay.h
+++ b/arch/s390/include/asm/delay.h
@@ -15,6 +15,7 @@
 #define _S390_DELAY_H
 
 extern void __udelay(unsigned long usecs);
+extern void udelay_simple(unsigned long usecs);
 extern void __delay(unsigned long loops);
 
 #define udelay(n) __udelay(n)
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 0bdb704ae051..1a928f84afd6 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -281,6 +281,9 @@ extern char empty_zero_page[PAGE_SIZE];
 #define RCP_GR_BIT      50
 #define RCP_GC_BIT      49
 
+/* User dirty bit for KVM's migration feature */
+#define KVM_UD_BIT      47
+
 #ifndef __s390x__
 
 /* Bits in the segment table address-space-control-element */
@@ -575,12 +578,16 @@ static inline void ptep_rcp_copy(pte_t *ptep)
         unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
 
         skey = page_get_storage_key(page_to_phys(page));
-        if (skey & _PAGE_CHANGED)
+        if (skey & _PAGE_CHANGED) {
                 set_bit_simple(RCP_GC_BIT, pgste);
+                set_bit_simple(KVM_UD_BIT, pgste);
+        }
         if (skey & _PAGE_REFERENCED)
                 set_bit_simple(RCP_GR_BIT, pgste);
-        if (test_and_clear_bit_simple(RCP_HC_BIT, pgste))
+        if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) {
                 SetPageDirty(page);
+                set_bit_simple(KVM_UD_BIT, pgste);
+        }
         if (test_and_clear_bit_simple(RCP_HR_BIT, pgste))
                 SetPageReferenced(page);
 #endif
@@ -744,6 +751,40 @@ static inline pte_t pte_mkspecial(pte_t pte)
         return pte;
 }
 
+#ifdef CONFIG_PGSTE
+/*
+ * Get (and clear) the user dirty bit for a PTE.
+ */
+static inline int kvm_s390_test_and_clear_page_dirty(struct mm_struct *mm,
+                                                     pte_t *ptep)
+{
+        int dirty;
+        unsigned long *pgste;
+        struct page *page;
+        unsigned int skey;
+
+        if (!mm->context.pgstes)
+                return -EINVAL;
+        rcp_lock(ptep);
+        pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
+        page = virt_to_page(pte_val(*ptep));
+        skey = page_get_storage_key(page_to_phys(page));
+        if (skey & _PAGE_CHANGED) {
+                set_bit_simple(RCP_GC_BIT, pgste);
+                set_bit_simple(KVM_UD_BIT, pgste);
+        }
+        if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) {
+                SetPageDirty(page);
+                set_bit_simple(KVM_UD_BIT, pgste);
+        }
+        dirty = test_and_clear_bit_simple(KVM_UD_BIT, pgste);
+        if (skey & _PAGE_CHANGED)
+                page_clear_dirty(page);
+        rcp_unlock(ptep);
+        return dirty;
+}
+#endif
+
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
                                             unsigned long addr, pte_t *ptep)
diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h
index af2c9ac28a07..a7226f8143fb 100644
--- a/arch/s390/include/asm/ptrace.h
+++ b/arch/s390/include/asm/ptrace.h
@@ -490,6 +490,7 @@ extern void user_disable_single_step(struct task_struct *);
 
 #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
 #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
+#define user_stack_pointer(regs)((regs)->gprs[15])
 #define regs_return_value(regs)((regs)->gprs[2])
 #define profile_pc(regs) instruction_pointer(regs)
 extern void show_regs(struct pt_regs * regs);
diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h
index 6813772171f2..4734c3f05354 100644
--- a/arch/s390/include/asm/qdio.h
+++ b/arch/s390/include/asm/qdio.h
@@ -299,7 +299,13 @@ struct qdio_ssqd_desc {
         u8 mbccnt;
         u16 qdioac2;
         u64 sch_token;
-        u64:64;
+        u8 mro;
+        u8 mri;
+        u8:8;
+        u8 sbalic;
+        u16:16;
+        u8:8;
+        u8 mmwc;
 } __attribute__ ((packed));
 
 /* params are: ccw_device, qdio_error, queue_number,
diff --git a/arch/s390/include/asm/syscall.h b/arch/s390/include/asm/syscall.h
new file mode 100644
index 000000000000..6e623971fbb9
--- /dev/null
+++ b/arch/s390/include/asm/syscall.h
@@ -0,0 +1,80 @@
+/*
+ * Access to user system call parameters and results
+ *
+ *  Copyright IBM Corp. 2008
+ *  Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef _ASM_SYSCALL_H
+#define _ASM_SYSCALL_H  1
+
+#include <asm/ptrace.h>
+
+static inline long syscall_get_nr(struct task_struct *task,
+                                  struct pt_regs *regs)
+{
+        if (regs->trap != __LC_SVC_OLD_PSW)
+                return -1;
+        return regs->gprs[2];
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        regs->gprs[2] = regs->orig_gpr2;
+}
+
+static inline long syscall_get_error(struct task_struct *task,
+                                     struct pt_regs *regs)
+{
+        return (regs->gprs[2] >= -4096UL) ? -regs->gprs[2] : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        return regs->gprs[2];
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+                                            struct pt_regs *regs,
+                                            int error, long val)
+{
+        regs->gprs[2] = error ? -error : val;
+}
+
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         unsigned long *args)
+{
+        BUG_ON(i + n > 6);
+#ifdef CONFIG_COMPAT
+        if (test_tsk_thread_flag(task, TIF_31BIT)) {
+                if (i + n == 6)
+                        args[--n] = (u32) regs->args[0];
+                while (n-- > 0)
+                        args[n] = (u32) regs->gprs[2 + i + n];
+        }
+#endif
+        if (i + n == 6)
+                args[--n] = regs->args[0];
+        memcpy(args, &regs->gprs[2 + i], n * sizeof(args[0]));
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         const unsigned long *args)
+{
+        BUG_ON(i + n > 6);
+        if (i + n == 6)
+                regs->args[0] = args[--n];
+        memcpy(&regs->gprs[2 + i], args, n * sizeof(args[0]));
+}
+
+#endif  /* _ASM_SYSCALL_H */
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
index 91a8f93ad355..ea40a9d690fc 100644
--- a/arch/s390/include/asm/thread_info.h
+++ b/arch/s390/include/asm/thread_info.h
@@ -86,6 +86,7 @@ static inline struct thread_info *current_thread_info(void)
  * thread information flags bit numbers
  */
 #define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_NOTIFY_RESUME       1       /* callback before returning to user */
 #define TIF_SIGPENDING          2       /* signal pending */
 #define TIF_NEED_RESCHED        3       /* rescheduling necessary */
 #define TIF_RESTART_SVC         4       /* restart svc with new svc number */
@@ -100,6 +101,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_RESTORE_SIGMASK     20      /* restore signal mask in do_signal() */
 
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
diff --git a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c
index d7f22226fc4e..98e246dc0233 100644
--- a/arch/s390/kernel/compat_linux.c
+++ b/arch/s390/kernel/compat_linux.c
@@ -608,14 +608,6 @@ asmlinkage long sys32_settimeofday(struct compat_timeval __user *tv, struct time
         return do_sys_settimeofday(tv ? &kts : NULL, tz ? &ktz : NULL);
 }
 
-/* These are here just in case some old sparc32 binary calls it. */
-asmlinkage long sys32_pause(void)
-{
-        current->state = TASK_INTERRUPTIBLE;
-        schedule();
-        return -ERESTARTNOHAND;
-}
-
 asmlinkage long sys32_pread64(unsigned int fd, char __user *ubuf,
                                 size_t count, u32 poshi, u32 poslo)
 {
diff --git a/arch/s390/kernel/compat_linux.h b/arch/s390/kernel/compat_linux.h
index 20723a062017..05f8516366ab 100644
--- a/arch/s390/kernel/compat_linux.h
+++ b/arch/s390/kernel/compat_linux.h
@@ -206,7 +206,6 @@ long sys32_gettimeofday(struct compat_timeval __user *tv,
                         struct timezone __user *tz);
 long sys32_settimeofday(struct compat_timeval __user *tv,
                         struct timezone __user *tz);
-long sys32_pause(void);
 long sys32_pread64(unsigned int fd, char __user *ubuf, size_t count,
                    u32 poshi, u32 poslo);
 long sys32_pwrite64(unsigned int fd, const char __user *ubuf,
diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
index 328a20e880b5..ee51ca9e23b5 100644
--- a/arch/s390/kernel/compat_wrapper.S
+++ b/arch/s390/kernel/compat_wrapper.S
@@ -128,8 +128,6 @@ sys32_alarm_wrapper:
         llgfr   %r2,%r2                 # unsigned int
         jg      sys_alarm               # branch to system call
 
-#sys32_pause_wrapper                    # void
-
         .globl  compat_sys_utime_wrapper
 compat_sys_utime_wrapper:
         llgtr   %r2,%r2                 # char *
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 708cf9cf9a35..ed500ef799b7 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -49,9 +49,9 @@ SP_ILC	     =	STACK_FRAME_OVERHEAD + __PT_ILC
 SP_TRAP      =  STACK_FRAME_OVERHEAD + __PT_TRAP
 SP_SIZE      =  STACK_FRAME_OVERHEAD + __PT_SIZE
 
-_TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
+_TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
                  _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
-_TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
+_TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
                  _TIF_MCCK_PENDING)
 
 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
@@ -318,6 +318,8 @@ sysc_work:
         bo      BASED(sysc_reschedule)
         tm      __TI_flags+3(%r9),_TIF_SIGPENDING
         bnz     BASED(sysc_sigpending)
+        tm      __TI_flags+3(%r9),_TIF_NOTIFY_RESUME
+        bnz     BASED(sysc_notify_resume)
         tm      __TI_flags+3(%r9),_TIF_RESTART_SVC
         bo      BASED(sysc_restart)
         tm      __TI_flags+3(%r9),_TIF_SINGLE_STEP
@@ -356,6 +358,16 @@ sysc_sigpending:
         b       BASED(sysc_work_loop)
 
 #
+# _TIF_NOTIFY_RESUME is set, call do_notify_resume
+#
+sysc_notify_resume:
+        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        l       %r1,BASED(.Ldo_notify_resume)
+        la      %r14,BASED(sysc_work_loop)
+        br      %r1                     # call do_notify_resume
+
+
+#
 # _TIF_RESTART_SVC is set, set up registers and restart svc
 #
 sysc_restart:
@@ -378,20 +390,21 @@ sysc_singlestep:
         br      %r1                     # branch to do_single_step
 
 #
-# call trace before and after sys_call
+# call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
+# and after the system call
 #
 sysc_tracesys:
-        l       %r1,BASED(.Ltrace)
+        l       %r1,BASED(.Ltrace_entry)
         la      %r2,SP_PTREGS(%r15)     # load pt_regs
         la      %r3,0
         srl     %r7,2
         st      %r7,SP_R2(%r15)
         basr    %r14,%r1
-        clc     SP_R2(4,%r15),BASED(.Lnr_syscalls)
+        cl      %r2,BASED(.Lnr_syscalls)
         bnl     BASED(sysc_tracenogo)
         l       %r8,BASED(.Lsysc_table)
-        l       %r7,SP_R2(%r15)         # strace might have changed the
-        sll     %r7,2                   #  system call
+        lr      %r7,%r2
+        sll     %r7,2                   # *4
         l       %r8,0(%r7,%r8)
 sysc_tracego:
         lm      %r3,%r6,SP_R3(%r15)
@@ -401,9 +414,8 @@ sysc_tracego:
 sysc_tracenogo:
         tm      __TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
         bz      BASED(sysc_return)
-        l       %r1,BASED(.Ltrace)
+        l       %r1,BASED(.Ltrace_exit)
         la      %r2,SP_PTREGS(%r15)     # load pt_regs
-        la      %r3,1
         la      %r14,BASED(sysc_return)
         br      %r1
 
@@ -666,6 +678,8 @@ io_work_loop:
         bo      BASED(io_reschedule)
         tm      __TI_flags+3(%r9),_TIF_SIGPENDING
         bnz     BASED(io_sigpending)
+        tm      __TI_flags+3(%r9),_TIF_NOTIFY_RESUME
+        bnz     BASED(io_notify_resume)
         b       BASED(io_restore)
 io_work_done:
 
@@ -704,6 +718,19 @@ io_sigpending:
         TRACE_IRQS_OFF
         b       BASED(io_work_loop)
 
+#
+# _TIF_SIGPENDING is set, call do_signal
+#
+io_notify_resume:
+        TRACE_IRQS_ON
+        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
+        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        l       %r1,BASED(.Ldo_notify_resume)
+        basr    %r14,%r1                # call do_signal
+        stnsm   __SF_EMPTY(%r15),0xfc   # disable I/O and ext. interrupts
+        TRACE_IRQS_OFF
+        b       BASED(io_work_loop)
+
 /*
  * External interrupt handler routine
  */
@@ -1070,6 +1097,8 @@ cleanup_io_leave_insn:
 .Ldo_IRQ:       .long   do_IRQ
 .Ldo_extint:    .long   do_extint
 .Ldo_signal:    .long   do_signal
+.Ldo_notify_resume:
+                .long   do_notify_resume
 .Lhandle_per:   .long   do_single_step
 .Ldo_execve:    .long   do_execve
 .Lexecve_tail:  .long   execve_tail
@@ -1079,7 +1108,8 @@ cleanup_io_leave_insn:
 .Lpreempt_schedule_irq:
                 .long   preempt_schedule_irq
 #endif
-.Ltrace:        .long   syscall_trace
+.Ltrace_entry:  .long   do_syscall_trace_enter
+.Ltrace_exit:   .long   do_syscall_trace_exit
 .Lschedtail:    .long   schedule_tail
 .Lsysc_table:   .long   sys_call_table
 #ifdef CONFIG_TRACE_IRQFLAGS
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index fee10177dbfc..d7ce150453f2 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -52,9 +52,9 @@ SP_SIZE      =	STACK_FRAME_OVERHEAD + __PT_SIZE
 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
 STACK_SIZE  = 1 << STACK_SHIFT
 
-_TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
+_TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
                  _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
-_TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
+_TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
                  _TIF_MCCK_PENDING)
 
 #define BASED(name) name-system_call(%r13)
@@ -310,6 +310,8 @@ sysc_work:
         jo      sysc_reschedule
         tm      __TI_flags+7(%r9),_TIF_SIGPENDING
         jnz     sysc_sigpending
+        tm      __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
+        jnz     sysc_notify_resume
         tm      __TI_flags+7(%r9),_TIF_RESTART_SVC
         jo      sysc_restart
         tm      __TI_flags+7(%r9),_TIF_SINGLE_STEP
@@ -345,6 +347,14 @@ sysc_sigpending:
         j       sysc_work_loop
 
 #
+# _TIF_NOTIFY_RESUME is set, call do_notify_resume
+#
+sysc_notify_resume:
+        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        larl    %r14,sysc_work_loop
+        jg      do_notify_resume        # call do_notify_resume
+
+#
 # _TIF_RESTART_SVC is set, set up registers and restart svc
 #
 sysc_restart:
@@ -367,20 +377,19 @@ sysc_singlestep:
         jg      do_single_step          # branch to do_sigtrap
 
 #
-# call syscall_trace before and after system call
-# special linkage: %r12 contains the return address for trace_svc
+# call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
+# and after the system call
 #
 sysc_tracesys:
         la      %r2,SP_PTREGS(%r15)     # load pt_regs
         la      %r3,0
         srl     %r7,2
         stg     %r7,SP_R2(%r15)
-        brasl   %r14,syscall_trace
+        brasl   %r14,do_syscall_trace_enter
         lghi    %r0,NR_syscalls
-        clg     %r0,SP_R2(%r15)
+        clgr    %r0,%r2
         jnh     sysc_tracenogo
-        lg      %r7,SP_R2(%r15)         # strace might have changed the
-        sll     %r7,2                   # system call
+        slag    %r7,%r2,2               # *4
         lgf     %r8,0(%r7,%r10)
 sysc_tracego:
         lmg     %r3,%r6,SP_R3(%r15)
@@ -391,9 +400,8 @@ sysc_tracenogo:
         tm      __TI_flags+7(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)
         jz      sysc_return
         la      %r2,SP_PTREGS(%r15)     # load pt_regs
-        la      %r3,1
         larl    %r14,sysc_return        # return point is sysc_return
-        jg      syscall_trace
+        jg      do_syscall_trace_exit
 
 #
 # a new process exits the kernel with ret_from_fork
@@ -672,6 +680,8 @@ io_work_loop:
         jo      io_reschedule
         tm      __TI_flags+7(%r9),_TIF_SIGPENDING
         jnz     io_sigpending
+        tm      __TI_flags+7(%r9),_TIF_NOTIFY_RESUME
+        jnz     io_notify_resume
         j       io_restore
 io_work_done:
 
@@ -712,6 +722,18 @@ io_sigpending:
         TRACE_IRQS_OFF
         j       io_work_loop
 
+#
+# _TIF_NOTIFY_RESUME or is set, call do_notify_resume
+#
+io_notify_resume:
+        TRACE_IRQS_ON
+        stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
+        la      %r2,SP_PTREGS(%r15)     # load pt_regs
+        brasl   %r14,do_notify_resume   # call do_notify_resume
+        stnsm   __SF_EMPTY(%r15),0xfc   # disable I/O and ext. interrupts
+        TRACE_IRQS_OFF
+        j       io_work_loop
+
 /*
  * External interrupt handler routine
  */
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index c8b08289eb87..1f31be1ecc4b 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -35,6 +35,7 @@
 #include <linux/signal.h>
 #include <linux/elf.h>
 #include <linux/regset.h>
+#include <linux/tracehook.h>
 
 #include <asm/segment.h>
 #include <asm/page.h>
@@ -639,40 +640,44 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
 }
 #endif
 
-asmlinkage void
-syscall_trace(struct pt_regs *regs, int entryexit)
+asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
 {
-        if (unlikely(current->audit_context) && entryexit)
-                audit_syscall_exit(AUDITSC_RESULT(regs->gprs[2]), regs->gprs[2]);
-
-        if (!test_thread_flag(TIF_SYSCALL_TRACE))
-                goto out;
-        if (!(current->ptrace & PT_PTRACED))
-                goto out;
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-                                 ? 0x80 : 0));
+        long ret;
 
         /*
-         * If the debuffer has set an invalid system call number,
-         * we prepare to skip the system call restart handling.
+         * The sysc_tracesys code in entry.S stored the system
+         * call number to gprs[2].
          */
-        if (!entryexit && regs->gprs[2] >= NR_syscalls)
+        ret = regs->gprs[2];
+        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
+            (tracehook_report_syscall_entry(regs) ||
+             regs->gprs[2] >= NR_syscalls)) {
+                /*
+                 * Tracing decided this syscall should not happen or the
+                 * debugger stored an invalid system call number. Skip
+                 * the system call and the system call restart handling.
+                 */
                 regs->trap = -1;
-
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (current->exit_code) {
-                send_sig(current->exit_code, current, 1);
-                current->exit_code = 0;
+                ret = -1;
         }
- out:
-        if (unlikely(current->audit_context) && !entryexit)
-                audit_syscall_entry(test_thread_flag(TIF_31BIT)?AUDIT_ARCH_S390:AUDIT_ARCH_S390X,
-                                    regs->gprs[2], regs->orig_gpr2, regs->gprs[3],
-                                    regs->gprs[4], regs->gprs[5]);
+
+        if (unlikely(current->audit_context))
+                audit_syscall_entry(test_thread_flag(TIF_31BIT) ?
+                                        AUDIT_ARCH_S390 : AUDIT_ARCH_S390X,
+                                    regs->gprs[2], regs->orig_gpr2,
+                                    regs->gprs[3], regs->gprs[4],
+                                    regs->gprs[5]);
+        return ret;
+}
+
+asmlinkage void do_syscall_trace_exit(struct pt_regs *regs)
+{
+        if (unlikely(current->audit_context))
+                audit_syscall_exit(AUDITSC_RESULT(regs->gprs[2]),
+                                   regs->gprs[2]);
+
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(regs, 0);
 }
 
 /*
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index b97682040215..4f7fc3059a8e 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -24,6 +24,7 @@
 #include <linux/tty.h>
 #include <linux/personality.h>
 #include <linux/binfmts.h>
+#include <linux/tracehook.h>
 #include <asm/ucontext.h>
 #include <asm/uaccess.h>
 #include <asm/lowcore.h>
@@ -507,6 +508,12 @@ void do_signal(struct pt_regs *regs)
                          */
                         if (current->thread.per_info.single_step)
                                 set_thread_flag(TIF_SINGLE_STEP);
+
+                        /*
+                         * Let tracing know that we've done the handler setup.
+                         */
+                        tracehook_signal_handler(signr, &info, &ka, regs,
+                                         test_thread_flag(TIF_SINGLE_STEP));
                 }
                 return;
         }
@@ -526,3 +533,9 @@ void do_signal(struct pt_regs *regs)
                 set_thread_flag(TIF_RESTART_SVC);
         }
 }
+
+void do_notify_resume(struct pt_regs *regs)
+{
+        clear_thread_flag(TIF_NOTIFY_RESUME);
+        tracehook_notify_resume(regs);
+}
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 00b9b4dec5eb..9e8b1f9b8f4d 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -585,6 +585,8 @@ int __cpuinit start_secondary(void *cpuvoid)
         /* Enable pfault pseudo page faults on this cpu. */
         pfault_init();
 
+        /* call cpu notifiers */
+        notify_cpu_starting(smp_processor_id());
         /* Mark this cpu as online */
         spin_lock(&call_lock);
         cpu_set(smp_processor_id(), cpu_online_map);
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index c66d35e55142..3ae303914b42 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -37,7 +37,7 @@ SYSCALL(sys_stime,sys_ni_syscall,sys32_stime_wrapper)		/* 25 old stime syscall *
 SYSCALL(sys_ptrace,sys_ptrace,sys32_ptrace_wrapper)
 SYSCALL(sys_alarm,sys_alarm,sys32_alarm_wrapper)
 NI_SYSCALL                                                      /* old fstat syscall */
-SYSCALL(sys_pause,sys_pause,sys32_pause)
+SYSCALL(sys_pause,sys_pause,sys_pause)
 SYSCALL(sys_utime,sys_utime,compat_sys_utime_wrapper)           /* 30 */
 NI_SYSCALL                                                      /* old stty syscall */
 NI_SYSCALL                                                      /* old gtty syscall */
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index ca114fe46ffb..b94e9e3b694a 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -169,6 +169,8 @@ void init_cpu_timer(void)
 
 static void clock_comparator_interrupt(__u16 code)
 {
+        if (S390_lowcore.clock_comparator == -1ULL)
+                set_clock_comparator(S390_lowcore.clock_comparator);
 }
 
 static void etr_timing_alert(struct etr_irq_parm *);
@@ -1354,7 +1356,7 @@ static void __init stp_reset(void)
 
         stp_page = alloc_bootmem_pages(PAGE_SIZE);
         rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
-        if (rc == 1)
+        if (rc == 0)
                 set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
         else if (stp_online) {
                 printk(KERN_WARNING "Running on non STP capable machine.\n");
diff --git a/arch/s390/lib/delay.c b/arch/s390/lib/delay.c
index fc6ab6094df8..6ccb9fab055a 100644
--- a/arch/s390/lib/delay.c
+++ b/arch/s390/lib/delay.c
@@ -1,14 +1,9 @@
 /*
- *  arch/s390/lib/delay.c
  *    Precise Delay Loops for S390
  *
- *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
- *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
- *
- *  Derived from "arch/i386/lib/delay.c"
- *    Copyright (C) 1993 Linus Torvalds
- *    Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
+ *    Copyright IBM Corp. 1999,2008
+ *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
+ *               Heiko Carstens <heiko.carstens@de.ibm.com>,
  */
 
 #include <linux/sched.h>
@@ -29,30 +24,31 @@ void __delay(unsigned long loops)
         asm volatile("0: brct %0,0b" : : "d" ((loops/2) + 1));
 }
 
-/*
- * Waits for 'usecs' microseconds using the TOD clock comparator.
- */
-void __udelay(unsigned long usecs)
+static void __udelay_disabled(unsigned long usecs)
 {
-        u64 end, time, old_cc = 0;
-        unsigned long flags, cr0, mask, dummy;
-        int irq_context;
+        unsigned long mask, cr0, cr0_saved;
+        u64 clock_saved;
 
-        irq_context = in_interrupt();
-        if (!irq_context)
-                local_bh_disable();
-        local_irq_save(flags);
-        if (raw_irqs_disabled_flags(flags)) {
-                old_cc = local_tick_disable();
-                S390_lowcore.clock_comparator = -1ULL;
-                __ctl_store(cr0, 0, 0);
-                dummy = (cr0 & 0xffff00e0) | 0x00000800;
-                __ctl_load(dummy , 0, 0);
-                mask = psw_kernel_bits | PSW_MASK_WAIT | PSW_MASK_EXT;
-        } else
-                mask = psw_kernel_bits | PSW_MASK_WAIT |
-                        PSW_MASK_EXT | PSW_MASK_IO;
+        clock_saved = local_tick_disable();
+        set_clock_comparator(get_clock() + ((u64) usecs << 12));
+        __ctl_store(cr0_saved, 0, 0);
+        cr0 = (cr0_saved & 0xffff00e0) | 0x00000800;
+        __ctl_load(cr0 , 0, 0);
+        mask = psw_kernel_bits | PSW_MASK_WAIT | PSW_MASK_EXT;
+        trace_hardirqs_on();
+        __load_psw_mask(mask);
+        local_irq_disable();
+        __ctl_load(cr0_saved, 0, 0);
+        local_tick_enable(clock_saved);
+        set_clock_comparator(S390_lowcore.clock_comparator);
+}
+
+static void __udelay_enabled(unsigned long usecs)
+{
+        unsigned long mask;
+        u64 end, time;
 
+        mask = psw_kernel_bits | PSW_MASK_WAIT | PSW_MASK_EXT | PSW_MASK_IO;
         end = get_clock() + ((u64) usecs << 12);
         do {
                 time = end < S390_lowcore.clock_comparator ?
@@ -62,13 +58,50 @@ void __udelay(unsigned long usecs)
                 __load_psw_mask(mask);
                 local_irq_disable();
         } while (get_clock() < end);
+        set_clock_comparator(S390_lowcore.clock_comparator);
+}
 
-        if (raw_irqs_disabled_flags(flags)) {
-                __ctl_load(cr0, 0, 0);
-                local_tick_enable(old_cc);
+/*
+ * Waits for 'usecs' microseconds using the TOD clock comparator.
+ */
+void __udelay(unsigned long usecs)
+{
+        unsigned long flags;
+
+        preempt_disable();
+        local_irq_save(flags);
+        if (in_irq()) {
+                __udelay_disabled(usecs);
+                goto out;
         }
-        if (!irq_context)
+        if (in_softirq()) {
+                if (raw_irqs_disabled_flags(flags))
+                        __udelay_disabled(usecs);
+                else
+                        __udelay_enabled(usecs);
+                goto out;
+        }
+        if (raw_irqs_disabled_flags(flags)) {
+                local_bh_disable();
+                __udelay_disabled(usecs);
                 _local_bh_enable();
-        set_clock_comparator(S390_lowcore.clock_comparator);
+                goto out;
+        }
+        __udelay_enabled(usecs);
+out:
         local_irq_restore(flags);
+        preempt_enable();
+}
+
+/*
+ * Simple udelay variant. To be used on startup and reboot
+ * when the interrupt handler isn't working.
+ */
+void udelay_simple(unsigned long usecs)
+{
+        u64 end;
+
+        end = get_clock() + ((u64) usecs << 12);
+        while (get_clock() < end)
+                cpu_relax();
 }
diff --git a/arch/s390/mm/extmem.c b/arch/s390/mm/extmem.c
index f231f5ec74b6..580fc64cc735 100644
--- a/arch/s390/mm/extmem.c
+++ b/arch/s390/mm/extmem.c
@@ -43,20 +43,40 @@
 #define DCSS_FINDSEG    0x0c
 #define DCSS_LOADNOLY   0x10
 #define DCSS_SEGEXT     0x18
+#define DCSS_LOADSHRX   0x20
+#define DCSS_LOADNSRX   0x24
+#define DCSS_FINDSEGX   0x2c
+#define DCSS_SEGEXTX    0x38
 #define DCSS_FINDSEGA   0x0c
 
 struct qrange {
-        unsigned int  start; // 3byte start address, 1 byte type
-        unsigned int  end;   // 3byte end address, 1 byte reserved
+        unsigned long  start; /* last byte type */
+        unsigned long  end;   /* last byte reserved */
 };
 
 struct qout64 {
+        unsigned long segstart;
+        unsigned long segend;
+        int segcnt;
+        int segrcnt;
+        struct qrange range[6];
+};
+
+#ifdef CONFIG_64BIT
+struct qrange_old {
+        unsigned int start; /* last byte type */
+        unsigned int end;   /* last byte reserved */
+};
+
+/* output area format for the Diag x'64' old subcode x'18' */
+struct qout64_old {
         int segstart;
         int segend;
         int segcnt;
         int segrcnt;
-        struct qrange range[6];
+        struct qrange_old range[6];
 };
+#endif
 
 struct qin64 {
         char qopcode;
@@ -86,6 +106,55 @@ static DEFINE_MUTEX(dcss_lock);
 static LIST_HEAD(dcss_list);
 static char *segtype_string[] = { "SW", "EW", "SR", "ER", "SN", "EN", "SC",
                                         "EW/EN-MIXED" };
+static int loadshr_scode, loadnsr_scode, findseg_scode;
+static int segext_scode, purgeseg_scode;
+static int scode_set;
+
+/* set correct Diag x'64' subcodes. */
+static int
+dcss_set_subcodes(void)
+{
+#ifdef CONFIG_64BIT
+        char *name = kmalloc(8 * sizeof(char), GFP_DMA);
+        unsigned long rx, ry;
+        int rc;
+
+        if (name == NULL)
+                return -ENOMEM;
+
+        rx = (unsigned long) name;
+        ry = DCSS_FINDSEGX;
+
+        strcpy(name, "dummy");
+        asm volatile(
+                "       diag    %0,%1,0x64\n"
+                "0:     ipm     %2\n"
+                "       srl     %2,28\n"
+                "       j       2f\n"
+                "1:     la      %2,3\n"
+                "2:\n"
+                EX_TABLE(0b, 1b)
+                : "+d" (rx), "+d" (ry), "=d" (rc) : : "cc");
+
+        kfree(name);
+        /* Diag x'64' new subcodes are supported, set to new subcodes */
+        if (rc != 3) {
+                loadshr_scode = DCSS_LOADSHRX;
+                loadnsr_scode = DCSS_LOADNSRX;
+                purgeseg_scode = DCSS_PURGESEG;
+                findseg_scode = DCSS_FINDSEGX;
+                segext_scode = DCSS_SEGEXTX;
+                return 0;
+        }
+#endif
+        /* Diag x'64' new subcodes are not supported, set to old subcodes */
+        loadshr_scode = DCSS_LOADNOLY;
+        loadnsr_scode = DCSS_LOADNSR;
+        purgeseg_scode = DCSS_PURGESEG;
+        findseg_scode = DCSS_FINDSEG;
+        segext_scode = DCSS_SEGEXT;
+        return 0;
+}
 
 /*
  * Create the 8 bytes, ebcdic VM segment name from
@@ -135,25 +204,45 @@ segment_by_name (char *name)
  * Perform a function on a dcss segment.
  */
 static inline int
-dcss_diag (__u8 func, void *parameter,
+dcss_diag(int *func, void *parameter,
            unsigned long *ret1, unsigned long *ret2)
 {
         unsigned long rx, ry;
         int rc;
 
+        if (scode_set == 0) {
+                rc = dcss_set_subcodes();
+                if (rc < 0)
+                        return rc;
+                scode_set = 1;
+        }
         rx = (unsigned long) parameter;
-        ry = (unsigned long) func;
-        asm volatile(
+        ry = (unsigned long) *func;
+
 #ifdef CONFIG_64BIT
-                "       sam31\n"
-                "       diag    %0,%1,0x64\n"
-                "       sam64\n"
+        /* 64-bit Diag x'64' new subcode, keep in 64-bit addressing mode */
+        if (*func > DCSS_SEGEXT)
+                asm volatile(
+                        "       diag    %0,%1,0x64\n"
+                        "       ipm     %2\n"
+                        "       srl     %2,28\n"
+                        : "+d" (rx), "+d" (ry), "=d" (rc) : : "cc");
+        /* 31-bit Diag x'64' old subcode, switch to 31-bit addressing mode */
+        else
+                asm volatile(
+                        "       sam31\n"
+                        "       diag    %0,%1,0x64\n"
+                        "       sam64\n"
+                        "       ipm     %2\n"
+                        "       srl     %2,28\n"
+                        : "+d" (rx), "+d" (ry), "=d" (rc) : : "cc");
 #else
+        asm volatile(
                 "       diag    %0,%1,0x64\n"
-#endif
                 "       ipm     %2\n"
                 "       srl     %2,28\n"
                 : "+d" (rx), "+d" (ry), "=d" (rc) : : "cc");
+#endif
         *ret1 = rx;
         *ret2 = ry;
         return rc;
@@ -190,14 +279,45 @@ query_segment_type (struct dcss_segment *seg)
         qin->qoutlen = sizeof(struct qout64);
         memcpy (qin->qname, seg->dcss_name, 8);
 
-        diag_cc = dcss_diag (DCSS_SEGEXT, qin, &dummy, &vmrc);
+        diag_cc = dcss_diag(&segext_scode, qin, &dummy, &vmrc);
 
+        if (diag_cc < 0) {
+                rc = diag_cc;
+                goto out_free;
+        }
         if (diag_cc > 1) {
                 PRINT_WARN ("segment_type: diag returned error %ld\n", vmrc);
                 rc = dcss_diag_translate_rc (vmrc);
                 goto out_free;
         }
 
+#ifdef CONFIG_64BIT
+        /* Only old format of output area of Diagnose x'64' is supported,
+           copy data for the new format. */
+        if (segext_scode == DCSS_SEGEXT) {
+                struct qout64_old *qout_old;
+                qout_old = kzalloc(sizeof(struct qout64_old), GFP_DMA);
+                if (qout_old == NULL) {
+                        rc = -ENOMEM;
+                        goto out_free;
+                }
+                memcpy(qout_old, qout, sizeof(struct qout64_old));
+                qout->segstart = (unsigned long) qout_old->segstart;
+                qout->segend = (unsigned long) qout_old->segend;
+                qout->segcnt = qout_old->segcnt;
+                qout->segrcnt = qout_old->segrcnt;
+
+                if (qout->segcnt > 6)
+                        qout->segrcnt = 6;
+                for (i = 0; i < qout->segrcnt; i++) {
+                        qout->range[i].start =
+                                (unsigned long) qout_old->range[i].start;
+                        qout->range[i].end =
+                                (unsigned long) qout_old->range[i].end;
+                }
+                kfree(qout_old);
+        }
+#endif
         if (qout->segcnt > 6) {
                 rc = -ENOTSUPP;
                 goto out_free;
@@ -269,6 +389,30 @@ segment_type (char* name)
 }
 
 /*
+ * check if segment collides with other segments that are currently loaded
+ * returns 1 if this is the case, 0 if no collision was found
+ */
+static int
+segment_overlaps_others (struct dcss_segment *seg)
+{
+        struct list_head *l;
+        struct dcss_segment *tmp;
+
+        BUG_ON(!mutex_is_locked(&dcss_lock));
+        list_for_each(l, &dcss_list) {
+                tmp = list_entry(l, struct dcss_segment, list);
+                if ((tmp->start_addr >> 20) > (seg->end >> 20))
+                        continue;
+                if ((tmp->end >> 20) < (seg->start_addr >> 20))
+                        continue;
+                if (seg == tmp)
+                        continue;
+                return 1;
+        }
+        return 0;
+}
+
+/*
  * real segment loading function, called from segment_load
  */
 static int
@@ -276,7 +420,8 @@ __segment_load (char *name, int do_nonshared, unsigned long *addr, unsigned long
 {
         struct dcss_segment *seg = kmalloc(sizeof(struct dcss_segment),
                         GFP_DMA);
-        int dcss_command, rc, diag_cc;
+        int rc, diag_cc;
+        unsigned long start_addr, end_addr, dummy;
 
         if (seg == NULL) {
                 rc = -ENOMEM;
@@ -287,6 +432,13 @@ __segment_load (char *name, int do_nonshared, unsigned long *addr, unsigned long
         if (rc < 0)
                 goto out_free;
 
+        if (loadshr_scode == DCSS_LOADSHRX) {
+                if (segment_overlaps_others(seg)) {
+                        rc = -EBUSY;
+                        goto out_free;
+                }
+        }
+
         rc = vmem_add_mapping(seg->start_addr, seg->end - seg->start_addr + 1);
 
         if (rc)
@@ -316,20 +468,28 @@ __segment_load (char *name, int do_nonshared, unsigned long *addr, unsigned long
         }
 
         if (do_nonshared)
-                dcss_command = DCSS_LOADNSR;
+                diag_cc = dcss_diag(&loadnsr_scode, seg->dcss_name,
+                                &start_addr, &end_addr);
         else
-                dcss_command = DCSS_LOADNOLY;
-
-        diag_cc = dcss_diag(dcss_command, seg->dcss_name,
-                        &seg->start_addr, &seg->end);
+                diag_cc = dcss_diag(&loadshr_scode, seg->dcss_name,
+                                &start_addr, &end_addr);
+        if (diag_cc < 0) {
+                dcss_diag(&purgeseg_scode, seg->dcss_name,
+                                &dummy, &dummy);
+                rc = diag_cc;
+                goto out_resource;
+        }
         if (diag_cc > 1) {
                 PRINT_WARN ("segment_load: could not load segment %s - "
-                                "diag returned error (%ld)\n",name,seg->end);
-                rc = dcss_diag_translate_rc (seg->end);
-                dcss_diag(DCSS_PURGESEG, seg->dcss_name,
-                                &seg->start_addr, &seg->end);
+                                "diag returned error (%ld)\n",
+                                name, end_addr);
+                rc = dcss_diag_translate_rc(end_addr);
+                dcss_diag(&purgeseg_scode, seg->dcss_name,
+                                &dummy, &dummy);
                 goto out_resource;
         }
+        seg->start_addr = start_addr;
+        seg->end = end_addr;
         seg->do_nonshared = do_nonshared;
         atomic_set(&seg->ref_count, 1);
         list_add(&seg->list, &dcss_list);
@@ -423,8 +583,8 @@ int
 segment_modify_shared (char *name, int do_nonshared)
 {
         struct dcss_segment *seg;
-        unsigned long dummy;
-        int dcss_command, rc, diag_cc;
+        unsigned long start_addr, end_addr, dummy;
+        int rc, diag_cc;
 
         mutex_lock(&dcss_lock);
         seg = segment_by_name (name);
@@ -445,38 +605,51 @@ segment_modify_shared (char *name, int do_nonshared)
                 goto out_unlock;
         }
         release_resource(seg->res);
-        if (do_nonshared) {
-                dcss_command = DCSS_LOADNSR;
+        if (do_nonshared)
                 seg->res->flags &= ~IORESOURCE_READONLY;
-        } else {
-                dcss_command = DCSS_LOADNOLY;
+        else
                 if (seg->vm_segtype == SEG_TYPE_SR ||
                     seg->vm_segtype == SEG_TYPE_ER)
                         seg->res->flags |= IORESOURCE_READONLY;
-        }
+
         if (request_resource(&iomem_resource, seg->res)) {
                 PRINT_WARN("segment_modify_shared: could not reload segment %s"
                            " - overlapping resources\n", name);
                 rc = -EBUSY;
                 kfree(seg->res);
-                goto out_del;
+                goto out_del_mem;
+        }
+
+        dcss_diag(&purgeseg_scode, seg->dcss_name, &dummy, &dummy);
+        if (do_nonshared)
+                diag_cc = dcss_diag(&loadnsr_scode, seg->dcss_name,
+                                &start_addr, &end_addr);
+        else
+                diag_cc = dcss_diag(&loadshr_scode, seg->dcss_name,
+                                &start_addr, &end_addr);
+        if (diag_cc < 0) {
+                rc = diag_cc;
+                goto out_del_res;
         }
-        dcss_diag(DCSS_PURGESEG, seg->dcss_name, &dummy, &dummy);
-        diag_cc = dcss_diag(dcss_command, seg->dcss_name,
-                        &seg->start_addr, &seg->end);
         if (diag_cc > 1) {
                 PRINT_WARN ("segment_modify_shared: could not reload segment %s"
-                                " - diag returned error (%ld)\n",name,seg->end);
-                rc = dcss_diag_translate_rc (seg->end);
-                goto out_del;
+                                " - diag returned error (%ld)\n",
+                                name, end_addr);
+                rc = dcss_diag_translate_rc(end_addr);
+                goto out_del_res;
         }
+        seg->start_addr = start_addr;
+        seg->end = end_addr;
         seg->do_nonshared = do_nonshared;
         rc = 0;
         goto out_unlock;
- out_del:
+ out_del_res:
+        release_resource(seg->res);
+        kfree(seg->res);
+ out_del_mem:
         vmem_remove_mapping(seg->start_addr, seg->end - seg->start_addr + 1);
         list_del(&seg->list);
-        dcss_diag(DCSS_PURGESEG, seg->dcss_name, &dummy, &dummy);
+        dcss_diag(&purgeseg_scode, seg->dcss_name, &dummy, &dummy);
         kfree(seg);
  out_unlock:
         mutex_unlock(&dcss_lock);
@@ -510,7 +683,7 @@ segment_unload(char *name)
         kfree(seg->res);
         vmem_remove_mapping(seg->start_addr, seg->end - seg->start_addr + 1);
         list_del(&seg->list);
-        dcss_diag(DCSS_PURGESEG, seg->dcss_name, &dummy, &dummy);
+        dcss_diag(&purgeseg_scode, seg->dcss_name, &dummy, &dummy);
         kfree(seg);
 out_unlock:
         mutex_unlock(&dcss_lock);
@@ -545,7 +718,7 @@ segment_save(char *name)
         endpfn = (seg->end) >> PAGE_SHIFT;
         sprintf(cmd1, "DEFSEG %s", name);
         for (i=0; i<seg->segcnt; i++) {
-                sprintf(cmd1+strlen(cmd1), " %X-%X %s",
+                sprintf(cmd1+strlen(cmd1), " %lX-%lX %s",
                         seg->range[i].start >> PAGE_SHIFT,
                         seg->range[i].end >> PAGE_SHIFT,
                         segtype_string[seg->range[i].start & 0xff]);
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index 60c50841143e..001778f9adaf 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -82,6 +82,8 @@ asmlinkage void __cpuinit start_secondary(void)
 
         preempt_disable();
 
+        notify_cpu_starting(smp_processor_id());
+
         local_irq_enable();
 
         calibrate_delay();
diff --git a/arch/sparc/kernel/of_device.c b/arch/sparc/kernel/of_device.c
index c481d45f97b7..f58c537446a8 100644
--- a/arch/sparc/kernel/of_device.c
+++ b/arch/sparc/kernel/of_device.c
@@ -241,7 +241,7 @@ static int of_bus_sbus_map(u32 *addr, const u32 *range, int na, int ns, int pna)
         return of_bus_default_map(addr, range, na, ns, pna);
 }
 
-static unsigned int of_bus_sbus_get_flags(const u32 *addr)
+static unsigned long of_bus_sbus_get_flags(const u32 *addr, unsigned long flags)
 {
         return IORESOURCE_MEM;
 }
diff --git a/arch/sparc/kernel/ptrace.c b/arch/sparc/kernel/ptrace.c
index 20699c701412..8ce6285a06d5 100644
--- a/arch/sparc/kernel/ptrace.c
+++ b/arch/sparc/kernel/ptrace.c
@@ -288,7 +288,7 @@ static const struct user_regset sparc32_regsets[] = {
          */
         [REGSET_GENERAL] = {
                 .core_note_type = NT_PRSTATUS,
-                .n = 38 * sizeof(u32),
+                .n = 38,
                 .size = sizeof(u32), .align = sizeof(u32),
                 .get = genregs32_get, .set = genregs32_set
         },
@@ -304,7 +304,7 @@ static const struct user_regset sparc32_regsets[] = {
          */
         [REGSET_FP] = {
                 .core_note_type = NT_PRFPREG,
-                .n = 99 * sizeof(u32),
+                .n = 99,
                 .size = sizeof(u32), .align = sizeof(u32),
                 .get = fpregs32_get, .set = fpregs32_set
         },
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
index 69596402a500..446767e8f569 100644
--- a/arch/sparc/kernel/sun4d_smp.c
+++ b/arch/sparc/kernel/sun4d_smp.c
@@ -88,6 +88,7 @@ void __init smp4d_callin(void)
         local_flush_cache_all();
         local_flush_tlb_all();
 
+        notify_cpu_starting(cpuid);
         /*
          * Unblock the master CPU _only_ when the scheduler state
          * of all secondary CPUs will be up-to-date, so after
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
index a14a76ac7f36..9964890dc1db 100644
--- a/arch/sparc/kernel/sun4m_smp.c
+++ b/arch/sparc/kernel/sun4m_smp.c
@@ -71,6 +71,8 @@ void __cpuinit smp4m_callin(void)
         local_flush_cache_all();
         local_flush_tlb_all();
 
+        notify_cpu_starting(cpuid);
+
         /* Get our local ticker going. */
         smp_setup_percpu_timer();
 
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index 23963882bc18..7495bc774685 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -7,6 +7,7 @@
 
 #include <linux/module.h>
 #include <linux/sched.h>
+#include <linux/linkage.h>
 #include <linux/ptrace.h>
 #include <linux/errno.h>
 #include <linux/kernel_stat.h>
@@ -866,7 +867,7 @@ static void kill_prom_timer(void)
         : "g1", "g2");
 }
 
-void init_irqwork_curcpu(void)
+void notrace init_irqwork_curcpu(void)
 {
         int cpu = hard_smp_processor_id();
 
@@ -897,7 +898,7 @@ static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type
         }
 }
 
-void __cpuinit sun4v_register_mondo_queues(int this_cpu)
+void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
 {
         struct trap_per_cpu *tb = &trap_block[this_cpu];
 
diff --git a/arch/sparc64/kernel/of_device.c b/arch/sparc64/kernel/of_device.c
index f845f150f565..100ebd527499 100644
--- a/arch/sparc64/kernel/of_device.c
+++ b/arch/sparc64/kernel/of_device.c
@@ -169,7 +169,7 @@ static unsigned long of_bus_default_get_flags(const u32 *addr, unsigned long fla
 
 static int of_bus_pci_match(struct device_node *np)
 {
-        if (!strcmp(np->type, "pci") || !strcmp(np->type, "pciex")) {
+        if (!strcmp(np->name, "pci")) {
                 const char *model = of_get_property(np, "model", NULL);
 
                 if (model && !strcmp(model, "SUNW,simba"))
@@ -200,7 +200,7 @@ static int of_bus_simba_match(struct device_node *np)
         /* Treat PCI busses lacking ranges property just like
          * simba.
          */
-        if (!strcmp(np->type, "pci") || !strcmp(np->type, "pciex")) {
+        if (!strcmp(np->name, "pci")) {
                 if (!of_find_property(np, "ranges", NULL))
                         return 1;
         }
@@ -429,7 +429,7 @@ static int __init use_1to1_mapping(struct device_node *pp)
          * it lacks a ranges property, and this will include
          * cases like Simba.
          */
-        if (!strcmp(pp->type, "pci") || !strcmp(pp->type, "pciex"))
+        if (!strcmp(pp->name, "pci"))
                 return 0;
 
         return 1;
@@ -714,8 +714,7 @@ static unsigned int __init build_one_device_irq(struct of_device *op,
                                 break;
                         }
                 } else {
-                        if (!strcmp(pp->type, "pci") ||
-                            !strcmp(pp->type, "pciex")) {
+                        if (!strcmp(pp->name, "pci")) {
                                 unsigned int this_orig_irq = irq;
 
                                 irq = pci_irq_swizzle(dp, pp, irq);
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index 55096195458f..80dad76f8b81 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -425,7 +425,7 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
         dev->current_state = 4;         /* unknown power state */
         dev->error_state = pci_channel_io_normal;
 
-        if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
+        if (!strcmp(node->name, "pci")) {
                 /* a PCI-PCI bridge */
                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index ef5fe29202c2..f85b6bebb0be 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -575,7 +575,7 @@ static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm
 {
         unsigned long csr_reg, csr, csr_error_bits;
         irqreturn_t ret = IRQ_NONE;
-        u16 stat;
+        u16 stat, *addr;
 
         if (is_pbm_a) {
                 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
@@ -597,7 +597,9 @@ static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm
                         printk("%s: PCI SERR signal asserted.\n", pbm->name);
                 ret = IRQ_HANDLED;
         }
-        pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
+        addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
+                                        0, PCI_STATUS);
+        pci_config_read16(addr, &stat);
         if (stat & (PCI_STATUS_PARITY |
                     PCI_STATUS_SIG_TARGET_ABORT |
                     PCI_STATUS_REC_TARGET_ABORT |
@@ -605,7 +607,7 @@ static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm
                     PCI_STATUS_SIG_SYSTEM_ERROR)) {
                 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
                        pbm->name, stat);
-                pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
+                pci_config_write16(addr, 0xffff);
                 ret = IRQ_HANDLED;
         }
         return ret;
@@ -744,16 +746,16 @@ static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
          * the second will just error out since we do not pass in
          * IRQF_SHARED.
          */
-        err = request_irq(op->irqs[1], psycho_ue_intr, 0,
+        err = request_irq(op->irqs[1], psycho_ue_intr, IRQF_SHARED,
                           "PSYCHO_UE", pbm);
-        err = request_irq(op->irqs[2], psycho_ce_intr, 0,
+        err = request_irq(op->irqs[2], psycho_ce_intr, IRQF_SHARED,
                           "PSYCHO_CE", pbm);
 
         /* This one, however, ought not to fail.  We can just warn
          * about it since the system can still operate properly even
          * if this fails.
          */
-        err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
+        err = request_irq(op->irqs[0], psycho_pcierr_intr, IRQF_SHARED,
                           "PSYCHO_PCIERR", pbm);
         if (err)
                 printk(KERN_WARNING "%s: Could not register PCIERR, "
diff --git a/arch/sparc64/kernel/prom.c b/arch/sparc64/kernel/prom.c
index 3c048ac4e638..7151513f156e 100644
--- a/arch/sparc64/kernel/prom.c
+++ b/arch/sparc64/kernel/prom.c
@@ -156,55 +156,11 @@ static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
                 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
 }
 
-#define PSYCHO_IMAP_SCSI        0x1000UL
-#define PSYCHO_IMAP_ETH         0x1008UL
-#define PSYCHO_IMAP_BPP         0x1010UL
-#define PSYCHO_IMAP_AU_REC      0x1018UL
-#define PSYCHO_IMAP_AU_PLAY     0x1020UL
-#define PSYCHO_IMAP_PFAIL       0x1028UL
-#define PSYCHO_IMAP_KMS         0x1030UL
-#define PSYCHO_IMAP_FLPY        0x1038UL
-#define PSYCHO_IMAP_SHW         0x1040UL
-#define PSYCHO_IMAP_KBD         0x1048UL
-#define PSYCHO_IMAP_MS          0x1050UL
-#define PSYCHO_IMAP_SER         0x1058UL
-#define PSYCHO_IMAP_TIM0        0x1060UL
-#define PSYCHO_IMAP_TIM1        0x1068UL
-#define PSYCHO_IMAP_UE          0x1070UL
-#define PSYCHO_IMAP_CE          0x1078UL
-#define PSYCHO_IMAP_A_ERR       0x1080UL
-#define PSYCHO_IMAP_B_ERR       0x1088UL
-#define PSYCHO_IMAP_PMGMT       0x1090UL
-#define PSYCHO_IMAP_GFX         0x1098UL
-#define PSYCHO_IMAP_EUPA        0x10a0UL
-
-static unsigned long __psycho_onboard_imap_off[] = {
-/*0x20*/        PSYCHO_IMAP_SCSI,
-/*0x21*/        PSYCHO_IMAP_ETH,
-/*0x22*/        PSYCHO_IMAP_BPP,
-/*0x23*/        PSYCHO_IMAP_AU_REC,
-/*0x24*/        PSYCHO_IMAP_AU_PLAY,
-/*0x25*/        PSYCHO_IMAP_PFAIL,
-/*0x26*/        PSYCHO_IMAP_KMS,
-/*0x27*/        PSYCHO_IMAP_FLPY,
-/*0x28*/        PSYCHO_IMAP_SHW,
-/*0x29*/        PSYCHO_IMAP_KBD,
-/*0x2a*/        PSYCHO_IMAP_MS,
-/*0x2b*/        PSYCHO_IMAP_SER,
-/*0x2c*/        PSYCHO_IMAP_TIM0,
-/*0x2d*/        PSYCHO_IMAP_TIM1,
-/*0x2e*/        PSYCHO_IMAP_UE,
-/*0x2f*/        PSYCHO_IMAP_CE,
-/*0x30*/        PSYCHO_IMAP_A_ERR,
-/*0x31*/        PSYCHO_IMAP_B_ERR,
-/*0x32*/        PSYCHO_IMAP_PMGMT,
-/*0x33*/        PSYCHO_IMAP_GFX,
-/*0x34*/        PSYCHO_IMAP_EUPA,
-};
+#define PSYCHO_OBIO_IMAP_BASE   0x1000UL
+
 #define PSYCHO_ONBOARD_IRQ_BASE         0x20
-#define PSYCHO_ONBOARD_IRQ_LAST         0x34
 #define psycho_onboard_imap_offset(__ino) \
-        __psycho_onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
+        (PSYCHO_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
 
 #define PSYCHO_ICLR_A_SLOT0     0x1400UL
 #define PSYCHO_ICLR_SCSI        0x1800UL
@@ -228,10 +184,6 @@ static unsigned int psycho_irq_build(struct device_node *dp,
                 imap_off = psycho_pcislot_imap_offset(ino);
         } else {
                 /* Onboard device */
-                if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
-                        prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
-                        prom_halt();
-                }
                 imap_off = psycho_onboard_imap_offset(ino);
         }
 
@@ -318,23 +270,6 @@ static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
 
 #define SABRE_IMAP_A_SLOT0      0x0c00UL
 #define SABRE_IMAP_B_SLOT0      0x0c20UL
-#define SABRE_IMAP_SCSI         0x1000UL
-#define SABRE_IMAP_ETH          0x1008UL
-#define SABRE_IMAP_BPP          0x1010UL
-#define SABRE_IMAP_AU_REC       0x1018UL
-#define SABRE_IMAP_AU_PLAY      0x1020UL
-#define SABRE_IMAP_PFAIL        0x1028UL
-#define SABRE_IMAP_KMS          0x1030UL
-#define SABRE_IMAP_FLPY         0x1038UL
-#define SABRE_IMAP_SHW          0x1040UL
-#define SABRE_IMAP_KBD          0x1048UL
-#define SABRE_IMAP_MS           0x1050UL
-#define SABRE_IMAP_SER          0x1058UL
-#define SABRE_IMAP_UE           0x1070UL
-#define SABRE_IMAP_CE           0x1078UL
-#define SABRE_IMAP_PCIERR       0x1080UL
-#define SABRE_IMAP_GFX          0x1098UL
-#define SABRE_IMAP_EUPA         0x10a0UL
 #define SABRE_ICLR_A_SLOT0      0x1400UL
 #define SABRE_ICLR_B_SLOT0      0x1480UL
 #define SABRE_ICLR_SCSI         0x1800UL
@@ -364,33 +299,10 @@ static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
                 return SABRE_IMAP_B_SLOT0 + (slot * 8);
 }
 
-static unsigned long __sabre_onboard_imap_off[] = {
-/*0x20*/        SABRE_IMAP_SCSI,
-/*0x21*/        SABRE_IMAP_ETH,
-/*0x22*/        SABRE_IMAP_BPP,
-/*0x23*/        SABRE_IMAP_AU_REC,
-/*0x24*/        SABRE_IMAP_AU_PLAY,
-/*0x25*/        SABRE_IMAP_PFAIL,
-/*0x26*/        SABRE_IMAP_KMS,
-/*0x27*/        SABRE_IMAP_FLPY,
-/*0x28*/        SABRE_IMAP_SHW,
-/*0x29*/        SABRE_IMAP_KBD,
-/*0x2a*/        SABRE_IMAP_MS,
-/*0x2b*/        SABRE_IMAP_SER,
-/*0x2c*/        0 /* reserved */,
-/*0x2d*/        0 /* reserved */,
-/*0x2e*/        SABRE_IMAP_UE,
-/*0x2f*/        SABRE_IMAP_CE,
-/*0x30*/        SABRE_IMAP_PCIERR,
-/*0x31*/        0 /* reserved */,
-/*0x32*/        0 /* reserved */,
-/*0x33*/        SABRE_IMAP_GFX,
-/*0x34*/        SABRE_IMAP_EUPA,
-};
-#define SABRE_ONBOARD_IRQ_BASE          0x20
-#define SABRE_ONBOARD_IRQ_LAST          0x30
+#define SABRE_OBIO_IMAP_BASE    0x1000UL
+#define SABRE_ONBOARD_IRQ_BASE  0x20
 #define sabre_onboard_imap_offset(__ino) \
-        __sabre_onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
+        (SABRE_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
 
 #define sabre_iclr_offset(ino)                                        \
         ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) :  \
@@ -453,10 +365,6 @@ static unsigned int sabre_irq_build(struct device_node *dp,
                 imap_off = sabre_pcislot_imap_offset(ino);
         } else {
                 /* onboard device */
-                if (ino > SABRE_ONBOARD_IRQ_LAST) {
-                        prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
-                        prom_halt();
-                }
                 imap_off = sabre_onboard_imap_offset(ino);
         }
 
diff --git a/arch/sparc64/kernel/ptrace.c b/arch/sparc64/kernel/ptrace.c
index bd578cc4856d..10306e476e38 100644
--- a/arch/sparc64/kernel/ptrace.c
+++ b/arch/sparc64/kernel/ptrace.c
@@ -443,7 +443,7 @@ static const struct user_regset sparc64_regsets[] = {
          */
         [REGSET_GENERAL] = {
                 .core_note_type = NT_PRSTATUS,
-                .n = 36 * sizeof(u64),
+                .n = 36,
                 .size = sizeof(u64), .align = sizeof(u64),
                 .get = genregs64_get, .set = genregs64_set
         },
@@ -455,7 +455,7 @@ static const struct user_regset sparc64_regsets[] = {
          */
         [REGSET_FP] = {
                 .core_note_type = NT_PRFPREG,
-                .n = 35 * sizeof(u64),
+                .n = 35,
                 .size = sizeof(u64), .align = sizeof(u64),
                 .get = fpregs64_get, .set = fpregs64_set
         },
@@ -801,7 +801,7 @@ static const struct user_regset sparc32_regsets[] = {
          */
         [REGSET_GENERAL] = {
                 .core_note_type = NT_PRSTATUS,
-                .n = 38 * sizeof(u32),
+                .n = 38,
                 .size = sizeof(u32), .align = sizeof(u32),
                 .get = genregs32_get, .set = genregs32_set
         },
@@ -817,7 +817,7 @@ static const struct user_regset sparc32_regsets[] = {
          */
         [REGSET_FP] = {
                 .core_note_type = NT_PRFPREG,
-                .n = 99 * sizeof(u32),
+                .n = 99,
                 .size = sizeof(u32), .align = sizeof(u32),
                 .get = fpregs32_get, .set = fpregs32_set
         },
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index 3d924121c796..c824df13f589 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -10,6 +10,7 @@
 
 #include <linux/module.h>
 #include <linux/sched.h>
+#include <linux/linkage.h>
 #include <linux/kernel.h>
 #include <linux/signal.h>
 #include <linux/smp.h>
@@ -2453,7 +2454,7 @@ struct trap_per_cpu trap_block[NR_CPUS];
 /* This can get invoked before sched_init() so play it super safe
  * and use hard_smp_processor_id().
  */
-void init_cur_cpu_trap(struct thread_info *t)
+void notrace init_cur_cpu_trap(struct thread_info *t)
 {
         int cpu = hard_smp_processor_id();
         struct trap_per_cpu *p = &trap_block[cpu];
diff --git a/arch/um/Kconfig.char b/arch/um/Kconfig.char
index 1b238ebae6b3..70dabd1e0652 100644
--- a/arch/um/Kconfig.char
+++ b/arch/um/Kconfig.char
@@ -203,6 +203,10 @@ config SOUND
         tristate
         default UML_SOUND
 
+config SOUND_OSS_CORE
+        bool
+        default UML_SOUND
+
 config HOSTAUDIO
         tristate
         default UML_SOUND
diff --git a/arch/um/kernel/smp.c b/arch/um/kernel/smp.c
index be2d50c3aa95..045772142844 100644
--- a/arch/um/kernel/smp.c
+++ b/arch/um/kernel/smp.c
@@ -85,6 +85,7 @@ static int idle_proc(void *cpup)
         while (!cpu_isset(cpu, smp_commenced_mask))
                 cpu_relax();
 
+        notify_cpu_starting(cpu);
         cpu_set(cpu, cpu_online_map);
         default_idle();
         return 0;
diff --git a/arch/um/sys-x86_64/syscall_table.c b/arch/um/sys-x86_64/syscall_table.c
index c128eb897008..32f5fbe2d0d2 100644
--- a/arch/um/sys-x86_64/syscall_table.c
+++ b/arch/um/sys-x86_64/syscall_table.c
@@ -41,12 +41,12 @@
 #define stub_rt_sigreturn sys_rt_sigreturn
 
 #define __SYSCALL(nr, sym) extern asmlinkage void sym(void) ;
-#undef _ASM_X86_64_UNISTD_H_
+#undef ASM_X86__UNISTD_64_H
 #include <asm-x86/unistd_64.h>
 
 #undef __SYSCALL
 #define __SYSCALL(nr, sym) [ nr ] = sym,
-#undef _ASM_X86_64_UNISTD_H_
+#undef ASM_X86__UNISTD_64_H
 
 typedef void (*sys_call_ptr_t)(void);
 
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 633f25dd9ee2..25e2f7a20d66 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -29,6 +29,7 @@ config X86
         select HAVE_FTRACE
         select HAVE_KVM if ((X86_32 && !X86_VOYAGER && !X86_VISWS && !X86_NUMAQ) || X86_64)
         select HAVE_ARCH_KGDB if !X86_VOYAGER
+        select HAVE_ARCH_TRACEHOOK
         select HAVE_GENERIC_DMA_COHERENT if X86_32
         select HAVE_EFFICIENT_UNALIGNED_ACCESS
 
@@ -553,6 +554,7 @@ config CALGARY_IOMMU_ENABLED_BY_DEFAULT
 config AMD_IOMMU
         bool "AMD IOMMU support"
         select SWIOTLB
+        select PCI_MSI
         depends on X86_64 && PCI && ACPI
         help
           With this option you can enable support for AMD IOMMU hardware in
@@ -1020,7 +1022,7 @@ config HAVE_ARCH_ALLOC_REMAP
 
 config ARCH_FLATMEM_ENABLE
         def_bool y
-        depends on X86_32 && ARCH_SELECT_MEMORY_MODEL && X86_PC && !NUMA
+        depends on X86_32 && ARCH_SELECT_MEMORY_MODEL && !NUMA
 
 config ARCH_DISCONTIGMEM_ENABLE
         def_bool y
@@ -1036,7 +1038,7 @@ config ARCH_SPARSEMEM_DEFAULT
 
 config ARCH_SPARSEMEM_ENABLE
         def_bool y
-        depends on X86_64 || NUMA || (EXPERIMENTAL && X86_PC)
+        depends on X86_64 || NUMA || (EXPERIMENTAL && X86_PC) || X86_GENERICARCH
         select SPARSEMEM_STATIC if X86_32
         select SPARSEMEM_VMEMMAP_ENABLE if X86_64
 
@@ -1167,10 +1169,10 @@ config MTRR
           You can safely say Y even if your machine doesn't have MTRRs, you'll
           just add about 9 KB to your kernel.
 
-          See <file:Documentation/mtrr.txt> for more information.
+          See <file:Documentation/x86/mtrr.txt> for more information.
 
 config MTRR_SANITIZER
-        bool
+        def_bool y
         prompt "MTRR cleanup support"
         depends on MTRR
         help
@@ -1181,7 +1183,7 @@ config MTRR_SANITIZER
           The largest mtrr entry size for a continous block can be set with
           mtrr_chunk_size.
 
-          If unsure, say N.
+          If unsure, say Y.
 
 config MTRR_SANITIZER_ENABLE_DEFAULT
         int "MTRR cleanup enable value (0-1)"
@@ -1241,7 +1243,6 @@ config IRQBALANCE
 config SECCOMP
         def_bool y
         prompt "Enable seccomp to safely compute untrusted bytecode"
-        depends on PROC_FS
         help
           This kernel feature is useful for number crunching applications
           that may need to compute untrusted bytecode during their
@@ -1249,7 +1250,7 @@ config SECCOMP
           the process as file descriptors supporting the read/write
           syscalls, it's possible to isolate those applications in
           their own address space using seccomp. Once seccomp is
-          enabled via /proc/<pid>/seccomp, it cannot be disabled
+          enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
           and the task is only allowed to execute a few safe syscalls
           defined by each seccomp mode.
 
@@ -1406,14 +1407,14 @@ config PHYSICAL_ALIGN
           Don't change this unless you know what you are doing.
 
 config HOTPLUG_CPU
-        bool "Support for suspend on SMP and hot-pluggable CPUs (EXPERIMENTAL)"
-        depends on SMP && HOTPLUG && EXPERIMENTAL && !X86_VOYAGER
+        bool "Support for hot-pluggable CPUs"
+        depends on SMP && HOTPLUG && !X86_VOYAGER
         ---help---
-          Say Y here to experiment with turning CPUs off and on, and to
-          enable suspend on SMP systems. CPUs can be controlled through
-          /sys/devices/system/cpu.
-          Say N if you want to disable CPU hotplug and don't need to
-          suspend.
+          Say Y here to allow turning CPUs off and on. CPUs can be
+          controlled through /sys/devices/system/cpu.
+          ( Note: power management support will enable this option
+            automatically on SMP systems. )
+          Say N if you want to disable CPU hotplug.
 
 config COMPAT_VDSO
         def_bool y
@@ -1428,6 +1429,51 @@ config COMPAT_VDSO
 
           If unsure, say Y.
 
+config CMDLINE_BOOL
+        bool "Built-in kernel command line"
+        default n
+        help
+          Allow for specifying boot arguments to the kernel at
+          build time.  On some systems (e.g. embedded ones), it is
+          necessary or convenient to provide some or all of the
+          kernel boot arguments with the kernel itself (that is,
+          to not rely on the boot loader to provide them.)
+
+          To compile command line arguments into the kernel,
+          set this option to 'Y', then fill in the
+          the boot arguments in CONFIG_CMDLINE.
+
+          Systems with fully functional boot loaders (i.e. non-embedded)
+          should leave this option set to 'N'.
+
+config CMDLINE
+        string "Built-in kernel command string"
+        depends on CMDLINE_BOOL
+        default ""
+        help
+          Enter arguments here that should be compiled into the kernel
+          image and used at boot time.  If the boot loader provides a
+          command line at boot time, it is appended to this string to
+          form the full kernel command line, when the system boots.
+
+          However, you can use the CONFIG_CMDLINE_OVERRIDE option to
+          change this behavior.
+
+          In most cases, the command line (whether built-in or provided
+          by the boot loader) should specify the device for the root
+          file system.
+
+config CMDLINE_OVERRIDE
+        bool "Built-in command line overrides boot loader arguments"
+        default n
+        depends on CMDLINE_BOOL
+        help
+          Set this option to 'Y' to have the kernel ignore the boot loader
+          command line, and use ONLY the built-in command line.
+
+          This is used to work around broken boot loaders.  This should
+          be set to 'N' under normal conditions.
+
 endmenu
 
 config ARCH_ENABLE_MEMORY_HOTPLUG
@@ -1693,6 +1739,14 @@ config DMAR_FLOPPY_WA
          workaround will setup a 1:1 mapping for the first
          16M to make floppy (an ISA device) work.
 
+config INTR_REMAP
+        bool "Support for Interrupt Remapping (EXPERIMENTAL)"
+        depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI && EXPERIMENTAL
+        help
+         Supports Interrupt remapping for IO-APIC and MSI devices.
+         To use x2apic mode in the CPU's which support x2APIC enhancements or
+         to support platforms with CPU's having > 8 bit APIC ID, say Y.
+
 source "drivers/pci/pcie/Kconfig"
 
 source "drivers/pci/Kconfig"
@@ -1823,7 +1877,7 @@ config COMPAT_FOR_U64_ALIGNMENT
 
 config SYSVIPC_COMPAT
         def_bool y
-        depends on X86_64 && COMPAT && SYSVIPC
+        depends on COMPAT && SYSVIPC
 
 endmenu
 
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index b225219c448c..f8843c3ae77d 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -418,3 +418,75 @@ config X86_MINIMUM_CPU_FAMILY
 config X86_DEBUGCTLMSR
         def_bool y
         depends on !(MK6 || MWINCHIPC6 || MWINCHIP2 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386)
+
+menuconfig PROCESSOR_SELECT
+        default y
+        bool "Supported processor vendors" if EMBEDDED
+        help
+          This lets you choose what x86 vendor support code your kernel
+          will include.
+
+config CPU_SUP_INTEL
+        default y
+        bool "Support Intel processors" if PROCESSOR_SELECT
+        help
+          This enables extended support for Intel processors
+
+config CPU_SUP_CYRIX_32
+        default y
+        bool "Support Cyrix processors" if PROCESSOR_SELECT
+        depends on !64BIT
+        help
+          This enables extended support for Cyrix processors
+
+config CPU_SUP_AMD
+        default y
+        bool "Support AMD processors" if PROCESSOR_SELECT
+        help
+          This enables extended support for AMD processors
+
+config CPU_SUP_CENTAUR_32
+        default y
+        bool "Support Centaur processors" if PROCESSOR_SELECT
+        depends on !64BIT
+        help
+          This enables extended support for Centaur processors
+
+config CPU_SUP_CENTAUR_64
+        default y
+        bool "Support Centaur processors" if PROCESSOR_SELECT
+        depends on 64BIT
+        help
+          This enables extended support for Centaur processors
+
+config CPU_SUP_TRANSMETA_32
+        default y
+        bool "Support Transmeta processors" if PROCESSOR_SELECT
+        depends on !64BIT
+        help
+          This enables extended support for Transmeta processors
+
+config CPU_SUP_UMC_32
+        default y
+        bool "Support UMC processors" if PROCESSOR_SELECT
+        depends on !64BIT
+        help
+          This enables extended support for UMC processors
+
+config X86_DS
+        bool "Debug Store support"
+        default y
+        help
+          Add support for Debug Store.
+          This allows the kernel to provide a memory buffer to the hardware
+          to store various profiling and tracing events.
+
+config X86_PTRACE_BTS
+        bool "ptrace interface to Branch Trace Store"
+        default y
+        depends on (X86_DS && X86_DEBUGCTLMSR)
+        help
+          Add a ptrace interface to allow collecting an execution trace
+          of the traced task.
+          This collects control flow changes in a (cyclic) buffer and allows
+          debuggers to fill in the gaps and show an execution trace of the debuggee.
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index ba7736cf2ec7..29c5fbf08392 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -137,14 +137,15 @@ relocated:
  */
         movl output_len(%ebx), %eax
         pushl %eax
+                        # push arguments for decompress_kernel:
         pushl %ebp      # output address
         movl input_len(%ebx), %eax
         pushl %eax      # input_len
         leal input_data(%ebx), %eax
         pushl %eax      # input_data
         leal boot_heap(%ebx), %eax
-        pushl %eax      # heap area as third argument
-        pushl %esi      # real mode pointer as second arg
+        pushl %eax      # heap area
+        pushl %esi      # real mode pointer
         call decompress_kernel
         addl $20, %esp
         popl %ecx
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 9fea73706479..5780d361105b 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -16,7 +16,7 @@
  */
 #undef CONFIG_PARAVIRT
 #ifdef CONFIG_X86_32
-#define _ASM_DESC_H_ 1
+#define ASM_X86__DESC_H 1
 #endif
 
 #ifdef CONFIG_X86_64
@@ -27,7 +27,7 @@
 #include <linux/linkage.h>
 #include <linux/screen_info.h>
 #include <linux/elf.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/page.h>
 #include <asm/boot.h>
 #include <asm/bootparam.h>
@@ -251,7 +251,7 @@ static void __putstr(int error, const char *s)
                                 y--;
                         }
                 } else {
-                        vidmem [(x + cols * y) * 2] = c;
+                        vidmem[(x + cols * y) * 2] = c;
                         if (++x >= cols) {
                                 x = 0;
                                 if (++y >= lines) {
@@ -277,7 +277,8 @@ static void *memset(void *s, int c, unsigned n)
         int i;
         char *ss = s;
 
-        for (i = 0; i < n; i++) ss[i] = c;
+        for (i = 0; i < n; i++)
+                ss[i] = c;
         return s;
 }
 
@@ -287,7 +288,8 @@ static void *memcpy(void *dest, const void *src, unsigned n)
         const char *s = src;
         char *d = dest;
 
-        for (i = 0; i < n; i++) d[i] = s[i];
+        for (i = 0; i < n; i++)
+                d[i] = s[i];
         return dest;
 }
 
diff --git a/arch/x86/boot/compressed/relocs.c b/arch/x86/boot/compressed/relocs.c
index a1310c52fc0c..857e492c571e 100644
--- a/arch/x86/boot/compressed/relocs.c
+++ b/arch/x86/boot/compressed/relocs.c
@@ -492,7 +492,7 @@ static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym))
                         continue;
                 }
                 sh_symtab = sec_symtab->symtab;
-                sym_strtab = sec->link->strtab;
+                sym_strtab = sec_symtab->link->strtab;
                 for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Rel); j++) {
                         Elf32_Rel *rel;
                         Elf32_Sym *sym;
diff --git a/arch/x86/boot/cpu.c b/arch/x86/boot/cpu.c
index 75298fe2edca..6ec6bb6e9957 100644
--- a/arch/x86/boot/cpu.c
+++ b/arch/x86/boot/cpu.c
@@ -59,17 +59,18 @@ int validate_cpu(void)
                         u32 e = err_flags[i];
 
                         for (j = 0; j < 32; j++) {
-                                int n = (i << 5)+j;
-                                if (*msg_strs < n) {
+                                if (msg_strs[0] < i ||
+                                    (msg_strs[0] == i && msg_strs[1] < j)) {
                                         /* Skip to the next string */
-                                        do {
-                                                msg_strs++;
-                                        } while (*msg_strs);
-                                        msg_strs++;
+                                        msg_strs += 2;
+                                        while (*msg_strs++)
+                                                ;
                                 }
                                 if (e & 1) {
-                                        if (*msg_strs == n && msg_strs[1])
-                                                printf("%s ", msg_strs+1);
+                                        if (msg_strs[0] == i &&
+                                            msg_strs[1] == j &&
+                                            msg_strs[2])
+                                                printf("%s ", msg_strs+2);
                                         else
                                                 printf("%d:%d ", i, j);
                                 }
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
index af86e431acfa..b993062e9a5f 100644
--- a/arch/x86/boot/header.S
+++ b/arch/x86/boot/header.S
@@ -30,7 +30,6 @@ SYSSEG		= DEF_SYSSEG		/* system loaded at 0x10000 (65536) */
 SYSSIZE         = DEF_SYSSIZE           /* system size: # of 16-byte clicks */
                                         /* to be loaded */
 ROOT_DEV        = 0                     /* ROOT_DEV is now written by "build" */
-SWAP_DEV        = 0                     /* SWAP_DEV is now written by "build" */
 
 #ifndef SVGA_MODE
 #define SVGA_MODE ASK_VGA
diff --git a/arch/x86/boot/mkcpustr.c b/arch/x86/boot/mkcpustr.c
index bbe76953bae9..8ef60f20b371 100644
--- a/arch/x86/boot/mkcpustr.c
+++ b/arch/x86/boot/mkcpustr.c
@@ -15,33 +15,33 @@
 
 #include <stdio.h>
 
-#include "../kernel/cpu/feature_names.c"
-
-#if NCAPFLAGS > 8
-# error "Need to adjust the boot code handling of CPUID strings"
-#endif
+#include "../kernel/cpu/capflags.c"
 
 int main(void)
 {
-        int i;
+        int i, j;
         const char *str;
 
         printf("static const char x86_cap_strs[] = \n");
 
-        for (i = 0; i < NCAPINTS*32; i++) {
-                str = x86_cap_flags[i];
-
-                if (i == NCAPINTS*32-1) {
-                        /* The last entry must be unconditional; this
-                           also consumes the compiler-added null character */
-                        if (!str)
-                                str = "";
-                        printf("\t\"\\x%02x\"\"%s\"\n", i, str);
-                } else if (str) {
-                        printf("#if REQUIRED_MASK%d & (1 << %d)\n"
-                               "\t\"\\x%02x\"\"%s\\0\"\n"
-                               "#endif\n",
-                               i >> 5, i & 31, i, str);
+        for (i = 0; i < NCAPINTS; i++) {
+                for (j = 0; j < 32; j++) {
+                        str = x86_cap_flags[i*32+j];
+
+                        if (i == NCAPINTS-1 && j == 31) {
+                                /* The last entry must be unconditional; this
+                                   also consumes the compiler-added null
+                                   character */
+                                if (!str)
+                                        str = "";
+                                printf("\t\"\\x%02x\\x%02x\"\"%s\"\n",
+                                       i, j, str);
+                        } else if (str) {
+                                printf("#if REQUIRED_MASK%d & (1 << %d)\n"
+                                       "\t\"\\x%02x\\x%02x\"\"%s\\0\"\n"
+                                       "#endif\n",
+                                       i, j, i, j, str);
+                        }
                 }
         }
         printf("\t;\n");
diff --git a/arch/x86/configs/i386_defconfig b/arch/x86/configs/i386_defconfig
index 104275e191a8..ef9a52005ec9 100644
--- a/arch/x86/configs/i386_defconfig
+++ b/arch/x86/configs/i386_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc4
-# Mon Aug 25 15:04:00 2008
+# Linux kernel version: 2.6.27-rc5
+# Wed Sep  3 17:23:09 2008
 #
 # CONFIG_64BIT is not set
 CONFIG_X86_32=y
@@ -202,7 +202,7 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
 # CONFIG_M586 is not set
 # CONFIG_M586TSC is not set
 # CONFIG_M586MMX is not set
-# CONFIG_M686 is not set
+CONFIG_M686=y
 # CONFIG_MPENTIUMII is not set
 # CONFIG_MPENTIUMIII is not set
 # CONFIG_MPENTIUMM is not set
@@ -221,13 +221,14 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
 # CONFIG_MVIAC3_2 is not set
 # CONFIG_MVIAC7 is not set
 # CONFIG_MPSC is not set
-CONFIG_MCORE2=y
+# CONFIG_MCORE2 is not set
 # CONFIG_GENERIC_CPU is not set
 CONFIG_X86_GENERIC=y
 CONFIG_X86_CPU=y
 CONFIG_X86_CMPXCHG=y
 CONFIG_X86_L1_CACHE_SHIFT=7
 CONFIG_X86_XADD=y
+# CONFIG_X86_PPRO_FENCE is not set
 CONFIG_X86_WP_WORKS_OK=y
 CONFIG_X86_INVLPG=y
 CONFIG_X86_BSWAP=y
@@ -235,14 +236,15 @@ CONFIG_X86_POPAD_OK=y
 CONFIG_X86_INTEL_USERCOPY=y
 CONFIG_X86_USE_PPRO_CHECKSUM=y
 CONFIG_X86_TSC=y
+CONFIG_X86_CMOV=y
 CONFIG_X86_MINIMUM_CPU_FAMILY=4
 CONFIG_X86_DEBUGCTLMSR=y
 CONFIG_HPET_TIMER=y
 CONFIG_HPET_EMULATE_RTC=y
 CONFIG_DMI=y
 # CONFIG_IOMMU_HELPER is not set
-CONFIG_NR_CPUS=4
-# CONFIG_SCHED_SMT is not set
+CONFIG_NR_CPUS=64
+CONFIG_SCHED_SMT=y
 CONFIG_SCHED_MC=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
@@ -254,7 +256,8 @@ CONFIG_VM86=y
 # CONFIG_TOSHIBA is not set
 # CONFIG_I8K is not set
 CONFIG_X86_REBOOTFIXUPS=y
-# CONFIG_MICROCODE is not set
+CONFIG_MICROCODE=y
+CONFIG_MICROCODE_OLD_INTERFACE=y
 CONFIG_X86_MSR=y
 CONFIG_X86_CPUID=y
 # CONFIG_NOHIGHMEM is not set
@@ -2115,7 +2118,7 @@ CONFIG_IO_DELAY_0X80=y
 CONFIG_DEFAULT_IO_DELAY_TYPE=0
 CONFIG_DEBUG_BOOT_PARAMS=y
 # CONFIG_CPA_DEBUG is not set
-# CONFIG_OPTIMIZE_INLINING is not set
+CONFIG_OPTIMIZE_INLINING=y
 
 #
 # Security options
diff --git a/arch/x86/configs/x86_64_defconfig b/arch/x86/configs/x86_64_defconfig
index 678c8acefe04..e620ea6e2a7a 100644
--- a/arch/x86/configs/x86_64_defconfig
+++ b/arch/x86/configs/x86_64_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc4
-# Mon Aug 25 14:40:46 2008
+# Linux kernel version: 2.6.27-rc5
+# Wed Sep  3 17:13:39 2008
 #
 CONFIG_64BIT=y
 # CONFIG_X86_32 is not set
@@ -218,17 +218,14 @@ CONFIG_X86_PC=y
 # CONFIG_MVIAC3_2 is not set
 # CONFIG_MVIAC7 is not set
 # CONFIG_MPSC is not set
-CONFIG_MCORE2=y
-# CONFIG_GENERIC_CPU is not set
+# CONFIG_MCORE2 is not set
+CONFIG_GENERIC_CPU=y
 CONFIG_X86_CPU=y
-CONFIG_X86_L1_CACHE_BYTES=64
-CONFIG_X86_INTERNODE_CACHE_BYTES=64
+CONFIG_X86_L1_CACHE_BYTES=128
+CONFIG_X86_INTERNODE_CACHE_BYTES=128
 CONFIG_X86_CMPXCHG=y
-CONFIG_X86_L1_CACHE_SHIFT=6
+CONFIG_X86_L1_CACHE_SHIFT=7
 CONFIG_X86_WP_WORKS_OK=y
-CONFIG_X86_INTEL_USERCOPY=y
-CONFIG_X86_USE_PPRO_CHECKSUM=y
-CONFIG_X86_P6_NOP=y
 CONFIG_X86_TSC=y
 CONFIG_X86_CMPXCHG64=y
 CONFIG_X86_CMOV=y
@@ -243,9 +240,8 @@ CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y
 CONFIG_AMD_IOMMU=y
 CONFIG_SWIOTLB=y
 CONFIG_IOMMU_HELPER=y
-# CONFIG_MAXSMP is not set
-CONFIG_NR_CPUS=4
-# CONFIG_SCHED_SMT is not set
+CONFIG_NR_CPUS=64
+CONFIG_SCHED_SMT=y
 CONFIG_SCHED_MC=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
@@ -254,7 +250,8 @@ CONFIG_X86_LOCAL_APIC=y
 CONFIG_X86_IO_APIC=y
 # CONFIG_X86_MCE is not set
 # CONFIG_I8K is not set
-# CONFIG_MICROCODE is not set
+CONFIG_MICROCODE=y
+CONFIG_MICROCODE_OLD_INTERFACE=y
 CONFIG_X86_MSR=y
 CONFIG_X86_CPUID=y
 CONFIG_NUMA=y
@@ -290,7 +287,7 @@ CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
 CONFIG_MTRR=y
 # CONFIG_MTRR_SANITIZER is not set
-# CONFIG_X86_PAT is not set
+CONFIG_X86_PAT=y
 CONFIG_EFI=y
 CONFIG_SECCOMP=y
 # CONFIG_HZ_100 is not set
@@ -2089,7 +2086,7 @@ CONFIG_IO_DELAY_0X80=y
 CONFIG_DEFAULT_IO_DELAY_TYPE=0
 CONFIG_DEBUG_BOOT_PARAMS=y
 # CONFIG_CPA_DEBUG is not set
-# CONFIG_OPTIMIZE_INLINING is not set
+CONFIG_OPTIMIZE_INLINING=y
 
 #
 # Security options
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index 3874c2de5403..903de4aa5094 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -10,6 +10,8 @@ obj-$(CONFIG_CRYPTO_AES_X86_64) += aes-x86_64.o
 obj-$(CONFIG_CRYPTO_TWOFISH_X86_64) += twofish-x86_64.o
 obj-$(CONFIG_CRYPTO_SALSA20_X86_64) += salsa20-x86_64.o
 
+obj-$(CONFIG_CRYPTO_CRC32C_INTEL) += crc32c-intel.o
+
 aes-i586-y := aes-i586-asm_32.o aes_glue.o
 twofish-i586-y := twofish-i586-asm_32.o twofish_glue.o
 salsa20-i586-y := salsa20-i586-asm_32.o salsa20_glue.o
diff --git a/arch/x86/crypto/crc32c-intel.c b/arch/x86/crypto/crc32c-intel.c
new file mode 100644
index 000000000000..070afc5b6c94
--- /dev/null
+++ b/arch/x86/crypto/crc32c-intel.c
@@ -0,0 +1,197 @@
+/*
+ * Using hardware provided CRC32 instruction to accelerate the CRC32 disposal.
+ * CRC32C polynomial:0x1EDC6F41(BE)/0x82F63B78(LE)
+ * CRC32 is a new instruction in Intel SSE4.2, the reference can be found at:
+ * http://www.intel.com/products/processor/manuals/
+ * Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+ * Volume 2A: Instruction Set Reference, A-M
+ *
+ * Copyright (c) 2008 Austin Zhang <austin_zhang@linux.intel.com>
+ * Copyright (c) 2008 Kent Liu <kent.liu@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <crypto/internal/hash.h>
+
+#include <asm/cpufeature.h>
+
+#define CHKSUM_BLOCK_SIZE       1
+#define CHKSUM_DIGEST_SIZE      4
+
+#define SCALE_F sizeof(unsigned long)
+
+#ifdef CONFIG_X86_64
+#define REX_PRE "0x48, "
+#else
+#define REX_PRE
+#endif
+
+static u32 crc32c_intel_le_hw_byte(u32 crc, unsigned char const *data, size_t length)
+{
+        while (length--) {
+                __asm__ __volatile__(
+                        ".byte 0xf2, 0xf, 0x38, 0xf0, 0xf1"
+                        :"=S"(crc)
+                        :"0"(crc), "c"(*data)
+                );
+                data++;
+        }
+
+        return crc;
+}
+
+static u32 __pure crc32c_intel_le_hw(u32 crc, unsigned char const *p, size_t len)
+{
+        unsigned int iquotient = len / SCALE_F;
+        unsigned int iremainder = len % SCALE_F;
+        unsigned long *ptmp = (unsigned long *)p;
+
+        while (iquotient--) {
+                __asm__ __volatile__(
+                        ".byte 0xf2, " REX_PRE "0xf, 0x38, 0xf1, 0xf1;"
+                        :"=S"(crc)
+                        :"0"(crc), "c"(*ptmp)
+                );
+                ptmp++;
+        }
+
+        if (iremainder)
+                crc = crc32c_intel_le_hw_byte(crc, (unsigned char *)ptmp,
+                                 iremainder);
+
+        return crc;
+}
+
+/*
+ * Setting the seed allows arbitrary accumulators and flexible XOR policy
+ * If your algorithm starts with ~0, then XOR with ~0 before you set
+ * the seed.
+ */
+static int crc32c_intel_setkey(struct crypto_ahash *hash, const u8 *key,
+                        unsigned int keylen)
+{
+        u32 *mctx = crypto_ahash_ctx(hash);
+
+        if (keylen != sizeof(u32)) {
+                crypto_ahash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+                return -EINVAL;
+        }
+        *mctx = le32_to_cpup((__le32 *)key);
+        return 0;
+}
+
+static int crc32c_intel_init(struct ahash_request *req)
+{
+        u32 *mctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
+        u32 *crcp = ahash_request_ctx(req);
+
+        *crcp = *mctx;
+
+        return 0;
+}
+
+static int crc32c_intel_update(struct ahash_request *req)
+{
+        struct crypto_hash_walk walk;
+        u32 *crcp = ahash_request_ctx(req);
+        u32 crc = *crcp;
+        int nbytes;
+
+        for (nbytes = crypto_hash_walk_first(req, &walk); nbytes;
+           nbytes = crypto_hash_walk_done(&walk, 0))
+        crc = crc32c_intel_le_hw(crc, walk.data, nbytes);
+
+        *crcp = crc;
+        return 0;
+}
+
+static int crc32c_intel_final(struct ahash_request *req)
+{
+        u32 *crcp = ahash_request_ctx(req);
+
+        *(__le32 *)req->result = ~cpu_to_le32p(crcp);
+        return 0;
+}
+
+static int crc32c_intel_digest(struct ahash_request *req)
+{
+        struct crypto_hash_walk walk;
+        u32 *mctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
+        u32 crc = *mctx;
+        int nbytes;
+
+        for (nbytes = crypto_hash_walk_first(req, &walk); nbytes;
+           nbytes = crypto_hash_walk_done(&walk, 0))
+                crc = crc32c_intel_le_hw(crc, walk.data, nbytes);
+
+        *(__le32 *)req->result = ~cpu_to_le32(crc);
+        return 0;
+}
+
+static int crc32c_intel_cra_init(struct crypto_tfm *tfm)
+{
+        u32 *key = crypto_tfm_ctx(tfm);
+
+        *key = ~0;
+
+        tfm->crt_ahash.reqsize = sizeof(u32);
+
+        return 0;
+}
+
+static struct crypto_alg alg = {
+        .cra_name               =       "crc32c",
+        .cra_driver_name        =       "crc32c-intel",
+        .cra_priority           =       200,
+        .cra_flags              =       CRYPTO_ALG_TYPE_AHASH,
+        .cra_blocksize          =       CHKSUM_BLOCK_SIZE,
+        .cra_alignmask          =       3,
+        .cra_ctxsize            =       sizeof(u32),
+        .cra_module             =       THIS_MODULE,
+        .cra_list               =       LIST_HEAD_INIT(alg.cra_list),
+        .cra_init               =       crc32c_intel_cra_init,
+        .cra_type               =       &crypto_ahash_type,
+        .cra_u                  =       {
+                .ahash = {
+                        .digestsize    =       CHKSUM_DIGEST_SIZE,
+                        .setkey        =       crc32c_intel_setkey,
+                        .init          =       crc32c_intel_init,
+                        .update        =       crc32c_intel_update,
+                        .final         =       crc32c_intel_final,
+                        .digest        =       crc32c_intel_digest,
+                }
+        }
+};
+
+
+static int __init crc32c_intel_mod_init(void)
+{
+        if (cpu_has_xmm4_2)
+                return crypto_register_alg(&alg);
+        else
+                return -ENODEV;
+}
+
+static void __exit crc32c_intel_mod_fini(void)
+{
+        crypto_unregister_alg(&alg);
+}
+
+module_init(crc32c_intel_mod_init);
+module_exit(crc32c_intel_mod_fini);
+
+MODULE_AUTHOR("Austin Zhang <austin.zhang@intel.com>, Kent Liu <kent.liu@intel.com>");
+MODULE_DESCRIPTION("CRC32c (Castagnoli) optimization using Intel Hardware.");
+MODULE_LICENSE("GPL");
+
+MODULE_ALIAS("crc32c");
+MODULE_ALIAS("crc32c-intel");
+
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index a0e1dbe67dc1..127ec3f07214 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -85,8 +85,10 @@ static void dump_thread32(struct pt_regs *regs, struct user32 *dump)
         dump->regs.ax = regs->ax;
         dump->regs.ds = current->thread.ds;
         dump->regs.es = current->thread.es;
-        asm("movl %%fs,%0" : "=r" (fs)); dump->regs.fs = fs;
-        asm("movl %%gs,%0" : "=r" (gs)); dump->regs.gs = gs;
+        savesegment(fs, fs);
+        dump->regs.fs = fs;
+        savesegment(gs, gs);
+        dump->regs.gs = gs;
         dump->regs.orig_ax = regs->orig_ax;
         dump->regs.ip = regs->ip;
         dump->regs.cs = regs->cs;
@@ -430,8 +432,9 @@ beyond_if:
         current->mm->start_stack =
                 (unsigned long)create_aout_tables((char __user *)bprm->p, bprm);
         /* start thread */
-        asm volatile("movl %0,%%fs" :: "r" (0)); \
-        asm volatile("movl %0,%%es; movl %0,%%ds": :"r" (__USER32_DS));
+        loadsegment(fs, 0);
+        loadsegment(ds, __USER32_DS);
+        loadsegment(es, __USER32_DS);
         load_gs_index(0);
         (regs)->ip = ex.a_entry;
         (regs)->sp = current->mm->start_stack;
diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c
index 20af4c79579a..8d64c1bc8474 100644
--- a/arch/x86/ia32/ia32_signal.c
+++ b/arch/x86/ia32/ia32_signal.c
@@ -179,9 +179,10 @@ struct sigframe
         u32 pretcode;
         int sig;
         struct sigcontext_ia32 sc;
-        struct _fpstate_ia32 fpstate;
+        struct _fpstate_ia32 fpstate_unused; /* look at kernel/sigframe.h */
         unsigned int extramask[_COMPAT_NSIG_WORDS-1];
         char retcode[8];
+        /* fp state follows here */
 };
 
 struct rt_sigframe
@@ -192,8 +193,8 @@ struct rt_sigframe
         u32 puc;
         compat_siginfo_t info;
         struct ucontext_ia32 uc;
-        struct _fpstate_ia32 fpstate;
         char retcode[8];
+        /* fp state follows here */
 };
 
 #define COPY(x)         {               \
@@ -206,7 +207,7 @@ struct rt_sigframe
         { unsigned int cur;                                             \
           unsigned short pre;                                           \
           err |= __get_user(pre, &sc->seg);                             \
-          asm volatile("movl %%" #seg ",%0" : "=r" (cur));              \
+          savesegment(seg, cur);                                        \
           pre |= mask;                                                  \
           if (pre != cur) loadsegment(seg, pre); }
 
@@ -215,7 +216,7 @@ static int ia32_restore_sigcontext(struct pt_regs *regs,
                                    unsigned int *peax)
 {
         unsigned int tmpflags, gs, oldgs, err = 0;
-        struct _fpstate_ia32 __user *buf;
+        void __user *buf;
         u32 tmp;
 
         /* Always make any pending restarted system calls return -EINTR */
@@ -235,7 +236,7 @@ static int ia32_restore_sigcontext(struct pt_regs *regs,
          */
         err |= __get_user(gs, &sc->gs);
         gs |= 3;
-        asm("movl %%gs,%0" : "=r" (oldgs));
+        savesegment(gs, oldgs);
         if (gs != oldgs)
                 load_gs_index(gs);
 
@@ -259,26 +260,12 @@ static int ia32_restore_sigcontext(struct pt_regs *regs,
 
         err |= __get_user(tmp, &sc->fpstate);
         buf = compat_ptr(tmp);
-        if (buf) {
-                if (!access_ok(VERIFY_READ, buf, sizeof(*buf)))
-                        goto badframe;
-                err |= restore_i387_ia32(buf);
-        } else {
-                struct task_struct *me = current;
-
-                if (used_math()) {
-                        clear_fpu(me);
-                        clear_used_math();
-                }
-        }
+        err |= restore_i387_xstate_ia32(buf);
 
         err |= __get_user(tmp, &sc->ax);
         *peax = tmp;
 
         return err;
-
-badframe:
-        return 1;
 }
 
 asmlinkage long sys32_sigreturn(struct pt_regs *regs)
@@ -350,19 +337,18 @@ badframe:
  */
 
 static int ia32_setup_sigcontext(struct sigcontext_ia32 __user *sc,
-                                 struct _fpstate_ia32 __user *fpstate,
+                                 void __user *fpstate,
                                  struct pt_regs *regs, unsigned int mask)
 {
         int tmp, err = 0;
 
-        tmp = 0;
-        __asm__("movl %%gs,%0" : "=r"(tmp): "0"(tmp));
+        savesegment(gs, tmp);
         err |= __put_user(tmp, (unsigned int __user *)&sc->gs);
-        __asm__("movl %%fs,%0" : "=r"(tmp): "0"(tmp));
+        savesegment(fs, tmp);
         err |= __put_user(tmp, (unsigned int __user *)&sc->fs);
-        __asm__("movl %%ds,%0" : "=r"(tmp): "0"(tmp));
+        savesegment(ds, tmp);
         err |= __put_user(tmp, (unsigned int __user *)&sc->ds);
-        __asm__("movl %%es,%0" : "=r"(tmp): "0"(tmp));
+        savesegment(es, tmp);
         err |= __put_user(tmp, (unsigned int __user *)&sc->es);
 
         err |= __put_user((u32)regs->di, &sc->di);
@@ -381,7 +367,7 @@ static int ia32_setup_sigcontext(struct sigcontext_ia32 __user *sc,
         err |= __put_user((u32)regs->flags, &sc->flags);
         err |= __put_user((u32)regs->sp, &sc->sp_at_signal);
 
-        tmp = save_i387_ia32(fpstate);
+        tmp = save_i387_xstate_ia32(fpstate);
         if (tmp < 0)
                 err = -EFAULT;
         else {
@@ -402,7 +388,8 @@ static int ia32_setup_sigcontext(struct sigcontext_ia32 __user *sc,
  * Determine which stack to use..
  */
 static void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
-                                 size_t frame_size)
+                                 size_t frame_size,
+                                 void **fpstate)
 {
         unsigned long sp;
 
@@ -421,6 +408,11 @@ static void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
                  ka->sa.sa_restorer)
                 sp = (unsigned long) ka->sa.sa_restorer;
 
+        if (used_math()) {
+                sp = sp - sig_xstate_ia32_size;
+                *fpstate = (struct _fpstate_ia32 *) sp;
+        }
+
         sp -= frame_size;
         /* Align the stack pointer according to the i386 ABI,
          * i.e. so that on function entry ((sp + 4) & 15) == 0. */
@@ -434,6 +426,7 @@ int ia32_setup_frame(int sig, struct k_sigaction *ka,
         struct sigframe __user *frame;
         void __user *restorer;
         int err = 0;
+        void __user *fpstate = NULL;
 
         /* copy_to_user optimizes that into a single 8 byte store */
         static const struct {
@@ -448,7 +441,7 @@ int ia32_setup_frame(int sig, struct k_sigaction *ka,
                 0,
         };
 
-        frame = get_sigframe(ka, regs, sizeof(*frame));
+        frame = get_sigframe(ka, regs, sizeof(*frame), &fpstate);
 
         if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
                 goto give_sigsegv;
@@ -457,8 +450,7 @@ int ia32_setup_frame(int sig, struct k_sigaction *ka,
         if (err)
                 goto give_sigsegv;
 
-        err |= ia32_setup_sigcontext(&frame->sc, &frame->fpstate, regs,
-                                        set->sig[0]);
+        err |= ia32_setup_sigcontext(&frame->sc, fpstate, regs, set->sig[0]);
         if (err)
                 goto give_sigsegv;
 
@@ -498,8 +490,8 @@ int ia32_setup_frame(int sig, struct k_sigaction *ka,
         regs->dx = 0;
         regs->cx = 0;
 
-        asm volatile("movl %0,%%ds" :: "r" (__USER32_DS));
-        asm volatile("movl %0,%%es" :: "r" (__USER32_DS));
+        loadsegment(ds, __USER32_DS);
+        loadsegment(es, __USER32_DS);
 
         regs->cs = __USER32_CS;
         regs->ss = __USER32_DS;
@@ -522,6 +514,7 @@ int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         struct rt_sigframe __user *frame;
         void __user *restorer;
         int err = 0;
+        void __user *fpstate = NULL;
 
         /* __copy_to_user optimizes that into a single 8 byte store */
         static const struct {
@@ -537,7 +530,7 @@ int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                 0,
         };
 
-        frame = get_sigframe(ka, regs, sizeof(*frame));
+        frame = get_sigframe(ka, regs, sizeof(*frame), &fpstate);
 
         if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
                 goto give_sigsegv;
@@ -550,13 +543,16 @@ int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                 goto give_sigsegv;
 
         /* Create the ucontext.  */
-        err |= __put_user(0, &frame->uc.uc_flags);
+        if (cpu_has_xsave)
+                err |= __put_user(UC_FP_XSTATE, &frame->uc.uc_flags);
+        else
+                err |= __put_user(0, &frame->uc.uc_flags);
         err |= __put_user(0, &frame->uc.uc_link);
         err |= __put_user(current->sas_ss_sp, &frame->uc.uc_stack.ss_sp);
         err |= __put_user(sas_ss_flags(regs->sp),
                           &frame->uc.uc_stack.ss_flags);
         err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
-        err |= ia32_setup_sigcontext(&frame->uc.uc_mcontext, &frame->fpstate,
+        err |= ia32_setup_sigcontext(&frame->uc.uc_mcontext, fpstate,
                                      regs, set->sig[0]);
         err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
         if (err)
@@ -591,8 +587,8 @@ int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         regs->dx = (unsigned long) &frame->info;
         regs->cx = (unsigned long) &frame->uc;
 
-        asm volatile("movl %0,%%ds" :: "r" (__USER32_DS));
-        asm volatile("movl %0,%%es" :: "r" (__USER32_DS));
+        loadsegment(ds, __USER32_DS);
+        loadsegment(es, __USER32_DS);
 
         regs->cs = __USER32_CS;
         regs->ss = __USER32_DS;
diff --git a/arch/x86/ia32/sys_ia32.c b/arch/x86/ia32/sys_ia32.c
index d3c64088b981..beda4232ce69 100644
--- a/arch/x86/ia32/sys_ia32.c
+++ b/arch/x86/ia32/sys_ia32.c
@@ -556,15 +556,6 @@ asmlinkage long sys32_rt_sigqueueinfo(int pid, int sig,
         return ret;
 }
 
-/* These are here just in case some old ia32 binary calls it. */
-asmlinkage long sys32_pause(void)
-{
-        current->state = TASK_INTERRUPTIBLE;
-        schedule();
-        return -ERESTARTNOHAND;
-}
-
-
 #ifdef CONFIG_SYSCTL_SYSCALL
 struct sysctl_ia32 {
         unsigned int    name;
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 3db651fc8ec5..c9be69fedb70 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -38,7 +38,7 @@ obj-y			+= tsc.o io_delay.o rtc.o
 
 obj-$(CONFIG_X86_TRAMPOLINE)    += trampoline.o
 obj-y                           += process.o
-obj-y                           += i387.o
+obj-y                           += i387.o xsave.o
 obj-y                           += ptrace.o
 obj-y                           += ds.o
 obj-$(CONFIG_X86_32)            += tls.o
@@ -69,6 +69,7 @@ obj-$(CONFIG_KEXEC)		+= machine_kexec_$(BITS).o
 obj-$(CONFIG_KEXEC)             += relocate_kernel_$(BITS).o crash.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump_$(BITS).o
 obj-$(CONFIG_X86_NUMAQ)         += numaq_32.o
+obj-$(CONFIG_X86_ES7000)        += es7000_32.o
 obj-$(CONFIG_X86_SUMMIT_NUMA)   += summit_32.o
 obj-y                           += vsmp_64.o
 obj-$(CONFIG_KPROBES)           += kprobes.o
@@ -104,6 +105,8 @@ obj-$(CONFIG_OLPC)		+= olpc.o
 ifeq ($(CONFIG_X86_64),y)
         obj-y                           += genapic_64.o genapic_flat_64.o genx2apic_uv_x.o tlb_uv.o
         obj-y                           += bios_uv.o
+        obj-y                           += genx2apic_cluster.o
+        obj-y                           += genx2apic_phys.o
         obj-$(CONFIG_X86_PM_TIMER)      += pmtimer_64.o
         obj-$(CONFIG_AUDIT)             += audit_64.o
 
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index bfd10fd211cd..c2ac1b4515a0 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -58,7 +58,6 @@ EXPORT_SYMBOL(acpi_disabled);
 #ifdef  CONFIG_X86_64
 
 #include <asm/proto.h>
-#include <asm/genapic.h>
 
 #else                           /* X86 */
 
@@ -97,8 +96,6 @@ static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
 #warning ACPI uses CMPXCHG, i486 and later hardware
 #endif
 
-static int acpi_mcfg_64bit_base_addr __initdata = FALSE;
-
 /* --------------------------------------------------------------------------
                               Boot-time Configuration
    -------------------------------------------------------------------------- */
@@ -160,6 +157,8 @@ char *__init __acpi_map_table(unsigned long phys, unsigned long size)
 struct acpi_mcfg_allocation *pci_mmcfg_config;
 int pci_mmcfg_config_num;
 
+static int acpi_mcfg_64bit_base_addr __initdata = FALSE;
+
 static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg)
 {
         if (!strcmp(mcfg->header.oem_id, "SGI"))
@@ -253,10 +252,8 @@ static void __cpuinit acpi_register_lapic(int id, u8 enabled)
                 return;
         }
 
-#ifdef CONFIG_X86_32
         if (boot_cpu_physical_apicid != -1U)
                 ver = apic_version[boot_cpu_physical_apicid];
-#endif
 
         generic_processor_info(id, ver);
 }
@@ -775,11 +772,9 @@ static void __init acpi_register_lapic_address(unsigned long address)
 
         set_fixmap_nocache(FIX_APIC_BASE, address);
         if (boot_cpu_physical_apicid == -1U) {
-                boot_cpu_physical_apicid  = GET_APIC_ID(read_apic_id());
-#ifdef CONFIG_X86_32
+                boot_cpu_physical_apicid  = read_apic_id();
                 apic_version[boot_cpu_physical_apicid] =
                          GET_APIC_VERSION(apic_read(APIC_LVR));
-#endif
         }
 }
 
@@ -1351,7 +1346,9 @@ static void __init acpi_process_madt(void)
                                 acpi_ioapic = 1;
 
                                 smp_found_config = 1;
+#ifdef CONFIG_X86_32
                                 setup_apic_routing();
+#endif
                         }
                 }
                 if (error == -EINVAL) {
@@ -1605,6 +1602,14 @@ static struct dmi_system_id __initdata acpi_dmi_table[] = {
          */
         {
          .callback = dmi_ignore_irq0_timer_override,
+         .ident = "HP nx6115 laptop",
+         .matches = {
+                     DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+                     DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6115"),
+                     },
+         },
+        {
+         .callback = dmi_ignore_irq0_timer_override,
          .ident = "HP NX6125 laptop",
          .matches = {
                      DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
@@ -1619,6 +1624,14 @@ static struct dmi_system_id __initdata acpi_dmi_table[] = {
                      DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"),
                      },
          },
+        {
+         .callback = dmi_ignore_irq0_timer_override,
+         .ident = "HP 6715b laptop",
+         .matches = {
+                     DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
+                     DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6715b"),
+                     },
+         },
         {}
 };
 
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 65a0c1b48696..fb04e49776ba 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -231,25 +231,25 @@ static void alternatives_smp_lock(u8 **start, u8 **end, u8 *text, u8 *text_end)
                         continue;
                 if (*ptr > text_end)
                         continue;
-                text_poke(*ptr, ((unsigned char []){0xf0}), 1); /* add lock prefix */
+                /* turn DS segment override prefix into lock prefix */
+                text_poke(*ptr, ((unsigned char []){0xf0}), 1);
         };
 }
 
 static void alternatives_smp_unlock(u8 **start, u8 **end, u8 *text, u8 *text_end)
 {
         u8 **ptr;
-        char insn[1];
 
         if (noreplace_smp)
                 return;
 
-        add_nops(insn, 1);
         for (ptr = start; ptr < end; ptr++) {
                 if (*ptr < text)
                         continue;
                 if (*ptr > text_end)
                         continue;
-                text_poke(*ptr, insn, 1);
+                /* turn lock prefix into DS segment override prefix */
+                text_poke(*ptr, ((unsigned char []){0x3E}), 1);
         };
 }
 
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index 69b4d060b21c..34e4d112b1ef 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -33,6 +33,10 @@
 
 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
 
+/* A list of preallocated protection domains */
+static LIST_HEAD(iommu_pd_list);
+static DEFINE_SPINLOCK(iommu_pd_list_lock);
+
 /*
  * general struct to manage commands send to an IOMMU
  */
@@ -51,6 +55,102 @@ static int iommu_has_npcache(struct amd_iommu *iommu)
 
 /****************************************************************************
  *
+ * Interrupt handling functions
+ *
+ ****************************************************************************/
+
+static void iommu_print_event(void *__evt)
+{
+        u32 *event = __evt;
+        int type  = (event[1] >> EVENT_TYPE_SHIFT)  & EVENT_TYPE_MASK;
+        int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
+        int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
+        int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
+        u64 address = (u64)(((u64)event[3]) << 32) | event[2];
+
+        printk(KERN_ERR "AMD IOMMU: Event logged [");
+
+        switch (type) {
+        case EVENT_TYPE_ILL_DEV:
+                printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
+                       "address=0x%016llx flags=0x%04x]\n",
+                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
+                       address, flags);
+                break;
+        case EVENT_TYPE_IO_FAULT:
+                printk("IO_PAGE_FAULT device=%02x:%02x.%x "
+                       "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
+                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
+                       domid, address, flags);
+                break;
+        case EVENT_TYPE_DEV_TAB_ERR:
+                printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
+                       "address=0x%016llx flags=0x%04x]\n",
+                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
+                       address, flags);
+                break;
+        case EVENT_TYPE_PAGE_TAB_ERR:
+                printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
+                       "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
+                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
+                       domid, address, flags);
+                break;
+        case EVENT_TYPE_ILL_CMD:
+                printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
+                break;
+        case EVENT_TYPE_CMD_HARD_ERR:
+                printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
+                       "flags=0x%04x]\n", address, flags);
+                break;
+        case EVENT_TYPE_IOTLB_INV_TO:
+                printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
+                       "address=0x%016llx]\n",
+                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
+                       address);
+                break;
+        case EVENT_TYPE_INV_DEV_REQ:
+                printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
+                       "address=0x%016llx flags=0x%04x]\n",
+                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
+                       address, flags);
+                break;
+        default:
+                printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
+        }
+}
+
+static void iommu_poll_events(struct amd_iommu *iommu)
+{
+        u32 head, tail;
+        unsigned long flags;
+
+        spin_lock_irqsave(&iommu->lock, flags);
+
+        head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
+        tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
+
+        while (head != tail) {
+                iommu_print_event(iommu->evt_buf + head);
+                head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
+        }
+
+        writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
+
+        spin_unlock_irqrestore(&iommu->lock, flags);
+}
+
+irqreturn_t amd_iommu_int_handler(int irq, void *data)
+{
+        struct amd_iommu *iommu;
+
+        list_for_each_entry(iommu, &amd_iommu_list, list)
+                iommu_poll_events(iommu);
+
+        return IRQ_HANDLED;
+}
+
+/****************************************************************************
+ *
  * IOMMU command queuing functions
  *
  ****************************************************************************/
@@ -101,10 +201,10 @@ static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
  */
 static int iommu_completion_wait(struct amd_iommu *iommu)
 {
-        int ret, ready = 0;
+        int ret = 0, ready = 0;
         unsigned status = 0;
         struct iommu_cmd cmd;
-        unsigned long i = 0;
+        unsigned long flags, i = 0;
 
         memset(&cmd, 0, sizeof(cmd));
         cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
@@ -112,10 +212,12 @@ static int iommu_completion_wait(struct amd_iommu *iommu)
 
         iommu->need_sync = 0;
 
-        ret = iommu_queue_command(iommu, &cmd);
+        spin_lock_irqsave(&iommu->lock, flags);
+
+        ret = __iommu_queue_command(iommu, &cmd);
 
         if (ret)
-                return ret;
+                goto out;
 
         while (!ready && (i < EXIT_LOOP_COUNT)) {
                 ++i;
@@ -130,6 +232,8 @@ static int iommu_completion_wait(struct amd_iommu *iommu)
 
         if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
                 printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
+out:
+        spin_unlock_irqrestore(&iommu->lock, flags);
 
         return 0;
 }
@@ -140,6 +244,7 @@ static int iommu_completion_wait(struct amd_iommu *iommu)
 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
 {
         struct iommu_cmd cmd;
+        int ret;
 
         BUG_ON(iommu == NULL);
 
@@ -147,9 +252,11 @@ static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
         CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
         cmd.data[0] = devid;
 
+        ret = iommu_queue_command(iommu, &cmd);
+
         iommu->need_sync = 1;
 
-        return iommu_queue_command(iommu, &cmd);
+        return ret;
 }
 
 /*
@@ -159,6 +266,7 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
                 u64 address, u16 domid, int pde, int s)
 {
         struct iommu_cmd cmd;
+        int ret;
 
         memset(&cmd, 0, sizeof(cmd));
         address &= PAGE_MASK;
@@ -171,9 +279,11 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
         if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
                 cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
 
+        ret = iommu_queue_command(iommu, &cmd);
+
         iommu->need_sync = 1;
 
-        return iommu_queue_command(iommu, &cmd);
+        return ret;
 }
 
 /*
@@ -203,6 +313,14 @@ static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
         return 0;
 }
 
+/* Flush the whole IO/TLB for a given protection domain */
+static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
+{
+        u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
+
+        iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
+}
+
 /****************************************************************************
  *
  * The functions below are used the create the page table mappings for
@@ -362,11 +480,6 @@ static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
  * efficient allocator.
  *
  ****************************************************************************/
-static unsigned long dma_mask_to_pages(unsigned long mask)
-{
-        return (mask >> PAGE_SHIFT) +
-                (PAGE_ALIGN(mask & ~PAGE_MASK) >> PAGE_SHIFT);
-}
 
 /*
  * The address allocator core function.
@@ -375,25 +488,31 @@ static unsigned long dma_mask_to_pages(unsigned long mask)
  */
 static unsigned long dma_ops_alloc_addresses(struct device *dev,
                                              struct dma_ops_domain *dom,
-                                             unsigned int pages)
+                                             unsigned int pages,
+                                             unsigned long align_mask,
+                                             u64 dma_mask)
 {
-        unsigned long limit = dma_mask_to_pages(*dev->dma_mask);
+        unsigned long limit;
         unsigned long address;
-        unsigned long size = dom->aperture_size >> PAGE_SHIFT;
         unsigned long boundary_size;
 
         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
                         PAGE_SIZE) >> PAGE_SHIFT;
-        limit = limit < size ? limit : size;
+        limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
+                                       dma_mask >> PAGE_SHIFT);
 
-        if (dom->next_bit >= limit)
+        if (dom->next_bit >= limit) {
                 dom->next_bit = 0;
+                dom->need_flush = true;
+        }
 
         address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
-                        0 , boundary_size, 0);
-        if (address == -1)
+                                   0 , boundary_size, align_mask);
+        if (address == -1) {
                 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
-                                0, boundary_size, 0);
+                                0, boundary_size, align_mask);
+                dom->need_flush = true;
+        }
 
         if (likely(address != -1)) {
                 dom->next_bit = address + pages;
@@ -459,7 +578,7 @@ static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
         if (start_page + pages > last_page)
                 pages = last_page - start_page;
 
-        set_bit_string(dom->bitmap, start_page, pages);
+        iommu_area_reserve(dom->bitmap, start_page, pages);
 }
 
 static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
@@ -553,6 +672,9 @@ static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
         dma_dom->bitmap[0] = 1;
         dma_dom->next_bit = 0;
 
+        dma_dom->need_flush = false;
+        dma_dom->target_dev = 0xffff;
+
         /* Intialize the exclusion range if necessary */
         if (iommu->exclusion_start &&
             iommu->exclusion_start < dma_dom->aperture_size) {
@@ -623,12 +745,13 @@ static void set_device_domain(struct amd_iommu *iommu,
 
         u64 pte_root = virt_to_phys(domain->pt_root);
 
-        pte_root |= (domain->mode & 0x07) << 9;
-        pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | 2;
+        pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
+                    << DEV_ENTRY_MODE_SHIFT;
+        pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
 
         write_lock_irqsave(&amd_iommu_devtable_lock, flags);
-        amd_iommu_dev_table[devid].data[0] = pte_root;
-        amd_iommu_dev_table[devid].data[1] = pte_root >> 32;
+        amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
+        amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
         amd_iommu_dev_table[devid].data[2] = domain->id;
 
         amd_iommu_pd_table[devid] = domain;
@@ -646,6 +769,45 @@ static void set_device_domain(struct amd_iommu *iommu,
  *****************************************************************************/
 
 /*
+ * This function checks if the driver got a valid device from the caller to
+ * avoid dereferencing invalid pointers.
+ */
+static bool check_device(struct device *dev)
+{
+        if (!dev || !dev->dma_mask)
+                return false;
+
+        return true;
+}
+
+/*
+ * In this function the list of preallocated protection domains is traversed to
+ * find the domain for a specific device
+ */
+static struct dma_ops_domain *find_protection_domain(u16 devid)
+{
+        struct dma_ops_domain *entry, *ret = NULL;
+        unsigned long flags;
+
+        if (list_empty(&iommu_pd_list))
+                return NULL;
+
+        spin_lock_irqsave(&iommu_pd_list_lock, flags);
+
+        list_for_each_entry(entry, &iommu_pd_list, list) {
+                if (entry->target_dev == devid) {
+                        ret = entry;
+                        list_del(&ret->list);
+                        break;
+                }
+        }
+
+        spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
+
+        return ret;
+}
+
+/*
  * In the dma_ops path we only have the struct device. This function
  * finds the corresponding IOMMU, the protection domain and the
  * requestor id for a given device.
@@ -661,27 +823,30 @@ static int get_device_resources(struct device *dev,
         struct pci_dev *pcidev;
         u16 _bdf;
 
-        BUG_ON(!dev || dev->bus != &pci_bus_type || !dev->dma_mask);
+        *iommu = NULL;
+        *domain = NULL;
+        *bdf = 0xffff;
+
+        if (dev->bus != &pci_bus_type)
+                return 0;
 
         pcidev = to_pci_dev(dev);
         _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
 
         /* device not translated by any IOMMU in the system? */
-        if (_bdf > amd_iommu_last_bdf) {
-                *iommu = NULL;
-                *domain = NULL;
-                *bdf = 0xffff;
+        if (_bdf > amd_iommu_last_bdf)
                 return 0;
-        }
 
         *bdf = amd_iommu_alias_table[_bdf];
 
         *iommu = amd_iommu_rlookup_table[*bdf];
         if (*iommu == NULL)
                 return 0;
-        dma_dom = (*iommu)->default_dom;
         *domain = domain_for_device(*bdf);
         if (*domain == NULL) {
+                dma_dom = find_protection_domain(*bdf);
+                if (!dma_dom)
+                        dma_dom = (*iommu)->default_dom;
                 *domain = &dma_dom->domain;
                 set_device_domain(*iommu, *domain, *bdf);
                 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
@@ -760,17 +925,24 @@ static dma_addr_t __map_single(struct device *dev,
                                struct dma_ops_domain *dma_dom,
                                phys_addr_t paddr,
                                size_t size,
-                               int dir)
+                               int dir,
+                               bool align,
+                               u64 dma_mask)
 {
         dma_addr_t offset = paddr & ~PAGE_MASK;
         dma_addr_t address, start;
         unsigned int pages;
+        unsigned long align_mask = 0;
         int i;
 
         pages = iommu_num_pages(paddr, size);
         paddr &= PAGE_MASK;
 
-        address = dma_ops_alloc_addresses(dev, dma_dom, pages);
+        if (align)
+                align_mask = (1UL << get_order(size)) - 1;
+
+        address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
+                                          dma_mask);
         if (unlikely(address == bad_dma_address))
                 goto out;
 
@@ -782,6 +954,12 @@ static dma_addr_t __map_single(struct device *dev,
         }
         address += offset;
 
+        if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
+                iommu_flush_tlb(iommu, dma_dom->domain.id);
+                dma_dom->need_flush = false;
+        } else if (unlikely(iommu_has_npcache(iommu)))
+                iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
+
 out:
         return address;
 }
@@ -812,6 +990,9 @@ static void __unmap_single(struct amd_iommu *iommu,
         }
 
         dma_ops_free_addresses(dma_dom, dma_addr, pages);
+
+        if (amd_iommu_unmap_flush)
+                iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
 }
 
 /*
@@ -825,6 +1006,12 @@ static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
         struct protection_domain *domain;
         u16 devid;
         dma_addr_t addr;
+        u64 dma_mask;
+
+        if (!check_device(dev))
+                return bad_dma_address;
+
+        dma_mask = *dev->dma_mask;
 
         get_device_resources(dev, &iommu, &domain, &devid);
 
@@ -833,14 +1020,12 @@ static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
                 return (dma_addr_t)paddr;
 
         spin_lock_irqsave(&domain->lock, flags);
-        addr = __map_single(dev, iommu, domain->priv, paddr, size, dir);
+        addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
+                            dma_mask);
         if (addr == bad_dma_address)
                 goto out;
 
-        if (iommu_has_npcache(iommu))
-                iommu_flush_pages(iommu, domain->id, addr, size);
-
-        if (iommu->need_sync)
+        if (unlikely(iommu->need_sync))
                 iommu_completion_wait(iommu);
 
 out:
@@ -860,7 +1045,8 @@ static void unmap_single(struct device *dev, dma_addr_t dma_addr,
         struct protection_domain *domain;
         u16 devid;
 
-        if (!get_device_resources(dev, &iommu, &domain, &devid))
+        if (!check_device(dev) ||
+            !get_device_resources(dev, &iommu, &domain, &devid))
                 /* device not handled by any AMD IOMMU */
                 return;
 
@@ -868,9 +1054,7 @@ static void unmap_single(struct device *dev, dma_addr_t dma_addr,
 
         __unmap_single(iommu, domain->priv, dma_addr, size, dir);
 
-        iommu_flush_pages(iommu, domain->id, dma_addr, size);
-
-        if (iommu->need_sync)
+        if (unlikely(iommu->need_sync))
                 iommu_completion_wait(iommu);
 
         spin_unlock_irqrestore(&domain->lock, flags);
@@ -909,6 +1093,12 @@ static int map_sg(struct device *dev, struct scatterlist *sglist,
         struct scatterlist *s;
         phys_addr_t paddr;
         int mapped_elems = 0;
+        u64 dma_mask;
+
+        if (!check_device(dev))
+                return 0;
+
+        dma_mask = *dev->dma_mask;
 
         get_device_resources(dev, &iommu, &domain, &devid);
 
@@ -921,19 +1111,17 @@ static int map_sg(struct device *dev, struct scatterlist *sglist,
                 paddr = sg_phys(s);
 
                 s->dma_address = __map_single(dev, iommu, domain->priv,
-                                              paddr, s->length, dir);
+                                              paddr, s->length, dir, false,
+                                              dma_mask);
 
                 if (s->dma_address) {
                         s->dma_length = s->length;
                         mapped_elems++;
                 } else
                         goto unmap;
-                if (iommu_has_npcache(iommu))
-                        iommu_flush_pages(iommu, domain->id, s->dma_address,
-                                          s->dma_length);
         }
 
-        if (iommu->need_sync)
+        if (unlikely(iommu->need_sync))
                 iommu_completion_wait(iommu);
 
 out:
@@ -967,7 +1155,8 @@ static void unmap_sg(struct device *dev, struct scatterlist *sglist,
         u16 devid;
         int i;
 
-        if (!get_device_resources(dev, &iommu, &domain, &devid))
+        if (!check_device(dev) ||
+            !get_device_resources(dev, &iommu, &domain, &devid))
                 return;
 
         spin_lock_irqsave(&domain->lock, flags);
@@ -975,12 +1164,10 @@ static void unmap_sg(struct device *dev, struct scatterlist *sglist,
         for_each_sg(sglist, s, nelems, i) {
                 __unmap_single(iommu, domain->priv, s->dma_address,
                                s->dma_length, dir);
-                iommu_flush_pages(iommu, domain->id, s->dma_address,
-                                  s->dma_length);
                 s->dma_address = s->dma_length = 0;
         }
 
-        if (iommu->need_sync)
+        if (unlikely(iommu->need_sync))
                 iommu_completion_wait(iommu);
 
         spin_unlock_irqrestore(&domain->lock, flags);
@@ -998,25 +1185,33 @@ static void *alloc_coherent(struct device *dev, size_t size,
         struct protection_domain *domain;
         u16 devid;
         phys_addr_t paddr;
+        u64 dma_mask = dev->coherent_dma_mask;
+
+        if (!check_device(dev))
+                return NULL;
 
+        if (!get_device_resources(dev, &iommu, &domain, &devid))
+                flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
+
+        flag |= __GFP_ZERO;
         virt_addr = (void *)__get_free_pages(flag, get_order(size));
         if (!virt_addr)
                 return 0;
 
-        memset(virt_addr, 0, size);
         paddr = virt_to_phys(virt_addr);
 
-        get_device_resources(dev, &iommu, &domain, &devid);
-
         if (!iommu || !domain) {
                 *dma_addr = (dma_addr_t)paddr;
                 return virt_addr;
         }
 
+        if (!dma_mask)
+                dma_mask = *dev->dma_mask;
+
         spin_lock_irqsave(&domain->lock, flags);
 
         *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
-                                 size, DMA_BIDIRECTIONAL);
+                                 size, DMA_BIDIRECTIONAL, true, dma_mask);
 
         if (*dma_addr == bad_dma_address) {
                 free_pages((unsigned long)virt_addr, get_order(size));
@@ -1024,10 +1219,7 @@ static void *alloc_coherent(struct device *dev, size_t size,
                 goto out;
         }
 
-        if (iommu_has_npcache(iommu))
-                iommu_flush_pages(iommu, domain->id, *dma_addr, size);
-
-        if (iommu->need_sync)
+        if (unlikely(iommu->need_sync))
                 iommu_completion_wait(iommu);
 
 out:
@@ -1038,8 +1230,6 @@ out:
 
 /*
  * The exported free_coherent function for dma_ops.
- * FIXME: fix the generic x86 DMA layer so that it actually calls that
- *        function.
  */
 static void free_coherent(struct device *dev, size_t size,
                           void *virt_addr, dma_addr_t dma_addr)
@@ -1049,6 +1239,9 @@ static void free_coherent(struct device *dev, size_t size,
         struct protection_domain *domain;
         u16 devid;
 
+        if (!check_device(dev))
+                return;
+
         get_device_resources(dev, &iommu, &domain, &devid);
 
         if (!iommu || !domain)
@@ -1057,9 +1250,8 @@ static void free_coherent(struct device *dev, size_t size,
         spin_lock_irqsave(&domain->lock, flags);
 
         __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
-        iommu_flush_pages(iommu, domain->id, dma_addr, size);
 
-        if (iommu->need_sync)
+        if (unlikely(iommu->need_sync))
                 iommu_completion_wait(iommu);
 
         spin_unlock_irqrestore(&domain->lock, flags);
@@ -1069,6 +1261,30 @@ free_mem:
 }
 
 /*
+ * This function is called by the DMA layer to find out if we can handle a
+ * particular device. It is part of the dma_ops.
+ */
+static int amd_iommu_dma_supported(struct device *dev, u64 mask)
+{
+        u16 bdf;
+        struct pci_dev *pcidev;
+
+        /* No device or no PCI device */
+        if (!dev || dev->bus != &pci_bus_type)
+                return 0;
+
+        pcidev = to_pci_dev(dev);
+
+        bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
+
+        /* Out of our scope? */
+        if (bdf > amd_iommu_last_bdf)
+                return 0;
+
+        return 1;
+}
+
+/*
  * The function for pre-allocating protection domains.
  *
  * If the driver core informs the DMA layer if a driver grabs a device
@@ -1097,10 +1313,9 @@ void prealloc_protection_domains(void)
                 if (!dma_dom)
                         continue;
                 init_unity_mappings_for_device(dma_dom, devid);
-                set_device_domain(iommu, &dma_dom->domain, devid);
-                printk(KERN_INFO "AMD IOMMU: Allocated domain %d for device ",
-                       dma_dom->domain.id);
-                print_devid(devid, 1);
+                dma_dom->target_dev = devid;
+
+                list_add_tail(&dma_dom->list, &iommu_pd_list);
         }
 }
 
@@ -1111,6 +1326,7 @@ static struct dma_mapping_ops amd_iommu_dma_ops = {
         .unmap_single = unmap_single,
         .map_sg = map_sg,
         .unmap_sg = unmap_sg,
+        .dma_supported = amd_iommu_dma_supported,
 };
 
 /*
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
index a69cc0f52042..148fcfe22f17 100644
--- a/arch/x86/kernel/amd_iommu_init.c
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -22,6 +22,8 @@
 #include <linux/gfp.h>
 #include <linux/list.h>
 #include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/msi.h>
 #include <asm/pci-direct.h>
 #include <asm/amd_iommu_types.h>
 #include <asm/amd_iommu.h>
@@ -30,7 +32,6 @@
 /*
  * definitions for the ACPI scanning code
  */
-#define PCI_BUS(x) (((x) >> 8) & 0xff)
 #define IVRS_HEADER_LENGTH 48
 
 #define ACPI_IVHD_TYPE                  0x10
@@ -121,6 +122,7 @@ LIST_HEAD(amd_iommu_unity_map);		/* a list of required unity mappings
                                            we find in ACPI */
 unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */
 int amd_iommu_isolate;                  /* if 1, device isolation is enabled */
+bool amd_iommu_unmap_flush;             /* if true, flush on every unmap */
 
 LIST_HEAD(amd_iommu_list);              /* list of all AMD IOMMUs in the
                                            system */
@@ -234,7 +236,7 @@ static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
 {
         u32 ctrl;
 
-        ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
+        ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
         ctrl &= ~(1 << bit);
         writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
 }
@@ -242,13 +244,23 @@ static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
 /* Function to enable the hardware */
 void __init iommu_enable(struct amd_iommu *iommu)
 {
-        printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
-        print_devid(iommu->devid, 0);
-        printk(" cap 0x%hx\n", iommu->cap_ptr);
+        printk(KERN_INFO "AMD IOMMU: Enabling IOMMU "
+               "at %02x:%02x.%x cap 0x%hx\n",
+               iommu->dev->bus->number,
+               PCI_SLOT(iommu->dev->devfn),
+               PCI_FUNC(iommu->dev->devfn),
+               iommu->cap_ptr);
 
         iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
 }
 
+/* Function to enable IOMMU event logging and event interrupts */
+void __init iommu_enable_event_logging(struct amd_iommu *iommu)
+{
+        iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
+        iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
+}
+
 /*
  * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
  * the system has one.
@@ -286,6 +298,14 @@ static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
  ****************************************************************************/
 
 /*
+ * This function calculates the length of a given IVHD entry
+ */
+static inline int ivhd_entry_length(u8 *ivhd)
+{
+        return 0x04 << (*ivhd >> 6);
+}
+
+/*
  * This function reads the last device id the IOMMU has to handle from the PCI
  * capability header for this IOMMU
  */
@@ -329,7 +349,7 @@ static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
                 default:
                         break;
                 }
-                p += 0x04 << (*p >> 6);
+                p += ivhd_entry_length(p);
         }
 
         WARN_ON(p != end);
@@ -414,7 +434,32 @@ static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
 
 static void __init free_command_buffer(struct amd_iommu *iommu)
 {
-        free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
+        free_pages((unsigned long)iommu->cmd_buf,
+                   get_order(iommu->cmd_buf_size));
+}
+
+/* allocates the memory where the IOMMU will log its events to */
+static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
+{
+        u64 entry;
+        iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
+                                                get_order(EVT_BUFFER_SIZE));
+
+        if (iommu->evt_buf == NULL)
+                return NULL;
+
+        entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
+        memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
+                    &entry, sizeof(entry));
+
+        iommu->evt_buf_size = EVT_BUFFER_SIZE;
+
+        return iommu->evt_buf;
+}
+
+static void __init free_event_buffer(struct amd_iommu *iommu)
+{
+        free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
 }
 
 /* sets a specific bit in the device table entry. */
@@ -487,19 +532,21 @@ static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
  */
 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
 {
-        int bus = PCI_BUS(iommu->devid);
-        int dev = PCI_SLOT(iommu->devid);
-        int fn  = PCI_FUNC(iommu->devid);
         int cap_ptr = iommu->cap_ptr;
-        u32 range;
+        u32 range, misc;
 
-        iommu->cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_CAP_HDR_OFFSET);
+        pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
+                              &iommu->cap);
+        pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
+                              &range);
+        pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
+                              &misc);
 
-        range = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
         iommu->first_device = calc_devid(MMIO_GET_BUS(range),
                                          MMIO_GET_FD(range));
         iommu->last_device = calc_devid(MMIO_GET_BUS(range),
                                         MMIO_GET_LD(range));
+        iommu->evt_msi_num = MMIO_MSI_NUM(misc);
 }
 
 /*
@@ -604,7 +651,7 @@ static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
                         break;
                 }
 
-                p += 0x04 << (e->type >> 6);
+                p += ivhd_entry_length(p);
         }
 }
 
@@ -622,6 +669,7 @@ static int __init init_iommu_devices(struct amd_iommu *iommu)
 static void __init free_iommu_one(struct amd_iommu *iommu)
 {
         free_command_buffer(iommu);
+        free_event_buffer(iommu);
         iommu_unmap_mmio_space(iommu);
 }
 
@@ -649,8 +697,12 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
         /*
          * Copy data from ACPI table entry to the iommu struct
          */
-        iommu->devid = h->devid;
+        iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
+        if (!iommu->dev)
+                return 1;
+
         iommu->cap_ptr = h->cap_ptr;
+        iommu->pci_seg = h->pci_seg;
         iommu->mmio_phys = h->mmio_phys;
         iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
         if (!iommu->mmio_base)
@@ -661,10 +713,18 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
         if (!iommu->cmd_buf)
                 return -ENOMEM;
 
+        iommu->evt_buf = alloc_event_buffer(iommu);
+        if (!iommu->evt_buf)
+                return -ENOMEM;
+
+        iommu->int_enabled = false;
+
         init_iommu_from_pci(iommu);
         init_iommu_from_acpi(iommu, h);
         init_iommu_devices(iommu);
 
+        pci_enable_device(iommu->dev);
+
         return 0;
 }
 
@@ -706,6 +766,95 @@ static int __init init_iommu_all(struct acpi_table_header *table)
 
 /****************************************************************************
  *
+ * The following functions initialize the MSI interrupts for all IOMMUs
+ * in the system. Its a bit challenging because there could be multiple
+ * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
+ * pci_dev.
+ *
+ ****************************************************************************/
+
+static int __init iommu_setup_msix(struct amd_iommu *iommu)
+{
+        struct amd_iommu *curr;
+        struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */
+        int nvec = 0, i;
+
+        list_for_each_entry(curr, &amd_iommu_list, list) {
+                if (curr->dev == iommu->dev) {
+                        entries[nvec].entry = curr->evt_msi_num;
+                        entries[nvec].vector = 0;
+                        curr->int_enabled = true;
+                        nvec++;
+                }
+        }
+
+        if (pci_enable_msix(iommu->dev, entries, nvec)) {
+                pci_disable_msix(iommu->dev);
+                return 1;
+        }
+
+        for (i = 0; i < nvec; ++i) {
+                int r = request_irq(entries->vector, amd_iommu_int_handler,
+                                    IRQF_SAMPLE_RANDOM,
+                                    "AMD IOMMU",
+                                    NULL);
+                if (r)
+                        goto out_free;
+        }
+
+        return 0;
+
+out_free:
+        for (i -= 1; i >= 0; --i)
+                free_irq(entries->vector, NULL);
+
+        pci_disable_msix(iommu->dev);
+
+        return 1;
+}
+
+static int __init iommu_setup_msi(struct amd_iommu *iommu)
+{
+        int r;
+        struct amd_iommu *curr;
+
+        list_for_each_entry(curr, &amd_iommu_list, list) {
+                if (curr->dev == iommu->dev)
+                        curr->int_enabled = true;
+        }
+
+
+        if (pci_enable_msi(iommu->dev))
+                return 1;
+
+        r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
+                        IRQF_SAMPLE_RANDOM,
+                        "AMD IOMMU",
+                        NULL);
+
+        if (r) {
+                pci_disable_msi(iommu->dev);
+                return 1;
+        }
+
+        return 0;
+}
+
+static int __init iommu_init_msi(struct amd_iommu *iommu)
+{
+        if (iommu->int_enabled)
+                return 0;
+
+        if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX))
+                return iommu_setup_msix(iommu);
+        else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
+                return iommu_setup_msi(iommu);
+
+        return 1;
+}
+
+/****************************************************************************
+ *
  * The next functions belong to the third pass of parsing the ACPI
  * table. In this last pass the memory mapping requirements are
  * gathered (like exclusion and unity mapping reanges).
@@ -811,7 +960,6 @@ static void init_device_table(void)
         for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
                 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
                 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
-                set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT);
         }
 }
 
@@ -825,6 +973,8 @@ static void __init enable_iommus(void)
 
         list_for_each_entry(iommu, &amd_iommu_list, list) {
                 iommu_set_exclusion_range(iommu);
+                iommu_init_msi(iommu);
+                iommu_enable_event_logging(iommu);
                 iommu_enable(iommu);
         }
 }
@@ -995,11 +1145,17 @@ int __init amd_iommu_init(void)
         else
                 printk("disabled\n");
 
+        if (amd_iommu_unmap_flush)
+                printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
+        else
+                printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
+
 out:
         return ret;
 
 free:
-        free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1);
+        free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
+                   get_order(MAX_DOMAIN_ID/8));
 
         free_pages((unsigned long)amd_iommu_pd_table,
                    get_order(rlookup_table_size));
@@ -1057,8 +1213,10 @@ void __init amd_iommu_detect(void)
 static int __init parse_amd_iommu_options(char *str)
 {
         for (; *str; ++str) {
-                if (strcmp(str, "isolate") == 0)
+                if (strncmp(str, "isolate", 7) == 0)
                         amd_iommu_isolate = 1;
+                if (strncmp(str, "fullflush", 11) == 0)
+                        amd_iommu_unmap_flush = true;
         }
 
         return 1;
diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index 44e21826db11..9a32b37ee2ee 100644
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -455,11 +455,11 @@ out:
                    force_iommu ||
                    valid_agp ||
                    fallback_aper_force) {
-                printk(KERN_ERR
+                printk(KERN_INFO
                         "Your BIOS doesn't leave a aperture memory hole\n");
-                printk(KERN_ERR
+                printk(KERN_INFO
                         "Please enable the IOMMU option in the BIOS setup\n");
-                printk(KERN_ERR
+                printk(KERN_INFO
                         "This costs you %d MB of RAM\n",
                                 32 << fallback_aper_order);
 
diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c
index f88bd0d982b0..a91c57cb666a 100644
--- a/arch/x86/kernel/apic_32.c
+++ b/arch/x86/kernel/apic_32.c
@@ -60,10 +60,8 @@ unsigned long mp_lapic_addr;
 static int force_enable_local_apic;
 int disable_apic;
 
-/* Local APIC timer verification ok */
-static int local_apic_timer_verify_ok;
 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
-static int local_apic_timer_disabled;
+static int disable_apic_timer __cpuinitdata;
 /* Local APIC timer works in C2 */
 int local_apic_timer_c2_ok;
 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
@@ -130,7 +128,11 @@ static inline int lapic_get_version(void)
  */
 static inline int lapic_is_integrated(void)
 {
+#ifdef CONFIG_X86_64
+        return 1;
+#else
         return APIC_INTEGRATED(lapic_get_version());
+#endif
 }
 
 /*
@@ -145,13 +147,18 @@ static int modern_apic(void)
         return lapic_get_version() >= 0x14;
 }
 
-void apic_wait_icr_idle(void)
+/*
+ * Paravirt kernels also might be using these below ops. So we still
+ * use generic apic_read()/apic_write(), which might be pointing to different
+ * ops in PARAVIRT case.
+ */
+void xapic_wait_icr_idle(void)
 {
         while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
                 cpu_relax();
 }
 
-u32 safe_apic_wait_icr_idle(void)
+u32 safe_xapic_wait_icr_idle(void)
 {
         u32 send_status;
         int timeout;
@@ -167,16 +174,48 @@ u32 safe_apic_wait_icr_idle(void)
         return send_status;
 }
 
+void xapic_icr_write(u32 low, u32 id)
+{
+        apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
+        apic_write(APIC_ICR, low);
+}
+
+u64 xapic_icr_read(void)
+{
+        u32 icr1, icr2;
+
+        icr2 = apic_read(APIC_ICR2);
+        icr1 = apic_read(APIC_ICR);
+
+        return icr1 | ((u64)icr2 << 32);
+}
+
+static struct apic_ops xapic_ops = {
+        .read = native_apic_mem_read,
+        .write = native_apic_mem_write,
+        .icr_read = xapic_icr_read,
+        .icr_write = xapic_icr_write,
+        .wait_icr_idle = xapic_wait_icr_idle,
+        .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
+};
+
+struct apic_ops __read_mostly *apic_ops = &xapic_ops;
+EXPORT_SYMBOL_GPL(apic_ops);
+
 /**
  * enable_NMI_through_LVT0 - enable NMI through local vector table 0
  */
 void __cpuinit enable_NMI_through_LVT0(void)
 {
-        unsigned int v = APIC_DM_NMI;
+        unsigned int v;
 
-        /* Level triggered for 82489DX */
+        /* unmask and set to NMI */
+        v = APIC_DM_NMI;
+
+        /* Level triggered for 82489DX (32bit mode) */
         if (!lapic_is_integrated())
                 v |= APIC_LVT_LEVEL_TRIGGER;
+
         apic_write(APIC_LVT0, v);
 }
 
@@ -193,9 +232,13 @@ int get_physical_broadcast(void)
  */
 int lapic_get_maxlvt(void)
 {
-        unsigned int v = apic_read(APIC_LVR);
+        unsigned int v;
 
-        /* 82489DXs do not report # of LVT entries. */
+        v = apic_read(APIC_LVR);
+        /*
+         * - we always have APIC integrated on 64bit mode
+         * - 82489DXs do not report # of LVT entries
+         */
         return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
 }
 
@@ -203,8 +246,12 @@ int lapic_get_maxlvt(void)
  * Local APIC timer
  */
 
-/* Clock divisor is set to 16 */
+/* Clock divisor */
+#ifdef CONFG_X86_64
+#define APIC_DIVISOR 1
+#else
 #define APIC_DIVISOR 16
+#endif
 
 /*
  * This function sets up the local APIC timer, with a timeout of
@@ -212,6 +259,9 @@ int lapic_get_maxlvt(void)
  * this function twice on the boot CPU, once with a bogus timeout
  * value, second time for real. The other (noncalibrating) CPUs
  * call this function only once, with the real, calibrated value.
+ *
+ * We do reads before writes even if unnecessary, to get around the
+ * P5 APIC double write bug.
  */
 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
 {
@@ -233,14 +283,44 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
          */
         tmp_value = apic_read(APIC_TDCR);
         apic_write(APIC_TDCR,
-                   (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
-                   APIC_TDR_DIV_16);
+                (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
+                APIC_TDR_DIV_16);
 
         if (!oneshot)
                 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
 }
 
 /*
+ * Setup extended LVT, AMD specific (K8, family 10h)
+ *
+ * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
+ * MCE interrupts are supported. Thus MCE offset must be set to 0.
+ */
+
+#define APIC_EILVT_LVTOFF_MCE 0
+#define APIC_EILVT_LVTOFF_IBS 1
+
+static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
+{
+        unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
+        unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;
+
+        apic_write(reg, v);
+}
+
+u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
+{
+        setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
+        return APIC_EILVT_LVTOFF_MCE;
+}
+
+u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
+{
+        setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
+        return APIC_EILVT_LVTOFF_IBS;
+}
+
+/*
  * Program the next event, relative to now
  */
 static int lapic_next_event(unsigned long delta,
@@ -259,8 +339,8 @@ static void lapic_timer_setup(enum clock_event_mode mode,
         unsigned long flags;
         unsigned int v;
 
-        /* Lapic used for broadcast ? */
-        if (!local_apic_timer_verify_ok)
+        /* Lapic used as dummy for broadcast ? */
+        if (evt->features & CLOCK_EVT_FEAT_DUMMY)
                 return;
 
         local_irq_save(flags);
@@ -473,7 +553,7 @@ static int __init calibrate_APIC_clock(void)
                 return -1;
         }
 
-        local_apic_timer_verify_ok = 1;
+        levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
 
         /* We trust the pm timer based calibration */
         if (!pm_referenced) {
@@ -507,11 +587,11 @@ static int __init calibrate_APIC_clock(void)
                 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
                         apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
                 else
-                        local_apic_timer_verify_ok = 0;
+                        levt->features |= CLOCK_EVT_FEAT_DUMMY;
         } else
                 local_irq_enable();
 
-        if (!local_apic_timer_verify_ok) {
+        if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
                 printk(KERN_WARNING
                        "APIC timer disabled due to verification failure.\n");
                         return -1;
@@ -533,7 +613,8 @@ void __init setup_boot_APIC_clock(void)
          * timer as a dummy clock event source on SMP systems, so the
          * broadcast mechanism is used. On UP systems simply ignore it.
          */
-        if (local_apic_timer_disabled) {
+        if (disable_apic_timer) {
+                printk(KERN_INFO "Disabling APIC timer\n");
                 /* No broadcast on UP ! */
                 if (num_possible_cpus() > 1) {
                         lapic_clockevent.mult = 1;
@@ -602,7 +683,11 @@ static void local_apic_timer_interrupt(void)
         /*
          * the NMI deadlock-detector uses this.
          */
+#ifdef CONFIG_X86_64
+        add_pda(apic_timer_irqs, 1);
+#else
         per_cpu(irq_stat, cpu).apic_timer_irqs++;
+#endif
 
         evt->event_handler(evt);
 }
@@ -642,35 +727,6 @@ int setup_profiling_timer(unsigned int multiplier)
 }
 
 /*
- * Setup extended LVT, AMD specific (K8, family 10h)
- *
- * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
- * MCE interrupts are supported. Thus MCE offset must be set to 0.
- */
-
-#define APIC_EILVT_LVTOFF_MCE 0
-#define APIC_EILVT_LVTOFF_IBS 1
-
-static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
-{
-        unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
-        unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;
-        apic_write(reg, v);
-}
-
-u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
-{
-        setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
-        return APIC_EILVT_LVTOFF_MCE;
-}
-
-u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
-{
-        setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
-        return APIC_EILVT_LVTOFF_IBS;
-}
-
-/*
  * Local APIC start and shutdown
  */
 
@@ -715,7 +771,7 @@ void clear_local_APIC(void)
         }
 
         /* lets not touch this if we didn't frob it */
-#ifdef CONFIG_X86_MCE_P4THERMAL
+#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
         if (maxlvt >= 5) {
                 v = apic_read(APIC_LVTTHMR);
                 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
@@ -732,10 +788,6 @@ void clear_local_APIC(void)
         if (maxlvt >= 4)
                 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
 
-#ifdef CONFIG_X86_MCE_P4THERMAL
-        if (maxlvt >= 5)
-                apic_write(APIC_LVTTHMR, APIC_LVT_MASKED);
-#endif
         /* Integrated APIC (!82489DX) ? */
         if (lapic_is_integrated()) {
                 if (maxlvt > 3)
@@ -750,7 +802,7 @@ void clear_local_APIC(void)
  */
 void disable_local_APIC(void)
 {
-        unsigned long value;
+        unsigned int value;
 
         clear_local_APIC();
 
@@ -762,6 +814,7 @@ void disable_local_APIC(void)
         value &= ~APIC_SPIV_APIC_ENABLED;
         apic_write(APIC_SPIV, value);
 
+#ifdef CONFIG_X86_32
         /*
          * When LAPIC was disabled by the BIOS and enabled by the kernel,
          * restore the disabled state.
@@ -773,6 +826,7 @@ void disable_local_APIC(void)
                 l &= ~MSR_IA32_APICBASE_ENABLE;
                 wrmsr(MSR_IA32_APICBASE, l, h);
         }
+#endif
 }
 
 /*
@@ -789,11 +843,15 @@ void lapic_shutdown(void)
                 return;
 
         local_irq_save(flags);
-        clear_local_APIC();
 
-        if (enabled_via_apicbase)
+#ifdef CONFIG_X86_32
+        if (!enabled_via_apicbase)
+                clear_local_APIC();
+        else
+#endif
                 disable_local_APIC();
 
+
         local_irq_restore(flags);
 }
 
@@ -838,6 +896,12 @@ int __init verify_local_APIC(void)
          */
         reg0 = apic_read(APIC_ID);
         apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
+        apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
+        reg1 = apic_read(APIC_ID);
+        apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
+        apic_write(APIC_ID, reg0);
+        if (reg1 != (reg0 ^ APIC_ID_MASK))
+                return 0;
 
         /*
          * The next two are just to see if we have sane values.
@@ -863,14 +927,15 @@ void __init sync_Arb_IDs(void)
          */
         if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
                 return;
+
         /*
          * Wait for idle.
          */
         apic_wait_icr_idle();
 
         apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
-        apic_write(APIC_ICR,
-                   APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);
+        apic_write(APIC_ICR, APIC_DEST_ALLINC |
+                        APIC_INT_LEVELTRIG | APIC_DM_INIT);
 }
 
 /*
@@ -878,7 +943,7 @@ void __init sync_Arb_IDs(void)
  */
 void __init init_bsp_APIC(void)
 {
-        unsigned long value;
+        unsigned int value;
 
         /*
          * Don't do the setup now if we have a SMP BIOS as the
@@ -899,11 +964,13 @@ void __init init_bsp_APIC(void)
         value &= ~APIC_VECTOR_MASK;
         value |= APIC_SPIV_APIC_ENABLED;
 
+#ifdef CONFIG_X86_32
         /* This bit is reserved on P4/Xeon and should be cleared */
         if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
             (boot_cpu_data.x86 == 15))
                 value &= ~APIC_SPIV_FOCUS_DISABLED;
         else
+#endif
                 value |= APIC_SPIV_FOCUS_DISABLED;
         value |= SPURIOUS_APIC_VECTOR;
         apic_write(APIC_SPIV, value);
@@ -922,6 +989,16 @@ static void __cpuinit lapic_setup_esr(void)
 {
         unsigned long oldvalue, value, maxlvt;
         if (lapic_is_integrated() && !esr_disable) {
+                if (esr_disable) {
+                        /*
+                         * Something untraceable is creating bad interrupts on
+                         * secondary quads ... for the moment, just leave the
+                         * ESR disabled - we can't do anything useful with the
+                         * errors anyway - mbligh
+                         */
+                        printk(KERN_INFO "Leaving ESR disabled.\n");
+                        return;
+                }
                 /* !82489DX */
                 maxlvt = lapic_get_maxlvt();
                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
@@ -942,16 +1019,7 @@ static void __cpuinit lapic_setup_esr(void)
                                 "vector: 0x%08lx  after: 0x%08lx\n",
                                 oldvalue, value);
         } else {
-                if (esr_disable)
-                        /*
-                         * Something untraceable is creating bad interrupts on
-                         * secondary quads ... for the moment, just leave the
-                         * ESR disabled - we can't do anything useful with the
-                         * errors anyway - mbligh
-                         */
-                        printk(KERN_INFO "Leaving ESR disabled.\n");
-                else
-                        printk(KERN_INFO "No ESR for 82489DX.\n");
+                printk(KERN_INFO "No ESR for 82489DX.\n");
         }
 }
 
@@ -1089,13 +1157,17 @@ void __cpuinit setup_local_APIC(void)
 
 void __cpuinit end_local_APIC_setup(void)
 {
-        unsigned long value;
-
         lapic_setup_esr();
-        /* Disable the local apic timer */
-        value = apic_read(APIC_LVTT);
-        value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
-        apic_write(APIC_LVTT, value);
+
+#ifdef CONFIG_X86_32
+        {
+                unsigned int value;
+                /* Disable the local apic timer */
+                value = apic_read(APIC_LVTT);
+                value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
+                apic_write(APIC_LVTT, value);
+        }
+#endif
 
         setup_apic_nmi_watchdog(NULL);
         apic_pm_activate();
@@ -1205,7 +1277,7 @@ void __init init_apic_mappings(void)
          * default configuration (or the MP table is broken).
          */
         if (boot_cpu_physical_apicid == -1U)
-                boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
+                boot_cpu_physical_apicid = read_apic_id();
 
 }
 
@@ -1242,7 +1314,7 @@ int __init APIC_init_uniprocessor(void)
          * might be zero if read from MP tables. Get it from LAPIC.
          */
 #ifdef CONFIG_CRASH_DUMP
-        boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
+        boot_cpu_physical_apicid = read_apic_id();
 #endif
         physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
 
@@ -1321,59 +1393,12 @@ void smp_error_interrupt(struct pt_regs *regs)
         irq_exit();
 }
 
-#ifdef CONFIG_SMP
-void __init smp_intr_init(void)
-{
-        /*
-         * IRQ0 must be given a fixed assignment and initialized,
-         * because it's used before the IO-APIC is set up.
-         */
-        set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
-
-        /*
-         * The reschedule interrupt is a CPU-to-CPU reschedule-helper
-         * IPI, driven by wakeup.
-         */
-        alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
-
-        /* IPI for invalidation */
-        alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
-
-        /* IPI for generic function call */
-        alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
-
-        /* IPI for single call function */
-        set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
-                                call_function_single_interrupt);
-}
-#endif
-
-/*
- * Initialize APIC interrupts
- */
-void __init apic_intr_init(void)
-{
-#ifdef CONFIG_SMP
-        smp_intr_init();
-#endif
-        /* self generated IPI for local APIC timer */
-        alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
-
-        /* IPI vectors for APIC spurious and error interrupts */
-        alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
-        alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
-
-        /* thermal monitor LVT interrupt */
-#ifdef CONFIG_X86_MCE_P4THERMAL
-        alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
-#endif
-}
-
 /**
  * connect_bsp_APIC - attach the APIC to the interrupt system
  */
 void __init connect_bsp_APIC(void)
 {
+#ifdef CONFIG_X86_32
         if (pic_mode) {
                 /*
                  * Do not trust the local APIC being empty at bootup.
@@ -1388,6 +1413,7 @@ void __init connect_bsp_APIC(void)
                 outb(0x70, 0x22);
                 outb(0x01, 0x23);
         }
+#endif
         enable_apic_mode();
 }
 
@@ -1400,6 +1426,9 @@ void __init connect_bsp_APIC(void)
  */
 void disconnect_bsp_APIC(int virt_wire_setup)
 {
+        unsigned int value;
+
+#ifdef CONFIG_X86_32
         if (pic_mode) {
                 /*
                  * Put the board back into PIC mode (has an effect only on
@@ -1411,54 +1440,53 @@ void disconnect_bsp_APIC(int virt_wire_setup)
                                 "entering PIC mode.\n");
                 outb(0x70, 0x22);
                 outb(0x00, 0x23);
-        } else {
-                /* Go back to Virtual Wire compatibility mode */
-                unsigned long value;
+                return;
+        }
+#endif
 
-                /* For the spurious interrupt use vector F, and enable it */
-                value = apic_read(APIC_SPIV);
-                value &= ~APIC_VECTOR_MASK;
-                value |= APIC_SPIV_APIC_ENABLED;
-                value |= 0xf;
-                apic_write(APIC_SPIV, value);
+        /* Go back to Virtual Wire compatibility mode */
 
-                if (!virt_wire_setup) {
-                        /*
-                         * For LVT0 make it edge triggered, active high,
-                         * external and enabled
-                         */
-                        value = apic_read(APIC_LVT0);
-                        value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
-                                APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
-                                APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
-                        value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
-                        value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
-                        apic_write(APIC_LVT0, value);
-                } else {
-                        /* Disable LVT0 */
-                        apic_write(APIC_LVT0, APIC_LVT_MASKED);
-                }
+        /* For the spurious interrupt use vector F, and enable it */
+        value = apic_read(APIC_SPIV);
+        value &= ~APIC_VECTOR_MASK;
+        value |= APIC_SPIV_APIC_ENABLED;
+        value |= 0xf;
+        apic_write(APIC_SPIV, value);
 
+        if (!virt_wire_setup) {
                 /*
-                 * For LVT1 make it edge triggered, active high, nmi and
-                 * enabled
+                 * For LVT0 make it edge triggered, active high,
+                 * external and enabled
                  */
-                value = apic_read(APIC_LVT1);
-                value &= ~(
-                        APIC_MODE_MASK | APIC_SEND_PENDING |
+                value = apic_read(APIC_LVT0);
+                value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
                         APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
                 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
-                value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
-                apic_write(APIC_LVT1, value);
+                value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
+                apic_write(APIC_LVT0, value);
+        } else {
+                /* Disable LVT0 */
+                apic_write(APIC_LVT0, APIC_LVT_MASKED);
         }
+
+        /*
+         * For LVT1 make it edge triggered, active high,
+         * nmi and enabled
+         */
+        value = apic_read(APIC_LVT1);
+        value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
+                        APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
+                        APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
+        value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
+        value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
+        apic_write(APIC_LVT1, value);
 }
 
 void __cpuinit generic_processor_info(int apicid, int version)
 {
         int cpu;
         cpumask_t tmp_map;
-        physid_mask_t phys_cpu;
 
         /*
          * Validate version
@@ -1471,9 +1499,6 @@ void __cpuinit generic_processor_info(int apicid, int version)
         }
         apic_version[apicid] = version;
 
-        phys_cpu = apicid_to_cpu_present(apicid);
-        physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
-
         if (num_processors >= NR_CPUS) {
                 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
                         "  Processor ignored.\n", NR_CPUS);
@@ -1484,17 +1509,19 @@ void __cpuinit generic_processor_info(int apicid, int version)
         cpus_complement(tmp_map, cpu_present_map);
         cpu = first_cpu(tmp_map);
 
-        if (apicid == boot_cpu_physical_apicid)
+        physid_set(apicid, phys_cpu_present_map);
+        if (apicid == boot_cpu_physical_apicid) {
                 /*
                  * x86_bios_cpu_apicid is required to have processors listed
                  * in same order as logical cpu numbers. Hence the first
                  * entry is BSP, and so on.
                  */
                 cpu = 0;
-
+        }
         if (apicid > max_physical_apicid)
                 max_physical_apicid = apicid;
 
+#ifdef CONFIG_X86_32
         /*
          * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
          * but we need to work other dependencies like SMP_SUSPEND etc
@@ -1514,7 +1541,9 @@ void __cpuinit generic_processor_info(int apicid, int version)
                         def_to_bigsmp = 1;
                 }
         }
-#ifdef CONFIG_SMP
+#endif
+
+#if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
         /* are we being called early in kernel startup? */
         if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
                 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
@@ -1527,6 +1556,7 @@ void __cpuinit generic_processor_info(int apicid, int version)
                 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
         }
 #endif
+
         cpu_set(cpu, cpu_possible_map);
         cpu_set(cpu, cpu_present_map);
 }
@@ -1537,6 +1567,11 @@ void __cpuinit generic_processor_info(int apicid, int version)
 #ifdef CONFIG_PM
 
 static struct {
+        /*
+         * 'active' is true if the local APIC was enabled by us and
+         * not the BIOS; this signifies that we are also responsible
+         * for disabling it before entering apm/acpi suspend
+         */
         int active;
         /* r/w apic fields */
         unsigned int apic_id;
@@ -1577,7 +1612,7 @@ static int lapic_suspend(struct sys_device *dev, pm_message_t state)
         apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
         apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
         apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
-#ifdef CONFIG_X86_MCE_P4THERMAL
+#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
         if (maxlvt >= 5)
                 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
 #endif
@@ -1601,16 +1636,23 @@ static int lapic_resume(struct sys_device *dev)
 
         local_irq_save(flags);
 
-        /*
-         * Make sure the APICBASE points to the right address
-         *
-         * FIXME! This will be wrong if we ever support suspend on
-         * SMP! We'll need to do this as part of the CPU restore!
-         */
-        rdmsr(MSR_IA32_APICBASE, l, h);
-        l &= ~MSR_IA32_APICBASE_BASE;
-        l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
-        wrmsr(MSR_IA32_APICBASE, l, h);
+#ifdef CONFIG_X86_64
+        if (x2apic)
+                enable_x2apic();
+        else
+#endif
+        {
+                /*
+                 * Make sure the APICBASE points to the right address
+                 *
+                 * FIXME! This will be wrong if we ever support suspend on
+                 * SMP! We'll need to do this as part of the CPU restore!
+                 */
+                rdmsr(MSR_IA32_APICBASE, l, h);
+                l &= ~MSR_IA32_APICBASE_BASE;
+                l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+                wrmsr(MSR_IA32_APICBASE, l, h);
+        }
 
         apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
         apic_write(APIC_ID, apic_pm_state.apic_id);
@@ -1620,7 +1662,7 @@ static int lapic_resume(struct sys_device *dev)
         apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
         apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
         apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
-#ifdef CONFIG_X86_MCE_P4THERMAL
+#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
         if (maxlvt >= 5)
                 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
 #endif
@@ -1634,7 +1676,9 @@ static int lapic_resume(struct sys_device *dev)
         apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
         apic_write(APIC_ESR, 0);
         apic_read(APIC_ESR);
+
         local_irq_restore(flags);
+
         return 0;
 }
 
@@ -1690,20 +1734,20 @@ static int __init parse_lapic(char *arg)
 }
 early_param("lapic", parse_lapic);
 
-static int __init parse_nolapic(char *arg)
+static int __init setup_disableapic(char *arg)
 {
         disable_apic = 1;
         setup_clear_cpu_cap(X86_FEATURE_APIC);
         return 0;
 }
-early_param("nolapic", parse_nolapic);
+early_param("disableapic", setup_disableapic);
 
-static int __init parse_disable_lapic_timer(char *arg)
+/* same as disableapic, for compatibility */
+static int __init setup_nolapic(char *arg)
 {
-        local_apic_timer_disabled = 1;
-        return 0;
+        return setup_disableapic(arg);
 }
-early_param("nolapic_timer", parse_disable_lapic_timer);
+early_param("nolapic", setup_nolapic);
 
 static int __init parse_lapic_timer_c2_ok(char *arg)
 {
@@ -1712,15 +1756,40 @@ static int __init parse_lapic_timer_c2_ok(char *arg)
 }
 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
 
+static int __init parse_disable_apic_timer(char *arg)
+{
+        disable_apic_timer = 1;
+        return 0;
+}
+early_param("noapictimer", parse_disable_apic_timer);
+
+static int __init parse_nolapic_timer(char *arg)
+{
+        disable_apic_timer = 1;
+        return 0;
+}
+early_param("nolapic_timer", parse_nolapic_timer);
+
 static int __init apic_set_verbosity(char *arg)
 {
-        if (!arg)
+        if (!arg)  {
+#ifdef CONFIG_X86_64
+                skip_ioapic_setup = 0;
+                ioapic_force = 1;
+                return 0;
+#endif
                 return -EINVAL;
+        }
 
-        if (strcmp(arg, "debug") == 0)
+        if (strcmp("debug", arg) == 0)
                 apic_verbosity = APIC_DEBUG;
-        else if (strcmp(arg, "verbose") == 0)
+        else if (strcmp("verbose", arg) == 0)
                 apic_verbosity = APIC_VERBOSE;
+        else {
+                printk(KERN_WARNING "APIC Verbosity level %s not recognised"
+                        " use apic=verbose or apic=debug\n", arg);
+                return -EINVAL;
+        }
 
         return 0;
 }
diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
index 446c062e831c..53898b65a6ae 100644
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic_64.c
@@ -27,6 +27,7 @@
 #include <linux/clockchips.h>
 #include <linux/acpi_pmtmr.h>
 #include <linux/module.h>
+#include <linux/dmar.h>
 
 #include <asm/atomic.h>
 #include <asm/smp.h>
@@ -39,13 +40,20 @@
 #include <asm/proto.h>
 #include <asm/timex.h>
 #include <asm/apic.h>
+#include <asm/i8259.h>
 
 #include <mach_ipi.h>
 #include <mach_apic.h>
 
+/* Disable local APIC timer from the kernel commandline or via dmi quirk */
 static int disable_apic_timer __cpuinitdata;
 static int apic_calibrate_pmtmr __initdata;
 int disable_apic;
+int disable_x2apic;
+int x2apic;
+
+/* x2apic enabled before OS handover */
+int x2apic_preenabled;
 
 /* Local APIC timer works in C2 */
 int local_apic_timer_c2_ok;
@@ -73,6 +81,9 @@ static void lapic_timer_setup(enum clock_event_mode mode,
 static void lapic_timer_broadcast(cpumask_t mask);
 static void apic_pm_activate(void);
 
+/*
+ * The local apic timer can be used for any function which is CPU local.
+ */
 static struct clock_event_device lapic_clockevent = {
         .name           = "lapic",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
@@ -99,11 +110,15 @@ static inline int lapic_get_version(void)
 }
 
 /*
- * Check, if the APIC is integrated or a seperate chip
+ * Check, if the APIC is integrated or a separate chip
  */
 static inline int lapic_is_integrated(void)
 {
+#ifdef CONFIG_X86_64
         return 1;
+#else
+        return APIC_INTEGRATED(lapic_get_version());
+#endif
 }
 
 /*
@@ -118,13 +133,18 @@ static int modern_apic(void)
         return lapic_get_version() >= 0x14;
 }
 
-void apic_wait_icr_idle(void)
+/*
+ * Paravirt kernels also might be using these below ops. So we still
+ * use generic apic_read()/apic_write(), which might be pointing to different
+ * ops in PARAVIRT case.
+ */
+void xapic_wait_icr_idle(void)
 {
         while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
                 cpu_relax();
 }
 
-u32 safe_apic_wait_icr_idle(void)
+u32 safe_xapic_wait_icr_idle(void)
 {
         u32 send_status;
         int timeout;
@@ -140,6 +160,68 @@ u32 safe_apic_wait_icr_idle(void)
         return send_status;
 }
 
+void xapic_icr_write(u32 low, u32 id)
+{
+        apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
+        apic_write(APIC_ICR, low);
+}
+
+u64 xapic_icr_read(void)
+{
+        u32 icr1, icr2;
+
+        icr2 = apic_read(APIC_ICR2);
+        icr1 = apic_read(APIC_ICR);
+
+        return icr1 | ((u64)icr2 << 32);
+}
+
+static struct apic_ops xapic_ops = {
+        .read = native_apic_mem_read,
+        .write = native_apic_mem_write,
+        .icr_read = xapic_icr_read,
+        .icr_write = xapic_icr_write,
+        .wait_icr_idle = xapic_wait_icr_idle,
+        .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
+};
+
+struct apic_ops __read_mostly *apic_ops = &xapic_ops;
+EXPORT_SYMBOL_GPL(apic_ops);
+
+static void x2apic_wait_icr_idle(void)
+{
+        /* no need to wait for icr idle in x2apic */
+        return;
+}
+
+static u32 safe_x2apic_wait_icr_idle(void)
+{
+        /* no need to wait for icr idle in x2apic */
+        return 0;
+}
+
+void x2apic_icr_write(u32 low, u32 id)
+{
+        wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
+}
+
+u64 x2apic_icr_read(void)
+{
+        unsigned long val;
+
+        rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
+        return val;
+}
+
+static struct apic_ops x2apic_ops = {
+        .read = native_apic_msr_read,
+        .write = native_apic_msr_write,
+        .icr_read = x2apic_icr_read,
+        .icr_write = x2apic_icr_write,
+        .wait_icr_idle = x2apic_wait_icr_idle,
+        .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
+};
+
 /**
  * enable_NMI_through_LVT0 - enable NMI through local vector table 0
  */
@@ -149,6 +231,11 @@ void __cpuinit enable_NMI_through_LVT0(void)
 
         /* unmask and set to NMI */
         v = APIC_DM_NMI;
+
+        /* Level triggered for 82489DX (32bit mode) */
+        if (!lapic_is_integrated())
+                v |= APIC_LVT_LEVEL_TRIGGER;
+
         apic_write(APIC_LVT0, v);
 }
 
@@ -157,14 +244,28 @@ void __cpuinit enable_NMI_through_LVT0(void)
  */
 int lapic_get_maxlvt(void)
 {
-        unsigned int v, maxlvt;
+        unsigned int v;
 
         v = apic_read(APIC_LVR);
-        maxlvt = GET_APIC_MAXLVT(v);
-        return maxlvt;
+        /*
+         * - we always have APIC integrated on 64bit mode
+         * - 82489DXs do not report # of LVT entries
+         */
+        return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
 }
 
 /*
+ * Local APIC timer
+ */
+
+/* Clock divisor */
+#ifdef CONFG_X86_64
+#define APIC_DIVISOR 1
+#else
+#define APIC_DIVISOR 16
+#endif
+
+/*
  * This function sets up the local APIC timer, with a timeout of
  * 'clocks' APIC bus clock. During calibration we actually call
  * this function twice on the boot CPU, once with a bogus timeout
@@ -174,7 +275,6 @@ int lapic_get_maxlvt(void)
  * We do reads before writes even if unnecessary, to get around the
  * P5 APIC double write bug.
  */
-
 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
 {
         unsigned int lvtt_value, tmp_value;
@@ -182,6 +282,9 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
         lvtt_value = LOCAL_TIMER_VECTOR;
         if (!oneshot)
                 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
+        if (!lapic_is_integrated())
+                lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
+
         if (!irqen)
                 lvtt_value |= APIC_LVT_MASKED;
 
@@ -191,12 +294,12 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
          * Divide PICLK by 16
          */
         tmp_value = apic_read(APIC_TDCR);
-        apic_write(APIC_TDCR, (tmp_value
-                                & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
-                                | APIC_TDR_DIV_16);
+        apic_write(APIC_TDCR,
+                (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
+                APIC_TDR_DIV_16);
 
         if (!oneshot)
-                apic_write(APIC_TMICT, clocks);
+                apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
 }
 
 /*
@@ -366,7 +469,7 @@ static int __init calibrate_APIC_clock(void)
         lapic_clockevent.min_delta_ns =
                 clockevent_delta2ns(0xF, &lapic_clockevent);
 
-        calibration_result = result / HZ;
+        calibration_result = (result * APIC_DIVISOR) / HZ;
 
         /*
          * Do a sanity check on the APIC calibration result
@@ -388,10 +491,10 @@ static int __init calibrate_APIC_clock(void)
 void __init setup_boot_APIC_clock(void)
 {
         /*
-         * The local apic timer can be disabled via the kernel commandline.
-         * Register the lapic timer as a dummy clock event source on SMP
-         * systems, so the broadcast mechanism is used. On UP systems simply
-         * ignore it.
+         * The local apic timer can be disabled via the kernel
+         * commandline or from the CPU detection code. Register the lapic
+         * timer as a dummy clock event source on SMP systems, so the
+         * broadcast mechanism is used. On UP systems simply ignore it.
          */
         if (disable_apic_timer) {
                 printk(KERN_INFO "Disabling APIC timer\n");
@@ -403,7 +506,9 @@ void __init setup_boot_APIC_clock(void)
                 return;
         }
 
-        printk(KERN_INFO "Using local APIC timer interrupts.\n");
+        apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
+                    "calibrating APIC timer ...\n");
+
         if (calibrate_APIC_clock()) {
                 /* No broadcast on UP ! */
                 if (num_possible_cpus() > 1)
@@ -422,6 +527,7 @@ void __init setup_boot_APIC_clock(void)
                 printk(KERN_WARNING "APIC timer registered as dummy,"
                         " due to nmi_watchdog=%d!\n", nmi_watchdog);
 
+        /* Setup the lapic or request the broadcast */
         setup_APIC_timer();
 }
 
@@ -460,7 +566,11 @@ static void local_apic_timer_interrupt(void)
         /*
          * the NMI deadlock-detector uses this.
          */
+#ifdef CONFIG_X86_64
         add_pda(apic_timer_irqs, 1);
+#else
+        per_cpu(irq_stat, cpu).apic_timer_irqs++;
+#endif
 
         evt->event_handler(evt);
 }
@@ -491,6 +601,7 @@ void smp_apic_timer_interrupt(struct pt_regs *regs)
         irq_enter();
         local_apic_timer_interrupt();
         irq_exit();
+
         set_irq_regs(old_regs);
 }
 
@@ -544,6 +655,13 @@ void clear_local_APIC(void)
                 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
         }
 
+        /* lets not touch this if we didn't frob it */
+#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
+        if (maxlvt >= 5) {
+                v = apic_read(APIC_LVTTHMR);
+                apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
+        }
+#endif
         /*
          * Clean APIC state for other OSs:
          */
@@ -554,8 +672,14 @@ void clear_local_APIC(void)
                 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
         if (maxlvt >= 4)
                 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
-        apic_write(APIC_ESR, 0);
-        apic_read(APIC_ESR);
+
+        /* Integrated APIC (!82489DX) ? */
+        if (lapic_is_integrated()) {
+                if (maxlvt > 3)
+                        /* Clear ESR due to Pentium errata 3AP and 11AP */
+                        apic_write(APIC_ESR, 0);
+                apic_read(APIC_ESR);
+        }
 }
 
 /**
@@ -574,8 +698,28 @@ void disable_local_APIC(void)
         value = apic_read(APIC_SPIV);
         value &= ~APIC_SPIV_APIC_ENABLED;
         apic_write(APIC_SPIV, value);
+
+#ifdef CONFIG_X86_32
+        /*
+         * When LAPIC was disabled by the BIOS and enabled by the kernel,
+         * restore the disabled state.
+         */
+        if (enabled_via_apicbase) {
+                unsigned int l, h;
+
+                rdmsr(MSR_IA32_APICBASE, l, h);
+                l &= ~MSR_IA32_APICBASE_ENABLE;
+                wrmsr(MSR_IA32_APICBASE, l, h);
+        }
+#endif
 }
 
+/*
+ * If Linux enabled the LAPIC against the BIOS default disable it down before
+ * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
+ * not power-off.  Additionally clear all LVT entries before disable_local_APIC
+ * for the case where Linux didn't enable the LAPIC.
+ */
 void lapic_shutdown(void)
 {
         unsigned long flags;
@@ -585,7 +729,13 @@ void lapic_shutdown(void)
 
         local_irq_save(flags);
 
-        disable_local_APIC();
+#ifdef CONFIG_X86_32
+        if (!enabled_via_apicbase)
+                clear_local_APIC();
+        else
+#endif
+                disable_local_APIC();
+
 
         local_irq_restore(flags);
 }
@@ -629,10 +779,10 @@ int __init verify_local_APIC(void)
         /*
          * The ID register is read/write in a real APIC.
          */
-        reg0 = read_apic_id();
+        reg0 = apic_read(APIC_ID);
         apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
         apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
-        reg1 = read_apic_id();
+        reg1 = apic_read(APIC_ID);
         apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
         apic_write(APIC_ID, reg0);
         if (reg1 != (reg0 ^ APIC_ID_MASK))
@@ -656,8 +806,11 @@ int __init verify_local_APIC(void)
  */
 void __init sync_Arb_IDs(void)
 {
-        /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
-        if (modern_apic())
+        /*
+         * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
+         * needed on AMD.
+         */
+        if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
                 return;
 
         /*
@@ -666,8 +819,8 @@ void __init sync_Arb_IDs(void)
         apic_wait_icr_idle();
 
         apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
-        apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
-                                | APIC_DM_INIT);
+        apic_write(APIC_ICR, APIC_DEST_ALLINC |
+                        APIC_INT_LEVELTRIG | APIC_DM_INIT);
 }
 
 /*
@@ -684,8 +837,6 @@ void __init init_bsp_APIC(void)
         if (smp_found_config || !cpu_has_apic)
                 return;
 
-        value = apic_read(APIC_LVR);
-
         /*
          * Do not trust the local APIC being empty at bootup.
          */
@@ -697,7 +848,15 @@ void __init init_bsp_APIC(void)
         value = apic_read(APIC_SPIV);
         value &= ~APIC_VECTOR_MASK;
         value |= APIC_SPIV_APIC_ENABLED;
-        value |= APIC_SPIV_FOCUS_DISABLED;
+
+#ifdef CONFIG_X86_32
+        /* This bit is reserved on P4/Xeon and should be cleared */
+        if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
+            (boot_cpu_data.x86 == 15))
+                value &= ~APIC_SPIV_FOCUS_DISABLED;
+        else
+#endif
+                value |= APIC_SPIV_FOCUS_DISABLED;
         value |= SPURIOUS_APIC_VECTOR;
         apic_write(APIC_SPIV, value);
 
@@ -706,9 +865,50 @@ void __init init_bsp_APIC(void)
          */
         apic_write(APIC_LVT0, APIC_DM_EXTINT);
         value = APIC_DM_NMI;
+        if (!lapic_is_integrated())             /* 82489DX */
+                value |= APIC_LVT_LEVEL_TRIGGER;
         apic_write(APIC_LVT1, value);
 }
 
+static void __cpuinit lapic_setup_esr(void)
+{
+        unsigned long oldvalue, value, maxlvt;
+        if (lapic_is_integrated() && !esr_disable) {
+                if (esr_disable) {
+                        /*
+                         * Something untraceable is creating bad interrupts on
+                         * secondary quads ... for the moment, just leave the
+                         * ESR disabled - we can't do anything useful with the
+                         * errors anyway - mbligh
+                         */
+                        printk(KERN_INFO "Leaving ESR disabled.\n");
+                        return;
+                }
+                /* !82489DX */
+                maxlvt = lapic_get_maxlvt();
+                if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
+                        apic_write(APIC_ESR, 0);
+                oldvalue = apic_read(APIC_ESR);
+
+                /* enables sending errors */
+                value = ERROR_APIC_VECTOR;
+                apic_write(APIC_LVTERR, value);
+                /*
+                 * spec says clear errors after enabling vector.
+                 */
+                if (maxlvt > 3)
+                        apic_write(APIC_ESR, 0);
+                value = apic_read(APIC_ESR);
+                if (value != oldvalue)
+                        apic_printk(APIC_VERBOSE, "ESR value before enabling "
+                                "vector: 0x%08lx  after: 0x%08lx\n",
+                                oldvalue, value);
+        } else {
+                printk(KERN_INFO "No ESR for 82489DX.\n");
+        }
+}
+
+
 /**
  * setup_local_APIC - setup the local APIC
  */
@@ -814,25 +1014,143 @@ void __cpuinit setup_local_APIC(void)
         preempt_enable();
 }
 
-static void __cpuinit lapic_setup_esr(void)
-{
-        unsigned maxlvt = lapic_get_maxlvt();
-
-        apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
-        /*
-         * spec says clear errors after enabling vector.
-         */
-        if (maxlvt > 3)
-                apic_write(APIC_ESR, 0);
-}
-
 void __cpuinit end_local_APIC_setup(void)
 {
         lapic_setup_esr();
+
+#ifdef CONFIG_X86_32
+        {
+                unsigned int value;
+                /* Disable the local apic timer */
+                value = apic_read(APIC_LVTT);
+                value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
+                apic_write(APIC_LVTT, value);
+        }
+#endif
+
         setup_apic_nmi_watchdog(NULL);
         apic_pm_activate();
 }
 
+void check_x2apic(void)
+{
+        int msr, msr2;
+
+        rdmsr(MSR_IA32_APICBASE, msr, msr2);
+
+        if (msr & X2APIC_ENABLE) {
+                printk("x2apic enabled by BIOS, switching to x2apic ops\n");
+                x2apic_preenabled = x2apic = 1;
+                apic_ops = &x2apic_ops;
+        }
+}
+
+void enable_x2apic(void)
+{
+        int msr, msr2;
+
+        rdmsr(MSR_IA32_APICBASE, msr, msr2);
+        if (!(msr & X2APIC_ENABLE)) {
+                printk("Enabling x2apic\n");
+                wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
+        }
+}
+
+void enable_IR_x2apic(void)
+{
+#ifdef CONFIG_INTR_REMAP
+        int ret;
+        unsigned long flags;
+
+        if (!cpu_has_x2apic)
+                return;
+
+        if (!x2apic_preenabled && disable_x2apic) {
+                printk(KERN_INFO
+                       "Skipped enabling x2apic and Interrupt-remapping "
+                       "because of nox2apic\n");
+                return;
+        }
+
+        if (x2apic_preenabled && disable_x2apic)
+                panic("Bios already enabled x2apic, can't enforce nox2apic");
+
+        if (!x2apic_preenabled && skip_ioapic_setup) {
+                printk(KERN_INFO
+                       "Skipped enabling x2apic and Interrupt-remapping "
+                       "because of skipping io-apic setup\n");
+                return;
+        }
+
+        ret = dmar_table_init();
+        if (ret) {
+                printk(KERN_INFO
+                       "dmar_table_init() failed with %d:\n", ret);
+
+                if (x2apic_preenabled)
+                        panic("x2apic enabled by bios. But IR enabling failed");
+                else
+                        printk(KERN_INFO
+                               "Not enabling x2apic,Intr-remapping\n");
+                return;
+        }
+
+        local_irq_save(flags);
+        mask_8259A();
+        save_mask_IO_APIC_setup();
+
+        ret = enable_intr_remapping(1);
+
+        if (ret && x2apic_preenabled) {
+                local_irq_restore(flags);
+                panic("x2apic enabled by bios. But IR enabling failed");
+        }
+
+        if (ret)
+                goto end;
+
+        if (!x2apic) {
+                x2apic = 1;
+                apic_ops = &x2apic_ops;
+                enable_x2apic();
+        }
+end:
+        if (ret)
+                /*
+                 * IR enabling failed
+                 */
+                restore_IO_APIC_setup();
+        else
+                reinit_intr_remapped_IO_APIC(x2apic_preenabled);
+
+        unmask_8259A();
+        local_irq_restore(flags);
+
+        if (!ret) {
+                if (!x2apic_preenabled)
+                        printk(KERN_INFO
+                               "Enabled x2apic and interrupt-remapping\n");
+                else
+                        printk(KERN_INFO
+                               "Enabled Interrupt-remapping\n");
+        } else
+                printk(KERN_ERR
+                       "Failed to enable Interrupt-remapping and x2apic\n");
+#else
+        if (!cpu_has_x2apic)
+                return;
+
+        if (x2apic_preenabled)
+                panic("x2apic enabled prior OS handover,"
+                      " enable CONFIG_INTR_REMAP");
+
+        printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
+               " and x2apic\n");
+#endif
+
+        return;
+}
+
 /*
  * Detect and enable local APICs on non-SMP boards.
  * Original code written by Keir Fraser.
@@ -872,7 +1190,7 @@ void __init early_init_lapic_mapping(void)
          * Fetch the APIC ID of the BSP in case we have a
          * default configuration (or the MP table is broken).
          */
-        boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
+        boot_cpu_physical_apicid = read_apic_id();
 }
 
 /**
@@ -880,6 +1198,11 @@ void __init early_init_lapic_mapping(void)
  */
 void __init init_apic_mappings(void)
 {
+        if (x2apic) {
+                boot_cpu_physical_apicid = read_apic_id();
+                return;
+        }
+
         /*
          * If no local APIC can be found then set up a fake all
          * zeroes page to simulate the local APIC and another
@@ -899,13 +1222,15 @@ void __init init_apic_mappings(void)
          * Fetch the APIC ID of the BSP in case we have a
          * default configuration (or the MP table is broken).
          */
-        boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
+        boot_cpu_physical_apicid = read_apic_id();
 }
 
 /*
  * This initializes the IO-APIC and APIC hardware if this is
  * a UP kernel.
  */
+int apic_version[MAX_APICS];
+
 int __init APIC_init_uniprocessor(void)
 {
         if (disable_apic) {
@@ -918,6 +1243,9 @@ int __init APIC_init_uniprocessor(void)
                 return -1;
         }
 
+        enable_IR_x2apic();
+        setup_apic_routing();
+
         verify_local_APIC();
 
         connect_bsp_APIC();
@@ -1004,17 +1332,57 @@ asmlinkage void smp_error_interrupt(void)
 }
 
 /**
- *  * connect_bsp_APIC - attach the APIC to the interrupt system
- *   */
+ * connect_bsp_APIC - attach the APIC to the interrupt system
+ */
 void __init connect_bsp_APIC(void)
 {
+#ifdef CONFIG_X86_32
+        if (pic_mode) {
+                /*
+                 * Do not trust the local APIC being empty at bootup.
+                 */
+                clear_local_APIC();
+                /*
+                 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
+                 * local APIC to INT and NMI lines.
+                 */
+                apic_printk(APIC_VERBOSE, "leaving PIC mode, "
+                                "enabling APIC mode.\n");
+                outb(0x70, 0x22);
+                outb(0x01, 0x23);
+        }
+#endif
         enable_apic_mode();
 }
 
+/**
+ * disconnect_bsp_APIC - detach the APIC from the interrupt system
+ * @virt_wire_setup:    indicates, whether virtual wire mode is selected
+ *
+ * Virtual wire mode is necessary to deliver legacy interrupts even when the
+ * APIC is disabled.
+ */
 void disconnect_bsp_APIC(int virt_wire_setup)
 {
+        unsigned int value;
+
+#ifdef CONFIG_X86_32
+        if (pic_mode) {
+                /*
+                 * Put the board back into PIC mode (has an effect only on
+                 * certain older boards).  Note that APIC interrupts, including
+                 * IPIs, won't work beyond this point!  The only exception are
+                 * INIT IPIs.
+                 */
+                apic_printk(APIC_VERBOSE, "disabling APIC mode, "
+                                "entering PIC mode.\n");
+                outb(0x70, 0x22);
+                outb(0x00, 0x23);
+                return;
+        }
+#endif
+
         /* Go back to Virtual Wire compatibility mode */
-        unsigned long value;
 
         /* For the spurious interrupt use vector F, and enable it */
         value = apic_read(APIC_SPIV);
@@ -1040,7 +1408,10 @@ void disconnect_bsp_APIC(int virt_wire_setup)
                 apic_write(APIC_LVT0, APIC_LVT_MASKED);
         }
 
-        /* For LVT1 make it edge triggered, active high, nmi and enabled */
+        /*
+         * For LVT1 make it edge triggered, active high,
+         * nmi and enabled
+         */
         value = apic_read(APIC_LVT1);
         value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
@@ -1055,9 +1426,20 @@ void __cpuinit generic_processor_info(int apicid, int version)
         int cpu;
         cpumask_t tmp_map;
 
+        /*
+         * Validate version
+         */
+        if (version == 0x0) {
+                printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
+                                "fixing up to 0x10. (tell your hw vendor)\n",
+                                version);
+                version = 0x10;
+        }
+        apic_version[apicid] = version;
+
         if (num_processors >= NR_CPUS) {
                 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
-                       " Processor ignored.\n", NR_CPUS);
+                        "  Processor ignored.\n", NR_CPUS);
                 return;
         }
 
@@ -1077,6 +1459,29 @@ void __cpuinit generic_processor_info(int apicid, int version)
         if (apicid > max_physical_apicid)
                 max_physical_apicid = apicid;
 
+#ifdef CONFIG_X86_32
+        /*
+         * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
+         * but we need to work other dependencies like SMP_SUSPEND etc
+         * before this can be done without some confusion.
+         * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
+         *       - Ashok Raj <ashok.raj@intel.com>
+         */
+        if (max_physical_apicid >= 8) {
+                switch (boot_cpu_data.x86_vendor) {
+                case X86_VENDOR_INTEL:
+                        if (!APIC_XAPIC(version)) {
+                                def_to_bigsmp = 0;
+                                break;
+                        }
+                        /* If P4 and above fall through */
+                case X86_VENDOR_AMD:
+                        def_to_bigsmp = 1;
+                }
+        }
+#endif
+
+#if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
         /* are we being called early in kernel startup? */
         if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
                 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
@@ -1088,20 +1493,28 @@ void __cpuinit generic_processor_info(int apicid, int version)
                 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
                 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
         }
+#endif
 
         cpu_set(cpu, cpu_possible_map);
         cpu_set(cpu, cpu_present_map);
 }
 
+int hard_smp_processor_id(void)
+{
+        return read_apic_id();
+}
+
 /*
  * Power management
  */
 #ifdef CONFIG_PM
 
 static struct {
-        /* 'active' is true if the local APIC was enabled by us and
-           not the BIOS; this signifies that we are also responsible
-           for disabling it before entering apm/acpi suspend */
+        /*
+         * 'active' is true if the local APIC was enabled by us and
+         * not the BIOS; this signifies that we are also responsible
+         * for disabling it before entering apm/acpi suspend
+         */
         int active;
         /* r/w apic fields */
         unsigned int apic_id;
@@ -1129,7 +1542,7 @@ static int lapic_suspend(struct sys_device *dev, pm_message_t state)
 
         maxlvt = lapic_get_maxlvt();
 
-        apic_pm_state.apic_id = read_apic_id();
+        apic_pm_state.apic_id = apic_read(APIC_ID);
         apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
         apic_pm_state.apic_ldr = apic_read(APIC_LDR);
         apic_pm_state.apic_dfr = apic_read(APIC_DFR);
@@ -1142,10 +1555,11 @@ static int lapic_suspend(struct sys_device *dev, pm_message_t state)
         apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
         apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
         apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
-#ifdef CONFIG_X86_MCE_INTEL
+#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
         if (maxlvt >= 5)
                 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
 #endif
+
         local_irq_save(flags);
         disable_local_APIC();
         local_irq_restore(flags);
@@ -1164,10 +1578,25 @@ static int lapic_resume(struct sys_device *dev)
         maxlvt = lapic_get_maxlvt();
 
         local_irq_save(flags);
-        rdmsr(MSR_IA32_APICBASE, l, h);
-        l &= ~MSR_IA32_APICBASE_BASE;
-        l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
-        wrmsr(MSR_IA32_APICBASE, l, h);
+
+#ifdef CONFIG_X86_64
+        if (x2apic)
+                enable_x2apic();
+        else
+#endif
+        {
+                /*
+                 * Make sure the APICBASE points to the right address
+                 *
+                 * FIXME! This will be wrong if we ever support suspend on
+                 * SMP! We'll need to do this as part of the CPU restore!
+                 */
+                rdmsr(MSR_IA32_APICBASE, l, h);
+                l &= ~MSR_IA32_APICBASE_BASE;
+                l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+                wrmsr(MSR_IA32_APICBASE, l, h);
+        }
+
         apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
         apic_write(APIC_ID, apic_pm_state.apic_id);
         apic_write(APIC_DFR, apic_pm_state.apic_dfr);
@@ -1176,7 +1605,7 @@ static int lapic_resume(struct sys_device *dev)
         apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
         apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
         apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
-#ifdef CONFIG_X86_MCE_INTEL
+#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
         if (maxlvt >= 5)
                 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
 #endif
@@ -1190,10 +1619,17 @@ static int lapic_resume(struct sys_device *dev)
         apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
         apic_write(APIC_ESR, 0);
         apic_read(APIC_ESR);
+
         local_irq_restore(flags);
+
         return 0;
 }
 
+/*
+ * This device has no shutdown method - fully functioning local APICs
+ * are needed on every CPU up until machine_halt/restart/poweroff.
+ */
+
 static struct sysdev_class lapic_sysclass = {
         .name           = "lapic",
         .resume         = lapic_resume,
@@ -1307,31 +1743,19 @@ __cpuinit int apic_is_clustered_box(void)
         return (clusters > 2);
 }
 
-/*
- * APIC command line parameters
- */
-static int __init apic_set_verbosity(char *str)
+static __init int setup_nox2apic(char *str)
 {
-        if (str == NULL)  {
-                skip_ioapic_setup = 0;
-                ioapic_force = 1;
-                return 0;
-        }
-        if (strcmp("debug", str) == 0)
-                apic_verbosity = APIC_DEBUG;
-        else if (strcmp("verbose", str) == 0)
-                apic_verbosity = APIC_VERBOSE;
-        else {
-                printk(KERN_WARNING "APIC Verbosity level %s not recognised"
-                                " use apic=verbose or apic=debug\n", str);
-                return -EINVAL;
-        }
-
+        disable_x2apic = 1;
+        clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
         return 0;
 }
-early_param("apic", apic_set_verbosity);
+early_param("nox2apic", setup_nox2apic);
+
 
-static __init int setup_disableapic(char *str)
+/*
+ * APIC command line parameters
+ */
+static int __init setup_disableapic(char *arg)
 {
         disable_apic = 1;
         setup_clear_cpu_cap(X86_FEATURE_APIC);
@@ -1340,9 +1764,9 @@ static __init int setup_disableapic(char *str)
 early_param("disableapic", setup_disableapic);
 
 /* same as disableapic, for compatibility */
-static __init int setup_nolapic(char *str)
+static int __init setup_nolapic(char *arg)
 {
-        return setup_disableapic(str);
+        return setup_disableapic(arg);
 }
 early_param("nolapic", setup_nolapic);
 
@@ -1353,14 +1777,19 @@ static int __init parse_lapic_timer_c2_ok(char *arg)
 }
 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
 
-static __init int setup_noapictimer(char *str)
+static int __init parse_disable_apic_timer(char *arg)
 {
-        if (str[0] != ' ' && str[0] != 0)
-                return 0;
         disable_apic_timer = 1;
-        return 1;
+        return 0;
 }
-__setup("noapictimer", setup_noapictimer);
+early_param("noapictimer", parse_disable_apic_timer);
+
+static int __init parse_nolapic_timer(char *arg)
+{
+        disable_apic_timer = 1;
+        return 0;
+}
+early_param("nolapic_timer", parse_nolapic_timer);
 
 static __init int setup_apicpmtimer(char *s)
 {
@@ -1370,6 +1799,31 @@ static __init int setup_apicpmtimer(char *s)
 }
 __setup("apicpmtimer", setup_apicpmtimer);
 
+static int __init apic_set_verbosity(char *arg)
+{
+        if (!arg)  {
+#ifdef CONFIG_X86_64
+                skip_ioapic_setup = 0;
+                ioapic_force = 1;
+                return 0;
+#endif
+                return -EINVAL;
+        }
+
+        if (strcmp("debug", arg) == 0)
+                apic_verbosity = APIC_DEBUG;
+        else if (strcmp("verbose", arg) == 0)
+                apic_verbosity = APIC_VERBOSE;
+        else {
+                printk(KERN_WARNING "APIC Verbosity level %s not recognised"
+                        " use apic=verbose or apic=debug\n", arg);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+early_param("apic", apic_set_verbosity);
+
 static int __init lapic_insert_resource(void)
 {
         if (!apic_phys)
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 9ee24e6bc4b0..5145a6e72bbb 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -228,12 +228,12 @@
 #include <linux/suspend.h>
 #include <linux/kthread.h>
 #include <linux/jiffies.h>
-#include <linux/smp_lock.h>
 
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/desc.h>
 #include <asm/i8253.h>
+#include <asm/olpc.h>
 #include <asm/paravirt.h>
 #include <asm/reboot.h>
 
@@ -2217,7 +2217,7 @@ static int __init apm_init(void)
 
         dmi_check_system(apm_dmi_table);
 
-        if (apm_info.bios.version == 0 || paravirt_enabled()) {
+        if (apm_info.bios.version == 0 || paravirt_enabled() || machine_is_olpc()) {
                 printk(KERN_INFO "apm: BIOS not found.\n");
                 return -ENODEV;
         }
diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c
index aa89387006fe..505543a75a56 100644
--- a/arch/x86/kernel/asm-offsets_64.c
+++ b/arch/x86/kernel/asm-offsets_64.c
@@ -22,7 +22,7 @@
 
 #define __NO_STUBS 1
 #undef __SYSCALL
-#undef _ASM_X86_64_UNISTD_H_
+#undef ASM_X86__UNISTD_64_H
 #define __SYSCALL(nr, sym) [nr] = 1,
 static char syscalls[] = {
 #include <asm/unistd.h>
diff --git a/arch/x86/kernel/bios_uv.c b/arch/x86/kernel/bios_uv.c
index c639bd55391c..fdd585f9c53d 100644
--- a/arch/x86/kernel/bios_uv.c
+++ b/arch/x86/kernel/bios_uv.c
@@ -25,11 +25,11 @@ x86_bios_strerror(long status)
 {
         const char *str;
         switch (status) {
-        case  0: str = "Call completed without error"; break;
-        case -1: str = "Not implemented"; break;
-        case -2: str = "Invalid argument"; break;
-        case -3: str = "Call completed with error"; break;
-        default: str = "Unknown BIOS status code"; break;
+        case  0: str = "Call completed without error";  break;
+        case -1: str = "Not implemented";               break;
+        case -2: str = "Invalid argument";              break;
+        case -3: str = "Call completed with error";     break;
+        default: str = "Unknown BIOS status code";      break;
         }
         return str;
 }
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index ee76eaad3001..7f0b45a5d788 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -3,22 +3,30 @@
 #
 
 obj-y                   := intel_cacheinfo.o addon_cpuid_features.o
-obj-y                   += proc.o feature_names.o
-
-obj-$(CONFIG_X86_32)    += common.o bugs.o
-obj-$(CONFIG_X86_64)    += common_64.o bugs_64.o
-obj-$(CONFIG_X86_32)    += amd.o
-obj-$(CONFIG_X86_64)    += amd_64.o
-obj-$(CONFIG_X86_32)    += cyrix.o
-obj-$(CONFIG_X86_32)    += centaur.o
-obj-$(CONFIG_X86_64)    += centaur_64.o
-obj-$(CONFIG_X86_32)    += transmeta.o
-obj-$(CONFIG_X86_32)    += intel.o
-obj-$(CONFIG_X86_64)    += intel_64.o
-obj-$(CONFIG_X86_32)    += umc.o
+obj-y                   += proc.o capflags.o powerflags.o common.o
+
+obj-$(CONFIG_X86_32)    += bugs.o cmpxchg.o
+obj-$(CONFIG_X86_64)    += bugs_64.o
+
+obj-$(CONFIG_CPU_SUP_INTEL)             += intel.o
+obj-$(CONFIG_CPU_SUP_AMD)               += amd.o
+obj-$(CONFIG_CPU_SUP_CYRIX_32)          += cyrix.o
+obj-$(CONFIG_CPU_SUP_CENTAUR_32)        += centaur.o
+obj-$(CONFIG_CPU_SUP_CENTAUR_64)        += centaur_64.o
+obj-$(CONFIG_CPU_SUP_TRANSMETA_32)      += transmeta.o
+obj-$(CONFIG_CPU_SUP_UMC_32)            += umc.o
 
 obj-$(CONFIG_X86_MCE)   += mcheck/
 obj-$(CONFIG_MTRR)      += mtrr/
 obj-$(CONFIG_CPU_FREQ)  += cpufreq/
 
 obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o
+
+quiet_cmd_mkcapflags = MKCAP   $@
+      cmd_mkcapflags = $(PERL) $(srctree)/$(src)/mkcapflags.pl $< $@
+
+cpufeature = $(src)/../../../../include/asm-x86/cpufeature.h
+
+targets += capflags.c
+$(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.pl FORCE
+        $(call if_changed,mkcapflags)
diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index a6ef672adbba..0d9c993aa93e 100644
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -7,6 +7,8 @@
 #include <asm/pat.h>
 #include <asm/processor.h>
 
+#include <mach_apic.h>
+
 struct cpuid_bit {
         u16 feature;
         u8 reg;
@@ -48,6 +50,92 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
         }
 }
 
+/* leaf 0xb SMT level */
+#define SMT_LEVEL       0
+
+/* leaf 0xb sub-leaf types */
+#define INVALID_TYPE    0
+#define SMT_TYPE        1
+#define CORE_TYPE       2
+
+#define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
+#define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
+#define LEVEL_MAX_SIBLINGS(ebx)         ((ebx) & 0xffff)
+
+/*
+ * Check for extended topology enumeration cpuid leaf 0xb and if it
+ * exists, use it for populating initial_apicid and cpu topology
+ * detection.
+ */
+void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_SMP
+        unsigned int eax, ebx, ecx, edx, sub_index;
+        unsigned int ht_mask_width, core_plus_mask_width;
+        unsigned int core_select_mask, core_level_siblings;
+
+        if (c->cpuid_level < 0xb)
+                return;
+
+        cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
+
+        /*
+         * check if the cpuid leaf 0xb is actually implemented.
+         */
+        if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE))
+                return;
+
+        set_cpu_cap(c, X86_FEATURE_XTOPOLOGY);
+
+        /*
+         * initial apic id, which also represents 32-bit extended x2apic id.
+         */
+        c->initial_apicid = edx;
+
+        /*
+         * Populate HT related information from sub-leaf level 0.
+         */
+        core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx);
+        core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
+
+        sub_index = 1;
+        do {
+                cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
+
+                /*
+                 * Check for the Core type in the implemented sub leaves.
+                 */
+                if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
+                        core_level_siblings = LEVEL_MAX_SIBLINGS(ebx);
+                        core_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
+                        break;
+                }
+
+                sub_index++;
+        } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
+
+        core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width;
+
+#ifdef CONFIG_X86_32
+        c->cpu_core_id = phys_pkg_id(c->initial_apicid, ht_mask_width)
+                                                 & core_select_mask;
+        c->phys_proc_id = phys_pkg_id(c->initial_apicid, core_plus_mask_width);
+#else
+        c->cpu_core_id = phys_pkg_id(ht_mask_width) & core_select_mask;
+        c->phys_proc_id = phys_pkg_id(core_plus_mask_width);
+#endif
+        c->x86_max_cores = (core_level_siblings / smp_num_siblings);
+
+
+        printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
+               c->phys_proc_id);
+        if (c->x86_max_cores > 1)
+                printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
+                       c->cpu_core_id);
+        return;
+#endif
+}
+
 #ifdef CONFIG_X86_PAT
 void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
 {
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 18514ed26104..32e73520adf7 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1,13 +1,22 @@
 #include <linux/init.h>
 #include <linux/bitops.h>
 #include <linux/mm.h>
+
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/apic.h>
 
+#ifdef CONFIG_X86_64
+# include <asm/numa_64.h>
+# include <asm/mmconfig.h>
+# include <asm/cacheflush.h>
+#endif
+
 #include <mach_apic.h>
+
 #include "cpu.h"
 
+#ifdef CONFIG_X86_32
 /*
  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  *      misexecution of code under Linux. Owners of such processors should
@@ -24,26 +33,273 @@
 extern void vide(void);
 __asm__(".align 4\nvide: ret");
 
-static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
+static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
 {
-        if (cpuid_eax(0x80000000) >= 0x80000007) {
-                c->x86_power = cpuid_edx(0x80000007);
-                if (c->x86_power & (1<<8))
-                        set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+/*
+ * General Systems BIOSen alias the cpu frequency registers
+ * of the Elan at 0x000df000. Unfortuantly, one of the Linux
+ * drivers subsequently pokes it, and changes the CPU speed.
+ * Workaround : Remove the unneeded alias.
+ */
+#define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
+#define CBAR_ENB        (0x80000000)
+#define CBAR_KEY        (0X000000CB)
+        if (c->x86_model == 9 || c->x86_model == 10) {
+                if (inl (CBAR) & CBAR_ENB)
+                        outl (0 | CBAR_KEY, CBAR);
         }
-
-        /*  Set MTRR capability flag if appropriate */
-        if (c->x86_model == 13 || c->x86_model == 9 ||
-           (c->x86_model == 8 && c->x86_mask >= 8))
-                set_cpu_cap(c, X86_FEATURE_K6_MTRR);
 }
 
-static void __cpuinit init_amd(struct cpuinfo_x86 *c)
+
+static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
 {
         u32 l, h;
         int mbytes = num_physpages >> (20-PAGE_SHIFT);
-        int r;
 
+        if (c->x86_model < 6) {
+                /* Based on AMD doc 20734R - June 2000 */
+                if (c->x86_model == 0) {
+                        clear_cpu_cap(c, X86_FEATURE_APIC);
+                        set_cpu_cap(c, X86_FEATURE_PGE);
+                }
+                return;
+        }
+
+        if (c->x86_model == 6 && c->x86_mask == 1) {
+                const int K6_BUG_LOOP = 1000000;
+                int n;
+                void (*f_vide)(void);
+                unsigned long d, d2;
+
+                printk(KERN_INFO "AMD K6 stepping B detected - ");
+
+                /*
+                 * It looks like AMD fixed the 2.6.2 bug and improved indirect
+                 * calls at the same time.
+                 */
+
+                n = K6_BUG_LOOP;
+                f_vide = vide;
+                rdtscl(d);
+                while (n--)
+                        f_vide();
+                rdtscl(d2);
+                d = d2-d;
+
+                if (d > 20*K6_BUG_LOOP)
+                        printk("system stability may be impaired when more than 32 MB are used.\n");
+                else
+                        printk("probably OK (after B9730xxxx).\n");
+                printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
+        }
+
+        /* K6 with old style WHCR */
+        if (c->x86_model < 8 ||
+           (c->x86_model == 8 && c->x86_mask < 8)) {
+                /* We can only write allocate on the low 508Mb */
+                if (mbytes > 508)
+                        mbytes = 508;
+
+                rdmsr(MSR_K6_WHCR, l, h);
+                if ((l&0x0000FFFF) == 0) {
+                        unsigned long flags;
+                        l = (1<<0)|((mbytes/4)<<1);
+                        local_irq_save(flags);
+                        wbinvd();
+                        wrmsr(MSR_K6_WHCR, l, h);
+                        local_irq_restore(flags);
+                        printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
+                                mbytes);
+                }
+                return;
+        }
+
+        if ((c->x86_model == 8 && c->x86_mask > 7) ||
+             c->x86_model == 9 || c->x86_model == 13) {
+                /* The more serious chips .. */
+
+                if (mbytes > 4092)
+                        mbytes = 4092;
+
+                rdmsr(MSR_K6_WHCR, l, h);
+                if ((l&0xFFFF0000) == 0) {
+                        unsigned long flags;
+                        l = ((mbytes>>2)<<22)|(1<<16);
+                        local_irq_save(flags);
+                        wbinvd();
+                        wrmsr(MSR_K6_WHCR, l, h);
+                        local_irq_restore(flags);
+                        printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
+                                mbytes);
+                }
+
+                return;
+        }
+
+        if (c->x86_model == 10) {
+                /* AMD Geode LX is model 10 */
+                /* placeholder for any needed mods */
+                return;
+        }
+}
+
+static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
+{
+        u32 l, h;
+
+        /*
+         * Bit 15 of Athlon specific MSR 15, needs to be 0
+         * to enable SSE on Palomino/Morgan/Barton CPU's.
+         * If the BIOS didn't enable it already, enable it here.
+         */
+        if (c->x86_model >= 6 && c->x86_model <= 10) {
+                if (!cpu_has(c, X86_FEATURE_XMM)) {
+                        printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
+                        rdmsr(MSR_K7_HWCR, l, h);
+                        l &= ~0x00008000;
+                        wrmsr(MSR_K7_HWCR, l, h);
+                        set_cpu_cap(c, X86_FEATURE_XMM);
+                }
+        }
+
+        /*
+         * It's been determined by AMD that Athlons since model 8 stepping 1
+         * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
+         * As per AMD technical note 27212 0.2
+         */
+        if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
+                rdmsr(MSR_K7_CLK_CTL, l, h);
+                if ((l & 0xfff00000) != 0x20000000) {
+                        printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
+                                ((l & 0x000fffff)|0x20000000));
+                        wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
+                }
+        }
+
+        set_cpu_cap(c, X86_FEATURE_K7);
+}
+#endif
+
+#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
+static int __cpuinit nearby_node(int apicid)
+{
+        int i, node;
+
+        for (i = apicid - 1; i >= 0; i--) {
+                node = apicid_to_node[i];
+                if (node != NUMA_NO_NODE && node_online(node))
+                        return node;
+        }
+        for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
+                node = apicid_to_node[i];
+                if (node != NUMA_NO_NODE && node_online(node))
+                        return node;
+        }
+        return first_node(node_online_map); /* Shouldn't happen */
+}
+#endif
+
+/*
+ * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
+ * Assumes number of cores is a power of two.
+ */
+static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_X86_HT
+        unsigned bits;
+
+        bits = c->x86_coreid_bits;
+
+        /* Low order bits define the core id (index of core in socket) */
+        c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
+        /* Convert the initial APIC ID into the socket ID */
+        c->phys_proc_id = c->initial_apicid >> bits;
+#endif
+}
+
+static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
+{
+#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
+        int cpu = smp_processor_id();
+        int node;
+        unsigned apicid = hard_smp_processor_id();
+
+        node = c->phys_proc_id;
+        if (apicid_to_node[apicid] != NUMA_NO_NODE)
+                node = apicid_to_node[apicid];
+        if (!node_online(node)) {
+                /* Two possibilities here:
+                   - The CPU is missing memory and no node was created.
+                   In that case try picking one from a nearby CPU
+                   - The APIC IDs differ from the HyperTransport node IDs
+                   which the K8 northbridge parsing fills in.
+                   Assume they are all increased by a constant offset,
+                   but in the same order as the HT nodeids.
+                   If that doesn't result in a usable node fall back to the
+                   path for the previous case.  */
+
+                int ht_nodeid = c->initial_apicid;
+
+                if (ht_nodeid >= 0 &&
+                    apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
+                        node = apicid_to_node[ht_nodeid];
+                /* Pick a nearby node */
+                if (!node_online(node))
+                        node = nearby_node(apicid);
+        }
+        numa_set_node(cpu, node);
+
+        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
+#endif
+}
+
+static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_X86_HT
+        unsigned bits, ecx;
+
+        /* Multi core CPU? */
+        if (c->extended_cpuid_level < 0x80000008)
+                return;
+
+        ecx = cpuid_ecx(0x80000008);
+
+        c->x86_max_cores = (ecx & 0xff) + 1;
+
+        /* CPU telling us the core id bits shift? */
+        bits = (ecx >> 12) & 0xF;
+
+        /* Otherwise recompute */
+        if (bits == 0) {
+                while ((1 << bits) < c->x86_max_cores)
+                        bits++;
+        }
+
+        c->x86_coreid_bits = bits;
+#endif
+}
+
+static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
+{
+        early_init_amd_mc(c);
+
+        /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
+        if (c->x86_power & (1<<8))
+                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+
+#ifdef CONFIG_X86_64
+        set_cpu_cap(c, X86_FEATURE_SYSCALL32);
+#else
+        /*  Set MTRR capability flag if appropriate */
+        if (c->x86 == 5)
+                if (c->x86_model == 13 || c->x86_model == 9 ||
+                    (c->x86_model == 8 && c->x86_mask >= 8))
+                        set_cpu_cap(c, X86_FEATURE_K6_MTRR);
+#endif
+}
+
+static void __cpuinit init_amd(struct cpuinfo_x86 *c)
+{
 #ifdef CONFIG_SMP
         unsigned long long value;
 
@@ -54,7 +310,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
          * Errata 63 for SH-B3 steppings
          * Errata 122 for all steppings (F+ have it disabled by default)
          */
-        if (c->x86 == 15) {
+        if (c->x86 == 0xf) {
                 rdmsrl(MSR_K7_HWCR, value);
                 value |= 1 << 6;
                 wrmsrl(MSR_K7_HWCR, value);
@@ -64,209 +320,119 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         early_init_amd(c);
 
         /*
-         *      FIXME: We should handle the K5 here. Set up the write
-         *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
-         *      no bus pipeline)
-         */
-
-        /*
          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
          */
         clear_cpu_cap(c, 0*32+31);
 
-        r = get_model_name(c);
+#ifdef CONFIG_X86_64
+        /* On C+ stepping K8 rep microcode works well for copy/memset */
+        if (c->x86 == 0xf) {
+                u32 level;
 
-        switch (c->x86) {
-        case 4:
-                /*
-                 * General Systems BIOSen alias the cpu frequency registers
-                 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
-                 * drivers subsequently pokes it, and changes the CPU speed.
-                 * Workaround : Remove the unneeded alias.
-                 */
-#define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
-#define CBAR_ENB        (0x80000000)
-#define CBAR_KEY        (0X000000CB)
-                        if (c->x86_model == 9 || c->x86_model == 10) {
-                                if (inl (CBAR) & CBAR_ENB)
-                                        outl (0 | CBAR_KEY, CBAR);
-                        }
-                        break;
-        case 5:
-                        if (c->x86_model < 6) {
-                                /* Based on AMD doc 20734R - June 2000 */
-                                if (c->x86_model == 0) {
-                                        clear_cpu_cap(c, X86_FEATURE_APIC);
-                                        set_cpu_cap(c, X86_FEATURE_PGE);
-                                }
-                                break;
-                        }
-
-                        if (c->x86_model == 6 && c->x86_mask == 1) {
-                                const int K6_BUG_LOOP = 1000000;
-                                int n;
-                                void (*f_vide)(void);
-                                unsigned long d, d2;
-
-                                printk(KERN_INFO "AMD K6 stepping B detected - ");
-
-                                /*
-                                 * It looks like AMD fixed the 2.6.2 bug and improved indirect
-                                 * calls at the same time.
-                                 */
-
-                                n = K6_BUG_LOOP;
-                                f_vide = vide;
-                                rdtscl(d);
-                                while (n--)
-                                        f_vide();
-                                rdtscl(d2);
-                                d = d2-d;
-
-                                if (d > 20*K6_BUG_LOOP)
-                                        printk("system stability may be impaired when more than 32 MB are used.\n");
-                                else
-                                        printk("probably OK (after B9730xxxx).\n");
-                                printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
-                        }
-
-                        /* K6 with old style WHCR */
-                        if (c->x86_model < 8 ||
-                           (c->x86_model == 8 && c->x86_mask < 8)) {
-                                /* We can only write allocate on the low 508Mb */
-                                if (mbytes > 508)
-                                        mbytes = 508;
-
-                                rdmsr(MSR_K6_WHCR, l, h);
-                                if ((l&0x0000FFFF) == 0) {
-                                        unsigned long flags;
-                                        l = (1<<0)|((mbytes/4)<<1);
-                                        local_irq_save(flags);
-                                        wbinvd();
-                                        wrmsr(MSR_K6_WHCR, l, h);
-                                        local_irq_restore(flags);
-                                        printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
-                                                mbytes);
-                                }
-                                break;
-                        }
-
-                        if ((c->x86_model == 8 && c->x86_mask > 7) ||
-                             c->x86_model == 9 || c->x86_model == 13) {
-                                /* The more serious chips .. */
-
-                                if (mbytes > 4092)
-                                        mbytes = 4092;
-
-                                rdmsr(MSR_K6_WHCR, l, h);
-                                if ((l&0xFFFF0000) == 0) {
-                                        unsigned long flags;
-                                        l = ((mbytes>>2)<<22)|(1<<16);
-                                        local_irq_save(flags);
-                                        wbinvd();
-                                        wrmsr(MSR_K6_WHCR, l, h);
-                                        local_irq_restore(flags);
-                                        printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
-                                                mbytes);
-                                }
-
-                                break;
-                        }
-
-                        if (c->x86_model == 10) {
-                                /* AMD Geode LX is model 10 */
-                                /* placeholder for any needed mods */
-                                break;
-                        }
-                        break;
-        case 6: /* An Athlon/Duron */
-
-                        /*
-                         * Bit 15 of Athlon specific MSR 15, needs to be 0
-                         * to enable SSE on Palomino/Morgan/Barton CPU's.
-                         * If the BIOS didn't enable it already, enable it here.
-                         */
-                        if (c->x86_model >= 6 && c->x86_model <= 10) {
-                                if (!cpu_has(c, X86_FEATURE_XMM)) {
-                                        printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
-                                        rdmsr(MSR_K7_HWCR, l, h);
-                                        l &= ~0x00008000;
-                                        wrmsr(MSR_K7_HWCR, l, h);
-                                        set_cpu_cap(c, X86_FEATURE_XMM);
-                                }
-                        }
-
-                        /*
-                         * It's been determined by AMD that Athlons since model 8 stepping 1
-                         * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
-                         * As per AMD technical note 27212 0.2
-                         */
-                        if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
-                                rdmsr(MSR_K7_CLK_CTL, l, h);
-                                if ((l & 0xfff00000) != 0x20000000) {
-                                        printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
-                                                ((l & 0x000fffff)|0x20000000));
-                                        wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
-                                }
-                        }
-                        break;
+                level = cpuid_eax(1);
+                if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
+                        set_cpu_cap(c, X86_FEATURE_REP_GOOD);
         }
+        if (c->x86 == 0x10 || c->x86 == 0x11)
+                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+#else
+
+        /*
+         *      FIXME: We should handle the K5 here. Set up the write
+         *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
+         *      no bus pipeline)
+         */
 
         switch (c->x86) {
-        case 15:
-        /* Use K8 tuning for Fam10h and Fam11h */
-        case 0x10:
-        case 0x11:
-                set_cpu_cap(c, X86_FEATURE_K8);
+        case 4:
+                init_amd_k5(c);
                 break;
-        case 6:
-                set_cpu_cap(c, X86_FEATURE_K7);
+        case 5:
+                init_amd_k6(c);
+                break;
+        case 6: /* An Athlon/Duron */
+                init_amd_k7(c);
                 break;
         }
+
+        /* K6s reports MCEs but don't actually have all the MSRs */
+        if (c->x86 < 6)
+                clear_cpu_cap(c, X86_FEATURE_MCE);
+#endif
+
+        /* Enable workaround for FXSAVE leak */
         if (c->x86 >= 6)
                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 
-        display_cacheinfo(c);
-
-        if (cpuid_eax(0x80000000) >= 0x80000008)
-                c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
+        if (!c->x86_model_id[0]) {
+                switch (c->x86) {
+                case 0xf:
+                        /* Should distinguish Models here, but this is only
+                           a fallback anyways. */
+                        strcpy(c->x86_model_id, "Hammer");
+                        break;
+                }
+        }
 
-#ifdef CONFIG_X86_HT
-        /*
-         * On a AMD multi core setup the lower bits of the APIC id
-         * distinguish the cores.
-         */
-        if (c->x86_max_cores > 1) {
-                int cpu = smp_processor_id();
-                unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
+        display_cacheinfo(c);
 
-                if (bits == 0) {
-                        while ((1 << bits) < c->x86_max_cores)
-                                bits++;
-                }
-                c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
-                c->phys_proc_id >>= bits;
-                printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
-                       cpu, c->x86_max_cores, c->cpu_core_id);
+        /* Multi core CPU? */
+        if (c->extended_cpuid_level >= 0x80000008) {
+                amd_detect_cmp(c);
+                srat_detect_node(c);
         }
+
+#ifdef CONFIG_X86_32
+        detect_ht(c);
 #endif
 
-        if (cpuid_eax(0x80000000) >= 0x80000006) {
-                if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
+        if (c->extended_cpuid_level >= 0x80000006) {
+                if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
                         num_cache_leaves = 4;
                 else
                         num_cache_leaves = 3;
         }
 
-        /* K6s reports MCEs but don't actually have all the MSRs */
-        if (c->x86 < 6)
-                clear_cpu_cap(c, X86_FEATURE_MCE);
+        if (c->x86 >= 0xf && c->x86 <= 0x11)
+                set_cpu_cap(c, X86_FEATURE_K8);
 
-        if (cpu_has_xmm2)
+        if (cpu_has_xmm2) {
+                /* MFENCE stops RDTSC speculation */
                 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
+        }
+
+#ifdef CONFIG_X86_64
+        if (c->x86 == 0x10) {
+                /* do this for boot cpu */
+                if (c == &boot_cpu_data)
+                        check_enable_amd_mmconf_dmi();
+
+                fam10h_check_enable_mmcfg();
+        }
+
+        if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
+                unsigned long long tseg;
+
+                /*
+                 * Split up direct mapping around the TSEG SMM area.
+                 * Don't do it for gbpages because there seems very little
+                 * benefit in doing so.
+                 */
+                if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
+                    printk(KERN_DEBUG "tseg: %010llx\n", tseg);
+                    if ((tseg>>PMD_SHIFT) <
+                                (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
+                        ((tseg>>PMD_SHIFT) <
+                                (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
+                         (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
+                        set_memory_4k((unsigned long)__va(tseg), 1);
+                }
+        }
+#endif
 }
 
+#ifdef CONFIG_X86_32
 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 {
         /* AMD errata T13 (order #21922) */
@@ -279,10 +445,12 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int
         }
         return size;
 }
+#endif
 
 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
         .c_vendor       = "AMD",
         .c_ident        = { "AuthenticAMD" },
+#ifdef CONFIG_X86_32
         .c_models = {
                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
                   {
@@ -295,9 +463,11 @@ static struct cpu_dev amd_cpu_dev __cpuinitdata = {
                   }
                 },
         },
+        .c_size_cache   = amd_size_cache,
+#endif
         .c_early_init   = early_init_amd,
         .c_init         = init_amd,
-        .c_size_cache   = amd_size_cache,
+        .c_x86_vendor   = X86_VENDOR_AMD,
 };
 
-cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);
+cpu_dev_register(amd_cpu_dev);
diff --git a/arch/x86/kernel/cpu/amd_64.c b/arch/x86/kernel/cpu/amd_64.c
deleted file mode 100644
index d1692b2a41ff..000000000000
--- a/arch/x86/kernel/cpu/amd_64.c
+++ /dev/null
@@ -1,224 +0,0 @@
-#include <linux/init.h>
-#include <linux/mm.h>
-
-#include <asm/numa_64.h>
-#include <asm/mmconfig.h>
-#include <asm/cacheflush.h>
-
-#include <mach_apic.h>
-
-#include "cpu.h"
-
-int force_mwait __cpuinitdata;
-
-#ifdef CONFIG_NUMA
-static int __cpuinit nearby_node(int apicid)
-{
-        int i, node;
-
-        for (i = apicid - 1; i >= 0; i--) {
-                node = apicid_to_node[i];
-                if (node != NUMA_NO_NODE && node_online(node))
-                        return node;
-        }
-        for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
-                node = apicid_to_node[i];
-                if (node != NUMA_NO_NODE && node_online(node))
-                        return node;
-        }
-        return first_node(node_online_map); /* Shouldn't happen */
-}
-#endif
-
-/*
- * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
- * Assumes number of cores is a power of two.
- */
-static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
-{
-#ifdef CONFIG_SMP
-        unsigned bits;
-#ifdef CONFIG_NUMA
-        int cpu = smp_processor_id();
-        int node = 0;
-        unsigned apicid = hard_smp_processor_id();
-#endif
-        bits = c->x86_coreid_bits;
-
-        /* Low order bits define the core id (index of core in socket) */
-        c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
-        /* Convert the initial APIC ID into the socket ID */
-        c->phys_proc_id = c->initial_apicid >> bits;
-
-#ifdef CONFIG_NUMA
-        node = c->phys_proc_id;
-        if (apicid_to_node[apicid] != NUMA_NO_NODE)
-                node = apicid_to_node[apicid];
-        if (!node_online(node)) {
-                /* Two possibilities here:
-                   - The CPU is missing memory and no node was created.
-                   In that case try picking one from a nearby CPU
-                   - The APIC IDs differ from the HyperTransport node IDs
-                   which the K8 northbridge parsing fills in.
-                   Assume they are all increased by a constant offset,
-                   but in the same order as the HT nodeids.
-                   If that doesn't result in a usable node fall back to the
-                   path for the previous case.  */
-
-                int ht_nodeid = c->initial_apicid;
-
-                if (ht_nodeid >= 0 &&
-                    apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
-                        node = apicid_to_node[ht_nodeid];
-                /* Pick a nearby node */
-                if (!node_online(node))
-                        node = nearby_node(apicid);
-        }
-        numa_set_node(cpu, node);
-
-        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
-#endif
-#endif
-}
-
-static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
-{
-#ifdef CONFIG_SMP
-        unsigned bits, ecx;
-
-        /* Multi core CPU? */
-        if (c->extended_cpuid_level < 0x80000008)
-                return;
-
-        ecx = cpuid_ecx(0x80000008);
-
-        c->x86_max_cores = (ecx & 0xff) + 1;
-
-        /* CPU telling us the core id bits shift? */
-        bits = (ecx >> 12) & 0xF;
-
-        /* Otherwise recompute */
-        if (bits == 0) {
-                while ((1 << bits) < c->x86_max_cores)
-                        bits++;
-        }
-
-        c->x86_coreid_bits = bits;
-
-#endif
-}
-
-static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
-{
-        early_init_amd_mc(c);
-
-        /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
-        if (c->x86_power & (1<<8))
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-
-        set_cpu_cap(c, X86_FEATURE_SYSCALL32);
-}
-
-static void __cpuinit init_amd(struct cpuinfo_x86 *c)
-{
-        unsigned level;
-
-#ifdef CONFIG_SMP
-        unsigned long value;
-
-        /*
-         * Disable TLB flush filter by setting HWCR.FFDIS on K8
-         * bit 6 of msr C001_0015
-         *
-         * Errata 63 for SH-B3 steppings
-         * Errata 122 for all steppings (F+ have it disabled by default)
-         */
-        if (c->x86 == 0xf) {
-                rdmsrl(MSR_K8_HWCR, value);
-                value |= 1 << 6;
-                wrmsrl(MSR_K8_HWCR, value);
-        }
-#endif
-
-        /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
-           3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
-        clear_cpu_cap(c, 0*32+31);
-
-        /* On C+ stepping K8 rep microcode works well for copy/memset */
-        if (c->x86 == 0xf) {
-                level = cpuid_eax(1);
-                if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
-                        set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-        }
-        if (c->x86 == 0x10 || c->x86 == 0x11)
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-
-        /* Enable workaround for FXSAVE leak */
-        if (c->x86 >= 6)
-                set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
-
-        level = get_model_name(c);
-        if (!level) {
-                switch (c->x86) {
-                case 0xf:
-                        /* Should distinguish Models here, but this is only
-                           a fallback anyways. */
-                        strcpy(c->x86_model_id, "Hammer");
-                        break;
-                }
-        }
-        display_cacheinfo(c);
-
-        /* Multi core CPU? */
-        if (c->extended_cpuid_level >= 0x80000008)
-                amd_detect_cmp(c);
-
-        if (c->extended_cpuid_level >= 0x80000006 &&
-                (cpuid_edx(0x80000006) & 0xf000))
-                num_cache_leaves = 4;
-        else
-                num_cache_leaves = 3;
-
-        if (c->x86 >= 0xf && c->x86 <= 0x11)
-                set_cpu_cap(c, X86_FEATURE_K8);
-
-        /* MFENCE stops RDTSC speculation */
-        set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
-
-        if (c->x86 == 0x10) {
-                /* do this for boot cpu */
-                if (c == &boot_cpu_data)
-                        check_enable_amd_mmconf_dmi();
-
-                fam10h_check_enable_mmcfg();
-        }
-
-        if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
-                unsigned long long tseg;
-
-                /*
-                 * Split up direct mapping around the TSEG SMM area.
-                 * Don't do it for gbpages because there seems very little
-                 * benefit in doing so.
-                 */
-                if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
-                    printk(KERN_DEBUG "tseg: %010llx\n", tseg);
-                    if ((tseg>>PMD_SHIFT) <
-                                (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
-                        ((tseg>>PMD_SHIFT) <
-                                (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
-                         (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
-                        set_memory_4k((unsigned long)__va(tseg), 1);
-                }
-        }
-}
-
-static struct cpu_dev amd_cpu_dev __cpuinitdata = {
-        .c_vendor       = "AMD",
-        .c_ident        = { "AuthenticAMD" },
-        .c_early_init   = early_init_amd,
-        .c_init         = init_amd,
-};
-
-cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);
-
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index a0534c04d38a..89bfdd9cacc6 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -289,7 +289,6 @@ static void __cpuinit init_c3(struct cpuinfo_x86 *c)
         if (c->x86_model >= 6 && c->x86_model < 9)
                 set_cpu_cap(c, X86_FEATURE_3DNOW);
 
-        get_model_name(c);
         display_cacheinfo(c);
 }
 
@@ -475,6 +474,7 @@ static struct cpu_dev centaur_cpu_dev __cpuinitdata = {
         .c_early_init   = early_init_centaur,
         .c_init         = init_centaur,
         .c_size_cache   = centaur_size_cache,
+        .c_x86_vendor   = X86_VENDOR_CENTAUR,
 };
 
-cpu_vendor_dev_register(X86_VENDOR_CENTAUR, &centaur_cpu_dev);
+cpu_dev_register(centaur_cpu_dev);
diff --git a/arch/x86/kernel/cpu/centaur_64.c b/arch/x86/kernel/cpu/centaur_64.c
index 1d181c40e2e1..a1625f5a1e78 100644
--- a/arch/x86/kernel/cpu/centaur_64.c
+++ b/arch/x86/kernel/cpu/centaur_64.c
@@ -16,9 +16,10 @@ static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
 
 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
 {
+        early_init_centaur(c);
+
         if (c->x86 == 0x6 && c->x86_model >= 0xf) {
                 c->x86_cache_alignment = c->x86_clflush_size * 2;
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
         }
         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
@@ -29,7 +30,8 @@ static struct cpu_dev centaur_cpu_dev __cpuinitdata = {
         .c_ident        = { "CentaurHauls" },
         .c_early_init   = early_init_centaur,
         .c_init         = init_centaur,
+        .c_x86_vendor   = X86_VENDOR_CENTAUR,
 };
 
-cpu_vendor_dev_register(X86_VENDOR_CENTAUR, &centaur_cpu_dev);
+cpu_dev_register(centaur_cpu_dev);
 
diff --git a/arch/x86/kernel/cpu/cmpxchg.c b/arch/x86/kernel/cpu/cmpxchg.c
new file mode 100644
index 000000000000..2056ccf572cc
--- /dev/null
+++ b/arch/x86/kernel/cpu/cmpxchg.c
@@ -0,0 +1,72 @@
+/*
+ * cmpxchg*() fallbacks for CPU not supporting these instructions
+ */
+
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <linux/module.h>
+
+#ifndef CONFIG_X86_CMPXCHG
+unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
+{
+        u8 prev;
+        unsigned long flags;
+
+        /* Poor man's cmpxchg for 386. Unsuitable for SMP */
+        local_irq_save(flags);
+        prev = *(u8 *)ptr;
+        if (prev == old)
+                *(u8 *)ptr = new;
+        local_irq_restore(flags);
+        return prev;
+}
+EXPORT_SYMBOL(cmpxchg_386_u8);
+
+unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
+{
+        u16 prev;
+        unsigned long flags;
+
+        /* Poor man's cmpxchg for 386. Unsuitable for SMP */
+        local_irq_save(flags);
+        prev = *(u16 *)ptr;
+        if (prev == old)
+                *(u16 *)ptr = new;
+        local_irq_restore(flags);
+        return prev;
+}
+EXPORT_SYMBOL(cmpxchg_386_u16);
+
+unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
+{
+        u32 prev;
+        unsigned long flags;
+
+        /* Poor man's cmpxchg for 386. Unsuitable for SMP */
+        local_irq_save(flags);
+        prev = *(u32 *)ptr;
+        if (prev == old)
+                *(u32 *)ptr = new;
+        local_irq_restore(flags);
+        return prev;
+}
+EXPORT_SYMBOL(cmpxchg_386_u32);
+#endif
+
+#ifndef CONFIG_X86_CMPXCHG64
+unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
+{
+        u64 prev;
+        unsigned long flags;
+
+        /* Poor man's cmpxchg8b for 386 and 486. Unsuitable for SMP */
+        local_irq_save(flags);
+        prev = *(u64 *)ptr;
+        if (prev == old)
+                *(u64 *)ptr = new;
+        local_irq_restore(flags);
+        return prev;
+}
+EXPORT_SYMBOL(cmpxchg_486_u64);
+#endif
+
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 8aab8517642e..7581b62df184 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1,28 +1,62 @@
 #include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
 #include <linux/string.h>
+#include <linux/bootmem.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/kgdb.h>
+#include <linux/topology.h>
 #include <linux/delay.h>
 #include <linux/smp.h>
-#include <linux/module.h>
 #include <linux/percpu.h>
-#include <linux/bootmem.h>
-#include <asm/processor.h>
 #include <asm/i387.h>
 #include <asm/msr.h>
 #include <asm/io.h>
+#include <asm/linkage.h>
 #include <asm/mmu_context.h>
 #include <asm/mtrr.h>
 #include <asm/mce.h>
 #include <asm/pat.h>
 #include <asm/asm.h>
+#include <asm/numa.h>
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/mpspec.h>
 #include <asm/apic.h>
 #include <mach_apic.h>
+#include <asm/genapic.h>
 #endif
 
+#include <asm/pda.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/desc.h>
+#include <asm/atomic.h>
+#include <asm/proto.h>
+#include <asm/sections.h>
+#include <asm/setup.h>
+
 #include "cpu.h"
 
+static struct cpu_dev *this_cpu __cpuinitdata;
+
+#ifdef CONFIG_X86_64
+/* We need valid kernel segments for data and code in long mode too
+ * IRET will check the segment types  kkeil 2000/10/28
+ * Also sysret mandates a special GDT layout
+ */
+/* The TLS descriptors are currently at a different place compared to i386.
+   Hopefully nobody expects them at a fixed place (Wine?) */
 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
+        [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
+        [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
+        [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
+        [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
+        [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
+        [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
+} };
+#else
+DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
@@ -56,17 +90,150 @@ DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
         [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
         [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
 } };
+#endif
 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
 
-__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
-
+#ifdef CONFIG_X86_32
 static int cachesize_override __cpuinitdata = -1;
 static int disable_x86_serial_nr __cpuinitdata = 1;
 
-struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
+static int __init cachesize_setup(char *str)
+{
+        get_option(&str, &cachesize_override);
+        return 1;
+}
+__setup("cachesize=", cachesize_setup);
+
+static int __init x86_fxsr_setup(char *s)
+{
+        setup_clear_cpu_cap(X86_FEATURE_FXSR);
+        setup_clear_cpu_cap(X86_FEATURE_XMM);
+        return 1;
+}
+__setup("nofxsr", x86_fxsr_setup);
+
+static int __init x86_sep_setup(char *s)
+{
+        setup_clear_cpu_cap(X86_FEATURE_SEP);
+        return 1;
+}
+__setup("nosep", x86_sep_setup);
+
+/* Standard macro to see if a specific flag is changeable */
+static inline int flag_is_changeable_p(u32 flag)
+{
+        u32 f1, f2;
+
+        asm("pushfl\n\t"
+            "pushfl\n\t"
+            "popl %0\n\t"
+            "movl %0,%1\n\t"
+            "xorl %2,%0\n\t"
+            "pushl %0\n\t"
+            "popfl\n\t"
+            "pushfl\n\t"
+            "popl %0\n\t"
+            "popfl\n\t"
+            : "=&r" (f1), "=&r" (f2)
+            : "ir" (flag));
+
+        return ((f1^f2) & flag) != 0;
+}
+
+/* Probe for the CPUID instruction */
+static int __cpuinit have_cpuid_p(void)
+{
+        return flag_is_changeable_p(X86_EFLAGS_ID);
+}
+
+static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
+{
+        if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
+                /* Disable processor serial number */
+                unsigned long lo, hi;
+                rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
+                lo |= 0x200000;
+                wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
+                printk(KERN_NOTICE "CPU serial number disabled.\n");
+                clear_cpu_cap(c, X86_FEATURE_PN);
+
+                /* Disabling the serial number may affect the cpuid level */
+                c->cpuid_level = cpuid_eax(0);
+        }
+}
+
+static int __init x86_serial_nr_setup(char *s)
+{
+        disable_x86_serial_nr = 0;
+        return 1;
+}
+__setup("serialnumber", x86_serial_nr_setup);
+#else
+static inline int flag_is_changeable_p(u32 flag)
+{
+        return 1;
+}
+/* Probe for the CPUID instruction */
+static inline int have_cpuid_p(void)
+{
+        return 1;
+}
+static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
+{
+}
+#endif
+
+/*
+ * Naming convention should be: <Name> [(<Codename>)]
+ * This table only is used unless init_<vendor>() below doesn't set it;
+ * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
+ *
+ */
+
+/* Look up CPU names by table lookup. */
+static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
+{
+        struct cpu_model_info *info;
+
+        if (c->x86_model >= 16)
+                return NULL;    /* Range check */
+
+        if (!this_cpu)
+                return NULL;
+
+        info = this_cpu->c_models;
+
+        while (info && info->family) {
+                if (info->family == c->x86)
+                        return info->model_names[c->x86_model];
+                info++;
+        }
+        return NULL;            /* Not found */
+}
+
+__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
+
+/* Current gdt points %fs at the "master" per-cpu area: after this,
+ * it's on the real one. */
+void switch_to_new_gdt(void)
+{
+        struct desc_ptr gdt_descr;
+
+        gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
+        gdt_descr.size = GDT_SIZE - 1;
+        load_gdt(&gdt_descr);
+#ifdef CONFIG_X86_32
+        asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
+#endif
+}
+
+static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
 
 static void __cpuinit default_init(struct cpuinfo_x86 *c)
 {
+#ifdef CONFIG_X86_64
+        display_cacheinfo(c);
+#else
         /* Not much we can do here... */
         /* Check if at least it has cpuid */
         if (c->cpuid_level == -1) {
@@ -76,28 +243,22 @@ static void __cpuinit default_init(struct cpuinfo_x86 *c)
                 else if (c->x86 == 3)
                         strcpy(c->x86_model_id, "386");
         }
+#endif
 }
 
 static struct cpu_dev __cpuinitdata default_cpu = {
         .c_init = default_init,
         .c_vendor = "Unknown",
+        .c_x86_vendor = X86_VENDOR_UNKNOWN,
 };
-static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
 
-static int __init cachesize_setup(char *str)
-{
-        get_option(&str, &cachesize_override);
-        return 1;
-}
-__setup("cachesize=", cachesize_setup);
-
-int __cpuinit get_model_name(struct cpuinfo_x86 *c)
+static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
 {
         unsigned int *v;
         char *p, *q;
 
-        if (cpuid_eax(0x80000000) < 0x80000004)
-                return 0;
+        if (c->extended_cpuid_level < 0x80000004)
+                return;
 
         v = (unsigned int *) c->x86_model_id;
         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
@@ -116,30 +277,34 @@ int __cpuinit get_model_name(struct cpuinfo_x86 *c)
              while (q <= &c->x86_model_id[48])
                   *q++ = '\0';  /* Zero-pad the rest */
         }
-
-        return 1;
 }
 
-
 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 {
-        unsigned int n, dummy, ecx, edx, l2size;
+        unsigned int n, dummy, ebx, ecx, edx, l2size;
 
-        n = cpuid_eax(0x80000000);
+        n = c->extended_cpuid_level;
 
         if (n >= 0x80000005) {
-                cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
+                cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
-                        edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
-                c->x86_cache_size = (ecx>>24)+(edx>>24);
+                                edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
+                c->x86_cache_size = (ecx>>24) + (edx>>24);
+#ifdef CONFIG_X86_64
+                /* On K8 L1 TLB is inclusive, so don't count it */
+                c->x86_tlbsize = 0;
+#endif
         }
 
         if (n < 0x80000006)     /* Some chips just has a large L1. */
                 return;
 
-        ecx = cpuid_ecx(0x80000006);
+        cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
         l2size = ecx >> 16;
 
+#ifdef CONFIG_X86_64
+        c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
+#else
         /* do processor-specific cache resizing */
         if (this_cpu->c_size_cache)
                 l2size = this_cpu->c_size_cache(c, l2size);
@@ -150,116 +315,106 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 
         if (l2size == 0)
                 return;         /* Again, no L2 cache is possible */
+#endif
 
         c->x86_cache_size = l2size;
 
         printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
-               l2size, ecx & 0xFF);
+                        l2size, ecx & 0xFF);
 }
 
-/*
- * Naming convention should be: <Name> [(<Codename>)]
- * This table only is used unless init_<vendor>() below doesn't set it;
- * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
- *
- */
-
-/* Look up CPU names by table lookup. */
-static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
+void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 {
-        struct cpu_model_info *info;
+#ifdef CONFIG_X86_HT
+        u32 eax, ebx, ecx, edx;
+        int index_msb, core_bits;
 
-        if (c->x86_model >= 16)
-                return NULL;    /* Range check */
+        if (!cpu_has(c, X86_FEATURE_HT))
+                return;
 
-        if (!this_cpu)
-                return NULL;
+        if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
+                goto out;
 
-        info = this_cpu->c_models;
+        if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
+                return;
 
-        while (info && info->family) {
-                if (info->family == c->x86)
-                        return info->model_names[c->x86_model];
-                info++;
+        cpuid(1, &eax, &ebx, &ecx, &edx);
+
+        smp_num_siblings = (ebx & 0xff0000) >> 16;
+
+        if (smp_num_siblings == 1) {
+                printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
+        } else if (smp_num_siblings > 1) {
+
+                if (smp_num_siblings > NR_CPUS) {
+                        printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
+                                        smp_num_siblings);
+                        smp_num_siblings = 1;
+                        return;
+                }
+
+                index_msb = get_count_order(smp_num_siblings);
+#ifdef CONFIG_X86_64
+                c->phys_proc_id = phys_pkg_id(index_msb);
+#else
+                c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
+#endif
+
+                smp_num_siblings = smp_num_siblings / c->x86_max_cores;
+
+                index_msb = get_count_order(smp_num_siblings);
+
+                core_bits = get_count_order(c->x86_max_cores);
+
+#ifdef CONFIG_X86_64
+                c->cpu_core_id = phys_pkg_id(index_msb) &
+                                               ((1 << core_bits) - 1);
+#else
+                c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
+                                               ((1 << core_bits) - 1);
+#endif
         }
-        return NULL;            /* Not found */
-}
 
+out:
+        if ((c->x86_max_cores * smp_num_siblings) > 1) {
+                printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
+                       c->phys_proc_id);
+                printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
+                       c->cpu_core_id);
+        }
+#endif
+}
 
-static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
+static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 {
         char *v = c->x86_vendor_id;
         int i;
         static int printed;
 
         for (i = 0; i < X86_VENDOR_NUM; i++) {
-                if (cpu_devs[i]) {
-                        if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
-                            (cpu_devs[i]->c_ident[1] &&
-                             !strcmp(v, cpu_devs[i]->c_ident[1]))) {
-                                c->x86_vendor = i;
-                                if (!early)
-                                        this_cpu = cpu_devs[i];
-                                return;
-                        }
+                if (!cpu_devs[i])
+                        break;
+
+                if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
+                    (cpu_devs[i]->c_ident[1] &&
+                     !strcmp(v, cpu_devs[i]->c_ident[1]))) {
+                        this_cpu = cpu_devs[i];
+                        c->x86_vendor = this_cpu->c_x86_vendor;
+                        return;
                 }
         }
+
         if (!printed) {
                 printed++;
-                printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
+                printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
                 printk(KERN_ERR "CPU: Your system may be unstable.\n");
         }
+
         c->x86_vendor = X86_VENDOR_UNKNOWN;
         this_cpu = &default_cpu;
 }
 
-
-static int __init x86_fxsr_setup(char *s)
-{
-        setup_clear_cpu_cap(X86_FEATURE_FXSR);
-        setup_clear_cpu_cap(X86_FEATURE_XMM);
-        return 1;
-}
-__setup("nofxsr", x86_fxsr_setup);
-
-
-static int __init x86_sep_setup(char *s)
-{
-        setup_clear_cpu_cap(X86_FEATURE_SEP);
-        return 1;
-}
-__setup("nosep", x86_sep_setup);
-
-
-/* Standard macro to see if a specific flag is changeable */
-static inline int flag_is_changeable_p(u32 flag)
-{
-        u32 f1, f2;
-
-        asm("pushfl\n\t"
-            "pushfl\n\t"
-            "popl %0\n\t"
-            "movl %0,%1\n\t"
-            "xorl %2,%0\n\t"
-            "pushl %0\n\t"
-            "popfl\n\t"
-            "pushfl\n\t"
-            "popl %0\n\t"
-            "popfl\n\t"
-            : "=&r" (f1), "=&r" (f2)
-            : "ir" (flag));
-
-        return ((f1^f2) & flag) != 0;
-}
-
-
-/* Probe for the CPUID instruction */
-static int __cpuinit have_cpuid_p(void)
-{
-        return flag_is_changeable_p(X86_EFLAGS_ID);
-}
-
-void __init cpu_detect(struct cpuinfo_x86 *c)
+void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
 {
         /* Get vendor name */
         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
@@ -268,48 +423,85 @@ void __init cpu_detect(struct cpuinfo_x86 *c)
               (unsigned int *)&c->x86_vendor_id[4]);
 
         c->x86 = 4;
+        /* Intel-defined flags: level 0x00000001 */
         if (c->cpuid_level >= 0x00000001) {
                 u32 junk, tfms, cap0, misc;
                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
-                c->x86 = (tfms >> 8) & 15;
-                c->x86_model = (tfms >> 4) & 15;
+                c->x86 = (tfms >> 8) & 0xf;
+                c->x86_model = (tfms >> 4) & 0xf;
+                c->x86_mask = tfms & 0xf;
                 if (c->x86 == 0xf)
                         c->x86 += (tfms >> 20) & 0xff;
                 if (c->x86 >= 0x6)
-                        c->x86_model += ((tfms >> 16) & 0xF) << 4;
-                c->x86_mask = tfms & 15;
+                        c->x86_model += ((tfms >> 16) & 0xf) << 4;
                 if (cap0 & (1<<19)) {
-                        c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
+                        c->x86_cache_alignment = c->x86_clflush_size;
                 }
         }
 }
-static void __cpuinit early_get_cap(struct cpuinfo_x86 *c)
+
+static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 {
         u32 tfms, xlvl;
-        unsigned int ebx;
+        u32 ebx;
 
-        memset(&c->x86_capability, 0, sizeof c->x86_capability);
-        if (have_cpuid_p()) {
-                /* Intel-defined flags: level 0x00000001 */
-                if (c->cpuid_level >= 0x00000001) {
-                        u32 capability, excap;
-                        cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
-                        c->x86_capability[0] = capability;
-                        c->x86_capability[4] = excap;
-                }
+        /* Intel-defined flags: level 0x00000001 */
+        if (c->cpuid_level >= 0x00000001) {
+                u32 capability, excap;
+                cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
+                c->x86_capability[0] = capability;
+                c->x86_capability[4] = excap;
+        }
 
-                /* AMD-defined flags: level 0x80000001 */
-                xlvl = cpuid_eax(0x80000000);
-                if ((xlvl & 0xffff0000) == 0x80000000) {
-                        if (xlvl >= 0x80000001) {
-                                c->x86_capability[1] = cpuid_edx(0x80000001);
-                                c->x86_capability[6] = cpuid_ecx(0x80000001);
-                        }
+        /* AMD-defined flags: level 0x80000001 */
+        xlvl = cpuid_eax(0x80000000);
+        c->extended_cpuid_level = xlvl;
+        if ((xlvl & 0xffff0000) == 0x80000000) {
+                if (xlvl >= 0x80000001) {
+                        c->x86_capability[1] = cpuid_edx(0x80000001);
+                        c->x86_capability[6] = cpuid_ecx(0x80000001);
                 }
+        }
+
+#ifdef CONFIG_X86_64
+        if (c->extended_cpuid_level >= 0x80000008) {
+                u32 eax = cpuid_eax(0x80000008);
 
+                c->x86_virt_bits = (eax >> 8) & 0xff;
+                c->x86_phys_bits = eax & 0xff;
         }
+#endif
+
+        if (c->extended_cpuid_level >= 0x80000007)
+                c->x86_power = cpuid_edx(0x80000007);
+
+}
+
+static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_X86_32
+        int i;
 
+        /*
+         * First of all, decide if this is a 486 or higher
+         * It's a 486 if we can modify the AC flag
+         */
+        if (flag_is_changeable_p(X86_EFLAGS_AC))
+                c->x86 = 4;
+        else
+                c->x86 = 3;
+
+        for (i = 0; i < X86_VENDOR_NUM; i++)
+                if (cpu_devs[i] && cpu_devs[i]->c_identify) {
+                        c->x86_vendor_id[0] = 0;
+                        cpu_devs[i]->c_identify(c);
+                        if (c->x86_vendor_id[0]) {
+                                get_cpu_vendor(c);
+                                break;
+                        }
+                }
+#endif
 }
 
 /*
@@ -321,138 +513,113 @@ static void __cpuinit early_get_cap(struct cpuinfo_x86 *c)
  * WARNING: this function is only called on the BP.  Don't add code here
  * that is supposed to run on all CPUs.
  */
-static void __init early_cpu_detect(void)
+static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 {
-        struct cpuinfo_x86 *c = &boot_cpu_data;
-
-        c->x86_cache_alignment = 32;
+#ifdef CONFIG_X86_64
+        c->x86_clflush_size = 64;
+#else
         c->x86_clflush_size = 32;
+#endif
+        c->x86_cache_alignment = c->x86_clflush_size;
+
+        memset(&c->x86_capability, 0, sizeof c->x86_capability);
+        c->extended_cpuid_level = 0;
 
         if (!have_cpuid_p())
+                identify_cpu_without_cpuid(c);
+
+        /* cyrix could have cpuid enabled via c_identify()*/
+        if (!have_cpuid_p())
                 return;
 
         cpu_detect(c);
 
-        get_cpu_vendor(c, 1);
+        get_cpu_vendor(c);
+
+        get_cpu_cap(c);
 
-        early_get_cap(c);
+        if (this_cpu->c_early_init)
+                this_cpu->c_early_init(c);
 
-        if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
-            cpu_devs[c->x86_vendor]->c_early_init)
-                cpu_devs[c->x86_vendor]->c_early_init(c);
+        validate_pat_support(c);
+}
+
+void __init early_cpu_init(void)
+{
+        struct cpu_dev **cdev;
+        int count = 0;
+
+        printk("KERNEL supported cpus:\n");
+        for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
+                struct cpu_dev *cpudev = *cdev;
+                unsigned int j;
+
+                if (count >= X86_VENDOR_NUM)
+                        break;
+                cpu_devs[count] = cpudev;
+                count++;
+
+                for (j = 0; j < 2; j++) {
+                        if (!cpudev->c_ident[j])
+                                continue;
+                        printk("  %s %s\n", cpudev->c_vendor,
+                                cpudev->c_ident[j]);
+                }
+        }
+
+        early_identify_cpu(&boot_cpu_data);
 }
 
 /*
  * The NOPL instruction is supposed to exist on all CPUs with
- * family >= 6, unfortunately, that's not true in practice because
+ * family >= 6; unfortunately, that's not true in practice because
  * of early VIA chips and (more importantly) broken virtualizers that
- * are not easy to detect.  Hence, probe for it based on first
- * principles.
+ * are not easy to detect.  In the latter case it doesn't even *fail*
+ * reliably, so probing for it doesn't even work.  Disable it completely
+ * unless we can find a reliable way to detect all the broken cases.
  */
 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
 {
-        const u32 nopl_signature = 0x888c53b1; /* Random number */
-        u32 has_nopl = nopl_signature;
-
         clear_cpu_cap(c, X86_FEATURE_NOPL);
-        if (c->x86 >= 6) {
-                asm volatile("\n"
-                             "1:      .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
-                             "2:\n"
-                             "        .section .fixup,\"ax\"\n"
-                             "3:      xor %0,%0\n"
-                             "        jmp 2b\n"
-                             "        .previous\n"
-                             _ASM_EXTABLE(1b,3b)
-                             : "+a" (has_nopl));
-
-                if (has_nopl == nopl_signature)
-                        set_cpu_cap(c, X86_FEATURE_NOPL);
-        }
 }
 
 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 {
-        u32 tfms, xlvl;
-        unsigned int ebx;
-
-        if (have_cpuid_p()) {
-                /* Get vendor name */
-                cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
-                      (unsigned int *)&c->x86_vendor_id[0],
-                      (unsigned int *)&c->x86_vendor_id[8],
-                      (unsigned int *)&c->x86_vendor_id[4]);
-
-                get_cpu_vendor(c, 0);
-                /* Initialize the standard set of capabilities */
-                /* Note that the vendor-specific code below might override */
-                /* Intel-defined flags: level 0x00000001 */
-                if (c->cpuid_level >= 0x00000001) {
-                        u32 capability, excap;
-                        cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
-                        c->x86_capability[0] = capability;
-                        c->x86_capability[4] = excap;
-                        c->x86 = (tfms >> 8) & 15;
-                        c->x86_model = (tfms >> 4) & 15;
-                        if (c->x86 == 0xf)
-                                c->x86 += (tfms >> 20) & 0xff;
-                        if (c->x86 >= 0x6)
-                                c->x86_model += ((tfms >> 16) & 0xF) << 4;
-                        c->x86_mask = tfms & 15;
-                        c->initial_apicid = (ebx >> 24) & 0xFF;
-#ifdef CONFIG_X86_HT
-                        c->apicid = phys_pkg_id(c->initial_apicid, 0);
-                        c->phys_proc_id = c->initial_apicid;
-#else
-                        c->apicid = c->initial_apicid;
-#endif
-                        if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
-                                c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
-                } else {
-                        /* Have CPUID level 0 only - unheard of */
-                        c->x86 = 4;
-                }
+        c->extended_cpuid_level = 0;
 
-                /* AMD-defined flags: level 0x80000001 */
-                xlvl = cpuid_eax(0x80000000);
-                if ((xlvl & 0xffff0000) == 0x80000000) {
-                        if (xlvl >= 0x80000001) {
-                                c->x86_capability[1] = cpuid_edx(0x80000001);
-                                c->x86_capability[6] = cpuid_ecx(0x80000001);
-                        }
-                        if (xlvl >= 0x80000004)
-                                get_model_name(c); /* Default name */
-                }
+        if (!have_cpuid_p())
+                identify_cpu_without_cpuid(c);
 
-                init_scattered_cpuid_features(c);
-                detect_nopl(c);
-        }
-}
+        /* cyrix could have cpuid enabled via c_identify()*/
+        if (!have_cpuid_p())
+                return;
 
-static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
-{
-        if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
-                /* Disable processor serial number */
-                unsigned long lo, hi;
-                rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
-                lo |= 0x200000;
-                wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
-                printk(KERN_NOTICE "CPU serial number disabled.\n");
-                clear_cpu_cap(c, X86_FEATURE_PN);
+        cpu_detect(c);
 
-                /* Disabling the serial number may affect the cpuid level */
-                c->cpuid_level = cpuid_eax(0);
-        }
-}
+        get_cpu_vendor(c);
 
-static int __init x86_serial_nr_setup(char *s)
-{
-        disable_x86_serial_nr = 0;
-        return 1;
-}
-__setup("serialnumber", x86_serial_nr_setup);
+        get_cpu_cap(c);
+
+        if (c->cpuid_level >= 0x00000001) {
+                c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
+#ifdef CONFIG_X86_32
+# ifdef CONFIG_X86_HT
+                c->apicid = phys_pkg_id(c->initial_apicid, 0);
+# else
+                c->apicid = c->initial_apicid;
+# endif
+#endif
+
+#ifdef CONFIG_X86_HT
+                c->phys_proc_id = c->initial_apicid;
+#endif
+        }
 
+        get_model_name(c); /* Default name */
 
+        init_scattered_cpuid_features(c);
+        detect_nopl(c);
+}
 
 /*
  * This does the hard work of actually picking apart the CPU stuff...
@@ -464,30 +631,29 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
         c->loops_per_jiffy = loops_per_jiffy;
         c->x86_cache_size = -1;
         c->x86_vendor = X86_VENDOR_UNKNOWN;
-        c->cpuid_level = -1;    /* CPUID not detected */
         c->x86_model = c->x86_mask = 0; /* So far unknown... */
         c->x86_vendor_id[0] = '\0'; /* Unset */
         c->x86_model_id[0] = '\0';  /* Unset */
         c->x86_max_cores = 1;
+        c->x86_coreid_bits = 0;
+#ifdef CONFIG_X86_64
+        c->x86_clflush_size = 64;
+#else
+        c->cpuid_level = -1;    /* CPUID not detected */
         c->x86_clflush_size = 32;
+#endif
+        c->x86_cache_alignment = c->x86_clflush_size;
         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 
-        if (!have_cpuid_p()) {
-                /*
-                 * First of all, decide if this is a 486 or higher
-                 * It's a 486 if we can modify the AC flag
-                 */
-                if (flag_is_changeable_p(X86_EFLAGS_AC))
-                        c->x86 = 4;
-                else
-                        c->x86 = 3;
-        }
-
         generic_identify(c);
 
         if (this_cpu->c_identify)
                 this_cpu->c_identify(c);
 
+#ifdef CONFIG_X86_64
+        c->apicid = phys_pkg_id(0);
+#endif
+
         /*
          * Vendor-specific initialization.  In this section we
          * canonicalize the feature flags, meaning if there are
@@ -521,6 +687,10 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
                                 c->x86, c->x86_model);
         }
 
+#ifdef CONFIG_X86_64
+        detect_ht(c);
+#endif
+
         /*
          * On SMP, boot_cpu_data holds the common feature set between
          * all CPUs; so make sure that we indicate which features are
@@ -529,7 +699,7 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
          */
         if (c != &boot_cpu_data) {
                 /* AND the already accumulated flags with these */
-                for (i = 0 ; i < NCAPINTS ; i++)
+                for (i = 0; i < NCAPINTS; i++)
                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
         }
 
@@ -537,72 +707,79 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
         for (i = 0; i < NCAPINTS; i++)
                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
 
+#ifdef CONFIG_X86_MCE
         /* Init Machine Check Exception if available. */
         mcheck_init(c);
+#endif
 
         select_idle_routine(c);
+
+#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
+        numa_add_cpu(smp_processor_id());
+#endif
 }
 
 void __init identify_boot_cpu(void)
 {
         identify_cpu(&boot_cpu_data);
+#ifdef CONFIG_X86_32
         sysenter_setup();
         enable_sep_cpu();
+#endif
 }
 
 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
 {
         BUG_ON(c == &boot_cpu_data);
         identify_cpu(c);
+#ifdef CONFIG_X86_32
         enable_sep_cpu();
+#endif
         mtrr_ap_init();
 }
 
-#ifdef CONFIG_X86_HT
-void __cpuinit detect_ht(struct cpuinfo_x86 *c)
-{
-        u32     eax, ebx, ecx, edx;
-        int     index_msb, core_bits;
-
-        cpuid(1, &eax, &ebx, &ecx, &edx);
-
-        if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
-                return;
-
-        smp_num_siblings = (ebx & 0xff0000) >> 16;
+struct msr_range {
+        unsigned min;
+        unsigned max;
+};
 
-        if (smp_num_siblings == 1) {
-                printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
-        } else if (smp_num_siblings > 1) {
+static struct msr_range msr_range_array[] __cpuinitdata = {
+        { 0x00000000, 0x00000418},
+        { 0xc0000000, 0xc000040b},
+        { 0xc0010000, 0xc0010142},
+        { 0xc0011000, 0xc001103b},
+};
 
-                if (smp_num_siblings > NR_CPUS) {
-                        printk(KERN_WARNING "CPU: Unsupported number of the "
-                                        "siblings %d", smp_num_siblings);
-                        smp_num_siblings = 1;
-                        return;
+static void __cpuinit print_cpu_msr(void)
+{
+        unsigned index;
+        u64 val;
+        int i;
+        unsigned index_min, index_max;
+
+        for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
+                index_min = msr_range_array[i].min;
+                index_max = msr_range_array[i].max;
+                for (index = index_min; index < index_max; index++) {
+                        if (rdmsrl_amd_safe(index, &val))
+                                continue;
+                        printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
                 }
+        }
+}
 
-                index_msb = get_count_order(smp_num_siblings);
-                c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
-
-                printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
-                       c->phys_proc_id);
-
-                smp_num_siblings = smp_num_siblings / c->x86_max_cores;
-
-                index_msb = get_count_order(smp_num_siblings) ;
+static int show_msr __cpuinitdata;
+static __init int setup_show_msr(char *arg)
+{
+        int num;
 
-                core_bits = get_count_order(c->x86_max_cores);
+        get_option(&arg, &num);
 
-                c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
-                                               ((1 << core_bits) - 1);
-
-                if (c->x86_max_cores > 1)
-                        printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
-                               c->cpu_core_id);
-        }
+        if (num > 0)
+                show_msr = num;
+        return 1;
 }
-#endif
+__setup("show_msr=", setup_show_msr);
 
 static __init int setup_noclflush(char *arg)
 {
@@ -621,17 +798,25 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
                 vendor = c->x86_vendor_id;
 
         if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
-                printk("%s ", vendor);
+                printk(KERN_CONT "%s ", vendor);
 
-        if (!c->x86_model_id[0])
-                printk("%d86", c->x86);
+        if (c->x86_model_id[0])
+                printk(KERN_CONT "%s", c->x86_model_id);
         else
-                printk("%s", c->x86_model_id);
+                printk(KERN_CONT "%d86", c->x86);
 
         if (c->x86_mask || c->cpuid_level >= 0)
-                printk(" stepping %02x\n", c->x86_mask);
+                printk(KERN_CONT " stepping %02x\n", c->x86_mask);
         else
-                printk("\n");
+                printk(KERN_CONT "\n");
+
+#ifdef CONFIG_SMP
+        if (c->cpu_index < show_msr)
+                print_cpu_msr();
+#else
+        if (show_msr)
+                print_cpu_msr();
+#endif
 }
 
 static __init int setup_disablecpuid(char *arg)
@@ -647,19 +832,89 @@ __setup("clearcpuid=", setup_disablecpuid);
 
 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
 
-void __init early_cpu_init(void)
+#ifdef CONFIG_X86_64
+struct x8664_pda **_cpu_pda __read_mostly;
+EXPORT_SYMBOL(_cpu_pda);
+
+struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
+
+char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
+
+void __cpuinit pda_init(int cpu)
+{
+        struct x8664_pda *pda = cpu_pda(cpu);
+
+        /* Setup up data that may be needed in __get_free_pages early */
+        loadsegment(fs, 0);
+        loadsegment(gs, 0);
+        /* Memory clobbers used to order PDA accessed */
+        mb();
+        wrmsrl(MSR_GS_BASE, pda);
+        mb();
+
+        pda->cpunumber = cpu;
+        pda->irqcount = -1;
+        pda->kernelstack = (unsigned long)stack_thread_info() -
+                                 PDA_STACKOFFSET + THREAD_SIZE;
+        pda->active_mm = &init_mm;
+        pda->mmu_state = 0;
+
+        if (cpu == 0) {
+                /* others are initialized in smpboot.c */
+                pda->pcurrent = &init_task;
+                pda->irqstackptr = boot_cpu_stack;
+                pda->irqstackptr += IRQSTACKSIZE - 64;
+        } else {
+                if (!pda->irqstackptr) {
+                        pda->irqstackptr = (char *)
+                                __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
+                        if (!pda->irqstackptr)
+                                panic("cannot allocate irqstack for cpu %d",
+                                      cpu);
+                        pda->irqstackptr += IRQSTACKSIZE - 64;
+                }
+
+                if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
+                        pda->nodenumber = cpu_to_node(cpu);
+        }
+}
+
+char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
+                           DEBUG_STKSZ] __page_aligned_bss;
+
+extern asmlinkage void ignore_sysret(void);
+
+/* May not be marked __init: used by software suspend */
+void syscall_init(void)
 {
-        struct cpu_vendor_dev *cvdev;
+        /*
+         * LSTAR and STAR live in a bit strange symbiosis.
+         * They both write to the same internal register. STAR allows to
+         * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
+         */
+        wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
+        wrmsrl(MSR_LSTAR, system_call);
+        wrmsrl(MSR_CSTAR, ignore_sysret);
 
-        for (cvdev = __x86cpuvendor_start ;
-             cvdev < __x86cpuvendor_end   ;
-             cvdev++)
-                cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
+#ifdef CONFIG_IA32_EMULATION
+        syscall32_cpu_init();
+#endif
 
-        early_cpu_detect();
-        validate_pat_support(&boot_cpu_data);
+        /* Flags to clear on syscall */
+        wrmsrl(MSR_SYSCALL_MASK,
+               X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
 }
 
+unsigned long kernel_eflags;
+
+/*
+ * Copies of the original ist values from the tss are only accessed during
+ * debugging, no special alignment required.
+ */
+DEFINE_PER_CPU(struct orig_ist, orig_ist);
+
+#else
+
 /* Make sure %fs is initialized properly in idle threads */
 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
 {
@@ -667,25 +922,136 @@ struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
         regs->fs = __KERNEL_PERCPU;
         return regs;
 }
-
-/* Current gdt points %fs at the "master" per-cpu area: after this,
- * it's on the real one. */
-void switch_to_new_gdt(void)
-{
-        struct desc_ptr gdt_descr;
-
-        gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
-        gdt_descr.size = GDT_SIZE - 1;
-        load_gdt(&gdt_descr);
-        asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
-}
+#endif
 
 /*
  * cpu_init() initializes state that is per-CPU. Some data is already
  * initialized (naturally) in the bootstrap process, such as the GDT
  * and IDT. We reload them nevertheless, this function acts as a
  * 'CPU state barrier', nothing should get across.
+ * A lot of state is already set up in PDA init for 64 bit
  */
+#ifdef CONFIG_X86_64
+void __cpuinit cpu_init(void)
+{
+        int cpu = stack_smp_processor_id();
+        struct tss_struct *t = &per_cpu(init_tss, cpu);
+        struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
+        unsigned long v;
+        char *estacks = NULL;
+        struct task_struct *me;
+        int i;
+
+        /* CPU 0 is initialised in head64.c */
+        if (cpu != 0)
+                pda_init(cpu);
+        else
+                estacks = boot_exception_stacks;
+
+        me = current;
+
+        if (cpu_test_and_set(cpu, cpu_initialized))
+                panic("CPU#%d already initialized!\n", cpu);
+
+        printk(KERN_INFO "Initializing CPU#%d\n", cpu);
+
+        clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
+
+        /*
+         * Initialize the per-CPU GDT with the boot GDT,
+         * and set up the GDT descriptor:
+         */
+
+        switch_to_new_gdt();
+        load_idt((const struct desc_ptr *)&idt_descr);
+
+        memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
+        syscall_init();
+
+        wrmsrl(MSR_FS_BASE, 0);
+        wrmsrl(MSR_KERNEL_GS_BASE, 0);
+        barrier();
+
+        check_efer();
+        if (cpu != 0 && x2apic)
+                enable_x2apic();
+
+        /*
+         * set up and load the per-CPU TSS
+         */
+        if (!orig_ist->ist[0]) {
+                static const unsigned int order[N_EXCEPTION_STACKS] = {
+                  [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
+                  [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
+                };
+                for (v = 0; v < N_EXCEPTION_STACKS; v++) {
+                        if (cpu) {
+                                estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
+                                if (!estacks)
+                                        panic("Cannot allocate exception "
+                                              "stack %ld %d\n", v, cpu);
+                        }
+                        estacks += PAGE_SIZE << order[v];
+                        orig_ist->ist[v] = t->x86_tss.ist[v] =
+                                        (unsigned long)estacks;
+                }
+        }
+
+        t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
+        /*
+         * <= is required because the CPU will access up to
+         * 8 bits beyond the end of the IO permission bitmap.
+         */
+        for (i = 0; i <= IO_BITMAP_LONGS; i++)
+                t->io_bitmap[i] = ~0UL;
+
+        atomic_inc(&init_mm.mm_count);
+        me->active_mm = &init_mm;
+        if (me->mm)
+                BUG();
+        enter_lazy_tlb(&init_mm, me);
+
+        load_sp0(t, &current->thread);
+        set_tss_desc(cpu, t);
+        load_TR_desc();
+        load_LDT(&init_mm.context);
+
+#ifdef CONFIG_KGDB
+        /*
+         * If the kgdb is connected no debug regs should be altered.  This
+         * is only applicable when KGDB and a KGDB I/O module are built
+         * into the kernel and you are using early debugging with
+         * kgdbwait. KGDB will control the kernel HW breakpoint registers.
+         */
+        if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
+                arch_kgdb_ops.correct_hw_break();
+        else {
+#endif
+        /*
+         * Clear all 6 debug registers:
+         */
+
+        set_debugreg(0UL, 0);
+        set_debugreg(0UL, 1);
+        set_debugreg(0UL, 2);
+        set_debugreg(0UL, 3);
+        set_debugreg(0UL, 6);
+        set_debugreg(0UL, 7);
+#ifdef CONFIG_KGDB
+        /* If the kgdb is connected no debug regs should be altered. */
+        }
+#endif
+
+        fpu_init();
+
+        raw_local_save_flags(kernel_eflags);
+
+        if (is_uv_system())
+                uv_cpu_init();
+}
+
+#else
+
 void __cpuinit cpu_init(void)
 {
         int cpu = smp_processor_id();
@@ -739,9 +1105,20 @@ void __cpuinit cpu_init(void)
         /*
          * Force FPU initialization:
          */
-        current_thread_info()->status = 0;
+        if (cpu_has_xsave)
+                current_thread_info()->status = TS_XSAVE;
+        else
+                current_thread_info()->status = 0;
         clear_used_math();
         mxcsr_feature_mask_init();
+
+        /*
+         * Boot processor to setup the FP and extended state context info.
+         */
+        if (!smp_processor_id())
+                init_thread_xstate();
+
+        xsave_init();
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -755,3 +1132,5 @@ void __cpuinit cpu_uninit(void)
         per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
 }
 #endif
+
+#endif
diff --git a/arch/x86/kernel/cpu/common_64.c b/arch/x86/kernel/cpu/common_64.c
deleted file mode 100644
index a11f5d4477cd..000000000000
--- a/arch/x86/kernel/cpu/common_64.c
+++ /dev/null
@@ -1,712 +0,0 @@
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/bootmem.h>
-#include <linux/bitops.h>
-#include <linux/module.h>
-#include <linux/kgdb.h>
-#include <linux/topology.h>
-#include <linux/delay.h>
-#include <linux/smp.h>
-#include <linux/percpu.h>
-#include <asm/i387.h>
-#include <asm/msr.h>
-#include <asm/io.h>
-#include <asm/linkage.h>
-#include <asm/mmu_context.h>
-#include <asm/mtrr.h>
-#include <asm/mce.h>
-#include <asm/pat.h>
-#include <asm/asm.h>
-#include <asm/numa.h>
-#ifdef CONFIG_X86_LOCAL_APIC
-#include <asm/mpspec.h>
-#include <asm/apic.h>
-#include <mach_apic.h>
-#endif
-#include <asm/pda.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/desc.h>
-#include <asm/atomic.h>
-#include <asm/proto.h>
-#include <asm/sections.h>
-#include <asm/setup.h>
-#include <asm/genapic.h>
-
-#include "cpu.h"
-
-/* We need valid kernel segments for data and code in long mode too
- * IRET will check the segment types  kkeil 2000/10/28
- * Also sysret mandates a special GDT layout
- */
-/* The TLS descriptors are currently at a different place compared to i386.
-   Hopefully nobody expects them at a fixed place (Wine?) */
-DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
-        [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
-        [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
-        [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
-        [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
-        [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
-        [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
-} };
-EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
-
-__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
-
-/* Current gdt points %fs at the "master" per-cpu area: after this,
- * it's on the real one. */
-void switch_to_new_gdt(void)
-{
-        struct desc_ptr gdt_descr;
-
-        gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
-        gdt_descr.size = GDT_SIZE - 1;
-        load_gdt(&gdt_descr);
-}
-
-struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
-
-static void __cpuinit default_init(struct cpuinfo_x86 *c)
-{
-        display_cacheinfo(c);
-}
-
-static struct cpu_dev __cpuinitdata default_cpu = {
-        .c_init = default_init,
-        .c_vendor = "Unknown",
-};
-static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
-
-int __cpuinit get_model_name(struct cpuinfo_x86 *c)
-{
-        unsigned int *v;
-
-        if (c->extended_cpuid_level < 0x80000004)
-                return 0;
-
-        v = (unsigned int *) c->x86_model_id;
-        cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
-        cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
-        cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
-        c->x86_model_id[48] = 0;
-        return 1;
-}
-
-
-void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
-{
-        unsigned int n, dummy, ebx, ecx, edx;
-
-        n = c->extended_cpuid_level;
-
-        if (n >= 0x80000005) {
-                cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
-                printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
-                       "D cache %dK (%d bytes/line)\n",
-                       edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
-                c->x86_cache_size = (ecx>>24) + (edx>>24);
-                /* On K8 L1 TLB is inclusive, so don't count it */
-                c->x86_tlbsize = 0;
-        }
-
-        if (n >= 0x80000006) {
-                cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
-                ecx = cpuid_ecx(0x80000006);
-                c->x86_cache_size = ecx >> 16;
-                c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
-
-                printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
-                c->x86_cache_size, ecx & 0xFF);
-        }
-}
-
-void __cpuinit detect_ht(struct cpuinfo_x86 *c)
-{
-#ifdef CONFIG_SMP
-        u32 eax, ebx, ecx, edx;
-        int index_msb, core_bits;
-
-        cpuid(1, &eax, &ebx, &ecx, &edx);
-
-
-        if (!cpu_has(c, X86_FEATURE_HT))
-                return;
-        if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
-                goto out;
-
-        smp_num_siblings = (ebx & 0xff0000) >> 16;
-
-        if (smp_num_siblings == 1) {
-                printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
-        } else if (smp_num_siblings > 1) {
-
-                if (smp_num_siblings > NR_CPUS) {
-                        printk(KERN_WARNING "CPU: Unsupported number of "
-                               "siblings %d", smp_num_siblings);
-                        smp_num_siblings = 1;
-                        return;
-                }
-
-                index_msb = get_count_order(smp_num_siblings);
-                c->phys_proc_id = phys_pkg_id(index_msb);
-
-                smp_num_siblings = smp_num_siblings / c->x86_max_cores;
-
-                index_msb = get_count_order(smp_num_siblings);
-
-                core_bits = get_count_order(c->x86_max_cores);
-
-                c->cpu_core_id = phys_pkg_id(index_msb) &
-                                               ((1 << core_bits) - 1);
-        }
-out:
-        if ((c->x86_max_cores * smp_num_siblings) > 1) {
-                printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
-                       c->phys_proc_id);
-                printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
-                       c->cpu_core_id);
-        }
-
-#endif
-}
-
-static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
-{
-        char *v = c->x86_vendor_id;
-        int i;
-        static int printed;
-
-        for (i = 0; i < X86_VENDOR_NUM; i++) {
-                if (cpu_devs[i]) {
-                        if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
-                            (cpu_devs[i]->c_ident[1] &&
-                            !strcmp(v, cpu_devs[i]->c_ident[1]))) {
-                                c->x86_vendor = i;
-                                this_cpu = cpu_devs[i];
-                                return;
-                        }
-                }
-        }
-        if (!printed) {
-                printed++;
-                printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
-                printk(KERN_ERR "CPU: Your system may be unstable.\n");
-        }
-        c->x86_vendor = X86_VENDOR_UNKNOWN;
-}
-
-static void __init early_cpu_support_print(void)
-{
-        int i,j;
-        struct cpu_dev *cpu_devx;
-
-        printk("KERNEL supported cpus:\n");
-        for (i = 0; i < X86_VENDOR_NUM; i++) {
-                cpu_devx = cpu_devs[i];
-                if (!cpu_devx)
-                        continue;
-                for (j = 0; j < 2; j++) {
-                        if (!cpu_devx->c_ident[j])
-                                continue;
-                        printk("  %s %s\n", cpu_devx->c_vendor,
-                                cpu_devx->c_ident[j]);
-                }
-        }
-}
-
-/*
- * The NOPL instruction is supposed to exist on all CPUs with
- * family >= 6, unfortunately, that's not true in practice because
- * of early VIA chips and (more importantly) broken virtualizers that
- * are not easy to detect.  Hence, probe for it based on first
- * principles.
- *
- * Note: no 64-bit chip is known to lack these, but put the code here
- * for consistency with 32 bits, and to make it utterly trivial to
- * diagnose the problem should it ever surface.
- */
-static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
-{
-        const u32 nopl_signature = 0x888c53b1; /* Random number */
-        u32 has_nopl = nopl_signature;
-
-        clear_cpu_cap(c, X86_FEATURE_NOPL);
-        if (c->x86 >= 6) {
-                asm volatile("\n"
-                             "1:      .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
-                             "2:\n"
-                             "        .section .fixup,\"ax\"\n"
-                             "3:      xor %0,%0\n"
-                             "        jmp 2b\n"
-                             "        .previous\n"
-                             _ASM_EXTABLE(1b,3b)
-                             : "+a" (has_nopl));
-
-                if (has_nopl == nopl_signature)
-                        set_cpu_cap(c, X86_FEATURE_NOPL);
-        }
-}
-
-static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
-
-void __init early_cpu_init(void)
-{
-        struct cpu_vendor_dev *cvdev;
-
-        for (cvdev = __x86cpuvendor_start ;
-             cvdev < __x86cpuvendor_end   ;
-             cvdev++)
-                cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
-        early_cpu_support_print();
-        early_identify_cpu(&boot_cpu_data);
-}
-
-/* Do some early cpuid on the boot CPU to get some parameter that are
-   needed before check_bugs. Everything advanced is in identify_cpu
-   below. */
-static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
-{
-        u32 tfms, xlvl;
-
-        c->loops_per_jiffy = loops_per_jiffy;
-        c->x86_cache_size = -1;
-        c->x86_vendor = X86_VENDOR_UNKNOWN;
-        c->x86_model = c->x86_mask = 0; /* So far unknown... */
-        c->x86_vendor_id[0] = '\0'; /* Unset */
-        c->x86_model_id[0] = '\0';  /* Unset */
-        c->x86_clflush_size = 64;
-        c->x86_cache_alignment = c->x86_clflush_size;
-        c->x86_max_cores = 1;
-        c->x86_coreid_bits = 0;
-        c->extended_cpuid_level = 0;
-        memset(&c->x86_capability, 0, sizeof c->x86_capability);
-
-        /* Get vendor name */
-        cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
-              (unsigned int *)&c->x86_vendor_id[0],
-              (unsigned int *)&c->x86_vendor_id[8],
-              (unsigned int *)&c->x86_vendor_id[4]);
-
-        get_cpu_vendor(c);
-
-        /* Initialize the standard set of capabilities */
-        /* Note that the vendor-specific code below might override */
-
-        /* Intel-defined flags: level 0x00000001 */
-        if (c->cpuid_level >= 0x00000001) {
-                __u32 misc;
-                cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
-                      &c->x86_capability[0]);
-                c->x86 = (tfms >> 8) & 0xf;
-                c->x86_model = (tfms >> 4) & 0xf;
-                c->x86_mask = tfms & 0xf;
-                if (c->x86 == 0xf)
-                        c->x86 += (tfms >> 20) & 0xff;
-                if (c->x86 >= 0x6)
-                        c->x86_model += ((tfms >> 16) & 0xF) << 4;
-                if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
-                        c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
-        } else {
-                /* Have CPUID level 0 only - unheard of */
-                c->x86 = 4;
-        }
-
-        c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
-#ifdef CONFIG_SMP
-        c->phys_proc_id = c->initial_apicid;
-#endif
-        /* AMD-defined flags: level 0x80000001 */
-        xlvl = cpuid_eax(0x80000000);
-        c->extended_cpuid_level = xlvl;
-        if ((xlvl & 0xffff0000) == 0x80000000) {
-                if (xlvl >= 0x80000001) {
-                        c->x86_capability[1] = cpuid_edx(0x80000001);
-                        c->x86_capability[6] = cpuid_ecx(0x80000001);
-                }
-                if (xlvl >= 0x80000004)
-                        get_model_name(c); /* Default name */
-        }
-
-        /* Transmeta-defined flags: level 0x80860001 */
-        xlvl = cpuid_eax(0x80860000);
-        if ((xlvl & 0xffff0000) == 0x80860000) {
-                /* Don't set x86_cpuid_level here for now to not confuse. */
-                if (xlvl >= 0x80860001)
-                        c->x86_capability[2] = cpuid_edx(0x80860001);
-        }
-
-        if (c->extended_cpuid_level >= 0x80000007)
-                c->x86_power = cpuid_edx(0x80000007);
-
-        if (c->extended_cpuid_level >= 0x80000008) {
-                u32 eax = cpuid_eax(0x80000008);
-
-                c->x86_virt_bits = (eax >> 8) & 0xff;
-                c->x86_phys_bits = eax & 0xff;
-        }
-
-        detect_nopl(c);
-
-        if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
-            cpu_devs[c->x86_vendor]->c_early_init)
-                cpu_devs[c->x86_vendor]->c_early_init(c);
-
-        validate_pat_support(c);
-}
-
-/*
- * This does the hard work of actually picking apart the CPU stuff...
- */
-static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
-{
-        int i;
-
-        early_identify_cpu(c);
-
-        init_scattered_cpuid_features(c);
-
-        c->apicid = phys_pkg_id(0);
-
-        /*
-         * Vendor-specific initialization.  In this section we
-         * canonicalize the feature flags, meaning if there are
-         * features a certain CPU supports which CPUID doesn't
-         * tell us, CPUID claiming incorrect flags, or other bugs,
-         * we handle them here.
-         *
-         * At the end of this section, c->x86_capability better
-         * indicate the features this CPU genuinely supports!
-         */
-        if (this_cpu->c_init)
-                this_cpu->c_init(c);
-
-        detect_ht(c);
-
-        /*
-         * On SMP, boot_cpu_data holds the common feature set between
-         * all CPUs; so make sure that we indicate which features are
-         * common between the CPUs.  The first time this routine gets
-         * executed, c == &boot_cpu_data.
-         */
-        if (c != &boot_cpu_data) {
-                /* AND the already accumulated flags with these */
-                for (i = 0; i < NCAPINTS; i++)
-                        boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
-        }
-
-        /* Clear all flags overriden by options */
-        for (i = 0; i < NCAPINTS; i++)
-                c->x86_capability[i] &= ~cleared_cpu_caps[i];
-
-#ifdef CONFIG_X86_MCE
-        mcheck_init(c);
-#endif
-        select_idle_routine(c);
-
-#ifdef CONFIG_NUMA
-        numa_add_cpu(smp_processor_id());
-#endif
-
-}
-
-void __cpuinit identify_boot_cpu(void)
-{
-        identify_cpu(&boot_cpu_data);
-}
-
-void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
-{
-        BUG_ON(c == &boot_cpu_data);
-        identify_cpu(c);
-        mtrr_ap_init();
-}
-
-static __init int setup_noclflush(char *arg)
-{
-        setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
-        return 1;
-}
-__setup("noclflush", setup_noclflush);
-
-void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
-{
-        if (c->x86_model_id[0])
-                printk(KERN_CONT "%s", c->x86_model_id);
-
-        if (c->x86_mask || c->cpuid_level >= 0)
-                printk(KERN_CONT " stepping %02x\n", c->x86_mask);
-        else
-                printk(KERN_CONT "\n");
-}
-
-static __init int setup_disablecpuid(char *arg)
-{
-        int bit;
-        if (get_option(&arg, &bit) && bit < NCAPINTS*32)
-                setup_clear_cpu_cap(bit);
-        else
-                return 0;
-        return 1;
-}
-__setup("clearcpuid=", setup_disablecpuid);
-
-cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
-
-struct x8664_pda **_cpu_pda __read_mostly;
-EXPORT_SYMBOL(_cpu_pda);
-
-struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
-
-char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
-
-unsigned long __supported_pte_mask __read_mostly = ~0UL;
-EXPORT_SYMBOL_GPL(__supported_pte_mask);
-
-static int do_not_nx __cpuinitdata;
-
-/* noexec=on|off
-Control non executable mappings for 64bit processes.
-
-on      Enable(default)
-off     Disable
-*/
-static int __init nonx_setup(char *str)
-{
-        if (!str)
-                return -EINVAL;
-        if (!strncmp(str, "on", 2)) {
-                __supported_pte_mask |= _PAGE_NX;
-                do_not_nx = 0;
-        } else if (!strncmp(str, "off", 3)) {
-                do_not_nx = 1;
-                __supported_pte_mask &= ~_PAGE_NX;
-        }
-        return 0;
-}
-early_param("noexec", nonx_setup);
-
-int force_personality32;
-
-/* noexec32=on|off
-Control non executable heap for 32bit processes.
-To control the stack too use noexec=off
-
-on      PROT_READ does not imply PROT_EXEC for 32bit processes (default)
-off     PROT_READ implies PROT_EXEC
-*/
-static int __init nonx32_setup(char *str)
-{
-        if (!strcmp(str, "on"))
-                force_personality32 &= ~READ_IMPLIES_EXEC;
-        else if (!strcmp(str, "off"))
-                force_personality32 |= READ_IMPLIES_EXEC;
-        return 1;
-}
-__setup("noexec32=", nonx32_setup);
-
-void pda_init(int cpu)
-{
-        struct x8664_pda *pda = cpu_pda(cpu);
-
-        /* Setup up data that may be needed in __get_free_pages early */
-        loadsegment(fs, 0);
-        loadsegment(gs, 0);
-        /* Memory clobbers used to order PDA accessed */
-        mb();
-        wrmsrl(MSR_GS_BASE, pda);
-        mb();
-
-        pda->cpunumber = cpu;
-        pda->irqcount = -1;
-        pda->kernelstack = (unsigned long)stack_thread_info() -
-                                 PDA_STACKOFFSET + THREAD_SIZE;
-        pda->active_mm = &init_mm;
-        pda->mmu_state = 0;
-
-        if (cpu == 0) {
-                /* others are initialized in smpboot.c */
-                pda->pcurrent = &init_task;
-                pda->irqstackptr = boot_cpu_stack;
-                pda->irqstackptr += IRQSTACKSIZE - 64;
-        } else {
-                if (!pda->irqstackptr) {
-                        pda->irqstackptr = (char *)
-                                __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
-                        if (!pda->irqstackptr)
-                                panic("cannot allocate irqstack for cpu %d",
-                                      cpu);
-                        pda->irqstackptr += IRQSTACKSIZE - 64;
-                }
-
-                if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
-                        pda->nodenumber = cpu_to_node(cpu);
-        }
-}
-
-char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
-                           DEBUG_STKSZ] __page_aligned_bss;
-
-extern asmlinkage void ignore_sysret(void);
-
-/* May not be marked __init: used by software suspend */
-void syscall_init(void)
-{
-        /*
-         * LSTAR and STAR live in a bit strange symbiosis.
-         * They both write to the same internal register. STAR allows to
-         * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
-         */
-        wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
-        wrmsrl(MSR_LSTAR, system_call);
-        wrmsrl(MSR_CSTAR, ignore_sysret);
-
-#ifdef CONFIG_IA32_EMULATION
-        syscall32_cpu_init();
-#endif
-
-        /* Flags to clear on syscall */
-        wrmsrl(MSR_SYSCALL_MASK,
-               X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
-}
-
-void __cpuinit check_efer(void)
-{
-        unsigned long efer;
-
-        rdmsrl(MSR_EFER, efer);
-        if (!(efer & EFER_NX) || do_not_nx)
-                __supported_pte_mask &= ~_PAGE_NX;
-}
-
-unsigned long kernel_eflags;
-
-/*
- * Copies of the original ist values from the tss are only accessed during
- * debugging, no special alignment required.
- */
-DEFINE_PER_CPU(struct orig_ist, orig_ist);
-
-/*
- * cpu_init() initializes state that is per-CPU. Some data is already
- * initialized (naturally) in the bootstrap process, such as the GDT
- * and IDT. We reload them nevertheless, this function acts as a
- * 'CPU state barrier', nothing should get across.
- * A lot of state is already set up in PDA init.
- */
-void __cpuinit cpu_init(void)
-{
-        int cpu = stack_smp_processor_id();
-        struct tss_struct *t = &per_cpu(init_tss, cpu);
-        struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
-        unsigned long v;
-        char *estacks = NULL;
-        struct task_struct *me;
-        int i;
-
-        /* CPU 0 is initialised in head64.c */
-        if (cpu != 0)
-                pda_init(cpu);
-        else
-                estacks = boot_exception_stacks;
-
-        me = current;
-
-        if (cpu_test_and_set(cpu, cpu_initialized))
-                panic("CPU#%d already initialized!\n", cpu);
-
-        printk(KERN_INFO "Initializing CPU#%d\n", cpu);
-
-        clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
-
-        /*
-         * Initialize the per-CPU GDT with the boot GDT,
-         * and set up the GDT descriptor:
-         */
-
-        switch_to_new_gdt();
-        load_idt((const struct desc_ptr *)&idt_descr);
-
-        memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
-        syscall_init();
-
-        wrmsrl(MSR_FS_BASE, 0);
-        wrmsrl(MSR_KERNEL_GS_BASE, 0);
-        barrier();
-
-        check_efer();
-
-        /*
-         * set up and load the per-CPU TSS
-         */
-        if (!orig_ist->ist[0]) {
-                static const unsigned int order[N_EXCEPTION_STACKS] = {
-                  [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
-                  [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
-                };
-                for (v = 0; v < N_EXCEPTION_STACKS; v++) {
-                        if (cpu) {
-                                estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
-                                if (!estacks)
-                                        panic("Cannot allocate exception "
-                                              "stack %ld %d\n", v, cpu);
-                        }
-                        estacks += PAGE_SIZE << order[v];
-                        orig_ist->ist[v] = t->x86_tss.ist[v] =
-                                        (unsigned long)estacks;
-                }
-        }
-
-        t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
-        /*
-         * <= is required because the CPU will access up to
-         * 8 bits beyond the end of the IO permission bitmap.
-         */
-        for (i = 0; i <= IO_BITMAP_LONGS; i++)
-                t->io_bitmap[i] = ~0UL;
-
-        atomic_inc(&init_mm.mm_count);
-        me->active_mm = &init_mm;
-        if (me->mm)
-                BUG();
-        enter_lazy_tlb(&init_mm, me);
-
-        load_sp0(t, &current->thread);
-        set_tss_desc(cpu, t);
-        load_TR_desc();
-        load_LDT(&init_mm.context);
-
-#ifdef CONFIG_KGDB
-        /*
-         * If the kgdb is connected no debug regs should be altered.  This
-         * is only applicable when KGDB and a KGDB I/O module are built
-         * into the kernel and you are using early debugging with
-         * kgdbwait. KGDB will control the kernel HW breakpoint registers.
-         */
-        if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
-                arch_kgdb_ops.correct_hw_break();
-        else {
-#endif
-        /*
-         * Clear all 6 debug registers:
-         */
-
-        set_debugreg(0UL, 0);
-        set_debugreg(0UL, 1);
-        set_debugreg(0UL, 2);
-        set_debugreg(0UL, 3);
-        set_debugreg(0UL, 6);
-        set_debugreg(0UL, 7);
-#ifdef CONFIG_KGDB
-        /* If the kgdb is connected no debug regs should be altered. */
-        }
-#endif
-
-        fpu_init();
-
-        raw_local_save_flags(kernel_eflags);
-
-        if (is_uv_system())
-                uv_cpu_init();
-}
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index 4d894e8565fe..de4094a39210 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -21,23 +21,16 @@ struct cpu_dev {
         void            (*c_init)(struct cpuinfo_x86 * c);
         void            (*c_identify)(struct cpuinfo_x86 * c);
         unsigned int    (*c_size_cache)(struct cpuinfo_x86 * c, unsigned int size);
+        int     c_x86_vendor;
 };
 
-extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM];
+#define cpu_dev_register(cpu_devX) \
+        static struct cpu_dev *__cpu_dev_##cpu_devX __used \
+        __attribute__((__section__(".x86_cpu_dev.init"))) = \
+        &cpu_devX;
 
-struct cpu_vendor_dev {
-        int vendor;
-        struct cpu_dev *cpu_dev;
-};
-
-#define cpu_vendor_dev_register(cpu_vendor_id, cpu_dev) \
-        static struct cpu_vendor_dev __cpu_vendor_dev_##cpu_vendor_id __used \
-        __attribute__((__section__(".x86cpuvendor.init"))) = \
-        { cpu_vendor_id, cpu_dev }
-
-extern struct cpu_vendor_dev __x86cpuvendor_start[], __x86cpuvendor_end[];
+extern struct cpu_dev *__x86_cpu_dev_start[], *__x86_cpu_dev_end[];
 
-extern int get_model_name(struct cpuinfo_x86 *c);
 extern void display_cacheinfo(struct cpuinfo_x86 *c);
 
 #endif
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index dd097b835839..c24c4a487b7c 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -256,7 +256,8 @@ static u32 get_cur_val(const cpumask_t *mask)
  * Only IA32_APERF/IA32_MPERF ratio is architecturally defined and
  * no meaning should be associated with absolute values of these MSRs.
  */
-static unsigned int get_measured_perf(unsigned int cpu)
+static unsigned int get_measured_perf(struct cpufreq_policy *policy,
+                                      unsigned int cpu)
 {
         union {
                 struct {
@@ -326,7 +327,7 @@ static unsigned int get_measured_perf(unsigned int cpu)
 
 #endif
 
-        retval = per_cpu(drv_data, cpu)->max_freq * perf_percent / 100;
+        retval = per_cpu(drv_data, policy->cpu)->max_freq * perf_percent / 100;
 
         put_cpu();
         set_cpus_allowed_ptr(current, &saved_mask);
@@ -785,7 +786,11 @@ static int __init acpi_cpufreq_init(void)
         if (ret)
                 return ret;
 
-        return cpufreq_register_driver(&acpi_cpufreq_driver);
+        ret = cpufreq_register_driver(&acpi_cpufreq_driver);
+        if (ret)
+                free_percpu(acpi_perf_data);
+
+        return ret;
 }
 
 static void __exit acpi_cpufreq_exit(void)
@@ -795,8 +800,6 @@ static void __exit acpi_cpufreq_exit(void)
         cpufreq_unregister_driver(&acpi_cpufreq_driver);
 
         free_percpu(acpi_perf_data);
-
-        return;
 }
 
 module_param(acpi_pstate_strict, uint, 0644);
diff --git a/arch/x86/kernel/cpu/cpufreq/elanfreq.c b/arch/x86/kernel/cpu/cpufreq/elanfreq.c
index e4a4bf870e94..fe613c93b366 100644
--- a/arch/x86/kernel/cpu/cpufreq/elanfreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/elanfreq.c
@@ -25,8 +25,8 @@
 #include <linux/cpufreq.h>
 
 #include <asm/msr.h>
-#include <asm/timex.h>
-#include <asm/io.h>
+#include <linux/timex.h>
+#include <linux/io.h>
 
 #define REG_CSCIR 0x22          /* Chip Setup and Control Index Register    */
 #define REG_CSCDR 0x23          /* Chip Setup and Control Data  Register    */
@@ -82,7 +82,7 @@ static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
         u8 clockspeed_reg;    /* Clock Speed Register */
 
         local_irq_disable();
-        outb_p(0x80,REG_CSCIR);
+        outb_p(0x80, REG_CSCIR);
         clockspeed_reg = inb_p(REG_CSCDR);
         local_irq_enable();
 
@@ -98,10 +98,10 @@ static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
         }
 
         /* 33 MHz is not 32 MHz... */
-        if ((clockspeed_reg & 0xE0)==0xA0)
+        if ((clockspeed_reg & 0xE0) == 0xA0)
                 return 33000;
 
-        return ((1<<((clockspeed_reg & 0xE0) >> 5)) * 1000);
+        return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000;
 }
 
 
@@ -117,7 +117,7 @@ static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
  *      There is no return value.
  */
 
-static void elanfreq_set_cpu_state (unsigned int state)
+static void elanfreq_set_cpu_state(unsigned int state)
 {
         struct cpufreq_freqs    freqs;
 
@@ -144,20 +144,20 @@ static void elanfreq_set_cpu_state (unsigned int state)
          */
 
         local_irq_disable();
-        outb_p(0x40,REG_CSCIR);         /* Disable hyperspeed mode */
-        outb_p(0x00,REG_CSCDR);
+        outb_p(0x40, REG_CSCIR);                /* Disable hyperspeed mode */
+        outb_p(0x00, REG_CSCDR);
         local_irq_enable();             /* wait till internal pipelines and */
         udelay(1000);                   /* buffers have cleaned up          */
 
         local_irq_disable();
 
         /* now, set the CPU clock speed register (0x80) */
-        outb_p(0x80,REG_CSCIR);
-        outb_p(elan_multiplier[state].val80h,REG_CSCDR);
+        outb_p(0x80, REG_CSCIR);
+        outb_p(elan_multiplier[state].val80h, REG_CSCDR);
 
         /* now, the hyperspeed bit in PMU Force Mode Register (0x40) */
-        outb_p(0x40,REG_CSCIR);
-        outb_p(elan_multiplier[state].val40h,REG_CSCDR);
+        outb_p(0x40, REG_CSCIR);
+        outb_p(elan_multiplier[state].val40h, REG_CSCDR);
         udelay(10000);
         local_irq_enable();
 
@@ -173,12 +173,12 @@ static void elanfreq_set_cpu_state (unsigned int state)
  *      for the hardware supported by the driver.
  */
 
-static int elanfreq_verify (struct cpufreq_policy *policy)
+static int elanfreq_verify(struct cpufreq_policy *policy)
 {
         return cpufreq_frequency_table_verify(policy, &elanfreq_table[0]);
 }
 
-static int elanfreq_target (struct cpufreq_policy *policy,
+static int elanfreq_target(struct cpufreq_policy *policy,
                             unsigned int target_freq,
                             unsigned int relation)
 {
@@ -205,7 +205,7 @@ static int elanfreq_cpu_init(struct cpufreq_policy *policy)
 
         /* capability check */
         if ((c->x86_vendor != X86_VENDOR_AMD) ||
-            (c->x86 != 4) || (c->x86_model!=10))
+            (c->x86 != 4) || (c->x86_model != 10))
                 return -ENODEV;
 
         /* max freq */
@@ -213,7 +213,7 @@ static int elanfreq_cpu_init(struct cpufreq_policy *policy)
                 max_freq = elanfreq_get_cpu_frequency(0);
 
         /* table init */
-        for (i=0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) {
+        for (i = 0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) {
                 if (elanfreq_table[i].frequency > max_freq)
                         elanfreq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
         }
@@ -224,7 +224,7 @@ static int elanfreq_cpu_init(struct cpufreq_policy *policy)
 
         result = cpufreq_frequency_table_cpuinfo(policy, elanfreq_table);
         if (result)
-                return (result);
+                return result;
 
         cpufreq_frequency_table_get_attr(elanfreq_table, policy->cpu);
         return 0;
@@ -260,7 +260,7 @@ __setup("elanfreq=", elanfreq_setup);
 #endif
 
 
-static struct freq_attr* elanfreq_attr[] = {
+static struct freq_attr *elanfreq_attr[] = {
         &cpufreq_freq_attr_scaling_available_freqs,
         NULL,
 };
@@ -284,9 +284,9 @@ static int __init elanfreq_init(void)
 
         /* Test if we have the right hardware */
         if ((c->x86_vendor != X86_VENDOR_AMD) ||
-                (c->x86 != 4) || (c->x86_model!=10)) {
+                (c->x86 != 4) || (c->x86_model != 10)) {
                 printk(KERN_INFO "elanfreq: error: no Elan processor found!\n");
-                return -ENODEV;
+                return -ENODEV;
         }
         return cpufreq_register_driver(&elanfreq_driver);
 }
@@ -298,7 +298,7 @@ static void __exit elanfreq_exit(void)
 }
 
 
-module_param (max_freq, int, 0444);
+module_param(max_freq, int, 0444);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Robert Schwebel <r.schwebel@pengutronix.de>, Sven Geggus <sven@geggus.net>");
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
index f1685fb91fbd..b8e05ee4f736 100644
--- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
@@ -171,7 +171,7 @@ static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
         }
 
         if (c->x86 != 0xF) {
-                printk(KERN_WARNING PFX "Unknown p4-clockmod-capable CPU. Please send an e-mail to <cpufreq@lists.linux.org.uk>\n");
+                printk(KERN_WARNING PFX "Unknown p4-clockmod-capable CPU. Please send an e-mail to <cpufreq@vger.kernel.org>\n");
                 return 0;
         }
 
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k6.c b/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
index eb9b62b0830c..b5ced806a316 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
@@ -15,12 +15,11 @@
 #include <linux/slab.h>
 
 #include <asm/msr.h>
-#include <asm/timex.h>
-#include <asm/io.h>
+#include <linux/timex.h>
+#include <linux/io.h>
 
-
-#define POWERNOW_IOPORT 0xfff0         /* it doesn't matter where, as long
-                                          as it is unused */
+#define POWERNOW_IOPORT 0xfff0          /* it doesn't matter where, as long
+                                           as it is unused */
 
 static unsigned int                     busfreq;   /* FSB, in 10 kHz */
 static unsigned int                     max_multiplier;
@@ -53,7 +52,7 @@ static int powernow_k6_get_cpu_multiplier(void)
 
         msrval = POWERNOW_IOPORT + 0x1;
         wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
-        invalue=inl(POWERNOW_IOPORT + 0x8);
+        invalue = inl(POWERNOW_IOPORT + 0x8);
         msrval = POWERNOW_IOPORT + 0x0;
         wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
 
@@ -67,9 +66,9 @@ static int powernow_k6_get_cpu_multiplier(void)
  *
  *   Tries to change the PowerNow! multiplier
  */
-static void powernow_k6_set_state (unsigned int best_i)
+static void powernow_k6_set_state(unsigned int best_i)
 {
-        unsigned long           outvalue=0, invalue=0;
+        unsigned long           outvalue = 0, invalue = 0;
         unsigned long           msrval;
         struct cpufreq_freqs    freqs;
 
@@ -90,10 +89,10 @@ static void powernow_k6_set_state (unsigned int best_i)
 
         msrval = POWERNOW_IOPORT + 0x1;
         wrmsr(MSR_K6_EPMR, msrval, 0); /* enable the PowerNow port */
-        invalue=inl(POWERNOW_IOPORT + 0x8);
+        invalue = inl(POWERNOW_IOPORT + 0x8);
         invalue = invalue & 0xf;
         outvalue = outvalue | invalue;
-        outl(outvalue ,(POWERNOW_IOPORT + 0x8));
+        outl(outvalue , (POWERNOW_IOPORT + 0x8));
         msrval = POWERNOW_IOPORT + 0x0;
         wrmsr(MSR_K6_EPMR, msrval, 0); /* disable it again */
 
@@ -124,7 +123,7 @@ static int powernow_k6_verify(struct cpufreq_policy *policy)
  *
  * sets a new CPUFreq policy
  */
-static int powernow_k6_target (struct cpufreq_policy *policy,
+static int powernow_k6_target(struct cpufreq_policy *policy,
                                unsigned int target_freq,
                                unsigned int relation)
 {
@@ -152,7 +151,7 @@ static int powernow_k6_cpu_init(struct cpufreq_policy *policy)
         busfreq = cpu_khz / max_multiplier;
 
         /* table init */
-        for (i=0; (clock_ratio[i].frequency != CPUFREQ_TABLE_END); i++) {
+        for (i = 0; (clock_ratio[i].frequency != CPUFREQ_TABLE_END); i++) {
                 if (clock_ratio[i].index > max_multiplier)
                         clock_ratio[i].frequency = CPUFREQ_ENTRY_INVALID;
                 else
@@ -165,7 +164,7 @@ static int powernow_k6_cpu_init(struct cpufreq_policy *policy)
 
         result = cpufreq_frequency_table_cpuinfo(policy, clock_ratio);
         if (result)
-                return (result);
+                return result;
 
         cpufreq_frequency_table_get_attr(clock_ratio, policy->cpu);
 
@@ -176,8 +175,8 @@ static int powernow_k6_cpu_init(struct cpufreq_policy *policy)
 static int powernow_k6_cpu_exit(struct cpufreq_policy *policy)
 {
         unsigned int i;
-        for (i=0; i<8; i++) {
-                if (i==max_multiplier)
+        for (i = 0; i < 8; i++) {
+                if (i == max_multiplier)
                         powernow_k6_set_state(i);
         }
         cpufreq_frequency_table_put_attr(policy->cpu);
@@ -189,7 +188,7 @@ static unsigned int powernow_k6_get(unsigned int cpu)
         return busfreq * powernow_k6_get_cpu_multiplier();
 }
 
-static struct freq_attr* powernow_k6_attr[] = {
+static struct freq_attr *powernow_k6_attr[] = {
         &cpufreq_freq_attr_scaling_available_freqs,
         NULL,
 };
@@ -227,7 +226,7 @@ static int __init powernow_k6_init(void)
         }
 
         if (cpufreq_register_driver(&powernow_k6_driver)) {
-                release_region (POWERNOW_IOPORT, 16);
+                release_region(POWERNOW_IOPORT, 16);
                 return -EINVAL;
         }
 
@@ -243,13 +242,13 @@ static int __init powernow_k6_init(void)
 static void __exit powernow_k6_exit(void)
 {
         cpufreq_unregister_driver(&powernow_k6_driver);
-        release_region (POWERNOW_IOPORT, 16);
+        release_region(POWERNOW_IOPORT, 16);
 }
 
 
-MODULE_AUTHOR ("Arjan van de Ven <arjanv@redhat.com>, Dave Jones <davej@codemonkey.org.uk>, Dominik Brodowski <linux@brodo.de>");
-MODULE_DESCRIPTION ("PowerNow! driver for AMD K6-2+ / K6-3+ processors.");
-MODULE_LICENSE ("GPL");
+MODULE_AUTHOR("Arjan van de Ven <arjanv@redhat.com>, Dave Jones <davej@codemonkey.org.uk>, Dominik Brodowski <linux@brodo.de>");
+MODULE_DESCRIPTION("PowerNow! driver for AMD K6-2+ / K6-3+ processors.");
+MODULE_LICENSE("GPL");
 
 module_init(powernow_k6_init);
 module_exit(powernow_k6_exit);
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
index 15e13c01cc36..3b5f06423e77 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
@@ -26,7 +26,7 @@
 #include <asm/cpufeature.h>
 
 #define PFX             "speedstep-centrino: "
-#define MAINTAINER      "cpufreq@lists.linux.org.uk"
+#define MAINTAINER      "cpufreq@vger.kernel.org"
 
 #define dprintk(msg...) \
         cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index 898a5a2002ed..ffd0f5ed071a 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -121,7 +121,7 @@ static void __cpuinit set_cx86_reorder(void)
         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
 
         /* Load/Store Serialize to mem access disable (=reorder it) */
-        setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
+        setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);
         /* set load/store serialize from 1GB to 4GB */
         ccr3 |= 0xe0;
         setCx86(CX86_CCR3, ccr3);
@@ -132,11 +132,11 @@ static void __cpuinit set_cx86_memwb(void)
         printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
 
         /* CCR2 bit 2: unlock NW bit */
-        setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
+        setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);
         /* set 'Not Write-through' */
         write_cr0(read_cr0() | X86_CR0_NW);
         /* CCR2 bit 2: lock NW bit and set WT1 */
-        setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14);
+        setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14);
 }
 
 /*
@@ -150,14 +150,14 @@ static void __cpuinit geode_configure(void)
         local_irq_save(flags);
 
         /* Suspend on halt power saving and enable #SUSP pin */
-        setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
+        setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x88);
 
         ccr3 = getCx86(CX86_CCR3);
         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN */
 
 
         /* FPU fast, DTE cache, Mem bypass */
-        setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);
+        setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x38);
         setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
 
         set_cx86_memwb();
@@ -291,7 +291,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                 /* GXm supports extended cpuid levels 'ala' AMD */
                 if (c->cpuid_level == 2) {
                         /* Enable cxMMX extensions (GX1 Datasheet 54) */
-                        setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
+                        setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) | 1);
 
                         /*
                          * GXm : 0x30 ... 0x5f GXm  datasheet 51
@@ -301,7 +301,6 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                          */
                         if ((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <= dir1 && dir1 <= 0x8f))
                                 geode_configure();
-                        get_model_name(c);  /* get CPU marketing name */
                         return;
                 } else { /* MediaGX */
                         Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
@@ -314,7 +313,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                 if (dir1 > 7) {
                         dir0_msn++;  /* M II */
                         /* Enable MMX extensions (App note 108) */
-                        setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
+                        setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1);
                 } else {
                         c->coma_bug = 1;      /* 6x86MX, it has the bug. */
                 }
@@ -429,7 +428,7 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
                         local_irq_save(flags);
                         ccr3 = getCx86(CX86_CCR3);
                         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN  */
-                        setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80);  /* enable cpuid  */
+                        setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80);  /* enable cpuid  */
                         setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
                         local_irq_restore(flags);
                 }
@@ -442,14 +441,16 @@ static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
         .c_early_init   = early_init_cyrix,
         .c_init         = init_cyrix,
         .c_identify     = cyrix_identify,
+        .c_x86_vendor   = X86_VENDOR_CYRIX,
 };
 
-cpu_vendor_dev_register(X86_VENDOR_CYRIX, &cyrix_cpu_dev);
+cpu_dev_register(cyrix_cpu_dev);
 
 static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
         .c_vendor       = "NSC",
         .c_ident        = { "Geode by NSC" },
         .c_init         = init_nsc,
+        .c_x86_vendor   = X86_VENDOR_NSC,
 };
 
-cpu_vendor_dev_register(X86_VENDOR_NSC, &nsc_cpu_dev);
+cpu_dev_register(nsc_cpu_dev);
diff --git a/arch/x86/kernel/cpu/feature_names.c b/arch/x86/kernel/cpu/feature_names.c
deleted file mode 100644
index c9017799497c..000000000000
--- a/arch/x86/kernel/cpu/feature_names.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Strings for the various x86 capability flags.
- *
- * This file must not contain any executable code.
- */
-
-#include <asm/cpufeature.h>
-
-/*
- * These flag bits must match the definitions in <asm/cpufeature.h>.
- * NULL means this bit is undefined or reserved; either way it doesn't
- * have meaning as far as Linux is concerned.  Note that it's important
- * to realize there is a difference between this table and CPUID -- if
- * applications want to get the raw CPUID data, they should access
- * /dev/cpu/<cpu_nr>/cpuid instead.
- */
-const char * const x86_cap_flags[NCAPINTS*32] = {
-        /* Intel-defined */
-        "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
-        "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
-        "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
-        "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
-
-        /* AMD-defined */
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
-        NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
-        "3dnowext", "3dnow",
-
-        /* Transmeta-defined */
-        "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-
-        /* Other (Linux-defined) */
-        "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
-        NULL, NULL, NULL, NULL,
-        "constant_tsc", "up", NULL, "arch_perfmon",
-        "pebs", "bts", NULL, NULL,
-        "rep_good", NULL, NULL, NULL,
-        "nopl", NULL, NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-
-        /* Intel-defined (#2) */
-        "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
-        "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
-        NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-
-        /* VIA/Cyrix/Centaur-defined */
-        NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
-        "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-
-        /* AMD-defined (#2) */
-        "lahf_lm", "cmp_legacy", "svm", "extapic",
-        "cr8_legacy", "abm", "sse4a", "misalignsse",
-        "3dnowprefetch", "osvw", "ibs", "sse5",
-        "skinit", "wdt", NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-
-        /* Auxiliary (Linux-defined) */
-        "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-        NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-};
-
-const char *const x86_power_flags[32] = {
-        "ts",   /* temperature sensor */
-        "fid",  /* frequency id control */
-        "vid",  /* voltage id control */
-        "ttp",  /* thermal trip */
-        "tm",
-        "stc",
-        "100mhzsteps",
-        "hwpstate",
-        "",     /* tsc invariant mapped to constant_tsc */
-                /* nothing */
-};
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b75f2569b8f8..99468dbd08da 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -15,6 +15,11 @@
 #include <asm/ds.h>
 #include <asm/bugs.h>
 
+#ifdef CONFIG_X86_64
+#include <asm/topology.h>
+#include <asm/numa_64.h>
+#endif
+
 #include "cpu.h"
 
 #ifdef CONFIG_X86_LOCAL_APIC
@@ -23,23 +28,22 @@
 #include <mach_apic.h>
 #endif
 
-#ifdef CONFIG_X86_INTEL_USERCOPY
-/*
- * Alignment at which movsl is preferred for bulk memory copies.
- */
-struct movsl_mask movsl_mask __read_mostly;
-#endif
-
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
-        /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
-        if (c->x86 == 15 && c->x86_cache_alignment == 64)
-                c->x86_cache_alignment = 128;
         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+
+#ifdef CONFIG_X86_64
+        set_cpu_cap(c, X86_FEATURE_SYSENTER32);
+#else
+        /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
+        if (c->x86 == 15 && c->x86_cache_alignment == 64)
+                c->x86_cache_alignment = 128;
+#endif
 }
 
+#ifdef CONFIG_X86_32
 /*
  *      Early probe support logic for ppro memory erratum #50
  *
@@ -59,15 +63,54 @@ int __cpuinit ppro_with_ram_bug(void)
         return 0;
 }
 
+#ifdef CONFIG_X86_F00F_BUG
+static void __cpuinit trap_init_f00f_bug(void)
+{
+        __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
 
-/*
- * P4 Xeon errata 037 workaround.
- * Hardware prefetcher may cause stale data to be loaded into the cache.
- */
-static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
+        /*
+         * Update the IDT descriptor and reload the IDT so that
+         * it uses the read-only mapped virtual address.
+         */
+        idt_descr.address = fix_to_virt(FIX_F00F_IDT);
+        load_idt(&idt_descr);
+}
+#endif
+
+static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 {
         unsigned long lo, hi;
 
+#ifdef CONFIG_X86_F00F_BUG
+        /*
+         * All current models of Pentium and Pentium with MMX technology CPUs
+         * have the F0 0F bug, which lets nonprivileged users lock up the system.
+         * Note that the workaround only should be initialized once...
+         */
+        c->f00f_bug = 0;
+        if (!paravirt_enabled() && c->x86 == 5) {
+                static int f00f_workaround_enabled;
+
+                c->f00f_bug = 1;
+                if (!f00f_workaround_enabled) {
+                        trap_init_f00f_bug();
+                        printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
+                        f00f_workaround_enabled = 1;
+                }
+        }
+#endif
+
+        /*
+         * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
+         * model 3 mask 3
+         */
+        if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
+                clear_cpu_cap(c, X86_FEATURE_SEP);
+
+        /*
+         * P4 Xeon errata 037 workaround.
+         * Hardware prefetcher may cause stale data to be loaded into the cache.
+         */
         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
                 if ((lo & (1<<9)) == 0) {
@@ -77,13 +120,68 @@ static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
                 }
         }
+
+        /*
+         * See if we have a good local APIC by checking for buggy Pentia,
+         * i.e. all B steppings and the C2 stepping of P54C when using their
+         * integrated APIC (see 11AP erratum in "Pentium Processor
+         * Specification Update").
+         */
+        if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
+            (c->x86_mask < 0x6 || c->x86_mask == 0xb))
+                set_cpu_cap(c, X86_FEATURE_11AP);
+
+
+#ifdef CONFIG_X86_INTEL_USERCOPY
+        /*
+         * Set up the preferred alignment for movsl bulk memory moves
+         */
+        switch (c->x86) {
+        case 4:         /* 486: untested */
+                break;
+        case 5:         /* Old Pentia: untested */
+                break;
+        case 6:         /* PII/PIII only like movsl with 8-byte alignment */
+                movsl_mask.mask = 7;
+                break;
+        case 15:        /* P4 is OK down to 8-byte alignment */
+                movsl_mask.mask = 7;
+                break;
+        }
+#endif
+
+#ifdef CONFIG_X86_NUMAQ
+        numaq_tsc_disable();
+#endif
 }
+#else
+static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
+{
+}
+#endif
 
+static void __cpuinit srat_detect_node(void)
+{
+#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
+        unsigned node;
+        int cpu = smp_processor_id();
+        int apicid = hard_smp_processor_id();
+
+        /* Don't do the funky fallback heuristics the AMD version employs
+           for now. */
+        node = apicid_to_node[apicid];
+        if (node == NUMA_NO_NODE || !node_online(node))
+                node = first_node(node_online_map);
+        numa_set_node(cpu, node);
+
+        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
+#endif
+}
 
 /*
  * find out the number of processor cores on the die
  */
-static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c)
+static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 {
         unsigned int eax, ebx, ecx, edx;
 
@@ -98,45 +196,51 @@ static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c)
                 return 1;
 }
 
-#ifdef CONFIG_X86_F00F_BUG
-static void __cpuinit trap_init_f00f_bug(void)
+static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 {
-        __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
-
-        /*
-         * Update the IDT descriptor and reload the IDT so that
-         * it uses the read-only mapped virtual address.
-         */
-        idt_descr.address = fix_to_virt(FIX_F00F_IDT);
-        load_idt(&idt_descr);
+        /* Intel VMX MSR indicated features */
+#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
+#define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
+#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
+#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
+#define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
+#define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
+
+        u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
+
+        clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
+        clear_cpu_cap(c, X86_FEATURE_VNMI);
+        clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
+        clear_cpu_cap(c, X86_FEATURE_EPT);
+        clear_cpu_cap(c, X86_FEATURE_VPID);
+
+        rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
+        msr_ctl = vmx_msr_high | vmx_msr_low;
+        if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
+                set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
+        if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
+                set_cpu_cap(c, X86_FEATURE_VNMI);
+        if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
+                rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
+                      vmx_msr_low, vmx_msr_high);
+                msr_ctl2 = vmx_msr_high | vmx_msr_low;
+                if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
+                    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
+                        set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
+                if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
+                        set_cpu_cap(c, X86_FEATURE_EPT);
+                if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
+                        set_cpu_cap(c, X86_FEATURE_VPID);
+        }
 }
-#endif
 
 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 {
         unsigned int l2 = 0;
-        char *p = NULL;
 
         early_init_intel(c);
 
-#ifdef CONFIG_X86_F00F_BUG
-        /*
-         * All current models of Pentium and Pentium with MMX technology CPUs
-         * have the F0 0F bug, which lets nonprivileged users lock up the system.
-         * Note that the workaround only should be initialized once...
-         */
-        c->f00f_bug = 0;
-        if (!paravirt_enabled() && c->x86 == 5) {
-                static int f00f_workaround_enabled;
-
-                c->f00f_bug = 1;
-                if (!f00f_workaround_enabled) {
-                        trap_init_f00f_bug();
-                        printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
-                        f00f_workaround_enabled = 1;
-                }
-        }
-#endif
+        intel_workarounds(c);
 
         l2 = init_intel_cacheinfo(c);
         if (c->cpuid_level > 9) {
@@ -146,16 +250,32 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
         }
 
-        /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
-        if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
-                clear_cpu_cap(c, X86_FEATURE_SEP);
+        if (cpu_has_xmm2)
+                set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
+        if (cpu_has_ds) {
+                unsigned int l1;
+                rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
+                if (!(l1 & (1<<11)))
+                        set_cpu_cap(c, X86_FEATURE_BTS);
+                if (!(l1 & (1<<12)))
+                        set_cpu_cap(c, X86_FEATURE_PEBS);
+                ds_init_intel(c);
+        }
 
+#ifdef CONFIG_X86_64
+        if (c->x86 == 15)
+                c->x86_cache_alignment = c->x86_clflush_size * 2;
+        if (c->x86 == 6)
+                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+#else
         /*
          * Names for the Pentium II/Celeron processors
          * detectable only by also checking the cache size.
          * Dixon is NOT a Celeron.
          */
         if (c->x86 == 6) {
+                char *p = NULL;
+
                 switch (c->x86_model) {
                 case 5:
                         if (c->x86_mask == 0) {
@@ -178,70 +298,41 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                                 p = "Celeron (Coppermine)";
                         break;
                 }
-        }
-
-        if (p)
-                strcpy(c->x86_model_id, p);
-
-        c->x86_max_cores = num_cpu_cores(c);
-
-        detect_ht(c);
 
-        /* Work around errata */
-        Intel_errata_workarounds(c);
-
-#ifdef CONFIG_X86_INTEL_USERCOPY
-        /*
-         * Set up the preferred alignment for movsl bulk memory moves
-         */
-        switch (c->x86) {
-        case 4:         /* 486: untested */
-                break;
-        case 5:         /* Old Pentia: untested */
-                break;
-        case 6:         /* PII/PIII only like movsl with 8-byte alignment */
-                movsl_mask.mask = 7;
-                break;
-        case 15:        /* P4 is OK down to 8-byte alignment */
-                movsl_mask.mask = 7;
-                break;
+                if (p)
+                        strcpy(c->x86_model_id, p);
         }
-#endif
 
-        if (cpu_has_xmm2)
-                set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
-        if (c->x86 == 15) {
+        if (c->x86 == 15)
                 set_cpu_cap(c, X86_FEATURE_P4);
-        }
         if (c->x86 == 6)
                 set_cpu_cap(c, X86_FEATURE_P3);
-        if (cpu_has_ds) {
-                unsigned int l1;
-                rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
-                if (!(l1 & (1<<11)))
-                        set_cpu_cap(c, X86_FEATURE_BTS);
-                if (!(l1 & (1<<12)))
-                        set_cpu_cap(c, X86_FEATURE_PEBS);
-        }
 
         if (cpu_has_bts)
-                ds_init_intel(c);
+                ptrace_bts_init_intel(c);
 
-        /*
-         * See if we have a good local APIC by checking for buggy Pentia,
-         * i.e. all B steppings and the C2 stepping of P54C when using their
-         * integrated APIC (see 11AP erratum in "Pentium Processor
-         * Specification Update").
-         */
-        if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
-            (c->x86_mask < 0x6 || c->x86_mask == 0xb))
-                set_cpu_cap(c, X86_FEATURE_11AP);
+#endif
 
-#ifdef CONFIG_X86_NUMAQ
-        numaq_tsc_disable();
+        detect_extended_topology(c);
+        if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
+                /*
+                 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
+                 * detection.
+                 */
+                c->x86_max_cores = intel_num_cpu_cores(c);
+#ifdef CONFIG_X86_32
+                detect_ht(c);
 #endif
+        }
+
+        /* Work around errata */
+        srat_detect_node();
+
+        if (cpu_has(c, X86_FEATURE_VMX))
+                detect_vmx_virtcap(c);
 }
 
+#ifdef CONFIG_X86_32
 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 {
         /*
@@ -254,10 +345,12 @@ static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned i
                 size = 256;
         return size;
 }
+#endif
 
 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
         .c_vendor       = "Intel",
         .c_ident        = { "GenuineIntel" },
+#ifdef CONFIG_X86_32
         .c_models = {
                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
                   {
@@ -307,76 +400,12 @@ static struct cpu_dev intel_cpu_dev __cpuinitdata = {
                   }
                 },
         },
+        .c_size_cache   = intel_size_cache,
+#endif
         .c_early_init   = early_init_intel,
         .c_init         = init_intel,
-        .c_size_cache   = intel_size_cache,
+        .c_x86_vendor   = X86_VENDOR_INTEL,
 };
 
-cpu_vendor_dev_register(X86_VENDOR_INTEL, &intel_cpu_dev);
-
-#ifndef CONFIG_X86_CMPXCHG
-unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
-{
-        u8 prev;
-        unsigned long flags;
-
-        /* Poor man's cmpxchg for 386. Unsuitable for SMP */
-        local_irq_save(flags);
-        prev = *(u8 *)ptr;
-        if (prev == old)
-                *(u8 *)ptr = new;
-        local_irq_restore(flags);
-        return prev;
-}
-EXPORT_SYMBOL(cmpxchg_386_u8);
-
-unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
-{
-        u16 prev;
-        unsigned long flags;
-
-        /* Poor man's cmpxchg for 386. Unsuitable for SMP */
-        local_irq_save(flags);
-        prev = *(u16 *)ptr;
-        if (prev == old)
-                *(u16 *)ptr = new;
-        local_irq_restore(flags);
-        return prev;
-}
-EXPORT_SYMBOL(cmpxchg_386_u16);
-
-unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
-{
-        u32 prev;
-        unsigned long flags;
-
-        /* Poor man's cmpxchg for 386. Unsuitable for SMP */
-        local_irq_save(flags);
-        prev = *(u32 *)ptr;
-        if (prev == old)
-                *(u32 *)ptr = new;
-        local_irq_restore(flags);
-        return prev;
-}
-EXPORT_SYMBOL(cmpxchg_386_u32);
-#endif
-
-#ifndef CONFIG_X86_CMPXCHG64
-unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
-{
-        u64 prev;
-        unsigned long flags;
-
-        /* Poor man's cmpxchg8b for 386 and 486. Unsuitable for SMP */
-        local_irq_save(flags);
-        prev = *(u64 *)ptr;
-        if (prev == old)
-                *(u64 *)ptr = new;
-        local_irq_restore(flags);
-        return prev;
-}
-EXPORT_SYMBOL(cmpxchg_486_u64);
-#endif
-
-/* arch_initcall(intel_cpu_init); */
+cpu_dev_register(intel_cpu_dev);
 
diff --git a/arch/x86/kernel/cpu/intel_64.c b/arch/x86/kernel/cpu/intel_64.c
deleted file mode 100644
index 1019c58d39f0..000000000000
--- a/arch/x86/kernel/cpu/intel_64.c
+++ /dev/null
@@ -1,95 +0,0 @@
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <asm/processor.h>
-#include <asm/ptrace.h>
-#include <asm/topology.h>
-#include <asm/numa_64.h>
-
-#include "cpu.h"
-
-static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
-{
-        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
-            (c->x86 == 0x6 && c->x86_model >= 0x0e))
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-
-        set_cpu_cap(c, X86_FEATURE_SYSENTER32);
-}
-
-/*
- * find out the number of processor cores on the die
- */
-static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
-{
-        unsigned int eax, t;
-
-        if (c->cpuid_level < 4)
-                return 1;
-
-        cpuid_count(4, 0, &eax, &t, &t, &t);
-
-        if (eax & 0x1f)
-                return ((eax >> 26) + 1);
-        else
-                return 1;
-}
-
-static void __cpuinit srat_detect_node(void)
-{
-#ifdef CONFIG_NUMA
-        unsigned node;
-        int cpu = smp_processor_id();
-        int apicid = hard_smp_processor_id();
-
-        /* Don't do the funky fallback heuristics the AMD version employs
-           for now. */
-        node = apicid_to_node[apicid];
-        if (node == NUMA_NO_NODE || !node_online(node))
-                node = first_node(node_online_map);
-        numa_set_node(cpu, node);
-
-        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
-#endif
-}
-
-static void __cpuinit init_intel(struct cpuinfo_x86 *c)
-{
-        init_intel_cacheinfo(c);
-        if (c->cpuid_level > 9) {
-                unsigned eax = cpuid_eax(10);
-                /* Check for version and the number of counters */
-                if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
-                        set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
-        }
-
-        if (cpu_has_ds) {
-                unsigned int l1, l2;
-                rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
-                if (!(l1 & (1<<11)))
-                        set_cpu_cap(c, X86_FEATURE_BTS);
-                if (!(l1 & (1<<12)))
-                        set_cpu_cap(c, X86_FEATURE_PEBS);
-        }
-
-
-        if (cpu_has_bts)
-                ds_init_intel(c);
-
-        if (c->x86 == 15)
-                c->x86_cache_alignment = c->x86_clflush_size * 2;
-        if (c->x86 == 6)
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-        set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
-        c->x86_max_cores = intel_num_cpu_cores(c);
-
-        srat_detect_node();
-}
-
-static struct cpu_dev intel_cpu_dev __cpuinitdata = {
-        .c_vendor       = "Intel",
-        .c_ident        = { "GenuineIntel" },
-        .c_early_init   = early_init_intel,
-        .c_init         = init_intel,
-};
-cpu_vendor_dev_register(X86_VENDOR_INTEL, &intel_cpu_dev);
-
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 6b0a10b002f1..3f46afbb1cf1 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -1,8 +1,8 @@
 /*
- *      Routines to indentify caches on Intel CPU.
+ *      Routines to indentify caches on Intel CPU.
  *
- *      Changes:
- *      Venkatesh Pallipadi     : Adding cache identification through cpuid(4)
+ *      Changes:
+ *      Venkatesh Pallipadi     : Adding cache identification through cpuid(4)
  *              Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
  *      Andi Kleen / Andreas Herrmann   : CPUID4 emulation on AMD.
  */
@@ -13,6 +13,7 @@
 #include <linux/compiler.h>
 #include <linux/cpu.h>
 #include <linux/sched.h>
+#include <linux/pci.h>
 
 #include <asm/processor.h>
 #include <asm/smp.h>
@@ -130,9 +131,18 @@ struct _cpuid4_info {
         union _cpuid4_leaf_ebx ebx;
         union _cpuid4_leaf_ecx ecx;
         unsigned long size;
+        unsigned long can_disable;
         cpumask_t shared_cpu_map;       /* future?: only cpus/node is needed */
 };
 
+#ifdef CONFIG_PCI
+static struct pci_device_id k8_nb_id[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
+        {}
+};
+#endif
+
 unsigned short                  num_cache_leaves;
 
 /* AMD doesn't have CPUID4. Emulate it here to report the same
@@ -182,9 +192,10 @@ static unsigned short assocs[] __cpuinitdata = {
 static unsigned char levels[] __cpuinitdata = { 1, 1, 2, 3 };
 static unsigned char types[] __cpuinitdata = { 1, 2, 3, 3 };
 
-static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
-                       union _cpuid4_leaf_ebx *ebx,
-                       union _cpuid4_leaf_ecx *ecx)
+static void __cpuinit
+amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
+                     union _cpuid4_leaf_ebx *ebx,
+                     union _cpuid4_leaf_ecx *ecx)
 {
         unsigned dummy;
         unsigned line_size, lines_per_tag, assoc, size_in_kb;
@@ -251,27 +262,40 @@ static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
                 (ebx->split.ways_of_associativity + 1) - 1;
 }
 
-static int __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
+static void __cpuinit
+amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
+{
+        if (index < 3)
+                return;
+        this_leaf->can_disable = 1;
+}
+
+static int
+__cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
 {
         union _cpuid4_leaf_eax  eax;
         union _cpuid4_leaf_ebx  ebx;
         union _cpuid4_leaf_ecx  ecx;
         unsigned                edx;
 
-        if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+        if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
                 amd_cpuid4(index, &eax, &ebx, &ecx);
-        else
-                cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full,  &edx);
+                if (boot_cpu_data.x86 >= 0x10)
+                        amd_check_l3_disable(index, this_leaf);
+        } else {
+                cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
+        }
+
         if (eax.split.type == CACHE_TYPE_NULL)
                 return -EIO; /* better error ? */
 
         this_leaf->eax = eax;
         this_leaf->ebx = ebx;
         this_leaf->ecx = ecx;
-        this_leaf->size = (ecx.split.number_of_sets + 1) *
-                (ebx.split.coherency_line_size + 1) *
-                (ebx.split.physical_line_partition + 1) *
-                (ebx.split.ways_of_associativity + 1);
+        this_leaf->size = (ecx.split.number_of_sets          + 1) *
+                          (ebx.split.coherency_line_size     + 1) *
+                          (ebx.split.physical_line_partition + 1) *
+                          (ebx.split.ways_of_associativity   + 1);
         return 0;
 }
 
@@ -453,7 +477,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 
 /* pointer to _cpuid4_info array (for each cache leaf) */
 static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
-#define CPUID4_INFO_IDX(x, y)    (&((per_cpu(cpuid4_info, x))[y]))
+#define CPUID4_INFO_IDX(x, y)   (&((per_cpu(cpuid4_info, x))[y]))
 
 #ifdef CONFIG_SMP
 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
@@ -490,7 +514,7 @@ static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
 
         this_leaf = CPUID4_INFO_IDX(cpu, index);
         for_each_cpu_mask_nr(sibling, this_leaf->shared_cpu_map) {
-                sibling_leaf = CPUID4_INFO_IDX(sibling, index); 
+                sibling_leaf = CPUID4_INFO_IDX(sibling, index);
                 cpu_clear(cpu, sibling_leaf->shared_cpu_map);
         }
 }
@@ -572,7 +596,7 @@ struct _index_kobject {
 
 /* pointer to array of kobjects for cpuX/cache/indexY */
 static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
-#define INDEX_KOBJECT_PTR(x, y)    (&((per_cpu(index_kobject, x))[y]))
+#define INDEX_KOBJECT_PTR(x, y)         (&((per_cpu(index_kobject, x))[y]))
 
 #define show_one_plus(file_name, object, val)                           \
 static ssize_t show_##file_name                                         \
@@ -637,6 +661,99 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) {
         }
 }
 
+#define to_object(k)    container_of(k, struct _index_kobject, kobj)
+#define to_attr(a)      container_of(a, struct _cache_attr, attr)
+
+#ifdef CONFIG_PCI
+static struct pci_dev *get_k8_northbridge(int node)
+{
+        struct pci_dev *dev = NULL;
+        int i;
+
+        for (i = 0; i <= node; i++) {
+                do {
+                        dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
+                        if (!dev)
+                                break;
+                } while (!pci_match_id(&k8_nb_id[0], dev));
+                if (!dev)
+                        break;
+        }
+        return dev;
+}
+#else
+static struct pci_dev *get_k8_northbridge(int node)
+{
+        return NULL;
+}
+#endif
+
+static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
+{
+        int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
+        struct pci_dev *dev = NULL;
+        ssize_t ret = 0;
+        int i;
+
+        if (!this_leaf->can_disable)
+                return sprintf(buf, "Feature not enabled\n");
+
+        dev = get_k8_northbridge(node);
+        if (!dev) {
+                printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
+                return -EINVAL;
+        }
+
+        for (i = 0; i < 2; i++) {
+                unsigned int reg;
+
+                pci_read_config_dword(dev, 0x1BC + i * 4, &reg);
+
+                ret += sprintf(buf, "%sEntry: %d\n", buf, i);
+                ret += sprintf(buf, "%sReads:  %s\tNew Entries: %s\n",  
+                        buf,
+                        reg & 0x80000000 ? "Disabled" : "Allowed",
+                        reg & 0x40000000 ? "Disabled" : "Allowed");
+                ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n",
+                        buf, (reg & 0x30000) >> 16, reg & 0xfff);
+        }
+        return ret;
+}
+
+static ssize_t
+store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
+                    size_t count)
+{
+        int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
+        struct pci_dev *dev = NULL;
+        unsigned int ret, index, val;
+
+        if (!this_leaf->can_disable)
+                return 0;
+
+        if (strlen(buf) > 15)
+                return -EINVAL;
+
+        ret = sscanf(buf, "%x %x", &index, &val);
+        if (ret != 2)
+                return -EINVAL;
+        if (index > 1)
+                return -EINVAL;
+
+        val |= 0xc0000000;
+        dev = get_k8_northbridge(node);
+        if (!dev) {
+                printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
+                return -EINVAL;
+        }
+
+        pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
+        wbinvd();
+        pci_write_config_dword(dev, 0x1BC + index * 4, val);
+
+        return 1;
+}
+
 struct _cache_attr {
         struct attribute attr;
         ssize_t (*show)(struct _cpuid4_info *, char *);
@@ -657,6 +774,8 @@ define_one_ro(size);
 define_one_ro(shared_cpu_map);
 define_one_ro(shared_cpu_list);
 
+static struct _cache_attr cache_disable = __ATTR(cache_disable, 0644, show_cache_disable, store_cache_disable);
+
 static struct attribute * default_attrs[] = {
         &type.attr,
         &level.attr,
@@ -667,12 +786,10 @@ static struct attribute * default_attrs[] = {
         &size.attr,
         &shared_cpu_map.attr,
         &shared_cpu_list.attr,
+        &cache_disable.attr,
         NULL
 };
 
-#define to_object(k) container_of(k, struct _index_kobject, kobj)
-#define to_attr(a) container_of(a, struct _cache_attr, attr)
-
 static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
 {
         struct _cache_attr *fattr = to_attr(attr);
@@ -682,14 +799,22 @@ static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
         ret = fattr->show ?
                 fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
                         buf) :
-                0;
+                0;
         return ret;
 }
 
 static ssize_t store(struct kobject * kobj, struct attribute * attr,
                      const char * buf, size_t count)
 {
-        return 0;
+        struct _cache_attr *fattr = to_attr(attr);
+        struct _index_kobject *this_leaf = to_object(kobj);
+        ssize_t ret;
+
+        ret = fattr->store ?
+                fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
+                        buf, count) :
+                0;
+        return ret;
 }
 
 static struct sysfs_ops sysfs_ops = {
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c
index 726a5fcdf341..4b031a4ac856 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_64.c
@@ -860,7 +860,7 @@ error:
         return err;
 }
 
-static void mce_remove_device(unsigned int cpu)
+static __cpuinit void mce_remove_device(unsigned int cpu)
 {
         int i;
 
diff --git a/arch/x86/kernel/cpu/mkcapflags.pl b/arch/x86/kernel/cpu/mkcapflags.pl
new file mode 100644
index 000000000000..dfea390e1608
--- /dev/null
+++ b/arch/x86/kernel/cpu/mkcapflags.pl
@@ -0,0 +1,32 @@
+#!/usr/bin/perl
+#
+# Generate the x86_cap_flags[] array from include/asm-x86/cpufeature.h
+#
+
+($in, $out) = @ARGV;
+
+open(IN, "< $in\0")   or die "$0: cannot open: $in: $!\n";
+open(OUT, "> $out\0") or die "$0: cannot create: $out: $!\n";
+
+print OUT "#include <asm/cpufeature.h>\n\n";
+print OUT "const char * const x86_cap_flags[NCAPINTS*32] = {\n";
+
+while (defined($line = <IN>)) {
+        if ($line =~ /^\s*\#\s*define\s+(X86_FEATURE_(\S+))\s+(.*)$/) {
+                $macro = $1;
+                $feature = $2;
+                $tail = $3;
+                if ($tail =~ /\/\*\s*\"([^"]*)\".*\*\//) {
+                        $feature = $1;
+                }
+
+                if ($feature ne '') {
+                        printf OUT "\t%-32s = \"%s\",\n",
+                                "[$macro]", "\L$feature";
+                }
+        }
+}
+print OUT "};\n";
+
+close(IN);
+close(OUT);
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index cb7d3b6a80eb..4e8d77f01eeb 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -401,12 +401,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
                 tmp |= ~((1<<(hi - 1)) - 1);
 
                 if (tmp != mask_lo) {
-                        static int once = 1;
-
-                        if (once) {
-                                printk(KERN_INFO "mtrr: your BIOS has set up an incorrect mask, fixing it up.\n");
-                                once = 0;
-                        }
+                        WARN_ONCE(1, KERN_INFO "mtrr: your BIOS has set up an incorrect mask, fixing it up.\n");
                         mask_lo = tmp;
                 }
         }
diff --git a/arch/x86/kernel/cpu/mtrr/if.c b/arch/x86/kernel/cpu/mtrr/if.c
index 84c480bb3715..4c4214690dd1 100644
--- a/arch/x86/kernel/cpu/mtrr/if.c
+++ b/arch/x86/kernel/cpu/mtrr/if.c
@@ -405,9 +405,9 @@ static int mtrr_seq_show(struct seq_file *seq, void *offset)
                         }
                         /* RED-PEN: base can be > 32bit */ 
                         len += seq_printf(seq, 
-                                   "reg%02i: base=0x%05lx000 (%4luMB), size=%4lu%cB: %s, count=%d\n",
+                                   "reg%02i: base=0x%06lx000 (%5luMB), size=%5lu%cB, count=%d: %s\n",
                              i, base, base >> (20 - PAGE_SHIFT), size, factor,
-                             mtrr_attrib_to_str(type), mtrr_usage_table[i]);
+                             mtrr_usage_table[i], mtrr_attrib_to_str(type));
                 }
         }
         return 0;
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index b117d7f8a564..c78c04821ea1 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -729,7 +729,7 @@ struct var_mtrr_range_state {
         mtrr_type type;
 };
 
-struct var_mtrr_range_state __initdata range_state[RANGE_NUM];
+static struct var_mtrr_range_state __initdata range_state[RANGE_NUM];
 static int __initdata debug_print;
 
 static int __init
@@ -759,7 +759,8 @@ x86_get_mtrr_mem_range(struct res_range *range, int nr_range,
         /* take out UC ranges */
         for (i = 0; i < num_var_ranges; i++) {
                 type = range_state[i].type;
-                if (type != MTRR_TYPE_UNCACHABLE)
+                if (type != MTRR_TYPE_UNCACHABLE &&
+                    type != MTRR_TYPE_WRPROT)
                         continue;
                 size = range_state[i].size_pfn;
                 if (!size)
@@ -834,7 +835,14 @@ static int __init enable_mtrr_cleanup_setup(char *str)
                 enable_mtrr_cleanup = 1;
         return 0;
 }
-early_param("enble_mtrr_cleanup", enable_mtrr_cleanup_setup);
+early_param("enable_mtrr_cleanup", enable_mtrr_cleanup_setup);
+
+static int __init mtrr_cleanup_debug_setup(char *str)
+{
+        debug_print = 1;
+        return 0;
+}
+early_param("mtrr_cleanup_debug", mtrr_cleanup_debug_setup);
 
 struct var_mtrr_state {
         unsigned long   range_startk;
@@ -898,6 +906,27 @@ set_var_mtrr_all(unsigned int address_bits)
         }
 }
 
+static unsigned long to_size_factor(unsigned long sizek, char *factorp)
+{
+        char factor;
+        unsigned long base = sizek;
+
+        if (base & ((1<<10) - 1)) {
+                /* not MB alignment */
+                factor = 'K';
+        } else if (base & ((1<<20) - 1)){
+                factor = 'M';
+                base >>= 10;
+        } else {
+                factor = 'G';
+                base >>= 20;
+        }
+
+        *factorp = factor;
+
+        return base;
+}
+
 static unsigned int __init
 range_to_mtrr(unsigned int reg, unsigned long range_startk,
               unsigned long range_sizek, unsigned char type)
@@ -919,13 +948,21 @@ range_to_mtrr(unsigned int reg, unsigned long range_startk,
                         align = max_align;
 
                 sizek = 1 << align;
-                if (debug_print)
+                if (debug_print) {
+                        char start_factor = 'K', size_factor = 'K';
+                        unsigned long start_base, size_base;
+
+                        start_base = to_size_factor(range_startk, &start_factor),
+                        size_base = to_size_factor(sizek, &size_factor),
+
                         printk(KERN_DEBUG "Setting variable MTRR %d, "
-                                "base: %ldMB, range: %ldMB, type %s\n",
-                                reg, range_startk >> 10, sizek >> 10,
+                                "base: %ld%cB, range: %ld%cB, type %s\n",
+                                reg, start_base, start_factor,
+                                size_base, size_factor,
                                 (type == MTRR_TYPE_UNCACHABLE)?"UC":
                                     ((type == MTRR_TYPE_WRBACK)?"WB":"Other")
                                 );
+                }
                 save_var_mtrr(reg++, range_startk, sizek, type);
                 range_startk += sizek;
                 range_sizek -= sizek;
@@ -970,6 +1007,8 @@ range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek,
         /* try to append some small hole */
         range0_basek = state->range_startk;
         range0_sizek = ALIGN(state->range_sizek, chunk_sizek);
+
+        /* no increase */
         if (range0_sizek == state->range_sizek) {
                 if (debug_print)
                         printk(KERN_DEBUG "rangeX: %016lx - %016lx\n",
@@ -980,13 +1019,40 @@ range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek,
                 return 0;
         }
 
-        range0_sizek -= chunk_sizek;
-        if (range0_sizek && sizek) {
-            while (range0_basek + range0_sizek > (basek + sizek)) {
-                range0_sizek -= chunk_sizek;
-                if (!range0_sizek)
-                        break;
-            }
+        /* only cut back, when it is not the last */
+        if (sizek) {
+                while (range0_basek + range0_sizek > (basek + sizek)) {
+                        if (range0_sizek >= chunk_sizek)
+                                range0_sizek -= chunk_sizek;
+                        else
+                                range0_sizek = 0;
+
+                        if (!range0_sizek)
+                                break;
+                }
+        }
+
+second_try:
+        range_basek = range0_basek + range0_sizek;
+
+        /* one hole in the middle */
+        if (range_basek > basek && range_basek <= (basek + sizek))
+                second_sizek = range_basek - basek;
+
+        if (range0_sizek > state->range_sizek) {
+
+                /* one hole in middle or at end */
+                hole_sizek = range0_sizek - state->range_sizek - second_sizek;
+
+                /* hole size should be less than half of range0 size */
+                if (hole_sizek >= (range0_sizek >> 1) &&
+                    range0_sizek >= chunk_sizek) {
+                        range0_sizek -= chunk_sizek;
+                        second_sizek = 0;
+                        hole_sizek = 0;
+
+                        goto second_try;
+                }
         }
 
         if (range0_sizek) {
@@ -996,50 +1062,28 @@ range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek,
                                 (range0_basek + range0_sizek)<<10);
                 state->reg = range_to_mtrr(state->reg, range0_basek,
                                 range0_sizek, MTRR_TYPE_WRBACK);
-
-        }
-
-        range_basek = range0_basek + range0_sizek;
-        range_sizek = chunk_sizek;
-
-        if (range_basek + range_sizek > basek &&
-            range_basek + range_sizek <= (basek + sizek)) {
-                /* one hole */
-                second_basek = basek;
-                second_sizek = range_basek + range_sizek - basek;
         }
 
-        /* if last piece, only could one hole near end */
-        if ((second_basek || !basek) &&
-            range_sizek - (state->range_sizek - range0_sizek) - second_sizek <
-            (chunk_sizek >> 1)) {
-                /*
-                 * one hole in middle (second_sizek is 0) or at end
-                 * (second_sizek is 0 )
-                 */
-                hole_sizek = range_sizek - (state->range_sizek - range0_sizek)
-                                 - second_sizek;
-                hole_basek = range_basek + range_sizek - hole_sizek
-                                 - second_sizek;
-        } else {
-                /* fallback for big hole, or several holes */
+        if (range0_sizek < state->range_sizek) {
+                /* need to handle left over */
                 range_sizek = state->range_sizek - range0_sizek;
-                second_basek = 0;
-                second_sizek = 0;
+
+                if (debug_print)
+                        printk(KERN_DEBUG "range: %016lx - %016lx\n",
+                                 range_basek<<10,
+                                 (range_basek + range_sizek)<<10);
+                state->reg = range_to_mtrr(state->reg, range_basek,
+                                 range_sizek, MTRR_TYPE_WRBACK);
         }
 
-        if (debug_print)
-                printk(KERN_DEBUG "range: %016lx - %016lx\n", range_basek<<10,
-                         (range_basek + range_sizek)<<10);
-        state->reg = range_to_mtrr(state->reg, range_basek, range_sizek,
-                                         MTRR_TYPE_WRBACK);
         if (hole_sizek) {
+                hole_basek = range_basek - hole_sizek - second_sizek;
                 if (debug_print)
                         printk(KERN_DEBUG "hole: %016lx - %016lx\n",
-                                 hole_basek<<10, (hole_basek + hole_sizek)<<10);
-                state->reg = range_to_mtrr(state->reg, hole_basek, hole_sizek,
-                                                 MTRR_TYPE_UNCACHABLE);
-
+                                 hole_basek<<10,
+                                 (hole_basek + hole_sizek)<<10);
+                state->reg = range_to_mtrr(state->reg, hole_basek,
+                                 hole_sizek, MTRR_TYPE_UNCACHABLE);
         }
 
         return second_sizek;
@@ -1154,11 +1198,11 @@ struct mtrr_cleanup_result {
 };
 
 /*
- * gran_size: 1M, 2M, ..., 2G
- * chunk size: gran_size, ..., 4G
- * so we need (2+13)*6
+ * gran_size: 64K, 128K, 256K, 512K, 1M, 2M, ..., 2G
+ * chunk size: gran_size, ..., 2G
+ * so we need (1+16)*8
  */
-#define NUM_RESULT      90
+#define NUM_RESULT      136
 #define PSHIFT          (PAGE_SHIFT - 10)
 
 static struct mtrr_cleanup_result __initdata result[NUM_RESULT];
@@ -1168,13 +1212,14 @@ static unsigned long __initdata min_loss_pfn[RANGE_NUM];
 static int __init mtrr_cleanup(unsigned address_bits)
 {
         unsigned long extra_remove_base, extra_remove_size;
-        unsigned long i, base, size, def, dummy;
+        unsigned long base, size, def, dummy;
         mtrr_type type;
         int nr_range, nr_range_new;
         u64 chunk_size, gran_size;
         unsigned long range_sums, range_sums_new;
         int index_good;
         int num_reg_good;
+        int i;
 
         /* extra one for all 0 */
         int num[MTRR_NUM_TYPES + 1];
@@ -1204,6 +1249,8 @@ static int __init mtrr_cleanup(unsigned address_bits)
                         continue;
                 if (!size)
                         type = MTRR_NUM_TYPES;
+                if (type == MTRR_TYPE_WRPROT)
+                        type = MTRR_TYPE_UNCACHABLE;
                 num[type]++;
         }
 
@@ -1216,23 +1263,57 @@ static int __init mtrr_cleanup(unsigned address_bits)
                 num_var_ranges - num[MTRR_NUM_TYPES])
                 return 0;
 
+        /* print original var MTRRs at first, for debugging: */
+        printk(KERN_DEBUG "original variable MTRRs\n");
+        for (i = 0; i < num_var_ranges; i++) {
+                char start_factor = 'K', size_factor = 'K';
+                unsigned long start_base, size_base;
+
+                size_base = range_state[i].size_pfn << (PAGE_SHIFT - 10);
+                if (!size_base)
+                        continue;
+
+                size_base = to_size_factor(size_base, &size_factor),
+                start_base = range_state[i].base_pfn << (PAGE_SHIFT - 10);
+                start_base = to_size_factor(start_base, &start_factor),
+                type = range_state[i].type;
+
+                printk(KERN_DEBUG "reg %d, base: %ld%cB, range: %ld%cB, type %s\n",
+                        i, start_base, start_factor,
+                        size_base, size_factor,
+                        (type == MTRR_TYPE_UNCACHABLE) ? "UC" :
+                            ((type == MTRR_TYPE_WRPROT) ? "WP" :
+                             ((type == MTRR_TYPE_WRBACK) ? "WB" : "Other"))
+                        );
+        }
+
         memset(range, 0, sizeof(range));
         extra_remove_size = 0;
-        if (mtrr_tom2) {
-                extra_remove_base = 1 << (32 - PAGE_SHIFT);
+        extra_remove_base = 1 << (32 - PAGE_SHIFT);
+        if (mtrr_tom2)
                 extra_remove_size =
                         (mtrr_tom2 >> PAGE_SHIFT) - extra_remove_base;
-        }
         nr_range = x86_get_mtrr_mem_range(range, 0, extra_remove_base,
                                           extra_remove_size);
+        /*
+         * [0, 1M) should always be coverred by var mtrr with WB
+         * and fixed mtrrs should take effective before var mtrr for it
+         */
+        nr_range = add_range_with_merge(range, nr_range, 0,
+                                        (1ULL<<(20 - PAGE_SHIFT)) - 1);
+        /* sort the ranges */
+        sort(range, nr_range, sizeof(struct res_range), cmp_range, NULL);
+
         range_sums = sum_ranges(range, nr_range);
         printk(KERN_INFO "total RAM coverred: %ldM\n",
                range_sums >> (20 - PAGE_SHIFT));
 
         if (mtrr_chunk_size && mtrr_gran_size) {
                 int num_reg;
+                char gran_factor, chunk_factor, lose_factor;
+                unsigned long gran_base, chunk_base, lose_base;
 
-                debug_print = 1;
+                debug_print++;
                 /* convert ranges to var ranges state */
                 num_reg = x86_setup_var_mtrrs(range, nr_range, mtrr_chunk_size,
                                               mtrr_gran_size);
@@ -1256,34 +1337,48 @@ static int __init mtrr_cleanup(unsigned address_bits)
                         result[i].lose_cover_sizek =
                                 (range_sums - range_sums_new) << PSHIFT;
 
-                printk(KERN_INFO "%sgran_size: %ldM \tchunk_size: %ldM \t",
-                         result[i].bad?"*BAD*":" ", result[i].gran_sizek >> 10,
-                         result[i].chunk_sizek >> 10);
-                printk(KERN_CONT "num_reg: %d  \tlose cover RAM: %s%ldM \n",
+                gran_base = to_size_factor(result[i].gran_sizek, &gran_factor),
+                chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor),
+                lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor),
+                printk(KERN_INFO "%sgran_size: %ld%c \tchunk_size: %ld%c \t",
+                         result[i].bad?"*BAD*":" ",
+                         gran_base, gran_factor, chunk_base, chunk_factor);
+                printk(KERN_CONT "num_reg: %d  \tlose cover RAM: %s%ld%c\n",
                          result[i].num_reg, result[i].bad?"-":"",
-                         result[i].lose_cover_sizek >> 10);
+                         lose_base, lose_factor);
                 if (!result[i].bad) {
                         set_var_mtrr_all(address_bits);
                         return 1;
                 }
                 printk(KERN_INFO "invalid mtrr_gran_size or mtrr_chunk_size, "
                        "will find optimal one\n");
-                debug_print = 0;
+                debug_print--;
                 memset(result, 0, sizeof(result[0]));
         }
 
         i = 0;
         memset(min_loss_pfn, 0xff, sizeof(min_loss_pfn));
         memset(result, 0, sizeof(result));
-        for (gran_size = (1ULL<<20); gran_size < (1ULL<<32); gran_size <<= 1) {
-                for (chunk_size = gran_size; chunk_size < (1ULL<<33);
+        for (gran_size = (1ULL<<16); gran_size < (1ULL<<32); gran_size <<= 1) {
+                char gran_factor;
+                unsigned long gran_base;
+
+                if (debug_print)
+                        gran_base = to_size_factor(gran_size >> 10, &gran_factor);
+
+                for (chunk_size = gran_size; chunk_size < (1ULL<<32);
                      chunk_size <<= 1) {
                         int num_reg;
 
-                        if (debug_print)
-                                printk(KERN_INFO
-                               "\ngran_size: %lldM   chunk_size_size: %lldM\n",
-                                       gran_size >> 20, chunk_size >> 20);
+                        if (debug_print) {
+                                char chunk_factor;
+                                unsigned long chunk_base;
+
+                                chunk_base = to_size_factor(chunk_size>>10, &chunk_factor),
+                                printk(KERN_INFO "\n");
+                                printk(KERN_INFO "gran_size: %ld%c   chunk_size: %ld%c \n",
+                                       gran_base, gran_factor, chunk_base, chunk_factor);
+                        }
                         if (i >= NUM_RESULT)
                                 continue;
 
@@ -1326,12 +1421,18 @@ static int __init mtrr_cleanup(unsigned address_bits)
 
         /* print out all */
         for (i = 0; i < NUM_RESULT; i++) {
-                printk(KERN_INFO "%sgran_size: %ldM \tchunk_size: %ldM \t",
-                       result[i].bad?"*BAD* ":" ", result[i].gran_sizek >> 10,
-                       result[i].chunk_sizek >> 10);
-                printk(KERN_CONT "num_reg: %d \tlose RAM: %s%ldM\n",
-                       result[i].num_reg, result[i].bad?"-":"",
-                       result[i].lose_cover_sizek >> 10);
+                char gran_factor, chunk_factor, lose_factor;
+                unsigned long gran_base, chunk_base, lose_base;
+
+                gran_base = to_size_factor(result[i].gran_sizek, &gran_factor),
+                chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor),
+                lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor),
+                printk(KERN_INFO "%sgran_size: %ld%c \tchunk_size: %ld%c \t",
+                         result[i].bad?"*BAD*":" ",
+                         gran_base, gran_factor, chunk_base, chunk_factor);
+                printk(KERN_CONT "num_reg: %d  \tlose cover RAM: %s%ld%c\n",
+                         result[i].num_reg, result[i].bad?"-":"",
+                         lose_base, lose_factor);
         }
 
         /* try to find the optimal index */
@@ -1339,10 +1440,8 @@ static int __init mtrr_cleanup(unsigned address_bits)
                 nr_mtrr_spare_reg = num_var_ranges - 1;
         num_reg_good = -1;
         for (i = num_var_ranges - nr_mtrr_spare_reg; i > 0; i--) {
-                if (!min_loss_pfn[i]) {
+                if (!min_loss_pfn[i])
                         num_reg_good = i;
-                        break;
-                }
         }
 
         index_good = -1;
@@ -1358,21 +1457,26 @@ static int __init mtrr_cleanup(unsigned address_bits)
         }
 
         if (index_good != -1) {
+                char gran_factor, chunk_factor, lose_factor;
+                unsigned long gran_base, chunk_base, lose_base;
+
                 printk(KERN_INFO "Found optimal setting for mtrr clean up\n");
                 i = index_good;
-                printk(KERN_INFO "gran_size: %ldM \tchunk_size: %ldM \t",
-                                result[i].gran_sizek >> 10,
-                                result[i].chunk_sizek >> 10);
-                printk(KERN_CONT "num_reg: %d \tlose RAM: %ldM\n",
-                                result[i].num_reg,
-                                result[i].lose_cover_sizek >> 10);
+                gran_base = to_size_factor(result[i].gran_sizek, &gran_factor),
+                chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor),
+                lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor),
+                printk(KERN_INFO "gran_size: %ld%c \tchunk_size: %ld%c \t",
+                         gran_base, gran_factor, chunk_base, chunk_factor);
+                printk(KERN_CONT "num_reg: %d  \tlose RAM: %ld%c\n",
+                         result[i].num_reg, lose_base, lose_factor);
                 /* convert ranges to var ranges state */
                 chunk_size = result[i].chunk_sizek;
                 chunk_size <<= 10;
                 gran_size = result[i].gran_sizek;
                 gran_size <<= 10;
-                debug_print = 1;
+                debug_print++;
                 x86_setup_var_mtrrs(range, nr_range, chunk_size, gran_size);
+                debug_print--;
                 set_var_mtrr_all(address_bits);
                 return 1;
         }
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 05cc22dbd4ff..6bff382094f5 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -295,13 +295,19 @@ static int setup_k7_watchdog(unsigned nmi_hz)
         /* setup the timer */
         wrmsr(evntsel_msr, evntsel, 0);
         write_watchdog_counter(perfctr_msr, "K7_PERFCTR0",nmi_hz);
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        evntsel |= K7_EVNTSEL_ENABLE;
-        wrmsr(evntsel_msr, evntsel, 0);
 
+        /* initialize the wd struct before enabling */
         wd->perfctr_msr = perfctr_msr;
         wd->evntsel_msr = evntsel_msr;
         wd->cccr_msr = 0;  /* unused */
+
+        /* ok, everything is initialized, announce that we're set */
+        cpu_nmi_set_wd_enabled();
+
+        apic_write(APIC_LVTPC, APIC_DM_NMI);
+        evntsel |= K7_EVNTSEL_ENABLE;
+        wrmsr(evntsel_msr, evntsel, 0);
+
         return 1;
 }
 
@@ -379,13 +385,19 @@ static int setup_p6_watchdog(unsigned nmi_hz)
         wrmsr(evntsel_msr, evntsel, 0);
         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
         write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0",nmi_hz);
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        evntsel |= P6_EVNTSEL0_ENABLE;
-        wrmsr(evntsel_msr, evntsel, 0);
 
+        /* initialize the wd struct before enabling */
         wd->perfctr_msr = perfctr_msr;
         wd->evntsel_msr = evntsel_msr;
         wd->cccr_msr = 0;  /* unused */
+
+        /* ok, everything is initialized, announce that we're set */
+        cpu_nmi_set_wd_enabled();
+
+        apic_write(APIC_LVTPC, APIC_DM_NMI);
+        evntsel |= P6_EVNTSEL0_ENABLE;
+        wrmsr(evntsel_msr, evntsel, 0);
+
         return 1;
 }
 
@@ -432,6 +444,27 @@ static const struct wd_ops p6_wd_ops = {
 #define P4_CCCR_ENABLE          (1 << 12)
 #define P4_CCCR_OVF             (1 << 31)
 
+#define P4_CONTROLS 18
+static unsigned int p4_controls[18] = {
+        MSR_P4_BPU_CCCR0,
+        MSR_P4_BPU_CCCR1,
+        MSR_P4_BPU_CCCR2,
+        MSR_P4_BPU_CCCR3,
+        MSR_P4_MS_CCCR0,
+        MSR_P4_MS_CCCR1,
+        MSR_P4_MS_CCCR2,
+        MSR_P4_MS_CCCR3,
+        MSR_P4_FLAME_CCCR0,
+        MSR_P4_FLAME_CCCR1,
+        MSR_P4_FLAME_CCCR2,
+        MSR_P4_FLAME_CCCR3,
+        MSR_P4_IQ_CCCR0,
+        MSR_P4_IQ_CCCR1,
+        MSR_P4_IQ_CCCR2,
+        MSR_P4_IQ_CCCR3,
+        MSR_P4_IQ_CCCR4,
+        MSR_P4_IQ_CCCR5,
+};
 /*
  * Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
  * CRU_ESCR0 (with any non-null event selector) through a complemented
@@ -473,6 +506,26 @@ static int setup_p4_watchdog(unsigned nmi_hz)
                 evntsel_msr = MSR_P4_CRU_ESCR0;
                 cccr_msr = MSR_P4_IQ_CCCR0;
                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
+
+                /*
+                 * If we're on the kdump kernel or other situation, we may
+                 * still have other performance counter registers set to
+                 * interrupt and they'll keep interrupting forever because
+                 * of the P4_CCCR_OVF quirk. So we need to ACK all the
+                 * pending interrupts and disable all the registers here,
+                 * before reenabling the NMI delivery. Refer to p4_rearm()
+                 * about the P4_CCCR_OVF quirk.
+                 */
+                if (reset_devices) {
+                        unsigned int low, high;
+                        int i;
+
+                        for (i = 0; i < P4_CONTROLS; i++) {
+                                rdmsr(p4_controls[i], low, high);
+                                low &= ~(P4_CCCR_ENABLE | P4_CCCR_OVF);
+                                wrmsr(p4_controls[i], low, high);
+                        }
+                }
         } else {
                 /* logical cpu 1 */
                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
@@ -499,12 +552,17 @@ static int setup_p4_watchdog(unsigned nmi_hz)
         wrmsr(evntsel_msr, evntsel, 0);
         wrmsr(cccr_msr, cccr_val, 0);
         write_watchdog_counter(perfctr_msr, "P4_IQ_COUNTER0", nmi_hz);
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        cccr_val |= P4_CCCR_ENABLE;
-        wrmsr(cccr_msr, cccr_val, 0);
+
         wd->perfctr_msr = perfctr_msr;
         wd->evntsel_msr = evntsel_msr;
         wd->cccr_msr = cccr_msr;
+
+        /* ok, everything is initialized, announce that we're set */
+        cpu_nmi_set_wd_enabled();
+
+        apic_write(APIC_LVTPC, APIC_DM_NMI);
+        cccr_val |= P4_CCCR_ENABLE;
+        wrmsr(cccr_msr, cccr_val, 0);
         return 1;
 }
 
@@ -620,13 +678,17 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
         wrmsr(evntsel_msr, evntsel, 0);
         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
         write_watchdog_counter32(perfctr_msr, "INTEL_ARCH_PERFCTR0", nmi_hz);
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
-        wrmsr(evntsel_msr, evntsel, 0);
 
         wd->perfctr_msr = perfctr_msr;
         wd->evntsel_msr = evntsel_msr;
         wd->cccr_msr = 0;  /* unused */
+
+        /* ok, everything is initialized, announce that we're set */
+        cpu_nmi_set_wd_enabled();
+
+        apic_write(APIC_LVTPC, APIC_DM_NMI);
+        evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+        wrmsr(evntsel_msr, evntsel, 0);
         intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
         return 1;
 }
diff --git a/arch/x86/kernel/cpu/powerflags.c b/arch/x86/kernel/cpu/powerflags.c
new file mode 100644
index 000000000000..5abbea297e0c
--- /dev/null
+++ b/arch/x86/kernel/cpu/powerflags.c
@@ -0,0 +1,20 @@
+/*
+ * Strings for the various x86 power flags
+ *
+ * This file must not contain any executable code.
+ */
+
+#include <asm/cpufeature.h>
+
+const char *const x86_power_flags[32] = {
+        "ts",   /* temperature sensor */
+        "fid",  /* frequency id control */
+        "vid",  /* voltage id control */
+        "ttp",  /* thermal trip */
+        "tm",
+        "stc",
+        "100mhzsteps",
+        "hwpstate",
+        "",     /* tsc invariant mapped to constant_tsc */
+                /* nothing */
+};
diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c
index b911a2c61b8f..52b3fefbd5af 100644
--- a/arch/x86/kernel/cpu/transmeta.c
+++ b/arch/x86/kernel/cpu/transmeta.c
@@ -5,6 +5,18 @@
 #include <asm/msr.h>
 #include "cpu.h"
 
+static void __cpuinit early_init_transmeta(struct cpuinfo_x86 *c)
+{
+        u32 xlvl;
+
+        /* Transmeta-defined flags: level 0x80860001 */
+        xlvl = cpuid_eax(0x80860000);
+        if ((xlvl & 0xffff0000) == 0x80860000) {
+                if (xlvl >= 0x80860001)
+                        c->x86_capability[2] = cpuid_edx(0x80860001);
+        }
+}
+
 static void __cpuinit init_transmeta(struct cpuinfo_x86 *c)
 {
         unsigned int cap_mask, uk, max, dummy;
@@ -12,7 +24,8 @@ static void __cpuinit init_transmeta(struct cpuinfo_x86 *c)
         unsigned int cpu_rev, cpu_freq = 0, cpu_flags, new_cpu_rev;
         char cpu_info[65];
 
-        get_model_name(c);      /* Same as AMD/Cyrix */
+        early_init_transmeta(c);
+
         display_cacheinfo(c);
 
         /* Print CMS and CPU revision */
@@ -85,23 +98,12 @@ static void __cpuinit init_transmeta(struct cpuinfo_x86 *c)
 #endif
 }
 
-static void __cpuinit transmeta_identify(struct cpuinfo_x86 *c)
-{
-        u32 xlvl;
-
-        /* Transmeta-defined flags: level 0x80860001 */
-        xlvl = cpuid_eax(0x80860000);
-        if ((xlvl & 0xffff0000) == 0x80860000) {
-                if (xlvl >= 0x80860001)
-                        c->x86_capability[2] = cpuid_edx(0x80860001);
-        }
-}
-
 static struct cpu_dev transmeta_cpu_dev __cpuinitdata = {
         .c_vendor       = "Transmeta",
         .c_ident        = { "GenuineTMx86", "TransmetaCPU" },
+        .c_early_init   = early_init_transmeta,
         .c_init         = init_transmeta,
-        .c_identify     = transmeta_identify,
+        .c_x86_vendor   = X86_VENDOR_TRANSMETA,
 };
 
-cpu_vendor_dev_register(X86_VENDOR_TRANSMETA, &transmeta_cpu_dev);
+cpu_dev_register(transmeta_cpu_dev);
diff --git a/arch/x86/kernel/cpu/umc.c b/arch/x86/kernel/cpu/umc.c
index b1fc90989d75..e777f79e0960 100644
--- a/arch/x86/kernel/cpu/umc.c
+++ b/arch/x86/kernel/cpu/umc.c
@@ -19,7 +19,8 @@ static struct cpu_dev umc_cpu_dev __cpuinitdata = {
                   }
                 },
         },
+        .c_x86_vendor   = X86_VENDOR_UMC,
 };
 
-cpu_vendor_dev_register(X86_VENDOR_UMC, &umc_cpu_dev);
+cpu_dev_register(umc_cpu_dev);
 
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 8e9cd6a8ec12..6a44d6465991 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -36,7 +36,6 @@
 #include <linux/smp_lock.h>
 #include <linux/major.h>
 #include <linux/fs.h>
-#include <linux/smp_lock.h>
 #include <linux/device.h>
 #include <linux/cpu.h>
 #include <linux/notifier.h>
diff --git a/arch/x86/kernel/crash_dump_64.c b/arch/x86/kernel/crash_dump_64.c
index 15e6c6bc4a46..e90a60ef10c2 100644
--- a/arch/x86/kernel/crash_dump_64.c
+++ b/arch/x86/kernel/crash_dump_64.c
@@ -7,9 +7,8 @@
 
 #include <linux/errno.h>
 #include <linux/crash_dump.h>
-
-#include <asm/uaccess.h>
-#include <asm/io.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
 
 /**
  * copy_oldmem_page - copy one page from "oldmem"
@@ -25,7 +24,7 @@
  * in the current kernel. We stitch up a pte, similar to kmap_atomic.
  */
 ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
-                               size_t csize, unsigned long offset, int userbuf)
+                size_t csize, unsigned long offset, int userbuf)
 {
         void  *vaddr;
 
@@ -33,14 +32,16 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
                 return 0;
 
         vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
+        if (!vaddr)
+                return -ENOMEM;
 
         if (userbuf) {
-                if (copy_to_user(buf, (vaddr + offset), csize)) {
+                if (copy_to_user(buf, vaddr + offset, csize)) {
                         iounmap(vaddr);
                         return -EFAULT;
                 }
         } else
-        memcpy(buf, (vaddr + offset), csize);
+                memcpy(buf, vaddr + offset, csize);
 
         iounmap(vaddr);
         return csize;
diff --git a/arch/x86/kernel/ds.c b/arch/x86/kernel/ds.c
index 11c11b8ec48d..2b69994fd3a8 100644
--- a/arch/x86/kernel/ds.c
+++ b/arch/x86/kernel/ds.c
@@ -2,26 +2,49 @@
  * Debug Store support
  *
  * This provides a low-level interface to the hardware's Debug Store
- * feature that is used for last branch recording (LBR) and
+ * feature that is used for branch trace store (BTS) and
  * precise-event based sampling (PEBS).
  *
- * Different architectures use a different DS layout/pointer size.
- * The below functions therefore work on a void*.
+ * It manages:
+ * - per-thread and per-cpu allocation of BTS and PEBS
+ * - buffer memory allocation (optional)
+ * - buffer overflow handling
+ * - buffer access
  *
+ * It assumes:
+ * - get_task_struct on all parameter tasks
+ * - current is allowed to trace parameter tasks
  *
- * Since there is no user for PEBS, yet, only LBR (or branch
- * trace store, BTS) is supported.
  *
- *
- * Copyright (C) 2007 Intel Corporation.
- * Markus Metzger <markus.t.metzger@intel.com>, Dec 2007
+ * Copyright (C) 2007-2008 Intel Corporation.
+ * Markus Metzger <markus.t.metzger@intel.com>, 2007-2008
  */
 
+
+#ifdef CONFIG_X86_DS
+
 #include <asm/ds.h>
 
 #include <linux/errno.h>
 #include <linux/string.h>
 #include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+
+
+/*
+ * The configuration for a particular DS hardware implementation.
+ */
+struct ds_configuration {
+        /* the size of the DS structure in bytes */
+        unsigned char  sizeof_ds;
+        /* the size of one pointer-typed field in the DS structure in bytes;
+           this covers the first 8 fields related to buffer management. */
+        unsigned char  sizeof_field;
+        /* the size of a BTS/PEBS record in bytes */
+        unsigned char  sizeof_rec[2];
+};
+static struct ds_configuration ds_cfg;
 
 
 /*
@@ -44,378 +67,747 @@
  *   (interrupt occurs when write pointer passes interrupt pointer)
  * - value to which counter is reset following counter overflow
  *
- * On later architectures, the last branch recording hardware uses
- * 64bit pointers even in 32bit mode.
- *
- *
- * Branch Trace Store (BTS) records store information about control
- * flow changes. They at least provide the following information:
- * - source linear address
- * - destination linear address
+ * Later architectures use 64bit pointers throughout, whereas earlier
+ * architectures use 32bit pointers in 32bit mode.
  *
- * Netburst supported a predicated bit that had been dropped in later
- * architectures. We do not suppor it.
  *
+ * We compute the base address for the first 8 fields based on:
+ * - the field size stored in the DS configuration
+ * - the relative field position
+ * - an offset giving the start of the respective region
  *
- * In order to abstract from the actual DS and BTS layout, we describe
- * the access to the relevant fields.
- * Thanks to Andi Kleen for proposing this design.
+ * This offset is further used to index various arrays holding
+ * information for BTS and PEBS at the respective index.
  *
- * The implementation, however, is not as general as it might seem. In
- * order to stay somewhat simple and efficient, we assume an
- * underlying unsigned type (mostly a pointer type) and we expect the
- * field to be at least as big as that type.
+ * On later 32bit processors, we only access the lower 32bit of the
+ * 64bit pointer fields. The upper halves will be zeroed out.
  */
 
-/*
- * A special from_ip address to indicate that the BTS record is an
- * info record that needs to be interpreted or skipped.
- */
-#define BTS_ESCAPE_ADDRESS (-1)
+enum ds_field {
+        ds_buffer_base = 0,
+        ds_index,
+        ds_absolute_maximum,
+        ds_interrupt_threshold,
+};
 
-/*
- * A field access descriptor
- */
-struct access_desc {
-        unsigned char offset;
-        unsigned char size;
+enum ds_qualifier {
+        ds_bts  = 0,
+        ds_pebs
 };
 
+static inline unsigned long ds_get(const unsigned char *base,
+                                   enum ds_qualifier qual, enum ds_field field)
+{
+        base += (ds_cfg.sizeof_field * (field + (4 * qual)));
+        return *(unsigned long *)base;
+}
+
+static inline void ds_set(unsigned char *base, enum ds_qualifier qual,
+                          enum ds_field field, unsigned long value)
+{
+        base += (ds_cfg.sizeof_field * (field + (4 * qual)));
+        (*(unsigned long *)base) = value;
+}
+
+
 /*
- * The configuration for a particular DS/BTS hardware implementation.
+ * Locking is done only for allocating BTS or PEBS resources and for
+ * guarding context and buffer memory allocation.
+ *
+ * Most functions require the current task to own the ds context part
+ * they are going to access. All the locking is done when validating
+ * access to the context.
  */
-struct ds_configuration {
-        /* the DS configuration */
-        unsigned char  sizeof_ds;
-        struct access_desc bts_buffer_base;
-        struct access_desc bts_index;
-        struct access_desc bts_absolute_maximum;
-        struct access_desc bts_interrupt_threshold;
-        /* the BTS configuration */
-        unsigned char  sizeof_bts;
-        struct access_desc from_ip;
-        struct access_desc to_ip;
-        /* BTS variants used to store additional information like
-           timestamps */
-        struct access_desc info_type;
-        struct access_desc info_data;
-        unsigned long debugctl_mask;
-};
+static spinlock_t ds_lock = __SPIN_LOCK_UNLOCKED(ds_lock);
 
 /*
- * The global configuration used by the below accessor functions
+ * Validate that the current task is allowed to access the BTS/PEBS
+ * buffer of the parameter task.
+ *
+ * Returns 0, if access is granted; -Eerrno, otherwise.
  */
-static struct ds_configuration ds_cfg;
+static inline int ds_validate_access(struct ds_context *context,
+                                     enum ds_qualifier qual)
+{
+        if (!context)
+                return -EPERM;
+
+        if (context->owner[qual] == current)
+                return 0;
+
+        return -EPERM;
+}
+
 
 /*
- * Accessor functions for some DS and BTS fields using the above
- * global ptrace_bts_cfg.
+ * We either support (system-wide) per-cpu or per-thread allocation.
+ * We distinguish the two based on the task_struct pointer, where a
+ * NULL pointer indicates per-cpu allocation for the current cpu.
+ *
+ * Allocations are use-counted. As soon as resources are allocated,
+ * further allocations must be of the same type (per-cpu or
+ * per-thread). We model this by counting allocations (i.e. the number
+ * of tracers of a certain type) for one type negatively:
+ *   =0  no tracers
+ *   >0  number of per-thread tracers
+ *   <0  number of per-cpu tracers
+ *
+ * The below functions to get and put tracers and to check the
+ * allocation type require the ds_lock to be held by the caller.
+ *
+ * Tracers essentially gives the number of ds contexts for a certain
+ * type of allocation.
  */
-static inline unsigned long get_bts_buffer_base(char *base)
+static long tracers;
+
+static inline void get_tracer(struct task_struct *task)
 {
-        return *(unsigned long *)(base + ds_cfg.bts_buffer_base.offset);
+        tracers += (task ? 1 : -1);
 }
-static inline void set_bts_buffer_base(char *base, unsigned long value)
+
+static inline void put_tracer(struct task_struct *task)
 {
-        (*(unsigned long *)(base + ds_cfg.bts_buffer_base.offset)) = value;
+        tracers -= (task ? 1 : -1);
 }
-static inline unsigned long get_bts_index(char *base)
+
+static inline int check_tracer(struct task_struct *task)
 {
-        return *(unsigned long *)(base + ds_cfg.bts_index.offset);
+        return (task ? (tracers >= 0) : (tracers <= 0));
 }
-static inline void set_bts_index(char *base, unsigned long value)
+
+
+/*
+ * The DS context is either attached to a thread or to a cpu:
+ * - in the former case, the thread_struct contains a pointer to the
+ *   attached context.
+ * - in the latter case, we use a static array of per-cpu context
+ *   pointers.
+ *
+ * Contexts are use-counted. They are allocated on first access and
+ * deallocated when the last user puts the context.
+ *
+ * We distinguish between an allocating and a non-allocating get of a
+ * context:
+ * - the allocating get is used for requesting BTS/PEBS resources. It
+ *   requires the caller to hold the global ds_lock.
+ * - the non-allocating get is used for all other cases. A
+ *   non-existing context indicates an error. It acquires and releases
+ *   the ds_lock itself for obtaining the context.
+ *
+ * A context and its DS configuration are allocated and deallocated
+ * together. A context always has a DS configuration of the
+ * appropriate size.
+ */
+static DEFINE_PER_CPU(struct ds_context *, system_context);
+
+#define this_system_context per_cpu(system_context, smp_processor_id())
+
+/*
+ * Returns the pointer to the parameter task's context or to the
+ * system-wide context, if task is NULL.
+ *
+ * Increases the use count of the returned context, if not NULL.
+ */
+static inline struct ds_context *ds_get_context(struct task_struct *task)
 {
-        (*(unsigned long *)(base + ds_cfg.bts_index.offset)) = value;
+        struct ds_context *context;
+
+        spin_lock(&ds_lock);
+
+        context = (task ? task->thread.ds_ctx : this_system_context);
+        if (context)
+                context->count++;
+
+        spin_unlock(&ds_lock);
+
+        return context;
 }
-static inline unsigned long get_bts_absolute_maximum(char *base)
+
+/*
+ * Same as ds_get_context, but allocates the context and it's DS
+ * structure, if necessary; returns NULL; if out of memory.
+ *
+ * pre: requires ds_lock to be held
+ */
+static inline struct ds_context *ds_alloc_context(struct task_struct *task)
 {
-        return *(unsigned long *)(base + ds_cfg.bts_absolute_maximum.offset);
+        struct ds_context **p_context =
+                (task ? &task->thread.ds_ctx : &this_system_context);
+        struct ds_context *context = *p_context;
+
+        if (!context) {
+                context = kzalloc(sizeof(*context), GFP_KERNEL);
+
+                if (!context)
+                        return NULL;
+
+                context->ds = kzalloc(ds_cfg.sizeof_ds, GFP_KERNEL);
+                if (!context->ds) {
+                        kfree(context);
+                        return NULL;
+                }
+
+                *p_context = context;
+
+                context->this = p_context;
+                context->task = task;
+
+                if (task)
+                        set_tsk_thread_flag(task, TIF_DS_AREA_MSR);
+
+                if (!task || (task == current))
+                        wrmsr(MSR_IA32_DS_AREA, (unsigned long)context->ds, 0);
+
+                get_tracer(task);
+        }
+
+        context->count++;
+
+        return context;
 }
-static inline void set_bts_absolute_maximum(char *base, unsigned long value)
+
+/*
+ * Decreases the use count of the parameter context, if not NULL.
+ * Deallocates the context, if the use count reaches zero.
+ */
+static inline void ds_put_context(struct ds_context *context)
 {
-        (*(unsigned long *)(base + ds_cfg.bts_absolute_maximum.offset)) = value;
+        if (!context)
+                return;
+
+        spin_lock(&ds_lock);
+
+        if (--context->count)
+                goto out;
+
+        *(context->this) = NULL;
+
+        if (context->task)
+                clear_tsk_thread_flag(context->task, TIF_DS_AREA_MSR);
+
+        if (!context->task || (context->task == current))
+                wrmsrl(MSR_IA32_DS_AREA, 0);
+
+        put_tracer(context->task);
+
+        /* free any leftover buffers from tracers that did not
+         * deallocate them properly. */
+        kfree(context->buffer[ds_bts]);
+        kfree(context->buffer[ds_pebs]);
+        kfree(context->ds);
+        kfree(context);
+ out:
+        spin_unlock(&ds_lock);
 }
-static inline unsigned long get_bts_interrupt_threshold(char *base)
+
+
+/*
+ * Handle a buffer overflow
+ *
+ * task: the task whose buffers are overflowing;
+ *       NULL for a buffer overflow on the current cpu
+ * context: the ds context
+ * qual: the buffer type
+ */
+static void ds_overflow(struct task_struct *task, struct ds_context *context,
+                        enum ds_qualifier qual)
 {
-        return *(unsigned long *)(base + ds_cfg.bts_interrupt_threshold.offset);
+        if (!context)
+                return;
+
+        if (context->callback[qual])
+                (*context->callback[qual])(task);
+
+        /* todo: do some more overflow handling */
 }
-static inline void set_bts_interrupt_threshold(char *base, unsigned long value)
+
+
+/*
+ * Allocate a non-pageable buffer of the parameter size.
+ * Checks the memory and the locked memory rlimit.
+ *
+ * Returns the buffer, if successful;
+ *         NULL, if out of memory or rlimit exceeded.
+ *
+ * size: the requested buffer size in bytes
+ * pages (out): if not NULL, contains the number of pages reserved
+ */
+static inline void *ds_allocate_buffer(size_t size, unsigned int *pages)
 {
-        (*(unsigned long *)(base + ds_cfg.bts_interrupt_threshold.offset)) = value;
+        unsigned long rlim, vm, pgsz;
+        void *buffer;
+
+        pgsz = PAGE_ALIGN(size) >> PAGE_SHIFT;
+
+        rlim = current->signal->rlim[RLIMIT_AS].rlim_cur >> PAGE_SHIFT;
+        vm   = current->mm->total_vm  + pgsz;
+        if (rlim < vm)
+                return NULL;
+
+        rlim = current->signal->rlim[RLIMIT_MEMLOCK].rlim_cur >> PAGE_SHIFT;
+        vm   = current->mm->locked_vm  + pgsz;
+        if (rlim < vm)
+                return NULL;
+
+        buffer = kzalloc(size, GFP_KERNEL);
+        if (!buffer)
+                return NULL;
+
+        current->mm->total_vm  += pgsz;
+        current->mm->locked_vm += pgsz;
+
+        if (pages)
+                *pages = pgsz;
+
+        return buffer;
 }
-static inline unsigned long get_from_ip(char *base)
+
+static int ds_request(struct task_struct *task, void *base, size_t size,
+                      ds_ovfl_callback_t ovfl, enum ds_qualifier qual)
 {
-        return *(unsigned long *)(base + ds_cfg.from_ip.offset);
+        struct ds_context *context;
+        unsigned long buffer, adj;
+        const unsigned long alignment = (1 << 3);
+        int error = 0;
+
+        if (!ds_cfg.sizeof_ds)
+                return -EOPNOTSUPP;
+
+        /* we require some space to do alignment adjustments below */
+        if (size < (alignment + ds_cfg.sizeof_rec[qual]))
+                return -EINVAL;
+
+        /* buffer overflow notification is not yet implemented */
+        if (ovfl)
+                return -EOPNOTSUPP;
+
+
+        spin_lock(&ds_lock);
+
+        if (!check_tracer(task))
+                return -EPERM;
+
+        error = -ENOMEM;
+        context = ds_alloc_context(task);
+        if (!context)
+                goto out_unlock;
+
+        error = -EALREADY;
+        if (context->owner[qual] == current)
+                goto out_unlock;
+        error = -EPERM;
+        if (context->owner[qual] != NULL)
+                goto out_unlock;
+        context->owner[qual] = current;
+
+        spin_unlock(&ds_lock);
+
+
+        error = -ENOMEM;
+        if (!base) {
+                base = ds_allocate_buffer(size, &context->pages[qual]);
+                if (!base)
+                        goto out_release;
+
+                context->buffer[qual]   = base;
+        }
+        error = 0;
+
+        context->callback[qual] = ovfl;
+
+        /* adjust the buffer address and size to meet alignment
+         * constraints:
+         * - buffer is double-word aligned
+         * - size is multiple of record size
+         *
+         * We checked the size at the very beginning; we have enough
+         * space to do the adjustment.
+         */
+        buffer = (unsigned long)base;
+
+        adj = ALIGN(buffer, alignment) - buffer;
+        buffer += adj;
+        size   -= adj;
+
+        size /= ds_cfg.sizeof_rec[qual];
+        size *= ds_cfg.sizeof_rec[qual];
+
+        ds_set(context->ds, qual, ds_buffer_base, buffer);
+        ds_set(context->ds, qual, ds_index, buffer);
+        ds_set(context->ds, qual, ds_absolute_maximum, buffer + size);
+
+        if (ovfl) {
+                /* todo: select a suitable interrupt threshold */
+        } else
+                ds_set(context->ds, qual,
+                       ds_interrupt_threshold, buffer + size + 1);
+
+        /* we keep the context until ds_release */
+        return error;
+
+ out_release:
+        context->owner[qual] = NULL;
+        ds_put_context(context);
+        return error;
+
+ out_unlock:
+        spin_unlock(&ds_lock);
+        ds_put_context(context);
+        return error;
 }
-static inline void set_from_ip(char *base, unsigned long value)
+
+int ds_request_bts(struct task_struct *task, void *base, size_t size,
+                   ds_ovfl_callback_t ovfl)
 {
-        (*(unsigned long *)(base + ds_cfg.from_ip.offset)) = value;
+        return ds_request(task, base, size, ovfl, ds_bts);
 }
-static inline unsigned long get_to_ip(char *base)
+
+int ds_request_pebs(struct task_struct *task, void *base, size_t size,
+                    ds_ovfl_callback_t ovfl)
 {
-        return *(unsigned long *)(base + ds_cfg.to_ip.offset);
+        return ds_request(task, base, size, ovfl, ds_pebs);
 }
-static inline void set_to_ip(char *base, unsigned long value)
+
+static int ds_release(struct task_struct *task, enum ds_qualifier qual)
 {
-        (*(unsigned long *)(base + ds_cfg.to_ip.offset)) = value;
+        struct ds_context *context;
+        int error;
+
+        context = ds_get_context(task);
+        error = ds_validate_access(context, qual);
+        if (error < 0)
+                goto out;
+
+        kfree(context->buffer[qual]);
+        context->buffer[qual] = NULL;
+
+        current->mm->total_vm  -= context->pages[qual];
+        current->mm->locked_vm -= context->pages[qual];
+        context->pages[qual] = 0;
+        context->owner[qual] = NULL;
+
+        /*
+         * we put the context twice:
+         *   once for the ds_get_context
+         *   once for the corresponding ds_request
+         */
+        ds_put_context(context);
+ out:
+        ds_put_context(context);
+        return error;
 }
-static inline unsigned char get_info_type(char *base)
+
+int ds_release_bts(struct task_struct *task)
 {
-        return *(unsigned char *)(base + ds_cfg.info_type.offset);
+        return ds_release(task, ds_bts);
 }
-static inline void set_info_type(char *base, unsigned char value)
+
+int ds_release_pebs(struct task_struct *task)
 {
-        (*(unsigned char *)(base + ds_cfg.info_type.offset)) = value;
+        return ds_release(task, ds_pebs);
 }
-static inline unsigned long get_info_data(char *base)
+
+static int ds_get_index(struct task_struct *task, size_t *pos,
+                        enum ds_qualifier qual)
 {
-        return *(unsigned long *)(base + ds_cfg.info_data.offset);
+        struct ds_context *context;
+        unsigned long base, index;
+        int error;
+
+        context = ds_get_context(task);
+        error = ds_validate_access(context, qual);
+        if (error < 0)
+                goto out;
+
+        base  = ds_get(context->ds, qual, ds_buffer_base);
+        index = ds_get(context->ds, qual, ds_index);
+
+        error = ((index - base) / ds_cfg.sizeof_rec[qual]);
+        if (pos)
+                *pos = error;
+ out:
+        ds_put_context(context);
+        return error;
 }
-static inline void set_info_data(char *base, unsigned long value)
+
+int ds_get_bts_index(struct task_struct *task, size_t *pos)
 {
-        (*(unsigned long *)(base + ds_cfg.info_data.offset)) = value;
+        return ds_get_index(task, pos, ds_bts);
 }
 
+int ds_get_pebs_index(struct task_struct *task, size_t *pos)
+{
+        return ds_get_index(task, pos, ds_pebs);
+}
 
-int ds_allocate(void **dsp, size_t bts_size_in_bytes)
+static int ds_get_end(struct task_struct *task, size_t *pos,
+                      enum ds_qualifier qual)
 {
-        size_t bts_size_in_records;
-        unsigned long bts;
-        void *ds;
+        struct ds_context *context;
+        unsigned long base, end;
+        int error;
+
+        context = ds_get_context(task);
+        error = ds_validate_access(context, qual);
+        if (error < 0)
+                goto out;
+
+        base = ds_get(context->ds, qual, ds_buffer_base);
+        end  = ds_get(context->ds, qual, ds_absolute_maximum);
+
+        error = ((end - base) / ds_cfg.sizeof_rec[qual]);
+        if (pos)
+                *pos = error;
+ out:
+        ds_put_context(context);
+        return error;
+}
 
-        if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
-                return -EOPNOTSUPP;
+int ds_get_bts_end(struct task_struct *task, size_t *pos)
+{
+        return ds_get_end(task, pos, ds_bts);
+}
 
-        if (bts_size_in_bytes < 0)
-                return -EINVAL;
+int ds_get_pebs_end(struct task_struct *task, size_t *pos)
+{
+        return ds_get_end(task, pos, ds_pebs);
+}
 
-        bts_size_in_records =
-                bts_size_in_bytes / ds_cfg.sizeof_bts;
-        bts_size_in_bytes =
-                bts_size_in_records * ds_cfg.sizeof_bts;
+static int ds_access(struct task_struct *task, size_t index,
+                     const void **record, enum ds_qualifier qual)
+{
+        struct ds_context *context;
+        unsigned long base, idx;
+        int error;
 
-        if (bts_size_in_bytes <= 0)
+        if (!record)
                 return -EINVAL;
 
-        bts = (unsigned long)kzalloc(bts_size_in_bytes, GFP_KERNEL);
-
-        if (!bts)
-                return -ENOMEM;
+        context = ds_get_context(task);
+        error = ds_validate_access(context, qual);
+        if (error < 0)
+                goto out;
 
-        ds = kzalloc(ds_cfg.sizeof_ds, GFP_KERNEL);
+        base = ds_get(context->ds, qual, ds_buffer_base);
+        idx = base + (index * ds_cfg.sizeof_rec[qual]);
 
-        if (!ds) {
-                kfree((void *)bts);
-                return -ENOMEM;
-        }
-
-        set_bts_buffer_base(ds, bts);
-        set_bts_index(ds, bts);
-        set_bts_absolute_maximum(ds, bts + bts_size_in_bytes);
-        set_bts_interrupt_threshold(ds, bts + bts_size_in_bytes + 1);
+        error = -EINVAL;
+        if (idx > ds_get(context->ds, qual, ds_absolute_maximum))
+                goto out;
 
-        *dsp = ds;
-        return 0;
+        *record = (const void *)idx;
+        error = ds_cfg.sizeof_rec[qual];
+ out:
+        ds_put_context(context);
+        return error;
 }
 
-int ds_free(void **dsp)
+int ds_access_bts(struct task_struct *task, size_t index, const void **record)
 {
-        if (*dsp) {
-                kfree((void *)get_bts_buffer_base(*dsp));
-                kfree(*dsp);
-                *dsp = NULL;
-        }
-        return 0;
+        return ds_access(task, index, record, ds_bts);
 }
 
-int ds_get_bts_size(void *ds)
+int ds_access_pebs(struct task_struct *task, size_t index, const void **record)
 {
-        int size_in_bytes;
-
-        if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
-                return -EOPNOTSUPP;
-
-        if (!ds)
-                return 0;
-
-        size_in_bytes =
-                get_bts_absolute_maximum(ds) -
-                get_bts_buffer_base(ds);
-        return size_in_bytes;
+        return ds_access(task, index, record, ds_pebs);
 }
 
-int ds_get_bts_end(void *ds)
+static int ds_write(struct task_struct *task, const void *record, size_t size,
+                    enum ds_qualifier qual, int force)
 {
-        int size_in_bytes = ds_get_bts_size(ds);
-
-        if (size_in_bytes <= 0)
-                return size_in_bytes;
+        struct ds_context *context;
+        int error;
 
-        return size_in_bytes / ds_cfg.sizeof_bts;
-}
+        if (!record)
+                return -EINVAL;
 
-int ds_get_bts_index(void *ds)
-{
-        int index_offset_in_bytes;
+        error = -EPERM;
+        context = ds_get_context(task);
+        if (!context)
+                goto out;
 
-        if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
-                return -EOPNOTSUPP;
+        if (!force) {
+                error = ds_validate_access(context, qual);
+                if (error < 0)
+                        goto out;
+        }
 
-        index_offset_in_bytes =
-                get_bts_index(ds) -
-                get_bts_buffer_base(ds);
+        error = 0;
+        while (size) {
+                unsigned long base, index, end, write_end, int_th;
+                unsigned long write_size, adj_write_size;
+
+                /*
+                 * write as much as possible without producing an
+                 * overflow interrupt.
+                 *
+                 * interrupt_threshold must either be
+                 * - bigger than absolute_maximum or
+                 * - point to a record between buffer_base and absolute_maximum
+                 *
+                 * index points to a valid record.
+                 */
+                base   = ds_get(context->ds, qual, ds_buffer_base);
+                index  = ds_get(context->ds, qual, ds_index);
+                end    = ds_get(context->ds, qual, ds_absolute_maximum);
+                int_th = ds_get(context->ds, qual, ds_interrupt_threshold);
+
+                write_end = min(end, int_th);
+
+                /* if we are already beyond the interrupt threshold,
+                 * we fill the entire buffer */
+                if (write_end <= index)
+                        write_end = end;
+
+                if (write_end <= index)
+                        goto out;
+
+                write_size = min((unsigned long) size, write_end - index);
+                memcpy((void *)index, record, write_size);
+
+                record = (const char *)record + write_size;
+                size  -= write_size;
+                error += write_size;
+
+                adj_write_size = write_size / ds_cfg.sizeof_rec[qual];
+                adj_write_size *= ds_cfg.sizeof_rec[qual];
+
+                /* zero out trailing bytes */
+                memset((char *)index + write_size, 0,
+                       adj_write_size - write_size);
+                index += adj_write_size;
+
+                if (index >= end)
+                        index = base;
+                ds_set(context->ds, qual, ds_index, index);
+
+                if (index >= int_th)
+                        ds_overflow(task, context, qual);
+        }
 
-        return index_offset_in_bytes / ds_cfg.sizeof_bts;
+ out:
+        ds_put_context(context);
+        return error;
 }
 
-int ds_set_overflow(void *ds, int method)
+int ds_write_bts(struct task_struct *task, const void *record, size_t size)
 {
-        switch (method) {
-        case DS_O_SIGNAL:
-                return -EOPNOTSUPP;
-        case DS_O_WRAP:
-                return 0;
-        default:
-                return -EINVAL;
-        }
+        return ds_write(task, record, size, ds_bts, /* force = */ 0);
 }
 
-int ds_get_overflow(void *ds)
+int ds_write_pebs(struct task_struct *task, const void *record, size_t size)
 {
-        return DS_O_WRAP;
+        return ds_write(task, record, size, ds_pebs, /* force = */ 0);
 }
 
-int ds_clear(void *ds)
+int ds_unchecked_write_bts(struct task_struct *task,
+                           const void *record, size_t size)
 {
-        int bts_size = ds_get_bts_size(ds);
-        unsigned long bts_base;
-
-        if (bts_size <= 0)
-                return bts_size;
-
-        bts_base = get_bts_buffer_base(ds);
-        memset((void *)bts_base, 0, bts_size);
-
-        set_bts_index(ds, bts_base);
-        return 0;
+        return ds_write(task, record, size, ds_bts, /* force = */ 1);
 }
 
-int ds_read_bts(void *ds, int index, struct bts_struct *out)
+int ds_unchecked_write_pebs(struct task_struct *task,
+                            const void *record, size_t size)
 {
-        void *bts;
+        return ds_write(task, record, size, ds_pebs, /* force = */ 1);
+}
 
-        if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
-                return -EOPNOTSUPP;
+static int ds_reset_or_clear(struct task_struct *task,
+                             enum ds_qualifier qual, int clear)
+{
+        struct ds_context *context;
+        unsigned long base, end;
+        int error;
 
-        if (index < 0)
-                return -EINVAL;
+        context = ds_get_context(task);
+        error = ds_validate_access(context, qual);
+        if (error < 0)
+                goto out;
 
-        if (index >= ds_get_bts_size(ds))
-                return -EINVAL;
+        base = ds_get(context->ds, qual, ds_buffer_base);
+        end  = ds_get(context->ds, qual, ds_absolute_maximum);
 
-        bts = (void *)(get_bts_buffer_base(ds) + (index * ds_cfg.sizeof_bts));
+        if (clear)
+                memset((void *)base, 0, end - base);
 
-        memset(out, 0, sizeof(*out));
-        if (get_from_ip(bts) == BTS_ESCAPE_ADDRESS) {
-                out->qualifier       = get_info_type(bts);
-                out->variant.jiffies = get_info_data(bts);
-        } else {
-                out->qualifier = BTS_BRANCH;
-                out->variant.lbr.from_ip = get_from_ip(bts);
-                out->variant.lbr.to_ip   = get_to_ip(bts);
-        }
+        ds_set(context->ds, qual, ds_index, base);
 
-        return sizeof(*out);;
+        error = 0;
+ out:
+        ds_put_context(context);
+        return error;
 }
 
-int ds_write_bts(void *ds, const struct bts_struct *in)
+int ds_reset_bts(struct task_struct *task)
 {
-        unsigned long bts;
-
-        if (!ds_cfg.sizeof_ds || !ds_cfg.sizeof_bts)
-                return -EOPNOTSUPP;
-
-        if (ds_get_bts_size(ds) <= 0)
-                return -ENXIO;
+        return ds_reset_or_clear(task, ds_bts, /* clear = */ 0);
+}
 
-        bts = get_bts_index(ds);
+int ds_reset_pebs(struct task_struct *task)
+{
+        return ds_reset_or_clear(task, ds_pebs, /* clear = */ 0);
+}
 
-        memset((void *)bts, 0, ds_cfg.sizeof_bts);
-        switch (in->qualifier) {
-        case BTS_INVALID:
-                break;
+int ds_clear_bts(struct task_struct *task)
+{
+        return ds_reset_or_clear(task, ds_bts, /* clear = */ 1);
+}
 
-        case BTS_BRANCH:
-                set_from_ip((void *)bts, in->variant.lbr.from_ip);
-                set_to_ip((void *)bts, in->variant.lbr.to_ip);
-                break;
+int ds_clear_pebs(struct task_struct *task)
+{
+        return ds_reset_or_clear(task, ds_pebs, /* clear = */ 1);
+}
 
-        case BTS_TASK_ARRIVES:
-        case BTS_TASK_DEPARTS:
-                set_from_ip((void *)bts, BTS_ESCAPE_ADDRESS);
-                set_info_type((void *)bts, in->qualifier);
-                set_info_data((void *)bts, in->variant.jiffies);
-                break;
+int ds_get_pebs_reset(struct task_struct *task, u64 *value)
+{
+        struct ds_context *context;
+        int error;
 
-        default:
+        if (!value)
                 return -EINVAL;
-        }
 
-        bts = bts + ds_cfg.sizeof_bts;
-        if (bts >= get_bts_absolute_maximum(ds))
-                bts = get_bts_buffer_base(ds);
-        set_bts_index(ds, bts);
+        context = ds_get_context(task);
+        error = ds_validate_access(context, ds_pebs);
+        if (error < 0)
+                goto out;
 
-        return ds_cfg.sizeof_bts;
+        *value = *(u64 *)(context->ds + (ds_cfg.sizeof_field * 8));
+
+        error = 0;
+ out:
+        ds_put_context(context);
+        return error;
 }
 
-unsigned long ds_debugctl_mask(void)
+int ds_set_pebs_reset(struct task_struct *task, u64 value)
 {
-        return ds_cfg.debugctl_mask;
-}
+        struct ds_context *context;
+        int error;
 
-#ifdef __i386__
-static const struct ds_configuration ds_cfg_netburst = {
-        .sizeof_ds = 9 * 4,
-        .bts_buffer_base = { 0, 4 },
-        .bts_index = { 4, 4 },
-        .bts_absolute_maximum = { 8, 4 },
-        .bts_interrupt_threshold = { 12, 4 },
-        .sizeof_bts = 3 * 4,
-        .from_ip = { 0, 4 },
-        .to_ip = { 4, 4 },
-        .info_type = { 4, 1 },
-        .info_data = { 8, 4 },
-        .debugctl_mask = (1<<2)|(1<<3)
-};
+        context = ds_get_context(task);
+        error = ds_validate_access(context, ds_pebs);
+        if (error < 0)
+                goto out;
 
-static const struct ds_configuration ds_cfg_pentium_m = {
-        .sizeof_ds = 9 * 4,
-        .bts_buffer_base = { 0, 4 },
-        .bts_index = { 4, 4 },
-        .bts_absolute_maximum = { 8, 4 },
-        .bts_interrupt_threshold = { 12, 4 },
-        .sizeof_bts = 3 * 4,
-        .from_ip = { 0, 4 },
-        .to_ip = { 4, 4 },
-        .info_type = { 4, 1 },
-        .info_data = { 8, 4 },
-        .debugctl_mask = (1<<6)|(1<<7)
+        *(u64 *)(context->ds + (ds_cfg.sizeof_field * 8)) = value;
+
+        error = 0;
+ out:
+        ds_put_context(context);
+        return error;
+}
+
+static const struct ds_configuration ds_cfg_var = {
+        .sizeof_ds    = sizeof(long) * 12,
+        .sizeof_field = sizeof(long),
+        .sizeof_rec[ds_bts]   = sizeof(long) * 3,
+        .sizeof_rec[ds_pebs]  = sizeof(long) * 10
 };
-#endif /* _i386_ */
-
-static const struct ds_configuration ds_cfg_core2 = {
-        .sizeof_ds = 9 * 8,
-        .bts_buffer_base = { 0, 8 },
-        .bts_index = { 8, 8 },
-        .bts_absolute_maximum = { 16, 8 },
-        .bts_interrupt_threshold = { 24, 8 },
-        .sizeof_bts = 3 * 8,
-        .from_ip = { 0, 8 },
-        .to_ip = { 8, 8 },
-        .info_type = { 8, 1 },
-        .info_data = { 16, 8 },
-        .debugctl_mask = (1<<6)|(1<<7)|(1<<9)
+static const struct ds_configuration ds_cfg_64 = {
+        .sizeof_ds    = 8 * 12,
+        .sizeof_field = 8,
+        .sizeof_rec[ds_bts]   = 8 * 3,
+        .sizeof_rec[ds_pebs]  = 8 * 10
 };
 
 static inline void
@@ -429,14 +821,13 @@ void __cpuinit ds_init_intel(struct cpuinfo_x86 *c)
         switch (c->x86) {
         case 0x6:
                 switch (c->x86_model) {
-#ifdef __i386__
                 case 0xD:
                 case 0xE: /* Pentium M */
-                        ds_configure(&ds_cfg_pentium_m);
+                        ds_configure(&ds_cfg_var);
                         break;
-#endif /* _i386_ */
                 case 0xF: /* Core2 */
-                        ds_configure(&ds_cfg_core2);
+                case 0x1C: /* Atom */
+                        ds_configure(&ds_cfg_64);
                         break;
                 default:
                         /* sorry, don't know about them */
@@ -445,13 +836,11 @@ void __cpuinit ds_init_intel(struct cpuinfo_x86 *c)
                 break;
         case 0xF:
                 switch (c->x86_model) {
-#ifdef __i386__
                 case 0x0:
                 case 0x1:
                 case 0x2: /* Netburst */
-                        ds_configure(&ds_cfg_netburst);
+                        ds_configure(&ds_cfg_var);
                         break;
-#endif /* _i386_ */
                 default:
                         /* sorry, don't know about them */
                         break;
@@ -462,3 +851,14 @@ void __cpuinit ds_init_intel(struct cpuinfo_x86 *c)
                 break;
         }
 }
+
+void ds_free(struct ds_context *context)
+{
+        /* This is called when the task owning the parameter context
+         * is dying. There should not be any user of that context left
+         * to disturb us, anymore. */
+        unsigned long leftovers = context->count;
+        while (leftovers--)
+                ds_put_context(context);
+}
+#endif /* CONFIG_X86_DS */
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index 66e48aa2dd1b..78e642feac30 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -148,6 +148,9 @@ void __init e820_print_map(char *who)
                 case E820_NVS:
                         printk(KERN_CONT "(ACPI NVS)\n");
                         break;
+                case E820_UNUSABLE:
+                        printk("(unusable)\n");
+                        break;
                 default:
                         printk(KERN_CONT "type %u\n", e820.map[i].type);
                         break;
@@ -1260,6 +1263,7 @@ static inline const char *e820_type_to_string(int e820_type)
         case E820_RAM:  return "System RAM";
         case E820_ACPI: return "ACPI Tables";
         case E820_NVS:  return "ACPI Non-volatile Storage";
+        case E820_UNUSABLE:     return "Unusable memory";
         default:        return "reserved";
         }
 }
@@ -1267,6 +1271,7 @@ static inline const char *e820_type_to_string(int e820_type)
 /*
  * Mark e820 reserved areas as busy for the resource manager.
  */
+static struct resource __initdata *e820_res;
 void __init e820_reserve_resources(void)
 {
         int i;
@@ -1274,6 +1279,7 @@ void __init e820_reserve_resources(void)
         u64 end;
 
         res = alloc_bootmem_low(sizeof(struct resource) * e820.nr_map);
+        e820_res = res;
         for (i = 0; i < e820.nr_map; i++) {
                 end = e820.map[i].addr + e820.map[i].size - 1;
 #ifndef CONFIG_RESOURCES_64BIT
@@ -1287,7 +1293,14 @@ void __init e820_reserve_resources(void)
                 res->end = end;
 
                 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
-                insert_resource(&iomem_resource, res);
+
+                /*
+                 * don't register the region that could be conflicted with
+                 * pci device BAR resource and insert them later in
+                 * pcibios_resource_survey()
+                 */
+                if (e820.map[i].type != E820_RESERVED || res->start < (1ULL<<20))
+                        insert_resource(&iomem_resource, res);
                 res++;
         }
 
@@ -1299,6 +1312,19 @@ void __init e820_reserve_resources(void)
         }
 }
 
+void __init e820_reserve_resources_late(void)
+{
+        int i;
+        struct resource *res;
+
+        res = e820_res;
+        for (i = 0; i < e820.nr_map; i++) {
+                if (!res->parent && res->end)
+                        reserve_region_with_split(&iomem_resource, res->start, res->end, res->name);
+                res++;
+        }
+}
+
 char *__init default_machine_specific_memory_setup(void)
 {
         char *who = "BIOS-e820";
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 4353cf5e6fac..24bb5faf5efa 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -95,6 +95,20 @@ static void __init nvidia_bugs(int num, int slot, int func)
 
 }
 
+#ifdef CONFIG_DMAR
+static void __init intel_g33_dmar(int num, int slot, int func)
+{
+        struct acpi_table_header *dmar_tbl;
+        acpi_status status;
+
+        status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
+        if (ACPI_SUCCESS(status)) {
+                printk(KERN_INFO "BIOS BUG: DMAR advertised on Intel G31/G33 chipset -- ignoring\n");
+                dmar_disabled = 1;
+        }
+}
+#endif
+
 #define QFLAG_APPLY_ONCE        0x1
 #define QFLAG_APPLIED           0x2
 #define QFLAG_DONE              (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@@ -114,6 +128,10 @@ static struct chipset early_qrk[] __initdata = {
           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
           PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
+#ifdef CONFIG_DMAR
+        { PCI_VENDOR_ID_INTEL, 0x29c0,
+          PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, intel_g33_dmar },
+#endif
         {}
 };
 
diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c
index 06cc8d4254b1..945a31cdd81f 100644
--- a/arch/x86/kernel/efi.c
+++ b/arch/x86/kernel/efi.c
@@ -414,9 +414,11 @@ void __init efi_init(void)
         if (memmap.map == NULL)
                 printk(KERN_ERR "Could not map the EFI memory map!\n");
         memmap.map_end = memmap.map + (memmap.nr_map * memmap.desc_size);
+
         if (memmap.desc_size != sizeof(efi_memory_desc_t))
-                printk(KERN_WARNING "Kernel-defined memdesc"
-                       "doesn't match the one from EFI!\n");
+                printk(KERN_WARNING
+                  "Kernel-defined memdesc doesn't match the one from EFI!\n");
+
         if (add_efi_memmap)
                 do_add_efi_memmap();
 
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 89434d439605..cf3a0b2d0059 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -275,9 +275,9 @@ ENTRY(native_usergs_sysret64)
 ENTRY(ret_from_fork)
         CFI_DEFAULT_STACK
         push kernel_eflags(%rip)
-        CFI_ADJUST_CFA_OFFSET 4
+        CFI_ADJUST_CFA_OFFSET 8
         popf                            # reset kernel eflags
-        CFI_ADJUST_CFA_OFFSET -4
+        CFI_ADJUST_CFA_OFFSET -8
         call schedule_tail
         GET_THREAD_INFO(%rcx)
         testl $(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT),TI_flags(%rcx)
diff --git a/arch/x86/mach-es7000/es7000plat.c b/arch/x86/kernel/es7000_32.c
index 50189af14b85..849e5cd485b8 100644
--- a/arch/x86/mach-es7000/es7000plat.c
+++ b/arch/x86/kernel/es7000_32.c
@@ -39,10 +39,93 @@
 #include <asm/nmi.h>
 #include <asm/smp.h>
 #include <asm/apicdef.h>
-#include "es7000.h"
 #include <mach_mpparse.h>
 
 /*
+ * ES7000 chipsets
+ */
+
+#define NON_UNISYS              0
+#define ES7000_CLASSIC          1
+#define ES7000_ZORRO            2
+
+
+#define MIP_REG                 1
+#define MIP_PSAI_REG            4
+
+#define MIP_BUSY                1
+#define MIP_SPIN                0xf0000
+#define MIP_VALID               0x0100000000000000ULL
+#define MIP_PORT(VALUE) ((VALUE >> 32) & 0xffff)
+
+#define MIP_RD_LO(VALUE)        (VALUE & 0xffffffff)
+
+struct mip_reg_info {
+        unsigned long long mip_info;
+        unsigned long long delivery_info;
+        unsigned long long host_reg;
+        unsigned long long mip_reg;
+};
+
+struct part_info {
+        unsigned char type;
+        unsigned char length;
+        unsigned char part_id;
+        unsigned char apic_mode;
+        unsigned long snum;
+        char ptype[16];
+        char sname[64];
+        char pname[64];
+};
+
+struct psai {
+        unsigned long long entry_type;
+        unsigned long long addr;
+        unsigned long long bep_addr;
+};
+
+struct es7000_mem_info {
+        unsigned char type;
+        unsigned char length;
+        unsigned char resv[6];
+        unsigned long long  start;
+        unsigned long long  size;
+};
+
+struct es7000_oem_table {
+        unsigned long long hdr;
+        struct mip_reg_info mip;
+        struct part_info pif;
+        struct es7000_mem_info shm;
+        struct psai psai;
+};
+
+#ifdef CONFIG_ACPI
+
+struct oem_table {
+        struct acpi_table_header Header;
+        u32 OEMTableAddr;
+        u32 OEMTableSize;
+};
+
+extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
+#endif
+
+struct mip_reg {
+        unsigned long long off_0;
+        unsigned long long off_8;
+        unsigned long long off_10;
+        unsigned long long off_18;
+        unsigned long long off_20;
+        unsigned long long off_28;
+        unsigned long long off_30;
+        unsigned long long off_38;
+};
+
+#define MIP_SW_APIC             0x1020b
+#define MIP_FUNC(VALUE)         (VALUE & 0xff)
+
+/*
  * ES7000 Globals
  */
 
@@ -72,7 +155,7 @@ es7000_rename_gsi(int ioapic, int gsi)
                         base += nr_ioapic_registers[i];
         }
 
-        if (!ioapic && (gsi < 16)) 
+        if (!ioapic && (gsi < 16))
                 gsi += base;
         return gsi;
 }
diff --git a/arch/x86/kernel/genapic_64.c b/arch/x86/kernel/genapic_64.c
index eaff0bbb1444..6c9bfc9e1e95 100644
--- a/arch/x86/kernel/genapic_64.c
+++ b/arch/x86/kernel/genapic_64.c
@@ -16,87 +16,63 @@
 #include <linux/ctype.h>
 #include <linux/init.h>
 #include <linux/hardirq.h>
+#include <linux/dmar.h>
 
 #include <asm/smp.h>
 #include <asm/ipi.h>
 #include <asm/genapic.h>
 
-#ifdef CONFIG_ACPI
-#include <acpi/acpi_bus.h>
-#endif
-
-DEFINE_PER_CPU(int, x2apic_extra_bits);
+extern struct genapic apic_flat;
+extern struct genapic apic_physflat;
+extern struct genapic apic_x2xpic_uv_x;
+extern struct genapic apic_x2apic_phys;
+extern struct genapic apic_x2apic_cluster;
 
 struct genapic __read_mostly *genapic = &apic_flat;
 
-static enum uv_system_type uv_system_type;
+static struct genapic *apic_probe[] __initdata = {
+        &apic_x2apic_uv_x,
+        &apic_x2apic_phys,
+        &apic_x2apic_cluster,
+        &apic_physflat,
+        NULL,
+};
 
 /*
  * Check the APIC IDs in bios_cpu_apicid and choose the APIC mode.
  */
 void __init setup_apic_routing(void)
 {
-        if (uv_system_type == UV_NON_UNIQUE_APIC)
-                genapic = &apic_x2apic_uv_x;
-        else
-#ifdef CONFIG_ACPI
-        /*
-         * Quirk: some x86_64 machines can only use physical APIC mode
-         * regardless of how many processors are present (x86_64 ES7000
-         * is an example).
-         */
-        if (acpi_gbl_FADT.header.revision > FADT2_REVISION_ID &&
-                        (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL))
-                genapic = &apic_physflat;
-        else
-#endif
-
-        if (max_physical_apicid < 8)
-                genapic = &apic_flat;
-        else
-                genapic = &apic_physflat;
+        if (genapic == &apic_x2apic_phys || genapic == &apic_x2apic_cluster) {
+                if (!intr_remapping_enabled)
+                        genapic = &apic_flat;
+        }
 
-        printk(KERN_INFO "Setting APIC routing to %s\n", genapic->name);
+        if (genapic == &apic_flat) {
+                if (max_physical_apicid >= 8)
+                        genapic = &apic_physflat;
+                printk(KERN_INFO "Setting APIC routing to %s\n", genapic->name);
+        }
 }
 
 /* Same for both flat and physical. */
 
-void send_IPI_self(int vector)
+void apic_send_IPI_self(int vector)
 {
         __send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
 }
 
 int __init acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
-        if (!strcmp(oem_id, "SGI")) {
-                if (!strcmp(oem_table_id, "UVL"))
-                        uv_system_type = UV_LEGACY_APIC;
-                else if (!strcmp(oem_table_id, "UVX"))
-                        uv_system_type = UV_X2APIC;
-                else if (!strcmp(oem_table_id, "UVH"))
-                        uv_system_type = UV_NON_UNIQUE_APIC;
+        int i;
+
+        for (i = 0; apic_probe[i]; ++i) {
+                if (apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id)) {
+                        genapic = apic_probe[i];
+                        printk(KERN_INFO "Setting APIC routing to %s.\n",
+                                genapic->name);
+                        return 1;
+                }
         }
         return 0;
 }
-
-unsigned int read_apic_id(void)
-{
-        unsigned int id;
-
-        WARN_ON(preemptible() && num_online_cpus() > 1);
-        id = apic_read(APIC_ID);
-        if (uv_system_type >= UV_X2APIC)
-                id  |= __get_cpu_var(x2apic_extra_bits);
-        return id;
-}
-
-enum uv_system_type get_uv_system_type(void)
-{
-        return uv_system_type;
-}
-
-int is_uv_system(void)
-{
-        return uv_system_type != UV_NONE;
-}
-EXPORT_SYMBOL_GPL(is_uv_system);
diff --git a/arch/x86/kernel/genapic_flat_64.c b/arch/x86/kernel/genapic_flat_64.c
index 786548a62d38..9eca5ba7a6b1 100644
--- a/arch/x86/kernel/genapic_flat_64.c
+++ b/arch/x86/kernel/genapic_flat_64.c
@@ -15,9 +15,20 @@
 #include <linux/kernel.h>
 #include <linux/ctype.h>
 #include <linux/init.h>
+#include <linux/hardirq.h>
 #include <asm/smp.h>
 #include <asm/ipi.h>
 #include <asm/genapic.h>
+#include <mach_apicdef.h>
+
+#ifdef CONFIG_ACPI
+#include <acpi/acpi_bus.h>
+#endif
+
+static int __init flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+        return 1;
+}
 
 static cpumask_t flat_target_cpus(void)
 {
@@ -95,9 +106,33 @@ static void flat_send_IPI_all(int vector)
                 __send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
 }
 
+static unsigned int get_apic_id(unsigned long x)
+{
+        unsigned int id;
+
+        id = (((x)>>24) & 0xFFu);
+        return id;
+}
+
+static unsigned long set_apic_id(unsigned int id)
+{
+        unsigned long x;
+
+        x = ((id & 0xFFu)<<24);
+        return x;
+}
+
+static unsigned int read_xapic_id(void)
+{
+        unsigned int id;
+
+        id = get_apic_id(apic_read(APIC_ID));
+        return id;
+}
+
 static int flat_apic_id_registered(void)
 {
-        return physid_isset(GET_APIC_ID(read_apic_id()), phys_cpu_present_map);
+        return physid_isset(read_xapic_id(), phys_cpu_present_map);
 }
 
 static unsigned int flat_cpu_mask_to_apicid(cpumask_t cpumask)
@@ -112,6 +147,7 @@ static unsigned int phys_pkg_id(int index_msb)
 
 struct genapic apic_flat =  {
         .name = "flat",
+        .acpi_madt_oem_check = flat_acpi_madt_oem_check,
         .int_delivery_mode = dest_LowestPrio,
         .int_dest_mode = (APIC_DEST_LOGICAL != 0),
         .target_cpus = flat_target_cpus,
@@ -121,8 +157,12 @@ struct genapic apic_flat =  {
         .send_IPI_all = flat_send_IPI_all,
         .send_IPI_allbutself = flat_send_IPI_allbutself,
         .send_IPI_mask = flat_send_IPI_mask,
+        .send_IPI_self = apic_send_IPI_self,
         .cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
         .phys_pkg_id = phys_pkg_id,
+        .get_apic_id = get_apic_id,
+        .set_apic_id = set_apic_id,
+        .apic_id_mask = (0xFFu<<24),
 };
 
 /*
@@ -130,6 +170,21 @@ struct genapic apic_flat =  {
  * We cannot use logical delivery in this case because the mask
  * overflows, so use physical mode.
  */
+static int __init physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+#ifdef CONFIG_ACPI
+        /*
+         * Quirk: some x86_64 machines can only use physical APIC mode
+         * regardless of how many processors are present (x86_64 ES7000
+         * is an example).
+         */
+        if (acpi_gbl_FADT.header.revision > FADT2_REVISION_ID &&
+                (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL))
+                return 1;
+#endif
+
+        return 0;
+}
 
 static cpumask_t physflat_target_cpus(void)
 {
@@ -176,6 +231,7 @@ static unsigned int physflat_cpu_mask_to_apicid(cpumask_t cpumask)
 
 struct genapic apic_physflat =  {
         .name = "physical flat",
+        .acpi_madt_oem_check = physflat_acpi_madt_oem_check,
         .int_delivery_mode = dest_Fixed,
         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
         .target_cpus = physflat_target_cpus,
@@ -185,6 +241,10 @@ struct genapic apic_physflat =  {
         .send_IPI_all = physflat_send_IPI_all,
         .send_IPI_allbutself = physflat_send_IPI_allbutself,
         .send_IPI_mask = physflat_send_IPI_mask,
+        .send_IPI_self = apic_send_IPI_self,
         .cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
         .phys_pkg_id = phys_pkg_id,
+        .get_apic_id = get_apic_id,
+        .set_apic_id = set_apic_id,
+        .apic_id_mask = (0xFFu<<24),
 };
diff --git a/arch/x86/kernel/genx2apic_cluster.c b/arch/x86/kernel/genx2apic_cluster.c
new file mode 100644
index 000000000000..e4bf2cc0d743
--- /dev/null
+++ b/arch/x86/kernel/genx2apic_cluster.c
@@ -0,0 +1,159 @@
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/ctype.h>
+#include <linux/init.h>
+#include <linux/dmar.h>
+
+#include <asm/smp.h>
+#include <asm/ipi.h>
+#include <asm/genapic.h>
+
+DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
+
+static int __init x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+        if (cpu_has_x2apic)
+                return 1;
+
+        return 0;
+}
+
+/* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
+
+static cpumask_t x2apic_target_cpus(void)
+{
+        return cpumask_of_cpu(0);
+}
+
+/*
+ * for now each logical cpu is in its own vector allocation domain.
+ */
+static cpumask_t x2apic_vector_allocation_domain(int cpu)
+{
+        cpumask_t domain = CPU_MASK_NONE;
+        cpu_set(cpu, domain);
+        return domain;
+}
+
+static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
+                                   unsigned int dest)
+{
+        unsigned long cfg;
+
+        cfg = __prepare_ICR(0, vector, dest);
+
+        /*
+         * send the IPI.
+         */
+        x2apic_icr_write(cfg, apicid);
+}
+
+/*
+ * for now, we send the IPI's one by one in the cpumask.
+ * TBD: Based on the cpu mask, we can send the IPI's to the cluster group
+ * at once. We have 16 cpu's in a cluster. This will minimize IPI register
+ * writes.
+ */
+static void x2apic_send_IPI_mask(cpumask_t mask, int vector)
+{
+        unsigned long flags;
+        unsigned long query_cpu;
+
+        local_irq_save(flags);
+        for_each_cpu_mask(query_cpu, mask) {
+                __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_logical_apicid, query_cpu),
+                                       vector, APIC_DEST_LOGICAL);
+        }
+        local_irq_restore(flags);
+}
+
+static void x2apic_send_IPI_allbutself(int vector)
+{
+        cpumask_t mask = cpu_online_map;
+
+        cpu_clear(smp_processor_id(), mask);
+
+        if (!cpus_empty(mask))
+                x2apic_send_IPI_mask(mask, vector);
+}
+
+static void x2apic_send_IPI_all(int vector)
+{
+        x2apic_send_IPI_mask(cpu_online_map, vector);
+}
+
+static int x2apic_apic_id_registered(void)
+{
+        return 1;
+}
+
+static unsigned int x2apic_cpu_mask_to_apicid(cpumask_t cpumask)
+{
+        int cpu;
+
+        /*
+         * We're using fixed IRQ delivery, can only return one phys APIC ID.
+         * May as well be the first.
+         */
+        cpu = first_cpu(cpumask);
+        if ((unsigned)cpu < NR_CPUS)
+                return per_cpu(x86_cpu_to_logical_apicid, cpu);
+        else
+                return BAD_APICID;
+}
+
+static unsigned int get_apic_id(unsigned long x)
+{
+        unsigned int id;
+
+        id = x;
+        return id;
+}
+
+static unsigned long set_apic_id(unsigned int id)
+{
+        unsigned long x;
+
+        x = id;
+        return x;
+}
+
+static unsigned int phys_pkg_id(int index_msb)
+{
+        return current_cpu_data.initial_apicid >> index_msb;
+}
+
+static void x2apic_send_IPI_self(int vector)
+{
+        apic_write(APIC_SELF_IPI, vector);
+}
+
+static void init_x2apic_ldr(void)
+{
+        int cpu = smp_processor_id();
+
+        per_cpu(x86_cpu_to_logical_apicid, cpu) = apic_read(APIC_LDR);
+        return;
+}
+
+struct genapic apic_x2apic_cluster = {
+        .name = "cluster x2apic",
+        .acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
+        .int_delivery_mode = dest_LowestPrio,
+        .int_dest_mode = (APIC_DEST_LOGICAL != 0),
+        .target_cpus = x2apic_target_cpus,
+        .vector_allocation_domain = x2apic_vector_allocation_domain,
+        .apic_id_registered = x2apic_apic_id_registered,
+        .init_apic_ldr = init_x2apic_ldr,
+        .send_IPI_all = x2apic_send_IPI_all,
+        .send_IPI_allbutself = x2apic_send_IPI_allbutself,
+        .send_IPI_mask = x2apic_send_IPI_mask,
+        .send_IPI_self = x2apic_send_IPI_self,
+        .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
+        .phys_pkg_id = phys_pkg_id,
+        .get_apic_id = get_apic_id,
+        .set_apic_id = set_apic_id,
+        .apic_id_mask = (0xFFFFFFFFu),
+};
diff --git a/arch/x86/kernel/genx2apic_phys.c b/arch/x86/kernel/genx2apic_phys.c
new file mode 100644
index 000000000000..8f1343df2627
--- /dev/null
+++ b/arch/x86/kernel/genx2apic_phys.c
@@ -0,0 +1,154 @@
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/ctype.h>
+#include <linux/init.h>
+#include <linux/dmar.h>
+
+#include <asm/smp.h>
+#include <asm/ipi.h>
+#include <asm/genapic.h>
+
+static int x2apic_phys;
+
+static int set_x2apic_phys_mode(char *arg)
+{
+        x2apic_phys = 1;
+        return 0;
+}
+early_param("x2apic_phys", set_x2apic_phys_mode);
+
+static int __init x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+        if (cpu_has_x2apic && x2apic_phys)
+                return 1;
+
+        return 0;
+}
+
+/* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
+
+static cpumask_t x2apic_target_cpus(void)
+{
+        return cpumask_of_cpu(0);
+}
+
+static cpumask_t x2apic_vector_allocation_domain(int cpu)
+{
+        cpumask_t domain = CPU_MASK_NONE;
+        cpu_set(cpu, domain);
+        return domain;
+}
+
+static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
+                                   unsigned int dest)
+{
+        unsigned long cfg;
+
+        cfg = __prepare_ICR(0, vector, dest);
+
+        /*
+         * send the IPI.
+         */
+        x2apic_icr_write(cfg, apicid);
+}
+
+static void x2apic_send_IPI_mask(cpumask_t mask, int vector)
+{
+        unsigned long flags;
+        unsigned long query_cpu;
+
+        local_irq_save(flags);
+        for_each_cpu_mask(query_cpu, mask) {
+                __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
+                                       vector, APIC_DEST_PHYSICAL);
+        }
+        local_irq_restore(flags);
+}
+
+static void x2apic_send_IPI_allbutself(int vector)
+{
+        cpumask_t mask = cpu_online_map;
+
+        cpu_clear(smp_processor_id(), mask);
+
+        if (!cpus_empty(mask))
+                x2apic_send_IPI_mask(mask, vector);
+}
+
+static void x2apic_send_IPI_all(int vector)
+{
+        x2apic_send_IPI_mask(cpu_online_map, vector);
+}
+
+static int x2apic_apic_id_registered(void)
+{
+        return 1;
+}
+
+static unsigned int x2apic_cpu_mask_to_apicid(cpumask_t cpumask)
+{
+        int cpu;
+
+        /*
+         * We're using fixed IRQ delivery, can only return one phys APIC ID.
+         * May as well be the first.
+         */
+        cpu = first_cpu(cpumask);
+        if ((unsigned)cpu < NR_CPUS)
+                return per_cpu(x86_cpu_to_apicid, cpu);
+        else
+                return BAD_APICID;
+}
+
+static unsigned int get_apic_id(unsigned long x)
+{
+        unsigned int id;
+
+        id = x;
+        return id;
+}
+
+static unsigned long set_apic_id(unsigned int id)
+{
+        unsigned long x;
+
+        x = id;
+        return x;
+}
+
+static unsigned int phys_pkg_id(int index_msb)
+{
+        return current_cpu_data.initial_apicid >> index_msb;
+}
+
+void x2apic_send_IPI_self(int vector)
+{
+        apic_write(APIC_SELF_IPI, vector);
+}
+
+void init_x2apic_ldr(void)
+{
+        return;
+}
+
+struct genapic apic_x2apic_phys = {
+        .name = "physical x2apic",
+        .acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
+        .int_delivery_mode = dest_Fixed,
+        .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
+        .target_cpus = x2apic_target_cpus,
+        .vector_allocation_domain = x2apic_vector_allocation_domain,
+        .apic_id_registered = x2apic_apic_id_registered,
+        .init_apic_ldr = init_x2apic_ldr,
+        .send_IPI_all = x2apic_send_IPI_all,
+        .send_IPI_allbutself = x2apic_send_IPI_allbutself,
+        .send_IPI_mask = x2apic_send_IPI_mask,
+        .send_IPI_self = x2apic_send_IPI_self,
+        .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
+        .phys_pkg_id = phys_pkg_id,
+        .get_apic_id = get_apic_id,
+        .set_apic_id = set_apic_id,
+        .apic_id_mask = (0xFFFFFFFFu),
+};
diff --git a/arch/x86/kernel/genx2apic_uv_x.c b/arch/x86/kernel/genx2apic_uv_x.c
index bfa837cb16be..ae2ffc8a400c 100644
--- a/arch/x86/kernel/genx2apic_uv_x.c
+++ b/arch/x86/kernel/genx2apic_uv_x.c
@@ -12,12 +12,12 @@
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 #include <linux/string.h>
-#include <linux/kernel.h>
 #include <linux/ctype.h>
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/bootmem.h>
 #include <linux/module.h>
+#include <linux/hardirq.h>
 #include <asm/smp.h>
 #include <asm/ipi.h>
 #include <asm/genapic.h>
@@ -26,6 +26,36 @@
 #include <asm/uv/uv_hub.h>
 #include <asm/uv/bios.h>
 
+DEFINE_PER_CPU(int, x2apic_extra_bits);
+
+static enum uv_system_type uv_system_type;
+
+static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+{
+        if (!strcmp(oem_id, "SGI")) {
+                if (!strcmp(oem_table_id, "UVL"))
+                        uv_system_type = UV_LEGACY_APIC;
+                else if (!strcmp(oem_table_id, "UVX"))
+                        uv_system_type = UV_X2APIC;
+                else if (!strcmp(oem_table_id, "UVH")) {
+                        uv_system_type = UV_NON_UNIQUE_APIC;
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+enum uv_system_type get_uv_system_type(void)
+{
+        return uv_system_type;
+}
+
+int is_uv_system(void)
+{
+        return uv_system_type != UV_NONE;
+}
+EXPORT_SYMBOL_GPL(is_uv_system);
+
 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 
@@ -123,6 +153,10 @@ static int uv_apic_id_registered(void)
         return 1;
 }
 
+static void uv_init_apic_ldr(void)
+{
+}
+
 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
 {
         int cpu;
@@ -138,9 +172,34 @@ static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
                 return BAD_APICID;
 }
 
+static unsigned int get_apic_id(unsigned long x)
+{
+        unsigned int id;
+
+        WARN_ON(preemptible() && num_online_cpus() > 1);
+        id = x | __get_cpu_var(x2apic_extra_bits);
+
+        return id;
+}
+
+static unsigned long set_apic_id(unsigned int id)
+{
+        unsigned long x;
+
+        /* maskout x2apic_extra_bits ? */
+        x = id;
+        return x;
+}
+
+static unsigned int uv_read_apic_id(void)
+{
+
+        return get_apic_id(apic_read(APIC_ID));
+}
+
 static unsigned int phys_pkg_id(int index_msb)
 {
-        return GET_APIC_ID(read_apic_id()) >> index_msb;
+        return uv_read_apic_id() >> index_msb;
 }
 
 #ifdef ZZZ              /* Needs x2apic patch */
@@ -152,17 +211,22 @@ static void uv_send_IPI_self(int vector)
 
 struct genapic apic_x2apic_uv_x = {
         .name = "UV large system",
+        .acpi_madt_oem_check = uv_acpi_madt_oem_check,
         .int_delivery_mode = dest_Fixed,
         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
         .target_cpus = uv_target_cpus,
         .vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
         .apic_id_registered = uv_apic_id_registered,
+        .init_apic_ldr = uv_init_apic_ldr,
         .send_IPI_all = uv_send_IPI_all,
         .send_IPI_allbutself = uv_send_IPI_allbutself,
         .send_IPI_mask = uv_send_IPI_mask,
         /* ZZZ.send_IPI_self = uv_send_IPI_self, */
         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
         .phys_pkg_id = phys_pkg_id,     /* Fixme ZZZ */
+        .get_apic_id = get_apic_id,
+        .set_apic_id = set_apic_id,
+        .apic_id_mask = (0xFFFFFFFFu),
 };
 
 static __cpuinit void set_x2apic_extra_bits(int pnode)
@@ -401,3 +465,5 @@ void __cpuinit uv_cpu_init(void)
         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
                 set_x2apic_extra_bits(uv_hub_info->pnode);
 }
+
+
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 9bfc4d72fb2e..d16084f90649 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -108,12 +108,11 @@ void __init x86_64_start_kernel(char * real_mode_data)
         }
         load_idt((const struct desc_ptr *)&idt_descr);
 
-        early_printk("Kernel alive\n");
+        if (console_loglevel == 10)
+                early_printk("Kernel alive\n");
 
         x86_64_init_pda();
 
-        early_printk("Kernel really alive\n");
-
         x86_64_start_reservations(real_mode_data);
 }
 
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index a7010c3a377a..e835b4eea70b 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -172,10 +172,6 @@ num_subarch_entries = (. - subarch_entries) / 4
  *
  * Note that the stack is not yet set up!
  */
-#define PTE_ATTR        0x007           /* PRESENT+RW+USER */
-#define PDE_ATTR        0x067           /* PRESENT+RW+USER+DIRTY+ACCESSED */
-#define PGD_ATTR        0x001           /* PRESENT (no other attributes) */
-
 default_entry:
 #ifdef CONFIG_X86_PAE
 
@@ -196,9 +192,9 @@ default_entry:
         movl $pa(pg0), %edi
         movl %edi, pa(init_pg_tables_start)
         movl $pa(swapper_pg_pmd), %edx
-        movl $PTE_ATTR, %eax
+        movl $PTE_IDENT_ATTR, %eax
 10:
-        leal PDE_ATTR(%edi),%ecx                /* Create PMD entry */
+        leal PDE_IDENT_ATTR(%edi),%ecx          /* Create PMD entry */
         movl %ecx,(%edx)                        /* Store PMD entry */
                                                 /* Upper half already zero */
         addl $8,%edx
@@ -215,7 +211,7 @@ default_entry:
          * End condition: we must map up to and including INIT_MAP_BEYOND_END
          * bytes beyond the end of our own page tables.
          */
-        leal (INIT_MAP_BEYOND_END+PTE_ATTR)(%edi),%ebp
+        leal (INIT_MAP_BEYOND_END+PTE_IDENT_ATTR)(%edi),%ebp
         cmpl %ebp,%eax
         jb 10b
 1:
@@ -224,7 +220,7 @@ default_entry:
         movl %eax, pa(max_pfn_mapped)
 
         /* Do early initialization of the fixmap area */
-        movl $pa(swapper_pg_fixmap)+PDE_ATTR,%eax
+        movl $pa(swapper_pg_fixmap)+PDE_IDENT_ATTR,%eax
         movl %eax,pa(swapper_pg_pmd+0x1000*KPMDS-8)
 #else   /* Not PAE */
 
@@ -233,9 +229,9 @@ page_pde_offset = (__PAGE_OFFSET >> 20);
         movl $pa(pg0), %edi
         movl %edi, pa(init_pg_tables_start)
         movl $pa(swapper_pg_dir), %edx
-        movl $PTE_ATTR, %eax
+        movl $PTE_IDENT_ATTR, %eax
 10:
-        leal PDE_ATTR(%edi),%ecx                /* Create PDE entry */
+        leal PDE_IDENT_ATTR(%edi),%ecx          /* Create PDE entry */
         movl %ecx,(%edx)                        /* Store identity PDE entry */
         movl %ecx,page_pde_offset(%edx)         /* Store kernel PDE entry */
         addl $4,%edx
@@ -249,7 +245,7 @@ page_pde_offset = (__PAGE_OFFSET >> 20);
          * bytes beyond the end of our own page tables; the +0x007 is
          * the attribute bits
          */
-        leal (INIT_MAP_BEYOND_END+PTE_ATTR)(%edi),%ebp
+        leal (INIT_MAP_BEYOND_END+PTE_IDENT_ATTR)(%edi),%ebp
         cmpl %ebp,%eax
         jb 10b
         movl %edi,pa(init_pg_tables_end)
@@ -257,7 +253,7 @@ page_pde_offset = (__PAGE_OFFSET >> 20);
         movl %eax, pa(max_pfn_mapped)
 
         /* Do early initialization of the fixmap area */
-        movl $pa(swapper_pg_fixmap)+PDE_ATTR,%eax
+        movl $pa(swapper_pg_fixmap)+PDE_IDENT_ATTR,%eax
         movl %eax,pa(swapper_pg_dir+0xffc)
 #endif
         jmp 3f
@@ -634,19 +630,19 @@ ENTRY(empty_zero_page)
         /* Page-aligned for the benefit of paravirt? */
         .align PAGE_SIZE_asm
 ENTRY(swapper_pg_dir)
-        .long   pa(swapper_pg_pmd+PGD_ATTR),0           /* low identity map */
+        .long   pa(swapper_pg_pmd+PGD_IDENT_ATTR),0     /* low identity map */
 # if KPMDS == 3
-        .long   pa(swapper_pg_pmd+PGD_ATTR),0
-        .long   pa(swapper_pg_pmd+PGD_ATTR+0x1000),0
-        .long   pa(swapper_pg_pmd+PGD_ATTR+0x2000),0
+        .long   pa(swapper_pg_pmd+PGD_IDENT_ATTR),0
+        .long   pa(swapper_pg_pmd+PGD_IDENT_ATTR+0x1000),0
+        .long   pa(swapper_pg_pmd+PGD_IDENT_ATTR+0x2000),0
 # elif KPMDS == 2
         .long   0,0
-        .long   pa(swapper_pg_pmd+PGD_ATTR),0
-        .long   pa(swapper_pg_pmd+PGD_ATTR+0x1000),0
+        .long   pa(swapper_pg_pmd+PGD_IDENT_ATTR),0
+        .long   pa(swapper_pg_pmd+PGD_IDENT_ATTR+0x1000),0
 # elif KPMDS == 1
         .long   0,0
         .long   0,0
-        .long   pa(swapper_pg_pmd+PGD_ATTR),0
+        .long   pa(swapper_pg_pmd+PGD_IDENT_ATTR),0
 # else
 #  error "Kernel PMDs should be 1, 2 or 3"
 # endif
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index db3280afe886..26cfdc1d7c7f 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -110,7 +110,7 @@ startup_64:
         movq    %rdi, %rax
         shrq    $PMD_SHIFT, %rax
         andq    $(PTRS_PER_PMD - 1), %rax
-        leaq    __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx
+        leaq    __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
         leaq    level2_spare_pgt(%rip), %rbx
         movq    %rdx, 0(%rbx, %rax, 8)
 ident_complete:
@@ -374,7 +374,7 @@ NEXT_PAGE(level2_ident_pgt)
         /* Since I easily can, map the first 1G.
          * Don't set NX because code runs from these pages.
          */
-        PMDS(0, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD)
+        PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
 
 NEXT_PAGE(level2_kernel_pgt)
         /*
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index eb9ddd8efb82..45723f1fe198 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -21,9 +21,12 @@
 # include <asm/sigcontext32.h>
 # include <asm/user32.h>
 #else
-# define save_i387_ia32         save_i387
-# define restore_i387_ia32      restore_i387
+# define save_i387_xstate_ia32          save_i387_xstate
+# define restore_i387_xstate_ia32       restore_i387_xstate
 # define _fpstate_ia32          _fpstate
+# define _xstate_ia32           _xstate
+# define sig_xstate_ia32_size   sig_xstate_size
+# define fx_sw_reserved_ia32    fx_sw_reserved
 # define user_i387_ia32_struct  user_i387_struct
 # define user32_fxsr_struct     user_fxsr_struct
 #endif
@@ -36,6 +39,7 @@
 
 static unsigned int             mxcsr_feature_mask __read_mostly = 0xffffffffu;
 unsigned int xstate_size;
+unsigned int sig_xstate_ia32_size = sizeof(struct _fpstate_ia32);
 static struct i387_fxsave_struct fx_scratch __cpuinitdata;
 
 void __cpuinit mxcsr_feature_mask_init(void)
@@ -61,6 +65,11 @@ void __init init_thread_xstate(void)
                 return;
         }
 
+        if (cpu_has_xsave) {
+                xsave_cntxt_init();
+                return;
+        }
+
         if (cpu_has_fxsr)
                 xstate_size = sizeof(struct i387_fxsave_struct);
 #ifdef CONFIG_X86_32
@@ -83,9 +92,19 @@ void __cpuinit fpu_init(void)
 
         write_cr0(oldcr0 & ~(X86_CR0_TS|X86_CR0_EM)); /* clear TS and EM */
 
+        /*
+         * Boot processor to setup the FP and extended state context info.
+         */
+        if (!smp_processor_id())
+                init_thread_xstate();
+        xsave_init();
+
         mxcsr_feature_mask_init();
         /* clean state in init */
-        current_thread_info()->status = 0;
+        if (cpu_has_xsave)
+                current_thread_info()->status = TS_XSAVE;
+        else
+                current_thread_info()->status = 0;
         clear_used_math();
 }
 #endif  /* CONFIG_X86_64 */
@@ -195,6 +214,13 @@ int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
          */
         target->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask;
 
+        /*
+         * update the header bits in the xsave header, indicating the
+         * presence of FP and SSE state.
+         */
+        if (cpu_has_xsave)
+                target->thread.xstate->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE;
+
         return ret;
 }
 
@@ -395,6 +421,12 @@ int fpregs_set(struct task_struct *target, const struct user_regset *regset,
         if (!ret)
                 convert_to_fxsr(target, &env);
 
+        /*
+         * update the header bit in the xsave header, indicating the
+         * presence of FP.
+         */
+        if (cpu_has_xsave)
+                target->thread.xstate->xsave.xsave_hdr.xstate_bv |= XSTATE_FP;
         return ret;
 }
 
@@ -407,7 +439,6 @@ static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf)
         struct task_struct *tsk = current;
         struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave;
 
-        unlazy_fpu(tsk);
         fp->status = fp->swd;
         if (__copy_to_user(buf, fp, sizeof(struct i387_fsave_struct)))
                 return -1;
@@ -421,8 +452,6 @@ static int save_i387_fxsave(struct _fpstate_ia32 __user *buf)
         struct user_i387_ia32_struct env;
         int err = 0;
 
-        unlazy_fpu(tsk);
-
         convert_from_fxsr(&env, tsk);
         if (__copy_to_user(buf, &env, sizeof(env)))
                 return -1;
@@ -432,16 +461,40 @@ static int save_i387_fxsave(struct _fpstate_ia32 __user *buf)
         if (err)
                 return -1;
 
-        if (__copy_to_user(&buf->_fxsr_env[0], fx,
-                           sizeof(struct i387_fxsave_struct)))
+        if (__copy_to_user(&buf->_fxsr_env[0], fx, xstate_size))
                 return -1;
         return 1;
 }
 
-int save_i387_ia32(struct _fpstate_ia32 __user *buf)
+static int save_i387_xsave(void __user *buf)
+{
+        struct _fpstate_ia32 __user *fx = buf;
+        int err = 0;
+
+        if (save_i387_fxsave(fx) < 0)
+                return -1;
+
+        err = __copy_to_user(&fx->sw_reserved, &fx_sw_reserved_ia32,
+                             sizeof(struct _fpx_sw_bytes));
+        err |= __put_user(FP_XSTATE_MAGIC2,
+                          (__u32 __user *) (buf + sig_xstate_ia32_size
+                                            - FP_XSTATE_MAGIC2_SIZE));
+        if (err)
+                return -1;
+
+        return 1;
+}
+
+int save_i387_xstate_ia32(void __user *buf)
 {
+        struct _fpstate_ia32 __user *fp = (struct _fpstate_ia32 __user *) buf;
+        struct task_struct *tsk = current;
+
         if (!used_math())
                 return 0;
+
+        if (!access_ok(VERIFY_WRITE, buf, sig_xstate_ia32_size))
+                return -EACCES;
         /*
          * This will cause a "finit" to be triggered by the next
          * attempted FPU operation by the 'current' process.
@@ -451,13 +504,17 @@ int save_i387_ia32(struct _fpstate_ia32 __user *buf)
         if (!HAVE_HWFP) {
                 return fpregs_soft_get(current, NULL,
                                        0, sizeof(struct user_i387_ia32_struct),
-                                       NULL, buf) ? -1 : 1;
+                                       NULL, fp) ? -1 : 1;
         }
 
+        unlazy_fpu(tsk);
+
+        if (cpu_has_xsave)
+                return save_i387_xsave(fp);
         if (cpu_has_fxsr)
-                return save_i387_fxsave(buf);
+                return save_i387_fxsave(fp);
         else
-                return save_i387_fsave(buf);
+                return save_i387_fsave(fp);
 }
 
 static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf)
@@ -468,14 +525,15 @@ static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf)
                                 sizeof(struct i387_fsave_struct));
 }
 
-static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf)
+static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf,
+                               unsigned int size)
 {
         struct task_struct *tsk = current;
         struct user_i387_ia32_struct env;
         int err;
 
         err = __copy_from_user(&tsk->thread.xstate->fxsave, &buf->_fxsr_env[0],
-                               sizeof(struct i387_fxsave_struct));
+                               size);
         /* mxcsr reserved bits must be masked to zero for security reasons */
         tsk->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask;
         if (err || __copy_from_user(&env, buf, sizeof(env)))
@@ -485,14 +543,69 @@ static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf)
         return 0;
 }
 
-int restore_i387_ia32(struct _fpstate_ia32 __user *buf)
+static int restore_i387_xsave(void __user *buf)
+{
+        struct _fpx_sw_bytes fx_sw_user;
+        struct _fpstate_ia32 __user *fx_user =
+                        ((struct _fpstate_ia32 __user *) buf);
+        struct i387_fxsave_struct __user *fx =
+                (struct i387_fxsave_struct __user *) &fx_user->_fxsr_env[0];
+        struct xsave_hdr_struct *xsave_hdr =
+                                &current->thread.xstate->xsave.xsave_hdr;
+        u64 mask;
+        int err;
+
+        if (check_for_xstate(fx, buf, &fx_sw_user))
+                goto fx_only;
+
+        mask = fx_sw_user.xstate_bv;
+
+        err = restore_i387_fxsave(buf, fx_sw_user.xstate_size);
+
+        xsave_hdr->xstate_bv &= pcntxt_mask;
+        /*
+         * These bits must be zero.
+         */
+        xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0;
+
+        /*
+         * Init the state that is not present in the memory layout
+         * and enabled by the OS.
+         */
+        mask = ~(pcntxt_mask & ~mask);
+        xsave_hdr->xstate_bv &= mask;
+
+        return err;
+fx_only:
+        /*
+         * Couldn't find the extended state information in the memory
+         * layout. Restore the FP/SSE and init the other extended state
+         * enabled by the OS.
+         */
+        xsave_hdr->xstate_bv = XSTATE_FPSSE;
+        return restore_i387_fxsave(buf, sizeof(struct i387_fxsave_struct));
+}
+
+int restore_i387_xstate_ia32(void __user *buf)
 {
         int err;
         struct task_struct *tsk = current;
+        struct _fpstate_ia32 __user *fp = (struct _fpstate_ia32 __user *) buf;
 
         if (HAVE_HWFP)
                 clear_fpu(tsk);
 
+        if (!buf) {
+                if (used_math()) {
+                        clear_fpu(tsk);
+                        clear_used_math();
+                }
+
+                return 0;
+        } else
+                if (!access_ok(VERIFY_READ, buf, sig_xstate_ia32_size))
+                        return -EACCES;
+
         if (!used_math()) {
                 err = init_fpu(tsk);
                 if (err)
@@ -500,14 +613,17 @@ int restore_i387_ia32(struct _fpstate_ia32 __user *buf)
         }
 
         if (HAVE_HWFP) {
-                if (cpu_has_fxsr)
-                        err = restore_i387_fxsave(buf);
+                if (cpu_has_xsave)
+                        err = restore_i387_xsave(buf);
+                else if (cpu_has_fxsr)
+                        err = restore_i387_fxsave(fp, sizeof(struct
+                                                           i387_fxsave_struct));
                 else
-                        err = restore_i387_fsave(buf);
+                        err = restore_i387_fsave(fp);
         } else {
                 err = fpregs_soft_set(current, NULL,
                                       0, sizeof(struct user_i387_ia32_struct),
-                                      NULL, buf) != 0;
+                                      NULL, fp) != 0;
         }
         set_used_math();
 
diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c
index dc92b49d9204..4b8a53d841f7 100644
--- a/arch/x86/kernel/i8259.c
+++ b/arch/x86/kernel/i8259.c
@@ -282,6 +282,30 @@ static int __init i8259A_init_sysfs(void)
 
 device_initcall(i8259A_init_sysfs);
 
+void mask_8259A(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&i8259A_lock, flags);
+
+        outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
+        outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
+
+        spin_unlock_irqrestore(&i8259A_lock, flags);
+}
+
+void unmask_8259A(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&i8259A_lock, flags);
+
+        outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
+        outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
+
+        spin_unlock_irqrestore(&i8259A_lock, flags);
+}
+
 void init_8259A(int auto_eoi)
 {
         unsigned long flags;
diff --git a/arch/x86/kernel/io_apic_32.c b/arch/x86/kernel/io_apic_32.c
index 09cddb57bec4..e710289f673e 100644
--- a/arch/x86/kernel/io_apic_32.c
+++ b/arch/x86/kernel/io_apic_32.c
@@ -46,10 +46,13 @@
 #include <asm/nmi.h>
 #include <asm/msidef.h>
 #include <asm/hypertransport.h>
+#include <asm/setup.h>
 
 #include <mach_apic.h>
 #include <mach_apicdef.h>
 
+#define __apicdebuginit(type) static type __init
+
 int (*ioapic_renumber_irq)(int ioapic, int irq);
 atomic_t irq_mis_count;
 
@@ -1341,7 +1344,8 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
         ioapic_write_entry(apic, pin, entry);
 }
 
-void __init print_IO_APIC(void)
+
+__apicdebuginit(void) print_IO_APIC(void)
 {
         int apic, i;
         union IO_APIC_reg_00 reg_00;
@@ -1456,9 +1460,7 @@ void __init print_IO_APIC(void)
         return;
 }
 
-#if 0
-
-static void print_APIC_bitfield(int base)
+__apicdebuginit(void) print_APIC_bitfield(int base)
 {
         unsigned int v;
         int i, j;
@@ -1479,9 +1481,10 @@ static void print_APIC_bitfield(int base)
         }
 }
 
-void /*__init*/ print_local_APIC(void *dummy)
+__apicdebuginit(void) print_local_APIC(void *dummy)
 {
         unsigned int v, ver, maxlvt;
+        u64 icr;
 
         if (apic_verbosity == APIC_QUIET)
                 return;
@@ -1490,7 +1493,7 @@ void /*__init*/ print_local_APIC(void *dummy)
                 smp_processor_id(), hard_smp_processor_id());
         v = apic_read(APIC_ID);
         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v,
-                        GET_APIC_ID(read_apic_id()));
+                        GET_APIC_ID(v));
         v = apic_read(APIC_LVR);
         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
         ver = GET_APIC_VERSION(v);
@@ -1532,10 +1535,9 @@ void /*__init*/ print_local_APIC(void *dummy)
                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
         }
 
-        v = apic_read(APIC_ICR);
-        printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
-        v = apic_read(APIC_ICR2);
-        printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
+        icr = apic_icr_read();
+        printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
+        printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
 
         v = apic_read(APIC_LVTT);
         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
@@ -1563,12 +1565,12 @@ void /*__init*/ print_local_APIC(void *dummy)
         printk("\n");
 }
 
-void print_all_local_APICs(void)
+__apicdebuginit(void) print_all_local_APICs(void)
 {
         on_each_cpu(print_local_APIC, NULL, 1);
 }
 
-void /*__init*/ print_PIC(void)
+__apicdebuginit(void) print_PIC(void)
 {
         unsigned int v;
         unsigned long flags;
@@ -1600,7 +1602,17 @@ void /*__init*/ print_PIC(void)
         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
 }
 
-#endif  /*  0  */
+__apicdebuginit(int) print_all_ICs(void)
+{
+        print_PIC();
+        print_all_local_APICs();
+        print_IO_APIC();
+
+        return 0;
+}
+
+fs_initcall(print_all_ICs);
+
 
 static void __init enable_IO_APIC(void)
 {
@@ -1698,8 +1710,7 @@ void disable_IO_APIC(void)
                 entry.dest_mode       = 0; /* Physical */
                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
                 entry.vector          = 0;
-                entry.dest.physical.physical_dest =
-                                        GET_APIC_ID(read_apic_id());
+                entry.dest.physical.physical_dest = read_apic_id();
 
                 /*
                  * Add it to the IO-APIC irq-routing table:
@@ -1725,10 +1736,8 @@ static void __init setup_ioapic_ids_from_mpc(void)
         unsigned char old_id;
         unsigned long flags;
 
-#ifdef CONFIG_X86_NUMAQ
-        if (found_numaq)
+        if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
                 return;
-#endif
 
         /*
          * Don't check I/O APIC IDs for xAPIC systems.  They have
@@ -2329,8 +2338,6 @@ void __init setup_IO_APIC(void)
         setup_IO_APIC_irqs();
         init_IO_APIC_traps();
         check_timer();
-        if (!acpi_ioapic)
-                print_IO_APIC();
 }
 
 /*
diff --git a/arch/x86/kernel/io_apic_64.c b/arch/x86/kernel/io_apic_64.c
index 61a83b70c18f..a1bec2969c6a 100644
--- a/arch/x86/kernel/io_apic_64.c
+++ b/arch/x86/kernel/io_apic_64.c
@@ -37,6 +37,7 @@
 #include <acpi/acpi_bus.h>
 #endif
 #include <linux/bootmem.h>
+#include <linux/dmar.h>
 
 #include <asm/idle.h>
 #include <asm/io.h>
@@ -49,10 +50,13 @@
 #include <asm/nmi.h>
 #include <asm/msidef.h>
 #include <asm/hypertransport.h>
+#include <asm/irq_remapping.h>
 
 #include <mach_ipi.h>
 #include <mach_apic.h>
 
+#define __apicdebuginit(type) static type __init
+
 struct irq_cfg {
         cpumask_t domain;
         cpumask_t old_domain;
@@ -87,8 +91,6 @@ int first_system_vector = 0xfe;
 
 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
 
-#define __apicdebuginit  __init
-
 int sis_apic_bug; /* not actually supported, dummy for compile */
 
 static int no_timer_check;
@@ -108,6 +110,9 @@ static DEFINE_SPINLOCK(vector_lock);
  */
 int nr_ioapic_registers[MAX_IO_APICS];
 
+/* I/O APIC RTE contents at the OS boot up */
+struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
+
 /* I/O APIC entries */
 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
 int nr_ioapics;
@@ -303,7 +308,12 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
                 pin = entry->pin;
                 if (pin == -1)
                         break;
-                io_apic_write(apic, 0x11 + pin*2, dest);
+                /*
+                 * With interrupt-remapping, destination information comes
+                 * from interrupt-remapping table entry.
+                 */
+                if (!irq_remapped(irq))
+                        io_apic_write(apic, 0x11 + pin*2, dest);
                 reg = io_apic_read(apic, 0x10 + pin*2);
                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
                 reg |= vector;
@@ -440,6 +450,69 @@ static void clear_IO_APIC (void)
                         clear_IO_APIC_pin(apic, pin);
 }
 
+/*
+ * Saves and masks all the unmasked IO-APIC RTE's
+ */
+int save_mask_IO_APIC_setup(void)
+{
+        union IO_APIC_reg_01 reg_01;
+        unsigned long flags;
+        int apic, pin;
+
+        /*
+         * The number of IO-APIC IRQ registers (== #pins):
+         */
+        for (apic = 0; apic < nr_ioapics; apic++) {
+                spin_lock_irqsave(&ioapic_lock, flags);
+                reg_01.raw = io_apic_read(apic, 1);
+                spin_unlock_irqrestore(&ioapic_lock, flags);
+                nr_ioapic_registers[apic] = reg_01.bits.entries+1;
+        }
+
+        for (apic = 0; apic < nr_ioapics; apic++) {
+                early_ioapic_entries[apic] =
+                        kzalloc(sizeof(struct IO_APIC_route_entry) *
+                                nr_ioapic_registers[apic], GFP_KERNEL);
+                if (!early_ioapic_entries[apic])
+                        return -ENOMEM;
+        }
+
+        for (apic = 0; apic < nr_ioapics; apic++)
+                for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
+                        struct IO_APIC_route_entry entry;
+
+                        entry = early_ioapic_entries[apic][pin] =
+                                ioapic_read_entry(apic, pin);
+                        if (!entry.mask) {
+                                entry.mask = 1;
+                                ioapic_write_entry(apic, pin, entry);
+                        }
+                }
+        return 0;
+}
+
+void restore_IO_APIC_setup(void)
+{
+        int apic, pin;
+
+        for (apic = 0; apic < nr_ioapics; apic++)
+                for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
+                        ioapic_write_entry(apic, pin,
+                                           early_ioapic_entries[apic][pin]);
+}
+
+void reinit_intr_remapped_IO_APIC(int intr_remapping)
+{
+        /*
+         * for now plain restore of previous settings.
+         * TBD: In the case of OS enabling interrupt-remapping,
+         * IO-APIC RTE's need to be setup to point to interrupt-remapping
+         * table entries. for now, do a plain restore, and wait for
+         * the setup_IO_APIC_irqs() to do proper initialization.
+         */
+        restore_IO_APIC_setup();
+}
+
 int skip_ioapic_setup;
 int ioapic_force;
 
@@ -839,18 +912,98 @@ void __setup_vector_irq(int cpu)
 }
 
 static struct irq_chip ioapic_chip;
+#ifdef CONFIG_INTR_REMAP
+static struct irq_chip ir_ioapic_chip;
+#endif
 
 static void ioapic_register_intr(int irq, unsigned long trigger)
 {
-        if (trigger) {
+        if (trigger)
                 irq_desc[irq].status |= IRQ_LEVEL;
-                set_irq_chip_and_handler_name(irq, &ioapic_chip,
-                                              handle_fasteoi_irq, "fasteoi");
-        } else {
+        else
                 irq_desc[irq].status &= ~IRQ_LEVEL;
+
+#ifdef CONFIG_INTR_REMAP
+        if (irq_remapped(irq)) {
+                irq_desc[irq].status |= IRQ_MOVE_PCNTXT;
+                if (trigger)
+                        set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
+                                                      handle_fasteoi_irq,
+                                                     "fasteoi");
+                else
+                        set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
+                                                      handle_edge_irq, "edge");
+                return;
+        }
+#endif
+        if (trigger)
+                set_irq_chip_and_handler_name(irq, &ioapic_chip,
+                                              handle_fasteoi_irq,
+                                              "fasteoi");
+        else
                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
                                               handle_edge_irq, "edge");
+}
+
+static int setup_ioapic_entry(int apic, int irq,
+                              struct IO_APIC_route_entry *entry,
+                              unsigned int destination, int trigger,
+                              int polarity, int vector)
+{
+        /*
+         * add it to the IO-APIC irq-routing table:
+         */
+        memset(entry,0,sizeof(*entry));
+
+#ifdef CONFIG_INTR_REMAP
+        if (intr_remapping_enabled) {
+                struct intel_iommu *iommu = map_ioapic_to_ir(apic);
+                struct irte irte;
+                struct IR_IO_APIC_route_entry *ir_entry =
+                        (struct IR_IO_APIC_route_entry *) entry;
+                int index;
+
+                if (!iommu)
+                        panic("No mapping iommu for ioapic %d\n", apic);
+
+                index = alloc_irte(iommu, irq, 1);
+                if (index < 0)
+                        panic("Failed to allocate IRTE for ioapic %d\n", apic);
+
+                memset(&irte, 0, sizeof(irte));
+
+                irte.present = 1;
+                irte.dst_mode = INT_DEST_MODE;
+                irte.trigger_mode = trigger;
+                irte.dlvry_mode = INT_DELIVERY_MODE;
+                irte.vector = vector;
+                irte.dest_id = IRTE_DEST(destination);
+
+                modify_irte(irq, &irte);
+
+                ir_entry->index2 = (index >> 15) & 0x1;
+                ir_entry->zero = 0;
+                ir_entry->format = 1;
+                ir_entry->index = (index & 0x7fff);
+        } else
+#endif
+        {
+                entry->delivery_mode = INT_DELIVERY_MODE;
+                entry->dest_mode = INT_DEST_MODE;
+                entry->dest = destination;
         }
+
+        entry->mask = 0;                                /* enable IRQ */
+        entry->trigger = trigger;
+        entry->polarity = polarity;
+        entry->vector = vector;
+
+        /* Mask level triggered irqs.
+         * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
+         */
+        if (trigger)
+                entry->mask = 1;
+        return 0;
 }
 
 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
@@ -875,24 +1028,15 @@ static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
                     apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
                     irq, trigger, polarity);
 
-        /*
-         * add it to the IO-APIC irq-routing table:
-         */
-        memset(&entry,0,sizeof(entry));
-
-        entry.delivery_mode = INT_DELIVERY_MODE;
-        entry.dest_mode = INT_DEST_MODE;
-        entry.dest = cpu_mask_to_apicid(mask);
-        entry.mask = 0;                         /* enable IRQ */
-        entry.trigger = trigger;
-        entry.polarity = polarity;
-        entry.vector = cfg->vector;
 
-        /* Mask level triggered irqs.
-         * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
-         */
-        if (trigger)
-                entry.mask = 1;
+        if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
+                               cpu_mask_to_apicid(mask), trigger, polarity,
+                               cfg->vector)) {
+                printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
+                       mp_ioapics[apic].mp_apicid, pin);
+                __clear_irq_vector(irq);
+                return;
+        }
 
         ioapic_register_intr(irq, trigger);
         if (irq < 16)
@@ -944,6 +1088,9 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
 {
         struct IO_APIC_route_entry entry;
 
+        if (intr_remapping_enabled)
+                return;
+
         memset(&entry, 0, sizeof(entry));
 
         /*
@@ -970,7 +1117,8 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
         ioapic_write_entry(apic, pin, entry);
 }
 
-void __apicdebuginit print_IO_APIC(void)
+
+__apicdebuginit(void) print_IO_APIC(void)
 {
         int apic, i;
         union IO_APIC_reg_00 reg_00;
@@ -1064,9 +1212,7 @@ void __apicdebuginit print_IO_APIC(void)
         return;
 }
 
-#if 0
-
-static __apicdebuginit void print_APIC_bitfield (int base)
+__apicdebuginit(void) print_APIC_bitfield(int base)
 {
         unsigned int v;
         int i, j;
@@ -1087,9 +1233,10 @@ static __apicdebuginit void print_APIC_bitfield (int base)
         }
 }
 
-void __apicdebuginit print_local_APIC(void * dummy)
+__apicdebuginit(void) print_local_APIC(void *dummy)
 {
         unsigned int v, ver, maxlvt;
+        unsigned long icr;
 
         if (apic_verbosity == APIC_QUIET)
                 return;
@@ -1097,7 +1244,7 @@ void __apicdebuginit print_local_APIC(void * dummy)
         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
                 smp_processor_id(), hard_smp_processor_id());
         v = apic_read(APIC_ID);
-        printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
+        printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
         v = apic_read(APIC_LVR);
         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
         ver = GET_APIC_VERSION(v);
@@ -1133,10 +1280,9 @@ void __apicdebuginit print_local_APIC(void * dummy)
         v = apic_read(APIC_ESR);
         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
 
-        v = apic_read(APIC_ICR);
-        printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
-        v = apic_read(APIC_ICR2);
-        printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
+        icr = apic_icr_read();
+        printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
+        printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
 
         v = apic_read(APIC_LVTT);
         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
@@ -1164,12 +1310,12 @@ void __apicdebuginit print_local_APIC(void * dummy)
         printk("\n");
 }
 
-void print_all_local_APICs (void)
+__apicdebuginit(void) print_all_local_APICs(void)
 {
         on_each_cpu(print_local_APIC, NULL, 1);
 }
 
-void __apicdebuginit print_PIC(void)
+__apicdebuginit(void) print_PIC(void)
 {
         unsigned int v;
         unsigned long flags;
@@ -1201,7 +1347,17 @@ void __apicdebuginit print_PIC(void)
         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
 }
 
-#endif  /*  0  */
+__apicdebuginit(int) print_all_ICs(void)
+{
+        print_PIC();
+        print_all_local_APICs();
+        print_IO_APIC();
+
+        return 0;
+}
+
+fs_initcall(print_all_ICs);
+
 
 void __init enable_IO_APIC(void)
 {
@@ -1291,7 +1447,7 @@ void disable_IO_APIC(void)
                 entry.dest_mode       = 0; /* Physical */
                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
                 entry.vector          = 0;
-                entry.dest          = GET_APIC_ID(read_apic_id());
+                entry.dest            = read_apic_id();
 
                 /*
                  * Add it to the IO-APIC irq-routing table:
@@ -1397,6 +1553,147 @@ static int ioapic_retrigger_irq(unsigned int irq)
  */
 
 #ifdef CONFIG_SMP
+
+#ifdef CONFIG_INTR_REMAP
+static void ir_irq_migration(struct work_struct *work);
+
+static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
+
+/*
+ * Migrate the IO-APIC irq in the presence of intr-remapping.
+ *
+ * For edge triggered, irq migration is a simple atomic update(of vector
+ * and cpu destination) of IRTE and flush the hardware cache.
+ *
+ * For level triggered, we need to modify the io-apic RTE aswell with the update
+ * vector information, along with modifying IRTE with vector and destination.
+ * So irq migration for level triggered is little  bit more complex compared to
+ * edge triggered migration. But the good news is, we use the same algorithm
+ * for level triggered migration as we have today, only difference being,
+ * we now initiate the irq migration from process context instead of the
+ * interrupt context.
+ *
+ * In future, when we do a directed EOI (combined with cpu EOI broadcast
+ * suppression) to the IO-APIC, level triggered irq migration will also be
+ * as simple as edge triggered migration and we can do the irq migration
+ * with a simple atomic update to IO-APIC RTE.
+ */
+static void migrate_ioapic_irq(int irq, cpumask_t mask)
+{
+        struct irq_cfg *cfg = irq_cfg + irq;
+        struct irq_desc *desc = irq_desc + irq;
+        cpumask_t tmp, cleanup_mask;
+        struct irte irte;
+        int modify_ioapic_rte = desc->status & IRQ_LEVEL;
+        unsigned int dest;
+        unsigned long flags;
+
+        cpus_and(tmp, mask, cpu_online_map);
+        if (cpus_empty(tmp))
+                return;
+
+        if (get_irte(irq, &irte))
+                return;
+
+        if (assign_irq_vector(irq, mask))
+                return;
+
+        cpus_and(tmp, cfg->domain, mask);
+        dest = cpu_mask_to_apicid(tmp);
+
+        if (modify_ioapic_rte) {
+                spin_lock_irqsave(&ioapic_lock, flags);
+                __target_IO_APIC_irq(irq, dest, cfg->vector);
+                spin_unlock_irqrestore(&ioapic_lock, flags);
+        }
+
+        irte.vector = cfg->vector;
+        irte.dest_id = IRTE_DEST(dest);
+
+        /*
+         * Modified the IRTE and flushes the Interrupt entry cache.
+         */
+        modify_irte(irq, &irte);
+
+        if (cfg->move_in_progress) {
+                cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
+                cfg->move_cleanup_count = cpus_weight(cleanup_mask);
+                send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
+                cfg->move_in_progress = 0;
+        }
+
+        irq_desc[irq].affinity = mask;
+}
+
+static int migrate_irq_remapped_level(int irq)
+{
+        int ret = -1;
+
+        mask_IO_APIC_irq(irq);
+
+        if (io_apic_level_ack_pending(irq)) {
+                /*
+                 * Interrupt in progress. Migrating irq now will change the
+                 * vector information in the IO-APIC RTE and that will confuse
+                 * the EOI broadcast performed by cpu.
+                 * So, delay the irq migration to the next instance.
+                 */
+                schedule_delayed_work(&ir_migration_work, 1);
+                goto unmask;
+        }
+
+        /* everthing is clear. we have right of way */
+        migrate_ioapic_irq(irq, irq_desc[irq].pending_mask);
+
+        ret = 0;
+        irq_desc[irq].status &= ~IRQ_MOVE_PENDING;
+        cpus_clear(irq_desc[irq].pending_mask);
+
+unmask:
+        unmask_IO_APIC_irq(irq);
+        return ret;
+}
+
+static void ir_irq_migration(struct work_struct *work)
+{
+        int irq;
+
+        for (irq = 0; irq < NR_IRQS; irq++) {
+                struct irq_desc *desc = irq_desc + irq;
+                if (desc->status & IRQ_MOVE_PENDING) {
+                        unsigned long flags;
+
+                        spin_lock_irqsave(&desc->lock, flags);
+                        if (!desc->chip->set_affinity ||
+                            !(desc->status & IRQ_MOVE_PENDING)) {
+                                desc->status &= ~IRQ_MOVE_PENDING;
+                                spin_unlock_irqrestore(&desc->lock, flags);
+                                continue;
+                        }
+
+                        desc->chip->set_affinity(irq,
+                                                 irq_desc[irq].pending_mask);
+                        spin_unlock_irqrestore(&desc->lock, flags);
+                }
+        }
+}
+
+/*
+ * Migrates the IRQ destination in the process context.
+ */
+static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
+{
+        if (irq_desc[irq].status & IRQ_LEVEL) {
+                irq_desc[irq].status |= IRQ_MOVE_PENDING;
+                irq_desc[irq].pending_mask = mask;
+                migrate_irq_remapped_level(irq);
+                return;
+        }
+
+        migrate_ioapic_irq(irq, mask);
+}
+#endif
+
 asmlinkage void smp_irq_move_cleanup_interrupt(void)
 {
         unsigned vector, me;
@@ -1453,6 +1750,17 @@ static void irq_complete_move(unsigned int irq)
 #else
 static inline void irq_complete_move(unsigned int irq) {}
 #endif
+#ifdef CONFIG_INTR_REMAP
+static void ack_x2apic_level(unsigned int irq)
+{
+        ack_x2APIC_irq();
+}
+
+static void ack_x2apic_edge(unsigned int irq)
+{
+        ack_x2APIC_irq();
+}
+#endif
 
 static void ack_apic_edge(unsigned int irq)
 {
@@ -1527,6 +1835,21 @@ static struct irq_chip ioapic_chip __read_mostly = {
         .retrigger      = ioapic_retrigger_irq,
 };
 
+#ifdef CONFIG_INTR_REMAP
+static struct irq_chip ir_ioapic_chip __read_mostly = {
+        .name           = "IR-IO-APIC",
+        .startup        = startup_ioapic_irq,
+        .mask           = mask_IO_APIC_irq,
+        .unmask         = unmask_IO_APIC_irq,
+        .ack            = ack_x2apic_edge,
+        .eoi            = ack_x2apic_level,
+#ifdef CONFIG_SMP
+        .set_affinity   = set_ir_ioapic_affinity_irq,
+#endif
+        .retrigger      = ioapic_retrigger_irq,
+};
+#endif
+
 static inline void init_IO_APIC_traps(void)
 {
         int irq;
@@ -1712,6 +2035,8 @@ static inline void __init check_timer(void)
          * 8259A.
          */
         if (pin1 == -1) {
+                if (intr_remapping_enabled)
+                        panic("BIOS bug: timer not connected to IO-APIC");
                 pin1 = pin2;
                 apic1 = apic2;
                 no_pin1 = 1;
@@ -1738,6 +2063,8 @@ static inline void __init check_timer(void)
                                 clear_IO_APIC_pin(0, pin1);
                         goto out;
                 }
+                if (intr_remapping_enabled)
+                        panic("timer doesn't work through Interrupt-remapped IO-APIC");
                 clear_IO_APIC_pin(apic1, pin1);
                 if (!no_pin1)
                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
@@ -1854,8 +2181,6 @@ void __init setup_IO_APIC(void)
         setup_IO_APIC_irqs();
         init_IO_APIC_traps();
         check_timer();
-        if (!acpi_ioapic)
-                print_IO_APIC();
 }
 
 struct sysfs_ioapic_data {
@@ -1977,6 +2302,9 @@ void destroy_irq(unsigned int irq)
 
         dynamic_irq_cleanup(irq);
 
+#ifdef CONFIG_INTR_REMAP
+        free_irte(irq);
+#endif
         spin_lock_irqsave(&vector_lock, flags);
         __clear_irq_vector(irq);
         spin_unlock_irqrestore(&vector_lock, flags);
@@ -1995,11 +2323,42 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
 
         tmp = TARGET_CPUS;
         err = assign_irq_vector(irq, tmp);
-        if (!err) {
-                cpus_and(tmp, cfg->domain, tmp);
-                dest = cpu_mask_to_apicid(tmp);
+        if (err)
+                return err;
+
+        cpus_and(tmp, cfg->domain, tmp);
+        dest = cpu_mask_to_apicid(tmp);
+
+#ifdef CONFIG_INTR_REMAP
+        if (irq_remapped(irq)) {
+                struct irte irte;
+                int ir_index;
+                u16 sub_handle;
+
+                ir_index = map_irq_to_irte_handle(irq, &sub_handle);
+                BUG_ON(ir_index == -1);
+
+                memset (&irte, 0, sizeof(irte));
+
+                irte.present = 1;
+                irte.dst_mode = INT_DEST_MODE;
+                irte.trigger_mode = 0; /* edge */
+                irte.dlvry_mode = INT_DELIVERY_MODE;
+                irte.vector = cfg->vector;
+                irte.dest_id = IRTE_DEST(dest);
+
+                modify_irte(irq, &irte);
 
                 msg->address_hi = MSI_ADDR_BASE_HI;
+                msg->data = sub_handle;
+                msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
+                                  MSI_ADDR_IR_SHV |
+                                  MSI_ADDR_IR_INDEX1(ir_index) |
+                                  MSI_ADDR_IR_INDEX2(ir_index);
+        } else
+#endif
+        {
+                msg->address_hi = MSI_ADDR_BASE_HI;
                 msg->address_lo =
                         MSI_ADDR_BASE_LO |
                         ((INT_DEST_MODE == 0) ?
@@ -2049,6 +2408,55 @@ static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
         write_msi_msg(irq, &msg);
         irq_desc[irq].affinity = mask;
 }
+
+#ifdef CONFIG_INTR_REMAP
+/*
+ * Migrate the MSI irq to another cpumask. This migration is
+ * done in the process context using interrupt-remapping hardware.
+ */
+static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
+{
+        struct irq_cfg *cfg = irq_cfg + irq;
+        unsigned int dest;
+        cpumask_t tmp, cleanup_mask;
+        struct irte irte;
+
+        cpus_and(tmp, mask, cpu_online_map);
+        if (cpus_empty(tmp))
+                return;
+
+        if (get_irte(irq, &irte))
+                return;
+
+        if (assign_irq_vector(irq, mask))
+                return;
+
+        cpus_and(tmp, cfg->domain, mask);
+        dest = cpu_mask_to_apicid(tmp);
+
+        irte.vector = cfg->vector;
+        irte.dest_id = IRTE_DEST(dest);
+
+        /*
+         * atomically update the IRTE with the new destination and vector.
+         */
+        modify_irte(irq, &irte);
+
+        /*
+         * After this point, all the interrupts will start arriving
+         * at the new destination. So, time to cleanup the previous
+         * vector allocation.
+         */
+        if (cfg->move_in_progress) {
+                cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
+                cfg->move_cleanup_count = cpus_weight(cleanup_mask);
+                send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
+                cfg->move_in_progress = 0;
+        }
+
+        irq_desc[irq].affinity = mask;
+}
+#endif
 #endif /* CONFIG_SMP */
 
 /*
@@ -2066,26 +2474,157 @@ static struct irq_chip msi_chip = {
         .retrigger      = ioapic_retrigger_irq,
 };
 
-int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
+#ifdef CONFIG_INTR_REMAP
+static struct irq_chip msi_ir_chip = {
+        .name           = "IR-PCI-MSI",
+        .unmask         = unmask_msi_irq,
+        .mask           = mask_msi_irq,
+        .ack            = ack_x2apic_edge,
+#ifdef CONFIG_SMP
+        .set_affinity   = ir_set_msi_irq_affinity,
+#endif
+        .retrigger      = ioapic_retrigger_irq,
+};
+
+/*
+ * Map the PCI dev to the corresponding remapping hardware unit
+ * and allocate 'nvec' consecutive interrupt-remapping table entries
+ * in it.
+ */
+static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
 {
+        struct intel_iommu *iommu;
+        int index;
+
+        iommu = map_dev_to_ir(dev);
+        if (!iommu) {
+                printk(KERN_ERR
+                       "Unable to map PCI %s to iommu\n", pci_name(dev));
+                return -ENOENT;
+        }
+
+        index = alloc_irte(iommu, irq, nvec);
+        if (index < 0) {
+                printk(KERN_ERR
+                       "Unable to allocate %d IRTE for PCI %s\n", nvec,
+                        pci_name(dev));
+                return -ENOSPC;
+        }
+        return index;
+}
+#endif
+
+static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
+{
+        int ret;
         struct msi_msg msg;
+
+        ret = msi_compose_msg(dev, irq, &msg);
+        if (ret < 0)
+                return ret;
+
+        set_irq_msi(irq, desc);
+        write_msi_msg(irq, &msg);
+
+#ifdef CONFIG_INTR_REMAP
+        if (irq_remapped(irq)) {
+                struct irq_desc *desc = irq_desc + irq;
+                /*
+                 * irq migration in process context
+                 */
+                desc->status |= IRQ_MOVE_PCNTXT;
+                set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
+        } else
+#endif
+                set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
+
+        return 0;
+}
+
+int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
+{
         int irq, ret;
+
         irq = create_irq();
         if (irq < 0)
                 return irq;
 
-        ret = msi_compose_msg(dev, irq, &msg);
+#ifdef CONFIG_INTR_REMAP
+        if (!intr_remapping_enabled)
+                goto no_ir;
+
+        ret = msi_alloc_irte(dev, irq, 1);
+        if (ret < 0)
+                goto error;
+no_ir:
+#endif
+        ret = setup_msi_irq(dev, desc, irq);
         if (ret < 0) {
                 destroy_irq(irq);
                 return ret;
         }
+        return 0;
 
-        set_irq_msi(irq, desc);
-        write_msi_msg(irq, &msg);
+#ifdef CONFIG_INTR_REMAP
+error:
+        destroy_irq(irq);
+        return ret;
+#endif
+}
 
-        set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
+int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        int irq, ret, sub_handle;
+        struct msi_desc *desc;
+#ifdef CONFIG_INTR_REMAP
+        struct intel_iommu *iommu = 0;
+        int index = 0;
+#endif
+
+        sub_handle = 0;
+        list_for_each_entry(desc, &dev->msi_list, list) {
+                irq = create_irq();
+                if (irq < 0)
+                        return irq;
+#ifdef CONFIG_INTR_REMAP
+                if (!intr_remapping_enabled)
+                        goto no_ir;
 
+                if (!sub_handle) {
+                        /*
+                         * allocate the consecutive block of IRTE's
+                         * for 'nvec'
+                         */
+                        index = msi_alloc_irte(dev, irq, nvec);
+                        if (index < 0) {
+                                ret = index;
+                                goto error;
+                        }
+                } else {
+                        iommu = map_dev_to_ir(dev);
+                        if (!iommu) {
+                                ret = -ENOENT;
+                                goto error;
+                        }
+                        /*
+                         * setup the mapping between the irq and the IRTE
+                         * base index, the sub_handle pointing to the
+                         * appropriate interrupt remap table entry.
+                         */
+                        set_irte_irq(irq, iommu, index, sub_handle);
+                }
+no_ir:
+#endif
+                ret = setup_msi_irq(dev, desc, irq);
+                if (ret < 0)
+                        goto error;
+                sub_handle++;
+        }
         return 0;
+
+error:
+        destroy_irq(irq);
+        return ret;
 }
 
 void arch_teardown_msi_irq(unsigned int irq)
@@ -2333,6 +2872,10 @@ void __init setup_ioapic_dest(void)
                                 setup_IO_APIC_irq(ioapic, pin, irq,
                                                   irq_trigger(irq_entry),
                                                   irq_polarity(irq_entry));
+#ifdef CONFIG_INTR_REMAP
+                        else if (intr_remapping_enabled)
+                                set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
+#endif
                         else
                                 set_ioapic_affinity_irq(irq, TARGET_CPUS);
                 }
diff --git a/arch/x86/kernel/ioport.c b/arch/x86/kernel/ioport.c
index 50e5e4a31c85..191914302744 100644
--- a/arch/x86/kernel/ioport.c
+++ b/arch/x86/kernel/ioport.c
@@ -14,6 +14,7 @@
 #include <linux/slab.h>
 #include <linux/thread_info.h>
 #include <linux/syscalls.h>
+#include <asm/syscalls.h>
 
 /* Set EXTENT bits starting at BASE in BITMAP to value TURN_ON. */
 static void set_bitmap(unsigned long *bitmap, unsigned int base,
diff --git a/arch/x86/kernel/ipi.c b/arch/x86/kernel/ipi.c
index 3f7537b669d3..f1c688e46f35 100644
--- a/arch/x86/kernel/ipi.c
+++ b/arch/x86/kernel/ipi.c
@@ -20,6 +20,8 @@
 
 #ifdef CONFIG_X86_32
 #include <mach_apic.h>
+#include <mach_ipi.h>
+
 /*
  * the following functions deal with sending IPIs between CPUs.
  *
@@ -147,7 +149,6 @@ void send_IPI_mask_sequence(cpumask_t mask, int vector)
 }
 
 /* must come after the send_IPI functions above for inlining */
-#include <mach_ipi.h>
 static int convert_apicid_to_cpu(int apic_id)
 {
         int i;
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 1cf8c1fcc088..b71e02d42f4f 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -325,7 +325,7 @@ skip:
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ",
                                 per_cpu(irq_stat,j).irq_call_count);
-                seq_printf(p, "  function call interrupts\n");
+                seq_printf(p, "  Function call interrupts\n");
                 seq_printf(p, "TLB: ");
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ",
diff --git a/arch/x86/kernel/irq_64.c b/arch/x86/kernel/irq_64.c
index 1f78b238d8d2..f065fe9071b9 100644
--- a/arch/x86/kernel/irq_64.c
+++ b/arch/x86/kernel/irq_64.c
@@ -129,7 +129,7 @@ skip:
                 seq_printf(p, "CAL: ");
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_call_count);
-                seq_printf(p, "  function call interrupts\n");
+                seq_printf(p, "  Function call interrupts\n");
                 seq_printf(p, "TLB: ");
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_tlb_count);
diff --git a/arch/x86/kernel/irqinit_32.c b/arch/x86/kernel/irqinit_32.c
index d66914287ee1..9200a1e2752d 100644
--- a/arch/x86/kernel/irqinit_32.c
+++ b/arch/x86/kernel/irqinit_32.c
@@ -74,6 +74,15 @@ void __init init_ISA_irqs (void)
         }
 }
 
+/*
+ * IRQ2 is cascade interrupt to second interrupt controller
+ */
+static struct irqaction irq2 = {
+        .handler = no_action,
+        .mask = CPU_MASK_NONE,
+        .name = "cascade",
+};
+
 /* Overridden in paravirt.c */
 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 
@@ -98,6 +107,46 @@ void __init native_init_IRQ(void)
                         set_intr_gate(vector, interrupt[i]);
         }
 
+#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_SMP)
+        /*
+         * IRQ0 must be given a fixed assignment and initialized,
+         * because it's used before the IO-APIC is set up.
+         */
+        set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
+
+        /*
+         * The reschedule interrupt is a CPU-to-CPU reschedule-helper
+         * IPI, driven by wakeup.
+         */
+        alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
+
+        /* IPI for invalidation */
+        alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
+
+        /* IPI for generic function call */
+        alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
+
+        /* IPI for single call function */
+        set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR, call_function_single_interrupt);
+#endif
+
+#ifdef CONFIG_X86_LOCAL_APIC
+        /* self generated IPI for local APIC timer */
+        alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
+
+        /* IPI vectors for APIC spurious and error interrupts */
+        alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
+        alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
+#endif
+
+#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_MCE_P4THERMAL)
+        /* thermal monitor LVT interrupt */
+        alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
+#endif
+
+        if (!acpi_ioapic)
+                setup_irq(2, &irq2);
+
         /* setup after call gates are initialised (usually add in
          * the architecture specific gates)
          */
diff --git a/arch/x86/kernel/k8.c b/arch/x86/kernel/k8.c
index 7377ccb21335..304d8bad6559 100644
--- a/arch/x86/kernel/k8.c
+++ b/arch/x86/kernel/k8.c
@@ -16,8 +16,9 @@ EXPORT_SYMBOL(num_k8_northbridges);
 static u32 *flush_words;
 
 struct pci_device_id k8_nb_ids[] = {
-        { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
-        { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
         {}
 };
 EXPORT_SYMBOL(k8_nb_ids);
diff --git a/arch/x86/kernel/kdebugfs.c b/arch/x86/kernel/kdebugfs.c
index f2d43bc75514..ff7d3b0124f1 100644
--- a/arch/x86/kernel/kdebugfs.c
+++ b/arch/x86/kernel/kdebugfs.c
@@ -139,6 +139,7 @@ static int __init create_setup_data_nodes(struct dentry *parent)
                 if (PageHighMem(pg)) {
                         data = ioremap_cache(pa_data, sizeof(*data));
                         if (!data) {
+                                kfree(node);
                                 error = -ENXIO;
                                 goto err_dir;
                         }
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index f47f0eb886b8..10435a120d22 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -69,6 +69,9 @@ static int gdb_x86vector = -1;
  */
 void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
 {
+#ifndef CONFIG_X86_32
+        u32 *gdb_regs32 = (u32 *)gdb_regs;
+#endif
         gdb_regs[GDB_AX]        = regs->ax;
         gdb_regs[GDB_BX]        = regs->bx;
         gdb_regs[GDB_CX]        = regs->cx;
@@ -76,9 +79,9 @@ void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
         gdb_regs[GDB_SI]        = regs->si;
         gdb_regs[GDB_DI]        = regs->di;
         gdb_regs[GDB_BP]        = regs->bp;
-        gdb_regs[GDB_PS]        = regs->flags;
         gdb_regs[GDB_PC]        = regs->ip;
 #ifdef CONFIG_X86_32
+        gdb_regs[GDB_PS]        = regs->flags;
         gdb_regs[GDB_DS]        = regs->ds;
         gdb_regs[GDB_ES]        = regs->es;
         gdb_regs[GDB_CS]        = regs->cs;
@@ -94,6 +97,9 @@ void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
         gdb_regs[GDB_R13]       = regs->r13;
         gdb_regs[GDB_R14]       = regs->r14;
         gdb_regs[GDB_R15]       = regs->r15;
+        gdb_regs32[GDB_PS]      = regs->flags;
+        gdb_regs32[GDB_CS]      = regs->cs;
+        gdb_regs32[GDB_SS]      = regs->ss;
 #endif
         gdb_regs[GDB_SP]        = regs->sp;
 }
@@ -112,6 +118,9 @@ void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
  */
 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
 {
+#ifndef CONFIG_X86_32
+        u32 *gdb_regs32 = (u32 *)gdb_regs;
+#endif
         gdb_regs[GDB_AX]        = 0;
         gdb_regs[GDB_BX]        = 0;
         gdb_regs[GDB_CX]        = 0;
@@ -129,8 +138,10 @@ void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
         gdb_regs[GDB_FS]        = 0xFFFF;
         gdb_regs[GDB_GS]        = 0xFFFF;
 #else
-        gdb_regs[GDB_PS]        = *(unsigned long *)(p->thread.sp + 8);
-        gdb_regs[GDB_PC]        = 0;
+        gdb_regs32[GDB_PS]      = *(unsigned long *)(p->thread.sp + 8);
+        gdb_regs32[GDB_CS]      = __KERNEL_CS;
+        gdb_regs32[GDB_SS]      = __KERNEL_DS;
+        gdb_regs[GDB_PC]        = p->thread.ip;
         gdb_regs[GDB_R8]        = 0;
         gdb_regs[GDB_R9]        = 0;
         gdb_regs[GDB_R10]       = 0;
@@ -153,6 +164,9 @@ void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
  */
 void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
 {
+#ifndef CONFIG_X86_32
+        u32 *gdb_regs32 = (u32 *)gdb_regs;
+#endif
         regs->ax                = gdb_regs[GDB_AX];
         regs->bx                = gdb_regs[GDB_BX];
         regs->cx                = gdb_regs[GDB_CX];
@@ -160,9 +174,9 @@ void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
         regs->si                = gdb_regs[GDB_SI];
         regs->di                = gdb_regs[GDB_DI];
         regs->bp                = gdb_regs[GDB_BP];
-        regs->flags             = gdb_regs[GDB_PS];
         regs->ip                = gdb_regs[GDB_PC];
 #ifdef CONFIG_X86_32
+        regs->flags             = gdb_regs[GDB_PS];
         regs->ds                = gdb_regs[GDB_DS];
         regs->es                = gdb_regs[GDB_ES];
         regs->cs                = gdb_regs[GDB_CS];
@@ -175,6 +189,9 @@ void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
         regs->r13               = gdb_regs[GDB_R13];
         regs->r14               = gdb_regs[GDB_R14];
         regs->r15               = gdb_regs[GDB_R15];
+        regs->flags             = gdb_regs32[GDB_PS];
+        regs->cs                = gdb_regs32[GDB_CS];
+        regs->ss                = gdb_regs32[GDB_SS];
 #endif
 }
 
@@ -378,10 +395,8 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
                 if (remcomInBuffer[0] == 's') {
                         linux_regs->flags |= X86_EFLAGS_TF;
                         kgdb_single_step = 1;
-                        if (kgdb_contthread) {
-                                atomic_set(&kgdb_cpu_doing_single_step,
-                                           raw_smp_processor_id());
-                        }
+                        atomic_set(&kgdb_cpu_doing_single_step,
+                                   raw_smp_processor_id());
                 }
 
                 get_debugreg(dr6, 6);
@@ -440,12 +455,7 @@ static int __kgdb_notify(struct die_args *args, unsigned long cmd)
                 return NOTIFY_DONE;
 
         case DIE_NMI_IPI:
-                if (atomic_read(&kgdb_active) != -1) {
-                        /* KGDB CPU roundup */
-                        kgdb_nmicallback(raw_smp_processor_id(), regs);
-                        was_in_debug_nmi[raw_smp_processor_id()] = 1;
-                        touch_nmi_watchdog();
-                }
+                /* Just ignore, we will handle the roundup on DIE_NMI. */
                 return NOTIFY_DONE;
 
         case DIE_NMIUNKNOWN:
@@ -466,9 +476,15 @@ static int __kgdb_notify(struct die_args *args, unsigned long cmd)
 
         case DIE_DEBUG:
                 if (atomic_read(&kgdb_cpu_doing_single_step) ==
-                        raw_smp_processor_id() &&
-                        user_mode(regs))
-                        return single_step_cont(regs, args);
+                    raw_smp_processor_id()) {
+                        if (user_mode(regs))
+                                return single_step_cont(regs, args);
+                        break;
+                } else if (test_thread_flag(TIF_SINGLESTEP))
+                        /* This means a user thread is single stepping
+                         * a system call which should be ignored
+                         */
+                        return NOTIFY_DONE;
                 /* fall through */
         default:
                 if (user_mode(regs))
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index 8b7a3cf37d2b..478bca986eca 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -178,7 +178,7 @@ static void kvm_flush_tlb(void)
         kvm_deferred_mmu_op(&ftlb, sizeof ftlb);
 }
 
-static void kvm_release_pt(u32 pfn)
+static void kvm_release_pt(unsigned long pfn)
 {
         struct kvm_mmu_op_release_pt rpt = {
                 .header.op = KVM_MMU_OP_RELEASE_PT,
diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c
index b68e21f06f4f..0ed5f939b905 100644
--- a/arch/x86/kernel/ldt.c
+++ b/arch/x86/kernel/ldt.c
@@ -18,6 +18,7 @@
 #include <asm/ldt.h>
 #include <asm/desc.h>
 #include <asm/mmu_context.h>
+#include <asm/syscalls.h>
 
 #ifdef CONFIG_SMP
 static void flush_ldt(void *current_mm)
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index b3fb430725cb..f98f4e1dba09 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -397,7 +397,9 @@ static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
        generic_bigsmp_probe();
 #endif
 
+#ifdef CONFIG_X86_32
         setup_apic_routing();
+#endif
         if (!num_processors)
                 printk(KERN_ERR "MPTABLE: no processors registered!\n");
         return num_processors;
diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c
index abb78a2cc4ad..2c97f07f1c2c 100644
--- a/arch/x86/kernel/nmi.c
+++ b/arch/x86/kernel/nmi.c
@@ -299,6 +299,15 @@ void acpi_nmi_disable(void)
                 on_each_cpu(__acpi_nmi_disable, NULL, 1);
 }
 
+/*
+ * This function is called as soon the LAPIC NMI watchdog driver has everything
+ * in place and it's ready to check if the NMIs belong to the NMI watchdog
+ */
+void cpu_nmi_set_wd_enabled(void)
+{
+        __get_cpu_var(wd_enabled) = 1;
+}
+
 void setup_apic_nmi_watchdog(void *unused)
 {
         if (__get_cpu_var(wd_enabled))
@@ -311,8 +320,6 @@ void setup_apic_nmi_watchdog(void *unused)
 
         switch (nmi_watchdog) {
         case NMI_LOCAL_APIC:
-                 /* enable it before to avoid race with handler */
-                __get_cpu_var(wd_enabled) = 1;
                 if (lapic_watchdog_init(nmi_hz) < 0) {
                         __get_cpu_var(wd_enabled) = 0;
                         return;
diff --git a/arch/x86/kernel/numaq_32.c b/arch/x86/kernel/numaq_32.c
index eecc8c18f010..4caff39078e0 100644
--- a/arch/x86/kernel/numaq_32.c
+++ b/arch/x86/kernel/numaq_32.c
@@ -229,6 +229,12 @@ static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable,
         }
 }
 
+static int __init numaq_setup_ioapic_ids(void)
+{
+        /* so can skip it */
+        return 1;
+}
+
 static struct x86_quirks numaq_x86_quirks __initdata = {
         .arch_pre_time_init     = numaq_pre_time_init,
         .arch_time_init         = NULL,
@@ -243,6 +249,7 @@ static struct x86_quirks numaq_x86_quirks __initdata = {
         .mpc_oem_bus_info       = mpc_oem_bus_info,
         .mpc_oem_pci_bus        = mpc_oem_pci_bus,
         .smp_read_mpc_oem       = smp_read_mpc_oem,
+        .setup_ioapic_ids       = numaq_setup_ioapic_ids,
 };
 
 void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem,
diff --git a/arch/x86/kernel/olpc.c b/arch/x86/kernel/olpc.c
index 3e6672274807..7a13fac63a1f 100644
--- a/arch/x86/kernel/olpc.c
+++ b/arch/x86/kernel/olpc.c
@@ -190,12 +190,12 @@ EXPORT_SYMBOL_GPL(olpc_ec_cmd);
 static void __init platform_detect(void)
 {
         size_t propsize;
-        u32 rev;
+        __be32 rev;
 
         if (ofw("getprop", 4, 1, NULL, "board-revision-int", &rev, 4,
                         &propsize) || propsize != 4) {
                 printk(KERN_ERR "ofw: getprop call failed!\n");
-                rev = 0;
+                rev = cpu_to_be32(0);
         }
         olpc_platform_info.boardrev = be32_to_cpu(rev);
 }
@@ -203,7 +203,7 @@ static void __init platform_detect(void)
 static void __init platform_detect(void)
 {
         /* stopgap until OFW support is added to the kernel */
-        olpc_platform_info.boardrev = be32_to_cpu(0xc2);
+        olpc_platform_info.boardrev = 0xc2;
 }
 #endif
 
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 300da17e61cb..6b0bb73998dd 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -330,6 +330,7 @@ struct pv_cpu_ops pv_cpu_ops = {
 #endif
         .wbinvd = native_wbinvd,
         .read_msr = native_read_msr_safe,
+        .read_msr_amd = native_read_msr_amd_safe,
         .write_msr = native_write_msr_safe,
         .read_tsc = native_read_tsc,
         .read_pmc = native_read_pmc,
@@ -373,8 +374,6 @@ struct pv_cpu_ops pv_cpu_ops = {
 
 struct pv_apic_ops pv_apic_ops = {
 #ifdef CONFIG_X86_LOCAL_APIC
-        .apic_write = native_apic_write,
-        .apic_read = native_apic_read,
         .setup_boot_clock = setup_boot_APIC_clock,
         .setup_secondary_clock = setup_secondary_APIC_clock,
         .startup_ipi_hook = paravirt_nop,
diff --git a/arch/x86/kernel/paravirt_patch_32.c b/arch/x86/kernel/paravirt_patch_32.c
index 58262218781b..9fe644f4861d 100644
--- a/arch/x86/kernel/paravirt_patch_32.c
+++ b/arch/x86/kernel/paravirt_patch_32.c
@@ -23,7 +23,7 @@ unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
                         start = start_##ops##_##x;              \
                         end = end_##ops##_##x;                  \
                         goto patch_site
-        switch(type) {
+        switch (type) {
                 PATCH_SITE(pv_irq_ops, irq_disable);
                 PATCH_SITE(pv_irq_ops, irq_enable);
                 PATCH_SITE(pv_irq_ops, restore_fl);
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index dcdac6c826e9..080d1d27f37a 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -261,7 +261,7 @@ static void iommu_range_reserve(struct iommu_table *tbl,
                                badbit, tbl, start_addr, npages);
         }
 
-        set_bit_string(tbl->it_map, index, npages);
+        iommu_area_reserve(tbl->it_map, index, npages);
 
         spin_unlock_irqrestore(&tbl->it_lock, flags);
 }
@@ -491,6 +491,8 @@ static void* calgary_alloc_coherent(struct device *dev, size_t size,
         npages = size >> PAGE_SHIFT;
         order = get_order(size);
 
+        flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
+
         /* alloc enough pages (and possibly more) */
         ret = (void *)__get_free_pages(flag, order);
         if (!ret)
@@ -510,8 +512,22 @@ error:
         return ret;
 }
 
+static void calgary_free_coherent(struct device *dev, size_t size,
+                                  void *vaddr, dma_addr_t dma_handle)
+{
+        unsigned int npages;
+        struct iommu_table *tbl = find_iommu_table(dev);
+
+        size = PAGE_ALIGN(size);
+        npages = size >> PAGE_SHIFT;
+
+        iommu_free(tbl, dma_handle, npages);
+        free_pages((unsigned long)vaddr, get_order(size));
+}
+
 static struct dma_mapping_ops calgary_dma_ops = {
         .alloc_coherent = calgary_alloc_coherent,
+        .free_coherent = calgary_free_coherent,
         .map_single = calgary_map_single,
         .unmap_single = calgary_unmap_single,
         .map_sg = calgary_map_sg,
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 87d4d6964ec2..0a3824e837b4 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -41,11 +41,12 @@ EXPORT_SYMBOL(bad_dma_address);
 /* Dummy device used for NULL arguments (normally ISA). Better would
    be probably a smaller DMA mask, but this is bug-to-bug compatible
    to older i386. */
-struct device fallback_dev = {
+struct device x86_dma_fallback_dev = {
         .bus_id = "fallback device",
         .coherent_dma_mask = DMA_32BIT_MASK,
-        .dma_mask = &fallback_dev.coherent_dma_mask,
+        .dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
 };
+EXPORT_SYMBOL(x86_dma_fallback_dev);
 
 int dma_set_mask(struct device *dev, u64 mask)
 {
@@ -82,7 +83,7 @@ void __init dma32_reserve_bootmem(void)
          * using 512M as goal
          */
         align = 64ULL<<20;
-        size = round_up(dma32_bootmem_size, align);
+        size = roundup(dma32_bootmem_size, align);
         dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
                                  512ULL<<20);
         if (dma32_bootmem_ptr)
@@ -133,6 +134,37 @@ unsigned long iommu_num_pages(unsigned long addr, unsigned long len)
 EXPORT_SYMBOL(iommu_num_pages);
 #endif
 
+void *dma_generic_alloc_coherent(struct device *dev, size_t size,
+                                 dma_addr_t *dma_addr, gfp_t flag)
+{
+        unsigned long dma_mask;
+        struct page *page;
+        dma_addr_t addr;
+
+        dma_mask = dma_alloc_coherent_mask(dev, flag);
+
+        flag |= __GFP_ZERO;
+again:
+        page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
+        if (!page)
+                return NULL;
+
+        addr = page_to_phys(page);
+        if (!is_buffer_dma_capable(dma_mask, addr, size)) {
+                __free_pages(page, get_order(size));
+
+                if (dma_mask < DMA_32BIT_MASK && !(flag & GFP_DMA)) {
+                        flag = (flag & ~GFP_DMA32) | GFP_DMA;
+                        goto again;
+                }
+
+                return NULL;
+        }
+
+        *dma_addr = addr;
+        return page_address(page);
+}
+
 /*
  * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
  * documentation.
@@ -241,147 +273,6 @@ int dma_supported(struct device *dev, u64 mask)
 }
 EXPORT_SYMBOL(dma_supported);
 
-/* Allocate DMA memory on node near device */
-static noinline struct page *
-dma_alloc_pages(struct device *dev, gfp_t gfp, unsigned order)
-{
-        int node;
-
-        node = dev_to_node(dev);
-
-        return alloc_pages_node(node, gfp, order);
-}
-
-/*
- * Allocate memory for a coherent mapping.
- */
-void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-                   gfp_t gfp)
-{
-        struct dma_mapping_ops *ops = get_dma_ops(dev);
-        void *memory = NULL;
-        struct page *page;
-        unsigned long dma_mask = 0;
-        dma_addr_t bus;
-        int noretry = 0;
-
-        /* ignore region specifiers */
-        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
-
-        if (dma_alloc_from_coherent(dev, size, dma_handle, &memory))
-                return memory;
-
-        if (!dev) {
-                dev = &fallback_dev;
-                gfp |= GFP_DMA;
-        }
-        dma_mask = dev->coherent_dma_mask;
-        if (dma_mask == 0)
-                dma_mask = (gfp & GFP_DMA) ? DMA_24BIT_MASK : DMA_32BIT_MASK;
-
-        /* Device not DMA able */
-        if (dev->dma_mask == NULL)
-                return NULL;
-
-        /* Don't invoke OOM killer or retry in lower 16MB DMA zone */
-        if (gfp & __GFP_DMA)
-                noretry = 1;
-
-#ifdef CONFIG_X86_64
-        /* Why <=? Even when the mask is smaller than 4GB it is often
-           larger than 16MB and in this case we have a chance of
-           finding fitting memory in the next higher zone first. If
-           not retry with true GFP_DMA. -AK */
-        if (dma_mask <= DMA_32BIT_MASK && !(gfp & GFP_DMA)) {
-                gfp |= GFP_DMA32;
-                if (dma_mask < DMA_32BIT_MASK)
-                        noretry = 1;
-        }
-#endif
-
- again:
-        page = dma_alloc_pages(dev,
-                noretry ? gfp | __GFP_NORETRY : gfp, get_order(size));
-        if (page == NULL)
-                return NULL;
-
-        {
-                int high, mmu;
-                bus = page_to_phys(page);
-                memory = page_address(page);
-                high = (bus + size) >= dma_mask;
-                mmu = high;
-                if (force_iommu && !(gfp & GFP_DMA))
-                        mmu = 1;
-                else if (high) {
-                        free_pages((unsigned long)memory,
-                                   get_order(size));
-
-                        /* Don't use the 16MB ZONE_DMA unless absolutely
-                           needed. It's better to use remapping first. */
-                        if (dma_mask < DMA_32BIT_MASK && !(gfp & GFP_DMA)) {
-                                gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
-                                goto again;
-                        }
-
-                        /* Let low level make its own zone decisions */
-                        gfp &= ~(GFP_DMA32|GFP_DMA);
-
-                        if (ops->alloc_coherent)
-                                return ops->alloc_coherent(dev, size,
-                                                           dma_handle, gfp);
-                        return NULL;
-                }
-
-                memset(memory, 0, size);
-                if (!mmu) {
-                        *dma_handle = bus;
-                        return memory;
-                }
-        }
-
-        if (ops->alloc_coherent) {
-                free_pages((unsigned long)memory, get_order(size));
-                gfp &= ~(GFP_DMA|GFP_DMA32);
-                return ops->alloc_coherent(dev, size, dma_handle, gfp);
-        }
-
-        if (ops->map_simple) {
-                *dma_handle = ops->map_simple(dev, virt_to_phys(memory),
-                                              size,
-                                              PCI_DMA_BIDIRECTIONAL);
-                if (*dma_handle != bad_dma_address)
-                        return memory;
-        }
-
-        if (panic_on_overflow)
-                panic("dma_alloc_coherent: IOMMU overflow by %lu bytes\n",
-                      (unsigned long)size);
-        free_pages((unsigned long)memory, get_order(size));
-        return NULL;
-}
-EXPORT_SYMBOL(dma_alloc_coherent);
-
-/*
- * Unmap coherent memory.
- * The caller must ensure that the device has finished accessing the mapping.
- */
-void dma_free_coherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t bus)
-{
-        struct dma_mapping_ops *ops = get_dma_ops(dev);
-
-        int order = get_order(size);
-        WARN_ON(irqs_disabled());       /* for portability */
-        if (dma_release_from_coherent(dev, order, vaddr))
-                return;
-        if (ops->unmap_single)
-                ops->unmap_single(dev, bus, size, 0);
-        free_pages((unsigned long)vaddr, order);
-}
-EXPORT_SYMBOL(dma_free_coherent);
-
 static int __init pci_iommu_init(void)
 {
         calgary_iommu_init();
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index 49285f8fd4d5..145f1c83369f 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -27,8 +27,8 @@
 #include <linux/scatterlist.h>
 #include <linux/iommu-helper.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 #include <asm/atomic.h>
-#include <asm/io.h>
 #include <asm/mtrr.h>
 #include <asm/pgtable.h>
 #include <asm/proto.h>
@@ -80,9 +80,10 @@ AGPEXTERN int agp_memory_reserved;
 AGPEXTERN __u32 *agp_gatt_table;
 
 static unsigned long next_bit;  /* protected by iommu_bitmap_lock */
-static int need_flush;          /* global flush state. set for each gart wrap */
+static bool need_flush;         /* global flush state. set for each gart wrap */
 
-static unsigned long alloc_iommu(struct device *dev, int size)
+static unsigned long alloc_iommu(struct device *dev, int size,
+                                 unsigned long align_mask)
 {
         unsigned long offset, flags;
         unsigned long boundary_size;
@@ -90,26 +91,27 @@ static unsigned long alloc_iommu(struct device *dev, int size)
 
         base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
                            PAGE_SIZE) >> PAGE_SHIFT;
-        boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
+        boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
                               PAGE_SIZE) >> PAGE_SHIFT;
 
         spin_lock_irqsave(&iommu_bitmap_lock, flags);
         offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
-                                  size, base_index, boundary_size, 0);
+                                  size, base_index, boundary_size, align_mask);
         if (offset == -1) {
-                need_flush = 1;
+                need_flush = true;
                 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
-                                          size, base_index, boundary_size, 0);
+                                          size, base_index, boundary_size,
+                                          align_mask);
         }
         if (offset != -1) {
                 next_bit = offset+size;
                 if (next_bit >= iommu_pages) {
                         next_bit = 0;
-                        need_flush = 1;
+                        need_flush = true;
                 }
         }
         if (iommu_fullflush)
-                need_flush = 1;
+                need_flush = true;
         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 
         return offset;
@@ -134,7 +136,7 @@ static void flush_gart(void)
         spin_lock_irqsave(&iommu_bitmap_lock, flags);
         if (need_flush) {
                 k8_flush_garts();
-                need_flush = 0;
+                need_flush = false;
         }
         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 }
@@ -173,7 +175,8 @@ static void dump_leak(void)
                iommu_leak_pages);
         for (i = 0; i < iommu_leak_pages; i += 2) {
                 printk(KERN_DEBUG "%lu: ", iommu_pages-i);
-                printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0);
+                printk_address((unsigned long) iommu_leak_tab[iommu_pages-i],
+                                0);
                 printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
         }
         printk(KERN_DEBUG "\n");
@@ -212,34 +215,24 @@ static void iommu_full(struct device *dev, size_t size, int dir)
 static inline int
 need_iommu(struct device *dev, unsigned long addr, size_t size)
 {
-        u64 mask = *dev->dma_mask;
-        int high = addr + size > mask;
-        int mmu = high;
-
-        if (force_iommu)
-                mmu = 1;
-
-        return mmu;
+        return force_iommu ||
+                !is_buffer_dma_capable(*dev->dma_mask, addr, size);
 }
 
 static inline int
 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
 {
-        u64 mask = *dev->dma_mask;
-        int high = addr + size > mask;
-        int mmu = high;
-
-        return mmu;
+        return !is_buffer_dma_capable(*dev->dma_mask, addr, size);
 }
 
 /* Map a single continuous physical area into the IOMMU.
  * Caller needs to check if the iommu is needed and flush.
  */
 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
-                                size_t size, int dir)
+                                size_t size, int dir, unsigned long align_mask)
 {
         unsigned long npages = iommu_num_pages(phys_mem, size);
-        unsigned long iommu_page = alloc_iommu(dev, npages);
+        unsigned long iommu_page = alloc_iommu(dev, npages, align_mask);
         int i;
 
         if (iommu_page == -1) {
@@ -259,16 +252,6 @@ static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
         return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
 }
 
-static dma_addr_t
-gart_map_simple(struct device *dev, phys_addr_t paddr, size_t size, int dir)
-{
-        dma_addr_t map = dma_map_area(dev, paddr, size, dir);
-
-        flush_gart();
-
-        return map;
-}
-
 /* Map a single area into the IOMMU */
 static dma_addr_t
 gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
@@ -276,12 +259,13 @@ gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
         unsigned long bus;
 
         if (!dev)
-                dev = &fallback_dev;
+                dev = &x86_dma_fallback_dev;
 
         if (!need_iommu(dev, paddr, size))
                 return paddr;
 
-        bus = gart_map_simple(dev, paddr, size, dir);
+        bus = dma_map_area(dev, paddr, size, dir, 0);
+        flush_gart();
 
         return bus;
 }
@@ -340,7 +324,7 @@ static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
                 unsigned long addr = sg_phys(s);
 
                 if (nonforced_iommu(dev, addr, s->length)) {
-                        addr = dma_map_area(dev, addr, s->length, dir);
+                        addr = dma_map_area(dev, addr, s->length, dir, 0);
                         if (addr == bad_dma_address) {
                                 if (i > 0)
                                         gart_unmap_sg(dev, sg, i, dir);
@@ -362,7 +346,7 @@ static int __dma_map_cont(struct device *dev, struct scatterlist *start,
                           int nelems, struct scatterlist *sout,
                           unsigned long pages)
 {
-        unsigned long iommu_start = alloc_iommu(dev, pages);
+        unsigned long iommu_start = alloc_iommu(dev, pages, 0);
         unsigned long iommu_page = iommu_start;
         struct scatterlist *s;
         int i;
@@ -427,7 +411,7 @@ gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
                 return 0;
 
         if (!dev)
-                dev = &fallback_dev;
+                dev = &x86_dma_fallback_dev;
 
         out = 0;
         start = 0;
@@ -499,6 +483,46 @@ error:
         return 0;
 }
 
+/* allocate and map a coherent mapping */
+static void *
+gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
+                    gfp_t flag)
+{
+        dma_addr_t paddr;
+        unsigned long align_mask;
+        struct page *page;
+
+        if (force_iommu && !(flag & GFP_DMA)) {
+                flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
+                page = alloc_pages(flag | __GFP_ZERO, get_order(size));
+                if (!page)
+                        return NULL;
+
+                align_mask = (1UL << get_order(size)) - 1;
+                paddr = dma_map_area(dev, page_to_phys(page), size,
+                                     DMA_BIDIRECTIONAL, align_mask);
+
+                flush_gart();
+                if (paddr != bad_dma_address) {
+                        *dma_addr = paddr;
+                        return page_address(page);
+                }
+                __free_pages(page, get_order(size));
+        } else
+                return dma_generic_alloc_coherent(dev, size, dma_addr, flag);
+
+        return NULL;
+}
+
+/* free a coherent mapping */
+static void
+gart_free_coherent(struct device *dev, size_t size, void *vaddr,
+                   dma_addr_t dma_addr)
+{
+        gart_unmap_single(dev, dma_addr, size, DMA_BIDIRECTIONAL);
+        free_pages((unsigned long)vaddr, get_order(size));
+}
+
 static int no_agp;
 
 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
@@ -626,7 +650,6 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
         struct pci_dev *dev;
         void *gatt;
         int i, error;
-        unsigned long start_pfn, end_pfn;
 
         printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
         aper_size = aper_base = info->aper_size = 0;
@@ -650,13 +673,13 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
         info->aper_size = aper_size >> 20;
 
         gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
-        gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
+        gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
+                                        get_order(gatt_size));
         if (!gatt)
                 panic("Cannot allocate GATT table");
         if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
                 panic("Could not set GART PTEs to uncacheable pages");
 
-        memset(gatt, 0, gatt_size);
         agp_gatt_table = gatt;
 
         enable_gart_translations();
@@ -665,19 +688,14 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
         if (!error)
                 error = sysdev_register(&device_gart);
         if (error)
-                panic("Could not register gart_sysdev -- would corrupt data on next suspend");
+                panic("Could not register gart_sysdev -- "
+                      "would corrupt data on next suspend");
 
         flush_gart();
 
         printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
                aper_base, aper_size>>10);
 
-        /* need to map that range */
-        end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
-        if (end_pfn > max_low_pfn_mapped) {
-                start_pfn = (aper_base>>PAGE_SHIFT);
-                init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
-        }
         return 0;
 
  nommu:
@@ -687,20 +705,13 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
         return -1;
 }
 
-extern int agp_amd64_init(void);
-
 static struct dma_mapping_ops gart_dma_ops = {
         .map_single                     = gart_map_single,
-        .map_simple                     = gart_map_simple,
         .unmap_single                   = gart_unmap_single,
-        .sync_single_for_cpu            = NULL,
-        .sync_single_for_device         = NULL,
-        .sync_single_range_for_cpu      = NULL,
-        .sync_single_range_for_device   = NULL,
-        .sync_sg_for_cpu                = NULL,
-        .sync_sg_for_device             = NULL,
         .map_sg                         = gart_map_sg,
         .unmap_sg                       = gart_unmap_sg,
+        .alloc_coherent                 = gart_alloc_coherent,
+        .free_coherent                  = gart_free_coherent,
 };
 
 void gart_iommu_shutdown(void)
@@ -727,7 +738,8 @@ void __init gart_iommu_init(void)
 {
         struct agp_kern_info info;
         unsigned long iommu_start;
-        unsigned long aper_size;
+        unsigned long aper_base, aper_size;
+        unsigned long start_pfn, end_pfn;
         unsigned long scratch;
         long i;
 
@@ -759,30 +771,35 @@ void __init gart_iommu_init(void)
             (no_agp && init_k8_gatt(&info) < 0)) {
                 if (max_pfn > MAX_DMA32_PFN) {
                         printk(KERN_WARNING "More than 4GB of memory "
-                                          "but GART IOMMU not available.\n"
-                               KERN_WARNING "falling back to iommu=soft.\n");
+                               "but GART IOMMU not available.\n");
+                        printk(KERN_WARNING "falling back to iommu=soft.\n");
                 }
                 return;
         }
 
+        /* need to map that range */
+        aper_size = info.aper_size << 20;
+        aper_base = info.aper_base;
+        end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
+        if (end_pfn > max_low_pfn_mapped) {
+                start_pfn = (aper_base>>PAGE_SHIFT);
+                init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
+        }
+
         printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
-        aper_size = info.aper_size * 1024 * 1024;
         iommu_size = check_iommu_size(info.aper_base, aper_size);
         iommu_pages = iommu_size >> PAGE_SHIFT;
 
-        iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL,
+        iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
                                                       get_order(iommu_pages/8));
         if (!iommu_gart_bitmap)
                 panic("Cannot allocate iommu bitmap\n");
-        memset(iommu_gart_bitmap, 0, iommu_pages/8);
 
 #ifdef CONFIG_IOMMU_LEAK
         if (leak_trace) {
-                iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
+                iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL|__GFP_ZERO,
                                   get_order(iommu_pages*sizeof(void *)));
-                if (iommu_leak_tab)
-                        memset(iommu_leak_tab, 0, iommu_pages * 8);
-                else
+                if (!iommu_leak_tab)
                         printk(KERN_DEBUG
                                "PCI-DMA: Cannot allocate leak trace area\n");
         }
@@ -792,7 +809,7 @@ void __init gart_iommu_init(void)
          * Out of IOMMU space handling.
          * Reserve some invalid pages at the beginning of the GART.
          */
-        set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
+        iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
 
         agp_memory_reserved = iommu_size;
         printk(KERN_INFO
@@ -850,7 +867,8 @@ void __init gart_parse_options(char *p)
         if (!strncmp(p, "leak", 4)) {
                 leak_trace = 1;
                 p += 4;
-                if (*p == '=') ++p;
+                if (*p == '=')
+                        ++p;
                 if (isdigit(*p) && get_option(&p, &arg))
                         iommu_leak_pages = arg;
         }
diff --git a/arch/x86/kernel/pci-nommu.c b/arch/x86/kernel/pci-nommu.c
index 3f91f71cdc3e..c70ab5a5d4c8 100644
--- a/arch/x86/kernel/pci-nommu.c
+++ b/arch/x86/kernel/pci-nommu.c
@@ -14,7 +14,7 @@
 static int
 check_addr(char *name, struct device *hwdev, dma_addr_t bus, size_t size)
 {
-        if (hwdev && bus + size > *hwdev->dma_mask) {
+        if (hwdev && !is_buffer_dma_capable(*hwdev->dma_mask, bus, size)) {
                 if (*hwdev->dma_mask >= DMA_32BIT_MASK)
                         printk(KERN_ERR
                             "nommu_%s: overflow %Lx+%zu of device mask %Lx\n",
@@ -72,7 +72,15 @@ static int nommu_map_sg(struct device *hwdev, struct scatterlist *sg,
         return nents;
 }
 
+static void nommu_free_coherent(struct device *dev, size_t size, void *vaddr,
+                                dma_addr_t dma_addr)
+{
+        free_pages((unsigned long)vaddr, get_order(size));
+}
+
 struct dma_mapping_ops nommu_dma_ops = {
+        .alloc_coherent = dma_generic_alloc_coherent,
+        .free_coherent = nommu_free_coherent,
         .map_single = nommu_map_single,
         .map_sg = nommu_map_sg,
         .is_phys = 1,
diff --git a/arch/x86/kernel/pcspeaker.c b/arch/x86/kernel/pcspeaker.c
index bc1f2d3ea277..a311ffcaad16 100644
--- a/arch/x86/kernel/pcspeaker.c
+++ b/arch/x86/kernel/pcspeaker.c
@@ -1,20 +1,13 @@
 #include <linux/platform_device.h>
-#include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/init.h>
 
 static __init int add_pcspkr(void)
 {
         struct platform_device *pd;
-        int ret;
 
-        pd = platform_device_alloc("pcspkr", -1);
-        if (!pd)
-                return -ENOMEM;
+        pd = platform_device_register_simple("pcspkr", -1, NULL, 0);
 
-        ret = platform_device_add(pd);
-        if (ret)
-                platform_device_put(pd);
-
-        return ret;
+        return IS_ERR(pd) ? PTR_ERR(pd) : 0;
 }
 device_initcall(add_pcspkr);
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 7fc4d5b0a6a0..c622772744d8 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -15,7 +15,6 @@ unsigned long idle_nomwait;
 EXPORT_SYMBOL(idle_nomwait);
 
 struct kmem_cache *task_xstate_cachep;
-static int force_mwait __cpuinitdata;
 
 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
 {
@@ -185,7 +184,8 @@ static void mwait_idle(void)
 static void poll_idle(void)
 {
         local_irq_enable();
-        cpu_relax();
+        while (!need_resched())
+                cpu_relax();
 }
 
 /*
@@ -246,6 +246,14 @@ static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
         return 1;
 }
 
+static cpumask_t c1e_mask = CPU_MASK_NONE;
+static int c1e_detected;
+
+void c1e_remove_cpu(int cpu)
+{
+        cpu_clear(cpu, c1e_mask);
+}
+
 /*
  * C1E aware idle routine. We check for C1E active in the interrupt
  * pending message MSR. If we detect C1E, then we handle it the same
@@ -253,9 +261,6 @@ static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
  */
 static void c1e_idle(void)
 {
-        static cpumask_t c1e_mask = CPU_MASK_NONE;
-        static int c1e_detected;
-
         if (need_resched())
                 return;
 
@@ -265,8 +270,10 @@ static void c1e_idle(void)
                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
                         c1e_detected = 1;
-                        mark_tsc_unstable("TSC halt in C1E");
-                        printk(KERN_INFO "System has C1E enabled\n");
+                        if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
+                                mark_tsc_unstable("TSC halt in AMD C1E");
+                        printk(KERN_INFO "System has AMD C1E enabled\n");
+                        set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
                 }
         }
 
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 3b7a1ddcc0bc..205188db9626 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -37,6 +37,7 @@
 #include <linux/tick.h>
 #include <linux/percpu.h>
 #include <linux/prctl.h>
+#include <linux/dmi.h>
 
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
@@ -55,6 +56,9 @@
 #include <asm/tlbflush.h>
 #include <asm/cpu.h>
 #include <asm/kdebug.h>
+#include <asm/idle.h>
+#include <asm/syscalls.h>
+#include <asm/smp.h>
 
 asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
 
@@ -88,6 +92,7 @@ static void cpu_exit_clear(void)
         cpu_clear(cpu, cpu_callin_map);
 
         numa_remove_cpu(cpu);
+        c1e_remove_cpu(cpu);
 }
 
 /* We don't actually take CPU down, just spin without interrupts. */
@@ -159,6 +164,7 @@ void __show_registers(struct pt_regs *regs, int all)
         unsigned long d0, d1, d2, d3, d6, d7;
         unsigned long sp;
         unsigned short ss, gs;
+        const char *board;
 
         if (user_mode_vm(regs)) {
                 sp = regs->sp;
@@ -171,11 +177,15 @@ void __show_registers(struct pt_regs *regs, int all)
         }
 
         printk("\n");
-        printk("Pid: %d, comm: %s %s (%s %.*s)\n",
+
+        board = dmi_get_system_info(DMI_PRODUCT_NAME);
+        if (!board)
+                board = "";
+        printk("Pid: %d, comm: %s %s (%s %.*s) %s\n",
                         task_pid_nr(current), current->comm,
                         print_tainted(), init_utsname()->release,
                         (int)strcspn(init_utsname()->version, " "),
-                        init_utsname()->version);
+                        init_utsname()->version, board);
 
         printk("EIP: %04x:[<%08lx>] EFLAGS: %08lx CPU: %d\n",
                         (u16)regs->cs, regs->ip, regs->flags,
@@ -275,6 +285,14 @@ void exit_thread(void)
                 tss->x86_tss.io_bitmap_base = INVALID_IO_BITMAP_OFFSET;
                 put_cpu();
         }
+#ifdef CONFIG_X86_DS
+        /* Free any DS contexts that have not been properly released. */
+        if (unlikely(current->thread.ds_ctx)) {
+                /* we clear debugctl to make sure DS is not used. */
+                update_debugctlmsr(0);
+                ds_free(current->thread.ds_ctx);
+        }
+#endif /* CONFIG_X86_DS */
 }
 
 void flush_thread(void)
@@ -436,6 +454,35 @@ int set_tsc_mode(unsigned int val)
         return 0;
 }
 
+#ifdef CONFIG_X86_DS
+static int update_debugctl(struct thread_struct *prev,
+                        struct thread_struct *next, unsigned long debugctl)
+{
+        unsigned long ds_prev = 0;
+        unsigned long ds_next = 0;
+
+        if (prev->ds_ctx)
+                ds_prev = (unsigned long)prev->ds_ctx->ds;
+        if (next->ds_ctx)
+                ds_next = (unsigned long)next->ds_ctx->ds;
+
+        if (ds_next != ds_prev) {
+                /* we clear debugctl to make sure DS
+                 * is not in use when we change it */
+                debugctl = 0;
+                update_debugctlmsr(0);
+                wrmsr(MSR_IA32_DS_AREA, ds_next, 0);
+        }
+        return debugctl;
+}
+#else
+static int update_debugctl(struct thread_struct *prev,
+                        struct thread_struct *next, unsigned long debugctl)
+{
+        return debugctl;
+}
+#endif /* CONFIG_X86_DS */
+
 static noinline void
 __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
                  struct tss_struct *tss)
@@ -446,14 +493,7 @@ __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
         prev = &prev_p->thread;
         next = &next_p->thread;
 
-        debugctl = prev->debugctlmsr;
-        if (next->ds_area_msr != prev->ds_area_msr) {
-                /* we clear debugctl to make sure DS
-                 * is not in use when we change it */
-                debugctl = 0;
-                update_debugctlmsr(0);
-                wrmsr(MSR_IA32_DS_AREA, next->ds_area_msr, 0);
-        }
+        debugctl = update_debugctl(prev, next, prev->debugctlmsr);
 
         if (next->debugctlmsr != debugctl)
                 update_debugctlmsr(next->debugctlmsr);
@@ -477,13 +517,13 @@ __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
                         hard_enable_TSC();
         }
 
-#ifdef X86_BTS
+#ifdef CONFIG_X86_PTRACE_BTS
         if (test_tsk_thread_flag(prev_p, TIF_BTS_TRACE_TS))
                 ptrace_bts_take_timestamp(prev_p, BTS_TASK_DEPARTS);
 
         if (test_tsk_thread_flag(next_p, TIF_BTS_TRACE_TS))
                 ptrace_bts_take_timestamp(next_p, BTS_TASK_ARRIVES);
-#endif
+#endif /* CONFIG_X86_PTRACE_BTS */
 
 
         if (!test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 71553b664e2a..2a8ccb9238b4 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -37,11 +37,11 @@
 #include <linux/kdebug.h>
 #include <linux/tick.h>
 #include <linux/prctl.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
 
-#include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
-#include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/i387.h>
 #include <asm/mmu_context.h>
@@ -51,6 +51,7 @@
 #include <asm/proto.h>
 #include <asm/ia32.h>
 #include <asm/idle.h>
+#include <asm/syscalls.h>
 
 asmlinkage extern void ret_from_fork(void);
 
@@ -88,11 +89,13 @@ void exit_idle(void)
 #ifdef CONFIG_HOTPLUG_CPU
 DECLARE_PER_CPU(int, cpu_state);
 
-#include <asm/nmi.h>
+#include <linux/nmi.h>
 /* We halt the CPU with physical CPU hotplug */
 static inline void play_dead(void)
 {
         idle_task_exit();
+        c1e_remove_cpu(raw_smp_processor_id());
+
         mb();
         /* Ack it */
         __get_cpu_var(cpu_state) = CPU_DEAD;
@@ -151,7 +154,7 @@ void cpu_idle(void)
 }
 
 /* Prints also some state that isn't saved in the pt_regs */
-void __show_regs(struct pt_regs * regs)
+void __show_regs(struct pt_regs *regs)
 {
         unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs;
         unsigned long d0, d1, d2, d3, d6, d7;
@@ -160,59 +163,61 @@ void __show_regs(struct pt_regs * regs)
 
         printk("\n");
         print_modules();
-        printk("Pid: %d, comm: %.20s %s %s %.*s\n",
+        printk(KERN_INFO "Pid: %d, comm: %.20s %s %s %.*s\n",
                 current->pid, current->comm, print_tainted(),
                 init_utsname()->release,
                 (int)strcspn(init_utsname()->version, " "),
                 init_utsname()->version);
-        printk("RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
+        printk(KERN_INFO "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
         printk_address(regs->ip, 1);
-        printk("RSP: %04lx:%016lx  EFLAGS: %08lx\n", regs->ss, regs->sp,
-                regs->flags);
-        printk("RAX: %016lx RBX: %016lx RCX: %016lx\n",
+        printk(KERN_INFO "RSP: %04lx:%016lx  EFLAGS: %08lx\n", regs->ss,
+                        regs->sp, regs->flags);
+        printk(KERN_INFO "RAX: %016lx RBX: %016lx RCX: %016lx\n",
                regs->ax, regs->bx, regs->cx);
-        printk("RDX: %016lx RSI: %016lx RDI: %016lx\n",
+        printk(KERN_INFO "RDX: %016lx RSI: %016lx RDI: %016lx\n",
                regs->dx, regs->si, regs->di);
-        printk("RBP: %016lx R08: %016lx R09: %016lx\n",
+        printk(KERN_INFO "RBP: %016lx R08: %016lx R09: %016lx\n",
                regs->bp, regs->r8, regs->r9);
-        printk("R10: %016lx R11: %016lx R12: %016lx\n",
-               regs->r10, regs->r11, regs->r12); 
-        printk("R13: %016lx R14: %016lx R15: %016lx\n",
-               regs->r13, regs->r14, regs->r15); 
-
-        asm("movl %%ds,%0" : "=r" (ds)); 
-        asm("movl %%cs,%0" : "=r" (cs)); 
-        asm("movl %%es,%0" : "=r" (es)); 
+        printk(KERN_INFO "R10: %016lx R11: %016lx R12: %016lx\n",
+               regs->r10, regs->r11, regs->r12);
+        printk(KERN_INFO "R13: %016lx R14: %016lx R15: %016lx\n",
+               regs->r13, regs->r14, regs->r15);
+
+        asm("movl %%ds,%0" : "=r" (ds));
+        asm("movl %%cs,%0" : "=r" (cs));
+        asm("movl %%es,%0" : "=r" (es));
         asm("movl %%fs,%0" : "=r" (fsindex));
         asm("movl %%gs,%0" : "=r" (gsindex));
 
         rdmsrl(MSR_FS_BASE, fs);
-        rdmsrl(MSR_GS_BASE, gs); 
-        rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); 
+        rdmsrl(MSR_GS_BASE, gs);
+        rdmsrl(MSR_KERNEL_GS_BASE, shadowgs);
 
         cr0 = read_cr0();
         cr2 = read_cr2();
         cr3 = read_cr3();
         cr4 = read_cr4();
 
-        printk("FS:  %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", 
-               fs,fsindex,gs,gsindex,shadowgs); 
-        printk("CS:  %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds, es, cr0); 
-        printk("CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3, cr4);
+        printk(KERN_INFO "FS:  %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
+               fs, fsindex, gs, gsindex, shadowgs);
+        printk(KERN_INFO "CS:  %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds,
+                        es, cr0);
+        printk(KERN_INFO "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3,
+                        cr4);
 
         get_debugreg(d0, 0);
         get_debugreg(d1, 1);
         get_debugreg(d2, 2);
-        printk("DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
+        printk(KERN_INFO "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
         get_debugreg(d3, 3);
         get_debugreg(d6, 6);
         get_debugreg(d7, 7);
-        printk("DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
+        printk(KERN_INFO "DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
 }
 
 void show_regs(struct pt_regs *regs)
 {
-        printk("CPU %d:", smp_processor_id());
+        printk(KERN_INFO "CPU %d:", smp_processor_id());
         __show_regs(regs);
         show_trace(NULL, regs, (void *)(regs + 1), regs->bp);
 }
@@ -238,6 +243,14 @@ void exit_thread(void)
                 t->io_bitmap_max = 0;
                 put_cpu();
         }
+#ifdef CONFIG_X86_DS
+        /* Free any DS contexts that have not been properly released. */
+        if (unlikely(t->ds_ctx)) {
+                /* we clear debugctl to make sure DS is not used. */
+                update_debugctlmsr(0);
+                ds_free(t->ds_ctx);
+        }
+#endif /* CONFIG_X86_DS */
 }
 
 void flush_thread(void)
@@ -313,10 +326,10 @@ void prepare_to_copy(struct task_struct *tsk)
 
 int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
                 unsigned long unused,
-        struct task_struct * p, struct pt_regs * regs)
+        struct task_struct *p, struct pt_regs *regs)
 {
         int err;
-        struct pt_regs * childregs;
+        struct pt_regs *childregs;
         struct task_struct *me = current;
 
         childregs = ((struct pt_regs *)
@@ -361,10 +374,10 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
                 if (test_thread_flag(TIF_IA32))
                         err = do_set_thread_area(p, -1,
                                 (struct user_desc __user *)childregs->si, 0);
-                else                    
-#endif   
-                        err = do_arch_prctl(p, ARCH_SET_FS, childregs->r8); 
-                if (err) 
+                else
+#endif
+                        err = do_arch_prctl(p, ARCH_SET_FS, childregs->r8);
+                if (err)
                         goto out;
         }
         err = 0;
@@ -471,13 +484,27 @@ static inline void __switch_to_xtra(struct task_struct *prev_p,
         next = &next_p->thread;
 
         debugctl = prev->debugctlmsr;
-        if (next->ds_area_msr != prev->ds_area_msr) {
-                /* we clear debugctl to make sure DS
-                 * is not in use when we change it */
-                debugctl = 0;
-                update_debugctlmsr(0);
-                wrmsrl(MSR_IA32_DS_AREA, next->ds_area_msr);
+
+#ifdef CONFIG_X86_DS
+        {
+                unsigned long ds_prev = 0, ds_next = 0;
+
+                if (prev->ds_ctx)
+                        ds_prev = (unsigned long)prev->ds_ctx->ds;
+                if (next->ds_ctx)
+                        ds_next = (unsigned long)next->ds_ctx->ds;
+
+                if (ds_next != ds_prev) {
+                        /*
+                         * We clear debugctl to make sure DS
+                         * is not in use when we change it:
+                         */
+                        debugctl = 0;
+                        update_debugctlmsr(0);
+                        wrmsrl(MSR_IA32_DS_AREA, ds_next);
+                }
         }
+#endif /* CONFIG_X86_DS */
 
         if (next->debugctlmsr != debugctl)
                 update_debugctlmsr(next->debugctlmsr);
@@ -515,13 +542,13 @@ static inline void __switch_to_xtra(struct task_struct *prev_p,
                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
         }
 
-#ifdef X86_BTS
+#ifdef CONFIG_X86_PTRACE_BTS
         if (test_tsk_thread_flag(prev_p, TIF_BTS_TRACE_TS))
                 ptrace_bts_take_timestamp(prev_p, BTS_TASK_DEPARTS);
 
         if (test_tsk_thread_flag(next_p, TIF_BTS_TRACE_TS))
                 ptrace_bts_take_timestamp(next_p, BTS_TASK_ARRIVES);
-#endif
+#endif /* CONFIG_X86_PTRACE_BTS */
 }
 
 /*
@@ -543,7 +570,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
         unsigned fsindex, gsindex;
 
         /* we're going to use this soon, after a few expensive things */
-        if (next_p->fpu_counter>5)
+        if (next_p->fpu_counter > 5)
                 prefetch(next->xstate);
 
         /*
@@ -551,13 +578,13 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
          */
         load_sp0(tss, next);
 
-        /* 
+        /*
          * Switch DS and ES.
          * This won't pick up thread selector changes, but I guess that is ok.
          */
         savesegment(es, prev->es);
         if (unlikely(next->es | prev->es))
-                loadsegment(es, next->es); 
+                loadsegment(es, next->es);
 
         savesegment(ds, prev->ds);
         if (unlikely(next->ds | prev->ds))
@@ -583,7 +610,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
          */
         arch_leave_lazy_cpu_mode();
 
-        /* 
+        /*
          * Switch FS and GS.
          *
          * Segment register != 0 always requires a reload.  Also
@@ -592,13 +619,13 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
          */
         if (unlikely(fsindex | next->fsindex | prev->fs)) {
                 loadsegment(fs, next->fsindex);
-                /* 
+                /*
                  * Check if the user used a selector != 0; if yes
                  *  clear 64bit base, since overloaded base is always
                  *  mapped to the Null selector
                  */
                 if (fsindex)
-                        prev->fs = 0;                           
+                        prev->fs = 0;
         }
         /* when next process has a 64bit base use it */
         if (next->fs)
@@ -608,7 +635,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
         if (unlikely(gsindex | next->gsindex | prev->gs)) {
                 load_gs_index(next->gsindex);
                 if (gsindex)
-                        prev->gs = 0;                           
+                        prev->gs = 0;
         }
         if (next->gs)
                 wrmsrl(MSR_KERNEL_GS_BASE, next->gs);
@@ -617,12 +644,12 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
         /* Must be after DS reload */
         unlazy_fpu(prev_p);
 
-        /* 
+        /*
          * Switch the PDA and FPU contexts.
          */
         prev->usersp = read_pda(oldrsp);
         write_pda(oldrsp, next->usersp);
-        write_pda(pcurrent, next_p); 
+        write_pda(pcurrent, next_p);
 
         write_pda(kernelstack,
                   (unsigned long)task_stack_page(next_p) +
@@ -663,7 +690,7 @@ long sys_execve(char __user *name, char __user * __user *argv,
                 char __user * __user *envp, struct pt_regs *regs)
 {
         long error;
-        char * filename;
+        char *filename;
 
         filename = getname(name);
         error = PTR_ERR(filename);
@@ -721,55 +748,55 @@ asmlinkage long sys_vfork(struct pt_regs *regs)
 unsigned long get_wchan(struct task_struct *p)
 {
         unsigned long stack;
-        u64 fp,ip;
+        u64 fp, ip;
         int count = 0;
 
-        if (!p || p == current || p->state==TASK_RUNNING)
-                return 0; 
+        if (!p || p == current || p->state == TASK_RUNNING)
+                return 0;
         stack = (unsigned long)task_stack_page(p);
         if (p->thread.sp < stack || p->thread.sp > stack+THREAD_SIZE)
                 return 0;
         fp = *(u64 *)(p->thread.sp);
-        do { 
+        do {
                 if (fp < (unsigned long)stack ||
                     fp > (unsigned long)stack+THREAD_SIZE)
-                        return 0; 
+                        return 0;
                 ip = *(u64 *)(fp+8);
                 if (!in_sched_functions(ip))
                         return ip;
-                fp = *(u64 *)fp; 
-        } while (count++ < 16); 
+                fp = *(u64 *)fp;
+        } while (count++ < 16);
         return 0;
 }
 
 long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
-{ 
-        int ret = 0; 
+{
+        int ret = 0;
         int doit = task == current;
         int cpu;
 
-        switch (code) { 
+        switch (code) {
         case ARCH_SET_GS:
                 if (addr >= TASK_SIZE_OF(task))
-                        return -EPERM; 
+                        return -EPERM;
                 cpu = get_cpu();
-                /* handle small bases via the GDT because that's faster to 
+                /* handle small bases via the GDT because that's faster to
                    switch. */
-                if (addr <= 0xffffffff) {  
-                        set_32bit_tls(task, GS_TLS, addr); 
-                        if (doit) { 
+                if (addr <= 0xffffffff) {
+                        set_32bit_tls(task, GS_TLS, addr);
+                        if (doit) {
                                 load_TLS(&task->thread, cpu);
-                                load_gs_index(GS_TLS_SEL); 
+                                load_gs_index(GS_TLS_SEL);
                         }
-                        task->thread.gsindex = GS_TLS_SEL; 
+                        task->thread.gsindex = GS_TLS_SEL;
                         task->thread.gs = 0;
-                } else { 
+                } else {
                         task->thread.gsindex = 0;
                         task->thread.gs = addr;
                         if (doit) {
                                 load_gs_index(0);
                                 ret = checking_wrmsrl(MSR_KERNEL_GS_BASE, addr);
-                        } 
+                        }
                 }
                 put_cpu();
                 break;
@@ -823,8 +850,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
                                 rdmsrl(MSR_KERNEL_GS_BASE, base);
                         else
                                 base = task->thread.gs;
-                }
-                else
+                } else
                         base = task->thread.gs;
                 ret = put_user(base, (unsigned long __user *)addr);
                 break;
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index e37dccce85db..e375b658efc3 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -14,6 +14,7 @@
 #include <linux/errno.h>
 #include <linux/ptrace.h>
 #include <linux/regset.h>
+#include <linux/tracehook.h>
 #include <linux/user.h>
 #include <linux/elf.h>
 #include <linux/security.h>
@@ -69,7 +70,7 @@ static inline bool invalid_selector(u16 value)
 
 #define FLAG_MASK               FLAG_MASK_32
 
-static long *pt_regs_access(struct pt_regs *regs, unsigned long regno)
+static unsigned long *pt_regs_access(struct pt_regs *regs, unsigned long regno)
 {
         BUILD_BUG_ON(offsetof(struct pt_regs, bx) != 0);
         regno >>= 2;
@@ -554,45 +555,115 @@ static int ptrace_set_debugreg(struct task_struct *child,
         return 0;
 }
 
-#ifdef X86_BTS
+#ifdef CONFIG_X86_PTRACE_BTS
+/*
+ * The configuration for a particular BTS hardware implementation.
+ */
+struct bts_configuration {
+        /* the size of a BTS record in bytes; at most BTS_MAX_RECORD_SIZE */
+        unsigned char  sizeof_bts;
+        /* the size of a field in the BTS record in bytes */
+        unsigned char  sizeof_field;
+        /* a bitmask to enable/disable BTS in DEBUGCTL MSR */
+        unsigned long debugctl_mask;
+};
+static struct bts_configuration bts_cfg;
+
+#define BTS_MAX_RECORD_SIZE (8 * 3)
+
+
+/*
+ * Branch Trace Store (BTS) uses the following format. Different
+ * architectures vary in the size of those fields.
+ * - source linear address
+ * - destination linear address
+ * - flags
+ *
+ * Later architectures use 64bit pointers throughout, whereas earlier
+ * architectures use 32bit pointers in 32bit mode.
+ *
+ * We compute the base address for the first 8 fields based on:
+ * - the field size stored in the DS configuration
+ * - the relative field position
+ *
+ * In order to store additional information in the BTS buffer, we use
+ * a special source address to indicate that the record requires
+ * special interpretation.
+ *
+ * Netburst indicated via a bit in the flags field whether the branch
+ * was predicted; this is ignored.
+ */
+
+enum bts_field {
+        bts_from = 0,
+        bts_to,
+        bts_flags,
+
+        bts_escape = (unsigned long)-1,
+        bts_qual = bts_to,
+        bts_jiffies = bts_flags
+};
+
+static inline unsigned long bts_get(const char *base, enum bts_field field)
+{
+        base += (bts_cfg.sizeof_field * field);
+        return *(unsigned long *)base;
+}
 
-static int ptrace_bts_get_size(struct task_struct *child)
+static inline void bts_set(char *base, enum bts_field field, unsigned long val)
 {
-        if (!child->thread.ds_area_msr)
-                return -ENXIO;
+        base += (bts_cfg.sizeof_field * field);;
+        (*(unsigned long *)base) = val;
+}
 
-        return ds_get_bts_index((void *)child->thread.ds_area_msr);
+/*
+ * Translate a BTS record from the raw format into the bts_struct format
+ *
+ * out (out): bts_struct interpretation
+ * raw: raw BTS record
+ */
+static void ptrace_bts_translate_record(struct bts_struct *out, const void *raw)
+{
+        memset(out, 0, sizeof(*out));
+        if (bts_get(raw, bts_from) == bts_escape) {
+                out->qualifier       = bts_get(raw, bts_qual);
+                out->variant.jiffies = bts_get(raw, bts_jiffies);
+        } else {
+                out->qualifier = BTS_BRANCH;
+                out->variant.lbr.from_ip = bts_get(raw, bts_from);
+                out->variant.lbr.to_ip   = bts_get(raw, bts_to);
+        }
 }
 
-static int ptrace_bts_read_record(struct task_struct *child,
-                                  long index,
+static int ptrace_bts_read_record(struct task_struct *child, size_t index,
                                   struct bts_struct __user *out)
 {
         struct bts_struct ret;
-        int retval;
-        int bts_end;
-        int bts_index;
-
-        if (!child->thread.ds_area_msr)
-                return -ENXIO;
+        const void *bts_record;
+        size_t bts_index, bts_end;
+        int error;
 
-        if (index < 0)
-                return -EINVAL;
+        error = ds_get_bts_end(child, &bts_end);
+        if (error < 0)
+                return error;
 
-        bts_end = ds_get_bts_end((void *)child->thread.ds_area_msr);
         if (bts_end <= index)
                 return -EINVAL;
 
+        error = ds_get_bts_index(child, &bts_index);
+        if (error < 0)
+                return error;
+
         /* translate the ptrace bts index into the ds bts index */
-        bts_index = ds_get_bts_index((void *)child->thread.ds_area_msr);
-        bts_index -= (index + 1);
-        if (bts_index < 0)
-                bts_index += bts_end;
+        bts_index += bts_end - (index + 1);
+        if (bts_end <= bts_index)
+                bts_index -= bts_end;
 
-        retval = ds_read_bts((void *)child->thread.ds_area_msr,
-                             bts_index, &ret);
-        if (retval < 0)
-                return retval;
+        error = ds_access_bts(child, bts_index, &bts_record);
+        if (error < 0)
+                return error;
+
+        ptrace_bts_translate_record(&ret, bts_record);
 
         if (copy_to_user(out, &ret, sizeof(ret)))
                 return -EFAULT;
@@ -600,101 +671,106 @@ static int ptrace_bts_read_record(struct task_struct *child,
         return sizeof(ret);
 }
 
-static int ptrace_bts_clear(struct task_struct *child)
-{
-        if (!child->thread.ds_area_msr)
-                return -ENXIO;
-
-        return ds_clear((void *)child->thread.ds_area_msr);
-}
-
 static int ptrace_bts_drain(struct task_struct *child,
                             long size,
                             struct bts_struct __user *out)
 {
-        int end, i;
-        void *ds = (void *)child->thread.ds_area_msr;
-
-        if (!ds)
-                return -ENXIO;
+        struct bts_struct ret;
+        const unsigned char *raw;
+        size_t end, i;
+        int error;
 
-        end = ds_get_bts_index(ds);
-        if (end <= 0)
-                return end;
+        error = ds_get_bts_index(child, &end);
+        if (error < 0)
+                return error;
 
         if (size < (end * sizeof(struct bts_struct)))
                 return -EIO;
 
-        for (i = 0; i < end; i++, out++) {
-                struct bts_struct ret;
-                int retval;
+        error = ds_access_bts(child, 0, (const void **)&raw);
+        if (error < 0)
+                return error;
 
-                retval = ds_read_bts(ds, i, &ret);
-                if (retval < 0)
-                        return retval;
+        for (i = 0; i < end; i++, out++, raw += bts_cfg.sizeof_bts) {
+                ptrace_bts_translate_record(&ret, raw);
 
                 if (copy_to_user(out, &ret, sizeof(ret)))
                         return -EFAULT;
         }
 
-        ds_clear(ds);
+        error = ds_clear_bts(child);
+        if (error < 0)
+                return error;
 
         return end;
 }
 
+static void ptrace_bts_ovfl(struct task_struct *child)
+{
+        send_sig(child->thread.bts_ovfl_signal, child, 0);
+}
+
 static int ptrace_bts_config(struct task_struct *child,
                              long cfg_size,
                              const struct ptrace_bts_config __user *ucfg)
 {
         struct ptrace_bts_config cfg;
-        int bts_size, ret = 0;
-        void *ds;
+        int error = 0;
+
+        error = -EOPNOTSUPP;
+        if (!bts_cfg.sizeof_bts)
+                goto errout;
 
+        error = -EIO;
         if (cfg_size < sizeof(cfg))
-                return -EIO;
+                goto errout;
 
+        error = -EFAULT;
         if (copy_from_user(&cfg, ucfg, sizeof(cfg)))
-                return -EFAULT;
+                goto errout;
 
-        if ((int)cfg.size < 0)
-                return -EINVAL;
+        error = -EINVAL;
+        if ((cfg.flags & PTRACE_BTS_O_SIGNAL) &&
+            !(cfg.flags & PTRACE_BTS_O_ALLOC))
+                goto errout;
 
-        bts_size = 0;
-        ds = (void *)child->thread.ds_area_msr;
-        if (ds) {
-                bts_size = ds_get_bts_size(ds);
-                if (bts_size < 0)
-                        return bts_size;
-        }
-        cfg.size = PAGE_ALIGN(cfg.size);
+        if (cfg.flags & PTRACE_BTS_O_ALLOC) {
+                ds_ovfl_callback_t ovfl = NULL;
+                unsigned int sig = 0;
+
+                /* we ignore the error in case we were not tracing child */
+                (void)ds_release_bts(child);
 
-        if (bts_size != cfg.size) {
-                ret = ptrace_bts_realloc(child, cfg.size,
-                                         cfg.flags & PTRACE_BTS_O_CUT_SIZE);
-                if (ret < 0)
+                if (cfg.flags & PTRACE_BTS_O_SIGNAL) {
+                        if (!cfg.signal)
+                                goto errout;
+
+                        sig  = cfg.signal;
+                        ovfl = ptrace_bts_ovfl;
+                }
+
+                error = ds_request_bts(child, /* base = */ NULL, cfg.size, ovfl);
+                if (error < 0)
                         goto errout;
 
-                ds = (void *)child->thread.ds_area_msr;
+                child->thread.bts_ovfl_signal = sig;
         }
 
-        if (cfg.flags & PTRACE_BTS_O_SIGNAL)
-                ret = ds_set_overflow(ds, DS_O_SIGNAL);
-        else
-                ret = ds_set_overflow(ds, DS_O_WRAP);
-        if (ret < 0)
+        error = -EINVAL;
+        if (!child->thread.ds_ctx && cfg.flags)
                 goto errout;
 
         if (cfg.flags & PTRACE_BTS_O_TRACE)
-                child->thread.debugctlmsr |= ds_debugctl_mask();
+                child->thread.debugctlmsr |= bts_cfg.debugctl_mask;
         else
-                child->thread.debugctlmsr &= ~ds_debugctl_mask();
+                child->thread.debugctlmsr &= ~bts_cfg.debugctl_mask;
 
         if (cfg.flags & PTRACE_BTS_O_SCHED)
                 set_tsk_thread_flag(child, TIF_BTS_TRACE_TS);
         else
                 clear_tsk_thread_flag(child, TIF_BTS_TRACE_TS);
 
-        ret = sizeof(cfg);
+        error = sizeof(cfg);
 
 out:
         if (child->thread.debugctlmsr)
@@ -702,10 +778,10 @@ out:
         else
                 clear_tsk_thread_flag(child, TIF_DEBUGCTLMSR);
 
-        return ret;
+        return error;
 
 errout:
-        child->thread.debugctlmsr &= ~ds_debugctl_mask();
+        child->thread.debugctlmsr &= ~bts_cfg.debugctl_mask;
         clear_tsk_thread_flag(child, TIF_BTS_TRACE_TS);
         goto out;
 }
@@ -714,29 +790,40 @@ static int ptrace_bts_status(struct task_struct *child,
                              long cfg_size,
                              struct ptrace_bts_config __user *ucfg)
 {
-        void *ds = (void *)child->thread.ds_area_msr;
         struct ptrace_bts_config cfg;
+        size_t end;
+        const void *base, *max;
+        int error;
 
         if (cfg_size < sizeof(cfg))
                 return -EIO;
 
-        memset(&cfg, 0, sizeof(cfg));
+        error = ds_get_bts_end(child, &end);
+        if (error < 0)
+                return error;
 
-        if (ds) {
-                cfg.size = ds_get_bts_size(ds);
+        error = ds_access_bts(child, /* index = */ 0, &base);
+        if (error < 0)
+                return error;
 
-                if (ds_get_overflow(ds) == DS_O_SIGNAL)
-                        cfg.flags |= PTRACE_BTS_O_SIGNAL;
+        error = ds_access_bts(child, /* index = */ end, &max);
+        if (error < 0)
+                return error;
 
-                if (test_tsk_thread_flag(child, TIF_DEBUGCTLMSR) &&
-                    child->thread.debugctlmsr & ds_debugctl_mask())
-                        cfg.flags |= PTRACE_BTS_O_TRACE;
+        memset(&cfg, 0, sizeof(cfg));
+        cfg.size = (max - base);
+        cfg.signal = child->thread.bts_ovfl_signal;
+        cfg.bts_size = sizeof(struct bts_struct);
 
-                if (test_tsk_thread_flag(child, TIF_BTS_TRACE_TS))
-                        cfg.flags |= PTRACE_BTS_O_SCHED;
-        }
+        if (cfg.signal)
+                cfg.flags |= PTRACE_BTS_O_SIGNAL;
 
-        cfg.bts_size = sizeof(struct bts_struct);
+        if (test_tsk_thread_flag(child, TIF_DEBUGCTLMSR) &&
+            child->thread.debugctlmsr & bts_cfg.debugctl_mask)
+                cfg.flags |= PTRACE_BTS_O_TRACE;
+
+        if (test_tsk_thread_flag(child, TIF_BTS_TRACE_TS))
+                cfg.flags |= PTRACE_BTS_O_SCHED;
 
         if (copy_to_user(ucfg, &cfg, sizeof(cfg)))
                 return -EFAULT;
@@ -744,89 +831,38 @@ static int ptrace_bts_status(struct task_struct *child,
         return sizeof(cfg);
 }
 
-
 static int ptrace_bts_write_record(struct task_struct *child,
                                    const struct bts_struct *in)
 {
-        int retval;
+        unsigned char bts_record[BTS_MAX_RECORD_SIZE];
 
-        if (!child->thread.ds_area_msr)
-                return -ENXIO;
+        BUG_ON(BTS_MAX_RECORD_SIZE < bts_cfg.sizeof_bts);
 
-        retval = ds_write_bts((void *)child->thread.ds_area_msr, in);
-        if (retval)
-                return retval;
+        memset(bts_record, 0, bts_cfg.sizeof_bts);
+        switch (in->qualifier) {
+        case BTS_INVALID:
+                break;
 
-        return sizeof(*in);
-}
+        case BTS_BRANCH:
+                bts_set(bts_record, bts_from, in->variant.lbr.from_ip);
+                bts_set(bts_record, bts_to,   in->variant.lbr.to_ip);
+                break;
 
-static int ptrace_bts_realloc(struct task_struct *child,
-                              int size, int reduce_size)
-{
-        unsigned long rlim, vm;
-        int ret, old_size;
+        case BTS_TASK_ARRIVES:
+        case BTS_TASK_DEPARTS:
+                bts_set(bts_record, bts_from,    bts_escape);
+                bts_set(bts_record, bts_qual,    in->qualifier);
+                bts_set(bts_record, bts_jiffies, in->variant.jiffies);
+                break;
 
-        if (size < 0)
+        default:
                 return -EINVAL;
-
-        old_size = ds_get_bts_size((void *)child->thread.ds_area_msr);
-        if (old_size < 0)
-                return old_size;
-
-        ret = ds_free((void **)&child->thread.ds_area_msr);
-        if (ret < 0)
-                goto out;
-
-        size >>= PAGE_SHIFT;
-        old_size >>= PAGE_SHIFT;
-
-        current->mm->total_vm  -= old_size;
-        current->mm->locked_vm -= old_size;
-
-        if (size == 0)
-                goto out;
-
-        rlim = current->signal->rlim[RLIMIT_AS].rlim_cur >> PAGE_SHIFT;
-        vm = current->mm->total_vm  + size;
-        if (rlim < vm) {
-                ret = -ENOMEM;
-
-                if (!reduce_size)
-                        goto out;
-
-                size = rlim - current->mm->total_vm;
-                if (size <= 0)
-                        goto out;
-        }
-
-        rlim = current->signal->rlim[RLIMIT_MEMLOCK].rlim_cur >> PAGE_SHIFT;
-        vm = current->mm->locked_vm  + size;
-        if (rlim < vm) {
-                ret = -ENOMEM;
-
-                if (!reduce_size)
-                        goto out;
-
-                size = rlim - current->mm->locked_vm;
-                if (size <= 0)
-                        goto out;
         }
 
-        ret = ds_allocate((void **)&child->thread.ds_area_msr,
-                          size << PAGE_SHIFT);
-        if (ret < 0)
-                goto out;
-
-        current->mm->total_vm  += size;
-        current->mm->locked_vm += size;
-
-out:
-        if (child->thread.ds_area_msr)
-                set_tsk_thread_flag(child, TIF_DS_AREA_MSR);
-        else
-                clear_tsk_thread_flag(child, TIF_DS_AREA_MSR);
-
-        return ret;
+        /* The writing task will be the switched-to task on a context
+         * switch. It needs to write into the switched-from task's BTS
+         * buffer. */
+        return ds_unchecked_write_bts(child, bts_record, bts_cfg.sizeof_bts);
 }
 
 void ptrace_bts_take_timestamp(struct task_struct *tsk,
@@ -839,7 +875,66 @@ void ptrace_bts_take_timestamp(struct task_struct *tsk,
 
         ptrace_bts_write_record(tsk, &rec);
 }
-#endif /* X86_BTS */
+
+static const struct bts_configuration bts_cfg_netburst = {
+        .sizeof_bts    = sizeof(long) * 3,
+        .sizeof_field  = sizeof(long),
+        .debugctl_mask = (1<<2)|(1<<3)|(1<<5)
+};
+
+static const struct bts_configuration bts_cfg_pentium_m = {
+        .sizeof_bts    = sizeof(long) * 3,
+        .sizeof_field  = sizeof(long),
+        .debugctl_mask = (1<<6)|(1<<7)
+};
+
+static const struct bts_configuration bts_cfg_core2 = {
+        .sizeof_bts    = 8 * 3,
+        .sizeof_field  = 8,
+        .debugctl_mask = (1<<6)|(1<<7)|(1<<9)
+};
+
+static inline void bts_configure(const struct bts_configuration *cfg)
+{
+        bts_cfg = *cfg;
+}
+
+void __cpuinit ptrace_bts_init_intel(struct cpuinfo_x86 *c)
+{
+        switch (c->x86) {
+        case 0x6:
+                switch (c->x86_model) {
+                case 0xD:
+                case 0xE: /* Pentium M */
+                        bts_configure(&bts_cfg_pentium_m);
+                        break;
+                case 0xF: /* Core2 */
+        case 0x1C: /* Atom */
+                        bts_configure(&bts_cfg_core2);
+                        break;
+                default:
+                        /* sorry, don't know about them */
+                        break;
+                }
+                break;
+        case 0xF:
+                switch (c->x86_model) {
+                case 0x0:
+                case 0x1:
+                case 0x2: /* Netburst */
+                        bts_configure(&bts_cfg_netburst);
+                        break;
+                default:
+                        /* sorry, don't know about them */
+                        break;
+                }
+                break;
+        default:
+                /* sorry, don't know about them */
+                break;
+        }
+}
+#endif /* CONFIG_X86_PTRACE_BTS */
 
 /*
  * Called by kernel/ptrace.c when detaching..
@@ -852,15 +947,15 @@ void ptrace_disable(struct task_struct *child)
 #ifdef TIF_SYSCALL_EMU
         clear_tsk_thread_flag(child, TIF_SYSCALL_EMU);
 #endif
-        if (child->thread.ds_area_msr) {
-#ifdef X86_BTS
-                ptrace_bts_realloc(child, 0, 0);
-#endif
-                child->thread.debugctlmsr &= ~ds_debugctl_mask();
-                if (!child->thread.debugctlmsr)
-                        clear_tsk_thread_flag(child, TIF_DEBUGCTLMSR);
-                clear_tsk_thread_flag(child, TIF_BTS_TRACE_TS);
-        }
+#ifdef CONFIG_X86_PTRACE_BTS
+        (void)ds_release_bts(child);
+
+        child->thread.debugctlmsr &= ~bts_cfg.debugctl_mask;
+        if (!child->thread.debugctlmsr)
+                clear_tsk_thread_flag(child, TIF_DEBUGCTLMSR);
+
+        clear_tsk_thread_flag(child, TIF_BTS_TRACE_TS);
+#endif /* CONFIG_X86_PTRACE_BTS */
 }
 
 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
@@ -980,7 +1075,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         /*
          * These bits need more cooking - not enabled yet:
          */
-#ifdef X86_BTS
+#ifdef CONFIG_X86_PTRACE_BTS
         case PTRACE_BTS_CONFIG:
                 ret = ptrace_bts_config
                         (child, data, (struct ptrace_bts_config __user *)addr);
@@ -992,7 +1087,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 break;
 
         case PTRACE_BTS_SIZE:
-                ret = ptrace_bts_get_size(child);
+                ret = ds_get_bts_index(child, /* pos = */ NULL);
                 break;
 
         case PTRACE_BTS_GET:
@@ -1001,14 +1096,14 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 break;
 
         case PTRACE_BTS_CLEAR:
-                ret = ptrace_bts_clear(child);
+                ret = ds_clear_bts(child);
                 break;
 
         case PTRACE_BTS_DRAIN:
                 ret = ptrace_bts_drain
                         (child, data, (struct bts_struct __user *) addr);
                 break;
-#endif
+#endif /* CONFIG_X86_PTRACE_BTS */
 
         default:
                 ret = ptrace_request(child, request, addr, data);
@@ -1375,30 +1470,6 @@ void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, int error_code)
         force_sig_info(SIGTRAP, &info, tsk);
 }
 
-static void syscall_trace(struct pt_regs *regs)
-{
-        if (!(current->ptrace & PT_PTRACED))
-                return;
-
-#if 0
-        printk("trace %s ip %lx sp %lx ax %d origrax %d caller %lx tiflags %x ptrace %x\n",
-               current->comm,
-               regs->ip, regs->sp, regs->ax, regs->orig_ax, __builtin_return_address(0),
-               current_thread_info()->flags, current->ptrace);
-#endif
-
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-                                ? 0x80 : 0));
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (current->exit_code) {
-                send_sig(current->exit_code, current, 1);
-                current->exit_code = 0;
-        }
-}
 
 #ifdef CONFIG_X86_32
 # define IS_IA32        1
@@ -1432,8 +1503,9 @@ asmregparm long syscall_trace_enter(struct pt_regs *regs)
         if (unlikely(test_thread_flag(TIF_SYSCALL_EMU)))
                 ret = -1L;
 
-        if (ret || test_thread_flag(TIF_SYSCALL_TRACE))
-                syscall_trace(regs);
+        if ((ret || test_thread_flag(TIF_SYSCALL_TRACE)) &&
+            tracehook_report_syscall_entry(regs))
+                ret = -1L;
 
         if (unlikely(current->audit_context)) {
                 if (IS_IA32)
@@ -1459,7 +1531,7 @@ asmregparm void syscall_trace_leave(struct pt_regs *regs)
                 audit_syscall_exit(AUDITSC_RESULT(regs->ax), regs->ax);
 
         if (test_thread_flag(TIF_SYSCALL_TRACE))
-                syscall_trace(regs);
+                tracehook_report_syscall_exit(regs, 0);
 
         /*
          * If TIF_SYSCALL_EMU is set, we only get here because of
@@ -1475,6 +1547,6 @@ asmregparm void syscall_trace_leave(struct pt_regs *regs)
          * system call instruction.
          */
         if (test_thread_flag(TIF_SINGLESTEP) &&
-            (current->ptrace & PT_PTRACED))
+            tracehook_consider_fatal_signal(current, SIGTRAP, SIG_DFL))
                 send_sigtrap(current, regs, 0);
 }
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 724adfc63cb9..f4c93f1cfc19 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -29,7 +29,11 @@ EXPORT_SYMBOL(pm_power_off);
 
 static const struct desc_ptr no_idt = {};
 static int reboot_mode;
-enum reboot_type reboot_type = BOOT_KBD;
+/*
+ * Keyboard reset and triple fault may result in INIT, not RESET, which
+ * doesn't work when we're in vmx root mode.  Try ACPI first.
+ */
+enum reboot_type reboot_type = BOOT_ACPI;
 int reboot_force;
 
 #if defined(CONFIG_X86_32) && defined(CONFIG_SMP)
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 3ce3edfcc3cd..21b8e0a59780 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -223,6 +223,9 @@ unsigned long saved_video_mode;
 #define RAMDISK_LOAD_FLAG               0x4000
 
 static char __initdata command_line[COMMAND_LINE_SIZE];
+#ifdef CONFIG_CMDLINE_BOOL
+static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
+#endif
 
 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
 struct edd edd;
@@ -849,11 +852,28 @@ void __init setup_arch(char **cmdline_p)
         bss_resource.start = virt_to_phys(&__bss_start);
         bss_resource.end = virt_to_phys(&__bss_stop)-1;
 
+#ifdef CONFIG_CMDLINE_BOOL
+#ifdef CONFIG_CMDLINE_OVERRIDE
+        strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
+#else
+        if (builtin_cmdline[0]) {
+                /* append boot loader cmdline to builtin */
+                strlcat(builtin_cmdline, " ", COMMAND_LINE_SIZE);
+                strlcat(builtin_cmdline, boot_command_line, COMMAND_LINE_SIZE);
+                strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
+        }
+#endif
+#endif
+
         strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
         *cmdline_p = command_line;
 
         parse_early_param();
 
+#ifdef CONFIG_X86_64
+        check_efer();
+#endif
+
 #if defined(CONFIG_VMI) && defined(CONFIG_X86_32)
         /*
          * Must be before kernel pagetables are setup
@@ -926,7 +946,8 @@ void __init setup_arch(char **cmdline_p)
 #else
         num_physpages = max_pfn;
 
-        check_efer();
+        if (cpu_has_x2apic)
+                check_x2apic();
 
         /* How many end-of-memory variables you have, grandma! */
         /* need this before calling reserve_initrd */
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index 76e305e064f9..0e67f72d9316 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -162,9 +162,16 @@ void __init setup_per_cpu_areas(void)
                         printk(KERN_INFO
                                "cpu %d has no node %d or node-local memory\n",
                                 cpu, node);
+                        if (ptr)
+                                printk(KERN_DEBUG "per cpu data for cpu%d at %016lx\n",
+                                         cpu, __pa(ptr));
                 }
-                else
+                else {
                         ptr = alloc_bootmem_pages_node(NODE_DATA(node), size);
+                        if (ptr)
+                                printk(KERN_DEBUG "per cpu data for cpu%d on node%d at %016lx\n",
+                                         cpu, node, __pa(ptr));
+                }
 #endif
                 per_cpu_offset(cpu) = ptr - __per_cpu_start;
                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
diff --git a/arch/x86/kernel/sigframe.h b/arch/x86/kernel/sigframe.h
index 72bbb519d2dc..cc673aa55ce4 100644
--- a/arch/x86/kernel/sigframe.h
+++ b/arch/x86/kernel/sigframe.h
@@ -3,9 +3,18 @@ struct sigframe {
         char __user *pretcode;
         int sig;
         struct sigcontext sc;
-        struct _fpstate fpstate;
+        /*
+         * fpstate is unused. fpstate is moved/allocated after
+         * retcode[] below. This movement allows to have the FP state and the
+         * future state extensions (xsave) stay together.
+         * And at the same time retaining the unused fpstate, prevents changing
+         * the offset of extramask[] in the sigframe and thus prevent any
+         * legacy application accessing/modifying it.
+         */
+        struct _fpstate fpstate_unused;
         unsigned long extramask[_NSIG_WORDS-1];
         char retcode[8];
+        /* fp state follows here */
 };
 
 struct rt_sigframe {
@@ -15,13 +24,19 @@ struct rt_sigframe {
         void __user *puc;
         struct siginfo info;
         struct ucontext uc;
-        struct _fpstate fpstate;
         char retcode[8];
+        /* fp state follows here */
 };
 #else
 struct rt_sigframe {
         char __user *pretcode;
         struct ucontext uc;
         struct siginfo info;
+        /* fp state follows here */
 };
+
+int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+                sigset_t *set, struct pt_regs *regs);
+int ia32_setup_frame(int sig, struct k_sigaction *ka,
+                sigset_t *set, struct pt_regs *regs);
 #endif
diff --git a/arch/x86/kernel/signal_32.c b/arch/x86/kernel/signal_32.c
index 6fb5bcdd8933..b21070ea33a4 100644
--- a/arch/x86/kernel/signal_32.c
+++ b/arch/x86/kernel/signal_32.c
@@ -17,6 +17,7 @@
 #include <linux/errno.h>
 #include <linux/sched.h>
 #include <linux/wait.h>
+#include <linux/tracehook.h>
 #include <linux/elf.h>
 #include <linux/smp.h>
 #include <linux/mm.h>
@@ -26,6 +27,7 @@
 #include <asm/uaccess.h>
 #include <asm/i387.h>
 #include <asm/vdso.h>
+#include <asm/syscalls.h>
 
 #include "sigframe.h"
 
@@ -159,28 +161,14 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc,
         }
 
         {
-                struct _fpstate __user *buf;
+                void __user *buf;
 
                 err |= __get_user(buf, &sc->fpstate);
-                if (buf) {
-                        if (!access_ok(VERIFY_READ, buf, sizeof(*buf)))
-                                goto badframe;
-                        err |= restore_i387(buf);
-                } else {
-                        struct task_struct *me = current;
-
-                        if (used_math()) {
-                                clear_fpu(me);
-                                clear_used_math();
-                        }
-                }
+                err |= restore_i387_xstate(buf);
         }
 
         err |= __get_user(*pax, &sc->ax);
         return err;
-
-badframe:
-        return 1;
 }
 
 asmlinkage unsigned long sys_sigreturn(unsigned long __unused)
@@ -262,7 +250,7 @@ badframe:
  * Set up a signal frame.
  */
 static int
-setup_sigcontext(struct sigcontext __user *sc, struct _fpstate __user *fpstate,
+setup_sigcontext(struct sigcontext __user *sc, void __user *fpstate,
                  struct pt_regs *regs, unsigned long mask)
 {
         int tmp, err = 0;
@@ -289,7 +277,7 @@ setup_sigcontext(struct sigcontext __user *sc, struct _fpstate __user *fpstate,
         err |= __put_user(regs->sp, &sc->sp_at_signal);
         err |= __put_user(regs->ss, (unsigned int __user *)&sc->ss);
 
-        tmp = save_i387(fpstate);
+        tmp = save_i387_xstate(fpstate);
         if (tmp < 0)
                 err = 1;
         else
@@ -306,7 +294,8 @@ setup_sigcontext(struct sigcontext __user *sc, struct _fpstate __user *fpstate,
  * Determine which stack to use..
  */
 static inline void __user *
-get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
+get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size,
+             void **fpstate)
 {
         unsigned long sp;
 
@@ -332,6 +321,11 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
                         sp = (unsigned long) ka->sa.sa_restorer;
         }
 
+        if (used_math()) {
+                sp = sp - sig_xstate_size;
+                *fpstate = (struct _fpstate *) sp;
+        }
+
         sp -= frame_size;
         /*
          * Align the stack pointer according to the i386 ABI,
@@ -350,8 +344,9 @@ setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
         void __user *restorer;
         int err = 0;
         int usig;
+        void __user *fpstate = NULL;
 
-        frame = get_sigframe(ka, regs, sizeof(*frame));
+        frame = get_sigframe(ka, regs, sizeof(*frame), &fpstate);
 
         if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
                 goto give_sigsegv;
@@ -366,7 +361,7 @@ setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
         if (err)
                 goto give_sigsegv;
 
-        err = setup_sigcontext(&frame->sc, &frame->fpstate, regs, set->sig[0]);
+        err = setup_sigcontext(&frame->sc, fpstate, regs, set->sig[0]);
         if (err)
                 goto give_sigsegv;
 
@@ -427,8 +422,9 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         void __user *restorer;
         int err = 0;
         int usig;
+        void __user *fpstate = NULL;
 
-        frame = get_sigframe(ka, regs, sizeof(*frame));
+        frame = get_sigframe(ka, regs, sizeof(*frame), &fpstate);
 
         if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
                 goto give_sigsegv;
@@ -447,13 +443,16 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                 goto give_sigsegv;
 
         /* Create the ucontext.  */
-        err |= __put_user(0, &frame->uc.uc_flags);
+        if (cpu_has_xsave)
+                err |= __put_user(UC_FP_XSTATE, &frame->uc.uc_flags);
+        else
+                err |= __put_user(0, &frame->uc.uc_flags);
         err |= __put_user(0, &frame->uc.uc_link);
         err |= __put_user(current->sas_ss_sp, &frame->uc.uc_stack.ss_sp);
         err |= __put_user(sas_ss_flags(regs->sp),
                           &frame->uc.uc_stack.ss_flags);
         err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
-        err |= setup_sigcontext(&frame->uc.uc_mcontext, &frame->fpstate,
+        err |= setup_sigcontext(&frame->uc.uc_mcontext, fpstate,
                                 regs, set->sig[0]);
         err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
         if (err)
@@ -558,8 +557,6 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
          * handler too.
          */
         regs->flags &= ~X86_EFLAGS_TF;
-        if (test_thread_flag(TIF_SINGLESTEP))
-                ptrace_notify(SIGTRAP);
 
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
@@ -568,6 +565,9 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
 
+        tracehook_signal_handler(sig, info, ka, regs,
+                                 test_thread_flag(TIF_SINGLESTEP));
+
         return 0;
 }
 
@@ -661,5 +661,10 @@ do_notify_resume(struct pt_regs *regs, void *unused, __u32 thread_info_flags)
         if (thread_info_flags & _TIF_SIGPENDING)
                 do_signal(regs);
 
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+        }
+
         clear_thread_flag(TIF_IRET);
 }
diff --git a/arch/x86/kernel/signal_64.c b/arch/x86/kernel/signal_64.c
index ca316b5b742c..823a55bf8c39 100644
--- a/arch/x86/kernel/signal_64.c
+++ b/arch/x86/kernel/signal_64.c
@@ -15,17 +15,21 @@
 #include <linux/errno.h>
 #include <linux/wait.h>
 #include <linux/ptrace.h>
+#include <linux/tracehook.h>
 #include <linux/unistd.h>
 #include <linux/stddef.h>
 #include <linux/personality.h>
 #include <linux/compiler.h>
+#include <linux/uaccess.h>
+
 #include <asm/processor.h>
 #include <asm/ucontext.h>
-#include <asm/uaccess.h>
 #include <asm/i387.h>
 #include <asm/proto.h>
 #include <asm/ia32_unistd.h>
 #include <asm/mce.h>
+#include <asm/syscall.h>
+#include <asm/syscalls.h>
 #include "sigframe.h"
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
@@ -41,11 +45,6 @@
 # define FIX_EFLAGS     __FIX_EFLAGS
 #endif
 
-int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
-               sigset_t *set, struct pt_regs * regs); 
-int ia32_setup_frame(int sig, struct k_sigaction *ka,
-            sigset_t *set, struct pt_regs * regs); 
-
 asmlinkage long
 sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
                 struct pt_regs *regs)
@@ -54,69 +53,6 @@ sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
 }
 
 /*
- * Signal frame handlers.
- */
-
-static inline int save_i387(struct _fpstate __user *buf)
-{
-        struct task_struct *tsk = current;
-        int err = 0;
-
-        BUILD_BUG_ON(sizeof(struct user_i387_struct) !=
-                        sizeof(tsk->thread.xstate->fxsave));
-
-        if ((unsigned long)buf % 16)
-                printk("save_i387: bad fpstate %p\n", buf);
-
-        if (!used_math())
-                return 0;
-        clear_used_math(); /* trigger finit */
-        if (task_thread_info(tsk)->status & TS_USEDFPU) {
-                err = save_i387_checking((struct i387_fxsave_struct __user *)
-                                         buf);
-                if (err)
-                        return err;
-                task_thread_info(tsk)->status &= ~TS_USEDFPU;
-                stts();
-        } else {
-                if (__copy_to_user(buf, &tsk->thread.xstate->fxsave,
-                                   sizeof(struct i387_fxsave_struct)))
-                        return -1;
-        }
-        return 1;
-}
-
-/*
- * This restores directly out of user space. Exceptions are handled.
- */
-static inline int restore_i387(struct _fpstate __user *buf)
-{
-        struct task_struct *tsk = current;
-        int err;
-
-        if (!used_math()) {
-                err = init_fpu(tsk);
-                if (err)
-                        return err;
-        }
-
-        if (!(task_thread_info(current)->status & TS_USEDFPU)) {
-                clts();
-                task_thread_info(current)->status |= TS_USEDFPU;
-        }
-        err = restore_fpu_checking((__force struct i387_fxsave_struct *)buf);
-        if (unlikely(err)) {
-                /*
-                 * Encountered an error while doing the restore from the
-                 * user buffer, clear the fpu state.
-                 */
-                clear_fpu(tsk);
-                clear_used_math();
-        }
-        return err;
-}
-
-/*
  * Do a signal return; undo the signal stack.
  */
 static int
@@ -128,7 +64,7 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc,
         /* Always make any pending restarted system calls return -EINTR */
         current_thread_info()->restart_block.fn = do_no_restart_syscall;
 
-#define COPY(x)         err |= __get_user(regs->x, &sc->x)
+#define COPY(x)         (err |= __get_user(regs->x, &sc->x))
 
         COPY(di); COPY(si); COPY(bp); COPY(sp); COPY(bx);
         COPY(dx); COPY(cx); COPY(ip);
@@ -158,27 +94,13 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc,
         }
 
         {
-                struct _fpstate __user * buf;
+                struct _fpstate __user *buf;
                 err |= __get_user(buf, &sc->fpstate);
-
-                if (buf) {
-                        if (!access_ok(VERIFY_READ, buf, sizeof(*buf)))
-                                goto badframe;
-                        err |= restore_i387(buf);
-                } else {
-                        struct task_struct *me = current;
-                        if (used_math()) {
-                                clear_fpu(me);
-                                clear_used_math();
-                        }
-                }
+                err |= restore_i387_xstate(buf);
         }
 
         err |= __get_user(*pax, &sc->ax);
         return err;
-
-badframe:
-        return 1;
 }
 
 asmlinkage long sys_rt_sigreturn(struct pt_regs *regs)
@@ -198,7 +120,7 @@ asmlinkage long sys_rt_sigreturn(struct pt_regs *regs)
         current->blocked = set;
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
-        
+
         if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &ax))
                 goto badframe;
 
@@ -208,16 +130,17 @@ asmlinkage long sys_rt_sigreturn(struct pt_regs *regs)
         return ax;
 
 badframe:
-        signal_fault(regs,frame,"sigreturn");
+        signal_fault(regs, frame, "sigreturn");
         return 0;
-}       
+}
 
 /*
  * Set up a signal frame.
  */
 
 static inline int
-setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, unsigned long mask, struct task_struct *me)
+setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
+                unsigned long mask, struct task_struct *me)
 {
         int err = 0;
 
@@ -269,41 +192,41 @@ get_stack(struct k_sigaction *ka, struct pt_regs *regs, unsigned long size)
                         sp = current->sas_ss_sp + current->sas_ss_size;
         }
 
-        return (void __user *)round_down(sp - size, 16);
+        return (void __user *)round_down(sp - size, 64);
 }
 
 static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
-                           sigset_t *set, struct pt_regs * regs)
+                           sigset_t *set, struct pt_regs *regs)
 {
         struct rt_sigframe __user *frame;
-        struct _fpstate __user *fp = NULL; 
+        void __user *fp = NULL;
         int err = 0;
         struct task_struct *me = current;
 
         if (used_math()) {
-                fp = get_stack(ka, regs, sizeof(struct _fpstate)); 
+                fp = get_stack(ka, regs, sig_xstate_size);
                 frame = (void __user *)round_down(
                         (unsigned long)fp - sizeof(struct rt_sigframe), 16) - 8;
 
-                if (!access_ok(VERIFY_WRITE, fp, sizeof(struct _fpstate)))
-                        goto give_sigsegv;
-
-                if (save_i387(fp) < 0) 
-                        err |= -1; 
+                if (save_i387_xstate(fp) < 0)
+                        err |= -1;
         } else
                 frame = get_stack(ka, regs, sizeof(struct rt_sigframe)) - 8;
 
         if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
                 goto give_sigsegv;
 
-        if (ka->sa.sa_flags & SA_SIGINFO) { 
+        if (ka->sa.sa_flags & SA_SIGINFO) {
                 err |= copy_siginfo_to_user(&frame->info, info);
                 if (err)
                         goto give_sigsegv;
         }
-                
+
         /* Create the ucontext.  */
-        err |= __put_user(0, &frame->uc.uc_flags);
+        if (cpu_has_xsave)
+                err |= __put_user(UC_FP_XSTATE, &frame->uc.uc_flags);
+        else
+                err |= __put_user(0, &frame->uc.uc_flags);
         err |= __put_user(0, &frame->uc.uc_link);
         err |= __put_user(me->sas_ss_sp, &frame->uc.uc_stack.ss_sp);
         err |= __put_user(sas_ss_flags(regs->sp),
@@ -311,9 +234,9 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         err |= __put_user(me->sas_ss_size, &frame->uc.uc_stack.ss_size);
         err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0], me);
         err |= __put_user(fp, &frame->uc.uc_mcontext.fpstate);
-        if (sizeof(*set) == 16) { 
+        if (sizeof(*set) == 16) {
                 __put_user(set->sig[0], &frame->uc.uc_sigmask.sig[0]);
-                __put_user(set->sig[1], &frame->uc.uc_sigmask.sig[1]); 
+                __put_user(set->sig[1], &frame->uc.uc_sigmask.sig[1]);
         } else
                 err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
 
@@ -324,7 +247,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                 err |= __put_user(ka->sa.sa_restorer, &frame->pretcode);
         } else {
                 /* could use a vstub here */
-                goto give_sigsegv; 
+                goto give_sigsegv;
         }
 
         if (err)
@@ -332,7 +255,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
 
         /* Set up registers for signal handler */
         regs->di = sig;
-        /* In case the signal handler was declared without prototypes */ 
+        /* In case the signal handler was declared without prototypes */
         regs->ax = 0;
 
         /* This also works for non SA_SIGINFO handlers because they expect the
@@ -355,37 +278,8 @@ give_sigsegv:
 }
 
 /*
- * Return -1L or the syscall number that @regs is executing.
- */
-static long current_syscall(struct pt_regs *regs)
-{
-        /*
-         * We always sign-extend a -1 value being set here,
-         * so this is always either -1L or a syscall number.
-         */
-        return regs->orig_ax;
-}
-
-/*
- * Return a value that is -EFOO if the system call in @regs->orig_ax
- * returned an error.  This only works for @regs from @current.
- */
-static long current_syscall_ret(struct pt_regs *regs)
-{
-#ifdef CONFIG_IA32_EMULATION
-        if (test_thread_flag(TIF_IA32))
-                /*
-                 * Sign-extend the value so (int)-EFOO becomes (long)-EFOO
-                 * and will match correctly in comparisons.
-                 */
-                return (int) regs->ax;
-#endif
-        return regs->ax;
-}
-
-/*
  * OK, we're invoking a handler
- */     
+ */
 
 static int
 handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
@@ -394,9 +288,9 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
         int ret;
 
         /* Are we from a system call? */
-        if (current_syscall(regs) >= 0) {
+        if (syscall_get_nr(current, regs) >= 0) {
                 /* If so, check system call restarting.. */
-                switch (current_syscall_ret(regs)) {
+                switch (syscall_get_error(current, regs)) {
                 case -ERESTART_RESTARTBLOCK:
                 case -ERESTARTNOHAND:
                         regs->ax = -EINTR;
@@ -429,7 +323,7 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
                         ret = ia32_setup_rt_frame(sig, ka, info, oldset, regs);
                 else
                         ret = ia32_setup_frame(sig, ka, oldset, regs);
-        } else 
+        } else
 #endif
         ret = setup_rt_frame(sig, ka, info, oldset, regs);
 
@@ -453,15 +347,16 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
                  * handler too.
                  */
                 regs->flags &= ~X86_EFLAGS_TF;
-                if (test_thread_flag(TIF_SINGLESTEP))
-                        ptrace_notify(SIGTRAP);
 
                 spin_lock_irq(&current->sighand->siglock);
-                sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
+                sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
                 if (!(ka->sa.sa_flags & SA_NODEFER))
-                        sigaddset(&current->blocked,sig);
+                        sigaddset(&current->blocked, sig);
                 recalc_sigpending();
                 spin_unlock_irq(&current->sighand->siglock);
+
+                tracehook_signal_handler(sig, info, ka, regs,
+                                         test_thread_flag(TIF_SINGLESTEP));
         }
 
         return ret;
@@ -518,9 +413,9 @@ static void do_signal(struct pt_regs *regs)
         }
 
         /* Did we come from a system call? */
-        if (current_syscall(regs) >= 0) {
+        if (syscall_get_nr(current, regs) >= 0) {
                 /* Restart the system call - no handlers present */
-                switch (current_syscall_ret(regs)) {
+                switch (syscall_get_error(current, regs)) {
                 case -ERESTARTNOHAND:
                 case -ERESTARTSYS:
                 case -ERESTARTNOINTR:
@@ -558,17 +453,23 @@ void do_notify_resume(struct pt_regs *regs, void *unused,
         /* deal with pending signal delivery */
         if (thread_info_flags & _TIF_SIGPENDING)
                 do_signal(regs);
+
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+        }
 }
 
 void signal_fault(struct pt_regs *regs, void __user *frame, char *where)
-{ 
-        struct task_struct *me = current; 
+{
+        struct task_struct *me = current;
         if (show_unhandled_signals && printk_ratelimit()) {
                 printk("%s[%d] bad frame in %s frame:%p ip:%lx sp:%lx orax:%lx",
-               me->comm,me->pid,where,frame,regs->ip,regs->sp,regs->orig_ax);
+               me->comm, me->pid, where, frame, regs->ip,
+                   regs->sp, regs->orig_ax);
                 print_vma_addr(" in ", regs->ip);
                 printk("\n");
         }
 
-        force_sig(SIGSEGV, me); 
-} 
+        force_sig(SIGSEGV, me);
+}
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 7985c5b3f916..9056f7e272c0 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -88,7 +88,7 @@ static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
 #define get_idle_for_cpu(x)      (per_cpu(idle_thread_array, x))
 #define set_idle_for_cpu(x, p)   (per_cpu(idle_thread_array, x) = (p))
 #else
-struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
+static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
 #define get_idle_for_cpu(x)      (idle_thread_array[(x)])
 #define set_idle_for_cpu(x, p)   (idle_thread_array[(x)] = (p))
 #endif
@@ -123,13 +123,12 @@ EXPORT_PER_CPU_SYMBOL(cpu_info);
 
 static atomic_t init_deasserted;
 
-static int boot_cpu_logical_apicid;
 
 /* representing cpus for which sibling maps can be computed */
 static cpumask_t cpu_sibling_setup_map;
 
 /* Set if we find a B stepping CPU */
-int __cpuinitdata smp_b_stepping;
+static int __cpuinitdata smp_b_stepping;
 
 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
 
@@ -165,6 +164,8 @@ static void unmap_cpu_to_node(int cpu)
 #endif
 
 #ifdef CONFIG_X86_32
+static int boot_cpu_logical_apicid;
+
 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
                                         { [0 ... NR_CPUS-1] = BAD_APICID };
 
@@ -210,7 +211,7 @@ static void __cpuinit smp_callin(void)
         /*
          * (This works even if the APIC is not enabled.)
          */
-        phys_id = GET_APIC_ID(read_apic_id());
+        phys_id = read_apic_id();
         cpuid = smp_processor_id();
         if (cpu_isset(cpuid, cpu_callin_map)) {
                 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
@@ -257,6 +258,7 @@ static void __cpuinit smp_callin(void)
         end_local_APIC_setup();
         map_cpu_to_logical_apicid();
 
+        notify_cpu_starting(cpuid);
         /*
          * Get our bogomips.
          *
@@ -550,8 +552,7 @@ static inline void __inquire_remote_apic(int apicid)
                         printk(KERN_CONT
                                "a previous APIC delivery may have failed\n");
 
-                apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
-                apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]);
+                apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
 
                 timeout = 0;
                 do {
@@ -583,11 +584,9 @@ wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
         int maxlvt;
 
         /* Target chip */
-        apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
-
         /* Boot on the stack */
         /* Kick the second */
-        apic_write(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
+        apic_icr_write(APIC_DM_NMI | APIC_DEST_LOGICAL, logical_apicid);
 
         pr_debug("Waiting for send to finish...\n");
         send_status = safe_apic_wait_icr_idle();
@@ -640,13 +639,11 @@ wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
         /*
          * Turn INIT on target chip
          */
-        apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
-
         /*
          * Send IPI
          */
-        apic_write(APIC_ICR,
-                   APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
+        apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
+                       phys_apicid);
 
         pr_debug("Waiting for send to finish...\n");
         send_status = safe_apic_wait_icr_idle();
@@ -656,10 +653,8 @@ wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
         pr_debug("Deasserting INIT.\n");
 
         /* Target chip */
-        apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
-
         /* Send IPI */
-        apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
+        apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
 
         pr_debug("Waiting for send to finish...\n");
         send_status = safe_apic_wait_icr_idle();
@@ -702,11 +697,10 @@ wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
                  */
 
                 /* Target chip */
-                apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
-
                 /* Boot on the stack */
                 /* Kick the second */
-                apic_write(APIC_ICR, APIC_DM_STARTUP | (start_eip >> 12));
+                apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
+                               phys_apicid);
 
                 /*
                  * Give the other CPU some time to accept the IPI.
@@ -1175,10 +1169,17 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
          * Setup boot CPU information
          */
         smp_store_cpu_info(0); /* Final full version of the data */
+#ifdef CONFIG_X86_32
         boot_cpu_logical_apicid = logical_smp_processor_id();
+#endif
         current_thread_info()->cpu = 0;  /* needed? */
         set_cpu_sibling_map(0);
 
+#ifdef CONFIG_X86_64
+        enable_IR_x2apic();
+        setup_apic_routing();
+#endif
+
         if (smp_sanity_check(max_cpus) < 0) {
                 printk(KERN_INFO "SMP disabled\n");
                 disable_smp();
@@ -1186,9 +1187,9 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
         }
 
         preempt_disable();
-        if (GET_APIC_ID(read_apic_id()) != boot_cpu_physical_apicid) {
+        if (read_apic_id() != boot_cpu_physical_apicid) {
                 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
-                     GET_APIC_ID(read_apic_id()), boot_cpu_physical_apicid);
+                     read_apic_id(), boot_cpu_physical_apicid);
                 /* Or can we switch back to PIC here? */
         }
         preempt_enable();
@@ -1313,16 +1314,13 @@ __init void prefill_possible_map(void)
         if (!num_processors)
                 num_processors = 1;
 
-#ifdef CONFIG_HOTPLUG_CPU
         if (additional_cpus == -1) {
                 if (disabled_cpus > 0)
                         additional_cpus = disabled_cpus;
                 else
                         additional_cpus = 0;
         }
-#else
-        additional_cpus = 0;
-#endif
+
         possible = num_processors + additional_cpus;
         if (possible > NR_CPUS)
                 possible = NR_CPUS;
diff --git a/arch/x86/kernel/summit_32.c b/arch/x86/kernel/summit_32.c
index d67ce5f044ba..7b987852e876 100644
--- a/arch/x86/kernel/summit_32.c
+++ b/arch/x86/kernel/summit_32.c
@@ -30,7 +30,7 @@
 #include <linux/init.h>
 #include <asm/io.h>
 #include <asm/bios_ebda.h>
-#include <asm/mach-summit/mach_mpparse.h>
+#include <asm/summit/mpparse.h>
 
 static struct rio_table_hdr *rio_table_hdr __initdata;
 static struct scal_detail   *scal_devs[MAX_NUMNODES] __initdata;
diff --git a/arch/x86/kernel/sys_i386_32.c b/arch/x86/kernel/sys_i386_32.c
index 7066cb855a60..1884a8d12bfa 100644
--- a/arch/x86/kernel/sys_i386_32.c
+++ b/arch/x86/kernel/sys_i386_32.c
@@ -22,6 +22,8 @@
 #include <linux/uaccess.h>
 #include <linux/unistd.h>
 
+#include <asm/syscalls.h>
+
 asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
                           unsigned long prot, unsigned long flags,
                           unsigned long fd, unsigned long pgoff)
diff --git a/arch/x86/kernel/sys_x86_64.c b/arch/x86/kernel/sys_x86_64.c
index 3b360ef33817..6bc211accf08 100644
--- a/arch/x86/kernel/sys_x86_64.c
+++ b/arch/x86/kernel/sys_x86_64.c
@@ -13,15 +13,17 @@
 #include <linux/utsname.h>
 #include <linux/personality.h>
 #include <linux/random.h>
+#include <linux/uaccess.h>
 
-#include <asm/uaccess.h>
 #include <asm/ia32.h>
+#include <asm/syscalls.h>
 
-asmlinkage long sys_mmap(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long off)
+asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
+                unsigned long prot, unsigned long flags,
+                unsigned long fd, unsigned long off)
 {
         long error;
-        struct file * file;
+        struct file *file;
 
         error = -EINVAL;
         if (off & ~PAGE_MASK)
@@ -56,9 +58,9 @@ static void find_start_end(unsigned long flags, unsigned long *begin,
                    unmapped base down for this case. This can give
                    conflicts with the heap, but we assume that glibc
                    malloc knows how to fall back to mmap. Give it 1GB
-                   of playground for now. -AK */ 
-                *begin = 0x40000000; 
-                *end = 0x80000000;              
+                   of playground for now. -AK */
+                *begin = 0x40000000;
+                *end = 0x80000000;
                 if (current->flags & PF_RANDOMIZE) {
                         new_begin = randomize_range(*begin, *begin + 0x02000000, 0);
                         if (new_begin)
@@ -66,9 +68,9 @@ static void find_start_end(unsigned long flags, unsigned long *begin,
                 }
         } else {
                 *begin = TASK_UNMAPPED_BASE;
-                *end = TASK_SIZE; 
+                *end = TASK_SIZE;
         }
-} 
+}
 
 unsigned long
 arch_get_unmapped_area(struct file *filp, unsigned long addr,
@@ -78,11 +80,11 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
         struct vm_area_struct *vma;
         unsigned long start_addr;
         unsigned long begin, end;
-        
+
         if (flags & MAP_FIXED)
                 return addr;
 
-        find_start_end(flags, &begin, &end); 
+        find_start_end(flags, &begin, &end);
 
         if (len > end)
                 return -ENOMEM;
@@ -96,12 +98,12 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
         }
         if (((flags & MAP_32BIT) || test_thread_flag(TIF_IA32))
             && len <= mm->cached_hole_size) {
-                mm->cached_hole_size = 0;
+                mm->cached_hole_size = 0;
                 mm->free_area_cache = begin;
         }
         addr = mm->free_area_cache;
-        if (addr < begin) 
-                addr = begin; 
+        if (addr < begin)
+                addr = begin;
         start_addr = addr;
 
 full_search:
@@ -127,7 +129,7 @@ full_search:
                         return addr;
                 }
                 if (addr + mm->cached_hole_size < vma->vm_start)
-                        mm->cached_hole_size = vma->vm_start - addr;
+                        mm->cached_hole_size = vma->vm_start - addr;
 
                 addr = vma->vm_end;
         }
@@ -177,7 +179,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
                 vma = find_vma(mm, addr-len);
                 if (!vma || addr <= vma->vm_start)
                         /* remember the address as a hint for next time */
-                        return (mm->free_area_cache = addr-len);
+                        return mm->free_area_cache = addr-len;
         }
 
         if (mm->mmap_base < len)
@@ -194,7 +196,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
                 vma = find_vma(mm, addr);
                 if (!vma || addr+len <= vma->vm_start)
                         /* remember the address as a hint for next time */
-                        return (mm->free_area_cache = addr);
+                        return mm->free_area_cache = addr;
 
                 /* remember the largest hole we saw so far */
                 if (addr + mm->cached_hole_size < vma->vm_start)
@@ -224,13 +226,13 @@ bottomup:
 }
 
 
-asmlinkage long sys_uname(struct new_utsname __user * name)
+asmlinkage long sys_uname(struct new_utsname __user *name)
 {
         int err;
         down_read(&uts_sem);
-        err = copy_to_user(name, utsname(), sizeof (*name));
+        err = copy_to_user(name, utsname(), sizeof(*name));
         up_read(&uts_sem);
-        if (personality(current->personality) == PER_LINUX32) 
-                err |= copy_to_user(&name->machine, "i686", 5);                 
+        if (personality(current->personality) == PER_LINUX32)
+                err |= copy_to_user(&name->machine, "i686", 5);
         return err ? -EFAULT : 0;
 }
diff --git a/arch/x86/kernel/syscall_64.c b/arch/x86/kernel/syscall_64.c
index 170d43c17487..3d1be4f0fac5 100644
--- a/arch/x86/kernel/syscall_64.c
+++ b/arch/x86/kernel/syscall_64.c
@@ -8,12 +8,12 @@
 #define __NO_STUBS
 
 #define __SYSCALL(nr, sym) extern asmlinkage void sym(void) ;
-#undef _ASM_X86_64_UNISTD_H_
+#undef ASM_X86__UNISTD_64_H
 #include <asm/unistd_64.h>
 
 #undef __SYSCALL
 #define __SYSCALL(nr, sym) [nr] = sym,
-#undef _ASM_X86_64_UNISTD_H_
+#undef ASM_X86__UNISTD_64_H
 
 typedef void (*sys_call_ptr_t)(void);
 
diff --git a/arch/x86/kernel/time_32.c b/arch/x86/kernel/time_32.c
index ffe3c664afc0..bbecf8b6bf96 100644
--- a/arch/x86/kernel/time_32.c
+++ b/arch/x86/kernel/time_32.c
@@ -36,6 +36,7 @@
 #include <asm/arch_hooks.h>
 #include <asm/hpet.h>
 #include <asm/time.h>
+#include <asm/timer.h>
 
 #include "do_timer.h"
 
diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c
index ab6bf375a307..6bb7b8579e70 100644
--- a/arch/x86/kernel/tls.c
+++ b/arch/x86/kernel/tls.c
@@ -10,6 +10,7 @@
 #include <asm/ldt.h>
 #include <asm/processor.h>
 #include <asm/proto.h>
+#include <asm/syscalls.h>
 
 #include "tls.h"
 
diff --git a/arch/x86/kernel/traps_32.c b/arch/x86/kernel/traps_32.c
index 03df8e45e5a1..da5a5964fccb 100644
--- a/arch/x86/kernel/traps_32.c
+++ b/arch/x86/kernel/traps_32.c
@@ -1228,7 +1228,6 @@ void __init trap_init(void)
 
         set_bit(SYSCALL_VECTOR, used_vectors);
 
-        init_thread_xstate();
         /*
          * Should be a barrier for any external CPU state:
          */
diff --git a/arch/x86/kernel/traps_64.c b/arch/x86/kernel/traps_64.c
index 513caaca7115..2887a789e38f 100644
--- a/arch/x86/kernel/traps_64.c
+++ b/arch/x86/kernel/traps_64.c
@@ -32,6 +32,8 @@
 #include <linux/bug.h>
 #include <linux/nmi.h>
 #include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/io.h>
 
 #if defined(CONFIG_EDAC)
 #include <linux/edac.h>
@@ -45,9 +47,6 @@
 #include <asm/unwind.h>
 #include <asm/desc.h>
 #include <asm/i387.h>
-#include <asm/nmi.h>
-#include <asm/smp.h>
-#include <asm/io.h>
 #include <asm/pgalloc.h>
 #include <asm/proto.h>
 #include <asm/pda.h>
@@ -85,7 +84,8 @@ static inline void preempt_conditional_cli(struct pt_regs *regs)
 
 void printk_address(unsigned long address, int reliable)
 {
-        printk(" [<%016lx>] %s%pS\n", address, reliable ? "": "? ", (void *) address);
+        printk(" [<%016lx>] %s%pS\n",
+                        address, reliable ?     "" : "? ", (void *) address);
 }
 
 static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
@@ -98,7 +98,8 @@ static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
                 [STACKFAULT_STACK - 1] = "#SS",
                 [MCE_STACK - 1] = "#MC",
 #if DEBUG_STKSZ > EXCEPTION_STKSZ
-                [N_EXCEPTION_STACKS ... N_EXCEPTION_STACKS + DEBUG_STKSZ / EXCEPTION_STKSZ - 2] = "#DB[?]"
+                [N_EXCEPTION_STACKS ...
+                        N_EXCEPTION_STACKS + DEBUG_STKSZ / EXCEPTION_STKSZ - 2] = "#DB[?]"
 #endif
         };
         unsigned k;
@@ -163,7 +164,7 @@ static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
 }
 
 /*
- * x86-64 can have up to three kernel stacks: 
+ * x86-64 can have up to three kernel stacks:
  * process stack
  * interrupt stack
  * severe exception (double fault, nmi, stack fault, debug, mce) hardware stack
@@ -219,7 +220,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                 const struct stacktrace_ops *ops, void *data)
 {
         const unsigned cpu = get_cpu();
-        unsigned long *irqstack_end = (unsigned long*)cpu_pda(cpu)->irqstackptr;
+        unsigned long *irqstack_end = (unsigned long *)cpu_pda(cpu)->irqstackptr;
         unsigned used = 0;
         struct thread_info *tinfo;
 
@@ -237,7 +238,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
         if (!bp) {
                 if (task == current) {
                         /* Grab bp right from our regs */
-                        asm("movq %%rbp, %0" : "=r" (bp) :);
+                        asm("movq %%rbp, %0" : "=r" (bp) : );
                 } else {
                         /* bp is the last reg pushed by switch_to */
                         bp = *(unsigned long *) task->thread.sp;
@@ -339,9 +340,8 @@ static void
 show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
                 unsigned long *stack, unsigned long bp, char *log_lvl)
 {
-        printk("\nCall Trace:\n");
+        printk("Call Trace:\n");
         dump_trace(task, regs, stack, bp, &print_trace_ops, log_lvl);
-        printk("\n");
 }
 
 void show_trace(struct task_struct *task, struct pt_regs *regs,
@@ -357,11 +357,15 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
         unsigned long *stack;
         int i;
         const int cpu = smp_processor_id();
-        unsigned long *irqstack_end = (unsigned long *) (cpu_pda(cpu)->irqstackptr);
-        unsigned long *irqstack = (unsigned long *) (cpu_pda(cpu)->irqstackptr - IRQSTACKSIZE);
+        unsigned long *irqstack_end =
+                (unsigned long *) (cpu_pda(cpu)->irqstackptr);
+        unsigned long *irqstack =
+                (unsigned long *) (cpu_pda(cpu)->irqstackptr - IRQSTACKSIZE);
 
-        // debugging aid: "show_stack(NULL, NULL);" prints the
-        // back trace for this cpu.
+        /*
+         * debugging aid: "show_stack(NULL, NULL);" prints the
+         * back trace for this cpu.
+         */
 
         if (sp == NULL) {
                 if (task)
@@ -386,6 +390,7 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
                 printk(" %016lx", *stack++);
                 touch_nmi_watchdog();
         }
+        printk("\n");
         show_trace_log_lvl(task, regs, sp, bp, log_lvl);
 }
 
@@ -404,7 +409,7 @@ void dump_stack(void)
 
 #ifdef CONFIG_FRAME_POINTER
         if (!bp)
-                asm("movq %%rbp, %0" : "=r" (bp):);
+                asm("movq %%rbp, %0" : "=r" (bp) : );
 #endif
 
         printk("Pid: %d, comm: %.20s %s %s %.*s\n",
@@ -414,7 +419,6 @@ void dump_stack(void)
                 init_utsname()->version);
         show_trace(NULL, NULL, &stack, bp);
 }
-
 EXPORT_SYMBOL(dump_stack);
 
 void show_registers(struct pt_regs *regs)
@@ -443,7 +447,6 @@ void show_registers(struct pt_regs *regs)
                 printk("Stack: ");
                 show_stack_log_lvl(NULL, regs, (unsigned long *)sp,
                                 regs->bp, "");
-                printk("\n");
 
                 printk(KERN_EMERG "Code: ");
 
@@ -493,7 +496,7 @@ unsigned __kprobes long oops_begin(void)
         raw_local_irq_save(flags);
         cpu = smp_processor_id();
         if (!__raw_spin_trylock(&die_lock)) {
-                if (cpu == die_owner) 
+                if (cpu == die_owner)
                         /* nested oops. should stop eventually */;
                 else
                         __raw_spin_lock(&die_lock);
@@ -638,7 +641,7 @@ kernel_trap:
 }
 
 #define DO_ERROR(trapnr, signr, str, name) \
-asmlinkage void do_##name(struct pt_regs * regs, long error_code)       \
+asmlinkage void do_##name(struct pt_regs *regs, long error_code)        \
 {                                                                       \
         if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr)  \
                                                         == NOTIFY_STOP) \
@@ -648,7 +651,7 @@ asmlinkage void do_##name(struct pt_regs * regs, long error_code)	\
 }
 
 #define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr)         \
-asmlinkage void do_##name(struct pt_regs * regs, long error_code)       \
+asmlinkage void do_##name(struct pt_regs *regs, long error_code)        \
 {                                                                       \
         siginfo_t info;                                                 \
         info.si_signo = signr;                                          \
@@ -683,7 +686,7 @@ asmlinkage void do_stack_segment(struct pt_regs *regs, long error_code)
         preempt_conditional_cli(regs);
 }
 
-asmlinkage void do_double_fault(struct pt_regs * regs, long error_code)
+asmlinkage void do_double_fault(struct pt_regs *regs, long error_code)
 {
         static const char str[] = "double fault";
         struct task_struct *tsk = current;
@@ -778,9 +781,10 @@ io_check_error(unsigned char reason, struct pt_regs *regs)
 }
 
 static notrace __kprobes void
-unknown_nmi_error(unsigned char reason, struct pt_regs * regs)
+unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
 {
-        if (notify_die(DIE_NMIUNKNOWN, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
+        if (notify_die(DIE_NMIUNKNOWN, "nmi", regs, reason, 2, SIGINT) ==
+                        NOTIFY_STOP)
                 return;
         printk(KERN_EMERG "Uhhuh. NMI received for unknown reason %02x.\n",
                 reason);
@@ -882,7 +886,7 @@ asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs)
         else if (user_mode(eregs))
                 regs = task_pt_regs(current);
         /* Exception from kernel and interrupts are enabled. Move to
-           kernel process stack. */
+           kernel process stack. */
         else if (eregs->flags & X86_EFLAGS_IF)
                 regs = (struct pt_regs *)(eregs->sp -= sizeof(struct pt_regs));
         if (eregs != regs)
@@ -891,7 +895,7 @@ asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs)
 }
 
 /* runs on IST stack. */
-asmlinkage void __kprobes do_debug(struct pt_regs * regs,
+asmlinkage void __kprobes do_debug(struct pt_regs *regs,
                                    unsigned long error_code)
 {
         struct task_struct *tsk = current;
@@ -1035,7 +1039,7 @@ asmlinkage void do_coprocessor_error(struct pt_regs *regs)
 
 asmlinkage void bad_intr(void)
 {
-        printk("bad interrupt"); 
+        printk("bad interrupt");
 }
 
 asmlinkage void do_simd_coprocessor_error(struct pt_regs *regs)
@@ -1047,7 +1051,7 @@ asmlinkage void do_simd_coprocessor_error(struct pt_regs *regs)
 
         conditional_sti(regs);
         if (!user_mode(regs) &&
-                kernel_math_error(regs, "kernel simd math error", 19))
+                        kernel_math_error(regs, "kernel simd math error", 19))
                 return;
 
         /*
@@ -1092,7 +1096,7 @@ asmlinkage void do_simd_coprocessor_error(struct pt_regs *regs)
         force_sig_info(SIGFPE, &info, task);
 }
 
-asmlinkage void do_spurious_interrupt_bug(struct pt_regs * regs)
+asmlinkage void do_spurious_interrupt_bug(struct pt_regs *regs)
 {
 }
 
@@ -1134,7 +1138,7 @@ asmlinkage void math_state_restore(void)
         /*
          * Paranoid restore. send a SIGSEGV if we fail to restore the state.
          */
-        if (unlikely(restore_fpu_checking(&me->thread.xstate->fxsave))) {
+        if (unlikely(restore_fpu_checking(me))) {
                 stts();
                 force_sig(SIGSEGV, me);
                 return;
@@ -1149,8 +1153,10 @@ void __init trap_init(void)
         set_intr_gate(0, &divide_error);
         set_intr_gate_ist(1, &debug, DEBUG_STACK);
         set_intr_gate_ist(2, &nmi, NMI_STACK);
-        set_system_gate_ist(3, &int3, DEBUG_STACK); /* int3 can be called from all */
-        set_system_gate(4, &overflow); /* int4 can be called from all */
+        /* int3 can be called from all */
+        set_system_gate_ist(3, &int3, DEBUG_STACK);
+        /* int4 can be called from all */
+        set_system_gate(4, &overflow);
         set_intr_gate(5, &bounds);
         set_intr_gate(6, &invalid_op);
         set_intr_gate(7, &device_not_available);
@@ -1173,10 +1179,6 @@ void __init trap_init(void)
         set_system_gate(IA32_SYSCALL_VECTOR, ia32_syscall);
 #endif
         /*
-         * initialize the per thread extended state:
-         */
-        init_thread_xstate();
-        /*
          * Should be a barrier for any external CPU state:
          */
         cpu_init();
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 8f98e9de1b82..161bb850fc47 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -104,7 +104,7 @@ __setup("notsc", notsc_setup);
 /*
  * Read TSC and the reference counters. Take care of SMI disturbance
  */
-static u64 tsc_read_refs(u64 *pm, u64 *hpet)
+static u64 tsc_read_refs(u64 *p, int hpet)
 {
         u64 t1, t2;
         int i;
@@ -112,9 +112,9 @@ static u64 tsc_read_refs(u64 *pm, u64 *hpet)
         for (i = 0; i < MAX_RETRIES; i++) {
                 t1 = get_cycles();
                 if (hpet)
-                        *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
+                        *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
                 else
-                        *pm = acpi_pm_read_early();
+                        *p = acpi_pm_read_early();
                 t2 = get_cycles();
                 if ((t2 - t1) < SMI_TRESHOLD)
                         return t2;
@@ -123,13 +123,59 @@ static u64 tsc_read_refs(u64 *pm, u64 *hpet)
 }
 
 /*
+ * Calculate the TSC frequency from HPET reference
+ */
+static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
+{
+        u64 tmp;
+
+        if (hpet2 < hpet1)
+                hpet2 += 0x100000000ULL;
+        hpet2 -= hpet1;
+        tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
+        do_div(tmp, 1000000);
+        do_div(deltatsc, tmp);
+
+        return (unsigned long) deltatsc;
+}
+
+/*
+ * Calculate the TSC frequency from PMTimer reference
+ */
+static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
+{
+        u64 tmp;
+
+        if (!pm1 && !pm2)
+                return ULONG_MAX;
+
+        if (pm2 < pm1)
+                pm2 += (u64)ACPI_PM_OVRRUN;
+        pm2 -= pm1;
+        tmp = pm2 * 1000000000LL;
+        do_div(tmp, PMTMR_TICKS_PER_SEC);
+        do_div(deltatsc, tmp);
+
+        return (unsigned long) deltatsc;
+}
+
+#define CAL_MS          10
+#define CAL_LATCH       (CLOCK_TICK_RATE / (1000 / CAL_MS))
+#define CAL_PIT_LOOPS   1000
+
+#define CAL2_MS         50
+#define CAL2_LATCH      (CLOCK_TICK_RATE / (1000 / CAL2_MS))
+#define CAL2_PIT_LOOPS  5000
+
+
+/*
  * Try to calibrate the TSC against the Programmable
  * Interrupt Timer and return the frequency of the TSC
  * in kHz.
  *
  * Return ULONG_MAX on failure to calibrate.
  */
-static unsigned long pit_calibrate_tsc(void)
+static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
 {
         u64 tsc, t1, t2, delta;
         unsigned long tscmin, tscmax;
@@ -144,8 +190,8 @@ static unsigned long pit_calibrate_tsc(void)
          * (LSB then MSB) to begin countdown.
          */
         outb(0xb0, 0x43);
-        outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
-        outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
+        outb(latch & 0xff, 0x42);
+        outb(latch >> 8, 0x42);
 
         tsc = t1 = t2 = get_cycles();
 
@@ -166,31 +212,154 @@ static unsigned long pit_calibrate_tsc(void)
         /*
          * Sanity checks:
          *
-         * If we were not able to read the PIT more than 5000
+         * If we were not able to read the PIT more than loopmin
          * times, then we have been hit by a massive SMI
          *
          * If the maximum is 10 times larger than the minimum,
          * then we got hit by an SMI as well.
          */
-        if (pitcnt < 5000 || tscmax > 10 * tscmin)
+        if (pitcnt < loopmin || tscmax > 10 * tscmin)
                 return ULONG_MAX;
 
         /* Calculate the PIT value */
         delta = t2 - t1;
-        do_div(delta, 50);
+        do_div(delta, ms);
         return delta;
 }
 
+/*
+ * This reads the current MSB of the PIT counter, and
+ * checks if we are running on sufficiently fast and
+ * non-virtualized hardware.
+ *
+ * Our expectations are:
+ *
+ *  - the PIT is running at roughly 1.19MHz
+ *
+ *  - each IO is going to take about 1us on real hardware,
+ *    but we allow it to be much faster (by a factor of 10) or
+ *    _slightly_ slower (ie we allow up to a 2us read+counter
+ *    update - anything else implies a unacceptably slow CPU
+ *    or PIT for the fast calibration to work.
+ *
+ *  - with 256 PIT ticks to read the value, we have 214us to
+ *    see the same MSB (and overhead like doing a single TSC
+ *    read per MSB value etc).
+ *
+ *  - We're doing 2 reads per loop (LSB, MSB), and we expect
+ *    them each to take about a microsecond on real hardware.
+ *    So we expect a count value of around 100. But we'll be
+ *    generous, and accept anything over 50.
+ *
+ *  - if the PIT is stuck, and we see *many* more reads, we
+ *    return early (and the next caller of pit_expect_msb()
+ *    then consider it a failure when they don't see the
+ *    next expected value).
+ *
+ * These expectations mean that we know that we have seen the
+ * transition from one expected value to another with a fairly
+ * high accuracy, and we didn't miss any events. We can thus
+ * use the TSC value at the transitions to calculate a pretty
+ * good value for the TSC frequencty.
+ */
+static inline int pit_expect_msb(unsigned char val)
+{
+        int count = 0;
+
+        for (count = 0; count < 50000; count++) {
+                /* Ignore LSB */
+                inb(0x42);
+                if (inb(0x42) != val)
+                        break;
+        }
+        return count > 50;
+}
+
+/*
+ * How many MSB values do we want to see? We aim for a
+ * 15ms calibration, which assuming a 2us counter read
+ * error should give us roughly 150 ppm precision for
+ * the calibration.
+ */
+#define QUICK_PIT_MS 15
+#define QUICK_PIT_ITERATIONS (QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
+
+static unsigned long quick_pit_calibrate(void)
+{
+        /* Set the Gate high, disable speaker */
+        outb((inb(0x61) & ~0x02) | 0x01, 0x61);
+
+        /*
+         * Counter 2, mode 0 (one-shot), binary count
+         *
+         * NOTE! Mode 2 decrements by two (and then the
+         * output is flipped each time, giving the same
+         * final output frequency as a decrement-by-one),
+         * so mode 0 is much better when looking at the
+         * individual counts.
+         */
+        outb(0xb0, 0x43);
+
+        /* Start at 0xffff */
+        outb(0xff, 0x42);
+        outb(0xff, 0x42);
+
+        if (pit_expect_msb(0xff)) {
+                int i;
+                u64 t1, t2, delta;
+                unsigned char expect = 0xfe;
+
+                t1 = get_cycles();
+                for (i = 0; i < QUICK_PIT_ITERATIONS; i++, expect--) {
+                        if (!pit_expect_msb(expect))
+                                goto failed;
+                }
+                t2 = get_cycles();
+
+                /*
+                 * Make sure we can rely on the second TSC timestamp:
+                 */
+                if (!pit_expect_msb(expect))
+                        goto failed;
+
+                /*
+                 * Ok, if we get here, then we've seen the
+                 * MSB of the PIT decrement QUICK_PIT_ITERATIONS
+                 * times, and each MSB had many hits, so we never
+                 * had any sudden jumps.
+                 *
+                 * As a result, we can depend on there not being
+                 * any odd delays anywhere, and the TSC reads are
+                 * reliable.
+                 *
+                 * kHz = ticks / time-in-seconds / 1000;
+                 * kHz = (t2 - t1) / (QPI * 256 / PIT_TICK_RATE) / 1000
+                 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (QPI * 256 * 1000)
+                 */
+                delta = (t2 - t1)*PIT_TICK_RATE;
+                do_div(delta, QUICK_PIT_ITERATIONS*256*1000);
+                printk("Fast TSC calibration using PIT\n");
+                return delta;
+        }
+failed:
+        return 0;
+}
 
 /**
  * native_calibrate_tsc - calibrate the tsc on boot
  */
 unsigned long native_calibrate_tsc(void)
 {
-        u64 tsc1, tsc2, delta, pm1, pm2, hpet1, hpet2;
+        u64 tsc1, tsc2, delta, ref1, ref2;
         unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
-        unsigned long flags;
-        int hpet = is_hpet_enabled(), i;
+        unsigned long flags, latch, ms, fast_calibrate;
+        int hpet = is_hpet_enabled(), i, loopmin;
+
+        local_irq_save(flags);
+        fast_calibrate = quick_pit_calibrate();
+        local_irq_restore(flags);
+        if (fast_calibrate)
+                return fast_calibrate;
 
         /*
          * Run 5 calibration loops to get the lowest frequency value
@@ -216,7 +385,13 @@ unsigned long native_calibrate_tsc(void)
          * calibration delay loop as we have to wait for a certain
          * amount of time anyway.
          */
-        for (i = 0; i < 5; i++) {
+
+        /* Preset PIT loop values */
+        latch = CAL_LATCH;
+        ms = CAL_MS;
+        loopmin = CAL_PIT_LOOPS;
+
+        for (i = 0; i < 3; i++) {
                 unsigned long tsc_pit_khz;
 
                 /*
@@ -226,16 +401,16 @@ unsigned long native_calibrate_tsc(void)
                  * read the end value.
                  */
                 local_irq_save(flags);
-                tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
-                tsc_pit_khz = pit_calibrate_tsc();
-                tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
+                tsc1 = tsc_read_refs(&ref1, hpet);
+                tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
+                tsc2 = tsc_read_refs(&ref2, hpet);
                 local_irq_restore(flags);
 
                 /* Pick the lowest PIT TSC calibration so far */
                 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
 
                 /* hpet or pmtimer available ? */
-                if (!hpet && !pm1 && !pm2)
+                if (!hpet && !ref1 && !ref2)
                         continue;
 
                 /* Check, whether the sampling was disturbed by an SMI */
@@ -243,23 +418,41 @@ unsigned long native_calibrate_tsc(void)
                         continue;
 
                 tsc2 = (tsc2 - tsc1) * 1000000LL;
+                if (hpet)
+                        tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
+                else
+                        tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
 
-                if (hpet) {
-                        if (hpet2 < hpet1)
-                                hpet2 += 0x100000000ULL;
-                        hpet2 -= hpet1;
-                        tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
-                        do_div(tsc1, 1000000);
-                } else {
-                        if (pm2 < pm1)
-                                pm2 += (u64)ACPI_PM_OVRRUN;
-                        pm2 -= pm1;
-                        tsc1 = pm2 * 1000000000LL;
-                        do_div(tsc1, PMTMR_TICKS_PER_SEC);
+                tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
+
+                /* Check the reference deviation */
+                delta = ((u64) tsc_pit_min) * 100;
+                do_div(delta, tsc_ref_min);
+
+                /*
+                 * If both calibration results are inside a 10% window
+                 * then we can be sure, that the calibration
+                 * succeeded. We break out of the loop right away. We
+                 * use the reference value, as it is more precise.
+                 */
+                if (delta >= 90 && delta <= 110) {
+                        printk(KERN_INFO
+                               "TSC: PIT calibration matches %s. %d loops\n",
+                               hpet ? "HPET" : "PMTIMER", i + 1);
+                        return tsc_ref_min;
                 }
 
-                do_div(tsc2, tsc1);
-                tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
+                /*
+                 * Check whether PIT failed more than once. This
+                 * happens in virtualized environments. We need to
+                 * give the virtual PC a slightly longer timeframe for
+                 * the HPET/PMTIMER to make the result precise.
+                 */
+                if (i == 1 && tsc_pit_min == ULONG_MAX) {
+                        latch = CAL2_LATCH;
+                        ms = CAL2_MS;
+                        loopmin = CAL2_PIT_LOOPS;
+                }
         }
 
         /*
@@ -270,7 +463,7 @@ unsigned long native_calibrate_tsc(void)
                 printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
 
                 /* We don't have an alternative source, disable TSC */
-                if (!hpet && !pm1 && !pm2) {
+                if (!hpet && !ref1 && !ref2) {
                         printk("TSC: No reference (HPET/PMTIMER) available\n");
                         return 0;
                 }
@@ -278,7 +471,7 @@ unsigned long native_calibrate_tsc(void)
                 /* The alternative source failed as well, disable TSC */
                 if (tsc_ref_min == ULONG_MAX) {
                         printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
-                               "failed due to SMI disturbance.\n");
+                               "failed.\n");
                         return 0;
                 }
 
@@ -290,44 +483,25 @@ unsigned long native_calibrate_tsc(void)
         }
 
         /* We don't have an alternative source, use the PIT calibration value */
-        if (!hpet && !pm1 && !pm2) {
+        if (!hpet && !ref1 && !ref2) {
                 printk(KERN_INFO "TSC: Using PIT calibration value\n");
                 return tsc_pit_min;
         }
 
         /* The alternative source failed, use the PIT calibration value */
         if (tsc_ref_min == ULONG_MAX) {
-                printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed due "
-                       "to SMI disturbance. Using PIT calibration\n");
+                printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
+                       "Using PIT calibration\n");
                 return tsc_pit_min;
         }
 
-        /* Check the reference deviation */
-        delta = ((u64) tsc_pit_min) * 100;
-        do_div(delta, tsc_ref_min);
-
-        /*
-         * If both calibration results are inside a 5% window, the we
-         * use the lower frequency of those as it is probably the
-         * closest estimate.
-         */
-        if (delta >= 95 && delta <= 105) {
-                printk(KERN_INFO "TSC: PIT calibration confirmed by %s.\n",
-                       hpet ? "HPET" : "PMTIMER");
-                printk(KERN_INFO "TSC: using %s calibration value\n",
-                       tsc_pit_min <= tsc_ref_min ? "PIT" :
-                       hpet ? "HPET" : "PMTIMER");
-                return tsc_pit_min <= tsc_ref_min ? tsc_pit_min : tsc_ref_min;
-        }
-
-        printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
-               hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
-
         /*
          * The calibration values differ too much. In doubt, we use
          * the PIT value as we know that there are PMTIMERs around
-         * running at double speed.
+         * running at double speed. At least we let the user know:
          */
+        printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
+               hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
         printk(KERN_INFO "TSC: Using PIT calibration value\n");
         return tsc_pit_min;
 }
diff --git a/arch/x86/kernel/visws_quirks.c b/arch/x86/kernel/visws_quirks.c
index 594ef47f0a63..61a97e616f70 100644
--- a/arch/x86/kernel/visws_quirks.c
+++ b/arch/x86/kernel/visws_quirks.c
@@ -25,45 +25,31 @@
 #include <asm/visws/cobalt.h>
 #include <asm/visws/piix4.h>
 #include <asm/arch_hooks.h>
+#include <asm/io_apic.h>
 #include <asm/fixmap.h>
 #include <asm/reboot.h>
 #include <asm/setup.h>
 #include <asm/e820.h>
-#include <asm/smp.h>
 #include <asm/io.h>
 
 #include <mach_ipi.h>
 
 #include "mach_apic.h"
 
-#include <linux/init.h>
-#include <linux/smp.h>
-
 #include <linux/kernel_stat.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
 
-#include <asm/io.h>
-#include <asm/apic.h>
 #include <asm/i8259.h>
 #include <asm/irq_vectors.h>
-#include <asm/visws/cobalt.h>
 #include <asm/visws/lithium.h>
-#include <asm/visws/piix4.h>
 
 #include <linux/sched.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/pci_ids.h>
 
 extern int no_broadcast;
 
-#include <asm/io.h>
 #include <asm/apic.h>
-#include <asm/arch_hooks.h>
-#include <asm/visws/cobalt.h>
-#include <asm/visws/lithium.h>
 
 char visws_board_type   = -1;
 char visws_board_rev    = -1;
diff --git a/arch/x86/kernel/vm86_32.c b/arch/x86/kernel/vm86_32.c
index 38f566fa27d2..4eeb5cf9720d 100644
--- a/arch/x86/kernel/vm86_32.c
+++ b/arch/x86/kernel/vm86_32.c
@@ -46,6 +46,7 @@
 #include <asm/io.h>
 #include <asm/tlbflush.h>
 #include <asm/irq.h>
+#include <asm/syscalls.h>
 
 /*
  * Known problems:
diff --git a/arch/x86/kernel/vmi_32.c b/arch/x86/kernel/vmi_32.c
index 6ca515d6db54..8b6c393ab9fd 100644
--- a/arch/x86/kernel/vmi_32.c
+++ b/arch/x86/kernel/vmi_32.c
@@ -235,7 +235,7 @@ static void vmi_write_ldt_entry(struct desc_struct *dt, int entry,
                                 const void *desc)
 {
         u32 *ldt_entry = (u32 *)desc;
-        vmi_ops.write_idt_entry(dt, entry, ldt_entry[0], ldt_entry[1]);
+        vmi_ops.write_ldt_entry(dt, entry, ldt_entry[0], ldt_entry[1]);
 }
 
 static void vmi_load_sp0(struct tss_struct *tss,
@@ -393,13 +393,13 @@ static void *vmi_kmap_atomic_pte(struct page *page, enum km_type type)
 }
 #endif
 
-static void vmi_allocate_pte(struct mm_struct *mm, u32 pfn)
+static void vmi_allocate_pte(struct mm_struct *mm, unsigned long pfn)
 {
         vmi_set_page_type(pfn, VMI_PAGE_L1);
         vmi_ops.allocate_page(pfn, VMI_PAGE_L1, 0, 0, 0);
 }
 
-static void vmi_allocate_pmd(struct mm_struct *mm, u32 pfn)
+static void vmi_allocate_pmd(struct mm_struct *mm, unsigned long pfn)
 {
         /*
          * This call comes in very early, before mem_map is setup.
@@ -410,20 +410,20 @@ static void vmi_allocate_pmd(struct mm_struct *mm, u32 pfn)
         vmi_ops.allocate_page(pfn, VMI_PAGE_L2, 0, 0, 0);
 }
 
-static void vmi_allocate_pmd_clone(u32 pfn, u32 clonepfn, u32 start, u32 count)
+static void vmi_allocate_pmd_clone(unsigned long pfn, unsigned long clonepfn, unsigned long start, unsigned long count)
 {
         vmi_set_page_type(pfn, VMI_PAGE_L2 | VMI_PAGE_CLONE);
         vmi_check_page_type(clonepfn, VMI_PAGE_L2);
         vmi_ops.allocate_page(pfn, VMI_PAGE_L2 | VMI_PAGE_CLONE, clonepfn, start, count);
 }
 
-static void vmi_release_pte(u32 pfn)
+static void vmi_release_pte(unsigned long pfn)
 {
         vmi_ops.release_page(pfn, VMI_PAGE_L1);
         vmi_set_page_type(pfn, VMI_PAGE_NORMAL);
 }
 
-static void vmi_release_pmd(u32 pfn)
+static void vmi_release_pmd(unsigned long pfn)
 {
         vmi_ops.release_page(pfn, VMI_PAGE_L2);
         vmi_set_page_type(pfn, VMI_PAGE_NORMAL);
@@ -905,8 +905,8 @@ static inline int __init activate_vmi(void)
 #endif
 
 #ifdef CONFIG_X86_LOCAL_APIC
-        para_fill(pv_apic_ops.apic_read, APICRead);
-        para_fill(pv_apic_ops.apic_write, APICWrite);
+       para_fill(apic_ops->read, APICRead);
+       para_fill(apic_ops->write, APICWrite);
 #endif
 
         /*
diff --git a/arch/x86/kernel/vmlinux_32.lds.S b/arch/x86/kernel/vmlinux_32.lds.S
index af5bdad84604..a9b8560adbc2 100644
--- a/arch/x86/kernel/vmlinux_32.lds.S
+++ b/arch/x86/kernel/vmlinux_32.lds.S
@@ -140,10 +140,10 @@ SECTIONS
         *(.con_initcall.init)
         __con_initcall_end = .;
   }
-  .x86cpuvendor.init : AT(ADDR(.x86cpuvendor.init) - LOAD_OFFSET) {
-        __x86cpuvendor_start = .;
-        *(.x86cpuvendor.init)
-        __x86cpuvendor_end = .;
+  .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) {
+        __x86_cpu_dev_start = .;
+        *(.x86_cpu_dev.init)
+        __x86_cpu_dev_end = .;
   }
   SECURITY_INIT
   . = ALIGN(4);
@@ -180,6 +180,7 @@ SECTIONS
   . = ALIGN(PAGE_SIZE);
   .data.percpu  : AT(ADDR(.data.percpu) - LOAD_OFFSET) {
         __per_cpu_start = .;
+        *(.data.percpu.page_aligned)
         *(.data.percpu)
         *(.data.percpu.shared_aligned)
         __per_cpu_end = .;
diff --git a/arch/x86/kernel/vmlinux_64.lds.S b/arch/x86/kernel/vmlinux_64.lds.S
index 63e5c1a22e88..201e81a91a95 100644
--- a/arch/x86/kernel/vmlinux_64.lds.S
+++ b/arch/x86/kernel/vmlinux_64.lds.S
@@ -168,13 +168,12 @@ SECTIONS
         *(.con_initcall.init)
   }
   __con_initcall_end = .;
-  . = ALIGN(16);
-  __x86cpuvendor_start = .;
-  .x86cpuvendor.init : AT(ADDR(.x86cpuvendor.init) - LOAD_OFFSET) {
-        *(.x86cpuvendor.init)
+  __x86_cpu_dev_start = .;
+  .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) {
+        *(.x86_cpu_dev.init)
   }
-  __x86cpuvendor_end = .;
   SECURITY_INIT
+  __x86_cpu_dev_end = .;
 
   . = ALIGN(8);
   .parainstructions : AT(ADDR(.parainstructions) - LOAD_OFFSET) {
diff --git a/arch/x86/kernel/vsmp_64.c b/arch/x86/kernel/vsmp_64.c
index 0c029e8959c7..7766d36983fc 100644
--- a/arch/x86/kernel/vsmp_64.c
+++ b/arch/x86/kernel/vsmp_64.c
@@ -61,7 +61,7 @@ static void vsmp_irq_enable(void)
         native_restore_fl((flags | X86_EFLAGS_IF) & (~X86_EFLAGS_AC));
 }
 
-static unsigned __init vsmp_patch(u8 type, u16 clobbers, void *ibuf,
+static unsigned __init_or_module vsmp_patch(u8 type, u16 clobbers, void *ibuf,
                                   unsigned long addr, unsigned len)
 {
         switch (type) {
diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c
new file mode 100644
index 000000000000..07713d64debe
--- /dev/null
+++ b/arch/x86/kernel/xsave.c
@@ -0,0 +1,316 @@
+/*
+ * xsave/xrstor support.
+ *
+ * Author: Suresh Siddha <suresh.b.siddha@intel.com>
+ */
+#include <linux/bootmem.h>
+#include <linux/compat.h>
+#include <asm/i387.h>
+#ifdef CONFIG_IA32_EMULATION
+#include <asm/sigcontext32.h>
+#endif
+#include <asm/xcr.h>
+
+/*
+ * Supported feature mask by the CPU and the kernel.
+ */
+u64 pcntxt_mask;
+
+struct _fpx_sw_bytes fx_sw_reserved;
+#ifdef CONFIG_IA32_EMULATION
+struct _fpx_sw_bytes fx_sw_reserved_ia32;
+#endif
+
+/*
+ * Check for the presence of extended state information in the
+ * user fpstate pointer in the sigcontext.
+ */
+int check_for_xstate(struct i387_fxsave_struct __user *buf,
+                     void __user *fpstate,
+                     struct _fpx_sw_bytes *fx_sw_user)
+{
+        int min_xstate_size = sizeof(struct i387_fxsave_struct) +
+                              sizeof(struct xsave_hdr_struct);
+        unsigned int magic2;
+        int err;
+
+        err = __copy_from_user(fx_sw_user, &buf->sw_reserved[0],
+                               sizeof(struct _fpx_sw_bytes));
+
+        if (err)
+                return err;
+
+        /*
+         * First Magic check failed.
+         */
+        if (fx_sw_user->magic1 != FP_XSTATE_MAGIC1)
+                return -1;
+
+        /*
+         * Check for error scenarios.
+         */
+        if (fx_sw_user->xstate_size < min_xstate_size ||
+            fx_sw_user->xstate_size > xstate_size ||
+            fx_sw_user->xstate_size > fx_sw_user->extended_size)
+                return -1;
+
+        err = __get_user(magic2, (__u32 *) (((void *)fpstate) +
+                                            fx_sw_user->extended_size -
+                                            FP_XSTATE_MAGIC2_SIZE));
+        /*
+         * Check for the presence of second magic word at the end of memory
+         * layout. This detects the case where the user just copied the legacy
+         * fpstate layout with out copying the extended state information
+         * in the memory layout.
+         */
+        if (err || magic2 != FP_XSTATE_MAGIC2)
+                return -1;
+
+        return 0;
+}
+
+#ifdef CONFIG_X86_64
+/*
+ * Signal frame handlers.
+ */
+
+int save_i387_xstate(void __user *buf)
+{
+        struct task_struct *tsk = current;
+        int err = 0;
+
+        if (!access_ok(VERIFY_WRITE, buf, sig_xstate_size))
+                return -EACCES;
+
+        BUG_ON(sig_xstate_size < xstate_size);
+
+        if ((unsigned long)buf % 64)
+                printk("save_i387_xstate: bad fpstate %p\n", buf);
+
+        if (!used_math())
+                return 0;
+        clear_used_math(); /* trigger finit */
+        if (task_thread_info(tsk)->status & TS_USEDFPU) {
+                /*
+                 * Start with clearing the user buffer. This will present a
+                 * clean context for the bytes not touched by the fxsave/xsave.
+                 */
+                __clear_user(buf, sig_xstate_size);
+
+                if (task_thread_info(tsk)->status & TS_XSAVE)
+                        err = xsave_user(buf);
+                else
+                        err = fxsave_user(buf);
+
+                if (err)
+                        return err;
+                task_thread_info(tsk)->status &= ~TS_USEDFPU;
+                stts();
+        } else {
+                if (__copy_to_user(buf, &tsk->thread.xstate->fxsave,
+                                   xstate_size))
+                        return -1;
+        }
+
+        if (task_thread_info(tsk)->status & TS_XSAVE) {
+                struct _fpstate __user *fx = buf;
+
+                err = __copy_to_user(&fx->sw_reserved, &fx_sw_reserved,
+                                     sizeof(struct _fpx_sw_bytes));
+
+                err |= __put_user(FP_XSTATE_MAGIC2,
+                                  (__u32 __user *) (buf + sig_xstate_size
+                                                    - FP_XSTATE_MAGIC2_SIZE));
+        }
+
+        return 1;
+}
+
+/*
+ * Restore the extended state if present. Otherwise, restore the FP/SSE
+ * state.
+ */
+int restore_user_xstate(void __user *buf)
+{
+        struct _fpx_sw_bytes fx_sw_user;
+        u64 mask;
+        int err;
+
+        if (((unsigned long)buf % 64) ||
+             check_for_xstate(buf, buf, &fx_sw_user))
+                goto fx_only;
+
+        mask = fx_sw_user.xstate_bv;
+
+        /*
+         * restore the state passed by the user.
+         */
+        err = xrestore_user(buf, mask);
+        if (err)
+                return err;
+
+        /*
+         * init the state skipped by the user.
+         */
+        mask = pcntxt_mask & ~mask;
+
+        xrstor_state(init_xstate_buf, mask);
+
+        return 0;
+
+fx_only:
+        /*
+         * couldn't find the extended state information in the
+         * memory layout. Restore just the FP/SSE and init all
+         * the other extended state.
+         */
+        xrstor_state(init_xstate_buf, pcntxt_mask & ~XSTATE_FPSSE);
+        return fxrstor_checking((__force struct i387_fxsave_struct *)buf);
+}
+
+/*
+ * This restores directly out of user space. Exceptions are handled.
+ */
+int restore_i387_xstate(void __user *buf)
+{
+        struct task_struct *tsk = current;
+        int err = 0;
+
+        if (!buf) {
+                if (used_math())
+                        goto clear;
+                return 0;
+        } else
+                if (!access_ok(VERIFY_READ, buf, sig_xstate_size))
+                        return -EACCES;
+
+        if (!used_math()) {
+                err = init_fpu(tsk);
+                if (err)
+                        return err;
+        }
+
+        if (!(task_thread_info(current)->status & TS_USEDFPU)) {
+                clts();
+                task_thread_info(current)->status |= TS_USEDFPU;
+        }
+        if (task_thread_info(tsk)->status & TS_XSAVE)
+                err = restore_user_xstate(buf);
+        else
+                err = fxrstor_checking((__force struct i387_fxsave_struct *)
+                                       buf);
+        if (unlikely(err)) {
+                /*
+                 * Encountered an error while doing the restore from the
+                 * user buffer, clear the fpu state.
+                 */
+clear:
+                clear_fpu(tsk);
+                clear_used_math();
+        }
+        return err;
+}
+#endif
+
+/*
+ * Prepare the SW reserved portion of the fxsave memory layout, indicating
+ * the presence of the extended state information in the memory layout
+ * pointed by the fpstate pointer in the sigcontext.
+ * This will be saved when ever the FP and extended state context is
+ * saved on the user stack during the signal handler delivery to the user.
+ */
+void prepare_fx_sw_frame(void)
+{
+        int size_extended = (xstate_size - sizeof(struct i387_fxsave_struct)) +
+                             FP_XSTATE_MAGIC2_SIZE;
+
+        sig_xstate_size = sizeof(struct _fpstate) + size_extended;
+
+#ifdef CONFIG_IA32_EMULATION
+        sig_xstate_ia32_size = sizeof(struct _fpstate_ia32) + size_extended;
+#endif
+
+        memset(&fx_sw_reserved, 0, sizeof(fx_sw_reserved));
+
+        fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1;
+        fx_sw_reserved.extended_size = sig_xstate_size;
+        fx_sw_reserved.xstate_bv = pcntxt_mask;
+        fx_sw_reserved.xstate_size = xstate_size;
+#ifdef CONFIG_IA32_EMULATION
+        memcpy(&fx_sw_reserved_ia32, &fx_sw_reserved,
+               sizeof(struct _fpx_sw_bytes));
+        fx_sw_reserved_ia32.extended_size = sig_xstate_ia32_size;
+#endif
+}
+
+/*
+ * Represents init state for the supported extended state.
+ */
+struct xsave_struct *init_xstate_buf;
+
+#ifdef CONFIG_X86_64
+unsigned int sig_xstate_size = sizeof(struct _fpstate);
+#endif
+
+/*
+ * Enable the extended processor state save/restore feature
+ */
+void __cpuinit xsave_init(void)
+{
+        if (!cpu_has_xsave)
+                return;
+
+        set_in_cr4(X86_CR4_OSXSAVE);
+
+        /*
+         * Enable all the features that the HW is capable of
+         * and the Linux kernel is aware of.
+         */
+        xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
+}
+
+/*
+ * setup the xstate image representing the init state
+ */
+void setup_xstate_init(void)
+{
+        init_xstate_buf = alloc_bootmem(xstate_size);
+        init_xstate_buf->i387.mxcsr = MXCSR_DEFAULT;
+}
+
+/*
+ * Enable and initialize the xsave feature.
+ */
+void __init xsave_cntxt_init(void)
+{
+        unsigned int eax, ebx, ecx, edx;
+
+        cpuid_count(0xd, 0, &eax, &ebx, &ecx, &edx);
+        pcntxt_mask = eax + ((u64)edx << 32);
+
+        if ((pcntxt_mask & XSTATE_FPSSE) != XSTATE_FPSSE) {
+                printk(KERN_ERR "FP/SSE not shown under xsave features 0x%llx\n",
+                       pcntxt_mask);
+                BUG();
+        }
+
+        /*
+         * for now OS knows only about FP/SSE
+         */
+        pcntxt_mask = pcntxt_mask & XCNTXT_MASK;
+        xsave_init();
+
+        /*
+         * Recompute the context size for enabled features
+         */
+        cpuid_count(0xd, 0, &eax, &ebx, &ecx, &edx);
+        xstate_size = ebx;
+
+        prepare_fx_sw_frame();
+
+        setup_xstate_init();
+
+        printk(KERN_INFO "xsave/xrstor: enabled xstate_bv 0x%llx, "
+               "cntxt size 0x%x\n",
+               pcntxt_mask, xstate_size);
+}
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 0bfe2bd305eb..3da2508eb22a 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -711,6 +711,10 @@ static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp)
         u64 *spte;
         int young = 0;
 
+        /* always return old for EPT */
+        if (!shadow_accessed_mask)
+                return 0;
+
         spte = rmap_next(kvm, rmapp, NULL);
         while (spte) {
                 int _young;
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index e2ee264740c7..8233b86c778c 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -62,6 +62,7 @@ static int npt = 1;
 module_param(npt, int, S_IRUGO);
 
 static void kvm_reput_irq(struct vcpu_svm *svm);
+static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 
 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 {
@@ -878,6 +879,10 @@ set:
 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 {
         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
+        unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
+
+        if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
+                force_new_asid(vcpu);
 
         vcpu->arch.cr4 = cr4;
         if (!npt_enabled)
@@ -1027,6 +1032,13 @@ static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
                             (u32)fault_address, (u32)(fault_address >> 32),
                             handler);
+        /*
+         * FIXME: Tis shouldn't be necessary here, but there is a flush
+         * missing in the MMU code. Until we find this bug, flush the
+         * complete TLB here on an NPF
+         */
+        if (npt_enabled)
+                svm_flush_tlb(&svm->vcpu);
 
         if (event_injection)
                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 2a69773e3b26..7041cc52b562 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -3301,8 +3301,7 @@ static int __init vmx_init(void)
                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
                         VMX_EPT_WRITABLE_MASK |
                         VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
-                kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK,
-                                VMX_EPT_FAKE_DIRTY_MASK, 0ull,
+                kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
                                 VMX_EPT_EXECUTABLE_MASK);
                 kvm_enable_tdp();
         } else
diff --git a/arch/x86/kvm/vmx.h b/arch/x86/kvm/vmx.h
index 425a13436b3f..17e25995b65b 100644
--- a/arch/x86/kvm/vmx.h
+++ b/arch/x86/kvm/vmx.h
@@ -331,21 +331,6 @@ enum vmcs_field {
 
 #define AR_RESERVD_MASK 0xfffe0f00
 
-#define MSR_IA32_VMX_BASIC                      0x480
-#define MSR_IA32_VMX_PINBASED_CTLS              0x481
-#define MSR_IA32_VMX_PROCBASED_CTLS             0x482
-#define MSR_IA32_VMX_EXIT_CTLS                  0x483
-#define MSR_IA32_VMX_ENTRY_CTLS                 0x484
-#define MSR_IA32_VMX_MISC                       0x485
-#define MSR_IA32_VMX_CR0_FIXED0                 0x486
-#define MSR_IA32_VMX_CR0_FIXED1                 0x487
-#define MSR_IA32_VMX_CR4_FIXED0                 0x488
-#define MSR_IA32_VMX_CR4_FIXED1                 0x489
-#define MSR_IA32_VMX_VMCS_ENUM                  0x48a
-#define MSR_IA32_VMX_PROCBASED_CTLS2            0x48b
-#define MSR_IA32_VMX_EPT_VPID_CAP               0x48c
-
-#define MSR_IA32_FEATURE_CONTROL                0x3a
 #define MSR_IA32_FEATURE_CONTROL_LOCKED         0x1
 #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED  0x4
 
@@ -370,8 +355,6 @@ enum vmcs_field {
 #define VMX_EPT_READABLE_MASK                   0x1ull
 #define VMX_EPT_WRITABLE_MASK                   0x2ull
 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
-#define VMX_EPT_FAKE_ACCESSED_MASK              (1ull << 62)
-#define VMX_EPT_FAKE_DIRTY_MASK                 (1ull << 63)
 
 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
 
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index d9249a882aa5..65f0b8a47bed 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -55,6 +55,7 @@
 #include <linux/lguest_launcher.h>
 #include <linux/virtio_console.h>
 #include <linux/pm.h>
+#include <asm/apic.h>
 #include <asm/lguest.h>
 #include <asm/paravirt.h>
 #include <asm/param.h>
@@ -783,14 +784,44 @@ static void lguest_wbinvd(void)
  * code qualifies for Advanced.  It will also never interrupt anything.  It
  * does, however, allow us to get through the Linux boot code. */
 #ifdef CONFIG_X86_LOCAL_APIC
-static void lguest_apic_write(unsigned long reg, u32 v)
+static void lguest_apic_write(u32 reg, u32 v)
 {
 }
 
-static u32 lguest_apic_read(unsigned long reg)
+static u32 lguest_apic_read(u32 reg)
 {
         return 0;
 }
+
+static u64 lguest_apic_icr_read(void)
+{
+        return 0;
+}
+
+static void lguest_apic_icr_write(u32 low, u32 id)
+{
+        /* Warn to see if there's any stray references */
+        WARN_ON(1);
+}
+
+static void lguest_apic_wait_icr_idle(void)
+{
+        return;
+}
+
+static u32 lguest_apic_safe_wait_icr_idle(void)
+{
+        return 0;
+}
+
+static struct apic_ops lguest_basic_apic_ops = {
+        .read = lguest_apic_read,
+        .write = lguest_apic_write,
+        .icr_read = lguest_apic_icr_read,
+        .icr_write = lguest_apic_icr_write,
+        .wait_icr_idle = lguest_apic_wait_icr_idle,
+        .safe_wait_icr_idle = lguest_apic_safe_wait_icr_idle,
+};
 #endif
 
 /* STOP!  Until an interrupt comes in. */
@@ -990,8 +1021,7 @@ __init void lguest_init(void)
 
 #ifdef CONFIG_X86_LOCAL_APIC
         /* apic read/write intercepts */
-        pv_apic_ops.apic_write = lguest_apic_write;
-        pv_apic_ops.apic_read = lguest_apic_read;
+        apic_ops = &lguest_basic_apic_ops;
 #endif
 
         /* time operations */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index aa3fa4119424..55e11aa6d66c 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -17,9 +17,6 @@ ifeq ($(CONFIG_X86_32),y)
         lib-$(CONFIG_X86_USE_3DNOW) += mmx_32.o
 else
         obj-y += io_64.o iomap_copy_64.o
-
-        CFLAGS_csum-partial_64.o := -funroll-loops
-
         lib-y += csum-partial_64.o csum-copy_64.o csum-wrappers_64.o
         lib-y += thunk_64.o clear_page_64.o copy_page_64.o
         lib-y += memmove_64.o memset_64.o
diff --git a/arch/x86/lib/msr-on-cpu.c b/arch/x86/lib/msr-on-cpu.c
index 01b868ba82f8..321cf720dbb6 100644
--- a/arch/x86/lib/msr-on-cpu.c
+++ b/arch/x86/lib/msr-on-cpu.c
@@ -16,37 +16,46 @@ static void __rdmsr_on_cpu(void *info)
         rdmsr(rv->msr_no, rv->l, rv->h);
 }
 
-static void __rdmsr_safe_on_cpu(void *info)
+static void __wrmsr_on_cpu(void *info)
 {
         struct msr_info *rv = info;
 
-        rv->err = rdmsr_safe(rv->msr_no, &rv->l, &rv->h);
+        wrmsr(rv->msr_no, rv->l, rv->h);
 }
 
-static int _rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h, int safe)
+int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 {
-        int err = 0;
+        int err;
         struct msr_info rv;
 
         rv.msr_no = msr_no;
-        if (safe) {
-                err = smp_call_function_single(cpu, __rdmsr_safe_on_cpu,
-                                               &rv, 1);
-                err = err ? err : rv.err;
-        } else {
-                err = smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1);
-        }
+        err = smp_call_function_single(cpu, __rdmsr_on_cpu, &rv, 1);
         *l = rv.l;
         *h = rv.h;
 
         return err;
 }
 
-static void __wrmsr_on_cpu(void *info)
+int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+{
+        int err;
+        struct msr_info rv;
+
+        rv.msr_no = msr_no;
+        rv.l = l;
+        rv.h = h;
+        err = smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1);
+
+        return err;
+}
+
+/* These "safe" variants are slower and should be used when the target MSR
+   may not actually exist. */
+static void __rdmsr_safe_on_cpu(void *info)
 {
         struct msr_info *rv = info;
 
-        wrmsr(rv->msr_no, rv->l, rv->h);
+        rv->err = rdmsr_safe(rv->msr_no, &rv->l, &rv->h);
 }
 
 static void __wrmsr_safe_on_cpu(void *info)
@@ -56,45 +65,30 @@ static void __wrmsr_safe_on_cpu(void *info)
         rv->err = wrmsr_safe(rv->msr_no, rv->l, rv->h);
 }
 
-static int _wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h, int safe)
+int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 {
-        int err = 0;
+        int err;
         struct msr_info rv;
 
         rv.msr_no = msr_no;
-        rv.l = l;
-        rv.h = h;
-        if (safe) {
-                err = smp_call_function_single(cpu, __wrmsr_safe_on_cpu,
-                                               &rv, 1);
-                err = err ? err : rv.err;
-        } else {
-                err = smp_call_function_single(cpu, __wrmsr_on_cpu, &rv, 1);
-        }
-
-        return err;
-}
+        err = smp_call_function_single(cpu, __rdmsr_safe_on_cpu, &rv, 1);
+        *l = rv.l;
+        *h = rv.h;
 
-int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
-{
-        return _wrmsr_on_cpu(cpu, msr_no, l, h, 0);
+        return err ? err : rv.err;
 }
 
-int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
-{
-        return _rdmsr_on_cpu(cpu, msr_no, l, h, 0);
-}
-
-/* These "safe" variants are slower and should be used when the target MSR
-   may not actually exist. */
 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {
-        return _wrmsr_on_cpu(cpu, msr_no, l, h, 1);
-}
+        int err;
+        struct msr_info rv;
 
-int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
-{
-        return _rdmsr_on_cpu(cpu, msr_no, l, h, 1);
+        rv.msr_no = msr_no;
+        rv.l = l;
+        rv.h = h;
+        err = smp_call_function_single(cpu, __wrmsr_safe_on_cpu, &rv, 1);
+
+        return err ? err : rv.err;
 }
 
 EXPORT_SYMBOL(rdmsr_on_cpu);
diff --git a/arch/x86/lib/string_32.c b/arch/x86/lib/string_32.c
index 94972e7c094d..82004d2bf05e 100644
--- a/arch/x86/lib/string_32.c
+++ b/arch/x86/lib/string_32.c
@@ -22,7 +22,7 @@ char *strcpy(char *dest, const char *src)
                 "testb %%al,%%al\n\t"
                 "jne 1b"
                 : "=&S" (d0), "=&D" (d1), "=&a" (d2)
-                :"0" (src), "1" (dest) : "memory");
+                : "0" (src), "1" (dest) : "memory");
         return dest;
 }
 EXPORT_SYMBOL(strcpy);
@@ -42,7 +42,7 @@ char *strncpy(char *dest, const char *src, size_t count)
                 "stosb\n"
                 "2:"
                 : "=&S" (d0), "=&D" (d1), "=&c" (d2), "=&a" (d3)
-                :"0" (src), "1" (dest), "2" (count) : "memory");
+                : "0" (src), "1" (dest), "2" (count) : "memory");
         return dest;
 }
 EXPORT_SYMBOL(strncpy);
@@ -60,7 +60,7 @@ char *strcat(char *dest, const char *src)
                 "testb %%al,%%al\n\t"
                 "jne 1b"
                 : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3)
-                : "0" (src), "1" (dest), "2" (0), "3" (0xffffffffu): "memory");
+                : "0" (src), "1" (dest), "2" (0), "3" (0xffffffffu) : "memory");
         return dest;
 }
 EXPORT_SYMBOL(strcat);
@@ -105,9 +105,9 @@ int strcmp(const char *cs, const char *ct)
                 "2:\tsbbl %%eax,%%eax\n\t"
                 "orb $1,%%al\n"
                 "3:"
-                :"=a" (res), "=&S" (d0), "=&D" (d1)
-                :"1" (cs), "2" (ct)
-                :"memory");
+                : "=a" (res), "=&S" (d0), "=&D" (d1)
+                : "1" (cs), "2" (ct)
+                : "memory");
         return res;
 }
 EXPORT_SYMBOL(strcmp);
@@ -130,9 +130,9 @@ int strncmp(const char *cs, const char *ct, size_t count)
                 "3:\tsbbl %%eax,%%eax\n\t"
                 "orb $1,%%al\n"
                 "4:"
-                :"=a" (res), "=&S" (d0), "=&D" (d1), "=&c" (d2)
-                :"1" (cs), "2" (ct), "3" (count)
-                :"memory");
+                : "=a" (res), "=&S" (d0), "=&D" (d1), "=&c" (d2)
+                : "1" (cs), "2" (ct), "3" (count)
+                : "memory");
         return res;
 }
 EXPORT_SYMBOL(strncmp);
@@ -152,9 +152,9 @@ char *strchr(const char *s, int c)
                 "movl $1,%1\n"
                 "2:\tmovl %1,%0\n\t"
                 "decl %0"
-                :"=a" (res), "=&S" (d0)
-                :"1" (s), "0" (c)
-                :"memory");
+                : "=a" (res), "=&S" (d0)
+                : "1" (s), "0" (c)
+                : "memory");
         return res;
 }
 EXPORT_SYMBOL(strchr);
@@ -169,9 +169,9 @@ size_t strlen(const char *s)
                 "scasb\n\t"
                 "notl %0\n\t"
                 "decl %0"
-                :"=c" (res), "=&D" (d0)
-                :"1" (s), "a" (0), "0" (0xffffffffu)
-                :"memory");
+                : "=c" (res), "=&D" (d0)
+                : "1" (s), "a" (0), "0" (0xffffffffu)
+                : "memory");
         return res;
 }
 EXPORT_SYMBOL(strlen);
@@ -189,9 +189,9 @@ void *memchr(const void *cs, int c, size_t count)
                 "je 1f\n\t"
                 "movl $1,%0\n"
                 "1:\tdecl %0"
-                :"=D" (res), "=&c" (d0)
-                :"a" (c), "0" (cs), "1" (count)
-                :"memory");
+                : "=D" (res), "=&c" (d0)
+                : "a" (c), "0" (cs), "1" (count)
+                : "memory");
         return res;
 }
 EXPORT_SYMBOL(memchr);
@@ -228,9 +228,9 @@ size_t strnlen(const char *s, size_t count)
                 "cmpl $-1,%1\n\t"
                 "jne 1b\n"
                 "3:\tsubl %2,%0"
-                :"=a" (res), "=&d" (d0)
-                :"c" (s), "1" (count)
-                :"memory");
+                : "=a" (res), "=&d" (d0)
+                : "c" (s), "1" (count)
+                : "memory");
         return res;
 }
 EXPORT_SYMBOL(strnlen);
diff --git a/arch/x86/lib/strstr_32.c b/arch/x86/lib/strstr_32.c
index 42e8a50303f3..8e2d55f754bf 100644
--- a/arch/x86/lib/strstr_32.c
+++ b/arch/x86/lib/strstr_32.c
@@ -23,9 +23,9 @@ __asm__ __volatile__(
         "jne 1b\n\t"
         "xorl %%eax,%%eax\n\t"
         "2:"
-        :"=a" (__res), "=&c" (d0), "=&S" (d1)
-        :"0" (0), "1" (0xffffffff), "2" (cs), "g" (ct)
-        :"dx", "di");
+        : "=a" (__res), "=&c" (d0), "=&S" (d1)
+        : "0" (0), "1" (0xffffffff), "2" (cs), "g" (ct)
+        : "dx", "di");
 return __res;
 }
 
diff --git a/arch/x86/lib/usercopy_32.c b/arch/x86/lib/usercopy_32.c
index 24e60944971a..9e68075544f6 100644
--- a/arch/x86/lib/usercopy_32.c
+++ b/arch/x86/lib/usercopy_32.c
@@ -14,6 +14,13 @@
 #include <asm/uaccess.h>
 #include <asm/mmx.h>
 
+#ifdef CONFIG_X86_INTEL_USERCOPY
+/*
+ * Alignment at which movsl is preferred for bulk memory copies.
+ */
+struct movsl_mask movsl_mask __read_mostly;
+#endif
+
 static inline int __movsl_is_ok(unsigned long a1, unsigned long a2, unsigned long n)
 {
 #ifdef CONFIG_X86_INTEL_USERCOPY
diff --git a/arch/x86/mach-default/setup.c b/arch/x86/mach-default/setup.c
index 3d317836be9e..37b9ae4d44c5 100644
--- a/arch/x86/mach-default/setup.c
+++ b/arch/x86/mach-default/setup.c
@@ -10,13 +10,15 @@
 #include <asm/e820.h>
 #include <asm/setup.h>
 
+#include <mach_ipi.h>
+
 #ifdef CONFIG_HOTPLUG_CPU
 #define DEFAULT_SEND_IPI        (1)
 #else
 #define DEFAULT_SEND_IPI        (0)
 #endif
 
-int no_broadcast=DEFAULT_SEND_IPI;
+int no_broadcast = DEFAULT_SEND_IPI;
 
 /**
  * pre_intr_init_hook - initialisation prior to setting up interrupt vectors
@@ -36,15 +38,6 @@ void __init pre_intr_init_hook(void)
         init_ISA_irqs();
 }
 
-/*
- * IRQ2 is cascade interrupt to second interrupt controller
- */
-static struct irqaction irq2 = {
-        .handler = no_action,
-        .mask = CPU_MASK_NONE,
-        .name = "cascade",
-};
-
 /**
  * intr_init_hook - post gate setup interrupt initialisation
  *
@@ -60,12 +53,6 @@ void __init intr_init_hook(void)
                 if (x86_quirks->arch_intr_init())
                         return;
         }
-#ifdef CONFIG_X86_LOCAL_APIC
-        apic_intr_init();
-#endif
-
-        if (!acpi_ioapic)
-                setup_irq(2, &irq2);
 }
 
 /**
diff --git a/arch/x86/mach-es7000/Makefile b/arch/x86/mach-es7000/Makefile
deleted file mode 100644
index 3ef8b43b62fc..000000000000
--- a/arch/x86/mach-es7000/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-$(CONFIG_X86_ES7000)        := es7000plat.o
diff --git a/arch/x86/mach-es7000/es7000.h b/arch/x86/mach-es7000/es7000.h
deleted file mode 100644
index c8d5aa132fa0..000000000000
--- a/arch/x86/mach-es7000/es7000.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Written by: Garry Forsgren, Unisys Corporation
- *             Natalie Protasevich, Unisys Corporation
- * This file contains the code to configure and interface 
- * with Unisys ES7000 series hardware system manager.
- *
- * Copyright (c) 2003 Unisys Corporation.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it would be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Contact information: Unisys Corporation, Township Line & Union Meeting 
- * Roads-A, Unisys Way, Blue Bell, Pennsylvania, 19424, or:
- *
- * http://www.unisys.com
- */
-
-/*
- * ES7000 chipsets
- */
-
-#define NON_UNISYS              0
-#define ES7000_CLASSIC          1
-#define ES7000_ZORRO            2
-
-
-#define MIP_REG                 1
-#define MIP_PSAI_REG            4
-
-#define MIP_BUSY                1
-#define MIP_SPIN                0xf0000
-#define MIP_VALID               0x0100000000000000ULL
-#define MIP_PORT(VALUE) ((VALUE >> 32) & 0xffff)
-
-#define MIP_RD_LO(VALUE)        (VALUE & 0xffffffff)   
-
-struct mip_reg_info {
-        unsigned long long mip_info;
-        unsigned long long delivery_info;
-        unsigned long long host_reg;
-        unsigned long long mip_reg;
-};
-
-struct part_info {
-        unsigned char type;   
-        unsigned char length;
-        unsigned char part_id;
-        unsigned char apic_mode;
-        unsigned long snum;    
-        char ptype[16];
-        char sname[64];
-        char pname[64];
-};
-
-struct psai {
-        unsigned long long entry_type;
-        unsigned long long addr;
-        unsigned long long bep_addr;
-};
-
-struct es7000_mem_info {
-        unsigned char type;   
-        unsigned char length;
-        unsigned char resv[6];
-        unsigned long long  start; 
-        unsigned long long  size; 
-};
-
-struct es7000_oem_table {
-        unsigned long long hdr;
-        struct mip_reg_info mip;
-        struct part_info pif;
-        struct es7000_mem_info shm;
-        struct psai psai;
-};
-
-#ifdef CONFIG_ACPI
-
-struct oem_table {
-        struct acpi_table_header Header;
-        u32 OEMTableAddr;
-        u32 OEMTableSize;
-};
-
-extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
-#endif
-
-struct mip_reg {
-        unsigned long long off_0;
-        unsigned long long off_8;
-        unsigned long long off_10;
-        unsigned long long off_18;
-        unsigned long long off_20;
-        unsigned long long off_28;
-        unsigned long long off_30;
-        unsigned long long off_38;
-};
-
-#define MIP_SW_APIC             0x1020b
-#define MIP_FUNC(VALUE)         (VALUE & 0xff)
-
-extern int parse_unisys_oem (char *oemptr);
-extern void setup_unisys(void);
-extern int es7000_start_cpu(int cpu, unsigned long eip);
-extern void es7000_sw_apic(void);
diff --git a/arch/x86/mach-generic/Makefile b/arch/x86/mach-generic/Makefile
index 0dbd7803a1d5..6730f4e7c744 100644
--- a/arch/x86/mach-generic/Makefile
+++ b/arch/x86/mach-generic/Makefile
@@ -9,4 +9,3 @@ obj-$(CONFIG_X86_NUMAQ)		+= numaq.o
 obj-$(CONFIG_X86_SUMMIT)        += summit.o
 obj-$(CONFIG_X86_BIGSMP)        += bigsmp.o
 obj-$(CONFIG_X86_ES7000)        += es7000.o
-obj-$(CONFIG_X86_ES7000)        += ../../x86/mach-es7000/
diff --git a/arch/x86/mach-generic/bigsmp.c b/arch/x86/mach-generic/bigsmp.c
index 59d771714559..df37fc9d6a26 100644
--- a/arch/x86/mach-generic/bigsmp.c
+++ b/arch/x86/mach-generic/bigsmp.c
@@ -5,18 +5,17 @@
 #define APIC_DEFINITION 1
 #include <linux/threads.h>
 #include <linux/cpumask.h>
-#include <asm/smp.h>
 #include <asm/mpspec.h>
 #include <asm/genapic.h>
 #include <asm/fixmap.h>
 #include <asm/apicdef.h>
 #include <linux/kernel.h>
-#include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/dmi.h>
-#include <asm/mach-bigsmp/mach_apic.h>
-#include <asm/mach-bigsmp/mach_apicdef.h>
-#include <asm/mach-bigsmp/mach_ipi.h>
+#include <asm/bigsmp/apicdef.h>
+#include <linux/smp.h>
+#include <asm/bigsmp/apic.h>
+#include <asm/bigsmp/ipi.h>
 #include <asm/mach-default/mach_mpparse.h>
 
 static int dmi_bigsmp; /* can be set by dmi scanners */
diff --git a/arch/x86/mach-generic/es7000.c b/arch/x86/mach-generic/es7000.c
index 4742626f08c4..520cca0ee04e 100644
--- a/arch/x86/mach-generic/es7000.c
+++ b/arch/x86/mach-generic/es7000.c
@@ -4,20 +4,19 @@
 #define APIC_DEFINITION 1
 #include <linux/threads.h>
 #include <linux/cpumask.h>
-#include <asm/smp.h>
 #include <asm/mpspec.h>
 #include <asm/genapic.h>
 #include <asm/fixmap.h>
 #include <asm/apicdef.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
-#include <linux/smp.h>
 #include <linux/init.h>
-#include <asm/mach-es7000/mach_apicdef.h>
-#include <asm/mach-es7000/mach_apic.h>
-#include <asm/mach-es7000/mach_ipi.h>
-#include <asm/mach-es7000/mach_mpparse.h>
-#include <asm/mach-es7000/mach_wakecpu.h>
+#include <asm/es7000/apicdef.h>
+#include <linux/smp.h>
+#include <asm/es7000/apic.h>
+#include <asm/es7000/ipi.h>
+#include <asm/es7000/mpparse.h>
+#include <asm/es7000/wakecpu.h>
 
 static int probe_es7000(void)
 {
diff --git a/arch/x86/mach-generic/numaq.c b/arch/x86/mach-generic/numaq.c
index 8091e68764c4..8cf58394975e 100644
--- a/arch/x86/mach-generic/numaq.c
+++ b/arch/x86/mach-generic/numaq.c
@@ -4,7 +4,6 @@
 #define APIC_DEFINITION 1
 #include <linux/threads.h>
 #include <linux/cpumask.h>
-#include <linux/smp.h>
 #include <asm/mpspec.h>
 #include <asm/genapic.h>
 #include <asm/fixmap.h>
@@ -12,11 +11,12 @@
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/init.h>
-#include <asm/mach-numaq/mach_apic.h>
-#include <asm/mach-numaq/mach_apicdef.h>
-#include <asm/mach-numaq/mach_ipi.h>
-#include <asm/mach-numaq/mach_mpparse.h>
-#include <asm/mach-numaq/mach_wakecpu.h>
+#include <asm/numaq/apicdef.h>
+#include <linux/smp.h>
+#include <asm/numaq/apic.h>
+#include <asm/numaq/ipi.h>
+#include <asm/numaq/mpparse.h>
+#include <asm/numaq/wakecpu.h>
 #include <asm/numaq.h>
 
 static int mps_oem_check(struct mp_config_table *mpc, char *oem,
diff --git a/arch/x86/mach-generic/summit.c b/arch/x86/mach-generic/summit.c
index a97ea0f35b1e..6ad6b67a723d 100644
--- a/arch/x86/mach-generic/summit.c
+++ b/arch/x86/mach-generic/summit.c
@@ -4,19 +4,18 @@
 #define APIC_DEFINITION 1
 #include <linux/threads.h>
 #include <linux/cpumask.h>
-#include <asm/smp.h>
 #include <asm/mpspec.h>
 #include <asm/genapic.h>
 #include <asm/fixmap.h>
 #include <asm/apicdef.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
-#include <linux/smp.h>
 #include <linux/init.h>
-#include <asm/mach-summit/mach_apic.h>
-#include <asm/mach-summit/mach_apicdef.h>
-#include <asm/mach-summit/mach_ipi.h>
-#include <asm/mach-summit/mach_mpparse.h>
+#include <asm/summit/apicdef.h>
+#include <linux/smp.h>
+#include <asm/summit/apic.h>
+#include <asm/summit/ipi.h>
+#include <asm/summit/mpparse.h>
 
 static int probe_summit(void)
 {
diff --git a/arch/x86/mach-voyager/voyager_smp.c b/arch/x86/mach-voyager/voyager_smp.c
index ee0fba092157..199a5f4a873c 100644
--- a/arch/x86/mach-voyager/voyager_smp.c
+++ b/arch/x86/mach-voyager/voyager_smp.c
@@ -448,6 +448,8 @@ static void __init start_secondary(void *unused)
 
         VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
 
+        notify_cpu_starting(cpuid);
+
         /* enable interrupts */
         local_irq_enable();
 
diff --git a/arch/x86/mm/discontig_32.c b/arch/x86/mm/discontig_32.c
index 62fa440678d8..847c164725f4 100644
--- a/arch/x86/mm/discontig_32.c
+++ b/arch/x86/mm/discontig_32.c
@@ -328,7 +328,7 @@ void __init initmem_init(unsigned long start_pfn,
 
         get_memcfg_numa();
 
-        kva_pages = round_up(calculate_numa_remap_pages(), PTRS_PER_PTE);
+        kva_pages = roundup(calculate_numa_remap_pages(), PTRS_PER_PTE);
 
         kva_target_pfn = round_down(max_low_pfn - kva_pages, PTRS_PER_PTE);
         do {
diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.c
index a20d1fa64b4e..e7277cbcfb40 100644
--- a/arch/x86/mm/dump_pagetables.c
+++ b/arch/x86/mm/dump_pagetables.c
@@ -148,8 +148,8 @@ static void note_page(struct seq_file *m, struct pg_state *st,
          * we have now. "break" is either changing perms, levels or
          * address space marker.
          */
-        prot = pgprot_val(new_prot) & ~(PTE_PFN_MASK);
-        cur = pgprot_val(st->current_prot) & ~(PTE_PFN_MASK);
+        prot = pgprot_val(new_prot) & PTE_FLAGS_MASK;
+        cur = pgprot_val(st->current_prot) & PTE_FLAGS_MASK;
 
         if (!st->level) {
                 /* First entry */
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 455f3fe67b42..8f92cac4e6db 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -35,6 +35,7 @@
 #include <asm/tlbflush.h>
 #include <asm/proto.h>
 #include <asm-generic/sections.h>
+#include <asm/traps.h>
 
 /*
  * Page fault error code bits
@@ -357,8 +358,6 @@ static int is_errata100(struct pt_regs *regs, unsigned long address)
         return 0;
 }
 
-void do_invalid_op(struct pt_regs *, unsigned long);
-
 static int is_f00f_bug(struct pt_regs *regs, unsigned long address)
 {
 #ifdef CONFIG_X86_F00F_BUG
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 657a16ad61ba..7e05462ffb11 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -47,6 +47,7 @@
 #include <asm/paravirt.h>
 #include <asm/setup.h>
 #include <asm/cacheflush.h>
+#include <asm/smp.h>
 
 unsigned int __VMALLOC_RESERVE = 128 << 20;
 
@@ -194,11 +195,30 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base,
         pgd_t *pgd;
         pmd_t *pmd;
         pte_t *pte;
-        unsigned pages_2m = 0, pages_4k = 0;
+        unsigned pages_2m, pages_4k;
+        int mapping_iter;
+
+        /*
+         * First iteration will setup identity mapping using large/small pages
+         * based on use_pse, with other attributes same as set by
+         * the early code in head_32.S
+         *
+         * Second iteration will setup the appropriate attributes (NX, GLOBAL..)
+         * as desired for the kernel identity mapping.
+         *
+         * This two pass mechanism conforms to the TLB app note which says:
+         *
+         *     "Software should not write to a paging-structure entry in a way
+         *      that would change, for any linear address, both the page size
+         *      and either the page frame or attributes."
+         */
+        mapping_iter = 1;
 
         if (!cpu_has_pse)
                 use_pse = 0;
 
+repeat:
+        pages_2m = pages_4k = 0;
         pfn = start_pfn;
         pgd_idx = pgd_index((pfn<<PAGE_SHIFT) + PAGE_OFFSET);
         pgd = pgd_base + pgd_idx;
@@ -224,6 +244,13 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base,
                         if (use_pse) {
                                 unsigned int addr2;
                                 pgprot_t prot = PAGE_KERNEL_LARGE;
+                                /*
+                                 * first pass will use the same initial
+                                 * identity mapping attribute + _PAGE_PSE.
+                                 */
+                                pgprot_t init_prot =
+                                        __pgprot(PTE_IDENT_ATTR |
+                                                 _PAGE_PSE);
 
                                 addr2 = (pfn + PTRS_PER_PTE-1) * PAGE_SIZE +
                                         PAGE_OFFSET + PAGE_SIZE-1;
@@ -233,7 +260,10 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base,
                                         prot = PAGE_KERNEL_LARGE_EXEC;
 
                                 pages_2m++;
-                                set_pmd(pmd, pfn_pmd(pfn, prot));
+                                if (mapping_iter == 1)
+                                        set_pmd(pmd, pfn_pmd(pfn, init_prot));
+                                else
+                                        set_pmd(pmd, pfn_pmd(pfn, prot));
 
                                 pfn += PTRS_PER_PTE;
                                 continue;
@@ -245,17 +275,43 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base,
                         for (; pte_ofs < PTRS_PER_PTE && pfn < end_pfn;
                              pte++, pfn++, pte_ofs++, addr += PAGE_SIZE) {
                                 pgprot_t prot = PAGE_KERNEL;
+                                /*
+                                 * first pass will use the same initial
+                                 * identity mapping attribute.
+                                 */
+                                pgprot_t init_prot = __pgprot(PTE_IDENT_ATTR);
 
                                 if (is_kernel_text(addr))
                                         prot = PAGE_KERNEL_EXEC;
 
                                 pages_4k++;
-                                set_pte(pte, pfn_pte(pfn, prot));
+                                if (mapping_iter == 1)
+                                        set_pte(pte, pfn_pte(pfn, init_prot));
+                                else
+                                        set_pte(pte, pfn_pte(pfn, prot));
                         }
                 }
         }
-        update_page_count(PG_LEVEL_2M, pages_2m);
-        update_page_count(PG_LEVEL_4K, pages_4k);
+        if (mapping_iter == 1) {
+                /*
+                 * update direct mapping page count only in the first
+                 * iteration.
+                 */
+                update_page_count(PG_LEVEL_2M, pages_2m);
+                update_page_count(PG_LEVEL_4K, pages_4k);
+
+                /*
+                 * local global flush tlb, which will flush the previous
+                 * mappings present in both small and large page TLB's.
+                 */
+                __flush_tlb_all();
+
+                /*
+                 * Second iteration will set the actual desired PTE attributes.
+                 */
+                mapping_iter = 2;
+                goto repeat;
+        }
 }
 
 /*
@@ -458,11 +514,7 @@ static void __init pagetable_init(void)
 {
         pgd_t *pgd_base = swapper_pg_dir;
 
-        paravirt_pagetable_setup_start(pgd_base);
-
         permanent_kmaps_init(pgd_base);
-
-        paravirt_pagetable_setup_done(pgd_base);
 }
 
 #ifdef CONFIG_ACPI_SLEEP
@@ -722,7 +774,7 @@ void __init setup_bootmem_allocator(void)
         after_init_bootmem = 1;
 }
 
-static void __init find_early_table_space(unsigned long end)
+static void __init find_early_table_space(unsigned long end, int use_pse)
 {
         unsigned long puds, pmds, ptes, tables, start;
 
@@ -732,7 +784,7 @@ static void __init find_early_table_space(unsigned long end)
         pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT;
         tables += PAGE_ALIGN(pmds * sizeof(pmd_t));
 
-        if (cpu_has_pse) {
+        if (use_pse) {
                 unsigned long extra;
 
                 extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT);
@@ -772,12 +824,22 @@ unsigned long __init_refok init_memory_mapping(unsigned long start,
         pgd_t *pgd_base = swapper_pg_dir;
         unsigned long start_pfn, end_pfn;
         unsigned long big_page_start;
+#ifdef CONFIG_DEBUG_PAGEALLOC
+        /*
+         * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages.
+         * This will simplify cpa(), which otherwise needs to support splitting
+         * large pages into small in interrupt context, etc.
+         */
+        int use_pse = 0;
+#else
+        int use_pse = cpu_has_pse;
+#endif
 
         /*
          * Find space for the kernel direct mapping tables.
          */
         if (!after_init_bootmem)
-                find_early_table_space(end);
+                find_early_table_space(end, use_pse);
 
 #ifdef CONFIG_X86_PAE
         set_nx();
@@ -823,7 +885,7 @@ unsigned long __init_refok init_memory_mapping(unsigned long start,
         end_pfn = (end>>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT);
         if (start_pfn < end_pfn)
                 kernel_physical_mapping_init(pgd_base, start_pfn, end_pfn,
-                                                cpu_has_pse);
+                                             use_pse);
 
         /* tail is not big page alignment ? */
         start_pfn = end_pfn;
@@ -988,7 +1050,6 @@ void __init mem_init(void)
         if (boot_cpu_data.wp_works_ok < 0)
                 test_wp_bit();
 
-        cpa_init();
         save_pg_dir();
         zap_low_mappings();
 }
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index f4db5276fa21..d84d3e91d348 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -88,6 +88,62 @@ early_param("gbpages", parse_direct_gbpages_on);
 
 int after_bootmem;
 
+unsigned long __supported_pte_mask __read_mostly = ~0UL;
+EXPORT_SYMBOL_GPL(__supported_pte_mask);
+
+static int do_not_nx __cpuinitdata;
+
+/*
+ * noexec=on|off
+ * Control non-executable mappings for 64-bit processes.
+ *
+ * on   Enable (default)
+ * off  Disable
+ */
+static int __init nonx_setup(char *str)
+{
+        if (!str)
+                return -EINVAL;
+        if (!strncmp(str, "on", 2)) {
+                __supported_pte_mask |= _PAGE_NX;
+                do_not_nx = 0;
+        } else if (!strncmp(str, "off", 3)) {
+                do_not_nx = 1;
+                __supported_pte_mask &= ~_PAGE_NX;
+        }
+        return 0;
+}
+early_param("noexec", nonx_setup);
+
+void __cpuinit check_efer(void)
+{
+        unsigned long efer;
+
+        rdmsrl(MSR_EFER, efer);
+        if (!(efer & EFER_NX) || do_not_nx)
+                __supported_pte_mask &= ~_PAGE_NX;
+}
+
+int force_personality32;
+
+/*
+ * noexec32=on|off
+ * Control non executable heap for 32bit processes.
+ * To control the stack too use noexec=off
+ *
+ * on   PROT_READ does not imply PROT_EXEC for 32-bit processes (default)
+ * off  PROT_READ implies PROT_EXEC
+ */
+static int __init nonx32_setup(char *str)
+{
+        if (!strcmp(str, "on"))
+                force_personality32 &= ~READ_IMPLIES_EXEC;
+        else if (!strcmp(str, "off"))
+                force_personality32 |= READ_IMPLIES_EXEC;
+        return 1;
+}
+__setup("noexec32=", nonx32_setup);
+
 /*
  * NOTE: This function is marked __ref because it calls __init function
  * (alloc_bootmem_pages). It's safe to do it ONLY when after_bootmem == 0.
@@ -225,7 +281,7 @@ void __init init_extra_mapping_uc(unsigned long phys, unsigned long size)
 void __init cleanup_highmap(void)
 {
         unsigned long vaddr = __START_KERNEL_map;
-        unsigned long end = round_up((unsigned long)_end, PMD_SIZE) - 1;
+        unsigned long end = roundup((unsigned long)_end, PMD_SIZE) - 1;
         pmd_t *pmd = level2_kernel_pgt;
         pmd_t *last_pmd = pmd + PTRS_PER_PMD;
 
@@ -271,7 +327,8 @@ static __ref void unmap_low_page(void *adr)
 }
 
 static unsigned long __meminit
-phys_pte_init(pte_t *pte_page, unsigned long addr, unsigned long end)
+phys_pte_init(pte_t *pte_page, unsigned long addr, unsigned long end,
+              pgprot_t prot)
 {
         unsigned pages = 0;
         unsigned long last_map_addr = end;
@@ -289,36 +346,43 @@ phys_pte_init(pte_t *pte_page, unsigned long addr, unsigned long end)
                         break;
                 }
 
+                /*
+                 * We will re-use the existing mapping.
+                 * Xen for example has some special requirements, like mapping
+                 * pagetable pages as RO. So assume someone who pre-setup
+                 * these mappings are more intelligent.
+                 */
                 if (pte_val(*pte))
                         continue;
 
                 if (0)
                         printk("   pte=%p addr=%lx pte=%016lx\n",
                                pte, addr, pfn_pte(addr >> PAGE_SHIFT, PAGE_KERNEL).pte);
-                set_pte(pte, pfn_pte(addr >> PAGE_SHIFT, PAGE_KERNEL));
-                last_map_addr = (addr & PAGE_MASK) + PAGE_SIZE;
                 pages++;
+                set_pte(pte, pfn_pte(addr >> PAGE_SHIFT, prot));
+                last_map_addr = (addr & PAGE_MASK) + PAGE_SIZE;
         }
+
         update_page_count(PG_LEVEL_4K, pages);
 
         return last_map_addr;
 }
 
 static unsigned long __meminit
-phys_pte_update(pmd_t *pmd, unsigned long address, unsigned long end)
+phys_pte_update(pmd_t *pmd, unsigned long address, unsigned long end,
+                pgprot_t prot)
 {
         pte_t *pte = (pte_t *)pmd_page_vaddr(*pmd);
 
-        return phys_pte_init(pte, address, end);
+        return phys_pte_init(pte, address, end, prot);
 }
 
 static unsigned long __meminit
 phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end,
-                         unsigned long page_size_mask)
+              unsigned long page_size_mask, pgprot_t prot)
 {
         unsigned long pages = 0;
         unsigned long last_map_addr = end;
-        unsigned long start = address;
 
         int i = pmd_index(address);
 
@@ -326,6 +390,7 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end,
                 unsigned long pte_phys;
                 pmd_t *pmd = pmd_page + pmd_index(address);
                 pte_t *pte;
+                pgprot_t new_prot = prot;
 
                 if (address >= end) {
                         if (!after_bootmem) {
@@ -339,27 +404,40 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end,
                         if (!pmd_large(*pmd)) {
                                 spin_lock(&init_mm.page_table_lock);
                                 last_map_addr = phys_pte_update(pmd, address,
-                                                                end);
+                                                                end, prot);
                                 spin_unlock(&init_mm.page_table_lock);
+                                continue;
                         }
-                        /* Count entries we're using from level2_ident_pgt */
-                        if (start == 0)
-                                pages++;
-                        continue;
+                        /*
+                         * If we are ok with PG_LEVEL_2M mapping, then we will
+                         * use the existing mapping,
+                         *
+                         * Otherwise, we will split the large page mapping but
+                         * use the same existing protection bits except for
+                         * large page, so that we don't violate Intel's TLB
+                         * Application note (317080) which says, while changing
+                         * the page sizes, new and old translations should
+                         * not differ with respect to page frame and
+                         * attributes.
+                         */
+                        if (page_size_mask & (1 << PG_LEVEL_2M))
+                                continue;
+                        new_prot = pte_pgprot(pte_clrhuge(*(pte_t *)pmd));
                 }
 
                 if (page_size_mask & (1<<PG_LEVEL_2M)) {
                         pages++;
                         spin_lock(&init_mm.page_table_lock);
                         set_pte((pte_t *)pmd,
-                                pfn_pte(address >> PAGE_SHIFT, PAGE_KERNEL_LARGE));
+                                pfn_pte(address >> PAGE_SHIFT,
+                                        __pgprot(pgprot_val(prot) | _PAGE_PSE)));
                         spin_unlock(&init_mm.page_table_lock);
                         last_map_addr = (address & PMD_MASK) + PMD_SIZE;
                         continue;
                 }
 
                 pte = alloc_low_page(&pte_phys);
-                last_map_addr = phys_pte_init(pte, address, end);
+                last_map_addr = phys_pte_init(pte, address, end, new_prot);
                 unmap_low_page(pte);
 
                 spin_lock(&init_mm.page_table_lock);
@@ -372,12 +450,12 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end,
 
 static unsigned long __meminit
 phys_pmd_update(pud_t *pud, unsigned long address, unsigned long end,
-                         unsigned long page_size_mask)
+                unsigned long page_size_mask, pgprot_t prot)
 {
         pmd_t *pmd = pmd_offset(pud, 0);
         unsigned long last_map_addr;
 
-        last_map_addr = phys_pmd_init(pmd, address, end, page_size_mask);
+        last_map_addr = phys_pmd_init(pmd, address, end, page_size_mask, prot);
         __flush_tlb_all();
         return last_map_addr;
 }
@@ -394,6 +472,7 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end,
                 unsigned long pmd_phys;
                 pud_t *pud = pud_page + pud_index(addr);
                 pmd_t *pmd;
+                pgprot_t prot = PAGE_KERNEL;
 
                 if (addr >= end)
                         break;
@@ -405,10 +484,26 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end,
                 }
 
                 if (pud_val(*pud)) {
-                        if (!pud_large(*pud))
+                        if (!pud_large(*pud)) {
                                 last_map_addr = phys_pmd_update(pud, addr, end,
-                                                         page_size_mask);
-                        continue;
+                                                         page_size_mask, prot);
+                                continue;
+                        }
+                        /*
+                         * If we are ok with PG_LEVEL_1G mapping, then we will
+                         * use the existing mapping.
+                         *
+                         * Otherwise, we will split the gbpage mapping but use
+                         * the same existing protection  bits except for large
+                         * page, so that we don't violate Intel's TLB
+                         * Application note (317080) which says, while changing
+                         * the page sizes, new and old translations should
+                         * not differ with respect to page frame and
+                         * attributes.
+                         */
+                        if (page_size_mask & (1 << PG_LEVEL_1G))
+                                continue;
+                        prot = pte_pgprot(pte_clrhuge(*(pte_t *)pud));
                 }
 
                 if (page_size_mask & (1<<PG_LEVEL_1G)) {
@@ -422,7 +517,8 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end,
                 }
 
                 pmd = alloc_low_page(&pmd_phys);
-                last_map_addr = phys_pmd_init(pmd, addr, end, page_size_mask);
+                last_map_addr = phys_pmd_init(pmd, addr, end, page_size_mask,
+                                              prot);
                 unmap_low_page(pmd);
 
                 spin_lock(&init_mm.page_table_lock);
@@ -430,6 +526,7 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end,
                 spin_unlock(&init_mm.page_table_lock);
         }
         __flush_tlb_all();
+
         update_page_count(PG_LEVEL_1G, pages);
 
         return last_map_addr;
@@ -446,27 +543,28 @@ phys_pud_update(pgd_t *pgd, unsigned long addr, unsigned long end,
         return phys_pud_init(pud, addr, end, page_size_mask);
 }
 
-static void __init find_early_table_space(unsigned long end)
+static void __init find_early_table_space(unsigned long end, int use_pse,
+                                          int use_gbpages)
 {
         unsigned long puds, pmds, ptes, tables, start;
 
         puds = (end + PUD_SIZE - 1) >> PUD_SHIFT;
-        tables = round_up(puds * sizeof(pud_t), PAGE_SIZE);
-        if (direct_gbpages) {
+        tables = roundup(puds * sizeof(pud_t), PAGE_SIZE);
+        if (use_gbpages) {
                 unsigned long extra;
                 extra = end - ((end>>PUD_SHIFT) << PUD_SHIFT);
                 pmds = (extra + PMD_SIZE - 1) >> PMD_SHIFT;
         } else
                 pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT;
-        tables += round_up(pmds * sizeof(pmd_t), PAGE_SIZE);
+        tables += roundup(pmds * sizeof(pmd_t), PAGE_SIZE);
 
-        if (cpu_has_pse) {
+        if (use_pse) {
                 unsigned long extra;
                 extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT);
                 ptes = (extra + PAGE_SIZE - 1) >> PAGE_SHIFT;
         } else
                 ptes = (end + PAGE_SIZE - 1) >> PAGE_SHIFT;
-        tables += round_up(ptes * sizeof(pte_t), PAGE_SIZE);
+        tables += roundup(ptes * sizeof(pte_t), PAGE_SIZE);
 
         /*
          * RED-PEN putting page tables only on node 0 could
@@ -528,6 +626,7 @@ static unsigned long __init kernel_physical_mapping_init(unsigned long start,
                 pgd_populate(&init_mm, pgd, __va(pud_phys));
                 spin_unlock(&init_mm.page_table_lock);
         }
+        __flush_tlb_all();
 
         return last_map_addr;
 }
@@ -571,6 +670,7 @@ unsigned long __init_refok init_memory_mapping(unsigned long start,
 
         struct map_range mr[NR_RANGE_MR];
         int nr_range, i;
+        int use_pse, use_gbpages;
 
         printk(KERN_INFO "init_memory_mapping\n");
 
@@ -584,9 +684,21 @@ unsigned long __init_refok init_memory_mapping(unsigned long start,
         if (!after_bootmem)
                 init_gbpages();
 
-        if (direct_gbpages)
+#ifdef CONFIG_DEBUG_PAGEALLOC
+        /*
+         * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages.
+         * This will simplify cpa(), which otherwise needs to support splitting
+         * large pages into small in interrupt context, etc.
+         */
+        use_pse = use_gbpages = 0;
+#else
+        use_pse = cpu_has_pse;
+        use_gbpages = direct_gbpages;
+#endif
+
+        if (use_gbpages)
                 page_size_mask |= 1 << PG_LEVEL_1G;
-        if (cpu_has_pse)
+        if (use_pse)
                 page_size_mask |= 1 << PG_LEVEL_2M;
 
         memset(mr, 0, sizeof(mr));
@@ -647,7 +759,7 @@ unsigned long __init_refok init_memory_mapping(unsigned long start,
                          (mr[i].page_size_mask & (1<<PG_LEVEL_2M))?"2M":"4k"));
 
         if (!after_bootmem)
-                find_early_table_space(end);
+                find_early_table_space(end, use_pse, use_gbpages);
 
         for (i = 0; i < nr_range; i++)
                 last_map_addr = kernel_physical_mapping_init(
@@ -808,8 +920,6 @@ void __init mem_init(void)
                 reservedpages << (PAGE_SHIFT-10),
                 datasize >> 10,
                 initsize >> 10);
-
-        cpa_init();
 }
 
 void free_init_pages(char *what, unsigned long begin, unsigned long end)
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index d4b6e6a29ae3..6ab3196d12b4 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -83,6 +83,25 @@ int page_is_ram(unsigned long pagenr)
         return 0;
 }
 
+int pagerange_is_ram(unsigned long start, unsigned long end)
+{
+        int ram_page = 0, not_rampage = 0;
+        unsigned long page_nr;
+
+        for (page_nr = (start >> PAGE_SHIFT); page_nr < (end >> PAGE_SHIFT);
+             ++page_nr) {
+                if (page_is_ram(page_nr))
+                        ram_page = 1;
+                else
+                        not_rampage = 1;
+
+                if (ram_page == not_rampage)
+                        return -1;
+        }
+
+        return ram_page;
+}
+
 /*
  * Fix up the linear direct mapping of the kernel to avoid cache attribute
  * conflicts.
@@ -421,7 +440,7 @@ void unxlate_dev_mem_ptr(unsigned long phys, void *addr)
         return;
 }
 
-int __initdata early_ioremap_debug;
+static int __initdata early_ioremap_debug;
 
 static int __init early_ioremap_debug_setup(char *str)
 {
@@ -547,7 +566,7 @@ static inline void __init early_clear_fixmap(enum fixed_addresses idx)
 }
 
 
-int __initdata early_ioremap_nested;
+static int __initdata early_ioremap_nested;
 
 static int __init check_early_ioremap_leak(void)
 {
diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c
index a4dd793d6003..cebcbf152d46 100644
--- a/arch/x86/mm/numa_64.c
+++ b/arch/x86/mm/numa_64.c
@@ -79,7 +79,7 @@ static int __init allocate_cachealigned_memnodemap(void)
                 return 0;
 
         addr = 0x8000;
-        nodemap_size = round_up(sizeof(s16) * memnodemapsize, L1_CACHE_BYTES);
+        nodemap_size = roundup(sizeof(s16) * memnodemapsize, L1_CACHE_BYTES);
         nodemap_addr = find_e820_area(addr, max_pfn<<PAGE_SHIFT,
                                       nodemap_size, L1_CACHE_BYTES);
         if (nodemap_addr == -1UL) {
@@ -176,10 +176,10 @@ void __init setup_node_bootmem(int nodeid, unsigned long start,
         unsigned long start_pfn, last_pfn, bootmap_pages, bootmap_size;
         unsigned long bootmap_start, nodedata_phys;
         void *bootmap;
-        const int pgdat_size = round_up(sizeof(pg_data_t), PAGE_SIZE);
+        const int pgdat_size = roundup(sizeof(pg_data_t), PAGE_SIZE);
         int nid;
 
-        start = round_up(start, ZONE_ALIGN);
+        start = roundup(start, ZONE_ALIGN);
 
         printk(KERN_INFO "Bootmem setup node %d %016lx-%016lx\n", nodeid,
                start, end);
@@ -210,9 +210,9 @@ void __init setup_node_bootmem(int nodeid, unsigned long start,
         bootmap_pages = bootmem_bootmap_pages(last_pfn - start_pfn);
         nid = phys_to_nid(nodedata_phys);
         if (nid == nodeid)
-                bootmap_start = round_up(nodedata_phys + pgdat_size, PAGE_SIZE);
+                bootmap_start = roundup(nodedata_phys + pgdat_size, PAGE_SIZE);
         else
-                bootmap_start = round_up(start, PAGE_SIZE);
+                bootmap_start = roundup(start, PAGE_SIZE);
         /*
          * SMP_CACHE_BYTES could be enough, but init_bootmem_node like
          * to use that to align to PAGE_SIZE
diff --git a/arch/x86/mm/pageattr-test.c b/arch/x86/mm/pageattr-test.c
index d4aa503caaa2..e1d106909218 100644
--- a/arch/x86/mm/pageattr-test.c
+++ b/arch/x86/mm/pageattr-test.c
@@ -32,7 +32,7 @@ enum {
         GPS                     = (1<<30)
 };
 
-#define PAGE_TESTBIT    __pgprot(_PAGE_UNUSED1)
+#define PAGE_CPA_TEST   __pgprot(_PAGE_CPA_TEST)
 
 static int pte_testbit(pte_t pte)
 {
@@ -118,6 +118,7 @@ static int pageattr_test(void)
         unsigned int level;
         int i, k;
         int err;
+        unsigned long test_addr;
 
         if (print)
                 printk(KERN_INFO "CPA self-test:\n");
@@ -172,7 +173,8 @@ static int pageattr_test(void)
                         continue;
                 }
 
-                err = change_page_attr_set(addr[i], len[i], PAGE_TESTBIT);
+                test_addr = addr[i];
+                err = change_page_attr_set(&test_addr, len[i], PAGE_CPA_TEST, 0);
                 if (err < 0) {
                         printk(KERN_ERR "CPA %d failed %d\n", i, err);
                         failed++;
@@ -204,7 +206,8 @@ static int pageattr_test(void)
                         failed++;
                         continue;
                 }
-                err = change_page_attr_clear(addr[i], len[i], PAGE_TESTBIT);
+                test_addr = addr[i];
+                err = change_page_attr_clear(&test_addr, len[i], PAGE_CPA_TEST, 0);
                 if (err < 0) {
                         printk(KERN_ERR "CPA reverting failed: %d\n", err);
                         failed++;
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 43e2f8483e4f..a9ec89c3fbca 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -25,15 +25,27 @@
  * The current flushing context - we pass it instead of 5 arguments:
  */
 struct cpa_data {
-        unsigned long   vaddr;
+        unsigned long   *vaddr;
         pgprot_t        mask_set;
         pgprot_t        mask_clr;
         int             numpages;
-        int             flushtlb;
+        int             flags;
         unsigned long   pfn;
         unsigned        force_split : 1;
+        int             curpage;
 };
 
+/*
+ * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
+ * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
+ * entries change the page attribute in parallel to some other cpu
+ * splitting a large page entry along with changing the attribute.
+ */
+static DEFINE_SPINLOCK(cpa_lock);
+
+#define CPA_FLUSHTLB 1
+#define CPA_ARRAY 2
+
 #ifdef CONFIG_PROC_FS
 static unsigned long direct_pages_count[PG_LEVEL_NUM];
 
@@ -84,7 +96,7 @@ static inline unsigned long highmap_start_pfn(void)
 
 static inline unsigned long highmap_end_pfn(void)
 {
-        return __pa(round_up((unsigned long)_end, PMD_SIZE)) >> PAGE_SHIFT;
+        return __pa(roundup((unsigned long)_end, PMD_SIZE)) >> PAGE_SHIFT;
 }
 
 #endif
@@ -190,6 +202,41 @@ static void cpa_flush_range(unsigned long start, int numpages, int cache)
         }
 }
 
+static void cpa_flush_array(unsigned long *start, int numpages, int cache)
+{
+        unsigned int i, level;
+        unsigned long *addr;
+
+        BUG_ON(irqs_disabled());
+
+        on_each_cpu(__cpa_flush_range, NULL, 1);
+
+        if (!cache)
+                return;
+
+        /* 4M threshold */
+        if (numpages >= 1024) {
+                if (boot_cpu_data.x86_model >= 4)
+                        wbinvd();
+                return;
+        }
+        /*
+         * We only need to flush on one CPU,
+         * clflush is a MESI-coherent instruction that
+         * will cause all other CPUs to flush the same
+         * cachelines:
+         */
+        for (i = 0, addr = start; i < numpages; i++, addr++) {
+                pte_t *pte = lookup_address(*addr, &level);
+
+                /*
+                 * Only flush present addresses:
+                 */
+                if (pte && (pte_val(*pte) & _PAGE_PRESENT))
+                        clflush_cache_range((void *) *addr, PAGE_SIZE);
+        }
+}
+
 /*
  * Certain areas of memory on x86 require very specific protection flags,
  * for example the BIOS area or kernel text. Callers don't always get this
@@ -398,7 +445,7 @@ try_preserve_large_page(pte_t *kpte, unsigned long address,
                  */
                 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
                 __set_pmd_pte(kpte, address, new_pte);
-                cpa->flushtlb = 1;
+                cpa->flags |= CPA_FLUSHTLB;
                 do_split = 0;
         }
 
@@ -408,84 +455,6 @@ out_unlock:
         return do_split;
 }
 
-static LIST_HEAD(page_pool);
-static unsigned long pool_size, pool_pages, pool_low;
-static unsigned long pool_used, pool_failed;
-
-static void cpa_fill_pool(struct page **ret)
-{
-        gfp_t gfp = GFP_KERNEL;
-        unsigned long flags;
-        struct page *p;
-
-        /*
-         * Avoid recursion (on debug-pagealloc) and also signal
-         * our priority to get to these pagetables:
-         */
-        if (current->flags & PF_MEMALLOC)
-                return;
-        current->flags |= PF_MEMALLOC;
-
-        /*
-         * Allocate atomically from atomic contexts:
-         */
-        if (in_atomic() || irqs_disabled() || debug_pagealloc)
-                gfp =  GFP_ATOMIC | __GFP_NORETRY | __GFP_NOWARN;
-
-        while (pool_pages < pool_size || (ret && !*ret)) {
-                p = alloc_pages(gfp, 0);
-                if (!p) {
-                        pool_failed++;
-                        break;
-                }
-                /*
-                 * If the call site needs a page right now, provide it:
-                 */
-                if (ret && !*ret) {
-                        *ret = p;
-                        continue;
-                }
-                spin_lock_irqsave(&pgd_lock, flags);
-                list_add(&p->lru, &page_pool);
-                pool_pages++;
-                spin_unlock_irqrestore(&pgd_lock, flags);
-        }
-
-        current->flags &= ~PF_MEMALLOC;
-}
-
-#define SHIFT_MB                (20 - PAGE_SHIFT)
-#define ROUND_MB_GB             ((1 << 10) - 1)
-#define SHIFT_MB_GB             10
-#define POOL_PAGES_PER_GB       16
-
-void __init cpa_init(void)
-{
-        struct sysinfo si;
-        unsigned long gb;
-
-        si_meminfo(&si);
-        /*
-         * Calculate the number of pool pages:
-         *
-         * Convert totalram (nr of pages) to MiB and round to the next
-         * GiB. Shift MiB to Gib and multiply the result by
-         * POOL_PAGES_PER_GB:
-         */
-        if (debug_pagealloc) {
-                gb = ((si.totalram >> SHIFT_MB) + ROUND_MB_GB) >> SHIFT_MB_GB;
-                pool_size = POOL_PAGES_PER_GB * gb;
-        } else {
-                pool_size = 1;
-        }
-        pool_low = pool_size;
-
-        cpa_fill_pool(NULL);
-        printk(KERN_DEBUG
-               "CPA: page pool initialized %lu of %lu pages preallocated\n",
-               pool_pages, pool_size);
-}
-
 static int split_large_page(pte_t *kpte, unsigned long address)
 {
         unsigned long flags, pfn, pfninc = 1;
@@ -494,28 +463,15 @@ static int split_large_page(pte_t *kpte, unsigned long address)
         pgprot_t ref_prot;
         struct page *base;
 
-        /*
-         * Get a page from the pool. The pool list is protected by the
-         * pgd_lock, which we have to take anyway for the split
-         * operation:
-         */
-        spin_lock_irqsave(&pgd_lock, flags);
-        if (list_empty(&page_pool)) {
-                spin_unlock_irqrestore(&pgd_lock, flags);
-                base = NULL;
-                cpa_fill_pool(&base);
-                if (!base)
-                        return -ENOMEM;
-                spin_lock_irqsave(&pgd_lock, flags);
-        } else {
-                base = list_first_entry(&page_pool, struct page, lru);
-                list_del(&base->lru);
-                pool_pages--;
-
-                if (pool_pages < pool_low)
-                        pool_low = pool_pages;
-        }
+        if (!debug_pagealloc)
+                spin_unlock(&cpa_lock);
+        base = alloc_pages(GFP_KERNEL, 0);
+        if (!debug_pagealloc)
+                spin_lock(&cpa_lock);
+        if (!base)
+                return -ENOMEM;
 
+        spin_lock_irqsave(&pgd_lock, flags);
         /*
          * Check for races, another CPU might have split this page
          * up for us already:
@@ -572,11 +528,8 @@ out_unlock:
          * If we dropped out via the lookup_address check under
          * pgd_lock then stick the page back into the pool:
          */
-        if (base) {
-                list_add(&base->lru, &page_pool);
-                pool_pages++;
-        } else
-                pool_used++;
+        if (base)
+                __free_page(base);
         spin_unlock_irqrestore(&pgd_lock, flags);
 
         return 0;
@@ -584,11 +537,16 @@ out_unlock:
 
 static int __change_page_attr(struct cpa_data *cpa, int primary)
 {
-        unsigned long address = cpa->vaddr;
+        unsigned long address;
         int do_split, err;
         unsigned int level;
         pte_t *kpte, old_pte;
 
+        if (cpa->flags & CPA_ARRAY)
+                address = cpa->vaddr[cpa->curpage];
+        else
+                address = *cpa->vaddr;
+
 repeat:
         kpte = lookup_address(address, &level);
         if (!kpte)
@@ -600,7 +558,7 @@ repeat:
                         return 0;
                 WARN(1, KERN_WARNING "CPA: called for zero pte. "
                        "vaddr = %lx cpa->vaddr = %lx\n", address,
-                       cpa->vaddr);
+                       *cpa->vaddr);
                 return -EINVAL;
         }
 
@@ -626,7 +584,7 @@ repeat:
                  */
                 if (pte_val(old_pte) != pte_val(new_pte)) {
                         set_pte_atomic(kpte, new_pte);
-                        cpa->flushtlb = 1;
+                        cpa->flags |= CPA_FLUSHTLB;
                 }
                 cpa->numpages = 1;
                 return 0;
@@ -650,7 +608,25 @@ repeat:
          */
         err = split_large_page(kpte, address);
         if (!err) {
-                cpa->flushtlb = 1;
+                /*
+                 * Do a global flush tlb after splitting the large page
+                 * and before we do the actual change page attribute in the PTE.
+                 *
+                 * With out this, we violate the TLB application note, that says
+                 * "The TLBs may contain both ordinary and large-page
+                 *  translations for a 4-KByte range of linear addresses. This
+                 *  may occur if software modifies the paging structures so that
+                 *  the page size used for the address range changes. If the two
+                 *  translations differ with respect to page frame or attributes
+                 *  (e.g., permissions), processor behavior is undefined and may
+                 *  be implementation-specific."
+                 *
+                 * We do this global tlb flush inside the cpa_lock, so that we
+                 * don't allow any other cpu, with stale tlb entries change the
+                 * page attribute in parallel, that also falls into the
+                 * just split large page entry.
+                 */
+                flush_tlb_all();
                 goto repeat;
         }
 
@@ -663,6 +639,7 @@ static int cpa_process_alias(struct cpa_data *cpa)
 {
         struct cpa_data alias_cpa;
         int ret = 0;
+        unsigned long temp_cpa_vaddr, vaddr;
 
         if (cpa->pfn >= max_pfn_mapped)
                 return 0;
@@ -675,16 +652,24 @@ static int cpa_process_alias(struct cpa_data *cpa)
          * No need to redo, when the primary call touched the direct
          * mapping already:
          */
-        if (!(within(cpa->vaddr, PAGE_OFFSET,
+        if (cpa->flags & CPA_ARRAY)
+                vaddr = cpa->vaddr[cpa->curpage];
+        else
+                vaddr = *cpa->vaddr;
+
+        if (!(within(vaddr, PAGE_OFFSET,
                     PAGE_OFFSET + (max_low_pfn_mapped << PAGE_SHIFT))
 #ifdef CONFIG_X86_64
-                || within(cpa->vaddr, PAGE_OFFSET + (1UL<<32),
+                || within(vaddr, PAGE_OFFSET + (1UL<<32),
                     PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))
 #endif
         )) {
 
                 alias_cpa = *cpa;
-                alias_cpa.vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT);
+                temp_cpa_vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT);
+                alias_cpa.vaddr = &temp_cpa_vaddr;
+                alias_cpa.flags &= ~CPA_ARRAY;
+
 
                 ret = __change_page_attr_set_clr(&alias_cpa, 0);
         }
@@ -696,7 +681,7 @@ static int cpa_process_alias(struct cpa_data *cpa)
          * No need to redo, when the primary call touched the high
          * mapping already:
          */
-        if (within(cpa->vaddr, (unsigned long) _text, (unsigned long) _end))
+        if (within(vaddr, (unsigned long) _text, (unsigned long) _end))
                 return 0;
 
         /*
@@ -707,8 +692,9 @@ static int cpa_process_alias(struct cpa_data *cpa)
                 return 0;
 
         alias_cpa = *cpa;
-        alias_cpa.vaddr =
-                (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base;
+        temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base;
+        alias_cpa.vaddr = &temp_cpa_vaddr;
+        alias_cpa.flags &= ~CPA_ARRAY;
 
         /*
          * The high mapping range is imprecise, so ignore the return value.
@@ -728,8 +714,15 @@ static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
                  * preservation check.
                  */
                 cpa->numpages = numpages;
+                /* for array changes, we can't use large page */
+                if (cpa->flags & CPA_ARRAY)
+                        cpa->numpages = 1;
 
+                if (!debug_pagealloc)
+                        spin_lock(&cpa_lock);
                 ret = __change_page_attr(cpa, checkalias);
+                if (!debug_pagealloc)
+                        spin_unlock(&cpa_lock);
                 if (ret)
                         return ret;
 
@@ -746,7 +739,11 @@ static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
                  */
                 BUG_ON(cpa->numpages > numpages);
                 numpages -= cpa->numpages;
-                cpa->vaddr += cpa->numpages * PAGE_SIZE;
+                if (cpa->flags & CPA_ARRAY)
+                        cpa->curpage++;
+                else
+                        *cpa->vaddr += cpa->numpages * PAGE_SIZE;
+
         }
         return 0;
 }
@@ -757,9 +754,9 @@ static inline int cache_attr(pgprot_t attr)
                 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
 }
 
-static int change_page_attr_set_clr(unsigned long addr, int numpages,
+static int change_page_attr_set_clr(unsigned long *addr, int numpages,
                                     pgprot_t mask_set, pgprot_t mask_clr,
-                                    int force_split)
+                                    int force_split, int array)
 {
         struct cpa_data cpa;
         int ret, cache, checkalias;
@@ -774,21 +771,38 @@ static int change_page_attr_set_clr(unsigned long addr, int numpages,
                 return 0;
 
         /* Ensure we are PAGE_SIZE aligned */
-        if (addr & ~PAGE_MASK) {
-                addr &= PAGE_MASK;
-                /*
-                 * People should not be passing in unaligned addresses:
-                 */
-                WARN_ON_ONCE(1);
+        if (!array) {
+                if (*addr & ~PAGE_MASK) {
+                        *addr &= PAGE_MASK;
+                        /*
+                         * People should not be passing in unaligned addresses:
+                         */
+                        WARN_ON_ONCE(1);
+                }
+        } else {
+                int i;
+                for (i = 0; i < numpages; i++) {
+                        if (addr[i] & ~PAGE_MASK) {
+                                addr[i] &= PAGE_MASK;
+                                WARN_ON_ONCE(1);
+                        }
+                }
         }
 
+        /* Must avoid aliasing mappings in the highmem code */
+        kmap_flush_unused();
+
         cpa.vaddr = addr;
         cpa.numpages = numpages;
         cpa.mask_set = mask_set;
         cpa.mask_clr = mask_clr;
-        cpa.flushtlb = 0;
+        cpa.flags = 0;
+        cpa.curpage = 0;
         cpa.force_split = force_split;
 
+        if (array)
+                cpa.flags |= CPA_ARRAY;
+
         /* No alias checking for _NX bit modifications */
         checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
 
@@ -797,7 +811,7 @@ static int change_page_attr_set_clr(unsigned long addr, int numpages,
         /*
          * Check whether we really changed something:
          */
-        if (!cpa.flushtlb)
+        if (!(cpa.flags & CPA_FLUSHTLB))
                 goto out;
 
         /*
@@ -812,27 +826,30 @@ static int change_page_attr_set_clr(unsigned long addr, int numpages,
          * error case we fall back to cpa_flush_all (which uses
          * wbindv):
          */
-        if (!ret && cpu_has_clflush)
-                cpa_flush_range(addr, numpages, cache);
-        else
+        if (!ret && cpu_has_clflush) {
+                if (cpa.flags & CPA_ARRAY)
+                        cpa_flush_array(addr, numpages, cache);
+                else
+                        cpa_flush_range(*addr, numpages, cache);
+        } else
                 cpa_flush_all(cache);
 
 out:
-        cpa_fill_pool(NULL);
-
         return ret;
 }
 
-static inline int change_page_attr_set(unsigned long addr, int numpages,
-                                       pgprot_t mask)
+static inline int change_page_attr_set(unsigned long *addr, int numpages,
+                                       pgprot_t mask, int array)
 {
-        return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0);
+        return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
+                array);
 }
 
-static inline int change_page_attr_clear(unsigned long addr, int numpages,
-                                         pgprot_t mask)
+static inline int change_page_attr_clear(unsigned long *addr, int numpages,
+                                         pgprot_t mask, int array)
 {
-        return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0);
+        return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
+                array);
 }
 
 int _set_memory_uc(unsigned long addr, int numpages)
@@ -840,8 +857,8 @@ int _set_memory_uc(unsigned long addr, int numpages)
         /*
          * for now UC MINUS. see comments in ioremap_nocache()
          */
-        return change_page_attr_set(addr, numpages,
-                                    __pgprot(_PAGE_CACHE_UC_MINUS));
+        return change_page_attr_set(&addr, numpages,
+                                    __pgprot(_PAGE_CACHE_UC_MINUS), 0);
 }
 
 int set_memory_uc(unsigned long addr, int numpages)
@@ -857,10 +874,48 @@ int set_memory_uc(unsigned long addr, int numpages)
 }
 EXPORT_SYMBOL(set_memory_uc);
 
+int set_memory_array_uc(unsigned long *addr, int addrinarray)
+{
+        unsigned long start;
+        unsigned long end;
+        int i;
+        /*
+         * for now UC MINUS. see comments in ioremap_nocache()
+         */
+        for (i = 0; i < addrinarray; i++) {
+                start = __pa(addr[i]);
+                for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) {
+                        if (end != __pa(addr[i + 1]))
+                                break;
+                        i++;
+                }
+                if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL))
+                        goto out;
+        }
+
+        return change_page_attr_set(addr, addrinarray,
+                                    __pgprot(_PAGE_CACHE_UC_MINUS), 1);
+out:
+        for (i = 0; i < addrinarray; i++) {
+                unsigned long tmp = __pa(addr[i]);
+
+                if (tmp == start)
+                        break;
+                for (end = tmp + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) {
+                        if (end != __pa(addr[i + 1]))
+                                break;
+                        i++;
+                }
+                free_memtype(tmp, end);
+        }
+        return -EINVAL;
+}
+EXPORT_SYMBOL(set_memory_array_uc);
+
 int _set_memory_wc(unsigned long addr, int numpages)
 {
-        return change_page_attr_set(addr, numpages,
-                                    __pgprot(_PAGE_CACHE_WC));
+        return change_page_attr_set(&addr, numpages,
+                                    __pgprot(_PAGE_CACHE_WC), 0);
 }
 
 int set_memory_wc(unsigned long addr, int numpages)
@@ -878,8 +933,8 @@ EXPORT_SYMBOL(set_memory_wc);
 
 int _set_memory_wb(unsigned long addr, int numpages)
 {
-        return change_page_attr_clear(addr, numpages,
-                                      __pgprot(_PAGE_CACHE_MASK));
+        return change_page_attr_clear(&addr, numpages,
+                                      __pgprot(_PAGE_CACHE_MASK), 0);
 }
 
 int set_memory_wb(unsigned long addr, int numpages)
@@ -890,37 +945,59 @@ int set_memory_wb(unsigned long addr, int numpages)
 }
 EXPORT_SYMBOL(set_memory_wb);
 
+int set_memory_array_wb(unsigned long *addr, int addrinarray)
+{
+        int i;
+
+        for (i = 0; i < addrinarray; i++) {
+                unsigned long start = __pa(addr[i]);
+                unsigned long end;
+
+                for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) {
+                        if (end != __pa(addr[i + 1]))
+                                break;
+                        i++;
+                }
+                free_memtype(start, end);
+        }
+        return change_page_attr_clear(addr, addrinarray,
+                                      __pgprot(_PAGE_CACHE_MASK), 1);
+}
+EXPORT_SYMBOL(set_memory_array_wb);
+
 int set_memory_x(unsigned long addr, int numpages)
 {
-        return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX));
+        return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
 }
 EXPORT_SYMBOL(set_memory_x);
 
 int set_memory_nx(unsigned long addr, int numpages)
 {
-        return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX));
+        return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
 }
 EXPORT_SYMBOL(set_memory_nx);
 
 int set_memory_ro(unsigned long addr, int numpages)
 {
-        return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW));
+        return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
 }
+EXPORT_SYMBOL_GPL(set_memory_ro);
 
 int set_memory_rw(unsigned long addr, int numpages)
 {
-        return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW));
+        return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
 }
+EXPORT_SYMBOL_GPL(set_memory_rw);
 
 int set_memory_np(unsigned long addr, int numpages)
 {
-        return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT));
+        return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
 }
 
 int set_memory_4k(unsigned long addr, int numpages)
 {
-        return change_page_attr_set_clr(addr, numpages, __pgprot(0),
-                                        __pgprot(0), 1);
+        return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
+                                        __pgprot(0), 1, 0);
 }
 
 int set_pages_uc(struct page *page, int numpages)
@@ -973,22 +1050,38 @@ int set_pages_rw(struct page *page, int numpages)
 
 static int __set_pages_p(struct page *page, int numpages)
 {
-        struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page),
+        unsigned long tempaddr = (unsigned long) page_address(page);
+        struct cpa_data cpa = { .vaddr = &tempaddr,
                                 .numpages = numpages,
                                 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
-                                .mask_clr = __pgprot(0)};
+                                .mask_clr = __pgprot(0),
+                                .flags = 0};
 
-        return __change_page_attr_set_clr(&cpa, 1);
+        /*
+         * No alias checking needed for setting present flag. otherwise,
+         * we may need to break large pages for 64-bit kernel text
+         * mappings (this adds to complexity if we want to do this from
+         * atomic context especially). Let's keep it simple!
+         */
+        return __change_page_attr_set_clr(&cpa, 0);
 }
 
 static int __set_pages_np(struct page *page, int numpages)
 {
-        struct cpa_data cpa = { .vaddr = (unsigned long) page_address(page),
+        unsigned long tempaddr = (unsigned long) page_address(page);
+        struct cpa_data cpa = { .vaddr = &tempaddr,
                                 .numpages = numpages,
                                 .mask_set = __pgprot(0),
-                                .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW)};
+                                .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
+                                .flags = 0};
 
-        return __change_page_attr_set_clr(&cpa, 1);
+        /*
+         * No alias checking needed for setting not present flag. otherwise,
+         * we may need to break large pages for 64-bit kernel text
+         * mappings (this adds to complexity if we want to do this from
+         * atomic context especially). Let's keep it simple!
+         */
+        return __change_page_attr_set_clr(&cpa, 0);
 }
 
 void kernel_map_pages(struct page *page, int numpages, int enable)
@@ -1008,11 +1101,8 @@ void kernel_map_pages(struct page *page, int numpages, int enable)
 
         /*
          * The return value is ignored as the calls cannot fail.
-         * Large pages are kept enabled at boot time, and are
-         * split up quickly with DEBUG_PAGEALLOC. If a splitup
-         * fails here (due to temporary memory shortage) no damage
-         * is done because we just keep the largepage intact up
-         * to the next attempt when it will likely be split up:
+         * Large pages for identity mappings are not used at boot time
+         * and hence no memory allocations during large page split.
          */
         if (enable)
                 __set_pages_p(page, numpages);
@@ -1024,53 +1114,8 @@ void kernel_map_pages(struct page *page, int numpages, int enable)
          * but that can deadlock->flush only current cpu:
          */
         __flush_tlb_all();
-
-        /*
-         * Try to refill the page pool here. We can do this only after
-         * the tlb flush.
-         */
-        cpa_fill_pool(NULL);
 }
 
-#ifdef CONFIG_DEBUG_FS
-static int dpa_show(struct seq_file *m, void *v)
-{
-        seq_puts(m, "DEBUG_PAGEALLOC\n");
-        seq_printf(m, "pool_size     : %lu\n", pool_size);
-        seq_printf(m, "pool_pages    : %lu\n", pool_pages);
-        seq_printf(m, "pool_low      : %lu\n", pool_low);
-        seq_printf(m, "pool_used     : %lu\n", pool_used);
-        seq_printf(m, "pool_failed   : %lu\n", pool_failed);
-
-        return 0;
-}
-
-static int dpa_open(struct inode *inode, struct file *filp)
-{
-        return single_open(filp, dpa_show, NULL);
-}
-
-static const struct file_operations dpa_fops = {
-        .open           = dpa_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int __init debug_pagealloc_proc_init(void)
-{
-        struct dentry *de;
-
-        de = debugfs_create_file("debug_pagealloc", 0600, NULL, NULL,
-                                 &dpa_fops);
-        if (!de)
-                return -ENOMEM;
-
-        return 0;
-}
-__initcall(debug_pagealloc_proc_init);
-#endif
-
 #ifdef CONFIG_HIBERNATION
 
 bool kernel_page_present(struct page *page)
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index 2a50e0fa64a5..738fd0f24958 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -7,24 +7,24 @@
  * Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen.
  */
 
-#include <linux/mm.h>
+#include <linux/seq_file.h>
+#include <linux/bootmem.h>
+#include <linux/debugfs.h>
 #include <linux/kernel.h>
 #include <linux/gfp.h>
+#include <linux/mm.h>
 #include <linux/fs.h>
-#include <linux/bootmem.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
 
-#include <asm/msr.h>
-#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
 #include <asm/processor.h>
-#include <asm/page.h>
+#include <asm/tlbflush.h>
 #include <asm/pgtable.h>
-#include <asm/pat.h>
-#include <asm/e820.h>
-#include <asm/cacheflush.h>
 #include <asm/fcntl.h>
+#include <asm/e820.h>
 #include <asm/mtrr.h>
+#include <asm/page.h>
+#include <asm/msr.h>
+#include <asm/pat.h>
 #include <asm/io.h>
 
 #ifdef CONFIG_X86_PAT
@@ -46,6 +46,7 @@ early_param("nopat", nopat);
 
 
 static int debug_enable;
+
 static int __init pat_debug_setup(char *str)
 {
         debug_enable = 1;
@@ -145,14 +146,14 @@ static char *cattr_name(unsigned long flags)
  */
 
 struct memtype {
-        u64 start;
-        u64 end;
-        unsigned long type;
-        struct list_head nd;
+        u64                     start;
+        u64                     end;
+        unsigned long           type;
+        struct list_head        nd;
 };
 
 static LIST_HEAD(memtype_list);
-static DEFINE_SPINLOCK(memtype_lock);   /* protects memtype list */
+static DEFINE_SPINLOCK(memtype_lock);   /* protects memtype list */
 
 /*
  * Does intersection of PAT memory type and MTRR memory type and returns
@@ -180,8 +181,8 @@ static unsigned long pat_x_mtrr_type(u64 start, u64 end, unsigned long req_type)
         return req_type;
 }
 
-static int chk_conflict(struct memtype *new, struct memtype *entry,
-                        unsigned long *type)
+static int
+chk_conflict(struct memtype *new, struct memtype *entry, unsigned long *type)
 {
         if (new->type != entry->type) {
                 if (type) {
@@ -211,6 +212,66 @@ static struct memtype *cached_entry;
 static u64 cached_start;
 
 /*
+ * For RAM pages, mark the pages as non WB memory type using
+ * PageNonWB (PG_arch_1). We allow only one set_memory_uc() or
+ * set_memory_wc() on a RAM page at a time before marking it as WB again.
+ * This is ok, because only one driver will be owning the page and
+ * doing set_memory_*() calls.
+ *
+ * For now, we use PageNonWB to track that the RAM page is being mapped
+ * as non WB. In future, we will have to use one more flag
+ * (or some other mechanism in page_struct) to distinguish between
+ * UC and WC mapping.
+ */
+static int reserve_ram_pages_type(u64 start, u64 end, unsigned long req_type,
+                                  unsigned long *new_type)
+{
+        struct page *page;
+        u64 pfn, end_pfn;
+
+        for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) {
+                page = pfn_to_page(pfn);
+                if (page_mapped(page) || PageNonWB(page))
+                        goto out;
+
+                SetPageNonWB(page);
+        }
+        return 0;
+
+out:
+        end_pfn = pfn;
+        for (pfn = (start >> PAGE_SHIFT); pfn < end_pfn; ++pfn) {
+                page = pfn_to_page(pfn);
+                ClearPageNonWB(page);
+        }
+
+        return -EINVAL;
+}
+
+static int free_ram_pages_type(u64 start, u64 end)
+{
+        struct page *page;
+        u64 pfn, end_pfn;
+
+        for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) {
+                page = pfn_to_page(pfn);
+                if (page_mapped(page) || !PageNonWB(page))
+                        goto out;
+
+                ClearPageNonWB(page);
+        }
+        return 0;
+
+out:
+        end_pfn = pfn;
+        for (pfn = (start >> PAGE_SHIFT); pfn < end_pfn; ++pfn) {
+                page = pfn_to_page(pfn);
+                SetPageNonWB(page);
+        }
+        return -EINVAL;
+}
+
+/*
  * req_type typically has one of the:
  * - _PAGE_CACHE_WB
  * - _PAGE_CACHE_WC
@@ -226,14 +287,15 @@ static u64 cached_start;
  * it will return a negative return value.
  */
 int reserve_memtype(u64 start, u64 end, unsigned long req_type,
-                        unsigned long *new_type)
+                    unsigned long *new_type)
 {
         struct memtype *new, *entry;
         unsigned long actual_type;
         struct list_head *where;
+        int is_range_ram;
         int err = 0;
 
-        BUG_ON(start >= end); /* end is exclusive */
+        BUG_ON(start >= end); /* end is exclusive */
 
         if (!pat_enabled) {
                 /* This is identical to page table setting without PAT */
@@ -266,17 +328,24 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
                         actual_type = _PAGE_CACHE_WB;
                 else
                         actual_type = _PAGE_CACHE_UC_MINUS;
-        } else
+        } else {
                 actual_type = pat_x_mtrr_type(start, end,
                                               req_type & _PAGE_CACHE_MASK);
+        }
+
+        is_range_ram = pagerange_is_ram(start, end);
+        if (is_range_ram == 1)
+                return reserve_ram_pages_type(start, end, req_type, new_type);
+        else if (is_range_ram < 0)
+                return -EINVAL;
 
         new  = kmalloc(sizeof(struct memtype), GFP_KERNEL);
         if (!new)
                 return -ENOMEM;
 
-        new->start = start;
-        new->end = end;
-        new->type = actual_type;
+        new->start      = start;
+        new->end        = end;
+        new->type       = actual_type;
 
         if (new_type)
                 *new_type = actual_type;
@@ -335,6 +404,7 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
                        start, end, cattr_name(new->type), cattr_name(req_type));
                 kfree(new);
                 spin_unlock(&memtype_lock);
+
                 return err;
         }
 
@@ -358,6 +428,7 @@ int free_memtype(u64 start, u64 end)
 {
         struct memtype *entry;
         int err = -EINVAL;
+        int is_range_ram;
 
         if (!pat_enabled)
                 return 0;
@@ -366,6 +437,12 @@ int free_memtype(u64 start, u64 end)
         if (is_ISA_range(start, end - 1))
                 return 0;
 
+        is_range_ram = pagerange_is_ram(start, end);
+        if (is_range_ram == 1)
+                return free_ram_pages_type(start, end);
+        else if (is_range_ram < 0)
+                return -EINVAL;
+
         spin_lock(&memtype_lock);
         list_for_each_entry(entry, &memtype_list, nd) {
                 if (entry->start == start && entry->end == end) {
@@ -386,6 +463,7 @@ int free_memtype(u64 start, u64 end)
         }
 
         dprintk("free_memtype request 0x%Lx-0x%Lx\n", start, end);
+
         return err;
 }
 
@@ -492,9 +570,9 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
 
 void map_devmem(unsigned long pfn, unsigned long size, pgprot_t vma_prot)
 {
+        unsigned long want_flags = (pgprot_val(vma_prot) & _PAGE_CACHE_MASK);
         u64 addr = (u64)pfn << PAGE_SHIFT;
         unsigned long flags;
-        unsigned long want_flags = (pgprot_val(vma_prot) & _PAGE_CACHE_MASK);
 
         reserve_memtype(addr, addr + size, want_flags, &flags);
         if (flags != want_flags) {
@@ -514,7 +592,7 @@ void unmap_devmem(unsigned long pfn, unsigned long size, pgprot_t vma_prot)
         free_memtype(addr, addr + size);
 }
 
-#if defined(CONFIG_DEBUG_FS)
+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_X86_PAT)
 
 /* get Nth element of the linked list */
 static struct memtype *memtype_get_idx(loff_t pos)
@@ -537,6 +615,7 @@ static struct memtype *memtype_get_idx(loff_t pos)
         }
         spin_unlock(&memtype_lock);
         kfree(print_entry);
+
         return NULL;
 }
 
@@ -567,6 +646,7 @@ static int memtype_seq_show(struct seq_file *seq, void *v)
         seq_printf(seq, "%s @ 0x%Lx-0x%Lx\n", cattr_name(print_entry->type),
                         print_entry->start, print_entry->end);
         kfree(print_entry);
+
         return 0;
 }
 
@@ -598,4 +678,4 @@ static int __init pat_memtype_list_init(void)
 
 late_initcall(pat_memtype_list_init);
 
-#endif /* CONFIG_DEBUG_FS */
+#endif /* CONFIG_DEBUG_FS && CONFIG_X86_PAT */
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index d50302774fe2..86f2ffc43c3d 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -63,10 +63,8 @@ static inline void pgd_list_del(pgd_t *pgd)
 #define UNSHARED_PTRS_PER_PGD                           \
         (SHARED_KERNEL_PMD ? KERNEL_PGD_BOUNDARY : PTRS_PER_PGD)
 
-static void pgd_ctor(void *p)
+static void pgd_ctor(pgd_t *pgd)
 {
-        pgd_t *pgd = p;
-
         /* If the pgd points to a shared pagetable level (either the
            ptes in non-PAE, or shared PMD in PAE), then just copy the
            references from swapper_pg_dir. */
@@ -87,7 +85,7 @@ static void pgd_ctor(void *p)
                 pgd_list_add(pgd);
 }
 
-static void pgd_dtor(void *pgd)
+static void pgd_dtor(pgd_t *pgd)
 {
         unsigned long flags; /* can be called from interrupt context */
 
diff --git a/arch/x86/mm/pgtable_32.c b/arch/x86/mm/pgtable_32.c
index cab0abbd1ebe..0951db9ee519 100644
--- a/arch/x86/mm/pgtable_32.c
+++ b/arch/x86/mm/pgtable_32.c
@@ -123,7 +123,8 @@ static int __init parse_vmalloc(char *arg)
         if (!arg)
                 return -EINVAL;
 
-        __VMALLOC_RESERVE = memparse(arg, &arg);
+        /* Add VMALLOC_OFFSET to the parsed value due to vm area guard hole*/
+        __VMALLOC_RESERVE = memparse(arg, &arg) + VMALLOC_OFFSET;
         return 0;
 }
 early_param("vmalloc", parse_vmalloc);
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 0227694f7dab..8a5f1614a3d5 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -295,10 +295,12 @@ static void nmi_cpu_shutdown(void *dummy)
 
 static void nmi_shutdown(void)
 {
-        struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
+        struct op_msrs *msrs;
+
         nmi_enabled = 0;
         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
         unregister_die_notifier(&profile_exceptions_nb);
+        msrs = &get_cpu_var(cpu_msrs);
         model->shutdown(msrs);
         free_msrs();
         put_cpu_var(cpu_msrs);
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c
index 56b4757a1f47..43ac5af338d8 100644
--- a/arch/x86/oprofile/op_model_p4.c
+++ b/arch/x86/oprofile/op_model_p4.c
@@ -10,11 +10,12 @@
 
 #include <linux/oprofile.h>
 #include <linux/smp.h>
+#include <linux/ptrace.h>
+#include <linux/nmi.h>
 #include <asm/msr.h>
-#include <asm/ptrace.h>
 #include <asm/fixmap.h>
 #include <asm/apic.h>
-#include <asm/nmi.h>
+
 
 #include "op_x86_model.h"
 #include "op_counter.h"
@@ -40,7 +41,7 @@ static unsigned int num_controls = NUM_CONTROLS_NON_HT;
 static inline void setup_num_counters(void)
 {
 #ifdef CONFIG_SMP
-        if (smp_num_siblings == 2){
+        if (smp_num_siblings == 2) {
                 num_counters = NUM_COUNTERS_HT2;
                 num_controls = NUM_CONTROLS_HT2;
         }
@@ -86,7 +87,7 @@ struct p4_event_binding {
 #define CTR_FLAME_2    (1 << 6)
 #define CTR_IQ_5       (1 << 7)
 
-static struct p4_counter_binding p4_counters [NUM_COUNTERS_NON_HT] = {
+static struct p4_counter_binding p4_counters[NUM_COUNTERS_NON_HT] = {
         { CTR_BPU_0,   MSR_P4_BPU_PERFCTR0,   MSR_P4_BPU_CCCR0 },
         { CTR_MS_0,    MSR_P4_MS_PERFCTR0,    MSR_P4_MS_CCCR0 },
         { CTR_FLAME_0, MSR_P4_FLAME_PERFCTR0, MSR_P4_FLAME_CCCR0 },
@@ -97,32 +98,32 @@ static struct p4_counter_binding p4_counters [NUM_COUNTERS_NON_HT] = {
         { CTR_IQ_5,    MSR_P4_IQ_PERFCTR5,    MSR_P4_IQ_CCCR5 }
 };
 
-#define NUM_UNUSED_CCCRS        NUM_CCCRS_NON_HT - NUM_COUNTERS_NON_HT
+#define NUM_UNUSED_CCCRS (NUM_CCCRS_NON_HT - NUM_COUNTERS_NON_HT)
 
 /* p4 event codes in libop/op_event.h are indices into this table. */
 
 static struct p4_event_binding p4_events[NUM_EVENTS] = {
-        
+
         { /* BRANCH_RETIRED */
-                0x05, 0x06, 
+                0x05, 0x06,
                 { {CTR_IQ_4, MSR_P4_CRU_ESCR2},
                   {CTR_IQ_5, MSR_P4_CRU_ESCR3} }
         },
-        
+
         { /* MISPRED_BRANCH_RETIRED */
-                0x04, 0x03, 
+                0x04, 0x03,
                 { { CTR_IQ_4, MSR_P4_CRU_ESCR0},
                   { CTR_IQ_5, MSR_P4_CRU_ESCR1} }
         },
-        
+
         { /* TC_DELIVER_MODE */
                 0x01, 0x01,
-                { { CTR_MS_0, MSR_P4_TC_ESCR0},  
+                { { CTR_MS_0, MSR_P4_TC_ESCR0},
                   { CTR_MS_2, MSR_P4_TC_ESCR1} }
         },
-        
+
         { /* BPU_FETCH_REQUEST */
-                0x00, 0x03, 
+                0x00, 0x03,
                 { { CTR_BPU_0, MSR_P4_BPU_ESCR0},
                   { CTR_BPU_2, MSR_P4_BPU_ESCR1} }
         },
@@ -146,7 +147,7 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
         },
 
         { /* LOAD_PORT_REPLAY */
-                0x02, 0x04, 
+                0x02, 0x04,
                 { { CTR_FLAME_0, MSR_P4_SAAT_ESCR0},
                   { CTR_FLAME_2, MSR_P4_SAAT_ESCR1} }
         },
@@ -170,43 +171,43 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
         },
 
         { /* BSQ_CACHE_REFERENCE */
-                0x07, 0x0c, 
+                0x07, 0x0c,
                 { { CTR_BPU_0, MSR_P4_BSU_ESCR0},
                   { CTR_BPU_2, MSR_P4_BSU_ESCR1} }
         },
 
         { /* IOQ_ALLOCATION */
-                0x06, 0x03, 
+                0x06, 0x03,
                 { { CTR_BPU_0, MSR_P4_FSB_ESCR0},
                   { 0, 0 } }
         },
 
         { /* IOQ_ACTIVE_ENTRIES */
-                0x06, 0x1a, 
+                0x06, 0x1a,
                 { { CTR_BPU_2, MSR_P4_FSB_ESCR1},
                   { 0, 0 } }
         },
 
         { /* FSB_DATA_ACTIVITY */
-                0x06, 0x17, 
+                0x06, 0x17,
                 { { CTR_BPU_0, MSR_P4_FSB_ESCR0},
                   { CTR_BPU_2, MSR_P4_FSB_ESCR1} }
         },
 
         { /* BSQ_ALLOCATION */
-                0x07, 0x05, 
+                0x07, 0x05,
                 { { CTR_BPU_0, MSR_P4_BSU_ESCR0},
                   { 0, 0 } }
         },
 
         { /* BSQ_ACTIVE_ENTRIES */
                 0x07, 0x06,
-                { { CTR_BPU_2, MSR_P4_BSU_ESCR1 /* guess */},  
+                { { CTR_BPU_2, MSR_P4_BSU_ESCR1 /* guess */},
                   { 0, 0 } }
         },
 
         { /* X87_ASSIST */
-                0x05, 0x03, 
+                0x05, 0x03,
                 { { CTR_IQ_4, MSR_P4_CRU_ESCR2},
                   { CTR_IQ_5, MSR_P4_CRU_ESCR3} }
         },
@@ -216,21 +217,21 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
                 { { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
                   { CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
         },
-  
+
         { /* PACKED_SP_UOP */
-                0x01, 0x08, 
+                0x01, 0x08,
                 { { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
                   { CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
         },
-  
+
         { /* PACKED_DP_UOP */
-                0x01, 0x0c, 
+                0x01, 0x0c,
                 { { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
                   { CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
         },
 
         { /* SCALAR_SP_UOP */
-                0x01, 0x0a, 
+                0x01, 0x0a,
                 { { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
                   { CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
         },
@@ -242,31 +243,31 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
         },
 
         { /* 64BIT_MMX_UOP */
-                0x01, 0x02, 
+                0x01, 0x02,
                 { { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
                   { CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
         },
-  
+
         { /* 128BIT_MMX_UOP */
-                0x01, 0x1a, 
+                0x01, 0x1a,
                 { { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
                   { CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
         },
 
         { /* X87_FP_UOP */
-                0x01, 0x04, 
+                0x01, 0x04,
                 { { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
                   { CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
         },
-  
+
         { /* X87_SIMD_MOVES_UOP */
-                0x01, 0x2e, 
+                0x01, 0x2e,
                 { { CTR_FLAME_0, MSR_P4_FIRM_ESCR0},
                   { CTR_FLAME_2, MSR_P4_FIRM_ESCR1} }
         },
-  
+
         { /* MACHINE_CLEAR */
-                0x05, 0x02, 
+                0x05, 0x02,
                 { { CTR_IQ_4, MSR_P4_CRU_ESCR2},
                   { CTR_IQ_5, MSR_P4_CRU_ESCR3} }
         },
@@ -276,9 +277,9 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
                 { { CTR_BPU_0, MSR_P4_FSB_ESCR0},
                   { CTR_BPU_2, MSR_P4_FSB_ESCR1} }
         },
-  
+
         { /* TC_MS_XFER */
-                0x00, 0x05, 
+                0x00, 0x05,
                 { { CTR_MS_0, MSR_P4_MS_ESCR0},
                   { CTR_MS_2, MSR_P4_MS_ESCR1} }
         },
@@ -308,7 +309,7 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
         },
 
         { /* INSTR_RETIRED */
-                0x04, 0x02, 
+                0x04, 0x02,
                 { { CTR_IQ_4, MSR_P4_CRU_ESCR0},
                   { CTR_IQ_5, MSR_P4_CRU_ESCR1} }
         },
@@ -319,14 +320,14 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
                   { CTR_IQ_5, MSR_P4_CRU_ESCR1} }
         },
 
-        { /* UOP_TYPE */    
-                0x02, 0x02, 
+        { /* UOP_TYPE */
+                0x02, 0x02,
                 { { CTR_IQ_4, MSR_P4_RAT_ESCR0},
                   { CTR_IQ_5, MSR_P4_RAT_ESCR1} }
         },
 
         { /* RETIRED_MISPRED_BRANCH_TYPE */
-                0x02, 0x05, 
+                0x02, 0x05,
                 { { CTR_MS_0, MSR_P4_TBPU_ESCR0},
                   { CTR_MS_2, MSR_P4_TBPU_ESCR1} }
         },
@@ -349,8 +350,8 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
 #define ESCR_SET_OS_1(escr, os) ((escr) |= (((os) & 1) << 1))
 #define ESCR_SET_EVENT_SELECT(escr, sel) ((escr) |= (((sel) & 0x3f) << 25))
 #define ESCR_SET_EVENT_MASK(escr, mask) ((escr) |= (((mask) & 0xffff) << 9))
-#define ESCR_READ(escr,high,ev,i) do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0)
-#define ESCR_WRITE(escr,high,ev,i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0)
+#define ESCR_READ(escr, high, ev, i) do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
+#define ESCR_WRITE(escr, high, ev, i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
 
 #define CCCR_RESERVED_BITS 0x38030FFF
 #define CCCR_CLEAR(cccr) ((cccr) &= CCCR_RESERVED_BITS)
@@ -360,15 +361,15 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
 #define CCCR_SET_PMI_OVF_1(cccr) ((cccr) |= (1<<27))
 #define CCCR_SET_ENABLE(cccr) ((cccr) |= (1<<12))
 #define CCCR_SET_DISABLE(cccr) ((cccr) &= ~(1<<12))
-#define CCCR_READ(low, high, i) do {rdmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
-#define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
+#define CCCR_READ(low, high, i) do {rdmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
+#define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
 #define CCCR_OVF_P(cccr) ((cccr) & (1U<<31))
 #define CCCR_CLEAR_OVF(cccr) ((cccr) &= (~(1U<<31)))
 
-#define CTRL_IS_RESERVED(msrs,c) (msrs->controls[(c)].addr ? 1 : 0)
-#define CTR_IS_RESERVED(msrs,c) (msrs->counters[(c)].addr ? 1 : 0)
-#define CTR_READ(l,h,i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h));} while (0)
-#define CTR_WRITE(l,i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1);} while (0)
+#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
+#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
+#define CTR_READ(l, h, i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h)); } while (0)
+#define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1); } while (0)
 #define CTR_OVERFLOW_P(ctr) (!((ctr) & 0x80000000))
 
 
@@ -380,7 +381,7 @@ static unsigned int get_stagger(void)
 #ifdef CONFIG_SMP
         int cpu = smp_processor_id();
         return (cpu != first_cpu(per_cpu(cpu_sibling_map, cpu)));
-#endif  
+#endif
         return 0;
 }
 
@@ -395,25 +396,23 @@ static unsigned long reset_value[NUM_COUNTERS_NON_HT];
 
 static void p4_fill_in_addresses(struct op_msrs * const msrs)
 {
-        unsigned int i; 
+        unsigned int i;
         unsigned int addr, cccraddr, stag;
 
         setup_num_counters();
         stag = get_stagger();
 
         /* initialize some registers */
-        for (i = 0; i < num_counters; ++i) {
+        for (i = 0; i < num_counters; ++i)
                 msrs->counters[i].addr = 0;
-        }
-        for (i = 0; i < num_controls; ++i) {
+        for (i = 0; i < num_controls; ++i)
                 msrs->controls[i].addr = 0;
-        }
-        
+
         /* the counter & cccr registers we pay attention to */
         for (i = 0; i < num_counters; ++i) {
                 addr = p4_counters[VIRT_CTR(stag, i)].counter_address;
                 cccraddr = p4_counters[VIRT_CTR(stag, i)].cccr_address;
-                if (reserve_perfctr_nmi(addr)){
+                if (reserve_perfctr_nmi(addr)) {
                         msrs->counters[i].addr = addr;
                         msrs->controls[i].addr = cccraddr;
                 }
@@ -447,22 +446,22 @@ static void p4_fill_in_addresses(struct op_msrs * const msrs)
                 if (reserve_evntsel_nmi(addr))
                         msrs->controls[i].addr = addr;
         }
-        
+
         for (addr = MSR_P4_MS_ESCR0 + stag;
-             addr <= MSR_P4_TC_ESCR1; ++i, addr += addr_increment()) { 
+             addr <= MSR_P4_TC_ESCR1; ++i, addr += addr_increment()) {
                 if (reserve_evntsel_nmi(addr))
                         msrs->controls[i].addr = addr;
         }
-        
+
         for (addr = MSR_P4_IX_ESCR0 + stag;
-             addr <= MSR_P4_CRU_ESCR3; ++i, addr += addr_increment()) { 
+             addr <= MSR_P4_CRU_ESCR3; ++i, addr += addr_increment()) {
                 if (reserve_evntsel_nmi(addr))
                         msrs->controls[i].addr = addr;
         }
 
         /* there are 2 remaining non-contiguously located ESCRs */
 
-        if (num_counters == NUM_COUNTERS_NON_HT) {              
+        if (num_counters == NUM_COUNTERS_NON_HT) {
                 /* standard non-HT CPUs handle both remaining ESCRs*/
                 if (reserve_evntsel_nmi(MSR_P4_CRU_ESCR5))
                         msrs->controls[i++].addr = MSR_P4_CRU_ESCR5;
@@ -498,20 +497,20 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
         unsigned int stag;
 
         stag = get_stagger();
-        
+
         /* convert from counter *number* to counter *bit* */
         counter_bit = 1 << VIRT_CTR(stag, ctr);
-        
+
         /* find our event binding structure. */
         if (counter_config[ctr].event <= 0 || counter_config[ctr].event > NUM_EVENTS) {
-                printk(KERN_ERR 
-                       "oprofile: P4 event code 0x%lx out of range\n", 
+                printk(KERN_ERR
+                       "oprofile: P4 event code 0x%lx out of range\n",
                        counter_config[ctr].event);
                 return;
         }
-        
+
         ev = &(p4_events[counter_config[ctr].event - 1]);
-        
+
         for (i = 0; i < maxbind; i++) {
                 if (ev->bindings[i].virt_counter & counter_bit) {
 
@@ -526,25 +525,24 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
                                 ESCR_SET_OS_1(escr, counter_config[ctr].kernel);
                         }
                         ESCR_SET_EVENT_SELECT(escr, ev->event_select);
-                        ESCR_SET_EVENT_MASK(escr, counter_config[ctr].unit_mask);                       
+                        ESCR_SET_EVENT_MASK(escr, counter_config[ctr].unit_mask);
                         ESCR_WRITE(escr, high, ev, i);
-                       
+
                         /* modify CCCR */
                         CCCR_READ(cccr, high, VIRT_CTR(stag, ctr));
                         CCCR_CLEAR(cccr);
                         CCCR_SET_REQUIRED_BITS(cccr);
                         CCCR_SET_ESCR_SELECT(cccr, ev->escr_select);
-                        if (stag == 0) {
+                        if (stag == 0)
                                 CCCR_SET_PMI_OVF_0(cccr);
-                        } else {
+                        else
                                 CCCR_SET_PMI_OVF_1(cccr);
-                        }
                         CCCR_WRITE(cccr, high, VIRT_CTR(stag, ctr));
                         return;
                 }
         }
 
-        printk(KERN_ERR 
+        printk(KERN_ERR
                "oprofile: P4 event code 0x%lx no binding, stag %d ctr %d\n",
                counter_config[ctr].event, stag, ctr);
 }
@@ -559,14 +557,14 @@ static void p4_setup_ctrs(struct op_msrs const * const msrs)
         stag = get_stagger();
 
         rdmsr(MSR_IA32_MISC_ENABLE, low, high);
-        if (! MISC_PMC_ENABLED_P(low)) {
+        if (!MISC_PMC_ENABLED_P(low)) {
                 printk(KERN_ERR "oprofile: P4 PMC not available\n");
                 return;
         }
 
         /* clear the cccrs we will use */
         for (i = 0 ; i < num_counters ; i++) {
-                if (unlikely(!CTRL_IS_RESERVED(msrs,i)))
+                if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
                         continue;
                 rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
                 CCCR_CLEAR(low);
@@ -576,14 +574,14 @@ static void p4_setup_ctrs(struct op_msrs const * const msrs)
 
         /* clear all escrs (including those outside our concern) */
         for (i = num_counters; i < num_controls; i++) {
-                if (unlikely(!CTRL_IS_RESERVED(msrs,i)))
+                if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
                         continue;
                 wrmsr(msrs->controls[i].addr, 0, 0);
         }
 
         /* setup all counters */
         for (i = 0 ; i < num_counters ; ++i) {
-                if ((counter_config[i].enabled) && (CTRL_IS_RESERVED(msrs,i))) {
+                if ((counter_config[i].enabled) && (CTRL_IS_RESERVED(msrs, i))) {
                         reset_value[i] = counter_config[i].count;
                         pmc_setup_one_p4_counter(i);
                         CTR_WRITE(counter_config[i].count, VIRT_CTR(stag, i));
@@ -603,11 +601,11 @@ static int p4_check_ctrs(struct pt_regs * const regs,
         stag = get_stagger();
 
         for (i = 0; i < num_counters; ++i) {
-                
-                if (!reset_value[i]) 
+
+                if (!reset_value[i])
                         continue;
 
-                /* 
+                /*
                  * there is some eccentricity in the hardware which
                  * requires that we perform 2 extra corrections:
                  *
@@ -616,24 +614,24 @@ static int p4_check_ctrs(struct pt_regs * const regs,
                  *
                  * - write the counter back twice to ensure it gets
                  *   updated properly.
-                 * 
+                 *
                  * the former seems to be related to extra NMIs happening
                  * during the current NMI; the latter is reported as errata
                  * N15 in intel doc 249199-029, pentium 4 specification
                  * update, though their suggested work-around does not
                  * appear to solve the problem.
                  */
-                
+
                 real = VIRT_CTR(stag, i);
 
                 CCCR_READ(low, high, real);
-                CTR_READ(ctr, high, real);
+                CTR_READ(ctr, high, real);
                 if (CCCR_OVF_P(low) || CTR_OVERFLOW_P(ctr)) {
                         oprofile_add_sample(regs, i);
-                        CTR_WRITE(reset_value[i], real);
+                        CTR_WRITE(reset_value[i], real);
                         CCCR_CLEAR_OVF(low);
                         CCCR_WRITE(low, high, real);
-                        CTR_WRITE(reset_value[i], real);
+                        CTR_WRITE(reset_value[i], real);
                 }
         }
 
@@ -683,15 +681,16 @@ static void p4_shutdown(struct op_msrs const * const msrs)
         int i;
 
         for (i = 0 ; i < num_counters ; ++i) {
-                if (CTR_IS_RESERVED(msrs,i))
+                if (CTR_IS_RESERVED(msrs, i))
                         release_perfctr_nmi(msrs->counters[i].addr);
         }
-        /* some of the control registers are specially reserved in
+        /*
+         * some of the control registers are specially reserved in
          * conjunction with the counter registers (hence the starting offset).
          * This saves a few bits.
          */
         for (i = num_counters ; i < num_controls ; ++i) {
-                if (CTRL_IS_RESERVED(msrs,i))
+                if (CTRL_IS_RESERVED(msrs, i))
                         release_evntsel_nmi(msrs->controls[i].addr);
         }
 }
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 19af06927fbc..1d88d2b39771 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -250,10 +250,5 @@ int __init pci_acpi_init(void)
                         acpi_pci_irq_enable(dev);
         }
 
-#ifdef CONFIG_X86_IO_APIC
-        if (acpi_ioapic)
-                print_IO_APIC();
-#endif
-
         return 0;
 }
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 6a0fca78c362..22e057665e55 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -580,7 +580,7 @@ static int __cpuinit amd_cpu_notify(struct notifier_block *self,
                                     unsigned long action, void *hcpu)
 {
         int cpu = (long)hcpu;
-        switch(action) {
+        switch (action) {
         case CPU_ONLINE:
         case CPU_ONLINE_FROZEN:
                 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 8791fc55e715..844df0cbbd3e 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -33,6 +33,7 @@
 #include <linux/bootmem.h>
 
 #include <asm/pat.h>
+#include <asm/e820.h>
 
 #include "pci.h"
 
@@ -227,6 +228,8 @@ void __init pcibios_resource_survey(void)
         pcibios_allocate_bus_resources(&pci_root_buses);
         pcibios_allocate_resources(0);
         pcibios_allocate_resources(1);
+
+        e820_reserve_resources_late();
 }
 
 /**
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 8e077185e185..006599db0dc7 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -1043,35 +1043,44 @@ static void __init pcibios_fixup_irqs(void)
                 if (io_apic_assign_pci_irqs) {
                         int irq;
 
-                        if (pin) {
-                                /*
-                                 * interrupt pins are numbered starting
-                                 * from 1
-                                 */
-                                pin--;
-                                irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
-                                        PCI_SLOT(dev->devfn), pin);
-        /*
-         * Busses behind bridges are typically not listed in the MP-table.
-         * In this case we have to look up the IRQ based on the parent bus,
-         * parent slot, and pin number. The SMP code detects such bridged
-         * busses itself so we should get into this branch reliably.
-         */
-                                if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
-                                        struct pci_dev *bridge = dev->bus->self;
-
-                                        pin = (pin + PCI_SLOT(dev->devfn)) % 4;
-                                        irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
-                                                        PCI_SLOT(bridge->devfn), pin);
-                                        if (irq >= 0)
-                                                dev_warn(&dev->dev, "using bridge %s INT %c to get IRQ %d\n",
-                                                         pci_name(bridge),
-                                                         'A' + pin, irq);
-                                }
-                                if (irq >= 0) {
-                                        dev_info(&dev->dev, "PCI->APIC IRQ transform: INT %c -> IRQ %d\n", 'A' + pin, irq);
-                                        dev->irq = irq;
-                                }
+                        if (!pin)
+                                continue;
+
+                        /*
+                         * interrupt pins are numbered starting from 1
+                         */
+                        pin--;
+                        irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
+                                PCI_SLOT(dev->devfn), pin);
+                        /*
+                         * Busses behind bridges are typically not listed in the
+                         * MP-table.  In this case we have to look up the IRQ
+                         * based on the parent bus, parent slot, and pin number.
+                         * The SMP code detects such bridged busses itself so we
+                         * should get into this branch reliably.
+                         */
+                        if (irq < 0 && dev->bus->parent) {
+                                /* go back to the bridge */
+                                struct pci_dev *bridge = dev->bus->self;
+                                int bus;
+
+                                pin = (pin + PCI_SLOT(dev->devfn)) % 4;
+                                bus = bridge->bus->number;
+                                irq = IO_APIC_get_PCI_irq_vector(bus,
+                                                PCI_SLOT(bridge->devfn), pin);
+                                if (irq >= 0)
+                                        dev_warn(&dev->dev,
+                                                "using bridge %s INT %c to "
+                                                        "get IRQ %d\n",
+                                                 pci_name(bridge),
+                                                 'A' + pin, irq);
+                        }
+                        if (irq >= 0) {
+                                dev_info(&dev->dev,
+                                        "PCI->APIC IRQ transform: INT %c "
+                                                "-> IRQ %d\n",
+                                        'A' + pin, irq);
+                                dev->irq = irq;
                         }
                 }
 #endif
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index d9635764ce3d..654a2234f8f3 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -209,7 +209,7 @@ static int __init pci_mmcfg_check_hostbridge(void)
         return name != NULL;
 }
 
-static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
+static void __init pci_mmcfg_insert_resources(void)
 {
 #define PCI_MMCFG_RESOURCE_NAME_LEN 19
         int i;
@@ -233,7 +233,7 @@ static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
                          cfg->pci_segment);
                 res->start = cfg->address;
                 res->end = res->start + (num_buses << 20) - 1;
-                res->flags = IORESOURCE_MEM | resource_flags;
+                res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
                 insert_resource(&iomem_resource, res);
                 names += PCI_MMCFG_RESOURCE_NAME_LEN;
         }
@@ -434,11 +434,9 @@ static void __init __pci_mmcfg_init(int early)
             (pci_mmcfg_config[0].address == 0))
                 return;
 
-        if (pci_mmcfg_arch_init()) {
-                if (known_bridge)
-                        pci_mmcfg_insert_resources(IORESOURCE_BUSY);
+        if (pci_mmcfg_arch_init())
                 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
-        } else {
+        else {
                 /*
                  * Signal not to attempt to insert mmcfg resources because
                  * the architecture mmcfg setup could not initialize.
@@ -475,7 +473,7 @@ static int __init pci_mmcfg_late_insert_resources(void)
          * marked so it won't cause request errors when __request_region is
          * called.
          */
-        pci_mmcfg_insert_resources(0);
+        pci_mmcfg_insert_resources();
 
         return 0;
 }
diff --git a/arch/x86/power/cpu_32.c b/arch/x86/power/cpu_32.c
index d3e083dea720..274d06082f48 100644
--- a/arch/x86/power/cpu_32.c
+++ b/arch/x86/power/cpu_32.c
@@ -11,6 +11,7 @@
 #include <linux/suspend.h>
 #include <asm/mtrr.h>
 #include <asm/mce.h>
+#include <asm/xcr.h>
 
 static struct saved_context saved_context;
 
@@ -126,6 +127,12 @@ static void __restore_processor_state(struct saved_context *ctxt)
         if (boot_cpu_has(X86_FEATURE_SEP))
                 enable_sep_cpu();
 
+        /*
+         * restore XCR0 for xsave capable cpu's.
+         */
+        if (cpu_has_xsave)
+                xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
+
         fix_processor_context();
         do_fpu_end();
         mtrr_ap_init();
diff --git a/arch/x86/power/cpu_64.c b/arch/x86/power/cpu_64.c
index 66bdfb591fd8..e3b6cf70d62c 100644
--- a/arch/x86/power/cpu_64.c
+++ b/arch/x86/power/cpu_64.c
@@ -14,6 +14,7 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/mtrr.h>
+#include <asm/xcr.h>
 
 static void fix_processor_context(void);
 
@@ -122,6 +123,12 @@ static void __restore_processor_state(struct saved_context *ctxt)
         wrmsrl(MSR_GS_BASE, ctxt->gs_base);
         wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
 
+        /*
+         * restore XCR0 for xsave capable cpu's.
+         */
+        if (cpu_has_xsave)
+                xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
+
         fix_processor_context();
 
         do_fpu_end();
diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S
index 4fc7e872c85e..d1e9b53f9d33 100644
--- a/arch/x86/power/hibernate_asm_32.S
+++ b/arch/x86/power/hibernate_asm_32.S
@@ -1,5 +1,3 @@
-.text
-
 /*
  * This may not use any stack, nor any variable that is not "NoSave":
  *
@@ -12,17 +10,18 @@
 #include <asm/segment.h>
 #include <asm/page.h>
 #include <asm/asm-offsets.h>
+#include <asm/processor-flags.h>
 
-        .text
+.text
 
 ENTRY(swsusp_arch_suspend)
-
         movl %esp, saved_context_esp
         movl %ebx, saved_context_ebx
         movl %ebp, saved_context_ebp
         movl %esi, saved_context_esi
         movl %edi, saved_context_edi
-        pushfl ; popl saved_context_eflags
+        pushfl
+        popl saved_context_eflags
 
         call swsusp_save
         ret
@@ -59,7 +58,7 @@ done:
         movl    mmu_cr4_features, %ecx
         jecxz   1f      # cr4 Pentium and higher, skip if zero
         movl    %ecx, %edx
-        andl    $~(1<<7), %edx;  # PGE
+        andl    $~(X86_CR4_PGE), %edx
         movl    %edx, %cr4;  # turn off PGE
 1:
         movl    %cr3, %eax;  # flush TLB
@@ -74,7 +73,8 @@ done:
         movl saved_context_esi, %esi
         movl saved_context_edi, %edi
 
-        pushl saved_context_eflags ; popfl
+        pushl saved_context_eflags
+        popfl
 
         xorl    %eax, %eax
 
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index a4e201b47f64..a27d562a9744 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -36,6 +36,7 @@
 #include <xen/hvc-console.h>
 
 #include <asm/paravirt.h>
+#include <asm/apic.h>
 #include <asm/page.h>
 #include <asm/xen/hypercall.h>
 #include <asm/xen/hypervisor.h>
@@ -580,16 +581,47 @@ static void xen_io_delay(void)
 }
 
 #ifdef CONFIG_X86_LOCAL_APIC
-static u32 xen_apic_read(unsigned long reg)
+static u32 xen_apic_read(u32 reg)
 {
         return 0;
 }
 
-static void xen_apic_write(unsigned long reg, u32 val)
+static void xen_apic_write(u32 reg, u32 val)
 {
         /* Warn to see if there's any stray references */
         WARN_ON(1);
 }
+
+static u64 xen_apic_icr_read(void)
+{
+        return 0;
+}
+
+static void xen_apic_icr_write(u32 low, u32 id)
+{
+        /* Warn to see if there's any stray references */
+        WARN_ON(1);
+}
+
+static void xen_apic_wait_icr_idle(void)
+{
+        return;
+}
+
+static u32 xen_safe_apic_wait_icr_idle(void)
+{
+        return 0;
+}
+
+static struct apic_ops xen_basic_apic_ops = {
+        .read = xen_apic_read,
+        .write = xen_apic_write,
+        .icr_read = xen_apic_icr_read,
+        .icr_write = xen_apic_icr_write,
+        .wait_icr_idle = xen_apic_wait_icr_idle,
+        .safe_wait_icr_idle = xen_safe_apic_wait_icr_idle,
+};
+
 #endif
 
 static void xen_flush_tlb(void)
@@ -812,7 +844,7 @@ static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
 
 /* Early in boot, while setting up the initial pagetable, assume
    everything is pinned. */
-static __init void xen_alloc_pte_init(struct mm_struct *mm, u32 pfn)
+static __init void xen_alloc_pte_init(struct mm_struct *mm, unsigned long pfn)
 {
 #ifdef CONFIG_FLATMEM
         BUG_ON(mem_map);        /* should only be used early */
@@ -822,7 +854,7 @@ static __init void xen_alloc_pte_init(struct mm_struct *mm, u32 pfn)
 
 /* Early release_pte assumes that all pts are pinned, since there's
    only init_mm and anything attached to that is pinned. */
-static void xen_release_pte_init(u32 pfn)
+static void xen_release_pte_init(unsigned long pfn)
 {
         make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
 }
@@ -838,7 +870,7 @@ static void pin_pagetable_pfn(unsigned cmd, unsigned long pfn)
 
 /* This needs to make sure the new pte page is pinned iff its being
    attached to a pinned pagetable. */
-static void xen_alloc_ptpage(struct mm_struct *mm, u32 pfn, unsigned level)
+static void xen_alloc_ptpage(struct mm_struct *mm, unsigned long pfn, unsigned level)
 {
         struct page *page = pfn_to_page(pfn);
 
@@ -856,12 +888,12 @@ static void xen_alloc_ptpage(struct mm_struct *mm, u32 pfn, unsigned level)
         }
 }
 
-static void xen_alloc_pte(struct mm_struct *mm, u32 pfn)
+static void xen_alloc_pte(struct mm_struct *mm, unsigned long pfn)
 {
         xen_alloc_ptpage(mm, pfn, PT_PTE);
 }
 
-static void xen_alloc_pmd(struct mm_struct *mm, u32 pfn)
+static void xen_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
 {
         xen_alloc_ptpage(mm, pfn, PT_PMD);
 }
@@ -909,7 +941,7 @@ static void xen_pgd_free(struct mm_struct *mm, pgd_t *pgd)
 }
 
 /* This should never happen until we're OK to use struct page */
-static void xen_release_ptpage(u32 pfn, unsigned level)
+static void xen_release_ptpage(unsigned long pfn, unsigned level)
 {
         struct page *page = pfn_to_page(pfn);
 
@@ -923,23 +955,23 @@ static void xen_release_ptpage(u32 pfn, unsigned level)
         }
 }
 
-static void xen_release_pte(u32 pfn)
+static void xen_release_pte(unsigned long pfn)
 {
         xen_release_ptpage(pfn, PT_PTE);
 }
 
-static void xen_release_pmd(u32 pfn)
+static void xen_release_pmd(unsigned long pfn)
 {
         xen_release_ptpage(pfn, PT_PMD);
 }
 
 #if PAGETABLE_LEVELS == 4
-static void xen_alloc_pud(struct mm_struct *mm, u32 pfn)
+static void xen_alloc_pud(struct mm_struct *mm, unsigned long pfn)
 {
         xen_alloc_ptpage(mm, pfn, PT_PUD);
 }
 
-static void xen_release_pud(u32 pfn)
+static void xen_release_pud(unsigned long pfn)
 {
         xen_release_ptpage(pfn, PT_PUD);
 }
@@ -1273,8 +1305,6 @@ static const struct pv_irq_ops xen_irq_ops __initdata = {
 
 static const struct pv_apic_ops xen_apic_ops __initdata = {
 #ifdef CONFIG_X86_LOCAL_APIC
-        .apic_write = xen_apic_write,
-        .apic_read = xen_apic_read,
         .setup_boot_clock = paravirt_nop,
         .setup_secondary_clock = paravirt_nop,
         .startup_ipi_hook = paravirt_nop,
@@ -1677,6 +1707,13 @@ asmlinkage void __init xen_start_kernel(void)
         pv_apic_ops = xen_apic_ops;
         pv_mmu_ops = xen_mmu_ops;
 
+#ifdef CONFIG_X86_LOCAL_APIC
+        /*
+         * set up the basic apic ops.
+         */
+        apic_ops = &xen_basic_apic_ops;
+#endif
+
         if (xen_feature(XENFEAT_mmu_pt_update_preserve_ad)) {
                 pv_mmu_ops.ptep_modify_prot_start = xen_ptep_modify_prot_start;
                 pv_mmu_ops.ptep_modify_prot_commit = xen_ptep_modify_prot_commit;
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index b6acc3a0af46..d67901083888 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -42,7 +42,7 @@ char * __init xen_memory_setup(void)
 
         e820.nr_map = 0;
 
-        e820_add_region(0, PFN_PHYS(max_pfn), E820_RAM);
+        e820_add_region(0, PFN_PHYS((u64)max_pfn), E820_RAM);
 
         /*
          * Even though this is normal, usable memory under Xen, reserve